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frontend: generic: preliminary SDL support
[pcsx_rearmed.git] / frontend / plat_pollux.c
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55b0eeea 1/*
2 * (C) GraÅžvydas "notaz" Ignotas, 2009-2011
3 *
4 * This work is licensed under the terms of the GNU GPLv2 or later.
5 * See the COPYING file in the top-level directory.
6 */
7
8#include <stdio.h>
9#include <stdlib.h>
10#include <string.h>
11#include <sys/types.h>
12#include <sys/stat.h>
13#include <fcntl.h>
14#include <sys/ioctl.h>
15#include <unistd.h>
16#include <linux/fb.h>
17#include <sys/mman.h>
221be40d 18#include <linux/soundcard.h>
55b0eeea 19
20#include "common/input.h"
221be40d 21#include "gp2x/in_gp2x.h"
55b0eeea 22#include "common/menu.h"
23#include "warm/warm.h"
24#include "plugin_lib.h"
221be40d 25#include "pl_gun_ts.h"
02ee7e24 26#include "blit320.h"
faf2b2aa 27#include "in_tsbutton.h"
55b0eeea 28#include "main.h"
29#include "menu.h"
30#include "plat.h"
d3f3bf09 31#include "pcnt.h"
62d7fa95 32#include "../plugins/gpulib/cspace.h"
55b0eeea 33
221be40d 34int gp2x_dev_id;
35
36static int fbdev = -1, memdev = -1, battdev = -1, mixerdev = -1;
55b0eeea 37static volatile unsigned short *memregs;
38static volatile unsigned int *memregl;
39static void *fb_vaddrs[2];
40static unsigned int fb_paddrs[2];
41static int fb_work_buf;
02ee7e24 42static int cpu_clock_allowed, have_warm;
0b6c6da8 43static unsigned int saved_video_regs[2][6];
44#define FB_VRAM_SIZE (320*240*2*2*2) // 2 buffers with space for 24bpp mode
55b0eeea 45
46static unsigned short *psx_vram;
47static unsigned int psx_vram_padds[512];
02ee7e24 48static int psx_step, psx_width, psx_height, psx_bpp;
a72ac803 49static int psx_offset_x, psx_offset_y, psx_src_width, psx_src_height;
41f55c9f 50static int fb_offset_x, fb_offset_y;
55b0eeea 51
9b4bd105 52static void caanoo_init(void);
53
54
55b0eeea 55static void *fb_flip(void)
56{
0b6c6da8 57 memregl[0x406C>>2] = memregl[0x446C>>2] = fb_paddrs[fb_work_buf];
55b0eeea 58 memregl[0x4058>>2] |= 0x10;
0b6c6da8 59 memregl[0x4458>>2] |= 0x10;
55b0eeea 60 fb_work_buf ^= 1;
61 return fb_vaddrs[fb_work_buf];
62}
63
64static void pollux_changemode(int bpp, int is_bgr)
65{
66 int code = 0, bytes = 2;
67 unsigned int r;
68
69 printf("changemode: %dbpp %s\n", bpp, is_bgr ? "bgr" : "rgb");
70
71 memregl[0x4004>>2] = 0x00ef013f;
72 memregl[0x4000>>2] |= 1 << 3;
73
74 switch (bpp)
75 {
76 case 8:
77 code = 0x443a;
78 bytes = 1;
79 break;
80 case 16:
81 code = is_bgr ? 0xc342 : 0x4432;
82 bytes = 2;
83 break;
84 case 24:
85 code = is_bgr ? 0xc653 : 0x4653;
86 bytes = 3;
87 break;
88 default:
89 printf("unhandled bpp request: %d\n", bpp);
90 return;
91 }
92
0b6c6da8 93 // program both MLCs so that TV-out works
94 memregl[0x405c>>2] = memregl[0x445c>>2] = bytes;
95 memregl[0x4060>>2] = memregl[0x4460>>2] = 320 * bytes;
55b0eeea 96
97 r = memregl[0x4058>>2];
98 r = (r & 0xffff) | (code << 16) | 0x10;
99 memregl[0x4058>>2] = r;
0b6c6da8 100
101 r = memregl[0x4458>>2];
102 r = (r & 0xffff) | (code << 16) | 0x10;
103 memregl[0x4458>>2] = r;
55b0eeea 104}
105
106/* note: both PLLs are programmed the same way,
107 * the databook incorrectly states that PLL1 differs */
108static int decode_pll(unsigned int reg)
109{
110 long long v;
111 int p, m, s;
112
113 p = (reg >> 18) & 0x3f;
114 m = (reg >> 8) & 0x3ff;
115 s = reg & 0xff;
116
117 if (p == 0)
118 p = 1;
119
120 v = 27000000; // master clock
121 v = v * m / (p << s);
122 return v;
123}
124
125int plat_cpu_clock_get(void)
126{
127 return decode_pll(memregl[0xf004>>2]) / 1000000;
128}
129
130int plat_cpu_clock_apply(int mhz)
131{
132 int adiv, mdiv, pdiv, sdiv = 0;
133 int i, vf000, vf004;
134
135 if (!cpu_clock_allowed)
136 return -1;
137 if (mhz == plat_cpu_clock_get())
138 return 0;
139
140 // m = MDIV, p = PDIV, s = SDIV
141 #define SYS_CLK_FREQ 27
142 pdiv = 9;
143 mdiv = (mhz * pdiv) / SYS_CLK_FREQ;
144 if (mdiv & ~0x3ff)
145 return -1;
146 vf004 = (pdiv<<18) | (mdiv<<8) | sdiv;
147
148 // attempt to keep the AHB divider close to 250, but not higher
149 for (adiv = 1; mhz / adiv > 250; adiv++)
150 ;
151
152 vf000 = memregl[0xf000>>2];
153 vf000 = (vf000 & ~0x3c0) | ((adiv - 1) << 6);
154 memregl[0xf000>>2] = vf000;
155 memregl[0xf004>>2] = vf004;
156 memregl[0xf07c>>2] |= 0x8000;
157 for (i = 0; (memregl[0xf07c>>2] & 0x8000) && i < 0x100000; i++)
158 ;
159
160 printf("clock set to %dMHz, AHB set to %dMHz\n", mhz, mhz / adiv);
161
162 // stupid pll share hack - must restart audio
163 extern long SPUopen(void);
164 extern long SPUclose(void);
165 SPUclose();
166 SPUopen();
167
168 return 0;
169}
170
171int plat_get_bat_capacity(void)
172{
173 unsigned short magic_val = 0;
174
175 if (battdev < 0)
176 return -1;
177 if (read(battdev, &magic_val, sizeof(magic_val)) != sizeof(magic_val))
178 return -1;
179 switch (magic_val) {
180 default:
181 case 1: return 100;
182 case 2: return 66;
183 case 3: return 40;
184 case 4: return 0;
185 }
186}
187
188#define TIMER_BASE3 0x1980
189#define TIMER_REG(x) memregl[(TIMER_BASE3 + x) >> 2]
190
191static __attribute__((unused)) unsigned int timer_get(void)
192{
193 TIMER_REG(0x08) |= 0x48; /* run timer, latch value */
194 return TIMER_REG(0);
195}
196
197static void timer_cleanup(void)
198{
199 TIMER_REG(0x40) = 0x0c; /* be sure clocks are on */
200 TIMER_REG(0x08) = 0x23; /* stop the timer, clear irq in case it's pending */
201 TIMER_REG(0x00) = 0; /* clear counter */
202 TIMER_REG(0x40) = 0; /* clocks off */
203 TIMER_REG(0x44) = 0; /* dividers back to default */
204}
205
206void plat_video_menu_enter(int is_rom_loaded)
207{
208 if (pl_vout_buf != NULL) {
209 if (psx_bpp == 16)
210 // have to do rgb conversion for menu bg
211 bgr555_to_rgb565(pl_vout_buf, pl_vout_buf, 320*240*2);
212 else
213 memset(pl_vout_buf, 0, 320*240*2);
214 }
215
216 pollux_changemode(16, 0);
217}
218
219void plat_video_menu_begin(void)
220{
221}
222
223void plat_video_menu_end(void)
224{
225 g_menuscreen_ptr = fb_flip();
226}
227
228void plat_video_menu_leave(void)
229{
55b0eeea 230 if (psx_vram == NULL) {
231 fprintf(stderr, "GPU plugin did not provide vram\n");
232 exit(1);
233 }
234
221be40d 235 if (gp2x_dev_id == GP2X_DEV_CAANOO)
236 in_set_config_int(in_name_to_id("evdev:pollux-analog"),
55b0eeea 237 IN_CFG_ABS_DEAD_ZONE, analog_deadzone);
41f55c9f 238
239 memset(g_menuscreen_ptr, 0, 320*240 * psx_bpp/8);
240 g_menuscreen_ptr = fb_flip();
55b0eeea 241}
242
47821672 243void *plat_prepare_screenshot(int *w, int *h, int *bpp)
244{
245 bgr555_to_rgb565(pl_vout_buf, pl_vout_buf, 320*240*2);
246 *w = 320;
247 *h = 240;
248 *bpp = psx_bpp;
249 return pl_vout_buf;
250}
251
a805c855 252void plat_minimize(void)
253{
254}
255
55b0eeea 256static void pl_vout_set_raw_vram(void *vram)
257{
258 int i;
259
260 psx_vram = vram;
261
262 if (vram == NULL)
263 return;
264
265 if ((long)psx_vram & 0x7ff)
266 fprintf(stderr, "GPU plugin did not align vram\n");
267
268 for (i = 0; i < 512; i++) {
269 psx_vram[i * 1024] = 0; // touch
270 psx_vram_padds[i] = warm_virt2phys(&psx_vram[i * 1024]);
271 }
272}
273
55b0eeea 274static void spend_cycles(int loops)
275{
276 asm volatile (
277 " mov r0,%0 ;\n"
278 "0: subs r0,r0,#1 ;\n"
279 " bgt 0b"
280 :: "r" (loops) : "cc", "r0");
281}
282
283#define DMA_BASE6 0x0300
284#define DMA_REG(x) memregl[(DMA_BASE6 + x) >> 2]
285
286/* this takes ~1.5ms, while ldm/stm ~1.95ms */
287static void raw_flip_dma(int x, int y)
288{
41f55c9f 289 unsigned int dst = fb_paddrs[fb_work_buf] +
290 (fb_offset_y * 320 + fb_offset_x) * psx_bpp / 8;
02ee7e24 291 int spsx_line = y + psx_offset_y;
292 int spsx_offset = (x + psx_offset_x) & 0x3f8;
55b0eeea 293 int dst_stride = 320 * psx_bpp / 8;
a72ac803 294 int len = psx_src_width * psx_bpp / 8;
55b0eeea 295 int i;
296
297 warm_cache_op_all(WOP_D_CLEAN);
d3f3bf09 298 pcnt_start(PCNT_BLIT);
55b0eeea 299
300 dst &= ~7;
301 len &= ~7;
302
303 if (DMA_REG(0x0c) & 0x90000) {
304 printf("already runnig DMA?\n");
305 DMA_REG(0x0c) = 0x100000;
306 }
307 if ((DMA_REG(0x2c) & 0x0f) < 5) {
308 printf("DMA queue busy?\n");
309 DMA_REG(0x24) = 1;
310 }
311
a72ac803 312 for (i = psx_src_height; i > 0; i--, spsx_line += psx_step, dst += dst_stride) {
55b0eeea 313 while ((DMA_REG(0x2c) & 0x0f) < 4)
314 spend_cycles(10);
315
316 // XXX: it seems we must always set all regs, what is autoincrement there for?
317 DMA_REG(0x20) = 1; // queue wait cmd
318 DMA_REG(0x10) = psx_vram_padds[spsx_line & 511] + spsx_offset * 2; // DMA src
319 DMA_REG(0x14) = dst; // DMA dst
320 DMA_REG(0x18) = len - 1; // len
321 DMA_REG(0x1c) = 0x80000; // go
322 }
323
55b0eeea 324 if (psx_bpp == 16) {
325 pl_vout_buf = g_menuscreen_ptr;
6469a8c4 326 pl_print_hud(fb_offset_x);
55b0eeea 327 }
328
329 g_menuscreen_ptr = fb_flip();
a92f6af1 330 pl_rearmed_cbs.flip_cnt++;
d3f3bf09 331
332 pcnt_end(PCNT_BLIT);
55b0eeea 333}
334
02ee7e24 335#define make_flip_func(name, blitfunc) \
336static void name(int x, int y) \
337{ \
338 unsigned short *vram = psx_vram; \
339 unsigned char *dst = (unsigned char *)g_menuscreen_ptr + \
340 (fb_offset_y * 320 + fb_offset_x) * psx_bpp / 8; \
341 unsigned int src = (y + psx_offset_y) * 1024 + x + psx_offset_x; \
342 int dst_stride = 320 * psx_bpp / 8; \
a72ac803 343 int len = psx_src_width * psx_bpp / 8; \
02ee7e24 344 int i; \
345 \
346 pcnt_start(PCNT_BLIT); \
347 \
a72ac803 348 for (i = psx_src_height; i > 0; i--, src += psx_step * 1024, dst += dst_stride) { \
02ee7e24 349 src &= 1024*512-1; \
350 blitfunc(dst, vram + src, len); \
351 } \
352 \
353 if (psx_bpp == 16) { \
354 pl_vout_buf = g_menuscreen_ptr; \
6469a8c4 355 pl_print_hud(fb_offset_x); \
02ee7e24 356 } \
357 \
358 g_menuscreen_ptr = fb_flip(); \
a92f6af1 359 pl_rearmed_cbs.flip_cnt++; \
02ee7e24 360 \
361 pcnt_end(PCNT_BLIT); \
362}
363
364make_flip_func(raw_flip_soft, memcpy)
365make_flip_func(raw_flip_soft_368, blit320_368)
366make_flip_func(raw_flip_soft_512, blit320_512)
367make_flip_func(raw_flip_soft_640, blit320_640)
368
6469a8c4 369void *plat_gvideo_set_mode(int *w_, int *h_, int *bpp_)
55b0eeea 370{
02ee7e24 371 int poff_w, poff_h, w_max;
6469a8c4 372 int w = *w_, h = *h_, bpp = *bpp_;
55b0eeea 373
a72ac803 374 if (!w || !h || !bpp)
02ee7e24 375 return NULL;
55b0eeea 376
02ee7e24 377 printf("psx mode: %dx%d@%d\n", w, h, bpp);
a72ac803 378 psx_width = w;
379 psx_height = h;
380 psx_bpp = bpp;
55b0eeea 381
a72ac803 382 switch (w + (bpp != 16) + !soft_scaling) {
02ee7e24 383 case 640:
384 pl_rearmed_cbs.pl_vout_raw_flip = raw_flip_soft_640;
385 w_max = 640;
386 break;
387 case 512:
388 pl_rearmed_cbs.pl_vout_raw_flip = raw_flip_soft_512;
389 w_max = 512;
390 break;
391 case 384:
392 case 368:
393 pl_rearmed_cbs.pl_vout_raw_flip = raw_flip_soft_368;
394 w_max = 368;
395 break;
396 default:
397 pl_rearmed_cbs.pl_vout_raw_flip = have_warm ? raw_flip_dma : raw_flip_soft;
398 w_max = 320;
399 break;
55b0eeea 400 }
401
02ee7e24 402 psx_step = 1;
403 if (h > 256) {
404 psx_step = 2;
405 h /= 2;
406 }
407
408 poff_w = poff_h = 0;
409 if (w > w_max) {
410 poff_w = w / 2 - w_max / 2;
411 w = w_max;
412 }
413 fb_offset_x = 0;
414 if (w < 320)
415 fb_offset_x = 320/2 - w / 2;
416 if (h > 240) {
417 poff_h = h / 2 - 240/2;
418 h = 240;
419 }
420 fb_offset_y = 240/2 - h / 2;
421
422 psx_offset_x = poff_w;
423 psx_offset_y = poff_h;
a72ac803 424 psx_src_width = w;
425 psx_src_height = h;
02ee7e24 426
427 if (fb_offset_x || fb_offset_y) {
428 // not fullscreen, must clear borders
429 memset(g_menuscreen_ptr, 0, 320*240 * psx_bpp/8);
430 g_menuscreen_ptr = fb_flip();
431 memset(g_menuscreen_ptr, 0, 320*240 * psx_bpp/8);
432 }
433
434 pollux_changemode(bpp, 1);
435
221be40d 436 pl_set_gun_rect(fb_offset_x, fb_offset_y, w > 320 ? 320 : w, h);
437
6469a8c4 438 // adjust for hud
439 *w_ = 320;
440 *h_ = fb_offset_y + psx_src_height;
441
02ee7e24 442 return NULL;
55b0eeea 443}
444
6469a8c4 445/* not really used, we do raw_flip */
446void plat_gvideo_open(void)
447{
448}
449
450void *plat_gvideo_flip(void)
41f55c9f 451{
452 return NULL;
453}
454
6469a8c4 455void plat_gvideo_close(void)
456{
457}
458
0b6c6da8 459static void save_multiple_regs(unsigned int *dest, int base, int count)
460{
461 const volatile unsigned int *regs = memregl + base / 4;
462 int i;
463
464 for (i = 0; i < count; i++)
465 dest[i] = regs[i];
466}
467
468static void restore_multiple_regs(int base, const unsigned int *src, int count)
469{
470 volatile unsigned int *regs = memregl + base / 4;
471 int i;
472
473 for (i = 0; i < count; i++)
474 regs[i] = src[i];
475}
476
55b0eeea 477void plat_init(void)
478{
479 const char *main_fb_name = "/dev/fb0";
480 struct fb_fix_screeninfo fbfix;
481 int rate, timer_div, timer_div2;
482 int fbdev, ret, warm_ret;
221be40d 483 FILE *f;
55b0eeea 484
485 memdev = open("/dev/mem", O_RDWR);
486 if (memdev == -1) {
487 perror("open(/dev/mem) failed");
488 exit(1);
489 }
490
491 memregs = mmap(0, 0x20000, PROT_READ|PROT_WRITE, MAP_SHARED, memdev, 0xc0000000);
492 if (memregs == MAP_FAILED) {
493 perror("mmap(memregs) failed");
494 exit(1);
495 }
496 memregl = (volatile void *)memregs;
497
0b6c6da8 498 // save video regs of both MLCs
499 save_multiple_regs(saved_video_regs[0], 0x4058, ARRAY_SIZE(saved_video_regs[0]));
500 save_multiple_regs(saved_video_regs[1], 0x4458, ARRAY_SIZE(saved_video_regs[1]));
501
55b0eeea 502 fbdev = open(main_fb_name, O_RDWR);
503 if (fbdev == -1) {
504 fprintf(stderr, "%s: ", main_fb_name);
505 perror("open");
506 exit(1);
507 }
508
509 ret = ioctl(fbdev, FBIOGET_FSCREENINFO, &fbfix);
510 if (ret == -1) {
511 perror("ioctl(fbdev) failed");
512 exit(1);
513 }
514 printf("framebuffer: \"%s\" @ %08lx\n", fbfix.id, fbfix.smem_start);
515 fb_paddrs[0] = fbfix.smem_start;
516 fb_paddrs[1] = fb_paddrs[0] + 320*240*4; // leave space for 24bpp
517
0b6c6da8 518 fb_vaddrs[0] = mmap(0, FB_VRAM_SIZE, PROT_READ|PROT_WRITE,
55b0eeea 519 MAP_SHARED, memdev, fb_paddrs[0]);
520 if (fb_vaddrs[0] == MAP_FAILED) {
521 perror("mmap(fb_vaddrs) failed");
522 exit(1);
523 }
524 fb_vaddrs[1] = (char *)fb_vaddrs[0] + 320*240*4;
525
a72ac803 526 memset(fb_vaddrs[0], 0, FB_VRAM_SIZE);
55b0eeea 527 pollux_changemode(16, 0);
528 g_menuscreen_w = 320;
529 g_menuscreen_h = 240;
530 g_menuscreen_ptr = fb_flip();
531
55b0eeea 532 warm_ret = warm_init();
02ee7e24 533 have_warm = warm_ret == 0;
55b0eeea 534 warm_change_cb_upper(WCB_B_BIT, 1);
535
536 /* some firmwares have sys clk on PLL0, we can't adjust CPU clock
537 * by reprogramming the PLL0 then, as it overclocks system bus */
538 if ((memregl[0xf000>>2] & 0x03000030) == 0x01000000)
539 cpu_clock_allowed = 1;
540 else {
541 cpu_clock_allowed = 0;
542 fprintf(stderr, "unexpected PLL config (%08x), overclocking disabled\n",
543 memregl[0xf000>>2]);
544 }
545
546 /* find what PLL1 runs at, for the timer */
547 rate = decode_pll(memregl[0xf008>>2]);
548 printf("PLL1 @ %dHz\n", rate);
549
550 /* setup timer */
551 timer_div = (rate + 500000) / 1000000;
552 timer_div2 = 0;
553 while (timer_div > 256) {
554 timer_div /= 2;
555 timer_div2++;
556 }
557 if (1 <= timer_div && timer_div <= 256 && timer_div2 < 4) {
558 int timer_rate = (rate >> timer_div2) / timer_div;
559 if (TIMER_REG(0x08) & 8) {
560 fprintf(stderr, "warning: timer in use, overriding!\n");
561 timer_cleanup();
562 }
563 if (timer_rate != 1000000)
564 fprintf(stderr, "warning: timer drift %d us\n", timer_rate - 1000000);
565
566 timer_div2 = (timer_div2 + 3) & 3;
567 TIMER_REG(0x44) = ((timer_div - 1) << 4) | 2; /* using PLL1 */
568 TIMER_REG(0x40) = 0x0c; /* clocks on */
569 TIMER_REG(0x08) = 0x68 | timer_div2; /* run timer, clear irq, latch value */
570 }
571 else
572 fprintf(stderr, "warning: could not make use of timer\n");
573
574 /* setup DMA */
575 DMA_REG(0x0c) = 0x20000; // pending IRQ clear
576
577 battdev = open("/dev/pollux_batt", O_RDONLY);
578 if (battdev < 0)
579 perror("Warning: could't open pollux_batt");
580
221be40d 581 f = fopen("/dev/accel", "rb");
582 if (f) {
583 printf("detected Caanoo\n");
584 gp2x_dev_id = GP2X_DEV_CAANOO;
585 fclose(f);
586 }
587 else {
588 printf("detected Wiz\n");
589 gp2x_dev_id = GP2X_DEV_WIZ;
590 in_gp2x_init();
591 }
592
9b4bd105 593 in_tsbutton_init();
594 in_probe();
595 if (gp2x_dev_id == GP2X_DEV_CAANOO)
596 caanoo_init();
597
221be40d 598 mixerdev = open("/dev/mixer", O_RDWR);
599 if (mixerdev == -1)
600 perror("open(/dev/mixer)");
601
02ee7e24 602 pl_rearmed_cbs.pl_vout_raw_flip = have_warm ? raw_flip_dma : raw_flip_soft;
55b0eeea 603 pl_rearmed_cbs.pl_vout_set_raw_vram = pl_vout_set_raw_vram;
604
a72ac803 605 psx_src_width = 320;
606 psx_src_height = 240;
55b0eeea 607 psx_bpp = 16;
bb88ec28 608
609 pl_rearmed_cbs.screen_w = 320;
610 pl_rearmed_cbs.screen_h = 240;
55b0eeea 611}
612
613void plat_finish(void)
614{
615 warm_finish();
616 timer_cleanup();
0b6c6da8 617
618 memset(fb_vaddrs[0], 0, FB_VRAM_SIZE);
619 restore_multiple_regs(0x4058, saved_video_regs[0], ARRAY_SIZE(saved_video_regs[0]));
620 restore_multiple_regs(0x4458, saved_video_regs[1], ARRAY_SIZE(saved_video_regs[1]));
621 memregl[0x4058>>2] |= 0x10;
622 memregl[0x4458>>2] |= 0x10;
623 munmap(fb_vaddrs[0], FB_VRAM_SIZE);
624 close(fbdev);
55b0eeea 625
626 if (battdev >= 0)
627 close(battdev);
221be40d 628 if (mixerdev >= 0)
629 close(mixerdev);
55b0eeea 630 munmap((void *)memregs, 0x20000);
631 close(memdev);
632}
633
55b0eeea 634/* Caanoo stuff, perhaps move later */
635#include <linux/input.h>
636
637struct in_default_bind in_evdev_defbinds[] = {
638 { KEY_UP, IN_BINDTYPE_PLAYER12, DKEY_UP },
639 { KEY_DOWN, IN_BINDTYPE_PLAYER12, DKEY_DOWN },
640 { KEY_LEFT, IN_BINDTYPE_PLAYER12, DKEY_LEFT },
641 { KEY_RIGHT, IN_BINDTYPE_PLAYER12, DKEY_RIGHT },
642 { BTN_TOP, IN_BINDTYPE_PLAYER12, DKEY_TRIANGLE },
643 { BTN_THUMB, IN_BINDTYPE_PLAYER12, DKEY_CROSS },
644 { BTN_THUMB2, IN_BINDTYPE_PLAYER12, DKEY_CIRCLE },
645 { BTN_TRIGGER, IN_BINDTYPE_PLAYER12, DKEY_SQUARE },
646 { BTN_BASE3, IN_BINDTYPE_PLAYER12, DKEY_START },
647 { BTN_BASE4, IN_BINDTYPE_PLAYER12, DKEY_SELECT },
648 { BTN_TOP2, IN_BINDTYPE_PLAYER12, DKEY_L1 },
649 { BTN_PINKIE, IN_BINDTYPE_PLAYER12, DKEY_R1 },
650 { BTN_BASE, IN_BINDTYPE_EMU, SACTION_ENTER_MENU },
651 { 0, 0, 0 },
652};
653
654static const char * const caanoo_keys[KEY_MAX + 1] = {
655 [0 ... KEY_MAX] = NULL,
656 [KEY_UP] = "Up",
657 [KEY_LEFT] = "Left",
658 [KEY_RIGHT] = "Right",
659 [KEY_DOWN] = "Down",
660 [BTN_TRIGGER] = "A",
661 [BTN_THUMB] = "X",
662 [BTN_THUMB2] = "B",
663 [BTN_TOP] = "Y",
664 [BTN_TOP2] = "L",
665 [BTN_PINKIE] = "R",
666 [BTN_BASE] = "Home",
667 [BTN_BASE2] = "Lock",
668 [BTN_BASE3] = "I",
669 [BTN_BASE4] = "II",
670 [BTN_BASE5] = "Push",
671};
672
b944a30e 673struct haptic_data {
674 int count;
675 struct {
676 short time, strength;
677 } actions[120];
678};
679
680#define HAPTIC_IOCTL_MAGIC 'I'
681#define HAPTIC_PLAY_PATTERN _IOW(HAPTIC_IOCTL_MAGIC, 4, struct haptic_data)
682#define HAPTIC_INDIVIDUAL_MODE _IOW(HAPTIC_IOCTL_MAGIC, 5, unsigned int)
683#define HAPTIC_SET_VIB_LEVEL _IOW(HAPTIC_IOCTL_MAGIC, 9, unsigned int)
684
685static int hapticdev = -1;
3a40ff14 686static struct haptic_data haptic_seq[2];
b944a30e 687
3a40ff14 688static int haptic_read(const char *fname, struct haptic_data *data)
b944a30e 689{
690 int i, ret, v1, v2;
691 char buf[128], *p;
692 FILE *f;
693
3a40ff14 694 f = fopen(fname, "r");
b944a30e 695 if (f == NULL) {
6469a8c4 696 fprintf(stderr, "fopen(%s)", fname);
3a40ff14 697 perror("");
b944a30e 698 return -1;
699 }
700
3a40ff14 701 for (i = 0; i < sizeof(data->actions) / sizeof(data->actions[0]); ) {
b944a30e 702 p = fgets(buf, sizeof(buf), f);
703 if (p == NULL)
704 break;
705 while (*p != 0 && *p == ' ')
706 p++;
707 if (*p == 0 || *p == ';' || *p == '#')
708 continue;
709
710 ret = sscanf(buf, "%d %d", &v1, &v2);
711 if (ret != 2) {
712 fprintf(stderr, "can't parse: %s", buf);
713 continue;
714 }
715
3a40ff14 716 data->actions[i].time = v1;
717 data->actions[i].strength = v2;
b944a30e 718 i++;
719 }
720 fclose(f);
721
722 if (i == 0) {
3a40ff14 723 fprintf(stderr, "bad haptic file: %s\n", fname);
b944a30e 724 return -1;
725 }
3a40ff14 726 data->count = i;
727
728 return 0;
729}
730
731static int haptic_init(void)
732{
733 int ret, i;
734
735 ret = haptic_read("haptic_w.cfg", &haptic_seq[0]);
736 if (ret != 0)
737 return -1;
738 ret = haptic_read("haptic_s.cfg", &haptic_seq[1]);
739 if (ret != 0)
740 return -1;
b944a30e 741
742 hapticdev = open("/dev/isa1200", O_RDWR | O_NONBLOCK);
743 if (hapticdev == -1) {
744 perror("open(/dev/isa1200)");
745 return -1;
746 }
747
748 i = 0;
749 ret = ioctl(hapticdev, HAPTIC_INDIVIDUAL_MODE, &i); /* use 2 of them */
750 i = 3;
751 ret |= ioctl(hapticdev, HAPTIC_SET_VIB_LEVEL, &i); /* max */
752 if (ret != 0) {
753 fprintf(stderr, "haptic ioctls failed\n");
754 close(hapticdev);
755 hapticdev = -1;
756 return -1;
757 }
758
759 return 0;
760}
761
3a40ff14 762void plat_trigger_vibrate(int is_strong)
b944a30e 763{
764 int ret;
765
766 if (hapticdev == -2)
767 return; // it's broken
768 if (hapticdev < 0) {
769 ret = haptic_init();
770 if (ret < 0) {
771 hapticdev = -2;
772 return;
773 }
774 }
775
3a40ff14 776 ioctl(hapticdev, HAPTIC_PLAY_PATTERN, &haptic_seq[!!is_strong]);
b944a30e 777}
778
221be40d 779/* Wiz stuff */
780struct in_default_bind in_gp2x_defbinds[] =
781{
782 /* MXYZ SACB RLDU */
783 { GP2X_BTN_UP, IN_BINDTYPE_PLAYER12, DKEY_UP },
784 { GP2X_BTN_DOWN, IN_BINDTYPE_PLAYER12, DKEY_DOWN },
785 { GP2X_BTN_LEFT, IN_BINDTYPE_PLAYER12, DKEY_LEFT },
786 { GP2X_BTN_RIGHT, IN_BINDTYPE_PLAYER12, DKEY_RIGHT },
787 { GP2X_BTN_X, IN_BINDTYPE_PLAYER12, DKEY_CROSS },
788 { GP2X_BTN_B, IN_BINDTYPE_PLAYER12, DKEY_CIRCLE },
789 { GP2X_BTN_A, IN_BINDTYPE_PLAYER12, DKEY_SQUARE },
790 { GP2X_BTN_Y, IN_BINDTYPE_PLAYER12, DKEY_TRIANGLE },
791 { GP2X_BTN_L, IN_BINDTYPE_PLAYER12, DKEY_L1 },
792 { GP2X_BTN_R, IN_BINDTYPE_PLAYER12, DKEY_R1 },
793 { GP2X_BTN_START, IN_BINDTYPE_PLAYER12, DKEY_START },
794 { GP2X_BTN_SELECT, IN_BINDTYPE_EMU, SACTION_ENTER_MENU },
795 { GP2X_BTN_VOL_UP, IN_BINDTYPE_EMU, SACTION_VOLUME_UP },
796 { GP2X_BTN_VOL_DOWN, IN_BINDTYPE_EMU, SACTION_VOLUME_DOWN },
797 { 0, 0, 0 },
798};
799
800void plat_step_volume(int is_up)
801{
802 static int volume = 50;
803 int ret, val;
804
805 if (mixerdev < 0)
806 return;
807
808 if (is_up) {
809 volume += 5;
810 if (volume > 255) volume = 255;
811 }
812 else {
813 volume -= 5;
814 if (volume < 0) volume = 0;
815 }
816 val = volume;
817 val |= val << 8;
818
819 ret = ioctl(mixerdev, SOUND_MIXER_WRITE_PCM, &val);
820 if (ret == -1)
821 perror("WRITE_PCM");
822}
823
824// unused dummy for in_gp2x
825volatile unsigned short *gp2x_memregs;
826
9b4bd105 827static void caanoo_init(void)
55b0eeea 828{
9b4bd105 829 in_set_config(in_name_to_id("evdev:pollux-analog"), IN_CFG_KEY_NAMES,
830 caanoo_keys, sizeof(caanoo_keys));
55b0eeea 831}
ARM optimized PCSX fork