[pcsx_rearmed.git] / frontend / plat_pollux.c

/*
 * (C) Gražvydas "notaz" Ignotas, 2009-2011
 *
 * This work is licensed under the terms of the GNU GPLv2 or later.
 * See the COPYING file in the top-level directory.
 */

#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <sys/ioctl.h>
#include <unistd.h>
#include <linux/fb.h>
#include <sys/mman.h>

#include "common/input.h"
#include "common/menu.h"
#include "warm/warm.h"
#include "plugin_lib.h"
#include "cspace.h"
#include "main.h"
#include "menu.h"
#include "plat.h"
#include "pcnt.h"

static int fbdev = -1, memdev = -1, battdev = -1;
static volatile unsigned short *memregs;
static volatile unsigned int   *memregl;
static void *fb_vaddrs[2];
static unsigned int fb_paddrs[2];
static int fb_work_buf;
static int cpu_clock_allowed;
static unsigned int saved_video_regs[2][6];
#define FB_VRAM_SIZE (320*240*2*2*2) // 2 buffers with space for 24bpp mode

static unsigned short *psx_vram;
static unsigned int psx_vram_padds[512];
static int psx_offset, psx_step, psx_width, psx_height, psx_bpp;
static int fb_offset_x, fb_offset_y;

// TODO: get rid of this
struct vout_fbdev;
struct vout_fbdev *layer_fb;
int g_layer_x, g_layer_y, g_layer_w, g_layer_h;

int omap_enable_layer(int enabled)
{
	return 0;
}

static void *fb_flip(void)
{
	memregl[0x406C>>2] = memregl[0x446C>>2] = fb_paddrs[fb_work_buf];
	memregl[0x4058>>2] |= 0x10;
	memregl[0x4458>>2] |= 0x10;
	fb_work_buf ^= 1;
	return fb_vaddrs[fb_work_buf];
}

static void pollux_changemode(int bpp, int is_bgr)
{
	int code = 0, bytes = 2;
	unsigned int r;

	printf("changemode: %dbpp %s\n", bpp, is_bgr ? "bgr" : "rgb");

	memregl[0x4004>>2] = 0x00ef013f;
	memregl[0x4000>>2] |= 1 << 3;

	switch (bpp)
	{
		case 8:
			code = 0x443a;
			bytes = 1;
			break;
		case 16:
			code = is_bgr ? 0xc342 : 0x4432;
			bytes = 2;
			break;
		case 24:
			code = is_bgr ? 0xc653 : 0x4653;
			bytes = 3;
			break;
		default:
			printf("unhandled bpp request: %d\n", bpp);
			return;
	}

	// program both MLCs so that TV-out works
	memregl[0x405c>>2] = memregl[0x445c>>2] = bytes;
	memregl[0x4060>>2] = memregl[0x4460>>2] = 320 * bytes;

	r = memregl[0x4058>>2];
	r = (r & 0xffff) | (code << 16) | 0x10;
	memregl[0x4058>>2] = r;

	r = memregl[0x4458>>2];
	r = (r & 0xffff) | (code << 16) | 0x10;
	memregl[0x4458>>2] = r;
}

/* note: both PLLs are programmed the same way,
 * the databook incorrectly states that PLL1 differs */
static int decode_pll(unsigned int reg)
{
	long long v;
	int p, m, s;

	p = (reg >> 18) & 0x3f;
	m = (reg >> 8) & 0x3ff;
	s = reg & 0xff;

	if (p == 0)
		p = 1;

	v = 27000000; // master clock
	v = v * m / (p << s);
	return v;
}

int plat_cpu_clock_get(void)
{
	return decode_pll(memregl[0xf004>>2]) / 1000000;
}

int plat_cpu_clock_apply(int mhz)
{
	int adiv, mdiv, pdiv, sdiv = 0;
	int i, vf000, vf004;

	if (!cpu_clock_allowed)
		return -1;
	if (mhz == plat_cpu_clock_get())
		return 0;

	// m = MDIV, p = PDIV, s = SDIV
	#define SYS_CLK_FREQ 27
	pdiv = 9;
	mdiv = (mhz * pdiv) / SYS_CLK_FREQ;
	if (mdiv & ~0x3ff)
		return -1;
	vf004 = (pdiv<<18) | (mdiv<<8) | sdiv;

	// attempt to keep the AHB divider close to 250, but not higher
	for (adiv = 1; mhz / adiv > 250; adiv++)
		;

	vf000 = memregl[0xf000>>2];
	vf000 = (vf000 & ~0x3c0) | ((adiv - 1) << 6);
	memregl[0xf000>>2] = vf000;
	memregl[0xf004>>2] = vf004;
	memregl[0xf07c>>2] |= 0x8000;
	for (i = 0; (memregl[0xf07c>>2] & 0x8000) && i < 0x100000; i++)
		;

	printf("clock set to %dMHz, AHB set to %dMHz\n", mhz, mhz / adiv);

	// stupid pll share hack - must restart audio
	extern long SPUopen(void);
	extern long SPUclose(void);
	SPUclose();
	SPUopen();

	return 0;
}

int plat_get_bat_capacity(void)
{
	unsigned short magic_val = 0;

	if (battdev < 0)
		return -1;
	if (read(battdev, &magic_val, sizeof(magic_val)) != sizeof(magic_val))
		return -1;
	switch (magic_val) {
	default:
	case 1:	return 100;
	case 2: return 66;
	case 3: return 40;
	case 4: return 0;
	}
}

#define TIMER_BASE3 0x1980
#define TIMER_REG(x) memregl[(TIMER_BASE3 + x) >> 2]

static __attribute__((unused)) unsigned int timer_get(void)
{
	TIMER_REG(0x08) |= 0x48;  /* run timer, latch value */
	return TIMER_REG(0);
}

static void timer_cleanup(void)
{
	TIMER_REG(0x40) = 0x0c;	/* be sure clocks are on */
	TIMER_REG(0x08) = 0x23;	/* stop the timer, clear irq in case it's pending */
	TIMER_REG(0x00) = 0;	/* clear counter */
	TIMER_REG(0x40) = 0;	/* clocks off */
	TIMER_REG(0x44) = 0;	/* dividers back to default */
}

void plat_video_menu_enter(int is_rom_loaded)
{
	if (pl_vout_buf != NULL) {
		if (psx_bpp == 16)
			// have to do rgb conversion for menu bg
			bgr555_to_rgb565(pl_vout_buf, pl_vout_buf, 320*240*2);
		else
			memset(pl_vout_buf, 0, 320*240*2);
	}

	pollux_changemode(16, 0);
}

void plat_video_menu_begin(void)
{
}

void plat_video_menu_end(void)
{
	g_menuscreen_ptr = fb_flip();
}

void plat_video_menu_leave(void)
{
	if (psx_vram == NULL) {
		fprintf(stderr, "GPU plugin did not provide vram\n");
		exit(1);
	}

	in_set_config_int(in_name_to_id("evdev:pollux-analog"),
			IN_CFG_ABS_DEAD_ZONE, analog_deadzone);

	memset(g_menuscreen_ptr, 0, 320*240 * psx_bpp/8);
	g_menuscreen_ptr = fb_flip();
	memset(g_menuscreen_ptr, 0, 320*240 * psx_bpp/8);

	pollux_changemode(psx_bpp, 1);
}

static void pl_vout_set_raw_vram(void *vram)
{
	int i;

	psx_vram = vram;

	if (vram == NULL)
		return;

	if ((long)psx_vram & 0x7ff)
		fprintf(stderr, "GPU plugin did not align vram\n");

	for (i = 0; i < 512; i++) {
		psx_vram[i * 1024] = 0; // touch
		psx_vram_padds[i] = warm_virt2phys(&psx_vram[i * 1024]);
	}
}

static void *pl_vout_set_mode(int w, int h, int bpp)
{
	static int old_w, old_h, old_bpp;
	int poff_w, poff_h;

	if (!w || !h || !bpp || (w == old_w && h == old_h && bpp == old_bpp))
		return NULL;

	printf("psx mode: %dx%d@%d\n", w, h, bpp);

	psx_step = 1;
	if (h > 256) {
		psx_step = 2;
		h /= 2;
	}

	poff_w = poff_h = 0;
	if (w > 320) {
		poff_w = w / 2 - 320/2;
		w = 320;
	}
	if (h > 240) {
		poff_h = h / 2 - 240/2;
		h = 240;
	}
	fb_offset_x = 320/2 - w / 2;
	fb_offset_y = 240/2 - h / 2;

	psx_offset = poff_h * 1024 + poff_w;
	psx_width = w;
	psx_height = h;
	psx_bpp = bpp;

	if (fb_offset_x || fb_offset_y) {
		// not fullscreen, must clear borders
		memset(g_menuscreen_ptr, 0, 320*240 * psx_bpp/8);
		g_menuscreen_ptr = fb_flip();
		memset(g_menuscreen_ptr, 0, 320*240 * psx_bpp/8);
	}

	pollux_changemode(bpp, 1);

	return NULL;
}

static void spend_cycles(int loops)
{
	asm volatile (
		"   mov  r0,%0    ;\n"
		"0: subs r0,r0,#1 ;\n"
		"   bgt  0b"
		:: "r" (loops) : "cc", "r0");
}

#define DMA_BASE6 0x0300
#define DMA_REG(x) memregl[(DMA_BASE6 + x) >> 2]

/* this takes ~1.5ms, while ldm/stm ~1.95ms */
static void raw_flip_dma(int x, int y)
{
	unsigned int dst = fb_paddrs[fb_work_buf] +
			(fb_offset_y * 320 + fb_offset_x) * psx_bpp / 8;
	int spsx_line = y + (psx_offset >> 10);
	int spsx_offset = (x + psx_offset) & 0x3f8;
	int dst_stride = 320 * psx_bpp / 8;
	int len = psx_width * psx_bpp / 8;
	//unsigned int st = timer_get();
	int i;

	warm_cache_op_all(WOP_D_CLEAN);
	pcnt_start(PCNT_BLIT);

	dst &= ~7;
	len &= ~7;

	if (DMA_REG(0x0c) & 0x90000) {
		printf("already runnig DMA?\n");
		DMA_REG(0x0c) = 0x100000;
	}
	if ((DMA_REG(0x2c) & 0x0f) < 5) {
		printf("DMA queue busy?\n");
		DMA_REG(0x24) = 1;
	}

	for (i = psx_height; i > 0; i--, spsx_line += psx_step, dst += dst_stride) {
		while ((DMA_REG(0x2c) & 0x0f) < 4)
			spend_cycles(10);

		// XXX: it seems we must always set all regs, what is autoincrement there for?
		DMA_REG(0x20) = 1;		// queue wait cmd
		DMA_REG(0x10) = psx_vram_padds[spsx_line & 511] + spsx_offset * 2; // DMA src
		DMA_REG(0x14) = dst;		// DMA dst
		DMA_REG(0x18) = len - 1;	// len
		DMA_REG(0x1c) = 0x80000;	// go
	}

	//printf("d %d\n", timer_get() - st);

	if (psx_bpp == 16) {
		pl_vout_buf = g_menuscreen_ptr;
		pl_print_hud(320, fb_offset_y + psx_height, fb_offset_x);
	}

	g_menuscreen_ptr = fb_flip();
	pl_flip_cnt++;

	pcnt_end(PCNT_BLIT);
}

static void raw_flip_soft(int x, int y)
{
	unsigned short *src = psx_vram + y * 1024 + x + psx_offset;
	unsigned char *dst = (unsigned char *)g_menuscreen_ptr +
			(fb_offset_y * 320 + fb_offset_x) * psx_bpp / 8;
	int dst_stride = 320 * psx_bpp / 8;
	int len = psx_width * psx_bpp / 8;
	//unsigned int st = timer_get();
	int i;

	for (i = psx_height; i > 0; i--, src += psx_step * 1024, dst += dst_stride)
		memcpy(dst, src, len);

	//printf("s %d\n", timer_get() - st);

	if (psx_bpp == 16) {
		pl_vout_buf = g_menuscreen_ptr;
		pl_print_hud(320, fb_offset_y + psx_height, fb_offset_x);
	}

	g_menuscreen_ptr = fb_flip();
	pl_flip_cnt++;
}

static void *pl_vout_flip(void)
{
	return NULL;
}

static void save_multiple_regs(unsigned int *dest, int base, int count)
{
	const volatile unsigned int *regs = memregl + base / 4;
	int i;

	for (i = 0; i < count; i++)
		dest[i] = regs[i];
}

static void restore_multiple_regs(int base, const unsigned int *src, int count)
{
	volatile unsigned int *regs = memregl + base / 4;
	int i;

	for (i = 0; i < count; i++)
		regs[i] = src[i];
}

void plat_init(void)
{
	const char *main_fb_name = "/dev/fb0";
	struct fb_fix_screeninfo fbfix;
	int rate, timer_div, timer_div2;
	int fbdev, ret, warm_ret;

	memdev = open("/dev/mem", O_RDWR);
	if (memdev == -1) {
		perror("open(/dev/mem) failed");
		exit(1);
	}

	memregs	= mmap(0, 0x20000, PROT_READ|PROT_WRITE, MAP_SHARED, memdev, 0xc0000000);
	if (memregs == MAP_FAILED) {
		perror("mmap(memregs) failed");
		exit(1);
	}
	memregl = (volatile void *)memregs;

	// save video regs of both MLCs
	save_multiple_regs(saved_video_regs[0], 0x4058, ARRAY_SIZE(saved_video_regs[0]));
	save_multiple_regs(saved_video_regs[1], 0x4458, ARRAY_SIZE(saved_video_regs[1]));

	fbdev = open(main_fb_name, O_RDWR);
	if (fbdev == -1) {
		fprintf(stderr, "%s: ", main_fb_name);
		perror("open");
		exit(1);
	}

	ret = ioctl(fbdev, FBIOGET_FSCREENINFO, &fbfix);
	if (ret == -1) {
		perror("ioctl(fbdev) failed");
		exit(1);
	}
	printf("framebuffer: \"%s\" @ %08lx\n", fbfix.id, fbfix.smem_start);
	fb_paddrs[0] = fbfix.smem_start;
	fb_paddrs[1] = fb_paddrs[0] + 320*240*4; // leave space for 24bpp

	fb_vaddrs[0] = mmap(0, FB_VRAM_SIZE, PROT_READ|PROT_WRITE,
				MAP_SHARED, memdev, fb_paddrs[0]);
	if (fb_vaddrs[0] == MAP_FAILED) {
		perror("mmap(fb_vaddrs) failed");
		exit(1);
	}
	fb_vaddrs[1] = (char *)fb_vaddrs[0] + 320*240*4;

	pollux_changemode(16, 0);
	g_menuscreen_w = 320;
	g_menuscreen_h = 240;
	g_menuscreen_ptr = fb_flip();

	g_menubg_ptr = calloc(320*240*2, 1);
	if (g_menubg_ptr == NULL) {
		fprintf(stderr, "OOM\n");
		exit(1);
	}

	warm_ret = warm_init();
	warm_change_cb_upper(WCB_B_BIT, 1);

	/* some firmwares have sys clk on PLL0, we can't adjust CPU clock
	 * by reprogramming the PLL0 then, as it overclocks system bus */
	if ((memregl[0xf000>>2] & 0x03000030) == 0x01000000)
		cpu_clock_allowed = 1;
	else {
		cpu_clock_allowed = 0;
		fprintf(stderr, "unexpected PLL config (%08x), overclocking disabled\n",
			memregl[0xf000>>2]);
	}

	/* find what PLL1 runs at, for the timer */
	rate = decode_pll(memregl[0xf008>>2]);
	printf("PLL1 @ %dHz\n", rate);

	/* setup timer */
	timer_div = (rate + 500000) / 1000000;
	timer_div2 = 0;
	while (timer_div > 256) {
		timer_div /= 2;
		timer_div2++;
	}
	if (1 <= timer_div && timer_div <= 256 && timer_div2 < 4) {
		int timer_rate = (rate >> timer_div2) / timer_div;
		if (TIMER_REG(0x08) & 8) {
			fprintf(stderr, "warning: timer in use, overriding!\n");
			timer_cleanup();
		}
		if (timer_rate != 1000000)
			fprintf(stderr, "warning: timer drift %d us\n", timer_rate - 1000000);

		timer_div2 = (timer_div2 + 3) & 3;
		TIMER_REG(0x44) = ((timer_div - 1) << 4) | 2;	/* using PLL1 */
		TIMER_REG(0x40) = 0x0c;				/* clocks on */
		TIMER_REG(0x08) = 0x68 | timer_div2;		/* run timer, clear irq, latch value */
	}
	else
		fprintf(stderr, "warning: could not make use of timer\n");

	/* setup DMA */
	DMA_REG(0x0c) = 0x20000; // pending IRQ clear

	battdev = open("/dev/pollux_batt", O_RDONLY);
	if (battdev < 0)
		perror("Warning: could't open pollux_batt");

	// hmh
	plat_rescan_inputs();

	pl_rearmed_cbs.pl_vout_flip = pl_vout_flip;
	pl_rearmed_cbs.pl_vout_raw_flip = warm_ret == 0 ? raw_flip_dma : raw_flip_soft;
	pl_rearmed_cbs.pl_vout_set_mode = pl_vout_set_mode;
	pl_rearmed_cbs.pl_vout_set_raw_vram = pl_vout_set_raw_vram;

	psx_width = 320;
	psx_height = 240;
	psx_bpp = 16;
}

void plat_finish(void)
{
	warm_finish();
	timer_cleanup();

	memset(fb_vaddrs[0], 0, FB_VRAM_SIZE);
	restore_multiple_regs(0x4058, saved_video_regs[0], ARRAY_SIZE(saved_video_regs[0]));
	restore_multiple_regs(0x4458, saved_video_regs[1], ARRAY_SIZE(saved_video_regs[1]));
	memregl[0x4058>>2] |= 0x10;
	memregl[0x4458>>2] |= 0x10;
	munmap(fb_vaddrs[0], FB_VRAM_SIZE);
	close(fbdev);

	if (battdev >= 0)
		close(battdev);
	munmap((void *)memregs, 0x20000);
	close(memdev);
}

void in_update_analogs(void)
{
}

/* Caanoo stuff, perhaps move later */
#include <linux/input.h>

struct in_default_bind in_evdev_defbinds[] = {
	{ KEY_UP,	IN_BINDTYPE_PLAYER12, DKEY_UP },
	{ KEY_DOWN,	IN_BINDTYPE_PLAYER12, DKEY_DOWN },
	{ KEY_LEFT,	IN_BINDTYPE_PLAYER12, DKEY_LEFT },
	{ KEY_RIGHT,	IN_BINDTYPE_PLAYER12, DKEY_RIGHT },
	{ BTN_TOP,	IN_BINDTYPE_PLAYER12, DKEY_TRIANGLE },
	{ BTN_THUMB,	IN_BINDTYPE_PLAYER12, DKEY_CROSS },
	{ BTN_THUMB2,	IN_BINDTYPE_PLAYER12, DKEY_CIRCLE },
	{ BTN_TRIGGER,	IN_BINDTYPE_PLAYER12, DKEY_SQUARE },
	{ BTN_BASE3,	IN_BINDTYPE_PLAYER12, DKEY_START },
	{ BTN_BASE4,	IN_BINDTYPE_PLAYER12, DKEY_SELECT },
	{ BTN_TOP2,	IN_BINDTYPE_PLAYER12, DKEY_L1 },
	{ BTN_PINKIE,	IN_BINDTYPE_PLAYER12, DKEY_R1 },
	{ BTN_BASE,	IN_BINDTYPE_EMU, SACTION_ENTER_MENU },
	{ 0, 0, 0 },
};

static const char * const caanoo_keys[KEY_MAX + 1] = {
	[0 ... KEY_MAX] = NULL,
	[KEY_UP]        = "Up",
	[KEY_LEFT]      = "Left",
	[KEY_RIGHT]     = "Right",
	[KEY_DOWN]      = "Down",
	[BTN_TRIGGER]   = "A",
	[BTN_THUMB]     = "X",
	[BTN_THUMB2]    = "B",
	[BTN_TOP]       = "Y",
	[BTN_TOP2]      = "L",
	[BTN_PINKIE]    = "R",
	[BTN_BASE]      = "Home",
	[BTN_BASE2]     = "Lock",
	[BTN_BASE3]     = "I",
	[BTN_BASE4]     = "II",
	[BTN_BASE5]     = "Push",
};

int plat_rescan_inputs(void)
{
	in_probe();
	in_set_config(in_name_to_id("evdev:pollux-analog"), IN_CFG_KEY_NAMES,
		      caanoo_keys, sizeof(caanoo_keys));
	return 0;
}
Commit	Line	Data
55b0eeea	1	/*
	2	* (C) Gražvydas "notaz" Ignotas, 2009-2011
	3	*
	4	* This work is licensed under the terms of the GNU GPLv2 or later.
	5	* See the COPYING file in the top-level directory.
	6	*/
	7
	8	#include <stdio.h>
	9	#include <stdlib.h>
	10	#include <string.h>
	11	#include <sys/types.h>
	12	#include <sys/stat.h>
	13	#include <fcntl.h>
	14	#include <sys/ioctl.h>
	15	#include <unistd.h>
	16	#include <linux/fb.h>
	17	#include <sys/mman.h>
	18
	19	#include "common/input.h"
	20	#include "common/menu.h"
	21	#include "warm/warm.h"
	22	#include "plugin_lib.h"
	23	#include "cspace.h"
	24	#include "main.h"
	25	#include "menu.h"
	26	#include "plat.h"
d3f3bf09	27	#include "pcnt.h"
55b0eeea	28
	29	static int fbdev = -1, memdev = -1, battdev = -1;
	30	static volatile unsigned short *memregs;
	31	static volatile unsigned int *memregl;
	32	static void *fb_vaddrs[2];
	33	static unsigned int fb_paddrs[2];
	34	static int fb_work_buf;
	35	static int cpu_clock_allowed;
0b6c6da8	36	static unsigned int saved_video_regs[2][6];
0b6c6da8	37	#define FB_VRAM_SIZE (320240222) // 2 buffers with space for 24bpp mode
55b0eeea	38
	39	static unsigned short *psx_vram;
	40	static unsigned int psx_vram_padds[512];
	41	static int psx_offset, psx_step, psx_width, psx_height, psx_bpp;
41f55c9f	42	static int fb_offset_x, fb_offset_y;
55b0eeea	43
	44	// TODO: get rid of this
	45	struct vout_fbdev;
	46	struct vout_fbdev *layer_fb;
	47	int g_layer_x, g_layer_y, g_layer_w, g_layer_h;
	48
	49	int omap_enable_layer(int enabled)
	50	{
	51	return 0;
	52	}
	53
	54	static void *fb_flip(void)
	55	{
0b6c6da8	56	memregl[0x406C>>2] = memregl[0x446C>>2] = fb_paddrs[fb_work_buf];
55b0eeea	57	memregl[0x4058>>2] \|= 0x10;
0b6c6da8	58	memregl[0x4458>>2] \|= 0x10;
55b0eeea	59	fb_work_buf ^= 1;
	60	return fb_vaddrs[fb_work_buf];
	61	}
	62
	63	static void pollux_changemode(int bpp, int is_bgr)
	64	{
	65	int code = 0, bytes = 2;
	66	unsigned int r;
	67
	68	printf("changemode: %dbpp %s\n", bpp, is_bgr ? "bgr" : "rgb");
	69
	70	memregl[0x4004>>2] = 0x00ef013f;
	71	memregl[0x4000>>2] \|= 1 << 3;
	72
	73	switch (bpp)
	74	{
	75	case 8:
	76	code = 0x443a;
	77	bytes = 1;
	78	break;
	79	case 16:
	80	code = is_bgr ? 0xc342 : 0x4432;
	81	bytes = 2;
	82	break;
	83	case 24:
	84	code = is_bgr ? 0xc653 : 0x4653;
	85	bytes = 3;
	86	break;
	87	default:
	88	printf("unhandled bpp request: %d\n", bpp);
	89	return;
	90	}
	91
0b6c6da8	92	// program both MLCs so that TV-out works
	93	memregl[0x405c>>2] = memregl[0x445c>>2] = bytes;
	94	memregl[0x4060>>2] = memregl[0x4460>>2] = 320 * bytes;
55b0eeea	95
	96	r = memregl[0x4058>>2];
	97	r = (r & 0xffff) \| (code << 16) \| 0x10;
	98	memregl[0x4058>>2] = r;
0b6c6da8	99
	100	r = memregl[0x4458>>2];
	101	r = (r & 0xffff) \| (code << 16) \| 0x10;
	102	memregl[0x4458>>2] = r;
55b0eeea	103	}
	104
	105	/* note: both PLLs are programmed the same way,
	106	* the databook incorrectly states that PLL1 differs */
	107	static int decode_pll(unsigned int reg)
	108	{
	109	long long v;
	110	int p, m, s;
	111
	112	p = (reg >> 18) & 0x3f;
	113	m = (reg >> 8) & 0x3ff;
	114	s = reg & 0xff;
	115
	116	if (p == 0)
	117	p = 1;
	118
	119	v = 27000000; // master clock
	120	v = v * m / (p << s);
	121	return v;
	122	}
	123
	124	int plat_cpu_clock_get(void)
	125	{
	126	return decode_pll(memregl[0xf004>>2]) / 1000000;
	127	}
	128
	129	int plat_cpu_clock_apply(int mhz)
	130	{
	131	int adiv, mdiv, pdiv, sdiv = 0;
	132	int i, vf000, vf004;
	133
	134	if (!cpu_clock_allowed)
	135	return -1;
	136	if (mhz == plat_cpu_clock_get())
	137	return 0;
	138
	139	// m = MDIV, p = PDIV, s = SDIV
	140	#define SYS_CLK_FREQ 27
	141	pdiv = 9;
	142	mdiv = (mhz * pdiv) / SYS_CLK_FREQ;
	143	if (mdiv & ~0x3ff)
	144	return -1;
	145	vf004 = (pdiv<<18) \| (mdiv<<8) \| sdiv;
	146
	147	// attempt to keep the AHB divider close to 250, but not higher
	148	for (adiv = 1; mhz / adiv > 250; adiv++)
	149	;
	150
	151	vf000 = memregl[0xf000>>2];
	152	vf000 = (vf000 & ~0x3c0) \| ((adiv - 1) << 6);
	153	memregl[0xf000>>2] = vf000;
	154	memregl[0xf004>>2] = vf004;
	155	memregl[0xf07c>>2] \|= 0x8000;
	156	for (i = 0; (memregl[0xf07c>>2] & 0x8000) && i < 0x100000; i++)
	157	;
	158
	159	printf("clock set to %dMHz, AHB set to %dMHz\n", mhz, mhz / adiv);
	160
	161	// stupid pll share hack - must restart audio
	162	extern long SPUopen(void);
	163	extern long SPUclose(void);
	164	SPUclose();
	165	SPUopen();
	166
167	return 0;
168	}
169
170	int plat_get_bat_capacity(void)
171	{
172	unsigned short magic_val = 0;
173
174	if (battdev < 0)
175	return -1;
176	if (read(battdev, &magic_val, sizeof(magic_val)) != sizeof(magic_val))
177	return -1;
178	switch (magic_val) {
179	default:
180	case 1: return 100;
181	case 2: return 66;
182	case 3: return 40;
183	case 4: return 0;
184	}
185	}
186
187	#define TIMER_BASE3 0x1980
188	#define TIMER_REG(x) memregl[(TIMER_BASE3 + x) >> 2]
189
190	static __attribute__((unused)) unsigned int timer_get(void)
191	{
192	TIMER_REG(0x08) \|= 0x48; /* run timer, latch value */
193	return TIMER_REG(0);
194	}
195
196	static void timer_cleanup(void)
197	{
198	TIMER_REG(0x40) = 0x0c; /* be sure clocks are on */
199	TIMER_REG(0x08) = 0x23; /* stop the timer, clear irq in case it's pending */
200	TIMER_REG(0x00) = 0; /* clear counter */
201	TIMER_REG(0x40) = 0; /* clocks off */
202	TIMER_REG(0x44) = 0; /* dividers back to default */
203	}
204
205	void plat_video_menu_enter(int is_rom_loaded)
206	{
207	if (pl_vout_buf != NULL) {
208	if (psx_bpp == 16)
209	// have to do rgb conversion for menu bg
210	bgr555_to_rgb565(pl_vout_buf, pl_vout_buf, 3202402);
211	else
212	memset(pl_vout_buf, 0, 3202402);
213	}
214
215	pollux_changemode(16, 0);
216	}
217
218	void plat_video_menu_begin(void)
219	{
220	}
221
222	void plat_video_menu_end(void)
223	{
224	g_menuscreen_ptr = fb_flip();
225	}
226
227	void plat_video_menu_leave(void)
228	{
55b0eeea	229	if (psx_vram == NULL) {
	230	fprintf(stderr, "GPU plugin did not provide vram\n");
	231	exit(1);
	232	}
	233
	234	in_set_config_int(in_name_to_id("evdev:pollux-analog"),
	235	IN_CFG_ABS_DEAD_ZONE, analog_deadzone);
41f55c9f	236
	237	memset(g_menuscreen_ptr, 0, 320240 psx_bpp/8);
	238	g_menuscreen_ptr = fb_flip();
	239	memset(g_menuscreen_ptr, 0, 320240 psx_bpp/8);
	240
	241	pollux_changemode(psx_bpp, 1);
55b0eeea	242	}
	243
	244	static void pl_vout_set_raw_vram(void *vram)
	245	{
	246	int i;
	247
	248	psx_vram = vram;
	249
	250	if (vram == NULL)
	251	return;
	252
	253	if ((long)psx_vram & 0x7ff)
	254	fprintf(stderr, "GPU plugin did not align vram\n");
	255
	256	for (i = 0; i < 512; i++) {
	257	psx_vram[i * 1024] = 0; // touch
	258	psx_vram_padds[i] = warm_virt2phys(&psx_vram[i * 1024]);
	259	}
	260	}
	261
	262	static void *pl_vout_set_mode(int w, int h, int bpp)
	263	{
	264	static int old_w, old_h, old_bpp;
55b0eeea	265	int poff_w, poff_h;
	266
	267	if (!w \|\| !h \|\| !bpp \|\| (w == old_w && h == old_h && bpp == old_bpp))
	268	return NULL;
	269
	270	printf("psx mode: %dx%d@%d\n", w, h, bpp);
	271
	272	psx_step = 1;
	273	if (h > 256) {
	274	psx_step = 2;
	275	h /= 2;
	276	}
	277
	278	poff_w = poff_h = 0;
	279	if (w > 320) {
	280	poff_w = w / 2 - 320/2;
	281	w = 320;
	282	}
	283	if (h > 240) {
	284	poff_h = h / 2 - 240/2;
	285	h = 240;
	286	}
41f55c9f	287	fb_offset_x = 320/2 - w / 2;
41f55c9f	288	fb_offset_y = 240/2 - h / 2;
55b0eeea	289
	290	psx_offset = poff_h * 1024 + poff_w;
	291	psx_width = w;
	292	psx_height = h;
	293	psx_bpp = bpp;
41f55c9f	294
	295	if (fb_offset_x \|\| fb_offset_y) {
	296	// not fullscreen, must clear borders
	297	memset(g_menuscreen_ptr, 0, 320240 psx_bpp/8);
	298	g_menuscreen_ptr = fb_flip();
	299	memset(g_menuscreen_ptr, 0, 320240 psx_bpp/8);
	300	}
55b0eeea	301
	302	pollux_changemode(bpp, 1);
	303
	304	return NULL;
	305	}
	306
	307	static void spend_cycles(int loops)
	308	{
	309	asm volatile (
	310	" mov r0,%0 ;\n"
	311	"0: subs r0,r0,#1 ;\n"
	312	" bgt 0b"
	313	:: "r" (loops) : "cc", "r0");
	314	}
	315
	316	#define DMA_BASE6 0x0300
	317	#define DMA_REG(x) memregl[(DMA_BASE6 + x) >> 2]
	318
	319	/* this takes ~1.5ms, while ldm/stm ~1.95ms */
	320	static void raw_flip_dma(int x, int y)
	321	{
41f55c9f	322	unsigned int dst = fb_paddrs[fb_work_buf] +
41f55c9f	323	(fb_offset_y * 320 + fb_offset_x) * psx_bpp / 8;
55b0eeea	324	int spsx_line = y + (psx_offset >> 10);
	325	int spsx_offset = (x + psx_offset) & 0x3f8;
	326	int dst_stride = 320 * psx_bpp / 8;
	327	int len = psx_width * psx_bpp / 8;
	328	//unsigned int st = timer_get();
	329	int i;
	330
	331	warm_cache_op_all(WOP_D_CLEAN);
d3f3bf09	332	pcnt_start(PCNT_BLIT);
55b0eeea	333
	334	dst &= ~7;
	335	len &= ~7;
	336
	337	if (DMA_REG(0x0c) & 0x90000) {
	338	printf("already runnig DMA?\n");
	339	DMA_REG(0x0c) = 0x100000;
	340	}
	341	if ((DMA_REG(0x2c) & 0x0f) < 5) {
	342	printf("DMA queue busy?\n");
	343	DMA_REG(0x24) = 1;
	344	}
	345
	346	for (i = psx_height; i > 0; i--, spsx_line += psx_step, dst += dst_stride) {
	347	while ((DMA_REG(0x2c) & 0x0f) < 4)
	348	spend_cycles(10);
	349
	350	// XXX: it seems we must always set all regs, what is autoincrement there for?
	351	DMA_REG(0x20) = 1; // queue wait cmd
	352	DMA_REG(0x10) = psx_vram_padds[spsx_line & 511] + spsx_offset * 2; // DMA src
	353	DMA_REG(0x14) = dst; // DMA dst
	354	DMA_REG(0x18) = len - 1; // len
	355	DMA_REG(0x1c) = 0x80000; // go
	356	}
	357
	358	//printf("d %d\n", timer_get() - st);
	359
	360	if (psx_bpp == 16) {
	361	pl_vout_buf = g_menuscreen_ptr;
41f55c9f	362	pl_print_hud(320, fb_offset_y + psx_height, fb_offset_x);
55b0eeea	363	}
	364
	365	g_menuscreen_ptr = fb_flip();
	366	pl_flip_cnt++;
d3f3bf09	367
d3f3bf09	368	pcnt_end(PCNT_BLIT);
55b0eeea	369	}
	370
	371	static void raw_flip_soft(int x, int y)
	372	{
	373	unsigned short src = psx_vram + y 1024 + x + psx_offset;
41f55c9f	374	unsigned char dst = (unsigned char )g_menuscreen_ptr +
41f55c9f	375	(fb_offset_y * 320 + fb_offset_x) * psx_bpp / 8;
55b0eeea	376	int dst_stride = 320 * psx_bpp / 8;
	377	int len = psx_width * psx_bpp / 8;
	378	//unsigned int st = timer_get();
	379	int i;
	380
	381	for (i = psx_height; i > 0; i--, src += psx_step * 1024, dst += dst_stride)
	382	memcpy(dst, src, len);
	383
	384	//printf("s %d\n", timer_get() - st);
	385
	386	if (psx_bpp == 16) {
	387	pl_vout_buf = g_menuscreen_ptr;
41f55c9f	388	pl_print_hud(320, fb_offset_y + psx_height, fb_offset_x);
55b0eeea	389	}
	390
	391	g_menuscreen_ptr = fb_flip();
	392	pl_flip_cnt++;
	393	}
	394
41f55c9f	395	static void *pl_vout_flip(void)
	396	{
	397	return NULL;
	398	}
	399
0b6c6da8	400	static void save_multiple_regs(unsigned int *dest, int base, int count)
	401	{
	402	const volatile unsigned int *regs = memregl + base / 4;
	403	int i;
	404
	405	for (i = 0; i < count; i++)
	406	dest[i] = regs[i];
	407	}
	408
	409	static void restore_multiple_regs(int base, const unsigned int *src, int count)
	410	{
	411	volatile unsigned int *regs = memregl + base / 4;
	412	int i;
	413
	414	for (i = 0; i < count; i++)
	415	regs[i] = src[i];
	416	}
	417
55b0eeea	418	void plat_init(void)
	419	{
	420	const char *main_fb_name = "/dev/fb0";
	421	struct fb_fix_screeninfo fbfix;
	422	int rate, timer_div, timer_div2;
	423	int fbdev, ret, warm_ret;
	424
	425	memdev = open("/dev/mem", O_RDWR);
	426	if (memdev == -1) {
	427	perror("open(/dev/mem) failed");
	428	exit(1);
	429	}
	430
	431	memregs = mmap(0, 0x20000, PROT_READ\|PROT_WRITE, MAP_SHARED, memdev, 0xc0000000);
	432	if (memregs == MAP_FAILED) {
	433	perror("mmap(memregs) failed");
	434	exit(1);
	435	}
	436	memregl = (volatile void *)memregs;
	437
0b6c6da8	438	// save video regs of both MLCs
	439	save_multiple_regs(saved_video_regs[0], 0x4058, ARRAY_SIZE(saved_video_regs[0]));
	440	save_multiple_regs(saved_video_regs[1], 0x4458, ARRAY_SIZE(saved_video_regs[1]));
	441
55b0eeea	442	fbdev = open(main_fb_name, O_RDWR);
	443	if (fbdev == -1) {
	444	fprintf(stderr, "%s: ", main_fb_name);
	445	perror("open");
	446	exit(1);
	447	}
	448
	449	ret = ioctl(fbdev, FBIOGET_FSCREENINFO, &fbfix);
	450	if (ret == -1) {
	451	perror("ioctl(fbdev) failed");
	452	exit(1);
	453	}
	454	printf("framebuffer: \"%s\" @ %08lx\n", fbfix.id, fbfix.smem_start);
	455	fb_paddrs[0] = fbfix.smem_start;
	456	fb_paddrs[1] = fb_paddrs[0] + 3202404; // leave space for 24bpp
	457
0b6c6da8	458	fb_vaddrs[0] = mmap(0, FB_VRAM_SIZE, PROT_READ\|PROT_WRITE,
55b0eeea	459	MAP_SHARED, memdev, fb_paddrs[0]);
	460	if (fb_vaddrs[0] == MAP_FAILED) {
	461	perror("mmap(fb_vaddrs) failed");
	462	exit(1);
	463	}
	464	fb_vaddrs[1] = (char )fb_vaddrs[0] + 320240*4;
	465
	466	pollux_changemode(16, 0);
	467	g_menuscreen_w = 320;
	468	g_menuscreen_h = 240;
	469	g_menuscreen_ptr = fb_flip();
	470
	471	g_menubg_ptr = calloc(3202402, 1);
	472	if (g_menubg_ptr == NULL) {
	473	fprintf(stderr, "OOM\n");
	474	exit(1);
	475	}
	476
	477	warm_ret = warm_init();
	478	warm_change_cb_upper(WCB_B_BIT, 1);
	479
	480	/* some firmwares have sys clk on PLL0, we can't adjust CPU clock
	481	* by reprogramming the PLL0 then, as it overclocks system bus */
	482	if ((memregl[0xf000>>2] & 0x03000030) == 0x01000000)
	483	cpu_clock_allowed = 1;
	484	else {
	485	cpu_clock_allowed = 0;
	486	fprintf(stderr, "unexpected PLL config (%08x), overclocking disabled\n",
	487	memregl[0xf000>>2]);
	488	}
	489
	490	/* find what PLL1 runs at, for the timer */
	491	rate = decode_pll(memregl[0xf008>>2]);
	492	printf("PLL1 @ %dHz\n", rate);
	493
	494	/* setup timer */
	495	timer_div = (rate + 500000) / 1000000;
	496	timer_div2 = 0;
	497	while (timer_div > 256) {
	498	timer_div /= 2;
	499	timer_div2++;
	500	}
	501	if (1 <= timer_div && timer_div <= 256 && timer_div2 < 4) {
	502	int timer_rate = (rate >> timer_div2) / timer_div;
	503	if (TIMER_REG(0x08) & 8) {
	504	fprintf(stderr, "warning: timer in use, overriding!\n");
	505	timer_cleanup();
	506	}
	507	if (timer_rate != 1000000)
	508	fprintf(stderr, "warning: timer drift %d us\n", timer_rate - 1000000);
	509
	510	timer_div2 = (timer_div2 + 3) & 3;
	511	TIMER_REG(0x44) = ((timer_div - 1) << 4) \| 2; /* using PLL1 */
	512	TIMER_REG(0x40) = 0x0c; /* clocks on */
	513	TIMER_REG(0x08) = 0x68 \| timer_div2; /* run timer, clear irq, latch value */
	514	}
	515	else
	516	fprintf(stderr, "warning: could not make use of timer\n");
	517
	518	/* setup DMA */
	519	DMA_REG(0x0c) = 0x20000; // pending IRQ clear
	520
	521	battdev = open("/dev/pollux_batt", O_RDONLY);
	522	if (battdev < 0)
523	perror("Warning: could't open pollux_batt");
524
525	// hmh
526	plat_rescan_inputs();
527
41f55c9f	528	pl_rearmed_cbs.pl_vout_flip = pl_vout_flip;
55b0eeea	529	pl_rearmed_cbs.pl_vout_raw_flip = warm_ret == 0 ? raw_flip_dma : raw_flip_soft;
	530	pl_rearmed_cbs.pl_vout_set_mode = pl_vout_set_mode;
	531	pl_rearmed_cbs.pl_vout_set_raw_vram = pl_vout_set_raw_vram;
	532
	533	psx_width = 320;
	534	psx_height = 240;
	535	psx_bpp = 16;
	536	}
	537
	538	void plat_finish(void)
	539	{
	540	warm_finish();
	541	timer_cleanup();
0b6c6da8	542
	543	memset(fb_vaddrs[0], 0, FB_VRAM_SIZE);
	544	restore_multiple_regs(0x4058, saved_video_regs[0], ARRAY_SIZE(saved_video_regs[0]));
	545	restore_multiple_regs(0x4458, saved_video_regs[1], ARRAY_SIZE(saved_video_regs[1]));
	546	memregl[0x4058>>2] \|= 0x10;
	547	memregl[0x4458>>2] \|= 0x10;
	548	munmap(fb_vaddrs[0], FB_VRAM_SIZE);
	549	close(fbdev);
55b0eeea	550
	551	if (battdev >= 0)
	552	close(battdev);
55b0eeea	553	munmap((void *)memregs, 0x20000);
	554	close(memdev);
	555	}
	556
	557	void in_update_analogs(void)
	558	{
	559	}
	560
	561	/* Caanoo stuff, perhaps move later */
	562	#include <linux/input.h>
	563
	564	struct in_default_bind in_evdev_defbinds[] = {
	565	{ KEY_UP, IN_BINDTYPE_PLAYER12, DKEY_UP },
	566	{ KEY_DOWN, IN_BINDTYPE_PLAYER12, DKEY_DOWN },
	567	{ KEY_LEFT, IN_BINDTYPE_PLAYER12, DKEY_LEFT },
	568	{ KEY_RIGHT, IN_BINDTYPE_PLAYER12, DKEY_RIGHT },
	569	{ BTN_TOP, IN_BINDTYPE_PLAYER12, DKEY_TRIANGLE },
	570	{ BTN_THUMB, IN_BINDTYPE_PLAYER12, DKEY_CROSS },
	571	{ BTN_THUMB2, IN_BINDTYPE_PLAYER12, DKEY_CIRCLE },
	572	{ BTN_TRIGGER, IN_BINDTYPE_PLAYER12, DKEY_SQUARE },
	573	{ BTN_BASE3, IN_BINDTYPE_PLAYER12, DKEY_START },
	574	{ BTN_BASE4, IN_BINDTYPE_PLAYER12, DKEY_SELECT },
	575	{ BTN_TOP2, IN_BINDTYPE_PLAYER12, DKEY_L1 },
	576	{ BTN_PINKIE, IN_BINDTYPE_PLAYER12, DKEY_R1 },
	577	{ BTN_BASE, IN_BINDTYPE_EMU, SACTION_ENTER_MENU },
	578	{ 0, 0, 0 },
	579	};
	580
	581	static const char * const caanoo_keys[KEY_MAX + 1] = {
	582	[0 ... KEY_MAX] = NULL,
	583	[KEY_UP] = "Up",
	584	[KEY_LEFT] = "Left",
	585	[KEY_RIGHT] = "Right",
	586	[KEY_DOWN] = "Down",
	587	[BTN_TRIGGER] = "A",
	588	[BTN_THUMB] = "X",
	589	[BTN_THUMB2] = "B",
	590	[BTN_TOP] = "Y",
	591	[BTN_TOP2] = "L",
	592	[BTN_PINKIE] = "R",
	593	[BTN_BASE] = "Home",
	594	[BTN_BASE2] = "Lock",
	595	[BTN_BASE3] = "I",
	596	[BTN_BASE4] = "II",
	597	[BTN_BASE5] = "Push",
	598	};
	599
	600	int plat_rescan_inputs(void)
	601	{
	602	in_probe();
	603	in_set_config(in_name_to_id("evdev:pollux-analog"), IN_CFG_KEY_NAMES,
	604	caanoo_keys, sizeof(caanoo_keys));
	605	return 0;
	606	}