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Icache emulation from PCSX Redux + Senquack changes from PCSX4ALL (#198)
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / emu_if.c
CommitLineData
7e605697 1/*
009faf24 2 * (C) GraÅžvydas "notaz" Ignotas, 2010-2011
7e605697 3 *
4 * This work is licensed under the terms of GNU GPL version 2 or later.
5 * See the COPYING file in the top-level directory.
6 */
7
f95a77f7 8#include <stdio.h>
9
10#include "emu_if.h"
7e605697 11#include "pcsxmem.h"
7139f3c8 12#include "../psxhle.h"
d28b54b1 13#include "../r3000a.h"
52082bc1 14#include "../cdrom.h"
15#include "../psxdma.h"
16#include "../mdec.h"
59774ed0 17#include "../gte_arm.h"
009faf24 18#include "../gte_neon.h"
59774ed0 19#define FLAGLESS
20#include "../gte.h"
7139f3c8 21
ae602c19 22#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
23
7139f3c8 24//#define evprintf printf
25#define evprintf(...)
26
f95a77f7 27char invalid_code[0x100000];
c6d5790c 28static u32 scratch_buf[8*8*2] __attribute__((aligned(64)));
d28b54b1 29u32 event_cycles[PSXINT_COUNT];
f95a77f7 30
654e8cfb 31static void schedule_timeslice(void)
f95a77f7 32{
654e8cfb 33 u32 i, c = psxRegs.cycle;
5b8c000f 34 u32 irqs = psxRegs.interrupt;
654e8cfb 35 s32 min, dif;
36
5b8c000f 37 min = PSXCLK;
38 for (i = 0; irqs != 0; i++, irqs >>= 1) {
39 if (!(irqs & 1))
40 continue;
654e8cfb 41 dif = event_cycles[i] - c;
42 //evprintf(" ev %d\n", dif);
43 if (0 < dif && dif < min)
44 min = dif;
45 }
46 next_interupt = c + min;
654e8cfb 47}
ae602c19 48
52082bc1 49typedef void (irq_func)();
50
51static irq_func * const irq_funcs[] = {
52 [PSXINT_SIO] = sioInterrupt,
53 [PSXINT_CDR] = cdrInterrupt,
54 [PSXINT_CDREAD] = cdrReadInterrupt,
55 [PSXINT_GPUDMA] = gpuInterrupt,
56 [PSXINT_MDECOUTDMA] = mdec1Interrupt,
57 [PSXINT_SPUDMA] = spuInterrupt,
528ad661 58 [PSXINT_MDECINDMA] = mdec0Interrupt,
57a757ce 59 [PSXINT_GPUOTCDMA] = gpuotcInterrupt,
9f8b032d 60 [PSXINT_CDRDMA] = cdrDmaInterrupt,
61 [PSXINT_CDRLID] = cdrLidSeekInterrupt,
7f457614 62 [PSXINT_CDRPLAY] = cdrPlayInterrupt,
2b30c129 63 [PSXINT_SPU_UPDATE] = spuUpdate,
5b8c000f 64 [PSXINT_RCNT] = psxRcntUpdate,
52082bc1 65};
66
67/* local dupe of psxBranchTest, using event_cycles */
68static void irq_test(void)
69{
70 u32 irqs = psxRegs.interrupt;
71 u32 cycle = psxRegs.cycle;
72 u32 irq, irq_bits;
73
52082bc1 74 // irq_funcs() may queue more irqs
75 psxRegs.interrupt = 0;
76
77 for (irq = 0, irq_bits = irqs; irq_bits != 0; irq++, irq_bits >>= 1) {
78 if (!(irq_bits & 1))
79 continue;
80 if ((s32)(cycle - event_cycles[irq]) >= 0) {
81 irqs &= ~(1 << irq);
82 irq_funcs[irq]();
83 }
84 }
85 psxRegs.interrupt |= irqs;
86
87 if ((psxHu32(0x1070) & psxHu32(0x1074)) && (Status & 0x401) == 0x401) {
88 psxException(0x400, 0);
89 pending_exception = 1;
90 }
91}
92
654e8cfb 93void gen_interupt()
94{
654e8cfb 95 evprintf(" +ge %08x, %u->%u\n", psxRegs.pc, psxRegs.cycle, next_interupt);
7139f3c8 96
52082bc1 97 irq_test();
98 //psxBranchTest();
99 //pending_exception = 1;
7139f3c8 100
654e8cfb 101 schedule_timeslice();
ae602c19 102
654e8cfb 103 evprintf(" -ge %08x, %u->%u (%d)\n", psxRegs.pc, psxRegs.cycle,
104 next_interupt, next_interupt - psxRegs.cycle);
f95a77f7 105}
106
fca1aef2 107// from interpreter
108extern void MTC0(int reg, u32 val);
109
63cb0298 110void pcsx_mtc0(u32 reg, u32 val)
28bc5688 111{
63cb0298 112 evprintf("MTC0 %d #%x @%08x %u\n", reg, val, psxRegs.pc, psxRegs.cycle);
113 MTC0(reg, val);
fca1aef2 114 gen_interupt();
15d0ba02 115 if (Cause & Status & 0x0300) // possible sw irq
116 pending_exception = 1;
fca1aef2 117}
28bc5688 118
63cb0298 119void pcsx_mtc0_ds(u32 reg, u32 val)
fca1aef2 120{
63cb0298 121 evprintf("MTC0 %d #%x @%08x %u\n", reg, val, psxRegs.pc, psxRegs.cycle);
122 MTC0(reg, val);
28bc5688 123}
124
03f55e6b 125void new_dyna_before_save(void)
52082bc1 126{
5b8c000f 127 psxRegs.interrupt &= ~(1 << PSXINT_RCNT); // old savestate compat
128
52082bc1 129 // psxRegs.intCycle is always maintained, no need to convert
130}
131
5b8c000f 132void new_dyna_after_save(void)
133{
134 psxRegs.interrupt |= 1 << PSXINT_RCNT;
135}
136
03f55e6b 137static void new_dyna_restore(void)
52082bc1 138{
139 int i;
9f8b032d 140 for (i = 0; i < PSXINT_COUNT; i++)
52082bc1 141 event_cycles[i] = psxRegs.intCycle[i].sCycle + psxRegs.intCycle[i].cycle;
b1be1eee 142
5b8c000f 143 event_cycles[PSXINT_RCNT] = psxNextsCounter + psxNextCounter;
144 psxRegs.interrupt |= 1 << PSXINT_RCNT;
145 psxRegs.interrupt &= (1 << PSXINT_COUNT) - 1;
146
b1be1eee 147 new_dyna_pcsx_mem_load_state();
52082bc1 148}
149
03f55e6b 150void new_dyna_freeze(void *f, int mode)
151{
152 const char header_save[8] = "ariblks";
153 uint32_t addrs[1024 * 4];
154 int32_t size = 0;
155 int bytes;
156 char header[8];
157
158 if (mode != 0) { // save
159 size = new_dynarec_save_blocks(addrs, sizeof(addrs));
160 if (size == 0)
161 return;
162
163 SaveFuncs.write(f, header_save, sizeof(header_save));
164 SaveFuncs.write(f, &size, sizeof(size));
165 SaveFuncs.write(f, addrs, size);
166 }
167 else {
168 new_dyna_restore();
169
170 bytes = SaveFuncs.read(f, header, sizeof(header));
171 if (bytes != sizeof(header) || strcmp(header, header_save)) {
172 if (bytes > 0)
173 SaveFuncs.seek(f, -bytes, SEEK_CUR);
174 return;
175 }
176 SaveFuncs.read(f, &size, sizeof(size));
177 if (size <= 0)
178 return;
179 if (size > sizeof(addrs)) {
180 bytes = size - sizeof(addrs);
181 SaveFuncs.seek(f, bytes, SEEK_CUR);
182 size = sizeof(addrs);
183 }
184 bytes = SaveFuncs.read(f, addrs, size);
185 if (bytes != size)
186 return;
187
188 new_dynarec_load_blocks(addrs, size);
189 }
190
191 //printf("drc: %d block info entries %s\n", size/8, mode ? "saved" : "loaded");
192}
193
2167bef6 194/* GTE stuff */
b9b61529 195void *gte_handlers[64];
196
59774ed0 197void *gte_handlers_nf[64] = {
198 NULL , gteRTPS_nf , NULL , NULL , NULL , NULL , gteNCLIP_nf, NULL , // 00
199 NULL , NULL , NULL , NULL , gteOP_nf , NULL , NULL , NULL , // 08
200 gteDPCS_nf, gteINTPL_nf, gteMVMVA_nf, gteNCDS_nf, gteCDP_nf, NULL , gteNCDT_nf , NULL , // 10
201 NULL , NULL , NULL , gteNCCS_nf, gteCC_nf , NULL , gteNCS_nf , NULL , // 18
202 gteNCT_nf , NULL , NULL , NULL , NULL , NULL , NULL , NULL , // 20
203 gteSQR_nf , gteDCPL_nf , gteDPCT_nf , NULL , NULL , gteAVSZ3_nf, gteAVSZ4_nf, NULL , // 28
204 gteRTPT_nf, NULL , NULL , NULL , NULL , NULL , NULL , NULL , // 30
205 NULL , NULL , NULL , NULL , NULL , gteGPF_nf , gteGPL_nf , gteNCCT_nf, // 38
206};
207
bedfea38 208const char *gte_regnames[64] = {
209 NULL , "RTPS" , NULL , NULL , NULL , NULL , "NCLIP", NULL , // 00
210 NULL , NULL , NULL , NULL , "OP" , NULL , NULL , NULL , // 08
211 "DPCS", "INTPL", "MVMVA", "NCDS", "CDP", NULL , "NCDT" , NULL , // 10
212 NULL , NULL , NULL , "NCCS", "CC" , NULL , "NCS" , NULL , // 18
213 "NCT" , NULL , NULL , NULL , NULL , NULL , NULL , NULL , // 20
214 "SQR" , "DCPL" , "DPCT" , NULL , NULL , "AVSZ3", "AVSZ4", NULL , // 28
215 "RTPT", NULL , NULL , NULL , NULL , NULL , NULL , NULL , // 30
216 NULL , NULL , NULL , NULL , NULL , "GPF" , "GPL" , "NCCT", // 38
217};
218
b9b61529 219/* from gte.txt.. not sure if this is any good. */
220const char gte_cycletab[64] = {
221 /* 1 2 3 4 5 6 7 8 9 a b c d e f */
222 0, 15, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 6, 0, 0, 0,
223 8, 8, 8, 19, 13, 0, 44, 0, 0, 0, 0, 17, 11, 0, 14, 0,
224 30, 0, 0, 0, 0, 0, 0, 0, 5, 8, 17, 0, 0, 5, 6, 0,
225 23, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5, 5, 39,
226};
f95a77f7 227
2167bef6 228#define GCBIT(x) \
229 (1ll << (32+x))
230#define GDBIT(x) \
231 (1ll << (x))
232#define GCBITS3(b0,b1,b2) \
233 (GCBIT(b0) | GCBIT(b1) | GCBIT(b2))
234#define GDBITS2(b0,b1) \
235 (GDBIT(b0) | GDBIT(b1))
236#define GDBITS3(b0,b1,b2) \
237 (GDBITS2(b0,b1) | GDBIT(b2))
238#define GDBITS4(b0,b1,b2,b3) \
239 (GDBITS3(b0,b1,b2) | GDBIT(b3))
240#define GDBITS5(b0,b1,b2,b3,b4) \
241 (GDBITS4(b0,b1,b2,b3) | GDBIT(b4))
242#define GDBITS6(b0,b1,b2,b3,b4,b5) \
243 (GDBITS5(b0,b1,b2,b3,b4) | GDBIT(b5))
244#define GDBITS7(b0,b1,b2,b3,b4,b5,b6) \
245 (GDBITS6(b0,b1,b2,b3,b4,b5) | GDBIT(b6))
246#define GDBITS8(b0,b1,b2,b3,b4,b5,b6,b7) \
247 (GDBITS7(b0,b1,b2,b3,b4,b5,b6) | GDBIT(b7))
248#define GDBITS9(b0,b1,b2,b3,b4,b5,b6,b7,b8) \
249 (GDBITS8(b0,b1,b2,b3,b4,b5,b6,b7) | GDBIT(b8))
250#define GDBITS10(b0,b1,b2,b3,b4,b5,b6,b7,b8,b9) \
251 (GDBITS9(b0,b1,b2,b3,b4,b5,b6,b7,b8) | GDBIT(b9))
252
253const uint64_t gte_reg_reads[64] = {
254 [GTE_RTPS] = 0x1f0000ff00000000ll | GDBITS7(0,1,13,14,17,18,19),
255 [GTE_NCLIP] = GDBITS3(12,13,14),
256 [GTE_OP] = GCBITS3(0,2,4) | GDBITS3(9,10,11),
257 [GTE_DPCS] = GCBITS3(21,22,23) | GDBITS4(6,8,21,22),
258 [GTE_INTPL] = GCBITS3(21,22,23) | GDBITS7(6,8,9,10,11,21,22),
db481db4 259 [GTE_MVMVA] = 0x00ffffff00000000ll | GDBITS9(0,1,2,3,4,5,9,10,11), // XXX: maybe decode further?
260 [GTE_NCDS] = 0x00ffff0000000000ll | GDBITS6(0,1,6,8,21,22),
261 [GTE_CDP] = 0x00ffe00000000000ll | GDBITS7(6,8,9,10,11,21,22),
2167bef6 262 [GTE_NCDT] = 0x00ffff0000000000ll | GDBITS8(0,1,2,3,4,5,6,8),
db481db4 263 [GTE_NCCS] = 0x001fff0000000000ll | GDBITS5(0,1,6,21,22),
2167bef6 264 [GTE_CC] = 0x001fe00000000000ll | GDBITS6(6,9,10,11,21,22),
db481db4 265 [GTE_NCS] = 0x001fff0000000000ll | GDBITS5(0,1,6,21,22),
2167bef6 266 [GTE_NCT] = 0x001fff0000000000ll | GDBITS7(0,1,2,3,4,5,6),
267 [GTE_SQR] = GDBITS3(9,10,11),
268 [GTE_DCPL] = GCBITS3(21,22,23) | GDBITS7(6,8,9,10,11,21,22),
269 [GTE_DPCT] = GCBITS3(21,22,23) | GDBITS4(8,20,21,22),
270 [GTE_AVSZ3] = GCBIT(29) | GDBITS3(17,18,19),
271 [GTE_AVSZ4] = GCBIT(30) | GDBITS4(16,17,18,19),
272 [GTE_RTPT] = 0x1f0000ff00000000ll | GDBITS7(0,1,2,3,4,5,19),
273 [GTE_GPF] = GDBITS7(6,8,9,10,11,21,22),
274 [GTE_GPL] = GDBITS10(6,8,9,10,11,21,22,25,26,27),
275 [GTE_NCCT] = 0x001fff0000000000ll | GDBITS7(0,1,2,3,4,5,6),
276};
277
278// note: this excludes gteFLAG that is always written to
279const uint64_t gte_reg_writes[64] = {
280 [GTE_RTPS] = 0x0f0f7f00ll,
281 [GTE_NCLIP] = GDBIT(24),
282 [GTE_OP] = GDBITS6(9,10,11,25,26,27),
283 [GTE_DPCS] = GDBITS9(9,10,11,20,21,22,25,26,27),
284 [GTE_INTPL] = GDBITS9(9,10,11,20,21,22,25,26,27),
285 [GTE_MVMVA] = GDBITS6(9,10,11,25,26,27),
286 [GTE_NCDS] = GDBITS9(9,10,11,20,21,22,25,26,27),
287 [GTE_CDP] = GDBITS9(9,10,11,20,21,22,25,26,27),
288 [GTE_NCDT] = GDBITS9(9,10,11,20,21,22,25,26,27),
289 [GTE_NCCS] = GDBITS9(9,10,11,20,21,22,25,26,27),
290 [GTE_CC] = GDBITS9(9,10,11,20,21,22,25,26,27),
291 [GTE_NCS] = GDBITS9(9,10,11,20,21,22,25,26,27),
292 [GTE_NCT] = GDBITS9(9,10,11,20,21,22,25,26,27),
293 [GTE_SQR] = GDBITS6(9,10,11,25,26,27),
294 [GTE_DCPL] = GDBITS9(9,10,11,20,21,22,25,26,27),
295 [GTE_DPCT] = GDBITS9(9,10,11,20,21,22,25,26,27),
296 [GTE_AVSZ3] = GDBITS2(7,24),
297 [GTE_AVSZ4] = GDBITS2(7,24),
298 [GTE_RTPT] = 0x0f0f7f00ll,
299 [GTE_GPF] = GDBITS9(9,10,11,20,21,22,25,26,27),
300 [GTE_GPL] = GDBITS9(9,10,11,20,21,22,25,26,27),
301 [GTE_NCCT] = GDBITS9(9,10,11,20,21,22,25,26,27),
302};
303
f95a77f7 304static int ari64_init()
305{
b9b61529 306 extern void (*psxCP2[64])();
307 extern void psxNULL();
003cfc63 308 extern unsigned char *out;
f95a77f7 309 size_t i;
b9b61529 310
f95a77f7 311 new_dynarec_init();
7e605697 312 new_dyna_pcsx_mem_init();
7139f3c8 313
ae602c19 314 for (i = 0; i < ARRAY_SIZE(gte_handlers); i++)
b9b61529 315 if (psxCP2[i] != psxNULL)
316 gte_handlers[i] = psxCP2[i];
59774ed0 317
665f33e1 318#if defined(__arm__) && !defined(DRC_DBG)
59774ed0 319 gte_handlers[0x06] = gteNCLIP_arm;
665f33e1 320#ifdef HAVE_ARMV5
0c2ca3ba 321 gte_handlers_nf[0x01] = gteRTPS_nf_arm;
322 gte_handlers_nf[0x30] = gteRTPT_nf_arm;
59774ed0 323#endif
a80ae4a0 324#ifdef __ARM_NEON__
054175e9 325 // compiler's _nf version is still a lot slower than neon
0c2ca3ba 326 // _nf_arm RTPS is roughly the same, RTPT slower
59774ed0 327 gte_handlers[0x01] = gte_handlers_nf[0x01] = gteRTPS_neon;
328 gte_handlers[0x30] = gte_handlers_nf[0x30] = gteRTPT_neon;
a80ae4a0 329#endif
d3f3bf09 330#endif
331#ifdef DRC_DBG
332 memcpy(gte_handlers_nf, gte_handlers, sizeof(gte_handlers_nf));
009faf24 333#endif
7e605697 334 psxH_ptr = psxH;
054175e9 335 zeromem_ptr = zero_mem;
c6d5790c 336 scratch_buf_ptr = scratch_buf;
7e605697 337
0069615f 338 SysPrintf("Mapped (RAM/scrp/ROM/LUTs/TC):\n");
339 SysPrintf("%08x/%08x/%08x/%08x/%08x\n",
340 psxM, psxH, psxR, mem_rtab, out);
341
b9b61529 342 return 0;
f95a77f7 343}
344
345static void ari64_reset()
346{
f95a77f7 347 printf("ari64_reset\n");
7e605697 348 new_dyna_pcsx_mem_reset();
4b421010 349 invalidate_all_pages();
7f457614 350 new_dyna_restore();
4b421010 351 pending_exception = 1;
f95a77f7 352}
353
e4eb18c1 354// execute until predefined leave points
355// (HLE softcall exit and BIOS fastboot end)
356static void ari64_execute_until()
f95a77f7 357{
654e8cfb 358 schedule_timeslice();
359
360 evprintf("ari64_execute %08x, %u->%u (%d)\n", psxRegs.pc,
361 psxRegs.cycle, next_interupt, next_interupt - psxRegs.cycle);
7139f3c8 362
b9b61529 363 new_dyna_start();
654e8cfb 364
365 evprintf("ari64_execute end %08x, %u->%u (%d)\n", psxRegs.pc,
366 psxRegs.cycle, next_interupt, next_interupt - psxRegs.cycle);
f95a77f7 367}
368
e4eb18c1 369static void ari64_execute()
370{
371 while (!stop) {
372 ari64_execute_until();
373 evprintf("drc left @%08x\n", psxRegs.pc);
374 }
375}
376
4b421010 377static void ari64_clear(u32 addr, u32 size)
f95a77f7 378{
0ce47d46 379 u32 start, end, main_ram;
4b421010 380
58ebb94c 381 size *= 4; /* PCSX uses DMA units (words) */
76739a08 382
4b421010 383 evprintf("ari64_clear %08x %04x\n", addr, size);
384
385 /* check for RAM mirrors */
0ce47d46 386 main_ram = (addr & 0xffe00000) == 0x80000000;
4b421010 387
388 start = addr >> 12;
389 end = (addr + size) >> 12;
390
391 for (; start <= end; start++)
0ce47d46 392 if (!main_ram || !invalid_code[start])
4b421010 393 invalidate_block(start);
f95a77f7 394}
395
943a507a 396#ifdef ICACHE_EMULATION
397static void ari64_notify(int note, void *data) {
398 /*
399 Should be fixed when ARM dynarec has proper icache emulation.
400 switch (note)
401 {
402 case R3000ACPU_NOTIFY_CACHE_UNISOLATED:
403 break;
404 case R3000ACPU_NOTIFY_CACHE_ISOLATED:
405 Sent from psxDma3().
406 case R3000ACPU_NOTIFY_DMA3_EXE_LOAD:
407 default:
408 break;
409 }
410 */
411}
412#endif
413
f95a77f7 414static void ari64_shutdown()
415{
416 new_dynarec_cleanup();
92879b62 417 new_dyna_pcsx_mem_shutdown();
f95a77f7 418}
419
7139f3c8 420extern void intExecute();
421extern void intExecuteT();
422extern void intExecuteBlock();
423extern void intExecuteBlockT();
424#ifndef DRC_DBG
425#define intExecuteT intExecute
426#define intExecuteBlockT intExecuteBlock
427#endif
428
f95a77f7 429R3000Acpu psxRec = {
430 ari64_init,
431 ari64_reset,
448bbcae 432#ifndef DRC_DISABLE
f95a77f7 433 ari64_execute,
e4eb18c1 434 ari64_execute_until,
7139f3c8 435#else
436 intExecuteT,
437 intExecuteBlockT,
438#endif
f95a77f7 439 ari64_clear,
943a507a 440#ifdef ICACHE_EMULATION
441 ari64_notify,
442#endif
f95a77f7 443 ari64_shutdown
444};
7139f3c8 445
446// TODO: rm
447#ifndef DRC_DBG
448void do_insn_trace() {}
449void do_insn_cmp() {}
450#endif
451
448bbcae 452#ifdef DRC_DISABLE
054175e9 453unsigned int address;
ccf51908 454int pending_exception, stop;
7139f3c8 455unsigned int next_interupt;
2f546f9a 456int new_dynarec_did_compile;
2573466a 457int cycle_multiplier;
0ff8c62c 458int new_dynarec_hacks;
7e605697 459void *psxH_ptr;
054175e9 460void *zeromem_ptr;
461u8 zero_mem[0x1000];
003cfc63 462unsigned char *out;
0069615f 463void *mem_rtab;
c6d5790c 464void *scratch_buf_ptr;
448bbcae 465void new_dynarec_init() { (void)ari64_execute; }
3eb78778 466void new_dyna_start() {}
7139f3c8 467void new_dynarec_cleanup() {}
2c886904 468void new_dynarec_clear_full() {}
ccf51908 469void invalidate_all_pages() {}
470void invalidate_block(unsigned int block) {}
7e605697 471void new_dyna_pcsx_mem_init(void) {}
472void new_dyna_pcsx_mem_reset(void) {}
b1be1eee 473void new_dyna_pcsx_mem_load_state(void) {}
92879b62 474void new_dyna_pcsx_mem_shutdown(void) {}
03f55e6b 475int new_dynarec_save_blocks(void *save, int size) { return 0; }
476void new_dynarec_load_blocks(const void *save, int size) {}
7139f3c8 477#endif
478
479#ifdef DRC_DBG
480
481#include <stddef.h>
482static FILE *f;
483extern u32 last_io_addr;
484
485static void dump_mem(const char *fname, void *mem, size_t size)
486{
487 FILE *f1 = fopen(fname, "wb");
3eb78778 488 if (f1 == NULL)
489 f1 = fopen(strrchr(fname, '/') + 1, "wb");
7139f3c8 490 fwrite(mem, 1, size, f1);
491 fclose(f1);
492}
493
2185e39b 494static u32 memcheck_read(u32 a)
495{
496 if ((a >> 16) == 0x1f80)
497 // scratchpad/IO
498 return *(u32 *)(psxH + (a & 0xfffc));
499
500 if ((a >> 16) == 0x1f00)
501 // parallel
502 return *(u32 *)(psxP + (a & 0xfffc));
503
504// if ((a & ~0xe0600000) < 0x200000)
505 // RAM
506 return *(u32 *)(psxM + (a & 0x1ffffc));
507}
508
7139f3c8 509void do_insn_trace(void)
510{
511 static psxRegisters oldregs;
512 static u32 old_io_addr = (u32)-1;
513 static u32 old_io_data = 0xbad0c0de;
19776aef 514 static u32 event_cycles_o[PSXINT_COUNT];
7139f3c8 515 u32 *allregs_p = (void *)&psxRegs;
516 u32 *allregs_o = (void *)&oldregs;
2185e39b 517 u32 io_data;
7139f3c8 518 int i;
519 u8 byte;
520
19776aef 521 //last_io_addr = 0x5e2c8;
7139f3c8 522 if (f == NULL)
523 f = fopen("tracelog", "wb");
524
19776aef 525 // log reg changes
7139f3c8 526 oldregs.code = psxRegs.code; // don't care
527 for (i = 0; i < offsetof(psxRegisters, intCycle) / 4; i++) {
528 if (allregs_p[i] != allregs_o[i]) {
529 fwrite(&i, 1, 1, f);
530 fwrite(&allregs_p[i], 1, 4, f);
531 allregs_o[i] = allregs_p[i];
532 }
533 }
19776aef 534 // log event changes
535 for (i = 0; i < PSXINT_COUNT; i++) {
536 if (event_cycles[i] != event_cycles_o[i]) {
537 byte = 0xfc;
538 fwrite(&byte, 1, 1, f);
539 fwrite(&i, 1, 1, f);
540 fwrite(&event_cycles[i], 1, 4, f);
541 event_cycles_o[i] = event_cycles[i];
542 }
543 }
544 // log last io
7139f3c8 545 if (old_io_addr != last_io_addr) {
546 byte = 0xfd;
547 fwrite(&byte, 1, 1, f);
548 fwrite(&last_io_addr, 1, 4, f);
549 old_io_addr = last_io_addr;
550 }
2185e39b 551 io_data = memcheck_read(last_io_addr);
552 if (old_io_data != io_data) {
7139f3c8 553 byte = 0xfe;
554 fwrite(&byte, 1, 1, f);
2185e39b 555 fwrite(&io_data, 1, 4, f);
556 old_io_data = io_data;
7139f3c8 557 }
558 byte = 0xff;
559 fwrite(&byte, 1, 1, f);
560
561#if 0
562 if (psxRegs.cycle == 190230) {
563 dump_mem("/mnt/ntz/dev/pnd/tmp/psxram_i.dump", psxM, 0x200000);
564 dump_mem("/mnt/ntz/dev/pnd/tmp/psxregs_i.dump", psxH, 0x10000);
565 printf("dumped\n");
566 exit(1);
567 }
568#endif
569}
570
571static const char *regnames[offsetof(psxRegisters, intCycle) / 4] = {
572 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
573 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
574 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
575 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
576 "lo", "hi",
577 "C0_0", "C0_1", "C0_2", "C0_3", "C0_4", "C0_5", "C0_6", "C0_7",
578 "C0_8", "C0_9", "C0_10", "C0_11", "C0_12", "C0_13", "C0_14", "C0_15",
579 "C0_16", "C0_17", "C0_18", "C0_19", "C0_20", "C0_21", "C0_22", "C0_23",
580 "C0_24", "C0_25", "C0_26", "C0_27", "C0_28", "C0_29", "C0_30", "C0_31",
581
582 "C2D0", "C2D1", "C2D2", "C2D3", "C2D4", "C2D5", "C2D6", "C2D7",
583 "C2D8", "C2D9", "C2D10", "C2D11", "C2D12", "C2D13", "C2D14", "C2D15",
584 "C2D16", "C2D17", "C2D18", "C2D19", "C2D20", "C2D21", "C2D22", "C2D23",
585 "C2D24", "C2D25", "C2D26", "C2D27", "C2D28", "C2D29", "C2D30", "C2D31",
586
587 "C2C0", "C2C1", "C2C2", "C2C3", "C2C4", "C2C5", "C2C6", "C2C7",
588 "C2C8", "C2C9", "C2C10", "C2C11", "C2C12", "C2C13", "C2C14", "C2C15",
589 "C2C16", "C2C17", "C2C18", "C2C19", "C2C20", "C2C21", "C2C22", "C2C23",
590 "C2C24", "C2C25", "C2C26", "C2C27", "C2C28", "C2C29", "C2C30", "C2C31",
591
592 "PC", "code", "cycle", "interrupt",
593};
594
3eb78778 595static struct {
596 int reg;
597 u32 val, val_expect;
598 u32 pc, cycle;
599} miss_log[64];
600static int miss_log_i;
601#define miss_log_len (sizeof(miss_log)/sizeof(miss_log[0]))
602#define miss_log_mask (miss_log_len-1)
603
604static void miss_log_add(int reg, u32 val, u32 val_expect, u32 pc, u32 cycle)
605{
606 miss_log[miss_log_i].reg = reg;
607 miss_log[miss_log_i].val = val;
608 miss_log[miss_log_i].val_expect = val_expect;
609 miss_log[miss_log_i].pc = pc;
610 miss_log[miss_log_i].cycle = cycle;
611 miss_log_i = (miss_log_i + 1) & miss_log_mask;
612}
613
7139f3c8 614void breakme() {}
615
616void do_insn_cmp(void)
617{
618 static psxRegisters rregs;
619 static u32 mem_addr, mem_val;
620 u32 *allregs_p = (void *)&psxRegs;
621 u32 *allregs_e = (void *)&rregs;
622 static u32 ppc, failcount;
19776aef 623 int i, ret, bad = 0, which_event = -1;
624 u32 ev_cycles = 0;
7139f3c8 625 u8 code;
626
627 if (f == NULL)
628 f = fopen("tracelog", "rb");
629
630 while (1) {
631 if ((ret = fread(&code, 1, 1, f)) <= 0)
632 break;
633 if (ret <= 0)
634 break;
635 if (code == 0xff)
636 break;
19776aef 637 switch (code) {
638 case 0xfc:
639 which_event = 0;
640 fread(&which_event, 1, 1, f);
641 fread(&ev_cycles, 1, 4, f);
7139f3c8 642 continue;
19776aef 643 case 0xfd:
644 fread(&mem_addr, 1, 4, f);
645 continue;
646 case 0xfe:
647 fread(&mem_val, 1, 4, f);
7139f3c8 648 continue;
649 }
19776aef 650 fread(&allregs_e[code], 1, 4, f);
7139f3c8 651 }
652
653 if (ret <= 0) {
654 printf("EOF?\n");
655 goto end;
656 }
657
658 psxRegs.code = rregs.code; // don't care
2185e39b 659 psxRegs.cycle = rregs.cycle;
660 psxRegs.CP0.r[9] = rregs.CP0.r[9]; // Count
7139f3c8 661
19776aef 662 //if (psxRegs.cycle == 166172) breakme();
7139f3c8 663
664 if (memcmp(&psxRegs, &rregs, offsetof(psxRegisters, intCycle)) == 0 &&
2185e39b 665 mem_val == memcheck_read(mem_addr)
7139f3c8 666 ) {
667 failcount = 0;
668 goto ok;
669 }
670
671 for (i = 0; i < offsetof(psxRegisters, intCycle) / 4; i++) {
672 if (allregs_p[i] != allregs_e[i]) {
3eb78778 673 miss_log_add(i, allregs_p[i], allregs_e[i], psxRegs.pc, psxRegs.cycle);
7139f3c8 674 bad++;
675 }
676 }
677
2185e39b 678 if (mem_val != memcheck_read(mem_addr)) {
679 printf("bad mem @%08x: %08x %08x\n", mem_addr, memcheck_read(mem_addr), mem_val);
7139f3c8 680 goto end;
19776aef 681 }
682
683 if (which_event >= 0 && event_cycles[which_event] != ev_cycles) {
684 printf("bad ev_cycles #%d: %08x %08x\n", which_event, event_cycles[which_event], ev_cycles);
685 goto end;
7139f3c8 686 }
687
688 if (psxRegs.pc == rregs.pc && bad < 6 && failcount < 32) {
3eb78778 689 static int last_mcycle;
690 if (last_mcycle != psxRegs.cycle >> 20) {
691 printf("%u\n", psxRegs.cycle);
692 last_mcycle = psxRegs.cycle >> 20;
693 }
7139f3c8 694 failcount++;
695 goto ok;
696 }
697
698end:
3eb78778 699 for (i = 0; i < miss_log_len; i++, miss_log_i = (miss_log_i + 1) & miss_log_mask)
700 printf("bad %5s: %08x %08x, pc=%08x, cycle %u\n",
701 regnames[miss_log[miss_log_i].reg], miss_log[miss_log_i].val,
702 miss_log[miss_log_i].val_expect, miss_log[miss_log_i].pc, miss_log[miss_log_i].cycle);
703 printf("-- %d\n", bad);
704 for (i = 0; i < 8; i++)
705 printf("r%d=%08x r%2d=%08x r%2d=%08x r%2d=%08x\n", i, allregs_p[i],
87c06e51 706 i+8, allregs_p[i+8], i+16, allregs_p[i+16], i+24, allregs_p[i+24]);
7139f3c8 707 printf("PC: %08x/%08x, cycle %u\n", psxRegs.pc, ppc, psxRegs.cycle);
708 dump_mem("/mnt/ntz/dev/pnd/tmp/psxram.dump", psxM, 0x200000);
709 dump_mem("/mnt/ntz/dev/pnd/tmp/psxregs.dump", psxH, 0x10000);
710 exit(1);
711ok:
712 psxRegs.cycle = rregs.cycle + 2; // sync timing
713 ppc = psxRegs.pc;
714}
715
716#endif
ARM optimized PCSX fork