[pcsx_rearmed.git] / libpcsxcore / new_dynarec / emu_if.h

#include "new_dynarec.h"
#include "../r3000a.h"

extern char invalid_code[0x100000];

/* weird stuff */
#define EAX 0
#define ECX 1

/* same as psxRegs */
extern int reg[];

/* same as psxRegs.GPR.n.* */
extern int hi, lo;

/* same as psxRegs.CP0.n.* */
extern int reg_cop0[];
#define Status   psxRegs.CP0.n.Status
#define Cause    psxRegs.CP0.n.Cause
#define EPC      psxRegs.CP0.n.EPC
#define BadVAddr psxRegs.CP0.n.BadVAddr
#define Context  psxRegs.CP0.n.Context
#define EntryHi  psxRegs.CP0.n.EntryHi
#define Count    psxRegs.cycle // psxRegs.CP0.n.Count

/* COP2/GTE */
enum gte_opcodes {
	GTE_RTPS	= 0x01,
	GTE_NCLIP	= 0x06,
	GTE_OP		= 0x0c,
	GTE_DPCS	= 0x10,
	GTE_INTPL	= 0x11,
	GTE_MVMVA	= 0x12,
	GTE_NCDS	= 0x13,
	GTE_CDP		= 0x14,
	GTE_NCDT	= 0x16,
	GTE_NCCS	= 0x1b,
	GTE_CC		= 0x1c,
	GTE_NCS		= 0x1e,
	GTE_NCT		= 0x20,
	GTE_SQR		= 0x28,
	GTE_DCPL	= 0x29,
	GTE_DPCT	= 0x2a,
	GTE_AVSZ3	= 0x2d,
	GTE_AVSZ4	= 0x2e,
	GTE_RTPT	= 0x30,
	GTE_GPF		= 0x3d,
	GTE_GPL		= 0x3e,
	GTE_NCCT	= 0x3f,
};

extern int reg_cop2d[], reg_cop2c[];
extern void *gte_handlers[64];
extern void *gte_handlers_nf[64];
extern const char *gte_regnames[64];
extern const char gte_cycletab[64];
extern const uint64_t gte_reg_reads[64];
extern const uint64_t gte_reg_writes[64];

/* dummy */
extern int FCR0, FCR31;

/* mem */
extern void *mem_rtab;
extern void *mem_wtab;

void jump_handler_read8(u32 addr, u32 *table, u32 cycles);
void jump_handler_read16(u32 addr, u32 *table, u32 cycles);
void jump_handler_read32(u32 addr, u32 *table, u32 cycles);
void jump_handler_write8(u32 addr, u32 data, u32 cycles, u32 *table);
void jump_handler_write16(u32 addr, u32 data, u32 cycles, u32 *table);
void jump_handler_write32(u32 addr, u32 data, u32 cycles, u32 *table);
void jump_handler_write_h(u32 addr, u32 data, u32 cycles, void *handler);
void jump_handle_swl(u32 addr, u32 data, u32 cycles);
void jump_handle_swr(u32 addr, u32 data, u32 cycles);
void rcnt0_read_count_m0(u32 addr, u32, u32 cycles);
void rcnt0_read_count_m1(u32 addr, u32, u32 cycles);
void rcnt1_read_count_m0(u32 addr, u32, u32 cycles);
void rcnt1_read_count_m1(u32 addr, u32, u32 cycles);
void rcnt2_read_count_m0(u32 addr, u32, u32 cycles);
void rcnt2_read_count_m1(u32 addr, u32, u32 cycles);

extern unsigned int address;
extern void *psxH_ptr;
extern void *zeromem_ptr;

// same as invalid_code, just a region for ram write checks (inclusive)
extern u32 inv_code_start, inv_code_end;

/* cycles/irqs */
extern unsigned int next_interupt;
extern int pending_exception;

/* called by drc */
void pcsx_mtc0(u32 reg, u32 val);
void pcsx_mtc0_ds(u32 reg, u32 val);

/* misc */
extern void (*psxHLEt[])();
Commit	Line	Data
7139f3c8	1	#include "new_dynarec.h"
3d624f89	2	#include "../r3000a.h"
	3
	4	extern char invalid_code[0x100000];
	5
	6	/* weird stuff */
	7	#define EAX 0
	8	#define ECX 1
	9
	10	/* same as psxRegs */
	11	extern int reg[];
	12
	13	/* same as psxRegs.GPR.n.* */
	14	extern int hi, lo;
	15
	16	/* same as psxRegs.CP0.n.* */
7139f3c8	17	extern int reg_cop0[];
3d624f89	18	#define Status psxRegs.CP0.n.Status
	19	#define Cause psxRegs.CP0.n.Cause
	20	#define EPC psxRegs.CP0.n.EPC
	21	#define BadVAddr psxRegs.CP0.n.BadVAddr
	22	#define Context psxRegs.CP0.n.Context
	23	#define EntryHi psxRegs.CP0.n.EntryHi
822b27d1	24	#define Count psxRegs.cycle // psxRegs.CP0.n.Count
3d624f89	25
b9b61529	26	/* COP2/GTE */
054175e9	27	enum gte_opcodes {
	28	GTE_RTPS = 0x01,
	29	GTE_NCLIP = 0x06,
	30	GTE_OP = 0x0c,
	31	GTE_DPCS = 0x10,
	32	GTE_INTPL = 0x11,
	33	GTE_MVMVA = 0x12,
	34	GTE_NCDS = 0x13,
	35	GTE_CDP = 0x14,
	36	GTE_NCDT = 0x16,
	37	GTE_NCCS = 0x1b,
	38	GTE_CC = 0x1c,
	39	GTE_NCS = 0x1e,
	40	GTE_NCT = 0x20,
	41	GTE_SQR = 0x28,
	42	GTE_DCPL = 0x29,
	43	GTE_DPCT = 0x2a,
	44	GTE_AVSZ3 = 0x2d,
	45	GTE_AVSZ4 = 0x2e,
	46	GTE_RTPT = 0x30,
	47	GTE_GPF = 0x3d,
	48	GTE_GPL = 0x3e,
	49	GTE_NCCT = 0x3f,
	50	};
	51
b9b61529	52	extern int reg_cop2d[], reg_cop2c[];
b9b61529	53	extern void *gte_handlers[64];
59774ed0	54	extern void *gte_handlers_nf[64];
bedfea38	55	extern const char *gte_regnames[64];
b9b61529	56	extern const char gte_cycletab[64];
2167bef6	57	extern const uint64_t gte_reg_reads[64];
2167bef6	58	extern const uint64_t gte_reg_writes[64];
b9b61529	59
3d624f89	60	/* dummy */
	61	extern int FCR0, FCR31;
	62
	63	/* mem */
c6c3b1b3	64	extern void *mem_rtab;
	65	extern void *mem_wtab;
	66
	67	void jump_handler_read8(u32 addr, u32 *table, u32 cycles);
	68	void jump_handler_read16(u32 addr, u32 *table, u32 cycles);
	69	void jump_handler_read32(u32 addr, u32 *table, u32 cycles);
b96d3df7	70	void jump_handler_write8(u32 addr, u32 data, u32 cycles, u32 *table);
	71	void jump_handler_write16(u32 addr, u32 data, u32 cycles, u32 *table);
	72	void jump_handler_write32(u32 addr, u32 data, u32 cycles, u32 *table);
	73	void jump_handler_write_h(u32 addr, u32 data, u32 cycles, void *handler);
	74	void jump_handle_swl(u32 addr, u32 data, u32 cycles);
	75	void jump_handle_swr(u32 addr, u32 data, u32 cycles);
b1be1eee	76	void rcnt0_read_count_m0(u32 addr, u32, u32 cycles);
	77	void rcnt0_read_count_m1(u32 addr, u32, u32 cycles);
	78	void rcnt1_read_count_m0(u32 addr, u32, u32 cycles);
	79	void rcnt1_read_count_m1(u32 addr, u32, u32 cycles);
	80	void rcnt2_read_count_m0(u32 addr, u32, u32 cycles);
	81	void rcnt2_read_count_m1(u32 addr, u32, u32 cycles);
c6c3b1b3	82
f95a77f7	83	extern unsigned int address;
cbbab9cd	84	extern void *psxH_ptr;
054175e9	85	extern void *zeromem_ptr;
cbbab9cd	86
9be4ba64	87	// same as invalid_code, just a region for ram write checks (inclusive)
	88	extern u32 inv_code_start, inv_code_end;
	89
7139f3c8	90	/* cycles/irqs */
3d624f89	91	extern unsigned int next_interupt;
7139f3c8	92	extern int pending_exception;
3d624f89	93
3d624f89	94	/* called by drc */
63cb0298	95	void pcsx_mtc0(u32 reg, u32 val);
63cb0298	96	void pcsx_mtc0_ds(u32 reg, u32 val);
3d624f89	97
7139f3c8	98	/* misc */
67ba0fb4	99	extern void (*psxHLEt[])();