[pcsx_rearmed.git] / libpcsxcore / new_dynarec / emu_if.h

#include "new_dynarec.h"
#include "../r3000a.h"

extern char invalid_code[0x100000];

/* weird stuff */
#define EAX 0
#define ECX 1

/* same as psxRegs */
extern int reg[];

/* same as psxRegs.GPR.n.* */
extern int hi, lo;

/* same as psxRegs.CP0.n.* */
extern int reg_cop0[];
#define Status   psxRegs.CP0.n.Status
#define Cause    psxRegs.CP0.n.Cause
#define EPC      psxRegs.CP0.n.EPC
#define BadVAddr psxRegs.CP0.n.BadVAddr
#define Context  psxRegs.CP0.n.Context
#define EntryHi  psxRegs.CP0.n.EntryHi
#define Count    psxRegs.cycle // psxRegs.CP0.n.Count

/* COP2/GTE */
extern int reg_cop2d[], reg_cop2c[];
extern void *gte_handlers[64];
extern void *gte_handlers_nf[64];
extern const char *gte_regnames[64];
extern const char gte_cycletab[64];
extern const uint64_t gte_reg_reads[64];
extern const uint64_t gte_reg_writes[64];

/* dummy */
extern int FCR0, FCR31;

/* mem */
extern void *mem_rtab;
extern void *mem_wtab;

void jump_handler_read8(u32 addr, u32 *table, u32 cycles);
void jump_handler_read16(u32 addr, u32 *table, u32 cycles);
void jump_handler_read32(u32 addr, u32 *table, u32 cycles);
void jump_handler_write8(u32 addr, u32 data, u32 cycles, u32 *table);
void jump_handler_write16(u32 addr, u32 data, u32 cycles, u32 *table);
void jump_handler_write32(u32 addr, u32 data, u32 cycles, u32 *table);
void jump_handler_write_h(u32 addr, u32 data, u32 cycles, void *handler);
void jump_handle_swl(u32 addr, u32 data, u32 cycles);
void jump_handle_swr(u32 addr, u32 data, u32 cycles);
void rcnt0_read_count_m0(u32 addr, u32, u32 cycles);
void rcnt0_read_count_m1(u32 addr, u32, u32 cycles);
void rcnt1_read_count_m0(u32 addr, u32, u32 cycles);
void rcnt1_read_count_m1(u32 addr, u32, u32 cycles);
void rcnt2_read_count_m0(u32 addr, u32, u32 cycles);
void rcnt2_read_count_m1(u32 addr, u32, u32 cycles);

extern unsigned int address;
extern void *psxH_ptr;

// same as invalid_code, just a region for ram write checks (inclusive)
extern u32 inv_code_start, inv_code_end;

/* cycles/irqs */
extern unsigned int next_interupt;
extern int pending_exception;

/* called by drc */
void pcsx_mtc0(u32 reg, u32 val);
void pcsx_mtc0_ds(u32 reg, u32 val);

/* misc */
extern void (*psxHLEt[])();
Commit	Line	Data
7139f3c8	1	#include "new_dynarec.h"
3d624f89	2	#include "../r3000a.h"
	3
	4	extern char invalid_code[0x100000];
	5
	6	/* weird stuff */
	7	#define EAX 0
	8	#define ECX 1
	9
	10	/* same as psxRegs */
	11	extern int reg[];
	12
	13	/* same as psxRegs.GPR.n.* */
	14	extern int hi, lo;
	15
	16	/* same as psxRegs.CP0.n.* */
7139f3c8	17	extern int reg_cop0[];
3d624f89	18	#define Status psxRegs.CP0.n.Status
	19	#define Cause psxRegs.CP0.n.Cause
	20	#define EPC psxRegs.CP0.n.EPC
	21	#define BadVAddr psxRegs.CP0.n.BadVAddr
	22	#define Context psxRegs.CP0.n.Context
	23	#define EntryHi psxRegs.CP0.n.EntryHi
822b27d1	24	#define Count psxRegs.cycle // psxRegs.CP0.n.Count
3d624f89	25
b9b61529	26	/* COP2/GTE */
	27	extern int reg_cop2d[], reg_cop2c[];
	28	extern void *gte_handlers[64];
59774ed0	29	extern void *gte_handlers_nf[64];
bedfea38	30	extern const char *gte_regnames[64];
b9b61529	31	extern const char gte_cycletab[64];
2167bef6	32	extern const uint64_t gte_reg_reads[64];
2167bef6	33	extern const uint64_t gte_reg_writes[64];
b9b61529	34
3d624f89	35	/* dummy */
	36	extern int FCR0, FCR31;
	37
	38	/* mem */
c6c3b1b3	39	extern void *mem_rtab;
	40	extern void *mem_wtab;
	41
	42	void jump_handler_read8(u32 addr, u32 *table, u32 cycles);
	43	void jump_handler_read16(u32 addr, u32 *table, u32 cycles);
	44	void jump_handler_read32(u32 addr, u32 *table, u32 cycles);
b96d3df7	45	void jump_handler_write8(u32 addr, u32 data, u32 cycles, u32 *table);
	46	void jump_handler_write16(u32 addr, u32 data, u32 cycles, u32 *table);
	47	void jump_handler_write32(u32 addr, u32 data, u32 cycles, u32 *table);
	48	void jump_handler_write_h(u32 addr, u32 data, u32 cycles, void *handler);
	49	void jump_handle_swl(u32 addr, u32 data, u32 cycles);
	50	void jump_handle_swr(u32 addr, u32 data, u32 cycles);
b1be1eee	51	void rcnt0_read_count_m0(u32 addr, u32, u32 cycles);
	52	void rcnt0_read_count_m1(u32 addr, u32, u32 cycles);
	53	void rcnt1_read_count_m0(u32 addr, u32, u32 cycles);
	54	void rcnt1_read_count_m1(u32 addr, u32, u32 cycles);
	55	void rcnt2_read_count_m0(u32 addr, u32, u32 cycles);
	56	void rcnt2_read_count_m1(u32 addr, u32, u32 cycles);
c6c3b1b3	57
f95a77f7	58	extern unsigned int address;
cbbab9cd	59	extern void *psxH_ptr;
cbbab9cd	60
9be4ba64	61	// same as invalid_code, just a region for ram write checks (inclusive)
	62	extern u32 inv_code_start, inv_code_end;
	63
7139f3c8	64	/* cycles/irqs */
3d624f89	65	extern unsigned int next_interupt;
7139f3c8	66	extern int pending_exception;
3d624f89	67
3d624f89	68	/* called by drc */
63cb0298	69	void pcsx_mtc0(u32 reg, u32 val);
63cb0298	70	void pcsx_mtc0_ds(u32 reg, u32 val);
3d624f89	71
7139f3c8	72	/* misc */
67ba0fb4	73	extern void (*psxHLEt[])();