[pcsx_rearmed.git] / libpcsxcore / new_dynarec / linkage_arm.S

/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
 *   linkage_arm.s for PCSX                                                *
 *   Copyright (C) 2009-2011 Ari64                                         *
 *   Copyright (C) 2010-2013 Gražvydas "notaz" Ignotas                     *
 *                                                                         *
 *   This program is free software; you can redistribute it and/or modify  *
 *   it under the terms of the GNU General Public License as published by  *
 *   the Free Software Foundation; either version 2 of the License, or     *
 *   (at your option) any later version.                                   *
 *                                                                         *
 *   This program is distributed in the hope that it will be useful,       *
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
 *   GNU General Public License for more details.                          *
 *                                                                         *
 *   You should have received a copy of the GNU General Public License     *
 *   along with this program; if not, write to the                         *
 *   Free Software Foundation, Inc.,                                       *
 *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.          *
 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */

#include "arm_features.h"
#include "new_dynarec_config.h"
#include "linkage_offsets.h"


#ifdef __MACH__
#define dynarec_local		ESYM(dynarec_local)
#define ndrc_add_jump_out	ESYM(ndrc_add_jump_out)
#define ndrc_try_restore_block	ESYM(ndrc_try_restore_block)
#define ndrc_get_addr_ht	ESYM(ndrc_get_addr_ht)
#define ndrc_get_addr_ht_param	ESYM(ndrc_get_addr_ht_param)
#define ndrc_invalidate_addr	ESYM(ndrc_invalidate_addr)
#define gen_interupt		ESYM(gen_interupt)
#define gteCheckStallRaw	ESYM(gteCheckStallRaw)
#define psxException		ESYM(psxException)
#endif

	.bss
	.align	4
	.global dynarec_local
	.type	dynarec_local, %object
	.size	dynarec_local, LO_dynarec_local_size
dynarec_local:
	.space	LO_dynarec_local_size

#define DRC_VAR_(name, vname, size_) \
	vname = dynarec_local + LO_##name; \
	.global vname; \
	.type	vname, %object; \
	.size	vname, size_

#define DRC_VAR(name, size_) \
	DRC_VAR_(name, ESYM(name), size_)

DRC_VAR(next_interupt, 4)
DRC_VAR(cycle_count, 4)
DRC_VAR(last_count, 4)
DRC_VAR(pending_exception, 4)
DRC_VAR(stop, 4)
DRC_VAR(branch_target, 4)
DRC_VAR(address, 4)
DRC_VAR(hack_addr, 4)
DRC_VAR(psxRegs, LO_psxRegs_end - LO_psxRegs)

/* psxRegs */
@DRC_VAR(reg, 128)
DRC_VAR(lo, 4)
DRC_VAR(hi, 4)
DRC_VAR(reg_cop0, 128)
DRC_VAR(reg_cop2d, 128)
DRC_VAR(reg_cop2c, 128)
DRC_VAR(pcaddr, 4)
@DRC_VAR(code, 4)
@DRC_VAR(cycle, 4)
@DRC_VAR(interrupt, 4)
@DRC_VAR(intCycle, 256)

DRC_VAR(rcnts, 7*4*4)
DRC_VAR(inv_code_start, 4)
DRC_VAR(inv_code_end, 4)
DRC_VAR(mem_rtab, 4)
DRC_VAR(mem_wtab, 4)
DRC_VAR(psxH_ptr, 4)
DRC_VAR(zeromem_ptr, 4)
DRC_VAR(invc_ptr, 4)
DRC_VAR(scratch_buf_ptr, 4)
DRC_VAR(ram_offset, 4)
DRC_VAR(mini_ht, 256)


	.syntax unified
	.text
	.align	2

#ifndef HAVE_ARMV5
.macro blx rd
	mov	lr, pc
	bx	\rd
.endm
#endif

.macro load_varadr reg var
#if defined(HAVE_ARMV7) && defined(TEXRELS_FORBIDDEN)
	movw	\reg, #:lower16:(\var-(1678f+8))
	movt	\reg, #:upper16:(\var-(1678f+8))
1678:
	add	\reg, pc
#elif defined(HAVE_ARMV7) && !defined(__PIC__)
	movw	\reg, #:lower16:\var
	movt	\reg, #:upper16:\var
#else
	ldr	\reg, =\var
#endif
.endm

.macro load_varadr_ext reg var
#if defined(HAVE_ARMV7) && defined(TEXRELS_FORBIDDEN)
	movw	\reg, #:lower16:(ptr_\var-(1678f+8))
	movt	\reg, #:upper16:(ptr_\var-(1678f+8))
1678:
	ldr	\reg, [pc, \reg]
#else
	load_varadr \reg \var
#endif
.endm

.macro mov_16 reg imm
#ifdef HAVE_ARMV7
	movw	\reg, #\imm
#else
	mov	\reg, #(\imm & 0x00ff)
	orr	\reg, #(\imm & 0xff00)
#endif
.endm

.macro mov_24 reg imm
#ifdef HAVE_ARMV7
	movw	\reg, #(\imm & 0xffff)
	movt	\reg, #(\imm >> 16)
#else
	mov	\reg, #(\imm & 0x0000ff)
	orr	\reg, #(\imm & 0x00ff00)
	orr	\reg, #(\imm & 0xff0000)
#endif
.endm

FUNCTION(dyna_linker):
	/* r0 = virtual target address */
	/* r1 = pointer to an instruction to patch */
#ifndef NO_WRITE_EXEC
	ldr	r7, [r1]
	mov	r4, r0
	add	r6, r7, #2
	mov	r5, r1
	lsl	r6, r6, #8
	/* must not compile - that might expire the caller block */
	mov	r1, #0
	bl	ndrc_get_addr_ht_param

	movs	r8, r0
	beq	0f
	add	r6, r5, r6, asr #6  /* old target */
	teq	r0, r6
	moveq	pc, r0 /* Stale i-cache */
	mov	r0, r4
	mov	r1, r6
	bl	ndrc_add_jump_out

	sub	r2, r8, r5
	and	r1, r7, #0xff000000
	lsl	r2, r2, #6
	sub	r1, r1, #2
	add	r1, r1, r2, lsr #8
	str	r1, [r5]
	mov	pc, r8
0:
	mov	r0, r4
#else
	/* XXX: should be able to do better than this... */
#endif
	bl	ndrc_get_addr_ht
	mov	pc, r0
	.size	dyna_linker, .-dyna_linker

	.align	2
FUNCTION(jump_vaddr_r1):
	mov	r0, r1
	b	jump_vaddr_r0
	.size	jump_vaddr_r1, .-jump_vaddr_r1
FUNCTION(jump_vaddr_r2):
	mov	r0, r2
	b	jump_vaddr_r0
	.size	jump_vaddr_r2, .-jump_vaddr_r2
FUNCTION(jump_vaddr_r3):
	mov	r0, r3
	b	jump_vaddr_r0
	.size	jump_vaddr_r3, .-jump_vaddr_r3
FUNCTION(jump_vaddr_r4):
	mov	r0, r4
	b	jump_vaddr_r0
	.size	jump_vaddr_r4, .-jump_vaddr_r4
FUNCTION(jump_vaddr_r5):
	mov	r0, r5
	b	jump_vaddr_r0
	.size	jump_vaddr_r5, .-jump_vaddr_r5
FUNCTION(jump_vaddr_r6):
	mov	r0, r6
	b	jump_vaddr_r0
	.size	jump_vaddr_r6, .-jump_vaddr_r6
FUNCTION(jump_vaddr_r8):
	mov	r0, r8
	b	jump_vaddr_r0
	.size	jump_vaddr_r8, .-jump_vaddr_r8
FUNCTION(jump_vaddr_r9):
	mov	r0, r9
	b	jump_vaddr_r0
	.size	jump_vaddr_r9, .-jump_vaddr_r9
FUNCTION(jump_vaddr_r10):
	mov	r0, r10
	b	jump_vaddr_r0
	.size	jump_vaddr_r10, .-jump_vaddr_r10
FUNCTION(jump_vaddr_r12):
	mov	r0, r12
	b	jump_vaddr_r0
	.size	jump_vaddr_r12, .-jump_vaddr_r12
FUNCTION(jump_vaddr_r7):
	add	r0, r7, #0
	.size	jump_vaddr_r7, .-jump_vaddr_r7
FUNCTION(jump_vaddr_r0):
	bl	ndrc_get_addr_ht
	mov	pc, r0
	.size	jump_vaddr_r0, .-jump_vaddr_r0

	.align	2
FUNCTION(cc_interrupt):
	ldr	r0, [fp, #LO_last_count]
	mov	r1, #0
	add	r10, r0, r10
	str	r1, [fp, #LO_pending_exception]
	str	r10, [fp, #LO_cycle]		/* PCSX cycles */
@@	str	r10, [fp, #LO_reg_cop0+36]	/* Count - not on PSX */
	mov	r10, lr

	bl	gen_interupt
	mov	lr, r10
	ldr	r10, [fp, #LO_cycle]
	ldr	r0, [fp, #LO_next_interupt]
	ldr	r1, [fp, #LO_pending_exception]
	ldr	r2, [fp, #LO_stop]
	str	r0, [fp, #LO_last_count]
	sub	r10, r10, r0
	tst	r2, r2
	ldmfdne	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}
	tst	r1, r1
	moveq	pc, lr
	ldr	r0, [fp, #LO_pcaddr]
	bl	ndrc_get_addr_ht
	mov	pc, r0
	.size	cc_interrupt, .-cc_interrupt

	.align	2
FUNCTION(fp_exception):
	mov	r2, #0x10000000
.E7:
	ldr	r1, [fp, #LO_reg_cop0+48] /* Status */
	mov	r3, #0x80000000
	str	r0, [fp, #LO_reg_cop0+56] /* EPC */
	orr	r1, #2
	add	r2, r2, #0x2c
	str	r1, [fp, #LO_reg_cop0+48] /* Status */
	str	r2, [fp, #LO_reg_cop0+52] /* Cause */
	add	r0, r3, #0x80
	bl	ndrc_get_addr_ht
	mov	pc, r0
	.size	fp_exception, .-fp_exception
	.align	2
FUNCTION(fp_exception_ds):
	mov	r2, #0x90000000 /* Set high bit if delay slot */
	b	.E7
	.size	fp_exception_ds, .-fp_exception_ds

	.align	2
FUNCTION(jump_break_ds):
	mov	r0, #0x24
	mov	r1, #1
	b	call_psxException
FUNCTION(jump_break):
	mov	r0, #0x24
	mov	r1, #0
	b	call_psxException
FUNCTION(jump_syscall_ds):
	mov	r0, #0x20
	mov	r1, #1
	b	call_psxException
FUNCTION(jump_syscall):
	mov	r0, #0x20
	mov	r1, #0

call_psxException:
	ldr	r3, [fp, #LO_last_count]
	str	r2, [fp, #LO_pcaddr]
	add	r10, r3, r10
	str	r10, [fp, #LO_cycle]		/* PCSX cycles */
	bl	psxException

	/* note: psxException might do recursive recompiler call from it's HLE code,
	 * so be ready for this */
FUNCTION(jump_to_new_pc):
	ldr	r1, [fp, #LO_next_interupt]
	ldr	r10, [fp, #LO_cycle]
	ldr	r0, [fp, #LO_pcaddr]
	sub	r10, r10, r1
	str	r1, [fp, #LO_last_count]
	bl	ndrc_get_addr_ht
	mov	pc, r0
	.size	jump_to_new_pc, .-jump_to_new_pc

	.align	2
FUNCTION(new_dyna_leave):
	ldr	r0, [fp, #LO_last_count]
	add	r12, fp, #28
	add	r10, r0, r10
	str	r10, [fp, #LO_cycle]
	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}
	.size	new_dyna_leave, .-new_dyna_leave

	.align	2
FUNCTION(invalidate_addr_r0):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	b	invalidate_addr_call
	.size	invalidate_addr_r0, .-invalidate_addr_r0
	.align	2
FUNCTION(invalidate_addr_r1):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r1
	b	invalidate_addr_call
	.size	invalidate_addr_r1, .-invalidate_addr_r1
	.align	2
FUNCTION(invalidate_addr_r2):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r2
	b	invalidate_addr_call
	.size	invalidate_addr_r2, .-invalidate_addr_r2
	.align	2
FUNCTION(invalidate_addr_r3):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r3
	b	invalidate_addr_call
	.size	invalidate_addr_r3, .-invalidate_addr_r3
	.align	2
FUNCTION(invalidate_addr_r4):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r4
	b	invalidate_addr_call
	.size	invalidate_addr_r4, .-invalidate_addr_r4
	.align	2
FUNCTION(invalidate_addr_r5):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r5
	b	invalidate_addr_call
	.size	invalidate_addr_r5, .-invalidate_addr_r5
	.align	2
FUNCTION(invalidate_addr_r6):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r6
	b	invalidate_addr_call
	.size	invalidate_addr_r6, .-invalidate_addr_r6
	.align	2
FUNCTION(invalidate_addr_r7):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r7
	b	invalidate_addr_call
	.size	invalidate_addr_r7, .-invalidate_addr_r7
	.align	2
FUNCTION(invalidate_addr_r8):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r8
	b	invalidate_addr_call
	.size	invalidate_addr_r8, .-invalidate_addr_r8
	.align	2
FUNCTION(invalidate_addr_r9):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r9
	b	invalidate_addr_call
	.size	invalidate_addr_r9, .-invalidate_addr_r9
	.align	2
FUNCTION(invalidate_addr_r10):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r10
	b	invalidate_addr_call
	.size	invalidate_addr_r10, .-invalidate_addr_r10
	.align	2
FUNCTION(invalidate_addr_r12):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r12
	.size	invalidate_addr_r12, .-invalidate_addr_r12
	.align	2
invalidate_addr_call:
	ldr	r12, [fp, #LO_inv_code_start]
	ldr	lr, [fp, #LO_inv_code_end]
	cmp	r0, r12
	cmpcs   lr, r0
	blcc	ndrc_invalidate_addr
	ldmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, pc}
	.size	invalidate_addr_call, .-invalidate_addr_call

	.align	2
FUNCTION(new_dyna_start):
	/* ip is stored to conform EABI alignment */
	stmfd	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, lr}
	mov	fp, r0 /* dynarec_local */
	ldr	r0, [fp, #LO_pcaddr]
	bl	ndrc_get_addr_ht
	ldr	r1, [fp, #LO_next_interupt]
	ldr	r10, [fp, #LO_cycle]
	str	r1, [fp, #LO_last_count]
	sub	r10, r10, r1
	mov	pc, r0
	.size	new_dyna_start, .-new_dyna_start

/* --------------------------------------- */

.align	2

.macro pcsx_read_mem readop tab_shift
	/* r0 = address, r1 = handler_tab, r2 = cycles */
	lsl	r3, r0, #20
	lsr	r3, #(20+\tab_shift)
	ldr	r12, [fp, #LO_last_count]
	ldr	r1, [r1, r3, lsl #2]
	add	r2, r2, r12
	lsls	r1, #1
.if \tab_shift == 1
	lsl	r3, #1
	\readop	r0, [r1, r3]
.else
	\readop	r0, [r1, r3, lsl #\tab_shift]
.endif
	movcc	pc, lr
	str	r2, [fp, #LO_cycle]
	bx	r1
.endm

FUNCTION(jump_handler_read8):
	add     r1, #0x1000/4*4 + 0x1000/2*4 @ shift to r8 part
	pcsx_read_mem ldrbcc, 0

FUNCTION(jump_handler_read16):
	add     r1, #0x1000/4*4              @ shift to r16 part
	pcsx_read_mem ldrhcc, 1

FUNCTION(jump_handler_read32):
	pcsx_read_mem ldrcc, 2


.macro memhandler_post
	ldr	r0, [fp, #LO_next_interupt]
	ldr	r2, [fp, #LO_cycle]        @ memhandlers can modify cc, like dma
	str	r0, [fp, #LO_last_count]
	sub	r0, r2, r0
.endm

.macro pcsx_write_mem wrtop tab_shift
	/* r0 = address, r1 = data, r2 = cycles, r3 = handler_tab */
	lsl	r12,r0, #20
	lsr	r12, #(20+\tab_shift)
	ldr	r3, [r3, r12, lsl #2]
	str	r0, [fp, #LO_address]      @ some handlers still need it..
	lsls	r3, #1
	mov     r0, r2                     @ cycle return in case of direct store
.if \tab_shift == 1
	lsl	r12, #1
	\wrtop	r1, [r3, r12]
.else
	\wrtop	r1, [r3, r12, lsl #\tab_shift]
.endif
	movcc	pc, lr
	ldr	r12, [fp, #LO_last_count]
	mov     r0, r1
	add	r2, r2, r12
	str	r2, [fp, #LO_cycle]

	str	lr, [fp, #LO_saved_lr]
	blx	r3
	ldr	lr, [fp, #LO_saved_lr]

	memhandler_post
	bx	lr
.endm

FUNCTION(jump_handler_write8):
	add     r3, #0x1000/4*4 + 0x1000/2*4 @ shift to r8 part
	pcsx_write_mem strbcc, 0

FUNCTION(jump_handler_write16):
	add     r3, #0x1000/4*4              @ shift to r16 part
	pcsx_write_mem strhcc, 1

FUNCTION(jump_handler_write32):
	pcsx_write_mem strcc, 2

FUNCTION(jump_handler_write_h):
	/* r0 = address, r1 = data, r2 = cycles, r3 = handler */
	ldr	r12, [fp, #LO_last_count]
	str	r0, [fp, #LO_address]      @ some handlers still need it..
	add	r2, r2, r12
	mov     r0, r1
	str	r2, [fp, #LO_cycle]

	str	lr, [fp, #LO_saved_lr]
	blx	r3
	ldr	lr, [fp, #LO_saved_lr]

	memhandler_post
	bx	lr

FUNCTION(jump_handle_swl):
	/* r0 = address, r1 = data, r2 = cycles */
	ldr	r3, [fp, #LO_mem_wtab]
	mov	r12,r0,lsr #12
	ldr	r3, [r3, r12, lsl #2]
	lsls	r3, #1
	bcs	4f
	add	r3, r0, r3
	mov	r0, r2
	tst	r3, #2
	beq	101f
	tst	r3, #1
	beq	2f
3:
	str	r1, [r3, #-3]
	bx	lr
2:
	lsr	r2, r1, #8
	lsr	r1, #24
	strh	r2, [r3, #-2]
	strb	r1, [r3]
	bx	lr
101:
	tst	r3, #1
	lsrne	r1, #16		@ 1
	lsreq	r12, r1, #24	@ 0
	strhne	r1, [r3, #-1]
	strbeq	r12, [r3]
	bx	lr
4:
	mov	r0, r2
@	b	abort
	bx	lr		@ TODO?


FUNCTION(jump_handle_swr):
	/* r0 = address, r1 = data, r2 = cycles */
	ldr	r3, [fp, #LO_mem_wtab]
	mov	r12,r0,lsr #12
	ldr	r3, [r3, r12, lsl #2]
	lsls	r3, #1
	bcs	4f
	add	r3, r0, r3
	and	r12,r3, #3
	mov	r0, r2
	cmp	r12,#2
	strbgt	r1, [r3]	@ 3
	strheq	r1, [r3]	@ 2
	cmp	r12,#1
	strlt	r1, [r3]	@ 0
	bxne	lr
	lsr	r2, r1, #8	@ 1
	strb	r1, [r3]
	strh	r2, [r3, #1]
	bx	lr
4:
	mov	r0, r2
@	b	abort
	bx	lr		@ TODO?


.macro rcntx_read_mode0 num
	/* r0 = address, r2 = cycles */
	ldr	r3, [fp, #LO_rcnts+6*4+7*4*\num] @ cycleStart
	mov	r0, r2, lsl #16
	sub	r0, r0, r3, lsl #16
	lsr	r0, #16
	bx	lr
.endm

FUNCTION(rcnt0_read_count_m0):
	rcntx_read_mode0 0

FUNCTION(rcnt1_read_count_m0):
	rcntx_read_mode0 1

FUNCTION(rcnt2_read_count_m0):
	rcntx_read_mode0 2

FUNCTION(rcnt0_read_count_m1):
	/* r0 = address, r2 = cycles */
	ldr	r3, [fp, #LO_rcnts+6*4+7*4*0] @ cycleStart
	mov_16	r1, 0x3334
	sub	r2, r2, r3
	mul	r0, r1, r2		@ /= 5
	lsr	r0, #16
	bx	lr

FUNCTION(rcnt1_read_count_m1):
	/* r0 = address, r2 = cycles */
	ldr	r3, [fp, #LO_rcnts+6*4+7*4*1]
	mov_24	r1, 0x1e6cde
	sub	r2, r2, r3
	umull	r3, r0, r1, r2		@ ~ /= hsync_cycles, max ~0x1e6cdd
	bx	lr

FUNCTION(rcnt2_read_count_m1):
	/* r0 = address, r2 = cycles */
	ldr	r3, [fp, #LO_rcnts+6*4+7*4*2]
	mov	r0, r2, lsl #16-3
	sub	r0, r0, r3, lsl #16-3
	lsr	r0, #16			@ /= 8
	bx	lr

FUNCTION(call_gteStall):
	/* r0 = op_cycles, r1 = cycles */
	ldr	r2, [fp, #LO_last_count]
	str	lr, [fp, #LO_saved_lr]
	add	r1, r1, r2
	str	r1, [fp, #LO_cycle]
	add	r1, fp, #LO_psxRegs
	bl	gteCheckStallRaw
	ldr	lr, [fp, #LO_saved_lr]
	add	r10, r10, r0
	bx	lr

#ifdef HAVE_ARMV6

FUNCTION(get_reg):
	ldr	r12, [r0]
	and	r1, r1, #0xff
	ldr	r2, [r0, #4]
	orr	r1, r1, r1, lsl #8
	ldr	r3, [r0, #8]
	orr	r1, r1, r1, lsl #16   @ searched char in every byte
	ldrb    r0, [r0, #12]         @ last byte
	eor	r12, r12, r1
	eor	r2, r2, r1
	eor	r3, r3, r1
	cmp     r0, r1, lsr #24
	mov	r0, #12
	mvn	r1, #0                @ r1=~0
	bxeq	lr
	orr	r3, r3, #0xff000000   @ EXCLUDE_REG
	uadd8	r0, r12, r1           @ add and set GE bits when not 0 (match)
	mov	r12, #0
	sel	r0, r12, r1           @ 0 if no match, else ff in some byte
	uadd8	r2, r2, r1
	sel	r2, r12, r1
	uadd8	r3, r3, r1
	sel	r3, r12, r1
	mov	r12, #3
	clz     r0, r0                @ 0, 8, 16, 24 or 32
	clz     r2, r2
	clz     r3, r3
	sub	r0, r12, r0, lsr #3   @ 3, 2, 1, 0 or -1
	sub	r2, r12, r2, lsr #3
	sub	r3, r12, r3, lsr #3
	orr	r2, r2, #4
	orr	r3, r3, #8
	and	r0, r0, r2
	and	r0, r0, r3
	bx	lr

#endif /* HAVE_ARMV6 */

@ vim:filetype=armasm
Commit	Line	Data
57871462	1	/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
7e605697	2	* linkage_arm.s for PCSX *
0bbd1454	3	* Copyright (C) 2009-2011 Ari64 *
b1f89e6f	4	* Copyright (C) 2010-2013 Gražvydas "notaz" Ignotas *
57871462	5	* *
	6	* This program is free software; you can redistribute it and/or modify *
	7	* it under the terms of the GNU General Public License as published by *
	8	* the Free Software Foundation; either version 2 of the License, or *
	9	* (at your option) any later version. *
	10	* *
	11	* This program is distributed in the hope that it will be useful, *
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of *
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
	14	* GNU General Public License for more details. *
	15	* *
	16	* You should have received a copy of the GNU General Public License *
	17	* along with this program; if not, write to the *
	18	* Free Software Foundation, Inc., *
	19	* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
	20	* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
b021ee75	21
665f33e1	22	#include "arm_features.h"
d148d265	23	#include "new_dynarec_config.h"
b1f89e6f	24	#include "linkage_offsets.h"
	25
	26
	27	#ifdef __MACH__
	28	#define dynarec_local ESYM(dynarec_local)
104df9d3	29	#define ndrc_add_jump_out ESYM(ndrc_add_jump_out)
398d6924	30	#define ndrc_try_restore_block ESYM(ndrc_try_restore_block)
104df9d3	31	#define ndrc_get_addr_ht ESYM(ndrc_get_addr_ht)
	32	#define ndrc_get_addr_ht_param ESYM(ndrc_get_addr_ht_param)
	33	#define ndrc_invalidate_addr ESYM(ndrc_invalidate_addr)
b1f89e6f	34	#define gen_interupt ESYM(gen_interupt)
81dbbf4c	35	#define gteCheckStallRaw ESYM(gteCheckStallRaw)
d1150cd6	36	#define psxException ESYM(psxException)
b1f89e6f	37	#endif
f95a77f7	38
57871462	39	.bss
57871462	40	.align 4
b1f89e6f	41	.global dynarec_local
57871462	42	.type dynarec_local, %object
b1f89e6f	43	.size dynarec_local, LO_dynarec_local_size
57871462	44	dynarec_local:
b1f89e6f	45	.space LO_dynarec_local_size
	46
	47	#define DRC_VAR_(name, vname, size_) \
	48	vname = dynarec_local + LO_##name; \
	49	.global vname; \
	50	.type vname, %object; \
	51	.size vname, size_
	52
	53	#define DRC_VAR(name, size_) \
	54	DRC_VAR_(name, ESYM(name), size_)
	55
	56	DRC_VAR(next_interupt, 4)
	57	DRC_VAR(cycle_count, 4)
	58	DRC_VAR(last_count, 4)
	59	DRC_VAR(pending_exception, 4)
	60	DRC_VAR(stop, 4)
687b4580	61	DRC_VAR(branch_target, 4)
b1f89e6f	62	DRC_VAR(address, 4)
7f94b097	63	DRC_VAR(hack_addr, 4)
b1f89e6f	64	DRC_VAR(psxRegs, LO_psxRegs_end - LO_psxRegs)
f95a77f7	65
f95a77f7	66	/* psxRegs */
7c3a5182	67	@DRC_VAR(reg, 128)
b1f89e6f	68	DRC_VAR(lo, 4)
	69	DRC_VAR(hi, 4)
	70	DRC_VAR(reg_cop0, 128)
	71	DRC_VAR(reg_cop2d, 128)
	72	DRC_VAR(reg_cop2c, 128)
	73	DRC_VAR(pcaddr, 4)
	74	@DRC_VAR(code, 4)
	75	@DRC_VAR(cycle, 4)
	76	@DRC_VAR(interrupt, 4)
	77	@DRC_VAR(intCycle, 256)
	78
	79	DRC_VAR(rcnts, 744)
687b4580	80	DRC_VAR(inv_code_start, 4)
687b4580	81	DRC_VAR(inv_code_end, 4)
b1f89e6f	82	DRC_VAR(mem_rtab, 4)
	83	DRC_VAR(mem_wtab, 4)
	84	DRC_VAR(psxH_ptr, 4)
	85	DRC_VAR(zeromem_ptr, 4)
687b4580	86	DRC_VAR(invc_ptr, 4)
c6d5790c	87	DRC_VAR(scratch_buf_ptr, 4)
37387d8b	88	DRC_VAR(ram_offset, 4)
b1f89e6f	89	DRC_VAR(mini_ht, 256)
63cb0298	90
57871462	91
b861c0a9	92	.syntax unified
	93	.text
	94	.align 2
	95
665f33e1	96	#ifndef HAVE_ARMV5
	97	.macro blx rd
	98	mov lr, pc
	99	bx \rd
	100	.endm
	101	#endif
	102
c67af2ac	103	.macro load_varadr reg var
0e4ad319	104	#if defined(HAVE_ARMV7) && defined(TEXRELS_FORBIDDEN)
1f4e070a	105	movw \reg, #:lower16:(\var-(1678f+8))
1f4e070a	106	movt \reg, #:upper16:(\var-(1678f+8))
b861c0a9	107	1678:
b861c0a9	108	add \reg, pc
0e4ad319	109	#elif defined(HAVE_ARMV7) && !defined(__PIC__)
	110	movw \reg, #:lower16:\var
	111	movt \reg, #:upper16:\var
c67af2ac	112	#else
274c4243	113	ldr \reg, =\var
c67af2ac	114	#endif
274c4243	115	.endm
274c4243	116
b861c0a9	117	.macro load_varadr_ext reg var
0e4ad319	118	#if defined(HAVE_ARMV7) && defined(TEXRELS_FORBIDDEN)
1f4e070a	119	movw \reg, #:lower16:(ptr_\var-(1678f+8))
1f4e070a	120	movt \reg, #:upper16:(ptr_\var-(1678f+8))
b861c0a9	121	1678:
	122	ldr \reg, [pc, \reg]
	123	#else
	124	load_varadr \reg \var
	125	#endif
	126	.endm
	127
b1be1eee	128	.macro mov_16 reg imm
8f2bb0cb	129	#ifdef HAVE_ARMV7
b1be1eee	130	movw \reg, #\imm
c67af2ac	131	#else
b1be1eee	132	mov \reg, #(\imm & 0x00ff)
b1be1eee	133	orr \reg, #(\imm & 0xff00)
c67af2ac	134	#endif
b1be1eee	135	.endm
	136
	137	.macro mov_24 reg imm
8f2bb0cb	138	#ifdef HAVE_ARMV7
b1be1eee	139	movw \reg, #(\imm & 0xffff)
b1be1eee	140	movt \reg, #(\imm >> 16)
c67af2ac	141	#else
b1be1eee	142	mov \reg, #(\imm & 0x0000ff)
	143	orr \reg, #(\imm & 0x00ff00)
	144	orr \reg, #(\imm & 0xff0000)
c67af2ac	145	#endif
b1be1eee	146	.endm
b1be1eee	147
104df9d3	148	FUNCTION(dyna_linker):
	149	/* r0 = virtual target address */
	150	/* r1 = pointer to an instruction to patch */
d148d265	151	#ifndef NO_WRITE_EXEC
104df9d3	152	ldr r7, [r1]
	153	mov r4, r0
	154	add r6, r7, #2
	155	mov r5, r1
	156	lsl r6, r6, #8
	157	/* must not compile - that might expire the caller block */
	158	mov r1, #0
	159	bl ndrc_get_addr_ht_param
	160
	161	movs r8, r0
	162	beq 0f
	163	add r6, r5, r6, asr #6 /* old target */
398d6924	164	teq r0, r6
398d6924	165	moveq pc, r0 /* Stale i-cache */
398d6924	166	mov r0, r4
76f71c27	167	mov r1, r6
104df9d3	168	bl ndrc_add_jump_out
104df9d3	169
76f71c27	170	sub r2, r8, r5
57871462	171	and r1, r7, #0xff000000
	172	lsl r2, r2, #6
	173	sub r1, r1, #2
	174	add r1, r1, r2, lsr #8
	175	str r1, [r5]
76f71c27	176	mov pc, r8
104df9d3	177	0:
398d6924	178	mov r0, r4
d148d265	179	#else
d148d265	180	/* XXX: should be able to do better than this... */
d148d265	181	#endif
104df9d3	182	bl ndrc_get_addr_ht
57871462	183	mov pc, r0
4bdc30ab	184	.size dyna_linker, .-dyna_linker
7139f3c8	185
57871462	186	.align 2
5c6457c3	187	FUNCTION(jump_vaddr_r1):
57871462	188	mov r0, r1
104df9d3	189	b jump_vaddr_r0
57871462	190	.size jump_vaddr_r1, .-jump_vaddr_r1
5c6457c3	191	FUNCTION(jump_vaddr_r2):
57871462	192	mov r0, r2
104df9d3	193	b jump_vaddr_r0
57871462	194	.size jump_vaddr_r2, .-jump_vaddr_r2
5c6457c3	195	FUNCTION(jump_vaddr_r3):
57871462	196	mov r0, r3
104df9d3	197	b jump_vaddr_r0
57871462	198	.size jump_vaddr_r3, .-jump_vaddr_r3
5c6457c3	199	FUNCTION(jump_vaddr_r4):
57871462	200	mov r0, r4
104df9d3	201	b jump_vaddr_r0
57871462	202	.size jump_vaddr_r4, .-jump_vaddr_r4
5c6457c3	203	FUNCTION(jump_vaddr_r5):
57871462	204	mov r0, r5
104df9d3	205	b jump_vaddr_r0
57871462	206	.size jump_vaddr_r5, .-jump_vaddr_r5
5c6457c3	207	FUNCTION(jump_vaddr_r6):
57871462	208	mov r0, r6
104df9d3	209	b jump_vaddr_r0
57871462	210	.size jump_vaddr_r6, .-jump_vaddr_r6
5c6457c3	211	FUNCTION(jump_vaddr_r8):
57871462	212	mov r0, r8
104df9d3	213	b jump_vaddr_r0
57871462	214	.size jump_vaddr_r8, .-jump_vaddr_r8
5c6457c3	215	FUNCTION(jump_vaddr_r9):
57871462	216	mov r0, r9
104df9d3	217	b jump_vaddr_r0
57871462	218	.size jump_vaddr_r9, .-jump_vaddr_r9
5c6457c3	219	FUNCTION(jump_vaddr_r10):
57871462	220	mov r0, r10
104df9d3	221	b jump_vaddr_r0
57871462	222	.size jump_vaddr_r10, .-jump_vaddr_r10
5c6457c3	223	FUNCTION(jump_vaddr_r12):
57871462	224	mov r0, r12
104df9d3	225	b jump_vaddr_r0
57871462	226	.size jump_vaddr_r12, .-jump_vaddr_r12
5c6457c3	227	FUNCTION(jump_vaddr_r7):
57871462	228	add r0, r7, #0
57871462	229	.size jump_vaddr_r7, .-jump_vaddr_r7
104df9d3	230	FUNCTION(jump_vaddr_r0):
104df9d3	231	bl ndrc_get_addr_ht
57871462	232	mov pc, r0
104df9d3	233	.size jump_vaddr_r0, .-jump_vaddr_r0
7139f3c8	234
57871462	235	.align 2
5c6457c3	236	FUNCTION(cc_interrupt):
b1f89e6f	237	ldr r0, [fp, #LO_last_count]
57871462	238	mov r1, #0
57871462	239	add r10, r0, r10
b1f89e6f	240	str r1, [fp, #LO_pending_exception]
b1f89e6f	241	str r10, [fp, #LO_cycle] /* PCSX cycles */
b4ab351d	242	@@ str r10, [fp, #LO_reg_cop0+36] /* Count - not on PSX */
57871462	243	mov r10, lr
398d6924	244
57871462	245	bl gen_interupt
57871462	246	mov lr, r10
b1f89e6f	247	ldr r10, [fp, #LO_cycle]
	248	ldr r0, [fp, #LO_next_interupt]
	249	ldr r1, [fp, #LO_pending_exception]
	250	ldr r2, [fp, #LO_stop]
	251	str r0, [fp, #LO_last_count]
57871462	252	sub r10, r10, r0
57871462	253	tst r2, r2
b861c0a9	254	ldmfdne sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}
57871462	255	tst r1, r1
57871462	256	moveq pc, lr
b1f89e6f	257	ldr r0, [fp, #LO_pcaddr]
104df9d3	258	bl ndrc_get_addr_ht
57871462	259	mov pc, r0
57871462	260	.size cc_interrupt, .-cc_interrupt
7139f3c8	261
57871462	262	.align 2
5c6457c3	263	FUNCTION(fp_exception):
57871462	264	mov r2, #0x10000000
57871462	265	.E7:
b1f89e6f	266	ldr r1, [fp, #LO_reg_cop0+48] /* Status */
57871462	267	mov r3, #0x80000000
b1f89e6f	268	str r0, [fp, #LO_reg_cop0+56] /* EPC */
57871462	269	orr r1, #2
57871462	270	add r2, r2, #0x2c
b1f89e6f	271	str r1, [fp, #LO_reg_cop0+48] /* Status */
b1f89e6f	272	str r2, [fp, #LO_reg_cop0+52] /* Cause */
7139f3c8	273	add r0, r3, #0x80
104df9d3	274	bl ndrc_get_addr_ht
57871462	275	mov pc, r0
	276	.size fp_exception, .-fp_exception
	277	.align 2
5c6457c3	278	FUNCTION(fp_exception_ds):
57871462	279	mov r2, #0x90000000 /* Set high bit if delay slot */
	280	b .E7
	281	.size fp_exception_ds, .-fp_exception_ds
7139f3c8	282
57871462	283	.align 2
d1150cd6	284	FUNCTION(jump_break_ds):
	285	mov r0, #0x24
	286	mov r1, #1
	287	b call_psxException
	288	FUNCTION(jump_break):
	289	mov r0, #0x24
	290	mov r1, #0
	291	b call_psxException
	292	FUNCTION(jump_syscall_ds):
	293	mov r0, #0x20
	294	mov r1, #1
	295	b call_psxException
5c6457c3	296	FUNCTION(jump_syscall):
d1150cd6	297	mov r0, #0x20
	298	mov r1, #0
	299
	300	call_psxException:
	301	ldr r3, [fp, #LO_last_count]
	302	str r2, [fp, #LO_pcaddr]
	303	add r10, r3, r10
	304	str r10, [fp, #LO_cycle] /* PCSX cycles */
	305	bl psxException
7139f3c8	306
b1f89e6f	307	/* note: psxException might do recursive recompiler call from it's HLE code,
7139f3c8	308	* so be ready for this */
3968e69e	309	FUNCTION(jump_to_new_pc):
b1f89e6f	310	ldr r1, [fp, #LO_next_interupt]
	311	ldr r10, [fp, #LO_cycle]
	312	ldr r0, [fp, #LO_pcaddr]
822b27d1	313	sub r10, r10, r1
b1f89e6f	314	str r1, [fp, #LO_last_count]
104df9d3	315	bl ndrc_get_addr_ht
7139f3c8	316	mov pc, r0
3968e69e	317	.size jump_to_new_pc, .-jump_to_new_pc
0d16cda2	318
7139f3c8	319	.align 2
5c6457c3	320	FUNCTION(new_dyna_leave):
b1f89e6f	321	ldr r0, [fp, #LO_last_count]
7139f3c8	322	add r12, fp, #28
7139f3c8	323	add r10, r0, r10
b1f89e6f	324	str r10, [fp, #LO_cycle]
b021ee75	325	ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}
7139f3c8	326	.size new_dyna_leave, .-new_dyna_leave
7139f3c8	327
0bbd1454	328	.align 2
5c6457c3	329	FUNCTION(invalidate_addr_r0):
5df0e313	330	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
0bbd1454	331	b invalidate_addr_call
	332	.size invalidate_addr_r0, .-invalidate_addr_r0
	333	.align 2
5c6457c3	334	FUNCTION(invalidate_addr_r1):
5df0e313	335	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
9be4ba64	336	mov r0, r1
0bbd1454	337	b invalidate_addr_call
	338	.size invalidate_addr_r1, .-invalidate_addr_r1
	339	.align 2
5c6457c3	340	FUNCTION(invalidate_addr_r2):
5df0e313	341	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
9be4ba64	342	mov r0, r2
0bbd1454	343	b invalidate_addr_call
	344	.size invalidate_addr_r2, .-invalidate_addr_r2
	345	.align 2
5c6457c3	346	FUNCTION(invalidate_addr_r3):
5df0e313	347	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
9be4ba64	348	mov r0, r3
0bbd1454	349	b invalidate_addr_call
	350	.size invalidate_addr_r3, .-invalidate_addr_r3
	351	.align 2
5c6457c3	352	FUNCTION(invalidate_addr_r4):
5df0e313	353	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
9be4ba64	354	mov r0, r4
0bbd1454	355	b invalidate_addr_call
	356	.size invalidate_addr_r4, .-invalidate_addr_r4
	357	.align 2
5c6457c3	358	FUNCTION(invalidate_addr_r5):
5df0e313	359	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
9be4ba64	360	mov r0, r5
0bbd1454	361	b invalidate_addr_call
	362	.size invalidate_addr_r5, .-invalidate_addr_r5
	363	.align 2
5c6457c3	364	FUNCTION(invalidate_addr_r6):
5df0e313	365	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
9be4ba64	366	mov r0, r6
0bbd1454	367	b invalidate_addr_call
	368	.size invalidate_addr_r6, .-invalidate_addr_r6
	369	.align 2
5c6457c3	370	FUNCTION(invalidate_addr_r7):
5df0e313	371	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
9be4ba64	372	mov r0, r7
0bbd1454	373	b invalidate_addr_call
	374	.size invalidate_addr_r7, .-invalidate_addr_r7
	375	.align 2
5c6457c3	376	FUNCTION(invalidate_addr_r8):
5df0e313	377	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
9be4ba64	378	mov r0, r8
0bbd1454	379	b invalidate_addr_call
	380	.size invalidate_addr_r8, .-invalidate_addr_r8
	381	.align 2
5c6457c3	382	FUNCTION(invalidate_addr_r9):
5df0e313	383	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
9be4ba64	384	mov r0, r9
0bbd1454	385	b invalidate_addr_call
	386	.size invalidate_addr_r9, .-invalidate_addr_r9
	387	.align 2
5c6457c3	388	FUNCTION(invalidate_addr_r10):
5df0e313	389	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
9be4ba64	390	mov r0, r10
0bbd1454	391	b invalidate_addr_call
	392	.size invalidate_addr_r10, .-invalidate_addr_r10
	393	.align 2
5c6457c3	394	FUNCTION(invalidate_addr_r12):
5df0e313	395	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
9be4ba64	396	mov r0, r12
0bbd1454	397	.size invalidate_addr_r12, .-invalidate_addr_r12
0bbd1454	398	.align 2
b1f89e6f	399	invalidate_addr_call:
	400	ldr r12, [fp, #LO_inv_code_start]
	401	ldr lr, [fp, #LO_inv_code_end]
9be4ba64	402	cmp r0, r12
9be4ba64	403	cmpcs lr, r0
104df9d3	404	blcc ndrc_invalidate_addr
5df0e313	405	ldmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, pc}
0bbd1454	406	.size invalidate_addr_call, .-invalidate_addr_call
0bbd1454	407
57871462	408	.align 2
5c6457c3	409	FUNCTION(new_dyna_start):
b021ee75	410	/* ip is stored to conform EABI alignment */
b021ee75	411	stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, lr}
be516ebe	412	mov fp, r0 /* dynarec_local */
b1f89e6f	413	ldr r0, [fp, #LO_pcaddr]
104df9d3	414	bl ndrc_get_addr_ht
b1f89e6f	415	ldr r1, [fp, #LO_next_interupt]
	416	ldr r10, [fp, #LO_cycle]
	417	str r1, [fp, #LO_last_count]
7139f3c8	418	sub r10, r10, r1
7139f3c8	419	mov pc, r0
57871462	420	.size new_dyna_start, .-new_dyna_start
7139f3c8	421
7e605697	422	/* --------------------------------------- */
7139f3c8	423
7e605697	424	.align 2
c6c3b1b3	425
	426	.macro pcsx_read_mem readop tab_shift
	427	/* r0 = address, r1 = handler_tab, r2 = cycles */
	428	lsl r3, r0, #20
	429	lsr r3, #(20+\tab_shift)
b1f89e6f	430	ldr r12, [fp, #LO_last_count]
c6c3b1b3	431	ldr r1, [r1, r3, lsl #2]
	432	add r2, r2, r12
	433	lsls r1, #1
	434	.if \tab_shift == 1
	435	lsl r3, #1
	436	\readop r0, [r1, r3]
	437	.else
	438	\readop r0, [r1, r3, lsl #\tab_shift]
	439	.endif
	440	movcc pc, lr
b1f89e6f	441	str r2, [fp, #LO_cycle]
c6c3b1b3	442	bx r1
	443	.endm
	444
5c6457c3	445	FUNCTION(jump_handler_read8):
c6c3b1b3	446	add r1, #0x1000/44 + 0x1000/24 @ shift to r8 part
b861c0a9	447	pcsx_read_mem ldrbcc, 0
c6c3b1b3	448
5c6457c3	449	FUNCTION(jump_handler_read16):
c6c3b1b3	450	add r1, #0x1000/4*4 @ shift to r16 part
10858959	451	pcsx_read_mem ldrhcc, 1
c6c3b1b3	452
5c6457c3	453	FUNCTION(jump_handler_read32):
c6c3b1b3	454	pcsx_read_mem ldrcc, 2
c6c3b1b3	455
b96d3df7	456
9b9af0d1	457	.macro memhandler_post
	458	ldr r0, [fp, #LO_next_interupt]
	459	ldr r2, [fp, #LO_cycle] @ memhandlers can modify cc, like dma
	460	str r0, [fp, #LO_last_count]
	461	sub r0, r2, r0
	462	.endm
	463
b96d3df7	464	.macro pcsx_write_mem wrtop tab_shift
	465	/* r0 = address, r1 = data, r2 = cycles, r3 = handler_tab */
	466	lsl r12,r0, #20
	467	lsr r12, #(20+\tab_shift)
	468	ldr r3, [r3, r12, lsl #2]
b1f89e6f	469	str r0, [fp, #LO_address] @ some handlers still need it..
b96d3df7	470	lsls r3, #1
9b9af0d1	471	mov r0, r2 @ cycle return in case of direct store
b96d3df7	472	.if \tab_shift == 1
	473	lsl r12, #1
	474	\wrtop r1, [r3, r12]
	475	.else
	476	\wrtop r1, [r3, r12, lsl #\tab_shift]
	477	.endif
	478	movcc pc, lr
b1f89e6f	479	ldr r12, [fp, #LO_last_count]
b96d3df7	480	mov r0, r1
b96d3df7	481	add r2, r2, r12
b1f89e6f	482	str r2, [fp, #LO_cycle]
9b9af0d1	483
9b9af0d1	484	str lr, [fp, #LO_saved_lr]
b96d3df7	485	blx r3
9b9af0d1	486	ldr lr, [fp, #LO_saved_lr]
b96d3df7	487
9b9af0d1	488	memhandler_post
687b4580	489	bx lr
b96d3df7	490	.endm
b96d3df7	491
5c6457c3	492	FUNCTION(jump_handler_write8):
b96d3df7	493	add r3, #0x1000/44 + 0x1000/24 @ shift to r8 part
b861c0a9	494	pcsx_write_mem strbcc, 0
b96d3df7	495
5c6457c3	496	FUNCTION(jump_handler_write16):
b96d3df7	497	add r3, #0x1000/4*4 @ shift to r16 part
b861c0a9	498	pcsx_write_mem strhcc, 1
b96d3df7	499
5c6457c3	500	FUNCTION(jump_handler_write32):
b96d3df7	501	pcsx_write_mem strcc, 2
b96d3df7	502
5c6457c3	503	FUNCTION(jump_handler_write_h):
b96d3df7	504	/* r0 = address, r1 = data, r2 = cycles, r3 = handler */
b1f89e6f	505	ldr r12, [fp, #LO_last_count]
b1f89e6f	506	str r0, [fp, #LO_address] @ some handlers still need it..
b96d3df7	507	add r2, r2, r12
b96d3df7	508	mov r0, r1
b1f89e6f	509	str r2, [fp, #LO_cycle]
9b9af0d1	510
9b9af0d1	511	str lr, [fp, #LO_saved_lr]
b96d3df7	512	blx r3
9b9af0d1	513	ldr lr, [fp, #LO_saved_lr]
b96d3df7	514
9b9af0d1	515	memhandler_post
687b4580	516	bx lr
b96d3df7	517
5c6457c3	518	FUNCTION(jump_handle_swl):
b96d3df7	519	/* r0 = address, r1 = data, r2 = cycles */
b1f89e6f	520	ldr r3, [fp, #LO_mem_wtab]
b96d3df7	521	mov r12,r0,lsr #12
	522	ldr r3, [r3, r12, lsl #2]
	523	lsls r3, #1
	524	bcs 4f
	525	add r3, r0, r3
	526	mov r0, r2
	527	tst r3, #2
	528	beq 101f
	529	tst r3, #1
	530	beq 2f
	531	3:
	532	str r1, [r3, #-3]
	533	bx lr
	534	2:
	535	lsr r2, r1, #8
	536	lsr r1, #24
	537	strh r2, [r3, #-2]
	538	strb r1, [r3]
	539	bx lr
	540	101:
	541	tst r3, #1
	542	lsrne r1, #16 @ 1
	543	lsreq r12, r1, #24 @ 0
b861c0a9	544	strhne r1, [r3, #-1]
b861c0a9	545	strbeq r12, [r3]
b96d3df7	546	bx lr
	547	4:
	548	mov r0, r2
63cb0298	549	@ b abort
b96d3df7	550	bx lr @ TODO?
	551
	552
5c6457c3	553	FUNCTION(jump_handle_swr):
b96d3df7	554	/* r0 = address, r1 = data, r2 = cycles */
b1f89e6f	555	ldr r3, [fp, #LO_mem_wtab]
b96d3df7	556	mov r12,r0,lsr #12
	557	ldr r3, [r3, r12, lsl #2]
	558	lsls r3, #1
	559	bcs 4f
	560	add r3, r0, r3
	561	and r12,r3, #3
	562	mov r0, r2
	563	cmp r12,#2
b861c0a9	564	strbgt r1, [r3] @ 3
b861c0a9	565	strheq r1, [r3] @ 2
b96d3df7	566	cmp r12,#1
	567	strlt r1, [r3] @ 0
	568	bxne lr
	569	lsr r2, r1, #8 @ 1
	570	strb r1, [r3]
	571	strh r2, [r3, #1]
	572	bx lr
	573	4:
	574	mov r0, r2
63cb0298	575	@ b abort
b96d3df7	576	bx lr @ TODO?
	577
	578
b1be1eee	579	.macro rcntx_read_mode0 num
b1be1eee	580	/* r0 = address, r2 = cycles */
b1f89e6f	581	ldr r3, [fp, #LO_rcnts+64+74*\num] @ cycleStart
b1be1eee	582	mov r0, r2, lsl #16
b861c0a9	583	sub r0, r0, r3, lsl #16
b1be1eee	584	lsr r0, #16
	585	bx lr
	586	.endm
	587
5c6457c3	588	FUNCTION(rcnt0_read_count_m0):
b1be1eee	589	rcntx_read_mode0 0
b1be1eee	590
5c6457c3	591	FUNCTION(rcnt1_read_count_m0):
b1be1eee	592	rcntx_read_mode0 1
b1be1eee	593
5c6457c3	594	FUNCTION(rcnt2_read_count_m0):
b1be1eee	595	rcntx_read_mode0 2
b1be1eee	596
5c6457c3	597	FUNCTION(rcnt0_read_count_m1):
b1be1eee	598	/* r0 = address, r2 = cycles */
b1f89e6f	599	ldr r3, [fp, #LO_rcnts+64+74*0] @ cycleStart
b1be1eee	600	mov_16 r1, 0x3334
	601	sub r2, r2, r3
	602	mul r0, r1, r2 @ /= 5
	603	lsr r0, #16
	604	bx lr
	605
5c6457c3	606	FUNCTION(rcnt1_read_count_m1):
b1be1eee	607	/* r0 = address, r2 = cycles */
b1f89e6f	608	ldr r3, [fp, #LO_rcnts+64+74*1]
b1be1eee	609	mov_24 r1, 0x1e6cde
	610	sub r2, r2, r3
	611	umull r3, r0, r1, r2 @ ~ /= hsync_cycles, max ~0x1e6cdd
	612	bx lr
	613
5c6457c3	614	FUNCTION(rcnt2_read_count_m1):
b1be1eee	615	/* r0 = address, r2 = cycles */
b1f89e6f	616	ldr r3, [fp, #LO_rcnts+64+74*2]
b1be1eee	617	mov r0, r2, lsl #16-3
b861c0a9	618	sub r0, r0, r3, lsl #16-3
b1be1eee	619	lsr r0, #16 @ /= 8
	620	bx lr
	621
81dbbf4c	622	FUNCTION(call_gteStall):
	623	/* r0 = op_cycles, r1 = cycles */
	624	ldr r2, [fp, #LO_last_count]
	625	str lr, [fp, #LO_saved_lr]
	626	add r1, r1, r2
	627	str r1, [fp, #LO_cycle]
	628	add r1, fp, #LO_psxRegs
	629	bl gteCheckStallRaw
	630	ldr lr, [fp, #LO_saved_lr]
	631	add r10, r10, r0
	632	bx lr
	633
cdc2da64	634	#ifdef HAVE_ARMV6
	635
	636	FUNCTION(get_reg):
	637	ldr r12, [r0]
	638	and r1, r1, #0xff
	639	ldr r2, [r0, #4]
	640	orr r1, r1, r1, lsl #8
	641	ldr r3, [r0, #8]
	642	orr r1, r1, r1, lsl #16 @ searched char in every byte
	643	ldrb r0, [r0, #12] @ last byte
	644	eor r12, r12, r1
	645	eor r2, r2, r1
	646	eor r3, r3, r1
	647	cmp r0, r1, lsr #24
	648	mov r0, #12
	649	mvn r1, #0 @ r1=~0
	650	bxeq lr
	651	orr r3, r3, #0xff000000 @ EXCLUDE_REG
	652	uadd8 r0, r12, r1 @ add and set GE bits when not 0 (match)
	653	mov r12, #0
	654	sel r0, r12, r1 @ 0 if no match, else ff in some byte
	655	uadd8 r2, r2, r1
	656	sel r2, r12, r1
	657	uadd8 r3, r3, r1
	658	sel r3, r12, r1
	659	mov r12, #3
	660	clz r0, r0 @ 0, 8, 16, 24 or 32
	661	clz r2, r2
	662	clz r3, r3
	663	sub r0, r12, r0, lsr #3 @ 3, 2, 1, 0 or -1
	664	sub r2, r12, r2, lsr #3
	665	sub r3, r12, r3, lsr #3
	666	orr r2, r2, #4
	667	orr r3, r3, #8
	668	and r0, r0, r2
	669	and r0, r0, r3
	670	bx lr
	671
	672	#endif /* HAVE_ARMV6 */
	673
7e605697	674	@ vim:filetype=armasm