[pcsx_rearmed.git] / libpcsxcore / new_dynarec / linkage_arm64.S

/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
 *   linkage_arm.s for PCSX                                                *
 *   Copyright (C) 2009-2011 Ari64                                         *
 *   Copyright (C) 2021 notaz                                              *
 *                                                                         *
 *   This program is free software; you can redistribute it and/or modify  *
 *   it under the terms of the GNU General Public License as published by  *
 *   the Free Software Foundation; either version 2 of the License, or     *
 *   (at your option) any later version.                                   *
 *                                                                         *
 *   This program is distributed in the hope that it will be useful,       *
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
 *   GNU General Public License for more details.                          *
 *                                                                         *
 *   You should have received a copy of the GNU General Public License     *
 *   along with this program; if not, write to the                         *
 *   Free Software Foundation, Inc.,                                       *
 *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.          *
 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */

#include "arm_features.h"
#include "new_dynarec_config.h"
#include "assem_arm64.h"
#include "linkage_offsets.h"

#if (LO_mem_wtab & 7)
#error misligned pointers
#endif

.bss
	.align	4
	.global dynarec_local
	.type	dynarec_local, %object
	.size	dynarec_local, LO_dynarec_local_size
dynarec_local:
	.space	LO_dynarec_local_size

#define DRC_VAR_(name, vname, size_) \
	vname = dynarec_local + LO_##name; \
	.global vname; \
	.type	vname, %object; \
	.size	vname, size_

#define DRC_VAR(name, size_) \
	DRC_VAR_(name, ESYM(name), size_)

DRC_VAR(next_interupt, 4)
DRC_VAR(cycle_count, 4)
DRC_VAR(last_count, 4)
DRC_VAR(pending_exception, 4)
DRC_VAR(stop, 4)
DRC_VAR(branch_target, 4)
DRC_VAR(address, 4)
#DRC_VAR(align0, 16) /* unused/alignment */
DRC_VAR(psxRegs, LO_psxRegs_end - LO_psxRegs)

/* psxRegs */
#DRC_VAR(reg, 128)
DRC_VAR(lo, 4)
DRC_VAR(hi, 4)
DRC_VAR(reg_cop0, 128)
DRC_VAR(reg_cop2d, 128)
DRC_VAR(reg_cop2c, 128)
DRC_VAR(pcaddr, 4)
#DRC_VAR(code, 4)
#DRC_VAR(cycle, 4)
#DRC_VAR(interrupt, 4)
#DRC_VAR(intCycle, 256)

DRC_VAR(rcnts, 7*4*4)
DRC_VAR(inv_code_start, 4)
DRC_VAR(inv_code_end, 4)
DRC_VAR(mem_rtab, 8)
DRC_VAR(mem_wtab, 8)
DRC_VAR(psxH_ptr, 8)
DRC_VAR(invc_ptr, 8)
DRC_VAR(zeromem_ptr, 8)
DRC_VAR(scratch_buf_ptr, 8)
DRC_VAR(ram_offset, 8)
DRC_VAR(mini_ht, 256)
DRC_VAR(restore_candidate, 512)


	.text
	.align	2

/* r0 = virtual target address */
/* r1 = instruction to patch */
.macro dyna_linker_main
	/* XXX TODO: should be able to do better than this... */
	bl	get_addr_ht
	br	x0
.endm


FUNCTION(dyna_linker):
	/* r0 = virtual target address */
	/* r1 = instruction to patch */
	dyna_linker_main
	.size	dyna_linker, .-dyna_linker

FUNCTION(exec_pagefault):
	/* r0 = instruction pointer */
	/* r1 = fault address */
	/* r2 = cause */
	bl	abort
	.size	exec_pagefault, .-exec_pagefault

/* Special dynamic linker for the case where a page fault
   may occur in a branch delay slot */
FUNCTION(dyna_linker_ds):
	/* r0 = virtual target address */
	/* r1 = instruction to patch */
	dyna_linker_main
	.size	dyna_linker_ds, .-dyna_linker_ds

	.align	2
FUNCTION(cc_interrupt):
	ldr	w0, [rFP, #LO_last_count]
	mov	w2, #0x1fc
	add	rCC, w0, rCC
	str	wzr, [rFP, #LO_pending_exception]
	and	w2, w2, rCC, lsr #17
	add	x3, rFP, #LO_restore_candidate
	str	rCC, [rFP, #LO_cycle]		/* PCSX cycles */
#	str	rCC, [rFP, #LO_reg_cop0+36]	/* Count */
	ldr	w19, [x3, w2, uxtw]
	mov	x21, lr
	cbnz	w19, 4f
1:
	bl	gen_interupt
	mov	lr, x21
	ldr	rCC, [rFP, #LO_cycle]
	ldr	w0, [rFP, #LO_next_interupt]
	ldr	w1, [rFP, #LO_pending_exception]
	ldr	w2, [rFP, #LO_stop]
	str	w0, [rFP, #LO_last_count]
	sub	rCC, rCC, w0
	cbnz	w2, new_dyna_leave
	cbnz	w1, 2f
	ret
2:
	ldr	w0, [rFP, #LO_pcaddr]
	bl	get_addr_ht
	br	x0
4:
	/* Move 'dirty' blocks to the 'clean' list */
	lsl	w20, w2, #3
	str	wzr, [x3, w2, uxtw]
5:
	mov	w0, w20
	add	w20, w20, #1
	tbz	w19, #0, 6f
	bl	clean_blocks
6:
	lsr	w19, w19, #1
	tst	w20, #31
	bne	5b
	b	1b
	.size	cc_interrupt, .-cc_interrupt

	.align	2
FUNCTION(fp_exception):
	mov	w2, #0x10000000
0:
	ldr	w1, [rFP, #LO_reg_cop0+48] /* Status */
	mov	w3, #0x80000000
	str	w0, [rFP, #LO_reg_cop0+56] /* EPC */
	orr	w1, w1, #2
	add	w2, w2, #0x2c
	str	w1, [rFP, #LO_reg_cop0+48] /* Status */
	str	w2, [rFP, #LO_reg_cop0+52] /* Cause */
	add	w0, w3, #0x80
	bl	get_addr_ht
	br	x0
	.size	fp_exception, .-fp_exception
	.align	2
FUNCTION(fp_exception_ds):
	mov	w2, #0x90000000 /* Set high bit if delay slot */
	b	0b
	.size	fp_exception_ds, .-fp_exception_ds

	.align	2
FUNCTION(jump_syscall):
	ldr	w1, [rFP, #LO_reg_cop0+48] /* Status */
	mov	w3, #0x80000000
	str	w0, [rFP, #LO_reg_cop0+56] /* EPC */
	orr	w1, w1, #2
	mov	w2, #0x20
	str	w1, [rFP, #LO_reg_cop0+48] /* Status */
	str	w2, [rFP, #LO_reg_cop0+52] /* Cause */
	add	w0, w3, #0x80
	bl	get_addr_ht
	br	x0
	.size	jump_syscall, .-jump_syscall
	.align	2

	/* note: psxException might do recursive recompiler call from it's HLE code,
	 * so be ready for this */
FUNCTION(jump_to_new_pc):
	ldr	w1, [rFP, #LO_next_interupt]
	ldr	rCC, [rFP, #LO_cycle]
	ldr	w0, [rFP, #LO_pcaddr]
	sub	rCC, rCC, w1
	str	w1, [rFP, #LO_last_count]
	bl	get_addr_ht
	br	x0
	.size	jump_to_new_pc, .-jump_to_new_pc

	/* stack must be aligned by 16, and include space for save_regs() use */
	.align	2
FUNCTION(new_dyna_start):
	stp	x29, x30, [sp, #-SSP_ALL]!
	ldr	w1,  [x0, #LO_next_interupt]
	ldr	w2,  [x0, #LO_cycle]
	stp	x19, x20, [sp, #16*1]
	stp	x21, x22, [sp, #16*2]
	stp	x23, x24, [sp, #16*3]
	stp	x25, x26, [sp, #16*4]
	stp	x27, x28, [sp, #16*5]
	mov	rFP, x0
	ldr	w0,  [rFP, #LO_pcaddr]
	str	w1,  [rFP, #LO_last_count]
	sub	rCC, w2, w1
	bl	get_addr_ht
	br	x0
	.size	new_dyna_start, .-new_dyna_start

	.align	2
FUNCTION(new_dyna_leave):
	ldr	w0,  [rFP, #LO_last_count]
	add	rCC, rCC, w0
	str	rCC, [rFP, #LO_cycle]
	ldp	x19, x20, [sp, #16*1]
	ldp	x21, x22, [sp, #16*2]
	ldp	x23, x24, [sp, #16*3]
	ldp	x25, x26, [sp, #16*4]
	ldp	x27, x28, [sp, #16*5]
	ldp	x29, x30, [sp], #SSP_ALL
	ret
	.size	new_dyna_leave, .-new_dyna_leave

/* --------------------------------------- */

.align	2

.macro memhandler_pre
	/* w0 = adddr/data, x1 = rhandler, w2 = cycles, x3 = whandler */
	ldr	w4, [rFP, #LO_last_count]
	add	w4, w4, w2
	str	w4, [rFP, #LO_cycle]
.endm

.macro memhandler_post
	ldr	w2, [rFP, #LO_next_interupt]
	ldr	w1, [rFP, #LO_cycle]
	sub	w0, w1, w2
	str	w2, [rFP, #LO_last_count]
.endm

FUNCTION(do_memhandler_pre):
	memhandler_pre
	ret

FUNCTION(do_memhandler_post):
	memhandler_post
	ret

.macro pcsx_read_mem readop tab_shift
	/* w0 = address, x1 = handler_tab, w2 = cycles */
	ubfm	w4, w0, #\tab_shift, #11
	ldr	x3, [x1, w4, uxtw #3]
	adds	x3, x3, x3
	bcs	0f
	\readop	w0, [x3, w4, uxtw #\tab_shift]
	ret
0:
	stp	xzr, x30, [sp, #-16]!
	memhandler_pre
	blr	x3
.endm

FUNCTION(jump_handler_read8):
	add     x1, x1, #0x1000/4*8 + 0x1000/2*8  /* shift to r8 part */
	pcsx_read_mem ldrb, 0
	b	handler_read_end

FUNCTION(jump_handler_read16):
	add     x1, x1, #0x1000/4*8               /* shift to r16 part */
	pcsx_read_mem ldrh, 1
	b	handler_read_end

FUNCTION(jump_handler_read32):
	pcsx_read_mem ldr, 2

handler_read_end:
	ldp	xzr, x30, [sp], #16
	ret

.macro pcsx_write_mem wrtop movop tab_shift
	/* w0 = address, w1 = data, w2 = cycles, x3 = handler_tab */
	ubfm	w4, w0, #\tab_shift, #11
	ldr	x3, [x3, w4, uxtw #3]
	adds	x3, x3, x3
	bcs	0f
	mov	w0, w2                    /* cycle return */
	\wrtop	w1, [x3, w4, uxtw #\tab_shift]
	ret
0:
	stp	xzr, x30, [sp, #-16]!
	str	w0, [rFP, #LO_address]    /* some handlers still need it... */
	\movop	w0, w1
	memhandler_pre
	blr	x3
.endm

FUNCTION(jump_handler_write8):
	add     x3, x3, #0x1000/4*8 + 0x1000/2*8  /* shift to r8 part */
	pcsx_write_mem strb uxtb 0
	b	handler_write_end

FUNCTION(jump_handler_write16):
	add     x3, x3, #0x1000/4*8               /* shift to r16 part */
	pcsx_write_mem strh uxth 1
	b	handler_write_end

FUNCTION(jump_handler_write32):
	pcsx_write_mem str mov 2

handler_write_end:
	memhandler_post
	ldp	xzr, x30, [sp], #16
	ret

FUNCTION(jump_handle_swl):
	/* w0 = address, w1 = data, w2 = cycles */
	ldr	x3, [rFP, #LO_mem_wtab]
	mov	w4, w0, lsr #12
	ldr	x3, [x3, w4, uxtw #3]
	adds	x3, x3, x3
	bcs	4f
	add	x3, x0, x3
	mov	w0, w2
	tbz	x3, #1, 10f	// & 2
	tbz	x3, #0, 2f	// & 1
3:
	stur	w1, [x3, #-3]
	ret
2:
	lsr	w2, w1, #8
	lsr	w1, w1, #24
	sturh	w2, [x3, #-2]
	strb	w1, [x3]
	ret
10:
	tbz	x3, #0, 0f	// & 1
1:
	lsr	w1, w1, #16
	sturh	w1, [x3, #-1]
	ret
0:
	lsr	w2, w1, #24
	strb	w2, [x3]
	ret
4:
	mov	w0, w2		// todo
	bl	abort
	ret

FUNCTION(jump_handle_swr):
	/* w0 = address, w1 = data, w2 = cycles */
	ldr	x3, [rFP, #LO_mem_wtab]
	mov	w4, w0, lsr #12
	ldr	x3, [x3, w4, uxtw #3]
	adds	x3, x3, x3
	bcs	4f
	add	x3, x0, x3
	mov	w0, w2
	tbz	x3, #1, 10f	// & 2
	tbz	x3, #0, 2f	// & 1
3:
	strb	w1, [x3]
	ret
2:
	strh	w1, [x3]
	ret
10:
	tbz	x3, #0, 0f	// & 1
1:
	lsr	w2, w1, #8
	strb	w1, [x3]
	sturh	w2, [x3, #1]
	ret
0:
	str	w1, [x3]
	ret
4:
	mov	w0, w2		// todo
	bl	abort
	ret

FUNCTION(call_gteStall):
	/* w0 = op_cycles, w1 = cycles */
	ldr	w2, [rFP, #LO_last_count]
	str	lr, [rFP, #LO_saved_lr]
	add	w1, w1, w2
	str	w1, [rFP, #LO_cycle]
	add	x1, rFP, #LO_psxRegs
	bl	gteCheckStallRaw
	ldr	lr, [rFP, #LO_saved_lr]
	add	rCC, rCC, w0
	ret
Commit	Line	Data
be516ebe	1	/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
	2	* linkage_arm.s for PCSX *
	3	* Copyright (C) 2009-2011 Ari64 *
	4	* Copyright (C) 2021 notaz *
	5	* *
	6	* This program is free software; you can redistribute it and/or modify *
	7	* it under the terms of the GNU General Public License as published by *
	8	* the Free Software Foundation; either version 2 of the License, or *
	9	* (at your option) any later version. *
	10	* *
	11	* This program is distributed in the hope that it will be useful, *
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of *
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
	14	* GNU General Public License for more details. *
	15	* *
	16	* You should have received a copy of the GNU General Public License *
	17	* along with this program; if not, write to the *
	18	* Free Software Foundation, Inc., *
	19	* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
	20	* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
	21
	22	#include "arm_features.h"
	23	#include "new_dynarec_config.h"
	24	#include "assem_arm64.h"
	25	#include "linkage_offsets.h"
	26
39b71d9a	27	#if (LO_mem_wtab & 7)
	28	#error misligned pointers
	29	#endif
	30
be516ebe	31	.bss
	32	.align 4
	33	.global dynarec_local
	34	.type dynarec_local, %object
	35	.size dynarec_local, LO_dynarec_local_size
	36	dynarec_local:
	37	.space LO_dynarec_local_size
	38
	39	#define DRC_VAR_(name, vname, size_) \
	40	vname = dynarec_local + LO_##name; \
	41	.global vname; \
	42	.type vname, %object; \
	43	.size vname, size_
	44
	45	#define DRC_VAR(name, size_) \
	46	DRC_VAR_(name, ESYM(name), size_)
	47
	48	DRC_VAR(next_interupt, 4)
	49	DRC_VAR(cycle_count, 4)
	50	DRC_VAR(last_count, 4)
	51	DRC_VAR(pending_exception, 4)
	52	DRC_VAR(stop, 4)
687b4580	53	DRC_VAR(branch_target, 4)
be516ebe	54	DRC_VAR(address, 4)
687b4580	55	#DRC_VAR(align0, 16) /* unused/alignment */
be516ebe	56	DRC_VAR(psxRegs, LO_psxRegs_end - LO_psxRegs)
	57
	58	/* psxRegs */
7c3a5182	59	#DRC_VAR(reg, 128)
be516ebe	60	DRC_VAR(lo, 4)
	61	DRC_VAR(hi, 4)
	62	DRC_VAR(reg_cop0, 128)
	63	DRC_VAR(reg_cop2d, 128)
	64	DRC_VAR(reg_cop2c, 128)
	65	DRC_VAR(pcaddr, 4)
	66	#DRC_VAR(code, 4)
	67	#DRC_VAR(cycle, 4)
	68	#DRC_VAR(interrupt, 4)
	69	#DRC_VAR(intCycle, 256)
	70
	71	DRC_VAR(rcnts, 744)
be516ebe	72	DRC_VAR(inv_code_start, 4)
be516ebe	73	DRC_VAR(inv_code_end, 4)
687b4580	74	DRC_VAR(mem_rtab, 8)
	75	DRC_VAR(mem_wtab, 8)
	76	DRC_VAR(psxH_ptr, 8)
	77	DRC_VAR(invc_ptr, 8)
	78	DRC_VAR(zeromem_ptr, 8)
	79	DRC_VAR(scratch_buf_ptr, 8)
37387d8b	80	DRC_VAR(ram_offset, 8)
be516ebe	81	DRC_VAR(mini_ht, 256)
	82	DRC_VAR(restore_candidate, 512)
	83
	84
	85	.text
	86	.align 2
	87
	88	/* r0 = virtual target address */
	89	/* r1 = instruction to patch */
	90	.macro dyna_linker_main
d1e4ebd9	91	/* XXX TODO: should be able to do better than this... */
be516ebe	92	bl get_addr_ht
	93	br x0
	94	.endm
	95
	96
	97	FUNCTION(dyna_linker):
	98	/* r0 = virtual target address */
	99	/* r1 = instruction to patch */
	100	dyna_linker_main
	101	.size dyna_linker, .-dyna_linker
	102
	103	FUNCTION(exec_pagefault):
	104	/* r0 = instruction pointer */
	105	/* r1 = fault address */
	106	/* r2 = cause */
	107	bl abort
	108	.size exec_pagefault, .-exec_pagefault
	109
	110	/* Special dynamic linker for the case where a page fault
	111	may occur in a branch delay slot */
	112	FUNCTION(dyna_linker_ds):
	113	/* r0 = virtual target address */
	114	/* r1 = instruction to patch */
	115	dyna_linker_main
	116	.size dyna_linker_ds, .-dyna_linker_ds
	117
be516ebe	118	.align 2
be516ebe	119	FUNCTION(cc_interrupt):
d1e4ebd9	120	ldr w0, [rFP, #LO_last_count]
	121	mov w2, #0x1fc
	122	add rCC, w0, rCC
	123	str wzr, [rFP, #LO_pending_exception]
	124	and w2, w2, rCC, lsr #17
	125	add x3, rFP, #LO_restore_candidate
	126	str rCC, [rFP, #LO_cycle] /* PCSX cycles */
	127	# str rCC, [rFP, #LO_reg_cop0+36] /* Count */
	128	ldr w19, [x3, w2, uxtw]
	129	mov x21, lr
	130	cbnz w19, 4f
	131	1:
	132	bl gen_interupt
	133	mov lr, x21
	134	ldr rCC, [rFP, #LO_cycle]
	135	ldr w0, [rFP, #LO_next_interupt]
	136	ldr w1, [rFP, #LO_pending_exception]
	137	ldr w2, [rFP, #LO_stop]
	138	str w0, [rFP, #LO_last_count]
	139	sub rCC, rCC, w0
	140	cbnz w2, new_dyna_leave
	141	cbnz w1, 2f
	142	ret
	143	2:
	144	ldr w0, [rFP, #LO_pcaddr]
	145	bl get_addr_ht
	146	br x0
	147	4:
	148	/* Move 'dirty' blocks to the 'clean' list */
	149	lsl w20, w2, #3
	150	str wzr, [x3, w2, uxtw]
	151	5:
	152	mov w0, w20
	153	add w20, w20, #1
	154	tbz w19, #0, 6f
	155	bl clean_blocks
	156	6:
	157	lsr w19, w19, #1
	158	tst w20, #31
	159	bne 5b
	160	b 1b
be516ebe	161	.size cc_interrupt, .-cc_interrupt
be516ebe	162
be516ebe	163	.align 2
	164	FUNCTION(fp_exception):
	165	mov w2, #0x10000000
	166	0:
81dbbf4c	167	ldr w1, [rFP, #LO_reg_cop0+48] /* Status */
be516ebe	168	mov w3, #0x80000000
81dbbf4c	169	str w0, [rFP, #LO_reg_cop0+56] /* EPC */
be516ebe	170	orr w1, w1, #2
be516ebe	171	add w2, w2, #0x2c
81dbbf4c	172	str w1, [rFP, #LO_reg_cop0+48] /* Status */
81dbbf4c	173	str w2, [rFP, #LO_reg_cop0+52] /* Cause */
be516ebe	174	add w0, w3, #0x80
	175	bl get_addr_ht
	176	br x0
	177	.size fp_exception, .-fp_exception
	178	.align 2
	179	FUNCTION(fp_exception_ds):
	180	mov w2, #0x90000000 /* Set high bit if delay slot */
	181	b 0b
	182	.size fp_exception_ds, .-fp_exception_ds
	183
	184	.align 2
	185	FUNCTION(jump_syscall):
81dbbf4c	186	ldr w1, [rFP, #LO_reg_cop0+48] /* Status */
be516ebe	187	mov w3, #0x80000000
81dbbf4c	188	str w0, [rFP, #LO_reg_cop0+56] /* EPC */
be516ebe	189	orr w1, w1, #2
be516ebe	190	mov w2, #0x20
81dbbf4c	191	str w1, [rFP, #LO_reg_cop0+48] /* Status */
81dbbf4c	192	str w2, [rFP, #LO_reg_cop0+52] /* Cause */
be516ebe	193	add w0, w3, #0x80
	194	bl get_addr_ht
	195	br x0
	196	.size jump_syscall, .-jump_syscall
	197	.align 2
	198
be516ebe	199	/* note: psxException might do recursive recompiler call from it's HLE code,
be516ebe	200	* so be ready for this */
3968e69e	201	FUNCTION(jump_to_new_pc):
81dbbf4c	202	ldr w1, [rFP, #LO_next_interupt]
	203	ldr rCC, [rFP, #LO_cycle]
	204	ldr w0, [rFP, #LO_pcaddr]
3968e69e	205	sub rCC, rCC, w1
81dbbf4c	206	str w1, [rFP, #LO_last_count]
be516ebe	207	bl get_addr_ht
be516ebe	208	br x0
3968e69e	209	.size jump_to_new_pc, .-jump_to_new_pc
be516ebe	210
687b4580	211	/* stack must be aligned by 16, and include space for save_regs() use */
be516ebe	212	.align 2
be516ebe	213	FUNCTION(new_dyna_start):
687b4580	214	stp x29, x30, [sp, #-SSP_ALL]!
be516ebe	215	ldr w1, [x0, #LO_next_interupt]
	216	ldr w2, [x0, #LO_cycle]
	217	stp x19, x20, [sp, #16*1]
	218	stp x21, x22, [sp, #16*2]
	219	stp x23, x24, [sp, #16*3]
	220	stp x25, x26, [sp, #16*4]
	221	stp x27, x28, [sp, #16*5]
	222	mov rFP, x0
	223	ldr w0, [rFP, #LO_pcaddr]
	224	str w1, [rFP, #LO_last_count]
	225	sub rCC, w2, w1
	226	bl get_addr_ht
	227	br x0
	228	.size new_dyna_start, .-new_dyna_start
	229
	230	.align 2
	231	FUNCTION(new_dyna_leave):
	232	ldr w0, [rFP, #LO_last_count]
	233	add rCC, rCC, w0
	234	str rCC, [rFP, #LO_cycle]
	235	ldp x19, x20, [sp, #16*1]
	236	ldp x21, x22, [sp, #16*2]
	237	ldp x23, x24, [sp, #16*3]
	238	ldp x25, x26, [sp, #16*4]
	239	ldp x27, x28, [sp, #16*5]
687b4580	240	ldp x29, x30, [sp], #SSP_ALL
be516ebe	241	ret
	242	.size new_dyna_leave, .-new_dyna_leave
	243
	244	/* --------------------------------------- */
	245
	246	.align 2
	247
d1e4ebd9	248	.macro memhandler_pre
	249	/* w0 = adddr/data, x1 = rhandler, w2 = cycles, x3 = whandler */
	250	ldr w4, [rFP, #LO_last_count]
	251	add w4, w4, w2
	252	str w4, [rFP, #LO_cycle]
	253	.endm
	254
	255	.macro memhandler_post
	256	ldr w2, [rFP, #LO_next_interupt]
	257	ldr w1, [rFP, #LO_cycle]
	258	sub w0, w1, w2
	259	str w2, [rFP, #LO_last_count]
	260	.endm
	261
	262	FUNCTION(do_memhandler_pre):
	263	memhandler_pre
	264	ret
	265
	266	FUNCTION(do_memhandler_post):
	267	memhandler_post
	268	ret
	269
	270	.macro pcsx_read_mem readop tab_shift
	271	/* w0 = address, x1 = handler_tab, w2 = cycles */
d1e4ebd9	272	ubfm w4, w0, #\tab_shift, #11
	273	ldr x3, [x1, w4, uxtw #3]
	274	adds x3, x3, x3
	275	bcs 0f
	276	\readop w0, [x3, w4, uxtw #\tab_shift]
	277	ret
	278	0:
3968e69e	279	stp xzr, x30, [sp, #-16]!
d1e4ebd9	280	memhandler_pre
	281	blr x3
	282	.endm
	283
be516ebe	284	FUNCTION(jump_handler_read8):
3968e69e	285	add x1, x1, #0x1000/48 + 0x1000/28 /* shift to r8 part */
d1e4ebd9	286	pcsx_read_mem ldrb, 0
d1e4ebd9	287	b handler_read_end
be516ebe	288
be516ebe	289	FUNCTION(jump_handler_read16):
3968e69e	290	add x1, x1, #0x1000/48 / shift to r16 part */
d1e4ebd9	291	pcsx_read_mem ldrh, 1
d1e4ebd9	292	b handler_read_end
be516ebe	293
be516ebe	294	FUNCTION(jump_handler_read32):
d1e4ebd9	295	pcsx_read_mem ldr, 2
	296
	297	handler_read_end:
	298	ldp xzr, x30, [sp], #16
	299	ret
	300
	301	.macro pcsx_write_mem wrtop movop tab_shift
	302	/* w0 = address, w1 = data, w2 = cycles, x3 = handler_tab */
d1e4ebd9	303	ubfm w4, w0, #\tab_shift, #11
d1e4ebd9	304	ldr x3, [x3, w4, uxtw #3]
d1e4ebd9	305	adds x3, x3, x3
d1e4ebd9	306	bcs 0f
	307	mov w0, w2 /* cycle return */
	308	\wrtop w1, [x3, w4, uxtw #\tab_shift]
	309	ret
	310	0:
3968e69e	311	stp xzr, x30, [sp, #-16]!
3968e69e	312	str w0, [rFP, #LO_address] /* some handlers still need it... */
d1e4ebd9	313	\movop w0, w1
	314	memhandler_pre
	315	blr x3
	316	.endm
be516ebe	317
be516ebe	318	FUNCTION(jump_handler_write8):
3968e69e	319	add x3, x3, #0x1000/48 + 0x1000/28 /* shift to r8 part */
d1e4ebd9	320	pcsx_write_mem strb uxtb 0
d1e4ebd9	321	b handler_write_end
be516ebe	322
be516ebe	323	FUNCTION(jump_handler_write16):
3968e69e	324	add x3, x3, #0x1000/48 / shift to r16 part */
d1e4ebd9	325	pcsx_write_mem strh uxth 1
d1e4ebd9	326	b handler_write_end
be516ebe	327
be516ebe	328	FUNCTION(jump_handler_write32):
d1e4ebd9	329	pcsx_write_mem str mov 2
be516ebe	330
d1e4ebd9	331	handler_write_end:
	332	memhandler_post
	333	ldp xzr, x30, [sp], #16
	334	ret
be516ebe	335
be516ebe	336	FUNCTION(jump_handle_swl):
3968e69e	337	/* w0 = address, w1 = data, w2 = cycles */
81dbbf4c	338	ldr x3, [rFP, #LO_mem_wtab]
3968e69e	339	mov w4, w0, lsr #12
	340	ldr x3, [x3, w4, uxtw #3]
	341	adds x3, x3, x3
	342	bcs 4f
	343	add x3, x0, x3
	344	mov w0, w2
	345	tbz x3, #1, 10f // & 2
	346	tbz x3, #0, 2f // & 1
	347	3:
	348	stur w1, [x3, #-3]
	349	ret
	350	2:
	351	lsr w2, w1, #8
	352	lsr w1, w1, #24
	353	sturh w2, [x3, #-2]
	354	strb w1, [x3]
	355	ret
	356	10:
	357	tbz x3, #0, 0f // & 1
	358	1:
	359	lsr w1, w1, #16
	360	sturh w1, [x3, #-1]
	361	ret
	362	0:
	363	lsr w2, w1, #24
	364	strb w2, [x3]
	365	ret
	366	4:
	367	mov w0, w2 // todo
be516ebe	368	bl abort
3968e69e	369	ret
be516ebe	370
be516ebe	371	FUNCTION(jump_handle_swr):
3968e69e	372	/* w0 = address, w1 = data, w2 = cycles */
81dbbf4c	373	ldr x3, [rFP, #LO_mem_wtab]
3968e69e	374	mov w4, w0, lsr #12
	375	ldr x3, [x3, w4, uxtw #3]
	376	adds x3, x3, x3
	377	bcs 4f
	378	add x3, x0, x3
	379	mov w0, w2
	380	tbz x3, #1, 10f // & 2
	381	tbz x3, #0, 2f // & 1
	382	3:
	383	strb w1, [x3]
	384	ret
	385	2:
	386	strh w1, [x3]
	387	ret
	388	10:
	389	tbz x3, #0, 0f // & 1
	390	1:
	391	lsr w2, w1, #8
	392	strb w1, [x3]
	393	sturh w2, [x3, #1]
	394	ret
	395	0:
	396	str w1, [x3]
	397	ret
	398	4:
	399	mov w0, w2 // todo
be516ebe	400	bl abort
3968e69e	401	ret
be516ebe	402
81dbbf4c	403	FUNCTION(call_gteStall):
	404	/* w0 = op_cycles, w1 = cycles */
	405	ldr w2, [rFP, #LO_last_count]
	406	str lr, [rFP, #LO_saved_lr]
	407	add w1, w1, w2
	408	str w1, [rFP, #LO_cycle]
	409	add x1, rFP, #LO_psxRegs
	410	bl gteCheckStallRaw
	411	ldr lr, [rFP, #LO_saved_lr]
	412	add rCC, rCC, w0
	413	ret
	414