[pcsx_rearmed.git] / libpcsxcore / new_dynarec / linkage_arm64.S

/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
 *   linkage_arm.s for PCSX                                                *
 *   Copyright (C) 2009-2011 Ari64                                         *
 *   Copyright (C) 2021 notaz                                              *
 *                                                                         *
 *   This program is free software; you can redistribute it and/or modify  *
 *   it under the terms of the GNU General Public License as published by  *
 *   the Free Software Foundation; either version 2 of the License, or     *
 *   (at your option) any later version.                                   *
 *                                                                         *
 *   This program is distributed in the hope that it will be useful,       *
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
 *   GNU General Public License for more details.                          *
 *                                                                         *
 *   You should have received a copy of the GNU General Public License     *
 *   along with this program; if not, write to the                         *
 *   Free Software Foundation, Inc.,                                       *
 *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.          *
 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */

#include "arm_features.h"
#include "new_dynarec_config.h"
#include "assem_arm64.h"
#include "linkage_offsets.h"

.bss
	.align	4
	.global dynarec_local
	.type	dynarec_local, %object
	.size	dynarec_local, LO_dynarec_local_size
dynarec_local:
	.space	LO_dynarec_local_size

#define DRC_VAR_(name, vname, size_) \
	vname = dynarec_local + LO_##name; \
	.global vname; \
	.type	vname, %object; \
	.size	vname, size_

#define DRC_VAR(name, size_) \
	DRC_VAR_(name, ESYM(name), size_)

DRC_VAR(next_interupt, 4)
DRC_VAR(cycle_count, 4)
DRC_VAR(last_count, 4)
DRC_VAR(pending_exception, 4)
DRC_VAR(stop, 4)
DRC_VAR(branch_target, 4)
DRC_VAR(address, 4)
#DRC_VAR(align0, 16) /* unused/alignment */
DRC_VAR(psxRegs, LO_psxRegs_end - LO_psxRegs)

/* psxRegs */
#DRC_VAR(reg, 128)
DRC_VAR(lo, 4)
DRC_VAR(hi, 4)
DRC_VAR(reg_cop0, 128)
DRC_VAR(reg_cop2d, 128)
DRC_VAR(reg_cop2c, 128)
DRC_VAR(pcaddr, 4)
#DRC_VAR(code, 4)
#DRC_VAR(cycle, 4)
#DRC_VAR(interrupt, 4)
#DRC_VAR(intCycle, 256)

DRC_VAR(rcnts, 7*4*4)
DRC_VAR(inv_code_start, 4)
DRC_VAR(inv_code_end, 4)
DRC_VAR(mem_rtab, 8)
DRC_VAR(mem_wtab, 8)
DRC_VAR(psxH_ptr, 8)
DRC_VAR(invc_ptr, 8)
DRC_VAR(zeromem_ptr, 8)
DRC_VAR(scratch_buf_ptr, 8)
#DRC_VAR(align1, 16) /* unused/alignment */
DRC_VAR(mini_ht, 256)
DRC_VAR(restore_candidate, 512)


	.text
	.align	2

/* r0 = virtual target address */
/* r1 = instruction to patch */
.macro dyna_linker_main
	/* XXX: should be able to do better than this... */
	bl	get_addr_ht
	br	x0
.endm


FUNCTION(dyna_linker):
	/* r0 = virtual target address */
	/* r1 = instruction to patch */
	dyna_linker_main
	.size	dyna_linker, .-dyna_linker

FUNCTION(exec_pagefault):
	/* r0 = instruction pointer */
	/* r1 = fault address */
	/* r2 = cause */
	bl	abort
	.size	exec_pagefault, .-exec_pagefault

/* Special dynamic linker for the case where a page fault
   may occur in a branch delay slot */
FUNCTION(dyna_linker_ds):
	/* r0 = virtual target address */
	/* r1 = instruction to patch */
	dyna_linker_main
	.size	dyna_linker_ds, .-dyna_linker_ds

	.align	2

FUNCTION(jump_vaddr):
	bl	abort
	.size	jump_vaddr, .-jump_vaddr

	.align	2

FUNCTION(verify_code_ds):
	bl	abort
FUNCTION(verify_code):
	/* r1 = source */
	/* r2 = target */
	/* r3 = length */
	bl	abort
	.size	verify_code, .-verify_code
	.size	verify_code_ds, .-verify_code_ds

	.align	2
FUNCTION(cc_interrupt):
	bl	abort
	.size	cc_interrupt, .-cc_interrupt

	.align	2
FUNCTION(do_interrupt):
	bl	abort
	.size	do_interrupt, .-do_interrupt

	.align	2
FUNCTION(fp_exception):
	mov	w2, #0x10000000
0:
	ldr	w1, [fp, #LO_reg_cop0+48] /* Status */
	mov	w3, #0x80000000
	str	w0, [fp, #LO_reg_cop0+56] /* EPC */
	orr	w1, w1, #2
	add	w2, w2, #0x2c
	str	w1, [fp, #LO_reg_cop0+48] /* Status */
	str	w2, [fp, #LO_reg_cop0+52] /* Cause */
	add	w0, w3, #0x80
	bl	get_addr_ht
	br	x0
	.size	fp_exception, .-fp_exception
	.align	2
FUNCTION(fp_exception_ds):
	mov	w2, #0x90000000 /* Set high bit if delay slot */
	b	0b
	.size	fp_exception_ds, .-fp_exception_ds

	.align	2
FUNCTION(jump_syscall):
	ldr	w1, [fp, #LO_reg_cop0+48] /* Status */
	mov	w3, #0x80000000
	str	w0, [fp, #LO_reg_cop0+56] /* EPC */
	orr	w1, w1, #2
	mov	w2, #0x20
	str	w1, [fp, #LO_reg_cop0+48] /* Status */
	str	w2, [fp, #LO_reg_cop0+52] /* Cause */
	add	w0, w3, #0x80
	bl	get_addr_ht
	br	x0
	.size	jump_syscall, .-jump_syscall
	.align	2

	.align	2
FUNCTION(jump_syscall_hle):
	bl	abort

	/* note: psxException might do recursive recompiler call from it's HLE code,
	 * so be ready for this */
pcsx_return:
	bl	abort // w10
	ldr	w1, [fp, #LO_next_interupt]
	ldr	w10, [fp, #LO_cycle]
	ldr	w0, [fp, #LO_pcaddr]
	sub	w10, w10, w1
	str	w1, [fp, #LO_last_count]
	bl	get_addr_ht
	br	x0
	.size	jump_syscall_hle, .-jump_syscall_hle

	.align	2
FUNCTION(jump_hlecall):
	bl	abort
	.size	jump_hlecall, .-jump_hlecall

	.align	2
FUNCTION(jump_intcall):
	bl	abort
	.size	jump_intcall, .-jump_intcall

	/* stack must be aligned by 16, and include space for save_regs() use */
	.align	2
FUNCTION(new_dyna_start):
	stp	x29, x30, [sp, #-SSP_ALL]!
	ldr	w1,  [x0, #LO_next_interupt]
	ldr	w2,  [x0, #LO_cycle]
	stp	x19, x20, [sp, #16*1]
	stp	x21, x22, [sp, #16*2]
	stp	x23, x24, [sp, #16*3]
	stp	x25, x26, [sp, #16*4]
	stp	x27, x28, [sp, #16*5]
	mov	rFP, x0
	ldr	w0,  [rFP, #LO_pcaddr]
	str	w1,  [rFP, #LO_last_count]
	sub	rCC, w2, w1
	bl	get_addr_ht
	br	x0
	.size	new_dyna_start, .-new_dyna_start

	.align	2
FUNCTION(new_dyna_leave):
	ldr	w0,  [rFP, #LO_last_count]
	add	rCC, rCC, w0
	str	rCC, [rFP, #LO_cycle]
	ldp	x19, x20, [sp, #16*1]
	ldp	x21, x22, [sp, #16*2]
	ldp	x23, x24, [sp, #16*3]
	ldp	x25, x26, [sp, #16*4]
	ldp	x27, x28, [sp, #16*5]
	ldp	x29, x30, [sp], #SSP_ALL
	ret
	.size	new_dyna_leave, .-new_dyna_leave

/* --------------------------------------- */

.align	2

FUNCTION(jump_handler_read8):
	bl	abort

FUNCTION(jump_handler_read16):
	bl	abort

FUNCTION(jump_handler_read32):
	bl	abort

FUNCTION(jump_handler_write8):
	bl	abort

FUNCTION(jump_handler_write16):
	bl	abort

FUNCTION(jump_handler_write32):
	bl	abort

FUNCTION(jump_handler_write_h):
	bl	abort

FUNCTION(jump_handle_swl):
	bl	abort

FUNCTION(jump_handle_swr):
	bl	abort
Commit	Line	Data
be516ebe	1	/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
	2	* linkage_arm.s for PCSX *
	3	* Copyright (C) 2009-2011 Ari64 *
	4	* Copyright (C) 2021 notaz *
	5	* *
	6	* This program is free software; you can redistribute it and/or modify *
	7	* it under the terms of the GNU General Public License as published by *
	8	* the Free Software Foundation; either version 2 of the License, or *
	9	* (at your option) any later version. *
	10	* *
	11	* This program is distributed in the hope that it will be useful, *
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of *
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
	14	* GNU General Public License for more details. *
	15	* *
	16	* You should have received a copy of the GNU General Public License *
	17	* along with this program; if not, write to the *
	18	* Free Software Foundation, Inc., *
	19	* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
	20	* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
	21
	22	#include "arm_features.h"
	23	#include "new_dynarec_config.h"
	24	#include "assem_arm64.h"
	25	#include "linkage_offsets.h"
	26
	27	.bss
	28	.align 4
	29	.global dynarec_local
	30	.type dynarec_local, %object
	31	.size dynarec_local, LO_dynarec_local_size
	32	dynarec_local:
	33	.space LO_dynarec_local_size
	34
	35	#define DRC_VAR_(name, vname, size_) \
	36	vname = dynarec_local + LO_##name; \
	37	.global vname; \
	38	.type vname, %object; \
	39	.size vname, size_
	40
	41	#define DRC_VAR(name, size_) \
	42	DRC_VAR_(name, ESYM(name), size_)
	43
	44	DRC_VAR(next_interupt, 4)
	45	DRC_VAR(cycle_count, 4)
	46	DRC_VAR(last_count, 4)
	47	DRC_VAR(pending_exception, 4)
	48	DRC_VAR(stop, 4)
687b4580	49	DRC_VAR(branch_target, 4)
be516ebe	50	DRC_VAR(address, 4)
687b4580	51	#DRC_VAR(align0, 16) /* unused/alignment */
be516ebe	52	DRC_VAR(psxRegs, LO_psxRegs_end - LO_psxRegs)
	53
	54	/* psxRegs */
7c3a5182	55	#DRC_VAR(reg, 128)
be516ebe	56	DRC_VAR(lo, 4)
	57	DRC_VAR(hi, 4)
	58	DRC_VAR(reg_cop0, 128)
	59	DRC_VAR(reg_cop2d, 128)
	60	DRC_VAR(reg_cop2c, 128)
	61	DRC_VAR(pcaddr, 4)
	62	#DRC_VAR(code, 4)
	63	#DRC_VAR(cycle, 4)
	64	#DRC_VAR(interrupt, 4)
	65	#DRC_VAR(intCycle, 256)
	66
	67	DRC_VAR(rcnts, 744)
be516ebe	68	DRC_VAR(inv_code_start, 4)
be516ebe	69	DRC_VAR(inv_code_end, 4)
687b4580	70	DRC_VAR(mem_rtab, 8)
	71	DRC_VAR(mem_wtab, 8)
	72	DRC_VAR(psxH_ptr, 8)
	73	DRC_VAR(invc_ptr, 8)
	74	DRC_VAR(zeromem_ptr, 8)
	75	DRC_VAR(scratch_buf_ptr, 8)
	76	#DRC_VAR(align1, 16) /* unused/alignment */
be516ebe	77	DRC_VAR(mini_ht, 256)
	78	DRC_VAR(restore_candidate, 512)
	79
	80
	81	.text
	82	.align 2
	83
	84	/* r0 = virtual target address */
	85	/* r1 = instruction to patch */
	86	.macro dyna_linker_main
	87	/* XXX: should be able to do better than this... */
	88	bl get_addr_ht
	89	br x0
	90	.endm
	91
	92
	93	FUNCTION(dyna_linker):
	94	/* r0 = virtual target address */
	95	/* r1 = instruction to patch */
	96	dyna_linker_main
	97	.size dyna_linker, .-dyna_linker
	98
	99	FUNCTION(exec_pagefault):
	100	/* r0 = instruction pointer */
	101	/* r1 = fault address */
	102	/* r2 = cause */
	103	bl abort
	104	.size exec_pagefault, .-exec_pagefault
	105
	106	/* Special dynamic linker for the case where a page fault
	107	may occur in a branch delay slot */
	108	FUNCTION(dyna_linker_ds):
	109	/* r0 = virtual target address */
	110	/* r1 = instruction to patch */
	111	dyna_linker_main
	112	.size dyna_linker_ds, .-dyna_linker_ds
	113
	114	.align 2
	115
	116	FUNCTION(jump_vaddr):
	117	bl abort
	118	.size jump_vaddr, .-jump_vaddr
	119
	120	.align 2
	121
	122	FUNCTION(verify_code_ds):
	123	bl abort
be516ebe	124	FUNCTION(verify_code):
	125	/* r1 = source */
	126	/* r2 = target */
	127	/* r3 = length */
	128	bl abort
	129	.size verify_code, .-verify_code
7c3a5182	130	.size verify_code_ds, .-verify_code_ds
be516ebe	131
	132	.align 2
	133	FUNCTION(cc_interrupt):
	134	bl abort
	135	.size cc_interrupt, .-cc_interrupt
	136
	137	.align 2
	138	FUNCTION(do_interrupt):
	139	bl abort
	140	.size do_interrupt, .-do_interrupt
	141
	142	.align 2
	143	FUNCTION(fp_exception):
	144	mov w2, #0x10000000
	145	0:
	146	ldr w1, [fp, #LO_reg_cop0+48] /* Status */
	147	mov w3, #0x80000000
	148	str w0, [fp, #LO_reg_cop0+56] /* EPC */
	149	orr w1, w1, #2
	150	add w2, w2, #0x2c
	151	str w1, [fp, #LO_reg_cop0+48] /* Status */
	152	str w2, [fp, #LO_reg_cop0+52] /* Cause */
	153	add w0, w3, #0x80
	154	bl get_addr_ht
	155	br x0
	156	.size fp_exception, .-fp_exception
	157	.align 2
	158	FUNCTION(fp_exception_ds):
	159	mov w2, #0x90000000 /* Set high bit if delay slot */
	160	b 0b
	161	.size fp_exception_ds, .-fp_exception_ds
	162
	163	.align 2
	164	FUNCTION(jump_syscall):
	165	ldr w1, [fp, #LO_reg_cop0+48] /* Status */
	166	mov w3, #0x80000000
	167	str w0, [fp, #LO_reg_cop0+56] /* EPC */
	168	orr w1, w1, #2
	169	mov w2, #0x20
	170	str w1, [fp, #LO_reg_cop0+48] /* Status */
	171	str w2, [fp, #LO_reg_cop0+52] /* Cause */
	172	add w0, w3, #0x80
	173	bl get_addr_ht
	174	br x0
	175	.size jump_syscall, .-jump_syscall
	176	.align 2
	177
	178	.align 2
	179	FUNCTION(jump_syscall_hle):
	180	bl abort
	181
	182	/* note: psxException might do recursive recompiler call from it's HLE code,
	183	* so be ready for this */
	184	pcsx_return:
	185	bl abort // w10
	186	ldr w1, [fp, #LO_next_interupt]
	187	ldr w10, [fp, #LO_cycle]
	188	ldr w0, [fp, #LO_pcaddr]
	189	sub w10, w10, w1
	190	str w1, [fp, #LO_last_count]
	191	bl get_addr_ht
	192	br x0
	193	.size jump_syscall_hle, .-jump_syscall_hle
	194
195	.align 2
196	FUNCTION(jump_hlecall):
197	bl abort
198	.size jump_hlecall, .-jump_hlecall
199
200	.align 2
201	FUNCTION(jump_intcall):
202	bl abort
203	.size jump_intcall, .-jump_intcall
204
687b4580	205	/* stack must be aligned by 16, and include space for save_regs() use */
be516ebe	206	.align 2
be516ebe	207	FUNCTION(new_dyna_start):
687b4580	208	stp x29, x30, [sp, #-SSP_ALL]!
be516ebe	209	ldr w1, [x0, #LO_next_interupt]
	210	ldr w2, [x0, #LO_cycle]
	211	stp x19, x20, [sp, #16*1]
	212	stp x21, x22, [sp, #16*2]
	213	stp x23, x24, [sp, #16*3]
	214	stp x25, x26, [sp, #16*4]
	215	stp x27, x28, [sp, #16*5]
	216	mov rFP, x0
	217	ldr w0, [rFP, #LO_pcaddr]
	218	str w1, [rFP, #LO_last_count]
	219	sub rCC, w2, w1
	220	bl get_addr_ht
	221	br x0
	222	.size new_dyna_start, .-new_dyna_start
	223
	224	.align 2
	225	FUNCTION(new_dyna_leave):
	226	ldr w0, [rFP, #LO_last_count]
	227	add rCC, rCC, w0
	228	str rCC, [rFP, #LO_cycle]
	229	ldp x19, x20, [sp, #16*1]
	230	ldp x21, x22, [sp, #16*2]
	231	ldp x23, x24, [sp, #16*3]
	232	ldp x25, x26, [sp, #16*4]
	233	ldp x27, x28, [sp, #16*5]
687b4580	234	ldp x29, x30, [sp], #SSP_ALL
be516ebe	235	ret
	236	.size new_dyna_leave, .-new_dyna_leave
	237
	238	/* --------------------------------------- */
	239
	240	.align 2
	241
	242	FUNCTION(jump_handler_read8):
	243	bl abort
	244
	245	FUNCTION(jump_handler_read16):
	246	bl abort
	247
	248	FUNCTION(jump_handler_read32):
	249	bl abort
	250
	251	FUNCTION(jump_handler_write8):
	252	bl abort
	253
	254	FUNCTION(jump_handler_write16):
	255	bl abort
	256
	257	FUNCTION(jump_handler_write32):
	258	bl abort
	259
	260	FUNCTION(jump_handler_write_h):
	261	bl abort
	262
	263	FUNCTION(jump_handle_swl):
	264	bl abort
	265
	266	FUNCTION(jump_handle_swr):
	267	bl abort
	268