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Rewrite GPU bios functions according to OpenBIOS. (#192)
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
CommitLineData
57871462 1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
20d507ba 3 * Copyright (C) 2009-2011 Ari64 *
57871462 4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21#include <stdlib.h>
22#include <stdint.h> //include for uint64_t
23#include <assert.h>
d848b60a 24#include <errno.h>
4600ba03 25#include <sys/mman.h>
d148d265 26#ifdef __MACH__
27#include <libkern/OSCacheControl.h>
28#endif
1e212a25 29#ifdef _3DS
30#include <3ds_utils.h>
31#endif
32#ifdef VITA
33#include <psp2/kernel/sysmem.h>
34static int sceBlock;
35#endif
57871462 36
d148d265 37#include "new_dynarec_config.h"
3d624f89 38#include "emu_if.h" //emulator interface
57871462 39
4600ba03 40//#define DISASM
41//#define assem_debug printf
42//#define inv_debug printf
43#define assem_debug(...)
44#define inv_debug(...)
57871462 45
46#ifdef __i386__
47#include "assem_x86.h"
48#endif
49#ifdef __x86_64__
50#include "assem_x64.h"
51#endif
52#ifdef __arm__
53#include "assem_arm.h"
54#endif
55
56#define MAXBLOCK 4096
57#define MAX_OUTPUT_BLOCK_SIZE 262144
2573466a 58
57871462 59struct regstat
60{
61 signed char regmap_entry[HOST_REGS];
62 signed char regmap[HOST_REGS];
63 uint64_t was32;
64 uint64_t is32;
65 uint64_t wasdirty;
66 uint64_t dirty;
67 uint64_t u;
68 uint64_t uu;
69 u_int wasconst;
70 u_int isconst;
8575a877 71 u_int loadedconst; // host regs that have constants loaded
72 u_int waswritten; // MIPS regs that were used as store base before
57871462 73};
74
de5a60c3 75// note: asm depends on this layout
57871462 76struct ll_entry
77{
78 u_int vaddr;
de5a60c3 79 u_int reg_sv_flags;
57871462 80 void *addr;
81 struct ll_entry *next;
82};
83
e2b5e7aa 84 // used by asm:
85 u_char *out;
86 u_int hash_table[65536][4] __attribute__((aligned(16)));
87 struct ll_entry *jump_in[4096] __attribute__((aligned(16)));
88 struct ll_entry *jump_dirty[4096];
89
90 static struct ll_entry *jump_out[4096];
91 static u_int start;
92 static u_int *source;
93 static char insn[MAXBLOCK][10];
94 static u_char itype[MAXBLOCK];
95 static u_char opcode[MAXBLOCK];
96 static u_char opcode2[MAXBLOCK];
97 static u_char bt[MAXBLOCK];
98 static u_char rs1[MAXBLOCK];
99 static u_char rs2[MAXBLOCK];
100 static u_char rt1[MAXBLOCK];
101 static u_char rt2[MAXBLOCK];
102 static u_char us1[MAXBLOCK];
103 static u_char us2[MAXBLOCK];
104 static u_char dep1[MAXBLOCK];
105 static u_char dep2[MAXBLOCK];
106 static u_char lt1[MAXBLOCK];
bedfea38 107 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
108 static uint64_t gte_rt[MAXBLOCK];
109 static uint64_t gte_unneeded[MAXBLOCK];
ffb0b9e0 110 static u_int smrv[32]; // speculated MIPS register values
111 static u_int smrv_strong; // mask or regs that are likely to have correct values
112 static u_int smrv_weak; // same, but somewhat less likely
113 static u_int smrv_strong_next; // same, but after current insn executes
114 static u_int smrv_weak_next;
e2b5e7aa 115 static int imm[MAXBLOCK];
116 static u_int ba[MAXBLOCK];
117 static char likely[MAXBLOCK];
118 static char is_ds[MAXBLOCK];
119 static char ooo[MAXBLOCK];
120 static uint64_t unneeded_reg[MAXBLOCK];
121 static uint64_t unneeded_reg_upper[MAXBLOCK];
122 static uint64_t branch_unneeded_reg[MAXBLOCK];
123 static uint64_t branch_unneeded_reg_upper[MAXBLOCK];
124 static signed char regmap_pre[MAXBLOCK][HOST_REGS];
956f3129 125 static uint64_t current_constmap[HOST_REGS];
126 static uint64_t constmap[MAXBLOCK][HOST_REGS];
127 static struct regstat regs[MAXBLOCK];
128 static struct regstat branch_regs[MAXBLOCK];
e2b5e7aa 129 static signed char minimum_free_regs[MAXBLOCK];
130 static u_int needed_reg[MAXBLOCK];
131 static u_int wont_dirty[MAXBLOCK];
132 static u_int will_dirty[MAXBLOCK];
133 static int ccadj[MAXBLOCK];
134 static int slen;
135 static u_int instr_addr[MAXBLOCK];
136 static u_int link_addr[MAXBLOCK][3];
137 static int linkcount;
138 static u_int stubs[MAXBLOCK*3][8];
139 static int stubcount;
140 static u_int literals[1024][2];
141 static int literalcount;
142 static int is_delayslot;
143 static int cop1_usable;
144 static char shadow[1048576] __attribute__((aligned(16)));
145 static void *copy;
146 static int expirep;
147 static u_int stop_after_jal;
a327ad27 148#ifndef RAM_FIXED
149 static u_int ram_offset;
150#else
151 static const u_int ram_offset=0;
152#endif
e2b5e7aa 153
154 int new_dynarec_hacks;
155 int new_dynarec_did_compile;
57871462 156 extern u_char restore_candidate[512];
157 extern int cycle_count;
158
159 /* registers that may be allocated */
160 /* 1-31 gpr */
161#define HIREG 32 // hi
162#define LOREG 33 // lo
163#define FSREG 34 // FPU status (FCSR)
164#define CSREG 35 // Coprocessor status
165#define CCREG 36 // Cycle count
166#define INVCP 37 // Pointer to invalid_code
1edfcc68 167//#define MMREG 38 // Pointer to memory_map
619e5ded 168#define ROREG 39 // ram offset (if rdram!=0x80000000)
169#define TEMPREG 40
170#define FTEMP 40 // FPU temporary register
171#define PTEMP 41 // Prefetch temporary register
1edfcc68 172//#define TLREG 42 // TLB mapping offset
619e5ded 173#define RHASH 43 // Return address hash
174#define RHTBL 44 // Return address hash table address
175#define RTEMP 45 // JR/JALR address register
176#define MAXREG 45
177#define AGEN1 46 // Address generation temporary register
1edfcc68 178//#define AGEN2 47 // Address generation temporary register
179//#define MGEN1 48 // Maptable address generation temporary register
180//#define MGEN2 49 // Maptable address generation temporary register
619e5ded 181#define BTREG 50 // Branch target temporary register
57871462 182
183 /* instruction types */
184#define NOP 0 // No operation
185#define LOAD 1 // Load
186#define STORE 2 // Store
187#define LOADLR 3 // Unaligned load
188#define STORELR 4 // Unaligned store
9f51b4b9 189#define MOV 5 // Move
57871462 190#define ALU 6 // Arithmetic/logic
191#define MULTDIV 7 // Multiply/divide
192#define SHIFT 8 // Shift by register
193#define SHIFTIMM 9// Shift by immediate
194#define IMM16 10 // 16-bit immediate
195#define RJUMP 11 // Unconditional jump to register
196#define UJUMP 12 // Unconditional jump
197#define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
198#define SJUMP 14 // Conditional branch (regimm format)
199#define COP0 15 // Coprocessor 0
200#define COP1 16 // Coprocessor 1
201#define C1LS 17 // Coprocessor 1 load/store
202#define FJUMP 18 // Conditional branch (floating point)
203#define FLOAT 19 // Floating point unit
204#define FCONV 20 // Convert integer to float
205#define FCOMP 21 // Floating point compare (sets FSREG)
206#define SYSCALL 22// SYSCALL
207#define OTHER 23 // Other
208#define SPAN 24 // Branch/delay slot spans 2 pages
209#define NI 25 // Not implemented
7139f3c8 210#define HLECALL 26// PCSX fake opcodes for HLE
b9b61529 211#define COP2 27 // Coprocessor 2 move
212#define C2LS 28 // Coprocessor 2 load/store
213#define C2OP 29 // Coprocessor 2 operation
1e973cb0 214#define INTCALL 30// Call interpreter to handle rare corner cases
57871462 215
216 /* stubs */
217#define CC_STUB 1
218#define FP_STUB 2
219#define LOADB_STUB 3
220#define LOADH_STUB 4
221#define LOADW_STUB 5
222#define LOADD_STUB 6
223#define LOADBU_STUB 7
224#define LOADHU_STUB 8
225#define STOREB_STUB 9
226#define STOREH_STUB 10
227#define STOREW_STUB 11
228#define STORED_STUB 12
229#define STORELR_STUB 13
230#define INVCODE_STUB 14
231
232 /* branch codes */
233#define TAKEN 1
234#define NOTTAKEN 2
235#define NULLDS 3
236
237// asm linkage
238int new_recompile_block(int addr);
239void *get_addr_ht(u_int vaddr);
240void invalidate_block(u_int block);
241void invalidate_addr(u_int addr);
242void remove_hash(int vaddr);
57871462 243void dyna_linker();
244void dyna_linker_ds();
245void verify_code();
246void verify_code_vm();
247void verify_code_ds();
248void cc_interrupt();
249void fp_exception();
250void fp_exception_ds();
7139f3c8 251void jump_syscall_hle();
7139f3c8 252void jump_hlecall();
1e973cb0 253void jump_intcall();
7139f3c8 254void new_dyna_leave();
57871462 255
57871462 256// Needed by assembler
e2b5e7aa 257static void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
258static void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
259static void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
260static void load_all_regs(signed char i_regmap[]);
261static void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
262static void load_regs_entry(int t);
263static void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
264
265static int verify_dirty(u_int *ptr);
266static int get_final_value(int hr, int i, int *value);
267static void add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e);
268static void add_to_linker(int addr,int target,int ext);
57871462 269
e2b5e7aa 270static int tracedebug=0;
57871462 271
d148d265 272static void mprotect_w_x(void *start, void *end, int is_x)
273{
274#ifdef NO_WRITE_EXEC
1e212a25 275 #if defined(VITA)
276 // *Open* enables write on all memory that was
277 // allocated by sceKernelAllocMemBlockForVM()?
278 if (is_x)
279 sceKernelCloseVMDomain();
280 else
281 sceKernelOpenVMDomain();
282 #else
d148d265 283 u_long mstart = (u_long)start & ~4095ul;
284 u_long mend = (u_long)end;
285 if (mprotect((void *)mstart, mend - mstart,
286 PROT_READ | (is_x ? PROT_EXEC : PROT_WRITE)) != 0)
287 SysPrintf("mprotect(%c) failed: %s\n", is_x ? 'x' : 'w', strerror(errno));
1e212a25 288 #endif
d148d265 289#endif
290}
291
292static void start_tcache_write(void *start, void *end)
293{
294 mprotect_w_x(start, end, 0);
295}
296
297static void end_tcache_write(void *start, void *end)
298{
299#ifdef __arm__
300 size_t len = (char *)end - (char *)start;
301 #if defined(__BLACKBERRY_QNX__)
302 msync(start, len, MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE);
303 #elif defined(__MACH__)
304 sys_cache_control(kCacheFunctionPrepareForExecution, start, len);
305 #elif defined(VITA)
1e212a25 306 sceKernelSyncVMDomain(sceBlock, start, len);
307 #elif defined(_3DS)
308 ctr_flush_invalidate_cache();
d148d265 309 #else
310 __clear_cache(start, end);
311 #endif
312 (void)len;
313#endif
314
315 mprotect_w_x(start, end, 1);
316}
317
318static void *start_block(void)
319{
320 u_char *end = out + MAX_OUTPUT_BLOCK_SIZE;
321 if (end > (u_char *)BASE_ADDR + (1<<TARGET_SIZE_2))
322 end = (u_char *)BASE_ADDR + (1<<TARGET_SIZE_2);
323 start_tcache_write(out, end);
324 return out;
325}
326
327static void end_block(void *start)
328{
329 end_tcache_write(start, out);
330}
331
57871462 332//#define DEBUG_CYCLE_COUNT 1
333
b6e87b2b 334#define NO_CYCLE_PENALTY_THR 12
335
4e9dcd7f 336int cycle_multiplier; // 100 for 1.0
337
338static int CLOCK_ADJUST(int x)
339{
340 int s=(x>>31)|1;
341 return (x * cycle_multiplier + s * 50) / 100;
342}
343
94d23bb9 344static u_int get_page(u_int vaddr)
57871462 345{
0ce47d46 346 u_int page=vaddr&~0xe0000000;
347 if (page < 0x1000000)
348 page &= ~0x0e00000; // RAM mirrors
349 page>>=12;
57871462 350 if(page>2048) page=2048+(page&2047);
94d23bb9 351 return page;
352}
353
d25604ca 354// no virtual mem in PCSX
355static u_int get_vpage(u_int vaddr)
356{
357 return get_page(vaddr);
358}
94d23bb9 359
360// Get address from virtual address
361// This is called from the recompiled JR/JALR instructions
362void *get_addr(u_int vaddr)
363{
364 u_int page=get_page(vaddr);
365 u_int vpage=get_vpage(vaddr);
57871462 366 struct ll_entry *head;
367 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
368 head=jump_in[page];
369 while(head!=NULL) {
de5a60c3 370 if(head->vaddr==vaddr) {
57871462 371 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
581335b0 372 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
57871462 373 ht_bin[3]=ht_bin[1];
374 ht_bin[2]=ht_bin[0];
581335b0 375 ht_bin[1]=(u_int)head->addr;
57871462 376 ht_bin[0]=vaddr;
377 return head->addr;
378 }
379 head=head->next;
380 }
381 head=jump_dirty[vpage];
382 while(head!=NULL) {
de5a60c3 383 if(head->vaddr==vaddr) {
57871462 384 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
385 // Don't restore blocks which are about to expire from the cache
386 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
387 if(verify_dirty(head->addr)) {
388 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
389 invalid_code[vaddr>>12]=0;
9be4ba64 390 inv_code_start=inv_code_end=~0;
57871462 391 if(vpage<2048) {
57871462 392 restore_candidate[vpage>>3]|=1<<(vpage&7);
393 }
394 else restore_candidate[page>>3]|=1<<(page&7);
581335b0 395 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
57871462 396 if(ht_bin[0]==vaddr) {
581335b0 397 ht_bin[1]=(u_int)head->addr; // Replace existing entry
57871462 398 }
399 else
400 {
401 ht_bin[3]=ht_bin[1];
402 ht_bin[2]=ht_bin[0];
403 ht_bin[1]=(int)head->addr;
404 ht_bin[0]=vaddr;
405 }
406 return head->addr;
407 }
408 }
409 head=head->next;
410 }
411 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
412 int r=new_recompile_block(vaddr);
413 if(r==0) return get_addr(vaddr);
414 // Execute in unmapped page, generate pagefault execption
415 Status|=2;
416 Cause=(vaddr<<31)|0x8;
417 EPC=(vaddr&1)?vaddr-5:vaddr;
418 BadVAddr=(vaddr&~1);
419 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
420 EntryHi=BadVAddr&0xFFFFE000;
421 return get_addr_ht(0x80000000);
422}
423// Look up address in hash table first
424void *get_addr_ht(u_int vaddr)
425{
426 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
581335b0 427 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
57871462 428 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
429 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
430 return get_addr(vaddr);
431}
432
57871462 433void clear_all_regs(signed char regmap[])
434{
435 int hr;
436 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
437}
438
439signed char get_reg(signed char regmap[],int r)
440{
441 int hr;
442 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
443 return -1;
444}
445
446// Find a register that is available for two consecutive cycles
447signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
448{
449 int hr;
450 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
451 return -1;
452}
453
454int count_free_regs(signed char regmap[])
455{
456 int count=0;
457 int hr;
458 for(hr=0;hr<HOST_REGS;hr++)
459 {
460 if(hr!=EXCLUDE_REG) {
461 if(regmap[hr]<0) count++;
462 }
463 }
464 return count;
465}
466
467void dirty_reg(struct regstat *cur,signed char reg)
468{
469 int hr;
470 if(!reg) return;
471 for (hr=0;hr<HOST_REGS;hr++) {
472 if((cur->regmap[hr]&63)==reg) {
473 cur->dirty|=1<<hr;
474 }
475 }
476}
477
478// If we dirty the lower half of a 64 bit register which is now being
479// sign-extended, we need to dump the upper half.
480// Note: Do this only after completion of the instruction, because
481// some instructions may need to read the full 64-bit value even if
482// overwriting it (eg SLTI, DSRA32).
483static void flush_dirty_uppers(struct regstat *cur)
484{
485 int hr,reg;
486 for (hr=0;hr<HOST_REGS;hr++) {
487 if((cur->dirty>>hr)&1) {
488 reg=cur->regmap[hr];
9f51b4b9 489 if(reg>=64)
57871462 490 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
491 }
492 }
493}
494
495void set_const(struct regstat *cur,signed char reg,uint64_t value)
496{
497 int hr;
498 if(!reg) return;
499 for (hr=0;hr<HOST_REGS;hr++) {
500 if(cur->regmap[hr]==reg) {
501 cur->isconst|=1<<hr;
956f3129 502 current_constmap[hr]=value;
57871462 503 }
504 else if((cur->regmap[hr]^64)==reg) {
505 cur->isconst|=1<<hr;
956f3129 506 current_constmap[hr]=value>>32;
57871462 507 }
508 }
509}
510
511void clear_const(struct regstat *cur,signed char reg)
512{
513 int hr;
514 if(!reg) return;
515 for (hr=0;hr<HOST_REGS;hr++) {
516 if((cur->regmap[hr]&63)==reg) {
517 cur->isconst&=~(1<<hr);
518 }
519 }
520}
521
522int is_const(struct regstat *cur,signed char reg)
523{
524 int hr;
79c75f1b 525 if(reg<0) return 0;
57871462 526 if(!reg) return 1;
527 for (hr=0;hr<HOST_REGS;hr++) {
528 if((cur->regmap[hr]&63)==reg) {
529 return (cur->isconst>>hr)&1;
530 }
531 }
532 return 0;
533}
534uint64_t get_const(struct regstat *cur,signed char reg)
535{
536 int hr;
537 if(!reg) return 0;
538 for (hr=0;hr<HOST_REGS;hr++) {
539 if(cur->regmap[hr]==reg) {
956f3129 540 return current_constmap[hr];
57871462 541 }
542 }
c43b5311 543 SysPrintf("Unknown constant in r%d\n",reg);
57871462 544 exit(1);
545}
546
547// Least soon needed registers
548// Look at the next ten instructions and see which registers
549// will be used. Try not to reallocate these.
550void lsn(u_char hsn[], int i, int *preferred_reg)
551{
552 int j;
553 int b=-1;
554 for(j=0;j<9;j++)
555 {
556 if(i+j>=slen) {
557 j=slen-i-1;
558 break;
559 }
560 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
561 {
562 // Don't go past an unconditonal jump
563 j++;
564 break;
565 }
566 }
567 for(;j>=0;j--)
568 {
569 if(rs1[i+j]) hsn[rs1[i+j]]=j;
570 if(rs2[i+j]) hsn[rs2[i+j]]=j;
571 if(rt1[i+j]) hsn[rt1[i+j]]=j;
572 if(rt2[i+j]) hsn[rt2[i+j]]=j;
573 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
574 // Stores can allocate zero
575 hsn[rs1[i+j]]=j;
576 hsn[rs2[i+j]]=j;
577 }
578 // On some architectures stores need invc_ptr
579 #if defined(HOST_IMM8)
b9b61529 580 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
57871462 581 hsn[INVCP]=j;
582 }
583 #endif
584 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
585 {
586 hsn[CCREG]=j;
587 b=j;
588 }
589 }
590 if(b>=0)
591 {
592 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
593 {
594 // Follow first branch
595 int t=(ba[i+b]-start)>>2;
596 j=7-b;if(t+j>=slen) j=slen-t-1;
597 for(;j>=0;j--)
598 {
599 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
600 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
601 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
602 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
603 }
604 }
605 // TODO: preferred register based on backward branch
606 }
607 // Delay slot should preferably not overwrite branch conditions or cycle count
608 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
609 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
610 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
611 hsn[CCREG]=1;
612 // ...or hash tables
613 hsn[RHASH]=1;
614 hsn[RHTBL]=1;
615 }
616 // Coprocessor load/store needs FTEMP, even if not declared
b9b61529 617 if(itype[i]==C1LS||itype[i]==C2LS) {
57871462 618 hsn[FTEMP]=0;
619 }
620 // Load L/R also uses FTEMP as a temporary register
621 if(itype[i]==LOADLR) {
622 hsn[FTEMP]=0;
623 }
b7918751 624 // Also SWL/SWR/SDL/SDR
625 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
57871462 626 hsn[FTEMP]=0;
627 }
57871462 628 // Don't remove the miniht registers
629 if(itype[i]==UJUMP||itype[i]==RJUMP)
630 {
631 hsn[RHASH]=0;
632 hsn[RHTBL]=0;
633 }
634}
635
636// We only want to allocate registers if we're going to use them again soon
637int needed_again(int r, int i)
638{
639 int j;
640 int b=-1;
641 int rn=10;
9f51b4b9 642
57871462 643 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
644 {
645 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
646 return 0; // Don't need any registers if exiting the block
647 }
648 for(j=0;j<9;j++)
649 {
650 if(i+j>=slen) {
651 j=slen-i-1;
652 break;
653 }
654 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
655 {
656 // Don't go past an unconditonal jump
657 j++;
658 break;
659 }
1e973cb0 660 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
57871462 661 {
662 break;
663 }
664 }
665 for(;j>=1;j--)
666 {
667 if(rs1[i+j]==r) rn=j;
668 if(rs2[i+j]==r) rn=j;
669 if((unneeded_reg[i+j]>>r)&1) rn=10;
670 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
671 {
672 b=j;
673 }
674 }
675 /*
676 if(b>=0)
677 {
678 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
679 {
680 // Follow first branch
681 int o=rn;
682 int t=(ba[i+b]-start)>>2;
683 j=7-b;if(t+j>=slen) j=slen-t-1;
684 for(;j>=0;j--)
685 {
686 if(!((unneeded_reg[t+j]>>r)&1)) {
687 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
688 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
689 }
690 else rn=o;
691 }
692 }
693 }*/
b7217e13 694 if(rn<10) return 1;
581335b0 695 (void)b;
57871462 696 return 0;
697}
698
699// Try to match register allocations at the end of a loop with those
700// at the beginning
701int loop_reg(int i, int r, int hr)
702{
703 int j,k;
704 for(j=0;j<9;j++)
705 {
706 if(i+j>=slen) {
707 j=slen-i-1;
708 break;
709 }
710 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
711 {
712 // Don't go past an unconditonal jump
713 j++;
714 break;
715 }
716 }
717 k=0;
718 if(i>0){
719 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
720 k--;
721 }
722 for(;k<j;k++)
723 {
724 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
725 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
726 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
727 {
728 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
729 {
730 int t=(ba[i+k]-start)>>2;
731 int reg=get_reg(regs[t].regmap_entry,r);
732 if(reg>=0) return reg;
733 //reg=get_reg(regs[t+1].regmap_entry,r);
734 //if(reg>=0) return reg;
735 }
736 }
737 }
738 return hr;
739}
740
741
742// Allocate every register, preserving source/target regs
743void alloc_all(struct regstat *cur,int i)
744{
745 int hr;
9f51b4b9 746
57871462 747 for(hr=0;hr<HOST_REGS;hr++) {
748 if(hr!=EXCLUDE_REG) {
749 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
750 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
751 {
752 cur->regmap[hr]=-1;
753 cur->dirty&=~(1<<hr);
754 }
755 // Don't need zeros
756 if((cur->regmap[hr]&63)==0)
757 {
758 cur->regmap[hr]=-1;
759 cur->dirty&=~(1<<hr);
760 }
761 }
762 }
763}
764
57871462 765#ifdef __i386__
766#include "assem_x86.c"
767#endif
768#ifdef __x86_64__
769#include "assem_x64.c"
770#endif
771#ifdef __arm__
772#include "assem_arm.c"
773#endif
774
775// Add virtual address mapping to linked list
776void ll_add(struct ll_entry **head,int vaddr,void *addr)
777{
778 struct ll_entry *new_entry;
779 new_entry=malloc(sizeof(struct ll_entry));
780 assert(new_entry!=NULL);
781 new_entry->vaddr=vaddr;
de5a60c3 782 new_entry->reg_sv_flags=0;
57871462 783 new_entry->addr=addr;
784 new_entry->next=*head;
785 *head=new_entry;
786}
787
de5a60c3 788void ll_add_flags(struct ll_entry **head,int vaddr,u_int reg_sv_flags,void *addr)
57871462 789{
7139f3c8 790 ll_add(head,vaddr,addr);
de5a60c3 791 (*head)->reg_sv_flags=reg_sv_flags;
57871462 792}
793
794// Check if an address is already compiled
795// but don't return addresses which are about to expire from the cache
796void *check_addr(u_int vaddr)
797{
798 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
799 if(ht_bin[0]==vaddr) {
800 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
801 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
802 }
803 if(ht_bin[2]==vaddr) {
804 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
805 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
806 }
94d23bb9 807 u_int page=get_page(vaddr);
57871462 808 struct ll_entry *head;
809 head=jump_in[page];
810 while(head!=NULL) {
de5a60c3 811 if(head->vaddr==vaddr) {
57871462 812 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
813 // Update existing entry with current address
814 if(ht_bin[0]==vaddr) {
815 ht_bin[1]=(int)head->addr;
816 return head->addr;
817 }
818 if(ht_bin[2]==vaddr) {
819 ht_bin[3]=(int)head->addr;
820 return head->addr;
821 }
822 // Insert into hash table with low priority.
823 // Don't evict existing entries, as they are probably
824 // addresses that are being accessed frequently.
825 if(ht_bin[0]==-1) {
826 ht_bin[1]=(int)head->addr;
827 ht_bin[0]=vaddr;
828 }else if(ht_bin[2]==-1) {
829 ht_bin[3]=(int)head->addr;
830 ht_bin[2]=vaddr;
831 }
832 return head->addr;
833 }
834 }
835 head=head->next;
836 }
837 return 0;
838}
839
840void remove_hash(int vaddr)
841{
842 //printf("remove hash: %x\n",vaddr);
581335b0 843 u_int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
57871462 844 if(ht_bin[2]==vaddr) {
845 ht_bin[2]=ht_bin[3]=-1;
846 }
847 if(ht_bin[0]==vaddr) {
848 ht_bin[0]=ht_bin[2];
849 ht_bin[1]=ht_bin[3];
850 ht_bin[2]=ht_bin[3]=-1;
851 }
852}
853
854void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
855{
856 struct ll_entry *next;
857 while(*head) {
9f51b4b9 858 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
57871462 859 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
860 {
861 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
862 remove_hash((*head)->vaddr);
863 next=(*head)->next;
864 free(*head);
865 *head=next;
866 }
867 else
868 {
869 head=&((*head)->next);
870 }
871 }
872}
873
874// Remove all entries from linked list
875void ll_clear(struct ll_entry **head)
876{
877 struct ll_entry *cur;
878 struct ll_entry *next;
581335b0 879 if((cur=*head)) {
57871462 880 *head=0;
881 while(cur) {
882 next=cur->next;
883 free(cur);
884 cur=next;
885 }
886 }
887}
888
889// Dereference the pointers and remove if it matches
d148d265 890static void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
57871462 891{
892 while(head) {
893 int ptr=get_pointer(head->addr);
894 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
895 if(((ptr>>shift)==(addr>>shift)) ||
896 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
897 {
5088bb70 898 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
d148d265 899 void *host_addr=find_extjump_insn(head->addr);
dd3a91a1 900 #ifdef __arm__
d148d265 901 mark_clear_cache(host_addr);
dd3a91a1 902 #endif
d148d265 903 set_jump_target((int)host_addr,(int)head->addr);
57871462 904 }
905 head=head->next;
906 }
907}
908
909// This is called when we write to a compiled block (see do_invstub)
f76eeef9 910void invalidate_page(u_int page)
57871462 911{
57871462 912 struct ll_entry *head;
913 struct ll_entry *next;
914 head=jump_in[page];
915 jump_in[page]=0;
916 while(head!=NULL) {
917 inv_debug("INVALIDATE: %x\n",head->vaddr);
918 remove_hash(head->vaddr);
919 next=head->next;
920 free(head);
921 head=next;
922 }
923 head=jump_out[page];
924 jump_out[page]=0;
925 while(head!=NULL) {
926 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
d148d265 927 void *host_addr=find_extjump_insn(head->addr);
dd3a91a1 928 #ifdef __arm__
d148d265 929 mark_clear_cache(host_addr);
dd3a91a1 930 #endif
d148d265 931 set_jump_target((int)host_addr,(int)head->addr);
57871462 932 next=head->next;
933 free(head);
934 head=next;
935 }
57871462 936}
9be4ba64 937
938static void invalidate_block_range(u_int block, u_int first, u_int last)
57871462 939{
94d23bb9 940 u_int page=get_page(block<<12);
57871462 941 //printf("first=%d last=%d\n",first,last);
f76eeef9 942 invalidate_page(page);
57871462 943 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
944 assert(last<page+5);
945 // Invalidate the adjacent pages if a block crosses a 4K boundary
946 while(first<page) {
947 invalidate_page(first);
948 first++;
949 }
950 for(first=page+1;first<last;first++) {
951 invalidate_page(first);
952 }
dd3a91a1 953 #ifdef __arm__
954 do_clear_cache();
955 #endif
9f51b4b9 956
57871462 957 // Don't trap writes
958 invalid_code[block]=1;
f76eeef9 959
57871462 960 #ifdef USE_MINI_HT
961 memset(mini_ht,-1,sizeof(mini_ht));
962 #endif
963}
9be4ba64 964
965void invalidate_block(u_int block)
966{
967 u_int page=get_page(block<<12);
968 u_int vpage=get_vpage(block<<12);
969 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
970 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
971 u_int first,last;
972 first=last=page;
973 struct ll_entry *head;
974 head=jump_dirty[vpage];
975 //printf("page=%d vpage=%d\n",page,vpage);
976 while(head!=NULL) {
977 u_int start,end;
978 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
979 get_bounds((int)head->addr,&start,&end);
980 //printf("start: %x end: %x\n",start,end);
4a35de07 981 if(page<2048&&start>=(u_int)rdram&&end<(u_int)rdram+RAM_SIZE) {
9be4ba64 982 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
983 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
984 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
985 }
986 }
9be4ba64 987 }
988 head=head->next;
989 }
990 invalidate_block_range(block,first,last);
991}
992
57871462 993void invalidate_addr(u_int addr)
994{
9be4ba64 995 //static int rhits;
996 // this check is done by the caller
997 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
d25604ca 998 u_int page=get_vpage(addr);
9be4ba64 999 if(page<2048) { // RAM
1000 struct ll_entry *head;
1001 u_int addr_min=~0, addr_max=0;
4a35de07 1002 u_int mask=RAM_SIZE-1;
1003 u_int addr_main=0x80000000|(addr&mask);
9be4ba64 1004 int pg1;
4a35de07 1005 inv_code_start=addr_main&~0xfff;
1006 inv_code_end=addr_main|0xfff;
9be4ba64 1007 pg1=page;
1008 if (pg1>0) {
1009 // must check previous page too because of spans..
1010 pg1--;
1011 inv_code_start-=0x1000;
1012 }
1013 for(;pg1<=page;pg1++) {
1014 for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
1015 u_int start,end;
1016 get_bounds((int)head->addr,&start,&end);
4a35de07 1017 if(ram_offset) {
1018 start-=ram_offset;
1019 end-=ram_offset;
1020 }
1021 if(start<=addr_main&&addr_main<end) {
9be4ba64 1022 if(start<addr_min) addr_min=start;
1023 if(end>addr_max) addr_max=end;
1024 }
4a35de07 1025 else if(addr_main<start) {
9be4ba64 1026 if(start<inv_code_end)
1027 inv_code_end=start-1;
1028 }
1029 else {
1030 if(end>inv_code_start)
1031 inv_code_start=end;
1032 }
1033 }
1034 }
1035 if (addr_min!=~0) {
1036 inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1037 inv_code_start=inv_code_end=~0;
1038 invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1039 return;
1040 }
1041 else {
4a35de07 1042 inv_code_start=(addr&~mask)|(inv_code_start&mask);
1043 inv_code_end=(addr&~mask)|(inv_code_end&mask);
d25604ca 1044 inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);
9be4ba64 1045 return;
d25604ca 1046 }
9be4ba64 1047 }
57871462 1048 invalidate_block(addr>>12);
1049}
9be4ba64 1050
dd3a91a1 1051// This is called when loading a save state.
1052// Anything could have changed, so invalidate everything.
57871462 1053void invalidate_all_pages()
1054{
581335b0 1055 u_int page;
57871462 1056 for(page=0;page<4096;page++)
1057 invalidate_page(page);
1058 for(page=0;page<1048576;page++)
1059 if(!invalid_code[page]) {
1060 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1061 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1062 }
57871462 1063 #ifdef USE_MINI_HT
1064 memset(mini_ht,-1,sizeof(mini_ht));
1065 #endif
57871462 1066}
1067
1068// Add an entry to jump_out after making a link
1069void add_link(u_int vaddr,void *src)
1070{
94d23bb9 1071 u_int page=get_page(vaddr);
57871462 1072 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
76f71c27 1073 int *ptr=(int *)(src+4);
1074 assert((*ptr&0x0fff0000)==0x059f0000);
581335b0 1075 (void)ptr;
57871462 1076 ll_add(jump_out+page,vaddr,src);
1077 //int ptr=get_pointer(src);
1078 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1079}
1080
1081// If a code block was found to be unmodified (bit was set in
1082// restore_candidate) and it remains unmodified (bit is clear
1083// in invalid_code) then move the entries for that 4K page from
1084// the dirty list to the clean list.
1085void clean_blocks(u_int page)
1086{
1087 struct ll_entry *head;
1088 inv_debug("INV: clean_blocks page=%d\n",page);
1089 head=jump_dirty[page];
1090 while(head!=NULL) {
1091 if(!invalid_code[head->vaddr>>12]) {
1092 // Don't restore blocks which are about to expire from the cache
1093 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1094 u_int start,end;
581335b0 1095 if(verify_dirty(head->addr)) {
57871462 1096 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1097 u_int i;
1098 u_int inv=0;
1099 get_bounds((int)head->addr,&start,&end);
4cb76aa4 1100 if(start-(u_int)rdram<RAM_SIZE) {
57871462 1101 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1102 inv|=invalid_code[i];
1103 }
1104 }
4cb76aa4 1105 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
57871462 1106 inv=1;
1107 }
1108 if(!inv) {
1109 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1110 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1111 u_int ppage=page;
57871462 1112 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1113 //printf("page=%x, addr=%x\n",page,head->vaddr);
1114 //assert(head->vaddr>>12==(page|0x80000));
de5a60c3 1115 ll_add_flags(jump_in+ppage,head->vaddr,head->reg_sv_flags,clean_addr);
581335b0 1116 u_int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
de5a60c3 1117 if(ht_bin[0]==head->vaddr) {
581335b0 1118 ht_bin[1]=(u_int)clean_addr; // Replace existing entry
de5a60c3 1119 }
1120 if(ht_bin[2]==head->vaddr) {
581335b0 1121 ht_bin[3]=(u_int)clean_addr; // Replace existing entry
57871462 1122 }
1123 }
1124 }
1125 }
1126 }
1127 }
1128 head=head->next;
1129 }
1130}
1131
1132
1133void mov_alloc(struct regstat *current,int i)
1134{
1135 // Note: Don't need to actually alloc the source registers
1136 if((~current->is32>>rs1[i])&1) {
1137 //alloc_reg64(current,i,rs1[i]);
1138 alloc_reg64(current,i,rt1[i]);
1139 current->is32&=~(1LL<<rt1[i]);
1140 } else {
1141 //alloc_reg(current,i,rs1[i]);
1142 alloc_reg(current,i,rt1[i]);
1143 current->is32|=(1LL<<rt1[i]);
1144 }
1145 clear_const(current,rs1[i]);
1146 clear_const(current,rt1[i]);
1147 dirty_reg(current,rt1[i]);
1148}
1149
1150void shiftimm_alloc(struct regstat *current,int i)
1151{
57871462 1152 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1153 {
1154 if(rt1[i]) {
1155 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1156 else lt1[i]=rs1[i];
1157 alloc_reg(current,i,rt1[i]);
1158 current->is32|=1LL<<rt1[i];
1159 dirty_reg(current,rt1[i]);
dc49e339 1160 if(is_const(current,rs1[i])) {
1161 int v=get_const(current,rs1[i]);
1162 if(opcode2[i]==0x00) set_const(current,rt1[i],v<<imm[i]);
1163 if(opcode2[i]==0x02) set_const(current,rt1[i],(u_int)v>>imm[i]);
1164 if(opcode2[i]==0x03) set_const(current,rt1[i],v>>imm[i]);
1165 }
1166 else clear_const(current,rt1[i]);
57871462 1167 }
1168 }
dc49e339 1169 else
1170 {
1171 clear_const(current,rs1[i]);
1172 clear_const(current,rt1[i]);
1173 }
1174
57871462 1175 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1176 {
1177 if(rt1[i]) {
1178 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1179 alloc_reg64(current,i,rt1[i]);
1180 current->is32&=~(1LL<<rt1[i]);
1181 dirty_reg(current,rt1[i]);
1182 }
1183 }
1184 if(opcode2[i]==0x3c) // DSLL32
1185 {
1186 if(rt1[i]) {
1187 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1188 alloc_reg64(current,i,rt1[i]);
1189 current->is32&=~(1LL<<rt1[i]);
1190 dirty_reg(current,rt1[i]);
1191 }
1192 }
1193 if(opcode2[i]==0x3e) // DSRL32
1194 {
1195 if(rt1[i]) {
1196 alloc_reg64(current,i,rs1[i]);
1197 if(imm[i]==32) {
1198 alloc_reg64(current,i,rt1[i]);
1199 current->is32&=~(1LL<<rt1[i]);
1200 } else {
1201 alloc_reg(current,i,rt1[i]);
1202 current->is32|=1LL<<rt1[i];
1203 }
1204 dirty_reg(current,rt1[i]);
1205 }
1206 }
1207 if(opcode2[i]==0x3f) // DSRA32
1208 {
1209 if(rt1[i]) {
1210 alloc_reg64(current,i,rs1[i]);
1211 alloc_reg(current,i,rt1[i]);
1212 current->is32|=1LL<<rt1[i];
1213 dirty_reg(current,rt1[i]);
1214 }
1215 }
1216}
1217
1218void shift_alloc(struct regstat *current,int i)
1219{
1220 if(rt1[i]) {
1221 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1222 {
1223 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1224 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1225 alloc_reg(current,i,rt1[i]);
e1190b87 1226 if(rt1[i]==rs2[i]) {
1227 alloc_reg_temp(current,i,-1);
1228 minimum_free_regs[i]=1;
1229 }
57871462 1230 current->is32|=1LL<<rt1[i];
1231 } else { // DSLLV/DSRLV/DSRAV
1232 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1233 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1234 alloc_reg64(current,i,rt1[i]);
1235 current->is32&=~(1LL<<rt1[i]);
1236 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
e1190b87 1237 {
57871462 1238 alloc_reg_temp(current,i,-1);
e1190b87 1239 minimum_free_regs[i]=1;
1240 }
57871462 1241 }
1242 clear_const(current,rs1[i]);
1243 clear_const(current,rs2[i]);
1244 clear_const(current,rt1[i]);
1245 dirty_reg(current,rt1[i]);
1246 }
1247}
1248
1249void alu_alloc(struct regstat *current,int i)
1250{
1251 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1252 if(rt1[i]) {
1253 if(rs1[i]&&rs2[i]) {
1254 alloc_reg(current,i,rs1[i]);
1255 alloc_reg(current,i,rs2[i]);
1256 }
1257 else {
1258 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1259 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1260 }
1261 alloc_reg(current,i,rt1[i]);
1262 }
1263 current->is32|=1LL<<rt1[i];
1264 }
1265 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1266 if(rt1[i]) {
1267 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1268 {
1269 alloc_reg64(current,i,rs1[i]);
1270 alloc_reg64(current,i,rs2[i]);
1271 alloc_reg(current,i,rt1[i]);
1272 } else {
1273 alloc_reg(current,i,rs1[i]);
1274 alloc_reg(current,i,rs2[i]);
1275 alloc_reg(current,i,rt1[i]);
1276 }
1277 }
1278 current->is32|=1LL<<rt1[i];
1279 }
1280 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1281 if(rt1[i]) {
1282 if(rs1[i]&&rs2[i]) {
1283 alloc_reg(current,i,rs1[i]);
1284 alloc_reg(current,i,rs2[i]);
1285 }
1286 else
1287 {
1288 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1289 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1290 }
1291 alloc_reg(current,i,rt1[i]);
1292 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1293 {
1294 if(!((current->uu>>rt1[i])&1)) {
1295 alloc_reg64(current,i,rt1[i]);
1296 }
1297 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1298 if(rs1[i]&&rs2[i]) {
1299 alloc_reg64(current,i,rs1[i]);
1300 alloc_reg64(current,i,rs2[i]);
1301 }
1302 else
1303 {
1304 // Is is really worth it to keep 64-bit values in registers?
1305 #ifdef NATIVE_64BIT
1306 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1307 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1308 #endif
1309 }
1310 }
1311 current->is32&=~(1LL<<rt1[i]);
1312 } else {
1313 current->is32|=1LL<<rt1[i];
1314 }
1315 }
1316 }
1317 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1318 if(rt1[i]) {
1319 if(rs1[i]&&rs2[i]) {
1320 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1321 alloc_reg64(current,i,rs1[i]);
1322 alloc_reg64(current,i,rs2[i]);
1323 alloc_reg64(current,i,rt1[i]);
1324 } else {
1325 alloc_reg(current,i,rs1[i]);
1326 alloc_reg(current,i,rs2[i]);
1327 alloc_reg(current,i,rt1[i]);
1328 }
1329 }
1330 else {
1331 alloc_reg(current,i,rt1[i]);
1332 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1333 // DADD used as move, or zeroing
1334 // If we have a 64-bit source, then make the target 64 bits too
1335 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1336 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1337 alloc_reg64(current,i,rt1[i]);
1338 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1339 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1340 alloc_reg64(current,i,rt1[i]);
1341 }
1342 if(opcode2[i]>=0x2e&&rs2[i]) {
1343 // DSUB used as negation - 64-bit result
1344 // If we have a 32-bit register, extend it to 64 bits
1345 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1346 alloc_reg64(current,i,rt1[i]);
1347 }
1348 }
1349 }
1350 if(rs1[i]&&rs2[i]) {
1351 current->is32&=~(1LL<<rt1[i]);
1352 } else if(rs1[i]) {
1353 current->is32&=~(1LL<<rt1[i]);
1354 if((current->is32>>rs1[i])&1)
1355 current->is32|=1LL<<rt1[i];
1356 } else if(rs2[i]) {
1357 current->is32&=~(1LL<<rt1[i]);
1358 if((current->is32>>rs2[i])&1)
1359 current->is32|=1LL<<rt1[i];
1360 } else {
1361 current->is32|=1LL<<rt1[i];
1362 }
1363 }
1364 }
1365 clear_const(current,rs1[i]);
1366 clear_const(current,rs2[i]);
1367 clear_const(current,rt1[i]);
1368 dirty_reg(current,rt1[i]);
1369}
1370
1371void imm16_alloc(struct regstat *current,int i)
1372{
1373 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1374 else lt1[i]=rs1[i];
1375 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1376 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1377 current->is32&=~(1LL<<rt1[i]);
1378 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1379 // TODO: Could preserve the 32-bit flag if the immediate is zero
1380 alloc_reg64(current,i,rt1[i]);
1381 alloc_reg64(current,i,rs1[i]);
1382 }
1383 clear_const(current,rs1[i]);
1384 clear_const(current,rt1[i]);
1385 }
1386 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1387 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1388 current->is32|=1LL<<rt1[i];
1389 clear_const(current,rs1[i]);
1390 clear_const(current,rt1[i]);
1391 }
1392 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1393 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1394 if(rs1[i]!=rt1[i]) {
1395 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1396 alloc_reg64(current,i,rt1[i]);
1397 current->is32&=~(1LL<<rt1[i]);
1398 }
1399 }
1400 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1401 if(is_const(current,rs1[i])) {
1402 int v=get_const(current,rs1[i]);
1403 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1404 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1405 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1406 }
1407 else clear_const(current,rt1[i]);
1408 }
1409 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1410 if(is_const(current,rs1[i])) {
1411 int v=get_const(current,rs1[i]);
1412 set_const(current,rt1[i],v+imm[i]);
1413 }
1414 else clear_const(current,rt1[i]);
1415 current->is32|=1LL<<rt1[i];
1416 }
1417 else {
1418 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1419 current->is32|=1LL<<rt1[i];
1420 }
1421 dirty_reg(current,rt1[i]);
1422}
1423
1424void load_alloc(struct regstat *current,int i)
1425{
1426 clear_const(current,rt1[i]);
1427 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1428 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1429 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
373d1d07 1430 if(rt1[i]&&!((current->u>>rt1[i])&1)) {
57871462 1431 alloc_reg(current,i,rt1[i]);
373d1d07 1432 assert(get_reg(current->regmap,rt1[i])>=0);
57871462 1433 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1434 {
1435 current->is32&=~(1LL<<rt1[i]);
1436 alloc_reg64(current,i,rt1[i]);
1437 }
1438 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1439 {
1440 current->is32&=~(1LL<<rt1[i]);
1441 alloc_reg64(current,i,rt1[i]);
1442 alloc_all(current,i);
1443 alloc_reg64(current,i,FTEMP);
e1190b87 1444 minimum_free_regs[i]=HOST_REGS;
57871462 1445 }
1446 else current->is32|=1LL<<rt1[i];
1447 dirty_reg(current,rt1[i]);
57871462 1448 // LWL/LWR need a temporary register for the old value
1449 if(opcode[i]==0x22||opcode[i]==0x26)
1450 {
1451 alloc_reg(current,i,FTEMP);
1452 alloc_reg_temp(current,i,-1);
e1190b87 1453 minimum_free_regs[i]=1;
57871462 1454 }
1455 }
1456 else
1457 {
373d1d07 1458 // Load to r0 or unneeded register (dummy load)
57871462 1459 // but we still need a register to calculate the address
535d208a 1460 if(opcode[i]==0x22||opcode[i]==0x26)
1461 {
1462 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1463 }
57871462 1464 alloc_reg_temp(current,i,-1);
e1190b87 1465 minimum_free_regs[i]=1;
535d208a 1466 if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1467 {
1468 alloc_all(current,i);
1469 alloc_reg64(current,i,FTEMP);
e1190b87 1470 minimum_free_regs[i]=HOST_REGS;
535d208a 1471 }
57871462 1472 }
1473}
1474
1475void store_alloc(struct regstat *current,int i)
1476{
1477 clear_const(current,rs2[i]);
1478 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1479 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1480 alloc_reg(current,i,rs2[i]);
1481 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1482 alloc_reg64(current,i,rs2[i]);
1483 if(rs2[i]) alloc_reg(current,i,FTEMP);
1484 }
57871462 1485 #if defined(HOST_IMM8)
1486 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1487 else alloc_reg(current,i,INVCP);
1488 #endif
b7918751 1489 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
57871462 1490 alloc_reg(current,i,FTEMP);
1491 }
1492 // We need a temporary register for address generation
1493 alloc_reg_temp(current,i,-1);
e1190b87 1494 minimum_free_regs[i]=1;
57871462 1495}
1496
1497void c1ls_alloc(struct regstat *current,int i)
1498{
1499 //clear_const(current,rs1[i]); // FIXME
1500 clear_const(current,rt1[i]);
1501 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1502 alloc_reg(current,i,CSREG); // Status
1503 alloc_reg(current,i,FTEMP);
1504 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1505 alloc_reg64(current,i,FTEMP);
1506 }
57871462 1507 #if defined(HOST_IMM8)
1508 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1509 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1510 alloc_reg(current,i,INVCP);
1511 #endif
1512 // We need a temporary register for address generation
1513 alloc_reg_temp(current,i,-1);
1514}
1515
b9b61529 1516void c2ls_alloc(struct regstat *current,int i)
1517{
1518 clear_const(current,rt1[i]);
1519 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1520 alloc_reg(current,i,FTEMP);
b9b61529 1521 #if defined(HOST_IMM8)
1522 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1edfcc68 1523 if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
b9b61529 1524 alloc_reg(current,i,INVCP);
1525 #endif
1526 // We need a temporary register for address generation
1527 alloc_reg_temp(current,i,-1);
e1190b87 1528 minimum_free_regs[i]=1;
b9b61529 1529}
1530
57871462 1531#ifndef multdiv_alloc
1532void multdiv_alloc(struct regstat *current,int i)
1533{
1534 // case 0x18: MULT
1535 // case 0x19: MULTU
1536 // case 0x1A: DIV
1537 // case 0x1B: DIVU
1538 // case 0x1C: DMULT
1539 // case 0x1D: DMULTU
1540 // case 0x1E: DDIV
1541 // case 0x1F: DDIVU
1542 clear_const(current,rs1[i]);
1543 clear_const(current,rs2[i]);
1544 if(rs1[i]&&rs2[i])
1545 {
1546 if((opcode2[i]&4)==0) // 32-bit
1547 {
1548 current->u&=~(1LL<<HIREG);
1549 current->u&=~(1LL<<LOREG);
1550 alloc_reg(current,i,HIREG);
1551 alloc_reg(current,i,LOREG);
1552 alloc_reg(current,i,rs1[i]);
1553 alloc_reg(current,i,rs2[i]);
1554 current->is32|=1LL<<HIREG;
1555 current->is32|=1LL<<LOREG;
1556 dirty_reg(current,HIREG);
1557 dirty_reg(current,LOREG);
1558 }
1559 else // 64-bit
1560 {
1561 current->u&=~(1LL<<HIREG);
1562 current->u&=~(1LL<<LOREG);
1563 current->uu&=~(1LL<<HIREG);
1564 current->uu&=~(1LL<<LOREG);
1565 alloc_reg64(current,i,HIREG);
1566 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1567 alloc_reg64(current,i,rs1[i]);
1568 alloc_reg64(current,i,rs2[i]);
1569 alloc_all(current,i);
1570 current->is32&=~(1LL<<HIREG);
1571 current->is32&=~(1LL<<LOREG);
1572 dirty_reg(current,HIREG);
1573 dirty_reg(current,LOREG);
e1190b87 1574 minimum_free_regs[i]=HOST_REGS;
57871462 1575 }
1576 }
1577 else
1578 {
1579 // Multiply by zero is zero.
1580 // MIPS does not have a divide by zero exception.
1581 // The result is undefined, we return zero.
1582 alloc_reg(current,i,HIREG);
1583 alloc_reg(current,i,LOREG);
1584 current->is32|=1LL<<HIREG;
1585 current->is32|=1LL<<LOREG;
1586 dirty_reg(current,HIREG);
1587 dirty_reg(current,LOREG);
1588 }
1589}
1590#endif
1591
1592void cop0_alloc(struct regstat *current,int i)
1593{
1594 if(opcode2[i]==0) // MFC0
1595 {
1596 if(rt1[i]) {
1597 clear_const(current,rt1[i]);
1598 alloc_all(current,i);
1599 alloc_reg(current,i,rt1[i]);
1600 current->is32|=1LL<<rt1[i];
1601 dirty_reg(current,rt1[i]);
1602 }
1603 }
1604 else if(opcode2[i]==4) // MTC0
1605 {
1606 if(rs1[i]){
1607 clear_const(current,rs1[i]);
1608 alloc_reg(current,i,rs1[i]);
1609 alloc_all(current,i);
1610 }
1611 else {
1612 alloc_all(current,i); // FIXME: Keep r0
1613 current->u&=~1LL;
1614 alloc_reg(current,i,0);
1615 }
1616 }
1617 else
1618 {
1619 // TLBR/TLBWI/TLBWR/TLBP/ERET
1620 assert(opcode2[i]==0x10);
1621 alloc_all(current,i);
1622 }
e1190b87 1623 minimum_free_regs[i]=HOST_REGS;
57871462 1624}
1625
1626void cop1_alloc(struct regstat *current,int i)
1627{
1628 alloc_reg(current,i,CSREG); // Load status
1629 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1630 {
7de557a6 1631 if(rt1[i]){
1632 clear_const(current,rt1[i]);
1633 if(opcode2[i]==1) {
1634 alloc_reg64(current,i,rt1[i]); // DMFC1
1635 current->is32&=~(1LL<<rt1[i]);
1636 }else{
1637 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1638 current->is32|=1LL<<rt1[i];
1639 }
1640 dirty_reg(current,rt1[i]);
57871462 1641 }
57871462 1642 alloc_reg_temp(current,i,-1);
1643 }
1644 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1645 {
1646 if(rs1[i]){
1647 clear_const(current,rs1[i]);
1648 if(opcode2[i]==5)
1649 alloc_reg64(current,i,rs1[i]); // DMTC1
1650 else
1651 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1652 alloc_reg_temp(current,i,-1);
1653 }
1654 else {
1655 current->u&=~1LL;
1656 alloc_reg(current,i,0);
1657 alloc_reg_temp(current,i,-1);
1658 }
1659 }
e1190b87 1660 minimum_free_regs[i]=1;
57871462 1661}
1662void fconv_alloc(struct regstat *current,int i)
1663{
1664 alloc_reg(current,i,CSREG); // Load status
1665 alloc_reg_temp(current,i,-1);
e1190b87 1666 minimum_free_regs[i]=1;
57871462 1667}
1668void float_alloc(struct regstat *current,int i)
1669{
1670 alloc_reg(current,i,CSREG); // Load status
1671 alloc_reg_temp(current,i,-1);
e1190b87 1672 minimum_free_regs[i]=1;
57871462 1673}
b9b61529 1674void c2op_alloc(struct regstat *current,int i)
1675{
1676 alloc_reg_temp(current,i,-1);
1677}
57871462 1678void fcomp_alloc(struct regstat *current,int i)
1679{
1680 alloc_reg(current,i,CSREG); // Load status
1681 alloc_reg(current,i,FSREG); // Load flags
1682 dirty_reg(current,FSREG); // Flag will be modified
1683 alloc_reg_temp(current,i,-1);
e1190b87 1684 minimum_free_regs[i]=1;
57871462 1685}
1686
1687void syscall_alloc(struct regstat *current,int i)
1688{
1689 alloc_cc(current,i);
1690 dirty_reg(current,CCREG);
1691 alloc_all(current,i);
e1190b87 1692 minimum_free_regs[i]=HOST_REGS;
57871462 1693 current->isconst=0;
1694}
1695
1696void delayslot_alloc(struct regstat *current,int i)
1697{
1698 switch(itype[i]) {
1699 case UJUMP:
1700 case CJUMP:
1701 case SJUMP:
1702 case RJUMP:
1703 case FJUMP:
1704 case SYSCALL:
7139f3c8 1705 case HLECALL:
57871462 1706 case SPAN:
1707 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
c43b5311 1708 SysPrintf("Disabled speculative precompilation\n");
57871462 1709 stop_after_jal=1;
1710 break;
1711 case IMM16:
1712 imm16_alloc(current,i);
1713 break;
1714 case LOAD:
1715 case LOADLR:
1716 load_alloc(current,i);
1717 break;
1718 case STORE:
1719 case STORELR:
1720 store_alloc(current,i);
1721 break;
1722 case ALU:
1723 alu_alloc(current,i);
1724 break;
1725 case SHIFT:
1726 shift_alloc(current,i);
1727 break;
1728 case MULTDIV:
1729 multdiv_alloc(current,i);
1730 break;
1731 case SHIFTIMM:
1732 shiftimm_alloc(current,i);
1733 break;
1734 case MOV:
1735 mov_alloc(current,i);
1736 break;
1737 case COP0:
1738 cop0_alloc(current,i);
1739 break;
1740 case COP1:
b9b61529 1741 case COP2:
57871462 1742 cop1_alloc(current,i);
1743 break;
1744 case C1LS:
1745 c1ls_alloc(current,i);
1746 break;
b9b61529 1747 case C2LS:
1748 c2ls_alloc(current,i);
1749 break;
57871462 1750 case FCONV:
1751 fconv_alloc(current,i);
1752 break;
1753 case FLOAT:
1754 float_alloc(current,i);
1755 break;
1756 case FCOMP:
1757 fcomp_alloc(current,i);
1758 break;
b9b61529 1759 case C2OP:
1760 c2op_alloc(current,i);
1761 break;
57871462 1762 }
1763}
1764
1765// Special case where a branch and delay slot span two pages in virtual memory
1766static void pagespan_alloc(struct regstat *current,int i)
1767{
1768 current->isconst=0;
1769 current->wasconst=0;
1770 regs[i].wasconst=0;
e1190b87 1771 minimum_free_regs[i]=HOST_REGS;
57871462 1772 alloc_all(current,i);
1773 alloc_cc(current,i);
1774 dirty_reg(current,CCREG);
1775 if(opcode[i]==3) // JAL
1776 {
1777 alloc_reg(current,i,31);
1778 dirty_reg(current,31);
1779 }
1780 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1781 {
1782 alloc_reg(current,i,rs1[i]);
5067f341 1783 if (rt1[i]!=0) {
1784 alloc_reg(current,i,rt1[i]);
1785 dirty_reg(current,rt1[i]);
57871462 1786 }
1787 }
1788 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1789 {
1790 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1791 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1792 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1793 {
1794 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1795 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1796 }
1797 }
1798 else
1799 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1800 {
1801 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1802 if(!((current->is32>>rs1[i])&1))
1803 {
1804 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1805 }
1806 }
1807 else
1808 if(opcode[i]==0x11) // BC1
1809 {
1810 alloc_reg(current,i,FSREG);
1811 alloc_reg(current,i,CSREG);
1812 }
1813 //else ...
1814}
1815
e2b5e7aa 1816static void add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
57871462 1817{
1818 stubs[stubcount][0]=type;
1819 stubs[stubcount][1]=addr;
1820 stubs[stubcount][2]=retaddr;
1821 stubs[stubcount][3]=a;
1822 stubs[stubcount][4]=b;
1823 stubs[stubcount][5]=c;
1824 stubs[stubcount][6]=d;
1825 stubs[stubcount][7]=e;
1826 stubcount++;
1827}
1828
1829// Write out a single register
1830void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
1831{
1832 int hr;
1833 for(hr=0;hr<HOST_REGS;hr++) {
1834 if(hr!=EXCLUDE_REG) {
1835 if((regmap[hr]&63)==r) {
1836 if((dirty>>hr)&1) {
1837 if(regmap[hr]<64) {
1838 emit_storereg(r,hr);
57871462 1839 }else{
1840 emit_storereg(r|64,hr);
1841 }
1842 }
1843 }
1844 }
1845 }
1846}
1847
1848int mchecksum()
1849{
1850 //if(!tracedebug) return 0;
1851 int i;
1852 int sum=0;
1853 for(i=0;i<2097152;i++) {
1854 unsigned int temp=sum;
1855 sum<<=1;
1856 sum|=(~temp)>>31;
1857 sum^=((u_int *)rdram)[i];
1858 }
1859 return sum;
1860}
1861int rchecksum()
1862{
1863 int i;
1864 int sum=0;
1865 for(i=0;i<64;i++)
1866 sum^=((u_int *)reg)[i];
1867 return sum;
1868}
57871462 1869void rlist()
1870{
1871 int i;
1872 printf("TRACE: ");
1873 for(i=0;i<32;i++)
1874 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
1875 printf("\n");
57871462 1876}
1877
1878void enabletrace()
1879{
1880 tracedebug=1;
1881}
1882
1883void memdebug(int i)
1884{
1885 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
1886 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
1887 //rlist();
1888 //if(tracedebug) {
1889 //if(Count>=-2084597794) {
1890 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
1891 //if(0) {
1892 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
1893 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
1894 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
1895 rlist();
1896 #ifdef __i386__
1897 printf("TRACE: %x\n",(&i)[-1]);
1898 #endif
1899 #ifdef __arm__
1900 int j;
1901 printf("TRACE: %x \n",(&j)[10]);
1902 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
1903 #endif
1904 //fflush(stdout);
1905 }
1906 //printf("TRACE: %x\n",(&i)[-1]);
1907}
1908
57871462 1909void alu_assemble(int i,struct regstat *i_regs)
1910{
1911 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1912 if(rt1[i]) {
1913 signed char s1,s2,t;
1914 t=get_reg(i_regs->regmap,rt1[i]);
1915 if(t>=0) {
1916 s1=get_reg(i_regs->regmap,rs1[i]);
1917 s2=get_reg(i_regs->regmap,rs2[i]);
1918 if(rs1[i]&&rs2[i]) {
1919 assert(s1>=0);
1920 assert(s2>=0);
1921 if(opcode2[i]&2) emit_sub(s1,s2,t);
1922 else emit_add(s1,s2,t);
1923 }
1924 else if(rs1[i]) {
1925 if(s1>=0) emit_mov(s1,t);
1926 else emit_loadreg(rs1[i],t);
1927 }
1928 else if(rs2[i]) {
1929 if(s2>=0) {
1930 if(opcode2[i]&2) emit_neg(s2,t);
1931 else emit_mov(s2,t);
1932 }
1933 else {
1934 emit_loadreg(rs2[i],t);
1935 if(opcode2[i]&2) emit_neg(t,t);
1936 }
1937 }
1938 else emit_zeroreg(t);
1939 }
1940 }
1941 }
1942 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1943 if(rt1[i]) {
1944 signed char s1l,s2l,s1h,s2h,tl,th;
1945 tl=get_reg(i_regs->regmap,rt1[i]);
1946 th=get_reg(i_regs->regmap,rt1[i]|64);
1947 if(tl>=0) {
1948 s1l=get_reg(i_regs->regmap,rs1[i]);
1949 s2l=get_reg(i_regs->regmap,rs2[i]);
1950 s1h=get_reg(i_regs->regmap,rs1[i]|64);
1951 s2h=get_reg(i_regs->regmap,rs2[i]|64);
1952 if(rs1[i]&&rs2[i]) {
1953 assert(s1l>=0);
1954 assert(s2l>=0);
1955 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
1956 else emit_adds(s1l,s2l,tl);
1957 if(th>=0) {
1958 #ifdef INVERTED_CARRY
1959 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
1960 #else
1961 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
1962 #endif
1963 else emit_add(s1h,s2h,th);
1964 }
1965 }
1966 else if(rs1[i]) {
1967 if(s1l>=0) emit_mov(s1l,tl);
1968 else emit_loadreg(rs1[i],tl);
1969 if(th>=0) {
1970 if(s1h>=0) emit_mov(s1h,th);
1971 else emit_loadreg(rs1[i]|64,th);
1972 }
1973 }
1974 else if(rs2[i]) {
1975 if(s2l>=0) {
1976 if(opcode2[i]&2) emit_negs(s2l,tl);
1977 else emit_mov(s2l,tl);
1978 }
1979 else {
1980 emit_loadreg(rs2[i],tl);
1981 if(opcode2[i]&2) emit_negs(tl,tl);
1982 }
1983 if(th>=0) {
1984 #ifdef INVERTED_CARRY
1985 if(s2h>=0) emit_mov(s2h,th);
1986 else emit_loadreg(rs2[i]|64,th);
1987 if(opcode2[i]&2) {
1988 emit_adcimm(-1,th); // x86 has inverted carry flag
1989 emit_not(th,th);
1990 }
1991 #else
1992 if(opcode2[i]&2) {
1993 if(s2h>=0) emit_rscimm(s2h,0,th);
1994 else {
1995 emit_loadreg(rs2[i]|64,th);
1996 emit_rscimm(th,0,th);
1997 }
1998 }else{
1999 if(s2h>=0) emit_mov(s2h,th);
2000 else emit_loadreg(rs2[i]|64,th);
2001 }
2002 #endif
2003 }
2004 }
2005 else {
2006 emit_zeroreg(tl);
2007 if(th>=0) emit_zeroreg(th);
2008 }
2009 }
2010 }
2011 }
2012 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2013 if(rt1[i]) {
2014 signed char s1l,s1h,s2l,s2h,t;
2015 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2016 {
2017 t=get_reg(i_regs->regmap,rt1[i]);
2018 //assert(t>=0);
2019 if(t>=0) {
2020 s1l=get_reg(i_regs->regmap,rs1[i]);
2021 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2022 s2l=get_reg(i_regs->regmap,rs2[i]);
2023 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2024 if(rs2[i]==0) // rx<r0
2025 {
2026 assert(s1h>=0);
2027 if(opcode2[i]==0x2a) // SLT
2028 emit_shrimm(s1h,31,t);
2029 else // SLTU (unsigned can not be less than zero)
2030 emit_zeroreg(t);
2031 }
2032 else if(rs1[i]==0) // r0<rx
2033 {
2034 assert(s2h>=0);
2035 if(opcode2[i]==0x2a) // SLT
2036 emit_set_gz64_32(s2h,s2l,t);
2037 else // SLTU (set if not zero)
2038 emit_set_nz64_32(s2h,s2l,t);
2039 }
2040 else {
2041 assert(s1l>=0);assert(s1h>=0);
2042 assert(s2l>=0);assert(s2h>=0);
2043 if(opcode2[i]==0x2a) // SLT
2044 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2045 else // SLTU
2046 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2047 }
2048 }
2049 } else {
2050 t=get_reg(i_regs->regmap,rt1[i]);
2051 //assert(t>=0);
2052 if(t>=0) {
2053 s1l=get_reg(i_regs->regmap,rs1[i]);
2054 s2l=get_reg(i_regs->regmap,rs2[i]);
2055 if(rs2[i]==0) // rx<r0
2056 {
2057 assert(s1l>=0);
2058 if(opcode2[i]==0x2a) // SLT
2059 emit_shrimm(s1l,31,t);
2060 else // SLTU (unsigned can not be less than zero)
2061 emit_zeroreg(t);
2062 }
2063 else if(rs1[i]==0) // r0<rx
2064 {
2065 assert(s2l>=0);
2066 if(opcode2[i]==0x2a) // SLT
2067 emit_set_gz32(s2l,t);
2068 else // SLTU (set if not zero)
2069 emit_set_nz32(s2l,t);
2070 }
2071 else{
2072 assert(s1l>=0);assert(s2l>=0);
2073 if(opcode2[i]==0x2a) // SLT
2074 emit_set_if_less32(s1l,s2l,t);
2075 else // SLTU
2076 emit_set_if_carry32(s1l,s2l,t);
2077 }
2078 }
2079 }
2080 }
2081 }
2082 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2083 if(rt1[i]) {
2084 signed char s1l,s1h,s2l,s2h,th,tl;
2085 tl=get_reg(i_regs->regmap,rt1[i]);
2086 th=get_reg(i_regs->regmap,rt1[i]|64);
2087 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2088 {
2089 assert(tl>=0);
2090 if(tl>=0) {
2091 s1l=get_reg(i_regs->regmap,rs1[i]);
2092 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2093 s2l=get_reg(i_regs->regmap,rs2[i]);
2094 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2095 if(rs1[i]&&rs2[i]) {
2096 assert(s1l>=0);assert(s1h>=0);
2097 assert(s2l>=0);assert(s2h>=0);
2098 if(opcode2[i]==0x24) { // AND
2099 emit_and(s1l,s2l,tl);
2100 emit_and(s1h,s2h,th);
2101 } else
2102 if(opcode2[i]==0x25) { // OR
2103 emit_or(s1l,s2l,tl);
2104 emit_or(s1h,s2h,th);
2105 } else
2106 if(opcode2[i]==0x26) { // XOR
2107 emit_xor(s1l,s2l,tl);
2108 emit_xor(s1h,s2h,th);
2109 } else
2110 if(opcode2[i]==0x27) { // NOR
2111 emit_or(s1l,s2l,tl);
2112 emit_or(s1h,s2h,th);
2113 emit_not(tl,tl);
2114 emit_not(th,th);
2115 }
2116 }
2117 else
2118 {
2119 if(opcode2[i]==0x24) { // AND
2120 emit_zeroreg(tl);
2121 emit_zeroreg(th);
2122 } else
2123 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2124 if(rs1[i]){
2125 if(s1l>=0) emit_mov(s1l,tl);
2126 else emit_loadreg(rs1[i],tl);
2127 if(s1h>=0) emit_mov(s1h,th);
2128 else emit_loadreg(rs1[i]|64,th);
2129 }
2130 else
2131 if(rs2[i]){
2132 if(s2l>=0) emit_mov(s2l,tl);
2133 else emit_loadreg(rs2[i],tl);
2134 if(s2h>=0) emit_mov(s2h,th);
2135 else emit_loadreg(rs2[i]|64,th);
2136 }
2137 else{
2138 emit_zeroreg(tl);
2139 emit_zeroreg(th);
2140 }
2141 } else
2142 if(opcode2[i]==0x27) { // NOR
2143 if(rs1[i]){
2144 if(s1l>=0) emit_not(s1l,tl);
2145 else{
2146 emit_loadreg(rs1[i],tl);
2147 emit_not(tl,tl);
2148 }
2149 if(s1h>=0) emit_not(s1h,th);
2150 else{
2151 emit_loadreg(rs1[i]|64,th);
2152 emit_not(th,th);
2153 }
2154 }
2155 else
2156 if(rs2[i]){
2157 if(s2l>=0) emit_not(s2l,tl);
2158 else{
2159 emit_loadreg(rs2[i],tl);
2160 emit_not(tl,tl);
2161 }
2162 if(s2h>=0) emit_not(s2h,th);
2163 else{
2164 emit_loadreg(rs2[i]|64,th);
2165 emit_not(th,th);
2166 }
2167 }
2168 else {
2169 emit_movimm(-1,tl);
2170 emit_movimm(-1,th);
2171 }
2172 }
2173 }
2174 }
2175 }
2176 else
2177 {
2178 // 32 bit
2179 if(tl>=0) {
2180 s1l=get_reg(i_regs->regmap,rs1[i]);
2181 s2l=get_reg(i_regs->regmap,rs2[i]);
2182 if(rs1[i]&&rs2[i]) {
2183 assert(s1l>=0);
2184 assert(s2l>=0);
2185 if(opcode2[i]==0x24) { // AND
2186 emit_and(s1l,s2l,tl);
2187 } else
2188 if(opcode2[i]==0x25) { // OR
2189 emit_or(s1l,s2l,tl);
2190 } else
2191 if(opcode2[i]==0x26) { // XOR
2192 emit_xor(s1l,s2l,tl);
2193 } else
2194 if(opcode2[i]==0x27) { // NOR
2195 emit_or(s1l,s2l,tl);
2196 emit_not(tl,tl);
2197 }
2198 }
2199 else
2200 {
2201 if(opcode2[i]==0x24) { // AND
2202 emit_zeroreg(tl);
2203 } else
2204 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2205 if(rs1[i]){
2206 if(s1l>=0) emit_mov(s1l,tl);
2207 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2208 }
2209 else
2210 if(rs2[i]){
2211 if(s2l>=0) emit_mov(s2l,tl);
2212 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2213 }
2214 else emit_zeroreg(tl);
2215 } else
2216 if(opcode2[i]==0x27) { // NOR
2217 if(rs1[i]){
2218 if(s1l>=0) emit_not(s1l,tl);
2219 else {
2220 emit_loadreg(rs1[i],tl);
2221 emit_not(tl,tl);
2222 }
2223 }
2224 else
2225 if(rs2[i]){
2226 if(s2l>=0) emit_not(s2l,tl);
2227 else {
2228 emit_loadreg(rs2[i],tl);
2229 emit_not(tl,tl);
2230 }
2231 }
2232 else emit_movimm(-1,tl);
2233 }
2234 }
2235 }
2236 }
2237 }
2238 }
2239}
2240
2241void imm16_assemble(int i,struct regstat *i_regs)
2242{
2243 if (opcode[i]==0x0f) { // LUI
2244 if(rt1[i]) {
2245 signed char t;
2246 t=get_reg(i_regs->regmap,rt1[i]);
2247 //assert(t>=0);
2248 if(t>=0) {
2249 if(!((i_regs->isconst>>t)&1))
2250 emit_movimm(imm[i]<<16,t);
2251 }
2252 }
2253 }
2254 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2255 if(rt1[i]) {
2256 signed char s,t;
2257 t=get_reg(i_regs->regmap,rt1[i]);
2258 s=get_reg(i_regs->regmap,rs1[i]);
2259 if(rs1[i]) {
2260 //assert(t>=0);
2261 //assert(s>=0);
2262 if(t>=0) {
2263 if(!((i_regs->isconst>>t)&1)) {
2264 if(s<0) {
2265 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2266 emit_addimm(t,imm[i],t);
2267 }else{
2268 if(!((i_regs->wasconst>>s)&1))
2269 emit_addimm(s,imm[i],t);
2270 else
2271 emit_movimm(constmap[i][s]+imm[i],t);
2272 }
2273 }
2274 }
2275 } else {
2276 if(t>=0) {
2277 if(!((i_regs->isconst>>t)&1))
2278 emit_movimm(imm[i],t);
2279 }
2280 }
2281 }
2282 }
2283 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2284 if(rt1[i]) {
2285 signed char sh,sl,th,tl;
2286 th=get_reg(i_regs->regmap,rt1[i]|64);
2287 tl=get_reg(i_regs->regmap,rt1[i]);
2288 sh=get_reg(i_regs->regmap,rs1[i]|64);
2289 sl=get_reg(i_regs->regmap,rs1[i]);
2290 if(tl>=0) {
2291 if(rs1[i]) {
2292 assert(sh>=0);
2293 assert(sl>=0);
2294 if(th>=0) {
2295 emit_addimm64_32(sh,sl,imm[i],th,tl);
2296 }
2297 else {
2298 emit_addimm(sl,imm[i],tl);
2299 }
2300 } else {
2301 emit_movimm(imm[i],tl);
2302 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2303 }
2304 }
2305 }
2306 }
2307 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2308 if(rt1[i]) {
2309 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2310 signed char sh,sl,t;
2311 t=get_reg(i_regs->regmap,rt1[i]);
2312 sh=get_reg(i_regs->regmap,rs1[i]|64);
2313 sl=get_reg(i_regs->regmap,rs1[i]);
2314 //assert(t>=0);
2315 if(t>=0) {
2316 if(rs1[i]>0) {
2317 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2318 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2319 if(opcode[i]==0x0a) { // SLTI
2320 if(sl<0) {
2321 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2322 emit_slti32(t,imm[i],t);
2323 }else{
2324 emit_slti32(sl,imm[i],t);
2325 }
2326 }
2327 else { // SLTIU
2328 if(sl<0) {
2329 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2330 emit_sltiu32(t,imm[i],t);
2331 }else{
2332 emit_sltiu32(sl,imm[i],t);
2333 }
2334 }
2335 }else{ // 64-bit
2336 assert(sl>=0);
2337 if(opcode[i]==0x0a) // SLTI
2338 emit_slti64_32(sh,sl,imm[i],t);
2339 else // SLTIU
2340 emit_sltiu64_32(sh,sl,imm[i],t);
2341 }
2342 }else{
2343 // SLTI(U) with r0 is just stupid,
2344 // nonetheless examples can be found
2345 if(opcode[i]==0x0a) // SLTI
2346 if(0<imm[i]) emit_movimm(1,t);
2347 else emit_zeroreg(t);
2348 else // SLTIU
2349 {
2350 if(imm[i]) emit_movimm(1,t);
2351 else emit_zeroreg(t);
2352 }
2353 }
2354 }
2355 }
2356 }
2357 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2358 if(rt1[i]) {
2359 signed char sh,sl,th,tl;
2360 th=get_reg(i_regs->regmap,rt1[i]|64);
2361 tl=get_reg(i_regs->regmap,rt1[i]);
2362 sh=get_reg(i_regs->regmap,rs1[i]|64);
2363 sl=get_reg(i_regs->regmap,rs1[i]);
2364 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2365 if(opcode[i]==0x0c) //ANDI
2366 {
2367 if(rs1[i]) {
2368 if(sl<0) {
2369 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2370 emit_andimm(tl,imm[i],tl);
2371 }else{
2372 if(!((i_regs->wasconst>>sl)&1))
2373 emit_andimm(sl,imm[i],tl);
2374 else
2375 emit_movimm(constmap[i][sl]&imm[i],tl);
2376 }
2377 }
2378 else
2379 emit_zeroreg(tl);
2380 if(th>=0) emit_zeroreg(th);
2381 }
2382 else
2383 {
2384 if(rs1[i]) {
2385 if(sl<0) {
2386 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2387 }
2388 if(th>=0) {
2389 if(sh<0) {
2390 emit_loadreg(rs1[i]|64,th);
2391 }else{
2392 emit_mov(sh,th);
2393 }
2394 }
581335b0 2395 if(opcode[i]==0x0d) { // ORI
2396 if(sl<0) {
2397 emit_orimm(tl,imm[i],tl);
2398 }else{
2399 if(!((i_regs->wasconst>>sl)&1))
2400 emit_orimm(sl,imm[i],tl);
2401 else
2402 emit_movimm(constmap[i][sl]|imm[i],tl);
2403 }
57871462 2404 }
581335b0 2405 if(opcode[i]==0x0e) { // XORI
2406 if(sl<0) {
2407 emit_xorimm(tl,imm[i],tl);
2408 }else{
2409 if(!((i_regs->wasconst>>sl)&1))
2410 emit_xorimm(sl,imm[i],tl);
2411 else
2412 emit_movimm(constmap[i][sl]^imm[i],tl);
2413 }
57871462 2414 }
2415 }
2416 else {
2417 emit_movimm(imm[i],tl);
2418 if(th>=0) emit_zeroreg(th);
2419 }
2420 }
2421 }
2422 }
2423 }
2424}
2425
2426void shiftimm_assemble(int i,struct regstat *i_regs)
2427{
2428 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2429 {
2430 if(rt1[i]) {
2431 signed char s,t;
2432 t=get_reg(i_regs->regmap,rt1[i]);
2433 s=get_reg(i_regs->regmap,rs1[i]);
2434 //assert(t>=0);
dc49e339 2435 if(t>=0&&!((i_regs->isconst>>t)&1)){
57871462 2436 if(rs1[i]==0)
2437 {
2438 emit_zeroreg(t);
2439 }
2440 else
2441 {
2442 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2443 if(imm[i]) {
2444 if(opcode2[i]==0) // SLL
2445 {
2446 emit_shlimm(s<0?t:s,imm[i],t);
2447 }
2448 if(opcode2[i]==2) // SRL
2449 {
2450 emit_shrimm(s<0?t:s,imm[i],t);
2451 }
2452 if(opcode2[i]==3) // SRA
2453 {
2454 emit_sarimm(s<0?t:s,imm[i],t);
2455 }
2456 }else{
2457 // Shift by zero
2458 if(s>=0 && s!=t) emit_mov(s,t);
2459 }
2460 }
2461 }
2462 //emit_storereg(rt1[i],t); //DEBUG
2463 }
2464 }
2465 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2466 {
2467 if(rt1[i]) {
2468 signed char sh,sl,th,tl;
2469 th=get_reg(i_regs->regmap,rt1[i]|64);
2470 tl=get_reg(i_regs->regmap,rt1[i]);
2471 sh=get_reg(i_regs->regmap,rs1[i]|64);
2472 sl=get_reg(i_regs->regmap,rs1[i]);
2473 if(tl>=0) {
2474 if(rs1[i]==0)
2475 {
2476 emit_zeroreg(tl);
2477 if(th>=0) emit_zeroreg(th);
2478 }
2479 else
2480 {
2481 assert(sl>=0);
2482 assert(sh>=0);
2483 if(imm[i]) {
2484 if(opcode2[i]==0x38) // DSLL
2485 {
2486 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2487 emit_shlimm(sl,imm[i],tl);
2488 }
2489 if(opcode2[i]==0x3a) // DSRL
2490 {
2491 emit_shrdimm(sl,sh,imm[i],tl);
2492 if(th>=0) emit_shrimm(sh,imm[i],th);
2493 }
2494 if(opcode2[i]==0x3b) // DSRA
2495 {
2496 emit_shrdimm(sl,sh,imm[i],tl);
2497 if(th>=0) emit_sarimm(sh,imm[i],th);
2498 }
2499 }else{
2500 // Shift by zero
2501 if(sl!=tl) emit_mov(sl,tl);
2502 if(th>=0&&sh!=th) emit_mov(sh,th);
2503 }
2504 }
2505 }
2506 }
2507 }
2508 if(opcode2[i]==0x3c) // DSLL32
2509 {
2510 if(rt1[i]) {
2511 signed char sl,tl,th;
2512 tl=get_reg(i_regs->regmap,rt1[i]);
2513 th=get_reg(i_regs->regmap,rt1[i]|64);
2514 sl=get_reg(i_regs->regmap,rs1[i]);
2515 if(th>=0||tl>=0){
2516 assert(tl>=0);
2517 assert(th>=0);
2518 assert(sl>=0);
2519 emit_mov(sl,th);
2520 emit_zeroreg(tl);
2521 if(imm[i]>32)
2522 {
2523 emit_shlimm(th,imm[i]&31,th);
2524 }
2525 }
2526 }
2527 }
2528 if(opcode2[i]==0x3e) // DSRL32
2529 {
2530 if(rt1[i]) {
2531 signed char sh,tl,th;
2532 tl=get_reg(i_regs->regmap,rt1[i]);
2533 th=get_reg(i_regs->regmap,rt1[i]|64);
2534 sh=get_reg(i_regs->regmap,rs1[i]|64);
2535 if(tl>=0){
2536 assert(sh>=0);
2537 emit_mov(sh,tl);
2538 if(th>=0) emit_zeroreg(th);
2539 if(imm[i]>32)
2540 {
2541 emit_shrimm(tl,imm[i]&31,tl);
2542 }
2543 }
2544 }
2545 }
2546 if(opcode2[i]==0x3f) // DSRA32
2547 {
2548 if(rt1[i]) {
2549 signed char sh,tl;
2550 tl=get_reg(i_regs->regmap,rt1[i]);
2551 sh=get_reg(i_regs->regmap,rs1[i]|64);
2552 if(tl>=0){
2553 assert(sh>=0);
2554 emit_mov(sh,tl);
2555 if(imm[i]>32)
2556 {
2557 emit_sarimm(tl,imm[i]&31,tl);
2558 }
2559 }
2560 }
2561 }
2562}
2563
2564#ifndef shift_assemble
2565void shift_assemble(int i,struct regstat *i_regs)
2566{
2567 printf("Need shift_assemble for this architecture.\n");
2568 exit(1);
2569}
2570#endif
2571
2572void load_assemble(int i,struct regstat *i_regs)
2573{
2574 int s,th,tl,addr,map=-1;
2575 int offset;
2576 int jaddr=0;
5bf843dc 2577 int memtarget=0,c=0;
b1570849 2578 int fastload_reg_override=0;
57871462 2579 u_int hr,reglist=0;
2580 th=get_reg(i_regs->regmap,rt1[i]|64);
2581 tl=get_reg(i_regs->regmap,rt1[i]);
2582 s=get_reg(i_regs->regmap,rs1[i]);
2583 offset=imm[i];
2584 for(hr=0;hr<HOST_REGS;hr++) {
2585 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2586 }
2587 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2588 if(s>=0) {
2589 c=(i_regs->wasconst>>s)&1;
af4ee1fe 2590 if (c) {
2591 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
af4ee1fe 2592 }
57871462 2593 }
57871462 2594 //printf("load_assemble: c=%d\n",c);
2595 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2596 // FIXME: Even if the load is a NOP, we should check for pagefaults...
581335b0 2597 if((tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80))
f18c0f46 2598 ||rt1[i]==0) {
5bf843dc 2599 // could be FIFO, must perform the read
f18c0f46 2600 // ||dummy read
5bf843dc 2601 assem_debug("(forced read)\n");
2602 tl=get_reg(i_regs->regmap,-1);
2603 assert(tl>=0);
5bf843dc 2604 }
2605 if(offset||s<0||c) addr=tl;
2606 else addr=s;
535d208a 2607 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2608 if(tl>=0) {
2609 //printf("load_assemble: c=%d\n",c);
2610 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2611 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2612 reglist&=~(1<<tl);
2613 if(th>=0) reglist&=~(1<<th);
1edfcc68 2614 if(!c) {
2615 #ifdef RAM_OFFSET
2616 map=get_reg(i_regs->regmap,ROREG);
2617 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2618 #endif
2619 #ifdef R29_HACK
2620 // Strmnnrmn's speed hack
2621 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2622 #endif
2623 {
2624 jaddr=emit_fastpath_cmp_jump(i,addr,&fastload_reg_override);
535d208a 2625 }
1edfcc68 2626 }
2627 else if(ram_offset&&memtarget) {
2628 emit_addimm(addr,ram_offset,HOST_TEMPREG);
2629 fastload_reg_override=HOST_TEMPREG;
535d208a 2630 }
2631 int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2632 if (opcode[i]==0x20) { // LB
2633 if(!c||memtarget) {
2634 if(!dummy) {
57871462 2635 #ifdef HOST_IMM_ADDR32
2636 if(c)
2637 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2638 else
2639 #endif
2640 {
2641 //emit_xorimm(addr,3,tl);
57871462 2642 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
535d208a 2643 int x=0,a=tl;
2002a1db 2644#ifdef BIG_ENDIAN_MIPS
57871462 2645 if(!c) emit_xorimm(addr,3,tl);
2646 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2647#else
535d208a 2648 if(!c) a=addr;
dadf55f2 2649#endif
b1570849 2650 if(fastload_reg_override) a=fastload_reg_override;
2651
535d208a 2652 emit_movsbl_indexed_tlb(x,a,map,tl);
57871462 2653 }
57871462 2654 }
535d208a 2655 if(jaddr)
2656 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2657 }
535d208a 2658 else
2659 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2660 }
2661 if (opcode[i]==0x21) { // LH
2662 if(!c||memtarget) {
2663 if(!dummy) {
57871462 2664 #ifdef HOST_IMM_ADDR32
2665 if(c)
2666 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2667 else
2668 #endif
2669 {
535d208a 2670 int x=0,a=tl;
2002a1db 2671#ifdef BIG_ENDIAN_MIPS
57871462 2672 if(!c) emit_xorimm(addr,2,tl);
2673 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2674#else
535d208a 2675 if(!c) a=addr;
dadf55f2 2676#endif
b1570849 2677 if(fastload_reg_override) a=fastload_reg_override;
57871462 2678 //#ifdef
2679 //emit_movswl_indexed_tlb(x,tl,map,tl);
2680 //else
2681 if(map>=0) {
535d208a 2682 emit_movswl_indexed(x,a,tl);
2683 }else{
a327ad27 2684 #if 1 //def RAM_OFFSET
535d208a 2685 emit_movswl_indexed(x,a,tl);
2686 #else
2687 emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2688 #endif
2689 }
57871462 2690 }
57871462 2691 }
535d208a 2692 if(jaddr)
2693 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2694 }
535d208a 2695 else
2696 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2697 }
2698 if (opcode[i]==0x23) { // LW
2699 if(!c||memtarget) {
2700 if(!dummy) {
dadf55f2 2701 int a=addr;
b1570849 2702 if(fastload_reg_override) a=fastload_reg_override;
57871462 2703 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2704 #ifdef HOST_IMM_ADDR32
2705 if(c)
2706 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2707 else
2708 #endif
dadf55f2 2709 emit_readword_indexed_tlb(0,a,map,tl);
57871462 2710 }
535d208a 2711 if(jaddr)
2712 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2713 }
535d208a 2714 else
2715 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2716 }
2717 if (opcode[i]==0x24) { // LBU
2718 if(!c||memtarget) {
2719 if(!dummy) {
57871462 2720 #ifdef HOST_IMM_ADDR32
2721 if(c)
2722 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2723 else
2724 #endif
2725 {
2726 //emit_xorimm(addr,3,tl);
57871462 2727 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
535d208a 2728 int x=0,a=tl;
2002a1db 2729#ifdef BIG_ENDIAN_MIPS
57871462 2730 if(!c) emit_xorimm(addr,3,tl);
2731 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2732#else
535d208a 2733 if(!c) a=addr;
dadf55f2 2734#endif
b1570849 2735 if(fastload_reg_override) a=fastload_reg_override;
2736
535d208a 2737 emit_movzbl_indexed_tlb(x,a,map,tl);
57871462 2738 }
57871462 2739 }
535d208a 2740 if(jaddr)
2741 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2742 }
535d208a 2743 else
2744 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2745 }
2746 if (opcode[i]==0x25) { // LHU
2747 if(!c||memtarget) {
2748 if(!dummy) {
57871462 2749 #ifdef HOST_IMM_ADDR32
2750 if(c)
2751 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2752 else
2753 #endif
2754 {
535d208a 2755 int x=0,a=tl;
2002a1db 2756#ifdef BIG_ENDIAN_MIPS
57871462 2757 if(!c) emit_xorimm(addr,2,tl);
2758 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2759#else
535d208a 2760 if(!c) a=addr;
dadf55f2 2761#endif
b1570849 2762 if(fastload_reg_override) a=fastload_reg_override;
57871462 2763 //#ifdef
2764 //emit_movzwl_indexed_tlb(x,tl,map,tl);
2765 //#else
2766 if(map>=0) {
535d208a 2767 emit_movzwl_indexed(x,a,tl);
2768 }else{
a327ad27 2769 #if 1 //def RAM_OFFSET
535d208a 2770 emit_movzwl_indexed(x,a,tl);
2771 #else
2772 emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
2773 #endif
2774 }
57871462 2775 }
2776 }
535d208a 2777 if(jaddr)
2778 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2779 }
535d208a 2780 else
2781 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2782 }
2783 if (opcode[i]==0x27) { // LWU
2784 assert(th>=0);
2785 if(!c||memtarget) {
2786 if(!dummy) {
dadf55f2 2787 int a=addr;
b1570849 2788 if(fastload_reg_override) a=fastload_reg_override;
57871462 2789 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2790 #ifdef HOST_IMM_ADDR32
2791 if(c)
2792 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2793 else
2794 #endif
dadf55f2 2795 emit_readword_indexed_tlb(0,a,map,tl);
57871462 2796 }
535d208a 2797 if(jaddr)
2798 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2799 }
2800 else {
2801 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
57871462 2802 }
535d208a 2803 emit_zeroreg(th);
2804 }
2805 if (opcode[i]==0x37) { // LD
2806 if(!c||memtarget) {
2807 if(!dummy) {
dadf55f2 2808 int a=addr;
b1570849 2809 if(fastload_reg_override) a=fastload_reg_override;
57871462 2810 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
2811 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
2812 #ifdef HOST_IMM_ADDR32
2813 if(c)
2814 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
2815 else
2816 #endif
dadf55f2 2817 emit_readdword_indexed_tlb(0,a,map,th,tl);
57871462 2818 }
535d208a 2819 if(jaddr)
2820 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2821 }
535d208a 2822 else
2823 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
57871462 2824 }
535d208a 2825 }
2826 //emit_storereg(rt1[i],tl); // DEBUG
57871462 2827 //if(opcode[i]==0x23)
2828 //if(opcode[i]==0x24)
2829 //if(opcode[i]==0x23||opcode[i]==0x24)
2830 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
2831 {
2832 //emit_pusha();
2833 save_regs(0x100f);
2834 emit_readword((int)&last_count,ECX);
2835 #ifdef __i386__
2836 if(get_reg(i_regs->regmap,CCREG)<0)
2837 emit_loadreg(CCREG,HOST_CCREG);
2838 emit_add(HOST_CCREG,ECX,HOST_CCREG);
2839 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
2840 emit_writeword(HOST_CCREG,(int)&Count);
2841 #endif
2842 #ifdef __arm__
2843 if(get_reg(i_regs->regmap,CCREG)<0)
2844 emit_loadreg(CCREG,0);
2845 else
2846 emit_mov(HOST_CCREG,0);
2847 emit_add(0,ECX,0);
2848 emit_addimm(0,2*ccadj[i],0);
2849 emit_writeword(0,(int)&Count);
2850 #endif
2851 emit_call((int)memdebug);
2852 //emit_popa();
2853 restore_regs(0x100f);
581335b0 2854 }*/
57871462 2855}
2856
2857#ifndef loadlr_assemble
2858void loadlr_assemble(int i,struct regstat *i_regs)
2859{
2860 printf("Need loadlr_assemble for this architecture.\n");
2861 exit(1);
2862}
2863#endif
2864
2865void store_assemble(int i,struct regstat *i_regs)
2866{
2867 int s,th,tl,map=-1;
2868 int addr,temp;
2869 int offset;
581335b0 2870 int jaddr=0,type;
666a299d 2871 int memtarget=0,c=0;
57871462 2872 int agr=AGEN1+(i&1);
b1570849 2873 int faststore_reg_override=0;
57871462 2874 u_int hr,reglist=0;
2875 th=get_reg(i_regs->regmap,rs2[i]|64);
2876 tl=get_reg(i_regs->regmap,rs2[i]);
2877 s=get_reg(i_regs->regmap,rs1[i]);
2878 temp=get_reg(i_regs->regmap,agr);
2879 if(temp<0) temp=get_reg(i_regs->regmap,-1);
2880 offset=imm[i];
2881 if(s>=0) {
2882 c=(i_regs->wasconst>>s)&1;
af4ee1fe 2883 if(c) {
2884 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
af4ee1fe 2885 }
57871462 2886 }
2887 assert(tl>=0);
2888 assert(temp>=0);
2889 for(hr=0;hr<HOST_REGS;hr++) {
2890 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2891 }
2892 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2893 if(offset||s<0||c) addr=temp;
2894 else addr=s;
1edfcc68 2895 if(!c) {
2896 jaddr=emit_fastpath_cmp_jump(i,addr,&faststore_reg_override);
2897 }
2898 else if(ram_offset&&memtarget) {
2899 emit_addimm(addr,ram_offset,HOST_TEMPREG);
2900 faststore_reg_override=HOST_TEMPREG;
57871462 2901 }
2902
2903 if (opcode[i]==0x28) { // SB
2904 if(!c||memtarget) {
97a238a6 2905 int x=0,a=temp;
2002a1db 2906#ifdef BIG_ENDIAN_MIPS
57871462 2907 if(!c) emit_xorimm(addr,3,temp);
2908 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2909#else
97a238a6 2910 if(!c) a=addr;
dadf55f2 2911#endif
b1570849 2912 if(faststore_reg_override) a=faststore_reg_override;
57871462 2913 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
97a238a6 2914 emit_writebyte_indexed_tlb(tl,x,a,map,a);
57871462 2915 }
2916 type=STOREB_STUB;
2917 }
2918 if (opcode[i]==0x29) { // SH
2919 if(!c||memtarget) {
97a238a6 2920 int x=0,a=temp;
2002a1db 2921#ifdef BIG_ENDIAN_MIPS
57871462 2922 if(!c) emit_xorimm(addr,2,temp);
2923 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2924#else
97a238a6 2925 if(!c) a=addr;
dadf55f2 2926#endif
b1570849 2927 if(faststore_reg_override) a=faststore_reg_override;
57871462 2928 //#ifdef
2929 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
2930 //#else
2931 if(map>=0) {
97a238a6 2932 emit_writehword_indexed(tl,x,a);
57871462 2933 }else
a327ad27 2934 //emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
2935 emit_writehword_indexed(tl,x,a);
57871462 2936 }
2937 type=STOREH_STUB;
2938 }
2939 if (opcode[i]==0x2B) { // SW
dadf55f2 2940 if(!c||memtarget) {
2941 int a=addr;
b1570849 2942 if(faststore_reg_override) a=faststore_reg_override;
57871462 2943 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
dadf55f2 2944 emit_writeword_indexed_tlb(tl,0,a,map,temp);
2945 }
57871462 2946 type=STOREW_STUB;
2947 }
2948 if (opcode[i]==0x3F) { // SD
2949 if(!c||memtarget) {
dadf55f2 2950 int a=addr;
b1570849 2951 if(faststore_reg_override) a=faststore_reg_override;
57871462 2952 if(rs2[i]) {
2953 assert(th>=0);
2954 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
2955 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
dadf55f2 2956 emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
57871462 2957 }else{
2958 // Store zero
2959 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
2960 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
dadf55f2 2961 emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
57871462 2962 }
2963 }
2964 type=STORED_STUB;
2965 }
b96d3df7 2966 if(jaddr) {
2967 // PCSX store handlers don't check invcode again
2968 reglist|=1<<addr;
2969 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2970 jaddr=0;
2971 }
1edfcc68 2972 if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
57871462 2973 if(!c||memtarget) {
2974 #ifdef DESTRUCTIVE_SHIFT
2975 // The x86 shift operation is 'destructive'; it overwrites the
2976 // source register, so we need to make a copy first and use that.
2977 addr=temp;
2978 #endif
2979 #if defined(HOST_IMM8)
2980 int ir=get_reg(i_regs->regmap,INVCP);
2981 assert(ir>=0);
2982 emit_cmpmem_indexedsr12_reg(ir,addr,1);
2983 #else
2984 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
2985 #endif
0bbd1454 2986 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
2987 emit_callne(invalidate_addr_reg[addr]);
2988 #else
581335b0 2989 int jaddr2=(int)out;
57871462 2990 emit_jne(0);
2991 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
0bbd1454 2992 #endif
57871462 2993 }
2994 }
7a518516 2995 u_int addr_val=constmap[i][s]+offset;
3eaa7048 2996 if(jaddr) {
2997 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2998 } else if(c&&!memtarget) {
7a518516 2999 inline_writestub(type,i,addr_val,i_regs->regmap,rs2[i],ccadj[i],reglist);
3000 }
3001 // basic current block modification detection..
3002 // not looking back as that should be in mips cache already
3003 if(c&&start+i*4<addr_val&&addr_val<start+slen*4) {
c43b5311 3004 SysPrintf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4);
7a518516 3005 assert(i_regs->regmap==regs[i].regmap); // not delay slot
3006 if(i_regs->regmap==regs[i].regmap) {
3007 load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
3008 wb_dirtys(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty);
3009 emit_movimm(start+i*4+4,0);
3010 emit_writeword(0,(int)&pcaddr);
3011 emit_jmp((int)do_interrupt);
3012 }
3eaa7048 3013 }
57871462 3014 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3015 //if(opcode[i]==0x2B || opcode[i]==0x28)
3016 //if(opcode[i]==0x2B || opcode[i]==0x29)
3017 //if(opcode[i]==0x2B)
3018 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3019 {
28d74ee8 3020 #ifdef __i386__
3021 emit_pusha();
3022 #endif
3023 #ifdef __arm__
57871462 3024 save_regs(0x100f);
28d74ee8 3025 #endif
57871462 3026 emit_readword((int)&last_count,ECX);
3027 #ifdef __i386__
3028 if(get_reg(i_regs->regmap,CCREG)<0)
3029 emit_loadreg(CCREG,HOST_CCREG);
3030 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3031 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3032 emit_writeword(HOST_CCREG,(int)&Count);
3033 #endif
3034 #ifdef __arm__
3035 if(get_reg(i_regs->regmap,CCREG)<0)
3036 emit_loadreg(CCREG,0);
3037 else
3038 emit_mov(HOST_CCREG,0);
3039 emit_add(0,ECX,0);
3040 emit_addimm(0,2*ccadj[i],0);
3041 emit_writeword(0,(int)&Count);
3042 #endif
3043 emit_call((int)memdebug);
28d74ee8 3044 #ifdef __i386__
3045 emit_popa();
3046 #endif
3047 #ifdef __arm__
57871462 3048 restore_regs(0x100f);
28d74ee8 3049 #endif
581335b0 3050 }*/
57871462 3051}
3052
3053void storelr_assemble(int i,struct regstat *i_regs)
3054{
3055 int s,th,tl;
3056 int temp;
581335b0 3057 int temp2=-1;
57871462 3058 int offset;
581335b0 3059 int jaddr=0;
57871462 3060 int case1,case2,case3;
3061 int done0,done1,done2;
af4ee1fe 3062 int memtarget=0,c=0;
fab5d06d 3063 int agr=AGEN1+(i&1);
57871462 3064 u_int hr,reglist=0;
3065 th=get_reg(i_regs->regmap,rs2[i]|64);
3066 tl=get_reg(i_regs->regmap,rs2[i]);
3067 s=get_reg(i_regs->regmap,rs1[i]);
fab5d06d 3068 temp=get_reg(i_regs->regmap,agr);
3069 if(temp<0) temp=get_reg(i_regs->regmap,-1);
57871462 3070 offset=imm[i];
3071 if(s>=0) {
3072 c=(i_regs->isconst>>s)&1;
af4ee1fe 3073 if(c) {
3074 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
af4ee1fe 3075 }
57871462 3076 }
3077 assert(tl>=0);
3078 for(hr=0;hr<HOST_REGS;hr++) {
3079 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3080 }
535d208a 3081 assert(temp>=0);
1edfcc68 3082 if(!c) {
3083 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3084 if(!offset&&s!=temp) emit_mov(s,temp);
3085 jaddr=(int)out;
3086 emit_jno(0);
3087 }
3088 else
3089 {
3090 if(!memtarget||!rs1[i]) {
535d208a 3091 jaddr=(int)out;
3092 emit_jmp(0);
57871462 3093 }
535d208a 3094 }
1edfcc68 3095 #ifdef RAM_OFFSET
3096 int map=get_reg(i_regs->regmap,ROREG);
3097 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3098 #else
9f51b4b9 3099 if((u_int)rdram!=0x80000000)
1edfcc68 3100 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3101 #endif
535d208a 3102
3103 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3104 temp2=get_reg(i_regs->regmap,FTEMP);
3105 if(!rs2[i]) temp2=th=tl;
3106 }
57871462 3107
2002a1db 3108#ifndef BIG_ENDIAN_MIPS
3109 emit_xorimm(temp,3,temp);
3110#endif
535d208a 3111 emit_testimm(temp,2);
3112 case2=(int)out;
3113 emit_jne(0);
3114 emit_testimm(temp,1);
3115 case1=(int)out;
3116 emit_jne(0);
3117 // 0
3118 if (opcode[i]==0x2A) { // SWL
3119 emit_writeword_indexed(tl,0,temp);
3120 }
3121 if (opcode[i]==0x2E) { // SWR
3122 emit_writebyte_indexed(tl,3,temp);
3123 }
3124 if (opcode[i]==0x2C) { // SDL
3125 emit_writeword_indexed(th,0,temp);
3126 if(rs2[i]) emit_mov(tl,temp2);
3127 }
3128 if (opcode[i]==0x2D) { // SDR
3129 emit_writebyte_indexed(tl,3,temp);
3130 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3131 }
3132 done0=(int)out;
3133 emit_jmp(0);
3134 // 1
3135 set_jump_target(case1,(int)out);
3136 if (opcode[i]==0x2A) { // SWL
3137 // Write 3 msb into three least significant bytes
3138 if(rs2[i]) emit_rorimm(tl,8,tl);
3139 emit_writehword_indexed(tl,-1,temp);
3140 if(rs2[i]) emit_rorimm(tl,16,tl);
3141 emit_writebyte_indexed(tl,1,temp);
3142 if(rs2[i]) emit_rorimm(tl,8,tl);
3143 }
3144 if (opcode[i]==0x2E) { // SWR
3145 // Write two lsb into two most significant bytes
3146 emit_writehword_indexed(tl,1,temp);
3147 }
3148 if (opcode[i]==0x2C) { // SDL
3149 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3150 // Write 3 msb into three least significant bytes
3151 if(rs2[i]) emit_rorimm(th,8,th);
3152 emit_writehword_indexed(th,-1,temp);
3153 if(rs2[i]) emit_rorimm(th,16,th);
3154 emit_writebyte_indexed(th,1,temp);
3155 if(rs2[i]) emit_rorimm(th,8,th);
3156 }
3157 if (opcode[i]==0x2D) { // SDR
3158 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3159 // Write two lsb into two most significant bytes
3160 emit_writehword_indexed(tl,1,temp);
3161 }
3162 done1=(int)out;
3163 emit_jmp(0);
3164 // 2
3165 set_jump_target(case2,(int)out);
3166 emit_testimm(temp,1);
3167 case3=(int)out;
3168 emit_jne(0);
3169 if (opcode[i]==0x2A) { // SWL
3170 // Write two msb into two least significant bytes
3171 if(rs2[i]) emit_rorimm(tl,16,tl);
3172 emit_writehword_indexed(tl,-2,temp);
3173 if(rs2[i]) emit_rorimm(tl,16,tl);
3174 }
3175 if (opcode[i]==0x2E) { // SWR
3176 // Write 3 lsb into three most significant bytes
3177 emit_writebyte_indexed(tl,-1,temp);
3178 if(rs2[i]) emit_rorimm(tl,8,tl);
3179 emit_writehword_indexed(tl,0,temp);
3180 if(rs2[i]) emit_rorimm(tl,24,tl);
3181 }
3182 if (opcode[i]==0x2C) { // SDL
3183 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3184 // Write two msb into two least significant bytes
3185 if(rs2[i]) emit_rorimm(th,16,th);
3186 emit_writehword_indexed(th,-2,temp);
3187 if(rs2[i]) emit_rorimm(th,16,th);
3188 }
3189 if (opcode[i]==0x2D) { // SDR
3190 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3191 // Write 3 lsb into three most significant bytes
3192 emit_writebyte_indexed(tl,-1,temp);
3193 if(rs2[i]) emit_rorimm(tl,8,tl);
3194 emit_writehword_indexed(tl,0,temp);
3195 if(rs2[i]) emit_rorimm(tl,24,tl);
3196 }
3197 done2=(int)out;
3198 emit_jmp(0);
3199 // 3
3200 set_jump_target(case3,(int)out);
3201 if (opcode[i]==0x2A) { // SWL
3202 // Write msb into least significant byte
3203 if(rs2[i]) emit_rorimm(tl,24,tl);
3204 emit_writebyte_indexed(tl,-3,temp);
3205 if(rs2[i]) emit_rorimm(tl,8,tl);
3206 }
3207 if (opcode[i]==0x2E) { // SWR
3208 // Write entire word
3209 emit_writeword_indexed(tl,-3,temp);
3210 }
3211 if (opcode[i]==0x2C) { // SDL
3212 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3213 // Write msb into least significant byte
3214 if(rs2[i]) emit_rorimm(th,24,th);
3215 emit_writebyte_indexed(th,-3,temp);
3216 if(rs2[i]) emit_rorimm(th,8,th);
3217 }
3218 if (opcode[i]==0x2D) { // SDR
3219 if(rs2[i]) emit_mov(th,temp2);
3220 // Write entire word
3221 emit_writeword_indexed(tl,-3,temp);
3222 }
3223 set_jump_target(done0,(int)out);
3224 set_jump_target(done1,(int)out);
3225 set_jump_target(done2,(int)out);
3226 if (opcode[i]==0x2C) { // SDL
3227 emit_testimm(temp,4);
57871462 3228 done0=(int)out;
57871462 3229 emit_jne(0);
535d208a 3230 emit_andimm(temp,~3,temp);
3231 emit_writeword_indexed(temp2,4,temp);
3232 set_jump_target(done0,(int)out);
3233 }
3234 if (opcode[i]==0x2D) { // SDR
3235 emit_testimm(temp,4);
3236 done0=(int)out;
3237 emit_jeq(0);
3238 emit_andimm(temp,~3,temp);
3239 emit_writeword_indexed(temp2,-4,temp);
57871462 3240 set_jump_target(done0,(int)out);
57871462 3241 }
535d208a 3242 if(!c||!memtarget)
3243 add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
1edfcc68 3244 if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
535d208a 3245 #ifdef RAM_OFFSET
3246 int map=get_reg(i_regs->regmap,ROREG);
3247 if(map<0) map=HOST_TEMPREG;
3248 gen_orig_addr_w(temp,map);
3249 #else
57871462 3250 emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
535d208a 3251 #endif
57871462 3252 #if defined(HOST_IMM8)
3253 int ir=get_reg(i_regs->regmap,INVCP);
3254 assert(ir>=0);
3255 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3256 #else
3257 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3258 #endif
535d208a 3259 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3260 emit_callne(invalidate_addr_reg[temp]);
3261 #else
581335b0 3262 int jaddr2=(int)out;
57871462 3263 emit_jne(0);
3264 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
535d208a 3265 #endif
57871462 3266 }
3267 /*
3268 emit_pusha();
3269 //save_regs(0x100f);
3270 emit_readword((int)&last_count,ECX);
3271 if(get_reg(i_regs->regmap,CCREG)<0)
3272 emit_loadreg(CCREG,HOST_CCREG);
3273 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3274 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3275 emit_writeword(HOST_CCREG,(int)&Count);
3276 emit_call((int)memdebug);
3277 emit_popa();
3278 //restore_regs(0x100f);
581335b0 3279 */
57871462 3280}
3281
3282void c1ls_assemble(int i,struct regstat *i_regs)
3283{
3d624f89 3284 cop1_unusable(i, i_regs);
57871462 3285}
3286
b9b61529 3287void c2ls_assemble(int i,struct regstat *i_regs)
3288{
3289 int s,tl;
3290 int ar;
3291 int offset;
1fd1aceb 3292 int memtarget=0,c=0;
581335b0 3293 int jaddr2=0,type;
b9b61529 3294 int agr=AGEN1+(i&1);
ffb0b9e0 3295 int fastio_reg_override=0;
b9b61529 3296 u_int hr,reglist=0;
3297 u_int copr=(source[i]>>16)&0x1f;
3298 s=get_reg(i_regs->regmap,rs1[i]);
3299 tl=get_reg(i_regs->regmap,FTEMP);
3300 offset=imm[i];
3301 assert(rs1[i]>0);
3302 assert(tl>=0);
b9b61529 3303
3304 for(hr=0;hr<HOST_REGS;hr++) {
3305 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3306 }
3307 if(i_regs->regmap[HOST_CCREG]==CCREG)
3308 reglist&=~(1<<HOST_CCREG);
3309
3310 // get the address
3311 if (opcode[i]==0x3a) { // SWC2
3312 ar=get_reg(i_regs->regmap,agr);
3313 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3314 reglist|=1<<ar;
3315 } else { // LWC2
3316 ar=tl;
3317 }
1fd1aceb 3318 if(s>=0) c=(i_regs->wasconst>>s)&1;
3319 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
b9b61529 3320 if (!offset&&!c&&s>=0) ar=s;
3321 assert(ar>=0);
3322
3323 if (opcode[i]==0x3a) { // SWC2
3324 cop2_get_dreg(copr,tl,HOST_TEMPREG);
1fd1aceb 3325 type=STOREW_STUB;
b9b61529 3326 }
1fd1aceb 3327 else
b9b61529 3328 type=LOADW_STUB;
1fd1aceb 3329
3330 if(c&&!memtarget) {
3331 jaddr2=(int)out;
3332 emit_jmp(0); // inline_readstub/inline_writestub?
b9b61529 3333 }
1fd1aceb 3334 else {
3335 if(!c) {
ffb0b9e0 3336 jaddr2=emit_fastpath_cmp_jump(i,ar,&fastio_reg_override);
1fd1aceb 3337 }
a327ad27 3338 else if(ram_offset&&memtarget) {
3339 emit_addimm(ar,ram_offset,HOST_TEMPREG);
3340 fastio_reg_override=HOST_TEMPREG;
3341 }
1fd1aceb 3342 if (opcode[i]==0x32) { // LWC2
3343 #ifdef HOST_IMM_ADDR32
3344 if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3345 else
3346 #endif
ffb0b9e0 3347 int a=ar;
3348 if(fastio_reg_override) a=fastio_reg_override;
3349 emit_readword_indexed(0,a,tl);
1fd1aceb 3350 }
3351 if (opcode[i]==0x3a) { // SWC2
3352 #ifdef DESTRUCTIVE_SHIFT
3353 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3354 #endif
ffb0b9e0 3355 int a=ar;
3356 if(fastio_reg_override) a=fastio_reg_override;
3357 emit_writeword_indexed(tl,0,a);
1fd1aceb 3358 }
b9b61529 3359 }
3360 if(jaddr2)
3361 add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
0ff8c62c 3362 if(opcode[i]==0x3a) // SWC2
3363 if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
b9b61529 3364#if defined(HOST_IMM8)
3365 int ir=get_reg(i_regs->regmap,INVCP);
3366 assert(ir>=0);
3367 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3368#else
3369 emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3370#endif
0bbd1454 3371 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3372 emit_callne(invalidate_addr_reg[ar]);
3373 #else
581335b0 3374 int jaddr3=(int)out;
b9b61529 3375 emit_jne(0);
3376 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
0bbd1454 3377 #endif
b9b61529 3378 }
3379 if (opcode[i]==0x32) { // LWC2
3380 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3381 }
3382}
3383
57871462 3384#ifndef multdiv_assemble
3385void multdiv_assemble(int i,struct regstat *i_regs)
3386{
3387 printf("Need multdiv_assemble for this architecture.\n");
3388 exit(1);
3389}
3390#endif
3391
3392void mov_assemble(int i,struct regstat *i_regs)
3393{
3394 //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3395 //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
57871462 3396 if(rt1[i]) {
3397 signed char sh,sl,th,tl;
3398 th=get_reg(i_regs->regmap,rt1[i]|64);
3399 tl=get_reg(i_regs->regmap,rt1[i]);
3400 //assert(tl>=0);
3401 if(tl>=0) {
3402 sh=get_reg(i_regs->regmap,rs1[i]|64);
3403 sl=get_reg(i_regs->regmap,rs1[i]);
3404 if(sl>=0) emit_mov(sl,tl);
3405 else emit_loadreg(rs1[i],tl);
3406 if(th>=0) {
3407 if(sh>=0) emit_mov(sh,th);
3408 else emit_loadreg(rs1[i]|64,th);
3409 }
3410 }
3411 }
3412}
3413
3414#ifndef fconv_assemble
3415void fconv_assemble(int i,struct regstat *i_regs)
3416{
3417 printf("Need fconv_assemble for this architecture.\n");
3418 exit(1);
3419}
3420#endif
3421
3422#if 0
3423void float_assemble(int i,struct regstat *i_regs)
3424{
3425 printf("Need float_assemble for this architecture.\n");
3426 exit(1);
3427}
3428#endif
3429
3430void syscall_assemble(int i,struct regstat *i_regs)
3431{
3432 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3433 assert(ccreg==HOST_CCREG);
3434 assert(!is_delayslot);
581335b0 3435 (void)ccreg;
57871462 3436 emit_movimm(start+i*4,EAX); // Get PC
2573466a 3437 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
7139f3c8 3438 emit_jmp((int)jump_syscall_hle); // XXX
3439}
3440
3441void hlecall_assemble(int i,struct regstat *i_regs)
3442{
3443 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3444 assert(ccreg==HOST_CCREG);
3445 assert(!is_delayslot);
581335b0 3446 (void)ccreg;
7139f3c8 3447 emit_movimm(start+i*4+4,0); // Get PC
67ba0fb4 3448 emit_movimm((int)psxHLEt[source[i]&7],1);
2573466a 3449 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // XXX
67ba0fb4 3450 emit_jmp((int)jump_hlecall);
57871462 3451}
3452
1e973cb0 3453void intcall_assemble(int i,struct regstat *i_regs)
3454{
3455 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3456 assert(ccreg==HOST_CCREG);
3457 assert(!is_delayslot);
581335b0 3458 (void)ccreg;
1e973cb0 3459 emit_movimm(start+i*4,0); // Get PC
2573466a 3460 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
1e973cb0 3461 emit_jmp((int)jump_intcall);
3462}
3463
57871462 3464void ds_assemble(int i,struct regstat *i_regs)
3465{
ffb0b9e0 3466 speculate_register_values(i);
57871462 3467 is_delayslot=1;
3468 switch(itype[i]) {
3469 case ALU:
3470 alu_assemble(i,i_regs);break;
3471 case IMM16:
3472 imm16_assemble(i,i_regs);break;
3473 case SHIFT:
3474 shift_assemble(i,i_regs);break;
3475 case SHIFTIMM:
3476 shiftimm_assemble(i,i_regs);break;
3477 case LOAD:
3478 load_assemble(i,i_regs);break;
3479 case LOADLR:
3480 loadlr_assemble(i,i_regs);break;
3481 case STORE:
3482 store_assemble(i,i_regs);break;
3483 case STORELR:
3484 storelr_assemble(i,i_regs);break;
3485 case COP0:
3486 cop0_assemble(i,i_regs);break;
3487 case COP1:
3488 cop1_assemble(i,i_regs);break;
3489 case C1LS:
3490 c1ls_assemble(i,i_regs);break;
b9b61529 3491 case COP2:
3492 cop2_assemble(i,i_regs);break;
3493 case C2LS:
3494 c2ls_assemble(i,i_regs);break;
3495 case C2OP:
3496 c2op_assemble(i,i_regs);break;
57871462 3497 case FCONV:
3498 fconv_assemble(i,i_regs);break;
3499 case FLOAT:
3500 float_assemble(i,i_regs);break;
3501 case FCOMP:
3502 fcomp_assemble(i,i_regs);break;
3503 case MULTDIV:
3504 multdiv_assemble(i,i_regs);break;
3505 case MOV:
3506 mov_assemble(i,i_regs);break;
3507 case SYSCALL:
7139f3c8 3508 case HLECALL:
1e973cb0 3509 case INTCALL:
57871462 3510 case SPAN:
3511 case UJUMP:
3512 case RJUMP:
3513 case CJUMP:
3514 case SJUMP:
3515 case FJUMP:
c43b5311 3516 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
57871462 3517 }
3518 is_delayslot=0;
3519}
3520
3521// Is the branch target a valid internal jump?
3522int internal_branch(uint64_t i_is32,int addr)
3523{
3524 if(addr&1) return 0; // Indirect (register) jump
3525 if(addr>=start && addr<start+slen*4-4)
3526 {
71e490c5 3527 //int t=(addr-start)>>2;
57871462 3528 // Delay slots are not valid branch targets
3529 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
3530 // 64 -> 32 bit transition requires a recompile
3531 /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
3532 {
3533 if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
3534 else printf("optimizable: yes\n");
3535 }*/
3536 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
71e490c5 3537 return 1;
57871462 3538 }
3539 return 0;
3540}
3541
3542#ifndef wb_invalidate
3543void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
3544 uint64_t u,uint64_t uu)
3545{
3546 int hr;
3547 for(hr=0;hr<HOST_REGS;hr++) {
3548 if(hr!=EXCLUDE_REG) {
3549 if(pre[hr]!=entry[hr]) {
3550 if(pre[hr]>=0) {
3551 if((dirty>>hr)&1) {
3552 if(get_reg(entry,pre[hr])<0) {
3553 if(pre[hr]<64) {
3554 if(!((u>>pre[hr])&1)) {
3555 emit_storereg(pre[hr],hr);
3556 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
3557 emit_sarimm(hr,31,hr);
3558 emit_storereg(pre[hr]|64,hr);
3559 }
3560 }
3561 }else{
3562 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
3563 emit_storereg(pre[hr],hr);
3564 }
3565 }
3566 }
3567 }
3568 }
3569 }
3570 }
3571 }
3572 // Move from one register to another (no writeback)
3573 for(hr=0;hr<HOST_REGS;hr++) {
3574 if(hr!=EXCLUDE_REG) {
3575 if(pre[hr]!=entry[hr]) {
3576 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
3577 int nr;
3578 if((nr=get_reg(entry,pre[hr]))>=0) {
3579 emit_mov(hr,nr);
3580 }
3581 }
3582 }
3583 }
3584 }
3585}
3586#endif
3587
3588// Load the specified registers
3589// This only loads the registers given as arguments because
3590// we don't want to load things that will be overwritten
3591void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
3592{
3593 int hr;
3594 // Load 32-bit regs
3595 for(hr=0;hr<HOST_REGS;hr++) {
3596 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
3597 if(entry[hr]!=regmap[hr]) {
3598 if(regmap[hr]==rs1||regmap[hr]==rs2)
3599 {
3600 if(regmap[hr]==0) {
3601 emit_zeroreg(hr);
3602 }
3603 else
3604 {
3605 emit_loadreg(regmap[hr],hr);
3606 }
3607 }
3608 }
3609 }
3610 }
3611 //Load 64-bit regs
3612 for(hr=0;hr<HOST_REGS;hr++) {
3613 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
3614 if(entry[hr]!=regmap[hr]) {
3615 if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
3616 {
3617 assert(regmap[hr]!=64);
3618 if((is32>>(regmap[hr]&63))&1) {
3619 int lr=get_reg(regmap,regmap[hr]-64);
3620 if(lr>=0)
3621 emit_sarimm(lr,31,hr);
3622 else
3623 emit_loadreg(regmap[hr],hr);
3624 }
3625 else
3626 {
3627 emit_loadreg(regmap[hr],hr);
3628 }
3629 }
3630 }
3631 }
3632 }
3633}
3634
3635// Load registers prior to the start of a loop
3636// so that they are not loaded within the loop
3637static void loop_preload(signed char pre[],signed char entry[])
3638{
3639 int hr;
3640 for(hr=0;hr<HOST_REGS;hr++) {
3641 if(hr!=EXCLUDE_REG) {
3642 if(pre[hr]!=entry[hr]) {
3643 if(entry[hr]>=0) {
3644 if(get_reg(pre,entry[hr])<0) {
3645 assem_debug("loop preload:\n");
3646 //printf("loop preload: %d\n",hr);
3647 if(entry[hr]==0) {
3648 emit_zeroreg(hr);
3649 }
3650 else if(entry[hr]<TEMPREG)
3651 {
3652 emit_loadreg(entry[hr],hr);
3653 }
3654 else if(entry[hr]-64<TEMPREG)
3655 {
3656 emit_loadreg(entry[hr],hr);
3657 }
3658 }
3659 }
3660 }
3661 }
3662 }
3663}
3664
3665// Generate address for load/store instruction
b9b61529 3666// goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
57871462 3667void address_generation(int i,struct regstat *i_regs,signed char entry[])
3668{
b9b61529 3669 if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
5194fb95 3670 int ra=-1;
57871462 3671 int agr=AGEN1+(i&1);
57871462 3672 if(itype[i]==LOAD) {
3673 ra=get_reg(i_regs->regmap,rt1[i]);
9f51b4b9 3674 if(ra<0) ra=get_reg(i_regs->regmap,-1);
535d208a 3675 assert(ra>=0);
57871462 3676 }
3677 if(itype[i]==LOADLR) {
3678 ra=get_reg(i_regs->regmap,FTEMP);
3679 }
3680 if(itype[i]==STORE||itype[i]==STORELR) {
3681 ra=get_reg(i_regs->regmap,agr);
3682 if(ra<0) ra=get_reg(i_regs->regmap,-1);
3683 }
b9b61529 3684 if(itype[i]==C1LS||itype[i]==C2LS) {
3685 if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
57871462 3686 ra=get_reg(i_regs->regmap,FTEMP);
1fd1aceb 3687 else { // SWC1/SDC1/SWC2/SDC2
57871462 3688 ra=get_reg(i_regs->regmap,agr);
3689 if(ra<0) ra=get_reg(i_regs->regmap,-1);
3690 }
3691 }
3692 int rs=get_reg(i_regs->regmap,rs1[i]);
57871462 3693 if(ra>=0) {
3694 int offset=imm[i];
3695 int c=(i_regs->wasconst>>rs)&1;
3696 if(rs1[i]==0) {
3697 // Using r0 as a base address
57871462 3698 if(!entry||entry[ra]!=agr) {
3699 if (opcode[i]==0x22||opcode[i]==0x26) {
3700 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
3701 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
3702 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
3703 }else{
3704 emit_movimm(offset,ra);
3705 }
3706 } // else did it in the previous cycle
3707 }
3708 else if(rs<0) {
3709 if(!entry||entry[ra]!=rs1[i])
3710 emit_loadreg(rs1[i],ra);
3711 //if(!entry||entry[ra]!=rs1[i])
3712 // printf("poor load scheduling!\n");
3713 }
3714 else if(c) {
57871462 3715 if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
3716 if(!entry||entry[ra]!=agr) {
3717 if (opcode[i]==0x22||opcode[i]==0x26) {
3718 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
3719 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
3720 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
3721 }else{
3722 #ifdef HOST_IMM_ADDR32
1edfcc68 3723 if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32)) // LWC1/LDC1/LWC2/LDC2
57871462 3724 #endif
3725 emit_movimm(constmap[i][rs]+offset,ra);
8575a877 3726 regs[i].loadedconst|=1<<ra;
57871462 3727 }
3728 } // else did it in the previous cycle
3729 } // else load_consts already did it
3730 }
3731 if(offset&&!c&&rs1[i]) {
3732 if(rs>=0) {
3733 emit_addimm(rs,offset,ra);
3734 }else{
3735 emit_addimm(ra,offset,ra);
3736 }
3737 }
3738 }
3739 }
3740 // Preload constants for next instruction
b9b61529 3741 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
57871462 3742 int agr,ra;
57871462 3743 // Actual address
3744 agr=AGEN1+((i+1)&1);
3745 ra=get_reg(i_regs->regmap,agr);
3746 if(ra>=0) {
3747 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
3748 int offset=imm[i+1];
3749 int c=(regs[i+1].wasconst>>rs)&1;
3750 if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
3751 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
3752 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
3753 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
3754 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
3755 }else{
3756 #ifdef HOST_IMM_ADDR32
1edfcc68 3757 if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32)) // LWC1/LDC1/LWC2/LDC2
57871462 3758 #endif
3759 emit_movimm(constmap[i+1][rs]+offset,ra);
8575a877 3760 regs[i+1].loadedconst|=1<<ra;
57871462 3761 }
3762 }
3763 else if(rs1[i+1]==0) {
3764 // Using r0 as a base address
3765 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
3766 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
3767 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
3768 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
3769 }else{
3770 emit_movimm(offset,ra);
3771 }
3772 }
3773 }
3774 }
3775}
3776
e2b5e7aa 3777static int get_final_value(int hr, int i, int *value)
57871462 3778{
3779 int reg=regs[i].regmap[hr];
3780 while(i<slen-1) {
3781 if(regs[i+1].regmap[hr]!=reg) break;
3782 if(!((regs[i+1].isconst>>hr)&1)) break;
3783 if(bt[i+1]) break;
3784 i++;
3785 }
3786 if(i<slen-1) {
3787 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
3788 *value=constmap[i][hr];
3789 return 1;
3790 }
3791 if(!bt[i+1]) {
3792 if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
3793 // Load in delay slot, out-of-order execution
3794 if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
3795 {
57871462 3796 // Precompute load address
3797 *value=constmap[i][hr]+imm[i+2];
3798 return 1;
3799 }
3800 }
3801 if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
3802 {
57871462 3803 // Precompute load address
3804 *value=constmap[i][hr]+imm[i+1];
3805 //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
3806 return 1;
3807 }
3808 }
3809 }
3810 *value=constmap[i][hr];
3811 //printf("c=%x\n",(int)constmap[i][hr]);
3812 if(i==slen-1) return 1;
3813 if(reg<64) {
3814 return !((unneeded_reg[i+1]>>reg)&1);
3815 }else{
3816 return !((unneeded_reg_upper[i+1]>>reg)&1);
3817 }
3818}
3819
3820// Load registers with known constants
3821void load_consts(signed char pre[],signed char regmap[],int is32,int i)
3822{
8575a877 3823 int hr,hr2;
3824 // propagate loaded constant flags
3825 if(i==0||bt[i])
3826 regs[i].loadedconst=0;
3827 else {
3828 for(hr=0;hr<HOST_REGS;hr++) {
3829 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((regs[i-1].isconst>>hr)&1)&&pre[hr]==regmap[hr]
3830 &&regmap[hr]==regs[i-1].regmap[hr]&&((regs[i-1].loadedconst>>hr)&1))
3831 {
3832 regs[i].loadedconst|=1<<hr;
3833 }
3834 }
3835 }
57871462 3836 // Load 32-bit regs
3837 for(hr=0;hr<HOST_REGS;hr++) {
3838 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
3839 //if(entry[hr]!=regmap[hr]) {
8575a877 3840 if(!((regs[i].loadedconst>>hr)&1)) {
57871462 3841 if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
8575a877 3842 int value,similar=0;
57871462 3843 if(get_final_value(hr,i,&value)) {
8575a877 3844 // see if some other register has similar value
3845 for(hr2=0;hr2<HOST_REGS;hr2++) {
3846 if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
3847 if(is_similar_value(value,constmap[i][hr2])) {
3848 similar=1;
3849 break;
3850 }
3851 }
3852 }
3853 if(similar) {
3854 int value2;
3855 if(get_final_value(hr2,i,&value2)) // is this needed?
3856 emit_movimm_from(value2,hr2,value,hr);
3857 else
3858 emit_movimm(value,hr);
3859 }
3860 else if(value==0) {
57871462 3861 emit_zeroreg(hr);
3862 }
3863 else {
3864 emit_movimm(value,hr);
3865 }
3866 }
8575a877 3867 regs[i].loadedconst|=1<<hr;
57871462 3868 }
3869 }
3870 }
3871 }
3872 // Load 64-bit regs
3873 for(hr=0;hr<HOST_REGS;hr++) {
3874 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
3875 //if(entry[hr]!=regmap[hr]) {
3876 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
3877 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
3878 if((is32>>(regmap[hr]&63))&1) {
3879 int lr=get_reg(regmap,regmap[hr]-64);
3880 assert(lr>=0);
3881 emit_sarimm(lr,31,hr);
3882 }
3883 else
3884 {
3885 int value;
3886 if(get_final_value(hr,i,&value)) {
3887 if(value==0) {
3888 emit_zeroreg(hr);
3889 }
3890 else {
3891 emit_movimm(value,hr);
3892 }
3893 }
3894 }
3895 }
3896 }
3897 }
3898 }
3899}
3900void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
3901{
3902 int hr;
3903 // Load 32-bit regs
3904 for(hr=0;hr<HOST_REGS;hr++) {
3905 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
3906 if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
3907 int value=constmap[i][hr];
3908 if(value==0) {
3909 emit_zeroreg(hr);
3910 }
3911 else {
3912 emit_movimm(value,hr);
3913 }
3914 }
3915 }
3916 }
3917 // Load 64-bit regs
3918 for(hr=0;hr<HOST_REGS;hr++) {
3919 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
3920 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
3921 if((is32>>(regmap[hr]&63))&1) {
3922 int lr=get_reg(regmap,regmap[hr]-64);
3923 assert(lr>=0);
3924 emit_sarimm(lr,31,hr);
3925 }
3926 else
3927 {
3928 int value=constmap[i][hr];
3929 if(value==0) {
3930 emit_zeroreg(hr);
3931 }
3932 else {
3933 emit_movimm(value,hr);
3934 }
3935 }
3936 }
3937 }
3938 }
3939}
3940
3941// Write out all dirty registers (except cycle count)
3942void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
3943{
3944 int hr;
3945 for(hr=0;hr<HOST_REGS;hr++) {
3946 if(hr!=EXCLUDE_REG) {
3947 if(i_regmap[hr]>0) {
3948 if(i_regmap[hr]!=CCREG) {
3949 if((i_dirty>>hr)&1) {
3950 if(i_regmap[hr]<64) {
3951 emit_storereg(i_regmap[hr],hr);
57871462 3952 }else{
3953 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
3954 emit_storereg(i_regmap[hr],hr);
3955 }
3956 }
3957 }
3958 }
3959 }
3960 }
3961 }
3962}
3963// Write out dirty registers that we need to reload (pair with load_needed_regs)
3964// This writes the registers not written by store_regs_bt
3965void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
3966{
3967 int hr;
3968 int t=(addr-start)>>2;
3969 for(hr=0;hr<HOST_REGS;hr++) {
3970 if(hr!=EXCLUDE_REG) {
3971 if(i_regmap[hr]>0) {
3972 if(i_regmap[hr]!=CCREG) {
3973 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
3974 if((i_dirty>>hr)&1) {
3975 if(i_regmap[hr]<64) {
3976 emit_storereg(i_regmap[hr],hr);
57871462 3977 }else{
3978 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
3979 emit_storereg(i_regmap[hr],hr);
3980 }
3981 }
3982 }
3983 }
3984 }
3985 }
3986 }
3987 }
3988}
3989
3990// Load all registers (except cycle count)
3991void load_all_regs(signed char i_regmap[])
3992{
3993 int hr;
3994 for(hr=0;hr<HOST_REGS;hr++) {
3995 if(hr!=EXCLUDE_REG) {
3996 if(i_regmap[hr]==0) {
3997 emit_zeroreg(hr);
3998 }
3999 else
ea3d2e6e 4000 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
57871462 4001 {
4002 emit_loadreg(i_regmap[hr],hr);
4003 }
4004 }
4005 }
4006}
4007
4008// Load all current registers also needed by next instruction
4009void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4010{
4011 int hr;
4012 for(hr=0;hr<HOST_REGS;hr++) {
4013 if(hr!=EXCLUDE_REG) {
4014 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4015 if(i_regmap[hr]==0) {
4016 emit_zeroreg(hr);
4017 }
4018 else
ea3d2e6e 4019 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
57871462 4020 {
4021 emit_loadreg(i_regmap[hr],hr);
4022 }
4023 }
4024 }
4025 }
4026}
4027
4028// Load all regs, storing cycle count if necessary
4029void load_regs_entry(int t)
4030{
4031 int hr;
2573466a 4032 if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
4033 else if(ccadj[t]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST(ccadj[t]),HOST_CCREG);
57871462 4034 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4035 emit_storereg(CCREG,HOST_CCREG);
4036 }
4037 // Load 32-bit regs
4038 for(hr=0;hr<HOST_REGS;hr++) {
ea3d2e6e 4039 if(regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
57871462 4040 if(regs[t].regmap_entry[hr]==0) {
4041 emit_zeroreg(hr);
4042 }
4043 else if(regs[t].regmap_entry[hr]!=CCREG)
4044 {
4045 emit_loadreg(regs[t].regmap_entry[hr],hr);
4046 }
4047 }
4048 }
4049 // Load 64-bit regs
4050 for(hr=0;hr<HOST_REGS;hr++) {
ea3d2e6e 4051 if(regs[t].regmap_entry[hr]>=64&&regs[t].regmap_entry[hr]<TEMPREG+64) {
57871462 4052 assert(regs[t].regmap_entry[hr]!=64);
4053 if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4054 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4055 if(lr<0) {
4056 emit_loadreg(regs[t].regmap_entry[hr],hr);
4057 }
4058 else
4059 {
4060 emit_sarimm(lr,31,hr);
4061 }
4062 }
4063 else
4064 {
4065 emit_loadreg(regs[t].regmap_entry[hr],hr);
4066 }
4067 }
4068 }
4069}
4070
4071// Store dirty registers prior to branch
4072void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4073{
4074 if(internal_branch(i_is32,addr))
4075 {
4076 int t=(addr-start)>>2;
4077 int hr;
4078 for(hr=0;hr<HOST_REGS;hr++) {
4079 if(hr!=EXCLUDE_REG) {
4080 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4081 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4082 if((i_dirty>>hr)&1) {
4083 if(i_regmap[hr]<64) {
4084 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4085 emit_storereg(i_regmap[hr],hr);
4086 if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4087 #ifdef DESTRUCTIVE_WRITEBACK
4088 emit_sarimm(hr,31,hr);
4089 emit_storereg(i_regmap[hr]|64,hr);
4090 #else
4091 emit_sarimm(hr,31,HOST_TEMPREG);
4092 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4093 #endif
4094 }
4095 }
4096 }else{
4097 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4098 emit_storereg(i_regmap[hr],hr);
4099 }
4100 }
4101 }
4102 }
4103 }
4104 }
4105 }
4106 }
4107 else
4108 {
4109 // Branch out of this block, write out all dirty regs
4110 wb_dirtys(i_regmap,i_is32,i_dirty);
4111 }
4112}
4113
4114// Load all needed registers for branch target
4115void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4116{
4117 //if(addr>=start && addr<(start+slen*4))
4118 if(internal_branch(i_is32,addr))
4119 {
4120 int t=(addr-start)>>2;
4121 int hr;
4122 // Store the cycle count before loading something else
4123 if(i_regmap[HOST_CCREG]!=CCREG) {
4124 assert(i_regmap[HOST_CCREG]==-1);
4125 }
4126 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4127 emit_storereg(CCREG,HOST_CCREG);
4128 }
4129 // Load 32-bit regs
4130 for(hr=0;hr<HOST_REGS;hr++) {
ea3d2e6e 4131 if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
57871462 4132 #ifdef DESTRUCTIVE_WRITEBACK
4133 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4134 #else
4135 if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4136 #endif
4137 if(regs[t].regmap_entry[hr]==0) {
4138 emit_zeroreg(hr);
4139 }
4140 else if(regs[t].regmap_entry[hr]!=CCREG)
4141 {
4142 emit_loadreg(regs[t].regmap_entry[hr],hr);
4143 }
4144 }
4145 }
4146 }
4147 //Load 64-bit regs
4148 for(hr=0;hr<HOST_REGS;hr++) {
ea3d2e6e 4149 if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=64&&regs[t].regmap_entry[hr]<TEMPREG+64) {
57871462 4150 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4151 assert(regs[t].regmap_entry[hr]!=64);
4152 if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4153 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4154 if(lr<0) {
4155 emit_loadreg(regs[t].regmap_entry[hr],hr);
4156 }
4157 else
4158 {
4159 emit_sarimm(lr,31,hr);
4160 }
4161 }
4162 else
4163 {
4164 emit_loadreg(regs[t].regmap_entry[hr],hr);
4165 }
4166 }
4167 else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4168 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4169 assert(lr>=0);
4170 emit_sarimm(lr,31,hr);
4171 }
4172 }
4173 }
4174 }
4175}
4176
4177int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4178{
4179 if(addr>=start && addr<start+slen*4-4)
4180 {
4181 int t=(addr-start)>>2;
4182 int hr;
4183 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4184 for(hr=0;hr<HOST_REGS;hr++)
4185 {
4186 if(hr!=EXCLUDE_REG)
4187 {
4188 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4189 {
ea3d2e6e 4190 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
57871462 4191 {
4192 return 0;
4193 }
9f51b4b9 4194 else
57871462 4195 if((i_dirty>>hr)&1)
4196 {
ea3d2e6e 4197 if(i_regmap[hr]<TEMPREG)
57871462 4198 {
4199 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4200 return 0;
4201 }
ea3d2e6e 4202 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
57871462 4203 {
4204 if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4205 return 0;
4206 }
4207 }
4208 }
4209 else // Same register but is it 32-bit or dirty?
4210 if(i_regmap[hr]>=0)
4211 {
4212 if(!((regs[t].dirty>>hr)&1))
4213 {
4214 if((i_dirty>>hr)&1)
4215 {
4216 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4217 {
4218 //printf("%x: dirty no match\n",addr);
4219 return 0;
4220 }
4221 }
4222 }
4223 if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4224 {
4225 //printf("%x: is32 no match\n",addr);
4226 return 0;
4227 }
4228 }
4229 }
4230 }
4231 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
57871462 4232 // Delay slots are not valid branch targets
4233 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4234 // Delay slots require additional processing, so do not match
4235 if(is_ds[t]) return 0;
4236 }
4237 else
4238 {
4239 int hr;
4240 for(hr=0;hr<HOST_REGS;hr++)
4241 {
4242 if(hr!=EXCLUDE_REG)
4243 {
4244 if(i_regmap[hr]>=0)
4245 {
4246 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4247 {
4248 if((i_dirty>>hr)&1)
4249 {
4250 return 0;
4251 }
4252 }
4253 }
4254 }
4255 }
4256 }
4257 return 1;
4258}
4259
4260// Used when a branch jumps into the delay slot of another branch
4261void ds_assemble_entry(int i)
4262{
4263 int t=(ba[i]-start)>>2;
4264 if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4265 assem_debug("Assemble delay slot at %x\n",ba[i]);
4266 assem_debug("<->\n");
4267 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
4268 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4269 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4270 address_generation(t,&regs[t],regs[t].regmap_entry);
b9b61529 4271 if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
57871462 4272 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4273 cop1_usable=0;
4274 is_delayslot=0;
4275 switch(itype[t]) {
4276 case ALU:
4277 alu_assemble(t,&regs[t]);break;
4278 case IMM16:
4279 imm16_assemble(t,&regs[t]);break;
4280 case SHIFT:
4281 shift_assemble(t,&regs[t]);break;
4282 case SHIFTIMM:
4283 shiftimm_assemble(t,&regs[t]);break;
4284 case LOAD:
4285 load_assemble(t,&regs[t]);break;
4286 case LOADLR:
4287 loadlr_assemble(t,&regs[t]);break;
4288 case STORE:
4289 store_assemble(t,&regs[t]);break;
4290 case STORELR:
4291 storelr_assemble(t,&regs[t]);break;
4292 case COP0:
4293 cop0_assemble(t,&regs[t]);break;
4294 case COP1:
4295 cop1_assemble(t,&regs[t]);break;
4296 case C1LS:
4297 c1ls_assemble(t,&regs[t]);break;
b9b61529 4298 case COP2:
4299 cop2_assemble(t,&regs[t]);break;
4300 case C2LS:
4301 c2ls_assemble(t,&regs[t]);break;
4302 case C2OP:
4303 c2op_assemble(t,&regs[t]);break;
57871462 4304 case FCONV:
4305 fconv_assemble(t,&regs[t]);break;
4306 case FLOAT:
4307 float_assemble(t,&regs[t]);break;
4308 case FCOMP:
4309 fcomp_assemble(t,&regs[t]);break;
4310 case MULTDIV:
4311 multdiv_assemble(t,&regs[t]);break;
4312 case MOV:
4313 mov_assemble(t,&regs[t]);break;
4314 case SYSCALL:
7139f3c8 4315 case HLECALL:
1e973cb0 4316 case INTCALL:
57871462 4317 case SPAN:
4318 case UJUMP:
4319 case RJUMP:
4320 case CJUMP:
4321 case SJUMP:
4322 case FJUMP:
c43b5311 4323 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
57871462 4324 }
4325 store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4326 load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4327 if(internal_branch(regs[t].is32,ba[i]+4))
4328 assem_debug("branch: internal\n");
4329 else
4330 assem_debug("branch: external\n");
4331 assert(internal_branch(regs[t].is32,ba[i]+4));
4332 add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4333 emit_jmp(0);
4334}
4335
4336void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4337{
4338 int count;
4339 int jaddr;
4340 int idle=0;
b6e87b2b 4341 int t=0;
57871462 4342 if(itype[i]==RJUMP)
4343 {
4344 *adj=0;
4345 }
4346 //if(ba[i]>=start && ba[i]<(start+slen*4))
4347 if(internal_branch(branch_regs[i].is32,ba[i]))
4348 {
b6e87b2b 4349 t=(ba[i]-start)>>2;
57871462 4350 if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4351 else *adj=ccadj[t];
4352 }
4353 else
4354 {
4355 *adj=0;
4356 }
4357 count=ccadj[i];
4358 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4359 // Idle loop
4360 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4361 idle=(int)out;
4362 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4363 emit_andimm(HOST_CCREG,3,HOST_CCREG);
4364 jaddr=(int)out;
4365 emit_jmp(0);
4366 }
4367 else if(*adj==0||invert) {
b6e87b2b 4368 int cycles=CLOCK_ADJUST(count+2);
4369 // faster loop HACK
4370 if (t&&*adj) {
4371 int rel=t-i;
4372 if(-NO_CYCLE_PENALTY_THR<rel&&rel<0)
4373 cycles=CLOCK_ADJUST(*adj)+count+2-*adj;
4374 }
4375 emit_addimm_and_set_flags(cycles,HOST_CCREG);
57871462 4376 jaddr=(int)out;
4377 emit_jns(0);
4378 }
4379 else
4380 {
2573466a 4381 emit_cmpimm(HOST_CCREG,-CLOCK_ADJUST(count+2));
57871462 4382 jaddr=(int)out;
4383 emit_jns(0);
4384 }
4385 add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4386}
4387
4388void do_ccstub(int n)
4389{
4390 literal_pool(256);
4391 assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
4392 set_jump_target(stubs[n][1],(int)out);
4393 int i=stubs[n][4];
4394 if(stubs[n][6]==NULLDS) {
4395 // Delay slot instruction is nullified ("likely" branch)
4396 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4397 }
4398 else if(stubs[n][6]!=TAKEN) {
4399 wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4400 }
4401 else {
4402 if(internal_branch(branch_regs[i].is32,ba[i]))
4403 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4404 }
4405 if(stubs[n][5]!=-1)
4406 {
4407 // Save PC as return address
4408 emit_movimm(stubs[n][5],EAX);
4409 emit_writeword(EAX,(int)&pcaddr);
4410 }
4411 else
4412 {
4413 // Return address depends on which way the branch goes
4414 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
4415 {
4416 int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4417 int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4418 int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4419 int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4420 if(rs1[i]==0)
4421 {
4422 s1l=s2l;s1h=s2h;
4423 s2l=s2h=-1;
4424 }
4425 else if(rs2[i]==0)
4426 {
4427 s2l=s2h=-1;
4428 }
4429 if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
4430 s1h=s2h=-1;
4431 }
4432 assert(s1l>=0);
4433 #ifdef DESTRUCTIVE_WRITEBACK
4434 if(rs1[i]) {
4435 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
4436 emit_loadreg(rs1[i],s1l);
9f51b4b9 4437 }
57871462 4438 else {
4439 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
4440 emit_loadreg(rs2[i],s1l);
4441 }
4442 if(s2l>=0)
4443 if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
4444 emit_loadreg(rs2[i],s2l);
4445 #endif
4446 int hr=0;
5194fb95 4447 int addr=-1,alt=-1,ntaddr=-1;
57871462 4448 while(hr<HOST_REGS)
4449 {
4450 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4451 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4452 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4453 {
4454 addr=hr++;break;
4455 }
4456 hr++;
4457 }
4458 while(hr<HOST_REGS)
4459 {
4460 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4461 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4462 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4463 {
4464 alt=hr++;break;
4465 }
4466 hr++;
4467 }
4468 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
4469 {
4470 while(hr<HOST_REGS)
4471 {
4472 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4473 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4474 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4475 {
4476 ntaddr=hr;break;
4477 }
4478 hr++;
4479 }
4480 assert(hr<HOST_REGS);
4481 }
4482 if((opcode[i]&0x2f)==4) // BEQ
4483 {
4484 #ifdef HAVE_CMOV_IMM
4485 if(s1h<0) {
4486 if(s2l>=0) emit_cmp(s1l,s2l);
4487 else emit_test(s1l,s1l);
4488 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
4489 }
4490 else
4491 #endif
4492 {
4493 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4494 if(s1h>=0) {
4495 if(s2h>=0) emit_cmp(s1h,s2h);
4496 else emit_test(s1h,s1h);
4497 emit_cmovne_reg(alt,addr);
4498 }
4499 if(s2l>=0) emit_cmp(s1l,s2l);
4500 else emit_test(s1l,s1l);
4501 emit_cmovne_reg(alt,addr);
4502 }
4503 }
4504 if((opcode[i]&0x2f)==5) // BNE
4505 {
4506 #ifdef HAVE_CMOV_IMM
4507 if(s1h<0) {
4508 if(s2l>=0) emit_cmp(s1l,s2l);
4509 else emit_test(s1l,s1l);
4510 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
4511 }
4512 else
4513 #endif
4514 {
4515 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
4516 if(s1h>=0) {
4517 if(s2h>=0) emit_cmp(s1h,s2h);
4518 else emit_test(s1h,s1h);
4519 emit_cmovne_reg(alt,addr);
4520 }
4521 if(s2l>=0) emit_cmp(s1l,s2l);
4522 else emit_test(s1l,s1l);
4523 emit_cmovne_reg(alt,addr);
4524 }
4525 }
4526 if((opcode[i]&0x2f)==6) // BLEZ
4527 {
4528 //emit_movimm(ba[i],alt);
4529 //emit_movimm(start+i*4+8,addr);
4530 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4531 emit_cmpimm(s1l,1);
4532 if(s1h>=0) emit_mov(addr,ntaddr);
4533 emit_cmovl_reg(alt,addr);
4534 if(s1h>=0) {
4535 emit_test(s1h,s1h);
4536 emit_cmovne_reg(ntaddr,addr);
4537 emit_cmovs_reg(alt,addr);
4538 }
4539 }
4540 if((opcode[i]&0x2f)==7) // BGTZ
4541 {
4542 //emit_movimm(ba[i],addr);
4543 //emit_movimm(start+i*4+8,ntaddr);
4544 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
4545 emit_cmpimm(s1l,1);
4546 if(s1h>=0) emit_mov(addr,alt);
4547 emit_cmovl_reg(ntaddr,addr);
4548 if(s1h>=0) {
4549 emit_test(s1h,s1h);
4550 emit_cmovne_reg(alt,addr);
4551 emit_cmovs_reg(ntaddr,addr);
4552 }
4553 }
4554 if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
4555 {
4556 //emit_movimm(ba[i],alt);
4557 //emit_movimm(start+i*4+8,addr);
4558 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4559 if(s1h>=0) emit_test(s1h,s1h);
4560 else emit_test(s1l,s1l);
4561 emit_cmovs_reg(alt,addr);
4562 }
4563 if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
4564 {
4565 //emit_movimm(ba[i],addr);
4566 //emit_movimm(start+i*4+8,alt);
4567 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4568 if(s1h>=0) emit_test(s1h,s1h);
4569 else emit_test(s1l,s1l);
4570 emit_cmovs_reg(alt,addr);
4571 }
4572 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
4573 if(source[i]&0x10000) // BC1T
4574 {
4575 //emit_movimm(ba[i],alt);
4576 //emit_movimm(start+i*4+8,addr);
4577 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4578 emit_testimm(s1l,0x800000);
4579 emit_cmovne_reg(alt,addr);
4580 }
4581 else // BC1F
4582 {
4583 //emit_movimm(ba[i],addr);
4584 //emit_movimm(start+i*4+8,alt);
4585 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4586 emit_testimm(s1l,0x800000);
4587 emit_cmovne_reg(alt,addr);
4588 }
4589 }
4590 emit_writeword(addr,(int)&pcaddr);
4591 }
4592 else
4593 if(itype[i]==RJUMP)
4594 {
4595 int r=get_reg(branch_regs[i].regmap,rs1[i]);
4596 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
4597 r=get_reg(branch_regs[i].regmap,RTEMP);
4598 }
4599 emit_writeword(r,(int)&pcaddr);
4600 }
c43b5311 4601 else {SysPrintf("Unknown branch type in do_ccstub\n");exit(1);}
57871462 4602 }
4603 // Update cycle count
4604 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
2573466a 4605 if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG);
57871462 4606 emit_call((int)cc_interrupt);
2573466a 4607 if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG);
57871462 4608 if(stubs[n][6]==TAKEN) {
4609 if(internal_branch(branch_regs[i].is32,ba[i]))
4610 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
4611 else if(itype[i]==RJUMP) {
4612 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
4613 emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
4614 else
4615 emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
4616 }
4617 }else if(stubs[n][6]==NOTTAKEN) {
4618 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
4619 else load_all_regs(branch_regs[i].regmap);
4620 }else if(stubs[n][6]==NULLDS) {
4621 // Delay slot instruction is nullified ("likely" branch)
4622 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
4623 else load_all_regs(regs[i].regmap);
4624 }else{
4625 load_all_regs(branch_regs[i].regmap);
4626 }
4627 emit_jmp(stubs[n][2]); // return address
9f51b4b9 4628
57871462 4629 /* This works but uses a lot of memory...
4630 emit_readword((int)&last_count,ECX);
4631 emit_add(HOST_CCREG,ECX,EAX);
4632 emit_writeword(EAX,(int)&Count);
4633 emit_call((int)gen_interupt);
4634 emit_readword((int)&Count,HOST_CCREG);
4635 emit_readword((int)&next_interupt,EAX);
4636 emit_readword((int)&pending_exception,EBX);
4637 emit_writeword(EAX,(int)&last_count);
4638 emit_sub(HOST_CCREG,EAX,HOST_CCREG);
4639 emit_test(EBX,EBX);
4640 int jne_instr=(int)out;
4641 emit_jne(0);
4642 if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
4643 load_all_regs(branch_regs[i].regmap);
4644 emit_jmp(stubs[n][2]); // return address
4645 set_jump_target(jne_instr,(int)out);
4646 emit_readword((int)&pcaddr,EAX);
4647 // Call get_addr_ht instead of doing the hash table here.
4648 // This code is executed infrequently and takes up a lot of space
4649 // so smaller is better.
4650 emit_storereg(CCREG,HOST_CCREG);
4651 emit_pushreg(EAX);
4652 emit_call((int)get_addr_ht);
4653 emit_loadreg(CCREG,HOST_CCREG);
4654 emit_addimm(ESP,4,ESP);
4655 emit_jmpreg(EAX);*/
4656}
4657
e2b5e7aa 4658static void add_to_linker(int addr,int target,int ext)
57871462 4659{
4660 link_addr[linkcount][0]=addr;
4661 link_addr[linkcount][1]=target;
9f51b4b9 4662 link_addr[linkcount][2]=ext;
57871462 4663 linkcount++;
4664}
4665
eba830cd 4666static void ujump_assemble_write_ra(int i)
4667{
4668 int rt;
4669 unsigned int return_address;
4670 rt=get_reg(branch_regs[i].regmap,31);
4671 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
4672 //assert(rt>=0);
4673 return_address=start+i*4+8;
4674 if(rt>=0) {
4675 #ifdef USE_MINI_HT
4676 if(internal_branch(branch_regs[i].is32,return_address)&&rt1[i+1]!=31) {
4677 int temp=-1; // note: must be ds-safe
4678 #ifdef HOST_TEMPREG
4679 temp=HOST_TEMPREG;
4680 #endif
4681 if(temp>=0) do_miniht_insert(return_address,rt,temp);
4682 else emit_movimm(return_address,rt);
4683 }
4684 else
4685 #endif
4686 {
4687 #ifdef REG_PREFETCH
9f51b4b9 4688 if(temp>=0)
eba830cd 4689 {
4690 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
4691 }
4692 #endif
4693 emit_movimm(return_address,rt); // PC into link register
4694 #ifdef IMM_PREFETCH
4695 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
4696 #endif
4697 }
4698 }
4699}
4700
57871462 4701void ujump_assemble(int i,struct regstat *i_regs)
4702{
eba830cd 4703 int ra_done=0;
57871462 4704 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
4705 address_generation(i+1,i_regs,regs[i].regmap_entry);
4706 #ifdef REG_PREFETCH
4707 int temp=get_reg(branch_regs[i].regmap,PTEMP);
9f51b4b9 4708 if(rt1[i]==31&&temp>=0)
57871462 4709 {
581335b0 4710 signed char *i_regmap=i_regs->regmap;
57871462 4711 int return_address=start+i*4+8;
9f51b4b9 4712 if(get_reg(branch_regs[i].regmap,31)>0)
57871462 4713 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
4714 }
4715 #endif
eba830cd 4716 if(rt1[i]==31&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
4717 ujump_assemble_write_ra(i); // writeback ra for DS
4718 ra_done=1;
57871462 4719 }
4ef8f67d 4720 ds_assemble(i+1,i_regs);
4721 uint64_t bc_unneeded=branch_regs[i].u;
4722 uint64_t bc_unneeded_upper=branch_regs[i].uu;
4723 bc_unneeded|=1|(1LL<<rt1[i]);
4724 bc_unneeded_upper|=1|(1LL<<rt1[i]);
4725 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
4726 bc_unneeded,bc_unneeded_upper);
4727 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
eba830cd 4728 if(!ra_done&&rt1[i]==31)
4729 ujump_assemble_write_ra(i);
57871462 4730 int cc,adj;
4731 cc=get_reg(branch_regs[i].regmap,CCREG);
4732 assert(cc==HOST_CCREG);
4733 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4734 #ifdef REG_PREFETCH
4735 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
4736 #endif
4737 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
2573466a 4738 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
57871462 4739 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4740 if(internal_branch(branch_regs[i].is32,ba[i]))
4741 assem_debug("branch: internal\n");
4742 else
4743 assem_debug("branch: external\n");
4744 if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
4745 ds_assemble_entry(i);
4746 }
4747 else {
4748 add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
4749 emit_jmp(0);
4750 }
4751}
4752
eba830cd 4753static void rjump_assemble_write_ra(int i)
4754{
4755 int rt,return_address;
4756 assert(rt1[i+1]!=rt1[i]);
4757 assert(rt2[i+1]!=rt1[i]);
4758 rt=get_reg(branch_regs[i].regmap,rt1[i]);
4759 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
4760 assert(rt>=0);
4761 return_address=start+i*4+8;
4762 #ifdef REG_PREFETCH
9f51b4b9 4763 if(temp>=0)
eba830cd 4764 {
4765 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
4766 }
4767 #endif
4768 emit_movimm(return_address,rt); // PC into link register
4769 #ifdef IMM_PREFETCH
4770 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
4771 #endif
4772}
4773
57871462 4774void rjump_assemble(int i,struct regstat *i_regs)
4775{
57871462 4776 int temp;
581335b0 4777 int rs,cc;
eba830cd 4778 int ra_done=0;
57871462 4779 rs=get_reg(branch_regs[i].regmap,rs1[i]);
4780 assert(rs>=0);
4781 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
4782 // Delay slot abuse, make a copy of the branch address register
4783 temp=get_reg(branch_regs[i].regmap,RTEMP);
4784 assert(temp>=0);
4785 assert(regs[i].regmap[temp]==RTEMP);
4786 emit_mov(rs,temp);
4787 rs=temp;
4788 }
4789 address_generation(i+1,i_regs,regs[i].regmap_entry);
4790 #ifdef REG_PREFETCH
9f51b4b9 4791 if(rt1[i]==31)
57871462 4792 {
4793 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
581335b0 4794 signed char *i_regmap=i_regs->regmap;
57871462 4795 int return_address=start+i*4+8;
4796 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
4797 }
4798 }
4799 #endif
4800 #ifdef USE_MINI_HT
4801 if(rs1[i]==31) {
4802 int rh=get_reg(regs[i].regmap,RHASH);
4803 if(rh>=0) do_preload_rhash(rh);
4804 }
4805 #endif
eba830cd 4806 if(rt1[i]!=0&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
4807 rjump_assemble_write_ra(i);
4808 ra_done=1;
57871462 4809 }
d5910d5d 4810 ds_assemble(i+1,i_regs);
4811 uint64_t bc_unneeded=branch_regs[i].u;
4812 uint64_t bc_unneeded_upper=branch_regs[i].uu;
4813 bc_unneeded|=1|(1LL<<rt1[i]);
4814 bc_unneeded_upper|=1|(1LL<<rt1[i]);
4815 bc_unneeded&=~(1LL<<rs1[i]);
4816 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
4817 bc_unneeded,bc_unneeded_upper);
4818 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
eba830cd 4819 if(!ra_done&&rt1[i]!=0)
4820 rjump_assemble_write_ra(i);
57871462 4821 cc=get_reg(branch_regs[i].regmap,CCREG);
4822 assert(cc==HOST_CCREG);
581335b0 4823 (void)cc;
57871462 4824 #ifdef USE_MINI_HT
4825 int rh=get_reg(branch_regs[i].regmap,RHASH);
4826 int ht=get_reg(branch_regs[i].regmap,RHTBL);
4827 if(rs1[i]==31) {
4828 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
4829 do_preload_rhtbl(ht);
4830 do_rhash(rs,rh);
4831 }
4832 #endif
4833 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
4834 #ifdef DESTRUCTIVE_WRITEBACK
4835 if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
4836 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
4837 emit_loadreg(rs1[i],rs);
4838 }
4839 }
4840 #endif
4841 #ifdef REG_PREFETCH
4842 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
4843 #endif
4844 #ifdef USE_MINI_HT
4845 if(rs1[i]==31) {
4846 do_miniht_load(ht,rh);
4847 }
4848 #endif
4849 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
4850 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
4851 //assert(adj==0);
2573466a 4852 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
57871462 4853 add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
911f2d55 4854 if(itype[i+1]==COP0&&(source[i+1]&0x3f)==0x10)
4855 // special case for RFE
4856 emit_jmp(0);
4857 else
71e490c5 4858 emit_jns(0);
57871462 4859 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
4860 #ifdef USE_MINI_HT
4861 if(rs1[i]==31) {
4862 do_miniht_jump(rs,rh,ht);
4863 }
4864 else
4865 #endif
4866 {
4867 //if(rs!=EAX) emit_mov(rs,EAX);
4868 //emit_jmp((int)jump_vaddr_eax);
4869 emit_jmp(jump_vaddr_reg[rs]);
4870 }
4871 /* Check hash table
4872 temp=!rs;
4873 emit_mov(rs,temp);
4874 emit_shrimm(rs,16,rs);
4875 emit_xor(temp,rs,rs);
4876 emit_movzwl_reg(rs,rs);
4877 emit_shlimm(rs,4,rs);
4878 emit_cmpmem_indexed((int)hash_table,rs,temp);
4879 emit_jne((int)out+14);
4880 emit_readword_indexed((int)hash_table+4,rs,rs);
4881 emit_jmpreg(rs);
4882 emit_cmpmem_indexed((int)hash_table+8,rs,temp);
4883 emit_addimm_no_flags(8,rs);
4884 emit_jeq((int)out-17);
4885 // No hit on hash table, call compiler
4886 emit_pushreg(temp);
4887//DEBUG >
4888#ifdef DEBUG_CYCLE_COUNT
4889 emit_readword((int)&last_count,ECX);
4890 emit_add(HOST_CCREG,ECX,HOST_CCREG);
4891 emit_readword((int)&next_interupt,ECX);
4892 emit_writeword(HOST_CCREG,(int)&Count);
4893 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
4894 emit_writeword(ECX,(int)&last_count);
4895#endif
4896//DEBUG <
4897 emit_storereg(CCREG,HOST_CCREG);
4898 emit_call((int)get_addr);
4899 emit_loadreg(CCREG,HOST_CCREG);
4900 emit_addimm(ESP,4,ESP);
4901 emit_jmpreg(EAX);*/
4902 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
4903 if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
4904 #endif
4905}
4906
4907void cjump_assemble(int i,struct regstat *i_regs)
4908{
4909 signed char *i_regmap=i_regs->regmap;
4910 int cc;
4911 int match;
4912 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4913 assem_debug("match=%d\n",match);
4914 int s1h,s1l,s2h,s2l;
4915 int prev_cop1_usable=cop1_usable;
4916 int unconditional=0,nop=0;
4917 int only32=0;
57871462 4918 int invert=0;
4919 int internal=internal_branch(branch_regs[i].is32,ba[i]);
4920 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 4921 if(!match) invert=1;
4922 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
4923 if(i>(ba[i]-start)>>2) invert=1;
4924 #endif
9f51b4b9 4925
e1190b87 4926 if(ooo[i]) {
57871462 4927 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4928 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4929 s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4930 s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4931 }
4932 else {
4933 s1l=get_reg(i_regmap,rs1[i]);
4934 s1h=get_reg(i_regmap,rs1[i]|64);
4935 s2l=get_reg(i_regmap,rs2[i]);
4936 s2h=get_reg(i_regmap,rs2[i]|64);
4937 }
4938 if(rs1[i]==0&&rs2[i]==0)
4939 {
4940 if(opcode[i]&1) nop=1;
4941 else unconditional=1;
4942 //assert(opcode[i]!=5);
4943 //assert(opcode[i]!=7);
4944 //assert(opcode[i]!=0x15);
4945 //assert(opcode[i]!=0x17);
4946 }
4947 else if(rs1[i]==0)
4948 {
4949 s1l=s2l;s1h=s2h;
4950 s2l=s2h=-1;
4951 only32=(regs[i].was32>>rs2[i])&1;
4952 }
4953 else if(rs2[i]==0)
4954 {
4955 s2l=s2h=-1;
4956 only32=(regs[i].was32>>rs1[i])&1;
4957 }
4958 else {
4959 only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
4960 }
4961
e1190b87 4962 if(ooo[i]) {
57871462 4963 // Out of order execution (delay slot first)
4964 //printf("OOOE\n");
4965 address_generation(i+1,i_regs,regs[i].regmap_entry);
4966 ds_assemble(i+1,i_regs);
4967 int adj;
4968 uint64_t bc_unneeded=branch_regs[i].u;
4969 uint64_t bc_unneeded_upper=branch_regs[i].uu;
4970 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
4971 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
4972 bc_unneeded|=1;
4973 bc_unneeded_upper|=1;
4974 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
4975 bc_unneeded,bc_unneeded_upper);
4976 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
4977 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
4978 cc=get_reg(branch_regs[i].regmap,CCREG);
4979 assert(cc==HOST_CCREG);
9f51b4b9 4980 if(unconditional)
57871462 4981 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4982 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
4983 //assem_debug("cycle count (adj)\n");
4984 if(unconditional) {
4985 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
4986 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
2573466a 4987 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
57871462 4988 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4989 if(internal)
4990 assem_debug("branch: internal\n");
4991 else
4992 assem_debug("branch: external\n");
4993 if(internal&&is_ds[(ba[i]-start)>>2]) {
4994 ds_assemble_entry(i);
4995 }
4996 else {
4997 add_to_linker((int)out,ba[i],internal);
4998 emit_jmp(0);
4999 }
5000 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5001 if(((u_int)out)&7) emit_addnop(0);
5002 #endif
5003 }
5004 }
5005 else if(nop) {
2573466a 5006 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
57871462 5007 int jaddr=(int)out;
5008 emit_jns(0);
5009 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5010 }
5011 else {
5012 int taken=0,nottaken=0,nottaken1=0;
5013 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
2573466a 5014 if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
57871462 5015 if(!only32)
5016 {
5017 assert(s1h>=0);
5018 if(opcode[i]==4) // BEQ
5019 {
5020 if(s2h>=0) emit_cmp(s1h,s2h);
5021 else emit_test(s1h,s1h);
5022 nottaken1=(int)out;
5023 emit_jne(1);
5024 }
5025 if(opcode[i]==5) // BNE
5026 {
5027 if(s2h>=0) emit_cmp(s1h,s2h);
5028 else emit_test(s1h,s1h);
5029 if(invert) taken=(int)out;
5030 else add_to_linker((int)out,ba[i],internal);
5031 emit_jne(0);
5032 }
5033 if(opcode[i]==6) // BLEZ
5034 {
5035 emit_test(s1h,s1h);
5036 if(invert) taken=(int)out;
5037 else add_to_linker((int)out,ba[i],internal);
5038 emit_js(0);
5039 nottaken1=(int)out;
5040 emit_jne(1);
5041 }
5042 if(opcode[i]==7) // BGTZ
5043 {
5044 emit_test(s1h,s1h);
5045 nottaken1=(int)out;
5046 emit_js(1);
5047 if(invert) taken=(int)out;
5048 else add_to_linker((int)out,ba[i],internal);
5049 emit_jne(0);
5050 }
5051 } // if(!only32)
9f51b4b9 5052
57871462 5053 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5054 assert(s1l>=0);
5055 if(opcode[i]==4) // BEQ
5056 {
5057 if(s2l>=0) emit_cmp(s1l,s2l);
5058 else emit_test(s1l,s1l);
5059 if(invert){
5060 nottaken=(int)out;
5061 emit_jne(1);
5062 }else{
5063 add_to_linker((int)out,ba[i],internal);
5064 emit_jeq(0);
5065 }
5066 }
5067 if(opcode[i]==5) // BNE
5068 {
5069 if(s2l>=0) emit_cmp(s1l,s2l);
5070 else emit_test(s1l,s1l);
5071 if(invert){
5072 nottaken=(int)out;
5073 emit_jeq(1);
5074 }else{
5075 add_to_linker((int)out,ba[i],internal);
5076 emit_jne(0);
5077 }
5078 }
5079 if(opcode[i]==6) // BLEZ
5080 {
5081 emit_cmpimm(s1l,1);
5082 if(invert){
5083 nottaken=(int)out;
5084 emit_jge(1);
5085 }else{
5086 add_to_linker((int)out,ba[i],internal);
5087 emit_jl(0);
5088 }
5089 }
5090 if(opcode[i]==7) // BGTZ
5091 {
5092 emit_cmpimm(s1l,1);
5093 if(invert){
5094 nottaken=(int)out;
5095 emit_jl(1);
5096 }else{
5097 add_to_linker((int)out,ba[i],internal);
5098 emit_jge(0);
5099 }
5100 }
5101 if(invert) {
5102 if(taken) set_jump_target(taken,(int)out);
5103 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5104 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5105 if(adj) {
2573466a 5106 emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
57871462 5107 add_to_linker((int)out,ba[i],internal);
5108 }else{
5109 emit_addnop(13);
5110 add_to_linker((int)out,ba[i],internal*2);
5111 }
5112 emit_jmp(0);
5113 }else
5114 #endif
5115 {
2573466a 5116 if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
57871462 5117 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5118 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5119 if(internal)
5120 assem_debug("branch: internal\n");
5121 else
5122 assem_debug("branch: external\n");
5123 if(internal&&is_ds[(ba[i]-start)>>2]) {
5124 ds_assemble_entry(i);
5125 }
5126 else {
5127 add_to_linker((int)out,ba[i],internal);
5128 emit_jmp(0);
5129 }
5130 }
5131 set_jump_target(nottaken,(int)out);
5132 }
5133
5134 if(nottaken1) set_jump_target(nottaken1,(int)out);
5135 if(adj) {
2573466a 5136 if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
57871462 5137 }
5138 } // (!unconditional)
5139 } // if(ooo)
5140 else
5141 {
5142 // In-order execution (branch first)
5143 //if(likely[i]) printf("IOL\n");
5144 //else
5145 //printf("IOE\n");
5146 int taken=0,nottaken=0,nottaken1=0;
5147 if(!unconditional&&!nop) {
5148 if(!only32)
5149 {
5150 assert(s1h>=0);
5151 if((opcode[i]&0x2f)==4) // BEQ
5152 {
5153 if(s2h>=0) emit_cmp(s1h,s2h);
5154 else emit_test(s1h,s1h);
5155 nottaken1=(int)out;
5156 emit_jne(2);
5157 }
5158 if((opcode[i]&0x2f)==5) // BNE
5159 {
5160 if(s2h>=0) emit_cmp(s1h,s2h);
5161 else emit_test(s1h,s1h);
5162 taken=(int)out;
5163 emit_jne(1);
5164 }
5165 if((opcode[i]&0x2f)==6) // BLEZ
5166 {
5167 emit_test(s1h,s1h);
5168 taken=(int)out;
5169 emit_js(1);
5170 nottaken1=(int)out;
5171 emit_jne(2);
5172 }
5173 if((opcode[i]&0x2f)==7) // BGTZ
5174 {
5175 emit_test(s1h,s1h);
5176 nottaken1=(int)out;
5177 emit_js(2);
5178 taken=(int)out;
5179 emit_jne(1);
5180 }
5181 } // if(!only32)
9f51b4b9 5182
57871462 5183 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5184 assert(s1l>=0);
5185 if((opcode[i]&0x2f)==4) // BEQ
5186 {
5187 if(s2l>=0) emit_cmp(s1l,s2l);
5188 else emit_test(s1l,s1l);
5189 nottaken=(int)out;
5190 emit_jne(2);
5191 }
5192 if((opcode[i]&0x2f)==5) // BNE
5193 {
5194 if(s2l>=0) emit_cmp(s1l,s2l);
5195 else emit_test(s1l,s1l);
5196 nottaken=(int)out;
5197 emit_jeq(2);
5198 }
5199 if((opcode[i]&0x2f)==6) // BLEZ
5200 {
5201 emit_cmpimm(s1l,1);
5202 nottaken=(int)out;
5203 emit_jge(2);
5204 }
5205 if((opcode[i]&0x2f)==7) // BGTZ
5206 {
5207 emit_cmpimm(s1l,1);
5208 nottaken=(int)out;
5209 emit_jl(2);
5210 }
5211 } // if(!unconditional)
5212 int adj;
5213 uint64_t ds_unneeded=branch_regs[i].u;
5214 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5215 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5216 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5217 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5218 ds_unneeded|=1;
5219 ds_unneeded_upper|=1;
5220 // branch taken
5221 if(!nop) {
5222 if(taken) set_jump_target(taken,(int)out);
5223 assem_debug("1:\n");
5224 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5225 ds_unneeded,ds_unneeded_upper);
5226 // load regs
5227 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5228 address_generation(i+1,&branch_regs[i],0);
5229 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5230 ds_assemble(i+1,&branch_regs[i]);
5231 cc=get_reg(branch_regs[i].regmap,CCREG);
5232 if(cc==-1) {
5233 emit_loadreg(CCREG,cc=HOST_CCREG);
5234 // CHECK: Is the following instruction (fall thru) allocated ok?
5235 }
5236 assert(cc==HOST_CCREG);
5237 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5238 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5239 assem_debug("cycle count (adj)\n");
2573466a 5240 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
57871462 5241 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5242 if(internal)
5243 assem_debug("branch: internal\n");
5244 else
5245 assem_debug("branch: external\n");
5246 if(internal&&is_ds[(ba[i]-start)>>2]) {
5247 ds_assemble_entry(i);
5248 }
5249 else {
5250 add_to_linker((int)out,ba[i],internal);
5251 emit_jmp(0);
5252 }
5253 }
5254 // branch not taken
5255 cop1_usable=prev_cop1_usable;
5256 if(!unconditional) {
5257 if(nottaken1) set_jump_target(nottaken1,(int)out);
5258 set_jump_target(nottaken,(int)out);
5259 assem_debug("2:\n");
5260 if(!likely[i]) {
5261 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5262 ds_unneeded,ds_unneeded_upper);
5263 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5264 address_generation(i+1,&branch_regs[i],0);
5265 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5266 ds_assemble(i+1,&branch_regs[i]);
5267 }
5268 cc=get_reg(branch_regs[i].regmap,CCREG);
5269 if(cc==-1&&!likely[i]) {
5270 // Cycle count isn't in a register, temporarily load it then write it out
5271 emit_loadreg(CCREG,HOST_CCREG);
2573466a 5272 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
57871462 5273 int jaddr=(int)out;
5274 emit_jns(0);
5275 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5276 emit_storereg(CCREG,HOST_CCREG);
5277 }
5278 else{
5279 cc=get_reg(i_regmap,CCREG);
5280 assert(cc==HOST_CCREG);
2573466a 5281 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
57871462 5282 int jaddr=(int)out;
5283 emit_jns(0);
5284 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5285 }
5286 }
5287 }
5288}
5289
5290void sjump_assemble(int i,struct regstat *i_regs)
5291{
5292 signed char *i_regmap=i_regs->regmap;
5293 int cc;
5294 int match;
5295 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5296 assem_debug("smatch=%d\n",match);
5297 int s1h,s1l;
5298 int prev_cop1_usable=cop1_usable;
5299 int unconditional=0,nevertaken=0;
5300 int only32=0;
57871462 5301 int invert=0;
5302 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5303 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 5304 if(!match) invert=1;
5305 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5306 if(i>(ba[i]-start)>>2) invert=1;
5307 #endif
5308
5309 //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
df894a3a 5310 //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
57871462 5311
e1190b87 5312 if(ooo[i]) {
57871462 5313 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5314 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5315 }
5316 else {
5317 s1l=get_reg(i_regmap,rs1[i]);
5318 s1h=get_reg(i_regmap,rs1[i]|64);
5319 }
5320 if(rs1[i]==0)
5321 {
5322 if(opcode2[i]&1) unconditional=1;
5323 else nevertaken=1;
5324 // These are never taken (r0 is never less than zero)
5325 //assert(opcode2[i]!=0);
5326 //assert(opcode2[i]!=2);
5327 //assert(opcode2[i]!=0x10);
5328 //assert(opcode2[i]!=0x12);
5329 }
5330 else {
5331 only32=(regs[i].was32>>rs1[i])&1;
5332 }
5333
e1190b87 5334 if(ooo[i]) {
57871462 5335 // Out of order execution (delay slot first)
5336 //printf("OOOE\n");
5337 address_generation(i+1,i_regs,regs[i].regmap_entry);
5338 ds_assemble(i+1,i_regs);
5339 int adj;
5340 uint64_t bc_unneeded=branch_regs[i].u;
5341 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5342 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5343 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5344 bc_unneeded|=1;
5345 bc_unneeded_upper|=1;
5346 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5347 bc_unneeded,bc_unneeded_upper);
5348 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5349 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5350 if(rt1[i]==31) {
5351 int rt,return_address;
57871462 5352 rt=get_reg(branch_regs[i].regmap,31);
5353 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5354 if(rt>=0) {
5355 // Save the PC even if the branch is not taken
5356 return_address=start+i*4+8;
5357 emit_movimm(return_address,rt); // PC into link register
5358 #ifdef IMM_PREFETCH
5359 if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5360 #endif
5361 }
5362 }
5363 cc=get_reg(branch_regs[i].regmap,CCREG);
5364 assert(cc==HOST_CCREG);
9f51b4b9 5365 if(unconditional)
57871462 5366 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5367 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5368 assem_debug("cycle count (adj)\n");
5369 if(unconditional) {
5370 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5371 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
2573466a 5372 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
57871462 5373 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5374 if(internal)
5375 assem_debug("branch: internal\n");
5376 else
5377 assem_debug("branch: external\n");
5378 if(internal&&is_ds[(ba[i]-start)>>2]) {
5379 ds_assemble_entry(i);
5380 }
5381 else {
5382 add_to_linker((int)out,ba[i],internal);
5383 emit_jmp(0);
5384 }
5385 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5386 if(((u_int)out)&7) emit_addnop(0);
5387 #endif
5388 }
5389 }
5390 else if(nevertaken) {
2573466a 5391 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
57871462 5392 int jaddr=(int)out;
5393 emit_jns(0);
5394 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5395 }
5396 else {
5397 int nottaken=0;
5398 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
2573466a 5399 if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
57871462 5400 if(!only32)
5401 {
5402 assert(s1h>=0);
df894a3a 5403 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
57871462 5404 {
5405 emit_test(s1h,s1h);
5406 if(invert){
5407 nottaken=(int)out;
5408 emit_jns(1);
5409 }else{
5410 add_to_linker((int)out,ba[i],internal);
5411 emit_js(0);
5412 }
5413 }
df894a3a 5414 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
57871462 5415 {
5416 emit_test(s1h,s1h);
5417 if(invert){
5418 nottaken=(int)out;
5419 emit_js(1);
5420 }else{
5421 add_to_linker((int)out,ba[i],internal);
5422 emit_jns(0);
5423 }
5424 }
5425 } // if(!only32)
5426 else
5427 {
5428 assert(s1l>=0);
df894a3a 5429 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
57871462 5430 {
5431 emit_test(s1l,s1l);
5432 if(invert){
5433 nottaken=(int)out;
5434 emit_jns(1);
5435 }else{
5436 add_to_linker((int)out,ba[i],internal);
5437 emit_js(0);
5438 }
5439 }
df894a3a 5440 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
57871462 5441 {
5442 emit_test(s1l,s1l);
5443 if(invert){
5444 nottaken=(int)out;
5445 emit_js(1);
5446 }else{
5447 add_to_linker((int)out,ba[i],internal);
5448 emit_jns(0);
5449 }
5450 }
5451 } // if(!only32)
9f51b4b9 5452
57871462 5453 if(invert) {
5454 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5455 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5456 if(adj) {
2573466a 5457 emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
57871462 5458 add_to_linker((int)out,ba[i],internal);
5459 }else{
5460 emit_addnop(13);
5461 add_to_linker((int)out,ba[i],internal*2);
5462 }
5463 emit_jmp(0);
5464 }else
5465 #endif
5466 {
2573466a 5467 if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
57871462 5468 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5469 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5470 if(internal)
5471 assem_debug("branch: internal\n");
5472 else
5473 assem_debug("branch: external\n");
5474 if(internal&&is_ds[(ba[i]-start)>>2]) {
5475 ds_assemble_entry(i);
5476 }
5477 else {
5478 add_to_linker((int)out,ba[i],internal);
5479 emit_jmp(0);
5480 }
5481 }
5482 set_jump_target(nottaken,(int)out);
5483 }
5484
5485 if(adj) {
2573466a 5486 if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
57871462 5487 }
5488 } // (!unconditional)
5489 } // if(ooo)
5490 else
5491 {
5492 // In-order execution (branch first)
5493 //printf("IOE\n");
5494 int nottaken=0;
a6491170 5495 if(rt1[i]==31) {
5496 int rt,return_address;
a6491170 5497 rt=get_reg(branch_regs[i].regmap,31);
5498 if(rt>=0) {
5499 // Save the PC even if the branch is not taken
5500 return_address=start+i*4+8;
5501 emit_movimm(return_address,rt); // PC into link register
5502 #ifdef IMM_PREFETCH
5503 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5504 #endif
5505 }
5506 }
57871462 5507 if(!unconditional) {
5508 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5509 if(!only32)
5510 {
5511 assert(s1h>=0);
a6491170 5512 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
57871462 5513 {
5514 emit_test(s1h,s1h);
5515 nottaken=(int)out;
5516 emit_jns(1);
5517 }
a6491170 5518 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
57871462 5519 {
5520 emit_test(s1h,s1h);
5521 nottaken=(int)out;
5522 emit_js(1);
5523 }
5524 } // if(!only32)
5525 else
5526 {
5527 assert(s1l>=0);
a6491170 5528 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
57871462 5529 {
5530 emit_test(s1l,s1l);
5531 nottaken=(int)out;
5532 emit_jns(1);
5533 }
a6491170 5534 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
57871462 5535 {
5536 emit_test(s1l,s1l);
5537 nottaken=(int)out;
5538 emit_js(1);
5539 }
5540 }
5541 } // if(!unconditional)
5542 int adj;
5543 uint64_t ds_unneeded=branch_regs[i].u;
5544 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5545 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5546 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5547 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5548 ds_unneeded|=1;
5549 ds_unneeded_upper|=1;
5550 // branch taken
5551 if(!nevertaken) {
5552 //assem_debug("1:\n");
5553 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5554 ds_unneeded,ds_unneeded_upper);
5555 // load regs
5556 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5557 address_generation(i+1,&branch_regs[i],0);
5558 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5559 ds_assemble(i+1,&branch_regs[i]);
5560 cc=get_reg(branch_regs[i].regmap,CCREG);
5561 if(cc==-1) {
5562 emit_loadreg(CCREG,cc=HOST_CCREG);
5563 // CHECK: Is the following instruction (fall thru) allocated ok?
5564 }
5565 assert(cc==HOST_CCREG);
5566 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5567 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5568 assem_debug("cycle count (adj)\n");
2573466a 5569 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
57871462 5570 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5571 if(internal)
5572 assem_debug("branch: internal\n");
5573 else
5574 assem_debug("branch: external\n");
5575 if(internal&&is_ds[(ba[i]-start)>>2]) {
5576 ds_assemble_entry(i);
5577 }
5578 else {
5579 add_to_linker((int)out,ba[i],internal);
5580 emit_jmp(0);
5581 }
5582 }
5583 // branch not taken
5584 cop1_usable=prev_cop1_usable;
5585 if(!unconditional) {
5586 set_jump_target(nottaken,(int)out);
5587 assem_debug("1:\n");
5588 if(!likely[i]) {
5589 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5590 ds_unneeded,ds_unneeded_upper);
5591 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5592 address_generation(i+1,&branch_regs[i],0);
5593 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5594 ds_assemble(i+1,&branch_regs[i]);
5595 }
5596 cc=get_reg(branch_regs[i].regmap,CCREG);
5597 if(cc==-1&&!likely[i]) {
5598 // Cycle count isn't in a register, temporarily load it then write it out
5599 emit_loadreg(CCREG,HOST_CCREG);
2573466a 5600 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
57871462 5601 int jaddr=(int)out;
5602 emit_jns(0);
5603 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5604 emit_storereg(CCREG,HOST_CCREG);
5605 }
5606 else{
5607 cc=get_reg(i_regmap,CCREG);
5608 assert(cc==HOST_CCREG);
2573466a 5609 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
57871462 5610 int jaddr=(int)out;
5611 emit_jns(0);
5612 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5613 }
5614 }
5615 }
5616}
5617
5618void fjump_assemble(int i,struct regstat *i_regs)
5619{
5620 signed char *i_regmap=i_regs->regmap;
5621 int cc;
5622 int match;
5623 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5624 assem_debug("fmatch=%d\n",match);
5625 int fs,cs;
5626 int eaddr;
57871462 5627 int invert=0;
5628 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5629 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 5630 if(!match) invert=1;
5631 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5632 if(i>(ba[i]-start)>>2) invert=1;
5633 #endif
5634
e1190b87 5635 if(ooo[i]) {
57871462 5636 fs=get_reg(branch_regs[i].regmap,FSREG);
5637 address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
5638 }
5639 else {
5640 fs=get_reg(i_regmap,FSREG);
5641 }
5642
5643 // Check cop1 unusable
5644 if(!cop1_usable) {
5645 cs=get_reg(i_regmap,CSREG);
5646 assert(cs>=0);
5647 emit_testimm(cs,0x20000000);
5648 eaddr=(int)out;
5649 emit_jeq(0);
5650 add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
5651 cop1_usable=1;
5652 }
5653
e1190b87 5654 if(ooo[i]) {
57871462 5655 // Out of order execution (delay slot first)
5656 //printf("OOOE\n");
5657 ds_assemble(i+1,i_regs);
5658 int adj;
5659 uint64_t bc_unneeded=branch_regs[i].u;
5660 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5661 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5662 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5663 bc_unneeded|=1;
5664 bc_unneeded_upper|=1;
5665 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5666 bc_unneeded,bc_unneeded_upper);
5667 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5668 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5669 cc=get_reg(branch_regs[i].regmap,CCREG);
5670 assert(cc==HOST_CCREG);
5671 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5672 assem_debug("cycle count (adj)\n");
5673 if(1) {
5674 int nottaken=0;
2573466a 5675 if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
57871462 5676 if(1) {
5677 assert(fs>=0);
5678 emit_testimm(fs,0x800000);
5679 if(source[i]&0x10000) // BC1T
5680 {
5681 if(invert){
5682 nottaken=(int)out;
5683 emit_jeq(1);
5684 }else{
5685 add_to_linker((int)out,ba[i],internal);
5686 emit_jne(0);
5687 }
5688 }
5689 else // BC1F
5690 if(invert){
5691 nottaken=(int)out;
5692 emit_jne(1);
5693 }else{
5694 add_to_linker((int)out,ba[i],internal);
5695 emit_jeq(0);
5696 }
5697 {
5698 }
5699 } // if(!only32)
9f51b4b9 5700
57871462 5701 if(invert) {
2573466a 5702 if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
57871462 5703 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5704 else if(match) emit_addnop(13);
5705 #endif
5706 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5707 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5708 if(internal)
5709 assem_debug("branch: internal\n");
5710 else
5711 assem_debug("branch: external\n");
5712 if(internal&&is_ds[(ba[i]-start)>>2]) {
5713 ds_assemble_entry(i);
5714 }
5715 else {
5716 add_to_linker((int)out,ba[i],internal);
5717 emit_jmp(0);
5718 }
5719 set_jump_target(nottaken,(int)out);
5720 }
5721
5722 if(adj) {
2573466a 5723 if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
57871462 5724 }
5725 } // (!unconditional)
5726 } // if(ooo)
5727 else
5728 {
5729 // In-order execution (branch first)
5730 //printf("IOE\n");
5731 int nottaken=0;
5732 if(1) {
5733 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5734 if(1) {
5735 assert(fs>=0);
5736 emit_testimm(fs,0x800000);
5737 if(source[i]&0x10000) // BC1T
5738 {
5739 nottaken=(int)out;
5740 emit_jeq(1);
5741 }
5742 else // BC1F
5743 {
5744 nottaken=(int)out;
5745 emit_jne(1);
5746 }
5747 }
5748 } // if(!unconditional)
5749 int adj;
5750 uint64_t ds_unneeded=branch_regs[i].u;
5751 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5752 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5753 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5754 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5755 ds_unneeded|=1;
5756 ds_unneeded_upper|=1;
5757 // branch taken
5758 //assem_debug("1:\n");
5759 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5760 ds_unneeded,ds_unneeded_upper);
5761 // load regs
5762 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5763 address_generation(i+1,&branch_regs[i],0);
5764 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5765 ds_assemble(i+1,&branch_regs[i]);
5766 cc=get_reg(branch_regs[i].regmap,CCREG);
5767 if(cc==-1) {
5768 emit_loadreg(CCREG,cc=HOST_CCREG);
5769 // CHECK: Is the following instruction (fall thru) allocated ok?
5770 }
5771 assert(cc==HOST_CCREG);
5772 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5773 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5774 assem_debug("cycle count (adj)\n");
2573466a 5775 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
57871462 5776 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5777 if(internal)
5778 assem_debug("branch: internal\n");
5779 else
5780 assem_debug("branch: external\n");
5781 if(internal&&is_ds[(ba[i]-start)>>2]) {
5782 ds_assemble_entry(i);
5783 }
5784 else {
5785 add_to_linker((int)out,ba[i],internal);
5786 emit_jmp(0);
5787 }
5788
5789 // branch not taken
5790 if(1) { // <- FIXME (don't need this)
5791 set_jump_target(nottaken,(int)out);
5792 assem_debug("1:\n");
5793 if(!likely[i]) {
5794 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5795 ds_unneeded,ds_unneeded_upper);
5796 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5797 address_generation(i+1,&branch_regs[i],0);
5798 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5799 ds_assemble(i+1,&branch_regs[i]);
5800 }
5801 cc=get_reg(branch_regs[i].regmap,CCREG);
5802 if(cc==-1&&!likely[i]) {
5803 // Cycle count isn't in a register, temporarily load it then write it out
5804 emit_loadreg(CCREG,HOST_CCREG);
2573466a 5805 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
57871462 5806 int jaddr=(int)out;
5807 emit_jns(0);
5808 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5809 emit_storereg(CCREG,HOST_CCREG);
5810 }
5811 else{
5812 cc=get_reg(i_regmap,CCREG);
5813 assert(cc==HOST_CCREG);
2573466a 5814 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
57871462 5815 int jaddr=(int)out;
5816 emit_jns(0);
5817 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5818 }
5819 }
5820 }
5821}
5822
5823static void pagespan_assemble(int i,struct regstat *i_regs)
5824{
5825 int s1l=get_reg(i_regs->regmap,rs1[i]);
5826 int s1h=get_reg(i_regs->regmap,rs1[i]|64);
5827 int s2l=get_reg(i_regs->regmap,rs2[i]);
5828 int s2h=get_reg(i_regs->regmap,rs2[i]|64);
57871462 5829 int taken=0;
5830 int nottaken=0;
5831 int unconditional=0;
5832 if(rs1[i]==0)
5833 {
5834 s1l=s2l;s1h=s2h;
5835 s2l=s2h=-1;
5836 }
5837 else if(rs2[i]==0)
5838 {
5839 s2l=s2h=-1;
5840 }
5841 if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
5842 s1h=s2h=-1;
5843 }
5844 int hr=0;
581335b0 5845 int addr=-1,alt=-1,ntaddr=-1;
57871462 5846 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
5847 else {
5848 while(hr<HOST_REGS)
5849 {
5850 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5851 (i_regs->regmap[hr]&63)!=rs1[i] &&
5852 (i_regs->regmap[hr]&63)!=rs2[i] )
5853 {
5854 addr=hr++;break;
5855 }
5856 hr++;
5857 }
5858 }
5859 while(hr<HOST_REGS)
5860 {
5861 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
5862 (i_regs->regmap[hr]&63)!=rs1[i] &&
5863 (i_regs->regmap[hr]&63)!=rs2[i] )
5864 {
5865 alt=hr++;break;
5866 }
5867 hr++;
5868 }
5869 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
5870 {
5871 while(hr<HOST_REGS)
5872 {
5873 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
5874 (i_regs->regmap[hr]&63)!=rs1[i] &&
5875 (i_regs->regmap[hr]&63)!=rs2[i] )
5876 {
5877 ntaddr=hr;break;
5878 }
5879 hr++;
5880 }
5881 }
5882 assert(hr<HOST_REGS);
5883 if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
5884 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
5885 }
2573466a 5886 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
57871462 5887 if(opcode[i]==2) // J
5888 {
5889 unconditional=1;
5890 }
5891 if(opcode[i]==3) // JAL
5892 {
5893 // TODO: mini_ht
5894 int rt=get_reg(i_regs->regmap,31);
5895 emit_movimm(start+i*4+8,rt);
5896 unconditional=1;
5897 }
5898 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
5899 {
5900 emit_mov(s1l,addr);
5901 if(opcode2[i]==9) // JALR
5902 {
5067f341 5903 int rt=get_reg(i_regs->regmap,rt1[i]);
57871462 5904 emit_movimm(start+i*4+8,rt);
5905 }
5906 }
5907 if((opcode[i]&0x3f)==4) // BEQ
5908 {
5909 if(rs1[i]==rs2[i])
5910 {
5911 unconditional=1;
5912 }
5913 else
5914 #ifdef HAVE_CMOV_IMM
5915 if(s1h<0) {
5916 if(s2l>=0) emit_cmp(s1l,s2l);
5917 else emit_test(s1l,s1l);
5918 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5919 }
5920 else
5921 #endif
5922 {
5923 assert(s1l>=0);
5924 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5925 if(s1h>=0) {
5926 if(s2h>=0) emit_cmp(s1h,s2h);
5927 else emit_test(s1h,s1h);
5928 emit_cmovne_reg(alt,addr);
5929 }
5930 if(s2l>=0) emit_cmp(s1l,s2l);
5931 else emit_test(s1l,s1l);
5932 emit_cmovne_reg(alt,addr);
5933 }
5934 }
5935 if((opcode[i]&0x3f)==5) // BNE
5936 {
5937 #ifdef HAVE_CMOV_IMM
5938 if(s1h<0) {
5939 if(s2l>=0) emit_cmp(s1l,s2l);
5940 else emit_test(s1l,s1l);
5941 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5942 }
5943 else
5944 #endif
5945 {
5946 assert(s1l>=0);
5947 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5948 if(s1h>=0) {
5949 if(s2h>=0) emit_cmp(s1h,s2h);
5950 else emit_test(s1h,s1h);
5951 emit_cmovne_reg(alt,addr);
5952 }
5953 if(s2l>=0) emit_cmp(s1l,s2l);
5954 else emit_test(s1l,s1l);
5955 emit_cmovne_reg(alt,addr);
5956 }
5957 }
5958 if((opcode[i]&0x3f)==0x14) // BEQL
5959 {
5960 if(s1h>=0) {
5961 if(s2h>=0) emit_cmp(s1h,s2h);
5962 else emit_test(s1h,s1h);
5963 nottaken=(int)out;
5964 emit_jne(0);
5965 }
5966 if(s2l>=0) emit_cmp(s1l,s2l);
5967 else emit_test(s1l,s1l);
5968 if(nottaken) set_jump_target(nottaken,(int)out);
5969 nottaken=(int)out;
5970 emit_jne(0);
5971 }
5972 if((opcode[i]&0x3f)==0x15) // BNEL
5973 {
5974 if(s1h>=0) {
5975 if(s2h>=0) emit_cmp(s1h,s2h);
5976 else emit_test(s1h,s1h);
5977 taken=(int)out;
5978 emit_jne(0);
5979 }
5980 if(s2l>=0) emit_cmp(s1l,s2l);
5981 else emit_test(s1l,s1l);
5982 nottaken=(int)out;
5983 emit_jeq(0);
5984 if(taken) set_jump_target(taken,(int)out);
5985 }
5986 if((opcode[i]&0x3f)==6) // BLEZ
5987 {
5988 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5989 emit_cmpimm(s1l,1);
5990 if(s1h>=0) emit_mov(addr,ntaddr);
5991 emit_cmovl_reg(alt,addr);
5992 if(s1h>=0) {
5993 emit_test(s1h,s1h);
5994 emit_cmovne_reg(ntaddr,addr);
5995 emit_cmovs_reg(alt,addr);
5996 }
5997 }
5998 if((opcode[i]&0x3f)==7) // BGTZ
5999 {
6000 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6001 emit_cmpimm(s1l,1);
6002 if(s1h>=0) emit_mov(addr,alt);
6003 emit_cmovl_reg(ntaddr,addr);
6004 if(s1h>=0) {
6005 emit_test(s1h,s1h);
6006 emit_cmovne_reg(alt,addr);
6007 emit_cmovs_reg(ntaddr,addr);
6008 }
6009 }
6010 if((opcode[i]&0x3f)==0x16) // BLEZL
6011 {
6012 assert((opcode[i]&0x3f)!=0x16);
6013 }
6014 if((opcode[i]&0x3f)==0x17) // BGTZL
6015 {
6016 assert((opcode[i]&0x3f)!=0x17);
6017 }
6018 assert(opcode[i]!=1); // BLTZ/BGEZ
6019
6020 //FIXME: Check CSREG
6021 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6022 if((source[i]&0x30000)==0) // BC1F
6023 {
6024 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6025 emit_testimm(s1l,0x800000);
6026 emit_cmovne_reg(alt,addr);
6027 }
6028 if((source[i]&0x30000)==0x10000) // BC1T
6029 {
6030 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6031 emit_testimm(s1l,0x800000);
6032 emit_cmovne_reg(alt,addr);
6033 }
6034 if((source[i]&0x30000)==0x20000) // BC1FL
6035 {
6036 emit_testimm(s1l,0x800000);
6037 nottaken=(int)out;
6038 emit_jne(0);
6039 }
6040 if((source[i]&0x30000)==0x30000) // BC1TL
6041 {
6042 emit_testimm(s1l,0x800000);
6043 nottaken=(int)out;
6044 emit_jeq(0);
6045 }
6046 }
6047
6048 assert(i_regs->regmap[HOST_CCREG]==CCREG);
6049 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6050 if(likely[i]||unconditional)
6051 {
6052 emit_movimm(ba[i],HOST_BTREG);
6053 }
6054 else if(addr!=HOST_BTREG)
6055 {
6056 emit_mov(addr,HOST_BTREG);
6057 }
6058 void *branch_addr=out;
6059 emit_jmp(0);
6060 int target_addr=start+i*4+5;
6061 void *stub=out;
6062 void *compiled_target_addr=check_addr(target_addr);
6063 emit_extjump_ds((int)branch_addr,target_addr);
6064 if(compiled_target_addr) {
6065 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6066 add_link(target_addr,stub);
6067 }
6068 else set_jump_target((int)branch_addr,(int)stub);
6069 if(likely[i]) {
6070 // Not-taken path
6071 set_jump_target((int)nottaken,(int)out);
6072 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6073 void *branch_addr=out;
6074 emit_jmp(0);
6075 int target_addr=start+i*4+8;
6076 void *stub=out;
6077 void *compiled_target_addr=check_addr(target_addr);
6078 emit_extjump_ds((int)branch_addr,target_addr);
6079 if(compiled_target_addr) {
6080 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6081 add_link(target_addr,stub);
6082 }
6083 else set_jump_target((int)branch_addr,(int)stub);
6084 }
6085}
6086
6087// Assemble the delay slot for the above
6088static void pagespan_ds()
6089{
6090 assem_debug("initial delay slot:\n");
6091 u_int vaddr=start+1;
94d23bb9 6092 u_int page=get_page(vaddr);
6093 u_int vpage=get_vpage(vaddr);
57871462 6094 ll_add(jump_dirty+vpage,vaddr,(void *)out);
6095 do_dirty_stub_ds();
6096 ll_add(jump_in+page,vaddr,(void *)out);
6097 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6098 if(regs[0].regmap[HOST_CCREG]!=CCREG)
6099 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6100 if(regs[0].regmap[HOST_BTREG]!=BTREG)
6101 emit_writeword(HOST_BTREG,(int)&branch_target);
6102 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6103 address_generation(0,&regs[0],regs[0].regmap_entry);
b9b61529 6104 if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
57871462 6105 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6106 cop1_usable=0;
6107 is_delayslot=0;
6108 switch(itype[0]) {
6109 case ALU:
6110 alu_assemble(0,&regs[0]);break;
6111 case IMM16:
6112 imm16_assemble(0,&regs[0]);break;
6113 case SHIFT:
6114 shift_assemble(0,&regs[0]);break;
6115 case SHIFTIMM:
6116 shiftimm_assemble(0,&regs[0]);break;
6117 case LOAD:
6118 load_assemble(0,&regs[0]);break;
6119 case LOADLR:
6120 loadlr_assemble(0,&regs[0]);break;
6121 case STORE:
6122 store_assemble(0,&regs[0]);break;
6123 case STORELR:
6124 storelr_assemble(0,&regs[0]);break;
6125 case COP0:
6126 cop0_assemble(0,&regs[0]);break;
6127 case COP1:
6128 cop1_assemble(0,&regs[0]);break;
6129 case C1LS:
6130 c1ls_assemble(0,&regs[0]);break;
b9b61529 6131 case COP2:
6132 cop2_assemble(0,&regs[0]);break;
6133 case C2LS:
6134 c2ls_assemble(0,&regs[0]);break;
6135 case C2OP:
6136 c2op_assemble(0,&regs[0]);break;
57871462 6137 case FCONV:
6138 fconv_assemble(0,&regs[0]);break;
6139 case FLOAT:
6140 float_assemble(0,&regs[0]);break;
6141 case FCOMP:
6142 fcomp_assemble(0,&regs[0]);break;
6143 case MULTDIV:
6144 multdiv_assemble(0,&regs[0]);break;
6145 case MOV:
6146 mov_assemble(0,&regs[0]);break;
6147 case SYSCALL:
7139f3c8 6148 case HLECALL:
1e973cb0 6149 case INTCALL:
57871462 6150 case SPAN:
6151 case UJUMP:
6152 case RJUMP:
6153 case CJUMP:
6154 case SJUMP:
6155 case FJUMP:
c43b5311 6156 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
57871462 6157 }
6158 int btaddr=get_reg(regs[0].regmap,BTREG);
6159 if(btaddr<0) {
6160 btaddr=get_reg(regs[0].regmap,-1);
6161 emit_readword((int)&branch_target,btaddr);
6162 }
6163 assert(btaddr!=HOST_CCREG);
6164 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6165#ifdef HOST_IMM8
6166 emit_movimm(start+4,HOST_TEMPREG);
6167 emit_cmp(btaddr,HOST_TEMPREG);
6168#else
6169 emit_cmpimm(btaddr,start+4);
6170#endif
6171 int branch=(int)out;
6172 emit_jeq(0);
6173 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6174 emit_jmp(jump_vaddr_reg[btaddr]);
6175 set_jump_target(branch,(int)out);
6176 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6177 load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6178}
6179
6180// Basic liveness analysis for MIPS registers
6181void unneeded_registers(int istart,int iend,int r)
6182{
6183 int i;
bedfea38 6184 uint64_t u,uu,gte_u,b,bu,gte_bu;
0ff8c62c 6185 uint64_t temp_u,temp_uu,temp_gte_u=0;
57871462 6186 uint64_t tdep;
0ff8c62c 6187 uint64_t gte_u_unknown=0;
6188 if(new_dynarec_hacks&NDHACK_GTE_UNNEEDED)
6189 gte_u_unknown=~0ll;
57871462 6190 if(iend==slen-1) {
6191 u=1;uu=1;
0ff8c62c 6192 gte_u=gte_u_unknown;
57871462 6193 }else{
6194 u=unneeded_reg[iend+1];
6195 uu=unneeded_reg_upper[iend+1];
6196 u=1;uu=1;
0ff8c62c 6197 gte_u=gte_unneeded[iend+1];
57871462 6198 }
bedfea38 6199
57871462 6200 for (i=iend;i>=istart;i--)
6201 {
6202 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6203 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6204 {
6205 // If subroutine call, flag return address as a possible branch target
6206 if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
9f51b4b9 6207
57871462 6208 if(ba[i]<start || ba[i]>=(start+slen*4))
6209 {
6210 // Branch out of this block, flush all regs
6211 u=1;
6212 uu=1;
0ff8c62c 6213 gte_u=gte_u_unknown;
9f51b4b9 6214 /* Hexagon hack
57871462 6215 if(itype[i]==UJUMP&&rt1[i]==31)
6216 {
6217 uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6218 }
6219 if(itype[i]==RJUMP&&rs1[i]==31)
6220 {
6221 uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6222 }
4cb76aa4 6223 if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
57871462 6224 if(itype[i]==UJUMP&&rt1[i]==31)
6225 {
6226 //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6227 uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6228 }
6229 if(itype[i]==RJUMP&&rs1[i]==31)
6230 {
6231 //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6232 uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6233 }
6234 }*/
6235 branch_unneeded_reg[i]=u;
6236 branch_unneeded_reg_upper[i]=uu;
6237 // Merge in delay slot
6238 tdep=(~uu>>rt1[i+1])&1;
6239 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6240 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6241 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6242 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6243 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6244 u|=1;uu|=1;
bedfea38 6245 gte_u|=gte_rt[i+1];
6246 gte_u&=~gte_rs[i+1];
57871462 6247 // If branch is "likely" (and conditional)
6248 // then we skip the delay slot on the fall-thru path
6249 if(likely[i]) {
6250 if(i<slen-1) {
6251 u&=unneeded_reg[i+2];
6252 uu&=unneeded_reg_upper[i+2];
bedfea38 6253 gte_u&=gte_unneeded[i+2];
57871462 6254 }
6255 else
6256 {
6257 u=1;
6258 uu=1;
0ff8c62c 6259 gte_u=gte_u_unknown;
57871462 6260 }
6261 }
6262 }
6263 else
6264 {
6265 // Internal branch, flag target
6266 bt[(ba[i]-start)>>2]=1;
6267 if(ba[i]<=start+i*4) {
6268 // Backward branch
6269 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6270 {
6271 // Unconditional branch
6272 temp_u=1;temp_uu=1;
bedfea38 6273 temp_gte_u=0;
57871462 6274 } else {
6275 // Conditional branch (not taken case)
6276 temp_u=unneeded_reg[i+2];
6277 temp_uu=unneeded_reg_upper[i+2];
bedfea38 6278 temp_gte_u&=gte_unneeded[i+2];
57871462 6279 }
6280 // Merge in delay slot
6281 tdep=(~temp_uu>>rt1[i+1])&1;
6282 temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6283 temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6284 temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6285 temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6286 temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6287 temp_u|=1;temp_uu|=1;
bedfea38 6288 temp_gte_u|=gte_rt[i+1];
6289 temp_gte_u&=~gte_rs[i+1];
57871462 6290 // If branch is "likely" (and conditional)
6291 // then we skip the delay slot on the fall-thru path
6292 if(likely[i]) {
6293 if(i<slen-1) {
6294 temp_u&=unneeded_reg[i+2];
6295 temp_uu&=unneeded_reg_upper[i+2];
bedfea38 6296 temp_gte_u&=gte_unneeded[i+2];
57871462 6297 }
6298 else
6299 {
6300 temp_u=1;
6301 temp_uu=1;
0ff8c62c 6302 temp_gte_u=gte_u_unknown;
57871462 6303 }
6304 }
6305 tdep=(~temp_uu>>rt1[i])&1;
6306 temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6307 temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6308 temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6309 temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6310 temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6311 temp_u|=1;temp_uu|=1;
bedfea38 6312 temp_gte_u|=gte_rt[i];
6313 temp_gte_u&=~gte_rs[i];
57871462 6314 unneeded_reg[i]=temp_u;
6315 unneeded_reg_upper[i]=temp_uu;
bedfea38 6316 gte_unneeded[i]=temp_gte_u;
57871462 6317 // Only go three levels deep. This recursion can take an
6318 // excessive amount of time if there are a lot of nested loops.
6319 if(r<2) {
6320 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6321 }else{
6322 unneeded_reg[(ba[i]-start)>>2]=1;
6323 unneeded_reg_upper[(ba[i]-start)>>2]=1;
0ff8c62c 6324 gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown;
57871462 6325 }
6326 } /*else*/ if(1) {
6327 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6328 {
6329 // Unconditional branch
6330 u=unneeded_reg[(ba[i]-start)>>2];
6331 uu=unneeded_reg_upper[(ba[i]-start)>>2];
bedfea38 6332 gte_u=gte_unneeded[(ba[i]-start)>>2];
57871462 6333 branch_unneeded_reg[i]=u;
6334 branch_unneeded_reg_upper[i]=uu;
6335 //u=1;
6336 //uu=1;
6337 //branch_unneeded_reg[i]=u;
6338 //branch_unneeded_reg_upper[i]=uu;
6339 // Merge in delay slot
6340 tdep=(~uu>>rt1[i+1])&1;
6341 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6342 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6343 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6344 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6345 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6346 u|=1;uu|=1;
bedfea38 6347 gte_u|=gte_rt[i+1];
6348 gte_u&=~gte_rs[i+1];
57871462 6349 } else {
6350 // Conditional branch
6351 b=unneeded_reg[(ba[i]-start)>>2];
6352 bu=unneeded_reg_upper[(ba[i]-start)>>2];
bedfea38 6353 gte_bu=gte_unneeded[(ba[i]-start)>>2];
57871462 6354 branch_unneeded_reg[i]=b;
6355 branch_unneeded_reg_upper[i]=bu;
6356 //b=1;
6357 //bu=1;
6358 //branch_unneeded_reg[i]=b;
6359 //branch_unneeded_reg_upper[i]=bu;
6360 // Branch delay slot
6361 tdep=(~uu>>rt1[i+1])&1;
6362 b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6363 bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6364 b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6365 bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6366 bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6367 b|=1;bu|=1;
bedfea38 6368 gte_bu|=gte_rt[i+1];
6369 gte_bu&=~gte_rs[i+1];
57871462 6370 // If branch is "likely" then we skip the
6371 // delay slot on the fall-thru path
6372 if(likely[i]) {
6373 u=b;
6374 uu=bu;
bedfea38 6375 gte_u=gte_bu;
57871462 6376 if(i<slen-1) {
6377 u&=unneeded_reg[i+2];
6378 uu&=unneeded_reg_upper[i+2];
bedfea38 6379 gte_u&=gte_unneeded[i+2];
57871462 6380 //u=1;
6381 //uu=1;
6382 }
6383 } else {
6384 u&=b;
6385 uu&=bu;
bedfea38 6386 gte_u&=gte_bu;
57871462 6387 //u=1;
6388 //uu=1;
6389 }
6390 if(i<slen-1) {
6391 branch_unneeded_reg[i]&=unneeded_reg[i+2];
6392 branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6393 //branch_unneeded_reg[i]=1;
6394 //branch_unneeded_reg_upper[i]=1;
6395 } else {
6396 branch_unneeded_reg[i]=1;
6397 branch_unneeded_reg_upper[i]=1;
6398 }
6399 }
6400 }
6401 }
6402 }
1e973cb0 6403 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 6404 {
6405 // SYSCALL instruction (software interrupt)
6406 u=1;
6407 uu=1;
6408 }
6409 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6410 {
6411 // ERET instruction (return from interrupt)
6412 u=1;
6413 uu=1;
6414 }
6415 //u=uu=1; // DEBUG
6416 tdep=(~uu>>rt1[i])&1;
6417 // Written registers are unneeded
6418 u|=1LL<<rt1[i];
6419 u|=1LL<<rt2[i];
6420 uu|=1LL<<rt1[i];
6421 uu|=1LL<<rt2[i];
bedfea38 6422 gte_u|=gte_rt[i];
57871462 6423 // Accessed registers are needed
6424 u&=~(1LL<<rs1[i]);
6425 u&=~(1LL<<rs2[i]);
6426 uu&=~(1LL<<us1[i]);
6427 uu&=~(1LL<<us2[i]);
bedfea38 6428 gte_u&=~gte_rs[i];
eaa11918 6429 if(gte_rs[i]&&rt1[i]&&(unneeded_reg[i+1]&(1ll<<rt1[i])))
cbbd8dd7 6430 gte_u|=gte_rs[i]&gte_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded
57871462 6431 // Source-target dependencies
6432 uu&=~(tdep<<dep1[i]);
6433 uu&=~(tdep<<dep2[i]);
6434 // R0 is always unneeded
6435 u|=1;uu|=1;
6436 // Save it
6437 unneeded_reg[i]=u;
6438 unneeded_reg_upper[i]=uu;
bedfea38 6439 gte_unneeded[i]=gte_u;
57871462 6440 /*
6441 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6442 printf("U:");
6443 int r;
6444 for(r=1;r<=CCREG;r++) {
6445 if((unneeded_reg[i]>>r)&1) {
6446 if(r==HIREG) printf(" HI");
6447 else if(r==LOREG) printf(" LO");
6448 else printf(" r%d",r);
6449 }
6450 }
6451 printf(" UU:");
6452 for(r=1;r<=CCREG;r++) {
6453 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
6454 if(r==HIREG) printf(" HI");
6455 else if(r==LOREG) printf(" LO");
6456 else printf(" r%d",r);
6457 }
6458 }
6459 printf("\n");*/
6460 }
252c20fc 6461 for (i=iend;i>=istart;i--)
6462 {
6463 unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
6464 }
57871462 6465}
6466
71e490c5 6467// Write back dirty registers as soon as we will no longer modify them,
6468// so that we don't end up with lots of writes at the branches.
6469void clean_registers(int istart,int iend,int wr)
57871462 6470{
71e490c5 6471 int i;
6472 int r;
6473 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
6474 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
6475 if(iend==slen-1) {
6476 will_dirty_i=will_dirty_next=0;
6477 wont_dirty_i=wont_dirty_next=0;
6478 }else{
6479 will_dirty_i=will_dirty_next=will_dirty[iend+1];
6480 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
6481 }
6482 for (i=iend;i>=istart;i--)
57871462 6483 {
71e490c5 6484 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
57871462 6485 {
71e490c5 6486 if(ba[i]<start || ba[i]>=(start+slen*4))
57871462 6487 {
71e490c5 6488 // Branch out of this block, flush all regs
6489 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
57871462 6490 {
6491 // Unconditional branch
6492 will_dirty_i=0;
6493 wont_dirty_i=0;
6494 // Merge in delay slot (will dirty)
6495 for(r=0;r<HOST_REGS;r++) {
6496 if(r!=EXCLUDE_REG) {
6497 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6498 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6499 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
6500 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
6501 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6502 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6503 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6504 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6505 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6506 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
6507 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
6508 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6509 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6510 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6511 }
6512 }
6513 }
6514 else
6515 {
6516 // Conditional branch
6517 will_dirty_i=0;
6518 wont_dirty_i=wont_dirty_next;
6519 // Merge in delay slot (will dirty)
6520 for(r=0;r<HOST_REGS;r++) {
6521 if(r!=EXCLUDE_REG) {
6522 if(!likely[i]) {
6523 // Might not dirty if likely branch is not taken
6524 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6525 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6526 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
6527 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
6528 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6529 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
6530 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6531 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6532 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6533 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
6534 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
6535 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6536 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6537 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6538 }
6539 }
6540 }
6541 }
6542 // Merge in delay slot (wont dirty)
6543 for(r=0;r<HOST_REGS;r++) {
6544 if(r!=EXCLUDE_REG) {
6545 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
6546 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
6547 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
6548 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
6549 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6550 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
6551 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
6552 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
6553 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
6554 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6555 }
6556 }
6557 if(wr) {
6558 #ifndef DESTRUCTIVE_WRITEBACK
6559 branch_regs[i].dirty&=wont_dirty_i;
6560 #endif
6561 branch_regs[i].dirty|=will_dirty_i;
6562 }
6563 }
6564 else
6565 {
6566 // Internal branch
6567 if(ba[i]<=start+i*4) {
6568 // Backward branch
6569 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6570 {
6571 // Unconditional branch
6572 temp_will_dirty=0;
6573 temp_wont_dirty=0;
6574 // Merge in delay slot (will dirty)
6575 for(r=0;r<HOST_REGS;r++) {
6576 if(r!=EXCLUDE_REG) {
6577 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
6578 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
6579 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
6580 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
6581 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6582 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6583 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6584 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
6585 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
6586 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
6587 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
6588 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6589 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6590 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6591 }
6592 }
6593 } else {
6594 // Conditional branch (not taken case)
6595 temp_will_dirty=will_dirty_next;
6596 temp_wont_dirty=wont_dirty_next;
6597 // Merge in delay slot (will dirty)
6598 for(r=0;r<HOST_REGS;r++) {
6599 if(r!=EXCLUDE_REG) {
6600 if(!likely[i]) {
6601 // Will not dirty if likely branch is not taken
6602 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
6603 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
6604 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
6605 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
6606 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6607 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
6608 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6609 //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
6610 //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
6611 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
6612 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
6613 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6614 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6615 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6616 }
6617 }
6618 }
6619 }
6620 // Merge in delay slot (wont dirty)
6621 for(r=0;r<HOST_REGS;r++) {
6622 if(r!=EXCLUDE_REG) {
6623 if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
6624 if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
6625 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
6626 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
6627 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
6628 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
6629 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
6630 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
6631 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
6632 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
6633 }
6634 }
6635 // Deal with changed mappings
6636 if(i<iend) {
6637 for(r=0;r<HOST_REGS;r++) {
6638 if(r!=EXCLUDE_REG) {
6639 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
6640 temp_will_dirty&=~(1<<r);
6641 temp_wont_dirty&=~(1<<r);
6642 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
6643 temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6644 temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6645 } else {
6646 temp_will_dirty|=1<<r;
6647 temp_wont_dirty|=1<<r;
6648 }
6649 }
6650 }
6651 }
6652 }
6653 if(wr) {
6654 will_dirty[i]=temp_will_dirty;
6655 wont_dirty[i]=temp_wont_dirty;
6656 clean_registers((ba[i]-start)>>2,i-1,0);
6657 }else{
6658 // Limit recursion. It can take an excessive amount
6659 // of time if there are a lot of nested loops.
6660 will_dirty[(ba[i]-start)>>2]=0;
6661 wont_dirty[(ba[i]-start)>>2]=-1;
6662 }
6663 }
6664 /*else*/ if(1)
6665 {
6666 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6667 {
6668 // Unconditional branch
6669 will_dirty_i=0;
6670 wont_dirty_i=0;
6671 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
6672 for(r=0;r<HOST_REGS;r++) {
6673 if(r!=EXCLUDE_REG) {
6674 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
6675 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
6676 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
6677 }
e3234ecf 6678 if(branch_regs[i].regmap[r]>=0) {
6679 will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
6680 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
6681 }
57871462 6682 }
6683 }
6684 //}
6685 // Merge in delay slot
6686 for(r=0;r<HOST_REGS;r++) {
6687 if(r!=EXCLUDE_REG) {
6688 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6689 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6690 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
6691 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
6692 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6693 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6694 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6695 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6696 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6697 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
6698 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
6699 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6700 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6701 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6702 }
6703 }
6704 } else {
6705 // Conditional branch
6706 will_dirty_i=will_dirty_next;
6707 wont_dirty_i=wont_dirty_next;
6708 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
6709 for(r=0;r<HOST_REGS;r++) {
6710 if(r!=EXCLUDE_REG) {
e3234ecf 6711 signed char target_reg=branch_regs[i].regmap[r];
6712 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
57871462 6713 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
6714 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
6715 }
e3234ecf 6716 else if(target_reg>=0) {
6717 will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
6718 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
57871462 6719 }
6720 // Treat delay slot as part of branch too
6721 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
6722 will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
6723 wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
6724 }
6725 else
6726 {
6727 will_dirty[i+1]&=~(1<<r);
6728 }*/
6729 }
6730 }
6731 //}
6732 // Merge in delay slot
6733 for(r=0;r<HOST_REGS;r++) {
6734 if(r!=EXCLUDE_REG) {
6735 if(!likely[i]) {
6736 // Might not dirty if likely branch is not taken
6737 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6738 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6739 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
6740 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
6741 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6742 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6743 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6744 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6745 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6746 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
6747 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
6748 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6749 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6750 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6751 }
6752 }
6753 }
6754 }
e3234ecf 6755 // Merge in delay slot (won't dirty)
57871462 6756 for(r=0;r<HOST_REGS;r++) {
6757 if(r!=EXCLUDE_REG) {
6758 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
6759 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
6760 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
6761 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
6762 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6763 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
6764 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
6765 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
6766 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
6767 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6768 }
6769 }
6770 if(wr) {
6771 #ifndef DESTRUCTIVE_WRITEBACK
6772 branch_regs[i].dirty&=wont_dirty_i;
6773 #endif
6774 branch_regs[i].dirty|=will_dirty_i;
6775 }
6776 }
6777 }
6778 }
1e973cb0 6779 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 6780 {
6781 // SYSCALL instruction (software interrupt)
6782 will_dirty_i=0;
6783 wont_dirty_i=0;
6784 }
6785 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6786 {
6787 // ERET instruction (return from interrupt)
6788 will_dirty_i=0;
6789 wont_dirty_i=0;
6790 }
6791 will_dirty_next=will_dirty_i;
6792 wont_dirty_next=wont_dirty_i;
6793 for(r=0;r<HOST_REGS;r++) {
6794 if(r!=EXCLUDE_REG) {
6795 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6796 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6797 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6798 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6799 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6800 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
6801 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
6802 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6803 if(i>istart) {
9f51b4b9 6804 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
57871462 6805 {
6806 // Don't store a register immediately after writing it,
6807 // may prevent dual-issue.
6808 if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
6809 if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
6810 }
6811 }
6812 }
6813 }
6814 // Save it
6815 will_dirty[i]=will_dirty_i;
6816 wont_dirty[i]=wont_dirty_i;
6817 // Mark registers that won't be dirtied as not dirty
6818 if(wr) {
6819 /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
6820 for(r=0;r<HOST_REGS;r++) {
6821 if((will_dirty_i>>r)&1) {
6822 printf(" r%d",r);
6823 }
6824 }
6825 printf("\n");*/
6826
6827 //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
6828 regs[i].dirty|=will_dirty_i;
6829 #ifndef DESTRUCTIVE_WRITEBACK
6830 regs[i].dirty&=wont_dirty_i;
6831 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6832 {
6833 if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
6834 for(r=0;r<HOST_REGS;r++) {
6835 if(r!=EXCLUDE_REG) {
6836 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
6837 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
581335b0 6838 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
57871462 6839 }
6840 }
6841 }
6842 }
6843 else
6844 {
6845 if(i<iend) {
6846 for(r=0;r<HOST_REGS;r++) {
6847 if(r!=EXCLUDE_REG) {
6848 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
6849 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
581335b0 6850 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
57871462 6851 }
6852 }
6853 }
6854 }
6855 #endif
6856 //}
6857 }
6858 // Deal with changed mappings
6859 temp_will_dirty=will_dirty_i;
6860 temp_wont_dirty=wont_dirty_i;
6861 for(r=0;r<HOST_REGS;r++) {
6862 if(r!=EXCLUDE_REG) {
6863 int nr;
6864 if(regs[i].regmap[r]==regmap_pre[i][r]) {
6865 if(wr) {
6866 #ifndef DESTRUCTIVE_WRITEBACK
6867 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
6868 #endif
6869 regs[i].wasdirty|=will_dirty_i&(1<<r);
6870 }
6871 }
f776eb14 6872 else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
57871462 6873 // Register moved to a different register
6874 will_dirty_i&=~(1<<r);
6875 wont_dirty_i&=~(1<<r);
6876 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
6877 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
6878 if(wr) {
6879 #ifndef DESTRUCTIVE_WRITEBACK
6880 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
6881 #endif
6882 regs[i].wasdirty|=will_dirty_i&(1<<r);
6883 }
6884 }
6885 else {
6886 will_dirty_i&=~(1<<r);
6887 wont_dirty_i&=~(1<<r);
6888 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
6889 will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6890 wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6891 } else {
6892 wont_dirty_i|=1<<r;
581335b0 6893 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);assert(!((will_dirty>>r)&1));*/
57871462 6894 }
6895 }
6896 }
6897 }
6898 }
6899}
6900
4600ba03 6901#ifdef DISASM
57871462 6902 /* disassembly */
6903void disassemble_inst(int i)
6904{
6905 if (bt[i]) printf("*"); else printf(" ");
6906 switch(itype[i]) {
6907 case UJUMP:
6908 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
6909 case CJUMP:
6910 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
6911 case SJUMP:
6912 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
6913 case FJUMP:
6914 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
6915 case RJUMP:
74426039 6916 if (opcode[i]==0x9&&rt1[i]!=31)
5067f341 6917 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
6918 else
6919 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
6920 break;
57871462 6921 case SPAN:
6922 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
6923 case IMM16:
6924 if(opcode[i]==0xf) //LUI
6925 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
6926 else
6927 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
6928 break;
6929 case LOAD:
6930 case LOADLR:
6931 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
6932 break;
6933 case STORE:
6934 case STORELR:
6935 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
6936 break;
6937 case ALU:
6938 case SHIFT:
6939 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
6940 break;
6941 case MULTDIV:
6942 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
6943 break;
6944 case SHIFTIMM:
6945 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
6946 break;
6947 case MOV:
6948 if((opcode2[i]&0x1d)==0x10)
6949 printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
6950 else if((opcode2[i]&0x1d)==0x11)
6951 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
6952 else
6953 printf (" %x: %s\n",start+i*4,insn[i]);
6954 break;
6955 case COP0:
6956 if(opcode2[i]==0)
6957 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
6958 else if(opcode2[i]==4)
6959 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
6960 else printf (" %x: %s\n",start+i*4,insn[i]);
6961 break;
6962 case COP1:
6963 if(opcode2[i]<3)
6964 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
6965 else if(opcode2[i]>3)
6966 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
6967 else printf (" %x: %s\n",start+i*4,insn[i]);
6968 break;
b9b61529 6969 case COP2:
6970 if(opcode2[i]<3)
6971 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
6972 else if(opcode2[i]>3)
6973 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
6974 else printf (" %x: %s\n",start+i*4,insn[i]);
6975 break;
57871462 6976 case C1LS:
6977 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
6978 break;
b9b61529 6979 case C2LS:
6980 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
6981 break;
1e973cb0 6982 case INTCALL:
6983 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
6984 break;
57871462 6985 default:
6986 //printf (" %s %8x\n",insn[i],source[i]);
6987 printf (" %x: %s\n",start+i*4,insn[i]);
6988 }
6989}
4600ba03 6990#else
6991static void disassemble_inst(int i) {}
6992#endif // DISASM
57871462 6993
d848b60a 6994#define DRC_TEST_VAL 0x74657374
6995
6996static int new_dynarec_test(void)
6997{
6998 int (*testfunc)(void) = (void *)out;
d148d265 6999 void *beginning;
d848b60a 7000 int ret;
d148d265 7001
7002 beginning = start_block();
d848b60a 7003 emit_movimm(DRC_TEST_VAL,0); // test
7004 emit_jmpreg(14);
7005 literal_pool(0);
d148d265 7006 end_block(beginning);
d848b60a 7007 SysPrintf("testing if we can run recompiled code..\n");
7008 ret = testfunc();
7009 if (ret == DRC_TEST_VAL)
7010 SysPrintf("test passed.\n");
7011 else
7012 SysPrintf("test failed: %08x\n", ret);
7013 out=(u_char *)BASE_ADDR;
7014 return ret == DRC_TEST_VAL;
7015}
7016
dc990066 7017// clear the state completely, instead of just marking
7018// things invalid like invalidate_all_pages() does
7019void new_dynarec_clear_full()
57871462 7020{
57871462 7021 int n;
35775df7 7022 out=(u_char *)BASE_ADDR;
7023 memset(invalid_code,1,sizeof(invalid_code));
7024 memset(hash_table,0xff,sizeof(hash_table));
57871462 7025 memset(mini_ht,-1,sizeof(mini_ht));
7026 memset(restore_candidate,0,sizeof(restore_candidate));
dc990066 7027 memset(shadow,0,sizeof(shadow));
57871462 7028 copy=shadow;
7029 expirep=16384; // Expiry pointer, +2 blocks
7030 pending_exception=0;
7031 literalcount=0;
57871462 7032 stop_after_jal=0;
9be4ba64 7033 inv_code_start=inv_code_end=~0;
57871462 7034 // TLB
dc990066 7035 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7036 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7037 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7038}
7039
7040void new_dynarec_init()
7041{
d848b60a 7042 SysPrintf("Init new dynarec\n");
1e212a25 7043
7044 // allocate/prepare a buffer for translation cache
7045 // see assem_arm.h for some explanation
7046#if defined(BASE_ADDR_FIXED)
7047 if (mmap (translation_cache, 1 << TARGET_SIZE_2,
dc990066 7048 PROT_READ | PROT_WRITE | PROT_EXEC,
186935dc 7049 MAP_PRIVATE | MAP_ANONYMOUS,
1e212a25 7050 -1, 0) != translation_cache) {
7051 SysPrintf("mmap() failed: %s\n", strerror(errno));
7052 SysPrintf("disable BASE_ADDR_FIXED and recompile\n");
7053 abort();
7054 }
7055#elif defined(BASE_ADDR_DYNAMIC)
7056 #ifdef VITA
7057 sceBlock = sceKernelAllocMemBlockForVM("code", 1 << TARGET_SIZE_2);
7058 if (sceBlock < 0)
7059 SysPrintf("sceKernelAllocMemBlockForVM failed\n");
7060 int ret = sceKernelGetMemBlockBase(sceBlock, (void **)&translation_cache);
7061 if (ret < 0)
7062 SysPrintf("sceKernelGetMemBlockBase failed\n");
7063 #else
7064 translation_cache = mmap (NULL, 1 << TARGET_SIZE_2,
7065 PROT_READ | PROT_WRITE | PROT_EXEC,
7066 MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
7067 if (translation_cache == MAP_FAILED) {
d848b60a 7068 SysPrintf("mmap() failed: %s\n", strerror(errno));
1e212a25 7069 abort();
d848b60a 7070 }
1e212a25 7071 #endif
7072#else
7073 #ifndef NO_WRITE_EXEC
bdeade46 7074 // not all systems allow execute in data segment by default
25e52b2c 7075 if (mprotect((void *)BASE_ADDR, 1<<TARGET_SIZE_2, PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
d848b60a 7076 SysPrintf("mprotect() failed: %s\n", strerror(errno));
1e212a25 7077 #endif
dc990066 7078#endif
1e212a25 7079 out=(u_char *)BASE_ADDR;
2573466a 7080 cycle_multiplier=200;
dc990066 7081 new_dynarec_clear_full();
7082#ifdef HOST_IMM8
7083 // Copy this into local area so we don't have to put it in every literal pool
7084 invc_ptr=invalid_code;
7085#endif
57871462 7086 arch_init();
d848b60a 7087 new_dynarec_test();
a327ad27 7088#ifndef RAM_FIXED
7089 ram_offset=(u_int)rdram-0x80000000;
7090#endif
b105cf4f 7091 if (ram_offset!=0)
c43b5311 7092 SysPrintf("warning: RAM is not directly mapped, performance will suffer\n");
57871462 7093}
7094
7095void new_dynarec_cleanup()
7096{
7097 int n;
1e212a25 7098#if defined(BASE_ADDR_FIXED) || defined(BASE_ADDR_DYNAMIC)
7099 #ifdef VITA
7100 sceKernelFreeMemBlock(sceBlock);
7101 sceBlock = -1;
7102 #else
7103 if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0)
7104 SysPrintf("munmap() failed\n");
bdeade46 7105 #endif
1e212a25 7106#endif
57871462 7107 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7108 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7109 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7110 #ifdef ROM_COPY
c43b5311 7111 if (munmap (ROM_COPY, 67108864) < 0) {SysPrintf("munmap() failed\n");}
57871462 7112 #endif
7113}
7114
03f55e6b 7115static u_int *get_source_start(u_int addr, u_int *limit)
57871462 7116{
03f55e6b 7117 if (addr < 0x00200000 ||
7118 (0xa0000000 <= addr && addr < 0xa0200000)) {
7119 // used for BIOS calls mostly?
7120 *limit = (addr&0xa0000000)|0x00200000;
7121 return (u_int *)((u_int)rdram + (addr&0x1fffff));
7122 }
7123 else if (!Config.HLE && (
7124 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
7125 (0xbfc00000 <= addr && addr < 0xbfc80000))) {
7126 // BIOS
7127 *limit = (addr & 0xfff00000) | 0x80000;
7128 return (u_int *)((u_int)psxR + (addr&0x7ffff));
7129 }
7130 else if (addr >= 0x80000000 && addr < 0x80000000+RAM_SIZE) {
7131 *limit = (addr & 0x80600000) + 0x00200000;
7132 return (u_int *)((u_int)rdram + (addr&0x1fffff));
7133 }
581335b0 7134 return NULL;
03f55e6b 7135}
7136
7137static u_int scan_for_ret(u_int addr)
7138{
7139 u_int limit = 0;
7140 u_int *mem;
7141
7142 mem = get_source_start(addr, &limit);
7143 if (mem == NULL)
7144 return addr;
7145
7146 if (limit > addr + 0x1000)
7147 limit = addr + 0x1000;
7148 for (; addr < limit; addr += 4, mem++) {
7149 if (*mem == 0x03e00008) // jr $ra
7150 return addr + 8;
57871462 7151 }
581335b0 7152 return addr;
03f55e6b 7153}
7154
7155struct savestate_block {
7156 uint32_t addr;
7157 uint32_t regflags;
7158};
7159
7160static int addr_cmp(const void *p1_, const void *p2_)
7161{
7162 const struct savestate_block *p1 = p1_, *p2 = p2_;
7163 return p1->addr - p2->addr;
7164}
7165
7166int new_dynarec_save_blocks(void *save, int size)
7167{
7168 struct savestate_block *blocks = save;
7169 int maxcount = size / sizeof(blocks[0]);
7170 struct savestate_block tmp_blocks[1024];
7171 struct ll_entry *head;
7172 int p, s, d, o, bcnt;
7173 u_int addr;
7174
7175 o = 0;
7176 for (p = 0; p < sizeof(jump_in) / sizeof(jump_in[0]); p++) {
7177 bcnt = 0;
7178 for (head = jump_in[p]; head != NULL; head = head->next) {
7179 tmp_blocks[bcnt].addr = head->vaddr;
7180 tmp_blocks[bcnt].regflags = head->reg_sv_flags;
7181 bcnt++;
7182 }
7183 if (bcnt < 1)
7184 continue;
7185 qsort(tmp_blocks, bcnt, sizeof(tmp_blocks[0]), addr_cmp);
7186
7187 addr = tmp_blocks[0].addr;
7188 for (s = d = 0; s < bcnt; s++) {
7189 if (tmp_blocks[s].addr < addr)
7190 continue;
7191 if (d == 0 || tmp_blocks[d-1].addr != tmp_blocks[s].addr)
7192 tmp_blocks[d++] = tmp_blocks[s];
7193 addr = scan_for_ret(tmp_blocks[s].addr);
7194 }
7195
7196 if (o + d > maxcount)
7197 d = maxcount - o;
7198 memcpy(&blocks[o], tmp_blocks, d * sizeof(blocks[0]));
7199 o += d;
7200 }
7201
7202 return o * sizeof(blocks[0]);
7203}
7204
7205void new_dynarec_load_blocks(const void *save, int size)
7206{
7207 const struct savestate_block *blocks = save;
7208 int count = size / sizeof(blocks[0]);
7209 u_int regs_save[32];
7210 uint32_t f;
7211 int i, b;
7212
7213 get_addr(psxRegs.pc);
7214
7215 // change GPRs for speculation to at least partially work..
7216 memcpy(regs_save, &psxRegs.GPR, sizeof(regs_save));
7217 for (i = 1; i < 32; i++)
7218 psxRegs.GPR.r[i] = 0x80000000;
7219
7220 for (b = 0; b < count; b++) {
7221 for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) {
7222 if (f & 1)
7223 psxRegs.GPR.r[i] = 0x1f800000;
7224 }
7225
7226 get_addr(blocks[b].addr);
7227
7228 for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) {
7229 if (f & 1)
7230 psxRegs.GPR.r[i] = 0x80000000;
7231 }
7232 }
7233
7234 memcpy(&psxRegs.GPR, regs_save, sizeof(regs_save));
7235}
7236
7237int new_recompile_block(int addr)
7238{
7239 u_int pagelimit = 0;
7240 u_int state_rflags = 0;
7241 int i;
7242
57871462 7243 assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7244 //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7245 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
9f51b4b9 7246 //if(debug)
57871462 7247 //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
7248 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
7249 /*if(Count>=312978186) {
7250 rlist();
7251 }*/
7252 //rlist();
03f55e6b 7253
7254 // this is just for speculation
7255 for (i = 1; i < 32; i++) {
7256 if ((psxRegs.GPR.r[i] & 0xffff0000) == 0x1f800000)
7257 state_rflags |= 1 << i;
7258 }
7259
57871462 7260 start = (u_int)addr&~3;
7261 //assert(((u_int)addr&1)==0);
2f546f9a 7262 new_dynarec_did_compile=1;
9ad4d757 7263 if (Config.HLE && start == 0x80001000) // hlecall
560e4a12 7264 {
7139f3c8 7265 // XXX: is this enough? Maybe check hleSoftCall?
d148d265 7266 void *beginning=start_block();
7139f3c8 7267 u_int page=get_page(start);
d148d265 7268
7139f3c8 7269 invalid_code[start>>12]=0;
7270 emit_movimm(start,0);
7271 emit_writeword(0,(int)&pcaddr);
bb5285ef 7272 emit_jmp((int)new_dyna_leave);
15776b68 7273 literal_pool(0);
d148d265 7274 end_block(beginning);
03f55e6b 7275 ll_add_flags(jump_in+page,start,state_rflags,(void *)beginning);
7139f3c8 7276 return 0;
7277 }
03f55e6b 7278
7279 source = get_source_start(start, &pagelimit);
7280 if (source == NULL) {
7281 SysPrintf("Compile at bogus memory address: %08x\n", addr);
57871462 7282 exit(1);
7283 }
7284
7285 /* Pass 1: disassemble */
7286 /* Pass 2: register dependencies, branch targets */
7287 /* Pass 3: register allocation */
7288 /* Pass 4: branch dependencies */
7289 /* Pass 5: pre-alloc */
7290 /* Pass 6: optimize clean/dirty state */
7291 /* Pass 7: flag 32-bit registers */
7292 /* Pass 8: assembly */
7293 /* Pass 9: linker */
7294 /* Pass 10: garbage collection / free memory */
7295
03f55e6b 7296 int j;
57871462 7297 int done=0;
7298 unsigned int type,op,op2;
7299
7300 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
9f51b4b9 7301
57871462 7302 /* Pass 1 disassembly */
7303
7304 for(i=0;!done;i++) {
e1190b87 7305 bt[i]=0;likely[i]=0;ooo[i]=0;op2=0;
7306 minimum_free_regs[i]=0;
57871462 7307 opcode[i]=op=source[i]>>26;
7308 switch(op)
7309 {
7310 case 0x00: strcpy(insn[i],"special"); type=NI;
7311 op2=source[i]&0x3f;
7312 switch(op2)
7313 {
7314 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
7315 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
7316 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
7317 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
7318 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
7319 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
7320 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
7321 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
7322 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
7323 case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
7324 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
7325 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
7326 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
7327 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
7328 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
57871462 7329 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
7330 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
7331 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
7332 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
57871462 7333 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
7334 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
7335 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
7336 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
7337 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
7338 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
7339 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
7340 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
7341 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
7342 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
57871462 7343 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
7344 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
7345 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
7346 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
7347 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
7348 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
71e490c5 7349#if 0
7f2607ea 7350 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
7351 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
7352 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
7353 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
7354 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
7355 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
7356 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
7357 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
7358 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
7359 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
7360 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
57871462 7361 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
7362 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
7363 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
7364 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
7365 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
7366 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
7f2607ea 7367#endif
57871462 7368 }
7369 break;
7370 case 0x01: strcpy(insn[i],"regimm"); type=NI;
7371 op2=(source[i]>>16)&0x1f;
7372 switch(op2)
7373 {
7374 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
7375 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
7376 case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
7377 case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
7378 case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
7379 case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
7380 case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
7381 case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
7382 case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
7383 case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
7384 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
7385 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
7386 case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
7387 case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
7388 }
7389 break;
7390 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
7391 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
7392 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
7393 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
7394 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
7395 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
7396 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
7397 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
7398 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
7399 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
7400 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
7401 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
7402 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
7403 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
7404 case 0x10: strcpy(insn[i],"cop0"); type=NI;
7405 op2=(source[i]>>21)&0x1f;
7406 switch(op2)
7407 {
7408 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
7409 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
7410 case 0x10: strcpy(insn[i],"tlb"); type=NI;
7411 switch(source[i]&0x3f)
7412 {
7413 case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
7414 case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
7415 case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
7416 case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
576bbd8f 7417 case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
71e490c5 7418 //case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
57871462 7419 }
7420 }
7421 break;
7422 case 0x11: strcpy(insn[i],"cop1"); type=NI;
7423 op2=(source[i]>>21)&0x1f;
7424 switch(op2)
7425 {
7426 case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
7427 case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
7428 case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
7429 case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
7430 case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
7431 case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
7432 case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
7433 switch((source[i]>>16)&0x3)
7434 {
7435 case 0x00: strcpy(insn[i],"BC1F"); break;
7436 case 0x01: strcpy(insn[i],"BC1T"); break;
7437 case 0x02: strcpy(insn[i],"BC1FL"); break;
7438 case 0x03: strcpy(insn[i],"BC1TL"); break;
7439 }
7440 break;
7441 case 0x10: strcpy(insn[i],"C1.S"); type=NI;
7442 switch(source[i]&0x3f)
7443 {
7444 case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
7445 case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
7446 case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
7447 case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
7448 case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
7449 case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
7450 case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
7451 case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
7452 case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
7453 case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
7454 case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
7455 case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
7456 case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
7457 case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
7458 case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
7459 case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
7460 case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
7461 case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
7462 case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
7463 case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
7464 case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
7465 case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
7466 case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
7467 case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
7468 case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
7469 case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
7470 case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
7471 case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
7472 case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
7473 case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
7474 case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
7475 case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
7476 case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
7477 case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
7478 case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
7479 }
7480 break;
7481 case 0x11: strcpy(insn[i],"C1.D"); type=NI;
7482 switch(source[i]&0x3f)
7483 {
7484 case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
7485 case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
7486 case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
7487 case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
7488 case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
7489 case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
7490 case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
7491 case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
7492 case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
7493 case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
7494 case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
7495 case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
7496 case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
7497 case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
7498 case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
7499 case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
7500 case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
7501 case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
7502 case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
7503 case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
7504 case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
7505 case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
7506 case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
7507 case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
7508 case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
7509 case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
7510 case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
7511 case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
7512 case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
7513 case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
7514 case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
7515 case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
7516 case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
7517 case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
7518 case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
7519 }
7520 break;
7521 case 0x14: strcpy(insn[i],"C1.W"); type=NI;
7522 switch(source[i]&0x3f)
7523 {
7524 case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
7525 case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
7526 }
7527 break;
7528 case 0x15: strcpy(insn[i],"C1.L"); type=NI;
7529 switch(source[i]&0x3f)
7530 {
7531 case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
7532 case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
7533 }
7534 break;
7535 }
7536 break;
71e490c5 7537#if 0
57871462 7538 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
7539 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
7540 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
7541 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
7542 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
7543 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
7544 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
7545 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
996cc15d 7546#endif
57871462 7547 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
7548 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
7549 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
7550 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
7551 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
7552 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
7553 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
71e490c5 7554#if 0
57871462 7555 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
64bd6f82 7556#endif
57871462 7557 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
7558 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
7559 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
7560 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
71e490c5 7561#if 0
57871462 7562 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
7563 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
996cc15d 7564#endif
57871462 7565 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
7566 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
7567 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
7568 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
71e490c5 7569#if 0
57871462 7570 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
7571 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
7572 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
996cc15d 7573#endif
57871462 7574 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
7575 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
71e490c5 7576#if 0
57871462 7577 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
7578 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
7579 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
996cc15d 7580#endif
b9b61529 7581 case 0x12: strcpy(insn[i],"COP2"); type=NI;
7582 op2=(source[i]>>21)&0x1f;
bedfea38 7583 //if (op2 & 0x10) {
7584 if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
c7abc864 7585 if (gte_handlers[source[i]&0x3f]!=NULL) {
bedfea38 7586 if (gte_regnames[source[i]&0x3f]!=NULL)
7587 strcpy(insn[i],gte_regnames[source[i]&0x3f]);
7588 else
7589 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
c7abc864 7590 type=C2OP;
7591 }
7592 }
7593 else switch(op2)
b9b61529 7594 {
7595 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
7596 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
7597 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
7598 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
b9b61529 7599 }
7600 break;
7601 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
7602 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
7603 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
90ae6d4e 7604 default: strcpy(insn[i],"???"); type=NI;
c43b5311 7605 SysPrintf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
90ae6d4e 7606 break;
57871462 7607 }
7608 itype[i]=type;
7609 opcode2[i]=op2;
7610 /* Get registers/immediates */
7611 lt1[i]=0;
7612 us1[i]=0;
7613 us2[i]=0;
7614 dep1[i]=0;
7615 dep2[i]=0;
bedfea38 7616 gte_rs[i]=gte_rt[i]=0;
57871462 7617 switch(type) {
7618 case LOAD:
7619 rs1[i]=(source[i]>>21)&0x1f;
7620 rs2[i]=0;
7621 rt1[i]=(source[i]>>16)&0x1f;
7622 rt2[i]=0;
7623 imm[i]=(short)source[i];
7624 break;
7625 case STORE:
7626 case STORELR:
7627 rs1[i]=(source[i]>>21)&0x1f;
7628 rs2[i]=(source[i]>>16)&0x1f;
7629 rt1[i]=0;
7630 rt2[i]=0;
7631 imm[i]=(short)source[i];
7632 if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
7633 break;
7634 case LOADLR:
7635 // LWL/LWR only load part of the register,
7636 // therefore the target register must be treated as a source too
7637 rs1[i]=(source[i]>>21)&0x1f;
7638 rs2[i]=(source[i]>>16)&0x1f;
7639 rt1[i]=(source[i]>>16)&0x1f;
7640 rt2[i]=0;
7641 imm[i]=(short)source[i];
7642 if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
7643 if(op==0x26) dep1[i]=rt1[i]; // LWR
7644 break;
7645 case IMM16:
7646 if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
7647 else rs1[i]=(source[i]>>21)&0x1f;
7648 rs2[i]=0;
7649 rt1[i]=(source[i]>>16)&0x1f;
7650 rt2[i]=0;
7651 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
7652 imm[i]=(unsigned short)source[i];
7653 }else{
7654 imm[i]=(short)source[i];
7655 }
7656 if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
7657 if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
7658 if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
7659 break;
7660 case UJUMP:
7661 rs1[i]=0;
7662 rs2[i]=0;
7663 rt1[i]=0;
7664 rt2[i]=0;
7665 // The JAL instruction writes to r31.
7666 if (op&1) {
7667 rt1[i]=31;
7668 }
7669 rs2[i]=CCREG;
7670 break;
7671 case RJUMP:
7672 rs1[i]=(source[i]>>21)&0x1f;
7673 rs2[i]=0;
7674 rt1[i]=0;
7675 rt2[i]=0;
5067f341 7676 // The JALR instruction writes to rd.
57871462 7677 if (op2&1) {
5067f341 7678 rt1[i]=(source[i]>>11)&0x1f;
57871462 7679 }
7680 rs2[i]=CCREG;
7681 break;
7682 case CJUMP:
7683 rs1[i]=(source[i]>>21)&0x1f;
7684 rs2[i]=(source[i]>>16)&0x1f;
7685 rt1[i]=0;
7686 rt2[i]=0;
7687 if(op&2) { // BGTZ/BLEZ
7688 rs2[i]=0;
7689 }
7690 us1[i]=rs1[i];
7691 us2[i]=rs2[i];
7692 likely[i]=op>>4;
7693 break;
7694 case SJUMP:
7695 rs1[i]=(source[i]>>21)&0x1f;
7696 rs2[i]=CCREG;
7697 rt1[i]=0;
7698 rt2[i]=0;
7699 us1[i]=rs1[i];
7700 if(op2&0x10) { // BxxAL
7701 rt1[i]=31;
7702 // NOTE: If the branch is not taken, r31 is still overwritten
7703 }
7704 likely[i]=(op2&2)>>1;
7705 break;
7706 case FJUMP:
7707 rs1[i]=FSREG;
7708 rs2[i]=CSREG;
7709 rt1[i]=0;
7710 rt2[i]=0;
7711 likely[i]=((source[i])>>17)&1;
7712 break;
7713 case ALU:
7714 rs1[i]=(source[i]>>21)&0x1f; // source
7715 rs2[i]=(source[i]>>16)&0x1f; // subtract amount
7716 rt1[i]=(source[i]>>11)&0x1f; // destination
7717 rt2[i]=0;
7718 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
7719 us1[i]=rs1[i];us2[i]=rs2[i];
7720 }
7721 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
7722 dep1[i]=rs1[i];dep2[i]=rs2[i];
7723 }
7724 else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
7725 dep1[i]=rs1[i];dep2[i]=rs2[i];
7726 }
7727 break;
7728 case MULTDIV:
7729 rs1[i]=(source[i]>>21)&0x1f; // source
7730 rs2[i]=(source[i]>>16)&0x1f; // divisor
7731 rt1[i]=HIREG;
7732 rt2[i]=LOREG;
7733 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
7734 us1[i]=rs1[i];us2[i]=rs2[i];
7735 }
7736 break;
7737 case MOV:
7738 rs1[i]=0;
7739 rs2[i]=0;
7740 rt1[i]=0;
7741 rt2[i]=0;
7742 if(op2==0x10) rs1[i]=HIREG; // MFHI
7743 if(op2==0x11) rt1[i]=HIREG; // MTHI
7744 if(op2==0x12) rs1[i]=LOREG; // MFLO
7745 if(op2==0x13) rt1[i]=LOREG; // MTLO
7746 if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
7747 if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
7748 dep1[i]=rs1[i];
7749 break;
7750 case SHIFT:
7751 rs1[i]=(source[i]>>16)&0x1f; // target of shift
7752 rs2[i]=(source[i]>>21)&0x1f; // shift amount
7753 rt1[i]=(source[i]>>11)&0x1f; // destination
7754 rt2[i]=0;
7755 // DSLLV/DSRLV/DSRAV are 64-bit
7756 if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
7757 break;
7758 case SHIFTIMM:
7759 rs1[i]=(source[i]>>16)&0x1f;
7760 rs2[i]=0;
7761 rt1[i]=(source[i]>>11)&0x1f;
7762 rt2[i]=0;
7763 imm[i]=(source[i]>>6)&0x1f;
7764 // DSxx32 instructions
7765 if(op2>=0x3c) imm[i]|=0x20;
7766 // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
7767 if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
7768 break;
7769 case COP0:
7770 rs1[i]=0;
7771 rs2[i]=0;
7772 rt1[i]=0;
7773 rt2[i]=0;
7774 if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
7775 if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
7776 if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
7777 if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
7778 break;
7779 case COP1:
7780 rs1[i]=0;
7781 rs2[i]=0;
7782 rt1[i]=0;
7783 rt2[i]=0;
7784 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
7785 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
7786 if(op2==5) us1[i]=rs1[i]; // DMTC1
7787 rs2[i]=CSREG;
7788 break;
bedfea38 7789 case COP2:
7790 rs1[i]=0;
7791 rs2[i]=0;
7792 rt1[i]=0;
7793 rt2[i]=0;
7794 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC2/CFC2
7795 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC2/CTC2
7796 rs2[i]=CSREG;
7797 int gr=(source[i]>>11)&0x1F;
7798 switch(op2)
7799 {
7800 case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
7801 case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
0ff8c62c 7802 case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2
bedfea38 7803 case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
7804 }
7805 break;
57871462 7806 case C1LS:
7807 rs1[i]=(source[i]>>21)&0x1F;
7808 rs2[i]=CSREG;
7809 rt1[i]=0;
7810 rt2[i]=0;
7811 imm[i]=(short)source[i];
7812 break;
b9b61529 7813 case C2LS:
7814 rs1[i]=(source[i]>>21)&0x1F;
7815 rs2[i]=0;
7816 rt1[i]=0;
7817 rt2[i]=0;
7818 imm[i]=(short)source[i];
bedfea38 7819 if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
7820 else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
7821 break;
7822 case C2OP:
7823 rs1[i]=0;
7824 rs2[i]=0;
7825 rt1[i]=0;
7826 rt2[i]=0;
2167bef6 7827 gte_rs[i]=gte_reg_reads[source[i]&0x3f];
7828 gte_rt[i]=gte_reg_writes[source[i]&0x3f];
7829 gte_rt[i]|=1ll<<63; // every op changes flags
587a5b1c 7830 if((source[i]&0x3f)==GTE_MVMVA) {
7831 int v = (source[i] >> 15) & 3;
7832 gte_rs[i]&=~0xe3fll;
7833 if(v==3) gte_rs[i]|=0xe00ll;
7834 else gte_rs[i]|=3ll<<(v*2);
7835 }
b9b61529 7836 break;
57871462 7837 case FLOAT:
7838 case FCONV:
7839 rs1[i]=0;
7840 rs2[i]=CSREG;
7841 rt1[i]=0;
7842 rt2[i]=0;
7843 break;
7844 case FCOMP:
7845 rs1[i]=FSREG;
7846 rs2[i]=CSREG;
7847 rt1[i]=FSREG;
7848 rt2[i]=0;
7849 break;
7850 case SYSCALL:
7139f3c8 7851 case HLECALL:
1e973cb0 7852 case INTCALL:
57871462 7853 rs1[i]=CCREG;
7854 rs2[i]=0;
7855 rt1[i]=0;
7856 rt2[i]=0;
7857 break;
7858 default:
7859 rs1[i]=0;
7860 rs2[i]=0;
7861 rt1[i]=0;
7862 rt2[i]=0;
7863 }
7864 /* Calculate branch target addresses */
7865 if(type==UJUMP)
7866 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
7867 else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
7868 ba[i]=start+i*4+8; // Ignore never taken branch
7869 else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
7870 ba[i]=start+i*4+8; // Ignore never taken branch
7871 else if(type==CJUMP||type==SJUMP||type==FJUMP)
7872 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
7873 else ba[i]=-1;
3e535354 7874 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
7875 int do_in_intrp=0;
7876 // branch in delay slot?
7877 if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
7878 // don't handle first branch and call interpreter if it's hit
c43b5311 7879 SysPrintf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
3e535354 7880 do_in_intrp=1;
7881 }
7882 // basic load delay detection
7883 else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&rt1[i]!=0) {
7884 int t=(ba[i-1]-start)/4;
7885 if(0 <= t && t < i &&(rt1[i]==rs1[t]||rt1[i]==rs2[t])&&itype[t]!=CJUMP&&itype[t]!=SJUMP) {
7886 // jump target wants DS result - potential load delay effect
c43b5311 7887 SysPrintf("load delay @%08x (%08x)\n", addr + i*4, addr);
3e535354 7888 do_in_intrp=1;
7889 bt[t+1]=1; // expected return from interpreter
7890 }
7891 else if(i>=2&&rt1[i-2]==2&&rt1[i]==2&&rs1[i]!=2&&rs2[i]!=2&&rs1[i-1]!=2&&rs2[i-1]!=2&&
7892 !(i>=3&&(itype[i-3]==RJUMP||itype[i-3]==UJUMP||itype[i-3]==CJUMP||itype[i-3]==SJUMP))) {
7893 // v0 overwrite like this is a sign of trouble, bail out
c43b5311 7894 SysPrintf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
3e535354 7895 do_in_intrp=1;
7896 }
7897 }
3e535354 7898 if(do_in_intrp) {
7899 rs1[i-1]=CCREG;
7900 rs2[i-1]=rt1[i-1]=rt2[i-1]=0;
26869094 7901 ba[i-1]=-1;
7902 itype[i-1]=INTCALL;
7903 done=2;
3e535354 7904 i--; // don't compile the DS
26869094 7905 }
3e535354 7906 }
3e535354 7907 /* Is this the end of the block? */
7908 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
5067f341 7909 if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
1e973cb0 7910 done=2;
57871462 7911 }
7912 else {
7913 if(stop_after_jal) done=1;
7914 // Stop on BREAK
7915 if((source[i+1]&0xfc00003f)==0x0d) done=1;
7916 }
7917 // Don't recompile stuff that's already compiled
7918 if(check_addr(start+i*4+4)) done=1;
7919 // Don't get too close to the limit
7920 if(i>MAXBLOCK/2) done=1;
7921 }
75dec299 7922 if(itype[i]==SYSCALL&&stop_after_jal) done=1;
1e973cb0 7923 if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
7924 if(done==2) {
7925 // Does the block continue due to a branch?
7926 for(j=i-1;j>=0;j--)
7927 {
2a706964 7928 if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
1e973cb0 7929 if(ba[j]==start+i*4+4) done=j=0;
7930 if(ba[j]==start+i*4+8) done=j=0;
7931 }
7932 }
75dec299 7933 //assert(i<MAXBLOCK-1);
57871462 7934 if(start+i*4==pagelimit-4) done=1;
7935 assert(start+i*4<pagelimit);
7936 if (i==MAXBLOCK-1) done=1;
7937 // Stop if we're compiling junk
7938 if(itype[i]==NI&&opcode[i]==0x11) {
7939 done=stop_after_jal=1;
c43b5311 7940 SysPrintf("Disabled speculative precompilation\n");
57871462 7941 }
7942 }
7943 slen=i;
7944 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
7945 if(start+i*4==pagelimit) {
7946 itype[i-1]=SPAN;
7947 }
7948 }
7949 assert(slen>0);
7950
7951 /* Pass 2 - Register dependencies and branch targets */
7952
7953 unneeded_registers(0,slen-1,0);
9f51b4b9 7954
57871462 7955 /* Pass 3 - Register allocation */
7956
7957 struct regstat current; // Current register allocations/status
7958 current.is32=1;
7959 current.dirty=0;
7960 current.u=unneeded_reg[0];
7961 current.uu=unneeded_reg_upper[0];
7962 clear_all_regs(current.regmap);
7963 alloc_reg(&current,0,CCREG);
7964 dirty_reg(&current,CCREG);
7965 current.isconst=0;
7966 current.wasconst=0;
27727b63 7967 current.waswritten=0;
57871462 7968 int ds=0;
7969 int cc=0;
5194fb95 7970 int hr=-1;
6ebf4adf 7971
57871462 7972 if((u_int)addr&1) {
7973 // First instruction is delay slot
7974 cc=-1;
7975 bt[1]=1;
7976 ds=1;
7977 unneeded_reg[0]=1;
7978 unneeded_reg_upper[0]=1;
7979 current.regmap[HOST_BTREG]=BTREG;
7980 }
9f51b4b9 7981
57871462 7982 for(i=0;i<slen;i++)
7983 {
7984 if(bt[i])
7985 {
7986 int hr;
7987 for(hr=0;hr<HOST_REGS;hr++)
7988 {
7989 // Is this really necessary?
7990 if(current.regmap[hr]==0) current.regmap[hr]=-1;
7991 }
7992 current.isconst=0;
27727b63 7993 current.waswritten=0;
57871462 7994 }
7995 if(i>1)
7996 {
7997 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
7998 {
7999 if(rs1[i-2]==0||rs2[i-2]==0)
8000 {
8001 if(rs1[i-2]) {
8002 current.is32|=1LL<<rs1[i-2];
8003 int hr=get_reg(current.regmap,rs1[i-2]|64);
8004 if(hr>=0) current.regmap[hr]=-1;
8005 }
8006 if(rs2[i-2]) {
8007 current.is32|=1LL<<rs2[i-2];
8008 int hr=get_reg(current.regmap,rs2[i-2]|64);
8009 if(hr>=0) current.regmap[hr]=-1;
8010 }
8011 }
8012 }
8013 }
24385cae 8014 current.is32=-1LL;
24385cae 8015
57871462 8016 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8017 regs[i].wasconst=current.isconst;
8018 regs[i].was32=current.is32;
8019 regs[i].wasdirty=current.dirty;
8575a877 8020 regs[i].loadedconst=0;
57871462 8021 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8022 if(i+1<slen) {
8023 current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8024 current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8025 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8026 current.u|=1;
8027 current.uu|=1;
8028 } else {
8029 current.u=1;
8030 current.uu=1;
8031 }
8032 } else {
8033 if(i+1<slen) {
8034 current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
8035 current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8036 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8037 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8038 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8039 current.u|=1;
8040 current.uu|=1;
c43b5311 8041 } else { SysPrintf("oops, branch at end of block with no delay slot\n");exit(1); }
57871462 8042 }
8043 is_ds[i]=ds;
8044 if(ds) {
8045 ds=0; // Skip delay slot, already allocated as part of branch
8046 // ...but we need to alloc it in case something jumps here
8047 if(i+1<slen) {
8048 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
8049 current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
8050 }else{
8051 current.u=branch_unneeded_reg[i-1];
8052 current.uu=branch_unneeded_reg_upper[i-1];
8053 }
8054 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8055 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8056 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8057 current.u|=1;
8058 current.uu|=1;
8059 struct regstat temp;
8060 memcpy(&temp,&current,sizeof(current));
8061 temp.wasdirty=temp.dirty;
8062 temp.was32=temp.is32;
8063 // TODO: Take into account unconditional branches, as below
8064 delayslot_alloc(&temp,i);
8065 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
8066 regs[i].wasdirty=temp.wasdirty;
8067 regs[i].was32=temp.was32;
8068 regs[i].dirty=temp.dirty;
8069 regs[i].is32=temp.is32;
8070 regs[i].isconst=0;
8071 regs[i].wasconst=0;
8072 current.isconst=0;
8073 // Create entry (branch target) regmap
8074 for(hr=0;hr<HOST_REGS;hr++)
8075 {
8076 int r=temp.regmap[hr];
8077 if(r>=0) {
8078 if(r!=regmap_pre[i][hr]) {
8079 regs[i].regmap_entry[hr]=-1;
8080 }
8081 else
8082 {
8083 if(r<64){
8084 if((current.u>>r)&1) {
8085 regs[i].regmap_entry[hr]=-1;
8086 regs[i].regmap[hr]=-1;
8087 //Don't clear regs in the delay slot as the branch might need them
8088 //current.regmap[hr]=-1;
8089 }else
8090 regs[i].regmap_entry[hr]=r;
8091 }
8092 else {
8093 if((current.uu>>(r&63))&1) {
8094 regs[i].regmap_entry[hr]=-1;
8095 regs[i].regmap[hr]=-1;
8096 //Don't clear regs in the delay slot as the branch might need them
8097 //current.regmap[hr]=-1;
8098 }else
8099 regs[i].regmap_entry[hr]=r;
8100 }
8101 }
8102 } else {
8103 // First instruction expects CCREG to be allocated
9f51b4b9 8104 if(i==0&&hr==HOST_CCREG)
57871462 8105 regs[i].regmap_entry[hr]=CCREG;
8106 else
8107 regs[i].regmap_entry[hr]=-1;
8108 }
8109 }
8110 }
8111 else { // Not delay slot
8112 switch(itype[i]) {
8113 case UJUMP:
8114 //current.isconst=0; // DEBUG
8115 //current.wasconst=0; // DEBUG
8116 //regs[i].wasconst=0; // DEBUG
8117 clear_const(&current,rt1[i]);
8118 alloc_cc(&current,i);
8119 dirty_reg(&current,CCREG);
8120 if (rt1[i]==31) {
8121 alloc_reg(&current,i,31);
8122 dirty_reg(&current,31);
4ef8f67d 8123 //assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8124 //assert(rt1[i+1]!=rt1[i]);
57871462 8125 #ifdef REG_PREFETCH
8126 alloc_reg(&current,i,PTEMP);
8127 #endif
8128 //current.is32|=1LL<<rt1[i];
8129 }
269bb29a 8130 ooo[i]=1;
8131 delayslot_alloc(&current,i+1);
57871462 8132 //current.isconst=0; // DEBUG
8133 ds=1;
8134 //printf("i=%d, isconst=%x\n",i,current.isconst);
8135 break;
8136 case RJUMP:
8137 //current.isconst=0;
8138 //current.wasconst=0;
8139 //regs[i].wasconst=0;
8140 clear_const(&current,rs1[i]);
8141 clear_const(&current,rt1[i]);
8142 alloc_cc(&current,i);
8143 dirty_reg(&current,CCREG);
8144 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
8145 alloc_reg(&current,i,rs1[i]);
5067f341 8146 if (rt1[i]!=0) {
8147 alloc_reg(&current,i,rt1[i]);
8148 dirty_reg(&current,rt1[i]);
68b3faee 8149 assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
076655d1 8150 assert(rt1[i+1]!=rt1[i]);
57871462 8151 #ifdef REG_PREFETCH
8152 alloc_reg(&current,i,PTEMP);
8153 #endif
8154 }
8155 #ifdef USE_MINI_HT
8156 if(rs1[i]==31) { // JALR
8157 alloc_reg(&current,i,RHASH);
8158 #ifndef HOST_IMM_ADDR32
8159 alloc_reg(&current,i,RHTBL);
8160 #endif
8161 }
8162 #endif
8163 delayslot_alloc(&current,i+1);
8164 } else {
8165 // The delay slot overwrites our source register,
8166 // allocate a temporary register to hold the old value.
8167 current.isconst=0;
8168 current.wasconst=0;
8169 regs[i].wasconst=0;
8170 delayslot_alloc(&current,i+1);
8171 current.isconst=0;
8172 alloc_reg(&current,i,RTEMP);
8173 }
8174 //current.isconst=0; // DEBUG
e1190b87 8175 ooo[i]=1;
57871462 8176 ds=1;
8177 break;
8178 case CJUMP:
8179 //current.isconst=0;
8180 //current.wasconst=0;
8181 //regs[i].wasconst=0;
8182 clear_const(&current,rs1[i]);
8183 clear_const(&current,rs2[i]);
8184 if((opcode[i]&0x3E)==4) // BEQ/BNE
8185 {
8186 alloc_cc(&current,i);
8187 dirty_reg(&current,CCREG);
8188 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8189 if(rs2[i]) alloc_reg(&current,i,rs2[i]);
8190 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8191 {
8192 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8193 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
8194 }
8195 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
8196 (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
8197 // The delay slot overwrites one of our conditions.
8198 // Allocate the branch condition registers instead.
57871462 8199 current.isconst=0;
8200 current.wasconst=0;
8201 regs[i].wasconst=0;
8202 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8203 if(rs2[i]) alloc_reg(&current,i,rs2[i]);
8204 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8205 {
8206 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8207 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
8208 }
8209 }
e1190b87 8210 else
8211 {
8212 ooo[i]=1;
8213 delayslot_alloc(&current,i+1);
8214 }
57871462 8215 }
8216 else
8217 if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
8218 {
8219 alloc_cc(&current,i);
8220 dirty_reg(&current,CCREG);
8221 alloc_reg(&current,i,rs1[i]);
8222 if(!(current.is32>>rs1[i]&1))
8223 {
8224 alloc_reg64(&current,i,rs1[i]);
8225 }
8226 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
8227 // The delay slot overwrites one of our conditions.
8228 // Allocate the branch condition registers instead.
57871462 8229 current.isconst=0;
8230 current.wasconst=0;
8231 regs[i].wasconst=0;
8232 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8233 if(!((current.is32>>rs1[i])&1))
8234 {
8235 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8236 }
8237 }
e1190b87 8238 else
8239 {
8240 ooo[i]=1;
8241 delayslot_alloc(&current,i+1);
8242 }
57871462 8243 }
8244 else
8245 // Don't alloc the delay slot yet because we might not execute it
8246 if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
8247 {
8248 current.isconst=0;
8249 current.wasconst=0;
8250 regs[i].wasconst=0;
8251 alloc_cc(&current,i);
8252 dirty_reg(&current,CCREG);
8253 alloc_reg(&current,i,rs1[i]);
8254 alloc_reg(&current,i,rs2[i]);
8255 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8256 {
8257 alloc_reg64(&current,i,rs1[i]);
8258 alloc_reg64(&current,i,rs2[i]);
8259 }
8260 }
8261 else
8262 if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
8263 {
8264 current.isconst=0;
8265 current.wasconst=0;
8266 regs[i].wasconst=0;
8267 alloc_cc(&current,i);
8268 dirty_reg(&current,CCREG);
8269 alloc_reg(&current,i,rs1[i]);
8270 if(!(current.is32>>rs1[i]&1))
8271 {
8272 alloc_reg64(&current,i,rs1[i]);
8273 }
8274 }
8275 ds=1;
8276 //current.isconst=0;
8277 break;
8278 case SJUMP:
8279 //current.isconst=0;
8280 //current.wasconst=0;
8281 //regs[i].wasconst=0;
8282 clear_const(&current,rs1[i]);
8283 clear_const(&current,rt1[i]);
8284 //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
8285 if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
8286 {
8287 alloc_cc(&current,i);
8288 dirty_reg(&current,CCREG);
8289 alloc_reg(&current,i,rs1[i]);
8290 if(!(current.is32>>rs1[i]&1))
8291 {
8292 alloc_reg64(&current,i,rs1[i]);
8293 }
8294 if (rt1[i]==31) { // BLTZAL/BGEZAL
8295 alloc_reg(&current,i,31);
8296 dirty_reg(&current,31);
57871462 8297 //#ifdef REG_PREFETCH
8298 //alloc_reg(&current,i,PTEMP);
8299 //#endif
8300 //current.is32|=1LL<<rt1[i];
8301 }
e1190b87 8302 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) // The delay slot overwrites the branch condition.
8303 ||(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))) { // DS touches $ra
57871462 8304 // Allocate the branch condition registers instead.
57871462 8305 current.isconst=0;
8306 current.wasconst=0;
8307 regs[i].wasconst=0;
8308 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8309 if(!((current.is32>>rs1[i])&1))
8310 {
8311 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8312 }
8313 }
e1190b87 8314 else
8315 {
8316 ooo[i]=1;
8317 delayslot_alloc(&current,i+1);
8318 }
57871462 8319 }
8320 else
8321 // Don't alloc the delay slot yet because we might not execute it
8322 if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
8323 {
8324 current.isconst=0;
8325 current.wasconst=0;
8326 regs[i].wasconst=0;
8327 alloc_cc(&current,i);
8328 dirty_reg(&current,CCREG);
8329 alloc_reg(&current,i,rs1[i]);
8330 if(!(current.is32>>rs1[i]&1))
8331 {
8332 alloc_reg64(&current,i,rs1[i]);
8333 }
8334 }
8335 ds=1;
8336 //current.isconst=0;
8337 break;
8338 case FJUMP:
8339 current.isconst=0;
8340 current.wasconst=0;
8341 regs[i].wasconst=0;
8342 if(likely[i]==0) // BC1F/BC1T
8343 {
8344 // TODO: Theoretically we can run out of registers here on x86.
8345 // The delay slot can allocate up to six, and we need to check
8346 // CSREG before executing the delay slot. Possibly we can drop
8347 // the cycle count and then reload it after checking that the
8348 // FPU is in a usable state, or don't do out-of-order execution.
8349 alloc_cc(&current,i);
8350 dirty_reg(&current,CCREG);
8351 alloc_reg(&current,i,FSREG);
8352 alloc_reg(&current,i,CSREG);
8353 if(itype[i+1]==FCOMP) {
8354 // The delay slot overwrites the branch condition.
8355 // Allocate the branch condition registers instead.
57871462 8356 alloc_cc(&current,i);
8357 dirty_reg(&current,CCREG);
8358 alloc_reg(&current,i,CSREG);
8359 alloc_reg(&current,i,FSREG);
8360 }
8361 else {
e1190b87 8362 ooo[i]=1;
57871462 8363 delayslot_alloc(&current,i+1);
8364 alloc_reg(&current,i+1,CSREG);
8365 }
8366 }
8367 else
8368 // Don't alloc the delay slot yet because we might not execute it
8369 if(likely[i]) // BC1FL/BC1TL
8370 {
8371 alloc_cc(&current,i);
8372 dirty_reg(&current,CCREG);
8373 alloc_reg(&current,i,CSREG);
8374 alloc_reg(&current,i,FSREG);
8375 }
8376 ds=1;
8377 current.isconst=0;
8378 break;
8379 case IMM16:
8380 imm16_alloc(&current,i);
8381 break;
8382 case LOAD:
8383 case LOADLR:
8384 load_alloc(&current,i);
8385 break;
8386 case STORE:
8387 case STORELR:
8388 store_alloc(&current,i);
8389 break;
8390 case ALU:
8391 alu_alloc(&current,i);
8392 break;
8393 case SHIFT:
8394 shift_alloc(&current,i);
8395 break;
8396 case MULTDIV:
8397 multdiv_alloc(&current,i);
8398 break;
8399 case SHIFTIMM:
8400 shiftimm_alloc(&current,i);
8401 break;
8402 case MOV:
8403 mov_alloc(&current,i);
8404 break;
8405 case COP0:
8406 cop0_alloc(&current,i);
8407 break;
8408 case COP1:
b9b61529 8409 case COP2:
57871462 8410 cop1_alloc(&current,i);
8411 break;
8412 case C1LS:
8413 c1ls_alloc(&current,i);
8414 break;
b9b61529 8415 case C2LS:
8416 c2ls_alloc(&current,i);
8417 break;
8418 case C2OP:
8419 c2op_alloc(&current,i);
8420 break;
57871462 8421 case FCONV:
8422 fconv_alloc(&current,i);
8423 break;
8424 case FLOAT:
8425 float_alloc(&current,i);
8426 break;
8427 case FCOMP:
8428 fcomp_alloc(&current,i);
8429 break;
8430 case SYSCALL:
7139f3c8 8431 case HLECALL:
1e973cb0 8432 case INTCALL:
57871462 8433 syscall_alloc(&current,i);
8434 break;
8435 case SPAN:
8436 pagespan_alloc(&current,i);
8437 break;
8438 }
9f51b4b9 8439
57871462 8440 // Drop the upper half of registers that have become 32-bit
8441 current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
8442 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8443 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8444 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8445 current.uu|=1;
8446 } else {
8447 current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
8448 current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8449 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8450 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8451 current.uu|=1;
8452 }
8453
8454 // Create entry (branch target) regmap
8455 for(hr=0;hr<HOST_REGS;hr++)
8456 {
581335b0 8457 int r,or;
57871462 8458 r=current.regmap[hr];
8459 if(r>=0) {
8460 if(r!=regmap_pre[i][hr]) {
8461 // TODO: delay slot (?)
8462 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
8463 if(or<0||(r&63)>=TEMPREG){
8464 regs[i].regmap_entry[hr]=-1;
8465 }
8466 else
8467 {
8468 // Just move it to a different register
8469 regs[i].regmap_entry[hr]=r;
8470 // If it was dirty before, it's still dirty
8471 if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r&63);
8472 }
8473 }
8474 else
8475 {
8476 // Unneeded
8477 if(r==0){
8478 regs[i].regmap_entry[hr]=0;
8479 }
8480 else
8481 if(r<64){
8482 if((current.u>>r)&1) {
8483 regs[i].regmap_entry[hr]=-1;
8484 //regs[i].regmap[hr]=-1;
8485 current.regmap[hr]=-1;
8486 }else
8487 regs[i].regmap_entry[hr]=r;
8488 }
8489 else {
8490 if((current.uu>>(r&63))&1) {
8491 regs[i].regmap_entry[hr]=-1;
8492 //regs[i].regmap[hr]=-1;
8493 current.regmap[hr]=-1;
8494 }else
8495 regs[i].regmap_entry[hr]=r;
8496 }
8497 }
8498 } else {
8499 // Branches expect CCREG to be allocated at the target
9f51b4b9 8500 if(regmap_pre[i][hr]==CCREG)
57871462 8501 regs[i].regmap_entry[hr]=CCREG;
8502 else
8503 regs[i].regmap_entry[hr]=-1;
8504 }
8505 }
8506 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
8507 }
27727b63 8508
8509 if(i>0&&(itype[i-1]==STORE||itype[i-1]==STORELR||(itype[i-1]==C2LS&&opcode[i-1]==0x3a))&&(u_int)imm[i-1]<0x800)
8510 current.waswritten|=1<<rs1[i-1];
8511 current.waswritten&=~(1<<rt1[i]);
8512 current.waswritten&=~(1<<rt2[i]);
8513 if((itype[i]==STORE||itype[i]==STORELR||(itype[i]==C2LS&&opcode[i]==0x3a))&&(u_int)imm[i]>=0x800)
8514 current.waswritten&=~(1<<rs1[i]);
8515
57871462 8516 /* Branch post-alloc */
8517 if(i>0)
8518 {
8519 current.was32=current.is32;
8520 current.wasdirty=current.dirty;
8521 switch(itype[i-1]) {
8522 case UJUMP:
8523 memcpy(&branch_regs[i-1],&current,sizeof(current));
8524 branch_regs[i-1].isconst=0;
8525 branch_regs[i-1].wasconst=0;
8526 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
8527 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
8528 alloc_cc(&branch_regs[i-1],i-1);
8529 dirty_reg(&branch_regs[i-1],CCREG);
8530 if(rt1[i-1]==31) { // JAL
8531 alloc_reg(&branch_regs[i-1],i-1,31);
8532 dirty_reg(&branch_regs[i-1],31);
8533 branch_regs[i-1].is32|=1LL<<31;
8534 }
8535 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
956f3129 8536 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
57871462 8537 break;
8538 case RJUMP:
8539 memcpy(&branch_regs[i-1],&current,sizeof(current));
8540 branch_regs[i-1].isconst=0;
8541 branch_regs[i-1].wasconst=0;
8542 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
8543 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
8544 alloc_cc(&branch_regs[i-1],i-1);
8545 dirty_reg(&branch_regs[i-1],CCREG);
8546 alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
5067f341 8547 if(rt1[i-1]!=0) { // JALR
8548 alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
8549 dirty_reg(&branch_regs[i-1],rt1[i-1]);
8550 branch_regs[i-1].is32|=1LL<<rt1[i-1];
57871462 8551 }
8552 #ifdef USE_MINI_HT
8553 if(rs1[i-1]==31) { // JALR
8554 alloc_reg(&branch_regs[i-1],i-1,RHASH);
8555 #ifndef HOST_IMM_ADDR32
8556 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
8557 #endif
8558 }
8559 #endif
8560 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
956f3129 8561 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
57871462 8562 break;
8563 case CJUMP:
8564 if((opcode[i-1]&0x3E)==4) // BEQ/BNE
8565 {
8566 alloc_cc(&current,i-1);
8567 dirty_reg(&current,CCREG);
8568 if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
8569 (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
8570 // The delay slot overwrote one of our conditions
8571 // Delay slot goes after the test (in order)
8572 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8573 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8574 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8575 current.u|=1;
8576 current.uu|=1;
8577 delayslot_alloc(&current,i);
8578 current.isconst=0;
8579 }
8580 else
8581 {
8582 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
8583 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
8584 // Alloc the branch condition registers
8585 if(rs1[i-1]) alloc_reg(&current,i-1,rs1[i-1]);
8586 if(rs2[i-1]) alloc_reg(&current,i-1,rs2[i-1]);
8587 if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
8588 {
8589 if(rs1[i-1]) alloc_reg64(&current,i-1,rs1[i-1]);
8590 if(rs2[i-1]) alloc_reg64(&current,i-1,rs2[i-1]);
8591 }
8592 }
8593 memcpy(&branch_regs[i-1],&current,sizeof(current));
8594 branch_regs[i-1].isconst=0;
8595 branch_regs[i-1].wasconst=0;
8596 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
956f3129 8597 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
57871462 8598 }
8599 else
8600 if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
8601 {
8602 alloc_cc(&current,i-1);
8603 dirty_reg(&current,CCREG);
8604 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
8605 // The delay slot overwrote the branch condition
8606 // Delay slot goes after the test (in order)
8607 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8608 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8609 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8610 current.u|=1;
8611 current.uu|=1;
8612 delayslot_alloc(&current,i);
8613 current.isconst=0;
8614 }
8615 else
8616 {
8617 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
8618 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
8619 // Alloc the branch condition register
8620 alloc_reg(&current,i-1,rs1[i-1]);
8621 if(!(current.is32>>rs1[i-1]&1))
8622 {
8623 alloc_reg64(&current,i-1,rs1[i-1]);
8624 }
8625 }
8626 memcpy(&branch_regs[i-1],&current,sizeof(current));
8627 branch_regs[i-1].isconst=0;
8628 branch_regs[i-1].wasconst=0;
8629 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
956f3129 8630 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
57871462 8631 }
8632 else
8633 // Alloc the delay slot in case the branch is taken
8634 if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
8635 {
8636 memcpy(&branch_regs[i-1],&current,sizeof(current));
8637 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
8638 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
8639 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
8640 alloc_cc(&branch_regs[i-1],i);
8641 dirty_reg(&branch_regs[i-1],CCREG);
8642 delayslot_alloc(&branch_regs[i-1],i);
8643 branch_regs[i-1].isconst=0;
8644 alloc_reg(&current,i,CCREG); // Not taken path
8645 dirty_reg(&current,CCREG);
8646 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8647 }
8648 else
8649 if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
8650 {
8651 memcpy(&branch_regs[i-1],&current,sizeof(current));
8652 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
8653 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
8654 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
8655 alloc_cc(&branch_regs[i-1],i);
8656 dirty_reg(&branch_regs[i-1],CCREG);
8657 delayslot_alloc(&branch_regs[i-1],i);
8658 branch_regs[i-1].isconst=0;
8659 alloc_reg(&current,i,CCREG); // Not taken path
8660 dirty_reg(&current,CCREG);
8661 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8662 }
8663 break;
8664 case SJUMP:
8665 //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
8666 if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
8667 {
8668 alloc_cc(&current,i-1);
8669 dirty_reg(&current,CCREG);
8670 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
8671 // The delay slot overwrote the branch condition
8672 // Delay slot goes after the test (in order)
8673 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8674 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8675 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8676 current.u|=1;
8677 current.uu|=1;
8678 delayslot_alloc(&current,i);
8679 current.isconst=0;
8680 }
8681 else
8682 {
8683 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
8684 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
8685 // Alloc the branch condition register
8686 alloc_reg(&current,i-1,rs1[i-1]);
8687 if(!(current.is32>>rs1[i-1]&1))
8688 {
8689 alloc_reg64(&current,i-1,rs1[i-1]);
8690 }
8691 }
8692 memcpy(&branch_regs[i-1],&current,sizeof(current));
8693 branch_regs[i-1].isconst=0;
8694 branch_regs[i-1].wasconst=0;
8695 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
956f3129 8696 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
57871462 8697 }
8698 else
8699 // Alloc the delay slot in case the branch is taken
8700 if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
8701 {
8702 memcpy(&branch_regs[i-1],&current,sizeof(current));
8703 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
8704 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
8705 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
8706 alloc_cc(&branch_regs[i-1],i);
8707 dirty_reg(&branch_regs[i-1],CCREG);
8708 delayslot_alloc(&branch_regs[i-1],i);
8709 branch_regs[i-1].isconst=0;
8710 alloc_reg(&current,i,CCREG); // Not taken path
8711 dirty_reg(&current,CCREG);
8712 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8713 }
8714 // FIXME: BLTZAL/BGEZAL
8715 if(opcode2[i-1]&0x10) { // BxxZAL
8716 alloc_reg(&branch_regs[i-1],i-1,31);
8717 dirty_reg(&branch_regs[i-1],31);
8718 branch_regs[i-1].is32|=1LL<<31;
8719 }
8720 break;
8721 case FJUMP:
8722 if(likely[i-1]==0) // BC1F/BC1T
8723 {
8724 alloc_cc(&current,i-1);
8725 dirty_reg(&current,CCREG);
8726 if(itype[i]==FCOMP) {
8727 // The delay slot overwrote the branch condition
8728 // Delay slot goes after the test (in order)
8729 delayslot_alloc(&current,i);
8730 current.isconst=0;
8731 }
8732 else
8733 {
8734 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
8735 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
8736 // Alloc the branch condition register
8737 alloc_reg(&current,i-1,FSREG);
8738 }
8739 memcpy(&branch_regs[i-1],&current,sizeof(current));
8740 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
8741 }
8742 else // BC1FL/BC1TL
8743 {
8744 // Alloc the delay slot in case the branch is taken
8745 memcpy(&branch_regs[i-1],&current,sizeof(current));
8746 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
8747 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
8748 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
8749 alloc_cc(&branch_regs[i-1],i);
8750 dirty_reg(&branch_regs[i-1],CCREG);
8751 delayslot_alloc(&branch_regs[i-1],i);
8752 branch_regs[i-1].isconst=0;
8753 alloc_reg(&current,i,CCREG); // Not taken path
8754 dirty_reg(&current,CCREG);
8755 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8756 }
8757 break;
8758 }
8759
8760 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
8761 {
8762 if(rt1[i-1]==31) // JAL/JALR
8763 {
8764 // Subroutine call will return here, don't alloc any registers
8765 current.is32=1;
8766 current.dirty=0;
8767 clear_all_regs(current.regmap);
8768 alloc_reg(&current,i,CCREG);
8769 dirty_reg(&current,CCREG);
8770 }
8771 else if(i+1<slen)
8772 {
8773 // Internal branch will jump here, match registers to caller
8774 current.is32=0x3FFFFFFFFLL;
8775 current.dirty=0;
8776 clear_all_regs(current.regmap);
8777 alloc_reg(&current,i,CCREG);
8778 dirty_reg(&current,CCREG);
8779 for(j=i-1;j>=0;j--)
8780 {
8781 if(ba[j]==start+i*4+4) {
8782 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
8783 current.is32=branch_regs[j].is32;
8784 current.dirty=branch_regs[j].dirty;
8785 break;
8786 }
8787 }
8788 while(j>=0) {
8789 if(ba[j]==start+i*4+4) {
8790 for(hr=0;hr<HOST_REGS;hr++) {
8791 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
8792 current.regmap[hr]=-1;
8793 }
8794 current.is32&=branch_regs[j].is32;
8795 current.dirty&=branch_regs[j].dirty;
8796 }
8797 }
8798 j--;
8799 }
8800 }
8801 }
8802 }
8803
8804 // Count cycles in between branches
8805 ccadj[i]=cc;
7139f3c8 8806 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
57871462 8807 {
8808 cc=0;
8809 }
71e490c5 8810#if !defined(DRC_DBG)
054175e9 8811 else if(itype[i]==C2OP&&gte_cycletab[source[i]&0x3f]>2)
8812 {
8813 // GTE runs in parallel until accessed, divide by 2 for a rough guess
8814 cc+=gte_cycletab[source[i]&0x3f]/2;
8815 }
b6e87b2b 8816 else if(/*itype[i]==LOAD||itype[i]==STORE||*/itype[i]==C1LS) // load,store causes weird timing issues
fb407447 8817 {
8818 cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
8819 }
5fdcbb5a 8820 else if(i>1&&itype[i]==STORE&&itype[i-1]==STORE&&itype[i-2]==STORE&&!bt[i])
8821 {
8822 cc+=4;
8823 }
fb407447 8824 else if(itype[i]==C2LS)
8825 {
8826 cc+=4;
8827 }
8828#endif
57871462 8829 else
8830 {
8831 cc++;
8832 }
8833
8834 flush_dirty_uppers(&current);
8835 if(!is_ds[i]) {
8836 regs[i].is32=current.is32;
8837 regs[i].dirty=current.dirty;
8838 regs[i].isconst=current.isconst;
956f3129 8839 memcpy(constmap[i],current_constmap,sizeof(current_constmap));
57871462 8840 }
8841 for(hr=0;hr<HOST_REGS;hr++) {
8842 if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
8843 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
8844 regs[i].wasconst&=~(1<<hr);
8845 }
8846 }
8847 }
8848 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
27727b63 8849 regs[i].waswritten=current.waswritten;
57871462 8850 }
9f51b4b9 8851
57871462 8852 /* Pass 4 - Cull unused host registers */
9f51b4b9 8853
57871462 8854 uint64_t nr=0;
9f51b4b9 8855
57871462 8856 for (i=slen-1;i>=0;i--)
8857 {
8858 int hr;
8859 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
8860 {
8861 if(ba[i]<start || ba[i]>=(start+slen*4))
8862 {
8863 // Branch out of this block, don't need anything
8864 nr=0;
8865 }
8866 else
8867 {
8868 // Internal branch
8869 // Need whatever matches the target
8870 nr=0;
8871 int t=(ba[i]-start)>>2;
8872 for(hr=0;hr<HOST_REGS;hr++)
8873 {
8874 if(regs[i].regmap_entry[hr]>=0) {
8875 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
8876 }
8877 }
8878 }
8879 // Conditional branch may need registers for following instructions
8880 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
8881 {
8882 if(i<slen-2) {
8883 nr|=needed_reg[i+2];
8884 for(hr=0;hr<HOST_REGS;hr++)
8885 {
8886 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
8887 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
8888 }
8889 }
8890 }
8891 // Don't need stuff which is overwritten
f5955059 8892 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
8893 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
57871462 8894 // Merge in delay slot
8895 for(hr=0;hr<HOST_REGS;hr++)
8896 {
8897 if(!likely[i]) {
8898 // These are overwritten unless the branch is "likely"
8899 // and the delay slot is nullified if not taken
8900 if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8901 if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8902 }
8903 if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8904 if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8905 if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
8906 if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
8907 if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8908 if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8909 if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
8910 if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
8911 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
8912 if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8913 if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8914 }
8915 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
8916 if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8917 if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8918 }
b9b61529 8919 if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
57871462 8920 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
8921 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
8922 }
8923 }
8924 }
1e973cb0 8925 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 8926 {
8927 // SYSCALL instruction (software interrupt)
8928 nr=0;
8929 }
8930 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
8931 {
8932 // ERET instruction (return from interrupt)
8933 nr=0;
8934 }
8935 else // Non-branch
8936 {
8937 if(i<slen-1) {
8938 for(hr=0;hr<HOST_REGS;hr++) {
8939 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
8940 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
8941 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
8942 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
8943 }
8944 }
8945 }
8946 for(hr=0;hr<HOST_REGS;hr++)
8947 {
8948 // Overwritten registers are not needed
8949 if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8950 if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8951 if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8952 // Source registers are needed
8953 if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8954 if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8955 if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
8956 if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
8957 if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8958 if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8959 if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
8960 if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
8961 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
8962 if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8963 if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8964 }
8965 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
8966 if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8967 if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8968 }
b9b61529 8969 if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
57871462 8970 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
8971 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
8972 }
8973 // Don't store a register immediately after writing it,
8974 // may prevent dual-issue.
8975 // But do so if this is a branch target, otherwise we
8976 // might have to load the register before the branch.
8977 if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
8978 if((regmap_pre[i][hr]>0&&regmap_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
8979 (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
8980 if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8981 if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8982 }
8983 if((regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
8984 (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
8985 if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8986 if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8987 }
8988 }
8989 }
8990 // Cycle count is needed at branches. Assume it is needed at the target too.
8991 if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
8992 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
8993 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
8994 }
8995 // Save it
8996 needed_reg[i]=nr;
9f51b4b9 8997
57871462 8998 // Deallocate unneeded registers
8999 for(hr=0;hr<HOST_REGS;hr++)
9000 {
9001 if(!((nr>>hr)&1)) {
9002 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
9003 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9004 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9005 (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
9006 {
9007 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9008 {
9009 if(likely[i]) {
9010 regs[i].regmap[hr]=-1;
9011 regs[i].isconst&=~(1<<hr);
79c75f1b 9012 if(i<slen-2) {
9013 regmap_pre[i+2][hr]=-1;
9014 regs[i+2].wasconst&=~(1<<hr);
9015 }
57871462 9016 }
9017 }
9018 }
9019 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9020 {
9021 int d1=0,d2=0,map=0,temp=0;
9022 if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
9023 {
9024 d1=dep1[i+1];
9025 d2=dep2[i+1];
9026 }
b9b61529 9027 if(itype[i+1]==STORE || itype[i+1]==STORELR ||
9028 (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
57871462 9029 map=INVCP;
9030 }
9031 if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
b9b61529 9032 itype[i+1]==C1LS || itype[i+1]==C2LS)
57871462 9033 temp=FTEMP;
9034 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9035 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9036 (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
9037 (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
9038 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9039 regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
9040 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
9041 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
9042 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
9043 regs[i].regmap[hr]!=map )
9044 {
9045 regs[i].regmap[hr]=-1;
9046 regs[i].isconst&=~(1<<hr);
9047 if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
9048 (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
9049 (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
9050 (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
9051 (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
9052 branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
9053 (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
9054 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
9055 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
9056 branch_regs[i].regmap[hr]!=map)
9057 {
9058 branch_regs[i].regmap[hr]=-1;
9059 branch_regs[i].regmap_entry[hr]=-1;
9060 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9061 {
9062 if(!likely[i]&&i<slen-2) {
9063 regmap_pre[i+2][hr]=-1;
79c75f1b 9064 regs[i+2].wasconst&=~(1<<hr);
57871462 9065 }
9066 }
9067 }
9068 }
9069 }
9070 else
9071 {
9072 // Non-branch
9073 if(i>0)
9074 {
9075 int d1=0,d2=0,map=-1,temp=-1;
9076 if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
9077 {
9078 d1=dep1[i];
9079 d2=dep2[i];
9080 }
1edfcc68 9081 if(itype[i]==STORE || itype[i]==STORELR ||
b9b61529 9082 (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
57871462 9083 map=INVCP;
9084 }
9085 if(itype[i]==LOADLR || itype[i]==STORELR ||
b9b61529 9086 itype[i]==C1LS || itype[i]==C2LS)
57871462 9087 temp=FTEMP;
9088 if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9089 (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
9090 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9091 regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
9092 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
9093 (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
9094 {
9095 if(i<slen-1&&!is_ds[i]) {
9096 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
9097 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
9098 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
9099 {
c43b5311 9100 SysPrintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
57871462 9101 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
9102 }
9103 regmap_pre[i+1][hr]=-1;
9104 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
79c75f1b 9105 regs[i+1].wasconst&=~(1<<hr);
57871462 9106 }
9107 regs[i].regmap[hr]=-1;
9108 regs[i].isconst&=~(1<<hr);
9109 }
9110 }
9111 }
9112 }
9113 }
9114 }
9f51b4b9 9115
57871462 9116 /* Pass 5 - Pre-allocate registers */
9f51b4b9 9117
57871462 9118 // If a register is allocated during a loop, try to allocate it for the
9119 // entire loop, if possible. This avoids loading/storing registers
9120 // inside of the loop.
9f51b4b9 9121
57871462 9122 signed char f_regmap[HOST_REGS];
9123 clear_all_regs(f_regmap);
9124 for(i=0;i<slen-1;i++)
9125 {
9126 if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9127 {
9f51b4b9 9128 if(ba[i]>=start && ba[i]<(start+i*4))
57871462 9129 if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
9130 ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
9131 ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
9132 ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
b9b61529 9133 ||itype[i+1]==FCOMP||itype[i+1]==FCONV
9134 ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
57871462 9135 {
9136 int t=(ba[i]-start)>>2;
9137 if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
198df76f 9138 if(t<2||(itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||rt1[t-2]!=31) // call/ret assumes no registers allocated
57871462 9139 for(hr=0;hr<HOST_REGS;hr++)
9140 {
9141 if(regs[i].regmap[hr]>64) {
9142 if(!((regs[i].dirty>>hr)&1))
9143 f_regmap[hr]=regs[i].regmap[hr];
9144 else f_regmap[hr]=-1;
9145 }
b372a952 9146 else if(regs[i].regmap[hr]>=0) {
9147 if(f_regmap[hr]!=regs[i].regmap[hr]) {
9148 // dealloc old register
9149 int n;
9150 for(n=0;n<HOST_REGS;n++)
9151 {
9152 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
9153 }
9154 // and alloc new one
9155 f_regmap[hr]=regs[i].regmap[hr];
9156 }
9157 }
57871462 9158 if(branch_regs[i].regmap[hr]>64) {
9159 if(!((branch_regs[i].dirty>>hr)&1))
9160 f_regmap[hr]=branch_regs[i].regmap[hr];
9161 else f_regmap[hr]=-1;
9162 }
b372a952 9163 else if(branch_regs[i].regmap[hr]>=0) {
9164 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
9165 // dealloc old register
9166 int n;
9167 for(n=0;n<HOST_REGS;n++)
9168 {
9169 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
9170 }
9171 // and alloc new one
9172 f_regmap[hr]=branch_regs[i].regmap[hr];
9173 }
9174 }
e1190b87 9175 if(ooo[i]) {
9f51b4b9 9176 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
e1190b87 9177 f_regmap[hr]=branch_regs[i].regmap[hr];
9178 }else{
9f51b4b9 9179 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
57871462 9180 f_regmap[hr]=branch_regs[i].regmap[hr];
9181 }
9182 // Avoid dirty->clean transition
e1190b87 9183 #ifdef DESTRUCTIVE_WRITEBACK
57871462 9184 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
e1190b87 9185 #endif
9186 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
9187 // case above, however it's always a good idea. We can't hoist the
9188 // load if the register was already allocated, so there's no point
9189 // wasting time analyzing most of these cases. It only "succeeds"
9190 // when the mapping was different and the load can be replaced with
9191 // a mov, which is of negligible benefit. So such cases are
9192 // skipped below.
57871462 9193 if(f_regmap[hr]>0) {
198df76f 9194 if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
57871462 9195 int r=f_regmap[hr];
9196 for(j=t;j<=i;j++)
9197 {
9198 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9199 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
9200 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
9201 if(r>63) {
9202 // NB This can exclude the case where the upper-half
9203 // register is lower numbered than the lower-half
9204 // register. Not sure if it's worth fixing...
9205 if(get_reg(regs[j].regmap,r&63)<0) break;
e1190b87 9206 if(get_reg(regs[j].regmap_entry,r&63)<0) break;
57871462 9207 if(regs[j].is32&(1LL<<(r&63))) break;
9208 }
9209 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
9210 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9211 int k;
9212 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
9213 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
9214 if(r>63) {
9215 if(get_reg(regs[i].regmap,r&63)<0) break;
9216 if(get_reg(branch_regs[i].regmap,r&63)<0) break;
9217 }
9218 k=i;
9219 while(k>1&&regs[k-1].regmap[hr]==-1) {
e1190b87 9220 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
9221 //printf("no free regs for store %x\n",start+(k-1)*4);
9222 break;
57871462 9223 }
57871462 9224 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
9225 //printf("no-match due to different register\n");
9226 break;
9227 }
9228 if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
9229 //printf("no-match due to branch\n");
9230 break;
9231 }
9232 // call/ret fast path assumes no registers allocated
198df76f 9233 if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)&&rt1[k-3]==31) {
57871462 9234 break;
9235 }
9236 if(r>63) {
9237 // NB This can exclude the case where the upper-half
9238 // register is lower numbered than the lower-half
9239 // register. Not sure if it's worth fixing...
9240 if(get_reg(regs[k-1].regmap,r&63)<0) break;
9241 if(regs[k-1].is32&(1LL<<(r&63))) break;
9242 }
9243 k--;
9244 }
9245 if(i<slen-1) {
9246 if((regs[k].is32&(1LL<<f_regmap[hr]))!=
9247 (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
9248 //printf("bad match after branch\n");
9249 break;
9250 }
9251 }
9252 if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
9253 //printf("Extend r%d, %x ->\n",hr,start+k*4);
9254 while(k<i) {
9255 regs[k].regmap_entry[hr]=f_regmap[hr];
9256 regs[k].regmap[hr]=f_regmap[hr];
9257 regmap_pre[k+1][hr]=f_regmap[hr];
9258 regs[k].wasdirty&=~(1<<hr);
9259 regs[k].dirty&=~(1<<hr);
9260 regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
9261 regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
9262 regs[k].wasconst&=~(1<<hr);
9263 regs[k].isconst&=~(1<<hr);
9264 k++;
9265 }
9266 }
9267 else {
9268 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
9269 break;
9270 }
9271 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
9272 if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
9273 //printf("OK fill %x (r%d)\n",start+i*4,hr);
9274 regs[i].regmap_entry[hr]=f_regmap[hr];
9275 regs[i].regmap[hr]=f_regmap[hr];
9276 regs[i].wasdirty&=~(1<<hr);
9277 regs[i].dirty&=~(1<<hr);
9278 regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
9279 regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
9280 regs[i].wasconst&=~(1<<hr);
9281 regs[i].isconst&=~(1<<hr);
9282 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
9283 branch_regs[i].wasdirty&=~(1<<hr);
9284 branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
9285 branch_regs[i].regmap[hr]=f_regmap[hr];
9286 branch_regs[i].dirty&=~(1<<hr);
9287 branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
9288 branch_regs[i].wasconst&=~(1<<hr);
9289 branch_regs[i].isconst&=~(1<<hr);
9290 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
9291 regmap_pre[i+2][hr]=f_regmap[hr];
9292 regs[i+2].wasdirty&=~(1<<hr);
9293 regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
9294 assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
9295 (regs[i+2].was32&(1LL<<f_regmap[hr])));
9296 }
9297 }
9298 }
9299 for(k=t;k<j;k++) {
e1190b87 9300 // Alloc register clean at beginning of loop,
9301 // but may dirty it in pass 6
57871462 9302 regs[k].regmap_entry[hr]=f_regmap[hr];
9303 regs[k].regmap[hr]=f_regmap[hr];
57871462 9304 regs[k].dirty&=~(1<<hr);
9305 regs[k].wasconst&=~(1<<hr);
9306 regs[k].isconst&=~(1<<hr);
e1190b87 9307 if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) {
9308 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
9309 branch_regs[k].regmap[hr]=f_regmap[hr];
9310 branch_regs[k].dirty&=~(1<<hr);
9311 branch_regs[k].wasconst&=~(1<<hr);
9312 branch_regs[k].isconst&=~(1<<hr);
9313 if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
9314 regmap_pre[k+2][hr]=f_regmap[hr];
9315 regs[k+2].wasdirty&=~(1<<hr);
9316 assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))==
9317 (regs[k+2].was32&(1LL<<f_regmap[hr])));
9318 }
9319 }
9320 else
9321 {
9322 regmap_pre[k+1][hr]=f_regmap[hr];
9323 regs[k+1].wasdirty&=~(1<<hr);
9324 }
57871462 9325 }
9326 if(regs[j].regmap[hr]==f_regmap[hr])
9327 regs[j].regmap_entry[hr]=f_regmap[hr];
9328 break;
9329 }
9330 if(j==i) break;
9331 if(regs[j].regmap[hr]>=0)
9332 break;
9333 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
9334 //printf("no-match due to different register\n");
9335 break;
9336 }
9337 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
9338 //printf("32/64 mismatch %x %d\n",start+j*4,hr);
9339 break;
9340 }
e1190b87 9341 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
9342 {
9343 // Stop on unconditional branch
9344 break;
9345 }
9346 if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
9347 {
9348 if(ooo[j]) {
9f51b4b9 9349 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
e1190b87 9350 break;
9351 }else{
9f51b4b9 9352 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
e1190b87 9353 break;
9354 }
9355 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
9356 //printf("no-match due to different register (branch)\n");
57871462 9357 break;
9358 }
9359 }
e1190b87 9360 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
9361 //printf("No free regs for store %x\n",start+j*4);
9362 break;
9363 }
57871462 9364 if(f_regmap[hr]>=64) {
9365 if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
9366 break;
9367 }
9368 else
9369 {
9370 if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
9371 break;
9372 }
9373 }
9374 }
9375 }
9376 }
9377 }
9378 }
9379 }
9380 }else{
198df76f 9381 // Non branch or undetermined branch target
57871462 9382 for(hr=0;hr<HOST_REGS;hr++)
9383 {
9384 if(hr!=EXCLUDE_REG) {
9385 if(regs[i].regmap[hr]>64) {
9386 if(!((regs[i].dirty>>hr)&1))
9387 f_regmap[hr]=regs[i].regmap[hr];
9388 }
b372a952 9389 else if(regs[i].regmap[hr]>=0) {
9390 if(f_regmap[hr]!=regs[i].regmap[hr]) {
9391 // dealloc old register
9392 int n;
9393 for(n=0;n<HOST_REGS;n++)
9394 {
9395 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
9396 }
9397 // and alloc new one
9398 f_regmap[hr]=regs[i].regmap[hr];
9399 }
9400 }
57871462 9401 }
9402 }
9403 // Try to restore cycle count at branch targets
9404 if(bt[i]) {
9405 for(j=i;j<slen-1;j++) {
9406 if(regs[j].regmap[HOST_CCREG]!=-1) break;
e1190b87 9407 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
9408 //printf("no free regs for store %x\n",start+j*4);
9409 break;
57871462 9410 }
57871462 9411 }
9412 if(regs[j].regmap[HOST_CCREG]==CCREG) {
9413 int k=i;
9414 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
9415 while(k<j) {
9416 regs[k].regmap_entry[HOST_CCREG]=CCREG;
9417 regs[k].regmap[HOST_CCREG]=CCREG;
9418 regmap_pre[k+1][HOST_CCREG]=CCREG;
9419 regs[k+1].wasdirty|=1<<HOST_CCREG;
9420 regs[k].dirty|=1<<HOST_CCREG;
9421 regs[k].wasconst&=~(1<<HOST_CCREG);
9422 regs[k].isconst&=~(1<<HOST_CCREG);
9423 k++;
9424 }
9f51b4b9 9425 regs[j].regmap_entry[HOST_CCREG]=CCREG;
57871462 9426 }
9427 // Work backwards from the branch target
9428 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
9429 {
9430 //printf("Extend backwards\n");
9431 int k;
9432 k=i;
9433 while(regs[k-1].regmap[HOST_CCREG]==-1) {
e1190b87 9434 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
9435 //printf("no free regs for store %x\n",start+(k-1)*4);
9436 break;
57871462 9437 }
57871462 9438 k--;
9439 }
9440 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
9441 //printf("Extend CC, %x ->\n",start+k*4);
9442 while(k<=i) {
9443 regs[k].regmap_entry[HOST_CCREG]=CCREG;
9444 regs[k].regmap[HOST_CCREG]=CCREG;
9445 regmap_pre[k+1][HOST_CCREG]=CCREG;
9446 regs[k+1].wasdirty|=1<<HOST_CCREG;
9447 regs[k].dirty|=1<<HOST_CCREG;
9448 regs[k].wasconst&=~(1<<HOST_CCREG);
9449 regs[k].isconst&=~(1<<HOST_CCREG);
9450 k++;
9451 }
9452 }
9453 else {
9454 //printf("Fail Extend CC, %x ->\n",start+k*4);
9455 }
9456 }
9457 }
9458 if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
9459 itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
9460 itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
e1190b87 9461 itype[i]!=FCONV&&itype[i]!=FCOMP)
57871462 9462 {
9463 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
9464 }
9465 }
9466 }
9f51b4b9 9467
d61de97e 9468 // Cache memory offset or tlb map pointer if a register is available
9469 #ifndef HOST_IMM_ADDR32
9470 #ifndef RAM_OFFSET
1edfcc68 9471 if(0)
d61de97e 9472 #endif
9473 {
9474 int earliest_available[HOST_REGS];
9475 int loop_start[HOST_REGS];
9476 int score[HOST_REGS];
9477 int end[HOST_REGS];
1edfcc68 9478 int reg=ROREG;
d61de97e 9479
9480 // Init
9481 for(hr=0;hr<HOST_REGS;hr++) {
9482 score[hr]=0;earliest_available[hr]=0;
9483 loop_start[hr]=MAXBLOCK;
9484 }
9485 for(i=0;i<slen-1;i++)
9486 {
9487 // Can't do anything if no registers are available
9488 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i]) {
9489 for(hr=0;hr<HOST_REGS;hr++) {
9490 score[hr]=0;earliest_available[hr]=i+1;
9491 loop_start[hr]=MAXBLOCK;
9492 }
9493 }
9494 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
9495 if(!ooo[i]) {
9496 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) {
9497 for(hr=0;hr<HOST_REGS;hr++) {
9498 score[hr]=0;earliest_available[hr]=i+1;
9499 loop_start[hr]=MAXBLOCK;
9500 }
9501 }
198df76f 9502 }else{
9503 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) {
9504 for(hr=0;hr<HOST_REGS;hr++) {
9505 score[hr]=0;earliest_available[hr]=i+1;
9506 loop_start[hr]=MAXBLOCK;
9507 }
9508 }
d61de97e 9509 }
9510 }
9511 // Mark unavailable registers
9512 for(hr=0;hr<HOST_REGS;hr++) {
9513 if(regs[i].regmap[hr]>=0) {
9514 score[hr]=0;earliest_available[hr]=i+1;
9515 loop_start[hr]=MAXBLOCK;
9516 }
9517 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
9518 if(branch_regs[i].regmap[hr]>=0) {
9519 score[hr]=0;earliest_available[hr]=i+2;
9520 loop_start[hr]=MAXBLOCK;
9521 }
9522 }
9523 }
9524 // No register allocations after unconditional jumps
9525 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
9526 {
9527 for(hr=0;hr<HOST_REGS;hr++) {
9528 score[hr]=0;earliest_available[hr]=i+2;
9529 loop_start[hr]=MAXBLOCK;
9530 }
9531 i++; // Skip delay slot too
9532 //printf("skip delay slot: %x\n",start+i*4);
9533 }
9534 else
9535 // Possible match
9536 if(itype[i]==LOAD||itype[i]==LOADLR||
9537 itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) {
9538 for(hr=0;hr<HOST_REGS;hr++) {
9539 if(hr!=EXCLUDE_REG) {
9540 end[hr]=i-1;
9541 for(j=i;j<slen-1;j++) {
9542 if(regs[j].regmap[hr]>=0) break;
9543 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
9544 if(branch_regs[j].regmap[hr]>=0) break;
9545 if(ooo[j]) {
9546 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) break;
9547 }else{
9548 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) break;
9549 }
9550 }
9551 else if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) break;
9552 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
9553 int t=(ba[j]-start)>>2;
9554 if(t<j&&t>=earliest_available[hr]) {
198df76f 9555 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) { // call/ret assumes no registers allocated
9556 // Score a point for hoisting loop invariant
9557 if(t<loop_start[hr]) loop_start[hr]=t;
9558 //printf("set loop_start: i=%x j=%x (%x)\n",start+i*4,start+j*4,start+t*4);
9559 score[hr]++;
9560 end[hr]=j;
9561 }
d61de97e 9562 }
9563 else if(t<j) {
9564 if(regs[t].regmap[hr]==reg) {
9565 // Score a point if the branch target matches this register
9566 score[hr]++;
9567 end[hr]=j;
9568 }
9569 }
9570 if(itype[j+1]==LOAD||itype[j+1]==LOADLR||
9571 itype[j+1]==STORE||itype[j+1]==STORELR||itype[j+1]==C1LS) {
9572 score[hr]++;
9573 end[hr]=j;
9574 }
9575 }
9576 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
9577 {
9578 // Stop on unconditional branch
9579 break;
9580 }
9581 else
9582 if(itype[j]==LOAD||itype[j]==LOADLR||
9583 itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS) {
9584 score[hr]++;
9585 end[hr]=j;
9586 }
9587 }
9588 }
9589 }
9590 // Find highest score and allocate that register
9591 int maxscore=0;
9592 for(hr=0;hr<HOST_REGS;hr++) {
9593 if(hr!=EXCLUDE_REG) {
9594 if(score[hr]>score[maxscore]) {
9595 maxscore=hr;
9596 //printf("highest score: %d %d (%x->%x)\n",score[hr],hr,start+i*4,start+end[hr]*4);
9597 }
9598 }
9599 }
9600 if(score[maxscore]>1)
9601 {
9602 if(i<loop_start[maxscore]) loop_start[maxscore]=i;
9603 for(j=loop_start[maxscore];j<slen&&j<=end[maxscore];j++) {
9604 //if(regs[j].regmap[maxscore]>=0) {printf("oops: %x %x was %d=%d\n",loop_start[maxscore]*4+start,j*4+start,maxscore,regs[j].regmap[maxscore]);}
9605 assert(regs[j].regmap[maxscore]<0);
9606 if(j>loop_start[maxscore]) regs[j].regmap_entry[maxscore]=reg;
9607 regs[j].regmap[maxscore]=reg;
9608 regs[j].dirty&=~(1<<maxscore);
9609 regs[j].wasconst&=~(1<<maxscore);
9610 regs[j].isconst&=~(1<<maxscore);
9611 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
9612 branch_regs[j].regmap[maxscore]=reg;
9613 branch_regs[j].wasdirty&=~(1<<maxscore);
9614 branch_regs[j].dirty&=~(1<<maxscore);
9615 branch_regs[j].wasconst&=~(1<<maxscore);
9616 branch_regs[j].isconst&=~(1<<maxscore);
9617 if(itype[j]!=RJUMP&&itype[j]!=UJUMP&&(source[j]>>16)!=0x1000) {
9618 regmap_pre[j+2][maxscore]=reg;
9619 regs[j+2].wasdirty&=~(1<<maxscore);
9620 }
9621 // loop optimization (loop_preload)
9622 int t=(ba[j]-start)>>2;
198df76f 9623 if(t==loop_start[maxscore]) {
9624 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) // call/ret assumes no registers allocated
9625 regs[t].regmap_entry[maxscore]=reg;
9626 }
d61de97e 9627 }
9628 else
9629 {
9630 if(j<1||(itype[j-1]!=RJUMP&&itype[j-1]!=UJUMP&&itype[j-1]!=CJUMP&&itype[j-1]!=SJUMP&&itype[j-1]!=FJUMP)) {
9631 regmap_pre[j+1][maxscore]=reg;
9632 regs[j+1].wasdirty&=~(1<<maxscore);
9633 }
9634 }
9635 }
9636 i=j-1;
9637 if(itype[j-1]==RJUMP||itype[j-1]==UJUMP||itype[j-1]==CJUMP||itype[j-1]==SJUMP||itype[j-1]==FJUMP) i++; // skip delay slot
9638 for(hr=0;hr<HOST_REGS;hr++) {
9639 score[hr]=0;earliest_available[hr]=i+i;
9640 loop_start[hr]=MAXBLOCK;
9641 }
9642 }
9643 }
9644 }
9645 }
9646 #endif
9f51b4b9 9647
57871462 9648 // This allocates registers (if possible) one instruction prior
9649 // to use, which can avoid a load-use penalty on certain CPUs.
9650 for(i=0;i<slen-1;i++)
9651 {
9652 if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
9653 {
9654 if(!bt[i+1])
9655 {
b9b61529 9656 if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
9657 ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
57871462 9658 {
9659 if(rs1[i+1]) {
9660 if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
9661 {
9662 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
9663 {
9664 regs[i].regmap[hr]=regs[i+1].regmap[hr];
9665 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
9666 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
9667 regs[i].isconst&=~(1<<hr);
9668 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9669 constmap[i][hr]=constmap[i+1][hr];
9670 regs[i+1].wasdirty&=~(1<<hr);
9671 regs[i].dirty&=~(1<<hr);
9672 }
9673 }
9674 }
9675 if(rs2[i+1]) {
9676 if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
9677 {
9678 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
9679 {
9680 regs[i].regmap[hr]=regs[i+1].regmap[hr];
9681 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
9682 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
9683 regs[i].isconst&=~(1<<hr);
9684 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9685 constmap[i][hr]=constmap[i+1][hr];
9686 regs[i+1].wasdirty&=~(1<<hr);
9687 regs[i].dirty&=~(1<<hr);
9688 }
9689 }
9690 }
198df76f 9691 // Preload target address for load instruction (non-constant)
57871462 9692 if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
9693 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
9694 {
9695 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
9696 {
9697 regs[i].regmap[hr]=rs1[i+1];
9698 regmap_pre[i+1][hr]=rs1[i+1];
9699 regs[i+1].regmap_entry[hr]=rs1[i+1];
9700 regs[i].isconst&=~(1<<hr);
9701 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9702 constmap[i][hr]=constmap[i+1][hr];
9703 regs[i+1].wasdirty&=~(1<<hr);
9704 regs[i].dirty&=~(1<<hr);
9705 }
9706 }
9707 }
9f51b4b9 9708 // Load source into target register
57871462 9709 if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
9710 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
9711 {
9712 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
9713 {
9714 regs[i].regmap[hr]=rs1[i+1];
9715 regmap_pre[i+1][hr]=rs1[i+1];
9716 regs[i+1].regmap_entry[hr]=rs1[i+1];
9717 regs[i].isconst&=~(1<<hr);
9718 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9719 constmap[i][hr]=constmap[i+1][hr];
9720 regs[i+1].wasdirty&=~(1<<hr);
9721 regs[i].dirty&=~(1<<hr);
9722 }
9723 }
9724 }
198df76f 9725 // Address for store instruction (non-constant)
b9b61529 9726 if(itype[i+1]==STORE||itype[i+1]==STORELR
9727 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
57871462 9728 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
9729 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
9730 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
9731 else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
9732 assert(hr>=0);
9733 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
9734 {
9735 regs[i].regmap[hr]=rs1[i+1];
9736 regmap_pre[i+1][hr]=rs1[i+1];
9737 regs[i+1].regmap_entry[hr]=rs1[i+1];
9738 regs[i].isconst&=~(1<<hr);
9739 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9740 constmap[i][hr]=constmap[i+1][hr];
9741 regs[i+1].wasdirty&=~(1<<hr);
9742 regs[i].dirty&=~(1<<hr);
9743 }
9744 }
9745 }
b9b61529 9746 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
57871462 9747 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
9748 int nr;
9749 hr=get_reg(regs[i+1].regmap,FTEMP);
9750 assert(hr>=0);
9751 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
9752 {
9753 regs[i].regmap[hr]=rs1[i+1];
9754 regmap_pre[i+1][hr]=rs1[i+1];
9755 regs[i+1].regmap_entry[hr]=rs1[i+1];
9756 regs[i].isconst&=~(1<<hr);
9757 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9758 constmap[i][hr]=constmap[i+1][hr];
9759 regs[i+1].wasdirty&=~(1<<hr);
9760 regs[i].dirty&=~(1<<hr);
9761 }
9762 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
9763 {
9764 // move it to another register
9765 regs[i+1].regmap[hr]=-1;
9766 regmap_pre[i+2][hr]=-1;
9767 regs[i+1].regmap[nr]=FTEMP;
9768 regmap_pre[i+2][nr]=FTEMP;
9769 regs[i].regmap[nr]=rs1[i+1];
9770 regmap_pre[i+1][nr]=rs1[i+1];
9771 regs[i+1].regmap_entry[nr]=rs1[i+1];
9772 regs[i].isconst&=~(1<<nr);
9773 regs[i+1].isconst&=~(1<<nr);
9774 regs[i].dirty&=~(1<<nr);
9775 regs[i+1].wasdirty&=~(1<<nr);
9776 regs[i+1].dirty&=~(1<<nr);
9777 regs[i+2].wasdirty&=~(1<<nr);
9778 }
9779 }
9780 }
b9b61529 9781 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
9f51b4b9 9782 if(itype[i+1]==LOAD)
57871462 9783 hr=get_reg(regs[i+1].regmap,rt1[i+1]);
b9b61529 9784 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
57871462 9785 hr=get_reg(regs[i+1].regmap,FTEMP);
b9b61529 9786 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
57871462 9787 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
9788 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
9789 }
9790 if(hr>=0&&regs[i].regmap[hr]<0) {
9791 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
9792 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
9793 regs[i].regmap[hr]=AGEN1+((i+1)&1);
9794 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
9795 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
9796 regs[i].isconst&=~(1<<hr);
9797 regs[i+1].wasdirty&=~(1<<hr);
9798 regs[i].dirty&=~(1<<hr);
9799 }
9800 }
9801 }
9802 }
9803 }
9804 }
9805 }
9f51b4b9 9806
57871462 9807 /* Pass 6 - Optimize clean/dirty state */
9808 clean_registers(0,slen-1,1);
9f51b4b9 9809
57871462 9810 /* Pass 7 - Identify 32-bit registers */
04fd948a 9811 for (i=slen-1;i>=0;i--)
9812 {
9813 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9814 {
9815 // Conditional branch
9816 if((source[i]>>16)!=0x1000&&i<slen-2) {
9817 // Mark this address as a branch target since it may be called
9818 // upon return from interrupt
9819 bt[i+2]=1;
9820 }
9821 }
9822 }
57871462 9823
9824 if(itype[slen-1]==SPAN) {
9825 bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
9826 }
4600ba03 9827
9828#ifdef DISASM
57871462 9829 /* Debug/disassembly */
57871462 9830 for(i=0;i<slen;i++)
9831 {
9832 printf("U:");
9833 int r;
9834 for(r=1;r<=CCREG;r++) {
9835 if((unneeded_reg[i]>>r)&1) {
9836 if(r==HIREG) printf(" HI");
9837 else if(r==LOREG) printf(" LO");
9838 else printf(" r%d",r);
9839 }
9840 }
57871462 9841 printf("\n");
9842 #if defined(__i386__) || defined(__x86_64__)
9843 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
9844 #endif
9845 #ifdef __arm__
9846 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
9847 #endif
9848 printf("needs: ");
9849 if(needed_reg[i]&1) printf("eax ");
9850 if((needed_reg[i]>>1)&1) printf("ecx ");
9851 if((needed_reg[i]>>2)&1) printf("edx ");
9852 if((needed_reg[i]>>3)&1) printf("ebx ");
9853 if((needed_reg[i]>>5)&1) printf("ebp ");
9854 if((needed_reg[i]>>6)&1) printf("esi ");
9855 if((needed_reg[i]>>7)&1) printf("edi ");
57871462 9856 printf("\n");
57871462 9857 #if defined(__i386__) || defined(__x86_64__)
9858 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
9859 printf("dirty: ");
9860 if(regs[i].wasdirty&1) printf("eax ");
9861 if((regs[i].wasdirty>>1)&1) printf("ecx ");
9862 if((regs[i].wasdirty>>2)&1) printf("edx ");
9863 if((regs[i].wasdirty>>3)&1) printf("ebx ");
9864 if((regs[i].wasdirty>>5)&1) printf("ebp ");
9865 if((regs[i].wasdirty>>6)&1) printf("esi ");
9866 if((regs[i].wasdirty>>7)&1) printf("edi ");
9867 #endif
9868 #ifdef __arm__
9869 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
9870 printf("dirty: ");
9871 if(regs[i].wasdirty&1) printf("r0 ");
9872 if((regs[i].wasdirty>>1)&1) printf("r1 ");
9873 if((regs[i].wasdirty>>2)&1) printf("r2 ");
9874 if((regs[i].wasdirty>>3)&1) printf("r3 ");
9875 if((regs[i].wasdirty>>4)&1) printf("r4 ");
9876 if((regs[i].wasdirty>>5)&1) printf("r5 ");
9877 if((regs[i].wasdirty>>6)&1) printf("r6 ");
9878 if((regs[i].wasdirty>>7)&1) printf("r7 ");
9879 if((regs[i].wasdirty>>8)&1) printf("r8 ");
9880 if((regs[i].wasdirty>>9)&1) printf("r9 ");
9881 if((regs[i].wasdirty>>10)&1) printf("r10 ");
9882 if((regs[i].wasdirty>>12)&1) printf("r12 ");
9883 #endif
9884 printf("\n");
9885 disassemble_inst(i);
9886 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
9887 #if defined(__i386__) || defined(__x86_64__)
9888 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
9889 if(regs[i].dirty&1) printf("eax ");
9890 if((regs[i].dirty>>1)&1) printf("ecx ");
9891 if((regs[i].dirty>>2)&1) printf("edx ");
9892 if((regs[i].dirty>>3)&1) printf("ebx ");
9893 if((regs[i].dirty>>5)&1) printf("ebp ");
9894 if((regs[i].dirty>>6)&1) printf("esi ");
9895 if((regs[i].dirty>>7)&1) printf("edi ");
9896 #endif
9897 #ifdef __arm__
9898 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
9899 if(regs[i].dirty&1) printf("r0 ");
9900 if((regs[i].dirty>>1)&1) printf("r1 ");
9901 if((regs[i].dirty>>2)&1) printf("r2 ");
9902 if((regs[i].dirty>>3)&1) printf("r3 ");
9903 if((regs[i].dirty>>4)&1) printf("r4 ");
9904 if((regs[i].dirty>>5)&1) printf("r5 ");
9905 if((regs[i].dirty>>6)&1) printf("r6 ");
9906 if((regs[i].dirty>>7)&1) printf("r7 ");
9907 if((regs[i].dirty>>8)&1) printf("r8 ");
9908 if((regs[i].dirty>>9)&1) printf("r9 ");
9909 if((regs[i].dirty>>10)&1) printf("r10 ");
9910 if((regs[i].dirty>>12)&1) printf("r12 ");
9911 #endif
9912 printf("\n");
9913 if(regs[i].isconst) {
9914 printf("constants: ");
9915 #if defined(__i386__) || defined(__x86_64__)
9916 if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
9917 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
9918 if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
9919 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
9920 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
9921 if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
9922 if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
9923 #endif
9924 #ifdef __arm__
9925 if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
9926 if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
9927 if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
9928 if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
9929 if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
9930 if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
9931 if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
9932 if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
9933 if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
9934 if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
9935 if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
9936 if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
9937 #endif
9938 printf("\n");
9939 }
57871462 9940 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
9941 #if defined(__i386__) || defined(__x86_64__)
9942 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
9943 if(branch_regs[i].dirty&1) printf("eax ");
9944 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
9945 if((branch_regs[i].dirty>>2)&1) printf("edx ");
9946 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
9947 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
9948 if((branch_regs[i].dirty>>6)&1) printf("esi ");
9949 if((branch_regs[i].dirty>>7)&1) printf("edi ");
9950 #endif
9951 #ifdef __arm__
9952 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
9953 if(branch_regs[i].dirty&1) printf("r0 ");
9954 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
9955 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
9956 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
9957 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
9958 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
9959 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
9960 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
9961 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
9962 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
9963 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
9964 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
9965 #endif
57871462 9966 }
9967 }
4600ba03 9968#endif // DISASM
57871462 9969
9970 /* Pass 8 - Assembly */
9971 linkcount=0;stubcount=0;
9972 ds=0;is_delayslot=0;
9973 cop1_usable=0;
9974 uint64_t is32_pre=0;
9975 u_int dirty_pre=0;
d148d265 9976 void *beginning=start_block();
57871462 9977 if((u_int)addr&1) {
9978 ds=1;
9979 pagespan_ds();
9980 }
9ad4d757 9981 u_int instr_addr0_override=0;
9982
9ad4d757 9983 if (start == 0x80030000) {
9984 // nasty hack for fastbios thing
96186eba 9985 // override block entry to this code
9ad4d757 9986 instr_addr0_override=(u_int)out;
9987 emit_movimm(start,0);
96186eba 9988 // abuse io address var as a flag that we
9989 // have already returned here once
9990 emit_readword((int)&address,1);
9ad4d757 9991 emit_writeword(0,(int)&pcaddr);
96186eba 9992 emit_writeword(0,(int)&address);
9ad4d757 9993 emit_cmp(0,1);
9994 emit_jne((int)new_dyna_leave);
9995 }
57871462 9996 for(i=0;i<slen;i++)
9997 {
9998 //if(ds) printf("ds: ");
4600ba03 9999 disassemble_inst(i);
57871462 10000 if(ds) {
10001 ds=0; // Skip delay slot
10002 if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
10003 instr_addr[i]=0;
10004 } else {
ffb0b9e0 10005 speculate_register_values(i);
57871462 10006 #ifndef DESTRUCTIVE_WRITEBACK
10007 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10008 {
57871462 10009 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
10010 unneeded_reg[i],unneeded_reg_upper[i]);
10011 }
f776eb14 10012 if((itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)&&!likely[i]) {
10013 is32_pre=branch_regs[i].is32;
10014 dirty_pre=branch_regs[i].dirty;
10015 }else{
10016 is32_pre=regs[i].is32;
10017 dirty_pre=regs[i].dirty;
10018 }
57871462 10019 #endif
10020 // write back
10021 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10022 {
10023 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
10024 unneeded_reg[i],unneeded_reg_upper[i]);
10025 loop_preload(regmap_pre[i],regs[i].regmap_entry);
10026 }
10027 // branch target entry point
10028 instr_addr[i]=(u_int)out;
10029 assem_debug("<->\n");
10030 // load regs
10031 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
10032 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
10033 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
10034 address_generation(i,&regs[i],regs[i].regmap_entry);
10035 load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
10036 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10037 {
10038 // Load the delay slot registers if necessary
4ef8f67d 10039 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i]&&(rs1[i+1]!=rt1[i]||rt1[i]==0))
57871462 10040 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
4ef8f67d 10041 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i]&&(rs2[i+1]!=rt1[i]||rt1[i]==0))
57871462 10042 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
b9b61529 10043 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
57871462 10044 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10045 }
10046 else if(i+1<slen)
10047 {
10048 // Preload registers for following instruction
10049 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10050 if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
10051 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10052 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10053 if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
10054 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
10055 }
10056 // TODO: if(is_ooo(i)) address_generation(i+1);
10057 if(itype[i]==CJUMP||itype[i]==FJUMP)
10058 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
b9b61529 10059 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
57871462 10060 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10061 if(bt[i]) cop1_usable=0;
10062 // assemble
10063 switch(itype[i]) {
10064 case ALU:
10065 alu_assemble(i,&regs[i]);break;
10066 case IMM16:
10067 imm16_assemble(i,&regs[i]);break;
10068 case SHIFT:
10069 shift_assemble(i,&regs[i]);break;
10070 case SHIFTIMM:
10071 shiftimm_assemble(i,&regs[i]);break;
10072 case LOAD:
10073 load_assemble(i,&regs[i]);break;
10074 case LOADLR:
10075 loadlr_assemble(i,&regs[i]);break;
10076 case STORE:
10077 store_assemble(i,&regs[i]);break;
10078 case STORELR:
10079 storelr_assemble(i,&regs[i]);break;
10080 case COP0:
10081 cop0_assemble(i,&regs[i]);break;
10082 case COP1:
10083 cop1_assemble(i,&regs[i]);break;
10084 case C1LS:
10085 c1ls_assemble(i,&regs[i]);break;
b9b61529 10086 case COP2:
10087 cop2_assemble(i,&regs[i]);break;
10088 case C2LS:
10089 c2ls_assemble(i,&regs[i]);break;
10090 case C2OP:
10091 c2op_assemble(i,&regs[i]);break;
57871462 10092 case FCONV:
10093 fconv_assemble(i,&regs[i]);break;
10094 case FLOAT:
10095 float_assemble(i,&regs[i]);break;
10096 case FCOMP:
10097 fcomp_assemble(i,&regs[i]);break;
10098 case MULTDIV:
10099 multdiv_assemble(i,&regs[i]);break;
10100 case MOV:
10101 mov_assemble(i,&regs[i]);break;
10102 case SYSCALL:
10103 syscall_assemble(i,&regs[i]);break;
7139f3c8 10104 case HLECALL:
10105 hlecall_assemble(i,&regs[i]);break;
1e973cb0 10106 case INTCALL:
10107 intcall_assemble(i,&regs[i]);break;
57871462 10108 case UJUMP:
10109 ujump_assemble(i,&regs[i]);ds=1;break;
10110 case RJUMP:
10111 rjump_assemble(i,&regs[i]);ds=1;break;
10112 case CJUMP:
10113 cjump_assemble(i,&regs[i]);ds=1;break;
10114 case SJUMP:
10115 sjump_assemble(i,&regs[i]);ds=1;break;
10116 case FJUMP:
10117 fjump_assemble(i,&regs[i]);ds=1;break;
10118 case SPAN:
10119 pagespan_assemble(i,&regs[i]);break;
10120 }
10121 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10122 literal_pool(1024);
10123 else
10124 literal_pool_jumpover(256);
10125 }
10126 }
10127 //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
10128 // If the block did not end with an unconditional branch,
10129 // add a jump to the next instruction.
10130 if(i>1) {
10131 if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
10132 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10133 assert(i==slen);
10134 if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
10135 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10136 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10137 emit_loadreg(CCREG,HOST_CCREG);
2573466a 10138 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
57871462 10139 }
10140 else if(!likely[i-2])
10141 {
10142 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
10143 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
10144 }
10145 else
10146 {
10147 store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
10148 assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
10149 }
10150 add_to_linker((int)out,start+i*4,0);
10151 emit_jmp(0);
10152 }
10153 }
10154 else
10155 {
10156 assert(i>0);
10157 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10158 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10159 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10160 emit_loadreg(CCREG,HOST_CCREG);
2573466a 10161 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
57871462 10162 add_to_linker((int)out,start+i*4,0);
10163 emit_jmp(0);
10164 }
10165
10166 // TODO: delay slot stubs?
10167 // Stubs
10168 for(i=0;i<stubcount;i++)
10169 {
10170 switch(stubs[i][0])
10171 {
10172 case LOADB_STUB:
10173 case LOADH_STUB:
10174 case LOADW_STUB:
10175 case LOADD_STUB:
10176 case LOADBU_STUB:
10177 case LOADHU_STUB:
10178 do_readstub(i);break;
10179 case STOREB_STUB:
10180 case STOREH_STUB:
10181 case STOREW_STUB:
10182 case STORED_STUB:
10183 do_writestub(i);break;
10184 case CC_STUB:
10185 do_ccstub(i);break;
10186 case INVCODE_STUB:
10187 do_invstub(i);break;
10188 case FP_STUB:
10189 do_cop1stub(i);break;
10190 case STORELR_STUB:
10191 do_unalignedwritestub(i);break;
10192 }
10193 }
10194
9ad4d757 10195 if (instr_addr0_override)
10196 instr_addr[0] = instr_addr0_override;
10197
57871462 10198 /* Pass 9 - Linker */
10199 for(i=0;i<linkcount;i++)
10200 {
10201 assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
10202 literal_pool(64);
10203 if(!link_addr[i][2])
10204 {
10205 void *stub=out;
10206 void *addr=check_addr(link_addr[i][1]);
10207 emit_extjump(link_addr[i][0],link_addr[i][1]);
10208 if(addr) {
10209 set_jump_target(link_addr[i][0],(int)addr);
10210 add_link(link_addr[i][1],stub);
10211 }
10212 else set_jump_target(link_addr[i][0],(int)stub);
10213 }
10214 else
10215 {
10216 // Internal branch
10217 int target=(link_addr[i][1]-start)>>2;
10218 assert(target>=0&&target<slen);
10219 assert(instr_addr[target]);
10220 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10221 //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
10222 //#else
10223 set_jump_target(link_addr[i][0],instr_addr[target]);
10224 //#endif
10225 }
10226 }
10227 // External Branch Targets (jump_in)
10228 if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
10229 for(i=0;i<slen;i++)
10230 {
10231 if(bt[i]||i==0)
10232 {
10233 if(instr_addr[i]) // TODO - delay slots (=null)
10234 {
10235 u_int vaddr=start+i*4;
94d23bb9 10236 u_int page=get_page(vaddr);
10237 u_int vpage=get_vpage(vaddr);
57871462 10238 literal_pool(256);
57871462 10239 {
10240 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
10241 assem_debug("jump_in: %x\n",start+i*4);
10242 ll_add(jump_dirty+vpage,vaddr,(void *)out);
10243 int entry_point=do_dirty_stub(i);
03f55e6b 10244 ll_add_flags(jump_in+page,vaddr,state_rflags,(void *)entry_point);
57871462 10245 // If there was an existing entry in the hash table,
10246 // replace it with the new address.
10247 // Don't add new entries. We'll insert the
10248 // ones that actually get used in check_addr().
581335b0 10249 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
57871462 10250 if(ht_bin[0]==vaddr) {
10251 ht_bin[1]=entry_point;
10252 }
10253 if(ht_bin[2]==vaddr) {
10254 ht_bin[3]=entry_point;
10255 }
10256 }
57871462 10257 }
10258 }
10259 }
10260 // Write out the literal pool if necessary
10261 literal_pool(0);
10262 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10263 // Align code
10264 if(((u_int)out)&7) emit_addnop(13);
10265 #endif
d148d265 10266 assert((u_int)out-(u_int)beginning<MAX_OUTPUT_BLOCK_SIZE);
57871462 10267 //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
10268 memcpy(copy,source,slen*4);
10269 copy+=slen*4;
9f51b4b9 10270
d148d265 10271 end_block(beginning);
9f51b4b9 10272
57871462 10273 // If we're within 256K of the end of the buffer,
10274 // start over from the beginning. (Is 256K enough?)
bdeade46 10275 if((u_int)out>(u_int)BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
9f51b4b9 10276
57871462 10277 // Trap writes to any of the pages we compiled
10278 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
10279 invalid_code[i]=0;
57871462 10280 }
9be4ba64 10281 inv_code_start=inv_code_end=~0;
71e490c5 10282
b96d3df7 10283 // for PCSX we need to mark all mirrors too
b12c9fb8 10284 if(get_page(start)<(RAM_SIZE>>12))
10285 for(i=start>>12;i<=(start+slen*4)>>12;i++)
b96d3df7 10286 invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]=
10287 invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]=
10288 invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0;
9f51b4b9 10289
57871462 10290 /* Pass 10 - Free memory by expiring oldest blocks */
9f51b4b9 10291
bdeade46 10292 int end=((((int)out-(int)BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
57871462 10293 while(expirep!=end)
10294 {
10295 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
bdeade46 10296 int base=(int)BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
57871462 10297 inv_debug("EXP: Phase %d\n",expirep);
10298 switch((expirep>>11)&3)
10299 {
10300 case 0:
10301 // Clear jump_in and jump_dirty
10302 ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
10303 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
10304 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
10305 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
10306 break;
10307 case 1:
10308 // Clear pointers
10309 ll_kill_pointers(jump_out[expirep&2047],base,shift);
10310 ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
10311 break;
10312 case 2:
10313 // Clear hash table
10314 for(i=0;i<32;i++) {
581335b0 10315 u_int *ht_bin=hash_table[((expirep&2047)<<5)+i];
57871462 10316 if((ht_bin[3]>>shift)==(base>>shift) ||
10317 ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
10318 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
10319 ht_bin[2]=ht_bin[3]=-1;
10320 }
10321 if((ht_bin[1]>>shift)==(base>>shift) ||
10322 ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
10323 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
10324 ht_bin[0]=ht_bin[2];
10325 ht_bin[1]=ht_bin[3];
10326 ht_bin[2]=ht_bin[3]=-1;
10327 }
10328 }
10329 break;
10330 case 3:
10331 // Clear jump_out
dd3a91a1 10332 #ifdef __arm__
9f51b4b9 10333 if((expirep&2047)==0)
dd3a91a1 10334 do_clear_cache();
10335 #endif
57871462 10336 ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
10337 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
10338 break;
10339 }
10340 expirep=(expirep+1)&65535;
10341 }
10342 return 0;
10343}
b9b61529 10344
10345// vim:shiftwidth=2:expandtab
ARM optimized PCSX fork