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drc: handle some load delay cases with interpreter
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
CommitLineData
57871462 1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2010 Ari64 *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21#include <stdlib.h>
22#include <stdint.h> //include for uint64_t
23#include <assert.h>
24
3d624f89 25#include "emu_if.h" //emulator interface
57871462 26
27#include <sys/mman.h>
28
29#ifdef __i386__
30#include "assem_x86.h"
31#endif
32#ifdef __x86_64__
33#include "assem_x64.h"
34#endif
35#ifdef __arm__
36#include "assem_arm.h"
37#endif
38
39#define MAXBLOCK 4096
40#define MAX_OUTPUT_BLOCK_SIZE 262144
41#define CLOCK_DIVIDER 2
42
43struct regstat
44{
45 signed char regmap_entry[HOST_REGS];
46 signed char regmap[HOST_REGS];
47 uint64_t was32;
48 uint64_t is32;
49 uint64_t wasdirty;
50 uint64_t dirty;
51 uint64_t u;
52 uint64_t uu;
53 u_int wasconst;
54 u_int isconst;
55 uint64_t constmap[HOST_REGS];
56};
57
58struct ll_entry
59{
60 u_int vaddr;
61 u_int reg32;
62 void *addr;
63 struct ll_entry *next;
64};
65
66 u_int start;
67 u_int *source;
68 u_int pagelimit;
69 char insn[MAXBLOCK][10];
70 u_char itype[MAXBLOCK];
71 u_char opcode[MAXBLOCK];
72 u_char opcode2[MAXBLOCK];
73 u_char bt[MAXBLOCK];
74 u_char rs1[MAXBLOCK];
75 u_char rs2[MAXBLOCK];
76 u_char rt1[MAXBLOCK];
77 u_char rt2[MAXBLOCK];
78 u_char us1[MAXBLOCK];
79 u_char us2[MAXBLOCK];
80 u_char dep1[MAXBLOCK];
81 u_char dep2[MAXBLOCK];
82 u_char lt1[MAXBLOCK];
83 int imm[MAXBLOCK];
84 u_int ba[MAXBLOCK];
85 char likely[MAXBLOCK];
86 char is_ds[MAXBLOCK];
e1190b87 87 char ooo[MAXBLOCK];
57871462 88 uint64_t unneeded_reg[MAXBLOCK];
89 uint64_t unneeded_reg_upper[MAXBLOCK];
90 uint64_t branch_unneeded_reg[MAXBLOCK];
91 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
92 uint64_t p32[MAXBLOCK];
93 uint64_t pr32[MAXBLOCK];
94 signed char regmap_pre[MAXBLOCK][HOST_REGS];
95 signed char regmap[MAXBLOCK][HOST_REGS];
96 signed char regmap_entry[MAXBLOCK][HOST_REGS];
97 uint64_t constmap[MAXBLOCK][HOST_REGS];
57871462 98 struct regstat regs[MAXBLOCK];
99 struct regstat branch_regs[MAXBLOCK];
e1190b87 100 signed char minimum_free_regs[MAXBLOCK];
57871462 101 u_int needed_reg[MAXBLOCK];
102 uint64_t requires_32bit[MAXBLOCK];
103 u_int wont_dirty[MAXBLOCK];
104 u_int will_dirty[MAXBLOCK];
105 int ccadj[MAXBLOCK];
106 int slen;
107 u_int instr_addr[MAXBLOCK];
108 u_int link_addr[MAXBLOCK][3];
109 int linkcount;
110 u_int stubs[MAXBLOCK*3][8];
111 int stubcount;
112 u_int literals[1024][2];
113 int literalcount;
114 int is_delayslot;
115 int cop1_usable;
116 u_char *out;
117 struct ll_entry *jump_in[4096];
118 struct ll_entry *jump_out[4096];
119 struct ll_entry *jump_dirty[4096];
120 u_int hash_table[65536][4] __attribute__((aligned(16)));
121 char shadow[1048576] __attribute__((aligned(16)));
122 void *copy;
123 int expirep;
af4ee1fe 124#ifndef PCSX
57871462 125 u_int using_tlb;
af4ee1fe 126#else
127 static const u_int using_tlb=0;
128#endif
57871462 129 u_int stop_after_jal;
130 extern u_char restore_candidate[512];
131 extern int cycle_count;
132
133 /* registers that may be allocated */
134 /* 1-31 gpr */
135#define HIREG 32 // hi
136#define LOREG 33 // lo
137#define FSREG 34 // FPU status (FCSR)
138#define CSREG 35 // Coprocessor status
139#define CCREG 36 // Cycle count
140#define INVCP 37 // Pointer to invalid_code
619e5ded 141#define MMREG 38 // Pointer to memory_map
142#define ROREG 39 // ram offset (if rdram!=0x80000000)
143#define TEMPREG 40
144#define FTEMP 40 // FPU temporary register
145#define PTEMP 41 // Prefetch temporary register
146#define TLREG 42 // TLB mapping offset
147#define RHASH 43 // Return address hash
148#define RHTBL 44 // Return address hash table address
149#define RTEMP 45 // JR/JALR address register
150#define MAXREG 45
151#define AGEN1 46 // Address generation temporary register
152#define AGEN2 47 // Address generation temporary register
153#define MGEN1 48 // Maptable address generation temporary register
154#define MGEN2 49 // Maptable address generation temporary register
155#define BTREG 50 // Branch target temporary register
57871462 156
157 /* instruction types */
158#define NOP 0 // No operation
159#define LOAD 1 // Load
160#define STORE 2 // Store
161#define LOADLR 3 // Unaligned load
162#define STORELR 4 // Unaligned store
163#define MOV 5 // Move
164#define ALU 6 // Arithmetic/logic
165#define MULTDIV 7 // Multiply/divide
166#define SHIFT 8 // Shift by register
167#define SHIFTIMM 9// Shift by immediate
168#define IMM16 10 // 16-bit immediate
169#define RJUMP 11 // Unconditional jump to register
170#define UJUMP 12 // Unconditional jump
171#define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
172#define SJUMP 14 // Conditional branch (regimm format)
173#define COP0 15 // Coprocessor 0
174#define COP1 16 // Coprocessor 1
175#define C1LS 17 // Coprocessor 1 load/store
176#define FJUMP 18 // Conditional branch (floating point)
177#define FLOAT 19 // Floating point unit
178#define FCONV 20 // Convert integer to float
179#define FCOMP 21 // Floating point compare (sets FSREG)
180#define SYSCALL 22// SYSCALL
181#define OTHER 23 // Other
182#define SPAN 24 // Branch/delay slot spans 2 pages
183#define NI 25 // Not implemented
7139f3c8 184#define HLECALL 26// PCSX fake opcodes for HLE
b9b61529 185#define COP2 27 // Coprocessor 2 move
186#define C2LS 28 // Coprocessor 2 load/store
187#define C2OP 29 // Coprocessor 2 operation
1e973cb0 188#define INTCALL 30// Call interpreter to handle rare corner cases
57871462 189
190 /* stubs */
191#define CC_STUB 1
192#define FP_STUB 2
193#define LOADB_STUB 3
194#define LOADH_STUB 4
195#define LOADW_STUB 5
196#define LOADD_STUB 6
197#define LOADBU_STUB 7
198#define LOADHU_STUB 8
199#define STOREB_STUB 9
200#define STOREH_STUB 10
201#define STOREW_STUB 11
202#define STORED_STUB 12
203#define STORELR_STUB 13
204#define INVCODE_STUB 14
205
206 /* branch codes */
207#define TAKEN 1
208#define NOTTAKEN 2
209#define NULLDS 3
210
211// asm linkage
212int new_recompile_block(int addr);
213void *get_addr_ht(u_int vaddr);
214void invalidate_block(u_int block);
215void invalidate_addr(u_int addr);
216void remove_hash(int vaddr);
217void jump_vaddr();
218void dyna_linker();
219void dyna_linker_ds();
220void verify_code();
221void verify_code_vm();
222void verify_code_ds();
223void cc_interrupt();
224void fp_exception();
225void fp_exception_ds();
226void jump_syscall();
7139f3c8 227void jump_syscall_hle();
57871462 228void jump_eret();
7139f3c8 229void jump_hlecall();
1e973cb0 230void jump_intcall();
7139f3c8 231void new_dyna_leave();
57871462 232
233// TLB
234void TLBWI_new();
235void TLBWR_new();
236void read_nomem_new();
237void read_nomemb_new();
238void read_nomemh_new();
239void read_nomemd_new();
240void write_nomem_new();
241void write_nomemb_new();
242void write_nomemh_new();
243void write_nomemd_new();
244void write_rdram_new();
245void write_rdramb_new();
246void write_rdramh_new();
247void write_rdramd_new();
248extern u_int memory_map[1048576];
249
250// Needed by assembler
251void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
252void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
253void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
254void load_all_regs(signed char i_regmap[]);
255void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
256void load_regs_entry(int t);
257void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
258
259int tracedebug=0;
260
261//#define DEBUG_CYCLE_COUNT 1
262
263void nullf() {}
264//#define assem_debug printf
265//#define inv_debug printf
266#define assem_debug nullf
267#define inv_debug nullf
268
94d23bb9 269static void tlb_hacks()
57871462 270{
94d23bb9 271#ifndef DISABLE_TLB
57871462 272 // Goldeneye hack
273 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
274 {
275 u_int addr;
276 int n;
277 switch (ROM_HEADER->Country_code&0xFF)
278 {
279 case 0x45: // U
280 addr=0x34b30;
281 break;
282 case 0x4A: // J
283 addr=0x34b70;
284 break;
285 case 0x50: // E
286 addr=0x329f0;
287 break;
288 default:
289 // Unknown country code
290 addr=0;
291 break;
292 }
293 u_int rom_addr=(u_int)rom;
294 #ifdef ROM_COPY
295 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
296 // in the lower 4G of memory to use this hack. Copy it if necessary.
297 if((void *)rom>(void *)0xffffffff) {
298 munmap(ROM_COPY, 67108864);
299 if(mmap(ROM_COPY, 12582912,
300 PROT_READ | PROT_WRITE,
301 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
302 -1, 0) <= 0) {printf("mmap() failed\n");}
303 memcpy(ROM_COPY,rom,12582912);
304 rom_addr=(u_int)ROM_COPY;
305 }
306 #endif
307 if(addr) {
308 for(n=0x7F000;n<0x80000;n++) {
309 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
310 }
311 }
312 }
94d23bb9 313#endif
57871462 314}
315
94d23bb9 316static u_int get_page(u_int vaddr)
57871462 317{
0ce47d46 318#ifndef PCSX
57871462 319 u_int page=(vaddr^0x80000000)>>12;
0ce47d46 320#else
321 u_int page=vaddr&~0xe0000000;
322 if (page < 0x1000000)
323 page &= ~0x0e00000; // RAM mirrors
324 page>>=12;
325#endif
94d23bb9 326#ifndef DISABLE_TLB
57871462 327 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
94d23bb9 328#endif
57871462 329 if(page>2048) page=2048+(page&2047);
94d23bb9 330 return page;
331}
332
333static u_int get_vpage(u_int vaddr)
334{
335 u_int vpage=(vaddr^0x80000000)>>12;
336#ifndef DISABLE_TLB
57871462 337 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
94d23bb9 338#endif
57871462 339 if(vpage>2048) vpage=2048+(vpage&2047);
94d23bb9 340 return vpage;
341}
342
343// Get address from virtual address
344// This is called from the recompiled JR/JALR instructions
345void *get_addr(u_int vaddr)
346{
347 u_int page=get_page(vaddr);
348 u_int vpage=get_vpage(vaddr);
57871462 349 struct ll_entry *head;
350 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
351 head=jump_in[page];
352 while(head!=NULL) {
353 if(head->vaddr==vaddr&&head->reg32==0) {
354 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
355 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
356 ht_bin[3]=ht_bin[1];
357 ht_bin[2]=ht_bin[0];
358 ht_bin[1]=(int)head->addr;
359 ht_bin[0]=vaddr;
360 return head->addr;
361 }
362 head=head->next;
363 }
364 head=jump_dirty[vpage];
365 while(head!=NULL) {
366 if(head->vaddr==vaddr&&head->reg32==0) {
367 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
368 // Don't restore blocks which are about to expire from the cache
369 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
370 if(verify_dirty(head->addr)) {
371 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
372 invalid_code[vaddr>>12]=0;
373 memory_map[vaddr>>12]|=0x40000000;
374 if(vpage<2048) {
94d23bb9 375#ifndef DISABLE_TLB
57871462 376 if(tlb_LUT_r[vaddr>>12]) {
377 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
378 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
379 }
94d23bb9 380#endif
57871462 381 restore_candidate[vpage>>3]|=1<<(vpage&7);
382 }
383 else restore_candidate[page>>3]|=1<<(page&7);
384 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
385 if(ht_bin[0]==vaddr) {
386 ht_bin[1]=(int)head->addr; // Replace existing entry
387 }
388 else
389 {
390 ht_bin[3]=ht_bin[1];
391 ht_bin[2]=ht_bin[0];
392 ht_bin[1]=(int)head->addr;
393 ht_bin[0]=vaddr;
394 }
395 return head->addr;
396 }
397 }
398 head=head->next;
399 }
400 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
401 int r=new_recompile_block(vaddr);
402 if(r==0) return get_addr(vaddr);
403 // Execute in unmapped page, generate pagefault execption
404 Status|=2;
405 Cause=(vaddr<<31)|0x8;
406 EPC=(vaddr&1)?vaddr-5:vaddr;
407 BadVAddr=(vaddr&~1);
408 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
409 EntryHi=BadVAddr&0xFFFFE000;
410 return get_addr_ht(0x80000000);
411}
412// Look up address in hash table first
413void *get_addr_ht(u_int vaddr)
414{
415 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
416 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
417 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
418 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
419 return get_addr(vaddr);
420}
421
422void *get_addr_32(u_int vaddr,u_int flags)
423{
7139f3c8 424#ifdef FORCE32
425 return get_addr(vaddr);
560e4a12 426#else
57871462 427 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
428 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
429 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
430 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
94d23bb9 431 u_int page=get_page(vaddr);
432 u_int vpage=get_vpage(vaddr);
57871462 433 struct ll_entry *head;
434 head=jump_in[page];
435 while(head!=NULL) {
436 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
437 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
438 if(head->reg32==0) {
439 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
440 if(ht_bin[0]==-1) {
441 ht_bin[1]=(int)head->addr;
442 ht_bin[0]=vaddr;
443 }else if(ht_bin[2]==-1) {
444 ht_bin[3]=(int)head->addr;
445 ht_bin[2]=vaddr;
446 }
447 //ht_bin[3]=ht_bin[1];
448 //ht_bin[2]=ht_bin[0];
449 //ht_bin[1]=(int)head->addr;
450 //ht_bin[0]=vaddr;
451 }
452 return head->addr;
453 }
454 head=head->next;
455 }
456 head=jump_dirty[vpage];
457 while(head!=NULL) {
458 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
459 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
460 // Don't restore blocks which are about to expire from the cache
461 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
462 if(verify_dirty(head->addr)) {
463 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
464 invalid_code[vaddr>>12]=0;
465 memory_map[vaddr>>12]|=0x40000000;
466 if(vpage<2048) {
94d23bb9 467#ifndef DISABLE_TLB
57871462 468 if(tlb_LUT_r[vaddr>>12]) {
469 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
470 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
471 }
94d23bb9 472#endif
57871462 473 restore_candidate[vpage>>3]|=1<<(vpage&7);
474 }
475 else restore_candidate[page>>3]|=1<<(page&7);
476 if(head->reg32==0) {
477 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
478 if(ht_bin[0]==-1) {
479 ht_bin[1]=(int)head->addr;
480 ht_bin[0]=vaddr;
481 }else if(ht_bin[2]==-1) {
482 ht_bin[3]=(int)head->addr;
483 ht_bin[2]=vaddr;
484 }
485 //ht_bin[3]=ht_bin[1];
486 //ht_bin[2]=ht_bin[0];
487 //ht_bin[1]=(int)head->addr;
488 //ht_bin[0]=vaddr;
489 }
490 return head->addr;
491 }
492 }
493 head=head->next;
494 }
495 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
496 int r=new_recompile_block(vaddr);
497 if(r==0) return get_addr(vaddr);
498 // Execute in unmapped page, generate pagefault execption
499 Status|=2;
500 Cause=(vaddr<<31)|0x8;
501 EPC=(vaddr&1)?vaddr-5:vaddr;
502 BadVAddr=(vaddr&~1);
503 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
504 EntryHi=BadVAddr&0xFFFFE000;
505 return get_addr_ht(0x80000000);
560e4a12 506#endif
57871462 507}
508
509void clear_all_regs(signed char regmap[])
510{
511 int hr;
512 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
513}
514
515signed char get_reg(signed char regmap[],int r)
516{
517 int hr;
518 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
519 return -1;
520}
521
522// Find a register that is available for two consecutive cycles
523signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
524{
525 int hr;
526 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
527 return -1;
528}
529
530int count_free_regs(signed char regmap[])
531{
532 int count=0;
533 int hr;
534 for(hr=0;hr<HOST_REGS;hr++)
535 {
536 if(hr!=EXCLUDE_REG) {
537 if(regmap[hr]<0) count++;
538 }
539 }
540 return count;
541}
542
543void dirty_reg(struct regstat *cur,signed char reg)
544{
545 int hr;
546 if(!reg) return;
547 for (hr=0;hr<HOST_REGS;hr++) {
548 if((cur->regmap[hr]&63)==reg) {
549 cur->dirty|=1<<hr;
550 }
551 }
552}
553
554// If we dirty the lower half of a 64 bit register which is now being
555// sign-extended, we need to dump the upper half.
556// Note: Do this only after completion of the instruction, because
557// some instructions may need to read the full 64-bit value even if
558// overwriting it (eg SLTI, DSRA32).
559static void flush_dirty_uppers(struct regstat *cur)
560{
561 int hr,reg;
562 for (hr=0;hr<HOST_REGS;hr++) {
563 if((cur->dirty>>hr)&1) {
564 reg=cur->regmap[hr];
565 if(reg>=64)
566 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
567 }
568 }
569}
570
571void set_const(struct regstat *cur,signed char reg,uint64_t value)
572{
573 int hr;
574 if(!reg) return;
575 for (hr=0;hr<HOST_REGS;hr++) {
576 if(cur->regmap[hr]==reg) {
577 cur->isconst|=1<<hr;
578 cur->constmap[hr]=value;
579 }
580 else if((cur->regmap[hr]^64)==reg) {
581 cur->isconst|=1<<hr;
582 cur->constmap[hr]=value>>32;
583 }
584 }
585}
586
587void clear_const(struct regstat *cur,signed char reg)
588{
589 int hr;
590 if(!reg) return;
591 for (hr=0;hr<HOST_REGS;hr++) {
592 if((cur->regmap[hr]&63)==reg) {
593 cur->isconst&=~(1<<hr);
594 }
595 }
596}
597
598int is_const(struct regstat *cur,signed char reg)
599{
600 int hr;
601 if(!reg) return 1;
602 for (hr=0;hr<HOST_REGS;hr++) {
603 if((cur->regmap[hr]&63)==reg) {
604 return (cur->isconst>>hr)&1;
605 }
606 }
607 return 0;
608}
609uint64_t get_const(struct regstat *cur,signed char reg)
610{
611 int hr;
612 if(!reg) return 0;
613 for (hr=0;hr<HOST_REGS;hr++) {
614 if(cur->regmap[hr]==reg) {
615 return cur->constmap[hr];
616 }
617 }
618 printf("Unknown constant in r%d\n",reg);
619 exit(1);
620}
621
622// Least soon needed registers
623// Look at the next ten instructions and see which registers
624// will be used. Try not to reallocate these.
625void lsn(u_char hsn[], int i, int *preferred_reg)
626{
627 int j;
628 int b=-1;
629 for(j=0;j<9;j++)
630 {
631 if(i+j>=slen) {
632 j=slen-i-1;
633 break;
634 }
635 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
636 {
637 // Don't go past an unconditonal jump
638 j++;
639 break;
640 }
641 }
642 for(;j>=0;j--)
643 {
644 if(rs1[i+j]) hsn[rs1[i+j]]=j;
645 if(rs2[i+j]) hsn[rs2[i+j]]=j;
646 if(rt1[i+j]) hsn[rt1[i+j]]=j;
647 if(rt2[i+j]) hsn[rt2[i+j]]=j;
648 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
649 // Stores can allocate zero
650 hsn[rs1[i+j]]=j;
651 hsn[rs2[i+j]]=j;
652 }
653 // On some architectures stores need invc_ptr
654 #if defined(HOST_IMM8)
b9b61529 655 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
57871462 656 hsn[INVCP]=j;
657 }
658 #endif
659 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
660 {
661 hsn[CCREG]=j;
662 b=j;
663 }
664 }
665 if(b>=0)
666 {
667 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
668 {
669 // Follow first branch
670 int t=(ba[i+b]-start)>>2;
671 j=7-b;if(t+j>=slen) j=slen-t-1;
672 for(;j>=0;j--)
673 {
674 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
675 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
676 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
677 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
678 }
679 }
680 // TODO: preferred register based on backward branch
681 }
682 // Delay slot should preferably not overwrite branch conditions or cycle count
683 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
684 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
685 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
686 hsn[CCREG]=1;
687 // ...or hash tables
688 hsn[RHASH]=1;
689 hsn[RHTBL]=1;
690 }
691 // Coprocessor load/store needs FTEMP, even if not declared
b9b61529 692 if(itype[i]==C1LS||itype[i]==C2LS) {
57871462 693 hsn[FTEMP]=0;
694 }
695 // Load L/R also uses FTEMP as a temporary register
696 if(itype[i]==LOADLR) {
697 hsn[FTEMP]=0;
698 }
b7918751 699 // Also SWL/SWR/SDL/SDR
700 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
57871462 701 hsn[FTEMP]=0;
702 }
703 // Don't remove the TLB registers either
b9b61529 704 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
57871462 705 hsn[TLREG]=0;
706 }
707 // Don't remove the miniht registers
708 if(itype[i]==UJUMP||itype[i]==RJUMP)
709 {
710 hsn[RHASH]=0;
711 hsn[RHTBL]=0;
712 }
713}
714
715// We only want to allocate registers if we're going to use them again soon
716int needed_again(int r, int i)
717{
718 int j;
719 int b=-1;
720 int rn=10;
721 int hr;
722 u_char hsn[MAXREG+1];
723 int preferred_reg;
724
725 memset(hsn,10,sizeof(hsn));
726 lsn(hsn,i,&preferred_reg);
727
728 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
729 {
730 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
731 return 0; // Don't need any registers if exiting the block
732 }
733 for(j=0;j<9;j++)
734 {
735 if(i+j>=slen) {
736 j=slen-i-1;
737 break;
738 }
739 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
740 {
741 // Don't go past an unconditonal jump
742 j++;
743 break;
744 }
1e973cb0 745 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
57871462 746 {
747 break;
748 }
749 }
750 for(;j>=1;j--)
751 {
752 if(rs1[i+j]==r) rn=j;
753 if(rs2[i+j]==r) rn=j;
754 if((unneeded_reg[i+j]>>r)&1) rn=10;
755 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
756 {
757 b=j;
758 }
759 }
760 /*
761 if(b>=0)
762 {
763 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
764 {
765 // Follow first branch
766 int o=rn;
767 int t=(ba[i+b]-start)>>2;
768 j=7-b;if(t+j>=slen) j=slen-t-1;
769 for(;j>=0;j--)
770 {
771 if(!((unneeded_reg[t+j]>>r)&1)) {
772 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
773 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
774 }
775 else rn=o;
776 }
777 }
778 }*/
779 for(hr=0;hr<HOST_REGS;hr++) {
780 if(hr!=EXCLUDE_REG) {
781 if(rn<hsn[hr]) return 1;
782 }
783 }
784 return 0;
785}
786
787// Try to match register allocations at the end of a loop with those
788// at the beginning
789int loop_reg(int i, int r, int hr)
790{
791 int j,k;
792 for(j=0;j<9;j++)
793 {
794 if(i+j>=slen) {
795 j=slen-i-1;
796 break;
797 }
798 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
799 {
800 // Don't go past an unconditonal jump
801 j++;
802 break;
803 }
804 }
805 k=0;
806 if(i>0){
807 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
808 k--;
809 }
810 for(;k<j;k++)
811 {
812 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
813 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
814 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
815 {
816 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
817 {
818 int t=(ba[i+k]-start)>>2;
819 int reg=get_reg(regs[t].regmap_entry,r);
820 if(reg>=0) return reg;
821 //reg=get_reg(regs[t+1].regmap_entry,r);
822 //if(reg>=0) return reg;
823 }
824 }
825 }
826 return hr;
827}
828
829
830// Allocate every register, preserving source/target regs
831void alloc_all(struct regstat *cur,int i)
832{
833 int hr;
834
835 for(hr=0;hr<HOST_REGS;hr++) {
836 if(hr!=EXCLUDE_REG) {
837 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
838 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
839 {
840 cur->regmap[hr]=-1;
841 cur->dirty&=~(1<<hr);
842 }
843 // Don't need zeros
844 if((cur->regmap[hr]&63)==0)
845 {
846 cur->regmap[hr]=-1;
847 cur->dirty&=~(1<<hr);
848 }
849 }
850 }
851}
852
853
854void div64(int64_t dividend,int64_t divisor)
855{
856 lo=dividend/divisor;
857 hi=dividend%divisor;
858 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
859 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
860}
861void divu64(uint64_t dividend,uint64_t divisor)
862{
863 lo=dividend/divisor;
864 hi=dividend%divisor;
865 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
866 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
867}
868
869void mult64(uint64_t m1,uint64_t m2)
870{
871 unsigned long long int op1, op2, op3, op4;
872 unsigned long long int result1, result2, result3, result4;
873 unsigned long long int temp1, temp2, temp3, temp4;
874 int sign = 0;
875
876 if (m1 < 0)
877 {
878 op2 = -m1;
879 sign = 1 - sign;
880 }
881 else op2 = m1;
882 if (m2 < 0)
883 {
884 op4 = -m2;
885 sign = 1 - sign;
886 }
887 else op4 = m2;
888
889 op1 = op2 & 0xFFFFFFFF;
890 op2 = (op2 >> 32) & 0xFFFFFFFF;
891 op3 = op4 & 0xFFFFFFFF;
892 op4 = (op4 >> 32) & 0xFFFFFFFF;
893
894 temp1 = op1 * op3;
895 temp2 = (temp1 >> 32) + op1 * op4;
896 temp3 = op2 * op3;
897 temp4 = (temp3 >> 32) + op2 * op4;
898
899 result1 = temp1 & 0xFFFFFFFF;
900 result2 = temp2 + (temp3 & 0xFFFFFFFF);
901 result3 = (result2 >> 32) + temp4;
902 result4 = (result3 >> 32);
903
904 lo = result1 | (result2 << 32);
905 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
906 if (sign)
907 {
908 hi = ~hi;
909 if (!lo) hi++;
910 else lo = ~lo + 1;
911 }
912}
913
914void multu64(uint64_t m1,uint64_t m2)
915{
916 unsigned long long int op1, op2, op3, op4;
917 unsigned long long int result1, result2, result3, result4;
918 unsigned long long int temp1, temp2, temp3, temp4;
919
920 op1 = m1 & 0xFFFFFFFF;
921 op2 = (m1 >> 32) & 0xFFFFFFFF;
922 op3 = m2 & 0xFFFFFFFF;
923 op4 = (m2 >> 32) & 0xFFFFFFFF;
924
925 temp1 = op1 * op3;
926 temp2 = (temp1 >> 32) + op1 * op4;
927 temp3 = op2 * op3;
928 temp4 = (temp3 >> 32) + op2 * op4;
929
930 result1 = temp1 & 0xFFFFFFFF;
931 result2 = temp2 + (temp3 & 0xFFFFFFFF);
932 result3 = (result2 >> 32) + temp4;
933 result4 = (result3 >> 32);
934
935 lo = result1 | (result2 << 32);
936 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
937
938 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
939 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
940}
941
942uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
943{
944 if(bits) {
945 original<<=64-bits;
946 original>>=64-bits;
947 loaded<<=bits;
948 original|=loaded;
949 }
950 else original=loaded;
951 return original;
952}
953uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
954{
955 if(bits^56) {
956 original>>=64-(bits^56);
957 original<<=64-(bits^56);
958 loaded>>=bits^56;
959 original|=loaded;
960 }
961 else original=loaded;
962 return original;
963}
964
965#ifdef __i386__
966#include "assem_x86.c"
967#endif
968#ifdef __x86_64__
969#include "assem_x64.c"
970#endif
971#ifdef __arm__
972#include "assem_arm.c"
973#endif
974
975// Add virtual address mapping to linked list
976void ll_add(struct ll_entry **head,int vaddr,void *addr)
977{
978 struct ll_entry *new_entry;
979 new_entry=malloc(sizeof(struct ll_entry));
980 assert(new_entry!=NULL);
981 new_entry->vaddr=vaddr;
982 new_entry->reg32=0;
983 new_entry->addr=addr;
984 new_entry->next=*head;
985 *head=new_entry;
986}
987
988// Add virtual address mapping for 32-bit compiled block
989void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
990{
7139f3c8 991 ll_add(head,vaddr,addr);
992#ifndef FORCE32
993 (*head)->reg32=reg32;
994#endif
57871462 995}
996
997// Check if an address is already compiled
998// but don't return addresses which are about to expire from the cache
999void *check_addr(u_int vaddr)
1000{
1001 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
1002 if(ht_bin[0]==vaddr) {
1003 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1004 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
1005 }
1006 if(ht_bin[2]==vaddr) {
1007 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1008 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1009 }
94d23bb9 1010 u_int page=get_page(vaddr);
57871462 1011 struct ll_entry *head;
1012 head=jump_in[page];
1013 while(head!=NULL) {
1014 if(head->vaddr==vaddr&&head->reg32==0) {
1015 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1016 // Update existing entry with current address
1017 if(ht_bin[0]==vaddr) {
1018 ht_bin[1]=(int)head->addr;
1019 return head->addr;
1020 }
1021 if(ht_bin[2]==vaddr) {
1022 ht_bin[3]=(int)head->addr;
1023 return head->addr;
1024 }
1025 // Insert into hash table with low priority.
1026 // Don't evict existing entries, as they are probably
1027 // addresses that are being accessed frequently.
1028 if(ht_bin[0]==-1) {
1029 ht_bin[1]=(int)head->addr;
1030 ht_bin[0]=vaddr;
1031 }else if(ht_bin[2]==-1) {
1032 ht_bin[3]=(int)head->addr;
1033 ht_bin[2]=vaddr;
1034 }
1035 return head->addr;
1036 }
1037 }
1038 head=head->next;
1039 }
1040 return 0;
1041}
1042
1043void remove_hash(int vaddr)
1044{
1045 //printf("remove hash: %x\n",vaddr);
1046 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1047 if(ht_bin[2]==vaddr) {
1048 ht_bin[2]=ht_bin[3]=-1;
1049 }
1050 if(ht_bin[0]==vaddr) {
1051 ht_bin[0]=ht_bin[2];
1052 ht_bin[1]=ht_bin[3];
1053 ht_bin[2]=ht_bin[3]=-1;
1054 }
1055}
1056
1057void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1058{
1059 struct ll_entry *next;
1060 while(*head) {
1061 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1062 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1063 {
1064 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1065 remove_hash((*head)->vaddr);
1066 next=(*head)->next;
1067 free(*head);
1068 *head=next;
1069 }
1070 else
1071 {
1072 head=&((*head)->next);
1073 }
1074 }
1075}
1076
1077// Remove all entries from linked list
1078void ll_clear(struct ll_entry **head)
1079{
1080 struct ll_entry *cur;
1081 struct ll_entry *next;
1082 if(cur=*head) {
1083 *head=0;
1084 while(cur) {
1085 next=cur->next;
1086 free(cur);
1087 cur=next;
1088 }
1089 }
1090}
1091
1092// Dereference the pointers and remove if it matches
1093void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1094{
1095 while(head) {
1096 int ptr=get_pointer(head->addr);
1097 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1098 if(((ptr>>shift)==(addr>>shift)) ||
1099 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1100 {
5088bb70 1101 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
f76eeef9 1102 u_int host_addr=(u_int)kill_pointer(head->addr);
dd3a91a1 1103 #ifdef __arm__
1104 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1105 #endif
57871462 1106 }
1107 head=head->next;
1108 }
1109}
1110
1111// This is called when we write to a compiled block (see do_invstub)
f76eeef9 1112void invalidate_page(u_int page)
57871462 1113{
57871462 1114 struct ll_entry *head;
1115 struct ll_entry *next;
1116 head=jump_in[page];
1117 jump_in[page]=0;
1118 while(head!=NULL) {
1119 inv_debug("INVALIDATE: %x\n",head->vaddr);
1120 remove_hash(head->vaddr);
1121 next=head->next;
1122 free(head);
1123 head=next;
1124 }
1125 head=jump_out[page];
1126 jump_out[page]=0;
1127 while(head!=NULL) {
1128 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
f76eeef9 1129 u_int host_addr=(u_int)kill_pointer(head->addr);
dd3a91a1 1130 #ifdef __arm__
1131 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1132 #endif
57871462 1133 next=head->next;
1134 free(head);
1135 head=next;
1136 }
57871462 1137}
1138void invalidate_block(u_int block)
1139{
94d23bb9 1140 u_int page=get_page(block<<12);
1141 u_int vpage=get_vpage(block<<12);
57871462 1142 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1143 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1144 u_int first,last;
1145 first=last=page;
1146 struct ll_entry *head;
1147 head=jump_dirty[vpage];
1148 //printf("page=%d vpage=%d\n",page,vpage);
1149 while(head!=NULL) {
1150 u_int start,end;
1151 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1152 get_bounds((int)head->addr,&start,&end);
1153 //printf("start: %x end: %x\n",start,end);
4cb76aa4 1154 if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
57871462 1155 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1156 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1157 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1158 }
1159 }
90ae6d4e 1160#ifndef DISABLE_TLB
57871462 1161 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1162 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1163 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1164 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1165 }
1166 }
90ae6d4e 1167#endif
57871462 1168 }
1169 head=head->next;
1170 }
1171 //printf("first=%d last=%d\n",first,last);
f76eeef9 1172 invalidate_page(page);
57871462 1173 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1174 assert(last<page+5);
1175 // Invalidate the adjacent pages if a block crosses a 4K boundary
1176 while(first<page) {
1177 invalidate_page(first);
1178 first++;
1179 }
1180 for(first=page+1;first<last;first++) {
1181 invalidate_page(first);
1182 }
dd3a91a1 1183 #ifdef __arm__
1184 do_clear_cache();
1185 #endif
57871462 1186
1187 // Don't trap writes
1188 invalid_code[block]=1;
b12c9fb8 1189#ifdef PCSX
1190 invalid_code[((u_int)0x80000000>>12)|page]=1;
1191#endif
94d23bb9 1192#ifndef DISABLE_TLB
57871462 1193 // If there is a valid TLB entry for this page, remove write protect
1194 if(tlb_LUT_w[block]) {
1195 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1196 // CHECK: Is this right?
1197 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1198 u_int real_block=tlb_LUT_w[block]>>12;
1199 invalid_code[real_block]=1;
1200 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1201 }
1202 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
94d23bb9 1203#endif
f76eeef9 1204
57871462 1205 #ifdef USE_MINI_HT
1206 memset(mini_ht,-1,sizeof(mini_ht));
1207 #endif
1208}
1209void invalidate_addr(u_int addr)
1210{
1211 invalidate_block(addr>>12);
1212}
dd3a91a1 1213// This is called when loading a save state.
1214// Anything could have changed, so invalidate everything.
57871462 1215void invalidate_all_pages()
1216{
1217 u_int page,n;
1218 for(page=0;page<4096;page++)
1219 invalidate_page(page);
1220 for(page=0;page<1048576;page++)
1221 if(!invalid_code[page]) {
1222 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1223 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1224 }
1225 #ifdef __arm__
1226 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1227 #endif
1228 #ifdef USE_MINI_HT
1229 memset(mini_ht,-1,sizeof(mini_ht));
1230 #endif
94d23bb9 1231 #ifndef DISABLE_TLB
57871462 1232 // TLB
1233 for(page=0;page<0x100000;page++) {
1234 if(tlb_LUT_r[page]) {
1235 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1236 if(!tlb_LUT_w[page]||!invalid_code[page])
1237 memory_map[page]|=0x40000000; // Write protect
1238 }
1239 else memory_map[page]=-1;
1240 if(page==0x80000) page=0xC0000;
1241 }
1242 tlb_hacks();
94d23bb9 1243 #endif
57871462 1244}
1245
1246// Add an entry to jump_out after making a link
1247void add_link(u_int vaddr,void *src)
1248{
94d23bb9 1249 u_int page=get_page(vaddr);
57871462 1250 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1251 ll_add(jump_out+page,vaddr,src);
1252 //int ptr=get_pointer(src);
1253 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1254}
1255
1256// If a code block was found to be unmodified (bit was set in
1257// restore_candidate) and it remains unmodified (bit is clear
1258// in invalid_code) then move the entries for that 4K page from
1259// the dirty list to the clean list.
1260void clean_blocks(u_int page)
1261{
1262 struct ll_entry *head;
1263 inv_debug("INV: clean_blocks page=%d\n",page);
1264 head=jump_dirty[page];
1265 while(head!=NULL) {
1266 if(!invalid_code[head->vaddr>>12]) {
1267 // Don't restore blocks which are about to expire from the cache
1268 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1269 u_int start,end;
1270 if(verify_dirty((int)head->addr)) {
1271 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1272 u_int i;
1273 u_int inv=0;
1274 get_bounds((int)head->addr,&start,&end);
4cb76aa4 1275 if(start-(u_int)rdram<RAM_SIZE) {
57871462 1276 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1277 inv|=invalid_code[i];
1278 }
1279 }
1280 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1281 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1282 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1283 if(addr<start||addr>=end) inv=1;
1284 }
4cb76aa4 1285 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
57871462 1286 inv=1;
1287 }
1288 if(!inv) {
1289 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1290 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1291 u_int ppage=page;
94d23bb9 1292#ifndef DISABLE_TLB
57871462 1293 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
94d23bb9 1294#endif
57871462 1295 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1296 //printf("page=%x, addr=%x\n",page,head->vaddr);
1297 //assert(head->vaddr>>12==(page|0x80000));
1298 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1299 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1300 if(!head->reg32) {
1301 if(ht_bin[0]==head->vaddr) {
1302 ht_bin[1]=(int)clean_addr; // Replace existing entry
1303 }
1304 if(ht_bin[2]==head->vaddr) {
1305 ht_bin[3]=(int)clean_addr; // Replace existing entry
1306 }
1307 }
1308 }
1309 }
1310 }
1311 }
1312 }
1313 head=head->next;
1314 }
1315}
1316
1317
1318void mov_alloc(struct regstat *current,int i)
1319{
1320 // Note: Don't need to actually alloc the source registers
1321 if((~current->is32>>rs1[i])&1) {
1322 //alloc_reg64(current,i,rs1[i]);
1323 alloc_reg64(current,i,rt1[i]);
1324 current->is32&=~(1LL<<rt1[i]);
1325 } else {
1326 //alloc_reg(current,i,rs1[i]);
1327 alloc_reg(current,i,rt1[i]);
1328 current->is32|=(1LL<<rt1[i]);
1329 }
1330 clear_const(current,rs1[i]);
1331 clear_const(current,rt1[i]);
1332 dirty_reg(current,rt1[i]);
1333}
1334
1335void shiftimm_alloc(struct regstat *current,int i)
1336{
1337 clear_const(current,rs1[i]);
1338 clear_const(current,rt1[i]);
1339 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1340 {
1341 if(rt1[i]) {
1342 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1343 else lt1[i]=rs1[i];
1344 alloc_reg(current,i,rt1[i]);
1345 current->is32|=1LL<<rt1[i];
1346 dirty_reg(current,rt1[i]);
1347 }
1348 }
1349 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1350 {
1351 if(rt1[i]) {
1352 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1353 alloc_reg64(current,i,rt1[i]);
1354 current->is32&=~(1LL<<rt1[i]);
1355 dirty_reg(current,rt1[i]);
1356 }
1357 }
1358 if(opcode2[i]==0x3c) // DSLL32
1359 {
1360 if(rt1[i]) {
1361 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1362 alloc_reg64(current,i,rt1[i]);
1363 current->is32&=~(1LL<<rt1[i]);
1364 dirty_reg(current,rt1[i]);
1365 }
1366 }
1367 if(opcode2[i]==0x3e) // DSRL32
1368 {
1369 if(rt1[i]) {
1370 alloc_reg64(current,i,rs1[i]);
1371 if(imm[i]==32) {
1372 alloc_reg64(current,i,rt1[i]);
1373 current->is32&=~(1LL<<rt1[i]);
1374 } else {
1375 alloc_reg(current,i,rt1[i]);
1376 current->is32|=1LL<<rt1[i];
1377 }
1378 dirty_reg(current,rt1[i]);
1379 }
1380 }
1381 if(opcode2[i]==0x3f) // DSRA32
1382 {
1383 if(rt1[i]) {
1384 alloc_reg64(current,i,rs1[i]);
1385 alloc_reg(current,i,rt1[i]);
1386 current->is32|=1LL<<rt1[i];
1387 dirty_reg(current,rt1[i]);
1388 }
1389 }
1390}
1391
1392void shift_alloc(struct regstat *current,int i)
1393{
1394 if(rt1[i]) {
1395 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1396 {
1397 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1398 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1399 alloc_reg(current,i,rt1[i]);
e1190b87 1400 if(rt1[i]==rs2[i]) {
1401 alloc_reg_temp(current,i,-1);
1402 minimum_free_regs[i]=1;
1403 }
57871462 1404 current->is32|=1LL<<rt1[i];
1405 } else { // DSLLV/DSRLV/DSRAV
1406 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1407 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1408 alloc_reg64(current,i,rt1[i]);
1409 current->is32&=~(1LL<<rt1[i]);
1410 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
e1190b87 1411 {
57871462 1412 alloc_reg_temp(current,i,-1);
e1190b87 1413 minimum_free_regs[i]=1;
1414 }
57871462 1415 }
1416 clear_const(current,rs1[i]);
1417 clear_const(current,rs2[i]);
1418 clear_const(current,rt1[i]);
1419 dirty_reg(current,rt1[i]);
1420 }
1421}
1422
1423void alu_alloc(struct regstat *current,int i)
1424{
1425 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1426 if(rt1[i]) {
1427 if(rs1[i]&&rs2[i]) {
1428 alloc_reg(current,i,rs1[i]);
1429 alloc_reg(current,i,rs2[i]);
1430 }
1431 else {
1432 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1433 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1434 }
1435 alloc_reg(current,i,rt1[i]);
1436 }
1437 current->is32|=1LL<<rt1[i];
1438 }
1439 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1440 if(rt1[i]) {
1441 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1442 {
1443 alloc_reg64(current,i,rs1[i]);
1444 alloc_reg64(current,i,rs2[i]);
1445 alloc_reg(current,i,rt1[i]);
1446 } else {
1447 alloc_reg(current,i,rs1[i]);
1448 alloc_reg(current,i,rs2[i]);
1449 alloc_reg(current,i,rt1[i]);
1450 }
1451 }
1452 current->is32|=1LL<<rt1[i];
1453 }
1454 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1455 if(rt1[i]) {
1456 if(rs1[i]&&rs2[i]) {
1457 alloc_reg(current,i,rs1[i]);
1458 alloc_reg(current,i,rs2[i]);
1459 }
1460 else
1461 {
1462 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1463 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1464 }
1465 alloc_reg(current,i,rt1[i]);
1466 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1467 {
1468 if(!((current->uu>>rt1[i])&1)) {
1469 alloc_reg64(current,i,rt1[i]);
1470 }
1471 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1472 if(rs1[i]&&rs2[i]) {
1473 alloc_reg64(current,i,rs1[i]);
1474 alloc_reg64(current,i,rs2[i]);
1475 }
1476 else
1477 {
1478 // Is is really worth it to keep 64-bit values in registers?
1479 #ifdef NATIVE_64BIT
1480 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1481 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1482 #endif
1483 }
1484 }
1485 current->is32&=~(1LL<<rt1[i]);
1486 } else {
1487 current->is32|=1LL<<rt1[i];
1488 }
1489 }
1490 }
1491 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1492 if(rt1[i]) {
1493 if(rs1[i]&&rs2[i]) {
1494 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1495 alloc_reg64(current,i,rs1[i]);
1496 alloc_reg64(current,i,rs2[i]);
1497 alloc_reg64(current,i,rt1[i]);
1498 } else {
1499 alloc_reg(current,i,rs1[i]);
1500 alloc_reg(current,i,rs2[i]);
1501 alloc_reg(current,i,rt1[i]);
1502 }
1503 }
1504 else {
1505 alloc_reg(current,i,rt1[i]);
1506 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1507 // DADD used as move, or zeroing
1508 // If we have a 64-bit source, then make the target 64 bits too
1509 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1510 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1511 alloc_reg64(current,i,rt1[i]);
1512 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1513 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1514 alloc_reg64(current,i,rt1[i]);
1515 }
1516 if(opcode2[i]>=0x2e&&rs2[i]) {
1517 // DSUB used as negation - 64-bit result
1518 // If we have a 32-bit register, extend it to 64 bits
1519 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1520 alloc_reg64(current,i,rt1[i]);
1521 }
1522 }
1523 }
1524 if(rs1[i]&&rs2[i]) {
1525 current->is32&=~(1LL<<rt1[i]);
1526 } else if(rs1[i]) {
1527 current->is32&=~(1LL<<rt1[i]);
1528 if((current->is32>>rs1[i])&1)
1529 current->is32|=1LL<<rt1[i];
1530 } else if(rs2[i]) {
1531 current->is32&=~(1LL<<rt1[i]);
1532 if((current->is32>>rs2[i])&1)
1533 current->is32|=1LL<<rt1[i];
1534 } else {
1535 current->is32|=1LL<<rt1[i];
1536 }
1537 }
1538 }
1539 clear_const(current,rs1[i]);
1540 clear_const(current,rs2[i]);
1541 clear_const(current,rt1[i]);
1542 dirty_reg(current,rt1[i]);
1543}
1544
1545void imm16_alloc(struct regstat *current,int i)
1546{
1547 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1548 else lt1[i]=rs1[i];
1549 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1550 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1551 current->is32&=~(1LL<<rt1[i]);
1552 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1553 // TODO: Could preserve the 32-bit flag if the immediate is zero
1554 alloc_reg64(current,i,rt1[i]);
1555 alloc_reg64(current,i,rs1[i]);
1556 }
1557 clear_const(current,rs1[i]);
1558 clear_const(current,rt1[i]);
1559 }
1560 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1561 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1562 current->is32|=1LL<<rt1[i];
1563 clear_const(current,rs1[i]);
1564 clear_const(current,rt1[i]);
1565 }
1566 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1567 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1568 if(rs1[i]!=rt1[i]) {
1569 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1570 alloc_reg64(current,i,rt1[i]);
1571 current->is32&=~(1LL<<rt1[i]);
1572 }
1573 }
1574 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1575 if(is_const(current,rs1[i])) {
1576 int v=get_const(current,rs1[i]);
1577 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1578 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1579 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1580 }
1581 else clear_const(current,rt1[i]);
1582 }
1583 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1584 if(is_const(current,rs1[i])) {
1585 int v=get_const(current,rs1[i]);
1586 set_const(current,rt1[i],v+imm[i]);
1587 }
1588 else clear_const(current,rt1[i]);
1589 current->is32|=1LL<<rt1[i];
1590 }
1591 else {
1592 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1593 current->is32|=1LL<<rt1[i];
1594 }
1595 dirty_reg(current,rt1[i]);
1596}
1597
1598void load_alloc(struct regstat *current,int i)
1599{
1600 clear_const(current,rt1[i]);
1601 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1602 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1603 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1604 if(rt1[i]) {
1605 alloc_reg(current,i,rt1[i]);
535d208a 1606 if(get_reg(current->regmap,rt1[i])<0) {
1607 // dummy load, but we still need a register to calculate the address
1608 alloc_reg_temp(current,i,-1);
e1190b87 1609 minimum_free_regs[i]=1;
535d208a 1610 }
57871462 1611 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1612 {
1613 current->is32&=~(1LL<<rt1[i]);
1614 alloc_reg64(current,i,rt1[i]);
1615 }
1616 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1617 {
1618 current->is32&=~(1LL<<rt1[i]);
1619 alloc_reg64(current,i,rt1[i]);
1620 alloc_all(current,i);
1621 alloc_reg64(current,i,FTEMP);
e1190b87 1622 minimum_free_regs[i]=HOST_REGS;
57871462 1623 }
1624 else current->is32|=1LL<<rt1[i];
1625 dirty_reg(current,rt1[i]);
1626 // If using TLB, need a register for pointer to the mapping table
1627 if(using_tlb) alloc_reg(current,i,TLREG);
1628 // LWL/LWR need a temporary register for the old value
1629 if(opcode[i]==0x22||opcode[i]==0x26)
1630 {
1631 alloc_reg(current,i,FTEMP);
1632 alloc_reg_temp(current,i,-1);
e1190b87 1633 minimum_free_regs[i]=1;
57871462 1634 }
1635 }
1636 else
1637 {
1638 // Load to r0 (dummy load)
1639 // but we still need a register to calculate the address
535d208a 1640 if(opcode[i]==0x22||opcode[i]==0x26)
1641 {
1642 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1643 }
57871462 1644 alloc_reg_temp(current,i,-1);
e1190b87 1645 minimum_free_regs[i]=1;
535d208a 1646 if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1647 {
1648 alloc_all(current,i);
1649 alloc_reg64(current,i,FTEMP);
e1190b87 1650 minimum_free_regs[i]=HOST_REGS;
535d208a 1651 }
57871462 1652 }
1653}
1654
1655void store_alloc(struct regstat *current,int i)
1656{
1657 clear_const(current,rs2[i]);
1658 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1659 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1660 alloc_reg(current,i,rs2[i]);
1661 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1662 alloc_reg64(current,i,rs2[i]);
1663 if(rs2[i]) alloc_reg(current,i,FTEMP);
1664 }
1665 // If using TLB, need a register for pointer to the mapping table
1666 if(using_tlb) alloc_reg(current,i,TLREG);
1667 #if defined(HOST_IMM8)
1668 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1669 else alloc_reg(current,i,INVCP);
1670 #endif
b7918751 1671 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
57871462 1672 alloc_reg(current,i,FTEMP);
1673 }
1674 // We need a temporary register for address generation
1675 alloc_reg_temp(current,i,-1);
e1190b87 1676 minimum_free_regs[i]=1;
57871462 1677}
1678
1679void c1ls_alloc(struct regstat *current,int i)
1680{
1681 //clear_const(current,rs1[i]); // FIXME
1682 clear_const(current,rt1[i]);
1683 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1684 alloc_reg(current,i,CSREG); // Status
1685 alloc_reg(current,i,FTEMP);
1686 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1687 alloc_reg64(current,i,FTEMP);
1688 }
1689 // If using TLB, need a register for pointer to the mapping table
1690 if(using_tlb) alloc_reg(current,i,TLREG);
1691 #if defined(HOST_IMM8)
1692 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1693 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1694 alloc_reg(current,i,INVCP);
1695 #endif
1696 // We need a temporary register for address generation
1697 alloc_reg_temp(current,i,-1);
1698}
1699
b9b61529 1700void c2ls_alloc(struct regstat *current,int i)
1701{
1702 clear_const(current,rt1[i]);
1703 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1704 alloc_reg(current,i,FTEMP);
1705 // If using TLB, need a register for pointer to the mapping table
1706 if(using_tlb) alloc_reg(current,i,TLREG);
1707 #if defined(HOST_IMM8)
1708 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1709 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1710 alloc_reg(current,i,INVCP);
1711 #endif
1712 // We need a temporary register for address generation
1713 alloc_reg_temp(current,i,-1);
e1190b87 1714 minimum_free_regs[i]=1;
b9b61529 1715}
1716
57871462 1717#ifndef multdiv_alloc
1718void multdiv_alloc(struct regstat *current,int i)
1719{
1720 // case 0x18: MULT
1721 // case 0x19: MULTU
1722 // case 0x1A: DIV
1723 // case 0x1B: DIVU
1724 // case 0x1C: DMULT
1725 // case 0x1D: DMULTU
1726 // case 0x1E: DDIV
1727 // case 0x1F: DDIVU
1728 clear_const(current,rs1[i]);
1729 clear_const(current,rs2[i]);
1730 if(rs1[i]&&rs2[i])
1731 {
1732 if((opcode2[i]&4)==0) // 32-bit
1733 {
1734 current->u&=~(1LL<<HIREG);
1735 current->u&=~(1LL<<LOREG);
1736 alloc_reg(current,i,HIREG);
1737 alloc_reg(current,i,LOREG);
1738 alloc_reg(current,i,rs1[i]);
1739 alloc_reg(current,i,rs2[i]);
1740 current->is32|=1LL<<HIREG;
1741 current->is32|=1LL<<LOREG;
1742 dirty_reg(current,HIREG);
1743 dirty_reg(current,LOREG);
1744 }
1745 else // 64-bit
1746 {
1747 current->u&=~(1LL<<HIREG);
1748 current->u&=~(1LL<<LOREG);
1749 current->uu&=~(1LL<<HIREG);
1750 current->uu&=~(1LL<<LOREG);
1751 alloc_reg64(current,i,HIREG);
1752 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1753 alloc_reg64(current,i,rs1[i]);
1754 alloc_reg64(current,i,rs2[i]);
1755 alloc_all(current,i);
1756 current->is32&=~(1LL<<HIREG);
1757 current->is32&=~(1LL<<LOREG);
1758 dirty_reg(current,HIREG);
1759 dirty_reg(current,LOREG);
e1190b87 1760 minimum_free_regs[i]=HOST_REGS;
57871462 1761 }
1762 }
1763 else
1764 {
1765 // Multiply by zero is zero.
1766 // MIPS does not have a divide by zero exception.
1767 // The result is undefined, we return zero.
1768 alloc_reg(current,i,HIREG);
1769 alloc_reg(current,i,LOREG);
1770 current->is32|=1LL<<HIREG;
1771 current->is32|=1LL<<LOREG;
1772 dirty_reg(current,HIREG);
1773 dirty_reg(current,LOREG);
1774 }
1775}
1776#endif
1777
1778void cop0_alloc(struct regstat *current,int i)
1779{
1780 if(opcode2[i]==0) // MFC0
1781 {
1782 if(rt1[i]) {
1783 clear_const(current,rt1[i]);
1784 alloc_all(current,i);
1785 alloc_reg(current,i,rt1[i]);
1786 current->is32|=1LL<<rt1[i];
1787 dirty_reg(current,rt1[i]);
1788 }
1789 }
1790 else if(opcode2[i]==4) // MTC0
1791 {
1792 if(rs1[i]){
1793 clear_const(current,rs1[i]);
1794 alloc_reg(current,i,rs1[i]);
1795 alloc_all(current,i);
1796 }
1797 else {
1798 alloc_all(current,i); // FIXME: Keep r0
1799 current->u&=~1LL;
1800 alloc_reg(current,i,0);
1801 }
1802 }
1803 else
1804 {
1805 // TLBR/TLBWI/TLBWR/TLBP/ERET
1806 assert(opcode2[i]==0x10);
1807 alloc_all(current,i);
1808 }
e1190b87 1809 minimum_free_regs[i]=HOST_REGS;
57871462 1810}
1811
1812void cop1_alloc(struct regstat *current,int i)
1813{
1814 alloc_reg(current,i,CSREG); // Load status
1815 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1816 {
7de557a6 1817 if(rt1[i]){
1818 clear_const(current,rt1[i]);
1819 if(opcode2[i]==1) {
1820 alloc_reg64(current,i,rt1[i]); // DMFC1
1821 current->is32&=~(1LL<<rt1[i]);
1822 }else{
1823 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1824 current->is32|=1LL<<rt1[i];
1825 }
1826 dirty_reg(current,rt1[i]);
57871462 1827 }
57871462 1828 alloc_reg_temp(current,i,-1);
1829 }
1830 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1831 {
1832 if(rs1[i]){
1833 clear_const(current,rs1[i]);
1834 if(opcode2[i]==5)
1835 alloc_reg64(current,i,rs1[i]); // DMTC1
1836 else
1837 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1838 alloc_reg_temp(current,i,-1);
1839 }
1840 else {
1841 current->u&=~1LL;
1842 alloc_reg(current,i,0);
1843 alloc_reg_temp(current,i,-1);
1844 }
1845 }
e1190b87 1846 minimum_free_regs[i]=1;
57871462 1847}
1848void fconv_alloc(struct regstat *current,int i)
1849{
1850 alloc_reg(current,i,CSREG); // Load status
1851 alloc_reg_temp(current,i,-1);
e1190b87 1852 minimum_free_regs[i]=1;
57871462 1853}
1854void float_alloc(struct regstat *current,int i)
1855{
1856 alloc_reg(current,i,CSREG); // Load status
1857 alloc_reg_temp(current,i,-1);
e1190b87 1858 minimum_free_regs[i]=1;
57871462 1859}
b9b61529 1860void c2op_alloc(struct regstat *current,int i)
1861{
1862 alloc_reg_temp(current,i,-1);
1863}
57871462 1864void fcomp_alloc(struct regstat *current,int i)
1865{
1866 alloc_reg(current,i,CSREG); // Load status
1867 alloc_reg(current,i,FSREG); // Load flags
1868 dirty_reg(current,FSREG); // Flag will be modified
1869 alloc_reg_temp(current,i,-1);
e1190b87 1870 minimum_free_regs[i]=1;
57871462 1871}
1872
1873void syscall_alloc(struct regstat *current,int i)
1874{
1875 alloc_cc(current,i);
1876 dirty_reg(current,CCREG);
1877 alloc_all(current,i);
e1190b87 1878 minimum_free_regs[i]=HOST_REGS;
57871462 1879 current->isconst=0;
1880}
1881
1882void delayslot_alloc(struct regstat *current,int i)
1883{
1884 switch(itype[i]) {
1885 case UJUMP:
1886 case CJUMP:
1887 case SJUMP:
1888 case RJUMP:
1889 case FJUMP:
1890 case SYSCALL:
7139f3c8 1891 case HLECALL:
57871462 1892 case SPAN:
1893 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1894 printf("Disabled speculative precompilation\n");
1895 stop_after_jal=1;
1896 break;
1897 case IMM16:
1898 imm16_alloc(current,i);
1899 break;
1900 case LOAD:
1901 case LOADLR:
1902 load_alloc(current,i);
1903 break;
1904 case STORE:
1905 case STORELR:
1906 store_alloc(current,i);
1907 break;
1908 case ALU:
1909 alu_alloc(current,i);
1910 break;
1911 case SHIFT:
1912 shift_alloc(current,i);
1913 break;
1914 case MULTDIV:
1915 multdiv_alloc(current,i);
1916 break;
1917 case SHIFTIMM:
1918 shiftimm_alloc(current,i);
1919 break;
1920 case MOV:
1921 mov_alloc(current,i);
1922 break;
1923 case COP0:
1924 cop0_alloc(current,i);
1925 break;
1926 case COP1:
b9b61529 1927 case COP2:
57871462 1928 cop1_alloc(current,i);
1929 break;
1930 case C1LS:
1931 c1ls_alloc(current,i);
1932 break;
b9b61529 1933 case C2LS:
1934 c2ls_alloc(current,i);
1935 break;
57871462 1936 case FCONV:
1937 fconv_alloc(current,i);
1938 break;
1939 case FLOAT:
1940 float_alloc(current,i);
1941 break;
1942 case FCOMP:
1943 fcomp_alloc(current,i);
1944 break;
b9b61529 1945 case C2OP:
1946 c2op_alloc(current,i);
1947 break;
57871462 1948 }
1949}
1950
1951// Special case where a branch and delay slot span two pages in virtual memory
1952static void pagespan_alloc(struct regstat *current,int i)
1953{
1954 current->isconst=0;
1955 current->wasconst=0;
1956 regs[i].wasconst=0;
e1190b87 1957 minimum_free_regs[i]=HOST_REGS;
57871462 1958 alloc_all(current,i);
1959 alloc_cc(current,i);
1960 dirty_reg(current,CCREG);
1961 if(opcode[i]==3) // JAL
1962 {
1963 alloc_reg(current,i,31);
1964 dirty_reg(current,31);
1965 }
1966 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1967 {
1968 alloc_reg(current,i,rs1[i]);
5067f341 1969 if (rt1[i]!=0) {
1970 alloc_reg(current,i,rt1[i]);
1971 dirty_reg(current,rt1[i]);
57871462 1972 }
1973 }
1974 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1975 {
1976 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1977 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1978 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1979 {
1980 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1981 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1982 }
1983 }
1984 else
1985 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1986 {
1987 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1988 if(!((current->is32>>rs1[i])&1))
1989 {
1990 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1991 }
1992 }
1993 else
1994 if(opcode[i]==0x11) // BC1
1995 {
1996 alloc_reg(current,i,FSREG);
1997 alloc_reg(current,i,CSREG);
1998 }
1999 //else ...
2000}
2001
2002add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
2003{
2004 stubs[stubcount][0]=type;
2005 stubs[stubcount][1]=addr;
2006 stubs[stubcount][2]=retaddr;
2007 stubs[stubcount][3]=a;
2008 stubs[stubcount][4]=b;
2009 stubs[stubcount][5]=c;
2010 stubs[stubcount][6]=d;
2011 stubs[stubcount][7]=e;
2012 stubcount++;
2013}
2014
2015// Write out a single register
2016void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2017{
2018 int hr;
2019 for(hr=0;hr<HOST_REGS;hr++) {
2020 if(hr!=EXCLUDE_REG) {
2021 if((regmap[hr]&63)==r) {
2022 if((dirty>>hr)&1) {
2023 if(regmap[hr]<64) {
2024 emit_storereg(r,hr);
24385cae 2025#ifndef FORCE32
57871462 2026 if((is32>>regmap[hr])&1) {
2027 emit_sarimm(hr,31,hr);
2028 emit_storereg(r|64,hr);
2029 }
24385cae 2030#endif
57871462 2031 }else{
2032 emit_storereg(r|64,hr);
2033 }
2034 }
2035 }
2036 }
2037 }
2038}
2039
2040int mchecksum()
2041{
2042 //if(!tracedebug) return 0;
2043 int i;
2044 int sum=0;
2045 for(i=0;i<2097152;i++) {
2046 unsigned int temp=sum;
2047 sum<<=1;
2048 sum|=(~temp)>>31;
2049 sum^=((u_int *)rdram)[i];
2050 }
2051 return sum;
2052}
2053int rchecksum()
2054{
2055 int i;
2056 int sum=0;
2057 for(i=0;i<64;i++)
2058 sum^=((u_int *)reg)[i];
2059 return sum;
2060}
57871462 2061void rlist()
2062{
2063 int i;
2064 printf("TRACE: ");
2065 for(i=0;i<32;i++)
2066 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2067 printf("\n");
3d624f89 2068#ifndef DISABLE_COP1
57871462 2069 printf("TRACE: ");
2070 for(i=0;i<32;i++)
2071 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2072 printf("\n");
3d624f89 2073#endif
57871462 2074}
2075
2076void enabletrace()
2077{
2078 tracedebug=1;
2079}
2080
2081void memdebug(int i)
2082{
2083 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2084 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2085 //rlist();
2086 //if(tracedebug) {
2087 //if(Count>=-2084597794) {
2088 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2089 //if(0) {
2090 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2091 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2092 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2093 rlist();
2094 #ifdef __i386__
2095 printf("TRACE: %x\n",(&i)[-1]);
2096 #endif
2097 #ifdef __arm__
2098 int j;
2099 printf("TRACE: %x \n",(&j)[10]);
2100 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2101 #endif
2102 //fflush(stdout);
2103 }
2104 //printf("TRACE: %x\n",(&i)[-1]);
2105}
2106
2107void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2108{
2109 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2110}
2111
2112void alu_assemble(int i,struct regstat *i_regs)
2113{
2114 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2115 if(rt1[i]) {
2116 signed char s1,s2,t;
2117 t=get_reg(i_regs->regmap,rt1[i]);
2118 if(t>=0) {
2119 s1=get_reg(i_regs->regmap,rs1[i]);
2120 s2=get_reg(i_regs->regmap,rs2[i]);
2121 if(rs1[i]&&rs2[i]) {
2122 assert(s1>=0);
2123 assert(s2>=0);
2124 if(opcode2[i]&2) emit_sub(s1,s2,t);
2125 else emit_add(s1,s2,t);
2126 }
2127 else if(rs1[i]) {
2128 if(s1>=0) emit_mov(s1,t);
2129 else emit_loadreg(rs1[i],t);
2130 }
2131 else if(rs2[i]) {
2132 if(s2>=0) {
2133 if(opcode2[i]&2) emit_neg(s2,t);
2134 else emit_mov(s2,t);
2135 }
2136 else {
2137 emit_loadreg(rs2[i],t);
2138 if(opcode2[i]&2) emit_neg(t,t);
2139 }
2140 }
2141 else emit_zeroreg(t);
2142 }
2143 }
2144 }
2145 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2146 if(rt1[i]) {
2147 signed char s1l,s2l,s1h,s2h,tl,th;
2148 tl=get_reg(i_regs->regmap,rt1[i]);
2149 th=get_reg(i_regs->regmap,rt1[i]|64);
2150 if(tl>=0) {
2151 s1l=get_reg(i_regs->regmap,rs1[i]);
2152 s2l=get_reg(i_regs->regmap,rs2[i]);
2153 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2154 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2155 if(rs1[i]&&rs2[i]) {
2156 assert(s1l>=0);
2157 assert(s2l>=0);
2158 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2159 else emit_adds(s1l,s2l,tl);
2160 if(th>=0) {
2161 #ifdef INVERTED_CARRY
2162 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2163 #else
2164 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2165 #endif
2166 else emit_add(s1h,s2h,th);
2167 }
2168 }
2169 else if(rs1[i]) {
2170 if(s1l>=0) emit_mov(s1l,tl);
2171 else emit_loadreg(rs1[i],tl);
2172 if(th>=0) {
2173 if(s1h>=0) emit_mov(s1h,th);
2174 else emit_loadreg(rs1[i]|64,th);
2175 }
2176 }
2177 else if(rs2[i]) {
2178 if(s2l>=0) {
2179 if(opcode2[i]&2) emit_negs(s2l,tl);
2180 else emit_mov(s2l,tl);
2181 }
2182 else {
2183 emit_loadreg(rs2[i],tl);
2184 if(opcode2[i]&2) emit_negs(tl,tl);
2185 }
2186 if(th>=0) {
2187 #ifdef INVERTED_CARRY
2188 if(s2h>=0) emit_mov(s2h,th);
2189 else emit_loadreg(rs2[i]|64,th);
2190 if(opcode2[i]&2) {
2191 emit_adcimm(-1,th); // x86 has inverted carry flag
2192 emit_not(th,th);
2193 }
2194 #else
2195 if(opcode2[i]&2) {
2196 if(s2h>=0) emit_rscimm(s2h,0,th);
2197 else {
2198 emit_loadreg(rs2[i]|64,th);
2199 emit_rscimm(th,0,th);
2200 }
2201 }else{
2202 if(s2h>=0) emit_mov(s2h,th);
2203 else emit_loadreg(rs2[i]|64,th);
2204 }
2205 #endif
2206 }
2207 }
2208 else {
2209 emit_zeroreg(tl);
2210 if(th>=0) emit_zeroreg(th);
2211 }
2212 }
2213 }
2214 }
2215 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2216 if(rt1[i]) {
2217 signed char s1l,s1h,s2l,s2h,t;
2218 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2219 {
2220 t=get_reg(i_regs->regmap,rt1[i]);
2221 //assert(t>=0);
2222 if(t>=0) {
2223 s1l=get_reg(i_regs->regmap,rs1[i]);
2224 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2225 s2l=get_reg(i_regs->regmap,rs2[i]);
2226 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2227 if(rs2[i]==0) // rx<r0
2228 {
2229 assert(s1h>=0);
2230 if(opcode2[i]==0x2a) // SLT
2231 emit_shrimm(s1h,31,t);
2232 else // SLTU (unsigned can not be less than zero)
2233 emit_zeroreg(t);
2234 }
2235 else if(rs1[i]==0) // r0<rx
2236 {
2237 assert(s2h>=0);
2238 if(opcode2[i]==0x2a) // SLT
2239 emit_set_gz64_32(s2h,s2l,t);
2240 else // SLTU (set if not zero)
2241 emit_set_nz64_32(s2h,s2l,t);
2242 }
2243 else {
2244 assert(s1l>=0);assert(s1h>=0);
2245 assert(s2l>=0);assert(s2h>=0);
2246 if(opcode2[i]==0x2a) // SLT
2247 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2248 else // SLTU
2249 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2250 }
2251 }
2252 } else {
2253 t=get_reg(i_regs->regmap,rt1[i]);
2254 //assert(t>=0);
2255 if(t>=0) {
2256 s1l=get_reg(i_regs->regmap,rs1[i]);
2257 s2l=get_reg(i_regs->regmap,rs2[i]);
2258 if(rs2[i]==0) // rx<r0
2259 {
2260 assert(s1l>=0);
2261 if(opcode2[i]==0x2a) // SLT
2262 emit_shrimm(s1l,31,t);
2263 else // SLTU (unsigned can not be less than zero)
2264 emit_zeroreg(t);
2265 }
2266 else if(rs1[i]==0) // r0<rx
2267 {
2268 assert(s2l>=0);
2269 if(opcode2[i]==0x2a) // SLT
2270 emit_set_gz32(s2l,t);
2271 else // SLTU (set if not zero)
2272 emit_set_nz32(s2l,t);
2273 }
2274 else{
2275 assert(s1l>=0);assert(s2l>=0);
2276 if(opcode2[i]==0x2a) // SLT
2277 emit_set_if_less32(s1l,s2l,t);
2278 else // SLTU
2279 emit_set_if_carry32(s1l,s2l,t);
2280 }
2281 }
2282 }
2283 }
2284 }
2285 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2286 if(rt1[i]) {
2287 signed char s1l,s1h,s2l,s2h,th,tl;
2288 tl=get_reg(i_regs->regmap,rt1[i]);
2289 th=get_reg(i_regs->regmap,rt1[i]|64);
2290 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2291 {
2292 assert(tl>=0);
2293 if(tl>=0) {
2294 s1l=get_reg(i_regs->regmap,rs1[i]);
2295 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2296 s2l=get_reg(i_regs->regmap,rs2[i]);
2297 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2298 if(rs1[i]&&rs2[i]) {
2299 assert(s1l>=0);assert(s1h>=0);
2300 assert(s2l>=0);assert(s2h>=0);
2301 if(opcode2[i]==0x24) { // AND
2302 emit_and(s1l,s2l,tl);
2303 emit_and(s1h,s2h,th);
2304 } else
2305 if(opcode2[i]==0x25) { // OR
2306 emit_or(s1l,s2l,tl);
2307 emit_or(s1h,s2h,th);
2308 } else
2309 if(opcode2[i]==0x26) { // XOR
2310 emit_xor(s1l,s2l,tl);
2311 emit_xor(s1h,s2h,th);
2312 } else
2313 if(opcode2[i]==0x27) { // NOR
2314 emit_or(s1l,s2l,tl);
2315 emit_or(s1h,s2h,th);
2316 emit_not(tl,tl);
2317 emit_not(th,th);
2318 }
2319 }
2320 else
2321 {
2322 if(opcode2[i]==0x24) { // AND
2323 emit_zeroreg(tl);
2324 emit_zeroreg(th);
2325 } else
2326 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2327 if(rs1[i]){
2328 if(s1l>=0) emit_mov(s1l,tl);
2329 else emit_loadreg(rs1[i],tl);
2330 if(s1h>=0) emit_mov(s1h,th);
2331 else emit_loadreg(rs1[i]|64,th);
2332 }
2333 else
2334 if(rs2[i]){
2335 if(s2l>=0) emit_mov(s2l,tl);
2336 else emit_loadreg(rs2[i],tl);
2337 if(s2h>=0) emit_mov(s2h,th);
2338 else emit_loadreg(rs2[i]|64,th);
2339 }
2340 else{
2341 emit_zeroreg(tl);
2342 emit_zeroreg(th);
2343 }
2344 } else
2345 if(opcode2[i]==0x27) { // NOR
2346 if(rs1[i]){
2347 if(s1l>=0) emit_not(s1l,tl);
2348 else{
2349 emit_loadreg(rs1[i],tl);
2350 emit_not(tl,tl);
2351 }
2352 if(s1h>=0) emit_not(s1h,th);
2353 else{
2354 emit_loadreg(rs1[i]|64,th);
2355 emit_not(th,th);
2356 }
2357 }
2358 else
2359 if(rs2[i]){
2360 if(s2l>=0) emit_not(s2l,tl);
2361 else{
2362 emit_loadreg(rs2[i],tl);
2363 emit_not(tl,tl);
2364 }
2365 if(s2h>=0) emit_not(s2h,th);
2366 else{
2367 emit_loadreg(rs2[i]|64,th);
2368 emit_not(th,th);
2369 }
2370 }
2371 else {
2372 emit_movimm(-1,tl);
2373 emit_movimm(-1,th);
2374 }
2375 }
2376 }
2377 }
2378 }
2379 else
2380 {
2381 // 32 bit
2382 if(tl>=0) {
2383 s1l=get_reg(i_regs->regmap,rs1[i]);
2384 s2l=get_reg(i_regs->regmap,rs2[i]);
2385 if(rs1[i]&&rs2[i]) {
2386 assert(s1l>=0);
2387 assert(s2l>=0);
2388 if(opcode2[i]==0x24) { // AND
2389 emit_and(s1l,s2l,tl);
2390 } else
2391 if(opcode2[i]==0x25) { // OR
2392 emit_or(s1l,s2l,tl);
2393 } else
2394 if(opcode2[i]==0x26) { // XOR
2395 emit_xor(s1l,s2l,tl);
2396 } else
2397 if(opcode2[i]==0x27) { // NOR
2398 emit_or(s1l,s2l,tl);
2399 emit_not(tl,tl);
2400 }
2401 }
2402 else
2403 {
2404 if(opcode2[i]==0x24) { // AND
2405 emit_zeroreg(tl);
2406 } else
2407 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2408 if(rs1[i]){
2409 if(s1l>=0) emit_mov(s1l,tl);
2410 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2411 }
2412 else
2413 if(rs2[i]){
2414 if(s2l>=0) emit_mov(s2l,tl);
2415 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2416 }
2417 else emit_zeroreg(tl);
2418 } else
2419 if(opcode2[i]==0x27) { // NOR
2420 if(rs1[i]){
2421 if(s1l>=0) emit_not(s1l,tl);
2422 else {
2423 emit_loadreg(rs1[i],tl);
2424 emit_not(tl,tl);
2425 }
2426 }
2427 else
2428 if(rs2[i]){
2429 if(s2l>=0) emit_not(s2l,tl);
2430 else {
2431 emit_loadreg(rs2[i],tl);
2432 emit_not(tl,tl);
2433 }
2434 }
2435 else emit_movimm(-1,tl);
2436 }
2437 }
2438 }
2439 }
2440 }
2441 }
2442}
2443
2444void imm16_assemble(int i,struct regstat *i_regs)
2445{
2446 if (opcode[i]==0x0f) { // LUI
2447 if(rt1[i]) {
2448 signed char t;
2449 t=get_reg(i_regs->regmap,rt1[i]);
2450 //assert(t>=0);
2451 if(t>=0) {
2452 if(!((i_regs->isconst>>t)&1))
2453 emit_movimm(imm[i]<<16,t);
2454 }
2455 }
2456 }
2457 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2458 if(rt1[i]) {
2459 signed char s,t;
2460 t=get_reg(i_regs->regmap,rt1[i]);
2461 s=get_reg(i_regs->regmap,rs1[i]);
2462 if(rs1[i]) {
2463 //assert(t>=0);
2464 //assert(s>=0);
2465 if(t>=0) {
2466 if(!((i_regs->isconst>>t)&1)) {
2467 if(s<0) {
2468 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2469 emit_addimm(t,imm[i],t);
2470 }else{
2471 if(!((i_regs->wasconst>>s)&1))
2472 emit_addimm(s,imm[i],t);
2473 else
2474 emit_movimm(constmap[i][s]+imm[i],t);
2475 }
2476 }
2477 }
2478 } else {
2479 if(t>=0) {
2480 if(!((i_regs->isconst>>t)&1))
2481 emit_movimm(imm[i],t);
2482 }
2483 }
2484 }
2485 }
2486 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2487 if(rt1[i]) {
2488 signed char sh,sl,th,tl;
2489 th=get_reg(i_regs->regmap,rt1[i]|64);
2490 tl=get_reg(i_regs->regmap,rt1[i]);
2491 sh=get_reg(i_regs->regmap,rs1[i]|64);
2492 sl=get_reg(i_regs->regmap,rs1[i]);
2493 if(tl>=0) {
2494 if(rs1[i]) {
2495 assert(sh>=0);
2496 assert(sl>=0);
2497 if(th>=0) {
2498 emit_addimm64_32(sh,sl,imm[i],th,tl);
2499 }
2500 else {
2501 emit_addimm(sl,imm[i],tl);
2502 }
2503 } else {
2504 emit_movimm(imm[i],tl);
2505 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2506 }
2507 }
2508 }
2509 }
2510 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2511 if(rt1[i]) {
2512 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2513 signed char sh,sl,t;
2514 t=get_reg(i_regs->regmap,rt1[i]);
2515 sh=get_reg(i_regs->regmap,rs1[i]|64);
2516 sl=get_reg(i_regs->regmap,rs1[i]);
2517 //assert(t>=0);
2518 if(t>=0) {
2519 if(rs1[i]>0) {
2520 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2521 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2522 if(opcode[i]==0x0a) { // SLTI
2523 if(sl<0) {
2524 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2525 emit_slti32(t,imm[i],t);
2526 }else{
2527 emit_slti32(sl,imm[i],t);
2528 }
2529 }
2530 else { // SLTIU
2531 if(sl<0) {
2532 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2533 emit_sltiu32(t,imm[i],t);
2534 }else{
2535 emit_sltiu32(sl,imm[i],t);
2536 }
2537 }
2538 }else{ // 64-bit
2539 assert(sl>=0);
2540 if(opcode[i]==0x0a) // SLTI
2541 emit_slti64_32(sh,sl,imm[i],t);
2542 else // SLTIU
2543 emit_sltiu64_32(sh,sl,imm[i],t);
2544 }
2545 }else{
2546 // SLTI(U) with r0 is just stupid,
2547 // nonetheless examples can be found
2548 if(opcode[i]==0x0a) // SLTI
2549 if(0<imm[i]) emit_movimm(1,t);
2550 else emit_zeroreg(t);
2551 else // SLTIU
2552 {
2553 if(imm[i]) emit_movimm(1,t);
2554 else emit_zeroreg(t);
2555 }
2556 }
2557 }
2558 }
2559 }
2560 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2561 if(rt1[i]) {
2562 signed char sh,sl,th,tl;
2563 th=get_reg(i_regs->regmap,rt1[i]|64);
2564 tl=get_reg(i_regs->regmap,rt1[i]);
2565 sh=get_reg(i_regs->regmap,rs1[i]|64);
2566 sl=get_reg(i_regs->regmap,rs1[i]);
2567 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2568 if(opcode[i]==0x0c) //ANDI
2569 {
2570 if(rs1[i]) {
2571 if(sl<0) {
2572 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2573 emit_andimm(tl,imm[i],tl);
2574 }else{
2575 if(!((i_regs->wasconst>>sl)&1))
2576 emit_andimm(sl,imm[i],tl);
2577 else
2578 emit_movimm(constmap[i][sl]&imm[i],tl);
2579 }
2580 }
2581 else
2582 emit_zeroreg(tl);
2583 if(th>=0) emit_zeroreg(th);
2584 }
2585 else
2586 {
2587 if(rs1[i]) {
2588 if(sl<0) {
2589 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2590 }
2591 if(th>=0) {
2592 if(sh<0) {
2593 emit_loadreg(rs1[i]|64,th);
2594 }else{
2595 emit_mov(sh,th);
2596 }
2597 }
2598 if(opcode[i]==0x0d) //ORI
2599 if(sl<0) {
2600 emit_orimm(tl,imm[i],tl);
2601 }else{
2602 if(!((i_regs->wasconst>>sl)&1))
2603 emit_orimm(sl,imm[i],tl);
2604 else
2605 emit_movimm(constmap[i][sl]|imm[i],tl);
2606 }
2607 if(opcode[i]==0x0e) //XORI
2608 if(sl<0) {
2609 emit_xorimm(tl,imm[i],tl);
2610 }else{
2611 if(!((i_regs->wasconst>>sl)&1))
2612 emit_xorimm(sl,imm[i],tl);
2613 else
2614 emit_movimm(constmap[i][sl]^imm[i],tl);
2615 }
2616 }
2617 else {
2618 emit_movimm(imm[i],tl);
2619 if(th>=0) emit_zeroreg(th);
2620 }
2621 }
2622 }
2623 }
2624 }
2625}
2626
2627void shiftimm_assemble(int i,struct regstat *i_regs)
2628{
2629 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2630 {
2631 if(rt1[i]) {
2632 signed char s,t;
2633 t=get_reg(i_regs->regmap,rt1[i]);
2634 s=get_reg(i_regs->regmap,rs1[i]);
2635 //assert(t>=0);
2636 if(t>=0){
2637 if(rs1[i]==0)
2638 {
2639 emit_zeroreg(t);
2640 }
2641 else
2642 {
2643 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2644 if(imm[i]) {
2645 if(opcode2[i]==0) // SLL
2646 {
2647 emit_shlimm(s<0?t:s,imm[i],t);
2648 }
2649 if(opcode2[i]==2) // SRL
2650 {
2651 emit_shrimm(s<0?t:s,imm[i],t);
2652 }
2653 if(opcode2[i]==3) // SRA
2654 {
2655 emit_sarimm(s<0?t:s,imm[i],t);
2656 }
2657 }else{
2658 // Shift by zero
2659 if(s>=0 && s!=t) emit_mov(s,t);
2660 }
2661 }
2662 }
2663 //emit_storereg(rt1[i],t); //DEBUG
2664 }
2665 }
2666 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2667 {
2668 if(rt1[i]) {
2669 signed char sh,sl,th,tl;
2670 th=get_reg(i_regs->regmap,rt1[i]|64);
2671 tl=get_reg(i_regs->regmap,rt1[i]);
2672 sh=get_reg(i_regs->regmap,rs1[i]|64);
2673 sl=get_reg(i_regs->regmap,rs1[i]);
2674 if(tl>=0) {
2675 if(rs1[i]==0)
2676 {
2677 emit_zeroreg(tl);
2678 if(th>=0) emit_zeroreg(th);
2679 }
2680 else
2681 {
2682 assert(sl>=0);
2683 assert(sh>=0);
2684 if(imm[i]) {
2685 if(opcode2[i]==0x38) // DSLL
2686 {
2687 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2688 emit_shlimm(sl,imm[i],tl);
2689 }
2690 if(opcode2[i]==0x3a) // DSRL
2691 {
2692 emit_shrdimm(sl,sh,imm[i],tl);
2693 if(th>=0) emit_shrimm(sh,imm[i],th);
2694 }
2695 if(opcode2[i]==0x3b) // DSRA
2696 {
2697 emit_shrdimm(sl,sh,imm[i],tl);
2698 if(th>=0) emit_sarimm(sh,imm[i],th);
2699 }
2700 }else{
2701 // Shift by zero
2702 if(sl!=tl) emit_mov(sl,tl);
2703 if(th>=0&&sh!=th) emit_mov(sh,th);
2704 }
2705 }
2706 }
2707 }
2708 }
2709 if(opcode2[i]==0x3c) // DSLL32
2710 {
2711 if(rt1[i]) {
2712 signed char sl,tl,th;
2713 tl=get_reg(i_regs->regmap,rt1[i]);
2714 th=get_reg(i_regs->regmap,rt1[i]|64);
2715 sl=get_reg(i_regs->regmap,rs1[i]);
2716 if(th>=0||tl>=0){
2717 assert(tl>=0);
2718 assert(th>=0);
2719 assert(sl>=0);
2720 emit_mov(sl,th);
2721 emit_zeroreg(tl);
2722 if(imm[i]>32)
2723 {
2724 emit_shlimm(th,imm[i]&31,th);
2725 }
2726 }
2727 }
2728 }
2729 if(opcode2[i]==0x3e) // DSRL32
2730 {
2731 if(rt1[i]) {
2732 signed char sh,tl,th;
2733 tl=get_reg(i_regs->regmap,rt1[i]);
2734 th=get_reg(i_regs->regmap,rt1[i]|64);
2735 sh=get_reg(i_regs->regmap,rs1[i]|64);
2736 if(tl>=0){
2737 assert(sh>=0);
2738 emit_mov(sh,tl);
2739 if(th>=0) emit_zeroreg(th);
2740 if(imm[i]>32)
2741 {
2742 emit_shrimm(tl,imm[i]&31,tl);
2743 }
2744 }
2745 }
2746 }
2747 if(opcode2[i]==0x3f) // DSRA32
2748 {
2749 if(rt1[i]) {
2750 signed char sh,tl;
2751 tl=get_reg(i_regs->regmap,rt1[i]);
2752 sh=get_reg(i_regs->regmap,rs1[i]|64);
2753 if(tl>=0){
2754 assert(sh>=0);
2755 emit_mov(sh,tl);
2756 if(imm[i]>32)
2757 {
2758 emit_sarimm(tl,imm[i]&31,tl);
2759 }
2760 }
2761 }
2762 }
2763}
2764
2765#ifndef shift_assemble
2766void shift_assemble(int i,struct regstat *i_regs)
2767{
2768 printf("Need shift_assemble for this architecture.\n");
2769 exit(1);
2770}
2771#endif
2772
2773void load_assemble(int i,struct regstat *i_regs)
2774{
2775 int s,th,tl,addr,map=-1;
2776 int offset;
2777 int jaddr=0;
5bf843dc 2778 int memtarget=0,c=0;
57871462 2779 u_int hr,reglist=0;
2780 th=get_reg(i_regs->regmap,rt1[i]|64);
2781 tl=get_reg(i_regs->regmap,rt1[i]);
2782 s=get_reg(i_regs->regmap,rs1[i]);
2783 offset=imm[i];
2784 for(hr=0;hr<HOST_REGS;hr++) {
2785 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2786 }
2787 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2788 if(s>=0) {
2789 c=(i_regs->wasconst>>s)&1;
af4ee1fe 2790 if (c) {
2791 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2792 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2793 }
57871462 2794 }
57871462 2795 //printf("load_assemble: c=%d\n",c);
2796 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2797 // FIXME: Even if the load is a NOP, we should check for pagefaults...
5bf843dc 2798#ifdef PCSX
f18c0f46 2799 if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2800 ||rt1[i]==0) {
5bf843dc 2801 // could be FIFO, must perform the read
f18c0f46 2802 // ||dummy read
5bf843dc 2803 assem_debug("(forced read)\n");
2804 tl=get_reg(i_regs->regmap,-1);
2805 assert(tl>=0);
5bf843dc 2806 }
f18c0f46 2807#endif
5bf843dc 2808 if(offset||s<0||c) addr=tl;
2809 else addr=s;
535d208a 2810 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2811 if(tl>=0) {
2812 //printf("load_assemble: c=%d\n",c);
2813 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2814 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2815 reglist&=~(1<<tl);
2816 if(th>=0) reglist&=~(1<<th);
2817 if(!using_tlb) {
2818 if(!c) {
2819 #ifdef RAM_OFFSET
2820 map=get_reg(i_regs->regmap,ROREG);
2821 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2822 #endif
57871462 2823//#define R29_HACK 1
535d208a 2824 #ifdef R29_HACK
2825 // Strmnnrmn's speed hack
2826 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2827 #endif
2828 {
2829 emit_cmpimm(addr,RAM_SIZE);
2830 jaddr=(int)out;
2831 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2832 // Hint to branch predictor that the branch is unlikely to be taken
2833 if(rs1[i]>=28)
2834 emit_jno_unlikely(0);
2835 else
57871462 2836 #endif
535d208a 2837 emit_jno(0);
57871462 2838 }
535d208a 2839 }
2840 }else{ // using tlb
2841 int x=0;
2842 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2843 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2844 map=get_reg(i_regs->regmap,TLREG);
2845 assert(map>=0);
2846 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2847 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2848 }
2849 int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2850 if (opcode[i]==0x20) { // LB
2851 if(!c||memtarget) {
2852 if(!dummy) {
57871462 2853 #ifdef HOST_IMM_ADDR32
2854 if(c)
2855 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2856 else
2857 #endif
2858 {
2859 //emit_xorimm(addr,3,tl);
2860 //gen_tlb_addr_r(tl,map);
2861 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
535d208a 2862 int x=0,a=tl;
2002a1db 2863#ifdef BIG_ENDIAN_MIPS
57871462 2864 if(!c) emit_xorimm(addr,3,tl);
2865 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2866#else
535d208a 2867 if(!c) a=addr;
2002a1db 2868#endif
535d208a 2869 emit_movsbl_indexed_tlb(x,a,map,tl);
57871462 2870 }
57871462 2871 }
535d208a 2872 if(jaddr)
2873 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2874 }
535d208a 2875 else
2876 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2877 }
2878 if (opcode[i]==0x21) { // LH
2879 if(!c||memtarget) {
2880 if(!dummy) {
57871462 2881 #ifdef HOST_IMM_ADDR32
2882 if(c)
2883 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2884 else
2885 #endif
2886 {
535d208a 2887 int x=0,a=tl;
2002a1db 2888#ifdef BIG_ENDIAN_MIPS
57871462 2889 if(!c) emit_xorimm(addr,2,tl);
2890 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2891#else
535d208a 2892 if(!c) a=addr;
2002a1db 2893#endif
57871462 2894 //#ifdef
2895 //emit_movswl_indexed_tlb(x,tl,map,tl);
2896 //else
2897 if(map>=0) {
535d208a 2898 gen_tlb_addr_r(a,map);
2899 emit_movswl_indexed(x,a,tl);
2900 }else{
2901 #ifdef RAM_OFFSET
2902 emit_movswl_indexed(x,a,tl);
2903 #else
2904 emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2905 #endif
2906 }
57871462 2907 }
57871462 2908 }
535d208a 2909 if(jaddr)
2910 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2911 }
535d208a 2912 else
2913 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2914 }
2915 if (opcode[i]==0x23) { // LW
2916 if(!c||memtarget) {
2917 if(!dummy) {
57871462 2918 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2919 #ifdef HOST_IMM_ADDR32
2920 if(c)
2921 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2922 else
2923 #endif
2924 emit_readword_indexed_tlb(0,addr,map,tl);
57871462 2925 }
535d208a 2926 if(jaddr)
2927 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2928 }
535d208a 2929 else
2930 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2931 }
2932 if (opcode[i]==0x24) { // LBU
2933 if(!c||memtarget) {
2934 if(!dummy) {
57871462 2935 #ifdef HOST_IMM_ADDR32
2936 if(c)
2937 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2938 else
2939 #endif
2940 {
2941 //emit_xorimm(addr,3,tl);
2942 //gen_tlb_addr_r(tl,map);
2943 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
535d208a 2944 int x=0,a=tl;
2002a1db 2945#ifdef BIG_ENDIAN_MIPS
57871462 2946 if(!c) emit_xorimm(addr,3,tl);
2947 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2948#else
535d208a 2949 if(!c) a=addr;
2002a1db 2950#endif
535d208a 2951 emit_movzbl_indexed_tlb(x,a,map,tl);
57871462 2952 }
57871462 2953 }
535d208a 2954 if(jaddr)
2955 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2956 }
535d208a 2957 else
2958 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2959 }
2960 if (opcode[i]==0x25) { // LHU
2961 if(!c||memtarget) {
2962 if(!dummy) {
57871462 2963 #ifdef HOST_IMM_ADDR32
2964 if(c)
2965 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2966 else
2967 #endif
2968 {
535d208a 2969 int x=0,a=tl;
2002a1db 2970#ifdef BIG_ENDIAN_MIPS
57871462 2971 if(!c) emit_xorimm(addr,2,tl);
2972 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2973#else
535d208a 2974 if(!c) a=addr;
2002a1db 2975#endif
57871462 2976 //#ifdef
2977 //emit_movzwl_indexed_tlb(x,tl,map,tl);
2978 //#else
2979 if(map>=0) {
535d208a 2980 gen_tlb_addr_r(a,map);
2981 emit_movzwl_indexed(x,a,tl);
2982 }else{
2983 #ifdef RAM_OFFSET
2984 emit_movzwl_indexed(x,a,tl);
2985 #else
2986 emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
2987 #endif
2988 }
57871462 2989 }
2990 }
535d208a 2991 if(jaddr)
2992 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2993 }
535d208a 2994 else
2995 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2996 }
2997 if (opcode[i]==0x27) { // LWU
2998 assert(th>=0);
2999 if(!c||memtarget) {
3000 if(!dummy) {
57871462 3001 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3002 #ifdef HOST_IMM_ADDR32
3003 if(c)
3004 emit_readword_tlb(constmap[i][s]+offset,map,tl);
3005 else
3006 #endif
3007 emit_readword_indexed_tlb(0,addr,map,tl);
57871462 3008 }
535d208a 3009 if(jaddr)
3010 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3011 }
3012 else {
3013 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
57871462 3014 }
535d208a 3015 emit_zeroreg(th);
3016 }
3017 if (opcode[i]==0x37) { // LD
3018 if(!c||memtarget) {
3019 if(!dummy) {
57871462 3020 //gen_tlb_addr_r(tl,map);
3021 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3022 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3023 #ifdef HOST_IMM_ADDR32
3024 if(c)
3025 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3026 else
3027 #endif
3028 emit_readdword_indexed_tlb(0,addr,map,th,tl);
57871462 3029 }
535d208a 3030 if(jaddr)
3031 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 3032 }
535d208a 3033 else
3034 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
57871462 3035 }
535d208a 3036 }
3037 //emit_storereg(rt1[i],tl); // DEBUG
57871462 3038 //if(opcode[i]==0x23)
3039 //if(opcode[i]==0x24)
3040 //if(opcode[i]==0x23||opcode[i]==0x24)
3041 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3042 {
3043 //emit_pusha();
3044 save_regs(0x100f);
3045 emit_readword((int)&last_count,ECX);
3046 #ifdef __i386__
3047 if(get_reg(i_regs->regmap,CCREG)<0)
3048 emit_loadreg(CCREG,HOST_CCREG);
3049 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3050 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3051 emit_writeword(HOST_CCREG,(int)&Count);
3052 #endif
3053 #ifdef __arm__
3054 if(get_reg(i_regs->regmap,CCREG)<0)
3055 emit_loadreg(CCREG,0);
3056 else
3057 emit_mov(HOST_CCREG,0);
3058 emit_add(0,ECX,0);
3059 emit_addimm(0,2*ccadj[i],0);
3060 emit_writeword(0,(int)&Count);
3061 #endif
3062 emit_call((int)memdebug);
3063 //emit_popa();
3064 restore_regs(0x100f);
3065 }/**/
3066}
3067
3068#ifndef loadlr_assemble
3069void loadlr_assemble(int i,struct regstat *i_regs)
3070{
3071 printf("Need loadlr_assemble for this architecture.\n");
3072 exit(1);
3073}
3074#endif
3075
3076void store_assemble(int i,struct regstat *i_regs)
3077{
3078 int s,th,tl,map=-1;
3079 int addr,temp;
3080 int offset;
3081 int jaddr=0,jaddr2,type;
666a299d 3082 int memtarget=0,c=0;
57871462 3083 int agr=AGEN1+(i&1);
3084 u_int hr,reglist=0;
3085 th=get_reg(i_regs->regmap,rs2[i]|64);
3086 tl=get_reg(i_regs->regmap,rs2[i]);
3087 s=get_reg(i_regs->regmap,rs1[i]);
3088 temp=get_reg(i_regs->regmap,agr);
3089 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3090 offset=imm[i];
3091 if(s>=0) {
3092 c=(i_regs->wasconst>>s)&1;
af4ee1fe 3093 if(c) {
3094 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3095 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3096 }
57871462 3097 }
3098 assert(tl>=0);
3099 assert(temp>=0);
3100 for(hr=0;hr<HOST_REGS;hr++) {
3101 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3102 }
3103 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3104 if(offset||s<0||c) addr=temp;
3105 else addr=s;
3106 if(!using_tlb) {
3107 if(!c) {
3108 #ifdef R29_HACK
3109 // Strmnnrmn's speed hack
3110 memtarget=1;
4cb76aa4 3111 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
57871462 3112 #endif
4cb76aa4 3113 emit_cmpimm(addr,RAM_SIZE);
57871462 3114 #ifdef DESTRUCTIVE_SHIFT
3115 if(s==addr) emit_mov(s,temp);
3116 #endif
3117 #ifdef R29_HACK
4cb76aa4 3118 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
57871462 3119 #endif
3120 {
3121 jaddr=(int)out;
3122 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3123 // Hint to branch predictor that the branch is unlikely to be taken
3124 if(rs1[i]>=28)
3125 emit_jno_unlikely(0);
3126 else
3127 #endif
3128 emit_jno(0);
3129 }
3130 }
3131 }else{ // using tlb
3132 int x=0;
3133 if (opcode[i]==0x28) x=3; // SB
3134 if (opcode[i]==0x29) x=2; // SH
3135 map=get_reg(i_regs->regmap,TLREG);
3136 assert(map>=0);
3137 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3138 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3139 }
3140
3141 if (opcode[i]==0x28) { // SB
3142 if(!c||memtarget) {
97a238a6 3143 int x=0,a=temp;
2002a1db 3144#ifdef BIG_ENDIAN_MIPS
57871462 3145 if(!c) emit_xorimm(addr,3,temp);
3146 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 3147#else
97a238a6 3148 if(!c) a=addr;
2002a1db 3149#endif
57871462 3150 //gen_tlb_addr_w(temp,map);
3151 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
97a238a6 3152 emit_writebyte_indexed_tlb(tl,x,a,map,a);
57871462 3153 }
3154 type=STOREB_STUB;
3155 }
3156 if (opcode[i]==0x29) { // SH
3157 if(!c||memtarget) {
97a238a6 3158 int x=0,a=temp;
2002a1db 3159#ifdef BIG_ENDIAN_MIPS
57871462 3160 if(!c) emit_xorimm(addr,2,temp);
3161 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 3162#else
97a238a6 3163 if(!c) a=addr;
2002a1db 3164#endif
57871462 3165 //#ifdef
3166 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3167 //#else
3168 if(map>=0) {
97a238a6 3169 gen_tlb_addr_w(a,map);
3170 emit_writehword_indexed(tl,x,a);
57871462 3171 }else
97a238a6 3172 emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
57871462 3173 }
3174 type=STOREH_STUB;
3175 }
3176 if (opcode[i]==0x2B) { // SW
3177 if(!c||memtarget)
3178 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3179 emit_writeword_indexed_tlb(tl,0,addr,map,temp);
3180 type=STOREW_STUB;
3181 }
3182 if (opcode[i]==0x3F) { // SD
3183 if(!c||memtarget) {
3184 if(rs2[i]) {
3185 assert(th>=0);
3186 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3187 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3188 emit_writedword_indexed_tlb(th,tl,0,addr,map,temp);
3189 }else{
3190 // Store zero
3191 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3192 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3193 emit_writedword_indexed_tlb(tl,tl,0,addr,map,temp);
3194 }
3195 }
3196 type=STORED_STUB;
3197 }
57871462 3198 if(!using_tlb) {
3199 if(!c||memtarget) {
3200 #ifdef DESTRUCTIVE_SHIFT
3201 // The x86 shift operation is 'destructive'; it overwrites the
3202 // source register, so we need to make a copy first and use that.
3203 addr=temp;
3204 #endif
3205 #if defined(HOST_IMM8)
3206 int ir=get_reg(i_regs->regmap,INVCP);
3207 assert(ir>=0);
3208 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3209 #else
3210 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3211 #endif
0bbd1454 3212 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3213 emit_callne(invalidate_addr_reg[addr]);
3214 #else
57871462 3215 jaddr2=(int)out;
3216 emit_jne(0);
3217 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
0bbd1454 3218 #endif
57871462 3219 }
3220 }
3eaa7048 3221 if(jaddr) {
3222 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3223 } else if(c&&!memtarget) {
3224 inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3225 }
57871462 3226 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3227 //if(opcode[i]==0x2B || opcode[i]==0x28)
3228 //if(opcode[i]==0x2B || opcode[i]==0x29)
3229 //if(opcode[i]==0x2B)
3230 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3231 {
3232 //emit_pusha();
3233 save_regs(0x100f);
3234 emit_readword((int)&last_count,ECX);
3235 #ifdef __i386__
3236 if(get_reg(i_regs->regmap,CCREG)<0)
3237 emit_loadreg(CCREG,HOST_CCREG);
3238 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3239 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3240 emit_writeword(HOST_CCREG,(int)&Count);
3241 #endif
3242 #ifdef __arm__
3243 if(get_reg(i_regs->regmap,CCREG)<0)
3244 emit_loadreg(CCREG,0);
3245 else
3246 emit_mov(HOST_CCREG,0);
3247 emit_add(0,ECX,0);
3248 emit_addimm(0,2*ccadj[i],0);
3249 emit_writeword(0,(int)&Count);
3250 #endif
3251 emit_call((int)memdebug);
3252 //emit_popa();
3253 restore_regs(0x100f);
3254 }/**/
3255}
3256
3257void storelr_assemble(int i,struct regstat *i_regs)
3258{
3259 int s,th,tl;
3260 int temp;
3261 int temp2;
3262 int offset;
3263 int jaddr=0,jaddr2;
3264 int case1,case2,case3;
3265 int done0,done1,done2;
af4ee1fe 3266 int memtarget=0,c=0;
fab5d06d 3267 int agr=AGEN1+(i&1);
57871462 3268 u_int hr,reglist=0;
3269 th=get_reg(i_regs->regmap,rs2[i]|64);
3270 tl=get_reg(i_regs->regmap,rs2[i]);
3271 s=get_reg(i_regs->regmap,rs1[i]);
fab5d06d 3272 temp=get_reg(i_regs->regmap,agr);
3273 if(temp<0) temp=get_reg(i_regs->regmap,-1);
57871462 3274 offset=imm[i];
3275 if(s>=0) {
3276 c=(i_regs->isconst>>s)&1;
af4ee1fe 3277 if(c) {
3278 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3279 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3280 }
57871462 3281 }
3282 assert(tl>=0);
3283 for(hr=0;hr<HOST_REGS;hr++) {
3284 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3285 }
535d208a 3286 assert(temp>=0);
3287 if(!using_tlb) {
3288 if(!c) {
3289 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3290 if(!offset&&s!=temp) emit_mov(s,temp);
3291 jaddr=(int)out;
3292 emit_jno(0);
3293 }
3294 else
3295 {
3296 if(!memtarget||!rs1[i]) {
57871462 3297 jaddr=(int)out;
3298 emit_jmp(0);
3299 }
57871462 3300 }
535d208a 3301 #ifdef RAM_OFFSET
3302 int map=get_reg(i_regs->regmap,ROREG);
3303 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3304 gen_tlb_addr_w(temp,map);
3305 #else
3306 if((u_int)rdram!=0x80000000)
3307 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3308 #endif
3309 }else{ // using tlb
3310 int map=get_reg(i_regs->regmap,TLREG);
3311 assert(map>=0);
3312 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3313 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3314 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3315 if(!jaddr&&!memtarget) {
3316 jaddr=(int)out;
3317 emit_jmp(0);
57871462 3318 }
535d208a 3319 gen_tlb_addr_w(temp,map);
3320 }
3321
3322 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3323 temp2=get_reg(i_regs->regmap,FTEMP);
3324 if(!rs2[i]) temp2=th=tl;
3325 }
57871462 3326
2002a1db 3327#ifndef BIG_ENDIAN_MIPS
3328 emit_xorimm(temp,3,temp);
3329#endif
535d208a 3330 emit_testimm(temp,2);
3331 case2=(int)out;
3332 emit_jne(0);
3333 emit_testimm(temp,1);
3334 case1=(int)out;
3335 emit_jne(0);
3336 // 0
3337 if (opcode[i]==0x2A) { // SWL
3338 emit_writeword_indexed(tl,0,temp);
3339 }
3340 if (opcode[i]==0x2E) { // SWR
3341 emit_writebyte_indexed(tl,3,temp);
3342 }
3343 if (opcode[i]==0x2C) { // SDL
3344 emit_writeword_indexed(th,0,temp);
3345 if(rs2[i]) emit_mov(tl,temp2);
3346 }
3347 if (opcode[i]==0x2D) { // SDR
3348 emit_writebyte_indexed(tl,3,temp);
3349 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3350 }
3351 done0=(int)out;
3352 emit_jmp(0);
3353 // 1
3354 set_jump_target(case1,(int)out);
3355 if (opcode[i]==0x2A) { // SWL
3356 // Write 3 msb into three least significant bytes
3357 if(rs2[i]) emit_rorimm(tl,8,tl);
3358 emit_writehword_indexed(tl,-1,temp);
3359 if(rs2[i]) emit_rorimm(tl,16,tl);
3360 emit_writebyte_indexed(tl,1,temp);
3361 if(rs2[i]) emit_rorimm(tl,8,tl);
3362 }
3363 if (opcode[i]==0x2E) { // SWR
3364 // Write two lsb into two most significant bytes
3365 emit_writehword_indexed(tl,1,temp);
3366 }
3367 if (opcode[i]==0x2C) { // SDL
3368 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3369 // Write 3 msb into three least significant bytes
3370 if(rs2[i]) emit_rorimm(th,8,th);
3371 emit_writehword_indexed(th,-1,temp);
3372 if(rs2[i]) emit_rorimm(th,16,th);
3373 emit_writebyte_indexed(th,1,temp);
3374 if(rs2[i]) emit_rorimm(th,8,th);
3375 }
3376 if (opcode[i]==0x2D) { // SDR
3377 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3378 // Write two lsb into two most significant bytes
3379 emit_writehword_indexed(tl,1,temp);
3380 }
3381 done1=(int)out;
3382 emit_jmp(0);
3383 // 2
3384 set_jump_target(case2,(int)out);
3385 emit_testimm(temp,1);
3386 case3=(int)out;
3387 emit_jne(0);
3388 if (opcode[i]==0x2A) { // SWL
3389 // Write two msb into two least significant bytes
3390 if(rs2[i]) emit_rorimm(tl,16,tl);
3391 emit_writehword_indexed(tl,-2,temp);
3392 if(rs2[i]) emit_rorimm(tl,16,tl);
3393 }
3394 if (opcode[i]==0x2E) { // SWR
3395 // Write 3 lsb into three most significant bytes
3396 emit_writebyte_indexed(tl,-1,temp);
3397 if(rs2[i]) emit_rorimm(tl,8,tl);
3398 emit_writehword_indexed(tl,0,temp);
3399 if(rs2[i]) emit_rorimm(tl,24,tl);
3400 }
3401 if (opcode[i]==0x2C) { // SDL
3402 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3403 // Write two msb into two least significant bytes
3404 if(rs2[i]) emit_rorimm(th,16,th);
3405 emit_writehword_indexed(th,-2,temp);
3406 if(rs2[i]) emit_rorimm(th,16,th);
3407 }
3408 if (opcode[i]==0x2D) { // SDR
3409 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3410 // Write 3 lsb into three most significant bytes
3411 emit_writebyte_indexed(tl,-1,temp);
3412 if(rs2[i]) emit_rorimm(tl,8,tl);
3413 emit_writehword_indexed(tl,0,temp);
3414 if(rs2[i]) emit_rorimm(tl,24,tl);
3415 }
3416 done2=(int)out;
3417 emit_jmp(0);
3418 // 3
3419 set_jump_target(case3,(int)out);
3420 if (opcode[i]==0x2A) { // SWL
3421 // Write msb into least significant byte
3422 if(rs2[i]) emit_rorimm(tl,24,tl);
3423 emit_writebyte_indexed(tl,-3,temp);
3424 if(rs2[i]) emit_rorimm(tl,8,tl);
3425 }
3426 if (opcode[i]==0x2E) { // SWR
3427 // Write entire word
3428 emit_writeword_indexed(tl,-3,temp);
3429 }
3430 if (opcode[i]==0x2C) { // SDL
3431 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3432 // Write msb into least significant byte
3433 if(rs2[i]) emit_rorimm(th,24,th);
3434 emit_writebyte_indexed(th,-3,temp);
3435 if(rs2[i]) emit_rorimm(th,8,th);
3436 }
3437 if (opcode[i]==0x2D) { // SDR
3438 if(rs2[i]) emit_mov(th,temp2);
3439 // Write entire word
3440 emit_writeword_indexed(tl,-3,temp);
3441 }
3442 set_jump_target(done0,(int)out);
3443 set_jump_target(done1,(int)out);
3444 set_jump_target(done2,(int)out);
3445 if (opcode[i]==0x2C) { // SDL
3446 emit_testimm(temp,4);
57871462 3447 done0=(int)out;
57871462 3448 emit_jne(0);
535d208a 3449 emit_andimm(temp,~3,temp);
3450 emit_writeword_indexed(temp2,4,temp);
3451 set_jump_target(done0,(int)out);
3452 }
3453 if (opcode[i]==0x2D) { // SDR
3454 emit_testimm(temp,4);
3455 done0=(int)out;
3456 emit_jeq(0);
3457 emit_andimm(temp,~3,temp);
3458 emit_writeword_indexed(temp2,-4,temp);
57871462 3459 set_jump_target(done0,(int)out);
57871462 3460 }
535d208a 3461 if(!c||!memtarget)
3462 add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
57871462 3463 if(!using_tlb) {
535d208a 3464 #ifdef RAM_OFFSET
3465 int map=get_reg(i_regs->regmap,ROREG);
3466 if(map<0) map=HOST_TEMPREG;
3467 gen_orig_addr_w(temp,map);
3468 #else
57871462 3469 emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
535d208a 3470 #endif
57871462 3471 #if defined(HOST_IMM8)
3472 int ir=get_reg(i_regs->regmap,INVCP);
3473 assert(ir>=0);
3474 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3475 #else
3476 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3477 #endif
535d208a 3478 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3479 emit_callne(invalidate_addr_reg[temp]);
3480 #else
57871462 3481 jaddr2=(int)out;
3482 emit_jne(0);
3483 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
535d208a 3484 #endif
57871462 3485 }
3486 /*
3487 emit_pusha();
3488 //save_regs(0x100f);
3489 emit_readword((int)&last_count,ECX);
3490 if(get_reg(i_regs->regmap,CCREG)<0)
3491 emit_loadreg(CCREG,HOST_CCREG);
3492 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3493 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3494 emit_writeword(HOST_CCREG,(int)&Count);
3495 emit_call((int)memdebug);
3496 emit_popa();
3497 //restore_regs(0x100f);
3498 /**/
3499}
3500
3501void c1ls_assemble(int i,struct regstat *i_regs)
3502{
3d624f89 3503#ifndef DISABLE_COP1
57871462 3504 int s,th,tl;
3505 int temp,ar;
3506 int map=-1;
3507 int offset;
3508 int c=0;
3509 int jaddr,jaddr2=0,jaddr3,type;
3510 int agr=AGEN1+(i&1);
3511 u_int hr,reglist=0;
3512 th=get_reg(i_regs->regmap,FTEMP|64);
3513 tl=get_reg(i_regs->regmap,FTEMP);
3514 s=get_reg(i_regs->regmap,rs1[i]);
3515 temp=get_reg(i_regs->regmap,agr);
3516 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3517 offset=imm[i];
3518 assert(tl>=0);
3519 assert(rs1[i]>0);
3520 assert(temp>=0);
3521 for(hr=0;hr<HOST_REGS;hr++) {
3522 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3523 }
3524 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3525 if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3526 {
3527 // Loads use a temporary register which we need to save
3528 reglist|=1<<temp;
3529 }
3530 if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3531 ar=temp;
3532 else // LWC1/LDC1
3533 ar=tl;
3534 //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3535 //else c=(i_regs->wasconst>>s)&1;
3536 if(s>=0) c=(i_regs->wasconst>>s)&1;
3537 // Check cop1 unusable
3538 if(!cop1_usable) {
3539 signed char rs=get_reg(i_regs->regmap,CSREG);
3540 assert(rs>=0);
3541 emit_testimm(rs,0x20000000);
3542 jaddr=(int)out;
3543 emit_jeq(0);
3544 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3545 cop1_usable=1;
3546 }
3547 if (opcode[i]==0x39) { // SWC1 (get float address)
3548 emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],tl);
3549 }
3550 if (opcode[i]==0x3D) { // SDC1 (get double address)
3551 emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],tl);
3552 }
3553 // Generate address + offset
3554 if(!using_tlb) {
3555 if(!c)
4cb76aa4 3556 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
57871462 3557 }
3558 else
3559 {
3560 map=get_reg(i_regs->regmap,TLREG);
3561 assert(map>=0);
3562 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3563 map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3564 }
3565 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3566 map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3567 }
3568 }
3569 if (opcode[i]==0x39) { // SWC1 (read float)
3570 emit_readword_indexed(0,tl,tl);
3571 }
3572 if (opcode[i]==0x3D) { // SDC1 (read double)
3573 emit_readword_indexed(4,tl,th);
3574 emit_readword_indexed(0,tl,tl);
3575 }
3576 if (opcode[i]==0x31) { // LWC1 (get target address)
3577 emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],temp);
3578 }
3579 if (opcode[i]==0x35) { // LDC1 (get target address)
3580 emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],temp);
3581 }
3582 if(!using_tlb) {
3583 if(!c) {
3584 jaddr2=(int)out;
3585 emit_jno(0);
3586 }
4cb76aa4 3587 else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
57871462 3588 jaddr2=(int)out;
3589 emit_jmp(0); // inline_readstub/inline_writestub? Very rare case
3590 }
3591 #ifdef DESTRUCTIVE_SHIFT
3592 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3593 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3594 }
3595 #endif
3596 }else{
3597 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3598 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3599 }
3600 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3601 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3602 }
3603 }
3604 if (opcode[i]==0x31) { // LWC1
3605 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3606 //gen_tlb_addr_r(ar,map);
3607 //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3608 #ifdef HOST_IMM_ADDR32
3609 if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3610 else
3611 #endif
3612 emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3613 type=LOADW_STUB;
3614 }
3615 if (opcode[i]==0x35) { // LDC1
3616 assert(th>=0);
3617 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3618 //gen_tlb_addr_r(ar,map);
3619 //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3620 //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3621 #ifdef HOST_IMM_ADDR32
3622 if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3623 else
3624 #endif
3625 emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3626 type=LOADD_STUB;
3627 }
3628 if (opcode[i]==0x39) { // SWC1
3629 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3630 emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3631 type=STOREW_STUB;
3632 }
3633 if (opcode[i]==0x3D) { // SDC1
3634 assert(th>=0);
3635 //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3636 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3637 emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3638 type=STORED_STUB;
3639 }
3640 if(!using_tlb) {
3641 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3642 #ifndef DESTRUCTIVE_SHIFT
3643 temp=offset||c||s<0?ar:s;
3644 #endif
3645 #if defined(HOST_IMM8)
3646 int ir=get_reg(i_regs->regmap,INVCP);
3647 assert(ir>=0);
3648 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3649 #else
3650 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3651 #endif
0bbd1454 3652 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3653 emit_callne(invalidate_addr_reg[temp]);
3654 #else
57871462 3655 jaddr3=(int)out;
3656 emit_jne(0);
3657 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
0bbd1454 3658 #endif
57871462 3659 }
3660 }
3661 if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3662 if (opcode[i]==0x31) { // LWC1 (write float)
3663 emit_writeword_indexed(tl,0,temp);
3664 }
3665 if (opcode[i]==0x35) { // LDC1 (write double)
3666 emit_writeword_indexed(th,4,temp);
3667 emit_writeword_indexed(tl,0,temp);
3668 }
3669 //if(opcode[i]==0x39)
3670 /*if(opcode[i]==0x39||opcode[i]==0x31)
3671 {
3672 emit_pusha();
3673 emit_readword((int)&last_count,ECX);
3674 if(get_reg(i_regs->regmap,CCREG)<0)
3675 emit_loadreg(CCREG,HOST_CCREG);
3676 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3677 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3678 emit_writeword(HOST_CCREG,(int)&Count);
3679 emit_call((int)memdebug);
3680 emit_popa();
3681 }/**/
3d624f89 3682#else
3683 cop1_unusable(i, i_regs);
3684#endif
57871462 3685}
3686
b9b61529 3687void c2ls_assemble(int i,struct regstat *i_regs)
3688{
3689 int s,tl;
3690 int ar;
3691 int offset;
1fd1aceb 3692 int memtarget=0,c=0;
b9b61529 3693 int jaddr,jaddr2=0,jaddr3,type;
3694 int agr=AGEN1+(i&1);
3695 u_int hr,reglist=0;
3696 u_int copr=(source[i]>>16)&0x1f;
3697 s=get_reg(i_regs->regmap,rs1[i]);
3698 tl=get_reg(i_regs->regmap,FTEMP);
3699 offset=imm[i];
3700 assert(rs1[i]>0);
3701 assert(tl>=0);
3702 assert(!using_tlb);
3703
3704 for(hr=0;hr<HOST_REGS;hr++) {
3705 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3706 }
3707 if(i_regs->regmap[HOST_CCREG]==CCREG)
3708 reglist&=~(1<<HOST_CCREG);
3709
3710 // get the address
3711 if (opcode[i]==0x3a) { // SWC2
3712 ar=get_reg(i_regs->regmap,agr);
3713 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3714 reglist|=1<<ar;
3715 } else { // LWC2
3716 ar=tl;
3717 }
1fd1aceb 3718 if(s>=0) c=(i_regs->wasconst>>s)&1;
3719 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
b9b61529 3720 if (!offset&&!c&&s>=0) ar=s;
3721 assert(ar>=0);
3722
3723 if (opcode[i]==0x3a) { // SWC2
3724 cop2_get_dreg(copr,tl,HOST_TEMPREG);
1fd1aceb 3725 type=STOREW_STUB;
b9b61529 3726 }
1fd1aceb 3727 else
b9b61529 3728 type=LOADW_STUB;
1fd1aceb 3729
3730 if(c&&!memtarget) {
3731 jaddr2=(int)out;
3732 emit_jmp(0); // inline_readstub/inline_writestub?
b9b61529 3733 }
1fd1aceb 3734 else {
3735 if(!c) {
3736 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3737 jaddr2=(int)out;
3738 emit_jno(0);
3739 }
3740 if (opcode[i]==0x32) { // LWC2
3741 #ifdef HOST_IMM_ADDR32
3742 if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3743 else
3744 #endif
3745 emit_readword_indexed(0,ar,tl);
3746 }
3747 if (opcode[i]==0x3a) { // SWC2
3748 #ifdef DESTRUCTIVE_SHIFT
3749 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3750 #endif
3751 emit_writeword_indexed(tl,0,ar);
3752 }
b9b61529 3753 }
3754 if(jaddr2)
3755 add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3756 if (opcode[i]==0x3a) { // SWC2
3757#if defined(HOST_IMM8)
3758 int ir=get_reg(i_regs->regmap,INVCP);
3759 assert(ir>=0);
3760 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3761#else
3762 emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3763#endif
0bbd1454 3764 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3765 emit_callne(invalidate_addr_reg[ar]);
3766 #else
b9b61529 3767 jaddr3=(int)out;
3768 emit_jne(0);
3769 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
0bbd1454 3770 #endif
b9b61529 3771 }
3772 if (opcode[i]==0x32) { // LWC2
3773 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3774 }
3775}
3776
57871462 3777#ifndef multdiv_assemble
3778void multdiv_assemble(int i,struct regstat *i_regs)
3779{
3780 printf("Need multdiv_assemble for this architecture.\n");
3781 exit(1);
3782}
3783#endif
3784
3785void mov_assemble(int i,struct regstat *i_regs)
3786{
3787 //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3788 //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
57871462 3789 if(rt1[i]) {
3790 signed char sh,sl,th,tl;
3791 th=get_reg(i_regs->regmap,rt1[i]|64);
3792 tl=get_reg(i_regs->regmap,rt1[i]);
3793 //assert(tl>=0);
3794 if(tl>=0) {
3795 sh=get_reg(i_regs->regmap,rs1[i]|64);
3796 sl=get_reg(i_regs->regmap,rs1[i]);
3797 if(sl>=0) emit_mov(sl,tl);
3798 else emit_loadreg(rs1[i],tl);
3799 if(th>=0) {
3800 if(sh>=0) emit_mov(sh,th);
3801 else emit_loadreg(rs1[i]|64,th);
3802 }
3803 }
3804 }
3805}
3806
3807#ifndef fconv_assemble
3808void fconv_assemble(int i,struct regstat *i_regs)
3809{
3810 printf("Need fconv_assemble for this architecture.\n");
3811 exit(1);
3812}
3813#endif
3814
3815#if 0
3816void float_assemble(int i,struct regstat *i_regs)
3817{
3818 printf("Need float_assemble for this architecture.\n");
3819 exit(1);
3820}
3821#endif
3822
3823void syscall_assemble(int i,struct regstat *i_regs)
3824{
3825 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3826 assert(ccreg==HOST_CCREG);
3827 assert(!is_delayslot);
3828 emit_movimm(start+i*4,EAX); // Get PC
3829 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
7139f3c8 3830 emit_jmp((int)jump_syscall_hle); // XXX
3831}
3832
3833void hlecall_assemble(int i,struct regstat *i_regs)
3834{
3835 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3836 assert(ccreg==HOST_CCREG);
3837 assert(!is_delayslot);
3838 emit_movimm(start+i*4+4,0); // Get PC
67ba0fb4 3839 emit_movimm((int)psxHLEt[source[i]&7],1);
7139f3c8 3840 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // XXX
67ba0fb4 3841 emit_jmp((int)jump_hlecall);
57871462 3842}
3843
1e973cb0 3844void intcall_assemble(int i,struct regstat *i_regs)
3845{
3846 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3847 assert(ccreg==HOST_CCREG);
3848 assert(!is_delayslot);
3849 emit_movimm(start+i*4,0); // Get PC
3850 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3851 emit_jmp((int)jump_intcall);
3852}
3853
57871462 3854void ds_assemble(int i,struct regstat *i_regs)
3855{
3856 is_delayslot=1;
3857 switch(itype[i]) {
3858 case ALU:
3859 alu_assemble(i,i_regs);break;
3860 case IMM16:
3861 imm16_assemble(i,i_regs);break;
3862 case SHIFT:
3863 shift_assemble(i,i_regs);break;
3864 case SHIFTIMM:
3865 shiftimm_assemble(i,i_regs);break;
3866 case LOAD:
3867 load_assemble(i,i_regs);break;
3868 case LOADLR:
3869 loadlr_assemble(i,i_regs);break;
3870 case STORE:
3871 store_assemble(i,i_regs);break;
3872 case STORELR:
3873 storelr_assemble(i,i_regs);break;
3874 case COP0:
3875 cop0_assemble(i,i_regs);break;
3876 case COP1:
3877 cop1_assemble(i,i_regs);break;
3878 case C1LS:
3879 c1ls_assemble(i,i_regs);break;
b9b61529 3880 case COP2:
3881 cop2_assemble(i,i_regs);break;
3882 case C2LS:
3883 c2ls_assemble(i,i_regs);break;
3884 case C2OP:
3885 c2op_assemble(i,i_regs);break;
57871462 3886 case FCONV:
3887 fconv_assemble(i,i_regs);break;
3888 case FLOAT:
3889 float_assemble(i,i_regs);break;
3890 case FCOMP:
3891 fcomp_assemble(i,i_regs);break;
3892 case MULTDIV:
3893 multdiv_assemble(i,i_regs);break;
3894 case MOV:
3895 mov_assemble(i,i_regs);break;
3896 case SYSCALL:
7139f3c8 3897 case HLECALL:
1e973cb0 3898 case INTCALL:
57871462 3899 case SPAN:
3900 case UJUMP:
3901 case RJUMP:
3902 case CJUMP:
3903 case SJUMP:
3904 case FJUMP:
3905 printf("Jump in the delay slot. This is probably a bug.\n");
3906 }
3907 is_delayslot=0;
3908}
3909
3910// Is the branch target a valid internal jump?
3911int internal_branch(uint64_t i_is32,int addr)
3912{
3913 if(addr&1) return 0; // Indirect (register) jump
3914 if(addr>=start && addr<start+slen*4-4)
3915 {
3916 int t=(addr-start)>>2;
3917 // Delay slots are not valid branch targets
3918 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
3919 // 64 -> 32 bit transition requires a recompile
3920 /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
3921 {
3922 if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
3923 else printf("optimizable: yes\n");
3924 }*/
3925 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
a28c6ce8 3926#ifndef FORCE32
57871462 3927 if(requires_32bit[t]&~i_is32) return 0;
a28c6ce8 3928 else
3929#endif
3930 return 1;
57871462 3931 }
3932 return 0;
3933}
3934
3935#ifndef wb_invalidate
3936void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
3937 uint64_t u,uint64_t uu)
3938{
3939 int hr;
3940 for(hr=0;hr<HOST_REGS;hr++) {
3941 if(hr!=EXCLUDE_REG) {
3942 if(pre[hr]!=entry[hr]) {
3943 if(pre[hr]>=0) {
3944 if((dirty>>hr)&1) {
3945 if(get_reg(entry,pre[hr])<0) {
3946 if(pre[hr]<64) {
3947 if(!((u>>pre[hr])&1)) {
3948 emit_storereg(pre[hr],hr);
3949 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
3950 emit_sarimm(hr,31,hr);
3951 emit_storereg(pre[hr]|64,hr);
3952 }
3953 }
3954 }else{
3955 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
3956 emit_storereg(pre[hr],hr);
3957 }
3958 }
3959 }
3960 }
3961 }
3962 }
3963 }
3964 }
3965 // Move from one register to another (no writeback)
3966 for(hr=0;hr<HOST_REGS;hr++) {
3967 if(hr!=EXCLUDE_REG) {
3968 if(pre[hr]!=entry[hr]) {
3969 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
3970 int nr;
3971 if((nr=get_reg(entry,pre[hr]))>=0) {
3972 emit_mov(hr,nr);
3973 }
3974 }
3975 }
3976 }
3977 }
3978}
3979#endif
3980
3981// Load the specified registers
3982// This only loads the registers given as arguments because
3983// we don't want to load things that will be overwritten
3984void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
3985{
3986 int hr;
3987 // Load 32-bit regs
3988 for(hr=0;hr<HOST_REGS;hr++) {
3989 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
3990 if(entry[hr]!=regmap[hr]) {
3991 if(regmap[hr]==rs1||regmap[hr]==rs2)
3992 {
3993 if(regmap[hr]==0) {
3994 emit_zeroreg(hr);
3995 }
3996 else
3997 {
3998 emit_loadreg(regmap[hr],hr);
3999 }
4000 }
4001 }
4002 }
4003 }
4004 //Load 64-bit regs
4005 for(hr=0;hr<HOST_REGS;hr++) {
4006 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4007 if(entry[hr]!=regmap[hr]) {
4008 if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
4009 {
4010 assert(regmap[hr]!=64);
4011 if((is32>>(regmap[hr]&63))&1) {
4012 int lr=get_reg(regmap,regmap[hr]-64);
4013 if(lr>=0)
4014 emit_sarimm(lr,31,hr);
4015 else
4016 emit_loadreg(regmap[hr],hr);
4017 }
4018 else
4019 {
4020 emit_loadreg(regmap[hr],hr);
4021 }
4022 }
4023 }
4024 }
4025 }
4026}
4027
4028// Load registers prior to the start of a loop
4029// so that they are not loaded within the loop
4030static void loop_preload(signed char pre[],signed char entry[])
4031{
4032 int hr;
4033 for(hr=0;hr<HOST_REGS;hr++) {
4034 if(hr!=EXCLUDE_REG) {
4035 if(pre[hr]!=entry[hr]) {
4036 if(entry[hr]>=0) {
4037 if(get_reg(pre,entry[hr])<0) {
4038 assem_debug("loop preload:\n");
4039 //printf("loop preload: %d\n",hr);
4040 if(entry[hr]==0) {
4041 emit_zeroreg(hr);
4042 }
4043 else if(entry[hr]<TEMPREG)
4044 {
4045 emit_loadreg(entry[hr],hr);
4046 }
4047 else if(entry[hr]-64<TEMPREG)
4048 {
4049 emit_loadreg(entry[hr],hr);
4050 }
4051 }
4052 }
4053 }
4054 }
4055 }
4056}
4057
4058// Generate address for load/store instruction
b9b61529 4059// goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
57871462 4060void address_generation(int i,struct regstat *i_regs,signed char entry[])
4061{
b9b61529 4062 if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
57871462 4063 int ra;
4064 int agr=AGEN1+(i&1);
4065 int mgr=MGEN1+(i&1);
4066 if(itype[i]==LOAD) {
4067 ra=get_reg(i_regs->regmap,rt1[i]);
535d208a 4068 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4069 assert(ra>=0);
57871462 4070 }
4071 if(itype[i]==LOADLR) {
4072 ra=get_reg(i_regs->regmap,FTEMP);
4073 }
4074 if(itype[i]==STORE||itype[i]==STORELR) {
4075 ra=get_reg(i_regs->regmap,agr);
4076 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4077 }
b9b61529 4078 if(itype[i]==C1LS||itype[i]==C2LS) {
4079 if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
57871462 4080 ra=get_reg(i_regs->regmap,FTEMP);
1fd1aceb 4081 else { // SWC1/SDC1/SWC2/SDC2
57871462 4082 ra=get_reg(i_regs->regmap,agr);
4083 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4084 }
4085 }
4086 int rs=get_reg(i_regs->regmap,rs1[i]);
4087 int rm=get_reg(i_regs->regmap,TLREG);
4088 if(ra>=0) {
4089 int offset=imm[i];
4090 int c=(i_regs->wasconst>>rs)&1;
4091 if(rs1[i]==0) {
4092 // Using r0 as a base address
4093 /*if(rm>=0) {
4094 if(!entry||entry[rm]!=mgr) {
4095 generate_map_const(offset,rm);
4096 } // else did it in the previous cycle
4097 }*/
4098 if(!entry||entry[ra]!=agr) {
4099 if (opcode[i]==0x22||opcode[i]==0x26) {
4100 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4101 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4102 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4103 }else{
4104 emit_movimm(offset,ra);
4105 }
4106 } // else did it in the previous cycle
4107 }
4108 else if(rs<0) {
4109 if(!entry||entry[ra]!=rs1[i])
4110 emit_loadreg(rs1[i],ra);
4111 //if(!entry||entry[ra]!=rs1[i])
4112 // printf("poor load scheduling!\n");
4113 }
4114 else if(c) {
4115 if(rm>=0) {
4116 if(!entry||entry[rm]!=mgr) {
b9b61529 4117 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
57871462 4118 // Stores to memory go thru the mapper to detect self-modifying
4119 // code, loads don't.
4120 if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
4cb76aa4 4121 (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
57871462 4122 generate_map_const(constmap[i][rs]+offset,rm);
4123 }else{
4124 if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
4125 generate_map_const(constmap[i][rs]+offset,rm);
4126 }
4127 }
4128 }
4129 if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
4130 if(!entry||entry[ra]!=agr) {
4131 if (opcode[i]==0x22||opcode[i]==0x26) {
4132 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4133 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4134 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4135 }else{
4136 #ifdef HOST_IMM_ADDR32
b9b61529 4137 if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
57871462 4138 (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4139 #endif
4140 emit_movimm(constmap[i][rs]+offset,ra);
4141 }
4142 } // else did it in the previous cycle
4143 } // else load_consts already did it
4144 }
4145 if(offset&&!c&&rs1[i]) {
4146 if(rs>=0) {
4147 emit_addimm(rs,offset,ra);
4148 }else{
4149 emit_addimm(ra,offset,ra);
4150 }
4151 }
4152 }
4153 }
4154 // Preload constants for next instruction
b9b61529 4155 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
57871462 4156 int agr,ra;
4157 #ifndef HOST_IMM_ADDR32
4158 // Mapper entry
4159 agr=MGEN1+((i+1)&1);
4160 ra=get_reg(i_regs->regmap,agr);
4161 if(ra>=0) {
4162 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4163 int offset=imm[i+1];
4164 int c=(regs[i+1].wasconst>>rs)&1;
4165 if(c) {
b9b61529 4166 if(itype[i+1]==STORE||itype[i+1]==STORELR
4167 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
57871462 4168 // Stores to memory go thru the mapper to detect self-modifying
4169 // code, loads don't.
4170 if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4cb76aa4 4171 (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
57871462 4172 generate_map_const(constmap[i+1][rs]+offset,ra);
4173 }else{
4174 if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4175 generate_map_const(constmap[i+1][rs]+offset,ra);
4176 }
4177 }
4178 /*else if(rs1[i]==0) {
4179 generate_map_const(offset,ra);
4180 }*/
4181 }
4182 #endif
4183 // Actual address
4184 agr=AGEN1+((i+1)&1);
4185 ra=get_reg(i_regs->regmap,agr);
4186 if(ra>=0) {
4187 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4188 int offset=imm[i+1];
4189 int c=(regs[i+1].wasconst>>rs)&1;
4190 if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4191 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4192 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4193 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4194 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4195 }else{
4196 #ifdef HOST_IMM_ADDR32
b9b61529 4197 if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
57871462 4198 (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4199 #endif
4200 emit_movimm(constmap[i+1][rs]+offset,ra);
4201 }
4202 }
4203 else if(rs1[i+1]==0) {
4204 // Using r0 as a base address
4205 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4206 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4207 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4208 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4209 }else{
4210 emit_movimm(offset,ra);
4211 }
4212 }
4213 }
4214 }
4215}
4216
4217int get_final_value(int hr, int i, int *value)
4218{
4219 int reg=regs[i].regmap[hr];
4220 while(i<slen-1) {
4221 if(regs[i+1].regmap[hr]!=reg) break;
4222 if(!((regs[i+1].isconst>>hr)&1)) break;
4223 if(bt[i+1]) break;
4224 i++;
4225 }
4226 if(i<slen-1) {
4227 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4228 *value=constmap[i][hr];
4229 return 1;
4230 }
4231 if(!bt[i+1]) {
4232 if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4233 // Load in delay slot, out-of-order execution
4234 if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4235 {
4236 #ifdef HOST_IMM_ADDR32
4237 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4238 #endif
4239 // Precompute load address
4240 *value=constmap[i][hr]+imm[i+2];
4241 return 1;
4242 }
4243 }
4244 if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4245 {
4246 #ifdef HOST_IMM_ADDR32
4247 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4248 #endif
4249 // Precompute load address
4250 *value=constmap[i][hr]+imm[i+1];
4251 //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4252 return 1;
4253 }
4254 }
4255 }
4256 *value=constmap[i][hr];
4257 //printf("c=%x\n",(int)constmap[i][hr]);
4258 if(i==slen-1) return 1;
4259 if(reg<64) {
4260 return !((unneeded_reg[i+1]>>reg)&1);
4261 }else{
4262 return !((unneeded_reg_upper[i+1]>>reg)&1);
4263 }
4264}
4265
4266// Load registers with known constants
4267void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4268{
4269 int hr;
4270 // Load 32-bit regs
4271 for(hr=0;hr<HOST_REGS;hr++) {
4272 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4273 //if(entry[hr]!=regmap[hr]) {
4274 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4275 if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4276 int value;
4277 if(get_final_value(hr,i,&value)) {
4278 if(value==0) {
4279 emit_zeroreg(hr);
4280 }
4281 else {
4282 emit_movimm(value,hr);
4283 }
4284 }
4285 }
4286 }
4287 }
4288 }
4289 // Load 64-bit regs
4290 for(hr=0;hr<HOST_REGS;hr++) {
4291 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4292 //if(entry[hr]!=regmap[hr]) {
4293 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4294 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4295 if((is32>>(regmap[hr]&63))&1) {
4296 int lr=get_reg(regmap,regmap[hr]-64);
4297 assert(lr>=0);
4298 emit_sarimm(lr,31,hr);
4299 }
4300 else
4301 {
4302 int value;
4303 if(get_final_value(hr,i,&value)) {
4304 if(value==0) {
4305 emit_zeroreg(hr);
4306 }
4307 else {
4308 emit_movimm(value,hr);
4309 }
4310 }
4311 }
4312 }
4313 }
4314 }
4315 }
4316}
4317void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4318{
4319 int hr;
4320 // Load 32-bit regs
4321 for(hr=0;hr<HOST_REGS;hr++) {
4322 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4323 if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4324 int value=constmap[i][hr];
4325 if(value==0) {
4326 emit_zeroreg(hr);
4327 }
4328 else {
4329 emit_movimm(value,hr);
4330 }
4331 }
4332 }
4333 }
4334 // Load 64-bit regs
4335 for(hr=0;hr<HOST_REGS;hr++) {
4336 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4337 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4338 if((is32>>(regmap[hr]&63))&1) {
4339 int lr=get_reg(regmap,regmap[hr]-64);
4340 assert(lr>=0);
4341 emit_sarimm(lr,31,hr);
4342 }
4343 else
4344 {
4345 int value=constmap[i][hr];
4346 if(value==0) {
4347 emit_zeroreg(hr);
4348 }
4349 else {
4350 emit_movimm(value,hr);
4351 }
4352 }
4353 }
4354 }
4355 }
4356}
4357
4358// Write out all dirty registers (except cycle count)
4359void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4360{
4361 int hr;
4362 for(hr=0;hr<HOST_REGS;hr++) {
4363 if(hr!=EXCLUDE_REG) {
4364 if(i_regmap[hr]>0) {
4365 if(i_regmap[hr]!=CCREG) {
4366 if((i_dirty>>hr)&1) {
4367 if(i_regmap[hr]<64) {
4368 emit_storereg(i_regmap[hr],hr);
24385cae 4369#ifndef FORCE32
57871462 4370 if( ((i_is32>>i_regmap[hr])&1) ) {
4371 #ifdef DESTRUCTIVE_WRITEBACK
4372 emit_sarimm(hr,31,hr);
4373 emit_storereg(i_regmap[hr]|64,hr);
4374 #else
4375 emit_sarimm(hr,31,HOST_TEMPREG);
4376 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4377 #endif
4378 }
24385cae 4379#endif
57871462 4380 }else{
4381 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4382 emit_storereg(i_regmap[hr],hr);
4383 }
4384 }
4385 }
4386 }
4387 }
4388 }
4389 }
4390}
4391// Write out dirty registers that we need to reload (pair with load_needed_regs)
4392// This writes the registers not written by store_regs_bt
4393void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4394{
4395 int hr;
4396 int t=(addr-start)>>2;
4397 for(hr=0;hr<HOST_REGS;hr++) {
4398 if(hr!=EXCLUDE_REG) {
4399 if(i_regmap[hr]>0) {
4400 if(i_regmap[hr]!=CCREG) {
4401 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4402 if((i_dirty>>hr)&1) {
4403 if(i_regmap[hr]<64) {
4404 emit_storereg(i_regmap[hr],hr);
24385cae 4405#ifndef FORCE32
57871462 4406 if( ((i_is32>>i_regmap[hr])&1) ) {
4407 #ifdef DESTRUCTIVE_WRITEBACK
4408 emit_sarimm(hr,31,hr);
4409 emit_storereg(i_regmap[hr]|64,hr);
4410 #else
4411 emit_sarimm(hr,31,HOST_TEMPREG);
4412 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4413 #endif
4414 }
24385cae 4415#endif
57871462 4416 }else{
4417 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4418 emit_storereg(i_regmap[hr],hr);
4419 }
4420 }
4421 }
4422 }
4423 }
4424 }
4425 }
4426 }
4427}
4428
4429// Load all registers (except cycle count)
4430void load_all_regs(signed char i_regmap[])
4431{
4432 int hr;
4433 for(hr=0;hr<HOST_REGS;hr++) {
4434 if(hr!=EXCLUDE_REG) {
4435 if(i_regmap[hr]==0) {
4436 emit_zeroreg(hr);
4437 }
4438 else
4439 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG)
4440 {
4441 emit_loadreg(i_regmap[hr],hr);
4442 }
4443 }
4444 }
4445}
4446
4447// Load all current registers also needed by next instruction
4448void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4449{
4450 int hr;
4451 for(hr=0;hr<HOST_REGS;hr++) {
4452 if(hr!=EXCLUDE_REG) {
4453 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4454 if(i_regmap[hr]==0) {
4455 emit_zeroreg(hr);
4456 }
4457 else
4458 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG)
4459 {
4460 emit_loadreg(i_regmap[hr],hr);
4461 }
4462 }
4463 }
4464 }
4465}
4466
4467// Load all regs, storing cycle count if necessary
4468void load_regs_entry(int t)
4469{
4470 int hr;
4471 if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER,HOST_CCREG);
4472 else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t]*CLOCK_DIVIDER,HOST_CCREG);
4473 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4474 emit_storereg(CCREG,HOST_CCREG);
4475 }
4476 // Load 32-bit regs
4477 for(hr=0;hr<HOST_REGS;hr++) {
4478 if(regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<64) {
4479 if(regs[t].regmap_entry[hr]==0) {
4480 emit_zeroreg(hr);
4481 }
4482 else if(regs[t].regmap_entry[hr]!=CCREG)
4483 {
4484 emit_loadreg(regs[t].regmap_entry[hr],hr);
4485 }
4486 }
4487 }
4488 // Load 64-bit regs
4489 for(hr=0;hr<HOST_REGS;hr++) {
4490 if(regs[t].regmap_entry[hr]>=64) {
4491 assert(regs[t].regmap_entry[hr]!=64);
4492 if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4493 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4494 if(lr<0) {
4495 emit_loadreg(regs[t].regmap_entry[hr],hr);
4496 }
4497 else
4498 {
4499 emit_sarimm(lr,31,hr);
4500 }
4501 }
4502 else
4503 {
4504 emit_loadreg(regs[t].regmap_entry[hr],hr);
4505 }
4506 }
4507 }
4508}
4509
4510// Store dirty registers prior to branch
4511void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4512{
4513 if(internal_branch(i_is32,addr))
4514 {
4515 int t=(addr-start)>>2;
4516 int hr;
4517 for(hr=0;hr<HOST_REGS;hr++) {
4518 if(hr!=EXCLUDE_REG) {
4519 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4520 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4521 if((i_dirty>>hr)&1) {
4522 if(i_regmap[hr]<64) {
4523 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4524 emit_storereg(i_regmap[hr],hr);
4525 if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4526 #ifdef DESTRUCTIVE_WRITEBACK
4527 emit_sarimm(hr,31,hr);
4528 emit_storereg(i_regmap[hr]|64,hr);
4529 #else
4530 emit_sarimm(hr,31,HOST_TEMPREG);
4531 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4532 #endif
4533 }
4534 }
4535 }else{
4536 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4537 emit_storereg(i_regmap[hr],hr);
4538 }
4539 }
4540 }
4541 }
4542 }
4543 }
4544 }
4545 }
4546 else
4547 {
4548 // Branch out of this block, write out all dirty regs
4549 wb_dirtys(i_regmap,i_is32,i_dirty);
4550 }
4551}
4552
4553// Load all needed registers for branch target
4554void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4555{
4556 //if(addr>=start && addr<(start+slen*4))
4557 if(internal_branch(i_is32,addr))
4558 {
4559 int t=(addr-start)>>2;
4560 int hr;
4561 // Store the cycle count before loading something else
4562 if(i_regmap[HOST_CCREG]!=CCREG) {
4563 assert(i_regmap[HOST_CCREG]==-1);
4564 }
4565 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4566 emit_storereg(CCREG,HOST_CCREG);
4567 }
4568 // Load 32-bit regs
4569 for(hr=0;hr<HOST_REGS;hr++) {
4570 if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<64) {
4571 #ifdef DESTRUCTIVE_WRITEBACK
4572 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4573 #else
4574 if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4575 #endif
4576 if(regs[t].regmap_entry[hr]==0) {
4577 emit_zeroreg(hr);
4578 }
4579 else if(regs[t].regmap_entry[hr]!=CCREG)
4580 {
4581 emit_loadreg(regs[t].regmap_entry[hr],hr);
4582 }
4583 }
4584 }
4585 }
4586 //Load 64-bit regs
4587 for(hr=0;hr<HOST_REGS;hr++) {
4588 if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=64) {
4589 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4590 assert(regs[t].regmap_entry[hr]!=64);
4591 if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4592 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4593 if(lr<0) {
4594 emit_loadreg(regs[t].regmap_entry[hr],hr);
4595 }
4596 else
4597 {
4598 emit_sarimm(lr,31,hr);
4599 }
4600 }
4601 else
4602 {
4603 emit_loadreg(regs[t].regmap_entry[hr],hr);
4604 }
4605 }
4606 else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4607 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4608 assert(lr>=0);
4609 emit_sarimm(lr,31,hr);
4610 }
4611 }
4612 }
4613 }
4614}
4615
4616int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4617{
4618 if(addr>=start && addr<start+slen*4-4)
4619 {
4620 int t=(addr-start)>>2;
4621 int hr;
4622 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4623 for(hr=0;hr<HOST_REGS;hr++)
4624 {
4625 if(hr!=EXCLUDE_REG)
4626 {
4627 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4628 {
4629 if(regs[t].regmap_entry[hr]!=-1)
4630 {
4631 return 0;
4632 }
4633 else
4634 if((i_dirty>>hr)&1)
4635 {
4636 if(i_regmap[hr]<64)
4637 {
4638 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4639 return 0;
4640 }
4641 else
4642 {
4643 if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4644 return 0;
4645 }
4646 }
4647 }
4648 else // Same register but is it 32-bit or dirty?
4649 if(i_regmap[hr]>=0)
4650 {
4651 if(!((regs[t].dirty>>hr)&1))
4652 {
4653 if((i_dirty>>hr)&1)
4654 {
4655 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4656 {
4657 //printf("%x: dirty no match\n",addr);
4658 return 0;
4659 }
4660 }
4661 }
4662 if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4663 {
4664 //printf("%x: is32 no match\n",addr);
4665 return 0;
4666 }
4667 }
4668 }
4669 }
4670 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
a28c6ce8 4671#ifndef FORCE32
57871462 4672 if(requires_32bit[t]&~i_is32) return 0;
a28c6ce8 4673#endif
57871462 4674 // Delay slots are not valid branch targets
4675 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4676 // Delay slots require additional processing, so do not match
4677 if(is_ds[t]) return 0;
4678 }
4679 else
4680 {
4681 int hr;
4682 for(hr=0;hr<HOST_REGS;hr++)
4683 {
4684 if(hr!=EXCLUDE_REG)
4685 {
4686 if(i_regmap[hr]>=0)
4687 {
4688 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4689 {
4690 if((i_dirty>>hr)&1)
4691 {
4692 return 0;
4693 }
4694 }
4695 }
4696 }
4697 }
4698 }
4699 return 1;
4700}
4701
4702// Used when a branch jumps into the delay slot of another branch
4703void ds_assemble_entry(int i)
4704{
4705 int t=(ba[i]-start)>>2;
4706 if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4707 assem_debug("Assemble delay slot at %x\n",ba[i]);
4708 assem_debug("<->\n");
4709 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
4710 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4711 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4712 address_generation(t,&regs[t],regs[t].regmap_entry);
b9b61529 4713 if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
57871462 4714 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4715 cop1_usable=0;
4716 is_delayslot=0;
4717 switch(itype[t]) {
4718 case ALU:
4719 alu_assemble(t,&regs[t]);break;
4720 case IMM16:
4721 imm16_assemble(t,&regs[t]);break;
4722 case SHIFT:
4723 shift_assemble(t,&regs[t]);break;
4724 case SHIFTIMM:
4725 shiftimm_assemble(t,&regs[t]);break;
4726 case LOAD:
4727 load_assemble(t,&regs[t]);break;
4728 case LOADLR:
4729 loadlr_assemble(t,&regs[t]);break;
4730 case STORE:
4731 store_assemble(t,&regs[t]);break;
4732 case STORELR:
4733 storelr_assemble(t,&regs[t]);break;
4734 case COP0:
4735 cop0_assemble(t,&regs[t]);break;
4736 case COP1:
4737 cop1_assemble(t,&regs[t]);break;
4738 case C1LS:
4739 c1ls_assemble(t,&regs[t]);break;
b9b61529 4740 case COP2:
4741 cop2_assemble(t,&regs[t]);break;
4742 case C2LS:
4743 c2ls_assemble(t,&regs[t]);break;
4744 case C2OP:
4745 c2op_assemble(t,&regs[t]);break;
57871462 4746 case FCONV:
4747 fconv_assemble(t,&regs[t]);break;
4748 case FLOAT:
4749 float_assemble(t,&regs[t]);break;
4750 case FCOMP:
4751 fcomp_assemble(t,&regs[t]);break;
4752 case MULTDIV:
4753 multdiv_assemble(t,&regs[t]);break;
4754 case MOV:
4755 mov_assemble(t,&regs[t]);break;
4756 case SYSCALL:
7139f3c8 4757 case HLECALL:
1e973cb0 4758 case INTCALL:
57871462 4759 case SPAN:
4760 case UJUMP:
4761 case RJUMP:
4762 case CJUMP:
4763 case SJUMP:
4764 case FJUMP:
4765 printf("Jump in the delay slot. This is probably a bug.\n");
4766 }
4767 store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4768 load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4769 if(internal_branch(regs[t].is32,ba[i]+4))
4770 assem_debug("branch: internal\n");
4771 else
4772 assem_debug("branch: external\n");
4773 assert(internal_branch(regs[t].is32,ba[i]+4));
4774 add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4775 emit_jmp(0);
4776}
4777
4778void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4779{
4780 int count;
4781 int jaddr;
4782 int idle=0;
4783 if(itype[i]==RJUMP)
4784 {
4785 *adj=0;
4786 }
4787 //if(ba[i]>=start && ba[i]<(start+slen*4))
4788 if(internal_branch(branch_regs[i].is32,ba[i]))
4789 {
4790 int t=(ba[i]-start)>>2;
4791 if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4792 else *adj=ccadj[t];
4793 }
4794 else
4795 {
4796 *adj=0;
4797 }
4798 count=ccadj[i];
4799 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4800 // Idle loop
4801 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4802 idle=(int)out;
4803 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4804 emit_andimm(HOST_CCREG,3,HOST_CCREG);
4805 jaddr=(int)out;
4806 emit_jmp(0);
4807 }
4808 else if(*adj==0||invert) {
4809 emit_addimm_and_set_flags(CLOCK_DIVIDER*(count+2),HOST_CCREG);
4810 jaddr=(int)out;
4811 emit_jns(0);
4812 }
4813 else
4814 {
4815 emit_cmpimm(HOST_CCREG,-2*(count+2));
4816 jaddr=(int)out;
4817 emit_jns(0);
4818 }
4819 add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4820}
4821
4822void do_ccstub(int n)
4823{
4824 literal_pool(256);
4825 assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
4826 set_jump_target(stubs[n][1],(int)out);
4827 int i=stubs[n][4];
4828 if(stubs[n][6]==NULLDS) {
4829 // Delay slot instruction is nullified ("likely" branch)
4830 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4831 }
4832 else if(stubs[n][6]!=TAKEN) {
4833 wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4834 }
4835 else {
4836 if(internal_branch(branch_regs[i].is32,ba[i]))
4837 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4838 }
4839 if(stubs[n][5]!=-1)
4840 {
4841 // Save PC as return address
4842 emit_movimm(stubs[n][5],EAX);
4843 emit_writeword(EAX,(int)&pcaddr);
4844 }
4845 else
4846 {
4847 // Return address depends on which way the branch goes
4848 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
4849 {
4850 int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4851 int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4852 int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4853 int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4854 if(rs1[i]==0)
4855 {
4856 s1l=s2l;s1h=s2h;
4857 s2l=s2h=-1;
4858 }
4859 else if(rs2[i]==0)
4860 {
4861 s2l=s2h=-1;
4862 }
4863 if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
4864 s1h=s2h=-1;
4865 }
4866 assert(s1l>=0);
4867 #ifdef DESTRUCTIVE_WRITEBACK
4868 if(rs1[i]) {
4869 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
4870 emit_loadreg(rs1[i],s1l);
4871 }
4872 else {
4873 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
4874 emit_loadreg(rs2[i],s1l);
4875 }
4876 if(s2l>=0)
4877 if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
4878 emit_loadreg(rs2[i],s2l);
4879 #endif
4880 int hr=0;
4881 int addr,alt,ntaddr;
4882 while(hr<HOST_REGS)
4883 {
4884 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4885 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4886 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4887 {
4888 addr=hr++;break;
4889 }
4890 hr++;
4891 }
4892 while(hr<HOST_REGS)
4893 {
4894 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4895 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4896 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4897 {
4898 alt=hr++;break;
4899 }
4900 hr++;
4901 }
4902 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
4903 {
4904 while(hr<HOST_REGS)
4905 {
4906 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4907 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4908 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4909 {
4910 ntaddr=hr;break;
4911 }
4912 hr++;
4913 }
4914 assert(hr<HOST_REGS);
4915 }
4916 if((opcode[i]&0x2f)==4) // BEQ
4917 {
4918 #ifdef HAVE_CMOV_IMM
4919 if(s1h<0) {
4920 if(s2l>=0) emit_cmp(s1l,s2l);
4921 else emit_test(s1l,s1l);
4922 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
4923 }
4924 else
4925 #endif
4926 {
4927 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4928 if(s1h>=0) {
4929 if(s2h>=0) emit_cmp(s1h,s2h);
4930 else emit_test(s1h,s1h);
4931 emit_cmovne_reg(alt,addr);
4932 }
4933 if(s2l>=0) emit_cmp(s1l,s2l);
4934 else emit_test(s1l,s1l);
4935 emit_cmovne_reg(alt,addr);
4936 }
4937 }
4938 if((opcode[i]&0x2f)==5) // BNE
4939 {
4940 #ifdef HAVE_CMOV_IMM
4941 if(s1h<0) {
4942 if(s2l>=0) emit_cmp(s1l,s2l);
4943 else emit_test(s1l,s1l);
4944 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
4945 }
4946 else
4947 #endif
4948 {
4949 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
4950 if(s1h>=0) {
4951 if(s2h>=0) emit_cmp(s1h,s2h);
4952 else emit_test(s1h,s1h);
4953 emit_cmovne_reg(alt,addr);
4954 }
4955 if(s2l>=0) emit_cmp(s1l,s2l);
4956 else emit_test(s1l,s1l);
4957 emit_cmovne_reg(alt,addr);
4958 }
4959 }
4960 if((opcode[i]&0x2f)==6) // BLEZ
4961 {
4962 //emit_movimm(ba[i],alt);
4963 //emit_movimm(start+i*4+8,addr);
4964 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4965 emit_cmpimm(s1l,1);
4966 if(s1h>=0) emit_mov(addr,ntaddr);
4967 emit_cmovl_reg(alt,addr);
4968 if(s1h>=0) {
4969 emit_test(s1h,s1h);
4970 emit_cmovne_reg(ntaddr,addr);
4971 emit_cmovs_reg(alt,addr);
4972 }
4973 }
4974 if((opcode[i]&0x2f)==7) // BGTZ
4975 {
4976 //emit_movimm(ba[i],addr);
4977 //emit_movimm(start+i*4+8,ntaddr);
4978 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
4979 emit_cmpimm(s1l,1);
4980 if(s1h>=0) emit_mov(addr,alt);
4981 emit_cmovl_reg(ntaddr,addr);
4982 if(s1h>=0) {
4983 emit_test(s1h,s1h);
4984 emit_cmovne_reg(alt,addr);
4985 emit_cmovs_reg(ntaddr,addr);
4986 }
4987 }
4988 if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
4989 {
4990 //emit_movimm(ba[i],alt);
4991 //emit_movimm(start+i*4+8,addr);
4992 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4993 if(s1h>=0) emit_test(s1h,s1h);
4994 else emit_test(s1l,s1l);
4995 emit_cmovs_reg(alt,addr);
4996 }
4997 if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
4998 {
4999 //emit_movimm(ba[i],addr);
5000 //emit_movimm(start+i*4+8,alt);
5001 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5002 if(s1h>=0) emit_test(s1h,s1h);
5003 else emit_test(s1l,s1l);
5004 emit_cmovs_reg(alt,addr);
5005 }
5006 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
5007 if(source[i]&0x10000) // BC1T
5008 {
5009 //emit_movimm(ba[i],alt);
5010 //emit_movimm(start+i*4+8,addr);
5011 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5012 emit_testimm(s1l,0x800000);
5013 emit_cmovne_reg(alt,addr);
5014 }
5015 else // BC1F
5016 {
5017 //emit_movimm(ba[i],addr);
5018 //emit_movimm(start+i*4+8,alt);
5019 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5020 emit_testimm(s1l,0x800000);
5021 emit_cmovne_reg(alt,addr);
5022 }
5023 }
5024 emit_writeword(addr,(int)&pcaddr);
5025 }
5026 else
5027 if(itype[i]==RJUMP)
5028 {
5029 int r=get_reg(branch_regs[i].regmap,rs1[i]);
5030 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5031 r=get_reg(branch_regs[i].regmap,RTEMP);
5032 }
5033 emit_writeword(r,(int)&pcaddr);
5034 }
5035 else {printf("Unknown branch type in do_ccstub\n");exit(1);}
5036 }
5037 // Update cycle count
5038 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5039 if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
5040 emit_call((int)cc_interrupt);
5041 if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
5042 if(stubs[n][6]==TAKEN) {
5043 if(internal_branch(branch_regs[i].is32,ba[i]))
5044 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
5045 else if(itype[i]==RJUMP) {
5046 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5047 emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5048 else
5049 emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
5050 }
5051 }else if(stubs[n][6]==NOTTAKEN) {
5052 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5053 else load_all_regs(branch_regs[i].regmap);
5054 }else if(stubs[n][6]==NULLDS) {
5055 // Delay slot instruction is nullified ("likely" branch)
5056 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5057 else load_all_regs(regs[i].regmap);
5058 }else{
5059 load_all_regs(branch_regs[i].regmap);
5060 }
5061 emit_jmp(stubs[n][2]); // return address
5062
5063 /* This works but uses a lot of memory...
5064 emit_readword((int)&last_count,ECX);
5065 emit_add(HOST_CCREG,ECX,EAX);
5066 emit_writeword(EAX,(int)&Count);
5067 emit_call((int)gen_interupt);
5068 emit_readword((int)&Count,HOST_CCREG);
5069 emit_readword((int)&next_interupt,EAX);
5070 emit_readword((int)&pending_exception,EBX);
5071 emit_writeword(EAX,(int)&last_count);
5072 emit_sub(HOST_CCREG,EAX,HOST_CCREG);
5073 emit_test(EBX,EBX);
5074 int jne_instr=(int)out;
5075 emit_jne(0);
5076 if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
5077 load_all_regs(branch_regs[i].regmap);
5078 emit_jmp(stubs[n][2]); // return address
5079 set_jump_target(jne_instr,(int)out);
5080 emit_readword((int)&pcaddr,EAX);
5081 // Call get_addr_ht instead of doing the hash table here.
5082 // This code is executed infrequently and takes up a lot of space
5083 // so smaller is better.
5084 emit_storereg(CCREG,HOST_CCREG);
5085 emit_pushreg(EAX);
5086 emit_call((int)get_addr_ht);
5087 emit_loadreg(CCREG,HOST_CCREG);
5088 emit_addimm(ESP,4,ESP);
5089 emit_jmpreg(EAX);*/
5090}
5091
5092add_to_linker(int addr,int target,int ext)
5093{
5094 link_addr[linkcount][0]=addr;
5095 link_addr[linkcount][1]=target;
5096 link_addr[linkcount][2]=ext;
5097 linkcount++;
5098}
5099
5100void ujump_assemble(int i,struct regstat *i_regs)
5101{
5102 signed char *i_regmap=i_regs->regmap;
5103 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5104 address_generation(i+1,i_regs,regs[i].regmap_entry);
5105 #ifdef REG_PREFETCH
5106 int temp=get_reg(branch_regs[i].regmap,PTEMP);
5107 if(rt1[i]==31&&temp>=0)
5108 {
5109 int return_address=start+i*4+8;
5110 if(get_reg(branch_regs[i].regmap,31)>0)
5111 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5112 }
5113 #endif
5114 ds_assemble(i+1,i_regs);
5115 uint64_t bc_unneeded=branch_regs[i].u;
5116 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5117 bc_unneeded|=1|(1LL<<rt1[i]);
5118 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5119 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5120 bc_unneeded,bc_unneeded_upper);
5121 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5122 if(rt1[i]==31) {
5123 int rt;
5124 unsigned int return_address;
5125 assert(rt1[i+1]!=31);
5126 assert(rt2[i+1]!=31);
5127 rt=get_reg(branch_regs[i].regmap,31);
5128 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5129 //assert(rt>=0);
5130 return_address=start+i*4+8;
5131 if(rt>=0) {
5132 #ifdef USE_MINI_HT
5133 if(internal_branch(branch_regs[i].is32,return_address)) {
5134 int temp=rt+1;
5135 if(temp==EXCLUDE_REG||temp>=HOST_REGS||
5136 branch_regs[i].regmap[temp]>=0)
5137 {
5138 temp=get_reg(branch_regs[i].regmap,-1);
5139 }
5140 #ifdef HOST_TEMPREG
5141 if(temp<0) temp=HOST_TEMPREG;
5142 #endif
5143 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5144 else emit_movimm(return_address,rt);
5145 }
5146 else
5147 #endif
5148 {
5149 #ifdef REG_PREFETCH
5150 if(temp>=0)
5151 {
5152 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5153 }
5154 #endif
5155 emit_movimm(return_address,rt); // PC into link register
5156 #ifdef IMM_PREFETCH
5157 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5158 #endif
5159 }
5160 }
5161 }
5162 int cc,adj;
5163 cc=get_reg(branch_regs[i].regmap,CCREG);
5164 assert(cc==HOST_CCREG);
5165 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5166 #ifdef REG_PREFETCH
5167 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5168 #endif
5169 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5170 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5171 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5172 if(internal_branch(branch_regs[i].is32,ba[i]))
5173 assem_debug("branch: internal\n");
5174 else
5175 assem_debug("branch: external\n");
5176 if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5177 ds_assemble_entry(i);
5178 }
5179 else {
5180 add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5181 emit_jmp(0);
5182 }
5183}
5184
5185void rjump_assemble(int i,struct regstat *i_regs)
5186{
5187 signed char *i_regmap=i_regs->regmap;
5188 int temp;
5189 int rs,cc,adj;
5190 rs=get_reg(branch_regs[i].regmap,rs1[i]);
5191 assert(rs>=0);
5192 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5193 // Delay slot abuse, make a copy of the branch address register
5194 temp=get_reg(branch_regs[i].regmap,RTEMP);
5195 assert(temp>=0);
5196 assert(regs[i].regmap[temp]==RTEMP);
5197 emit_mov(rs,temp);
5198 rs=temp;
5199 }
5200 address_generation(i+1,i_regs,regs[i].regmap_entry);
5201 #ifdef REG_PREFETCH
5202 if(rt1[i]==31)
5203 {
5204 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5205 int return_address=start+i*4+8;
5206 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5207 }
5208 }
5209 #endif
5210 #ifdef USE_MINI_HT
5211 if(rs1[i]==31) {
5212 int rh=get_reg(regs[i].regmap,RHASH);
5213 if(rh>=0) do_preload_rhash(rh);
5214 }
5215 #endif
5216 ds_assemble(i+1,i_regs);
5217 uint64_t bc_unneeded=branch_regs[i].u;
5218 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5219 bc_unneeded|=1|(1LL<<rt1[i]);
5220 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5221 bc_unneeded&=~(1LL<<rs1[i]);
5222 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5223 bc_unneeded,bc_unneeded_upper);
5224 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5067f341 5225 if(rt1[i]!=0) {
57871462 5226 int rt,return_address;
5067f341 5227 assert(rt1[i+1]!=rt1[i]);
5228 assert(rt2[i+1]!=rt1[i]);
5229 rt=get_reg(branch_regs[i].regmap,rt1[i]);
57871462 5230 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5231 assert(rt>=0);
5232 return_address=start+i*4+8;
5233 #ifdef REG_PREFETCH
5234 if(temp>=0)
5235 {
5236 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5237 }
5238 #endif
5239 emit_movimm(return_address,rt); // PC into link register
5240 #ifdef IMM_PREFETCH
5241 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5242 #endif
5243 }
5244 cc=get_reg(branch_regs[i].regmap,CCREG);
5245 assert(cc==HOST_CCREG);
5246 #ifdef USE_MINI_HT
5247 int rh=get_reg(branch_regs[i].regmap,RHASH);
5248 int ht=get_reg(branch_regs[i].regmap,RHTBL);
5249 if(rs1[i]==31) {
5250 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5251 do_preload_rhtbl(ht);
5252 do_rhash(rs,rh);
5253 }
5254 #endif
5255 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5256 #ifdef DESTRUCTIVE_WRITEBACK
5257 if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5258 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5259 emit_loadreg(rs1[i],rs);
5260 }
5261 }
5262 #endif
5263 #ifdef REG_PREFETCH
5264 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5265 #endif
5266 #ifdef USE_MINI_HT
5267 if(rs1[i]==31) {
5268 do_miniht_load(ht,rh);
5269 }
5270 #endif
5271 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5272 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5273 //assert(adj==0);
5274 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5275 add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5276 emit_jns(0);
5277 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5278 #ifdef USE_MINI_HT
5279 if(rs1[i]==31) {
5280 do_miniht_jump(rs,rh,ht);
5281 }
5282 else
5283 #endif
5284 {
5285 //if(rs!=EAX) emit_mov(rs,EAX);
5286 //emit_jmp((int)jump_vaddr_eax);
5287 emit_jmp(jump_vaddr_reg[rs]);
5288 }
5289 /* Check hash table
5290 temp=!rs;
5291 emit_mov(rs,temp);
5292 emit_shrimm(rs,16,rs);
5293 emit_xor(temp,rs,rs);
5294 emit_movzwl_reg(rs,rs);
5295 emit_shlimm(rs,4,rs);
5296 emit_cmpmem_indexed((int)hash_table,rs,temp);
5297 emit_jne((int)out+14);
5298 emit_readword_indexed((int)hash_table+4,rs,rs);
5299 emit_jmpreg(rs);
5300 emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5301 emit_addimm_no_flags(8,rs);
5302 emit_jeq((int)out-17);
5303 // No hit on hash table, call compiler
5304 emit_pushreg(temp);
5305//DEBUG >
5306#ifdef DEBUG_CYCLE_COUNT
5307 emit_readword((int)&last_count,ECX);
5308 emit_add(HOST_CCREG,ECX,HOST_CCREG);
5309 emit_readword((int)&next_interupt,ECX);
5310 emit_writeword(HOST_CCREG,(int)&Count);
5311 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5312 emit_writeword(ECX,(int)&last_count);
5313#endif
5314//DEBUG <
5315 emit_storereg(CCREG,HOST_CCREG);
5316 emit_call((int)get_addr);
5317 emit_loadreg(CCREG,HOST_CCREG);
5318 emit_addimm(ESP,4,ESP);
5319 emit_jmpreg(EAX);*/
5320 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5321 if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5322 #endif
5323}
5324
5325void cjump_assemble(int i,struct regstat *i_regs)
5326{
5327 signed char *i_regmap=i_regs->regmap;
5328 int cc;
5329 int match;
5330 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5331 assem_debug("match=%d\n",match);
5332 int s1h,s1l,s2h,s2l;
5333 int prev_cop1_usable=cop1_usable;
5334 int unconditional=0,nop=0;
5335 int only32=0;
57871462 5336 int invert=0;
5337 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5338 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 5339 if(!match) invert=1;
5340 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5341 if(i>(ba[i]-start)>>2) invert=1;
5342 #endif
e1190b87 5343
5344 if(ooo[i]) {
57871462 5345 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5346 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5347 s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5348 s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5349 }
5350 else {
5351 s1l=get_reg(i_regmap,rs1[i]);
5352 s1h=get_reg(i_regmap,rs1[i]|64);
5353 s2l=get_reg(i_regmap,rs2[i]);
5354 s2h=get_reg(i_regmap,rs2[i]|64);
5355 }
5356 if(rs1[i]==0&&rs2[i]==0)
5357 {
5358 if(opcode[i]&1) nop=1;
5359 else unconditional=1;
5360 //assert(opcode[i]!=5);
5361 //assert(opcode[i]!=7);
5362 //assert(opcode[i]!=0x15);
5363 //assert(opcode[i]!=0x17);
5364 }
5365 else if(rs1[i]==0)
5366 {
5367 s1l=s2l;s1h=s2h;
5368 s2l=s2h=-1;
5369 only32=(regs[i].was32>>rs2[i])&1;
5370 }
5371 else if(rs2[i]==0)
5372 {
5373 s2l=s2h=-1;
5374 only32=(regs[i].was32>>rs1[i])&1;
5375 }
5376 else {
5377 only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5378 }
5379
e1190b87 5380 if(ooo[i]) {
57871462 5381 // Out of order execution (delay slot first)
5382 //printf("OOOE\n");
5383 address_generation(i+1,i_regs,regs[i].regmap_entry);
5384 ds_assemble(i+1,i_regs);
5385 int adj;
5386 uint64_t bc_unneeded=branch_regs[i].u;
5387 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5388 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5389 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5390 bc_unneeded|=1;
5391 bc_unneeded_upper|=1;
5392 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5393 bc_unneeded,bc_unneeded_upper);
5394 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5395 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5396 cc=get_reg(branch_regs[i].regmap,CCREG);
5397 assert(cc==HOST_CCREG);
5398 if(unconditional)
5399 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5400 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5401 //assem_debug("cycle count (adj)\n");
5402 if(unconditional) {
5403 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5404 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5405 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5406 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5407 if(internal)
5408 assem_debug("branch: internal\n");
5409 else
5410 assem_debug("branch: external\n");
5411 if(internal&&is_ds[(ba[i]-start)>>2]) {
5412 ds_assemble_entry(i);
5413 }
5414 else {
5415 add_to_linker((int)out,ba[i],internal);
5416 emit_jmp(0);
5417 }
5418 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5419 if(((u_int)out)&7) emit_addnop(0);
5420 #endif
5421 }
5422 }
5423 else if(nop) {
5424 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5425 int jaddr=(int)out;
5426 emit_jns(0);
5427 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5428 }
5429 else {
5430 int taken=0,nottaken=0,nottaken1=0;
5431 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5432 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5433 if(!only32)
5434 {
5435 assert(s1h>=0);
5436 if(opcode[i]==4) // BEQ
5437 {
5438 if(s2h>=0) emit_cmp(s1h,s2h);
5439 else emit_test(s1h,s1h);
5440 nottaken1=(int)out;
5441 emit_jne(1);
5442 }
5443 if(opcode[i]==5) // BNE
5444 {
5445 if(s2h>=0) emit_cmp(s1h,s2h);
5446 else emit_test(s1h,s1h);
5447 if(invert) taken=(int)out;
5448 else add_to_linker((int)out,ba[i],internal);
5449 emit_jne(0);
5450 }
5451 if(opcode[i]==6) // BLEZ
5452 {
5453 emit_test(s1h,s1h);
5454 if(invert) taken=(int)out;
5455 else add_to_linker((int)out,ba[i],internal);
5456 emit_js(0);
5457 nottaken1=(int)out;
5458 emit_jne(1);
5459 }
5460 if(opcode[i]==7) // BGTZ
5461 {
5462 emit_test(s1h,s1h);
5463 nottaken1=(int)out;
5464 emit_js(1);
5465 if(invert) taken=(int)out;
5466 else add_to_linker((int)out,ba[i],internal);
5467 emit_jne(0);
5468 }
5469 } // if(!only32)
5470
5471 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5472 assert(s1l>=0);
5473 if(opcode[i]==4) // BEQ
5474 {
5475 if(s2l>=0) emit_cmp(s1l,s2l);
5476 else emit_test(s1l,s1l);
5477 if(invert){
5478 nottaken=(int)out;
5479 emit_jne(1);
5480 }else{
5481 add_to_linker((int)out,ba[i],internal);
5482 emit_jeq(0);
5483 }
5484 }
5485 if(opcode[i]==5) // BNE
5486 {
5487 if(s2l>=0) emit_cmp(s1l,s2l);
5488 else emit_test(s1l,s1l);
5489 if(invert){
5490 nottaken=(int)out;
5491 emit_jeq(1);
5492 }else{
5493 add_to_linker((int)out,ba[i],internal);
5494 emit_jne(0);
5495 }
5496 }
5497 if(opcode[i]==6) // BLEZ
5498 {
5499 emit_cmpimm(s1l,1);
5500 if(invert){
5501 nottaken=(int)out;
5502 emit_jge(1);
5503 }else{
5504 add_to_linker((int)out,ba[i],internal);
5505 emit_jl(0);
5506 }
5507 }
5508 if(opcode[i]==7) // BGTZ
5509 {
5510 emit_cmpimm(s1l,1);
5511 if(invert){
5512 nottaken=(int)out;
5513 emit_jl(1);
5514 }else{
5515 add_to_linker((int)out,ba[i],internal);
5516 emit_jge(0);
5517 }
5518 }
5519 if(invert) {
5520 if(taken) set_jump_target(taken,(int)out);
5521 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5522 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5523 if(adj) {
5524 emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5525 add_to_linker((int)out,ba[i],internal);
5526 }else{
5527 emit_addnop(13);
5528 add_to_linker((int)out,ba[i],internal*2);
5529 }
5530 emit_jmp(0);
5531 }else
5532 #endif
5533 {
5534 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5535 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5536 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5537 if(internal)
5538 assem_debug("branch: internal\n");
5539 else
5540 assem_debug("branch: external\n");
5541 if(internal&&is_ds[(ba[i]-start)>>2]) {
5542 ds_assemble_entry(i);
5543 }
5544 else {
5545 add_to_linker((int)out,ba[i],internal);
5546 emit_jmp(0);
5547 }
5548 }
5549 set_jump_target(nottaken,(int)out);
5550 }
5551
5552 if(nottaken1) set_jump_target(nottaken1,(int)out);
5553 if(adj) {
5554 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5555 }
5556 } // (!unconditional)
5557 } // if(ooo)
5558 else
5559 {
5560 // In-order execution (branch first)
5561 //if(likely[i]) printf("IOL\n");
5562 //else
5563 //printf("IOE\n");
5564 int taken=0,nottaken=0,nottaken1=0;
5565 if(!unconditional&&!nop) {
5566 if(!only32)
5567 {
5568 assert(s1h>=0);
5569 if((opcode[i]&0x2f)==4) // BEQ
5570 {
5571 if(s2h>=0) emit_cmp(s1h,s2h);
5572 else emit_test(s1h,s1h);
5573 nottaken1=(int)out;
5574 emit_jne(2);
5575 }
5576 if((opcode[i]&0x2f)==5) // BNE
5577 {
5578 if(s2h>=0) emit_cmp(s1h,s2h);
5579 else emit_test(s1h,s1h);
5580 taken=(int)out;
5581 emit_jne(1);
5582 }
5583 if((opcode[i]&0x2f)==6) // BLEZ
5584 {
5585 emit_test(s1h,s1h);
5586 taken=(int)out;
5587 emit_js(1);
5588 nottaken1=(int)out;
5589 emit_jne(2);
5590 }
5591 if((opcode[i]&0x2f)==7) // BGTZ
5592 {
5593 emit_test(s1h,s1h);
5594 nottaken1=(int)out;
5595 emit_js(2);
5596 taken=(int)out;
5597 emit_jne(1);
5598 }
5599 } // if(!only32)
5600
5601 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5602 assert(s1l>=0);
5603 if((opcode[i]&0x2f)==4) // BEQ
5604 {
5605 if(s2l>=0) emit_cmp(s1l,s2l);
5606 else emit_test(s1l,s1l);
5607 nottaken=(int)out;
5608 emit_jne(2);
5609 }
5610 if((opcode[i]&0x2f)==5) // BNE
5611 {
5612 if(s2l>=0) emit_cmp(s1l,s2l);
5613 else emit_test(s1l,s1l);
5614 nottaken=(int)out;
5615 emit_jeq(2);
5616 }
5617 if((opcode[i]&0x2f)==6) // BLEZ
5618 {
5619 emit_cmpimm(s1l,1);
5620 nottaken=(int)out;
5621 emit_jge(2);
5622 }
5623 if((opcode[i]&0x2f)==7) // BGTZ
5624 {
5625 emit_cmpimm(s1l,1);
5626 nottaken=(int)out;
5627 emit_jl(2);
5628 }
5629 } // if(!unconditional)
5630 int adj;
5631 uint64_t ds_unneeded=branch_regs[i].u;
5632 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5633 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5634 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5635 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5636 ds_unneeded|=1;
5637 ds_unneeded_upper|=1;
5638 // branch taken
5639 if(!nop) {
5640 if(taken) set_jump_target(taken,(int)out);
5641 assem_debug("1:\n");
5642 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5643 ds_unneeded,ds_unneeded_upper);
5644 // load regs
5645 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5646 address_generation(i+1,&branch_regs[i],0);
5647 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5648 ds_assemble(i+1,&branch_regs[i]);
5649 cc=get_reg(branch_regs[i].regmap,CCREG);
5650 if(cc==-1) {
5651 emit_loadreg(CCREG,cc=HOST_CCREG);
5652 // CHECK: Is the following instruction (fall thru) allocated ok?
5653 }
5654 assert(cc==HOST_CCREG);
5655 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5656 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5657 assem_debug("cycle count (adj)\n");
5658 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5659 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5660 if(internal)
5661 assem_debug("branch: internal\n");
5662 else
5663 assem_debug("branch: external\n");
5664 if(internal&&is_ds[(ba[i]-start)>>2]) {
5665 ds_assemble_entry(i);
5666 }
5667 else {
5668 add_to_linker((int)out,ba[i],internal);
5669 emit_jmp(0);
5670 }
5671 }
5672 // branch not taken
5673 cop1_usable=prev_cop1_usable;
5674 if(!unconditional) {
5675 if(nottaken1) set_jump_target(nottaken1,(int)out);
5676 set_jump_target(nottaken,(int)out);
5677 assem_debug("2:\n");
5678 if(!likely[i]) {
5679 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5680 ds_unneeded,ds_unneeded_upper);
5681 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5682 address_generation(i+1,&branch_regs[i],0);
5683 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5684 ds_assemble(i+1,&branch_regs[i]);
5685 }
5686 cc=get_reg(branch_regs[i].regmap,CCREG);
5687 if(cc==-1&&!likely[i]) {
5688 // Cycle count isn't in a register, temporarily load it then write it out
5689 emit_loadreg(CCREG,HOST_CCREG);
5690 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5691 int jaddr=(int)out;
5692 emit_jns(0);
5693 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5694 emit_storereg(CCREG,HOST_CCREG);
5695 }
5696 else{
5697 cc=get_reg(i_regmap,CCREG);
5698 assert(cc==HOST_CCREG);
5699 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5700 int jaddr=(int)out;
5701 emit_jns(0);
5702 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5703 }
5704 }
5705 }
5706}
5707
5708void sjump_assemble(int i,struct regstat *i_regs)
5709{
5710 signed char *i_regmap=i_regs->regmap;
5711 int cc;
5712 int match;
5713 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5714 assem_debug("smatch=%d\n",match);
5715 int s1h,s1l;
5716 int prev_cop1_usable=cop1_usable;
5717 int unconditional=0,nevertaken=0;
5718 int only32=0;
57871462 5719 int invert=0;
5720 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5721 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 5722 if(!match) invert=1;
5723 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5724 if(i>(ba[i]-start)>>2) invert=1;
5725 #endif
5726
5727 //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
df894a3a 5728 //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
57871462 5729
e1190b87 5730 if(ooo[i]) {
57871462 5731 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5732 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5733 }
5734 else {
5735 s1l=get_reg(i_regmap,rs1[i]);
5736 s1h=get_reg(i_regmap,rs1[i]|64);
5737 }
5738 if(rs1[i]==0)
5739 {
5740 if(opcode2[i]&1) unconditional=1;
5741 else nevertaken=1;
5742 // These are never taken (r0 is never less than zero)
5743 //assert(opcode2[i]!=0);
5744 //assert(opcode2[i]!=2);
5745 //assert(opcode2[i]!=0x10);
5746 //assert(opcode2[i]!=0x12);
5747 }
5748 else {
5749 only32=(regs[i].was32>>rs1[i])&1;
5750 }
5751
e1190b87 5752 if(ooo[i]) {
57871462 5753 // Out of order execution (delay slot first)
5754 //printf("OOOE\n");
5755 address_generation(i+1,i_regs,regs[i].regmap_entry);
5756 ds_assemble(i+1,i_regs);
5757 int adj;
5758 uint64_t bc_unneeded=branch_regs[i].u;
5759 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5760 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5761 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5762 bc_unneeded|=1;
5763 bc_unneeded_upper|=1;
5764 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5765 bc_unneeded,bc_unneeded_upper);
5766 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5767 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5768 if(rt1[i]==31) {
5769 int rt,return_address;
57871462 5770 rt=get_reg(branch_regs[i].regmap,31);
5771 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5772 if(rt>=0) {
5773 // Save the PC even if the branch is not taken
5774 return_address=start+i*4+8;
5775 emit_movimm(return_address,rt); // PC into link register
5776 #ifdef IMM_PREFETCH
5777 if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5778 #endif
5779 }
5780 }
5781 cc=get_reg(branch_regs[i].regmap,CCREG);
5782 assert(cc==HOST_CCREG);
5783 if(unconditional)
5784 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5785 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5786 assem_debug("cycle count (adj)\n");
5787 if(unconditional) {
5788 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5789 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5790 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5791 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5792 if(internal)
5793 assem_debug("branch: internal\n");
5794 else
5795 assem_debug("branch: external\n");
5796 if(internal&&is_ds[(ba[i]-start)>>2]) {
5797 ds_assemble_entry(i);
5798 }
5799 else {
5800 add_to_linker((int)out,ba[i],internal);
5801 emit_jmp(0);
5802 }
5803 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5804 if(((u_int)out)&7) emit_addnop(0);
5805 #endif
5806 }
5807 }
5808 else if(nevertaken) {
5809 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5810 int jaddr=(int)out;
5811 emit_jns(0);
5812 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5813 }
5814 else {
5815 int nottaken=0;
5816 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5817 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5818 if(!only32)
5819 {
5820 assert(s1h>=0);
df894a3a 5821 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
57871462 5822 {
5823 emit_test(s1h,s1h);
5824 if(invert){
5825 nottaken=(int)out;
5826 emit_jns(1);
5827 }else{
5828 add_to_linker((int)out,ba[i],internal);
5829 emit_js(0);
5830 }
5831 }
df894a3a 5832 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
57871462 5833 {
5834 emit_test(s1h,s1h);
5835 if(invert){
5836 nottaken=(int)out;
5837 emit_js(1);
5838 }else{
5839 add_to_linker((int)out,ba[i],internal);
5840 emit_jns(0);
5841 }
5842 }
5843 } // if(!only32)
5844 else
5845 {
5846 assert(s1l>=0);
df894a3a 5847 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
57871462 5848 {
5849 emit_test(s1l,s1l);
5850 if(invert){
5851 nottaken=(int)out;
5852 emit_jns(1);
5853 }else{
5854 add_to_linker((int)out,ba[i],internal);
5855 emit_js(0);
5856 }
5857 }
df894a3a 5858 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
57871462 5859 {
5860 emit_test(s1l,s1l);
5861 if(invert){
5862 nottaken=(int)out;
5863 emit_js(1);
5864 }else{
5865 add_to_linker((int)out,ba[i],internal);
5866 emit_jns(0);
5867 }
5868 }
5869 } // if(!only32)
5870
5871 if(invert) {
5872 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5873 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5874 if(adj) {
5875 emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5876 add_to_linker((int)out,ba[i],internal);
5877 }else{
5878 emit_addnop(13);
5879 add_to_linker((int)out,ba[i],internal*2);
5880 }
5881 emit_jmp(0);
5882 }else
5883 #endif
5884 {
5885 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5886 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5887 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5888 if(internal)
5889 assem_debug("branch: internal\n");
5890 else
5891 assem_debug("branch: external\n");
5892 if(internal&&is_ds[(ba[i]-start)>>2]) {
5893 ds_assemble_entry(i);
5894 }
5895 else {
5896 add_to_linker((int)out,ba[i],internal);
5897 emit_jmp(0);
5898 }
5899 }
5900 set_jump_target(nottaken,(int)out);
5901 }
5902
5903 if(adj) {
5904 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5905 }
5906 } // (!unconditional)
5907 } // if(ooo)
5908 else
5909 {
5910 // In-order execution (branch first)
5911 //printf("IOE\n");
5912 int nottaken=0;
a6491170 5913 if(rt1[i]==31) {
5914 int rt,return_address;
a6491170 5915 rt=get_reg(branch_regs[i].regmap,31);
5916 if(rt>=0) {
5917 // Save the PC even if the branch is not taken
5918 return_address=start+i*4+8;
5919 emit_movimm(return_address,rt); // PC into link register
5920 #ifdef IMM_PREFETCH
5921 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5922 #endif
5923 }
5924 }
57871462 5925 if(!unconditional) {
5926 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5927 if(!only32)
5928 {
5929 assert(s1h>=0);
a6491170 5930 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
57871462 5931 {
5932 emit_test(s1h,s1h);
5933 nottaken=(int)out;
5934 emit_jns(1);
5935 }
a6491170 5936 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
57871462 5937 {
5938 emit_test(s1h,s1h);
5939 nottaken=(int)out;
5940 emit_js(1);
5941 }
5942 } // if(!only32)
5943 else
5944 {
5945 assert(s1l>=0);
a6491170 5946 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
57871462 5947 {
5948 emit_test(s1l,s1l);
5949 nottaken=(int)out;
5950 emit_jns(1);
5951 }
a6491170 5952 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
57871462 5953 {
5954 emit_test(s1l,s1l);
5955 nottaken=(int)out;
5956 emit_js(1);
5957 }
5958 }
5959 } // if(!unconditional)
5960 int adj;
5961 uint64_t ds_unneeded=branch_regs[i].u;
5962 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5963 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5964 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5965 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5966 ds_unneeded|=1;
5967 ds_unneeded_upper|=1;
5968 // branch taken
5969 if(!nevertaken) {
5970 //assem_debug("1:\n");
5971 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5972 ds_unneeded,ds_unneeded_upper);
5973 // load regs
5974 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5975 address_generation(i+1,&branch_regs[i],0);
5976 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5977 ds_assemble(i+1,&branch_regs[i]);
5978 cc=get_reg(branch_regs[i].regmap,CCREG);
5979 if(cc==-1) {
5980 emit_loadreg(CCREG,cc=HOST_CCREG);
5981 // CHECK: Is the following instruction (fall thru) allocated ok?
5982 }
5983 assert(cc==HOST_CCREG);
5984 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5985 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5986 assem_debug("cycle count (adj)\n");
5987 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5988 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5989 if(internal)
5990 assem_debug("branch: internal\n");
5991 else
5992 assem_debug("branch: external\n");
5993 if(internal&&is_ds[(ba[i]-start)>>2]) {
5994 ds_assemble_entry(i);
5995 }
5996 else {
5997 add_to_linker((int)out,ba[i],internal);
5998 emit_jmp(0);
5999 }
6000 }
6001 // branch not taken
6002 cop1_usable=prev_cop1_usable;
6003 if(!unconditional) {
6004 set_jump_target(nottaken,(int)out);
6005 assem_debug("1:\n");
6006 if(!likely[i]) {
6007 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6008 ds_unneeded,ds_unneeded_upper);
6009 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6010 address_generation(i+1,&branch_regs[i],0);
6011 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6012 ds_assemble(i+1,&branch_regs[i]);
6013 }
6014 cc=get_reg(branch_regs[i].regmap,CCREG);
6015 if(cc==-1&&!likely[i]) {
6016 // Cycle count isn't in a register, temporarily load it then write it out
6017 emit_loadreg(CCREG,HOST_CCREG);
6018 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6019 int jaddr=(int)out;
6020 emit_jns(0);
6021 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6022 emit_storereg(CCREG,HOST_CCREG);
6023 }
6024 else{
6025 cc=get_reg(i_regmap,CCREG);
6026 assert(cc==HOST_CCREG);
6027 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6028 int jaddr=(int)out;
6029 emit_jns(0);
6030 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6031 }
6032 }
6033 }
6034}
6035
6036void fjump_assemble(int i,struct regstat *i_regs)
6037{
6038 signed char *i_regmap=i_regs->regmap;
6039 int cc;
6040 int match;
6041 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6042 assem_debug("fmatch=%d\n",match);
6043 int fs,cs;
6044 int eaddr;
57871462 6045 int invert=0;
6046 int internal=internal_branch(branch_regs[i].is32,ba[i]);
6047 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 6048 if(!match) invert=1;
6049 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6050 if(i>(ba[i]-start)>>2) invert=1;
6051 #endif
6052
e1190b87 6053 if(ooo[i]) {
57871462 6054 fs=get_reg(branch_regs[i].regmap,FSREG);
6055 address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
6056 }
6057 else {
6058 fs=get_reg(i_regmap,FSREG);
6059 }
6060
6061 // Check cop1 unusable
6062 if(!cop1_usable) {
6063 cs=get_reg(i_regmap,CSREG);
6064 assert(cs>=0);
6065 emit_testimm(cs,0x20000000);
6066 eaddr=(int)out;
6067 emit_jeq(0);
6068 add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
6069 cop1_usable=1;
6070 }
6071
e1190b87 6072 if(ooo[i]) {
57871462 6073 // Out of order execution (delay slot first)
6074 //printf("OOOE\n");
6075 ds_assemble(i+1,i_regs);
6076 int adj;
6077 uint64_t bc_unneeded=branch_regs[i].u;
6078 uint64_t bc_unneeded_upper=branch_regs[i].uu;
6079 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6080 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
6081 bc_unneeded|=1;
6082 bc_unneeded_upper|=1;
6083 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6084 bc_unneeded,bc_unneeded_upper);
6085 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
6086 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6087 cc=get_reg(branch_regs[i].regmap,CCREG);
6088 assert(cc==HOST_CCREG);
6089 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6090 assem_debug("cycle count (adj)\n");
6091 if(1) {
6092 int nottaken=0;
6093 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6094 if(1) {
6095 assert(fs>=0);
6096 emit_testimm(fs,0x800000);
6097 if(source[i]&0x10000) // BC1T
6098 {
6099 if(invert){
6100 nottaken=(int)out;
6101 emit_jeq(1);
6102 }else{
6103 add_to_linker((int)out,ba[i],internal);
6104 emit_jne(0);
6105 }
6106 }
6107 else // BC1F
6108 if(invert){
6109 nottaken=(int)out;
6110 emit_jne(1);
6111 }else{
6112 add_to_linker((int)out,ba[i],internal);
6113 emit_jeq(0);
6114 }
6115 {
6116 }
6117 } // if(!only32)
6118
6119 if(invert) {
6120 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
6121 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6122 else if(match) emit_addnop(13);
6123 #endif
6124 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6125 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6126 if(internal)
6127 assem_debug("branch: internal\n");
6128 else
6129 assem_debug("branch: external\n");
6130 if(internal&&is_ds[(ba[i]-start)>>2]) {
6131 ds_assemble_entry(i);
6132 }
6133 else {
6134 add_to_linker((int)out,ba[i],internal);
6135 emit_jmp(0);
6136 }
6137 set_jump_target(nottaken,(int)out);
6138 }
6139
6140 if(adj) {
6141 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
6142 }
6143 } // (!unconditional)
6144 } // if(ooo)
6145 else
6146 {
6147 // In-order execution (branch first)
6148 //printf("IOE\n");
6149 int nottaken=0;
6150 if(1) {
6151 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6152 if(1) {
6153 assert(fs>=0);
6154 emit_testimm(fs,0x800000);
6155 if(source[i]&0x10000) // BC1T
6156 {
6157 nottaken=(int)out;
6158 emit_jeq(1);
6159 }
6160 else // BC1F
6161 {
6162 nottaken=(int)out;
6163 emit_jne(1);
6164 }
6165 }
6166 } // if(!unconditional)
6167 int adj;
6168 uint64_t ds_unneeded=branch_regs[i].u;
6169 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6170 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6171 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6172 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6173 ds_unneeded|=1;
6174 ds_unneeded_upper|=1;
6175 // branch taken
6176 //assem_debug("1:\n");
6177 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6178 ds_unneeded,ds_unneeded_upper);
6179 // load regs
6180 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6181 address_generation(i+1,&branch_regs[i],0);
6182 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6183 ds_assemble(i+1,&branch_regs[i]);
6184 cc=get_reg(branch_regs[i].regmap,CCREG);
6185 if(cc==-1) {
6186 emit_loadreg(CCREG,cc=HOST_CCREG);
6187 // CHECK: Is the following instruction (fall thru) allocated ok?
6188 }
6189 assert(cc==HOST_CCREG);
6190 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6191 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6192 assem_debug("cycle count (adj)\n");
6193 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6194 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6195 if(internal)
6196 assem_debug("branch: internal\n");
6197 else
6198 assem_debug("branch: external\n");
6199 if(internal&&is_ds[(ba[i]-start)>>2]) {
6200 ds_assemble_entry(i);
6201 }
6202 else {
6203 add_to_linker((int)out,ba[i],internal);
6204 emit_jmp(0);
6205 }
6206
6207 // branch not taken
6208 if(1) { // <- FIXME (don't need this)
6209 set_jump_target(nottaken,(int)out);
6210 assem_debug("1:\n");
6211 if(!likely[i]) {
6212 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6213 ds_unneeded,ds_unneeded_upper);
6214 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6215 address_generation(i+1,&branch_regs[i],0);
6216 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6217 ds_assemble(i+1,&branch_regs[i]);
6218 }
6219 cc=get_reg(branch_regs[i].regmap,CCREG);
6220 if(cc==-1&&!likely[i]) {
6221 // Cycle count isn't in a register, temporarily load it then write it out
6222 emit_loadreg(CCREG,HOST_CCREG);
6223 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6224 int jaddr=(int)out;
6225 emit_jns(0);
6226 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6227 emit_storereg(CCREG,HOST_CCREG);
6228 }
6229 else{
6230 cc=get_reg(i_regmap,CCREG);
6231 assert(cc==HOST_CCREG);
6232 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6233 int jaddr=(int)out;
6234 emit_jns(0);
6235 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6236 }
6237 }
6238 }
6239}
6240
6241static void pagespan_assemble(int i,struct regstat *i_regs)
6242{
6243 int s1l=get_reg(i_regs->regmap,rs1[i]);
6244 int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6245 int s2l=get_reg(i_regs->regmap,rs2[i]);
6246 int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6247 void *nt_branch=NULL;
6248 int taken=0;
6249 int nottaken=0;
6250 int unconditional=0;
6251 if(rs1[i]==0)
6252 {
6253 s1l=s2l;s1h=s2h;
6254 s2l=s2h=-1;
6255 }
6256 else if(rs2[i]==0)
6257 {
6258 s2l=s2h=-1;
6259 }
6260 if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6261 s1h=s2h=-1;
6262 }
6263 int hr=0;
6264 int addr,alt,ntaddr;
6265 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6266 else {
6267 while(hr<HOST_REGS)
6268 {
6269 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6270 (i_regs->regmap[hr]&63)!=rs1[i] &&
6271 (i_regs->regmap[hr]&63)!=rs2[i] )
6272 {
6273 addr=hr++;break;
6274 }
6275 hr++;
6276 }
6277 }
6278 while(hr<HOST_REGS)
6279 {
6280 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6281 (i_regs->regmap[hr]&63)!=rs1[i] &&
6282 (i_regs->regmap[hr]&63)!=rs2[i] )
6283 {
6284 alt=hr++;break;
6285 }
6286 hr++;
6287 }
6288 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6289 {
6290 while(hr<HOST_REGS)
6291 {
6292 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6293 (i_regs->regmap[hr]&63)!=rs1[i] &&
6294 (i_regs->regmap[hr]&63)!=rs2[i] )
6295 {
6296 ntaddr=hr;break;
6297 }
6298 hr++;
6299 }
6300 }
6301 assert(hr<HOST_REGS);
6302 if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6303 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6304 }
6305 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6306 if(opcode[i]==2) // J
6307 {
6308 unconditional=1;
6309 }
6310 if(opcode[i]==3) // JAL
6311 {
6312 // TODO: mini_ht
6313 int rt=get_reg(i_regs->regmap,31);
6314 emit_movimm(start+i*4+8,rt);
6315 unconditional=1;
6316 }
6317 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6318 {
6319 emit_mov(s1l,addr);
6320 if(opcode2[i]==9) // JALR
6321 {
5067f341 6322 int rt=get_reg(i_regs->regmap,rt1[i]);
57871462 6323 emit_movimm(start+i*4+8,rt);
6324 }
6325 }
6326 if((opcode[i]&0x3f)==4) // BEQ
6327 {
6328 if(rs1[i]==rs2[i])
6329 {
6330 unconditional=1;
6331 }
6332 else
6333 #ifdef HAVE_CMOV_IMM
6334 if(s1h<0) {
6335 if(s2l>=0) emit_cmp(s1l,s2l);
6336 else emit_test(s1l,s1l);
6337 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6338 }
6339 else
6340 #endif
6341 {
6342 assert(s1l>=0);
6343 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6344 if(s1h>=0) {
6345 if(s2h>=0) emit_cmp(s1h,s2h);
6346 else emit_test(s1h,s1h);
6347 emit_cmovne_reg(alt,addr);
6348 }
6349 if(s2l>=0) emit_cmp(s1l,s2l);
6350 else emit_test(s1l,s1l);
6351 emit_cmovne_reg(alt,addr);
6352 }
6353 }
6354 if((opcode[i]&0x3f)==5) // BNE
6355 {
6356 #ifdef HAVE_CMOV_IMM
6357 if(s1h<0) {
6358 if(s2l>=0) emit_cmp(s1l,s2l);
6359 else emit_test(s1l,s1l);
6360 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6361 }
6362 else
6363 #endif
6364 {
6365 assert(s1l>=0);
6366 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6367 if(s1h>=0) {
6368 if(s2h>=0) emit_cmp(s1h,s2h);
6369 else emit_test(s1h,s1h);
6370 emit_cmovne_reg(alt,addr);
6371 }
6372 if(s2l>=0) emit_cmp(s1l,s2l);
6373 else emit_test(s1l,s1l);
6374 emit_cmovne_reg(alt,addr);
6375 }
6376 }
6377 if((opcode[i]&0x3f)==0x14) // BEQL
6378 {
6379 if(s1h>=0) {
6380 if(s2h>=0) emit_cmp(s1h,s2h);
6381 else emit_test(s1h,s1h);
6382 nottaken=(int)out;
6383 emit_jne(0);
6384 }
6385 if(s2l>=0) emit_cmp(s1l,s2l);
6386 else emit_test(s1l,s1l);
6387 if(nottaken) set_jump_target(nottaken,(int)out);
6388 nottaken=(int)out;
6389 emit_jne(0);
6390 }
6391 if((opcode[i]&0x3f)==0x15) // BNEL
6392 {
6393 if(s1h>=0) {
6394 if(s2h>=0) emit_cmp(s1h,s2h);
6395 else emit_test(s1h,s1h);
6396 taken=(int)out;
6397 emit_jne(0);
6398 }
6399 if(s2l>=0) emit_cmp(s1l,s2l);
6400 else emit_test(s1l,s1l);
6401 nottaken=(int)out;
6402 emit_jeq(0);
6403 if(taken) set_jump_target(taken,(int)out);
6404 }
6405 if((opcode[i]&0x3f)==6) // BLEZ
6406 {
6407 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6408 emit_cmpimm(s1l,1);
6409 if(s1h>=0) emit_mov(addr,ntaddr);
6410 emit_cmovl_reg(alt,addr);
6411 if(s1h>=0) {
6412 emit_test(s1h,s1h);
6413 emit_cmovne_reg(ntaddr,addr);
6414 emit_cmovs_reg(alt,addr);
6415 }
6416 }
6417 if((opcode[i]&0x3f)==7) // BGTZ
6418 {
6419 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6420 emit_cmpimm(s1l,1);
6421 if(s1h>=0) emit_mov(addr,alt);
6422 emit_cmovl_reg(ntaddr,addr);
6423 if(s1h>=0) {
6424 emit_test(s1h,s1h);
6425 emit_cmovne_reg(alt,addr);
6426 emit_cmovs_reg(ntaddr,addr);
6427 }
6428 }
6429 if((opcode[i]&0x3f)==0x16) // BLEZL
6430 {
6431 assert((opcode[i]&0x3f)!=0x16);
6432 }
6433 if((opcode[i]&0x3f)==0x17) // BGTZL
6434 {
6435 assert((opcode[i]&0x3f)!=0x17);
6436 }
6437 assert(opcode[i]!=1); // BLTZ/BGEZ
6438
6439 //FIXME: Check CSREG
6440 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6441 if((source[i]&0x30000)==0) // BC1F
6442 {
6443 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6444 emit_testimm(s1l,0x800000);
6445 emit_cmovne_reg(alt,addr);
6446 }
6447 if((source[i]&0x30000)==0x10000) // BC1T
6448 {
6449 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6450 emit_testimm(s1l,0x800000);
6451 emit_cmovne_reg(alt,addr);
6452 }
6453 if((source[i]&0x30000)==0x20000) // BC1FL
6454 {
6455 emit_testimm(s1l,0x800000);
6456 nottaken=(int)out;
6457 emit_jne(0);
6458 }
6459 if((source[i]&0x30000)==0x30000) // BC1TL
6460 {
6461 emit_testimm(s1l,0x800000);
6462 nottaken=(int)out;
6463 emit_jeq(0);
6464 }
6465 }
6466
6467 assert(i_regs->regmap[HOST_CCREG]==CCREG);
6468 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6469 if(likely[i]||unconditional)
6470 {
6471 emit_movimm(ba[i],HOST_BTREG);
6472 }
6473 else if(addr!=HOST_BTREG)
6474 {
6475 emit_mov(addr,HOST_BTREG);
6476 }
6477 void *branch_addr=out;
6478 emit_jmp(0);
6479 int target_addr=start+i*4+5;
6480 void *stub=out;
6481 void *compiled_target_addr=check_addr(target_addr);
6482 emit_extjump_ds((int)branch_addr,target_addr);
6483 if(compiled_target_addr) {
6484 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6485 add_link(target_addr,stub);
6486 }
6487 else set_jump_target((int)branch_addr,(int)stub);
6488 if(likely[i]) {
6489 // Not-taken path
6490 set_jump_target((int)nottaken,(int)out);
6491 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6492 void *branch_addr=out;
6493 emit_jmp(0);
6494 int target_addr=start+i*4+8;
6495 void *stub=out;
6496 void *compiled_target_addr=check_addr(target_addr);
6497 emit_extjump_ds((int)branch_addr,target_addr);
6498 if(compiled_target_addr) {
6499 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6500 add_link(target_addr,stub);
6501 }
6502 else set_jump_target((int)branch_addr,(int)stub);
6503 }
6504}
6505
6506// Assemble the delay slot for the above
6507static void pagespan_ds()
6508{
6509 assem_debug("initial delay slot:\n");
6510 u_int vaddr=start+1;
94d23bb9 6511 u_int page=get_page(vaddr);
6512 u_int vpage=get_vpage(vaddr);
57871462 6513 ll_add(jump_dirty+vpage,vaddr,(void *)out);
6514 do_dirty_stub_ds();
6515 ll_add(jump_in+page,vaddr,(void *)out);
6516 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6517 if(regs[0].regmap[HOST_CCREG]!=CCREG)
6518 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6519 if(regs[0].regmap[HOST_BTREG]!=BTREG)
6520 emit_writeword(HOST_BTREG,(int)&branch_target);
6521 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6522 address_generation(0,&regs[0],regs[0].regmap_entry);
b9b61529 6523 if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
57871462 6524 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6525 cop1_usable=0;
6526 is_delayslot=0;
6527 switch(itype[0]) {
6528 case ALU:
6529 alu_assemble(0,&regs[0]);break;
6530 case IMM16:
6531 imm16_assemble(0,&regs[0]);break;
6532 case SHIFT:
6533 shift_assemble(0,&regs[0]);break;
6534 case SHIFTIMM:
6535 shiftimm_assemble(0,&regs[0]);break;
6536 case LOAD:
6537 load_assemble(0,&regs[0]);break;
6538 case LOADLR:
6539 loadlr_assemble(0,&regs[0]);break;
6540 case STORE:
6541 store_assemble(0,&regs[0]);break;
6542 case STORELR:
6543 storelr_assemble(0,&regs[0]);break;
6544 case COP0:
6545 cop0_assemble(0,&regs[0]);break;
6546 case COP1:
6547 cop1_assemble(0,&regs[0]);break;
6548 case C1LS:
6549 c1ls_assemble(0,&regs[0]);break;
b9b61529 6550 case COP2:
6551 cop2_assemble(0,&regs[0]);break;
6552 case C2LS:
6553 c2ls_assemble(0,&regs[0]);break;
6554 case C2OP:
6555 c2op_assemble(0,&regs[0]);break;
57871462 6556 case FCONV:
6557 fconv_assemble(0,&regs[0]);break;
6558 case FLOAT:
6559 float_assemble(0,&regs[0]);break;
6560 case FCOMP:
6561 fcomp_assemble(0,&regs[0]);break;
6562 case MULTDIV:
6563 multdiv_assemble(0,&regs[0]);break;
6564 case MOV:
6565 mov_assemble(0,&regs[0]);break;
6566 case SYSCALL:
7139f3c8 6567 case HLECALL:
1e973cb0 6568 case INTCALL:
57871462 6569 case SPAN:
6570 case UJUMP:
6571 case RJUMP:
6572 case CJUMP:
6573 case SJUMP:
6574 case FJUMP:
6575 printf("Jump in the delay slot. This is probably a bug.\n");
6576 }
6577 int btaddr=get_reg(regs[0].regmap,BTREG);
6578 if(btaddr<0) {
6579 btaddr=get_reg(regs[0].regmap,-1);
6580 emit_readword((int)&branch_target,btaddr);
6581 }
6582 assert(btaddr!=HOST_CCREG);
6583 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6584#ifdef HOST_IMM8
6585 emit_movimm(start+4,HOST_TEMPREG);
6586 emit_cmp(btaddr,HOST_TEMPREG);
6587#else
6588 emit_cmpimm(btaddr,start+4);
6589#endif
6590 int branch=(int)out;
6591 emit_jeq(0);
6592 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6593 emit_jmp(jump_vaddr_reg[btaddr]);
6594 set_jump_target(branch,(int)out);
6595 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6596 load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6597}
6598
6599// Basic liveness analysis for MIPS registers
6600void unneeded_registers(int istart,int iend,int r)
6601{
6602 int i;
6603 uint64_t u,uu,b,bu;
6604 uint64_t temp_u,temp_uu;
6605 uint64_t tdep;
6606 if(iend==slen-1) {
6607 u=1;uu=1;
6608 }else{
6609 u=unneeded_reg[iend+1];
6610 uu=unneeded_reg_upper[iend+1];
6611 u=1;uu=1;
6612 }
6613 for (i=iend;i>=istart;i--)
6614 {
6615 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6616 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6617 {
6618 // If subroutine call, flag return address as a possible branch target
6619 if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6620
6621 if(ba[i]<start || ba[i]>=(start+slen*4))
6622 {
6623 // Branch out of this block, flush all regs
6624 u=1;
6625 uu=1;
6626 /* Hexagon hack
6627 if(itype[i]==UJUMP&&rt1[i]==31)
6628 {
6629 uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6630 }
6631 if(itype[i]==RJUMP&&rs1[i]==31)
6632 {
6633 uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6634 }
4cb76aa4 6635 if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
57871462 6636 if(itype[i]==UJUMP&&rt1[i]==31)
6637 {
6638 //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6639 uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6640 }
6641 if(itype[i]==RJUMP&&rs1[i]==31)
6642 {
6643 //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6644 uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6645 }
6646 }*/
6647 branch_unneeded_reg[i]=u;
6648 branch_unneeded_reg_upper[i]=uu;
6649 // Merge in delay slot
6650 tdep=(~uu>>rt1[i+1])&1;
6651 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6652 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6653 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6654 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6655 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6656 u|=1;uu|=1;
6657 // If branch is "likely" (and conditional)
6658 // then we skip the delay slot on the fall-thru path
6659 if(likely[i]) {
6660 if(i<slen-1) {
6661 u&=unneeded_reg[i+2];
6662 uu&=unneeded_reg_upper[i+2];
6663 }
6664 else
6665 {
6666 u=1;
6667 uu=1;
6668 }
6669 }
6670 }
6671 else
6672 {
6673 // Internal branch, flag target
6674 bt[(ba[i]-start)>>2]=1;
6675 if(ba[i]<=start+i*4) {
6676 // Backward branch
6677 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6678 {
6679 // Unconditional branch
6680 temp_u=1;temp_uu=1;
6681 } else {
6682 // Conditional branch (not taken case)
6683 temp_u=unneeded_reg[i+2];
6684 temp_uu=unneeded_reg_upper[i+2];
6685 }
6686 // Merge in delay slot
6687 tdep=(~temp_uu>>rt1[i+1])&1;
6688 temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6689 temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6690 temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6691 temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6692 temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6693 temp_u|=1;temp_uu|=1;
6694 // If branch is "likely" (and conditional)
6695 // then we skip the delay slot on the fall-thru path
6696 if(likely[i]) {
6697 if(i<slen-1) {
6698 temp_u&=unneeded_reg[i+2];
6699 temp_uu&=unneeded_reg_upper[i+2];
6700 }
6701 else
6702 {
6703 temp_u=1;
6704 temp_uu=1;
6705 }
6706 }
6707 tdep=(~temp_uu>>rt1[i])&1;
6708 temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6709 temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6710 temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6711 temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6712 temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6713 temp_u|=1;temp_uu|=1;
6714 unneeded_reg[i]=temp_u;
6715 unneeded_reg_upper[i]=temp_uu;
6716 // Only go three levels deep. This recursion can take an
6717 // excessive amount of time if there are a lot of nested loops.
6718 if(r<2) {
6719 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6720 }else{
6721 unneeded_reg[(ba[i]-start)>>2]=1;
6722 unneeded_reg_upper[(ba[i]-start)>>2]=1;
6723 }
6724 } /*else*/ if(1) {
6725 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6726 {
6727 // Unconditional branch
6728 u=unneeded_reg[(ba[i]-start)>>2];
6729 uu=unneeded_reg_upper[(ba[i]-start)>>2];
6730 branch_unneeded_reg[i]=u;
6731 branch_unneeded_reg_upper[i]=uu;
6732 //u=1;
6733 //uu=1;
6734 //branch_unneeded_reg[i]=u;
6735 //branch_unneeded_reg_upper[i]=uu;
6736 // Merge in delay slot
6737 tdep=(~uu>>rt1[i+1])&1;
6738 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6739 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6740 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6741 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6742 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6743 u|=1;uu|=1;
6744 } else {
6745 // Conditional branch
6746 b=unneeded_reg[(ba[i]-start)>>2];
6747 bu=unneeded_reg_upper[(ba[i]-start)>>2];
6748 branch_unneeded_reg[i]=b;
6749 branch_unneeded_reg_upper[i]=bu;
6750 //b=1;
6751 //bu=1;
6752 //branch_unneeded_reg[i]=b;
6753 //branch_unneeded_reg_upper[i]=bu;
6754 // Branch delay slot
6755 tdep=(~uu>>rt1[i+1])&1;
6756 b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6757 bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6758 b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6759 bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6760 bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6761 b|=1;bu|=1;
6762 // If branch is "likely" then we skip the
6763 // delay slot on the fall-thru path
6764 if(likely[i]) {
6765 u=b;
6766 uu=bu;
6767 if(i<slen-1) {
6768 u&=unneeded_reg[i+2];
6769 uu&=unneeded_reg_upper[i+2];
6770 //u=1;
6771 //uu=1;
6772 }
6773 } else {
6774 u&=b;
6775 uu&=bu;
6776 //u=1;
6777 //uu=1;
6778 }
6779 if(i<slen-1) {
6780 branch_unneeded_reg[i]&=unneeded_reg[i+2];
6781 branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6782 //branch_unneeded_reg[i]=1;
6783 //branch_unneeded_reg_upper[i]=1;
6784 } else {
6785 branch_unneeded_reg[i]=1;
6786 branch_unneeded_reg_upper[i]=1;
6787 }
6788 }
6789 }
6790 }
6791 }
1e973cb0 6792 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 6793 {
6794 // SYSCALL instruction (software interrupt)
6795 u=1;
6796 uu=1;
6797 }
6798 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6799 {
6800 // ERET instruction (return from interrupt)
6801 u=1;
6802 uu=1;
6803 }
6804 //u=uu=1; // DEBUG
6805 tdep=(~uu>>rt1[i])&1;
6806 // Written registers are unneeded
6807 u|=1LL<<rt1[i];
6808 u|=1LL<<rt2[i];
6809 uu|=1LL<<rt1[i];
6810 uu|=1LL<<rt2[i];
6811 // Accessed registers are needed
6812 u&=~(1LL<<rs1[i]);
6813 u&=~(1LL<<rs2[i]);
6814 uu&=~(1LL<<us1[i]);
6815 uu&=~(1LL<<us2[i]);
6816 // Source-target dependencies
6817 uu&=~(tdep<<dep1[i]);
6818 uu&=~(tdep<<dep2[i]);
6819 // R0 is always unneeded
6820 u|=1;uu|=1;
6821 // Save it
6822 unneeded_reg[i]=u;
6823 unneeded_reg_upper[i]=uu;
6824 /*
6825 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6826 printf("U:");
6827 int r;
6828 for(r=1;r<=CCREG;r++) {
6829 if((unneeded_reg[i]>>r)&1) {
6830 if(r==HIREG) printf(" HI");
6831 else if(r==LOREG) printf(" LO");
6832 else printf(" r%d",r);
6833 }
6834 }
6835 printf(" UU:");
6836 for(r=1;r<=CCREG;r++) {
6837 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
6838 if(r==HIREG) printf(" HI");
6839 else if(r==LOREG) printf(" LO");
6840 else printf(" r%d",r);
6841 }
6842 }
6843 printf("\n");*/
6844 }
252c20fc 6845#ifdef FORCE32
6846 for (i=iend;i>=istart;i--)
6847 {
6848 unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
6849 }
6850#endif
57871462 6851}
6852
6853// Identify registers which are likely to contain 32-bit values
6854// This is used to predict whether any branches will jump to a
6855// location with 64-bit values in registers.
6856static void provisional_32bit()
6857{
6858 int i,j;
6859 uint64_t is32=1;
6860 uint64_t lastbranch=1;
6861
6862 for(i=0;i<slen;i++)
6863 {
6864 if(i>0) {
6865 if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
6866 if(i>1) is32=lastbranch;
6867 else is32=1;
6868 }
6869 }
6870 if(i>1)
6871 {
6872 if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
6873 if(likely[i-2]) {
6874 if(i>2) is32=lastbranch;
6875 else is32=1;
6876 }
6877 }
6878 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
6879 {
6880 if(rs1[i-2]==0||rs2[i-2]==0)
6881 {
6882 if(rs1[i-2]) {
6883 is32|=1LL<<rs1[i-2];
6884 }
6885 if(rs2[i-2]) {
6886 is32|=1LL<<rs2[i-2];
6887 }
6888 }
6889 }
6890 }
6891 // If something jumps here with 64-bit values
6892 // then promote those registers to 64 bits
6893 if(bt[i])
6894 {
6895 uint64_t temp_is32=is32;
6896 for(j=i-1;j>=0;j--)
6897 {
6898 if(ba[j]==start+i*4)
6899 //temp_is32&=branch_regs[j].is32;
6900 temp_is32&=p32[j];
6901 }
6902 for(j=i;j<slen;j++)
6903 {
6904 if(ba[j]==start+i*4)
6905 temp_is32=1;
6906 }
6907 is32=temp_is32;
6908 }
6909 int type=itype[i];
6910 int op=opcode[i];
6911 int op2=opcode2[i];
6912 int rt=rt1[i];
6913 int s1=rs1[i];
6914 int s2=rs2[i];
6915 if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
6916 // Branches don't write registers, consider the delay slot instead.
6917 type=itype[i+1];
6918 op=opcode[i+1];
6919 op2=opcode2[i+1];
6920 rt=rt1[i+1];
6921 s1=rs1[i+1];
6922 s2=rs2[i+1];
6923 lastbranch=is32;
6924 }
6925 switch(type) {
6926 case LOAD:
6927 if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
6928 opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
6929 is32&=~(1LL<<rt);
6930 else
6931 is32|=1LL<<rt;
6932 break;
6933 case STORE:
6934 case STORELR:
6935 break;
6936 case LOADLR:
6937 if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
6938 if(op==0x22) is32|=1LL<<rt; // LWL
6939 break;
6940 case IMM16:
6941 if (op==0x08||op==0x09|| // ADDI/ADDIU
6942 op==0x0a||op==0x0b|| // SLTI/SLTIU
6943 op==0x0c|| // ANDI
6944 op==0x0f) // LUI
6945 {
6946 is32|=1LL<<rt;
6947 }
6948 if(op==0x18||op==0x19) { // DADDI/DADDIU
6949 is32&=~(1LL<<rt);
6950 //if(imm[i]==0)
6951 // is32|=((is32>>s1)&1LL)<<rt;
6952 }
6953 if(op==0x0d||op==0x0e) { // ORI/XORI
6954 uint64_t sr=((is32>>s1)&1LL);
6955 is32&=~(1LL<<rt);
6956 is32|=sr<<rt;
6957 }
6958 break;
6959 case UJUMP:
6960 break;
6961 case RJUMP:
6962 break;
6963 case CJUMP:
6964 break;
6965 case SJUMP:
6966 break;
6967 case FJUMP:
6968 break;
6969 case ALU:
6970 if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
6971 is32|=1LL<<rt;
6972 }
6973 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
6974 is32|=1LL<<rt;
6975 }
6976 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
6977 uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
6978 is32&=~(1LL<<rt);
6979 is32|=sr<<rt;
6980 }
6981 else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
6982 if(s1==0&&s2==0) {
6983 is32|=1LL<<rt;
6984 }
6985 else if(s2==0) {
6986 uint64_t sr=((is32>>s1)&1LL);
6987 is32&=~(1LL<<rt);
6988 is32|=sr<<rt;
6989 }
6990 else if(s1==0) {
6991 uint64_t sr=((is32>>s2)&1LL);
6992 is32&=~(1LL<<rt);
6993 is32|=sr<<rt;
6994 }
6995 else {
6996 is32&=~(1LL<<rt);
6997 }
6998 }
6999 else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
7000 if(s1==0&&s2==0) {
7001 is32|=1LL<<rt;
7002 }
7003 else if(s2==0) {
7004 uint64_t sr=((is32>>s1)&1LL);
7005 is32&=~(1LL<<rt);
7006 is32|=sr<<rt;
7007 }
7008 else {
7009 is32&=~(1LL<<rt);
7010 }
7011 }
7012 break;
7013 case MULTDIV:
7014 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
7015 is32&=~((1LL<<HIREG)|(1LL<<LOREG));
7016 }
7017 else {
7018 is32|=(1LL<<HIREG)|(1LL<<LOREG);
7019 }
7020 break;
7021 case MOV:
7022 {
7023 uint64_t sr=((is32>>s1)&1LL);
7024 is32&=~(1LL<<rt);
7025 is32|=sr<<rt;
7026 }
7027 break;
7028 case SHIFT:
7029 if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
7030 else is32|=1LL<<rt; // SLLV/SRLV/SRAV
7031 break;
7032 case SHIFTIMM:
7033 is32|=1LL<<rt;
7034 // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
7035 if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
7036 break;
7037 case COP0:
7038 if(op2==0) is32|=1LL<<rt; // MFC0
7039 break;
7040 case COP1:
b9b61529 7041 case COP2:
57871462 7042 if(op2==0) is32|=1LL<<rt; // MFC1
7043 if(op2==1) is32&=~(1LL<<rt); // DMFC1
7044 if(op2==2) is32|=1LL<<rt; // CFC1
7045 break;
7046 case C1LS:
b9b61529 7047 case C2LS:
57871462 7048 break;
7049 case FLOAT:
7050 case FCONV:
7051 break;
7052 case FCOMP:
7053 break;
b9b61529 7054 case C2OP:
57871462 7055 case SYSCALL:
7139f3c8 7056 case HLECALL:
57871462 7057 break;
7058 default:
7059 break;
7060 }
7061 is32|=1;
7062 p32[i]=is32;
7063
7064 if(i>0)
7065 {
7066 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
7067 {
7068 if(rt1[i-1]==31) // JAL/JALR
7069 {
7070 // Subroutine call will return here, don't alloc any registers
7071 is32=1;
7072 }
7073 else if(i+1<slen)
7074 {
7075 // Internal branch will jump here, match registers to caller
7076 is32=0x3FFFFFFFFLL;
7077 }
7078 }
7079 }
7080 }
7081}
7082
7083// Identify registers which may be assumed to contain 32-bit values
7084// and where optimizations will rely on this.
7085// This is used to determine whether backward branches can safely
7086// jump to a location with 64-bit values in registers.
7087static void provisional_r32()
7088{
7089 u_int r32=0;
7090 int i;
7091
7092 for (i=slen-1;i>=0;i--)
7093 {
7094 int hr;
7095 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7096 {
7097 if(ba[i]<start || ba[i]>=(start+slen*4))
7098 {
7099 // Branch out of this block, don't need anything
7100 r32=0;
7101 }
7102 else
7103 {
7104 // Internal branch
7105 // Need whatever matches the target
7106 // (and doesn't get overwritten by the delay slot instruction)
7107 r32=0;
7108 int t=(ba[i]-start)>>2;
7109 if(ba[i]>start+i*4) {
7110 // Forward branch
7111 //if(!(requires_32bit[t]&~regs[i].was32))
7112 // r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7113 if(!(pr32[t]&~regs[i].was32))
7114 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7115 }else{
7116 // Backward branch
7117 if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
7118 r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7119 }
7120 }
7121 // Conditional branch may need registers for following instructions
7122 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7123 {
7124 if(i<slen-2) {
7125 //r32|=requires_32bit[i+2];
7126 r32|=pr32[i+2];
7127 r32&=regs[i].was32;
7128 // Mark this address as a branch target since it may be called
7129 // upon return from interrupt
7130 //bt[i+2]=1;
7131 }
7132 }
7133 // Merge in delay slot
7134 if(!likely[i]) {
7135 // These are overwritten unless the branch is "likely"
7136 // and the delay slot is nullified if not taken
7137 r32&=~(1LL<<rt1[i+1]);
7138 r32&=~(1LL<<rt2[i+1]);
7139 }
7140 // Assume these are needed (delay slot)
7141 if(us1[i+1]>0)
7142 {
7143 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7144 }
7145 if(us2[i+1]>0)
7146 {
7147 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7148 }
7149 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7150 {
7151 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7152 }
7153 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7154 {
7155 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7156 }
7157 }
1e973cb0 7158 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 7159 {
7160 // SYSCALL instruction (software interrupt)
7161 r32=0;
7162 }
7163 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7164 {
7165 // ERET instruction (return from interrupt)
7166 r32=0;
7167 }
7168 // Check 32 bits
7169 r32&=~(1LL<<rt1[i]);
7170 r32&=~(1LL<<rt2[i]);
7171 if(us1[i]>0)
7172 {
7173 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7174 }
7175 if(us2[i]>0)
7176 {
7177 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7178 }
7179 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7180 {
7181 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7182 }
7183 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7184 {
7185 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7186 }
7187 //requires_32bit[i]=r32;
7188 pr32[i]=r32;
7189
7190 // Dirty registers which are 32-bit, require 32-bit input
7191 // as they will be written as 32-bit values
7192 for(hr=0;hr<HOST_REGS;hr++)
7193 {
7194 if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
7195 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7196 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7197 pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7198 //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7199 }
7200 }
7201 }
7202 }
7203}
7204
7205// Write back dirty registers as soon as we will no longer modify them,
7206// so that we don't end up with lots of writes at the branches.
7207void clean_registers(int istart,int iend,int wr)
7208{
7209 int i;
7210 int r;
7211 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7212 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7213 if(iend==slen-1) {
7214 will_dirty_i=will_dirty_next=0;
7215 wont_dirty_i=wont_dirty_next=0;
7216 }else{
7217 will_dirty_i=will_dirty_next=will_dirty[iend+1];
7218 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7219 }
7220 for (i=iend;i>=istart;i--)
7221 {
7222 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7223 {
7224 if(ba[i]<start || ba[i]>=(start+slen*4))
7225 {
7226 // Branch out of this block, flush all regs
7227 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7228 {
7229 // Unconditional branch
7230 will_dirty_i=0;
7231 wont_dirty_i=0;
7232 // Merge in delay slot (will dirty)
7233 for(r=0;r<HOST_REGS;r++) {
7234 if(r!=EXCLUDE_REG) {
7235 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7236 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7237 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7238 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7239 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7240 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7241 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7242 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7243 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7244 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7245 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7246 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7247 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7248 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7249 }
7250 }
7251 }
7252 else
7253 {
7254 // Conditional branch
7255 will_dirty_i=0;
7256 wont_dirty_i=wont_dirty_next;
7257 // Merge in delay slot (will dirty)
7258 for(r=0;r<HOST_REGS;r++) {
7259 if(r!=EXCLUDE_REG) {
7260 if(!likely[i]) {
7261 // Might not dirty if likely branch is not taken
7262 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7263 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7264 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7265 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7266 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7267 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7268 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7269 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7270 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7271 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7272 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7273 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7274 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7275 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7276 }
7277 }
7278 }
7279 }
7280 // Merge in delay slot (wont dirty)
7281 for(r=0;r<HOST_REGS;r++) {
7282 if(r!=EXCLUDE_REG) {
7283 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7284 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7285 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7286 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7287 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7288 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7289 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7290 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7291 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7292 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7293 }
7294 }
7295 if(wr) {
7296 #ifndef DESTRUCTIVE_WRITEBACK
7297 branch_regs[i].dirty&=wont_dirty_i;
7298 #endif
7299 branch_regs[i].dirty|=will_dirty_i;
7300 }
7301 }
7302 else
7303 {
7304 // Internal branch
7305 if(ba[i]<=start+i*4) {
7306 // Backward branch
7307 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7308 {
7309 // Unconditional branch
7310 temp_will_dirty=0;
7311 temp_wont_dirty=0;
7312 // Merge in delay slot (will dirty)
7313 for(r=0;r<HOST_REGS;r++) {
7314 if(r!=EXCLUDE_REG) {
7315 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7316 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7317 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7318 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7319 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7320 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7321 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7322 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7323 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7324 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7325 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7326 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7327 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7328 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7329 }
7330 }
7331 } else {
7332 // Conditional branch (not taken case)
7333 temp_will_dirty=will_dirty_next;
7334 temp_wont_dirty=wont_dirty_next;
7335 // Merge in delay slot (will dirty)
7336 for(r=0;r<HOST_REGS;r++) {
7337 if(r!=EXCLUDE_REG) {
7338 if(!likely[i]) {
7339 // Will not dirty if likely branch is not taken
7340 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7341 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7342 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7343 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7344 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7345 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7346 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7347 //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7348 //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7349 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7350 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7351 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7352 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7353 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7354 }
7355 }
7356 }
7357 }
7358 // Merge in delay slot (wont dirty)
7359 for(r=0;r<HOST_REGS;r++) {
7360 if(r!=EXCLUDE_REG) {
7361 if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7362 if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7363 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7364 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7365 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7366 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7367 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7368 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7369 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7370 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7371 }
7372 }
7373 // Deal with changed mappings
7374 if(i<iend) {
7375 for(r=0;r<HOST_REGS;r++) {
7376 if(r!=EXCLUDE_REG) {
7377 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7378 temp_will_dirty&=~(1<<r);
7379 temp_wont_dirty&=~(1<<r);
7380 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7381 temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7382 temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7383 } else {
7384 temp_will_dirty|=1<<r;
7385 temp_wont_dirty|=1<<r;
7386 }
7387 }
7388 }
7389 }
7390 }
7391 if(wr) {
7392 will_dirty[i]=temp_will_dirty;
7393 wont_dirty[i]=temp_wont_dirty;
7394 clean_registers((ba[i]-start)>>2,i-1,0);
7395 }else{
7396 // Limit recursion. It can take an excessive amount
7397 // of time if there are a lot of nested loops.
7398 will_dirty[(ba[i]-start)>>2]=0;
7399 wont_dirty[(ba[i]-start)>>2]=-1;
7400 }
7401 }
7402 /*else*/ if(1)
7403 {
7404 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7405 {
7406 // Unconditional branch
7407 will_dirty_i=0;
7408 wont_dirty_i=0;
7409 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7410 for(r=0;r<HOST_REGS;r++) {
7411 if(r!=EXCLUDE_REG) {
7412 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7413 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7414 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7415 }
7416 }
7417 }
7418 //}
7419 // Merge in delay slot
7420 for(r=0;r<HOST_REGS;r++) {
7421 if(r!=EXCLUDE_REG) {
7422 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7423 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7424 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7425 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7426 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7427 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7428 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7429 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7430 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7431 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7432 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7433 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7434 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7435 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7436 }
7437 }
7438 } else {
7439 // Conditional branch
7440 will_dirty_i=will_dirty_next;
7441 wont_dirty_i=wont_dirty_next;
7442 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7443 for(r=0;r<HOST_REGS;r++) {
7444 if(r!=EXCLUDE_REG) {
7445 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7446 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7447 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7448 }
7449 else
7450 {
7451 will_dirty_i&=~(1<<r);
7452 }
7453 // Treat delay slot as part of branch too
7454 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7455 will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7456 wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7457 }
7458 else
7459 {
7460 will_dirty[i+1]&=~(1<<r);
7461 }*/
7462 }
7463 }
7464 //}
7465 // Merge in delay slot
7466 for(r=0;r<HOST_REGS;r++) {
7467 if(r!=EXCLUDE_REG) {
7468 if(!likely[i]) {
7469 // Might not dirty if likely branch is not taken
7470 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7471 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7472 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7473 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7474 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7475 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7476 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7477 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7478 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7479 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7480 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7481 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7482 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7483 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7484 }
7485 }
7486 }
7487 }
7488 // Merge in delay slot
7489 for(r=0;r<HOST_REGS;r++) {
7490 if(r!=EXCLUDE_REG) {
7491 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7492 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7493 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7494 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7495 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7496 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7497 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7498 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7499 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7500 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7501 }
7502 }
7503 if(wr) {
7504 #ifndef DESTRUCTIVE_WRITEBACK
7505 branch_regs[i].dirty&=wont_dirty_i;
7506 #endif
7507 branch_regs[i].dirty|=will_dirty_i;
7508 }
7509 }
7510 }
7511 }
1e973cb0 7512 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 7513 {
7514 // SYSCALL instruction (software interrupt)
7515 will_dirty_i=0;
7516 wont_dirty_i=0;
7517 }
7518 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7519 {
7520 // ERET instruction (return from interrupt)
7521 will_dirty_i=0;
7522 wont_dirty_i=0;
7523 }
7524 will_dirty_next=will_dirty_i;
7525 wont_dirty_next=wont_dirty_i;
7526 for(r=0;r<HOST_REGS;r++) {
7527 if(r!=EXCLUDE_REG) {
7528 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7529 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7530 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7531 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7532 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7533 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7534 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7535 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7536 if(i>istart) {
7537 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7538 {
7539 // Don't store a register immediately after writing it,
7540 // may prevent dual-issue.
7541 if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7542 if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7543 }
7544 }
7545 }
7546 }
7547 // Save it
7548 will_dirty[i]=will_dirty_i;
7549 wont_dirty[i]=wont_dirty_i;
7550 // Mark registers that won't be dirtied as not dirty
7551 if(wr) {
7552 /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7553 for(r=0;r<HOST_REGS;r++) {
7554 if((will_dirty_i>>r)&1) {
7555 printf(" r%d",r);
7556 }
7557 }
7558 printf("\n");*/
7559
7560 //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7561 regs[i].dirty|=will_dirty_i;
7562 #ifndef DESTRUCTIVE_WRITEBACK
7563 regs[i].dirty&=wont_dirty_i;
7564 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7565 {
7566 if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7567 for(r=0;r<HOST_REGS;r++) {
7568 if(r!=EXCLUDE_REG) {
7569 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7570 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7571 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7572 }
7573 }
7574 }
7575 }
7576 else
7577 {
7578 if(i<iend) {
7579 for(r=0;r<HOST_REGS;r++) {
7580 if(r!=EXCLUDE_REG) {
7581 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7582 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7583 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7584 }
7585 }
7586 }
7587 }
7588 #endif
7589 //}
7590 }
7591 // Deal with changed mappings
7592 temp_will_dirty=will_dirty_i;
7593 temp_wont_dirty=wont_dirty_i;
7594 for(r=0;r<HOST_REGS;r++) {
7595 if(r!=EXCLUDE_REG) {
7596 int nr;
7597 if(regs[i].regmap[r]==regmap_pre[i][r]) {
7598 if(wr) {
7599 #ifndef DESTRUCTIVE_WRITEBACK
7600 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7601 #endif
7602 regs[i].wasdirty|=will_dirty_i&(1<<r);
7603 }
7604 }
7605 else if((nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7606 // Register moved to a different register
7607 will_dirty_i&=~(1<<r);
7608 wont_dirty_i&=~(1<<r);
7609 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7610 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7611 if(wr) {
7612 #ifndef DESTRUCTIVE_WRITEBACK
7613 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7614 #endif
7615 regs[i].wasdirty|=will_dirty_i&(1<<r);
7616 }
7617 }
7618 else {
7619 will_dirty_i&=~(1<<r);
7620 wont_dirty_i&=~(1<<r);
7621 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7622 will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7623 wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7624 } else {
7625 wont_dirty_i|=1<<r;
7626 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7627 }
7628 }
7629 }
7630 }
7631 }
7632}
7633
7634 /* disassembly */
7635void disassemble_inst(int i)
7636{
7637 if (bt[i]) printf("*"); else printf(" ");
7638 switch(itype[i]) {
7639 case UJUMP:
7640 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7641 case CJUMP:
7642 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7643 case SJUMP:
7644 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7645 case FJUMP:
7646 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7647 case RJUMP:
74426039 7648 if (opcode[i]==0x9&&rt1[i]!=31)
5067f341 7649 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7650 else
7651 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7652 break;
57871462 7653 case SPAN:
7654 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7655 case IMM16:
7656 if(opcode[i]==0xf) //LUI
7657 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7658 else
7659 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7660 break;
7661 case LOAD:
7662 case LOADLR:
7663 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7664 break;
7665 case STORE:
7666 case STORELR:
7667 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7668 break;
7669 case ALU:
7670 case SHIFT:
7671 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7672 break;
7673 case MULTDIV:
7674 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7675 break;
7676 case SHIFTIMM:
7677 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7678 break;
7679 case MOV:
7680 if((opcode2[i]&0x1d)==0x10)
7681 printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7682 else if((opcode2[i]&0x1d)==0x11)
7683 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7684 else
7685 printf (" %x: %s\n",start+i*4,insn[i]);
7686 break;
7687 case COP0:
7688 if(opcode2[i]==0)
7689 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7690 else if(opcode2[i]==4)
7691 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7692 else printf (" %x: %s\n",start+i*4,insn[i]);
7693 break;
7694 case COP1:
7695 if(opcode2[i]<3)
7696 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7697 else if(opcode2[i]>3)
7698 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7699 else printf (" %x: %s\n",start+i*4,insn[i]);
7700 break;
b9b61529 7701 case COP2:
7702 if(opcode2[i]<3)
7703 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7704 else if(opcode2[i]>3)
7705 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7706 else printf (" %x: %s\n",start+i*4,insn[i]);
7707 break;
57871462 7708 case C1LS:
7709 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7710 break;
b9b61529 7711 case C2LS:
7712 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7713 break;
1e973cb0 7714 case INTCALL:
7715 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
7716 break;
57871462 7717 default:
7718 //printf (" %s %8x\n",insn[i],source[i]);
7719 printf (" %x: %s\n",start+i*4,insn[i]);
7720 }
7721}
7722
dc990066 7723// clear the state completely, instead of just marking
7724// things invalid like invalidate_all_pages() does
7725void new_dynarec_clear_full()
57871462 7726{
57871462 7727 int n;
7728 for(n=0x80000;n<0x80800;n++)
7729 invalid_code[n]=1;
7730 for(n=0;n<65536;n++)
7731 hash_table[n][0]=hash_table[n][2]=-1;
7732 memset(mini_ht,-1,sizeof(mini_ht));
7733 memset(restore_candidate,0,sizeof(restore_candidate));
dc990066 7734 memset(shadow,0,sizeof(shadow));
57871462 7735 copy=shadow;
7736 expirep=16384; // Expiry pointer, +2 blocks
7737 pending_exception=0;
7738 literalcount=0;
57871462 7739 stop_after_jal=0;
7740 // TLB
af4ee1fe 7741#ifndef DISABLE_TLB
57871462 7742 using_tlb=0;
af4ee1fe 7743#endif
57871462 7744 for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7745 memory_map[n]=-1;
7746 for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7747 memory_map[n]=((u_int)rdram-0x80000000)>>2;
7748 for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7749 memory_map[n]=-1;
dc990066 7750 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7751 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7752 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7753}
7754
7755void new_dynarec_init()
7756{
7757 printf("Init new dynarec\n");
7758 out=(u_char *)BASE_ADDR;
7759 if (mmap (out, 1<<TARGET_SIZE_2,
7760 PROT_READ | PROT_WRITE | PROT_EXEC,
7761 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
7762 -1, 0) <= 0) {printf("mmap() failed\n");}
7763#ifdef MUPEN64
7764 rdword=&readmem_dword;
7765 fake_pc.f.r.rs=&readmem_dword;
7766 fake_pc.f.r.rt=&readmem_dword;
7767 fake_pc.f.r.rd=&readmem_dword;
7768#endif
7769 int n;
7770 new_dynarec_clear_full();
7771#ifdef HOST_IMM8
7772 // Copy this into local area so we don't have to put it in every literal pool
7773 invc_ptr=invalid_code;
7774#endif
24385cae 7775#ifdef MUPEN64
57871462 7776 for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
7777 writemem[n] = write_nomem_new;
7778 writememb[n] = write_nomemb_new;
7779 writememh[n] = write_nomemh_new;
24385cae 7780#ifndef FORCE32
57871462 7781 writememd[n] = write_nomemd_new;
24385cae 7782#endif
57871462 7783 readmem[n] = read_nomem_new;
7784 readmemb[n] = read_nomemb_new;
7785 readmemh[n] = read_nomemh_new;
24385cae 7786#ifndef FORCE32
57871462 7787 readmemd[n] = read_nomemd_new;
24385cae 7788#endif
57871462 7789 }
7790 for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
7791 writemem[n] = write_rdram_new;
7792 writememb[n] = write_rdramb_new;
7793 writememh[n] = write_rdramh_new;
24385cae 7794#ifndef FORCE32
57871462 7795 writememd[n] = write_rdramd_new;
24385cae 7796#endif
57871462 7797 }
7798 for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
7799 writemem[n] = write_nomem_new;
7800 writememb[n] = write_nomemb_new;
7801 writememh[n] = write_nomemh_new;
24385cae 7802#ifndef FORCE32
57871462 7803 writememd[n] = write_nomemd_new;
24385cae 7804#endif
57871462 7805 readmem[n] = read_nomem_new;
7806 readmemb[n] = read_nomemb_new;
7807 readmemh[n] = read_nomemh_new;
24385cae 7808#ifndef FORCE32
57871462 7809 readmemd[n] = read_nomemd_new;
24385cae 7810#endif
57871462 7811 }
24385cae 7812#endif
57871462 7813 tlb_hacks();
7814 arch_init();
7815}
7816
7817void new_dynarec_cleanup()
7818{
7819 int n;
7820 if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
7821 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7822 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7823 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7824 #ifdef ROM_COPY
7825 if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
7826 #endif
7827}
7828
7829int new_recompile_block(int addr)
7830{
7831/*
7832 if(addr==0x800cd050) {
7833 int block;
7834 for(block=0x80000;block<0x80800;block++) invalidate_block(block);
7835 int n;
7836 for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
7837 }
7838*/
7839 //if(Count==365117028) tracedebug=1;
7840 assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7841 //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7842 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
7843 //if(debug)
7844 //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
7845 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
7846 /*if(Count>=312978186) {
7847 rlist();
7848 }*/
7849 //rlist();
7850 start = (u_int)addr&~3;
7851 //assert(((u_int)addr&1)==0);
7139f3c8 7852#ifdef PCSX
9ad4d757 7853 if (Config.HLE && start == 0x80001000) // hlecall
560e4a12 7854 {
7139f3c8 7855 // XXX: is this enough? Maybe check hleSoftCall?
bb5285ef 7856 u_int beginning=(u_int)out;
7139f3c8 7857 u_int page=get_page(start);
7139f3c8 7858 invalid_code[start>>12]=0;
7859 emit_movimm(start,0);
7860 emit_writeword(0,(int)&pcaddr);
bb5285ef 7861 emit_jmp((int)new_dyna_leave);
7862#ifdef __arm__
7863 __clear_cache((void *)beginning,out);
7864#endif
9ad4d757 7865 ll_add(jump_in+page,start,(void *)beginning);
7139f3c8 7866 return 0;
7867 }
560e4a12 7868 else if ((u_int)addr < 0x00200000 ||
7869 (0xa0000000 <= addr && addr < 0xa0200000)) {
7139f3c8 7870 // used for BIOS calls mostly?
560e4a12 7871 source = (u_int *)((u_int)rdram+(start&0x1fffff));
7872 pagelimit = (addr&0xa0000000)|0x00200000;
7873 }
7874 else if (!Config.HLE && (
7875/* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
7876 (0xbfc00000 <= addr && addr < 0xbfc80000))) {
7877 // BIOS
7878 source = (u_int *)((u_int)psxR+(start&0x7ffff));
7879 pagelimit = (addr&0xfff00000)|0x80000;
7139f3c8 7880 }
7881 else
7882#endif
3d624f89 7883#ifdef MUPEN64
57871462 7884 if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
7885 source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
7886 pagelimit = 0xa4001000;
7887 }
3d624f89 7888 else
7889#endif
4cb76aa4 7890 if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
57871462 7891 source = (u_int *)((u_int)rdram+start-0x80000000);
4cb76aa4 7892 pagelimit = 0x80000000+RAM_SIZE;
57871462 7893 }
90ae6d4e 7894#ifndef DISABLE_TLB
57871462 7895 else if ((signed int)addr >= (signed int)0xC0000000) {
7896 //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
7897 //if(tlb_LUT_r[start>>12])
7898 //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
7899 if((signed int)memory_map[start>>12]>=0) {
7900 source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
7901 pagelimit=(start+4096)&0xFFFFF000;
7902 int map=memory_map[start>>12];
7903 int i;
7904 for(i=0;i<5;i++) {
7905 //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
7906 if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
7907 }
7908 assem_debug("pagelimit=%x\n",pagelimit);
7909 assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
7910 }
7911 else {
7912 assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
7913 //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
560e4a12 7914 return -1; // Caller will invoke exception handler
57871462 7915 }
7916 //printf("source= %x\n",(int)source);
7917 }
90ae6d4e 7918#endif
57871462 7919 else {
7920 printf("Compile at bogus memory address: %x \n", (int)addr);
7921 exit(1);
7922 }
7923
7924 /* Pass 1: disassemble */
7925 /* Pass 2: register dependencies, branch targets */
7926 /* Pass 3: register allocation */
7927 /* Pass 4: branch dependencies */
7928 /* Pass 5: pre-alloc */
7929 /* Pass 6: optimize clean/dirty state */
7930 /* Pass 7: flag 32-bit registers */
7931 /* Pass 8: assembly */
7932 /* Pass 9: linker */
7933 /* Pass 10: garbage collection / free memory */
7934
7935 int i,j;
7936 int done=0;
7937 unsigned int type,op,op2;
7938
7939 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
7940
7941 /* Pass 1 disassembly */
7942
7943 for(i=0;!done;i++) {
e1190b87 7944 bt[i]=0;likely[i]=0;ooo[i]=0;op2=0;
7945 minimum_free_regs[i]=0;
57871462 7946 opcode[i]=op=source[i]>>26;
7947 switch(op)
7948 {
7949 case 0x00: strcpy(insn[i],"special"); type=NI;
7950 op2=source[i]&0x3f;
7951 switch(op2)
7952 {
7953 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
7954 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
7955 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
7956 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
7957 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
7958 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
7959 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
7960 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
7961 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
7962 case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
7963 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
7964 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
7965 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
7966 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
7967 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
7968 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
7969 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
7970 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
7971 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
7972 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
7973 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
7974 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
7975 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
7976 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
7977 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
7978 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
7979 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
7980 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
7981 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
7982 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
7983 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
7984 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
7985 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
7986 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
7987 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
7988 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
7989 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
7990 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
7991 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
7992 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
7993 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
7994 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
7995 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
7996 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
7997 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
7998 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
7999 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
8000 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
8001 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
8002 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
8003 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
8004 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
8005 }
8006 break;
8007 case 0x01: strcpy(insn[i],"regimm"); type=NI;
8008 op2=(source[i]>>16)&0x1f;
8009 switch(op2)
8010 {
8011 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
8012 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
8013 case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
8014 case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
8015 case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
8016 case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
8017 case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
8018 case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
8019 case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
8020 case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
8021 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
8022 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
8023 case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
8024 case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
8025 }
8026 break;
8027 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
8028 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
8029 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
8030 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
8031 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
8032 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
8033 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
8034 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
8035 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
8036 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
8037 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
8038 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
8039 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
8040 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
8041 case 0x10: strcpy(insn[i],"cop0"); type=NI;
8042 op2=(source[i]>>21)&0x1f;
8043 switch(op2)
8044 {
8045 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
8046 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
8047 case 0x10: strcpy(insn[i],"tlb"); type=NI;
8048 switch(source[i]&0x3f)
8049 {
8050 case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
8051 case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
8052 case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
8053 case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
576bbd8f 8054#ifdef PCSX
8055 case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
8056#else
57871462 8057 case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
576bbd8f 8058#endif
57871462 8059 }
8060 }
8061 break;
8062 case 0x11: strcpy(insn[i],"cop1"); type=NI;
8063 op2=(source[i]>>21)&0x1f;
8064 switch(op2)
8065 {
8066 case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
8067 case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
8068 case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
8069 case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
8070 case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
8071 case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
8072 case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
8073 switch((source[i]>>16)&0x3)
8074 {
8075 case 0x00: strcpy(insn[i],"BC1F"); break;
8076 case 0x01: strcpy(insn[i],"BC1T"); break;
8077 case 0x02: strcpy(insn[i],"BC1FL"); break;
8078 case 0x03: strcpy(insn[i],"BC1TL"); break;
8079 }
8080 break;
8081 case 0x10: strcpy(insn[i],"C1.S"); type=NI;
8082 switch(source[i]&0x3f)
8083 {
8084 case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
8085 case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
8086 case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
8087 case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
8088 case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
8089 case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
8090 case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
8091 case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
8092 case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
8093 case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
8094 case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
8095 case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
8096 case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
8097 case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
8098 case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
8099 case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
8100 case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
8101 case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
8102 case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
8103 case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
8104 case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
8105 case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
8106 case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
8107 case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
8108 case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
8109 case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
8110 case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
8111 case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
8112 case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
8113 case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
8114 case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
8115 case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
8116 case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
8117 case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
8118 case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
8119 }
8120 break;
8121 case 0x11: strcpy(insn[i],"C1.D"); type=NI;
8122 switch(source[i]&0x3f)
8123 {
8124 case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
8125 case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
8126 case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
8127 case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
8128 case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
8129 case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
8130 case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
8131 case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
8132 case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
8133 case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
8134 case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
8135 case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
8136 case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
8137 case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
8138 case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
8139 case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
8140 case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
8141 case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
8142 case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
8143 case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
8144 case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
8145 case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
8146 case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
8147 case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
8148 case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
8149 case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
8150 case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
8151 case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
8152 case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
8153 case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
8154 case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8155 case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8156 case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8157 case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8158 case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8159 }
8160 break;
8161 case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8162 switch(source[i]&0x3f)
8163 {
8164 case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8165 case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8166 }
8167 break;
8168 case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8169 switch(source[i]&0x3f)
8170 {
8171 case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8172 case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8173 }
8174 break;
8175 }
8176 break;
909168d6 8177#ifndef FORCE32
57871462 8178 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8179 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8180 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8181 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8182 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8183 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8184 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8185 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
996cc15d 8186#endif
57871462 8187 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8188 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8189 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8190 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8191 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8192 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8193 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
8194 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
8195 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8196 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8197 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8198 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
996cc15d 8199#ifndef FORCE32
57871462 8200 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8201 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
996cc15d 8202#endif
57871462 8203 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8204 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8205 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8206 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
996cc15d 8207#ifndef FORCE32
57871462 8208 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8209 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8210 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
996cc15d 8211#endif
57871462 8212 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8213 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
996cc15d 8214#ifndef FORCE32
57871462 8215 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8216 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8217 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
996cc15d 8218#endif
b9b61529 8219#ifdef PCSX
8220 case 0x12: strcpy(insn[i],"COP2"); type=NI;
c7abc864 8221 // note: COP MIPS-1 encoding differs from MIPS32
b9b61529 8222 op2=(source[i]>>21)&0x1f;
c7abc864 8223 if (source[i]&0x3f) {
8224 if (gte_handlers[source[i]&0x3f]!=NULL) {
8225 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8226 type=C2OP;
8227 }
8228 }
8229 else switch(op2)
b9b61529 8230 {
8231 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8232 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8233 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8234 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
b9b61529 8235 }
8236 break;
8237 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8238 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8239 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8240#endif
90ae6d4e 8241 default: strcpy(insn[i],"???"); type=NI;
75dec299 8242 printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
90ae6d4e 8243 break;
57871462 8244 }
8245 itype[i]=type;
8246 opcode2[i]=op2;
8247 /* Get registers/immediates */
8248 lt1[i]=0;
8249 us1[i]=0;
8250 us2[i]=0;
8251 dep1[i]=0;
8252 dep2[i]=0;
8253 switch(type) {
8254 case LOAD:
8255 rs1[i]=(source[i]>>21)&0x1f;
8256 rs2[i]=0;
8257 rt1[i]=(source[i]>>16)&0x1f;
8258 rt2[i]=0;
8259 imm[i]=(short)source[i];
8260 break;
8261 case STORE:
8262 case STORELR:
8263 rs1[i]=(source[i]>>21)&0x1f;
8264 rs2[i]=(source[i]>>16)&0x1f;
8265 rt1[i]=0;
8266 rt2[i]=0;
8267 imm[i]=(short)source[i];
8268 if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8269 break;
8270 case LOADLR:
8271 // LWL/LWR only load part of the register,
8272 // therefore the target register must be treated as a source too
8273 rs1[i]=(source[i]>>21)&0x1f;
8274 rs2[i]=(source[i]>>16)&0x1f;
8275 rt1[i]=(source[i]>>16)&0x1f;
8276 rt2[i]=0;
8277 imm[i]=(short)source[i];
8278 if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8279 if(op==0x26) dep1[i]=rt1[i]; // LWR
8280 break;
8281 case IMM16:
8282 if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8283 else rs1[i]=(source[i]>>21)&0x1f;
8284 rs2[i]=0;
8285 rt1[i]=(source[i]>>16)&0x1f;
8286 rt2[i]=0;
8287 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8288 imm[i]=(unsigned short)source[i];
8289 }else{
8290 imm[i]=(short)source[i];
8291 }
8292 if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8293 if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8294 if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8295 break;
8296 case UJUMP:
8297 rs1[i]=0;
8298 rs2[i]=0;
8299 rt1[i]=0;
8300 rt2[i]=0;
8301 // The JAL instruction writes to r31.
8302 if (op&1) {
8303 rt1[i]=31;
8304 }
8305 rs2[i]=CCREG;
8306 break;
8307 case RJUMP:
8308 rs1[i]=(source[i]>>21)&0x1f;
8309 rs2[i]=0;
8310 rt1[i]=0;
8311 rt2[i]=0;
5067f341 8312 // The JALR instruction writes to rd.
57871462 8313 if (op2&1) {
5067f341 8314 rt1[i]=(source[i]>>11)&0x1f;
57871462 8315 }
8316 rs2[i]=CCREG;
8317 break;
8318 case CJUMP:
8319 rs1[i]=(source[i]>>21)&0x1f;
8320 rs2[i]=(source[i]>>16)&0x1f;
8321 rt1[i]=0;
8322 rt2[i]=0;
8323 if(op&2) { // BGTZ/BLEZ
8324 rs2[i]=0;
8325 }
8326 us1[i]=rs1[i];
8327 us2[i]=rs2[i];
8328 likely[i]=op>>4;
8329 break;
8330 case SJUMP:
8331 rs1[i]=(source[i]>>21)&0x1f;
8332 rs2[i]=CCREG;
8333 rt1[i]=0;
8334 rt2[i]=0;
8335 us1[i]=rs1[i];
8336 if(op2&0x10) { // BxxAL
8337 rt1[i]=31;
8338 // NOTE: If the branch is not taken, r31 is still overwritten
8339 }
8340 likely[i]=(op2&2)>>1;
8341 break;
8342 case FJUMP:
8343 rs1[i]=FSREG;
8344 rs2[i]=CSREG;
8345 rt1[i]=0;
8346 rt2[i]=0;
8347 likely[i]=((source[i])>>17)&1;
8348 break;
8349 case ALU:
8350 rs1[i]=(source[i]>>21)&0x1f; // source
8351 rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8352 rt1[i]=(source[i]>>11)&0x1f; // destination
8353 rt2[i]=0;
8354 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8355 us1[i]=rs1[i];us2[i]=rs2[i];
8356 }
8357 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8358 dep1[i]=rs1[i];dep2[i]=rs2[i];
8359 }
8360 else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8361 dep1[i]=rs1[i];dep2[i]=rs2[i];
8362 }
8363 break;
8364 case MULTDIV:
8365 rs1[i]=(source[i]>>21)&0x1f; // source
8366 rs2[i]=(source[i]>>16)&0x1f; // divisor
8367 rt1[i]=HIREG;
8368 rt2[i]=LOREG;
8369 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8370 us1[i]=rs1[i];us2[i]=rs2[i];
8371 }
8372 break;
8373 case MOV:
8374 rs1[i]=0;
8375 rs2[i]=0;
8376 rt1[i]=0;
8377 rt2[i]=0;
8378 if(op2==0x10) rs1[i]=HIREG; // MFHI
8379 if(op2==0x11) rt1[i]=HIREG; // MTHI
8380 if(op2==0x12) rs1[i]=LOREG; // MFLO
8381 if(op2==0x13) rt1[i]=LOREG; // MTLO
8382 if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8383 if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8384 dep1[i]=rs1[i];
8385 break;
8386 case SHIFT:
8387 rs1[i]=(source[i]>>16)&0x1f; // target of shift
8388 rs2[i]=(source[i]>>21)&0x1f; // shift amount
8389 rt1[i]=(source[i]>>11)&0x1f; // destination
8390 rt2[i]=0;
8391 // DSLLV/DSRLV/DSRAV are 64-bit
8392 if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8393 break;
8394 case SHIFTIMM:
8395 rs1[i]=(source[i]>>16)&0x1f;
8396 rs2[i]=0;
8397 rt1[i]=(source[i]>>11)&0x1f;
8398 rt2[i]=0;
8399 imm[i]=(source[i]>>6)&0x1f;
8400 // DSxx32 instructions
8401 if(op2>=0x3c) imm[i]|=0x20;
8402 // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8403 if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8404 break;
8405 case COP0:
8406 rs1[i]=0;
8407 rs2[i]=0;
8408 rt1[i]=0;
8409 rt2[i]=0;
8410 if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8411 if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8412 if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8413 if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8414 break;
8415 case COP1:
b9b61529 8416 case COP2:
57871462 8417 rs1[i]=0;
8418 rs2[i]=0;
8419 rt1[i]=0;
8420 rt2[i]=0;
8421 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8422 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8423 if(op2==5) us1[i]=rs1[i]; // DMTC1
8424 rs2[i]=CSREG;
8425 break;
8426 case C1LS:
8427 rs1[i]=(source[i]>>21)&0x1F;
8428 rs2[i]=CSREG;
8429 rt1[i]=0;
8430 rt2[i]=0;
8431 imm[i]=(short)source[i];
8432 break;
b9b61529 8433 case C2LS:
8434 rs1[i]=(source[i]>>21)&0x1F;
8435 rs2[i]=0;
8436 rt1[i]=0;
8437 rt2[i]=0;
8438 imm[i]=(short)source[i];
8439 break;
57871462 8440 case FLOAT:
8441 case FCONV:
8442 rs1[i]=0;
8443 rs2[i]=CSREG;
8444 rt1[i]=0;
8445 rt2[i]=0;
8446 break;
8447 case FCOMP:
8448 rs1[i]=FSREG;
8449 rs2[i]=CSREG;
8450 rt1[i]=FSREG;
8451 rt2[i]=0;
8452 break;
8453 case SYSCALL:
7139f3c8 8454 case HLECALL:
1e973cb0 8455 case INTCALL:
57871462 8456 rs1[i]=CCREG;
8457 rs2[i]=0;
8458 rt1[i]=0;
8459 rt2[i]=0;
8460 break;
8461 default:
8462 rs1[i]=0;
8463 rs2[i]=0;
8464 rt1[i]=0;
8465 rt2[i]=0;
8466 }
8467 /* Calculate branch target addresses */
8468 if(type==UJUMP)
8469 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8470 else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8471 ba[i]=start+i*4+8; // Ignore never taken branch
8472 else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8473 ba[i]=start+i*4+8; // Ignore never taken branch
8474 else if(type==CJUMP||type==SJUMP||type==FJUMP)
8475 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8476 else ba[i]=-1;
26869094 8477#ifdef PCSX
3e535354 8478 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
8479 int do_in_intrp=0;
8480 // branch in delay slot?
8481 if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
8482 // don't handle first branch and call interpreter if it's hit
8483 printf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
8484 do_in_intrp=1;
8485 }
8486 // basic load delay detection
8487 else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&rt1[i]!=0) {
8488 int t=(ba[i-1]-start)/4;
8489 if(0 <= t && t < i &&(rt1[i]==rs1[t]||rt1[i]==rs2[t])&&itype[t]!=CJUMP&&itype[t]!=SJUMP) {
8490 // jump target wants DS result - potential load delay effect
8491 printf("load delay @%08x (%08x)\n", addr + i*4, addr);
8492 do_in_intrp=1;
8493 bt[t+1]=1; // expected return from interpreter
8494 }
8495 else if(i>=2&&rt1[i-2]==2&&rt1[i]==2&&rs1[i]!=2&&rs2[i]!=2&&rs1[i-1]!=2&&rs2[i-1]!=2&&
8496 !(i>=3&&(itype[i-3]==RJUMP||itype[i-3]==UJUMP||itype[i-3]==CJUMP||itype[i-3]==SJUMP))) {
8497 // v0 overwrite like this is a sign of trouble, bail out
8498 printf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
8499 do_in_intrp=1;
8500 }
8501 }
26869094 8502 // check for link register access in delay slot
3e535354 8503 // TODO: teach the recompiler to handle this
26869094 8504 int rt1_=rt1[i-1];
8505 if(rt1_!=0&&(rs1[i]==rt1_||rs2[i]==rt1_||rt1[i]==rt1_||rt2[i]==rt1_)) {
8506 printf("link access in delay slot @%08x (%08x)\n", addr + i*4, addr);
3e535354 8507 do_in_intrp=1;
8508 }
8509 if(do_in_intrp) {
8510 rs1[i-1]=CCREG;
8511 rs2[i-1]=rt1[i-1]=rt2[i-1]=0;
26869094 8512 ba[i-1]=-1;
8513 itype[i-1]=INTCALL;
8514 done=2;
3e535354 8515 i--; // don't compile the DS
26869094 8516 }
3e535354 8517 }
26869094 8518#endif
3e535354 8519 /* Is this the end of the block? */
8520 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
5067f341 8521 if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
1e973cb0 8522 done=2;
57871462 8523 }
8524 else {
8525 if(stop_after_jal) done=1;
8526 // Stop on BREAK
8527 if((source[i+1]&0xfc00003f)==0x0d) done=1;
8528 }
8529 // Don't recompile stuff that's already compiled
8530 if(check_addr(start+i*4+4)) done=1;
8531 // Don't get too close to the limit
8532 if(i>MAXBLOCK/2) done=1;
8533 }
75dec299 8534 if(itype[i]==SYSCALL&&stop_after_jal) done=1;
1e973cb0 8535 if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
8536 if(done==2) {
8537 // Does the block continue due to a branch?
8538 for(j=i-1;j>=0;j--)
8539 {
8540 if(ba[j]==start+i*4+4) done=j=0;
8541 if(ba[j]==start+i*4+8) done=j=0;
8542 }
8543 }
75dec299 8544 //assert(i<MAXBLOCK-1);
57871462 8545 if(start+i*4==pagelimit-4) done=1;
8546 assert(start+i*4<pagelimit);
8547 if (i==MAXBLOCK-1) done=1;
8548 // Stop if we're compiling junk
8549 if(itype[i]==NI&&opcode[i]==0x11) {
8550 done=stop_after_jal=1;
8551 printf("Disabled speculative precompilation\n");
8552 }
8553 }
8554 slen=i;
8555 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8556 if(start+i*4==pagelimit) {
8557 itype[i-1]=SPAN;
8558 }
8559 }
8560 assert(slen>0);
8561
8562 /* Pass 2 - Register dependencies and branch targets */
8563
8564 unneeded_registers(0,slen-1,0);
8565
8566 /* Pass 3 - Register allocation */
8567
8568 struct regstat current; // Current register allocations/status
8569 current.is32=1;
8570 current.dirty=0;
8571 current.u=unneeded_reg[0];
8572 current.uu=unneeded_reg_upper[0];
8573 clear_all_regs(current.regmap);
8574 alloc_reg(&current,0,CCREG);
8575 dirty_reg(&current,CCREG);
8576 current.isconst=0;
8577 current.wasconst=0;
8578 int ds=0;
8579 int cc=0;
8580 int hr;
6ebf4adf 8581
8582#ifndef FORCE32
57871462 8583 provisional_32bit();
6ebf4adf 8584#endif
57871462 8585 if((u_int)addr&1) {
8586 // First instruction is delay slot
8587 cc=-1;
8588 bt[1]=1;
8589 ds=1;
8590 unneeded_reg[0]=1;
8591 unneeded_reg_upper[0]=1;
8592 current.regmap[HOST_BTREG]=BTREG;
8593 }
8594
8595 for(i=0;i<slen;i++)
8596 {
8597 if(bt[i])
8598 {
8599 int hr;
8600 for(hr=0;hr<HOST_REGS;hr++)
8601 {
8602 // Is this really necessary?
8603 if(current.regmap[hr]==0) current.regmap[hr]=-1;
8604 }
8605 current.isconst=0;
8606 }
8607 if(i>1)
8608 {
8609 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8610 {
8611 if(rs1[i-2]==0||rs2[i-2]==0)
8612 {
8613 if(rs1[i-2]) {
8614 current.is32|=1LL<<rs1[i-2];
8615 int hr=get_reg(current.regmap,rs1[i-2]|64);
8616 if(hr>=0) current.regmap[hr]=-1;
8617 }
8618 if(rs2[i-2]) {
8619 current.is32|=1LL<<rs2[i-2];
8620 int hr=get_reg(current.regmap,rs2[i-2]|64);
8621 if(hr>=0) current.regmap[hr]=-1;
8622 }
8623 }
8624 }
8625 }
6ebf4adf 8626#ifndef FORCE32
57871462 8627 // If something jumps here with 64-bit values
8628 // then promote those registers to 64 bits
8629 if(bt[i])
8630 {
8631 uint64_t temp_is32=current.is32;
8632 for(j=i-1;j>=0;j--)
8633 {
8634 if(ba[j]==start+i*4)
8635 temp_is32&=branch_regs[j].is32;
8636 }
8637 for(j=i;j<slen;j++)
8638 {
8639 if(ba[j]==start+i*4)
8640 //temp_is32=1;
8641 temp_is32&=p32[j];
8642 }
8643 if(temp_is32!=current.is32) {
8644 //printf("dumping 32-bit regs (%x)\n",start+i*4);
8645 #ifdef DESTRUCTIVE_WRITEBACK
8646 for(hr=0;hr<HOST_REGS;hr++)
8647 {
8648 int r=current.regmap[hr];
8649 if(r>0&&r<64)
8650 {
8651 if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8652 temp_is32|=1LL<<r;
8653 //printf("restore %d\n",r);
8654 }
8655 }
8656 }
8657 #endif
8658 current.is32=temp_is32;
8659 }
8660 }
6ebf4adf 8661#else
24385cae 8662 current.is32=-1LL;
8663#endif
8664
57871462 8665 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8666 regs[i].wasconst=current.isconst;
8667 regs[i].was32=current.is32;
8668 regs[i].wasdirty=current.dirty;
6ebf4adf 8669 #if defined(DESTRUCTIVE_WRITEBACK) && !defined(FORCE32)
57871462 8670 // To change a dirty register from 32 to 64 bits, we must write
8671 // it out during the previous cycle (for branches, 2 cycles)
8672 if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8673 {
8674 uint64_t temp_is32=current.is32;
8675 for(j=i-1;j>=0;j--)
8676 {
8677 if(ba[j]==start+i*4+4)
8678 temp_is32&=branch_regs[j].is32;
8679 }
8680 for(j=i;j<slen;j++)
8681 {
8682 if(ba[j]==start+i*4+4)
8683 //temp_is32=1;
8684 temp_is32&=p32[j];
8685 }
8686 if(temp_is32!=current.is32) {
8687 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8688 for(hr=0;hr<HOST_REGS;hr++)
8689 {
8690 int r=current.regmap[hr];
8691 if(r>0)
8692 {
8693 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8694 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
8695 {
8696 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
8697 {
8698 //printf("dump %d/r%d\n",hr,r);
8699 current.regmap[hr]=-1;
8700 if(get_reg(current.regmap,r|64)>=0)
8701 current.regmap[get_reg(current.regmap,r|64)]=-1;
8702 }
8703 }
8704 }
8705 }
8706 }
8707 }
8708 }
8709 else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
8710 {
8711 uint64_t temp_is32=current.is32;
8712 for(j=i-1;j>=0;j--)
8713 {
8714 if(ba[j]==start+i*4+8)
8715 temp_is32&=branch_regs[j].is32;
8716 }
8717 for(j=i;j<slen;j++)
8718 {
8719 if(ba[j]==start+i*4+8)
8720 //temp_is32=1;
8721 temp_is32&=p32[j];
8722 }
8723 if(temp_is32!=current.is32) {
8724 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8725 for(hr=0;hr<HOST_REGS;hr++)
8726 {
8727 int r=current.regmap[hr];
8728 if(r>0)
8729 {
8730 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8731 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
8732 {
8733 //printf("dump %d/r%d\n",hr,r);
8734 current.regmap[hr]=-1;
8735 if(get_reg(current.regmap,r|64)>=0)
8736 current.regmap[get_reg(current.regmap,r|64)]=-1;
8737 }
8738 }
8739 }
8740 }
8741 }
8742 }
8743 #endif
8744 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8745 if(i+1<slen) {
8746 current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8747 current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8748 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8749 current.u|=1;
8750 current.uu|=1;
8751 } else {
8752 current.u=1;
8753 current.uu=1;
8754 }
8755 } else {
8756 if(i+1<slen) {
8757 current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
8758 current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8759 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8760 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8761 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8762 current.u|=1;
8763 current.uu|=1;
8764 } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
8765 }
8766 is_ds[i]=ds;
8767 if(ds) {
8768 ds=0; // Skip delay slot, already allocated as part of branch
8769 // ...but we need to alloc it in case something jumps here
8770 if(i+1<slen) {
8771 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
8772 current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
8773 }else{
8774 current.u=branch_unneeded_reg[i-1];
8775 current.uu=branch_unneeded_reg_upper[i-1];
8776 }
8777 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8778 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8779 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8780 current.u|=1;
8781 current.uu|=1;
8782 struct regstat temp;
8783 memcpy(&temp,&current,sizeof(current));
8784 temp.wasdirty=temp.dirty;
8785 temp.was32=temp.is32;
8786 // TODO: Take into account unconditional branches, as below
8787 delayslot_alloc(&temp,i);
8788 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
8789 regs[i].wasdirty=temp.wasdirty;
8790 regs[i].was32=temp.was32;
8791 regs[i].dirty=temp.dirty;
8792 regs[i].is32=temp.is32;
8793 regs[i].isconst=0;
8794 regs[i].wasconst=0;
8795 current.isconst=0;
8796 // Create entry (branch target) regmap
8797 for(hr=0;hr<HOST_REGS;hr++)
8798 {
8799 int r=temp.regmap[hr];
8800 if(r>=0) {
8801 if(r!=regmap_pre[i][hr]) {
8802 regs[i].regmap_entry[hr]=-1;
8803 }
8804 else
8805 {
8806 if(r<64){
8807 if((current.u>>r)&1) {
8808 regs[i].regmap_entry[hr]=-1;
8809 regs[i].regmap[hr]=-1;
8810 //Don't clear regs in the delay slot as the branch might need them
8811 //current.regmap[hr]=-1;
8812 }else
8813 regs[i].regmap_entry[hr]=r;
8814 }
8815 else {
8816 if((current.uu>>(r&63))&1) {
8817 regs[i].regmap_entry[hr]=-1;
8818 regs[i].regmap[hr]=-1;
8819 //Don't clear regs in the delay slot as the branch might need them
8820 //current.regmap[hr]=-1;
8821 }else
8822 regs[i].regmap_entry[hr]=r;
8823 }
8824 }
8825 } else {
8826 // First instruction expects CCREG to be allocated
8827 if(i==0&&hr==HOST_CCREG)
8828 regs[i].regmap_entry[hr]=CCREG;
8829 else
8830 regs[i].regmap_entry[hr]=-1;
8831 }
8832 }
8833 }
8834 else { // Not delay slot
8835 switch(itype[i]) {
8836 case UJUMP:
8837 //current.isconst=0; // DEBUG
8838 //current.wasconst=0; // DEBUG
8839 //regs[i].wasconst=0; // DEBUG
8840 clear_const(&current,rt1[i]);
8841 alloc_cc(&current,i);
8842 dirty_reg(&current,CCREG);
8843 if (rt1[i]==31) {
8844 alloc_reg(&current,i,31);
8845 dirty_reg(&current,31);
68b3faee 8846 assert(rs1[i+1]!=31&&rs2[i+1]!=31);
076655d1 8847 assert(rt1[i+1]!=rt1[i]);
57871462 8848 #ifdef REG_PREFETCH
8849 alloc_reg(&current,i,PTEMP);
8850 #endif
8851 //current.is32|=1LL<<rt1[i];
8852 }
e1190b87 8853 ooo[i]=1;
57871462 8854 delayslot_alloc(&current,i+1);
8855 //current.isconst=0; // DEBUG
8856 ds=1;
8857 //printf("i=%d, isconst=%x\n",i,current.isconst);
8858 break;
8859 case RJUMP:
8860 //current.isconst=0;
8861 //current.wasconst=0;
8862 //regs[i].wasconst=0;
8863 clear_const(&current,rs1[i]);
8864 clear_const(&current,rt1[i]);
8865 alloc_cc(&current,i);
8866 dirty_reg(&current,CCREG);
8867 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
8868 alloc_reg(&current,i,rs1[i]);
5067f341 8869 if (rt1[i]!=0) {
8870 alloc_reg(&current,i,rt1[i]);
8871 dirty_reg(&current,rt1[i]);
68b3faee 8872 assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
076655d1 8873 assert(rt1[i+1]!=rt1[i]);
57871462 8874 #ifdef REG_PREFETCH
8875 alloc_reg(&current,i,PTEMP);
8876 #endif
8877 }
8878 #ifdef USE_MINI_HT
8879 if(rs1[i]==31) { // JALR
8880 alloc_reg(&current,i,RHASH);
8881 #ifndef HOST_IMM_ADDR32
8882 alloc_reg(&current,i,RHTBL);
8883 #endif
8884 }
8885 #endif
8886 delayslot_alloc(&current,i+1);
8887 } else {
8888 // The delay slot overwrites our source register,
8889 // allocate a temporary register to hold the old value.
8890 current.isconst=0;
8891 current.wasconst=0;
8892 regs[i].wasconst=0;
8893 delayslot_alloc(&current,i+1);
8894 current.isconst=0;
8895 alloc_reg(&current,i,RTEMP);
8896 }
8897 //current.isconst=0; // DEBUG
e1190b87 8898 ooo[i]=1;
57871462 8899 ds=1;
8900 break;
8901 case CJUMP:
8902 //current.isconst=0;
8903 //current.wasconst=0;
8904 //regs[i].wasconst=0;
8905 clear_const(&current,rs1[i]);
8906 clear_const(&current,rs2[i]);
8907 if((opcode[i]&0x3E)==4) // BEQ/BNE
8908 {
8909 alloc_cc(&current,i);
8910 dirty_reg(&current,CCREG);
8911 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8912 if(rs2[i]) alloc_reg(&current,i,rs2[i]);
8913 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8914 {
8915 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8916 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
8917 }
8918 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
8919 (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
8920 // The delay slot overwrites one of our conditions.
8921 // Allocate the branch condition registers instead.
57871462 8922 current.isconst=0;
8923 current.wasconst=0;
8924 regs[i].wasconst=0;
8925 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8926 if(rs2[i]) alloc_reg(&current,i,rs2[i]);
8927 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8928 {
8929 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8930 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
8931 }
8932 }
e1190b87 8933 else
8934 {
8935 ooo[i]=1;
8936 delayslot_alloc(&current,i+1);
8937 }
57871462 8938 }
8939 else
8940 if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
8941 {
8942 alloc_cc(&current,i);
8943 dirty_reg(&current,CCREG);
8944 alloc_reg(&current,i,rs1[i]);
8945 if(!(current.is32>>rs1[i]&1))
8946 {
8947 alloc_reg64(&current,i,rs1[i]);
8948 }
8949 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
8950 // The delay slot overwrites one of our conditions.
8951 // Allocate the branch condition registers instead.
57871462 8952 current.isconst=0;
8953 current.wasconst=0;
8954 regs[i].wasconst=0;
8955 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8956 if(!((current.is32>>rs1[i])&1))
8957 {
8958 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8959 }
8960 }
e1190b87 8961 else
8962 {
8963 ooo[i]=1;
8964 delayslot_alloc(&current,i+1);
8965 }
57871462 8966 }
8967 else
8968 // Don't alloc the delay slot yet because we might not execute it
8969 if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
8970 {
8971 current.isconst=0;
8972 current.wasconst=0;
8973 regs[i].wasconst=0;
8974 alloc_cc(&current,i);
8975 dirty_reg(&current,CCREG);
8976 alloc_reg(&current,i,rs1[i]);
8977 alloc_reg(&current,i,rs2[i]);
8978 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8979 {
8980 alloc_reg64(&current,i,rs1[i]);
8981 alloc_reg64(&current,i,rs2[i]);
8982 }
8983 }
8984 else
8985 if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
8986 {
8987 current.isconst=0;
8988 current.wasconst=0;
8989 regs[i].wasconst=0;
8990 alloc_cc(&current,i);
8991 dirty_reg(&current,CCREG);
8992 alloc_reg(&current,i,rs1[i]);
8993 if(!(current.is32>>rs1[i]&1))
8994 {
8995 alloc_reg64(&current,i,rs1[i]);
8996 }
8997 }
8998 ds=1;
8999 //current.isconst=0;
9000 break;
9001 case SJUMP:
9002 //current.isconst=0;
9003 //current.wasconst=0;
9004 //regs[i].wasconst=0;
9005 clear_const(&current,rs1[i]);
9006 clear_const(&current,rt1[i]);
9007 //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
9008 if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
9009 {
9010 alloc_cc(&current,i);
9011 dirty_reg(&current,CCREG);
9012 alloc_reg(&current,i,rs1[i]);
9013 if(!(current.is32>>rs1[i]&1))
9014 {
9015 alloc_reg64(&current,i,rs1[i]);
9016 }
9017 if (rt1[i]==31) { // BLTZAL/BGEZAL
9018 alloc_reg(&current,i,31);
9019 dirty_reg(&current,31);
57871462 9020 //#ifdef REG_PREFETCH
9021 //alloc_reg(&current,i,PTEMP);
9022 //#endif
9023 //current.is32|=1LL<<rt1[i];
9024 }
e1190b87 9025 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) // The delay slot overwrites the branch condition.
9026 ||(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))) { // DS touches $ra
57871462 9027 // Allocate the branch condition registers instead.
57871462 9028 current.isconst=0;
9029 current.wasconst=0;
9030 regs[i].wasconst=0;
9031 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9032 if(!((current.is32>>rs1[i])&1))
9033 {
9034 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9035 }
9036 }
e1190b87 9037 else
9038 {
9039 ooo[i]=1;
9040 delayslot_alloc(&current,i+1);
9041 }
57871462 9042 }
9043 else
9044 // Don't alloc the delay slot yet because we might not execute it
9045 if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
9046 {
9047 current.isconst=0;
9048 current.wasconst=0;
9049 regs[i].wasconst=0;
9050 alloc_cc(&current,i);
9051 dirty_reg(&current,CCREG);
9052 alloc_reg(&current,i,rs1[i]);
9053 if(!(current.is32>>rs1[i]&1))
9054 {
9055 alloc_reg64(&current,i,rs1[i]);
9056 }
9057 }
9058 ds=1;
9059 //current.isconst=0;
9060 break;
9061 case FJUMP:
9062 current.isconst=0;
9063 current.wasconst=0;
9064 regs[i].wasconst=0;
9065 if(likely[i]==0) // BC1F/BC1T
9066 {
9067 // TODO: Theoretically we can run out of registers here on x86.
9068 // The delay slot can allocate up to six, and we need to check
9069 // CSREG before executing the delay slot. Possibly we can drop
9070 // the cycle count and then reload it after checking that the
9071 // FPU is in a usable state, or don't do out-of-order execution.
9072 alloc_cc(&current,i);
9073 dirty_reg(&current,CCREG);
9074 alloc_reg(&current,i,FSREG);
9075 alloc_reg(&current,i,CSREG);
9076 if(itype[i+1]==FCOMP) {
9077 // The delay slot overwrites the branch condition.
9078 // Allocate the branch condition registers instead.
57871462 9079 alloc_cc(&current,i);
9080 dirty_reg(&current,CCREG);
9081 alloc_reg(&current,i,CSREG);
9082 alloc_reg(&current,i,FSREG);
9083 }
9084 else {
e1190b87 9085 ooo[i]=1;
57871462 9086 delayslot_alloc(&current,i+1);
9087 alloc_reg(&current,i+1,CSREG);
9088 }
9089 }
9090 else
9091 // Don't alloc the delay slot yet because we might not execute it
9092 if(likely[i]) // BC1FL/BC1TL
9093 {
9094 alloc_cc(&current,i);
9095 dirty_reg(&current,CCREG);
9096 alloc_reg(&current,i,CSREG);
9097 alloc_reg(&current,i,FSREG);
9098 }
9099 ds=1;
9100 current.isconst=0;
9101 break;
9102 case IMM16:
9103 imm16_alloc(&current,i);
9104 break;
9105 case LOAD:
9106 case LOADLR:
9107 load_alloc(&current,i);
9108 break;
9109 case STORE:
9110 case STORELR:
9111 store_alloc(&current,i);
9112 break;
9113 case ALU:
9114 alu_alloc(&current,i);
9115 break;
9116 case SHIFT:
9117 shift_alloc(&current,i);
9118 break;
9119 case MULTDIV:
9120 multdiv_alloc(&current,i);
9121 break;
9122 case SHIFTIMM:
9123 shiftimm_alloc(&current,i);
9124 break;
9125 case MOV:
9126 mov_alloc(&current,i);
9127 break;
9128 case COP0:
9129 cop0_alloc(&current,i);
9130 break;
9131 case COP1:
b9b61529 9132 case COP2:
57871462 9133 cop1_alloc(&current,i);
9134 break;
9135 case C1LS:
9136 c1ls_alloc(&current,i);
9137 break;
b9b61529 9138 case C2LS:
9139 c2ls_alloc(&current,i);
9140 break;
9141 case C2OP:
9142 c2op_alloc(&current,i);
9143 break;
57871462 9144 case FCONV:
9145 fconv_alloc(&current,i);
9146 break;
9147 case FLOAT:
9148 float_alloc(&current,i);
9149 break;
9150 case FCOMP:
9151 fcomp_alloc(&current,i);
9152 break;
9153 case SYSCALL:
7139f3c8 9154 case HLECALL:
1e973cb0 9155 case INTCALL:
57871462 9156 syscall_alloc(&current,i);
9157 break;
9158 case SPAN:
9159 pagespan_alloc(&current,i);
9160 break;
9161 }
9162
9163 // Drop the upper half of registers that have become 32-bit
9164 current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
9165 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9166 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9167 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9168 current.uu|=1;
9169 } else {
9170 current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
9171 current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9172 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9173 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9174 current.uu|=1;
9175 }
9176
9177 // Create entry (branch target) regmap
9178 for(hr=0;hr<HOST_REGS;hr++)
9179 {
9180 int r,or,er;
9181 r=current.regmap[hr];
9182 if(r>=0) {
9183 if(r!=regmap_pre[i][hr]) {
9184 // TODO: delay slot (?)
9185 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9186 if(or<0||(r&63)>=TEMPREG){
9187 regs[i].regmap_entry[hr]=-1;
9188 }
9189 else
9190 {
9191 // Just move it to a different register
9192 regs[i].regmap_entry[hr]=r;
9193 // If it was dirty before, it's still dirty
9194 if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r&63);
9195 }
9196 }
9197 else
9198 {
9199 // Unneeded
9200 if(r==0){
9201 regs[i].regmap_entry[hr]=0;
9202 }
9203 else
9204 if(r<64){
9205 if((current.u>>r)&1) {
9206 regs[i].regmap_entry[hr]=-1;
9207 //regs[i].regmap[hr]=-1;
9208 current.regmap[hr]=-1;
9209 }else
9210 regs[i].regmap_entry[hr]=r;
9211 }
9212 else {
9213 if((current.uu>>(r&63))&1) {
9214 regs[i].regmap_entry[hr]=-1;
9215 //regs[i].regmap[hr]=-1;
9216 current.regmap[hr]=-1;
9217 }else
9218 regs[i].regmap_entry[hr]=r;
9219 }
9220 }
9221 } else {
9222 // Branches expect CCREG to be allocated at the target
9223 if(regmap_pre[i][hr]==CCREG)
9224 regs[i].regmap_entry[hr]=CCREG;
9225 else
9226 regs[i].regmap_entry[hr]=-1;
9227 }
9228 }
9229 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9230 }
9231 /* Branch post-alloc */
9232 if(i>0)
9233 {
9234 current.was32=current.is32;
9235 current.wasdirty=current.dirty;
9236 switch(itype[i-1]) {
9237 case UJUMP:
9238 memcpy(&branch_regs[i-1],&current,sizeof(current));
9239 branch_regs[i-1].isconst=0;
9240 branch_regs[i-1].wasconst=0;
9241 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9242 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9243 alloc_cc(&branch_regs[i-1],i-1);
9244 dirty_reg(&branch_regs[i-1],CCREG);
9245 if(rt1[i-1]==31) { // JAL
9246 alloc_reg(&branch_regs[i-1],i-1,31);
9247 dirty_reg(&branch_regs[i-1],31);
9248 branch_regs[i-1].is32|=1LL<<31;
9249 }
9250 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9251 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9252 break;
9253 case RJUMP:
9254 memcpy(&branch_regs[i-1],&current,sizeof(current));
9255 branch_regs[i-1].isconst=0;
9256 branch_regs[i-1].wasconst=0;
9257 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9258 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9259 alloc_cc(&branch_regs[i-1],i-1);
9260 dirty_reg(&branch_regs[i-1],CCREG);
9261 alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
5067f341 9262 if(rt1[i-1]!=0) { // JALR
9263 alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9264 dirty_reg(&branch_regs[i-1],rt1[i-1]);
9265 branch_regs[i-1].is32|=1LL<<rt1[i-1];
57871462 9266 }
9267 #ifdef USE_MINI_HT
9268 if(rs1[i-1]==31) { // JALR
9269 alloc_reg(&branch_regs[i-1],i-1,RHASH);
9270 #ifndef HOST_IMM_ADDR32
9271 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9272 #endif
9273 }
9274 #endif
9275 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9276 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9277 break;
9278 case CJUMP:
9279 if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9280 {
9281 alloc_cc(&current,i-1);
9282 dirty_reg(&current,CCREG);
9283 if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9284 (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9285 // The delay slot overwrote one of our conditions
9286 // Delay slot goes after the test (in order)
9287 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9288 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9289 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9290 current.u|=1;
9291 current.uu|=1;
9292 delayslot_alloc(&current,i);
9293 current.isconst=0;
9294 }
9295 else
9296 {
9297 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9298 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9299 // Alloc the branch condition registers
9300 if(rs1[i-1]) alloc_reg(&current,i-1,rs1[i-1]);
9301 if(rs2[i-1]) alloc_reg(&current,i-1,rs2[i-1]);
9302 if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9303 {
9304 if(rs1[i-1]) alloc_reg64(&current,i-1,rs1[i-1]);
9305 if(rs2[i-1]) alloc_reg64(&current,i-1,rs2[i-1]);
9306 }
9307 }
9308 memcpy(&branch_regs[i-1],&current,sizeof(current));
9309 branch_regs[i-1].isconst=0;
9310 branch_regs[i-1].wasconst=0;
9311 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9312 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9313 }
9314 else
9315 if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9316 {
9317 alloc_cc(&current,i-1);
9318 dirty_reg(&current,CCREG);
9319 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9320 // The delay slot overwrote the branch condition
9321 // Delay slot goes after the test (in order)
9322 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9323 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9324 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9325 current.u|=1;
9326 current.uu|=1;
9327 delayslot_alloc(&current,i);
9328 current.isconst=0;
9329 }
9330 else
9331 {
9332 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9333 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9334 // Alloc the branch condition register
9335 alloc_reg(&current,i-1,rs1[i-1]);
9336 if(!(current.is32>>rs1[i-1]&1))
9337 {
9338 alloc_reg64(&current,i-1,rs1[i-1]);
9339 }
9340 }
9341 memcpy(&branch_regs[i-1],&current,sizeof(current));
9342 branch_regs[i-1].isconst=0;
9343 branch_regs[i-1].wasconst=0;
9344 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9345 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9346 }
9347 else
9348 // Alloc the delay slot in case the branch is taken
9349 if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9350 {
9351 memcpy(&branch_regs[i-1],&current,sizeof(current));
9352 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9353 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9354 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9355 alloc_cc(&branch_regs[i-1],i);
9356 dirty_reg(&branch_regs[i-1],CCREG);
9357 delayslot_alloc(&branch_regs[i-1],i);
9358 branch_regs[i-1].isconst=0;
9359 alloc_reg(&current,i,CCREG); // Not taken path
9360 dirty_reg(&current,CCREG);
9361 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9362 }
9363 else
9364 if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9365 {
9366 memcpy(&branch_regs[i-1],&current,sizeof(current));
9367 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9368 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9369 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9370 alloc_cc(&branch_regs[i-1],i);
9371 dirty_reg(&branch_regs[i-1],CCREG);
9372 delayslot_alloc(&branch_regs[i-1],i);
9373 branch_regs[i-1].isconst=0;
9374 alloc_reg(&current,i,CCREG); // Not taken path
9375 dirty_reg(&current,CCREG);
9376 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9377 }
9378 break;
9379 case SJUMP:
9380 //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9381 if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9382 {
9383 alloc_cc(&current,i-1);
9384 dirty_reg(&current,CCREG);
9385 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9386 // The delay slot overwrote the branch condition
9387 // Delay slot goes after the test (in order)
9388 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9389 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9390 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9391 current.u|=1;
9392 current.uu|=1;
9393 delayslot_alloc(&current,i);
9394 current.isconst=0;
9395 }
9396 else
9397 {
9398 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9399 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9400 // Alloc the branch condition register
9401 alloc_reg(&current,i-1,rs1[i-1]);
9402 if(!(current.is32>>rs1[i-1]&1))
9403 {
9404 alloc_reg64(&current,i-1,rs1[i-1]);
9405 }
9406 }
9407 memcpy(&branch_regs[i-1],&current,sizeof(current));
9408 branch_regs[i-1].isconst=0;
9409 branch_regs[i-1].wasconst=0;
9410 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9411 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9412 }
9413 else
9414 // Alloc the delay slot in case the branch is taken
9415 if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9416 {
9417 memcpy(&branch_regs[i-1],&current,sizeof(current));
9418 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9419 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9420 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9421 alloc_cc(&branch_regs[i-1],i);
9422 dirty_reg(&branch_regs[i-1],CCREG);
9423 delayslot_alloc(&branch_regs[i-1],i);
9424 branch_regs[i-1].isconst=0;
9425 alloc_reg(&current,i,CCREG); // Not taken path
9426 dirty_reg(&current,CCREG);
9427 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9428 }
9429 // FIXME: BLTZAL/BGEZAL
9430 if(opcode2[i-1]&0x10) { // BxxZAL
9431 alloc_reg(&branch_regs[i-1],i-1,31);
9432 dirty_reg(&branch_regs[i-1],31);
9433 branch_regs[i-1].is32|=1LL<<31;
9434 }
9435 break;
9436 case FJUMP:
9437 if(likely[i-1]==0) // BC1F/BC1T
9438 {
9439 alloc_cc(&current,i-1);
9440 dirty_reg(&current,CCREG);
9441 if(itype[i]==FCOMP) {
9442 // The delay slot overwrote the branch condition
9443 // Delay slot goes after the test (in order)
9444 delayslot_alloc(&current,i);
9445 current.isconst=0;
9446 }
9447 else
9448 {
9449 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9450 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9451 // Alloc the branch condition register
9452 alloc_reg(&current,i-1,FSREG);
9453 }
9454 memcpy(&branch_regs[i-1],&current,sizeof(current));
9455 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9456 }
9457 else // BC1FL/BC1TL
9458 {
9459 // Alloc the delay slot in case the branch is taken
9460 memcpy(&branch_regs[i-1],&current,sizeof(current));
9461 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9462 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9463 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9464 alloc_cc(&branch_regs[i-1],i);
9465 dirty_reg(&branch_regs[i-1],CCREG);
9466 delayslot_alloc(&branch_regs[i-1],i);
9467 branch_regs[i-1].isconst=0;
9468 alloc_reg(&current,i,CCREG); // Not taken path
9469 dirty_reg(&current,CCREG);
9470 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9471 }
9472 break;
9473 }
9474
9475 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9476 {
9477 if(rt1[i-1]==31) // JAL/JALR
9478 {
9479 // Subroutine call will return here, don't alloc any registers
9480 current.is32=1;
9481 current.dirty=0;
9482 clear_all_regs(current.regmap);
9483 alloc_reg(&current,i,CCREG);
9484 dirty_reg(&current,CCREG);
9485 }
9486 else if(i+1<slen)
9487 {
9488 // Internal branch will jump here, match registers to caller
9489 current.is32=0x3FFFFFFFFLL;
9490 current.dirty=0;
9491 clear_all_regs(current.regmap);
9492 alloc_reg(&current,i,CCREG);
9493 dirty_reg(&current,CCREG);
9494 for(j=i-1;j>=0;j--)
9495 {
9496 if(ba[j]==start+i*4+4) {
9497 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9498 current.is32=branch_regs[j].is32;
9499 current.dirty=branch_regs[j].dirty;
9500 break;
9501 }
9502 }
9503 while(j>=0) {
9504 if(ba[j]==start+i*4+4) {
9505 for(hr=0;hr<HOST_REGS;hr++) {
9506 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9507 current.regmap[hr]=-1;
9508 }
9509 current.is32&=branch_regs[j].is32;
9510 current.dirty&=branch_regs[j].dirty;
9511 }
9512 }
9513 j--;
9514 }
9515 }
9516 }
9517 }
9518
9519 // Count cycles in between branches
9520 ccadj[i]=cc;
7139f3c8 9521 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
57871462 9522 {
9523 cc=0;
9524 }
fb407447 9525#ifdef PCSX
9526 else if(/*itype[i]==LOAD||*/itype[i]==STORE||itype[i]==C1LS) // load causes weird timing issues
9527 {
9528 cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
9529 }
9530 else if(itype[i]==C2LS)
9531 {
9532 cc+=4;
9533 }
9534#endif
57871462 9535 else
9536 {
9537 cc++;
9538 }
9539
9540 flush_dirty_uppers(&current);
9541 if(!is_ds[i]) {
9542 regs[i].is32=current.is32;
9543 regs[i].dirty=current.dirty;
9544 regs[i].isconst=current.isconst;
9545 memcpy(constmap[i],current.constmap,sizeof(current.constmap));
9546 }
9547 for(hr=0;hr<HOST_REGS;hr++) {
9548 if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
9549 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9550 regs[i].wasconst&=~(1<<hr);
9551 }
9552 }
9553 }
9554 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9555 }
9556
9557 /* Pass 4 - Cull unused host registers */
9558
9559 uint64_t nr=0;
9560
9561 for (i=slen-1;i>=0;i--)
9562 {
9563 int hr;
9564 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9565 {
9566 if(ba[i]<start || ba[i]>=(start+slen*4))
9567 {
9568 // Branch out of this block, don't need anything
9569 nr=0;
9570 }
9571 else
9572 {
9573 // Internal branch
9574 // Need whatever matches the target
9575 nr=0;
9576 int t=(ba[i]-start)>>2;
9577 for(hr=0;hr<HOST_REGS;hr++)
9578 {
9579 if(regs[i].regmap_entry[hr]>=0) {
9580 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9581 }
9582 }
9583 }
9584 // Conditional branch may need registers for following instructions
9585 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9586 {
9587 if(i<slen-2) {
9588 nr|=needed_reg[i+2];
9589 for(hr=0;hr<HOST_REGS;hr++)
9590 {
9591 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9592 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9593 }
9594 }
9595 }
9596 // Don't need stuff which is overwritten
9597 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9598 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9599 // Merge in delay slot
9600 for(hr=0;hr<HOST_REGS;hr++)
9601 {
9602 if(!likely[i]) {
9603 // These are overwritten unless the branch is "likely"
9604 // and the delay slot is nullified if not taken
9605 if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9606 if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9607 }
9608 if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9609 if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9610 if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9611 if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9612 if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9613 if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9614 if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9615 if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9616 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9617 if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9618 if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9619 }
9620 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9621 if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9622 if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9623 }
b9b61529 9624 if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
57871462 9625 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9626 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9627 }
9628 }
9629 }
1e973cb0 9630 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 9631 {
9632 // SYSCALL instruction (software interrupt)
9633 nr=0;
9634 }
9635 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9636 {
9637 // ERET instruction (return from interrupt)
9638 nr=0;
9639 }
9640 else // Non-branch
9641 {
9642 if(i<slen-1) {
9643 for(hr=0;hr<HOST_REGS;hr++) {
9644 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9645 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9646 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9647 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9648 }
9649 }
9650 }
9651 for(hr=0;hr<HOST_REGS;hr++)
9652 {
9653 // Overwritten registers are not needed
9654 if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9655 if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9656 if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9657 // Source registers are needed
9658 if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9659 if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9660 if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9661 if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9662 if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9663 if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9664 if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9665 if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9666 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9667 if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9668 if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9669 }
9670 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
9671 if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9672 if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9673 }
b9b61529 9674 if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
57871462 9675 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9676 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9677 }
9678 // Don't store a register immediately after writing it,
9679 // may prevent dual-issue.
9680 // But do so if this is a branch target, otherwise we
9681 // might have to load the register before the branch.
9682 if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
9683 if((regmap_pre[i][hr]>0&&regmap_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
9684 (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
9685 if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9686 if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9687 }
9688 if((regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
9689 (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
9690 if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9691 if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9692 }
9693 }
9694 }
9695 // Cycle count is needed at branches. Assume it is needed at the target too.
9696 if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
9697 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9698 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9699 }
9700 // Save it
9701 needed_reg[i]=nr;
9702
9703 // Deallocate unneeded registers
9704 for(hr=0;hr<HOST_REGS;hr++)
9705 {
9706 if(!((nr>>hr)&1)) {
9707 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
9708 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9709 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9710 (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
9711 {
9712 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9713 {
9714 if(likely[i]) {
9715 regs[i].regmap[hr]=-1;
9716 regs[i].isconst&=~(1<<hr);
9717 if(i<slen-2) regmap_pre[i+2][hr]=-1;
9718 }
9719 }
9720 }
9721 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9722 {
9723 int d1=0,d2=0,map=0,temp=0;
9724 if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
9725 {
9726 d1=dep1[i+1];
9727 d2=dep2[i+1];
9728 }
9729 if(using_tlb) {
9730 if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
9731 itype[i+1]==STORE || itype[i+1]==STORELR ||
b9b61529 9732 itype[i+1]==C1LS || itype[i+1]==C2LS)
57871462 9733 map=TLREG;
9734 } else
b9b61529 9735 if(itype[i+1]==STORE || itype[i+1]==STORELR ||
9736 (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
57871462 9737 map=INVCP;
9738 }
9739 if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
b9b61529 9740 itype[i+1]==C1LS || itype[i+1]==C2LS)
57871462 9741 temp=FTEMP;
9742 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9743 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9744 (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
9745 (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
9746 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9747 regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
9748 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
9749 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
9750 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
9751 regs[i].regmap[hr]!=map )
9752 {
9753 regs[i].regmap[hr]=-1;
9754 regs[i].isconst&=~(1<<hr);
9755 if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
9756 (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
9757 (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
9758 (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
9759 (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
9760 branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
9761 (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
9762 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
9763 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
9764 branch_regs[i].regmap[hr]!=map)
9765 {
9766 branch_regs[i].regmap[hr]=-1;
9767 branch_regs[i].regmap_entry[hr]=-1;
9768 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9769 {
9770 if(!likely[i]&&i<slen-2) {
9771 regmap_pre[i+2][hr]=-1;
9772 }
9773 }
9774 }
9775 }
9776 }
9777 else
9778 {
9779 // Non-branch
9780 if(i>0)
9781 {
9782 int d1=0,d2=0,map=-1,temp=-1;
9783 if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
9784 {
9785 d1=dep1[i];
9786 d2=dep2[i];
9787 }
9788 if(using_tlb) {
9789 if(itype[i]==LOAD || itype[i]==LOADLR ||
9790 itype[i]==STORE || itype[i]==STORELR ||
b9b61529 9791 itype[i]==C1LS || itype[i]==C2LS)
57871462 9792 map=TLREG;
b9b61529 9793 } else if(itype[i]==STORE || itype[i]==STORELR ||
9794 (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
57871462 9795 map=INVCP;
9796 }
9797 if(itype[i]==LOADLR || itype[i]==STORELR ||
b9b61529 9798 itype[i]==C1LS || itype[i]==C2LS)
57871462 9799 temp=FTEMP;
9800 if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9801 (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
9802 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9803 regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
9804 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
9805 (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
9806 {
9807 if(i<slen-1&&!is_ds[i]) {
9808 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
9809 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
9810 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
9811 {
9812 printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
9813 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
9814 }
9815 regmap_pre[i+1][hr]=-1;
9816 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
9817 }
9818 regs[i].regmap[hr]=-1;
9819 regs[i].isconst&=~(1<<hr);
9820 }
9821 }
9822 }
9823 }
9824 }
9825 }
9826
9827 /* Pass 5 - Pre-allocate registers */
9828
9829 // If a register is allocated during a loop, try to allocate it for the
9830 // entire loop, if possible. This avoids loading/storing registers
9831 // inside of the loop.
9832
9833 signed char f_regmap[HOST_REGS];
9834 clear_all_regs(f_regmap);
9835 for(i=0;i<slen-1;i++)
9836 {
9837 if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9838 {
9839 if(ba[i]>=start && ba[i]<(start+i*4))
9840 if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
9841 ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
9842 ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
9843 ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
b9b61529 9844 ||itype[i+1]==FCOMP||itype[i+1]==FCONV
9845 ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
57871462 9846 {
9847 int t=(ba[i]-start)>>2;
9848 if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
9849 if(t<2||(itype[t-2]!=UJUMP)) // call/ret assumes no registers allocated
9850 for(hr=0;hr<HOST_REGS;hr++)
9851 {
9852 if(regs[i].regmap[hr]>64) {
9853 if(!((regs[i].dirty>>hr)&1))
9854 f_regmap[hr]=regs[i].regmap[hr];
9855 else f_regmap[hr]=-1;
9856 }
b372a952 9857 else if(regs[i].regmap[hr]>=0) {
9858 if(f_regmap[hr]!=regs[i].regmap[hr]) {
9859 // dealloc old register
9860 int n;
9861 for(n=0;n<HOST_REGS;n++)
9862 {
9863 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
9864 }
9865 // and alloc new one
9866 f_regmap[hr]=regs[i].regmap[hr];
9867 }
9868 }
57871462 9869 if(branch_regs[i].regmap[hr]>64) {
9870 if(!((branch_regs[i].dirty>>hr)&1))
9871 f_regmap[hr]=branch_regs[i].regmap[hr];
9872 else f_regmap[hr]=-1;
9873 }
b372a952 9874 else if(branch_regs[i].regmap[hr]>=0) {
9875 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
9876 // dealloc old register
9877 int n;
9878 for(n=0;n<HOST_REGS;n++)
9879 {
9880 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
9881 }
9882 // and alloc new one
9883 f_regmap[hr]=branch_regs[i].regmap[hr];
9884 }
9885 }
e1190b87 9886 if(ooo[i]) {
9887 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
9888 f_regmap[hr]=branch_regs[i].regmap[hr];
9889 }else{
9890 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
57871462 9891 f_regmap[hr]=branch_regs[i].regmap[hr];
9892 }
9893 // Avoid dirty->clean transition
e1190b87 9894 #ifdef DESTRUCTIVE_WRITEBACK
57871462 9895 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
e1190b87 9896 #endif
9897 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
9898 // case above, however it's always a good idea. We can't hoist the
9899 // load if the register was already allocated, so there's no point
9900 // wasting time analyzing most of these cases. It only "succeeds"
9901 // when the mapping was different and the load can be replaced with
9902 // a mov, which is of negligible benefit. So such cases are
9903 // skipped below.
57871462 9904 if(f_regmap[hr]>0) {
e1190b87 9905 if(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0) {
57871462 9906 int r=f_regmap[hr];
9907 for(j=t;j<=i;j++)
9908 {
9909 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9910 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
9911 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
9912 if(r>63) {
9913 // NB This can exclude the case where the upper-half
9914 // register is lower numbered than the lower-half
9915 // register. Not sure if it's worth fixing...
9916 if(get_reg(regs[j].regmap,r&63)<0) break;
e1190b87 9917 if(get_reg(regs[j].regmap_entry,r&63)<0) break;
57871462 9918 if(regs[j].is32&(1LL<<(r&63))) break;
9919 }
9920 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
9921 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9922 int k;
9923 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
9924 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
9925 if(r>63) {
9926 if(get_reg(regs[i].regmap,r&63)<0) break;
9927 if(get_reg(branch_regs[i].regmap,r&63)<0) break;
9928 }
9929 k=i;
9930 while(k>1&&regs[k-1].regmap[hr]==-1) {
e1190b87 9931 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
9932 //printf("no free regs for store %x\n",start+(k-1)*4);
9933 break;
57871462 9934 }
57871462 9935 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
9936 //printf("no-match due to different register\n");
9937 break;
9938 }
9939 if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
9940 //printf("no-match due to branch\n");
9941 break;
9942 }
9943 // call/ret fast path assumes no registers allocated
9944 if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)) {
9945 break;
9946 }
9947 if(r>63) {
9948 // NB This can exclude the case where the upper-half
9949 // register is lower numbered than the lower-half
9950 // register. Not sure if it's worth fixing...
9951 if(get_reg(regs[k-1].regmap,r&63)<0) break;
9952 if(regs[k-1].is32&(1LL<<(r&63))) break;
9953 }
9954 k--;
9955 }
9956 if(i<slen-1) {
9957 if((regs[k].is32&(1LL<<f_regmap[hr]))!=
9958 (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
9959 //printf("bad match after branch\n");
9960 break;
9961 }
9962 }
9963 if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
9964 //printf("Extend r%d, %x ->\n",hr,start+k*4);
9965 while(k<i) {
9966 regs[k].regmap_entry[hr]=f_regmap[hr];
9967 regs[k].regmap[hr]=f_regmap[hr];
9968 regmap_pre[k+1][hr]=f_regmap[hr];
9969 regs[k].wasdirty&=~(1<<hr);
9970 regs[k].dirty&=~(1<<hr);
9971 regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
9972 regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
9973 regs[k].wasconst&=~(1<<hr);
9974 regs[k].isconst&=~(1<<hr);
9975 k++;
9976 }
9977 }
9978 else {
9979 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
9980 break;
9981 }
9982 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
9983 if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
9984 //printf("OK fill %x (r%d)\n",start+i*4,hr);
9985 regs[i].regmap_entry[hr]=f_regmap[hr];
9986 regs[i].regmap[hr]=f_regmap[hr];
9987 regs[i].wasdirty&=~(1<<hr);
9988 regs[i].dirty&=~(1<<hr);
9989 regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
9990 regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
9991 regs[i].wasconst&=~(1<<hr);
9992 regs[i].isconst&=~(1<<hr);
9993 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
9994 branch_regs[i].wasdirty&=~(1<<hr);
9995 branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
9996 branch_regs[i].regmap[hr]=f_regmap[hr];
9997 branch_regs[i].dirty&=~(1<<hr);
9998 branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
9999 branch_regs[i].wasconst&=~(1<<hr);
10000 branch_regs[i].isconst&=~(1<<hr);
10001 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
10002 regmap_pre[i+2][hr]=f_regmap[hr];
10003 regs[i+2].wasdirty&=~(1<<hr);
10004 regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
10005 assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
10006 (regs[i+2].was32&(1LL<<f_regmap[hr])));
10007 }
10008 }
10009 }
10010 for(k=t;k<j;k++) {
e1190b87 10011 // Alloc register clean at beginning of loop,
10012 // but may dirty it in pass 6
57871462 10013 regs[k].regmap_entry[hr]=f_regmap[hr];
10014 regs[k].regmap[hr]=f_regmap[hr];
57871462 10015 regs[k].dirty&=~(1<<hr);
10016 regs[k].wasconst&=~(1<<hr);
10017 regs[k].isconst&=~(1<<hr);
e1190b87 10018 if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) {
10019 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
10020 branch_regs[k].regmap[hr]=f_regmap[hr];
10021 branch_regs[k].dirty&=~(1<<hr);
10022 branch_regs[k].wasconst&=~(1<<hr);
10023 branch_regs[k].isconst&=~(1<<hr);
10024 if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
10025 regmap_pre[k+2][hr]=f_regmap[hr];
10026 regs[k+2].wasdirty&=~(1<<hr);
10027 assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))==
10028 (regs[k+2].was32&(1LL<<f_regmap[hr])));
10029 }
10030 }
10031 else
10032 {
10033 regmap_pre[k+1][hr]=f_regmap[hr];
10034 regs[k+1].wasdirty&=~(1<<hr);
10035 }
57871462 10036 }
10037 if(regs[j].regmap[hr]==f_regmap[hr])
10038 regs[j].regmap_entry[hr]=f_regmap[hr];
10039 break;
10040 }
10041 if(j==i) break;
10042 if(regs[j].regmap[hr]>=0)
10043 break;
10044 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
10045 //printf("no-match due to different register\n");
10046 break;
10047 }
10048 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
10049 //printf("32/64 mismatch %x %d\n",start+j*4,hr);
10050 break;
10051 }
e1190b87 10052 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10053 {
10054 // Stop on unconditional branch
10055 break;
10056 }
10057 if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
10058 {
10059 if(ooo[j]) {
10060 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
10061 break;
10062 }else{
10063 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
10064 break;
10065 }
10066 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
10067 //printf("no-match due to different register (branch)\n");
57871462 10068 break;
10069 }
10070 }
e1190b87 10071 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10072 //printf("No free regs for store %x\n",start+j*4);
10073 break;
10074 }
57871462 10075 if(f_regmap[hr]>=64) {
10076 if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
10077 break;
10078 }
10079 else
10080 {
10081 if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
10082 break;
10083 }
10084 }
10085 }
10086 }
10087 }
10088 }
10089 }
10090 }
10091 }else{
10092 int count=0;
10093 for(hr=0;hr<HOST_REGS;hr++)
10094 {
10095 if(hr!=EXCLUDE_REG) {
10096 if(regs[i].regmap[hr]>64) {
10097 if(!((regs[i].dirty>>hr)&1))
10098 f_regmap[hr]=regs[i].regmap[hr];
10099 }
b372a952 10100 else if(regs[i].regmap[hr]>=0) {
10101 if(f_regmap[hr]!=regs[i].regmap[hr]) {
10102 // dealloc old register
10103 int n;
10104 for(n=0;n<HOST_REGS;n++)
10105 {
10106 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10107 }
10108 // and alloc new one
10109 f_regmap[hr]=regs[i].regmap[hr];
10110 }
10111 }
57871462 10112 else if(regs[i].regmap[hr]<0) count++;
10113 }
10114 }
10115 // Try to restore cycle count at branch targets
10116 if(bt[i]) {
10117 for(j=i;j<slen-1;j++) {
10118 if(regs[j].regmap[HOST_CCREG]!=-1) break;
e1190b87 10119 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10120 //printf("no free regs for store %x\n",start+j*4);
10121 break;
57871462 10122 }
57871462 10123 }
10124 if(regs[j].regmap[HOST_CCREG]==CCREG) {
10125 int k=i;
10126 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
10127 while(k<j) {
10128 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10129 regs[k].regmap[HOST_CCREG]=CCREG;
10130 regmap_pre[k+1][HOST_CCREG]=CCREG;
10131 regs[k+1].wasdirty|=1<<HOST_CCREG;
10132 regs[k].dirty|=1<<HOST_CCREG;
10133 regs[k].wasconst&=~(1<<HOST_CCREG);
10134 regs[k].isconst&=~(1<<HOST_CCREG);
10135 k++;
10136 }
10137 regs[j].regmap_entry[HOST_CCREG]=CCREG;
10138 }
10139 // Work backwards from the branch target
10140 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
10141 {
10142 //printf("Extend backwards\n");
10143 int k;
10144 k=i;
10145 while(regs[k-1].regmap[HOST_CCREG]==-1) {
e1190b87 10146 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10147 //printf("no free regs for store %x\n",start+(k-1)*4);
10148 break;
57871462 10149 }
57871462 10150 k--;
10151 }
10152 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
10153 //printf("Extend CC, %x ->\n",start+k*4);
10154 while(k<=i) {
10155 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10156 regs[k].regmap[HOST_CCREG]=CCREG;
10157 regmap_pre[k+1][HOST_CCREG]=CCREG;
10158 regs[k+1].wasdirty|=1<<HOST_CCREG;
10159 regs[k].dirty|=1<<HOST_CCREG;
10160 regs[k].wasconst&=~(1<<HOST_CCREG);
10161 regs[k].isconst&=~(1<<HOST_CCREG);
10162 k++;
10163 }
10164 }
10165 else {
10166 //printf("Fail Extend CC, %x ->\n",start+k*4);
10167 }
10168 }
10169 }
10170 if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
10171 itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
10172 itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
e1190b87 10173 itype[i]!=FCONV&&itype[i]!=FCOMP)
57871462 10174 {
10175 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
10176 }
10177 }
10178 }
10179
10180 // This allocates registers (if possible) one instruction prior
10181 // to use, which can avoid a load-use penalty on certain CPUs.
10182 for(i=0;i<slen-1;i++)
10183 {
10184 if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10185 {
10186 if(!bt[i+1])
10187 {
b9b61529 10188 if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
10189 ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
57871462 10190 {
10191 if(rs1[i+1]) {
10192 if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10193 {
10194 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10195 {
10196 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10197 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10198 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10199 regs[i].isconst&=~(1<<hr);
10200 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10201 constmap[i][hr]=constmap[i+1][hr];
10202 regs[i+1].wasdirty&=~(1<<hr);
10203 regs[i].dirty&=~(1<<hr);
10204 }
10205 }
10206 }
10207 if(rs2[i+1]) {
10208 if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10209 {
10210 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10211 {
10212 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10213 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10214 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10215 regs[i].isconst&=~(1<<hr);
10216 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10217 constmap[i][hr]=constmap[i+1][hr];
10218 regs[i+1].wasdirty&=~(1<<hr);
10219 regs[i].dirty&=~(1<<hr);
10220 }
10221 }
10222 }
10223 if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10224 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10225 {
10226 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10227 {
10228 regs[i].regmap[hr]=rs1[i+1];
10229 regmap_pre[i+1][hr]=rs1[i+1];
10230 regs[i+1].regmap_entry[hr]=rs1[i+1];
10231 regs[i].isconst&=~(1<<hr);
10232 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10233 constmap[i][hr]=constmap[i+1][hr];
10234 regs[i+1].wasdirty&=~(1<<hr);
10235 regs[i].dirty&=~(1<<hr);
10236 }
10237 }
10238 }
10239 if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10240 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10241 {
10242 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10243 {
10244 regs[i].regmap[hr]=rs1[i+1];
10245 regmap_pre[i+1][hr]=rs1[i+1];
10246 regs[i+1].regmap_entry[hr]=rs1[i+1];
10247 regs[i].isconst&=~(1<<hr);
10248 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10249 constmap[i][hr]=constmap[i+1][hr];
10250 regs[i+1].wasdirty&=~(1<<hr);
10251 regs[i].dirty&=~(1<<hr);
10252 }
10253 }
10254 }
10255 #ifndef HOST_IMM_ADDR32
b9b61529 10256 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
57871462 10257 hr=get_reg(regs[i+1].regmap,TLREG);
10258 if(hr>=0) {
10259 int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10260 if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10261 int nr;
10262 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10263 {
10264 regs[i].regmap[hr]=MGEN1+((i+1)&1);
10265 regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10266 regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10267 regs[i].isconst&=~(1<<hr);
10268 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10269 constmap[i][hr]=constmap[i+1][hr];
10270 regs[i+1].wasdirty&=~(1<<hr);
10271 regs[i].dirty&=~(1<<hr);
10272 }
10273 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10274 {
10275 // move it to another register
10276 regs[i+1].regmap[hr]=-1;
10277 regmap_pre[i+2][hr]=-1;
10278 regs[i+1].regmap[nr]=TLREG;
10279 regmap_pre[i+2][nr]=TLREG;
10280 regs[i].regmap[nr]=MGEN1+((i+1)&1);
10281 regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10282 regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10283 regs[i].isconst&=~(1<<nr);
10284 regs[i+1].isconst&=~(1<<nr);
10285 regs[i].dirty&=~(1<<nr);
10286 regs[i+1].wasdirty&=~(1<<nr);
10287 regs[i+1].dirty&=~(1<<nr);
10288 regs[i+2].wasdirty&=~(1<<nr);
10289 }
10290 }
10291 }
10292 }
10293 #endif
b9b61529 10294 if(itype[i+1]==STORE||itype[i+1]==STORELR
10295 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
57871462 10296 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10297 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10298 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10299 else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10300 assert(hr>=0);
10301 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10302 {
10303 regs[i].regmap[hr]=rs1[i+1];
10304 regmap_pre[i+1][hr]=rs1[i+1];
10305 regs[i+1].regmap_entry[hr]=rs1[i+1];
10306 regs[i].isconst&=~(1<<hr);
10307 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10308 constmap[i][hr]=constmap[i+1][hr];
10309 regs[i+1].wasdirty&=~(1<<hr);
10310 regs[i].dirty&=~(1<<hr);
10311 }
10312 }
10313 }
b9b61529 10314 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
57871462 10315 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10316 int nr;
10317 hr=get_reg(regs[i+1].regmap,FTEMP);
10318 assert(hr>=0);
10319 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10320 {
10321 regs[i].regmap[hr]=rs1[i+1];
10322 regmap_pre[i+1][hr]=rs1[i+1];
10323 regs[i+1].regmap_entry[hr]=rs1[i+1];
10324 regs[i].isconst&=~(1<<hr);
10325 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10326 constmap[i][hr]=constmap[i+1][hr];
10327 regs[i+1].wasdirty&=~(1<<hr);
10328 regs[i].dirty&=~(1<<hr);
10329 }
10330 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10331 {
10332 // move it to another register
10333 regs[i+1].regmap[hr]=-1;
10334 regmap_pre[i+2][hr]=-1;
10335 regs[i+1].regmap[nr]=FTEMP;
10336 regmap_pre[i+2][nr]=FTEMP;
10337 regs[i].regmap[nr]=rs1[i+1];
10338 regmap_pre[i+1][nr]=rs1[i+1];
10339 regs[i+1].regmap_entry[nr]=rs1[i+1];
10340 regs[i].isconst&=~(1<<nr);
10341 regs[i+1].isconst&=~(1<<nr);
10342 regs[i].dirty&=~(1<<nr);
10343 regs[i+1].wasdirty&=~(1<<nr);
10344 regs[i+1].dirty&=~(1<<nr);
10345 regs[i+2].wasdirty&=~(1<<nr);
10346 }
10347 }
10348 }
b9b61529 10349 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
57871462 10350 if(itype[i+1]==LOAD)
10351 hr=get_reg(regs[i+1].regmap,rt1[i+1]);
b9b61529 10352 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
57871462 10353 hr=get_reg(regs[i+1].regmap,FTEMP);
b9b61529 10354 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
57871462 10355 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10356 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10357 }
10358 if(hr>=0&&regs[i].regmap[hr]<0) {
10359 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10360 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10361 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10362 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10363 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10364 regs[i].isconst&=~(1<<hr);
10365 regs[i+1].wasdirty&=~(1<<hr);
10366 regs[i].dirty&=~(1<<hr);
10367 }
10368 }
10369 }
10370 }
10371 }
10372 }
10373 }
10374
10375 /* Pass 6 - Optimize clean/dirty state */
10376 clean_registers(0,slen-1,1);
10377
10378 /* Pass 7 - Identify 32-bit registers */
a28c6ce8 10379#ifndef FORCE32
57871462 10380 provisional_r32();
10381
10382 u_int r32=0;
10383
10384 for (i=slen-1;i>=0;i--)
10385 {
10386 int hr;
10387 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10388 {
10389 if(ba[i]<start || ba[i]>=(start+slen*4))
10390 {
10391 // Branch out of this block, don't need anything
10392 r32=0;
10393 }
10394 else
10395 {
10396 // Internal branch
10397 // Need whatever matches the target
10398 // (and doesn't get overwritten by the delay slot instruction)
10399 r32=0;
10400 int t=(ba[i]-start)>>2;
10401 if(ba[i]>start+i*4) {
10402 // Forward branch
10403 if(!(requires_32bit[t]&~regs[i].was32))
10404 r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10405 }else{
10406 // Backward branch
10407 //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10408 // r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10409 if(!(pr32[t]&~regs[i].was32))
10410 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10411 }
10412 }
10413 // Conditional branch may need registers for following instructions
10414 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10415 {
10416 if(i<slen-2) {
10417 r32|=requires_32bit[i+2];
10418 r32&=regs[i].was32;
10419 // Mark this address as a branch target since it may be called
10420 // upon return from interrupt
10421 bt[i+2]=1;
10422 }
10423 }
10424 // Merge in delay slot
10425 if(!likely[i]) {
10426 // These are overwritten unless the branch is "likely"
10427 // and the delay slot is nullified if not taken
10428 r32&=~(1LL<<rt1[i+1]);
10429 r32&=~(1LL<<rt2[i+1]);
10430 }
10431 // Assume these are needed (delay slot)
10432 if(us1[i+1]>0)
10433 {
10434 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10435 }
10436 if(us2[i+1]>0)
10437 {
10438 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10439 }
10440 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10441 {
10442 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10443 }
10444 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10445 {
10446 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10447 }
10448 }
1e973cb0 10449 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 10450 {
10451 // SYSCALL instruction (software interrupt)
10452 r32=0;
10453 }
10454 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10455 {
10456 // ERET instruction (return from interrupt)
10457 r32=0;
10458 }
10459 // Check 32 bits
10460 r32&=~(1LL<<rt1[i]);
10461 r32&=~(1LL<<rt2[i]);
10462 if(us1[i]>0)
10463 {
10464 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10465 }
10466 if(us2[i]>0)
10467 {
10468 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10469 }
10470 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
10471 {
10472 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
10473 }
10474 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
10475 {
10476 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
10477 }
10478 requires_32bit[i]=r32;
10479
10480 // Dirty registers which are 32-bit, require 32-bit input
10481 // as they will be written as 32-bit values
10482 for(hr=0;hr<HOST_REGS;hr++)
10483 {
10484 if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
10485 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
10486 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
10487 requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
10488 }
10489 }
10490 }
10491 //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
10492 }
a28c6ce8 10493#endif
57871462 10494
10495 if(itype[slen-1]==SPAN) {
10496 bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
10497 }
10498
10499 /* Debug/disassembly */
10500 if((void*)assem_debug==(void*)printf)
10501 for(i=0;i<slen;i++)
10502 {
10503 printf("U:");
10504 int r;
10505 for(r=1;r<=CCREG;r++) {
10506 if((unneeded_reg[i]>>r)&1) {
10507 if(r==HIREG) printf(" HI");
10508 else if(r==LOREG) printf(" LO");
10509 else printf(" r%d",r);
10510 }
10511 }
90ae6d4e 10512#ifndef FORCE32
57871462 10513 printf(" UU:");
10514 for(r=1;r<=CCREG;r++) {
10515 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
10516 if(r==HIREG) printf(" HI");
10517 else if(r==LOREG) printf(" LO");
10518 else printf(" r%d",r);
10519 }
10520 }
10521 printf(" 32:");
10522 for(r=0;r<=CCREG;r++) {
10523 //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10524 if((regs[i].was32>>r)&1) {
10525 if(r==CCREG) printf(" CC");
10526 else if(r==HIREG) printf(" HI");
10527 else if(r==LOREG) printf(" LO");
10528 else printf(" r%d",r);
10529 }
10530 }
90ae6d4e 10531#endif
57871462 10532 printf("\n");
10533 #if defined(__i386__) || defined(__x86_64__)
10534 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
10535 #endif
10536 #ifdef __arm__
10537 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
10538 #endif
10539 printf("needs: ");
10540 if(needed_reg[i]&1) printf("eax ");
10541 if((needed_reg[i]>>1)&1) printf("ecx ");
10542 if((needed_reg[i]>>2)&1) printf("edx ");
10543 if((needed_reg[i]>>3)&1) printf("ebx ");
10544 if((needed_reg[i]>>5)&1) printf("ebp ");
10545 if((needed_reg[i]>>6)&1) printf("esi ");
10546 if((needed_reg[i]>>7)&1) printf("edi ");
10547 printf("r:");
10548 for(r=0;r<=CCREG;r++) {
10549 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10550 if((requires_32bit[i]>>r)&1) {
10551 if(r==CCREG) printf(" CC");
10552 else if(r==HIREG) printf(" HI");
10553 else if(r==LOREG) printf(" LO");
10554 else printf(" r%d",r);
10555 }
10556 }
10557 printf("\n");
10558 /*printf("pr:");
10559 for(r=0;r<=CCREG;r++) {
10560 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10561 if((pr32[i]>>r)&1) {
10562 if(r==CCREG) printf(" CC");
10563 else if(r==HIREG) printf(" HI");
10564 else if(r==LOREG) printf(" LO");
10565 else printf(" r%d",r);
10566 }
10567 }
10568 if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
10569 printf("\n");*/
10570 #if defined(__i386__) || defined(__x86_64__)
10571 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
10572 printf("dirty: ");
10573 if(regs[i].wasdirty&1) printf("eax ");
10574 if((regs[i].wasdirty>>1)&1) printf("ecx ");
10575 if((regs[i].wasdirty>>2)&1) printf("edx ");
10576 if((regs[i].wasdirty>>3)&1) printf("ebx ");
10577 if((regs[i].wasdirty>>5)&1) printf("ebp ");
10578 if((regs[i].wasdirty>>6)&1) printf("esi ");
10579 if((regs[i].wasdirty>>7)&1) printf("edi ");
10580 #endif
10581 #ifdef __arm__
10582 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
10583 printf("dirty: ");
10584 if(regs[i].wasdirty&1) printf("r0 ");
10585 if((regs[i].wasdirty>>1)&1) printf("r1 ");
10586 if((regs[i].wasdirty>>2)&1) printf("r2 ");
10587 if((regs[i].wasdirty>>3)&1) printf("r3 ");
10588 if((regs[i].wasdirty>>4)&1) printf("r4 ");
10589 if((regs[i].wasdirty>>5)&1) printf("r5 ");
10590 if((regs[i].wasdirty>>6)&1) printf("r6 ");
10591 if((regs[i].wasdirty>>7)&1) printf("r7 ");
10592 if((regs[i].wasdirty>>8)&1) printf("r8 ");
10593 if((regs[i].wasdirty>>9)&1) printf("r9 ");
10594 if((regs[i].wasdirty>>10)&1) printf("r10 ");
10595 if((regs[i].wasdirty>>12)&1) printf("r12 ");
10596 #endif
10597 printf("\n");
10598 disassemble_inst(i);
10599 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
10600 #if defined(__i386__) || defined(__x86_64__)
10601 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
10602 if(regs[i].dirty&1) printf("eax ");
10603 if((regs[i].dirty>>1)&1) printf("ecx ");
10604 if((regs[i].dirty>>2)&1) printf("edx ");
10605 if((regs[i].dirty>>3)&1) printf("ebx ");
10606 if((regs[i].dirty>>5)&1) printf("ebp ");
10607 if((regs[i].dirty>>6)&1) printf("esi ");
10608 if((regs[i].dirty>>7)&1) printf("edi ");
10609 #endif
10610 #ifdef __arm__
10611 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
10612 if(regs[i].dirty&1) printf("r0 ");
10613 if((regs[i].dirty>>1)&1) printf("r1 ");
10614 if((regs[i].dirty>>2)&1) printf("r2 ");
10615 if((regs[i].dirty>>3)&1) printf("r3 ");
10616 if((regs[i].dirty>>4)&1) printf("r4 ");
10617 if((regs[i].dirty>>5)&1) printf("r5 ");
10618 if((regs[i].dirty>>6)&1) printf("r6 ");
10619 if((regs[i].dirty>>7)&1) printf("r7 ");
10620 if((regs[i].dirty>>8)&1) printf("r8 ");
10621 if((regs[i].dirty>>9)&1) printf("r9 ");
10622 if((regs[i].dirty>>10)&1) printf("r10 ");
10623 if((regs[i].dirty>>12)&1) printf("r12 ");
10624 #endif
10625 printf("\n");
10626 if(regs[i].isconst) {
10627 printf("constants: ");
10628 #if defined(__i386__) || defined(__x86_64__)
10629 if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
10630 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
10631 if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
10632 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
10633 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
10634 if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
10635 if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
10636 #endif
10637 #ifdef __arm__
10638 if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
10639 if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
10640 if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
10641 if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
10642 if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
10643 if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
10644 if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
10645 if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
10646 if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
10647 if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
10648 if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
10649 if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
10650 #endif
10651 printf("\n");
10652 }
90ae6d4e 10653#ifndef FORCE32
57871462 10654 printf(" 32:");
10655 for(r=0;r<=CCREG;r++) {
10656 if((regs[i].is32>>r)&1) {
10657 if(r==CCREG) printf(" CC");
10658 else if(r==HIREG) printf(" HI");
10659 else if(r==LOREG) printf(" LO");
10660 else printf(" r%d",r);
10661 }
10662 }
10663 printf("\n");
90ae6d4e 10664#endif
57871462 10665 /*printf(" p32:");
10666 for(r=0;r<=CCREG;r++) {
10667 if((p32[i]>>r)&1) {
10668 if(r==CCREG) printf(" CC");
10669 else if(r==HIREG) printf(" HI");
10670 else if(r==LOREG) printf(" LO");
10671 else printf(" r%d",r);
10672 }
10673 }
10674 if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
10675 else printf("\n");*/
10676 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10677 #if defined(__i386__) || defined(__x86_64__)
10678 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
10679 if(branch_regs[i].dirty&1) printf("eax ");
10680 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
10681 if((branch_regs[i].dirty>>2)&1) printf("edx ");
10682 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
10683 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
10684 if((branch_regs[i].dirty>>6)&1) printf("esi ");
10685 if((branch_regs[i].dirty>>7)&1) printf("edi ");
10686 #endif
10687 #ifdef __arm__
10688 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
10689 if(branch_regs[i].dirty&1) printf("r0 ");
10690 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
10691 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
10692 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
10693 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
10694 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
10695 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
10696 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
10697 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
10698 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
10699 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
10700 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
10701 #endif
90ae6d4e 10702#ifndef FORCE32
57871462 10703 printf(" 32:");
10704 for(r=0;r<=CCREG;r++) {
10705 if((branch_regs[i].is32>>r)&1) {
10706 if(r==CCREG) printf(" CC");
10707 else if(r==HIREG) printf(" HI");
10708 else if(r==LOREG) printf(" LO");
10709 else printf(" r%d",r);
10710 }
10711 }
10712 printf("\n");
90ae6d4e 10713#endif
57871462 10714 }
10715 }
10716
10717 /* Pass 8 - Assembly */
10718 linkcount=0;stubcount=0;
10719 ds=0;is_delayslot=0;
10720 cop1_usable=0;
10721 uint64_t is32_pre=0;
10722 u_int dirty_pre=0;
10723 u_int beginning=(u_int)out;
10724 if((u_int)addr&1) {
10725 ds=1;
10726 pagespan_ds();
10727 }
9ad4d757 10728 u_int instr_addr0_override=0;
10729
10730#ifdef PCSX
10731 if (start == 0x80030000) {
10732 // nasty hack for fastbios thing
10733 instr_addr0_override=(u_int)out;
10734 emit_movimm(start,0);
10735 emit_readword((int)&pcaddr,1);
10736 emit_writeword(0,(int)&pcaddr);
10737 emit_cmp(0,1);
10738 emit_jne((int)new_dyna_leave);
10739 }
10740#endif
57871462 10741 for(i=0;i<slen;i++)
10742 {
10743 //if(ds) printf("ds: ");
10744 if((void*)assem_debug==(void*)printf) disassemble_inst(i);
10745 if(ds) {
10746 ds=0; // Skip delay slot
10747 if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
10748 instr_addr[i]=0;
10749 } else {
10750 #ifndef DESTRUCTIVE_WRITEBACK
10751 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10752 {
10753 wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
10754 unneeded_reg[i],unneeded_reg_upper[i]);
10755 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
10756 unneeded_reg[i],unneeded_reg_upper[i]);
10757 }
10758 is32_pre=regs[i].is32;
10759 dirty_pre=regs[i].dirty;
10760 #endif
10761 // write back
10762 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10763 {
10764 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
10765 unneeded_reg[i],unneeded_reg_upper[i]);
10766 loop_preload(regmap_pre[i],regs[i].regmap_entry);
10767 }
10768 // branch target entry point
10769 instr_addr[i]=(u_int)out;
10770 assem_debug("<->\n");
10771 // load regs
10772 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
10773 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
10774 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
10775 address_generation(i,&regs[i],regs[i].regmap_entry);
10776 load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
10777 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10778 {
10779 // Load the delay slot registers if necessary
10780 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10781 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10782 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10783 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
b9b61529 10784 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
57871462 10785 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10786 }
10787 else if(i+1<slen)
10788 {
10789 // Preload registers for following instruction
10790 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10791 if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
10792 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10793 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10794 if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
10795 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
10796 }
10797 // TODO: if(is_ooo(i)) address_generation(i+1);
10798 if(itype[i]==CJUMP||itype[i]==FJUMP)
10799 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
b9b61529 10800 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
57871462 10801 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10802 if(bt[i]) cop1_usable=0;
10803 // assemble
10804 switch(itype[i]) {
10805 case ALU:
10806 alu_assemble(i,&regs[i]);break;
10807 case IMM16:
10808 imm16_assemble(i,&regs[i]);break;
10809 case SHIFT:
10810 shift_assemble(i,&regs[i]);break;
10811 case SHIFTIMM:
10812 shiftimm_assemble(i,&regs[i]);break;
10813 case LOAD:
10814 load_assemble(i,&regs[i]);break;
10815 case LOADLR:
10816 loadlr_assemble(i,&regs[i]);break;
10817 case STORE:
10818 store_assemble(i,&regs[i]);break;
10819 case STORELR:
10820 storelr_assemble(i,&regs[i]);break;
10821 case COP0:
10822 cop0_assemble(i,&regs[i]);break;
10823 case COP1:
10824 cop1_assemble(i,&regs[i]);break;
10825 case C1LS:
10826 c1ls_assemble(i,&regs[i]);break;
b9b61529 10827 case COP2:
10828 cop2_assemble(i,&regs[i]);break;
10829 case C2LS:
10830 c2ls_assemble(i,&regs[i]);break;
10831 case C2OP:
10832 c2op_assemble(i,&regs[i]);break;
57871462 10833 case FCONV:
10834 fconv_assemble(i,&regs[i]);break;
10835 case FLOAT:
10836 float_assemble(i,&regs[i]);break;
10837 case FCOMP:
10838 fcomp_assemble(i,&regs[i]);break;
10839 case MULTDIV:
10840 multdiv_assemble(i,&regs[i]);break;
10841 case MOV:
10842 mov_assemble(i,&regs[i]);break;
10843 case SYSCALL:
10844 syscall_assemble(i,&regs[i]);break;
7139f3c8 10845 case HLECALL:
10846 hlecall_assemble(i,&regs[i]);break;
1e973cb0 10847 case INTCALL:
10848 intcall_assemble(i,&regs[i]);break;
57871462 10849 case UJUMP:
10850 ujump_assemble(i,&regs[i]);ds=1;break;
10851 case RJUMP:
10852 rjump_assemble(i,&regs[i]);ds=1;break;
10853 case CJUMP:
10854 cjump_assemble(i,&regs[i]);ds=1;break;
10855 case SJUMP:
10856 sjump_assemble(i,&regs[i]);ds=1;break;
10857 case FJUMP:
10858 fjump_assemble(i,&regs[i]);ds=1;break;
10859 case SPAN:
10860 pagespan_assemble(i,&regs[i]);break;
10861 }
10862 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10863 literal_pool(1024);
10864 else
10865 literal_pool_jumpover(256);
10866 }
10867 }
10868 //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
10869 // If the block did not end with an unconditional branch,
10870 // add a jump to the next instruction.
10871 if(i>1) {
10872 if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
10873 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10874 assert(i==slen);
10875 if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
10876 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10877 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10878 emit_loadreg(CCREG,HOST_CCREG);
10879 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10880 }
10881 else if(!likely[i-2])
10882 {
10883 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
10884 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
10885 }
10886 else
10887 {
10888 store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
10889 assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
10890 }
10891 add_to_linker((int)out,start+i*4,0);
10892 emit_jmp(0);
10893 }
10894 }
10895 else
10896 {
10897 assert(i>0);
10898 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10899 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10900 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10901 emit_loadreg(CCREG,HOST_CCREG);
10902 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10903 add_to_linker((int)out,start+i*4,0);
10904 emit_jmp(0);
10905 }
10906
10907 // TODO: delay slot stubs?
10908 // Stubs
10909 for(i=0;i<stubcount;i++)
10910 {
10911 switch(stubs[i][0])
10912 {
10913 case LOADB_STUB:
10914 case LOADH_STUB:
10915 case LOADW_STUB:
10916 case LOADD_STUB:
10917 case LOADBU_STUB:
10918 case LOADHU_STUB:
10919 do_readstub(i);break;
10920 case STOREB_STUB:
10921 case STOREH_STUB:
10922 case STOREW_STUB:
10923 case STORED_STUB:
10924 do_writestub(i);break;
10925 case CC_STUB:
10926 do_ccstub(i);break;
10927 case INVCODE_STUB:
10928 do_invstub(i);break;
10929 case FP_STUB:
10930 do_cop1stub(i);break;
10931 case STORELR_STUB:
10932 do_unalignedwritestub(i);break;
10933 }
10934 }
10935
9ad4d757 10936 if (instr_addr0_override)
10937 instr_addr[0] = instr_addr0_override;
10938
57871462 10939 /* Pass 9 - Linker */
10940 for(i=0;i<linkcount;i++)
10941 {
10942 assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
10943 literal_pool(64);
10944 if(!link_addr[i][2])
10945 {
10946 void *stub=out;
10947 void *addr=check_addr(link_addr[i][1]);
10948 emit_extjump(link_addr[i][0],link_addr[i][1]);
10949 if(addr) {
10950 set_jump_target(link_addr[i][0],(int)addr);
10951 add_link(link_addr[i][1],stub);
10952 }
10953 else set_jump_target(link_addr[i][0],(int)stub);
10954 }
10955 else
10956 {
10957 // Internal branch
10958 int target=(link_addr[i][1]-start)>>2;
10959 assert(target>=0&&target<slen);
10960 assert(instr_addr[target]);
10961 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10962 //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
10963 //#else
10964 set_jump_target(link_addr[i][0],instr_addr[target]);
10965 //#endif
10966 }
10967 }
10968 // External Branch Targets (jump_in)
10969 if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
10970 for(i=0;i<slen;i++)
10971 {
10972 if(bt[i]||i==0)
10973 {
10974 if(instr_addr[i]) // TODO - delay slots (=null)
10975 {
10976 u_int vaddr=start+i*4;
94d23bb9 10977 u_int page=get_page(vaddr);
10978 u_int vpage=get_vpage(vaddr);
57871462 10979 literal_pool(256);
10980 //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
a28c6ce8 10981#ifndef FORCE32
57871462 10982 if(!requires_32bit[i])
a28c6ce8 10983#else
10984 if(1)
10985#endif
57871462 10986 {
10987 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
10988 assem_debug("jump_in: %x\n",start+i*4);
10989 ll_add(jump_dirty+vpage,vaddr,(void *)out);
10990 int entry_point=do_dirty_stub(i);
10991 ll_add(jump_in+page,vaddr,(void *)entry_point);
10992 // If there was an existing entry in the hash table,
10993 // replace it with the new address.
10994 // Don't add new entries. We'll insert the
10995 // ones that actually get used in check_addr().
10996 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
10997 if(ht_bin[0]==vaddr) {
10998 ht_bin[1]=entry_point;
10999 }
11000 if(ht_bin[2]==vaddr) {
11001 ht_bin[3]=entry_point;
11002 }
11003 }
11004 else
11005 {
11006 u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
11007 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11008 assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
11009 //int entry_point=(int)out;
11010 ////assem_debug("entry_point: %x\n",entry_point);
11011 //load_regs_entry(i);
11012 //if(entry_point==(int)out)
11013 // entry_point=instr_addr[i];
11014 //else
11015 // emit_jmp(instr_addr[i]);
11016 //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11017 ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
11018 int entry_point=do_dirty_stub(i);
11019 ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11020 }
11021 }
11022 }
11023 }
11024 // Write out the literal pool if necessary
11025 literal_pool(0);
11026 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11027 // Align code
11028 if(((u_int)out)&7) emit_addnop(13);
11029 #endif
11030 assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
11031 //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
11032 memcpy(copy,source,slen*4);
11033 copy+=slen*4;
11034
11035 #ifdef __arm__
11036 __clear_cache((void *)beginning,out);
11037 #endif
11038
11039 // If we're within 256K of the end of the buffer,
11040 // start over from the beginning. (Is 256K enough?)
11041 if((int)out>BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
11042
11043 // Trap writes to any of the pages we compiled
11044 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
11045 invalid_code[i]=0;
90ae6d4e 11046#ifndef DISABLE_TLB
57871462 11047 memory_map[i]|=0x40000000;
11048 if((signed int)start>=(signed int)0xC0000000) {
11049 assert(using_tlb);
11050 j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
11051 invalid_code[j]=0;
11052 memory_map[j]|=0x40000000;
11053 //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
11054 }
90ae6d4e 11055#endif
57871462 11056 }
b12c9fb8 11057#ifdef PCSX
11058 // PCSX maps all RAM mirror invalid_code tests to 0x80000000..0x80000000+RAM_SIZE
11059 if(get_page(start)<(RAM_SIZE>>12))
11060 for(i=start>>12;i<=(start+slen*4)>>12;i++)
11061 invalid_code[((u_int)0x80000000>>12)|i]=0;
11062#endif
57871462 11063
11064 /* Pass 10 - Free memory by expiring oldest blocks */
11065
11066 int end=((((int)out-BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
11067 while(expirep!=end)
11068 {
11069 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
11070 int base=BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
11071 inv_debug("EXP: Phase %d\n",expirep);
11072 switch((expirep>>11)&3)
11073 {
11074 case 0:
11075 // Clear jump_in and jump_dirty
11076 ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
11077 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
11078 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
11079 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
11080 break;
11081 case 1:
11082 // Clear pointers
11083 ll_kill_pointers(jump_out[expirep&2047],base,shift);
11084 ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
11085 break;
11086 case 2:
11087 // Clear hash table
11088 for(i=0;i<32;i++) {
11089 int *ht_bin=hash_table[((expirep&2047)<<5)+i];
11090 if((ht_bin[3]>>shift)==(base>>shift) ||
11091 ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11092 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
11093 ht_bin[2]=ht_bin[3]=-1;
11094 }
11095 if((ht_bin[1]>>shift)==(base>>shift) ||
11096 ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11097 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
11098 ht_bin[0]=ht_bin[2];
11099 ht_bin[1]=ht_bin[3];
11100 ht_bin[2]=ht_bin[3]=-1;
11101 }
11102 }
11103 break;
11104 case 3:
11105 // Clear jump_out
dd3a91a1 11106 #ifdef __arm__
11107 if((expirep&2047)==0)
11108 do_clear_cache();
11109 #endif
57871462 11110 ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
11111 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
11112 break;
11113 }
11114 expirep=(expirep+1)&65535;
11115 }
11116 return 0;
11117}
b9b61529 11118
11119// vim:shiftwidth=2:expandtab
ARM optimized PCSX fork