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drc: don't cull ccreg
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
CommitLineData
57871462 1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
20d507ba 3 * Copyright (C) 2009-2011 Ari64 *
57871462 4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21#include <stdlib.h>
22#include <stdint.h> //include for uint64_t
23#include <assert.h>
d848b60a 24#include <errno.h>
4600ba03 25#include <sys/mman.h>
d148d265 26#ifdef __MACH__
27#include <libkern/OSCacheControl.h>
28#endif
1e212a25 29#ifdef _3DS
30#include <3ds_utils.h>
31#endif
32#ifdef VITA
33#include <psp2/kernel/sysmem.h>
34static int sceBlock;
35#endif
57871462 36
d148d265 37#include "new_dynarec_config.h"
3968e69e 38#include "../psxhle.h"
39#include "../psxinterpreter.h"
81dbbf4c 40#include "../gte.h"
41#include "emu_if.h" // emulator interface
57871462 42
d1e4ebd9 43#define noinline __attribute__((noinline,noclone))
b14b6a8f 44#ifndef ARRAY_SIZE
45#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
46#endif
e3c6bdb5 47#ifndef min
48#define min(a, b) ((b) < (a) ? (b) : (a))
49#endif
32631e6a 50#ifndef max
51#define max(a, b) ((b) > (a) ? (b) : (a))
52#endif
b14b6a8f 53
4600ba03 54//#define DISASM
32631e6a 55//#define ASSEM_PRINT
56
57#ifdef ASSEM_PRINT
58#define assem_debug printf
59#else
4600ba03 60#define assem_debug(...)
32631e6a 61#endif
62//#define inv_debug printf
4600ba03 63#define inv_debug(...)
57871462 64
65#ifdef __i386__
66#include "assem_x86.h"
67#endif
68#ifdef __x86_64__
69#include "assem_x64.h"
70#endif
71#ifdef __arm__
72#include "assem_arm.h"
73#endif
be516ebe 74#ifdef __aarch64__
75#include "assem_arm64.h"
76#endif
57871462 77
81dbbf4c 78#define RAM_SIZE 0x200000
57871462 79#define MAXBLOCK 4096
80#define MAX_OUTPUT_BLOCK_SIZE 262144
2573466a 81
2a014d73 82struct ndrc_mem
83{
84 u_char translation_cache[1 << TARGET_SIZE_2];
85 struct
86 {
87 struct tramp_insns ops[2048 / sizeof(struct tramp_insns)];
88 const void *f[2048 / sizeof(void *)];
89 } tramp;
90};
91
92#ifdef BASE_ADDR_DYNAMIC
93static struct ndrc_mem *ndrc;
94#else
95static struct ndrc_mem ndrc_ __attribute__((aligned(4096)));
96static struct ndrc_mem *ndrc = &ndrc_;
97#endif
98
b14b6a8f 99// stubs
100enum stub_type {
101 CC_STUB = 1,
102 FP_STUB = 2,
103 LOADB_STUB = 3,
104 LOADH_STUB = 4,
105 LOADW_STUB = 5,
106 LOADD_STUB = 6,
107 LOADBU_STUB = 7,
108 LOADHU_STUB = 8,
109 STOREB_STUB = 9,
110 STOREH_STUB = 10,
111 STOREW_STUB = 11,
112 STORED_STUB = 12,
113 STORELR_STUB = 13,
114 INVCODE_STUB = 14,
115};
116
57871462 117struct regstat
118{
2330734f 119 signed char regmap_entry[HOST_REGS]; // pre-insn + loop preloaded regs?
57871462 120 signed char regmap[HOST_REGS];
57871462 121 uint64_t wasdirty;
122 uint64_t dirty;
123 uint64_t u;
57871462 124 u_int wasconst;
125 u_int isconst;
8575a877 126 u_int loadedconst; // host regs that have constants loaded
127 u_int waswritten; // MIPS regs that were used as store base before
57871462 128};
129
de5a60c3 130// note: asm depends on this layout
57871462 131struct ll_entry
132{
133 u_int vaddr;
de5a60c3 134 u_int reg_sv_flags;
57871462 135 void *addr;
136 struct ll_entry *next;
137};
138
df4dc2b1 139struct ht_entry
140{
141 u_int vaddr[2];
142 void *tcaddr[2];
143};
144
b14b6a8f 145struct code_stub
146{
147 enum stub_type type;
148 void *addr;
149 void *retaddr;
150 u_int a;
151 uintptr_t b;
152 uintptr_t c;
153 u_int d;
154 u_int e;
155};
156
643aeae3 157struct link_entry
158{
159 void *addr;
160 u_int target;
161 u_int ext;
162};
163
cf95b4f0 164static struct decoded_insn
165{
166 u_char itype;
167 u_char opcode;
168 u_char opcode2;
169 u_char rs1;
170 u_char rs2;
171 u_char rt1;
172 u_char rt2;
173 u_char lt1;
174 u_char bt:1;
cf95b4f0 175 u_char ooo:1;
176 u_char is_ds:1;
fe807a8a 177 u_char is_jump:1;
178 u_char is_ujump:1;
37387d8b 179 u_char is_load:1;
180 u_char is_store:1;
cf95b4f0 181} dops[MAXBLOCK];
182
e2b5e7aa 183 // used by asm:
184 u_char *out;
df4dc2b1 185 struct ht_entry hash_table[65536] __attribute__((aligned(16)));
e2b5e7aa 186 struct ll_entry *jump_in[4096] __attribute__((aligned(16)));
187 struct ll_entry *jump_dirty[4096];
188
189 static struct ll_entry *jump_out[4096];
190 static u_int start;
191 static u_int *source;
192 static char insn[MAXBLOCK][10];
bedfea38 193 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
194 static uint64_t gte_rt[MAXBLOCK];
195 static uint64_t gte_unneeded[MAXBLOCK];
ffb0b9e0 196 static u_int smrv[32]; // speculated MIPS register values
197 static u_int smrv_strong; // mask or regs that are likely to have correct values
198 static u_int smrv_weak; // same, but somewhat less likely
199 static u_int smrv_strong_next; // same, but after current insn executes
200 static u_int smrv_weak_next;
e2b5e7aa 201 static int imm[MAXBLOCK];
202 static u_int ba[MAXBLOCK];
e2b5e7aa 203 static uint64_t unneeded_reg[MAXBLOCK];
e2b5e7aa 204 static uint64_t branch_unneeded_reg[MAXBLOCK];
2330734f 205 // pre-instruction [i], excluding loop-preload regs?
206 static signed char regmap_pre[MAXBLOCK][HOST_REGS];
40fca85b 207 // contains 'real' consts at [i] insn, but may differ from what's actually
208 // loaded in host reg as 'final' value is always loaded, see get_final_value()
209 static uint32_t current_constmap[HOST_REGS];
210 static uint32_t constmap[MAXBLOCK][HOST_REGS];
956f3129 211 static struct regstat regs[MAXBLOCK];
212 static struct regstat branch_regs[MAXBLOCK];
e2b5e7aa 213 static signed char minimum_free_regs[MAXBLOCK];
214 static u_int needed_reg[MAXBLOCK];
215 static u_int wont_dirty[MAXBLOCK];
216 static u_int will_dirty[MAXBLOCK];
217 static int ccadj[MAXBLOCK];
218 static int slen;
df4dc2b1 219 static void *instr_addr[MAXBLOCK];
643aeae3 220 static struct link_entry link_addr[MAXBLOCK];
e2b5e7aa 221 static int linkcount;
b14b6a8f 222 static struct code_stub stubs[MAXBLOCK*3];
e2b5e7aa 223 static int stubcount;
224 static u_int literals[1024][2];
225 static int literalcount;
226 static int is_delayslot;
e2b5e7aa 227 static char shadow[1048576] __attribute__((aligned(16)));
228 static void *copy;
229 static int expirep;
230 static u_int stop_after_jal;
39b71d9a 231 static u_int f1_hack; // 0 - off, ~0 - capture address, else addr
e2b5e7aa 232
233 int new_dynarec_hacks;
d62c125a 234 int new_dynarec_hacks_pergame;
32631e6a 235 int new_dynarec_hacks_old;
e2b5e7aa 236 int new_dynarec_did_compile;
687b4580 237
d62c125a 238 #define HACK_ENABLED(x) ((new_dynarec_hacks | new_dynarec_hacks_pergame) & (x))
239
687b4580 240 extern int cycle_count; // ... until end of the timeslice, counts -N -> 0
241 extern int last_count; // last absolute target, often = next_interupt
242 extern int pcaddr;
243 extern int pending_exception;
244 extern int branch_target;
37387d8b 245 extern uintptr_t ram_offset;
d1e4ebd9 246 extern uintptr_t mini_ht[32][2];
57871462 247 extern u_char restore_candidate[512];
57871462 248
249 /* registers that may be allocated */
250 /* 1-31 gpr */
7c3a5182 251#define LOREG 32 // lo
252#define HIREG 33 // hi
00fa9369 253//#define FSREG 34 // FPU status (FCSR)
57871462 254#define CSREG 35 // Coprocessor status
255#define CCREG 36 // Cycle count
256#define INVCP 37 // Pointer to invalid_code
1edfcc68 257//#define MMREG 38 // Pointer to memory_map
37387d8b 258#define ROREG 39 // ram offset (if rdram!=0x80000000)
619e5ded 259#define TEMPREG 40
260#define FTEMP 40 // FPU temporary register
261#define PTEMP 41 // Prefetch temporary register
1edfcc68 262//#define TLREG 42 // TLB mapping offset
619e5ded 263#define RHASH 43 // Return address hash
264#define RHTBL 44 // Return address hash table address
265#define RTEMP 45 // JR/JALR address register
266#define MAXREG 45
267#define AGEN1 46 // Address generation temporary register
1edfcc68 268//#define AGEN2 47 // Address generation temporary register
269//#define MGEN1 48 // Maptable address generation temporary register
270//#define MGEN2 49 // Maptable address generation temporary register
619e5ded 271#define BTREG 50 // Branch target temporary register
57871462 272
273 /* instruction types */
274#define NOP 0 // No operation
275#define LOAD 1 // Load
276#define STORE 2 // Store
277#define LOADLR 3 // Unaligned load
278#define STORELR 4 // Unaligned store
9f51b4b9 279#define MOV 5 // Move
57871462 280#define ALU 6 // Arithmetic/logic
281#define MULTDIV 7 // Multiply/divide
282#define SHIFT 8 // Shift by register
283#define SHIFTIMM 9// Shift by immediate
284#define IMM16 10 // 16-bit immediate
285#define RJUMP 11 // Unconditional jump to register
286#define UJUMP 12 // Unconditional jump
287#define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
288#define SJUMP 14 // Conditional branch (regimm format)
289#define COP0 15 // Coprocessor 0
290#define COP1 16 // Coprocessor 1
291#define C1LS 17 // Coprocessor 1 load/store
ad49de89 292//#define FJUMP 18 // Conditional branch (floating point)
00fa9369 293//#define FLOAT 19 // Floating point unit
294//#define FCONV 20 // Convert integer to float
295//#define FCOMP 21 // Floating point compare (sets FSREG)
57871462 296#define SYSCALL 22// SYSCALL
297#define OTHER 23 // Other
298#define SPAN 24 // Branch/delay slot spans 2 pages
299#define NI 25 // Not implemented
7139f3c8 300#define HLECALL 26// PCSX fake opcodes for HLE
b9b61529 301#define COP2 27 // Coprocessor 2 move
302#define C2LS 28 // Coprocessor 2 load/store
303#define C2OP 29 // Coprocessor 2 operation
1e973cb0 304#define INTCALL 30// Call interpreter to handle rare corner cases
57871462 305
57871462 306 /* branch codes */
307#define TAKEN 1
308#define NOTTAKEN 2
309#define NULLDS 3
310
7c3a5182 311#define DJT_1 (void *)1l // no function, just a label in assem_debug log
312#define DJT_2 (void *)2l
313
57871462 314// asm linkage
3968e69e 315int new_recompile_block(u_int addr);
57871462 316void *get_addr_ht(u_int vaddr);
317void invalidate_block(u_int block);
318void invalidate_addr(u_int addr);
319void remove_hash(int vaddr);
57871462 320void dyna_linker();
321void dyna_linker_ds();
322void verify_code();
57871462 323void verify_code_ds();
324void cc_interrupt();
325void fp_exception();
326void fp_exception_ds();
3968e69e 327void jump_to_new_pc();
81dbbf4c 328void call_gteStall();
7139f3c8 329void new_dyna_leave();
57871462 330
57871462 331// Needed by assembler
2330734f 332static void wb_register(signed char r, const signed char regmap[], uint64_t dirty);
333static void wb_dirtys(const signed char i_regmap[], uint64_t i_dirty);
334static void wb_needed_dirtys(const signed char i_regmap[], uint64_t i_dirty, int addr);
335static void load_all_regs(const signed char i_regmap[]);
336static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[]);
e2b5e7aa 337static void load_regs_entry(int t);
2330734f 338static void load_all_consts(const signed char regmap[], u_int dirty, int i);
81dbbf4c 339static u_int get_host_reglist(const signed char *regmap);
e2b5e7aa 340
3968e69e 341static int verify_dirty(const u_int *ptr);
e2b5e7aa 342static int get_final_value(int hr, int i, int *value);
b14b6a8f 343static void add_stub(enum stub_type type, void *addr, void *retaddr,
344 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e);
345static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
81dbbf4c 346 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist);
643aeae3 347static void add_to_linker(void *addr, u_int target, int ext);
37387d8b 348static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs,
349 int addr, int *offset_reg, int *addr_reg_override);
687b4580 350static void *get_direct_memhandler(void *table, u_int addr,
351 enum stub_type type, uintptr_t *addr_host);
32631e6a 352static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist);
687b4580 353static void pass_args(int a0, int a1);
2a014d73 354static void emit_far_jump(const void *f);
355static void emit_far_call(const void *f);
57871462 356
d148d265 357static void mprotect_w_x(void *start, void *end, int is_x)
358{
359#ifdef NO_WRITE_EXEC
1e212a25 360 #if defined(VITA)
361 // *Open* enables write on all memory that was
362 // allocated by sceKernelAllocMemBlockForVM()?
363 if (is_x)
364 sceKernelCloseVMDomain();
365 else
366 sceKernelOpenVMDomain();
367 #else
d148d265 368 u_long mstart = (u_long)start & ~4095ul;
369 u_long mend = (u_long)end;
370 if (mprotect((void *)mstart, mend - mstart,
371 PROT_READ | (is_x ? PROT_EXEC : PROT_WRITE)) != 0)
372 SysPrintf("mprotect(%c) failed: %s\n", is_x ? 'x' : 'w', strerror(errno));
1e212a25 373 #endif
d148d265 374#endif
375}
376
377static void start_tcache_write(void *start, void *end)
378{
379 mprotect_w_x(start, end, 0);
380}
381
382static void end_tcache_write(void *start, void *end)
383{
919981d0 384#if defined(__arm__) || defined(__aarch64__)
d148d265 385 size_t len = (char *)end - (char *)start;
386 #if defined(__BLACKBERRY_QNX__)
387 msync(start, len, MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE);
388 #elif defined(__MACH__)
389 sys_cache_control(kCacheFunctionPrepareForExecution, start, len);
390 #elif defined(VITA)
1e212a25 391 sceKernelSyncVMDomain(sceBlock, start, len);
392 #elif defined(_3DS)
393 ctr_flush_invalidate_cache();
919981d0 394 #elif defined(__aarch64__)
395 // as of 2021, __clear_cache() is still broken on arm64
396 // so here is a custom one :(
397 clear_cache_arm64(start, end);
d148d265 398 #else
399 __clear_cache(start, end);
400 #endif
401 (void)len;
402#endif
403
404 mprotect_w_x(start, end, 1);
405}
406
407static void *start_block(void)
408{
409 u_char *end = out + MAX_OUTPUT_BLOCK_SIZE;
2a014d73 410 if (end > ndrc->translation_cache + sizeof(ndrc->translation_cache))
411 end = ndrc->translation_cache + sizeof(ndrc->translation_cache);
d148d265 412 start_tcache_write(out, end);
413 return out;
414}
415
416static void end_block(void *start)
417{
418 end_tcache_write(start, out);
419}
420
919981d0 421// also takes care of w^x mappings when patching code
422static u_int needs_clear_cache[1<<(TARGET_SIZE_2-17)];
423
424static void mark_clear_cache(void *target)
425{
426 uintptr_t offset = (u_char *)target - ndrc->translation_cache;
427 u_int mask = 1u << ((offset >> 12) & 31);
428 if (!(needs_clear_cache[offset >> 17] & mask)) {
429 char *start = (char *)((uintptr_t)target & ~4095l);
430 start_tcache_write(start, start + 4095);
431 needs_clear_cache[offset >> 17] |= mask;
432 }
433}
434
435// Clearing the cache is rather slow on ARM Linux, so mark the areas
436// that need to be cleared, and then only clear these areas once.
437static void do_clear_cache(void)
438{
439 int i, j;
440 for (i = 0; i < (1<<(TARGET_SIZE_2-17)); i++)
441 {
442 u_int bitmap = needs_clear_cache[i];
443 if (!bitmap)
444 continue;
445 for (j = 0; j < 32; j++)
446 {
447 u_char *start, *end;
448 if (!(bitmap & (1<<j)))
449 continue;
450
451 start = ndrc->translation_cache + i*131072 + j*4096;
452 end = start + 4095;
453 for (j++; j < 32; j++) {
454 if (!(bitmap & (1<<j)))
455 break;
456 end += 4096;
457 }
458 end_tcache_write(start, end);
459 }
460 needs_clear_cache[i] = 0;
461 }
462}
463
57871462 464//#define DEBUG_CYCLE_COUNT 1
465
b6e87b2b 466#define NO_CYCLE_PENALTY_THR 12
467
26bd3dad 468int cycle_multiplier = CYCLE_MULT_DEFAULT; // 100 for 1.0
a3203cf4 469int cycle_multiplier_override;
32631e6a 470int cycle_multiplier_old;
4e9dcd7f 471
472static int CLOCK_ADJUST(int x)
473{
26bd3dad 474 int m = cycle_multiplier_override && cycle_multiplier == CYCLE_MULT_DEFAULT
a3203cf4 475 ? cycle_multiplier_override : cycle_multiplier;
4e9dcd7f 476 int s=(x>>31)|1;
a3203cf4 477 return (x * m + s * 50) / 100;
4e9dcd7f 478}
479
4919de1e 480static int ds_writes_rjump_rs(int i)
481{
cf95b4f0 482 return dops[i].rs1 != 0 && (dops[i].rs1 == dops[i+1].rt1 || dops[i].rs1 == dops[i+1].rt2);
4919de1e 483}
484
94d23bb9 485static u_int get_page(u_int vaddr)
57871462 486{
0ce47d46 487 u_int page=vaddr&~0xe0000000;
488 if (page < 0x1000000)
489 page &= ~0x0e00000; // RAM mirrors
490 page>>=12;
57871462 491 if(page>2048) page=2048+(page&2047);
94d23bb9 492 return page;
493}
494
d25604ca 495// no virtual mem in PCSX
496static u_int get_vpage(u_int vaddr)
497{
498 return get_page(vaddr);
499}
94d23bb9 500
df4dc2b1 501static struct ht_entry *hash_table_get(u_int vaddr)
502{
503 return &hash_table[((vaddr>>16)^vaddr)&0xFFFF];
504}
505
506static void hash_table_add(struct ht_entry *ht_bin, u_int vaddr, void *tcaddr)
507{
508 ht_bin->vaddr[1] = ht_bin->vaddr[0];
509 ht_bin->tcaddr[1] = ht_bin->tcaddr[0];
510 ht_bin->vaddr[0] = vaddr;
511 ht_bin->tcaddr[0] = tcaddr;
512}
513
514// some messy ari64's code, seems to rely on unsigned 32bit overflow
515static int doesnt_expire_soon(void *tcaddr)
516{
517 u_int diff = (u_int)((u_char *)tcaddr - out) << (32-TARGET_SIZE_2);
518 return diff > (u_int)(0x60000000 + (MAX_OUTPUT_BLOCK_SIZE << (32-TARGET_SIZE_2)));
519}
520
94d23bb9 521// Get address from virtual address
522// This is called from the recompiled JR/JALR instructions
d1e4ebd9 523void noinline *get_addr(u_int vaddr)
94d23bb9 524{
525 u_int page=get_page(vaddr);
526 u_int vpage=get_vpage(vaddr);
57871462 527 struct ll_entry *head;
528 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
529 head=jump_in[page];
530 while(head!=NULL) {
de5a60c3 531 if(head->vaddr==vaddr) {
643aeae3 532 //printf("TRACE: count=%d next=%d (get_addr match %x: %p)\n",Count,next_interupt,vaddr,head->addr);
df4dc2b1 533 hash_table_add(hash_table_get(vaddr), vaddr, head->addr);
57871462 534 return head->addr;
535 }
536 head=head->next;
537 }
538 head=jump_dirty[vpage];
539 while(head!=NULL) {
de5a60c3 540 if(head->vaddr==vaddr) {
643aeae3 541 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %p)\n",Count,next_interupt,vaddr,head->addr);
57871462 542 // Don't restore blocks which are about to expire from the cache
df4dc2b1 543 if (doesnt_expire_soon(head->addr))
544 if (verify_dirty(head->addr)) {
57871462 545 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
546 invalid_code[vaddr>>12]=0;
9be4ba64 547 inv_code_start=inv_code_end=~0;
57871462 548 if(vpage<2048) {
57871462 549 restore_candidate[vpage>>3]|=1<<(vpage&7);
550 }
551 else restore_candidate[page>>3]|=1<<(page&7);
df4dc2b1 552 struct ht_entry *ht_bin = hash_table_get(vaddr);
553 if (ht_bin->vaddr[0] == vaddr)
554 ht_bin->tcaddr[0] = head->addr; // Replace existing entry
57871462 555 else
df4dc2b1 556 hash_table_add(ht_bin, vaddr, head->addr);
557
57871462 558 return head->addr;
559 }
560 }
561 head=head->next;
562 }
563 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
564 int r=new_recompile_block(vaddr);
565 if(r==0) return get_addr(vaddr);
566 // Execute in unmapped page, generate pagefault execption
567 Status|=2;
568 Cause=(vaddr<<31)|0x8;
569 EPC=(vaddr&1)?vaddr-5:vaddr;
570 BadVAddr=(vaddr&~1);
571 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
572 EntryHi=BadVAddr&0xFFFFE000;
573 return get_addr_ht(0x80000000);
574}
575// Look up address in hash table first
576void *get_addr_ht(u_int vaddr)
577{
578 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
df4dc2b1 579 const struct ht_entry *ht_bin = hash_table_get(vaddr);
580 if (ht_bin->vaddr[0] == vaddr) return ht_bin->tcaddr[0];
581 if (ht_bin->vaddr[1] == vaddr) return ht_bin->tcaddr[1];
57871462 582 return get_addr(vaddr);
583}
584
57871462 585void clear_all_regs(signed char regmap[])
586{
587 int hr;
588 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
589}
590
d1e4ebd9 591static signed char get_reg(const signed char regmap[],int r)
57871462 592{
593 int hr;
594 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
595 return -1;
596}
597
598// Find a register that is available for two consecutive cycles
d1e4ebd9 599static signed char get_reg2(signed char regmap1[], const signed char regmap2[], int r)
57871462 600{
601 int hr;
602 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
603 return -1;
604}
605
606int count_free_regs(signed char regmap[])
607{
608 int count=0;
609 int hr;
610 for(hr=0;hr<HOST_REGS;hr++)
611 {
612 if(hr!=EXCLUDE_REG) {
613 if(regmap[hr]<0) count++;
614 }
615 }
616 return count;
617}
618
619void dirty_reg(struct regstat *cur,signed char reg)
620{
621 int hr;
622 if(!reg) return;
623 for (hr=0;hr<HOST_REGS;hr++) {
624 if((cur->regmap[hr]&63)==reg) {
625 cur->dirty|=1<<hr;
626 }
627 }
628}
629
40fca85b 630static void set_const(struct regstat *cur, signed char reg, uint32_t value)
57871462 631{
632 int hr;
633 if(!reg) return;
634 for (hr=0;hr<HOST_REGS;hr++) {
635 if(cur->regmap[hr]==reg) {
636 cur->isconst|=1<<hr;
956f3129 637 current_constmap[hr]=value;
57871462 638 }
57871462 639 }
640}
641
40fca85b 642static void clear_const(struct regstat *cur, signed char reg)
57871462 643{
644 int hr;
645 if(!reg) return;
646 for (hr=0;hr<HOST_REGS;hr++) {
647 if((cur->regmap[hr]&63)==reg) {
648 cur->isconst&=~(1<<hr);
649 }
650 }
651}
652
40fca85b 653static int is_const(struct regstat *cur, signed char reg)
57871462 654{
655 int hr;
79c75f1b 656 if(reg<0) return 0;
57871462 657 if(!reg) return 1;
658 for (hr=0;hr<HOST_REGS;hr++) {
659 if((cur->regmap[hr]&63)==reg) {
660 return (cur->isconst>>hr)&1;
661 }
662 }
663 return 0;
664}
40fca85b 665
666static uint32_t get_const(struct regstat *cur, signed char reg)
57871462 667{
668 int hr;
669 if(!reg) return 0;
670 for (hr=0;hr<HOST_REGS;hr++) {
671 if(cur->regmap[hr]==reg) {
956f3129 672 return current_constmap[hr];
57871462 673 }
674 }
c43b5311 675 SysPrintf("Unknown constant in r%d\n",reg);
7c3a5182 676 abort();
57871462 677}
678
679// Least soon needed registers
680// Look at the next ten instructions and see which registers
681// will be used. Try not to reallocate these.
682void lsn(u_char hsn[], int i, int *preferred_reg)
683{
684 int j;
685 int b=-1;
686 for(j=0;j<9;j++)
687 {
688 if(i+j>=slen) {
689 j=slen-i-1;
690 break;
691 }
fe807a8a 692 if (dops[i+j].is_ujump)
57871462 693 {
694 // Don't go past an unconditonal jump
695 j++;
696 break;
697 }
698 }
699 for(;j>=0;j--)
700 {
cf95b4f0 701 if(dops[i+j].rs1) hsn[dops[i+j].rs1]=j;
702 if(dops[i+j].rs2) hsn[dops[i+j].rs2]=j;
703 if(dops[i+j].rt1) hsn[dops[i+j].rt1]=j;
704 if(dops[i+j].rt2) hsn[dops[i+j].rt2]=j;
705 if(dops[i+j].itype==STORE || dops[i+j].itype==STORELR) {
57871462 706 // Stores can allocate zero
cf95b4f0 707 hsn[dops[i+j].rs1]=j;
708 hsn[dops[i+j].rs2]=j;
57871462 709 }
37387d8b 710 if (ram_offset && (dops[i+j].is_load || dops[i+j].is_store))
711 hsn[ROREG] = j;
57871462 712 // On some architectures stores need invc_ptr
713 #if defined(HOST_IMM8)
37387d8b 714 if (dops[i+j].is_store)
715 hsn[INVCP] = j;
57871462 716 #endif
cf95b4f0 717 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
57871462 718 {
719 hsn[CCREG]=j;
720 b=j;
721 }
722 }
723 if(b>=0)
724 {
725 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
726 {
727 // Follow first branch
728 int t=(ba[i+b]-start)>>2;
729 j=7-b;if(t+j>=slen) j=slen-t-1;
730 for(;j>=0;j--)
731 {
cf95b4f0 732 if(dops[t+j].rs1) if(hsn[dops[t+j].rs1]>j+b+2) hsn[dops[t+j].rs1]=j+b+2;
733 if(dops[t+j].rs2) if(hsn[dops[t+j].rs2]>j+b+2) hsn[dops[t+j].rs2]=j+b+2;
734 //if(dops[t+j].rt1) if(hsn[dops[t+j].rt1]>j+b+2) hsn[dops[t+j].rt1]=j+b+2;
735 //if(dops[t+j].rt2) if(hsn[dops[t+j].rt2]>j+b+2) hsn[dops[t+j].rt2]=j+b+2;
57871462 736 }
737 }
738 // TODO: preferred register based on backward branch
739 }
740 // Delay slot should preferably not overwrite branch conditions or cycle count
fe807a8a 741 if (i > 0 && dops[i-1].is_jump) {
cf95b4f0 742 if(dops[i-1].rs1) if(hsn[dops[i-1].rs1]>1) hsn[dops[i-1].rs1]=1;
743 if(dops[i-1].rs2) if(hsn[dops[i-1].rs2]>1) hsn[dops[i-1].rs2]=1;
57871462 744 hsn[CCREG]=1;
745 // ...or hash tables
746 hsn[RHASH]=1;
747 hsn[RHTBL]=1;
748 }
749 // Coprocessor load/store needs FTEMP, even if not declared
37387d8b 750 if(dops[i].itype==C2LS) {
57871462 751 hsn[FTEMP]=0;
752 }
753 // Load L/R also uses FTEMP as a temporary register
cf95b4f0 754 if(dops[i].itype==LOADLR) {
57871462 755 hsn[FTEMP]=0;
756 }
b7918751 757 // Also SWL/SWR/SDL/SDR
cf95b4f0 758 if(dops[i].opcode==0x2a||dops[i].opcode==0x2e||dops[i].opcode==0x2c||dops[i].opcode==0x2d) {
57871462 759 hsn[FTEMP]=0;
760 }
57871462 761 // Don't remove the miniht registers
cf95b4f0 762 if(dops[i].itype==UJUMP||dops[i].itype==RJUMP)
57871462 763 {
764 hsn[RHASH]=0;
765 hsn[RHTBL]=0;
766 }
767}
768
769// We only want to allocate registers if we're going to use them again soon
770int needed_again(int r, int i)
771{
772 int j;
773 int b=-1;
774 int rn=10;
9f51b4b9 775
fe807a8a 776 if (i > 0 && dops[i-1].is_ujump)
57871462 777 {
778 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
779 return 0; // Don't need any registers if exiting the block
780 }
781 for(j=0;j<9;j++)
782 {
783 if(i+j>=slen) {
784 j=slen-i-1;
785 break;
786 }
fe807a8a 787 if (dops[i+j].is_ujump)
57871462 788 {
789 // Don't go past an unconditonal jump
790 j++;
791 break;
792 }
cf95b4f0 793 if(dops[i+j].itype==SYSCALL||dops[i+j].itype==HLECALL||dops[i+j].itype==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
57871462 794 {
795 break;
796 }
797 }
798 for(;j>=1;j--)
799 {
cf95b4f0 800 if(dops[i+j].rs1==r) rn=j;
801 if(dops[i+j].rs2==r) rn=j;
57871462 802 if((unneeded_reg[i+j]>>r)&1) rn=10;
cf95b4f0 803 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
57871462 804 {
805 b=j;
806 }
807 }
b7217e13 808 if(rn<10) return 1;
581335b0 809 (void)b;
57871462 810 return 0;
811}
812
813// Try to match register allocations at the end of a loop with those
814// at the beginning
815int loop_reg(int i, int r, int hr)
816{
817 int j,k;
818 for(j=0;j<9;j++)
819 {
820 if(i+j>=slen) {
821 j=slen-i-1;
822 break;
823 }
fe807a8a 824 if (dops[i+j].is_ujump)
57871462 825 {
826 // Don't go past an unconditonal jump
827 j++;
828 break;
829 }
830 }
831 k=0;
832 if(i>0){
cf95b4f0 833 if(dops[i-1].itype==UJUMP||dops[i-1].itype==CJUMP||dops[i-1].itype==SJUMP)
57871462 834 k--;
835 }
836 for(;k<j;k++)
837 {
00fa9369 838 assert(r < 64);
839 if((unneeded_reg[i+k]>>r)&1) return hr;
cf95b4f0 840 if(i+k>=0&&(dops[i+k].itype==UJUMP||dops[i+k].itype==CJUMP||dops[i+k].itype==SJUMP))
57871462 841 {
842 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
843 {
844 int t=(ba[i+k]-start)>>2;
845 int reg=get_reg(regs[t].regmap_entry,r);
846 if(reg>=0) return reg;
847 //reg=get_reg(regs[t+1].regmap_entry,r);
848 //if(reg>=0) return reg;
849 }
850 }
851 }
852 return hr;
853}
854
855
856// Allocate every register, preserving source/target regs
857void alloc_all(struct regstat *cur,int i)
858{
859 int hr;
9f51b4b9 860
57871462 861 for(hr=0;hr<HOST_REGS;hr++) {
862 if(hr!=EXCLUDE_REG) {
cf95b4f0 863 if(((cur->regmap[hr]&63)!=dops[i].rs1)&&((cur->regmap[hr]&63)!=dops[i].rs2)&&
864 ((cur->regmap[hr]&63)!=dops[i].rt1)&&((cur->regmap[hr]&63)!=dops[i].rt2))
57871462 865 {
866 cur->regmap[hr]=-1;
867 cur->dirty&=~(1<<hr);
868 }
869 // Don't need zeros
870 if((cur->regmap[hr]&63)==0)
871 {
872 cur->regmap[hr]=-1;
873 cur->dirty&=~(1<<hr);
874 }
875 }
876 }
877}
878
d1e4ebd9 879#ifndef NDEBUG
880static int host_tempreg_in_use;
881
882static void host_tempreg_acquire(void)
883{
884 assert(!host_tempreg_in_use);
885 host_tempreg_in_use = 1;
886}
887
888static void host_tempreg_release(void)
889{
890 host_tempreg_in_use = 0;
891}
892#else
893static void host_tempreg_acquire(void) {}
894static void host_tempreg_release(void) {}
895#endif
896
32631e6a 897#ifdef ASSEM_PRINT
8062d65a 898extern void gen_interupt();
899extern void do_insn_cmp();
d1e4ebd9 900#define FUNCNAME(f) { f, " " #f }
8062d65a 901static const struct {
d1e4ebd9 902 void *addr;
8062d65a 903 const char *name;
904} function_names[] = {
905 FUNCNAME(cc_interrupt),
906 FUNCNAME(gen_interupt),
907 FUNCNAME(get_addr_ht),
908 FUNCNAME(get_addr),
909 FUNCNAME(jump_handler_read8),
910 FUNCNAME(jump_handler_read16),
911 FUNCNAME(jump_handler_read32),
912 FUNCNAME(jump_handler_write8),
913 FUNCNAME(jump_handler_write16),
914 FUNCNAME(jump_handler_write32),
915 FUNCNAME(invalidate_addr),
3968e69e 916 FUNCNAME(jump_to_new_pc),
81dbbf4c 917 FUNCNAME(call_gteStall),
8062d65a 918 FUNCNAME(new_dyna_leave),
919 FUNCNAME(pcsx_mtc0),
920 FUNCNAME(pcsx_mtc0_ds),
32631e6a 921#ifdef DRC_DBG
8062d65a 922 FUNCNAME(do_insn_cmp),
32631e6a 923#endif
3968e69e 924#ifdef __arm__
925 FUNCNAME(verify_code),
926#endif
8062d65a 927};
928
d1e4ebd9 929static const char *func_name(const void *a)
8062d65a 930{
931 int i;
932 for (i = 0; i < sizeof(function_names)/sizeof(function_names[0]); i++)
933 if (function_names[i].addr == a)
934 return function_names[i].name;
935 return "";
936}
937#else
938#define func_name(x) ""
939#endif
940
57871462 941#ifdef __i386__
942#include "assem_x86.c"
943#endif
944#ifdef __x86_64__
945#include "assem_x64.c"
946#endif
947#ifdef __arm__
948#include "assem_arm.c"
949#endif
be516ebe 950#ifdef __aarch64__
951#include "assem_arm64.c"
952#endif
57871462 953
2a014d73 954static void *get_trampoline(const void *f)
955{
956 size_t i;
957
958 for (i = 0; i < ARRAY_SIZE(ndrc->tramp.f); i++) {
959 if (ndrc->tramp.f[i] == f || ndrc->tramp.f[i] == NULL)
960 break;
961 }
962 if (i == ARRAY_SIZE(ndrc->tramp.f)) {
963 SysPrintf("trampoline table is full, last func %p\n", f);
964 abort();
965 }
966 if (ndrc->tramp.f[i] == NULL) {
967 start_tcache_write(&ndrc->tramp.f[i], &ndrc->tramp.f[i + 1]);
968 ndrc->tramp.f[i] = f;
969 end_tcache_write(&ndrc->tramp.f[i], &ndrc->tramp.f[i + 1]);
970 }
971 return &ndrc->tramp.ops[i];
972}
973
974static void emit_far_jump(const void *f)
975{
976 if (can_jump_or_call(f)) {
977 emit_jmp(f);
978 return;
979 }
980
981 f = get_trampoline(f);
982 emit_jmp(f);
983}
984
985static void emit_far_call(const void *f)
986{
987 if (can_jump_or_call(f)) {
988 emit_call(f);
989 return;
990 }
991
992 f = get_trampoline(f);
993 emit_call(f);
994}
995
57871462 996// Add virtual address mapping to linked list
997void ll_add(struct ll_entry **head,int vaddr,void *addr)
998{
999 struct ll_entry *new_entry;
1000 new_entry=malloc(sizeof(struct ll_entry));
1001 assert(new_entry!=NULL);
1002 new_entry->vaddr=vaddr;
de5a60c3 1003 new_entry->reg_sv_flags=0;
57871462 1004 new_entry->addr=addr;
1005 new_entry->next=*head;
1006 *head=new_entry;
1007}
1008
de5a60c3 1009void ll_add_flags(struct ll_entry **head,int vaddr,u_int reg_sv_flags,void *addr)
57871462 1010{
7139f3c8 1011 ll_add(head,vaddr,addr);
de5a60c3 1012 (*head)->reg_sv_flags=reg_sv_flags;
57871462 1013}
1014
1015// Check if an address is already compiled
1016// but don't return addresses which are about to expire from the cache
1017void *check_addr(u_int vaddr)
1018{
df4dc2b1 1019 struct ht_entry *ht_bin = hash_table_get(vaddr);
1020 size_t i;
b14b6a8f 1021 for (i = 0; i < ARRAY_SIZE(ht_bin->vaddr); i++) {
df4dc2b1 1022 if (ht_bin->vaddr[i] == vaddr)
1023 if (doesnt_expire_soon((u_char *)ht_bin->tcaddr[i] - MAX_OUTPUT_BLOCK_SIZE))
1024 if (isclean(ht_bin->tcaddr[i]))
1025 return ht_bin->tcaddr[i];
57871462 1026 }
94d23bb9 1027 u_int page=get_page(vaddr);
57871462 1028 struct ll_entry *head;
1029 head=jump_in[page];
df4dc2b1 1030 while (head != NULL) {
1031 if (head->vaddr == vaddr) {
1032 if (doesnt_expire_soon(head->addr)) {
57871462 1033 // Update existing entry with current address
df4dc2b1 1034 if (ht_bin->vaddr[0] == vaddr) {
1035 ht_bin->tcaddr[0] = head->addr;
57871462 1036 return head->addr;
1037 }
df4dc2b1 1038 if (ht_bin->vaddr[1] == vaddr) {
1039 ht_bin->tcaddr[1] = head->addr;
57871462 1040 return head->addr;
1041 }
1042 // Insert into hash table with low priority.
1043 // Don't evict existing entries, as they are probably
1044 // addresses that are being accessed frequently.
df4dc2b1 1045 if (ht_bin->vaddr[0] == -1) {
1046 ht_bin->vaddr[0] = vaddr;
1047 ht_bin->tcaddr[0] = head->addr;
1048 }
1049 else if (ht_bin->vaddr[1] == -1) {
1050 ht_bin->vaddr[1] = vaddr;
1051 ht_bin->tcaddr[1] = head->addr;
57871462 1052 }
1053 return head->addr;
1054 }
1055 }
1056 head=head->next;
1057 }
1058 return 0;
1059}
1060
1061void remove_hash(int vaddr)
1062{
1063 //printf("remove hash: %x\n",vaddr);
df4dc2b1 1064 struct ht_entry *ht_bin = hash_table_get(vaddr);
1065 if (ht_bin->vaddr[1] == vaddr) {
1066 ht_bin->vaddr[1] = -1;
1067 ht_bin->tcaddr[1] = NULL;
57871462 1068 }
df4dc2b1 1069 if (ht_bin->vaddr[0] == vaddr) {
1070 ht_bin->vaddr[0] = ht_bin->vaddr[1];
1071 ht_bin->tcaddr[0] = ht_bin->tcaddr[1];
1072 ht_bin->vaddr[1] = -1;
1073 ht_bin->tcaddr[1] = NULL;
57871462 1074 }
1075}
1076
943f42f3 1077static void ll_remove_matching_addrs(struct ll_entry **head,
1078 uintptr_t base_offs_s, int shift)
57871462 1079{
1080 struct ll_entry *next;
1081 while(*head) {
943f42f3 1082 uintptr_t o1 = (u_char *)(*head)->addr - ndrc->translation_cache;
1083 uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
1084 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s)
57871462 1085 {
643aeae3 1086 inv_debug("EXP: Remove pointer to %p (%x)\n",(*head)->addr,(*head)->vaddr);
57871462 1087 remove_hash((*head)->vaddr);
1088 next=(*head)->next;
1089 free(*head);
1090 *head=next;
1091 }
1092 else
1093 {
1094 head=&((*head)->next);
1095 }
1096 }
1097}
1098
1099// Remove all entries from linked list
1100void ll_clear(struct ll_entry **head)
1101{
1102 struct ll_entry *cur;
1103 struct ll_entry *next;
581335b0 1104 if((cur=*head)) {
57871462 1105 *head=0;
1106 while(cur) {
1107 next=cur->next;
1108 free(cur);
1109 cur=next;
1110 }
1111 }
1112}
1113
1114// Dereference the pointers and remove if it matches
943f42f3 1115static void ll_kill_pointers(struct ll_entry *head,
1116 uintptr_t base_offs_s, int shift)
57871462 1117{
1118 while(head) {
943f42f3 1119 u_char *ptr = get_pointer(head->addr);
1120 uintptr_t o1 = ptr - ndrc->translation_cache;
1121 uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
1122 inv_debug("EXP: Lookup pointer to %p at %p (%x)\n",ptr,head->addr,head->vaddr);
1123 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s)
57871462 1124 {
643aeae3 1125 inv_debug("EXP: Kill pointer at %p (%x)\n",head->addr,head->vaddr);
d148d265 1126 void *host_addr=find_extjump_insn(head->addr);
919981d0 1127 mark_clear_cache(host_addr);
df4dc2b1 1128 set_jump_target(host_addr, head->addr);
57871462 1129 }
1130 head=head->next;
1131 }
1132}
1133
1134// This is called when we write to a compiled block (see do_invstub)
d1e4ebd9 1135static void invalidate_page(u_int page)
57871462 1136{
57871462 1137 struct ll_entry *head;
1138 struct ll_entry *next;
1139 head=jump_in[page];
1140 jump_in[page]=0;
1141 while(head!=NULL) {
1142 inv_debug("INVALIDATE: %x\n",head->vaddr);
1143 remove_hash(head->vaddr);
1144 next=head->next;
1145 free(head);
1146 head=next;
1147 }
1148 head=jump_out[page];
1149 jump_out[page]=0;
1150 while(head!=NULL) {
643aeae3 1151 inv_debug("INVALIDATE: kill pointer to %x (%p)\n",head->vaddr,head->addr);
d148d265 1152 void *host_addr=find_extjump_insn(head->addr);
919981d0 1153 mark_clear_cache(host_addr);
3d680478 1154 set_jump_target(host_addr, head->addr); // point back to dyna_linker
57871462 1155 next=head->next;
1156 free(head);
1157 head=next;
1158 }
57871462 1159}
9be4ba64 1160
1161static void invalidate_block_range(u_int block, u_int first, u_int last)
57871462 1162{
94d23bb9 1163 u_int page=get_page(block<<12);
57871462 1164 //printf("first=%d last=%d\n",first,last);
f76eeef9 1165 invalidate_page(page);
57871462 1166 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1167 assert(last<page+5);
1168 // Invalidate the adjacent pages if a block crosses a 4K boundary
1169 while(first<page) {
1170 invalidate_page(first);
1171 first++;
1172 }
1173 for(first=page+1;first<last;first++) {
1174 invalidate_page(first);
1175 }
919981d0 1176 do_clear_cache();
9f51b4b9 1177
57871462 1178 // Don't trap writes
1179 invalid_code[block]=1;
f76eeef9 1180
57871462 1181 #ifdef USE_MINI_HT
1182 memset(mini_ht,-1,sizeof(mini_ht));
1183 #endif
1184}
9be4ba64 1185
1186void invalidate_block(u_int block)
1187{
1188 u_int page=get_page(block<<12);
1189 u_int vpage=get_vpage(block<<12);
1190 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1191 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1192 u_int first,last;
1193 first=last=page;
1194 struct ll_entry *head;
1195 head=jump_dirty[vpage];
1196 //printf("page=%d vpage=%d\n",page,vpage);
1197 while(head!=NULL) {
9be4ba64 1198 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
01d26796 1199 u_char *start, *end;
1200 get_bounds(head->addr, &start, &end);
1201 //printf("start: %p end: %p\n", start, end);
1202 if (page < 2048 && start >= rdram && end < rdram+RAM_SIZE) {
1203 if (((start-rdram)>>12) <= page && ((end-1-rdram)>>12) >= page) {
1204 if ((((start-rdram)>>12)&2047) < first) first = ((start-rdram)>>12)&2047;
1205 if ((((end-1-rdram)>>12)&2047) > last) last = ((end-1-rdram)>>12)&2047;
9be4ba64 1206 }
1207 }
9be4ba64 1208 }
1209 head=head->next;
1210 }
1211 invalidate_block_range(block,first,last);
1212}
1213
57871462 1214void invalidate_addr(u_int addr)
1215{
9be4ba64 1216 //static int rhits;
1217 // this check is done by the caller
1218 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
d25604ca 1219 u_int page=get_vpage(addr);
9be4ba64 1220 if(page<2048) { // RAM
1221 struct ll_entry *head;
1222 u_int addr_min=~0, addr_max=0;
4a35de07 1223 u_int mask=RAM_SIZE-1;
1224 u_int addr_main=0x80000000|(addr&mask);
9be4ba64 1225 int pg1;
4a35de07 1226 inv_code_start=addr_main&~0xfff;
1227 inv_code_end=addr_main|0xfff;
9be4ba64 1228 pg1=page;
1229 if (pg1>0) {
1230 // must check previous page too because of spans..
1231 pg1--;
1232 inv_code_start-=0x1000;
1233 }
1234 for(;pg1<=page;pg1++) {
1235 for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
01d26796 1236 u_char *start_h, *end_h;
1237 u_int start, end;
1238 get_bounds(head->addr, &start_h, &end_h);
1239 start = (uintptr_t)start_h - ram_offset;
1240 end = (uintptr_t)end_h - ram_offset;
4a35de07 1241 if(start<=addr_main&&addr_main<end) {
9be4ba64 1242 if(start<addr_min) addr_min=start;
1243 if(end>addr_max) addr_max=end;
1244 }
4a35de07 1245 else if(addr_main<start) {
9be4ba64 1246 if(start<inv_code_end)
1247 inv_code_end=start-1;
1248 }
1249 else {
1250 if(end>inv_code_start)
1251 inv_code_start=end;
1252 }
1253 }
1254 }
1255 if (addr_min!=~0) {
1256 inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1257 inv_code_start=inv_code_end=~0;
1258 invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1259 return;
1260 }
1261 else {
4a35de07 1262 inv_code_start=(addr&~mask)|(inv_code_start&mask);
1263 inv_code_end=(addr&~mask)|(inv_code_end&mask);
d25604ca 1264 inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);
9be4ba64 1265 return;
d25604ca 1266 }
9be4ba64 1267 }
57871462 1268 invalidate_block(addr>>12);
1269}
9be4ba64 1270
dd3a91a1 1271// This is called when loading a save state.
1272// Anything could have changed, so invalidate everything.
919981d0 1273void invalidate_all_pages(void)
57871462 1274{
581335b0 1275 u_int page;
57871462 1276 for(page=0;page<4096;page++)
1277 invalidate_page(page);
1278 for(page=0;page<1048576;page++)
1279 if(!invalid_code[page]) {
1280 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1281 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1282 }
57871462 1283 #ifdef USE_MINI_HT
1284 memset(mini_ht,-1,sizeof(mini_ht));
1285 #endif
919981d0 1286 do_clear_cache();
57871462 1287}
1288
d1e4ebd9 1289static void do_invstub(int n)
1290{
1291 literal_pool(20);
1292 u_int reglist=stubs[n].a;
1293 set_jump_target(stubs[n].addr, out);
1294 save_regs(reglist);
1295 if(stubs[n].b!=0) emit_mov(stubs[n].b,0);
2a014d73 1296 emit_far_call(invalidate_addr);
d1e4ebd9 1297 restore_regs(reglist);
1298 emit_jmp(stubs[n].retaddr); // return address
1299}
1300
57871462 1301// Add an entry to jump_out after making a link
d1e4ebd9 1302// src should point to code by emit_extjump2()
3d680478 1303void add_jump_out(u_int vaddr,void *src)
57871462 1304{
94d23bb9 1305 u_int page=get_page(vaddr);
3d680478 1306 inv_debug("add_jump_out: %p -> %x (%d)\n",src,vaddr,page);
d1e4ebd9 1307 check_extjump2(src);
57871462 1308 ll_add(jump_out+page,vaddr,src);
3d680478 1309 //inv_debug("add_jump_out: to %p\n",get_pointer(src));
57871462 1310}
1311
1312// If a code block was found to be unmodified (bit was set in
1313// restore_candidate) and it remains unmodified (bit is clear
1314// in invalid_code) then move the entries for that 4K page from
1315// the dirty list to the clean list.
1316void clean_blocks(u_int page)
1317{
1318 struct ll_entry *head;
1319 inv_debug("INV: clean_blocks page=%d\n",page);
1320 head=jump_dirty[page];
1321 while(head!=NULL) {
1322 if(!invalid_code[head->vaddr>>12]) {
1323 // Don't restore blocks which are about to expire from the cache
df4dc2b1 1324 if (doesnt_expire_soon(head->addr)) {
581335b0 1325 if(verify_dirty(head->addr)) {
01d26796 1326 u_char *start, *end;
643aeae3 1327 //printf("Possibly Restore %x (%p)\n",head->vaddr, head->addr);
57871462 1328 u_int i;
1329 u_int inv=0;
01d26796 1330 get_bounds(head->addr, &start, &end);
1331 if (start - rdram < RAM_SIZE) {
1332 for (i = (start-rdram+0x80000000)>>12; i <= (end-1-rdram+0x80000000)>>12; i++) {
57871462 1333 inv|=invalid_code[i];
1334 }
1335 }
4cb76aa4 1336 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
57871462 1337 inv=1;
1338 }
1339 if(!inv) {
df4dc2b1 1340 void *clean_addr = get_clean_addr(head->addr);
1341 if (doesnt_expire_soon(clean_addr)) {
57871462 1342 u_int ppage=page;
643aeae3 1343 inv_debug("INV: Restored %x (%p/%p)\n",head->vaddr, head->addr, clean_addr);
57871462 1344 //printf("page=%x, addr=%x\n",page,head->vaddr);
1345 //assert(head->vaddr>>12==(page|0x80000));
de5a60c3 1346 ll_add_flags(jump_in+ppage,head->vaddr,head->reg_sv_flags,clean_addr);
df4dc2b1 1347 struct ht_entry *ht_bin = hash_table_get(head->vaddr);
1348 if (ht_bin->vaddr[0] == head->vaddr)
1349 ht_bin->tcaddr[0] = clean_addr; // Replace existing entry
1350 if (ht_bin->vaddr[1] == head->vaddr)
1351 ht_bin->tcaddr[1] = clean_addr; // Replace existing entry
57871462 1352 }
1353 }
1354 }
1355 }
1356 }
1357 head=head->next;
1358 }
1359}
1360
8062d65a 1361/* Register allocation */
1362
1363// Note: registers are allocated clean (unmodified state)
1364// if you intend to modify the register, you must call dirty_reg().
1365static void alloc_reg(struct regstat *cur,int i,signed char reg)
1366{
1367 int r,hr;
b7ec323c 1368 int preferred_reg = PREFERRED_REG_FIRST
1369 + reg % (PREFERRED_REG_LAST - PREFERRED_REG_FIRST + 1);
1370 if (reg == CCREG) preferred_reg = HOST_CCREG;
1371 if (reg == PTEMP || reg == FTEMP) preferred_reg = 12;
1372 assert(PREFERRED_REG_FIRST != EXCLUDE_REG && EXCLUDE_REG != HOST_REGS);
8062d65a 1373
1374 // Don't allocate unused registers
1375 if((cur->u>>reg)&1) return;
1376
1377 // see if it's already allocated
1378 for(hr=0;hr<HOST_REGS;hr++)
1379 {
1380 if(cur->regmap[hr]==reg) return;
1381 }
1382
1383 // Keep the same mapping if the register was already allocated in a loop
1384 preferred_reg = loop_reg(i,reg,preferred_reg);
1385
1386 // Try to allocate the preferred register
1387 if(cur->regmap[preferred_reg]==-1) {
1388 cur->regmap[preferred_reg]=reg;
1389 cur->dirty&=~(1<<preferred_reg);
1390 cur->isconst&=~(1<<preferred_reg);
1391 return;
1392 }
1393 r=cur->regmap[preferred_reg];
1394 assert(r < 64);
1395 if((cur->u>>r)&1) {
1396 cur->regmap[preferred_reg]=reg;
1397 cur->dirty&=~(1<<preferred_reg);
1398 cur->isconst&=~(1<<preferred_reg);
1399 return;
1400 }
1401
1402 // Clear any unneeded registers
1403 // We try to keep the mapping consistent, if possible, because it
1404 // makes branches easier (especially loops). So we try to allocate
1405 // first (see above) before removing old mappings. If this is not
1406 // possible then go ahead and clear out the registers that are no
1407 // longer needed.
1408 for(hr=0;hr<HOST_REGS;hr++)
1409 {
1410 r=cur->regmap[hr];
1411 if(r>=0) {
1412 assert(r < 64);
1413 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
1414 }
1415 }
b7ec323c 1416
8062d65a 1417 // Try to allocate any available register, but prefer
1418 // registers that have not been used recently.
b7ec323c 1419 if (i > 0) {
1420 for (hr = PREFERRED_REG_FIRST; ; ) {
1421 if (cur->regmap[hr] < 0) {
1422 int oldreg = regs[i-1].regmap[hr];
1423 if (oldreg < 0 || (oldreg != dops[i-1].rs1 && oldreg != dops[i-1].rs2
1424 && oldreg != dops[i-1].rt1 && oldreg != dops[i-1].rt2))
1425 {
8062d65a 1426 cur->regmap[hr]=reg;
1427 cur->dirty&=~(1<<hr);
1428 cur->isconst&=~(1<<hr);
1429 return;
1430 }
1431 }
b7ec323c 1432 hr++;
1433 if (hr == EXCLUDE_REG)
1434 hr++;
1435 if (hr == HOST_REGS)
1436 hr = 0;
1437 if (hr == PREFERRED_REG_FIRST)
1438 break;
8062d65a 1439 }
1440 }
b7ec323c 1441
8062d65a 1442 // Try to allocate any available register
b7ec323c 1443 for (hr = PREFERRED_REG_FIRST; ; ) {
1444 if (cur->regmap[hr] < 0) {
8062d65a 1445 cur->regmap[hr]=reg;
1446 cur->dirty&=~(1<<hr);
1447 cur->isconst&=~(1<<hr);
1448 return;
1449 }
b7ec323c 1450 hr++;
1451 if (hr == EXCLUDE_REG)
1452 hr++;
1453 if (hr == HOST_REGS)
1454 hr = 0;
1455 if (hr == PREFERRED_REG_FIRST)
1456 break;
8062d65a 1457 }
1458
1459 // Ok, now we have to evict someone
1460 // Pick a register we hopefully won't need soon
1461 u_char hsn[MAXREG+1];
1462 memset(hsn,10,sizeof(hsn));
1463 int j;
1464 lsn(hsn,i,&preferred_reg);
1465 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
1466 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
1467 if(i>0) {
1468 // Don't evict the cycle count at entry points, otherwise the entry
1469 // stub will have to write it.
cf95b4f0 1470 if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2;
fe807a8a 1471 if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2;
8062d65a 1472 for(j=10;j>=3;j--)
1473 {
1474 // Alloc preferred register if available
1475 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
1476 for(hr=0;hr<HOST_REGS;hr++) {
1477 // Evict both parts of a 64-bit register
1478 if((cur->regmap[hr]&63)==r) {
1479 cur->regmap[hr]=-1;
1480 cur->dirty&=~(1<<hr);
1481 cur->isconst&=~(1<<hr);
1482 }
1483 }
1484 cur->regmap[preferred_reg]=reg;
1485 return;
1486 }
1487 for(r=1;r<=MAXREG;r++)
1488 {
cf95b4f0 1489 if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) {
8062d65a 1490 for(hr=0;hr<HOST_REGS;hr++) {
1491 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
1492 if(cur->regmap[hr]==r) {
1493 cur->regmap[hr]=reg;
1494 cur->dirty&=~(1<<hr);
1495 cur->isconst&=~(1<<hr);
1496 return;
1497 }
1498 }
1499 }
1500 }
1501 }
1502 }
1503 }
1504 for(j=10;j>=0;j--)
1505 {
1506 for(r=1;r<=MAXREG;r++)
1507 {
1508 if(hsn[r]==j) {
8062d65a 1509 for(hr=0;hr<HOST_REGS;hr++) {
1510 if(cur->regmap[hr]==r) {
1511 cur->regmap[hr]=reg;
1512 cur->dirty&=~(1<<hr);
1513 cur->isconst&=~(1<<hr);
1514 return;
1515 }
1516 }
1517 }
1518 }
1519 }
7c3a5182 1520 SysPrintf("This shouldn't happen (alloc_reg)");abort();
8062d65a 1521}
1522
1523// Allocate a temporary register. This is done without regard to
1524// dirty status or whether the register we request is on the unneeded list
1525// Note: This will only allocate one register, even if called multiple times
1526static void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
1527{
1528 int r,hr;
1529 int preferred_reg = -1;
1530
1531 // see if it's already allocated
1532 for(hr=0;hr<HOST_REGS;hr++)
1533 {
1534 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==reg) return;
1535 }
1536
1537 // Try to allocate any available register
1538 for(hr=HOST_REGS-1;hr>=0;hr--) {
1539 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
1540 cur->regmap[hr]=reg;
1541 cur->dirty&=~(1<<hr);
1542 cur->isconst&=~(1<<hr);
1543 return;
1544 }
1545 }
1546
1547 // Find an unneeded register
1548 for(hr=HOST_REGS-1;hr>=0;hr--)
1549 {
1550 r=cur->regmap[hr];
1551 if(r>=0) {
1552 assert(r < 64);
1553 if((cur->u>>r)&1) {
1554 if(i==0||((unneeded_reg[i-1]>>r)&1)) {
1555 cur->regmap[hr]=reg;
1556 cur->dirty&=~(1<<hr);
1557 cur->isconst&=~(1<<hr);
1558 return;
1559 }
1560 }
1561 }
1562 }
1563
1564 // Ok, now we have to evict someone
1565 // Pick a register we hopefully won't need soon
1566 // TODO: we might want to follow unconditional jumps here
1567 // TODO: get rid of dupe code and make this into a function
1568 u_char hsn[MAXREG+1];
1569 memset(hsn,10,sizeof(hsn));
1570 int j;
1571 lsn(hsn,i,&preferred_reg);
1572 //printf("hsn: %d %d %d %d %d %d %d\n",hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
1573 if(i>0) {
1574 // Don't evict the cycle count at entry points, otherwise the entry
1575 // stub will have to write it.
cf95b4f0 1576 if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2;
fe807a8a 1577 if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2;
8062d65a 1578 for(j=10;j>=3;j--)
1579 {
1580 for(r=1;r<=MAXREG;r++)
1581 {
cf95b4f0 1582 if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) {
8062d65a 1583 for(hr=0;hr<HOST_REGS;hr++) {
1584 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
1585 if(cur->regmap[hr]==r) {
1586 cur->regmap[hr]=reg;
1587 cur->dirty&=~(1<<hr);
1588 cur->isconst&=~(1<<hr);
1589 return;
1590 }
1591 }
1592 }
1593 }
1594 }
1595 }
1596 }
1597 for(j=10;j>=0;j--)
1598 {
1599 for(r=1;r<=MAXREG;r++)
1600 {
1601 if(hsn[r]==j) {
8062d65a 1602 for(hr=0;hr<HOST_REGS;hr++) {
1603 if(cur->regmap[hr]==r) {
1604 cur->regmap[hr]=reg;
1605 cur->dirty&=~(1<<hr);
1606 cur->isconst&=~(1<<hr);
1607 return;
1608 }
1609 }
1610 }
1611 }
1612 }
7c3a5182 1613 SysPrintf("This shouldn't happen");abort();
8062d65a 1614}
1615
ad49de89 1616static void mov_alloc(struct regstat *current,int i)
57871462 1617{
cf95b4f0 1618 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) {
32631e6a 1619 // logically this is needed but just won't work, no idea why
1620 //alloc_cc(current,i); // for stalls
1621 //dirty_reg(current,CCREG);
1622 }
1623
57871462 1624 // Note: Don't need to actually alloc the source registers
cf95b4f0 1625 //alloc_reg(current,i,dops[i].rs1);
1626 alloc_reg(current,i,dops[i].rt1);
ad49de89 1627
cf95b4f0 1628 clear_const(current,dops[i].rs1);
1629 clear_const(current,dops[i].rt1);
1630 dirty_reg(current,dops[i].rt1);
57871462 1631}
1632
ad49de89 1633static void shiftimm_alloc(struct regstat *current,int i)
57871462 1634{
cf95b4f0 1635 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
57871462 1636 {
cf95b4f0 1637 if(dops[i].rt1) {
1638 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1639 else dops[i].lt1=dops[i].rs1;
1640 alloc_reg(current,i,dops[i].rt1);
1641 dirty_reg(current,dops[i].rt1);
1642 if(is_const(current,dops[i].rs1)) {
1643 int v=get_const(current,dops[i].rs1);
1644 if(dops[i].opcode2==0x00) set_const(current,dops[i].rt1,v<<imm[i]);
1645 if(dops[i].opcode2==0x02) set_const(current,dops[i].rt1,(u_int)v>>imm[i]);
1646 if(dops[i].opcode2==0x03) set_const(current,dops[i].rt1,v>>imm[i]);
dc49e339 1647 }
cf95b4f0 1648 else clear_const(current,dops[i].rt1);
57871462 1649 }
1650 }
dc49e339 1651 else
1652 {
cf95b4f0 1653 clear_const(current,dops[i].rs1);
1654 clear_const(current,dops[i].rt1);
dc49e339 1655 }
1656
cf95b4f0 1657 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
57871462 1658 {
9c45ca93 1659 assert(0);
57871462 1660 }
cf95b4f0 1661 if(dops[i].opcode2==0x3c) // DSLL32
57871462 1662 {
9c45ca93 1663 assert(0);
57871462 1664 }
cf95b4f0 1665 if(dops[i].opcode2==0x3e) // DSRL32
57871462 1666 {
9c45ca93 1667 assert(0);
57871462 1668 }
cf95b4f0 1669 if(dops[i].opcode2==0x3f) // DSRA32
57871462 1670 {
9c45ca93 1671 assert(0);
57871462 1672 }
1673}
1674
ad49de89 1675static void shift_alloc(struct regstat *current,int i)
57871462 1676{
cf95b4f0 1677 if(dops[i].rt1) {
1678 if(dops[i].opcode2<=0x07) // SLLV/SRLV/SRAV
57871462 1679 {
cf95b4f0 1680 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
1681 if(dops[i].rs2) alloc_reg(current,i,dops[i].rs2);
1682 alloc_reg(current,i,dops[i].rt1);
1683 if(dops[i].rt1==dops[i].rs2) {
e1190b87 1684 alloc_reg_temp(current,i,-1);
1685 minimum_free_regs[i]=1;
1686 }
57871462 1687 } else { // DSLLV/DSRLV/DSRAV
00fa9369 1688 assert(0);
57871462 1689 }
cf95b4f0 1690 clear_const(current,dops[i].rs1);
1691 clear_const(current,dops[i].rs2);
1692 clear_const(current,dops[i].rt1);
1693 dirty_reg(current,dops[i].rt1);
57871462 1694 }
1695}
1696
ad49de89 1697static void alu_alloc(struct regstat *current,int i)
57871462 1698{
cf95b4f0 1699 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
1700 if(dops[i].rt1) {
1701 if(dops[i].rs1&&dops[i].rs2) {
1702 alloc_reg(current,i,dops[i].rs1);
1703 alloc_reg(current,i,dops[i].rs2);
57871462 1704 }
1705 else {
cf95b4f0 1706 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1707 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
57871462 1708 }
cf95b4f0 1709 alloc_reg(current,i,dops[i].rt1);
57871462 1710 }
57871462 1711 }
cf95b4f0 1712 if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
1713 if(dops[i].rt1) {
1714 alloc_reg(current,i,dops[i].rs1);
1715 alloc_reg(current,i,dops[i].rs2);
1716 alloc_reg(current,i,dops[i].rt1);
57871462 1717 }
57871462 1718 }
cf95b4f0 1719 if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
1720 if(dops[i].rt1) {
1721 if(dops[i].rs1&&dops[i].rs2) {
1722 alloc_reg(current,i,dops[i].rs1);
1723 alloc_reg(current,i,dops[i].rs2);
57871462 1724 }
1725 else
1726 {
cf95b4f0 1727 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1728 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
57871462 1729 }
cf95b4f0 1730 alloc_reg(current,i,dops[i].rt1);
57871462 1731 }
1732 }
cf95b4f0 1733 if(dops[i].opcode2>=0x2c&&dops[i].opcode2<=0x2f) { // DADD/DADDU/DSUB/DSUBU
00fa9369 1734 assert(0);
57871462 1735 }
cf95b4f0 1736 clear_const(current,dops[i].rs1);
1737 clear_const(current,dops[i].rs2);
1738 clear_const(current,dops[i].rt1);
1739 dirty_reg(current,dops[i].rt1);
57871462 1740}
1741
ad49de89 1742static void imm16_alloc(struct regstat *current,int i)
57871462 1743{
cf95b4f0 1744 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1745 else dops[i].lt1=dops[i].rs1;
1746 if(dops[i].rt1) alloc_reg(current,i,dops[i].rt1);
1747 if(dops[i].opcode==0x18||dops[i].opcode==0x19) { // DADDI/DADDIU
00fa9369 1748 assert(0);
57871462 1749 }
cf95b4f0 1750 else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
1751 clear_const(current,dops[i].rs1);
1752 clear_const(current,dops[i].rt1);
57871462 1753 }
cf95b4f0 1754 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
1755 if(is_const(current,dops[i].rs1)) {
1756 int v=get_const(current,dops[i].rs1);
1757 if(dops[i].opcode==0x0c) set_const(current,dops[i].rt1,v&imm[i]);
1758 if(dops[i].opcode==0x0d) set_const(current,dops[i].rt1,v|imm[i]);
1759 if(dops[i].opcode==0x0e) set_const(current,dops[i].rt1,v^imm[i]);
57871462 1760 }
cf95b4f0 1761 else clear_const(current,dops[i].rt1);
57871462 1762 }
cf95b4f0 1763 else if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
1764 if(is_const(current,dops[i].rs1)) {
1765 int v=get_const(current,dops[i].rs1);
1766 set_const(current,dops[i].rt1,v+imm[i]);
57871462 1767 }
cf95b4f0 1768 else clear_const(current,dops[i].rt1);
57871462 1769 }
1770 else {
cf95b4f0 1771 set_const(current,dops[i].rt1,imm[i]<<16); // LUI
57871462 1772 }
cf95b4f0 1773 dirty_reg(current,dops[i].rt1);
57871462 1774}
1775
ad49de89 1776static void load_alloc(struct regstat *current,int i)
57871462 1777{
cf95b4f0 1778 clear_const(current,dops[i].rt1);
1779 //if(dops[i].rs1!=dops[i].rt1&&needed_again(dops[i].rs1,i)) clear_const(current,dops[i].rs1); // Does this help or hurt?
1780 if(!dops[i].rs1) current->u&=~1LL; // Allow allocating r0 if it's the source register
37387d8b 1781 if (needed_again(dops[i].rs1, i))
1782 alloc_reg(current, i, dops[i].rs1);
1783 if (ram_offset)
1784 alloc_reg(current, i, ROREG);
cf95b4f0 1785 if(dops[i].rt1&&!((current->u>>dops[i].rt1)&1)) {
1786 alloc_reg(current,i,dops[i].rt1);
1787 assert(get_reg(current->regmap,dops[i].rt1)>=0);
1788 if(dops[i].opcode==0x27||dops[i].opcode==0x37) // LWU/LD
57871462 1789 {
ad49de89 1790 assert(0);
57871462 1791 }
cf95b4f0 1792 else if(dops[i].opcode==0x1A||dops[i].opcode==0x1B) // LDL/LDR
57871462 1793 {
ad49de89 1794 assert(0);
57871462 1795 }
cf95b4f0 1796 dirty_reg(current,dops[i].rt1);
57871462 1797 // LWL/LWR need a temporary register for the old value
cf95b4f0 1798 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
57871462 1799 {
1800 alloc_reg(current,i,FTEMP);
1801 alloc_reg_temp(current,i,-1);
e1190b87 1802 minimum_free_regs[i]=1;
57871462 1803 }
1804 }
1805 else
1806 {
373d1d07 1807 // Load to r0 or unneeded register (dummy load)
57871462 1808 // but we still need a register to calculate the address
cf95b4f0 1809 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
535d208a 1810 {
1811 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1812 }
57871462 1813 alloc_reg_temp(current,i,-1);
e1190b87 1814 minimum_free_regs[i]=1;
cf95b4f0 1815 if(dops[i].opcode==0x1A||dops[i].opcode==0x1B) // LDL/LDR
535d208a 1816 {
ad49de89 1817 assert(0);
535d208a 1818 }
57871462 1819 }
1820}
1821
1822void store_alloc(struct regstat *current,int i)
1823{
cf95b4f0 1824 clear_const(current,dops[i].rs2);
1825 if(!(dops[i].rs2)) current->u&=~1LL; // Allow allocating r0 if necessary
1826 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1827 alloc_reg(current,i,dops[i].rs2);
1828 if(dops[i].opcode==0x2c||dops[i].opcode==0x2d||dops[i].opcode==0x3f) { // 64-bit SDL/SDR/SD
ad49de89 1829 assert(0);
57871462 1830 }
37387d8b 1831 if (ram_offset)
1832 alloc_reg(current, i, ROREG);
57871462 1833 #if defined(HOST_IMM8)
1834 // On CPUs without 32-bit immediates we need a pointer to invalid_code
37387d8b 1835 alloc_reg(current, i, INVCP);
57871462 1836 #endif
cf95b4f0 1837 if(dops[i].opcode==0x2a||dops[i].opcode==0x2e||dops[i].opcode==0x2c||dops[i].opcode==0x2d) { // SWL/SWL/SDL/SDR
57871462 1838 alloc_reg(current,i,FTEMP);
1839 }
1840 // We need a temporary register for address generation
1841 alloc_reg_temp(current,i,-1);
e1190b87 1842 minimum_free_regs[i]=1;
57871462 1843}
1844
1845void c1ls_alloc(struct regstat *current,int i)
1846{
cf95b4f0 1847 clear_const(current,dops[i].rt1);
57871462 1848 alloc_reg(current,i,CSREG); // Status
57871462 1849}
1850
b9b61529 1851void c2ls_alloc(struct regstat *current,int i)
1852{
cf95b4f0 1853 clear_const(current,dops[i].rt1);
1854 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
b9b61529 1855 alloc_reg(current,i,FTEMP);
37387d8b 1856 if (ram_offset)
1857 alloc_reg(current, i, ROREG);
b9b61529 1858 #if defined(HOST_IMM8)
1859 // On CPUs without 32-bit immediates we need a pointer to invalid_code
37387d8b 1860 if (dops[i].opcode == 0x3a) // SWC2
b9b61529 1861 alloc_reg(current,i,INVCP);
1862 #endif
1863 // We need a temporary register for address generation
1864 alloc_reg_temp(current,i,-1);
e1190b87 1865 minimum_free_regs[i]=1;
b9b61529 1866}
1867
57871462 1868#ifndef multdiv_alloc
1869void multdiv_alloc(struct regstat *current,int i)
1870{
1871 // case 0x18: MULT
1872 // case 0x19: MULTU
1873 // case 0x1A: DIV
1874 // case 0x1B: DIVU
1875 // case 0x1C: DMULT
1876 // case 0x1D: DMULTU
1877 // case 0x1E: DDIV
1878 // case 0x1F: DDIVU
cf95b4f0 1879 clear_const(current,dops[i].rs1);
1880 clear_const(current,dops[i].rs2);
32631e6a 1881 alloc_cc(current,i); // for stalls
cf95b4f0 1882 if(dops[i].rs1&&dops[i].rs2)
57871462 1883 {
cf95b4f0 1884 if((dops[i].opcode2&4)==0) // 32-bit
57871462 1885 {
1886 current->u&=~(1LL<<HIREG);
1887 current->u&=~(1LL<<LOREG);
1888 alloc_reg(current,i,HIREG);
1889 alloc_reg(current,i,LOREG);
cf95b4f0 1890 alloc_reg(current,i,dops[i].rs1);
1891 alloc_reg(current,i,dops[i].rs2);
57871462 1892 dirty_reg(current,HIREG);
1893 dirty_reg(current,LOREG);
1894 }
1895 else // 64-bit
1896 {
00fa9369 1897 assert(0);
57871462 1898 }
1899 }
1900 else
1901 {
1902 // Multiply by zero is zero.
1903 // MIPS does not have a divide by zero exception.
1904 // The result is undefined, we return zero.
1905 alloc_reg(current,i,HIREG);
1906 alloc_reg(current,i,LOREG);
57871462 1907 dirty_reg(current,HIREG);
1908 dirty_reg(current,LOREG);
1909 }
1910}
1911#endif
1912
1913void cop0_alloc(struct regstat *current,int i)
1914{
cf95b4f0 1915 if(dops[i].opcode2==0) // MFC0
57871462 1916 {
cf95b4f0 1917 if(dops[i].rt1) {
1918 clear_const(current,dops[i].rt1);
57871462 1919 alloc_all(current,i);
cf95b4f0 1920 alloc_reg(current,i,dops[i].rt1);
1921 dirty_reg(current,dops[i].rt1);
57871462 1922 }
1923 }
cf95b4f0 1924 else if(dops[i].opcode2==4) // MTC0
57871462 1925 {
cf95b4f0 1926 if(dops[i].rs1){
1927 clear_const(current,dops[i].rs1);
1928 alloc_reg(current,i,dops[i].rs1);
57871462 1929 alloc_all(current,i);
1930 }
1931 else {
1932 alloc_all(current,i); // FIXME: Keep r0
1933 current->u&=~1LL;
1934 alloc_reg(current,i,0);
1935 }
1936 }
1937 else
1938 {
1939 // TLBR/TLBWI/TLBWR/TLBP/ERET
cf95b4f0 1940 assert(dops[i].opcode2==0x10);
57871462 1941 alloc_all(current,i);
1942 }
e1190b87 1943 minimum_free_regs[i]=HOST_REGS;
57871462 1944}
1945
81dbbf4c 1946static void cop2_alloc(struct regstat *current,int i)
57871462 1947{
cf95b4f0 1948 if (dops[i].opcode2 < 3) // MFC2/CFC2
57871462 1949 {
81dbbf4c 1950 alloc_cc(current,i); // for stalls
1951 dirty_reg(current,CCREG);
cf95b4f0 1952 if(dops[i].rt1){
1953 clear_const(current,dops[i].rt1);
1954 alloc_reg(current,i,dops[i].rt1);
1955 dirty_reg(current,dops[i].rt1);
57871462 1956 }
57871462 1957 }
cf95b4f0 1958 else if (dops[i].opcode2 > 3) // MTC2/CTC2
57871462 1959 {
cf95b4f0 1960 if(dops[i].rs1){
1961 clear_const(current,dops[i].rs1);
1962 alloc_reg(current,i,dops[i].rs1);
57871462 1963 }
1964 else {
1965 current->u&=~1LL;
1966 alloc_reg(current,i,0);
57871462 1967 }
1968 }
81dbbf4c 1969 alloc_reg_temp(current,i,-1);
e1190b87 1970 minimum_free_regs[i]=1;
57871462 1971}
00fa9369 1972
b9b61529 1973void c2op_alloc(struct regstat *current,int i)
1974{
81dbbf4c 1975 alloc_cc(current,i); // for stalls
1976 dirty_reg(current,CCREG);
b9b61529 1977 alloc_reg_temp(current,i,-1);
1978}
57871462 1979
1980void syscall_alloc(struct regstat *current,int i)
1981{
1982 alloc_cc(current,i);
1983 dirty_reg(current,CCREG);
1984 alloc_all(current,i);
e1190b87 1985 minimum_free_regs[i]=HOST_REGS;
57871462 1986 current->isconst=0;
1987}
1988
1989void delayslot_alloc(struct regstat *current,int i)
1990{
cf95b4f0 1991 switch(dops[i].itype) {
57871462 1992 case UJUMP:
1993 case CJUMP:
1994 case SJUMP:
1995 case RJUMP:
57871462 1996 case SYSCALL:
7139f3c8 1997 case HLECALL:
57871462 1998 case SPAN:
7c3a5182 1999 assem_debug("jump in the delay slot. this shouldn't happen.\n");//abort();
c43b5311 2000 SysPrintf("Disabled speculative precompilation\n");
57871462 2001 stop_after_jal=1;
2002 break;
2003 case IMM16:
2004 imm16_alloc(current,i);
2005 break;
2006 case LOAD:
2007 case LOADLR:
2008 load_alloc(current,i);
2009 break;
2010 case STORE:
2011 case STORELR:
2012 store_alloc(current,i);
2013 break;
2014 case ALU:
2015 alu_alloc(current,i);
2016 break;
2017 case SHIFT:
2018 shift_alloc(current,i);
2019 break;
2020 case MULTDIV:
2021 multdiv_alloc(current,i);
2022 break;
2023 case SHIFTIMM:
2024 shiftimm_alloc(current,i);
2025 break;
2026 case MOV:
2027 mov_alloc(current,i);
2028 break;
2029 case COP0:
2030 cop0_alloc(current,i);
2031 break;
2032 case COP1:
81dbbf4c 2033 break;
b9b61529 2034 case COP2:
81dbbf4c 2035 cop2_alloc(current,i);
57871462 2036 break;
2037 case C1LS:
2038 c1ls_alloc(current,i);
2039 break;
b9b61529 2040 case C2LS:
2041 c2ls_alloc(current,i);
2042 break;
b9b61529 2043 case C2OP:
2044 c2op_alloc(current,i);
2045 break;
57871462 2046 }
2047}
2048
2049// Special case where a branch and delay slot span two pages in virtual memory
2050static void pagespan_alloc(struct regstat *current,int i)
2051{
2052 current->isconst=0;
2053 current->wasconst=0;
2054 regs[i].wasconst=0;
e1190b87 2055 minimum_free_regs[i]=HOST_REGS;
57871462 2056 alloc_all(current,i);
2057 alloc_cc(current,i);
2058 dirty_reg(current,CCREG);
cf95b4f0 2059 if(dops[i].opcode==3) // JAL
57871462 2060 {
2061 alloc_reg(current,i,31);
2062 dirty_reg(current,31);
2063 }
cf95b4f0 2064 if(dops[i].opcode==0&&(dops[i].opcode2&0x3E)==8) // JR/JALR
57871462 2065 {
cf95b4f0 2066 alloc_reg(current,i,dops[i].rs1);
2067 if (dops[i].rt1!=0) {
2068 alloc_reg(current,i,dops[i].rt1);
2069 dirty_reg(current,dops[i].rt1);
57871462 2070 }
2071 }
cf95b4f0 2072 if((dops[i].opcode&0x2E)==4) // BEQ/BNE/BEQL/BNEL
57871462 2073 {
cf95b4f0 2074 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
2075 if(dops[i].rs2) alloc_reg(current,i,dops[i].rs2);
57871462 2076 }
2077 else
cf95b4f0 2078 if((dops[i].opcode&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
57871462 2079 {
cf95b4f0 2080 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
57871462 2081 }
57871462 2082 //else ...
2083}
2084
b14b6a8f 2085static void add_stub(enum stub_type type, void *addr, void *retaddr,
2086 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e)
2087{
d1e4ebd9 2088 assert(stubcount < ARRAY_SIZE(stubs));
b14b6a8f 2089 stubs[stubcount].type = type;
2090 stubs[stubcount].addr = addr;
2091 stubs[stubcount].retaddr = retaddr;
2092 stubs[stubcount].a = a;
2093 stubs[stubcount].b = b;
2094 stubs[stubcount].c = c;
2095 stubs[stubcount].d = d;
2096 stubs[stubcount].e = e;
57871462 2097 stubcount++;
2098}
2099
b14b6a8f 2100static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
81dbbf4c 2101 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist)
b14b6a8f 2102{
2103 add_stub(type, addr, retaddr, i, addr_reg, (uintptr_t)i_regs, ccadj, reglist);
2104}
2105
57871462 2106// Write out a single register
2330734f 2107static void wb_register(signed char r, const signed char regmap[], uint64_t dirty)
57871462 2108{
2109 int hr;
2110 for(hr=0;hr<HOST_REGS;hr++) {
2111 if(hr!=EXCLUDE_REG) {
2112 if((regmap[hr]&63)==r) {
2113 if((dirty>>hr)&1) {
ad49de89 2114 assert(regmap[hr]<64);
2115 emit_storereg(r,hr);
57871462 2116 }
2117 }
2118 }
2119 }
2120}
2121
8062d65a 2122static void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t u)
2123{
2124 //if(dirty_pre==dirty) return;
2125 int hr,reg;
2126 for(hr=0;hr<HOST_REGS;hr++) {
2127 if(hr!=EXCLUDE_REG) {
2128 reg=pre[hr];
2129 if(((~u)>>(reg&63))&1) {
2130 if(reg>0) {
2131 if(((dirty_pre&~dirty)>>hr)&1) {
2132 if(reg>0&&reg<34) {
2133 emit_storereg(reg,hr);
2134 }
2135 else if(reg>=64) {
2136 assert(0);
2137 }
2138 }
2139 }
2140 }
2141 }
2142 }
2143}
2144
687b4580 2145// trashes r2
2146static void pass_args(int a0, int a1)
2147{
2148 if(a0==1&&a1==0) {
2149 // must swap
2150 emit_mov(a0,2); emit_mov(a1,1); emit_mov(2,0);
2151 }
2152 else if(a0!=0&&a1==0) {
2153 emit_mov(a1,1);
2154 if (a0>=0) emit_mov(a0,0);
2155 }
2156 else {
2157 if(a0>=0&&a0!=0) emit_mov(a0,0);
2158 if(a1>=0&&a1!=1) emit_mov(a1,1);
2159 }
2160}
2161
2330734f 2162static void alu_assemble(int i, const struct regstat *i_regs)
57871462 2163{
cf95b4f0 2164 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
2165 if(dops[i].rt1) {
57871462 2166 signed char s1,s2,t;
cf95b4f0 2167 t=get_reg(i_regs->regmap,dops[i].rt1);
57871462 2168 if(t>=0) {
cf95b4f0 2169 s1=get_reg(i_regs->regmap,dops[i].rs1);
2170 s2=get_reg(i_regs->regmap,dops[i].rs2);
2171 if(dops[i].rs1&&dops[i].rs2) {
57871462 2172 assert(s1>=0);
2173 assert(s2>=0);
cf95b4f0 2174 if(dops[i].opcode2&2) emit_sub(s1,s2,t);
57871462 2175 else emit_add(s1,s2,t);
2176 }
cf95b4f0 2177 else if(dops[i].rs1) {
57871462 2178 if(s1>=0) emit_mov(s1,t);
cf95b4f0 2179 else emit_loadreg(dops[i].rs1,t);
57871462 2180 }
cf95b4f0 2181 else if(dops[i].rs2) {
57871462 2182 if(s2>=0) {
cf95b4f0 2183 if(dops[i].opcode2&2) emit_neg(s2,t);
57871462 2184 else emit_mov(s2,t);
2185 }
2186 else {
cf95b4f0 2187 emit_loadreg(dops[i].rs2,t);
2188 if(dops[i].opcode2&2) emit_neg(t,t);
57871462 2189 }
2190 }
2191 else emit_zeroreg(t);
2192 }
2193 }
2194 }
cf95b4f0 2195 if(dops[i].opcode2>=0x2c&&dops[i].opcode2<=0x2f) { // DADD/DADDU/DSUB/DSUBU
00fa9369 2196 assert(0);
57871462 2197 }
cf95b4f0 2198 if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
2199 if(dops[i].rt1) {
ad49de89 2200 signed char s1l,s2l,t;
57871462 2201 {
cf95b4f0 2202 t=get_reg(i_regs->regmap,dops[i].rt1);
57871462 2203 //assert(t>=0);
2204 if(t>=0) {
cf95b4f0 2205 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2206 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2207 if(dops[i].rs2==0) // rx<r0
57871462 2208 {
cf95b4f0 2209 if(dops[i].opcode2==0x2a&&dops[i].rs1!=0) { // SLT
06e425d7 2210 assert(s1l>=0);
57871462 2211 emit_shrimm(s1l,31,t);
06e425d7 2212 }
2213 else // SLTU (unsigned can not be less than zero, 0<0)
57871462 2214 emit_zeroreg(t);
2215 }
cf95b4f0 2216 else if(dops[i].rs1==0) // r0<rx
57871462 2217 {
2218 assert(s2l>=0);
cf95b4f0 2219 if(dops[i].opcode2==0x2a) // SLT
57871462 2220 emit_set_gz32(s2l,t);
2221 else // SLTU (set if not zero)
2222 emit_set_nz32(s2l,t);
2223 }
2224 else{
2225 assert(s1l>=0);assert(s2l>=0);
cf95b4f0 2226 if(dops[i].opcode2==0x2a) // SLT
57871462 2227 emit_set_if_less32(s1l,s2l,t);
2228 else // SLTU
2229 emit_set_if_carry32(s1l,s2l,t);
2230 }
2231 }
2232 }
2233 }
2234 }
cf95b4f0 2235 if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
2236 if(dops[i].rt1) {
ad49de89 2237 signed char s1l,s2l,tl;
cf95b4f0 2238 tl=get_reg(i_regs->regmap,dops[i].rt1);
57871462 2239 {
57871462 2240 if(tl>=0) {
cf95b4f0 2241 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2242 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2243 if(dops[i].rs1&&dops[i].rs2) {
57871462 2244 assert(s1l>=0);
2245 assert(s2l>=0);
cf95b4f0 2246 if(dops[i].opcode2==0x24) { // AND
57871462 2247 emit_and(s1l,s2l,tl);
2248 } else
cf95b4f0 2249 if(dops[i].opcode2==0x25) { // OR
57871462 2250 emit_or(s1l,s2l,tl);
2251 } else
cf95b4f0 2252 if(dops[i].opcode2==0x26) { // XOR
57871462 2253 emit_xor(s1l,s2l,tl);
2254 } else
cf95b4f0 2255 if(dops[i].opcode2==0x27) { // NOR
57871462 2256 emit_or(s1l,s2l,tl);
2257 emit_not(tl,tl);
2258 }
2259 }
2260 else
2261 {
cf95b4f0 2262 if(dops[i].opcode2==0x24) { // AND
57871462 2263 emit_zeroreg(tl);
2264 } else
cf95b4f0 2265 if(dops[i].opcode2==0x25||dops[i].opcode2==0x26) { // OR/XOR
2266 if(dops[i].rs1){
57871462 2267 if(s1l>=0) emit_mov(s1l,tl);
cf95b4f0 2268 else emit_loadreg(dops[i].rs1,tl); // CHECK: regmap_entry?
57871462 2269 }
2270 else
cf95b4f0 2271 if(dops[i].rs2){
57871462 2272 if(s2l>=0) emit_mov(s2l,tl);
cf95b4f0 2273 else emit_loadreg(dops[i].rs2,tl); // CHECK: regmap_entry?
57871462 2274 }
2275 else emit_zeroreg(tl);
2276 } else
cf95b4f0 2277 if(dops[i].opcode2==0x27) { // NOR
2278 if(dops[i].rs1){
57871462 2279 if(s1l>=0) emit_not(s1l,tl);
2280 else {
cf95b4f0 2281 emit_loadreg(dops[i].rs1,tl);
57871462 2282 emit_not(tl,tl);
2283 }
2284 }
2285 else
cf95b4f0 2286 if(dops[i].rs2){
57871462 2287 if(s2l>=0) emit_not(s2l,tl);
2288 else {
cf95b4f0 2289 emit_loadreg(dops[i].rs2,tl);
57871462 2290 emit_not(tl,tl);
2291 }
2292 }
2293 else emit_movimm(-1,tl);
2294 }
2295 }
2296 }
2297 }
2298 }
2299 }
2300}
2301
2330734f 2302static void imm16_assemble(int i, const struct regstat *i_regs)
57871462 2303{
cf95b4f0 2304 if (dops[i].opcode==0x0f) { // LUI
2305 if(dops[i].rt1) {
57871462 2306 signed char t;
cf95b4f0 2307 t=get_reg(i_regs->regmap,dops[i].rt1);
57871462 2308 //assert(t>=0);
2309 if(t>=0) {
2310 if(!((i_regs->isconst>>t)&1))
2311 emit_movimm(imm[i]<<16,t);
2312 }
2313 }
2314 }
cf95b4f0 2315 if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
2316 if(dops[i].rt1) {
57871462 2317 signed char s,t;
cf95b4f0 2318 t=get_reg(i_regs->regmap,dops[i].rt1);
2319 s=get_reg(i_regs->regmap,dops[i].rs1);
2320 if(dops[i].rs1) {
57871462 2321 //assert(t>=0);
2322 //assert(s>=0);
2323 if(t>=0) {
2324 if(!((i_regs->isconst>>t)&1)) {
2325 if(s<0) {
cf95b4f0 2326 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
57871462 2327 emit_addimm(t,imm[i],t);
2328 }else{
2329 if(!((i_regs->wasconst>>s)&1))
2330 emit_addimm(s,imm[i],t);
2331 else
2332 emit_movimm(constmap[i][s]+imm[i],t);
2333 }
2334 }
2335 }
2336 } else {
2337 if(t>=0) {
2338 if(!((i_regs->isconst>>t)&1))
2339 emit_movimm(imm[i],t);
2340 }
2341 }
2342 }
2343 }
cf95b4f0 2344 if(dops[i].opcode==0x18||dops[i].opcode==0x19) { // DADDI/DADDIU
2345 if(dops[i].rt1) {
7c3a5182 2346 signed char sl,tl;
cf95b4f0 2347 tl=get_reg(i_regs->regmap,dops[i].rt1);
2348 sl=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2349 if(tl>=0) {
cf95b4f0 2350 if(dops[i].rs1) {
57871462 2351 assert(sl>=0);
7c3a5182 2352 emit_addimm(sl,imm[i],tl);
57871462 2353 } else {
2354 emit_movimm(imm[i],tl);
57871462 2355 }
2356 }
2357 }
2358 }
cf95b4f0 2359 else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
2360 if(dops[i].rt1) {
2361 //assert(dops[i].rs1!=0); // r0 might be valid, but it's probably a bug
ad49de89 2362 signed char sl,t;
cf95b4f0 2363 t=get_reg(i_regs->regmap,dops[i].rt1);
2364 sl=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2365 //assert(t>=0);
2366 if(t>=0) {
cf95b4f0 2367 if(dops[i].rs1>0) {
2368 if(dops[i].opcode==0x0a) { // SLTI
57871462 2369 if(sl<0) {
cf95b4f0 2370 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
57871462 2371 emit_slti32(t,imm[i],t);
2372 }else{
2373 emit_slti32(sl,imm[i],t);
2374 }
2375 }
2376 else { // SLTIU
2377 if(sl<0) {
cf95b4f0 2378 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
57871462 2379 emit_sltiu32(t,imm[i],t);
2380 }else{
2381 emit_sltiu32(sl,imm[i],t);
2382 }
2383 }
57871462 2384 }else{
2385 // SLTI(U) with r0 is just stupid,
2386 // nonetheless examples can be found
cf95b4f0 2387 if(dops[i].opcode==0x0a) // SLTI
57871462 2388 if(0<imm[i]) emit_movimm(1,t);
2389 else emit_zeroreg(t);
2390 else // SLTIU
2391 {
2392 if(imm[i]) emit_movimm(1,t);
2393 else emit_zeroreg(t);
2394 }
2395 }
2396 }
2397 }
2398 }
cf95b4f0 2399 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
2400 if(dops[i].rt1) {
7c3a5182 2401 signed char sl,tl;
cf95b4f0 2402 tl=get_reg(i_regs->regmap,dops[i].rt1);
2403 sl=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2404 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
cf95b4f0 2405 if(dops[i].opcode==0x0c) //ANDI
57871462 2406 {
cf95b4f0 2407 if(dops[i].rs1) {
57871462 2408 if(sl<0) {
cf95b4f0 2409 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
57871462 2410 emit_andimm(tl,imm[i],tl);
2411 }else{
2412 if(!((i_regs->wasconst>>sl)&1))
2413 emit_andimm(sl,imm[i],tl);
2414 else
2415 emit_movimm(constmap[i][sl]&imm[i],tl);
2416 }
2417 }
2418 else
2419 emit_zeroreg(tl);
57871462 2420 }
2421 else
2422 {
cf95b4f0 2423 if(dops[i].rs1) {
57871462 2424 if(sl<0) {
cf95b4f0 2425 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
57871462 2426 }
cf95b4f0 2427 if(dops[i].opcode==0x0d) { // ORI
581335b0 2428 if(sl<0) {
2429 emit_orimm(tl,imm[i],tl);
2430 }else{
2431 if(!((i_regs->wasconst>>sl)&1))
2432 emit_orimm(sl,imm[i],tl);
2433 else
2434 emit_movimm(constmap[i][sl]|imm[i],tl);
2435 }
57871462 2436 }
cf95b4f0 2437 if(dops[i].opcode==0x0e) { // XORI
581335b0 2438 if(sl<0) {
2439 emit_xorimm(tl,imm[i],tl);
2440 }else{
2441 if(!((i_regs->wasconst>>sl)&1))
2442 emit_xorimm(sl,imm[i],tl);
2443 else
2444 emit_movimm(constmap[i][sl]^imm[i],tl);
2445 }
57871462 2446 }
2447 }
2448 else {
2449 emit_movimm(imm[i],tl);
57871462 2450 }
2451 }
2452 }
2453 }
2454 }
2455}
2456
2330734f 2457static void shiftimm_assemble(int i, const struct regstat *i_regs)
57871462 2458{
cf95b4f0 2459 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
57871462 2460 {
cf95b4f0 2461 if(dops[i].rt1) {
57871462 2462 signed char s,t;
cf95b4f0 2463 t=get_reg(i_regs->regmap,dops[i].rt1);
2464 s=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2465 //assert(t>=0);
dc49e339 2466 if(t>=0&&!((i_regs->isconst>>t)&1)){
cf95b4f0 2467 if(dops[i].rs1==0)
57871462 2468 {
2469 emit_zeroreg(t);
2470 }
2471 else
2472 {
cf95b4f0 2473 if(s<0&&i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
57871462 2474 if(imm[i]) {
cf95b4f0 2475 if(dops[i].opcode2==0) // SLL
57871462 2476 {
2477 emit_shlimm(s<0?t:s,imm[i],t);
2478 }
cf95b4f0 2479 if(dops[i].opcode2==2) // SRL
57871462 2480 {
2481 emit_shrimm(s<0?t:s,imm[i],t);
2482 }
cf95b4f0 2483 if(dops[i].opcode2==3) // SRA
57871462 2484 {
2485 emit_sarimm(s<0?t:s,imm[i],t);
2486 }
2487 }else{
2488 // Shift by zero
2489 if(s>=0 && s!=t) emit_mov(s,t);
2490 }
2491 }
2492 }
cf95b4f0 2493 //emit_storereg(dops[i].rt1,t); //DEBUG
57871462 2494 }
2495 }
cf95b4f0 2496 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
57871462 2497 {
9c45ca93 2498 assert(0);
57871462 2499 }
cf95b4f0 2500 if(dops[i].opcode2==0x3c) // DSLL32
57871462 2501 {
9c45ca93 2502 assert(0);
57871462 2503 }
cf95b4f0 2504 if(dops[i].opcode2==0x3e) // DSRL32
57871462 2505 {
9c45ca93 2506 assert(0);
57871462 2507 }
cf95b4f0 2508 if(dops[i].opcode2==0x3f) // DSRA32
57871462 2509 {
9c45ca93 2510 assert(0);
57871462 2511 }
2512}
2513
2514#ifndef shift_assemble
2330734f 2515static void shift_assemble(int i, const struct regstat *i_regs)
57871462 2516{
3968e69e 2517 signed char s,t,shift;
cf95b4f0 2518 if (dops[i].rt1 == 0)
3968e69e 2519 return;
cf95b4f0 2520 assert(dops[i].opcode2<=0x07); // SLLV/SRLV/SRAV
2521 t = get_reg(i_regs->regmap, dops[i].rt1);
2522 s = get_reg(i_regs->regmap, dops[i].rs1);
2523 shift = get_reg(i_regs->regmap, dops[i].rs2);
3968e69e 2524 if (t < 0)
2525 return;
2526
cf95b4f0 2527 if(dops[i].rs1==0)
3968e69e 2528 emit_zeroreg(t);
cf95b4f0 2529 else if(dops[i].rs2==0) {
3968e69e 2530 assert(s>=0);
2531 if(s!=t) emit_mov(s,t);
2532 }
2533 else {
2534 host_tempreg_acquire();
2535 emit_andimm(shift,31,HOST_TEMPREG);
cf95b4f0 2536 switch(dops[i].opcode2) {
3968e69e 2537 case 4: // SLLV
2538 emit_shl(s,HOST_TEMPREG,t);
2539 break;
2540 case 6: // SRLV
2541 emit_shr(s,HOST_TEMPREG,t);
2542 break;
2543 case 7: // SRAV
2544 emit_sar(s,HOST_TEMPREG,t);
2545 break;
2546 default:
2547 assert(0);
2548 }
2549 host_tempreg_release();
2550 }
57871462 2551}
3968e69e 2552
57871462 2553#endif
2554
8062d65a 2555enum {
2556 MTYPE_8000 = 0,
2557 MTYPE_8020,
2558 MTYPE_0000,
2559 MTYPE_A000,
2560 MTYPE_1F80,
2561};
2562
2563static int get_ptr_mem_type(u_int a)
2564{
2565 if(a < 0x00200000) {
2566 if(a<0x1000&&((start>>20)==0xbfc||(start>>24)==0xa0))
2567 // return wrong, must use memhandler for BIOS self-test to pass
2568 // 007 does similar stuff from a00 mirror, weird stuff
2569 return MTYPE_8000;
2570 return MTYPE_0000;
2571 }
2572 if(0x1f800000 <= a && a < 0x1f801000)
2573 return MTYPE_1F80;
2574 if(0x80200000 <= a && a < 0x80800000)
2575 return MTYPE_8020;
2576 if(0xa0000000 <= a && a < 0xa0200000)
2577 return MTYPE_A000;
2578 return MTYPE_8000;
2579}
2580
37387d8b 2581static int get_ro_reg(const struct regstat *i_regs, int host_tempreg_free)
2582{
2583 int r = get_reg(i_regs->regmap, ROREG);
2584 if (r < 0 && host_tempreg_free) {
2585 host_tempreg_acquire();
2586 emit_loadreg(ROREG, r = HOST_TEMPREG);
2587 }
2588 if (r < 0)
2589 abort();
2590 return r;
2591}
2592
2593static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs,
2594 int addr, int *offset_reg, int *addr_reg_override)
8062d65a 2595{
2596 void *jaddr = NULL;
37387d8b 2597 int type = 0;
2598 int mr = dops[i].rs1;
2599 *offset_reg = -1;
8062d65a 2600 if(((smrv_strong|smrv_weak)>>mr)&1) {
2601 type=get_ptr_mem_type(smrv[mr]);
2602 //printf("set %08x @%08x r%d %d\n", smrv[mr], start+i*4, mr, type);
2603 }
2604 else {
2605 // use the mirror we are running on
2606 type=get_ptr_mem_type(start);
2607 //printf("set nospec @%08x r%d %d\n", start+i*4, mr, type);
2608 }
2609
2610 if(type==MTYPE_8020) { // RAM 80200000+ mirror
d1e4ebd9 2611 host_tempreg_acquire();
8062d65a 2612 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
2613 addr=*addr_reg_override=HOST_TEMPREG;
2614 type=0;
2615 }
2616 else if(type==MTYPE_0000) { // RAM 0 mirror
d1e4ebd9 2617 host_tempreg_acquire();
8062d65a 2618 emit_orimm(addr,0x80000000,HOST_TEMPREG);
2619 addr=*addr_reg_override=HOST_TEMPREG;
2620 type=0;
2621 }
2622 else if(type==MTYPE_A000) { // RAM A mirror
d1e4ebd9 2623 host_tempreg_acquire();
8062d65a 2624 emit_andimm(addr,~0x20000000,HOST_TEMPREG);
2625 addr=*addr_reg_override=HOST_TEMPREG;
2626 type=0;
2627 }
2628 else if(type==MTYPE_1F80) { // scratchpad
2629 if (psxH == (void *)0x1f800000) {
d1e4ebd9 2630 host_tempreg_acquire();
3968e69e 2631 emit_xorimm(addr,0x1f800000,HOST_TEMPREG);
8062d65a 2632 emit_cmpimm(HOST_TEMPREG,0x1000);
d1e4ebd9 2633 host_tempreg_release();
8062d65a 2634 jaddr=out;
2635 emit_jc(0);
2636 }
2637 else {
2638 // do the usual RAM check, jump will go to the right handler
2639 type=0;
2640 }
2641 }
2642
37387d8b 2643 if (type == 0) // need ram check
8062d65a 2644 {
2645 emit_cmpimm(addr,RAM_SIZE);
37387d8b 2646 jaddr = out;
8062d65a 2647 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2648 // Hint to branch predictor that the branch is unlikely to be taken
37387d8b 2649 if (dops[i].rs1 >= 28)
8062d65a 2650 emit_jno_unlikely(0);
2651 else
2652 #endif
2653 emit_jno(0);
37387d8b 2654 if (ram_offset != 0)
2655 *offset_reg = get_ro_reg(i_regs, 0);
8062d65a 2656 }
2657
2658 return jaddr;
2659}
2660
687b4580 2661// return memhandler, or get directly accessable address and return 0
2662static void *get_direct_memhandler(void *table, u_int addr,
2663 enum stub_type type, uintptr_t *addr_host)
2664{
c979e8c2 2665 uintptr_t msb = 1ull << (sizeof(uintptr_t)*8 - 1);
687b4580 2666 uintptr_t l1, l2 = 0;
2667 l1 = ((uintptr_t *)table)[addr>>12];
c979e8c2 2668 if (!(l1 & msb)) {
687b4580 2669 uintptr_t v = l1 << 1;
2670 *addr_host = v + addr;
2671 return NULL;
2672 }
2673 else {
2674 l1 <<= 1;
2675 if (type == LOADB_STUB || type == LOADBU_STUB || type == STOREB_STUB)
2676 l2 = ((uintptr_t *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)];
2677 else if (type == LOADH_STUB || type == LOADHU_STUB || type == STOREH_STUB)
c979e8c2 2678 l2 = ((uintptr_t *)l1)[0x1000/4 + (addr&0xfff)/2];
687b4580 2679 else
c979e8c2 2680 l2 = ((uintptr_t *)l1)[(addr&0xfff)/4];
2681 if (!(l2 & msb)) {
687b4580 2682 uintptr_t v = l2 << 1;
2683 *addr_host = v + (addr&0xfff);
2684 return NULL;
2685 }
2686 return (void *)(l2 << 1);
2687 }
2688}
2689
81dbbf4c 2690static u_int get_host_reglist(const signed char *regmap)
2691{
2692 u_int reglist = 0, hr;
2693 for (hr = 0; hr < HOST_REGS; hr++) {
2694 if (hr != EXCLUDE_REG && regmap[hr] >= 0)
2695 reglist |= 1 << hr;
2696 }
2697 return reglist;
2698}
2699
2700static u_int reglist_exclude(u_int reglist, int r1, int r2)
2701{
2702 if (r1 >= 0)
2703 reglist &= ~(1u << r1);
2704 if (r2 >= 0)
2705 reglist &= ~(1u << r2);
2706 return reglist;
2707}
2708
e3c6bdb5 2709// find a temp caller-saved register not in reglist (so assumed to be free)
2710static int reglist_find_free(u_int reglist)
2711{
2712 u_int free_regs = ~reglist & CALLER_SAVE_REGS;
2713 if (free_regs == 0)
2714 return -1;
2715 return __builtin_ctz(free_regs);
2716}
2717
37387d8b 2718static void do_load_word(int a, int rt, int offset_reg)
2719{
2720 if (offset_reg >= 0)
2721 emit_ldr_dualindexed(offset_reg, a, rt);
2722 else
2723 emit_readword_indexed(0, a, rt);
2724}
2725
2726static void do_store_word(int a, int ofs, int rt, int offset_reg, int preseve_a)
2727{
2728 if (offset_reg < 0) {
2729 emit_writeword_indexed(rt, ofs, a);
2730 return;
2731 }
2732 if (ofs != 0)
2733 emit_addimm(a, ofs, a);
2734 emit_str_dualindexed(offset_reg, a, rt);
2735 if (ofs != 0 && preseve_a)
2736 emit_addimm(a, -ofs, a);
2737}
2738
2739static void do_store_hword(int a, int ofs, int rt, int offset_reg, int preseve_a)
2740{
2741 if (offset_reg < 0) {
2742 emit_writehword_indexed(rt, ofs, a);
2743 return;
2744 }
2745 if (ofs != 0)
2746 emit_addimm(a, ofs, a);
2747 emit_strh_dualindexed(offset_reg, a, rt);
2748 if (ofs != 0 && preseve_a)
2749 emit_addimm(a, -ofs, a);
2750}
2751
2752static void do_store_byte(int a, int rt, int offset_reg)
2753{
2754 if (offset_reg >= 0)
2755 emit_strb_dualindexed(offset_reg, a, rt);
2756 else
2757 emit_writebyte_indexed(rt, 0, a);
2758}
2759
2330734f 2760static void load_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 2761{
7c3a5182 2762 int s,tl,addr;
57871462 2763 int offset;
b14b6a8f 2764 void *jaddr=0;
5bf843dc 2765 int memtarget=0,c=0;
37387d8b 2766 int offset_reg = -1;
2767 int fastio_reg_override = -1;
81dbbf4c 2768 u_int reglist=get_host_reglist(i_regs->regmap);
cf95b4f0 2769 tl=get_reg(i_regs->regmap,dops[i].rt1);
2770 s=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2771 offset=imm[i];
57871462 2772 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2773 if(s>=0) {
2774 c=(i_regs->wasconst>>s)&1;
af4ee1fe 2775 if (c) {
2776 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
af4ee1fe 2777 }
57871462 2778 }
57871462 2779 //printf("load_assemble: c=%d\n",c);
643aeae3 2780 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
57871462 2781 // FIXME: Even if the load is a NOP, we should check for pagefaults...
581335b0 2782 if((tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80))
cf95b4f0 2783 ||dops[i].rt1==0) {
5bf843dc 2784 // could be FIFO, must perform the read
f18c0f46 2785 // ||dummy read
5bf843dc 2786 assem_debug("(forced read)\n");
2787 tl=get_reg(i_regs->regmap,-1);
2788 assert(tl>=0);
5bf843dc 2789 }
2790 if(offset||s<0||c) addr=tl;
2791 else addr=s;
535d208a 2792 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2793 if(tl>=0) {
2794 //printf("load_assemble: c=%d\n",c);
643aeae3 2795 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
535d208a 2796 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2797 reglist&=~(1<<tl);
1edfcc68 2798 if(!c) {
1edfcc68 2799 #ifdef R29_HACK
2800 // Strmnnrmn's speed hack
cf95b4f0 2801 if(dops[i].rs1!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
1edfcc68 2802 #endif
2803 {
37387d8b 2804 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
2805 &offset_reg, &fastio_reg_override);
535d208a 2806 }
1edfcc68 2807 }
37387d8b 2808 else if (ram_offset && memtarget) {
2809 offset_reg = get_ro_reg(i_regs, 0);
535d208a 2810 }
cf95b4f0 2811 int dummy=(dops[i].rt1==0)||(tl!=get_reg(i_regs->regmap,dops[i].rt1)); // ignore loads to r0 and unneeded reg
37387d8b 2812 switch (dops[i].opcode) {
2813 case 0x20: // LB
535d208a 2814 if(!c||memtarget) {
2815 if(!dummy) {
37387d8b 2816 int a = tl;
2817 if (!c) a = addr;
2818 if (fastio_reg_override >= 0)
2819 a = fastio_reg_override;
b1570849 2820
37387d8b 2821 if (offset_reg >= 0)
2822 emit_ldrsb_dualindexed(offset_reg, a, tl);
2823 else
2824 emit_movsbl_indexed(0, a, tl);
57871462 2825 }
535d208a 2826 if(jaddr)
2330734f 2827 add_stub_r(LOADB_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 2828 }
535d208a 2829 else
2330734f 2830 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 2831 break;
2832 case 0x21: // LH
535d208a 2833 if(!c||memtarget) {
2834 if(!dummy) {
37387d8b 2835 int a = tl;
2836 if (!c) a = addr;
2837 if (fastio_reg_override >= 0)
2838 a = fastio_reg_override;
2839 if (offset_reg >= 0)
2840 emit_ldrsh_dualindexed(offset_reg, a, tl);
2841 else
2842 emit_movswl_indexed(0, a, tl);
57871462 2843 }
535d208a 2844 if(jaddr)
2330734f 2845 add_stub_r(LOADH_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 2846 }
535d208a 2847 else
2330734f 2848 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 2849 break;
2850 case 0x23: // LW
535d208a 2851 if(!c||memtarget) {
2852 if(!dummy) {
37387d8b 2853 int a = addr;
2854 if (fastio_reg_override >= 0)
2855 a = fastio_reg_override;
2856 do_load_word(a, tl, offset_reg);
57871462 2857 }
535d208a 2858 if(jaddr)
2330734f 2859 add_stub_r(LOADW_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 2860 }
535d208a 2861 else
2330734f 2862 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 2863 break;
2864 case 0x24: // LBU
535d208a 2865 if(!c||memtarget) {
2866 if(!dummy) {
37387d8b 2867 int a = tl;
2868 if (!c) a = addr;
2869 if (fastio_reg_override >= 0)
2870 a = fastio_reg_override;
b1570849 2871
37387d8b 2872 if (offset_reg >= 0)
2873 emit_ldrb_dualindexed(offset_reg, a, tl);
2874 else
2875 emit_movzbl_indexed(0, a, tl);
57871462 2876 }
535d208a 2877 if(jaddr)
2330734f 2878 add_stub_r(LOADBU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 2879 }
535d208a 2880 else
2330734f 2881 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 2882 break;
2883 case 0x25: // LHU
535d208a 2884 if(!c||memtarget) {
2885 if(!dummy) {
37387d8b 2886 int a = tl;
2887 if(!c) a = addr;
2888 if (fastio_reg_override >= 0)
2889 a = fastio_reg_override;
2890 if (offset_reg >= 0)
2891 emit_ldrh_dualindexed(offset_reg, a, tl);
2892 else
2893 emit_movzwl_indexed(0, a, tl);
57871462 2894 }
535d208a 2895 if(jaddr)
2330734f 2896 add_stub_r(LOADHU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 2897 }
535d208a 2898 else
2330734f 2899 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 2900 break;
2901 case 0x27: // LWU
2902 case 0x37: // LD
2903 default:
9c45ca93 2904 assert(0);
57871462 2905 }
535d208a 2906 }
37387d8b 2907 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
d1e4ebd9 2908 host_tempreg_release();
57871462 2909}
2910
2911#ifndef loadlr_assemble
2330734f 2912static void loadlr_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 2913{
3968e69e 2914 int s,tl,temp,temp2,addr;
2915 int offset;
2916 void *jaddr=0;
2917 int memtarget=0,c=0;
37387d8b 2918 int offset_reg = -1;
2919 int fastio_reg_override = -1;
81dbbf4c 2920 u_int reglist=get_host_reglist(i_regs->regmap);
cf95b4f0 2921 tl=get_reg(i_regs->regmap,dops[i].rt1);
2922 s=get_reg(i_regs->regmap,dops[i].rs1);
3968e69e 2923 temp=get_reg(i_regs->regmap,-1);
2924 temp2=get_reg(i_regs->regmap,FTEMP);
2925 addr=get_reg(i_regs->regmap,AGEN1+(i&1));
2926 assert(addr<0);
2927 offset=imm[i];
3968e69e 2928 reglist|=1<<temp;
2929 if(offset||s<0||c) addr=temp2;
2930 else addr=s;
2931 if(s>=0) {
2932 c=(i_regs->wasconst>>s)&1;
2933 if(c) {
2934 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2935 }
2936 }
2937 if(!c) {
2938 emit_shlimm(addr,3,temp);
cf95b4f0 2939 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
3968e69e 2940 emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR
2941 }else{
2942 emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR
2943 }
37387d8b 2944 jaddr = emit_fastpath_cmp_jump(i, i_regs, temp2,
2945 &offset_reg, &fastio_reg_override);
3968e69e 2946 }
2947 else {
37387d8b 2948 if (ram_offset && memtarget) {
2949 offset_reg = get_ro_reg(i_regs, 0);
3968e69e 2950 }
cf95b4f0 2951 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
3968e69e 2952 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
2953 }else{
2954 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
2955 }
2956 }
cf95b4f0 2957 if (dops[i].opcode==0x22||dops[i].opcode==0x26) { // LWL/LWR
3968e69e 2958 if(!c||memtarget) {
37387d8b 2959 int a = temp2;
2960 if (fastio_reg_override >= 0)
2961 a = fastio_reg_override;
2962 do_load_word(a, temp2, offset_reg);
2963 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
2964 host_tempreg_release();
2330734f 2965 if(jaddr) add_stub_r(LOADW_STUB,jaddr,out,i,temp2,i_regs,ccadj_,reglist);
3968e69e 2966 }
2967 else
2330734f 2968 inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj_,reglist);
cf95b4f0 2969 if(dops[i].rt1) {
3968e69e 2970 assert(tl>=0);
2971 emit_andimm(temp,24,temp);
cf95b4f0 2972 if (dops[i].opcode==0x22) // LWL
3968e69e 2973 emit_xorimm(temp,24,temp);
2974 host_tempreg_acquire();
2975 emit_movimm(-1,HOST_TEMPREG);
cf95b4f0 2976 if (dops[i].opcode==0x26) {
3968e69e 2977 emit_shr(temp2,temp,temp2);
2978 emit_bic_lsr(tl,HOST_TEMPREG,temp,tl);
2979 }else{
2980 emit_shl(temp2,temp,temp2);
2981 emit_bic_lsl(tl,HOST_TEMPREG,temp,tl);
2982 }
2983 host_tempreg_release();
2984 emit_or(temp2,tl,tl);
2985 }
cf95b4f0 2986 //emit_storereg(dops[i].rt1,tl); // DEBUG
3968e69e 2987 }
cf95b4f0 2988 if (dops[i].opcode==0x1A||dops[i].opcode==0x1B) { // LDL/LDR
3968e69e 2989 assert(0);
2990 }
57871462 2991}
2992#endif
2993
2330734f 2994static void store_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 2995{
9c45ca93 2996 int s,tl;
57871462 2997 int addr,temp;
2998 int offset;
b14b6a8f 2999 void *jaddr=0;
37387d8b 3000 enum stub_type type=0;
666a299d 3001 int memtarget=0,c=0;
57871462 3002 int agr=AGEN1+(i&1);
37387d8b 3003 int offset_reg = -1;
3004 int fastio_reg_override = -1;
81dbbf4c 3005 u_int reglist=get_host_reglist(i_regs->regmap);
cf95b4f0 3006 tl=get_reg(i_regs->regmap,dops[i].rs2);
3007 s=get_reg(i_regs->regmap,dops[i].rs1);
57871462 3008 temp=get_reg(i_regs->regmap,agr);
3009 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3010 offset=imm[i];
3011 if(s>=0) {
3012 c=(i_regs->wasconst>>s)&1;
af4ee1fe 3013 if(c) {
3014 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
af4ee1fe 3015 }
57871462 3016 }
3017 assert(tl>=0);
3018 assert(temp>=0);
57871462 3019 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3020 if(offset||s<0||c) addr=temp;
3021 else addr=s;
37387d8b 3022 if (!c) {
3023 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
3024 &offset_reg, &fastio_reg_override);
1edfcc68 3025 }
37387d8b 3026 else if (ram_offset && memtarget) {
3027 offset_reg = get_ro_reg(i_regs, 0);
57871462 3028 }
3029
37387d8b 3030 switch (dops[i].opcode) {
3031 case 0x28: // SB
57871462 3032 if(!c||memtarget) {
37387d8b 3033 int a = temp;
3034 if (!c) a = addr;
3035 if (fastio_reg_override >= 0)
3036 a = fastio_reg_override;
3037 do_store_byte(a, tl, offset_reg);
3038 }
3039 type = STOREB_STUB;
3040 break;
3041 case 0x29: // SH
57871462 3042 if(!c||memtarget) {
37387d8b 3043 int a = temp;
3044 if (!c) a = addr;
3045 if (fastio_reg_override >= 0)
3046 a = fastio_reg_override;
3047 do_store_hword(a, 0, tl, offset_reg, 1);
3048 }
3049 type = STOREH_STUB;
3050 break;
3051 case 0x2B: // SW
dadf55f2 3052 if(!c||memtarget) {
37387d8b 3053 int a = addr;
3054 if (fastio_reg_override >= 0)
3055 a = fastio_reg_override;
3056 do_store_word(a, 0, tl, offset_reg, 1);
3057 }
3058 type = STOREW_STUB;
3059 break;
3060 case 0x3F: // SD
3061 default:
9c45ca93 3062 assert(0);
57871462 3063 }
37387d8b 3064 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
d1e4ebd9 3065 host_tempreg_release();
b96d3df7 3066 if(jaddr) {
3067 // PCSX store handlers don't check invcode again
3068 reglist|=1<<addr;
2330734f 3069 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist);
b96d3df7 3070 jaddr=0;
3071 }
cf95b4f0 3072 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
57871462 3073 if(!c||memtarget) {
3074 #ifdef DESTRUCTIVE_SHIFT
3075 // The x86 shift operation is 'destructive'; it overwrites the
3076 // source register, so we need to make a copy first and use that.
3077 addr=temp;
3078 #endif
3079 #if defined(HOST_IMM8)
3080 int ir=get_reg(i_regs->regmap,INVCP);
3081 assert(ir>=0);
3082 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3083 #else
643aeae3 3084 emit_cmpmem_indexedsr12_imm(invalid_code,addr,1);
57871462 3085 #endif
0bbd1454 3086 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3087 emit_callne(invalidate_addr_reg[addr]);
3088 #else
b14b6a8f 3089 void *jaddr2 = out;
57871462 3090 emit_jne(0);
b14b6a8f 3091 add_stub(INVCODE_STUB,jaddr2,out,reglist|(1<<HOST_CCREG),addr,0,0,0);
0bbd1454 3092 #endif
57871462 3093 }
3094 }
7a518516 3095 u_int addr_val=constmap[i][s]+offset;
3eaa7048 3096 if(jaddr) {
2330734f 3097 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3eaa7048 3098 } else if(c&&!memtarget) {
2330734f 3099 inline_writestub(type,i,addr_val,i_regs->regmap,dops[i].rs2,ccadj_,reglist);
7a518516 3100 }
3101 // basic current block modification detection..
3102 // not looking back as that should be in mips cache already
3968e69e 3103 // (see Spyro2 title->attract mode)
7a518516 3104 if(c&&start+i*4<addr_val&&addr_val<start+slen*4) {
c43b5311 3105 SysPrintf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4);
7a518516 3106 assert(i_regs->regmap==regs[i].regmap); // not delay slot
3107 if(i_regs->regmap==regs[i].regmap) {
ad49de89 3108 load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
3109 wb_dirtys(regs[i].regmap_entry,regs[i].wasdirty);
7a518516 3110 emit_movimm(start+i*4+4,0);
643aeae3 3111 emit_writeword(0,&pcaddr);
d1e4ebd9 3112 emit_addimm(HOST_CCREG,2,HOST_CCREG);
2a014d73 3113 emit_far_call(get_addr_ht);
d1e4ebd9 3114 emit_jmpreg(0);
7a518516 3115 }
3eaa7048 3116 }
57871462 3117}
3118
2330734f 3119static void storelr_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 3120{
9c45ca93 3121 int s,tl;
57871462 3122 int temp;
57871462 3123 int offset;
b14b6a8f 3124 void *jaddr=0;
37387d8b 3125 void *case1, *case23, *case3;
df4dc2b1 3126 void *done0, *done1, *done2;
af4ee1fe 3127 int memtarget=0,c=0;
fab5d06d 3128 int agr=AGEN1+(i&1);
37387d8b 3129 int offset_reg = -1;
81dbbf4c 3130 u_int reglist=get_host_reglist(i_regs->regmap);
cf95b4f0 3131 tl=get_reg(i_regs->regmap,dops[i].rs2);
3132 s=get_reg(i_regs->regmap,dops[i].rs1);
fab5d06d 3133 temp=get_reg(i_regs->regmap,agr);
3134 if(temp<0) temp=get_reg(i_regs->regmap,-1);
57871462 3135 offset=imm[i];
3136 if(s>=0) {
3137 c=(i_regs->isconst>>s)&1;
af4ee1fe 3138 if(c) {
3139 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
af4ee1fe 3140 }
57871462 3141 }
3142 assert(tl>=0);
535d208a 3143 assert(temp>=0);
1edfcc68 3144 if(!c) {
3145 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3146 if(!offset&&s!=temp) emit_mov(s,temp);
b14b6a8f 3147 jaddr=out;
1edfcc68 3148 emit_jno(0);
3149 }
3150 else
3151 {
cf95b4f0 3152 if(!memtarget||!dops[i].rs1) {
b14b6a8f 3153 jaddr=out;
535d208a 3154 emit_jmp(0);
57871462 3155 }
535d208a 3156 }
37387d8b 3157 if (ram_offset)
3158 offset_reg = get_ro_reg(i_regs, 0);
535d208a 3159
cf95b4f0 3160 if (dops[i].opcode==0x2C||dops[i].opcode==0x2D) { // SDL/SDR
9c45ca93 3161 assert(0);
535d208a 3162 }
57871462 3163
535d208a 3164 emit_testimm(temp,2);
37387d8b 3165 case23=out;
535d208a 3166 emit_jne(0);
3167 emit_testimm(temp,1);
df4dc2b1 3168 case1=out;
535d208a 3169 emit_jne(0);
3170 // 0
37387d8b 3171 if (dops[i].opcode == 0x2A) { // SWL
3172 // Write msb into least significant byte
3173 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
3174 do_store_byte(temp, tl, offset_reg);
3175 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
535d208a 3176 }
37387d8b 3177 else if (dops[i].opcode == 0x2E) { // SWR
3178 // Write entire word
3179 do_store_word(temp, 0, tl, offset_reg, 1);
535d208a 3180 }
37387d8b 3181 done0 = out;
535d208a 3182 emit_jmp(0);
3183 // 1
df4dc2b1 3184 set_jump_target(case1, out);
37387d8b 3185 if (dops[i].opcode == 0x2A) { // SWL
3186 // Write two msb into two least significant bytes
3187 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3188 do_store_hword(temp, -1, tl, offset_reg, 0);
3189 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
535d208a 3190 }
37387d8b 3191 else if (dops[i].opcode == 0x2E) { // SWR
3192 // Write 3 lsb into three most significant bytes
3193 do_store_byte(temp, tl, offset_reg);
3194 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3195 do_store_hword(temp, 1, tl, offset_reg, 0);
3196 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
535d208a 3197 }
df4dc2b1 3198 done1=out;
535d208a 3199 emit_jmp(0);
37387d8b 3200 // 2,3
3201 set_jump_target(case23, out);
535d208a 3202 emit_testimm(temp,1);
37387d8b 3203 case3 = out;
535d208a 3204 emit_jne(0);
37387d8b 3205 // 2
cf95b4f0 3206 if (dops[i].opcode==0x2A) { // SWL
37387d8b 3207 // Write 3 msb into three least significant bytes
3208 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3209 do_store_hword(temp, -2, tl, offset_reg, 1);
3210 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3211 do_store_byte(temp, tl, offset_reg);
3212 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
535d208a 3213 }
37387d8b 3214 else if (dops[i].opcode == 0x2E) { // SWR
3215 // Write two lsb into two most significant bytes
3216 do_store_hword(temp, 0, tl, offset_reg, 1);
535d208a 3217 }
37387d8b 3218 done2 = out;
535d208a 3219 emit_jmp(0);
3220 // 3
df4dc2b1 3221 set_jump_target(case3, out);
37387d8b 3222 if (dops[i].opcode == 0x2A) { // SWL
3223 do_store_word(temp, -3, tl, offset_reg, 0);
535d208a 3224 }
37387d8b 3225 else if (dops[i].opcode == 0x2E) { // SWR
3226 do_store_byte(temp, tl, offset_reg);
535d208a 3227 }
df4dc2b1 3228 set_jump_target(done0, out);
3229 set_jump_target(done1, out);
3230 set_jump_target(done2, out);
37387d8b 3231 if (offset_reg == HOST_TEMPREG)
3232 host_tempreg_release();
535d208a 3233 if(!c||!memtarget)
2330734f 3234 add_stub_r(STORELR_STUB,jaddr,out,i,temp,i_regs,ccadj_,reglist);
cf95b4f0 3235 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
57871462 3236 #if defined(HOST_IMM8)
3237 int ir=get_reg(i_regs->regmap,INVCP);
3238 assert(ir>=0);
3239 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3240 #else
643aeae3 3241 emit_cmpmem_indexedsr12_imm(invalid_code,temp,1);
57871462 3242 #endif
535d208a 3243 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3244 emit_callne(invalidate_addr_reg[temp]);
3245 #else
b14b6a8f 3246 void *jaddr2 = out;
57871462 3247 emit_jne(0);
b14b6a8f 3248 add_stub(INVCODE_STUB,jaddr2,out,reglist|(1<<HOST_CCREG),temp,0,0,0);
535d208a 3249 #endif
57871462 3250 }
57871462 3251}
3252
2330734f 3253static void cop0_assemble(int i, const struct regstat *i_regs, int ccadj_)
8062d65a 3254{
cf95b4f0 3255 if(dops[i].opcode2==0) // MFC0
8062d65a 3256 {
cf95b4f0 3257 signed char t=get_reg(i_regs->regmap,dops[i].rt1);
8062d65a 3258 u_int copr=(source[i]>>11)&0x1f;
3259 //assert(t>=0); // Why does this happen? OOT is weird
cf95b4f0 3260 if(t>=0&&dops[i].rt1!=0) {
8062d65a 3261 emit_readword(&reg_cop0[copr],t);
3262 }
3263 }
cf95b4f0 3264 else if(dops[i].opcode2==4) // MTC0
8062d65a 3265 {
cf95b4f0 3266 signed char s=get_reg(i_regs->regmap,dops[i].rs1);
8062d65a 3267 char copr=(source[i]>>11)&0x1f;
3268 assert(s>=0);
cf95b4f0 3269 wb_register(dops[i].rs1,i_regs->regmap,i_regs->dirty);
8062d65a 3270 if(copr==9||copr==11||copr==12||copr==13) {
3271 emit_readword(&last_count,HOST_TEMPREG);
3272 emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
3273 emit_add(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
2330734f 3274 emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG);
8062d65a 3275 emit_writeword(HOST_CCREG,&Count);
3276 }
3277 // What a mess. The status register (12) can enable interrupts,
3278 // so needs a special case to handle a pending interrupt.
3279 // The interrupt must be taken immediately, because a subsequent
3280 // instruction might disable interrupts again.
3281 if(copr==12||copr==13) {
3282 if (is_delayslot) {
3283 // burn cycles to cause cc_interrupt, which will
3284 // reschedule next_interupt. Relies on CCREG from above.
3285 assem_debug("MTC0 DS %d\n", copr);
3286 emit_writeword(HOST_CCREG,&last_count);
3287 emit_movimm(0,HOST_CCREG);
3288 emit_storereg(CCREG,HOST_CCREG);
cf95b4f0 3289 emit_loadreg(dops[i].rs1,1);
8062d65a 3290 emit_movimm(copr,0);
2a014d73 3291 emit_far_call(pcsx_mtc0_ds);
cf95b4f0 3292 emit_loadreg(dops[i].rs1,s);
8062d65a 3293 return;
3294 }
3295 emit_movimm(start+i*4+4,HOST_TEMPREG);
3296 emit_writeword(HOST_TEMPREG,&pcaddr);
3297 emit_movimm(0,HOST_TEMPREG);
3298 emit_writeword(HOST_TEMPREG,&pending_exception);
3299 }
8062d65a 3300 if(s==HOST_CCREG)
cf95b4f0 3301 emit_loadreg(dops[i].rs1,1);
8062d65a 3302 else if(s!=1)
3303 emit_mov(s,1);
3304 emit_movimm(copr,0);
2a014d73 3305 emit_far_call(pcsx_mtc0);
8062d65a 3306 if(copr==9||copr==11||copr==12||copr==13) {
3307 emit_readword(&Count,HOST_CCREG);
3308 emit_readword(&next_interupt,HOST_TEMPREG);
2330734f 3309 emit_addimm(HOST_CCREG,-ccadj_,HOST_CCREG);
8062d65a 3310 emit_sub(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
3311 emit_writeword(HOST_TEMPREG,&last_count);
3312 emit_storereg(CCREG,HOST_CCREG);
3313 }
3314 if(copr==12||copr==13) {
3315 assert(!is_delayslot);
3316 emit_readword(&pending_exception,14);
3317 emit_test(14,14);
d1e4ebd9 3318 void *jaddr = out;
3319 emit_jeq(0);
3320 emit_readword(&pcaddr, 0);
3321 emit_addimm(HOST_CCREG,2,HOST_CCREG);
2a014d73 3322 emit_far_call(get_addr_ht);
d1e4ebd9 3323 emit_jmpreg(0);
3324 set_jump_target(jaddr, out);
8062d65a 3325 }
cf95b4f0 3326 emit_loadreg(dops[i].rs1,s);
8062d65a 3327 }
3328 else
3329 {
cf95b4f0 3330 assert(dops[i].opcode2==0x10);
8062d65a 3331 //if((source[i]&0x3f)==0x10) // RFE
3332 {
3333 emit_readword(&Status,0);
3334 emit_andimm(0,0x3c,1);
3335 emit_andimm(0,~0xf,0);
3336 emit_orrshr_imm(1,2,0);
3337 emit_writeword(0,&Status);
3338 }
3339 }
3340}
3341
2330734f 3342static void cop1_unusable(int i, const struct regstat *i_regs)
8062d65a 3343{
3344 // XXX: should just just do the exception instead
3345 //if(!cop1_usable)
3346 {
3347 void *jaddr=out;
3348 emit_jmp(0);
3349 add_stub_r(FP_STUB,jaddr,out,i,0,i_regs,is_delayslot,0);
3350 }
3351}
3352
2330734f 3353static void cop1_assemble(int i, const struct regstat *i_regs)
8062d65a 3354{
3355 cop1_unusable(i, i_regs);
3356}
3357
2330734f 3358static void c1ls_assemble(int i, const struct regstat *i_regs)
57871462 3359{
3d624f89 3360 cop1_unusable(i, i_regs);
57871462 3361}
3362
8062d65a 3363// FP_STUB
3364static void do_cop1stub(int n)
3365{
3366 literal_pool(256);
3367 assem_debug("do_cop1stub %x\n",start+stubs[n].a*4);
3368 set_jump_target(stubs[n].addr, out);
3369 int i=stubs[n].a;
3370// int rs=stubs[n].b;
3371 struct regstat *i_regs=(struct regstat *)stubs[n].c;
3372 int ds=stubs[n].d;
3373 if(!ds) {
3374 load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
3375 //if(i_regs!=&regs[i]) printf("oops: regs[i]=%x i_regs=%x",(int)&regs[i],(int)i_regs);
3376 }
3377 //else {printf("fp exception in delay slot\n");}
3378 wb_dirtys(i_regs->regmap_entry,i_regs->wasdirty);
3379 if(regs[i].regmap_entry[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
3380 emit_movimm(start+(i-ds)*4,EAX); // Get PC
2330734f 3381 emit_addimm(HOST_CCREG,ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
2a014d73 3382 emit_far_jump(ds?fp_exception_ds:fp_exception);
8062d65a 3383}
3384
e3c6bdb5 3385static int cop2_is_stalling_op(int i, int *cycles)
3386{
cf95b4f0 3387 if (dops[i].opcode == 0x3a) { // SWC2
e3c6bdb5 3388 *cycles = 0;
3389 return 1;
3390 }
cf95b4f0 3391 if (dops[i].itype == COP2 && (dops[i].opcode2 == 0 || dops[i].opcode2 == 2)) { // MFC2/CFC2
e3c6bdb5 3392 *cycles = 0;
3393 return 1;
3394 }
cf95b4f0 3395 if (dops[i].itype == C2OP) {
e3c6bdb5 3396 *cycles = gte_cycletab[source[i] & 0x3f];
3397 return 1;
3398 }
3399 // ... what about MTC2/CTC2/LWC2?
3400 return 0;
3401}
3402
3403#if 0
3404static void log_gte_stall(int stall, u_int cycle)
3405{
3406 if ((u_int)stall <= 44)
3407 printf("x stall %2d %u\n", stall, cycle + last_count);
e3c6bdb5 3408}
3409
3410static void emit_log_gte_stall(int i, int stall, u_int reglist)
3411{
3412 save_regs(reglist);
3413 if (stall > 0)
3414 emit_movimm(stall, 0);
3415 else
3416 emit_mov(HOST_TEMPREG, 0);
2330734f 3417 emit_addimm(HOST_CCREG, ccadj[i], 1);
e3c6bdb5 3418 emit_far_call(log_gte_stall);
3419 restore_regs(reglist);
3420}
3421#endif
3422
32631e6a 3423static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist)
81dbbf4c 3424{
e3c6bdb5 3425 int j = i, other_gte_op_cycles = -1, stall = -MAXBLOCK, cycles_passed;
3426 int rtmp = reglist_find_free(reglist);
3427
32631e6a 3428 if (HACK_ENABLED(NDHACK_NO_STALLS))
81dbbf4c 3429 return;
81dbbf4c 3430 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3431 // happens occasionally... cc evicted? Don't bother then
3432 //printf("no cc %08x\n", start + i*4);
3433 return;
3434 }
cf95b4f0 3435 if (!dops[i].bt) {
e3c6bdb5 3436 for (j = i - 1; j >= 0; j--) {
cf95b4f0 3437 //if (dops[j].is_ds) break;
3438 if (cop2_is_stalling_op(j, &other_gte_op_cycles) || dops[j].bt)
e3c6bdb5 3439 break;
2330734f 3440 if (j > 0 && ccadj[j - 1] > ccadj[j])
3441 break;
e3c6bdb5 3442 }
32631e6a 3443 j = max(j, 0);
e3c6bdb5 3444 }
2330734f 3445 cycles_passed = ccadj[i] - ccadj[j];
e3c6bdb5 3446 if (other_gte_op_cycles >= 0)
3447 stall = other_gte_op_cycles - cycles_passed;
3448 else if (cycles_passed >= 44)
3449 stall = 0; // can't stall
3450 if (stall == -MAXBLOCK && rtmp >= 0) {
3451 // unknown stall, do the expensive runtime check
32631e6a 3452 assem_debug("; cop2_do_stall_check\n");
e3c6bdb5 3453#if 0 // too slow
3454 save_regs(reglist);
3455 emit_movimm(gte_cycletab[op], 0);
2330734f 3456 emit_addimm(HOST_CCREG, ccadj[i], 1);
e3c6bdb5 3457 emit_far_call(call_gteStall);
3458 restore_regs(reglist);
3459#else
3460 host_tempreg_acquire();
3461 emit_readword(&psxRegs.gteBusyCycle, rtmp);
2330734f 3462 emit_addimm(rtmp, -ccadj[i], rtmp);
e3c6bdb5 3463 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3464 emit_cmpimm(HOST_TEMPREG, 44);
3465 emit_cmovb_reg(rtmp, HOST_CCREG);
3466 //emit_log_gte_stall(i, 0, reglist);
3467 host_tempreg_release();
3468#endif
3469 }
3470 else if (stall > 0) {
3471 //emit_log_gte_stall(i, stall, reglist);
3472 emit_addimm(HOST_CCREG, stall, HOST_CCREG);
3473 }
3474
3475 // save gteBusyCycle, if needed
3476 if (gte_cycletab[op] == 0)
3477 return;
3478 other_gte_op_cycles = -1;
3479 for (j = i + 1; j < slen; j++) {
3480 if (cop2_is_stalling_op(j, &other_gte_op_cycles))
3481 break;
fe807a8a 3482 if (dops[j].is_jump) {
e3c6bdb5 3483 // check ds
3484 if (j + 1 < slen && cop2_is_stalling_op(j + 1, &other_gte_op_cycles))
3485 j++;
3486 break;
3487 }
3488 }
3489 if (other_gte_op_cycles >= 0)
3490 // will handle stall when assembling that op
3491 return;
2330734f 3492 cycles_passed = ccadj[min(j, slen -1)] - ccadj[i];
e3c6bdb5 3493 if (cycles_passed >= 44)
3494 return;
3495 assem_debug("; save gteBusyCycle\n");
3496 host_tempreg_acquire();
3497#if 0
3498 emit_readword(&last_count, HOST_TEMPREG);
3499 emit_add(HOST_TEMPREG, HOST_CCREG, HOST_TEMPREG);
2330734f 3500 emit_addimm(HOST_TEMPREG, ccadj[i], HOST_TEMPREG);
e3c6bdb5 3501 emit_addimm(HOST_TEMPREG, gte_cycletab[op]), HOST_TEMPREG);
3502 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3503#else
2330734f 3504 emit_addimm(HOST_CCREG, ccadj[i] + gte_cycletab[op], HOST_TEMPREG);
e3c6bdb5 3505 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3506#endif
3507 host_tempreg_release();
81dbbf4c 3508}
3509
32631e6a 3510static int is_mflohi(int i)
3511{
cf95b4f0 3512 return (dops[i].itype == MOV && (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG));
32631e6a 3513}
3514
3515static int check_multdiv(int i, int *cycles)
3516{
cf95b4f0 3517 if (dops[i].itype != MULTDIV)
32631e6a 3518 return 0;
cf95b4f0 3519 if (dops[i].opcode2 == 0x18 || dops[i].opcode2 == 0x19) // MULT(U)
32631e6a 3520 *cycles = 11; // approx from 7 11 14
3521 else
3522 *cycles = 37;
3523 return 1;
3524}
3525
2330734f 3526static void multdiv_prepare_stall(int i, const struct regstat *i_regs, int ccadj_)
32631e6a 3527{
3528 int j, found = 0, c = 0;
3529 if (HACK_ENABLED(NDHACK_NO_STALLS))
3530 return;
3531 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3532 // happens occasionally... cc evicted? Don't bother then
3533 return;
3534 }
3535 for (j = i + 1; j < slen; j++) {
cf95b4f0 3536 if (dops[j].bt)
32631e6a 3537 break;
3538 if ((found = is_mflohi(j)))
3539 break;
fe807a8a 3540 if (dops[j].is_jump) {
32631e6a 3541 // check ds
3542 if (j + 1 < slen && (found = is_mflohi(j + 1)))
3543 j++;
3544 break;
3545 }
3546 }
3547 if (found)
3548 // handle all in multdiv_do_stall()
3549 return;
3550 check_multdiv(i, &c);
3551 assert(c > 0);
3552 assem_debug("; muldiv prepare stall %d\n", c);
3553 host_tempreg_acquire();
2330734f 3554 emit_addimm(HOST_CCREG, ccadj_ + c, HOST_TEMPREG);
32631e6a 3555 emit_writeword(HOST_TEMPREG, &psxRegs.muldivBusyCycle);
3556 host_tempreg_release();
3557}
3558
3559static void multdiv_do_stall(int i, const struct regstat *i_regs)
3560{
3561 int j, known_cycles = 0;
3562 u_int reglist = get_host_reglist(i_regs->regmap);
3563 int rtmp = get_reg(i_regs->regmap, -1);
3564 if (rtmp < 0)
3565 rtmp = reglist_find_free(reglist);
3566 if (HACK_ENABLED(NDHACK_NO_STALLS))
3567 return;
3568 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG || rtmp < 0) {
3569 // happens occasionally... cc evicted? Don't bother then
3570 //printf("no cc/rtmp %08x\n", start + i*4);
3571 return;
3572 }
cf95b4f0 3573 if (!dops[i].bt) {
32631e6a 3574 for (j = i - 1; j >= 0; j--) {
cf95b4f0 3575 if (dops[j].is_ds) break;
2330734f 3576 if (check_multdiv(j, &known_cycles))
32631e6a 3577 break;
3578 if (is_mflohi(j))
3579 // already handled by this op
3580 return;
2330734f 3581 if (dops[j].bt || (j > 0 && ccadj[j - 1] > ccadj[j]))
3582 break;
32631e6a 3583 }
3584 j = max(j, 0);
3585 }
3586 if (known_cycles > 0) {
2330734f 3587 known_cycles -= ccadj[i] - ccadj[j];
32631e6a 3588 assem_debug("; muldiv stall resolved %d\n", known_cycles);
3589 if (known_cycles > 0)
3590 emit_addimm(HOST_CCREG, known_cycles, HOST_CCREG);
3591 return;
3592 }
3593 assem_debug("; muldiv stall unresolved\n");
3594 host_tempreg_acquire();
3595 emit_readword(&psxRegs.muldivBusyCycle, rtmp);
2330734f 3596 emit_addimm(rtmp, -ccadj[i], rtmp);
32631e6a 3597 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3598 emit_cmpimm(HOST_TEMPREG, 37);
3599 emit_cmovb_reg(rtmp, HOST_CCREG);
3600 //emit_log_gte_stall(i, 0, reglist);
3601 host_tempreg_release();
3602}
3603
8062d65a 3604static void cop2_get_dreg(u_int copr,signed char tl,signed char temp)
3605{
3606 switch (copr) {
3607 case 1:
3608 case 3:
3609 case 5:
3610 case 8:
3611 case 9:
3612 case 10:
3613 case 11:
3614 emit_readword(&reg_cop2d[copr],tl);
3615 emit_signextend16(tl,tl);
3616 emit_writeword(tl,&reg_cop2d[copr]); // hmh
3617 break;
3618 case 7:
3619 case 16:
3620 case 17:
3621 case 18:
3622 case 19:
3623 emit_readword(&reg_cop2d[copr],tl);
3624 emit_andimm(tl,0xffff,tl);
3625 emit_writeword(tl,&reg_cop2d[copr]);
3626 break;
3627 case 15:
3628 emit_readword(&reg_cop2d[14],tl); // SXY2
3629 emit_writeword(tl,&reg_cop2d[copr]);
3630 break;
3631 case 28:
3632 case 29:
3968e69e 3633 c2op_mfc2_29_assemble(tl,temp);
8062d65a 3634 break;
3635 default:
3636 emit_readword(&reg_cop2d[copr],tl);
3637 break;
3638 }
3639}
3640
3641static void cop2_put_dreg(u_int copr,signed char sl,signed char temp)
3642{
3643 switch (copr) {
3644 case 15:
3645 emit_readword(&reg_cop2d[13],temp); // SXY1
3646 emit_writeword(sl,&reg_cop2d[copr]);
3647 emit_writeword(temp,&reg_cop2d[12]); // SXY0
3648 emit_readword(&reg_cop2d[14],temp); // SXY2
3649 emit_writeword(sl,&reg_cop2d[14]);
3650 emit_writeword(temp,&reg_cop2d[13]); // SXY1
3651 break;
3652 case 28:
3653 emit_andimm(sl,0x001f,temp);
3654 emit_shlimm(temp,7,temp);
3655 emit_writeword(temp,&reg_cop2d[9]);
3656 emit_andimm(sl,0x03e0,temp);
3657 emit_shlimm(temp,2,temp);
3658 emit_writeword(temp,&reg_cop2d[10]);
3659 emit_andimm(sl,0x7c00,temp);
3660 emit_shrimm(temp,3,temp);
3661 emit_writeword(temp,&reg_cop2d[11]);
3662 emit_writeword(sl,&reg_cop2d[28]);
3663 break;
3664 case 30:
3968e69e 3665 emit_xorsar_imm(sl,sl,31,temp);
be516ebe 3666#if defined(HAVE_ARMV5) || defined(__aarch64__)
8062d65a 3667 emit_clz(temp,temp);
3668#else
3669 emit_movs(temp,HOST_TEMPREG);
3670 emit_movimm(0,temp);
3671 emit_jeq((int)out+4*4);
3672 emit_addpl_imm(temp,1,temp);
3673 emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG);
3674 emit_jns((int)out-2*4);
3675#endif
3676 emit_writeword(sl,&reg_cop2d[30]);
3677 emit_writeword(temp,&reg_cop2d[31]);
3678 break;
3679 case 31:
3680 break;
3681 default:
3682 emit_writeword(sl,&reg_cop2d[copr]);
3683 break;
3684 }
3685}
3686
2330734f 3687static void c2ls_assemble(int i, const struct regstat *i_regs, int ccadj_)
b9b61529 3688{
3689 int s,tl;
3690 int ar;
3691 int offset;
1fd1aceb 3692 int memtarget=0,c=0;
b14b6a8f 3693 void *jaddr2=NULL;
3694 enum stub_type type;
b9b61529 3695 int agr=AGEN1+(i&1);
37387d8b 3696 int offset_reg = -1;
3697 int fastio_reg_override = -1;
81dbbf4c 3698 u_int reglist=get_host_reglist(i_regs->regmap);
b9b61529 3699 u_int copr=(source[i]>>16)&0x1f;
cf95b4f0 3700 s=get_reg(i_regs->regmap,dops[i].rs1);
b9b61529 3701 tl=get_reg(i_regs->regmap,FTEMP);
3702 offset=imm[i];
cf95b4f0 3703 assert(dops[i].rs1>0);
b9b61529 3704 assert(tl>=0);
b9b61529 3705
b9b61529 3706 if(i_regs->regmap[HOST_CCREG]==CCREG)
3707 reglist&=~(1<<HOST_CCREG);
3708
3709 // get the address
cf95b4f0 3710 if (dops[i].opcode==0x3a) { // SWC2
b9b61529 3711 ar=get_reg(i_regs->regmap,agr);
3712 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3713 reglist|=1<<ar;
3714 } else { // LWC2
3715 ar=tl;
3716 }
1fd1aceb 3717 if(s>=0) c=(i_regs->wasconst>>s)&1;
3718 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
b9b61529 3719 if (!offset&&!c&&s>=0) ar=s;
3720 assert(ar>=0);
3721
32631e6a 3722 cop2_do_stall_check(0, i, i_regs, reglist);
3723
cf95b4f0 3724 if (dops[i].opcode==0x3a) { // SWC2
3968e69e 3725 cop2_get_dreg(copr,tl,-1);
1fd1aceb 3726 type=STOREW_STUB;
b9b61529 3727 }
1fd1aceb 3728 else
b9b61529 3729 type=LOADW_STUB;
1fd1aceb 3730
3731 if(c&&!memtarget) {
b14b6a8f 3732 jaddr2=out;
1fd1aceb 3733 emit_jmp(0); // inline_readstub/inline_writestub?
b9b61529 3734 }
1fd1aceb 3735 else {
3736 if(!c) {
37387d8b 3737 jaddr2 = emit_fastpath_cmp_jump(i, i_regs, ar,
3738 &offset_reg, &fastio_reg_override);
3739 }
3740 else if (ram_offset && memtarget) {
3741 offset_reg = get_ro_reg(i_regs, 0);
3742 }
3743 switch (dops[i].opcode) {
3744 case 0x32: { // LWC2
3745 int a = ar;
3746 if (fastio_reg_override >= 0)
3747 a = fastio_reg_override;
3748 do_load_word(a, tl, offset_reg);
3749 break;
1fd1aceb 3750 }
37387d8b 3751 case 0x3a: { // SWC2
1fd1aceb 3752 #ifdef DESTRUCTIVE_SHIFT
3753 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3754 #endif
37387d8b 3755 int a = ar;
3756 if (fastio_reg_override >= 0)
3757 a = fastio_reg_override;
3758 do_store_word(a, 0, tl, offset_reg, 1);
3759 break;
3760 }
3761 default:
3762 assert(0);
1fd1aceb 3763 }
b9b61529 3764 }
37387d8b 3765 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
d1e4ebd9 3766 host_tempreg_release();
b9b61529 3767 if(jaddr2)
2330734f 3768 add_stub_r(type,jaddr2,out,i,ar,i_regs,ccadj_,reglist);
cf95b4f0 3769 if(dops[i].opcode==0x3a) // SWC2
3770 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
b9b61529 3771#if defined(HOST_IMM8)
3772 int ir=get_reg(i_regs->regmap,INVCP);
3773 assert(ir>=0);
3774 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3775#else
643aeae3 3776 emit_cmpmem_indexedsr12_imm(invalid_code,ar,1);
b9b61529 3777#endif
0bbd1454 3778 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3779 emit_callne(invalidate_addr_reg[ar]);
3780 #else
b14b6a8f 3781 void *jaddr3 = out;
b9b61529 3782 emit_jne(0);
b14b6a8f 3783 add_stub(INVCODE_STUB,jaddr3,out,reglist|(1<<HOST_CCREG),ar,0,0,0);
0bbd1454 3784 #endif
b9b61529 3785 }
cf95b4f0 3786 if (dops[i].opcode==0x32) { // LWC2
d1e4ebd9 3787 host_tempreg_acquire();
b9b61529 3788 cop2_put_dreg(copr,tl,HOST_TEMPREG);
d1e4ebd9 3789 host_tempreg_release();
b9b61529 3790 }
3791}
3792
81dbbf4c 3793static void cop2_assemble(int i, const struct regstat *i_regs)
8062d65a 3794{
81dbbf4c 3795 u_int copr = (source[i]>>11) & 0x1f;
3796 signed char temp = get_reg(i_regs->regmap, -1);
3797
32631e6a 3798 if (!HACK_ENABLED(NDHACK_NO_STALLS)) {
3799 u_int reglist = reglist_exclude(get_host_reglist(i_regs->regmap), temp, -1);
cf95b4f0 3800 if (dops[i].opcode2 == 0 || dops[i].opcode2 == 2) { // MFC2/CFC2
3801 signed char tl = get_reg(i_regs->regmap, dops[i].rt1);
32631e6a 3802 reglist = reglist_exclude(reglist, tl, -1);
81dbbf4c 3803 }
32631e6a 3804 cop2_do_stall_check(0, i, i_regs, reglist);
81dbbf4c 3805 }
cf95b4f0 3806 if (dops[i].opcode2==0) { // MFC2
3807 signed char tl=get_reg(i_regs->regmap,dops[i].rt1);
3808 if(tl>=0&&dops[i].rt1!=0)
8062d65a 3809 cop2_get_dreg(copr,tl,temp);
3810 }
cf95b4f0 3811 else if (dops[i].opcode2==4) { // MTC2
3812 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
8062d65a 3813 cop2_put_dreg(copr,sl,temp);
3814 }
cf95b4f0 3815 else if (dops[i].opcode2==2) // CFC2
8062d65a 3816 {
cf95b4f0 3817 signed char tl=get_reg(i_regs->regmap,dops[i].rt1);
3818 if(tl>=0&&dops[i].rt1!=0)
8062d65a 3819 emit_readword(&reg_cop2c[copr],tl);
3820 }
cf95b4f0 3821 else if (dops[i].opcode2==6) // CTC2
8062d65a 3822 {
cf95b4f0 3823 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
8062d65a 3824 switch(copr) {
3825 case 4:
3826 case 12:
3827 case 20:
3828 case 26:
3829 case 27:
3830 case 29:
3831 case 30:
3832 emit_signextend16(sl,temp);
3833 break;
3834 case 31:
3968e69e 3835 c2op_ctc2_31_assemble(sl,temp);
8062d65a 3836 break;
3837 default:
3838 temp=sl;
3839 break;
3840 }
3841 emit_writeword(temp,&reg_cop2c[copr]);
3842 assert(sl>=0);
3843 }
3844}
3845
3968e69e 3846static void do_unalignedwritestub(int n)
3847{
3848 assem_debug("do_unalignedwritestub %x\n",start+stubs[n].a*4);
3849 literal_pool(256);
3850 set_jump_target(stubs[n].addr, out);
3851
3852 int i=stubs[n].a;
3853 struct regstat *i_regs=(struct regstat *)stubs[n].c;
3854 int addr=stubs[n].b;
3855 u_int reglist=stubs[n].e;
3856 signed char *i_regmap=i_regs->regmap;
3857 int temp2=get_reg(i_regmap,FTEMP);
3858 int rt;
cf95b4f0 3859 rt=get_reg(i_regmap,dops[i].rs2);
3968e69e 3860 assert(rt>=0);
3861 assert(addr>=0);
cf95b4f0 3862 assert(dops[i].opcode==0x2a||dops[i].opcode==0x2e); // SWL/SWR only implemented
3968e69e 3863 reglist|=(1<<addr);
3864 reglist&=~(1<<temp2);
3865
3968e69e 3866 // don't bother with it and call write handler
3867 save_regs(reglist);
3868 pass_args(addr,rt);
3869 int cc=get_reg(i_regmap,CCREG);
3870 if(cc<0)
3871 emit_loadreg(CCREG,2);
2330734f 3872 emit_addimm(cc<0?2:cc,(int)stubs[n].d+1,2);
cf95b4f0 3873 emit_far_call((dops[i].opcode==0x2a?jump_handle_swl:jump_handle_swr));
2330734f 3874 emit_addimm(0,-((int)stubs[n].d+1),cc<0?2:cc);
3968e69e 3875 if(cc<0)
3876 emit_storereg(CCREG,2);
3877 restore_regs(reglist);
3878 emit_jmp(stubs[n].retaddr); // return address
3968e69e 3879}
3880
57871462 3881#ifndef multdiv_assemble
3882void multdiv_assemble(int i,struct regstat *i_regs)
3883{
3884 printf("Need multdiv_assemble for this architecture.\n");
7c3a5182 3885 abort();
57871462 3886}
3887#endif
3888
2330734f 3889static void mov_assemble(int i, const struct regstat *i_regs)
57871462 3890{
cf95b4f0 3891 //if(dops[i].opcode2==0x10||dops[i].opcode2==0x12) { // MFHI/MFLO
3892 //if(dops[i].opcode2==0x11||dops[i].opcode2==0x13) { // MTHI/MTLO
3893 if(dops[i].rt1) {
7c3a5182 3894 signed char sl,tl;
cf95b4f0 3895 tl=get_reg(i_regs->regmap,dops[i].rt1);
57871462 3896 //assert(tl>=0);
3897 if(tl>=0) {
cf95b4f0 3898 sl=get_reg(i_regs->regmap,dops[i].rs1);
57871462 3899 if(sl>=0) emit_mov(sl,tl);
cf95b4f0 3900 else emit_loadreg(dops[i].rs1,tl);
57871462 3901 }
3902 }
cf95b4f0 3903 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) // MFHI/MFLO
32631e6a 3904 multdiv_do_stall(i, i_regs);
57871462 3905}
3906
3968e69e 3907// call interpreter, exception handler, things that change pc/regs/cycles ...
2330734f 3908static void call_c_cpu_handler(int i, const struct regstat *i_regs, int ccadj_, u_int pc, void *func)
57871462 3909{
3910 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3911 assert(ccreg==HOST_CCREG);
3912 assert(!is_delayslot);
581335b0 3913 (void)ccreg;
3968e69e 3914
3915 emit_movimm(pc,3); // Get PC
3916 emit_readword(&last_count,2);
3917 emit_writeword(3,&psxRegs.pc);
2330734f 3918 emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG);
3968e69e 3919 emit_add(2,HOST_CCREG,2);
3920 emit_writeword(2,&psxRegs.cycle);
2a014d73 3921 emit_far_call(func);
3922 emit_far_jump(jump_to_new_pc);
3968e69e 3923}
3924
2330734f 3925static void syscall_assemble(int i, const struct regstat *i_regs, int ccadj_)
3968e69e 3926{
3927 emit_movimm(0x20,0); // cause code
3928 emit_movimm(0,1); // not in delay slot
2330734f 3929 call_c_cpu_handler(i, i_regs, ccadj_, start+i*4, psxException);
7139f3c8 3930}
3931
2330734f 3932static void hlecall_assemble(int i, const struct regstat *i_regs, int ccadj_)
7139f3c8 3933{
3968e69e 3934 void *hlefunc = psxNULL;
dd79da89 3935 uint32_t hleCode = source[i] & 0x03ffffff;
3968e69e 3936 if (hleCode < ARRAY_SIZE(psxHLEt))
3937 hlefunc = psxHLEt[hleCode];
3938
2330734f 3939 call_c_cpu_handler(i, i_regs, ccadj_, start + i*4+4, hlefunc);
57871462 3940}
3941
2330734f 3942static void intcall_assemble(int i, const struct regstat *i_regs, int ccadj_)
1e973cb0 3943{
2330734f 3944 call_c_cpu_handler(i, i_regs, ccadj_, start + i*4, execI);
1e973cb0 3945}
3946
8062d65a 3947static void speculate_mov(int rs,int rt)
3948{
3949 if(rt!=0) {
3950 smrv_strong_next|=1<<rt;
3951 smrv[rt]=smrv[rs];
3952 }
3953}
3954
3955static void speculate_mov_weak(int rs,int rt)
3956{
3957 if(rt!=0) {
3958 smrv_weak_next|=1<<rt;
3959 smrv[rt]=smrv[rs];
3960 }
3961}
3962
3963static void speculate_register_values(int i)
3964{
3965 if(i==0) {
3966 memcpy(smrv,psxRegs.GPR.r,sizeof(smrv));
3967 // gp,sp are likely to stay the same throughout the block
3968 smrv_strong_next=(1<<28)|(1<<29)|(1<<30);
3969 smrv_weak_next=~smrv_strong_next;
3970 //printf(" llr %08x\n", smrv[4]);
3971 }
3972 smrv_strong=smrv_strong_next;
3973 smrv_weak=smrv_weak_next;
cf95b4f0 3974 switch(dops[i].itype) {
8062d65a 3975 case ALU:
cf95b4f0 3976 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
3977 else if((smrv_strong>>dops[i].rs2)&1) speculate_mov(dops[i].rs2,dops[i].rt1);
3978 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
3979 else if((smrv_weak>>dops[i].rs2)&1) speculate_mov_weak(dops[i].rs2,dops[i].rt1);
8062d65a 3980 else {
cf95b4f0 3981 smrv_strong_next&=~(1<<dops[i].rt1);
3982 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 3983 }
3984 break;
3985 case SHIFTIMM:
cf95b4f0 3986 smrv_strong_next&=~(1<<dops[i].rt1);
3987 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 3988 // fallthrough
3989 case IMM16:
cf95b4f0 3990 if(dops[i].rt1&&is_const(&regs[i],dops[i].rt1)) {
3991 int value,hr=get_reg(regs[i].regmap,dops[i].rt1);
8062d65a 3992 if(hr>=0) {
3993 if(get_final_value(hr,i,&value))
cf95b4f0 3994 smrv[dops[i].rt1]=value;
3995 else smrv[dops[i].rt1]=constmap[i][hr];
3996 smrv_strong_next|=1<<dops[i].rt1;
8062d65a 3997 }
3998 }
3999 else {
cf95b4f0 4000 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
4001 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
8062d65a 4002 }
4003 break;
4004 case LOAD:
cf95b4f0 4005 if(start<0x2000&&(dops[i].rt1==26||(smrv[dops[i].rt1]>>24)==0xa0)) {
8062d65a 4006 // special case for BIOS
cf95b4f0 4007 smrv[dops[i].rt1]=0xa0000000;
4008 smrv_strong_next|=1<<dops[i].rt1;
8062d65a 4009 break;
4010 }
4011 // fallthrough
4012 case SHIFT:
4013 case LOADLR:
4014 case MOV:
cf95b4f0 4015 smrv_strong_next&=~(1<<dops[i].rt1);
4016 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4017 break;
4018 case COP0:
4019 case COP2:
cf95b4f0 4020 if(dops[i].opcode2==0||dops[i].opcode2==2) { // MFC/CFC
4021 smrv_strong_next&=~(1<<dops[i].rt1);
4022 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4023 }
4024 break;
4025 case C2LS:
cf95b4f0 4026 if (dops[i].opcode==0x32) { // LWC2
4027 smrv_strong_next&=~(1<<dops[i].rt1);
4028 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4029 }
4030 break;
4031 }
4032#if 0
4033 int r=4;
4034 printf("x %08x %08x %d %d c %08x %08x\n",smrv[r],start+i*4,
4035 ((smrv_strong>>r)&1),(smrv_weak>>r)&1,regs[i].isconst,regs[i].wasconst);
4036#endif
4037}
4038
2330734f 4039static void ujump_assemble(int i, const struct regstat *i_regs);
4040static void rjump_assemble(int i, const struct regstat *i_regs);
4041static void cjump_assemble(int i, const struct regstat *i_regs);
4042static void sjump_assemble(int i, const struct regstat *i_regs);
4043static void pagespan_assemble(int i, const struct regstat *i_regs);
4044
4045static int assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 4046{
2330734f 4047 int ds = 0;
4048 switch (dops[i].itype) {
57871462 4049 case ALU:
2330734f 4050 alu_assemble(i, i_regs);
4051 break;
57871462 4052 case IMM16:
2330734f 4053 imm16_assemble(i, i_regs);
4054 break;
57871462 4055 case SHIFT:
2330734f 4056 shift_assemble(i, i_regs);
4057 break;
57871462 4058 case SHIFTIMM:
2330734f 4059 shiftimm_assemble(i, i_regs);
4060 break;
57871462 4061 case LOAD:
2330734f 4062 load_assemble(i, i_regs, ccadj_);
4063 break;
57871462 4064 case LOADLR:
2330734f 4065 loadlr_assemble(i, i_regs, ccadj_);
4066 break;
57871462 4067 case STORE:
2330734f 4068 store_assemble(i, i_regs, ccadj_);
4069 break;
57871462 4070 case STORELR:
2330734f 4071 storelr_assemble(i, i_regs, ccadj_);
4072 break;
57871462 4073 case COP0:
2330734f 4074 cop0_assemble(i, i_regs, ccadj_);
4075 break;
57871462 4076 case COP1:
2330734f 4077 cop1_assemble(i, i_regs);
4078 break;
57871462 4079 case C1LS:
2330734f 4080 c1ls_assemble(i, i_regs);
4081 break;
b9b61529 4082 case COP2:
2330734f 4083 cop2_assemble(i, i_regs);
4084 break;
b9b61529 4085 case C2LS:
2330734f 4086 c2ls_assemble(i, i_regs, ccadj_);
4087 break;
b9b61529 4088 case C2OP:
2330734f 4089 c2op_assemble(i, i_regs);
4090 break;
57871462 4091 case MULTDIV:
2330734f 4092 multdiv_assemble(i, i_regs);
4093 multdiv_prepare_stall(i, i_regs, ccadj_);
32631e6a 4094 break;
57871462 4095 case MOV:
2330734f 4096 mov_assemble(i, i_regs);
4097 break;
4098 case SYSCALL:
4099 syscall_assemble(i, i_regs, ccadj_);
4100 break;
4101 case HLECALL:
4102 hlecall_assemble(i, i_regs, ccadj_);
4103 break;
4104 case INTCALL:
4105 intcall_assemble(i, i_regs, ccadj_);
4106 break;
4107 case UJUMP:
4108 ujump_assemble(i, i_regs);
4109 ds = 1;
4110 break;
4111 case RJUMP:
4112 rjump_assemble(i, i_regs);
4113 ds = 1;
4114 break;
4115 case CJUMP:
4116 cjump_assemble(i, i_regs);
4117 ds = 1;
4118 break;
4119 case SJUMP:
4120 sjump_assemble(i, i_regs);
4121 ds = 1;
4122 break;
4123 case SPAN:
4124 pagespan_assemble(i, i_regs);
4125 break;
4126 case OTHER:
4127 case NI:
4128 // not handled, just skip
4129 break;
4130 default:
4131 assert(0);
4132 }
4133 return ds;
4134}
4135
4136static void ds_assemble(int i, const struct regstat *i_regs)
4137{
4138 speculate_register_values(i);
4139 is_delayslot = 1;
4140 switch (dops[i].itype) {
57871462 4141 case SYSCALL:
7139f3c8 4142 case HLECALL:
1e973cb0 4143 case INTCALL:
57871462 4144 case SPAN:
4145 case UJUMP:
4146 case RJUMP:
4147 case CJUMP:
4148 case SJUMP:
c43b5311 4149 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
2330734f 4150 break;
4151 default:
4152 assemble(i, i_regs, ccadj[i]);
57871462 4153 }
2330734f 4154 is_delayslot = 0;
57871462 4155}
4156
4157// Is the branch target a valid internal jump?
ad49de89 4158static int internal_branch(int addr)
57871462 4159{
4160 if(addr&1) return 0; // Indirect (register) jump
4161 if(addr>=start && addr<start+slen*4-4)
4162 {
71e490c5 4163 return 1;
57871462 4164 }
4165 return 0;
4166}
4167
ad49de89 4168static void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t u)
57871462 4169{
4170 int hr;
4171 for(hr=0;hr<HOST_REGS;hr++) {
4172 if(hr!=EXCLUDE_REG) {
4173 if(pre[hr]!=entry[hr]) {
4174 if(pre[hr]>=0) {
4175 if((dirty>>hr)&1) {
4176 if(get_reg(entry,pre[hr])<0) {
00fa9369 4177 assert(pre[hr]<64);
4178 if(!((u>>pre[hr])&1))
4179 emit_storereg(pre[hr],hr);
57871462 4180 }
4181 }
4182 }
4183 }
4184 }
4185 }
4186 // Move from one register to another (no writeback)
4187 for(hr=0;hr<HOST_REGS;hr++) {
4188 if(hr!=EXCLUDE_REG) {
4189 if(pre[hr]!=entry[hr]) {
4190 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
4191 int nr;
4192 if((nr=get_reg(entry,pre[hr]))>=0) {
4193 emit_mov(hr,nr);
4194 }
4195 }
4196 }
4197 }
4198 }
4199}
57871462 4200
4201// Load the specified registers
4202// This only loads the registers given as arguments because
4203// we don't want to load things that will be overwritten
ad49de89 4204static void load_regs(signed char entry[],signed char regmap[],int rs1,int rs2)
57871462 4205{
4206 int hr;
4207 // Load 32-bit regs
4208 for(hr=0;hr<HOST_REGS;hr++) {
4209 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4210 if(entry[hr]!=regmap[hr]) {
4211 if(regmap[hr]==rs1||regmap[hr]==rs2)
4212 {
4213 if(regmap[hr]==0) {
4214 emit_zeroreg(hr);
4215 }
4216 else
4217 {
4218 emit_loadreg(regmap[hr],hr);
4219 }
4220 }
4221 }
4222 }
4223 }
57871462 4224}
4225
4226// Load registers prior to the start of a loop
4227// so that they are not loaded within the loop
4228static void loop_preload(signed char pre[],signed char entry[])
4229{
4230 int hr;
4231 for(hr=0;hr<HOST_REGS;hr++) {
4232 if(hr!=EXCLUDE_REG) {
4233 if(pre[hr]!=entry[hr]) {
4234 if(entry[hr]>=0) {
4235 if(get_reg(pre,entry[hr])<0) {
4236 assem_debug("loop preload:\n");
4237 //printf("loop preload: %d\n",hr);
4238 if(entry[hr]==0) {
4239 emit_zeroreg(hr);
4240 }
4241 else if(entry[hr]<TEMPREG)
4242 {
4243 emit_loadreg(entry[hr],hr);
4244 }
4245 else if(entry[hr]-64<TEMPREG)
4246 {
4247 emit_loadreg(entry[hr],hr);
4248 }
4249 }
4250 }
4251 }
4252 }
4253 }
4254}
4255
4256// Generate address for load/store instruction
b9b61529 4257// goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
2330734f 4258void address_generation(int i, const struct regstat *i_regs, signed char entry[])
57871462 4259{
37387d8b 4260 if (dops[i].is_load || dops[i].is_store) {
5194fb95 4261 int ra=-1;
57871462 4262 int agr=AGEN1+(i&1);
cf95b4f0 4263 if(dops[i].itype==LOAD) {
4264 ra=get_reg(i_regs->regmap,dops[i].rt1);
9f51b4b9 4265 if(ra<0) ra=get_reg(i_regs->regmap,-1);
535d208a 4266 assert(ra>=0);
57871462 4267 }
cf95b4f0 4268 if(dops[i].itype==LOADLR) {
57871462 4269 ra=get_reg(i_regs->regmap,FTEMP);
4270 }
cf95b4f0 4271 if(dops[i].itype==STORE||dops[i].itype==STORELR) {
57871462 4272 ra=get_reg(i_regs->regmap,agr);
4273 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4274 }
37387d8b 4275 if(dops[i].itype==C2LS) {
cf95b4f0 4276 if ((dops[i].opcode&0x3b)==0x31||(dops[i].opcode&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
57871462 4277 ra=get_reg(i_regs->regmap,FTEMP);
1fd1aceb 4278 else { // SWC1/SDC1/SWC2/SDC2
57871462 4279 ra=get_reg(i_regs->regmap,agr);
4280 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4281 }
4282 }
cf95b4f0 4283 int rs=get_reg(i_regs->regmap,dops[i].rs1);
57871462 4284 if(ra>=0) {
4285 int offset=imm[i];
4286 int c=(i_regs->wasconst>>rs)&1;
cf95b4f0 4287 if(dops[i].rs1==0) {
57871462 4288 // Using r0 as a base address
57871462 4289 if(!entry||entry[ra]!=agr) {
cf95b4f0 4290 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
57871462 4291 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
cf95b4f0 4292 }else if (dops[i].opcode==0x1a||dops[i].opcode==0x1b) {
57871462 4293 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4294 }else{
4295 emit_movimm(offset,ra);
4296 }
4297 } // else did it in the previous cycle
4298 }
4299 else if(rs<0) {
cf95b4f0 4300 if(!entry||entry[ra]!=dops[i].rs1)
4301 emit_loadreg(dops[i].rs1,ra);
4302 //if(!entry||entry[ra]!=dops[i].rs1)
57871462 4303 // printf("poor load scheduling!\n");
4304 }
4305 else if(c) {
cf95b4f0 4306 if(dops[i].rs1!=dops[i].rt1||dops[i].itype!=LOAD) {
57871462 4307 if(!entry||entry[ra]!=agr) {
cf95b4f0 4308 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
57871462 4309 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
cf95b4f0 4310 }else if (dops[i].opcode==0x1a||dops[i].opcode==0x1b) {
57871462 4311 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4312 }else{
57871462 4313 emit_movimm(constmap[i][rs]+offset,ra);
8575a877 4314 regs[i].loadedconst|=1<<ra;
57871462 4315 }
4316 } // else did it in the previous cycle
4317 } // else load_consts already did it
4318 }
cf95b4f0 4319 if(offset&&!c&&dops[i].rs1) {
57871462 4320 if(rs>=0) {
4321 emit_addimm(rs,offset,ra);
4322 }else{
4323 emit_addimm(ra,offset,ra);
4324 }
4325 }
4326 }
4327 }
4328 // Preload constants for next instruction
37387d8b 4329 if (dops[i+1].is_load || dops[i+1].is_store) {
57871462 4330 int agr,ra;
57871462 4331 // Actual address
4332 agr=AGEN1+((i+1)&1);
4333 ra=get_reg(i_regs->regmap,agr);
4334 if(ra>=0) {
cf95b4f0 4335 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
57871462 4336 int offset=imm[i+1];
4337 int c=(regs[i+1].wasconst>>rs)&1;
cf95b4f0 4338 if(c&&(dops[i+1].rs1!=dops[i+1].rt1||dops[i+1].itype!=LOAD)) {
4339 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
57871462 4340 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
cf95b4f0 4341 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
57871462 4342 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4343 }else{
57871462 4344 emit_movimm(constmap[i+1][rs]+offset,ra);
8575a877 4345 regs[i+1].loadedconst|=1<<ra;
57871462 4346 }
4347 }
cf95b4f0 4348 else if(dops[i+1].rs1==0) {
57871462 4349 // Using r0 as a base address
cf95b4f0 4350 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
57871462 4351 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
cf95b4f0 4352 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
57871462 4353 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4354 }else{
4355 emit_movimm(offset,ra);
4356 }
4357 }
4358 }
4359 }
4360}
4361
e2b5e7aa 4362static int get_final_value(int hr, int i, int *value)
57871462 4363{
4364 int reg=regs[i].regmap[hr];
4365 while(i<slen-1) {
4366 if(regs[i+1].regmap[hr]!=reg) break;
4367 if(!((regs[i+1].isconst>>hr)&1)) break;
cf95b4f0 4368 if(dops[i+1].bt) break;
57871462 4369 i++;
4370 }
4371 if(i<slen-1) {
fe807a8a 4372 if (dops[i].is_jump) {
57871462 4373 *value=constmap[i][hr];
4374 return 1;
4375 }
cf95b4f0 4376 if(!dops[i+1].bt) {
fe807a8a 4377 if (dops[i+1].is_jump) {
57871462 4378 // Load in delay slot, out-of-order execution
cf95b4f0 4379 if(dops[i+2].itype==LOAD&&dops[i+2].rs1==reg&&dops[i+2].rt1==reg&&((regs[i+1].wasconst>>hr)&1))
57871462 4380 {
57871462 4381 // Precompute load address
4382 *value=constmap[i][hr]+imm[i+2];
4383 return 1;
4384 }
4385 }
cf95b4f0 4386 if(dops[i+1].itype==LOAD&&dops[i+1].rs1==reg&&dops[i+1].rt1==reg)
57871462 4387 {
57871462 4388 // Precompute load address
4389 *value=constmap[i][hr]+imm[i+1];
643aeae3 4390 //printf("c=%x imm=%lx\n",(long)constmap[i][hr],imm[i+1]);
57871462 4391 return 1;
4392 }
4393 }
4394 }
4395 *value=constmap[i][hr];
643aeae3 4396 //printf("c=%lx\n",(long)constmap[i][hr]);
57871462 4397 if(i==slen-1) return 1;
00fa9369 4398 assert(reg < 64);
4399 return !((unneeded_reg[i+1]>>reg)&1);
57871462 4400}
4401
4402// Load registers with known constants
ad49de89 4403static void load_consts(signed char pre[],signed char regmap[],int i)
57871462 4404{
8575a877 4405 int hr,hr2;
4406 // propagate loaded constant flags
cf95b4f0 4407 if(i==0||dops[i].bt)
8575a877 4408 regs[i].loadedconst=0;
4409 else {
4410 for(hr=0;hr<HOST_REGS;hr++) {
4411 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((regs[i-1].isconst>>hr)&1)&&pre[hr]==regmap[hr]
4412 &&regmap[hr]==regs[i-1].regmap[hr]&&((regs[i-1].loadedconst>>hr)&1))
4413 {
4414 regs[i].loadedconst|=1<<hr;
4415 }
4416 }
4417 }
57871462 4418 // Load 32-bit regs
4419 for(hr=0;hr<HOST_REGS;hr++) {
4420 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4421 //if(entry[hr]!=regmap[hr]) {
8575a877 4422 if(!((regs[i].loadedconst>>hr)&1)) {
ad49de89 4423 assert(regmap[hr]<64);
4424 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>0) {
8575a877 4425 int value,similar=0;
57871462 4426 if(get_final_value(hr,i,&value)) {
8575a877 4427 // see if some other register has similar value
4428 for(hr2=0;hr2<HOST_REGS;hr2++) {
4429 if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
4430 if(is_similar_value(value,constmap[i][hr2])) {
4431 similar=1;
4432 break;
4433 }
4434 }
4435 }
4436 if(similar) {
4437 int value2;
4438 if(get_final_value(hr2,i,&value2)) // is this needed?
4439 emit_movimm_from(value2,hr2,value,hr);
4440 else
4441 emit_movimm(value,hr);
4442 }
4443 else if(value==0) {
57871462 4444 emit_zeroreg(hr);
4445 }
4446 else {
4447 emit_movimm(value,hr);
4448 }
4449 }
8575a877 4450 regs[i].loadedconst|=1<<hr;
57871462 4451 }
4452 }
4453 }
4454 }
57871462 4455}
ad49de89 4456
2330734f 4457static void load_all_consts(const signed char regmap[], u_int dirty, int i)
57871462 4458{
4459 int hr;
4460 // Load 32-bit regs
4461 for(hr=0;hr<HOST_REGS;hr++) {
4462 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
ad49de89 4463 assert(regmap[hr] < 64);
4464 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>0) {
57871462 4465 int value=constmap[i][hr];
4466 if(value==0) {
4467 emit_zeroreg(hr);
4468 }
4469 else {
4470 emit_movimm(value,hr);
4471 }
4472 }
4473 }
4474 }
57871462 4475}
4476
4477// Write out all dirty registers (except cycle count)
2330734f 4478static void wb_dirtys(const signed char i_regmap[], uint64_t i_dirty)
57871462 4479{
4480 int hr;
4481 for(hr=0;hr<HOST_REGS;hr++) {
4482 if(hr!=EXCLUDE_REG) {
4483 if(i_regmap[hr]>0) {
4484 if(i_regmap[hr]!=CCREG) {
4485 if((i_dirty>>hr)&1) {
00fa9369 4486 assert(i_regmap[hr]<64);
4487 emit_storereg(i_regmap[hr],hr);
57871462 4488 }
4489 }
4490 }
4491 }
4492 }
4493}
ad49de89 4494
57871462 4495// Write out dirty registers that we need to reload (pair with load_needed_regs)
4496// This writes the registers not written by store_regs_bt
2330734f 4497static void wb_needed_dirtys(const signed char i_regmap[], uint64_t i_dirty, int addr)
57871462 4498{
4499 int hr;
4500 int t=(addr-start)>>2;
4501 for(hr=0;hr<HOST_REGS;hr++) {
4502 if(hr!=EXCLUDE_REG) {
4503 if(i_regmap[hr]>0) {
4504 if(i_regmap[hr]!=CCREG) {
ad49de89 4505 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1)) {
57871462 4506 if((i_dirty>>hr)&1) {
00fa9369 4507 assert(i_regmap[hr]<64);
4508 emit_storereg(i_regmap[hr],hr);
57871462 4509 }
4510 }
4511 }
4512 }
4513 }
4514 }
4515}
4516
4517// Load all registers (except cycle count)
2330734f 4518static void load_all_regs(const signed char i_regmap[])
57871462 4519{
4520 int hr;
4521 for(hr=0;hr<HOST_REGS;hr++) {
4522 if(hr!=EXCLUDE_REG) {
4523 if(i_regmap[hr]==0) {
4524 emit_zeroreg(hr);
4525 }
4526 else
ea3d2e6e 4527 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
57871462 4528 {
4529 emit_loadreg(i_regmap[hr],hr);
4530 }
4531 }
4532 }
4533}
4534
4535// Load all current registers also needed by next instruction
2330734f 4536static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[])
57871462 4537{
4538 int hr;
4539 for(hr=0;hr<HOST_REGS;hr++) {
4540 if(hr!=EXCLUDE_REG) {
4541 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4542 if(i_regmap[hr]==0) {
4543 emit_zeroreg(hr);
4544 }
4545 else
ea3d2e6e 4546 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
57871462 4547 {
4548 emit_loadreg(i_regmap[hr],hr);
4549 }
4550 }
4551 }
4552 }
4553}
4554
4555// Load all regs, storing cycle count if necessary
2330734f 4556static void load_regs_entry(int t)
57871462 4557{
4558 int hr;
cf95b4f0 4559 if(dops[t].is_ds) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
2330734f 4560 else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t],HOST_CCREG);
57871462 4561 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4562 emit_storereg(CCREG,HOST_CCREG);
4563 }
4564 // Load 32-bit regs
4565 for(hr=0;hr<HOST_REGS;hr++) {
ea3d2e6e 4566 if(regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
57871462 4567 if(regs[t].regmap_entry[hr]==0) {
4568 emit_zeroreg(hr);
4569 }
4570 else if(regs[t].regmap_entry[hr]!=CCREG)
4571 {
4572 emit_loadreg(regs[t].regmap_entry[hr],hr);
4573 }
4574 }
4575 }
57871462 4576}
4577
4578// Store dirty registers prior to branch
ad49de89 4579void store_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
57871462 4580{
ad49de89 4581 if(internal_branch(addr))
57871462 4582 {
4583 int t=(addr-start)>>2;
4584 int hr;
4585 for(hr=0;hr<HOST_REGS;hr++) {
4586 if(hr!=EXCLUDE_REG) {
4587 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
ad49de89 4588 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1)) {
57871462 4589 if((i_dirty>>hr)&1) {
00fa9369 4590 assert(i_regmap[hr]<64);
4591 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4592 emit_storereg(i_regmap[hr],hr);
57871462 4593 }
4594 }
4595 }
4596 }
4597 }
4598 }
4599 else
4600 {
4601 // Branch out of this block, write out all dirty regs
ad49de89 4602 wb_dirtys(i_regmap,i_dirty);
57871462 4603 }
4604}
4605
4606// Load all needed registers for branch target
ad49de89 4607static void load_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
57871462 4608{
4609 //if(addr>=start && addr<(start+slen*4))
ad49de89 4610 if(internal_branch(addr))
57871462 4611 {
4612 int t=(addr-start)>>2;
4613 int hr;
4614 // Store the cycle count before loading something else
4615 if(i_regmap[HOST_CCREG]!=CCREG) {
4616 assert(i_regmap[HOST_CCREG]==-1);
4617 }
4618 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4619 emit_storereg(CCREG,HOST_CCREG);
4620 }
4621 // Load 32-bit regs
4622 for(hr=0;hr<HOST_REGS;hr++) {
ea3d2e6e 4623 if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
00fa9369 4624 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
57871462 4625 if(regs[t].regmap_entry[hr]==0) {
4626 emit_zeroreg(hr);
4627 }
4628 else if(regs[t].regmap_entry[hr]!=CCREG)
4629 {
4630 emit_loadreg(regs[t].regmap_entry[hr],hr);
4631 }
4632 }
4633 }
4634 }
57871462 4635 }
4636}
4637
ad49de89 4638static int match_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
57871462 4639{
4640 if(addr>=start && addr<start+slen*4-4)
4641 {
4642 int t=(addr-start)>>2;
4643 int hr;
4644 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4645 for(hr=0;hr<HOST_REGS;hr++)
4646 {
4647 if(hr!=EXCLUDE_REG)
4648 {
4649 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4650 {
ea3d2e6e 4651 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
57871462 4652 {
4653 return 0;
4654 }
9f51b4b9 4655 else
57871462 4656 if((i_dirty>>hr)&1)
4657 {
ea3d2e6e 4658 if(i_regmap[hr]<TEMPREG)
57871462 4659 {
4660 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4661 return 0;
4662 }
ea3d2e6e 4663 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
57871462 4664 {
00fa9369 4665 assert(0);
57871462 4666 }
4667 }
4668 }
4669 else // Same register but is it 32-bit or dirty?
4670 if(i_regmap[hr]>=0)
4671 {
4672 if(!((regs[t].dirty>>hr)&1))
4673 {
4674 if((i_dirty>>hr)&1)
4675 {
4676 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4677 {
4678 //printf("%x: dirty no match\n",addr);
4679 return 0;
4680 }
4681 }
4682 }
57871462 4683 }
4684 }
4685 }
57871462 4686 // Delay slots are not valid branch targets
fe807a8a 4687 //if(t>0&&(dops[t-1].is_jump) return 0;
57871462 4688 // Delay slots require additional processing, so do not match
cf95b4f0 4689 if(dops[t].is_ds) return 0;
57871462 4690 }
4691 else
4692 {
4693 int hr;
4694 for(hr=0;hr<HOST_REGS;hr++)
4695 {
4696 if(hr!=EXCLUDE_REG)
4697 {
4698 if(i_regmap[hr]>=0)
4699 {
4700 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4701 {
4702 if((i_dirty>>hr)&1)
4703 {
4704 return 0;
4705 }
4706 }
4707 }
4708 }
4709 }
4710 }
4711 return 1;
4712}
4713
dd114d7d 4714#ifdef DRC_DBG
2330734f 4715static void drc_dbg_emit_do_cmp(int i, int ccadj_)
dd114d7d 4716{
4717 extern void do_insn_cmp();
3968e69e 4718 //extern int cycle;
81dbbf4c 4719 u_int hr, reglist = get_host_reglist(regs[i].regmap);
dd114d7d 4720
40fca85b 4721 assem_debug("//do_insn_cmp %08x\n", start+i*4);
dd114d7d 4722 save_regs(reglist);
40fca85b 4723 // write out changed consts to match the interpreter
cf95b4f0 4724 if (i > 0 && !dops[i].bt) {
40fca85b 4725 for (hr = 0; hr < HOST_REGS; hr++) {
2330734f 4726 int reg = regs[i].regmap_entry[hr]; // regs[i-1].regmap[hr];
40fca85b 4727 if (hr == EXCLUDE_REG || reg < 0)
4728 continue;
4729 if (!((regs[i-1].isconst >> hr) & 1))
4730 continue;
4731 if (i > 1 && reg == regs[i-2].regmap[hr] && constmap[i-1][hr] == constmap[i-2][hr])
4732 continue;
4733 emit_movimm(constmap[i-1][hr],0);
4734 emit_storereg(reg, 0);
4735 }
4736 }
dd114d7d 4737 emit_movimm(start+i*4,0);
643aeae3 4738 emit_writeword(0,&pcaddr);
2330734f 4739 int cc = get_reg(regs[i].regmap_entry, CCREG);
4740 if (cc < 0)
4741 emit_loadreg(CCREG, cc = 0);
4742 emit_addimm(cc, ccadj_, 0);
4743 emit_writeword(0, &psxRegs.cycle);
2a014d73 4744 emit_far_call(do_insn_cmp);
643aeae3 4745 //emit_readword(&cycle,0);
dd114d7d 4746 //emit_addimm(0,2,0);
643aeae3 4747 //emit_writeword(0,&cycle);
3968e69e 4748 (void)get_reg2;
dd114d7d 4749 restore_regs(reglist);
40fca85b 4750 assem_debug("\\\\do_insn_cmp\n");
dd114d7d 4751}
4752#else
2330734f 4753#define drc_dbg_emit_do_cmp(x,y)
dd114d7d 4754#endif
4755
57871462 4756// Used when a branch jumps into the delay slot of another branch
7c3a5182 4757static void ds_assemble_entry(int i)
57871462 4758{
2330734f 4759 int t = (ba[i] - start) >> 2;
4760 int ccadj_ = -CLOCK_ADJUST(1);
df4dc2b1 4761 if (!instr_addr[t])
4762 instr_addr[t] = out;
57871462 4763 assem_debug("Assemble delay slot at %x\n",ba[i]);
4764 assem_debug("<->\n");
2330734f 4765 drc_dbg_emit_do_cmp(t, ccadj_);
57871462 4766 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
ad49de89 4767 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty);
cf95b4f0 4768 load_regs(regs[t].regmap_entry,regs[t].regmap,dops[t].rs1,dops[t].rs2);
57871462 4769 address_generation(t,&regs[t],regs[t].regmap_entry);
37387d8b 4770 if (ram_offset && (dops[t].is_load || dops[t].is_store))
4771 load_regs(regs[t].regmap_entry,regs[t].regmap,ROREG,ROREG);
4772 if (dops[t].is_store)
ad49de89 4773 load_regs(regs[t].regmap_entry,regs[t].regmap,INVCP,INVCP);
57871462 4774 is_delayslot=0;
2330734f 4775 switch (dops[t].itype) {
57871462 4776 case SYSCALL:
7139f3c8 4777 case HLECALL:
1e973cb0 4778 case INTCALL:
57871462 4779 case SPAN:
4780 case UJUMP:
4781 case RJUMP:
4782 case CJUMP:
4783 case SJUMP:
c43b5311 4784 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
2330734f 4785 break;
4786 default:
4787 assemble(t, &regs[t], ccadj_);
57871462 4788 }
ad49de89 4789 store_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4);
4790 load_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4);
4791 if(internal_branch(ba[i]+4))
57871462 4792 assem_debug("branch: internal\n");
4793 else
4794 assem_debug("branch: external\n");
ad49de89 4795 assert(internal_branch(ba[i]+4));
4796 add_to_linker(out,ba[i]+4,internal_branch(ba[i]+4));
57871462 4797 emit_jmp(0);
4798}
4799
7c3a5182 4800static void emit_extjump(void *addr, u_int target)
4801{
4802 emit_extjump2(addr, target, dyna_linker);
4803}
4804
4805static void emit_extjump_ds(void *addr, u_int target)
4806{
4807 emit_extjump2(addr, target, dyna_linker_ds);
4808}
4809
d1e4ebd9 4810// Load 2 immediates optimizing for small code size
4811static void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
4812{
4813 emit_movimm(imm1,rt1);
4814 emit_movimm_from(imm1,rt1,imm2,rt2);
4815}
4816
2330734f 4817static void do_cc(int i, const signed char i_regmap[], int *adj,
4818 int addr, int taken, int invert)
57871462 4819{
2330734f 4820 int count, count_plus2;
b14b6a8f 4821 void *jaddr;
4822 void *idle=NULL;
b6e87b2b 4823 int t=0;
cf95b4f0 4824 if(dops[i].itype==RJUMP)
57871462 4825 {
4826 *adj=0;
4827 }
4828 //if(ba[i]>=start && ba[i]<(start+slen*4))
ad49de89 4829 if(internal_branch(ba[i]))
57871462 4830 {
b6e87b2b 4831 t=(ba[i]-start)>>2;
2330734f 4832 if(dops[t].is_ds) *adj=-CLOCK_ADJUST(1); // Branch into delay slot adds an extra cycle
57871462 4833 else *adj=ccadj[t];
4834 }
4835 else
4836 {
4837 *adj=0;
4838 }
2330734f 4839 count = ccadj[i];
4840 count_plus2 = count + CLOCK_ADJUST(2);
57871462 4841 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4842 // Idle loop
4843 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
b14b6a8f 4844 idle=out;
57871462 4845 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4846 emit_andimm(HOST_CCREG,3,HOST_CCREG);
b14b6a8f 4847 jaddr=out;
57871462 4848 emit_jmp(0);
4849 }
4850 else if(*adj==0||invert) {
2330734f 4851 int cycles = count_plus2;
b6e87b2b 4852 // faster loop HACK
bb4f300c 4853#if 0
b6e87b2b 4854 if (t&&*adj) {
4855 int rel=t-i;
4856 if(-NO_CYCLE_PENALTY_THR<rel&&rel<0)
2330734f 4857 cycles=*adj+count+2-*adj;
b6e87b2b 4858 }
bb4f300c 4859#endif
2330734f 4860 emit_addimm_and_set_flags(cycles, HOST_CCREG);
4861 jaddr = out;
57871462 4862 emit_jns(0);
4863 }
4864 else
4865 {
2330734f 4866 emit_cmpimm(HOST_CCREG, -count_plus2);
4867 jaddr = out;
57871462 4868 emit_jns(0);
4869 }
2330734f 4870 add_stub(CC_STUB,jaddr,idle?idle:out,(*adj==0||invert||idle)?0:count_plus2,i,addr,taken,0);
57871462 4871}
4872
b14b6a8f 4873static void do_ccstub(int n)
57871462 4874{
4875 literal_pool(256);
d1e4ebd9 4876 assem_debug("do_ccstub %x\n",start+(u_int)stubs[n].b*4);
b14b6a8f 4877 set_jump_target(stubs[n].addr, out);
4878 int i=stubs[n].b;
4879 if(stubs[n].d==NULLDS) {
57871462 4880 // Delay slot instruction is nullified ("likely" branch)
ad49de89 4881 wb_dirtys(regs[i].regmap,regs[i].dirty);
57871462 4882 }
b14b6a8f 4883 else if(stubs[n].d!=TAKEN) {
ad49de89 4884 wb_dirtys(branch_regs[i].regmap,branch_regs[i].dirty);
57871462 4885 }
4886 else {
ad49de89 4887 if(internal_branch(ba[i]))
4888 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 4889 }
b14b6a8f 4890 if(stubs[n].c!=-1)
57871462 4891 {
4892 // Save PC as return address
b14b6a8f 4893 emit_movimm(stubs[n].c,EAX);
643aeae3 4894 emit_writeword(EAX,&pcaddr);
57871462 4895 }
4896 else
4897 {
4898 // Return address depends on which way the branch goes
cf95b4f0 4899 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
57871462 4900 {
cf95b4f0 4901 int s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
4902 int s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
4903 if(dops[i].rs1==0)
57871462 4904 {
ad49de89 4905 s1l=s2l;
4906 s2l=-1;
57871462 4907 }
cf95b4f0 4908 else if(dops[i].rs2==0)
57871462 4909 {
ad49de89 4910 s2l=-1;
57871462 4911 }
4912 assert(s1l>=0);
4913 #ifdef DESTRUCTIVE_WRITEBACK
cf95b4f0 4914 if(dops[i].rs1) {
ad49de89 4915 if((branch_regs[i].dirty>>s1l)&&1)
cf95b4f0 4916 emit_loadreg(dops[i].rs1,s1l);
9f51b4b9 4917 }
57871462 4918 else {
ad49de89 4919 if((branch_regs[i].dirty>>s1l)&1)
cf95b4f0 4920 emit_loadreg(dops[i].rs2,s1l);
57871462 4921 }
4922 if(s2l>=0)
ad49de89 4923 if((branch_regs[i].dirty>>s2l)&1)
cf95b4f0 4924 emit_loadreg(dops[i].rs2,s2l);
57871462 4925 #endif
4926 int hr=0;
5194fb95 4927 int addr=-1,alt=-1,ntaddr=-1;
57871462 4928 while(hr<HOST_REGS)
4929 {
4930 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
cf95b4f0 4931 (branch_regs[i].regmap[hr]&63)!=dops[i].rs1 &&
4932 (branch_regs[i].regmap[hr]&63)!=dops[i].rs2 )
57871462 4933 {
4934 addr=hr++;break;
4935 }
4936 hr++;
4937 }
4938 while(hr<HOST_REGS)
4939 {
4940 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
cf95b4f0 4941 (branch_regs[i].regmap[hr]&63)!=dops[i].rs1 &&
4942 (branch_regs[i].regmap[hr]&63)!=dops[i].rs2 )
57871462 4943 {
4944 alt=hr++;break;
4945 }
4946 hr++;
4947 }
cf95b4f0 4948 if((dops[i].opcode&0x2E)==6) // BLEZ/BGTZ needs another register
57871462 4949 {
4950 while(hr<HOST_REGS)
4951 {
4952 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
cf95b4f0 4953 (branch_regs[i].regmap[hr]&63)!=dops[i].rs1 &&
4954 (branch_regs[i].regmap[hr]&63)!=dops[i].rs2 )
57871462 4955 {
4956 ntaddr=hr;break;
4957 }
4958 hr++;
4959 }
4960 assert(hr<HOST_REGS);
4961 }
cf95b4f0 4962 if((dops[i].opcode&0x2f)==4) // BEQ
57871462 4963 {
4964 #ifdef HAVE_CMOV_IMM
ad49de89 4965 if(s2l>=0) emit_cmp(s1l,s2l);
4966 else emit_test(s1l,s1l);
4967 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
4968 #else
4969 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4970 if(s2l>=0) emit_cmp(s1l,s2l);
4971 else emit_test(s1l,s1l);
4972 emit_cmovne_reg(alt,addr);
57871462 4973 #endif
57871462 4974 }
cf95b4f0 4975 if((dops[i].opcode&0x2f)==5) // BNE
57871462 4976 {
4977 #ifdef HAVE_CMOV_IMM
ad49de89 4978 if(s2l>=0) emit_cmp(s1l,s2l);
4979 else emit_test(s1l,s1l);
4980 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
4981 #else
4982 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
4983 if(s2l>=0) emit_cmp(s1l,s2l);
4984 else emit_test(s1l,s1l);
4985 emit_cmovne_reg(alt,addr);
57871462 4986 #endif
57871462 4987 }
cf95b4f0 4988 if((dops[i].opcode&0x2f)==6) // BLEZ
57871462 4989 {
4990 //emit_movimm(ba[i],alt);
4991 //emit_movimm(start+i*4+8,addr);
4992 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4993 emit_cmpimm(s1l,1);
57871462 4994 emit_cmovl_reg(alt,addr);
57871462 4995 }
cf95b4f0 4996 if((dops[i].opcode&0x2f)==7) // BGTZ
57871462 4997 {
4998 //emit_movimm(ba[i],addr);
4999 //emit_movimm(start+i*4+8,ntaddr);
5000 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5001 emit_cmpimm(s1l,1);
57871462 5002 emit_cmovl_reg(ntaddr,addr);
57871462 5003 }
cf95b4f0 5004 if((dops[i].opcode==1)&&(dops[i].opcode2&0x2D)==0) // BLTZ
57871462 5005 {
5006 //emit_movimm(ba[i],alt);
5007 //emit_movimm(start+i*4+8,addr);
5008 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
ad49de89 5009 emit_test(s1l,s1l);
57871462 5010 emit_cmovs_reg(alt,addr);
5011 }
cf95b4f0 5012 if((dops[i].opcode==1)&&(dops[i].opcode2&0x2D)==1) // BGEZ
57871462 5013 {
5014 //emit_movimm(ba[i],addr);
5015 //emit_movimm(start+i*4+8,alt);
5016 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
ad49de89 5017 emit_test(s1l,s1l);
57871462 5018 emit_cmovs_reg(alt,addr);
5019 }
cf95b4f0 5020 if(dops[i].opcode==0x11 && dops[i].opcode2==0x08 ) {
57871462 5021 if(source[i]&0x10000) // BC1T
5022 {
5023 //emit_movimm(ba[i],alt);
5024 //emit_movimm(start+i*4+8,addr);
5025 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5026 emit_testimm(s1l,0x800000);
5027 emit_cmovne_reg(alt,addr);
5028 }
5029 else // BC1F
5030 {
5031 //emit_movimm(ba[i],addr);
5032 //emit_movimm(start+i*4+8,alt);
5033 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5034 emit_testimm(s1l,0x800000);
5035 emit_cmovne_reg(alt,addr);
5036 }
5037 }
643aeae3 5038 emit_writeword(addr,&pcaddr);
57871462 5039 }
5040 else
cf95b4f0 5041 if(dops[i].itype==RJUMP)
57871462 5042 {
cf95b4f0 5043 int r=get_reg(branch_regs[i].regmap,dops[i].rs1);
4919de1e 5044 if (ds_writes_rjump_rs(i)) {
57871462 5045 r=get_reg(branch_regs[i].regmap,RTEMP);
5046 }
643aeae3 5047 emit_writeword(r,&pcaddr);
57871462 5048 }
7c3a5182 5049 else {SysPrintf("Unknown branch type in do_ccstub\n");abort();}
57871462 5050 }
5051 // Update cycle count
5052 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
2330734f 5053 if(stubs[n].a) emit_addimm(HOST_CCREG,(int)stubs[n].a,HOST_CCREG);
2a014d73 5054 emit_far_call(cc_interrupt);
2330734f 5055 if(stubs[n].a) emit_addimm(HOST_CCREG,-(int)stubs[n].a,HOST_CCREG);
b14b6a8f 5056 if(stubs[n].d==TAKEN) {
ad49de89 5057 if(internal_branch(ba[i]))
57871462 5058 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
cf95b4f0 5059 else if(dops[i].itype==RJUMP) {
57871462 5060 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
643aeae3 5061 emit_readword(&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
57871462 5062 else
cf95b4f0 5063 emit_loadreg(dops[i].rs1,get_reg(branch_regs[i].regmap,dops[i].rs1));
57871462 5064 }
b14b6a8f 5065 }else if(stubs[n].d==NOTTAKEN) {
57871462 5066 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5067 else load_all_regs(branch_regs[i].regmap);
b14b6a8f 5068 }else if(stubs[n].d==NULLDS) {
57871462 5069 // Delay slot instruction is nullified ("likely" branch)
5070 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5071 else load_all_regs(regs[i].regmap);
5072 }else{
5073 load_all_regs(branch_regs[i].regmap);
5074 }
d1e4ebd9 5075 if (stubs[n].retaddr)
5076 emit_jmp(stubs[n].retaddr);
5077 else
5078 do_jump_vaddr(stubs[n].e);
57871462 5079}
5080
643aeae3 5081static void add_to_linker(void *addr, u_int target, int ext)
57871462 5082{
643aeae3 5083 assert(linkcount < ARRAY_SIZE(link_addr));
5084 link_addr[linkcount].addr = addr;
5085 link_addr[linkcount].target = target;
5086 link_addr[linkcount].ext = ext;
57871462 5087 linkcount++;
5088}
5089
eba830cd 5090static void ujump_assemble_write_ra(int i)
5091{
5092 int rt;
5093 unsigned int return_address;
5094 rt=get_reg(branch_regs[i].regmap,31);
5095 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5096 //assert(rt>=0);
5097 return_address=start+i*4+8;
5098 if(rt>=0) {
5099 #ifdef USE_MINI_HT
cf95b4f0 5100 if(internal_branch(return_address)&&dops[i+1].rt1!=31) {
eba830cd 5101 int temp=-1; // note: must be ds-safe
5102 #ifdef HOST_TEMPREG
5103 temp=HOST_TEMPREG;
5104 #endif
5105 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5106 else emit_movimm(return_address,rt);
5107 }
5108 else
5109 #endif
5110 {
5111 #ifdef REG_PREFETCH
9f51b4b9 5112 if(temp>=0)
eba830cd 5113 {
643aeae3 5114 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
eba830cd 5115 }
5116 #endif
5117 emit_movimm(return_address,rt); // PC into link register
5118 #ifdef IMM_PREFETCH
df4dc2b1 5119 emit_prefetch(hash_table_get(return_address));
eba830cd 5120 #endif
5121 }
5122 }
5123}
5124
2330734f 5125static void ujump_assemble(int i, const struct regstat *i_regs)
57871462 5126{
eba830cd 5127 int ra_done=0;
57871462 5128 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5129 address_generation(i+1,i_regs,regs[i].regmap_entry);
5130 #ifdef REG_PREFETCH
5131 int temp=get_reg(branch_regs[i].regmap,PTEMP);
cf95b4f0 5132 if(dops[i].rt1==31&&temp>=0)
57871462 5133 {
581335b0 5134 signed char *i_regmap=i_regs->regmap;
57871462 5135 int return_address=start+i*4+8;
9f51b4b9 5136 if(get_reg(branch_regs[i].regmap,31)>0)
643aeae3 5137 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
57871462 5138 }
5139 #endif
cf95b4f0 5140 if(dops[i].rt1==31&&(dops[i].rt1==dops[i+1].rs1||dops[i].rt1==dops[i+1].rs2)) {
eba830cd 5141 ujump_assemble_write_ra(i); // writeback ra for DS
5142 ra_done=1;
57871462 5143 }
4ef8f67d 5144 ds_assemble(i+1,i_regs);
5145 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5146 bc_unneeded|=1|(1LL<<dops[i].rt1);
ad49de89 5147 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5148 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
cf95b4f0 5149 if(!ra_done&&dops[i].rt1==31)
eba830cd 5150 ujump_assemble_write_ra(i);
57871462 5151 int cc,adj;
5152 cc=get_reg(branch_regs[i].regmap,CCREG);
5153 assert(cc==HOST_CCREG);
ad49de89 5154 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5155 #ifdef REG_PREFETCH
cf95b4f0 5156 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
57871462 5157 #endif
5158 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
2330734f 5159 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
ad49de89 5160 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5161 if(internal_branch(ba[i]))
57871462 5162 assem_debug("branch: internal\n");
5163 else
5164 assem_debug("branch: external\n");
cf95b4f0 5165 if (internal_branch(ba[i]) && dops[(ba[i]-start)>>2].is_ds) {
57871462 5166 ds_assemble_entry(i);
5167 }
5168 else {
ad49de89 5169 add_to_linker(out,ba[i],internal_branch(ba[i]));
57871462 5170 emit_jmp(0);
5171 }
5172}
5173
eba830cd 5174static void rjump_assemble_write_ra(int i)
5175{
5176 int rt,return_address;
cf95b4f0 5177 assert(dops[i+1].rt1!=dops[i].rt1);
5178 assert(dops[i+1].rt2!=dops[i].rt1);
5179 rt=get_reg(branch_regs[i].regmap,dops[i].rt1);
eba830cd 5180 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5181 assert(rt>=0);
5182 return_address=start+i*4+8;
5183 #ifdef REG_PREFETCH
9f51b4b9 5184 if(temp>=0)
eba830cd 5185 {
643aeae3 5186 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
eba830cd 5187 }
5188 #endif
5189 emit_movimm(return_address,rt); // PC into link register
5190 #ifdef IMM_PREFETCH
df4dc2b1 5191 emit_prefetch(hash_table_get(return_address));
eba830cd 5192 #endif
5193}
5194
2330734f 5195static void rjump_assemble(int i, const struct regstat *i_regs)
57871462 5196{
57871462 5197 int temp;
581335b0 5198 int rs,cc;
eba830cd 5199 int ra_done=0;
cf95b4f0 5200 rs=get_reg(branch_regs[i].regmap,dops[i].rs1);
57871462 5201 assert(rs>=0);
4919de1e 5202 if (ds_writes_rjump_rs(i)) {
57871462 5203 // Delay slot abuse, make a copy of the branch address register
5204 temp=get_reg(branch_regs[i].regmap,RTEMP);
5205 assert(temp>=0);
5206 assert(regs[i].regmap[temp]==RTEMP);
5207 emit_mov(rs,temp);
5208 rs=temp;
5209 }
5210 address_generation(i+1,i_regs,regs[i].regmap_entry);
5211 #ifdef REG_PREFETCH
cf95b4f0 5212 if(dops[i].rt1==31)
57871462 5213 {
5214 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
581335b0 5215 signed char *i_regmap=i_regs->regmap;
57871462 5216 int return_address=start+i*4+8;
643aeae3 5217 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
57871462 5218 }
5219 }
5220 #endif
5221 #ifdef USE_MINI_HT
cf95b4f0 5222 if(dops[i].rs1==31) {
57871462 5223 int rh=get_reg(regs[i].regmap,RHASH);
5224 if(rh>=0) do_preload_rhash(rh);
5225 }
5226 #endif
cf95b4f0 5227 if(dops[i].rt1!=0&&(dops[i].rt1==dops[i+1].rs1||dops[i].rt1==dops[i+1].rs2)) {
eba830cd 5228 rjump_assemble_write_ra(i);
5229 ra_done=1;
57871462 5230 }
d5910d5d 5231 ds_assemble(i+1,i_regs);
5232 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5233 bc_unneeded|=1|(1LL<<dops[i].rt1);
5234 bc_unneeded&=~(1LL<<dops[i].rs1);
ad49de89 5235 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
cf95b4f0 5236 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,CCREG);
5237 if(!ra_done&&dops[i].rt1!=0)
eba830cd 5238 rjump_assemble_write_ra(i);
57871462 5239 cc=get_reg(branch_regs[i].regmap,CCREG);
5240 assert(cc==HOST_CCREG);
581335b0 5241 (void)cc;
57871462 5242 #ifdef USE_MINI_HT
5243 int rh=get_reg(branch_regs[i].regmap,RHASH);
5244 int ht=get_reg(branch_regs[i].regmap,RHTBL);
cf95b4f0 5245 if(dops[i].rs1==31) {
57871462 5246 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5247 do_preload_rhtbl(ht);
5248 do_rhash(rs,rh);
5249 }
5250 #endif
ad49de89 5251 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
57871462 5252 #ifdef DESTRUCTIVE_WRITEBACK
ad49de89 5253 if((branch_regs[i].dirty>>rs)&1) {
cf95b4f0 5254 if(dops[i].rs1!=dops[i+1].rt1&&dops[i].rs1!=dops[i+1].rt2) {
5255 emit_loadreg(dops[i].rs1,rs);
57871462 5256 }
5257 }
5258 #endif
5259 #ifdef REG_PREFETCH
cf95b4f0 5260 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
57871462 5261 #endif
5262 #ifdef USE_MINI_HT
cf95b4f0 5263 if(dops[i].rs1==31) {
57871462 5264 do_miniht_load(ht,rh);
5265 }
5266 #endif
5267 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5268 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5269 //assert(adj==0);
2330734f 5270 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
d1e4ebd9 5271 add_stub(CC_STUB,out,NULL,0,i,-1,TAKEN,rs);
cf95b4f0 5272 if(dops[i+1].itype==COP0&&(source[i+1]&0x3f)==0x10)
911f2d55 5273 // special case for RFE
5274 emit_jmp(0);
5275 else
71e490c5 5276 emit_jns(0);
ad49de89 5277 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
57871462 5278 #ifdef USE_MINI_HT
cf95b4f0 5279 if(dops[i].rs1==31) {
57871462 5280 do_miniht_jump(rs,rh,ht);
5281 }
5282 else
5283 #endif
5284 {
d1e4ebd9 5285 do_jump_vaddr(rs);
57871462 5286 }
57871462 5287 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
cf95b4f0 5288 if(dops[i].rt1!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
57871462 5289 #endif
5290}
5291
2330734f 5292static void cjump_assemble(int i, const struct regstat *i_regs)
57871462 5293{
2330734f 5294 const signed char *i_regmap = i_regs->regmap;
57871462 5295 int cc;
5296 int match;
ad49de89 5297 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5298 assem_debug("match=%d\n",match);
ad49de89 5299 int s1l,s2l;
57871462 5300 int unconditional=0,nop=0;
57871462 5301 int invert=0;
ad49de89 5302 int internal=internal_branch(ba[i]);
57871462 5303 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 5304 if(!match) invert=1;
5305 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5306 if(i>(ba[i]-start)>>2) invert=1;
5307 #endif
3968e69e 5308 #ifdef __aarch64__
5309 invert=1; // because of near cond. branches
5310 #endif
9f51b4b9 5311
cf95b4f0 5312 if(dops[i].ooo) {
5313 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5314 s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
57871462 5315 }
5316 else {
cf95b4f0 5317 s1l=get_reg(i_regmap,dops[i].rs1);
5318 s2l=get_reg(i_regmap,dops[i].rs2);
57871462 5319 }
cf95b4f0 5320 if(dops[i].rs1==0&&dops[i].rs2==0)
57871462 5321 {
cf95b4f0 5322 if(dops[i].opcode&1) nop=1;
57871462 5323 else unconditional=1;
cf95b4f0 5324 //assert(dops[i].opcode!=5);
5325 //assert(dops[i].opcode!=7);
5326 //assert(dops[i].opcode!=0x15);
5327 //assert(dops[i].opcode!=0x17);
57871462 5328 }
cf95b4f0 5329 else if(dops[i].rs1==0)
57871462 5330 {
ad49de89 5331 s1l=s2l;
5332 s2l=-1;
57871462 5333 }
cf95b4f0 5334 else if(dops[i].rs2==0)
57871462 5335 {
ad49de89 5336 s2l=-1;
57871462 5337 }
5338
cf95b4f0 5339 if(dops[i].ooo) {
57871462 5340 // Out of order execution (delay slot first)
5341 //printf("OOOE\n");
5342 address_generation(i+1,i_regs,regs[i].regmap_entry);
5343 ds_assemble(i+1,i_regs);
5344 int adj;
5345 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5346 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 5347 bc_unneeded|=1;
ad49de89 5348 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
cf95b4f0 5349 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs2);
ad49de89 5350 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
57871462 5351 cc=get_reg(branch_regs[i].regmap,CCREG);
5352 assert(cc==HOST_CCREG);
9f51b4b9 5353 if(unconditional)
ad49de89 5354 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5355 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5356 //assem_debug("cycle count (adj)\n");
5357 if(unconditional) {
5358 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5359 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
2330734f 5360 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
ad49de89 5361 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5362 if(internal)
5363 assem_debug("branch: internal\n");
5364 else
5365 assem_debug("branch: external\n");
cf95b4f0 5366 if (internal && dops[(ba[i]-start)>>2].is_ds) {
57871462 5367 ds_assemble_entry(i);
5368 }
5369 else {
643aeae3 5370 add_to_linker(out,ba[i],internal);
57871462 5371 emit_jmp(0);
5372 }
5373 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5374 if(((u_int)out)&7) emit_addnop(0);
5375 #endif
5376 }
5377 }
5378 else if(nop) {
2330734f 5379 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
b14b6a8f 5380 void *jaddr=out;
57871462 5381 emit_jns(0);
b14b6a8f 5382 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5383 }
5384 else {
df4dc2b1 5385 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
57871462 5386 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
2330734f 5387 if(adj&&!invert) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
9f51b4b9 5388
57871462 5389 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5390 assert(s1l>=0);
cf95b4f0 5391 if(dops[i].opcode==4) // BEQ
57871462 5392 {
5393 if(s2l>=0) emit_cmp(s1l,s2l);
5394 else emit_test(s1l,s1l);
5395 if(invert){
df4dc2b1 5396 nottaken=out;
7c3a5182 5397 emit_jne(DJT_1);
57871462 5398 }else{
643aeae3 5399 add_to_linker(out,ba[i],internal);
57871462 5400 emit_jeq(0);
5401 }
5402 }
cf95b4f0 5403 if(dops[i].opcode==5) // BNE
57871462 5404 {
5405 if(s2l>=0) emit_cmp(s1l,s2l);
5406 else emit_test(s1l,s1l);
5407 if(invert){
df4dc2b1 5408 nottaken=out;
7c3a5182 5409 emit_jeq(DJT_1);
57871462 5410 }else{
643aeae3 5411 add_to_linker(out,ba[i],internal);
57871462 5412 emit_jne(0);
5413 }
5414 }
cf95b4f0 5415 if(dops[i].opcode==6) // BLEZ
57871462 5416 {
5417 emit_cmpimm(s1l,1);
5418 if(invert){
df4dc2b1 5419 nottaken=out;
7c3a5182 5420 emit_jge(DJT_1);
57871462 5421 }else{
643aeae3 5422 add_to_linker(out,ba[i],internal);
57871462 5423 emit_jl(0);
5424 }
5425 }
cf95b4f0 5426 if(dops[i].opcode==7) // BGTZ
57871462 5427 {
5428 emit_cmpimm(s1l,1);
5429 if(invert){
df4dc2b1 5430 nottaken=out;
7c3a5182 5431 emit_jl(DJT_1);
57871462 5432 }else{
643aeae3 5433 add_to_linker(out,ba[i],internal);
57871462 5434 emit_jge(0);
5435 }
5436 }
5437 if(invert) {
df4dc2b1 5438 if(taken) set_jump_target(taken, out);
57871462 5439 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
cf95b4f0 5440 if (match && (!internal || !dops[(ba[i]-start)>>2].is_ds)) {
57871462 5441 if(adj) {
2330734f 5442 emit_addimm(cc,-adj,cc);
643aeae3 5443 add_to_linker(out,ba[i],internal);
57871462 5444 }else{
5445 emit_addnop(13);
643aeae3 5446 add_to_linker(out,ba[i],internal*2);
57871462 5447 }
5448 emit_jmp(0);
5449 }else
5450 #endif
5451 {
2330734f 5452 if(adj) emit_addimm(cc,-adj,cc);
ad49de89 5453 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5454 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5455 if(internal)
5456 assem_debug("branch: internal\n");
5457 else
5458 assem_debug("branch: external\n");
cf95b4f0 5459 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
57871462 5460 ds_assemble_entry(i);
5461 }
5462 else {
643aeae3 5463 add_to_linker(out,ba[i],internal);
57871462 5464 emit_jmp(0);
5465 }
5466 }
df4dc2b1 5467 set_jump_target(nottaken, out);
57871462 5468 }
5469
df4dc2b1 5470 if(nottaken1) set_jump_target(nottaken1, out);
57871462 5471 if(adj) {
2330734f 5472 if(!invert) emit_addimm(cc,adj,cc);
57871462 5473 }
5474 } // (!unconditional)
5475 } // if(ooo)
5476 else
5477 {
5478 // In-order execution (branch first)
df4dc2b1 5479 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
57871462 5480 if(!unconditional&&!nop) {
57871462 5481 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5482 assert(s1l>=0);
cf95b4f0 5483 if((dops[i].opcode&0x2f)==4) // BEQ
57871462 5484 {
5485 if(s2l>=0) emit_cmp(s1l,s2l);
5486 else emit_test(s1l,s1l);
df4dc2b1 5487 nottaken=out;
7c3a5182 5488 emit_jne(DJT_2);
57871462 5489 }
cf95b4f0 5490 if((dops[i].opcode&0x2f)==5) // BNE
57871462 5491 {
5492 if(s2l>=0) emit_cmp(s1l,s2l);
5493 else emit_test(s1l,s1l);
df4dc2b1 5494 nottaken=out;
7c3a5182 5495 emit_jeq(DJT_2);
57871462 5496 }
cf95b4f0 5497 if((dops[i].opcode&0x2f)==6) // BLEZ
57871462 5498 {
5499 emit_cmpimm(s1l,1);
df4dc2b1 5500 nottaken=out;
7c3a5182 5501 emit_jge(DJT_2);
57871462 5502 }
cf95b4f0 5503 if((dops[i].opcode&0x2f)==7) // BGTZ
57871462 5504 {
5505 emit_cmpimm(s1l,1);
df4dc2b1 5506 nottaken=out;
7c3a5182 5507 emit_jl(DJT_2);
57871462 5508 }
5509 } // if(!unconditional)
5510 int adj;
5511 uint64_t ds_unneeded=branch_regs[i].u;
cf95b4f0 5512 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
57871462 5513 ds_unneeded|=1;
57871462 5514 // branch taken
5515 if(!nop) {
df4dc2b1 5516 if(taken) set_jump_target(taken, out);
57871462 5517 assem_debug("1:\n");
ad49de89 5518 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
57871462 5519 // load regs
cf95b4f0 5520 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
57871462 5521 address_generation(i+1,&branch_regs[i],0);
37387d8b 5522 if (ram_offset)
5523 load_regs(regs[i].regmap,branch_regs[i].regmap,ROREG,ROREG);
ad49de89 5524 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
57871462 5525 ds_assemble(i+1,&branch_regs[i]);
5526 cc=get_reg(branch_regs[i].regmap,CCREG);
5527 if(cc==-1) {
5528 emit_loadreg(CCREG,cc=HOST_CCREG);
5529 // CHECK: Is the following instruction (fall thru) allocated ok?
5530 }
5531 assert(cc==HOST_CCREG);
ad49de89 5532 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5533 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5534 assem_debug("cycle count (adj)\n");
2330734f 5535 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
ad49de89 5536 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5537 if(internal)
5538 assem_debug("branch: internal\n");
5539 else
5540 assem_debug("branch: external\n");
cf95b4f0 5541 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
57871462 5542 ds_assemble_entry(i);
5543 }
5544 else {
643aeae3 5545 add_to_linker(out,ba[i],internal);
57871462 5546 emit_jmp(0);
5547 }
5548 }
5549 // branch not taken
57871462 5550 if(!unconditional) {
df4dc2b1 5551 if(nottaken1) set_jump_target(nottaken1, out);
5552 set_jump_target(nottaken, out);
57871462 5553 assem_debug("2:\n");
fe807a8a 5554 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
37387d8b 5555 // load regs
fe807a8a 5556 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5557 address_generation(i+1,&branch_regs[i],0);
37387d8b 5558 if (ram_offset)
5559 load_regs(regs[i].regmap,branch_regs[i].regmap,ROREG,ROREG);
5560 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
fe807a8a 5561 ds_assemble(i+1,&branch_regs[i]);
57871462 5562 cc=get_reg(branch_regs[i].regmap,CCREG);
fe807a8a 5563 if (cc == -1) {
57871462 5564 // Cycle count isn't in a register, temporarily load it then write it out
5565 emit_loadreg(CCREG,HOST_CCREG);
2330734f 5566 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
b14b6a8f 5567 void *jaddr=out;
57871462 5568 emit_jns(0);
b14b6a8f 5569 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5570 emit_storereg(CCREG,HOST_CCREG);
5571 }
5572 else{
5573 cc=get_reg(i_regmap,CCREG);
5574 assert(cc==HOST_CCREG);
2330734f 5575 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
b14b6a8f 5576 void *jaddr=out;
57871462 5577 emit_jns(0);
fe807a8a 5578 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5579 }
5580 }
5581 }
5582}
5583
2330734f 5584static void sjump_assemble(int i, const struct regstat *i_regs)
57871462 5585{
2330734f 5586 const signed char *i_regmap = i_regs->regmap;
57871462 5587 int cc;
5588 int match;
ad49de89 5589 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5590 assem_debug("smatch=%d\n",match);
ad49de89 5591 int s1l;
57871462 5592 int unconditional=0,nevertaken=0;
57871462 5593 int invert=0;
ad49de89 5594 int internal=internal_branch(ba[i]);
57871462 5595 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 5596 if(!match) invert=1;
5597 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5598 if(i>(ba[i]-start)>>2) invert=1;
5599 #endif
3968e69e 5600 #ifdef __aarch64__
5601 invert=1; // because of near cond. branches
5602 #endif
57871462 5603
cf95b4f0 5604 //if(dops[i].opcode2>=0x10) return; // FIXME (BxxZAL)
5605 //assert(dops[i].opcode2<0x10||dops[i].rs1==0); // FIXME (BxxZAL)
57871462 5606
cf95b4f0 5607 if(dops[i].ooo) {
5608 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
57871462 5609 }
5610 else {
cf95b4f0 5611 s1l=get_reg(i_regmap,dops[i].rs1);
57871462 5612 }
cf95b4f0 5613 if(dops[i].rs1==0)
57871462 5614 {
cf95b4f0 5615 if(dops[i].opcode2&1) unconditional=1;
57871462 5616 else nevertaken=1;
5617 // These are never taken (r0 is never less than zero)
cf95b4f0 5618 //assert(dops[i].opcode2!=0);
5619 //assert(dops[i].opcode2!=2);
5620 //assert(dops[i].opcode2!=0x10);
5621 //assert(dops[i].opcode2!=0x12);
57871462 5622 }
57871462 5623
cf95b4f0 5624 if(dops[i].ooo) {
57871462 5625 // Out of order execution (delay slot first)
5626 //printf("OOOE\n");
5627 address_generation(i+1,i_regs,regs[i].regmap_entry);
5628 ds_assemble(i+1,i_regs);
5629 int adj;
5630 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5631 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 5632 bc_unneeded|=1;
ad49de89 5633 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
cf95b4f0 5634 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs1);
ad49de89 5635 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
cf95b4f0 5636 if(dops[i].rt1==31) {
57871462 5637 int rt,return_address;
57871462 5638 rt=get_reg(branch_regs[i].regmap,31);
5639 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5640 if(rt>=0) {
5641 // Save the PC even if the branch is not taken
5642 return_address=start+i*4+8;
5643 emit_movimm(return_address,rt); // PC into link register
5644 #ifdef IMM_PREFETCH
df4dc2b1 5645 if(!nevertaken) emit_prefetch(hash_table_get(return_address));
57871462 5646 #endif
5647 }
5648 }
5649 cc=get_reg(branch_regs[i].regmap,CCREG);
5650 assert(cc==HOST_CCREG);
9f51b4b9 5651 if(unconditional)
ad49de89 5652 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5653 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5654 assem_debug("cycle count (adj)\n");
5655 if(unconditional) {
5656 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5657 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
2330734f 5658 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
ad49de89 5659 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5660 if(internal)
5661 assem_debug("branch: internal\n");
5662 else
5663 assem_debug("branch: external\n");
cf95b4f0 5664 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
57871462 5665 ds_assemble_entry(i);
5666 }
5667 else {
643aeae3 5668 add_to_linker(out,ba[i],internal);
57871462 5669 emit_jmp(0);
5670 }
5671 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5672 if(((u_int)out)&7) emit_addnop(0);
5673 #endif
5674 }
5675 }
5676 else if(nevertaken) {
2330734f 5677 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
b14b6a8f 5678 void *jaddr=out;
57871462 5679 emit_jns(0);
b14b6a8f 5680 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5681 }
5682 else {
df4dc2b1 5683 void *nottaken = NULL;
57871462 5684 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
2330734f 5685 if(adj&&!invert) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
57871462 5686 {
5687 assert(s1l>=0);
cf95b4f0 5688 if((dops[i].opcode2&0xf)==0) // BLTZ/BLTZAL
57871462 5689 {
5690 emit_test(s1l,s1l);
5691 if(invert){
df4dc2b1 5692 nottaken=out;
7c3a5182 5693 emit_jns(DJT_1);
57871462 5694 }else{
643aeae3 5695 add_to_linker(out,ba[i],internal);
57871462 5696 emit_js(0);
5697 }
5698 }
cf95b4f0 5699 if((dops[i].opcode2&0xf)==1) // BGEZ/BLTZAL
57871462 5700 {
5701 emit_test(s1l,s1l);
5702 if(invert){
df4dc2b1 5703 nottaken=out;
7c3a5182 5704 emit_js(DJT_1);
57871462 5705 }else{
643aeae3 5706 add_to_linker(out,ba[i],internal);
57871462 5707 emit_jns(0);
5708 }
5709 }
ad49de89 5710 }
9f51b4b9 5711
57871462 5712 if(invert) {
5713 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
cf95b4f0 5714 if (match && (!internal || !dops[(ba[i] - start) >> 2].is_ds)) {
57871462 5715 if(adj) {
2330734f 5716 emit_addimm(cc,-adj,cc);
643aeae3 5717 add_to_linker(out,ba[i],internal);
57871462 5718 }else{
5719 emit_addnop(13);
643aeae3 5720 add_to_linker(out,ba[i],internal*2);
57871462 5721 }
5722 emit_jmp(0);
5723 }else
5724 #endif
5725 {
2330734f 5726 if(adj) emit_addimm(cc,-adj,cc);
ad49de89 5727 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5728 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5729 if(internal)
5730 assem_debug("branch: internal\n");
5731 else
5732 assem_debug("branch: external\n");
cf95b4f0 5733 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
57871462 5734 ds_assemble_entry(i);
5735 }
5736 else {
643aeae3 5737 add_to_linker(out,ba[i],internal);
57871462 5738 emit_jmp(0);
5739 }
5740 }
df4dc2b1 5741 set_jump_target(nottaken, out);
57871462 5742 }
5743
5744 if(adj) {
2330734f 5745 if(!invert) emit_addimm(cc,adj,cc);
57871462 5746 }
5747 } // (!unconditional)
5748 } // if(ooo)
5749 else
5750 {
5751 // In-order execution (branch first)
5752 //printf("IOE\n");
df4dc2b1 5753 void *nottaken = NULL;
cf95b4f0 5754 if(dops[i].rt1==31) {
a6491170 5755 int rt,return_address;
a6491170 5756 rt=get_reg(branch_regs[i].regmap,31);
5757 if(rt>=0) {
5758 // Save the PC even if the branch is not taken
5759 return_address=start+i*4+8;
5760 emit_movimm(return_address,rt); // PC into link register
5761 #ifdef IMM_PREFETCH
df4dc2b1 5762 emit_prefetch(hash_table_get(return_address));
a6491170 5763 #endif
5764 }
5765 }
57871462 5766 if(!unconditional) {
5767 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
57871462 5768 assert(s1l>=0);
cf95b4f0 5769 if((dops[i].opcode2&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
57871462 5770 {
5771 emit_test(s1l,s1l);
df4dc2b1 5772 nottaken=out;
7c3a5182 5773 emit_jns(DJT_1);
57871462 5774 }
cf95b4f0 5775 if((dops[i].opcode2&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
57871462 5776 {
5777 emit_test(s1l,s1l);
df4dc2b1 5778 nottaken=out;
7c3a5182 5779 emit_js(DJT_1);
57871462 5780 }
57871462 5781 } // if(!unconditional)
5782 int adj;
5783 uint64_t ds_unneeded=branch_regs[i].u;
cf95b4f0 5784 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
57871462 5785 ds_unneeded|=1;
57871462 5786 // branch taken
5787 if(!nevertaken) {
5788 //assem_debug("1:\n");
ad49de89 5789 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
57871462 5790 // load regs
cf95b4f0 5791 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
57871462 5792 address_generation(i+1,&branch_regs[i],0);
37387d8b 5793 if (ram_offset)
5794 load_regs(regs[i].regmap,branch_regs[i].regmap,ROREG,ROREG);
ad49de89 5795 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
57871462 5796 ds_assemble(i+1,&branch_regs[i]);
5797 cc=get_reg(branch_regs[i].regmap,CCREG);
5798 if(cc==-1) {
5799 emit_loadreg(CCREG,cc=HOST_CCREG);
5800 // CHECK: Is the following instruction (fall thru) allocated ok?
5801 }
5802 assert(cc==HOST_CCREG);
ad49de89 5803 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5804 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5805 assem_debug("cycle count (adj)\n");
2330734f 5806 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
ad49de89 5807 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5808 if(internal)
5809 assem_debug("branch: internal\n");
5810 else
5811 assem_debug("branch: external\n");
cf95b4f0 5812 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
57871462 5813 ds_assemble_entry(i);
5814 }
5815 else {
643aeae3 5816 add_to_linker(out,ba[i],internal);
57871462 5817 emit_jmp(0);
5818 }
5819 }
5820 // branch not taken
57871462 5821 if(!unconditional) {
df4dc2b1 5822 set_jump_target(nottaken, out);
57871462 5823 assem_debug("1:\n");
fe807a8a 5824 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5825 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5826 address_generation(i+1,&branch_regs[i],0);
5827 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
5828 ds_assemble(i+1,&branch_regs[i]);
57871462 5829 cc=get_reg(branch_regs[i].regmap,CCREG);
fe807a8a 5830 if (cc == -1) {
57871462 5831 // Cycle count isn't in a register, temporarily load it then write it out
5832 emit_loadreg(CCREG,HOST_CCREG);
2330734f 5833 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
b14b6a8f 5834 void *jaddr=out;
57871462 5835 emit_jns(0);
b14b6a8f 5836 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5837 emit_storereg(CCREG,HOST_CCREG);
5838 }
5839 else{
5840 cc=get_reg(i_regmap,CCREG);
5841 assert(cc==HOST_CCREG);
2330734f 5842 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
b14b6a8f 5843 void *jaddr=out;
57871462 5844 emit_jns(0);
fe807a8a 5845 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5846 }
5847 }
5848 }
5849}
5850
2330734f 5851static void pagespan_assemble(int i, const struct regstat *i_regs)
57871462 5852{
cf95b4f0 5853 int s1l=get_reg(i_regs->regmap,dops[i].rs1);
5854 int s2l=get_reg(i_regs->regmap,dops[i].rs2);
df4dc2b1 5855 void *taken = NULL;
5856 void *nottaken = NULL;
57871462 5857 int unconditional=0;
cf95b4f0 5858 if(dops[i].rs1==0)
57871462 5859 {
ad49de89 5860 s1l=s2l;
5861 s2l=-1;
57871462 5862 }
cf95b4f0 5863 else if(dops[i].rs2==0)
57871462 5864 {
ad49de89 5865 s2l=-1;
57871462 5866 }
5867 int hr=0;
581335b0 5868 int addr=-1,alt=-1,ntaddr=-1;
57871462 5869 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
5870 else {
5871 while(hr<HOST_REGS)
5872 {
5873 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
cf95b4f0 5874 (i_regs->regmap[hr]&63)!=dops[i].rs1 &&
5875 (i_regs->regmap[hr]&63)!=dops[i].rs2 )
57871462 5876 {
5877 addr=hr++;break;
5878 }
5879 hr++;
5880 }
5881 }
5882 while(hr<HOST_REGS)
5883 {
5884 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
cf95b4f0 5885 (i_regs->regmap[hr]&63)!=dops[i].rs1 &&
5886 (i_regs->regmap[hr]&63)!=dops[i].rs2 )
57871462 5887 {
5888 alt=hr++;break;
5889 }
5890 hr++;
5891 }
cf95b4f0 5892 if((dops[i].opcode&0x2E)==6) // BLEZ/BGTZ needs another register
57871462 5893 {
5894 while(hr<HOST_REGS)
5895 {
5896 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
cf95b4f0 5897 (i_regs->regmap[hr]&63)!=dops[i].rs1 &&
5898 (i_regs->regmap[hr]&63)!=dops[i].rs2 )
57871462 5899 {
5900 ntaddr=hr;break;
5901 }
5902 hr++;
5903 }
5904 }
5905 assert(hr<HOST_REGS);
cf95b4f0 5906 if((dops[i].opcode&0x2e)==4||dops[i].opcode==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
ad49de89 5907 load_regs(regs[i].regmap_entry,regs[i].regmap,CCREG,CCREG);
57871462 5908 }
2330734f 5909 emit_addimm(HOST_CCREG, ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
cf95b4f0 5910 if(dops[i].opcode==2) // J
57871462 5911 {
5912 unconditional=1;
5913 }
cf95b4f0 5914 if(dops[i].opcode==3) // JAL
57871462 5915 {
5916 // TODO: mini_ht
5917 int rt=get_reg(i_regs->regmap,31);
5918 emit_movimm(start+i*4+8,rt);
5919 unconditional=1;
5920 }
cf95b4f0 5921 if(dops[i].opcode==0&&(dops[i].opcode2&0x3E)==8) // JR/JALR
57871462 5922 {
5923 emit_mov(s1l,addr);
cf95b4f0 5924 if(dops[i].opcode2==9) // JALR
57871462 5925 {
cf95b4f0 5926 int rt=get_reg(i_regs->regmap,dops[i].rt1);
57871462 5927 emit_movimm(start+i*4+8,rt);
5928 }
5929 }
cf95b4f0 5930 if((dops[i].opcode&0x3f)==4) // BEQ
57871462 5931 {
cf95b4f0 5932 if(dops[i].rs1==dops[i].rs2)
57871462 5933 {
5934 unconditional=1;
5935 }
5936 else
5937 #ifdef HAVE_CMOV_IMM
ad49de89 5938 if(1) {
57871462 5939 if(s2l>=0) emit_cmp(s1l,s2l);
5940 else emit_test(s1l,s1l);
5941 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5942 }
5943 else
5944 #endif
5945 {
5946 assert(s1l>=0);
5947 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
57871462 5948 if(s2l>=0) emit_cmp(s1l,s2l);
5949 else emit_test(s1l,s1l);
5950 emit_cmovne_reg(alt,addr);
5951 }
5952 }
cf95b4f0 5953 if((dops[i].opcode&0x3f)==5) // BNE
57871462 5954 {
5955 #ifdef HAVE_CMOV_IMM
ad49de89 5956 if(s2l>=0) emit_cmp(s1l,s2l);
5957 else emit_test(s1l,s1l);
5958 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5959 #else
5960 assert(s1l>=0);
5961 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5962 if(s2l>=0) emit_cmp(s1l,s2l);
5963 else emit_test(s1l,s1l);
5964 emit_cmovne_reg(alt,addr);
57871462 5965 #endif
57871462 5966 }
cf95b4f0 5967 if((dops[i].opcode&0x3f)==0x14) // BEQL
57871462 5968 {
57871462 5969 if(s2l>=0) emit_cmp(s1l,s2l);
5970 else emit_test(s1l,s1l);
df4dc2b1 5971 if(nottaken) set_jump_target(nottaken, out);
5972 nottaken=out;
57871462 5973 emit_jne(0);
5974 }
cf95b4f0 5975 if((dops[i].opcode&0x3f)==0x15) // BNEL
57871462 5976 {
57871462 5977 if(s2l>=0) emit_cmp(s1l,s2l);
5978 else emit_test(s1l,s1l);
df4dc2b1 5979 nottaken=out;
57871462 5980 emit_jeq(0);
df4dc2b1 5981 if(taken) set_jump_target(taken, out);
57871462 5982 }
cf95b4f0 5983 if((dops[i].opcode&0x3f)==6) // BLEZ
57871462 5984 {
5985 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5986 emit_cmpimm(s1l,1);
57871462 5987 emit_cmovl_reg(alt,addr);
57871462 5988 }
cf95b4f0 5989 if((dops[i].opcode&0x3f)==7) // BGTZ
57871462 5990 {
5991 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5992 emit_cmpimm(s1l,1);
57871462 5993 emit_cmovl_reg(ntaddr,addr);
57871462 5994 }
cf95b4f0 5995 if((dops[i].opcode&0x3f)==0x16) // BLEZL
57871462 5996 {
cf95b4f0 5997 assert((dops[i].opcode&0x3f)!=0x16);
57871462 5998 }
cf95b4f0 5999 if((dops[i].opcode&0x3f)==0x17) // BGTZL
57871462 6000 {
cf95b4f0 6001 assert((dops[i].opcode&0x3f)!=0x17);
57871462 6002 }
cf95b4f0 6003 assert(dops[i].opcode!=1); // BLTZ/BGEZ
57871462 6004
6005 //FIXME: Check CSREG
cf95b4f0 6006 if(dops[i].opcode==0x11 && dops[i].opcode2==0x08 ) {
57871462 6007 if((source[i]&0x30000)==0) // BC1F
6008 {
6009 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6010 emit_testimm(s1l,0x800000);
6011 emit_cmovne_reg(alt,addr);
6012 }
6013 if((source[i]&0x30000)==0x10000) // BC1T
6014 {
6015 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6016 emit_testimm(s1l,0x800000);
6017 emit_cmovne_reg(alt,addr);
6018 }
6019 if((source[i]&0x30000)==0x20000) // BC1FL
6020 {
6021 emit_testimm(s1l,0x800000);
df4dc2b1 6022 nottaken=out;
57871462 6023 emit_jne(0);
6024 }
6025 if((source[i]&0x30000)==0x30000) // BC1TL
6026 {
6027 emit_testimm(s1l,0x800000);
df4dc2b1 6028 nottaken=out;
57871462 6029 emit_jeq(0);
6030 }
6031 }
6032
6033 assert(i_regs->regmap[HOST_CCREG]==CCREG);
ad49de89 6034 wb_dirtys(regs[i].regmap,regs[i].dirty);
fe807a8a 6035 if(unconditional)
57871462 6036 {
6037 emit_movimm(ba[i],HOST_BTREG);
6038 }
6039 else if(addr!=HOST_BTREG)
6040 {
6041 emit_mov(addr,HOST_BTREG);
6042 }
6043 void *branch_addr=out;
6044 emit_jmp(0);
6045 int target_addr=start+i*4+5;
6046 void *stub=out;
6047 void *compiled_target_addr=check_addr(target_addr);
643aeae3 6048 emit_extjump_ds(branch_addr, target_addr);
57871462 6049 if(compiled_target_addr) {
df4dc2b1 6050 set_jump_target(branch_addr, compiled_target_addr);
3d680478 6051 add_jump_out(target_addr,stub);
57871462 6052 }
df4dc2b1 6053 else set_jump_target(branch_addr, stub);
57871462 6054}
6055
6056// Assemble the delay slot for the above
6057static void pagespan_ds()
6058{
6059 assem_debug("initial delay slot:\n");
6060 u_int vaddr=start+1;
94d23bb9 6061 u_int page=get_page(vaddr);
6062 u_int vpage=get_vpage(vaddr);
57871462 6063 ll_add(jump_dirty+vpage,vaddr,(void *)out);
3d680478 6064 do_dirty_stub_ds(slen*4);
57871462 6065 ll_add(jump_in+page,vaddr,(void *)out);
6066 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6067 if(regs[0].regmap[HOST_CCREG]!=CCREG)
ad49de89 6068 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty);
57871462 6069 if(regs[0].regmap[HOST_BTREG]!=BTREG)
643aeae3 6070 emit_writeword(HOST_BTREG,&branch_target);
cf95b4f0 6071 load_regs(regs[0].regmap_entry,regs[0].regmap,dops[0].rs1,dops[0].rs2);
57871462 6072 address_generation(0,&regs[0],regs[0].regmap_entry);
37387d8b 6073 if (ram_offset && (dops[0].is_load || dops[0].is_store))
6074 load_regs(regs[0].regmap_entry,regs[0].regmap,ROREG,ROREG);
6075 if (dops[0].is_store)
ad49de89 6076 load_regs(regs[0].regmap_entry,regs[0].regmap,INVCP,INVCP);
57871462 6077 is_delayslot=0;
2330734f 6078 switch (dops[0].itype) {
57871462 6079 case SYSCALL:
7139f3c8 6080 case HLECALL:
1e973cb0 6081 case INTCALL:
57871462 6082 case SPAN:
6083 case UJUMP:
6084 case RJUMP:
6085 case CJUMP:
6086 case SJUMP:
c43b5311 6087 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
2330734f 6088 break;
6089 default:
6090 assemble(0, &regs[0], 0);
57871462 6091 }
6092 int btaddr=get_reg(regs[0].regmap,BTREG);
6093 if(btaddr<0) {
6094 btaddr=get_reg(regs[0].regmap,-1);
643aeae3 6095 emit_readword(&branch_target,btaddr);
57871462 6096 }
6097 assert(btaddr!=HOST_CCREG);
6098 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6099#ifdef HOST_IMM8
d1e4ebd9 6100 host_tempreg_acquire();
57871462 6101 emit_movimm(start+4,HOST_TEMPREG);
6102 emit_cmp(btaddr,HOST_TEMPREG);
d1e4ebd9 6103 host_tempreg_release();
57871462 6104#else
6105 emit_cmpimm(btaddr,start+4);
6106#endif
df4dc2b1 6107 void *branch = out;
57871462 6108 emit_jeq(0);
ad49de89 6109 store_regs_bt(regs[0].regmap,regs[0].dirty,-1);
d1e4ebd9 6110 do_jump_vaddr(btaddr);
df4dc2b1 6111 set_jump_target(branch, out);
ad49de89 6112 store_regs_bt(regs[0].regmap,regs[0].dirty,start+4);
6113 load_regs_bt(regs[0].regmap,regs[0].dirty,start+4);
57871462 6114}
6115
6116// Basic liveness analysis for MIPS registers
6117void unneeded_registers(int istart,int iend,int r)
6118{
6119 int i;
00fa9369 6120 uint64_t u,gte_u,b,gte_b;
6121 uint64_t temp_u,temp_gte_u=0;
0ff8c62c 6122 uint64_t gte_u_unknown=0;
d62c125a 6123 if (HACK_ENABLED(NDHACK_GTE_UNNEEDED))
0ff8c62c 6124 gte_u_unknown=~0ll;
57871462 6125 if(iend==slen-1) {
00fa9369 6126 u=1;
0ff8c62c 6127 gte_u=gte_u_unknown;
57871462 6128 }else{
00fa9369 6129 //u=unneeded_reg[iend+1];
6130 u=1;
0ff8c62c 6131 gte_u=gte_unneeded[iend+1];
57871462 6132 }
bedfea38 6133
57871462 6134 for (i=iend;i>=istart;i--)
6135 {
6136 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
fe807a8a 6137 if(dops[i].is_jump)
57871462 6138 {
6139 // If subroutine call, flag return address as a possible branch target
cf95b4f0 6140 if(dops[i].rt1==31 && i<slen-2) dops[i+2].bt=1;
9f51b4b9 6141
57871462 6142 if(ba[i]<start || ba[i]>=(start+slen*4))
6143 {
6144 // Branch out of this block, flush all regs
6145 u=1;
0ff8c62c 6146 gte_u=gte_u_unknown;
57871462 6147 branch_unneeded_reg[i]=u;
57871462 6148 // Merge in delay slot
cf95b4f0 6149 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6150 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
00fa9369 6151 u|=1;
bedfea38 6152 gte_u|=gte_rt[i+1];
6153 gte_u&=~gte_rs[i+1];
57871462 6154 }
6155 else
6156 {
6157 // Internal branch, flag target
cf95b4f0 6158 dops[(ba[i]-start)>>2].bt=1;
57871462 6159 if(ba[i]<=start+i*4) {
6160 // Backward branch
fe807a8a 6161 if(dops[i].is_ujump)
57871462 6162 {
6163 // Unconditional branch
00fa9369 6164 temp_u=1;
bedfea38 6165 temp_gte_u=0;
57871462 6166 } else {
6167 // Conditional branch (not taken case)
6168 temp_u=unneeded_reg[i+2];
bedfea38 6169 temp_gte_u&=gte_unneeded[i+2];
57871462 6170 }
6171 // Merge in delay slot
cf95b4f0 6172 temp_u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6173 temp_u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
00fa9369 6174 temp_u|=1;
bedfea38 6175 temp_gte_u|=gte_rt[i+1];
6176 temp_gte_u&=~gte_rs[i+1];
cf95b4f0 6177 temp_u|=(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2);
6178 temp_u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
00fa9369 6179 temp_u|=1;
bedfea38 6180 temp_gte_u|=gte_rt[i];
6181 temp_gte_u&=~gte_rs[i];
57871462 6182 unneeded_reg[i]=temp_u;
bedfea38 6183 gte_unneeded[i]=temp_gte_u;
57871462 6184 // Only go three levels deep. This recursion can take an
6185 // excessive amount of time if there are a lot of nested loops.
6186 if(r<2) {
6187 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6188 }else{
6189 unneeded_reg[(ba[i]-start)>>2]=1;
0ff8c62c 6190 gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown;
57871462 6191 }
6192 } /*else*/ if(1) {
fe807a8a 6193 if (dops[i].is_ujump)
57871462 6194 {
6195 // Unconditional branch
6196 u=unneeded_reg[(ba[i]-start)>>2];
bedfea38 6197 gte_u=gte_unneeded[(ba[i]-start)>>2];
57871462 6198 branch_unneeded_reg[i]=u;
57871462 6199 // Merge in delay slot
cf95b4f0 6200 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6201 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
00fa9369 6202 u|=1;
bedfea38 6203 gte_u|=gte_rt[i+1];
6204 gte_u&=~gte_rs[i+1];
57871462 6205 } else {
6206 // Conditional branch
6207 b=unneeded_reg[(ba[i]-start)>>2];
00fa9369 6208 gte_b=gte_unneeded[(ba[i]-start)>>2];
57871462 6209 branch_unneeded_reg[i]=b;
57871462 6210 // Branch delay slot
cf95b4f0 6211 b|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6212 b&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
00fa9369 6213 b|=1;
6214 gte_b|=gte_rt[i+1];
6215 gte_b&=~gte_rs[i+1];
fe807a8a 6216 u&=b;
6217 gte_u&=gte_b;
57871462 6218 if(i<slen-1) {
6219 branch_unneeded_reg[i]&=unneeded_reg[i+2];
57871462 6220 } else {
6221 branch_unneeded_reg[i]=1;
57871462 6222 }
6223 }
6224 }
6225 }
6226 }
cf95b4f0 6227 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
57871462 6228 {
6229 // SYSCALL instruction (software interrupt)
6230 u=1;
57871462 6231 }
cf95b4f0 6232 else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
57871462 6233 {
6234 // ERET instruction (return from interrupt)
6235 u=1;
57871462 6236 }
00fa9369 6237 //u=1; // DEBUG
57871462 6238 // Written registers are unneeded
cf95b4f0 6239 u|=1LL<<dops[i].rt1;
6240 u|=1LL<<dops[i].rt2;
bedfea38 6241 gte_u|=gte_rt[i];
57871462 6242 // Accessed registers are needed
cf95b4f0 6243 u&=~(1LL<<dops[i].rs1);
6244 u&=~(1LL<<dops[i].rs2);
bedfea38 6245 gte_u&=~gte_rs[i];
cf95b4f0 6246 if(gte_rs[i]&&dops[i].rt1&&(unneeded_reg[i+1]&(1ll<<dops[i].rt1)))
cbbd8dd7 6247 gte_u|=gte_rs[i]&gte_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded
57871462 6248 // Source-target dependencies
57871462 6249 // R0 is always unneeded
00fa9369 6250 u|=1;
57871462 6251 // Save it
6252 unneeded_reg[i]=u;
bedfea38 6253 gte_unneeded[i]=gte_u;
57871462 6254 /*
6255 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6256 printf("U:");
6257 int r;
6258 for(r=1;r<=CCREG;r++) {
6259 if((unneeded_reg[i]>>r)&1) {
6260 if(r==HIREG) printf(" HI");
6261 else if(r==LOREG) printf(" LO");
6262 else printf(" r%d",r);
6263 }
6264 }
00fa9369 6265 printf("\n");
6266 */
252c20fc 6267 }
57871462 6268}
6269
71e490c5 6270// Write back dirty registers as soon as we will no longer modify them,
6271// so that we don't end up with lots of writes at the branches.
6272void clean_registers(int istart,int iend,int wr)
57871462 6273{
71e490c5 6274 int i;
6275 int r;
6276 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
6277 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
6278 if(iend==slen-1) {
6279 will_dirty_i=will_dirty_next=0;
6280 wont_dirty_i=wont_dirty_next=0;
6281 }else{
6282 will_dirty_i=will_dirty_next=will_dirty[iend+1];
6283 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
6284 }
6285 for (i=iend;i>=istart;i--)
57871462 6286 {
fe807a8a 6287 if(dops[i].is_jump)
57871462 6288 {
71e490c5 6289 if(ba[i]<start || ba[i]>=(start+slen*4))
57871462 6290 {
71e490c5 6291 // Branch out of this block, flush all regs
fe807a8a 6292 if (dops[i].is_ujump)
57871462 6293 {
6294 // Unconditional branch
6295 will_dirty_i=0;
6296 wont_dirty_i=0;
6297 // Merge in delay slot (will dirty)
6298 for(r=0;r<HOST_REGS;r++) {
6299 if(r!=EXCLUDE_REG) {
cf95b4f0 6300 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6301 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6302 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6303 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
57871462 6304 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6305 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6306 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
cf95b4f0 6307 if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6308 if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6309 if((regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6310 if((regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
57871462 6311 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6312 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6313 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6314 }
6315 }
6316 }
6317 else
6318 {
6319 // Conditional branch
6320 will_dirty_i=0;
6321 wont_dirty_i=wont_dirty_next;
6322 // Merge in delay slot (will dirty)
6323 for(r=0;r<HOST_REGS;r++) {
6324 if(r!=EXCLUDE_REG) {
fe807a8a 6325 if (1) { // !dops[i].likely) {
57871462 6326 // Might not dirty if likely branch is not taken
cf95b4f0 6327 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6328 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6329 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6330 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
57871462 6331 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6332 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
6333 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
cf95b4f0 6334 //if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6335 //if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6336 if((regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6337 if((regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
57871462 6338 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6339 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6340 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6341 }
6342 }
6343 }
6344 }
6345 // Merge in delay slot (wont dirty)
6346 for(r=0;r<HOST_REGS;r++) {
6347 if(r!=EXCLUDE_REG) {
cf95b4f0 6348 if((regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6349 if((regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
6350 if((regs[i].regmap[r]&63)==dops[i+1].rt1) wont_dirty_i|=1<<r;
6351 if((regs[i].regmap[r]&63)==dops[i+1].rt2) wont_dirty_i|=1<<r;
57871462 6352 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
cf95b4f0 6353 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6354 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
6355 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) wont_dirty_i|=1<<r;
6356 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) wont_dirty_i|=1<<r;
57871462 6357 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6358 }
6359 }
6360 if(wr) {
6361 #ifndef DESTRUCTIVE_WRITEBACK
6362 branch_regs[i].dirty&=wont_dirty_i;
6363 #endif
6364 branch_regs[i].dirty|=will_dirty_i;
6365 }
6366 }
6367 else
6368 {
6369 // Internal branch
6370 if(ba[i]<=start+i*4) {
6371 // Backward branch
fe807a8a 6372 if (dops[i].is_ujump)
57871462 6373 {
6374 // Unconditional branch
6375 temp_will_dirty=0;
6376 temp_wont_dirty=0;
6377 // Merge in delay slot (will dirty)
6378 for(r=0;r<HOST_REGS;r++) {
6379 if(r!=EXCLUDE_REG) {
cf95b4f0 6380 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) temp_will_dirty|=1<<r;
6381 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) temp_will_dirty|=1<<r;
6382 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) temp_will_dirty|=1<<r;
6383 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) temp_will_dirty|=1<<r;
57871462 6384 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6385 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6386 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
cf95b4f0 6387 if((regs[i].regmap[r]&63)==dops[i].rt1) temp_will_dirty|=1<<r;
6388 if((regs[i].regmap[r]&63)==dops[i].rt2) temp_will_dirty|=1<<r;
6389 if((regs[i].regmap[r]&63)==dops[i+1].rt1) temp_will_dirty|=1<<r;
6390 if((regs[i].regmap[r]&63)==dops[i+1].rt2) temp_will_dirty|=1<<r;
57871462 6391 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6392 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6393 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6394 }
6395 }
6396 } else {
6397 // Conditional branch (not taken case)
6398 temp_will_dirty=will_dirty_next;
6399 temp_wont_dirty=wont_dirty_next;
6400 // Merge in delay slot (will dirty)
6401 for(r=0;r<HOST_REGS;r++) {
6402 if(r!=EXCLUDE_REG) {
fe807a8a 6403 if (1) { // !dops[i].likely) {
57871462 6404 // Will not dirty if likely branch is not taken
cf95b4f0 6405 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) temp_will_dirty|=1<<r;
6406 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) temp_will_dirty|=1<<r;
6407 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) temp_will_dirty|=1<<r;
6408 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) temp_will_dirty|=1<<r;
57871462 6409 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6410 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
6411 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
cf95b4f0 6412 //if((regs[i].regmap[r]&63)==dops[i].rt1) temp_will_dirty|=1<<r;
6413 //if((regs[i].regmap[r]&63)==dops[i].rt2) temp_will_dirty|=1<<r;
6414 if((regs[i].regmap[r]&63)==dops[i+1].rt1) temp_will_dirty|=1<<r;
6415 if((regs[i].regmap[r]&63)==dops[i+1].rt2) temp_will_dirty|=1<<r;
57871462 6416 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6417 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6418 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6419 }
6420 }
6421 }
6422 }
6423 // Merge in delay slot (wont dirty)
6424 for(r=0;r<HOST_REGS;r++) {
6425 if(r!=EXCLUDE_REG) {
cf95b4f0 6426 if((regs[i].regmap[r]&63)==dops[i].rt1) temp_wont_dirty|=1<<r;
6427 if((regs[i].regmap[r]&63)==dops[i].rt2) temp_wont_dirty|=1<<r;
6428 if((regs[i].regmap[r]&63)==dops[i+1].rt1) temp_wont_dirty|=1<<r;
6429 if((regs[i].regmap[r]&63)==dops[i+1].rt2) temp_wont_dirty|=1<<r;
57871462 6430 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
cf95b4f0 6431 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) temp_wont_dirty|=1<<r;
6432 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) temp_wont_dirty|=1<<r;
6433 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) temp_wont_dirty|=1<<r;
6434 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) temp_wont_dirty|=1<<r;
57871462 6435 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
6436 }
6437 }
6438 // Deal with changed mappings
6439 if(i<iend) {
6440 for(r=0;r<HOST_REGS;r++) {
6441 if(r!=EXCLUDE_REG) {
6442 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
6443 temp_will_dirty&=~(1<<r);
6444 temp_wont_dirty&=~(1<<r);
6445 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
6446 temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6447 temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6448 } else {
6449 temp_will_dirty|=1<<r;
6450 temp_wont_dirty|=1<<r;
6451 }
6452 }
6453 }
6454 }
6455 }
6456 if(wr) {
6457 will_dirty[i]=temp_will_dirty;
6458 wont_dirty[i]=temp_wont_dirty;
6459 clean_registers((ba[i]-start)>>2,i-1,0);
6460 }else{
6461 // Limit recursion. It can take an excessive amount
6462 // of time if there are a lot of nested loops.
6463 will_dirty[(ba[i]-start)>>2]=0;
6464 wont_dirty[(ba[i]-start)>>2]=-1;
6465 }
6466 }
6467 /*else*/ if(1)
6468 {
fe807a8a 6469 if (dops[i].is_ujump)
57871462 6470 {
6471 // Unconditional branch
6472 will_dirty_i=0;
6473 wont_dirty_i=0;
6474 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
6475 for(r=0;r<HOST_REGS;r++) {
6476 if(r!=EXCLUDE_REG) {
6477 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
6478 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
6479 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
6480 }
e3234ecf 6481 if(branch_regs[i].regmap[r]>=0) {
6482 will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
6483 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
6484 }
57871462 6485 }
6486 }
6487 //}
6488 // Merge in delay slot
6489 for(r=0;r<HOST_REGS;r++) {
6490 if(r!=EXCLUDE_REG) {
cf95b4f0 6491 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6492 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6493 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6494 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
57871462 6495 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6496 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6497 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
cf95b4f0 6498 if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6499 if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6500 if((regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6501 if((regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
57871462 6502 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6503 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6504 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6505 }
6506 }
6507 } else {
6508 // Conditional branch
6509 will_dirty_i=will_dirty_next;
6510 wont_dirty_i=wont_dirty_next;
6511 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
6512 for(r=0;r<HOST_REGS;r++) {
6513 if(r!=EXCLUDE_REG) {
e3234ecf 6514 signed char target_reg=branch_regs[i].regmap[r];
6515 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
57871462 6516 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
6517 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
6518 }
e3234ecf 6519 else if(target_reg>=0) {
6520 will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
6521 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
57871462 6522 }
57871462 6523 }
6524 }
6525 //}
6526 // Merge in delay slot
6527 for(r=0;r<HOST_REGS;r++) {
6528 if(r!=EXCLUDE_REG) {
fe807a8a 6529 if (1) { // !dops[i].likely) {
57871462 6530 // Might not dirty if likely branch is not taken
cf95b4f0 6531 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6532 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6533 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6534 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
57871462 6535 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6536 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6537 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
cf95b4f0 6538 //if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6539 //if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6540 if((regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6541 if((regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
57871462 6542 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6543 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6544 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6545 }
6546 }
6547 }
6548 }
e3234ecf 6549 // Merge in delay slot (won't dirty)
57871462 6550 for(r=0;r<HOST_REGS;r++) {
6551 if(r!=EXCLUDE_REG) {
cf95b4f0 6552 if((regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6553 if((regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
6554 if((regs[i].regmap[r]&63)==dops[i+1].rt1) wont_dirty_i|=1<<r;
6555 if((regs[i].regmap[r]&63)==dops[i+1].rt2) wont_dirty_i|=1<<r;
57871462 6556 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
cf95b4f0 6557 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6558 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
6559 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) wont_dirty_i|=1<<r;
6560 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) wont_dirty_i|=1<<r;
57871462 6561 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6562 }
6563 }
6564 if(wr) {
6565 #ifndef DESTRUCTIVE_WRITEBACK
6566 branch_regs[i].dirty&=wont_dirty_i;
6567 #endif
6568 branch_regs[i].dirty|=will_dirty_i;
6569 }
6570 }
6571 }
6572 }
cf95b4f0 6573 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
57871462 6574 {
6575 // SYSCALL instruction (software interrupt)
6576 will_dirty_i=0;
6577 wont_dirty_i=0;
6578 }
cf95b4f0 6579 else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
57871462 6580 {
6581 // ERET instruction (return from interrupt)
6582 will_dirty_i=0;
6583 wont_dirty_i=0;
6584 }
6585 will_dirty_next=will_dirty_i;
6586 wont_dirty_next=wont_dirty_i;
6587 for(r=0;r<HOST_REGS;r++) {
6588 if(r!=EXCLUDE_REG) {
cf95b4f0 6589 if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6590 if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
57871462 6591 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6592 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6593 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
cf95b4f0 6594 if((regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6595 if((regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
57871462 6596 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6597 if(i>istart) {
fe807a8a 6598 if (!dops[i].is_jump)
57871462 6599 {
6600 // Don't store a register immediately after writing it,
6601 // may prevent dual-issue.
cf95b4f0 6602 if((regs[i].regmap[r]&63)==dops[i-1].rt1) wont_dirty_i|=1<<r;
6603 if((regs[i].regmap[r]&63)==dops[i-1].rt2) wont_dirty_i|=1<<r;
57871462 6604 }
6605 }
6606 }
6607 }
6608 // Save it
6609 will_dirty[i]=will_dirty_i;
6610 wont_dirty[i]=wont_dirty_i;
6611 // Mark registers that won't be dirtied as not dirty
6612 if(wr) {
57871462 6613 regs[i].dirty|=will_dirty_i;
6614 #ifndef DESTRUCTIVE_WRITEBACK
6615 regs[i].dirty&=wont_dirty_i;
fe807a8a 6616 if(dops[i].is_jump)
57871462 6617 {
fe807a8a 6618 if (i < iend-1 && !dops[i].is_ujump) {
57871462 6619 for(r=0;r<HOST_REGS;r++) {
6620 if(r!=EXCLUDE_REG) {
6621 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
6622 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
581335b0 6623 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
57871462 6624 }
6625 }
6626 }
6627 }
6628 else
6629 {
6630 if(i<iend) {
6631 for(r=0;r<HOST_REGS;r++) {
6632 if(r!=EXCLUDE_REG) {
6633 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
6634 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
581335b0 6635 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
57871462 6636 }
6637 }
6638 }
6639 }
6640 #endif
6641 //}
6642 }
6643 // Deal with changed mappings
6644 temp_will_dirty=will_dirty_i;
6645 temp_wont_dirty=wont_dirty_i;
6646 for(r=0;r<HOST_REGS;r++) {
6647 if(r!=EXCLUDE_REG) {
6648 int nr;
6649 if(regs[i].regmap[r]==regmap_pre[i][r]) {
6650 if(wr) {
6651 #ifndef DESTRUCTIVE_WRITEBACK
6652 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
6653 #endif
6654 regs[i].wasdirty|=will_dirty_i&(1<<r);
6655 }
6656 }
f776eb14 6657 else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
57871462 6658 // Register moved to a different register
6659 will_dirty_i&=~(1<<r);
6660 wont_dirty_i&=~(1<<r);
6661 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
6662 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
6663 if(wr) {
6664 #ifndef DESTRUCTIVE_WRITEBACK
6665 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
6666 #endif
6667 regs[i].wasdirty|=will_dirty_i&(1<<r);
6668 }
6669 }
6670 else {
6671 will_dirty_i&=~(1<<r);
6672 wont_dirty_i&=~(1<<r);
6673 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
6674 will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6675 wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6676 } else {
6677 wont_dirty_i|=1<<r;
581335b0 6678 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);assert(!((will_dirty>>r)&1));*/
57871462 6679 }
6680 }
6681 }
6682 }
6683 }
6684}
6685
4600ba03 6686#ifdef DISASM
57871462 6687 /* disassembly */
6688void disassemble_inst(int i)
6689{
cf95b4f0 6690 if (dops[i].bt) printf("*"); else printf(" ");
6691 switch(dops[i].itype) {
57871462 6692 case UJUMP:
6693 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
6694 case CJUMP:
cf95b4f0 6695 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2,i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
57871462 6696 case SJUMP:
cf95b4f0 6697 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
57871462 6698 case RJUMP:
cf95b4f0 6699 if (dops[i].opcode==0x9&&dops[i].rt1!=31)
6700 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1);
5067f341 6701 else
cf95b4f0 6702 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
5067f341 6703 break;
57871462 6704 case SPAN:
cf95b4f0 6705 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2,ba[i]);break;
57871462 6706 case IMM16:
cf95b4f0 6707 if(dops[i].opcode==0xf) //LUI
6708 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],dops[i].rt1,imm[i]&0xffff);
57871462 6709 else
cf95b4f0 6710 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
57871462 6711 break;
6712 case LOAD:
6713 case LOADLR:
cf95b4f0 6714 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
57871462 6715 break;
6716 case STORE:
6717 case STORELR:
cf95b4f0 6718 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rs2,dops[i].rs1,imm[i]);
57871462 6719 break;
6720 case ALU:
6721 case SHIFT:
cf95b4f0 6722 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,dops[i].rs2);
57871462 6723 break;
6724 case MULTDIV:
cf95b4f0 6725 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2);
57871462 6726 break;
6727 case SHIFTIMM:
cf95b4f0 6728 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
57871462 6729 break;
6730 case MOV:
cf95b4f0 6731 if((dops[i].opcode2&0x1d)==0x10)
6732 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rt1);
6733 else if((dops[i].opcode2&0x1d)==0x11)
6734 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
57871462 6735 else
6736 printf (" %x: %s\n",start+i*4,insn[i]);
6737 break;
6738 case COP0:
cf95b4f0 6739 if(dops[i].opcode2==0)
6740 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC0
6741 else if(dops[i].opcode2==4)
6742 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC0
57871462 6743 else printf (" %x: %s\n",start+i*4,insn[i]);
6744 break;
6745 case COP1:
cf95b4f0 6746 if(dops[i].opcode2<3)
6747 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC1
6748 else if(dops[i].opcode2>3)
6749 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC1
57871462 6750 else printf (" %x: %s\n",start+i*4,insn[i]);
6751 break;
b9b61529 6752 case COP2:
cf95b4f0 6753 if(dops[i].opcode2<3)
6754 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC2
6755 else if(dops[i].opcode2>3)
6756 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC2
b9b61529 6757 else printf (" %x: %s\n",start+i*4,insn[i]);
6758 break;
57871462 6759 case C1LS:
cf95b4f0 6760 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,imm[i]);
57871462 6761 break;
b9b61529 6762 case C2LS:
cf95b4f0 6763 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,imm[i]);
b9b61529 6764 break;
1e973cb0 6765 case INTCALL:
6766 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
6767 break;
57871462 6768 default:
6769 //printf (" %s %8x\n",insn[i],source[i]);
6770 printf (" %x: %s\n",start+i*4,insn[i]);
6771 }
6772}
4600ba03 6773#else
6774static void disassemble_inst(int i) {}
6775#endif // DISASM
57871462 6776
d848b60a 6777#define DRC_TEST_VAL 0x74657374
6778
be516ebe 6779static void new_dynarec_test(void)
d848b60a 6780{
be516ebe 6781 int (*testfunc)(void);
d148d265 6782 void *beginning;
be516ebe 6783 int ret[2];
6784 size_t i;
d148d265 6785
687b4580 6786 // check structure linkage
7c3a5182 6787 if ((u_char *)rcnts - (u_char *)&psxRegs != sizeof(psxRegs))
687b4580 6788 {
7c3a5182 6789 SysPrintf("linkage_arm* miscompilation/breakage detected.\n");
687b4580 6790 }
6791
be516ebe 6792 SysPrintf("testing if we can run recompiled code...\n");
6793 ((volatile u_int *)out)[0]++; // make cache dirty
6794
6795 for (i = 0; i < ARRAY_SIZE(ret); i++) {
2a014d73 6796 out = ndrc->translation_cache;
be516ebe 6797 beginning = start_block();
6798 emit_movimm(DRC_TEST_VAL + i, 0); // test
6799 emit_ret();
6800 literal_pool(0);
6801 end_block(beginning);
6802 testfunc = beginning;
6803 ret[i] = testfunc();
6804 }
6805
6806 if (ret[0] == DRC_TEST_VAL && ret[1] == DRC_TEST_VAL + 1)
d848b60a 6807 SysPrintf("test passed.\n");
6808 else
be516ebe 6809 SysPrintf("test failed, will likely crash soon (r=%08x %08x)\n", ret[0], ret[1]);
2a014d73 6810 out = ndrc->translation_cache;
d848b60a 6811}
6812
dc990066 6813// clear the state completely, instead of just marking
6814// things invalid like invalidate_all_pages() does
919981d0 6815void new_dynarec_clear_full(void)
57871462 6816{
57871462 6817 int n;
2a014d73 6818 out = ndrc->translation_cache;
35775df7 6819 memset(invalid_code,1,sizeof(invalid_code));
6820 memset(hash_table,0xff,sizeof(hash_table));
57871462 6821 memset(mini_ht,-1,sizeof(mini_ht));
6822 memset(restore_candidate,0,sizeof(restore_candidate));
dc990066 6823 memset(shadow,0,sizeof(shadow));
57871462 6824 copy=shadow;
6825 expirep=16384; // Expiry pointer, +2 blocks
6826 pending_exception=0;
6827 literalcount=0;
57871462 6828 stop_after_jal=0;
9be4ba64 6829 inv_code_start=inv_code_end=~0;
39b71d9a 6830 f1_hack=0;
57871462 6831 // TLB
dc990066 6832 for(n=0;n<4096;n++) ll_clear(jump_in+n);
6833 for(n=0;n<4096;n++) ll_clear(jump_out+n);
6834 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
32631e6a 6835
6836 cycle_multiplier_old = cycle_multiplier;
6837 new_dynarec_hacks_old = new_dynarec_hacks;
dc990066 6838}
6839
919981d0 6840void new_dynarec_init(void)
dc990066 6841{
d848b60a 6842 SysPrintf("Init new dynarec\n");
1e212a25 6843
2a014d73 6844#ifdef BASE_ADDR_DYNAMIC
1e212a25 6845 #ifdef VITA
6846 sceBlock = sceKernelAllocMemBlockForVM("code", 1 << TARGET_SIZE_2);
6847 if (sceBlock < 0)
6848 SysPrintf("sceKernelAllocMemBlockForVM failed\n");
2a014d73 6849 int ret = sceKernelGetMemBlockBase(sceBlock, (void **)&ndrc);
1e212a25 6850 if (ret < 0)
6851 SysPrintf("sceKernelGetMemBlockBase failed\n");
6852 #else
2a014d73 6853 uintptr_t desired_addr = 0;
6854 #ifdef __ELF__
6855 extern char _end;
6856 desired_addr = ((uintptr_t)&_end + 0xffffff) & ~0xffffffl;
6857 #endif
6858 ndrc = mmap((void *)desired_addr, sizeof(*ndrc),
1e212a25 6859 PROT_READ | PROT_WRITE | PROT_EXEC,
6860 MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
2a014d73 6861 if (ndrc == MAP_FAILED) {
d848b60a 6862 SysPrintf("mmap() failed: %s\n", strerror(errno));
1e212a25 6863 abort();
d848b60a 6864 }
1e212a25 6865 #endif
6866#else
6867 #ifndef NO_WRITE_EXEC
bdeade46 6868 // not all systems allow execute in data segment by default
2a014d73 6869 if (mprotect(ndrc, sizeof(ndrc->translation_cache) + sizeof(ndrc->tramp.ops),
6870 PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
d848b60a 6871 SysPrintf("mprotect() failed: %s\n", strerror(errno));
1e212a25 6872 #endif
dc990066 6873#endif
2a014d73 6874 out = ndrc->translation_cache;
2573466a 6875 cycle_multiplier=200;
dc990066 6876 new_dynarec_clear_full();
6877#ifdef HOST_IMM8
6878 // Copy this into local area so we don't have to put it in every literal pool
6879 invc_ptr=invalid_code;
6880#endif
57871462 6881 arch_init();
d848b60a 6882 new_dynarec_test();
01d26796 6883 ram_offset=(uintptr_t)rdram-0x80000000;
b105cf4f 6884 if (ram_offset!=0)
c43b5311 6885 SysPrintf("warning: RAM is not directly mapped, performance will suffer\n");
57871462 6886}
6887
919981d0 6888void new_dynarec_cleanup(void)
57871462 6889{
6890 int n;
2a014d73 6891#ifdef BASE_ADDR_DYNAMIC
1e212a25 6892 #ifdef VITA
6893 sceKernelFreeMemBlock(sceBlock);
6894 sceBlock = -1;
6895 #else
2a014d73 6896 if (munmap(ndrc, sizeof(*ndrc)) < 0)
1e212a25 6897 SysPrintf("munmap() failed\n");
bdeade46 6898 #endif
1e212a25 6899#endif
57871462 6900 for(n=0;n<4096;n++) ll_clear(jump_in+n);
6901 for(n=0;n<4096;n++) ll_clear(jump_out+n);
6902 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
6903 #ifdef ROM_COPY
c43b5311 6904 if (munmap (ROM_COPY, 67108864) < 0) {SysPrintf("munmap() failed\n");}
57871462 6905 #endif
6906}
6907
03f55e6b 6908static u_int *get_source_start(u_int addr, u_int *limit)
57871462 6909{
d62c125a 6910 if (!HACK_ENABLED(NDHACK_OVERRIDE_CYCLE_M))
a3203cf4 6911 cycle_multiplier_override = 0;
6912
03f55e6b 6913 if (addr < 0x00200000 ||
a3203cf4 6914 (0xa0000000 <= addr && addr < 0xa0200000))
6915 {
03f55e6b 6916 // used for BIOS calls mostly?
6917 *limit = (addr&0xa0000000)|0x00200000;
01d26796 6918 return (u_int *)(rdram + (addr&0x1fffff));
03f55e6b 6919 }
6920 else if (!Config.HLE && (
6921 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
a3203cf4 6922 (0xbfc00000 <= addr && addr < 0xbfc80000)))
6923 {
6924 // BIOS. The multiplier should be much higher as it's uncached 8bit mem,
6925 // but timings in PCSX are too tied to the interpreter's BIAS
d62c125a 6926 if (!HACK_ENABLED(NDHACK_OVERRIDE_CYCLE_M))
a3203cf4 6927 cycle_multiplier_override = 200;
6928
03f55e6b 6929 *limit = (addr & 0xfff00000) | 0x80000;
01d26796 6930 return (u_int *)((u_char *)psxR + (addr&0x7ffff));
03f55e6b 6931 }
6932 else if (addr >= 0x80000000 && addr < 0x80000000+RAM_SIZE) {
6933 *limit = (addr & 0x80600000) + 0x00200000;
01d26796 6934 return (u_int *)(rdram + (addr&0x1fffff));
03f55e6b 6935 }
581335b0 6936 return NULL;
03f55e6b 6937}
6938
6939static u_int scan_for_ret(u_int addr)
6940{
6941 u_int limit = 0;
6942 u_int *mem;
6943
6944 mem = get_source_start(addr, &limit);
6945 if (mem == NULL)
6946 return addr;
6947
6948 if (limit > addr + 0x1000)
6949 limit = addr + 0x1000;
6950 for (; addr < limit; addr += 4, mem++) {
6951 if (*mem == 0x03e00008) // jr $ra
6952 return addr + 8;
57871462 6953 }
581335b0 6954 return addr;
03f55e6b 6955}
6956
6957struct savestate_block {
6958 uint32_t addr;
6959 uint32_t regflags;
6960};
6961
6962static int addr_cmp(const void *p1_, const void *p2_)
6963{
6964 const struct savestate_block *p1 = p1_, *p2 = p2_;
6965 return p1->addr - p2->addr;
6966}
6967
6968int new_dynarec_save_blocks(void *save, int size)
6969{
6970 struct savestate_block *blocks = save;
6971 int maxcount = size / sizeof(blocks[0]);
6972 struct savestate_block tmp_blocks[1024];
6973 struct ll_entry *head;
6974 int p, s, d, o, bcnt;
6975 u_int addr;
6976
6977 o = 0;
b14b6a8f 6978 for (p = 0; p < ARRAY_SIZE(jump_in); p++) {
03f55e6b 6979 bcnt = 0;
6980 for (head = jump_in[p]; head != NULL; head = head->next) {
6981 tmp_blocks[bcnt].addr = head->vaddr;
6982 tmp_blocks[bcnt].regflags = head->reg_sv_flags;
6983 bcnt++;
6984 }
6985 if (bcnt < 1)
6986 continue;
6987 qsort(tmp_blocks, bcnt, sizeof(tmp_blocks[0]), addr_cmp);
6988
6989 addr = tmp_blocks[0].addr;
6990 for (s = d = 0; s < bcnt; s++) {
6991 if (tmp_blocks[s].addr < addr)
6992 continue;
6993 if (d == 0 || tmp_blocks[d-1].addr != tmp_blocks[s].addr)
6994 tmp_blocks[d++] = tmp_blocks[s];
6995 addr = scan_for_ret(tmp_blocks[s].addr);
6996 }
6997
6998 if (o + d > maxcount)
6999 d = maxcount - o;
7000 memcpy(&blocks[o], tmp_blocks, d * sizeof(blocks[0]));
7001 o += d;
7002 }
7003
7004 return o * sizeof(blocks[0]);
7005}
7006
7007void new_dynarec_load_blocks(const void *save, int size)
7008{
7009 const struct savestate_block *blocks = save;
7010 int count = size / sizeof(blocks[0]);
7011 u_int regs_save[32];
7012 uint32_t f;
7013 int i, b;
7014
7015 get_addr(psxRegs.pc);
7016
7017 // change GPRs for speculation to at least partially work..
7018 memcpy(regs_save, &psxRegs.GPR, sizeof(regs_save));
7019 for (i = 1; i < 32; i++)
7020 psxRegs.GPR.r[i] = 0x80000000;
7021
7022 for (b = 0; b < count; b++) {
7023 for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) {
7024 if (f & 1)
7025 psxRegs.GPR.r[i] = 0x1f800000;
7026 }
7027
7028 get_addr(blocks[b].addr);
7029
7030 for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) {
7031 if (f & 1)
7032 psxRegs.GPR.r[i] = 0x80000000;
7033 }
7034 }
7035
7036 memcpy(&psxRegs.GPR, regs_save, sizeof(regs_save));
7037}
7038
3968e69e 7039int new_recompile_block(u_int addr)
03f55e6b 7040{
7041 u_int pagelimit = 0;
7042 u_int state_rflags = 0;
7043 int i;
7044
1a4301c4 7045 assem_debug("NOTCOMPILED: addr = %x -> %p\n", addr, out);
57871462 7046 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
9f51b4b9 7047 //if(debug)
57871462 7048 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
03f55e6b 7049
7050 // this is just for speculation
7051 for (i = 1; i < 32; i++) {
7052 if ((psxRegs.GPR.r[i] & 0xffff0000) == 0x1f800000)
7053 state_rflags |= 1 << i;
7054 }
7055
57871462 7056 start = (u_int)addr&~3;
7c3a5182 7057 //assert(((u_int)addr&1)==0); // start-in-delay-slot flag
2f546f9a 7058 new_dynarec_did_compile=1;
9ad4d757 7059 if (Config.HLE && start == 0x80001000) // hlecall
560e4a12 7060 {
7139f3c8 7061 // XXX: is this enough? Maybe check hleSoftCall?
d148d265 7062 void *beginning=start_block();
7139f3c8 7063 u_int page=get_page(start);
d148d265 7064
7139f3c8 7065 invalid_code[start>>12]=0;
7066 emit_movimm(start,0);
643aeae3 7067 emit_writeword(0,&pcaddr);
2a014d73 7068 emit_far_jump(new_dyna_leave);
15776b68 7069 literal_pool(0);
d148d265 7070 end_block(beginning);
03f55e6b 7071 ll_add_flags(jump_in+page,start,state_rflags,(void *)beginning);
7139f3c8 7072 return 0;
7073 }
39b71d9a 7074 else if (f1_hack == ~0u || (f1_hack != 0 && start == f1_hack)) {
7075 void *beginning = start_block();
7076 u_int page = get_page(start);
7077 emit_readword(&psxRegs.GPR.n.sp, 0);
7078 emit_readptr(&mem_rtab, 1);
7079 emit_shrimm(0, 12, 2);
7080 emit_readptr_dualindexedx_ptrlen(1, 2, 1);
7081 emit_addimm(0, 0x18, 0);
7082 emit_adds_ptr(1, 1, 1);
7083 emit_ldr_dualindexed(1, 0, 0);
7084 emit_writeword(0, &psxRegs.GPR.r[26]); // lw k0, 0x18(sp)
7085 emit_far_call(get_addr_ht);
7086 emit_jmpreg(0); // jr k0
7087 literal_pool(0);
7088 end_block(beginning);
7089
7090 ll_add_flags(jump_in + page, start, state_rflags, beginning);
7091 SysPrintf("F1 hack to %08x\n", start);
7092 f1_hack = start;
7093 return 0;
7094 }
03f55e6b 7095
7096 source = get_source_start(start, &pagelimit);
7097 if (source == NULL) {
7098 SysPrintf("Compile at bogus memory address: %08x\n", addr);
7c3a5182 7099 abort();
57871462 7100 }
7101
7102 /* Pass 1: disassemble */
7103 /* Pass 2: register dependencies, branch targets */
7104 /* Pass 3: register allocation */
7105 /* Pass 4: branch dependencies */
7106 /* Pass 5: pre-alloc */
7107 /* Pass 6: optimize clean/dirty state */
7108 /* Pass 7: flag 32-bit registers */
7109 /* Pass 8: assembly */
7110 /* Pass 9: linker */
7111 /* Pass 10: garbage collection / free memory */
7112
03f55e6b 7113 int j;
57871462 7114 int done=0;
7115 unsigned int type,op,op2;
7116
7117 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
9f51b4b9 7118
57871462 7119 /* Pass 1 disassembly */
7120
7121 for(i=0;!done;i++) {
cf95b4f0 7122 dops[i].bt=0;
cf95b4f0 7123 dops[i].ooo=0;
7124 op2=0;
e1190b87 7125 minimum_free_regs[i]=0;
cf95b4f0 7126 dops[i].opcode=op=source[i]>>26;
57871462 7127 switch(op)
7128 {
7129 case 0x00: strcpy(insn[i],"special"); type=NI;
7130 op2=source[i]&0x3f;
7131 switch(op2)
7132 {
7133 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
7134 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
7135 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
7136 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
7137 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
7138 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
7139 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
7140 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
7141 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
7142 case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
7143 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
7144 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
7145 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
7146 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
7147 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
57871462 7148 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
7149 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
7150 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
7151 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
57871462 7152 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
7153 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
7154 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
7155 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
7156 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
7157 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
7158 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
7159 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
7160 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
7161 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
57871462 7162 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
7163 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
7164 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
7165 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
7166 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
7167 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
71e490c5 7168#if 0
7f2607ea 7169 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
7170 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
7171 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
7172 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
7173 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
7174 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
7175 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
7176 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
7177 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
7178 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
7179 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
57871462 7180 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
7181 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
7182 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
7183 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
7184 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
7185 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
7f2607ea 7186#endif
57871462 7187 }
7188 break;
7189 case 0x01: strcpy(insn[i],"regimm"); type=NI;
7190 op2=(source[i]>>16)&0x1f;
7191 switch(op2)
7192 {
7193 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
7194 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
4919de1e 7195 //case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
7196 //case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
7197 //case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
7198 //case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
7199 //case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
7200 //case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
7201 //case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
7202 //case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
57871462 7203 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
7204 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
4919de1e 7205 //case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
7206 //case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
57871462 7207 }
7208 break;
7209 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
7210 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
7211 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
7212 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
7213 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
7214 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
7215 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
7216 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
7217 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
7218 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
7219 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
7220 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
7221 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
7222 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
7223 case 0x10: strcpy(insn[i],"cop0"); type=NI;
7224 op2=(source[i]>>21)&0x1f;
7225 switch(op2)
7226 {
7227 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
00fa9369 7228 case 0x02: strcpy(insn[i],"CFC0"); type=COP0; break;
57871462 7229 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
00fa9369 7230 case 0x06: strcpy(insn[i],"CTC0"); type=COP0; break;
7231 case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
57871462 7232 }
7233 break;
00fa9369 7234 case 0x11: strcpy(insn[i],"cop1"); type=COP1;
57871462 7235 op2=(source[i]>>21)&0x1f;
57871462 7236 break;
71e490c5 7237#if 0
57871462 7238 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
7239 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
7240 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
7241 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
7242 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
7243 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
7244 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
7245 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
996cc15d 7246#endif
57871462 7247 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
7248 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
7249 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
7250 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
7251 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
7252 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
7253 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
71e490c5 7254#if 0
57871462 7255 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
64bd6f82 7256#endif
57871462 7257 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
7258 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
7259 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
7260 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
71e490c5 7261#if 0
57871462 7262 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
7263 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
996cc15d 7264#endif
57871462 7265 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
7266 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
7267 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
7268 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
71e490c5 7269#if 0
57871462 7270 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
7271 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
7272 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
996cc15d 7273#endif
57871462 7274 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
7275 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
71e490c5 7276#if 0
57871462 7277 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
7278 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
7279 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
996cc15d 7280#endif
b9b61529 7281 case 0x12: strcpy(insn[i],"COP2"); type=NI;
7282 op2=(source[i]>>21)&0x1f;
be516ebe 7283 //if (op2 & 0x10)
bedfea38 7284 if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
c7abc864 7285 if (gte_handlers[source[i]&0x3f]!=NULL) {
bedfea38 7286 if (gte_regnames[source[i]&0x3f]!=NULL)
7287 strcpy(insn[i],gte_regnames[source[i]&0x3f]);
7288 else
7289 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
c7abc864 7290 type=C2OP;
7291 }
7292 }
7293 else switch(op2)
b9b61529 7294 {
7295 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
7296 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
7297 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
7298 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
b9b61529 7299 }
7300 break;
7301 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
7302 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
7303 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
90ae6d4e 7304 default: strcpy(insn[i],"???"); type=NI;
c43b5311 7305 SysPrintf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
90ae6d4e 7306 break;
57871462 7307 }
cf95b4f0 7308 dops[i].itype=type;
7309 dops[i].opcode2=op2;
57871462 7310 /* Get registers/immediates */
cf95b4f0 7311 dops[i].lt1=0;
bedfea38 7312 gte_rs[i]=gte_rt[i]=0;
57871462 7313 switch(type) {
7314 case LOAD:
cf95b4f0 7315 dops[i].rs1=(source[i]>>21)&0x1f;
7316 dops[i].rs2=0;
7317 dops[i].rt1=(source[i]>>16)&0x1f;
7318 dops[i].rt2=0;
57871462 7319 imm[i]=(short)source[i];
7320 break;
7321 case STORE:
7322 case STORELR:
cf95b4f0 7323 dops[i].rs1=(source[i]>>21)&0x1f;
7324 dops[i].rs2=(source[i]>>16)&0x1f;
7325 dops[i].rt1=0;
7326 dops[i].rt2=0;
57871462 7327 imm[i]=(short)source[i];
57871462 7328 break;
7329 case LOADLR:
7330 // LWL/LWR only load part of the register,
7331 // therefore the target register must be treated as a source too
cf95b4f0 7332 dops[i].rs1=(source[i]>>21)&0x1f;
7333 dops[i].rs2=(source[i]>>16)&0x1f;
7334 dops[i].rt1=(source[i]>>16)&0x1f;
7335 dops[i].rt2=0;
57871462 7336 imm[i]=(short)source[i];
57871462 7337 break;
7338 case IMM16:
cf95b4f0 7339 if (op==0x0f) dops[i].rs1=0; // LUI instruction has no source register
7340 else dops[i].rs1=(source[i]>>21)&0x1f;
7341 dops[i].rs2=0;
7342 dops[i].rt1=(source[i]>>16)&0x1f;
7343 dops[i].rt2=0;
57871462 7344 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
7345 imm[i]=(unsigned short)source[i];
7346 }else{
7347 imm[i]=(short)source[i];
7348 }
57871462 7349 break;
7350 case UJUMP:
cf95b4f0 7351 dops[i].rs1=0;
7352 dops[i].rs2=0;
7353 dops[i].rt1=0;
7354 dops[i].rt2=0;
57871462 7355 // The JAL instruction writes to r31.
7356 if (op&1) {
cf95b4f0 7357 dops[i].rt1=31;
57871462 7358 }
cf95b4f0 7359 dops[i].rs2=CCREG;
57871462 7360 break;
7361 case RJUMP:
cf95b4f0 7362 dops[i].rs1=(source[i]>>21)&0x1f;
7363 dops[i].rs2=0;
7364 dops[i].rt1=0;
7365 dops[i].rt2=0;
5067f341 7366 // The JALR instruction writes to rd.
57871462 7367 if (op2&1) {
cf95b4f0 7368 dops[i].rt1=(source[i]>>11)&0x1f;
57871462 7369 }
cf95b4f0 7370 dops[i].rs2=CCREG;
57871462 7371 break;
7372 case CJUMP:
cf95b4f0 7373 dops[i].rs1=(source[i]>>21)&0x1f;
7374 dops[i].rs2=(source[i]>>16)&0x1f;
7375 dops[i].rt1=0;
7376 dops[i].rt2=0;
57871462 7377 if(op&2) { // BGTZ/BLEZ
cf95b4f0 7378 dops[i].rs2=0;
57871462 7379 }
57871462 7380 break;
7381 case SJUMP:
cf95b4f0 7382 dops[i].rs1=(source[i]>>21)&0x1f;
7383 dops[i].rs2=CCREG;
7384 dops[i].rt1=0;
7385 dops[i].rt2=0;
57871462 7386 if(op2&0x10) { // BxxAL
cf95b4f0 7387 dops[i].rt1=31;
57871462 7388 // NOTE: If the branch is not taken, r31 is still overwritten
7389 }
57871462 7390 break;
57871462 7391 case ALU:
cf95b4f0 7392 dops[i].rs1=(source[i]>>21)&0x1f; // source
7393 dops[i].rs2=(source[i]>>16)&0x1f; // subtract amount
7394 dops[i].rt1=(source[i]>>11)&0x1f; // destination
7395 dops[i].rt2=0;
57871462 7396 break;
7397 case MULTDIV:
cf95b4f0 7398 dops[i].rs1=(source[i]>>21)&0x1f; // source
7399 dops[i].rs2=(source[i]>>16)&0x1f; // divisor
7400 dops[i].rt1=HIREG;
7401 dops[i].rt2=LOREG;
57871462 7402 break;
7403 case MOV:
cf95b4f0 7404 dops[i].rs1=0;
7405 dops[i].rs2=0;
7406 dops[i].rt1=0;
7407 dops[i].rt2=0;
7408 if(op2==0x10) dops[i].rs1=HIREG; // MFHI
7409 if(op2==0x11) dops[i].rt1=HIREG; // MTHI
7410 if(op2==0x12) dops[i].rs1=LOREG; // MFLO
7411 if(op2==0x13) dops[i].rt1=LOREG; // MTLO
7412 if((op2&0x1d)==0x10) dops[i].rt1=(source[i]>>11)&0x1f; // MFxx
7413 if((op2&0x1d)==0x11) dops[i].rs1=(source[i]>>21)&0x1f; // MTxx
57871462 7414 break;
7415 case SHIFT:
cf95b4f0 7416 dops[i].rs1=(source[i]>>16)&0x1f; // target of shift
7417 dops[i].rs2=(source[i]>>21)&0x1f; // shift amount
7418 dops[i].rt1=(source[i]>>11)&0x1f; // destination
7419 dops[i].rt2=0;
57871462 7420 break;
7421 case SHIFTIMM:
cf95b4f0 7422 dops[i].rs1=(source[i]>>16)&0x1f;
7423 dops[i].rs2=0;
7424 dops[i].rt1=(source[i]>>11)&0x1f;
7425 dops[i].rt2=0;
57871462 7426 imm[i]=(source[i]>>6)&0x1f;
7427 // DSxx32 instructions
7428 if(op2>=0x3c) imm[i]|=0x20;
57871462 7429 break;
7430 case COP0:
cf95b4f0 7431 dops[i].rs1=0;
7432 dops[i].rs2=0;
7433 dops[i].rt1=0;
7434 dops[i].rt2=0;
7435 if(op2==0||op2==2) dops[i].rt1=(source[i]>>16)&0x1F; // MFC0/CFC0
7436 if(op2==4||op2==6) dops[i].rs1=(source[i]>>16)&0x1F; // MTC0/CTC0
7437 if(op2==4&&((source[i]>>11)&0x1f)==12) dops[i].rt2=CSREG; // Status
7438 if(op2==16) if((source[i]&0x3f)==0x18) dops[i].rs2=CCREG; // ERET
57871462 7439 break;
7440 case COP1:
cf95b4f0 7441 dops[i].rs1=0;
7442 dops[i].rs2=0;
7443 dops[i].rt1=0;
7444 dops[i].rt2=0;
7445 if(op2<3) dops[i].rt1=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
7446 if(op2>3) dops[i].rs1=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
7447 dops[i].rs2=CSREG;
57871462 7448 break;
bedfea38 7449 case COP2:
cf95b4f0 7450 dops[i].rs1=0;
7451 dops[i].rs2=0;
7452 dops[i].rt1=0;
7453 dops[i].rt2=0;
7454 if(op2<3) dops[i].rt1=(source[i]>>16)&0x1F; // MFC2/CFC2
7455 if(op2>3) dops[i].rs1=(source[i]>>16)&0x1F; // MTC2/CTC2
7456 dops[i].rs2=CSREG;
bedfea38 7457 int gr=(source[i]>>11)&0x1F;
7458 switch(op2)
7459 {
7460 case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
7461 case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
0ff8c62c 7462 case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2
bedfea38 7463 case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
7464 }
7465 break;
57871462 7466 case C1LS:
cf95b4f0 7467 dops[i].rs1=(source[i]>>21)&0x1F;
7468 dops[i].rs2=CSREG;
7469 dops[i].rt1=0;
7470 dops[i].rt2=0;
57871462 7471 imm[i]=(short)source[i];
7472 break;
b9b61529 7473 case C2LS:
cf95b4f0 7474 dops[i].rs1=(source[i]>>21)&0x1F;
7475 dops[i].rs2=0;
7476 dops[i].rt1=0;
7477 dops[i].rt2=0;
b9b61529 7478 imm[i]=(short)source[i];
bedfea38 7479 if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
7480 else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
7481 break;
7482 case C2OP:
cf95b4f0 7483 dops[i].rs1=0;
7484 dops[i].rs2=0;
7485 dops[i].rt1=0;
7486 dops[i].rt2=0;
2167bef6 7487 gte_rs[i]=gte_reg_reads[source[i]&0x3f];
7488 gte_rt[i]=gte_reg_writes[source[i]&0x3f];
7489 gte_rt[i]|=1ll<<63; // every op changes flags
587a5b1c 7490 if((source[i]&0x3f)==GTE_MVMVA) {
7491 int v = (source[i] >> 15) & 3;
7492 gte_rs[i]&=~0xe3fll;
7493 if(v==3) gte_rs[i]|=0xe00ll;
7494 else gte_rs[i]|=3ll<<(v*2);
7495 }
b9b61529 7496 break;
57871462 7497 case SYSCALL:
7139f3c8 7498 case HLECALL:
1e973cb0 7499 case INTCALL:
cf95b4f0 7500 dops[i].rs1=CCREG;
7501 dops[i].rs2=0;
7502 dops[i].rt1=0;
7503 dops[i].rt2=0;
57871462 7504 break;
7505 default:
cf95b4f0 7506 dops[i].rs1=0;
7507 dops[i].rs2=0;
7508 dops[i].rt1=0;
7509 dops[i].rt2=0;
57871462 7510 }
7511 /* Calculate branch target addresses */
7512 if(type==UJUMP)
7513 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
cf95b4f0 7514 else if(type==CJUMP&&dops[i].rs1==dops[i].rs2&&(op&1))
57871462 7515 ba[i]=start+i*4+8; // Ignore never taken branch
cf95b4f0 7516 else if(type==SJUMP&&dops[i].rs1==0&&!(op2&1))
57871462 7517 ba[i]=start+i*4+8; // Ignore never taken branch
ad49de89 7518 else if(type==CJUMP||type==SJUMP)
57871462 7519 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
7520 else ba[i]=-1;
4919de1e 7521
7522 /* simplify always (not)taken branches */
cf95b4f0 7523 if (type == CJUMP && dops[i].rs1 == dops[i].rs2) {
7524 dops[i].rs1 = dops[i].rs2 = 0;
4919de1e 7525 if (!(op & 1)) {
cf95b4f0 7526 dops[i].itype = type = UJUMP;
7527 dops[i].rs2 = CCREG;
4919de1e 7528 }
7529 }
cf95b4f0 7530 else if (type == SJUMP && dops[i].rs1 == 0 && (op2 & 1))
7531 dops[i].itype = type = UJUMP;
4919de1e 7532
fe807a8a 7533 dops[i].is_jump = (dops[i].itype == RJUMP || dops[i].itype == UJUMP || dops[i].itype == CJUMP || dops[i].itype == SJUMP);
7534 dops[i].is_ujump = (dops[i].itype == RJUMP || dops[i].itype == UJUMP); // || (source[i] >> 16) == 0x1000 // beq r0,r0
37387d8b 7535 dops[i].is_load = (dops[i].itype == LOAD || dops[i].itype == LOADLR || op == 0x32); // LWC2
7536 dops[i].is_store = (dops[i].itype == STORE || dops[i].itype == STORELR || op == 0x3a); // SWC2
fe807a8a 7537
4919de1e 7538 /* messy cases to just pass over to the interpreter */
fe807a8a 7539 if (i > 0 && dops[i-1].is_jump) {
3e535354 7540 int do_in_intrp=0;
7541 // branch in delay slot?
fe807a8a 7542 if (dops[i].is_jump) {
3e535354 7543 // don't handle first branch and call interpreter if it's hit
c43b5311 7544 SysPrintf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
3e535354 7545 do_in_intrp=1;
7546 }
7547 // basic load delay detection
cf95b4f0 7548 else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&dops[i].rt1!=0) {
3e535354 7549 int t=(ba[i-1]-start)/4;
cf95b4f0 7550 if(0 <= t && t < i &&(dops[i].rt1==dops[t].rs1||dops[i].rt1==dops[t].rs2)&&dops[t].itype!=CJUMP&&dops[t].itype!=SJUMP) {
3e535354 7551 // jump target wants DS result - potential load delay effect
c43b5311 7552 SysPrintf("load delay @%08x (%08x)\n", addr + i*4, addr);
3e535354 7553 do_in_intrp=1;
cf95b4f0 7554 dops[t+1].bt=1; // expected return from interpreter
3e535354 7555 }
cf95b4f0 7556 else if(i>=2&&dops[i-2].rt1==2&&dops[i].rt1==2&&dops[i].rs1!=2&&dops[i].rs2!=2&&dops[i-1].rs1!=2&&dops[i-1].rs2!=2&&
fe807a8a 7557 !(i>=3&&dops[i-3].is_jump)) {
3e535354 7558 // v0 overwrite like this is a sign of trouble, bail out
c43b5311 7559 SysPrintf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
3e535354 7560 do_in_intrp=1;
7561 }
7562 }
3e535354 7563 if(do_in_intrp) {
cf95b4f0 7564 dops[i-1].rs1=CCREG;
7565 dops[i-1].rs2=dops[i-1].rt1=dops[i-1].rt2=0;
26869094 7566 ba[i-1]=-1;
cf95b4f0 7567 dops[i-1].itype=INTCALL;
26869094 7568 done=2;
3e535354 7569 i--; // don't compile the DS
26869094 7570 }
3e535354 7571 }
4919de1e 7572
3e535354 7573 /* Is this the end of the block? */
fe807a8a 7574 if (i > 0 && dops[i-1].is_ujump) {
cf95b4f0 7575 if(dops[i-1].rt1==0) { // Continue past subroutine call (JAL)
1e973cb0 7576 done=2;
57871462 7577 }
7578 else {
7579 if(stop_after_jal) done=1;
7580 // Stop on BREAK
7581 if((source[i+1]&0xfc00003f)==0x0d) done=1;
7582 }
7583 // Don't recompile stuff that's already compiled
7584 if(check_addr(start+i*4+4)) done=1;
7585 // Don't get too close to the limit
7586 if(i>MAXBLOCK/2) done=1;
7587 }
cf95b4f0 7588 if(dops[i].itype==SYSCALL&&stop_after_jal) done=1;
7589 if(dops[i].itype==HLECALL||dops[i].itype==INTCALL) done=2;
1e973cb0 7590 if(done==2) {
7591 // Does the block continue due to a branch?
7592 for(j=i-1;j>=0;j--)
7593 {
2a706964 7594 if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
1e973cb0 7595 if(ba[j]==start+i*4+4) done=j=0;
7596 if(ba[j]==start+i*4+8) done=j=0;
7597 }
7598 }
75dec299 7599 //assert(i<MAXBLOCK-1);
57871462 7600 if(start+i*4==pagelimit-4) done=1;
7601 assert(start+i*4<pagelimit);
7602 if (i==MAXBLOCK-1) done=1;
7603 // Stop if we're compiling junk
cf95b4f0 7604 if(dops[i].itype==NI&&dops[i].opcode==0x11) {
57871462 7605 done=stop_after_jal=1;
c43b5311 7606 SysPrintf("Disabled speculative precompilation\n");
57871462 7607 }
7608 }
7609 slen=i;
fe807a8a 7610 if (dops[i-1].is_jump) {
57871462 7611 if(start+i*4==pagelimit) {
cf95b4f0 7612 dops[i-1].itype=SPAN;
57871462 7613 }
7614 }
7615 assert(slen>0);
7616
39b71d9a 7617 /* spacial hack(s) */
7618 if (i > 10 && source[i-1] == 0 && source[i-2] == 0x03e00008
7619 && source[i-4] == 0x8fbf0018 && source[i-6] == 0x00c0f809
7620 && dops[i-7].itype == STORE)
7621 {
7622 i = i-8;
7623 if (dops[i].itype == IMM16)
7624 i--;
7625 // swl r2, 15(r6); swr r2, 12(r6); sw r6, *; jalr r6
7626 if (dops[i].itype == STORELR && dops[i].rs1 == 6
7627 && dops[i-1].itype == STORELR && dops[i-1].rs1 == 6)
7628 {
7629 SysPrintf("F1 hack from %08x\n", start);
c979e8c2 7630 if (f1_hack == 0)
7631 f1_hack = ~0u;
39b71d9a 7632 }
7633 }
7634
57871462 7635 /* Pass 2 - Register dependencies and branch targets */
7636
7637 unneeded_registers(0,slen-1,0);
9f51b4b9 7638
57871462 7639 /* Pass 3 - Register allocation */
7640
7641 struct regstat current; // Current register allocations/status
57871462 7642 current.dirty=0;
7643 current.u=unneeded_reg[0];
57871462 7644 clear_all_regs(current.regmap);
7645 alloc_reg(&current,0,CCREG);
7646 dirty_reg(&current,CCREG);
7647 current.isconst=0;
7648 current.wasconst=0;
27727b63 7649 current.waswritten=0;
57871462 7650 int ds=0;
7651 int cc=0;
5194fb95 7652 int hr=-1;
6ebf4adf 7653
57871462 7654 if((u_int)addr&1) {
7655 // First instruction is delay slot
7656 cc=-1;
cf95b4f0 7657 dops[1].bt=1;
57871462 7658 ds=1;
7659 unneeded_reg[0]=1;
57871462 7660 current.regmap[HOST_BTREG]=BTREG;
7661 }
9f51b4b9 7662
57871462 7663 for(i=0;i<slen;i++)
7664 {
cf95b4f0 7665 if(dops[i].bt)
57871462 7666 {
7667 int hr;
7668 for(hr=0;hr<HOST_REGS;hr++)
7669 {
7670 // Is this really necessary?
7671 if(current.regmap[hr]==0) current.regmap[hr]=-1;
7672 }
7673 current.isconst=0;
27727b63 7674 current.waswritten=0;
57871462 7675 }
24385cae 7676
57871462 7677 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
7678 regs[i].wasconst=current.isconst;
57871462 7679 regs[i].wasdirty=current.dirty;
8575a877 7680 regs[i].loadedconst=0;
fe807a8a 7681 if (!dops[i].is_jump) {
57871462 7682 if(i+1<slen) {
cf95b4f0 7683 current.u=unneeded_reg[i+1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7684 current.u|=1;
57871462 7685 } else {
7686 current.u=1;
57871462 7687 }
7688 } else {
7689 if(i+1<slen) {
cf95b4f0 7690 current.u=branch_unneeded_reg[i]&~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7691 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7692 current.u|=1;
7c3a5182 7693 } else { SysPrintf("oops, branch at end of block with no delay slot\n");abort(); }
57871462 7694 }
cf95b4f0 7695 dops[i].is_ds=ds;
57871462 7696 if(ds) {
7697 ds=0; // Skip delay slot, already allocated as part of branch
7698 // ...but we need to alloc it in case something jumps here
7699 if(i+1<slen) {
7700 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
57871462 7701 }else{
7702 current.u=branch_unneeded_reg[i-1];
57871462 7703 }
cf95b4f0 7704 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7705 current.u|=1;
57871462 7706 struct regstat temp;
7707 memcpy(&temp,&current,sizeof(current));
7708 temp.wasdirty=temp.dirty;
57871462 7709 // TODO: Take into account unconditional branches, as below
7710 delayslot_alloc(&temp,i);
7711 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
7712 regs[i].wasdirty=temp.wasdirty;
57871462 7713 regs[i].dirty=temp.dirty;
57871462 7714 regs[i].isconst=0;
7715 regs[i].wasconst=0;
7716 current.isconst=0;
7717 // Create entry (branch target) regmap
7718 for(hr=0;hr<HOST_REGS;hr++)
7719 {
7720 int r=temp.regmap[hr];
7721 if(r>=0) {
7722 if(r!=regmap_pre[i][hr]) {
7723 regs[i].regmap_entry[hr]=-1;
7724 }
7725 else
7726 {
7c3a5182 7727 assert(r < 64);
57871462 7728 if((current.u>>r)&1) {
7729 regs[i].regmap_entry[hr]=-1;
7730 regs[i].regmap[hr]=-1;
7731 //Don't clear regs in the delay slot as the branch might need them
7732 //current.regmap[hr]=-1;
7733 }else
7734 regs[i].regmap_entry[hr]=r;
57871462 7735 }
7736 } else {
7737 // First instruction expects CCREG to be allocated
9f51b4b9 7738 if(i==0&&hr==HOST_CCREG)
57871462 7739 regs[i].regmap_entry[hr]=CCREG;
7740 else
7741 regs[i].regmap_entry[hr]=-1;
7742 }
7743 }
7744 }
7745 else { // Not delay slot
cf95b4f0 7746 switch(dops[i].itype) {
57871462 7747 case UJUMP:
7748 //current.isconst=0; // DEBUG
7749 //current.wasconst=0; // DEBUG
7750 //regs[i].wasconst=0; // DEBUG
cf95b4f0 7751 clear_const(&current,dops[i].rt1);
57871462 7752 alloc_cc(&current,i);
7753 dirty_reg(&current,CCREG);
cf95b4f0 7754 if (dops[i].rt1==31) {
57871462 7755 alloc_reg(&current,i,31);
7756 dirty_reg(&current,31);
cf95b4f0 7757 //assert(dops[i+1].rs1!=31&&dops[i+1].rs2!=31);
7758 //assert(dops[i+1].rt1!=dops[i].rt1);
57871462 7759 #ifdef REG_PREFETCH
7760 alloc_reg(&current,i,PTEMP);
7761 #endif
57871462 7762 }
cf95b4f0 7763 dops[i].ooo=1;
269bb29a 7764 delayslot_alloc(&current,i+1);
57871462 7765 //current.isconst=0; // DEBUG
7766 ds=1;
7767 //printf("i=%d, isconst=%x\n",i,current.isconst);
7768 break;
7769 case RJUMP:
7770 //current.isconst=0;
7771 //current.wasconst=0;
7772 //regs[i].wasconst=0;
cf95b4f0 7773 clear_const(&current,dops[i].rs1);
7774 clear_const(&current,dops[i].rt1);
57871462 7775 alloc_cc(&current,i);
7776 dirty_reg(&current,CCREG);
4919de1e 7777 if (!ds_writes_rjump_rs(i)) {
cf95b4f0 7778 alloc_reg(&current,i,dops[i].rs1);
7779 if (dops[i].rt1!=0) {
7780 alloc_reg(&current,i,dops[i].rt1);
7781 dirty_reg(&current,dops[i].rt1);
7782 assert(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt1);
7783 assert(dops[i+1].rt1!=dops[i].rt1);
57871462 7784 #ifdef REG_PREFETCH
7785 alloc_reg(&current,i,PTEMP);
7786 #endif
7787 }
7788 #ifdef USE_MINI_HT
cf95b4f0 7789 if(dops[i].rs1==31) { // JALR
57871462 7790 alloc_reg(&current,i,RHASH);
57871462 7791 alloc_reg(&current,i,RHTBL);
57871462 7792 }
7793 #endif
7794 delayslot_alloc(&current,i+1);
7795 } else {
7796 // The delay slot overwrites our source register,
7797 // allocate a temporary register to hold the old value.
7798 current.isconst=0;
7799 current.wasconst=0;
7800 regs[i].wasconst=0;
7801 delayslot_alloc(&current,i+1);
7802 current.isconst=0;
7803 alloc_reg(&current,i,RTEMP);
7804 }
7805 //current.isconst=0; // DEBUG
cf95b4f0 7806 dops[i].ooo=1;
57871462 7807 ds=1;
7808 break;
7809 case CJUMP:
7810 //current.isconst=0;
7811 //current.wasconst=0;
7812 //regs[i].wasconst=0;
cf95b4f0 7813 clear_const(&current,dops[i].rs1);
7814 clear_const(&current,dops[i].rs2);
7815 if((dops[i].opcode&0x3E)==4) // BEQ/BNE
57871462 7816 {
7817 alloc_cc(&current,i);
7818 dirty_reg(&current,CCREG);
cf95b4f0 7819 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
7820 if(dops[i].rs2) alloc_reg(&current,i,dops[i].rs2);
7821 if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2))||
7822 (dops[i].rs2&&(dops[i].rs2==dops[i+1].rt1||dops[i].rs2==dops[i+1].rt2))) {
57871462 7823 // The delay slot overwrites one of our conditions.
7824 // Allocate the branch condition registers instead.
57871462 7825 current.isconst=0;
7826 current.wasconst=0;
7827 regs[i].wasconst=0;
cf95b4f0 7828 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
7829 if(dops[i].rs2) alloc_reg(&current,i,dops[i].rs2);
57871462 7830 }
e1190b87 7831 else
7832 {
cf95b4f0 7833 dops[i].ooo=1;
e1190b87 7834 delayslot_alloc(&current,i+1);
7835 }
57871462 7836 }
7837 else
cf95b4f0 7838 if((dops[i].opcode&0x3E)==6) // BLEZ/BGTZ
57871462 7839 {
7840 alloc_cc(&current,i);
7841 dirty_reg(&current,CCREG);
cf95b4f0 7842 alloc_reg(&current,i,dops[i].rs1);
7843 if(dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) {
57871462 7844 // The delay slot overwrites one of our conditions.
7845 // Allocate the branch condition registers instead.
57871462 7846 current.isconst=0;
7847 current.wasconst=0;
7848 regs[i].wasconst=0;
cf95b4f0 7849 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
57871462 7850 }
e1190b87 7851 else
7852 {
cf95b4f0 7853 dops[i].ooo=1;
e1190b87 7854 delayslot_alloc(&current,i+1);
7855 }
57871462 7856 }
7857 else
7858 // Don't alloc the delay slot yet because we might not execute it
cf95b4f0 7859 if((dops[i].opcode&0x3E)==0x14) // BEQL/BNEL
57871462 7860 {
7861 current.isconst=0;
7862 current.wasconst=0;
7863 regs[i].wasconst=0;
7864 alloc_cc(&current,i);
7865 dirty_reg(&current,CCREG);
cf95b4f0 7866 alloc_reg(&current,i,dops[i].rs1);
7867 alloc_reg(&current,i,dops[i].rs2);
57871462 7868 }
7869 else
cf95b4f0 7870 if((dops[i].opcode&0x3E)==0x16) // BLEZL/BGTZL
57871462 7871 {
7872 current.isconst=0;
7873 current.wasconst=0;
7874 regs[i].wasconst=0;
7875 alloc_cc(&current,i);
7876 dirty_reg(&current,CCREG);
cf95b4f0 7877 alloc_reg(&current,i,dops[i].rs1);
57871462 7878 }
7879 ds=1;
7880 //current.isconst=0;
7881 break;
7882 case SJUMP:
7883 //current.isconst=0;
7884 //current.wasconst=0;
7885 //regs[i].wasconst=0;
cf95b4f0 7886 clear_const(&current,dops[i].rs1);
7887 clear_const(&current,dops[i].rt1);
7888 //if((dops[i].opcode2&0x1E)==0x0) // BLTZ/BGEZ
7889 if((dops[i].opcode2&0x0E)==0x0) // BLTZ/BGEZ
57871462 7890 {
7891 alloc_cc(&current,i);
7892 dirty_reg(&current,CCREG);
cf95b4f0 7893 alloc_reg(&current,i,dops[i].rs1);
7894 if (dops[i].rt1==31) { // BLTZAL/BGEZAL
57871462 7895 alloc_reg(&current,i,31);
7896 dirty_reg(&current,31);
57871462 7897 //#ifdef REG_PREFETCH
7898 //alloc_reg(&current,i,PTEMP);
7899 //#endif
57871462 7900 }
cf95b4f0 7901 if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) // The delay slot overwrites the branch condition.
7902 ||(dops[i].rt1==31&&(dops[i+1].rs1==31||dops[i+1].rs2==31||dops[i+1].rt1==31||dops[i+1].rt2==31))) { // DS touches $ra
57871462 7903 // Allocate the branch condition registers instead.
57871462 7904 current.isconst=0;
7905 current.wasconst=0;
7906 regs[i].wasconst=0;
cf95b4f0 7907 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
57871462 7908 }
e1190b87 7909 else
7910 {
cf95b4f0 7911 dops[i].ooo=1;
e1190b87 7912 delayslot_alloc(&current,i+1);
7913 }
57871462 7914 }
7915 else
7916 // Don't alloc the delay slot yet because we might not execute it
cf95b4f0 7917 if((dops[i].opcode2&0x1E)==0x2) // BLTZL/BGEZL
57871462 7918 {
7919 current.isconst=0;
7920 current.wasconst=0;
7921 regs[i].wasconst=0;
7922 alloc_cc(&current,i);
7923 dirty_reg(&current,CCREG);
cf95b4f0 7924 alloc_reg(&current,i,dops[i].rs1);
57871462 7925 }
7926 ds=1;
7927 //current.isconst=0;
7928 break;
57871462 7929 case IMM16:
7930 imm16_alloc(&current,i);
7931 break;
7932 case LOAD:
7933 case LOADLR:
7934 load_alloc(&current,i);
7935 break;
7936 case STORE:
7937 case STORELR:
7938 store_alloc(&current,i);
7939 break;
7940 case ALU:
7941 alu_alloc(&current,i);
7942 break;
7943 case SHIFT:
7944 shift_alloc(&current,i);
7945 break;
7946 case MULTDIV:
7947 multdiv_alloc(&current,i);
7948 break;
7949 case SHIFTIMM:
7950 shiftimm_alloc(&current,i);
7951 break;
7952 case MOV:
7953 mov_alloc(&current,i);
7954 break;
7955 case COP0:
7956 cop0_alloc(&current,i);
7957 break;
7958 case COP1:
81dbbf4c 7959 break;
b9b61529 7960 case COP2:
81dbbf4c 7961 cop2_alloc(&current,i);
57871462 7962 break;
7963 case C1LS:
7964 c1ls_alloc(&current,i);
7965 break;
b9b61529 7966 case C2LS:
7967 c2ls_alloc(&current,i);
7968 break;
7969 case C2OP:
7970 c2op_alloc(&current,i);
7971 break;
57871462 7972 case SYSCALL:
7139f3c8 7973 case HLECALL:
1e973cb0 7974 case INTCALL:
57871462 7975 syscall_alloc(&current,i);
7976 break;
7977 case SPAN:
7978 pagespan_alloc(&current,i);
7979 break;
7980 }
9f51b4b9 7981
57871462 7982 // Create entry (branch target) regmap
7983 for(hr=0;hr<HOST_REGS;hr++)
7984 {
581335b0 7985 int r,or;
57871462 7986 r=current.regmap[hr];
7987 if(r>=0) {
7988 if(r!=regmap_pre[i][hr]) {
7989 // TODO: delay slot (?)
7990 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
7991 if(or<0||(r&63)>=TEMPREG){
7992 regs[i].regmap_entry[hr]=-1;
7993 }
7994 else
7995 {
7996 // Just move it to a different register
7997 regs[i].regmap_entry[hr]=r;
7998 // If it was dirty before, it's still dirty
7999 if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r&63);
8000 }
8001 }
8002 else
8003 {
8004 // Unneeded
8005 if(r==0){
8006 regs[i].regmap_entry[hr]=0;
8007 }
8008 else
7c3a5182 8009 {
8010 assert(r<64);
57871462 8011 if((current.u>>r)&1) {
8012 regs[i].regmap_entry[hr]=-1;
8013 //regs[i].regmap[hr]=-1;
8014 current.regmap[hr]=-1;
8015 }else
8016 regs[i].regmap_entry[hr]=r;
8017 }
57871462 8018 }
8019 } else {
8020 // Branches expect CCREG to be allocated at the target
9f51b4b9 8021 if(regmap_pre[i][hr]==CCREG)
57871462 8022 regs[i].regmap_entry[hr]=CCREG;
8023 else
8024 regs[i].regmap_entry[hr]=-1;
8025 }
8026 }
8027 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
8028 }
27727b63 8029
cf95b4f0 8030 if(i>0&&(dops[i-1].itype==STORE||dops[i-1].itype==STORELR||(dops[i-1].itype==C2LS&&dops[i-1].opcode==0x3a))&&(u_int)imm[i-1]<0x800)
8031 current.waswritten|=1<<dops[i-1].rs1;
8032 current.waswritten&=~(1<<dops[i].rt1);
8033 current.waswritten&=~(1<<dops[i].rt2);
8034 if((dops[i].itype==STORE||dops[i].itype==STORELR||(dops[i].itype==C2LS&&dops[i].opcode==0x3a))&&(u_int)imm[i]>=0x800)
8035 current.waswritten&=~(1<<dops[i].rs1);
27727b63 8036
57871462 8037 /* Branch post-alloc */
8038 if(i>0)
8039 {
57871462 8040 current.wasdirty=current.dirty;
cf95b4f0 8041 switch(dops[i-1].itype) {
57871462 8042 case UJUMP:
8043 memcpy(&branch_regs[i-1],&current,sizeof(current));
8044 branch_regs[i-1].isconst=0;
8045 branch_regs[i-1].wasconst=0;
cf95b4f0 8046 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
57871462 8047 alloc_cc(&branch_regs[i-1],i-1);
8048 dirty_reg(&branch_regs[i-1],CCREG);
cf95b4f0 8049 if(dops[i-1].rt1==31) { // JAL
57871462 8050 alloc_reg(&branch_regs[i-1],i-1,31);
8051 dirty_reg(&branch_regs[i-1],31);
57871462 8052 }
8053 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
40fca85b 8054 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 8055 break;
8056 case RJUMP:
8057 memcpy(&branch_regs[i-1],&current,sizeof(current));
8058 branch_regs[i-1].isconst=0;
8059 branch_regs[i-1].wasconst=0;
cf95b4f0 8060 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
57871462 8061 alloc_cc(&branch_regs[i-1],i-1);
8062 dirty_reg(&branch_regs[i-1],CCREG);
cf95b4f0 8063 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rs1);
8064 if(dops[i-1].rt1!=0) { // JALR
8065 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rt1);
8066 dirty_reg(&branch_regs[i-1],dops[i-1].rt1);
57871462 8067 }
8068 #ifdef USE_MINI_HT
cf95b4f0 8069 if(dops[i-1].rs1==31) { // JALR
57871462 8070 alloc_reg(&branch_regs[i-1],i-1,RHASH);
57871462 8071 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
57871462 8072 }
8073 #endif
8074 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
40fca85b 8075 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 8076 break;
8077 case CJUMP:
cf95b4f0 8078 if((dops[i-1].opcode&0x3E)==4) // BEQ/BNE
57871462 8079 {
8080 alloc_cc(&current,i-1);
8081 dirty_reg(&current,CCREG);
cf95b4f0 8082 if((dops[i-1].rs1&&(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2))||
8083 (dops[i-1].rs2&&(dops[i-1].rs2==dops[i].rt1||dops[i-1].rs2==dops[i].rt2))) {
57871462 8084 // The delay slot overwrote one of our conditions
8085 // Delay slot goes after the test (in order)
cf95b4f0 8086 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 8087 current.u|=1;
57871462 8088 delayslot_alloc(&current,i);
8089 current.isconst=0;
8090 }
8091 else
8092 {
cf95b4f0 8093 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
57871462 8094 // Alloc the branch condition registers
cf95b4f0 8095 if(dops[i-1].rs1) alloc_reg(&current,i-1,dops[i-1].rs1);
8096 if(dops[i-1].rs2) alloc_reg(&current,i-1,dops[i-1].rs2);
57871462 8097 }
8098 memcpy(&branch_regs[i-1],&current,sizeof(current));
8099 branch_regs[i-1].isconst=0;
8100 branch_regs[i-1].wasconst=0;
8101 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
40fca85b 8102 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 8103 }
8104 else
cf95b4f0 8105 if((dops[i-1].opcode&0x3E)==6) // BLEZ/BGTZ
57871462 8106 {
8107 alloc_cc(&current,i-1);
8108 dirty_reg(&current,CCREG);
cf95b4f0 8109 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
57871462 8110 // The delay slot overwrote the branch condition
8111 // Delay slot goes after the test (in order)
cf95b4f0 8112 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 8113 current.u|=1;
57871462 8114 delayslot_alloc(&current,i);
8115 current.isconst=0;
8116 }
8117 else
8118 {
cf95b4f0 8119 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
57871462 8120 // Alloc the branch condition register
cf95b4f0 8121 alloc_reg(&current,i-1,dops[i-1].rs1);
57871462 8122 }
8123 memcpy(&branch_regs[i-1],&current,sizeof(current));
8124 branch_regs[i-1].isconst=0;
8125 branch_regs[i-1].wasconst=0;
8126 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
40fca85b 8127 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 8128 }
8129 else
8130 // Alloc the delay slot in case the branch is taken
cf95b4f0 8131 if((dops[i-1].opcode&0x3E)==0x14) // BEQL/BNEL
57871462 8132 {
8133 memcpy(&branch_regs[i-1],&current,sizeof(current));
cf95b4f0 8134 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
57871462 8135 alloc_cc(&branch_regs[i-1],i);
8136 dirty_reg(&branch_regs[i-1],CCREG);
8137 delayslot_alloc(&branch_regs[i-1],i);
8138 branch_regs[i-1].isconst=0;
8139 alloc_reg(&current,i,CCREG); // Not taken path
8140 dirty_reg(&current,CCREG);
8141 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8142 }
8143 else
cf95b4f0 8144 if((dops[i-1].opcode&0x3E)==0x16) // BLEZL/BGTZL
57871462 8145 {
8146 memcpy(&branch_regs[i-1],&current,sizeof(current));
cf95b4f0 8147 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
57871462 8148 alloc_cc(&branch_regs[i-1],i);
8149 dirty_reg(&branch_regs[i-1],CCREG);
8150 delayslot_alloc(&branch_regs[i-1],i);
8151 branch_regs[i-1].isconst=0;
8152 alloc_reg(&current,i,CCREG); // Not taken path
8153 dirty_reg(&current,CCREG);
8154 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8155 }
8156 break;
8157 case SJUMP:
cf95b4f0 8158 //if((dops[i-1].opcode2&0x1E)==0) // BLTZ/BGEZ
8159 if((dops[i-1].opcode2&0x0E)==0) // BLTZ/BGEZ
57871462 8160 {
8161 alloc_cc(&current,i-1);
8162 dirty_reg(&current,CCREG);
cf95b4f0 8163 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
57871462 8164 // The delay slot overwrote the branch condition
8165 // Delay slot goes after the test (in order)
cf95b4f0 8166 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 8167 current.u|=1;
57871462 8168 delayslot_alloc(&current,i);
8169 current.isconst=0;
8170 }
8171 else
8172 {
cf95b4f0 8173 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
57871462 8174 // Alloc the branch condition register
cf95b4f0 8175 alloc_reg(&current,i-1,dops[i-1].rs1);
57871462 8176 }
8177 memcpy(&branch_regs[i-1],&current,sizeof(current));
8178 branch_regs[i-1].isconst=0;
8179 branch_regs[i-1].wasconst=0;
8180 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
40fca85b 8181 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 8182 }
8183 else
8184 // Alloc the delay slot in case the branch is taken
cf95b4f0 8185 if((dops[i-1].opcode2&0x1E)==2) // BLTZL/BGEZL
57871462 8186 {
8187 memcpy(&branch_regs[i-1],&current,sizeof(current));
cf95b4f0 8188 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
57871462 8189 alloc_cc(&branch_regs[i-1],i);
8190 dirty_reg(&branch_regs[i-1],CCREG);
8191 delayslot_alloc(&branch_regs[i-1],i);
8192 branch_regs[i-1].isconst=0;
8193 alloc_reg(&current,i,CCREG); // Not taken path
8194 dirty_reg(&current,CCREG);
8195 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8196 }
8197 // FIXME: BLTZAL/BGEZAL
cf95b4f0 8198 if(dops[i-1].opcode2&0x10) { // BxxZAL
57871462 8199 alloc_reg(&branch_regs[i-1],i-1,31);
8200 dirty_reg(&branch_regs[i-1],31);
57871462 8201 }
8202 break;
57871462 8203 }
8204
fe807a8a 8205 if (dops[i-1].is_ujump)
57871462 8206 {
cf95b4f0 8207 if(dops[i-1].rt1==31) // JAL/JALR
57871462 8208 {
8209 // Subroutine call will return here, don't alloc any registers
57871462 8210 current.dirty=0;
8211 clear_all_regs(current.regmap);
8212 alloc_reg(&current,i,CCREG);
8213 dirty_reg(&current,CCREG);
8214 }
8215 else if(i+1<slen)
8216 {
8217 // Internal branch will jump here, match registers to caller
57871462 8218 current.dirty=0;
8219 clear_all_regs(current.regmap);
8220 alloc_reg(&current,i,CCREG);
8221 dirty_reg(&current,CCREG);
8222 for(j=i-1;j>=0;j--)
8223 {
8224 if(ba[j]==start+i*4+4) {
8225 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
57871462 8226 current.dirty=branch_regs[j].dirty;
8227 break;
8228 }
8229 }
8230 while(j>=0) {
8231 if(ba[j]==start+i*4+4) {
8232 for(hr=0;hr<HOST_REGS;hr++) {
8233 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
8234 current.regmap[hr]=-1;
8235 }
57871462 8236 current.dirty&=branch_regs[j].dirty;
8237 }
8238 }
8239 j--;
8240 }
8241 }
8242 }
8243 }
8244
8245 // Count cycles in between branches
2330734f 8246 ccadj[i] = CLOCK_ADJUST(cc);
fe807a8a 8247 if (i > 0 && (dops[i-1].is_jump || dops[i].itype == SYSCALL || dops[i].itype == HLECALL))
57871462 8248 {
8249 cc=0;
8250 }
71e490c5 8251#if !defined(DRC_DBG)
cf95b4f0 8252 else if(dops[i].itype==C2OP&&gte_cycletab[source[i]&0x3f]>2)
054175e9 8253 {
81dbbf4c 8254 // this should really be removed since the real stalls have been implemented,
8255 // but doing so causes sizeable perf regression against the older version
8256 u_int gtec = gte_cycletab[source[i] & 0x3f];
32631e6a 8257 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? gtec/2 : 2;
fb407447 8258 }
cf95b4f0 8259 else if(i>1&&dops[i].itype==STORE&&dops[i-1].itype==STORE&&dops[i-2].itype==STORE&&!dops[i].bt)
5fdcbb5a 8260 {
8261 cc+=4;
8262 }
cf95b4f0 8263 else if(dops[i].itype==C2LS)
fb407447 8264 {
81dbbf4c 8265 // same as with C2OP
32631e6a 8266 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? 4 : 2;
fb407447 8267 }
8268#endif
57871462 8269 else
8270 {
8271 cc++;
8272 }
8273
cf95b4f0 8274 if(!dops[i].is_ds) {
57871462 8275 regs[i].dirty=current.dirty;
8276 regs[i].isconst=current.isconst;
40fca85b 8277 memcpy(constmap[i],current_constmap,sizeof(constmap[i]));
57871462 8278 }
8279 for(hr=0;hr<HOST_REGS;hr++) {
8280 if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
8281 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
8282 regs[i].wasconst&=~(1<<hr);
8283 }
8284 }
8285 }
8286 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
27727b63 8287 regs[i].waswritten=current.waswritten;
57871462 8288 }
9f51b4b9 8289
57871462 8290 /* Pass 4 - Cull unused host registers */
9f51b4b9 8291
57871462 8292 uint64_t nr=0;
9f51b4b9 8293
57871462 8294 for (i=slen-1;i>=0;i--)
8295 {
8296 int hr;
fe807a8a 8297 if(dops[i].is_jump)
57871462 8298 {
8299 if(ba[i]<start || ba[i]>=(start+slen*4))
8300 {
8301 // Branch out of this block, don't need anything
8302 nr=0;
8303 }
8304 else
8305 {
8306 // Internal branch
8307 // Need whatever matches the target
8308 nr=0;
8309 int t=(ba[i]-start)>>2;
8310 for(hr=0;hr<HOST_REGS;hr++)
8311 {
8312 if(regs[i].regmap_entry[hr]>=0) {
8313 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
8314 }
8315 }
8316 }
8317 // Conditional branch may need registers for following instructions
fe807a8a 8318 if (!dops[i].is_ujump)
57871462 8319 {
8320 if(i<slen-2) {
8321 nr|=needed_reg[i+2];
8322 for(hr=0;hr<HOST_REGS;hr++)
8323 {
8324 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
8325 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
8326 }
8327 }
8328 }
8329 // Don't need stuff which is overwritten
f5955059 8330 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
8331 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
57871462 8332 // Merge in delay slot
8333 for(hr=0;hr<HOST_REGS;hr++)
8334 {
fe807a8a 8335 if(dops[i+1].rt1&&dops[i+1].rt1==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8336 if(dops[i+1].rt2&&dops[i+1].rt2==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
cf95b4f0 8337 if(dops[i+1].rs1==regmap_pre[i][hr]) nr|=1<<hr;
8338 if(dops[i+1].rs2==regmap_pre[i][hr]) nr|=1<<hr;
8339 if(dops[i+1].rs1==regs[i].regmap_entry[hr]) nr|=1<<hr;
8340 if(dops[i+1].rs2==regs[i].regmap_entry[hr]) nr|=1<<hr;
37387d8b 8341 if(ram_offset && (dops[i+1].is_load || dops[i+1].is_store)) {
8342 if(regmap_pre[i][hr]==ROREG) nr|=1<<hr;
8343 if(regs[i].regmap_entry[hr]==ROREG) nr|=1<<hr;
8344 }
8345 if(dops[i+1].is_store) {
57871462 8346 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
8347 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
8348 }
8349 }
8350 }
cf95b4f0 8351 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
57871462 8352 {
8353 // SYSCALL instruction (software interrupt)
8354 nr=0;
8355 }
cf95b4f0 8356 else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
57871462 8357 {
8358 // ERET instruction (return from interrupt)
8359 nr=0;
8360 }
8361 else // Non-branch
8362 {
8363 if(i<slen-1) {
8364 for(hr=0;hr<HOST_REGS;hr++) {
8365 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
8366 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
8367 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
8368 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
8369 }
8370 }
8371 }
8372 for(hr=0;hr<HOST_REGS;hr++)
8373 {
8374 // Overwritten registers are not needed
cf95b4f0 8375 if(dops[i].rt1&&dops[i].rt1==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8376 if(dops[i].rt2&&dops[i].rt2==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
57871462 8377 if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8378 // Source registers are needed
cf95b4f0 8379 if(dops[i].rs1==regmap_pre[i][hr]) nr|=1<<hr;
8380 if(dops[i].rs2==regmap_pre[i][hr]) nr|=1<<hr;
8381 if(dops[i].rs1==regs[i].regmap_entry[hr]) nr|=1<<hr;
8382 if(dops[i].rs2==regs[i].regmap_entry[hr]) nr|=1<<hr;
37387d8b 8383 if(ram_offset && (dops[i].is_load || dops[i].is_store)) {
8384 if(regmap_pre[i][hr]==ROREG) nr|=1<<hr;
8385 if(regs[i].regmap_entry[hr]==ROREG) nr|=1<<hr;
8386 }
8387 if(dops[i].is_store) {
57871462 8388 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
8389 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
8390 }
8391 // Don't store a register immediately after writing it,
8392 // may prevent dual-issue.
8393 // But do so if this is a branch target, otherwise we
8394 // might have to load the register before the branch.
cf95b4f0 8395 if(i>0&&!dops[i].bt&&((regs[i].wasdirty>>hr)&1)) {
7c3a5182 8396 if((regmap_pre[i][hr]>0&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1))) {
cf95b4f0 8397 if(dops[i-1].rt1==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8398 if(dops[i-1].rt2==(regmap_pre[i][hr]&63)) nr|=1<<hr;
57871462 8399 }
7c3a5182 8400 if((regs[i].regmap_entry[hr]>0&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1))) {
cf95b4f0 8401 if(dops[i-1].rt1==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8402 if(dops[i-1].rt2==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
57871462 8403 }
8404 }
8405 }
8406 // Cycle count is needed at branches. Assume it is needed at the target too.
cf95b4f0 8407 if(i==0||dops[i].bt||dops[i].itype==CJUMP||dops[i].itype==SPAN) {
57871462 8408 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
8409 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
8410 }
8411 // Save it
8412 needed_reg[i]=nr;
9f51b4b9 8413
57871462 8414 // Deallocate unneeded registers
8415 for(hr=0;hr<HOST_REGS;hr++)
8416 {
8417 if(!((nr>>hr)&1)) {
8418 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
fe807a8a 8419 if(dops[i].is_jump)
57871462 8420 {
37387d8b 8421 int map1 = 0, map2 = 0, temp = 0; // or -1 ??
8422 if (dops[i+1].is_load || dops[i+1].is_store)
8423 map1 = ROREG;
8424 if (dops[i+1].is_store)
8425 map2 = INVCP;
8426 if(dops[i+1].itype==LOADLR || dops[i+1].itype==STORELR || dops[i+1].itype==C2LS)
8427 temp = FTEMP;
cf95b4f0 8428 if((regs[i].regmap[hr]&63)!=dops[i].rs1 && (regs[i].regmap[hr]&63)!=dops[i].rs2 &&
8429 (regs[i].regmap[hr]&63)!=dops[i].rt1 && (regs[i].regmap[hr]&63)!=dops[i].rt2 &&
8430 (regs[i].regmap[hr]&63)!=dops[i+1].rt1 && (regs[i].regmap[hr]&63)!=dops[i+1].rt2 &&
8431 regs[i].regmap[hr]!=dops[i+1].rs1 && regs[i].regmap[hr]!=dops[i+1].rs2 &&
57871462 8432 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
8433 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
8434 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
37387d8b 8435 regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2)
57871462 8436 {
8437 regs[i].regmap[hr]=-1;
8438 regs[i].isconst&=~(1<<hr);
cf95b4f0 8439 if((branch_regs[i].regmap[hr]&63)!=dops[i].rs1 && (branch_regs[i].regmap[hr]&63)!=dops[i].rs2 &&
8440 (branch_regs[i].regmap[hr]&63)!=dops[i].rt1 && (branch_regs[i].regmap[hr]&63)!=dops[i].rt2 &&
8441 (branch_regs[i].regmap[hr]&63)!=dops[i+1].rt1 && (branch_regs[i].regmap[hr]&63)!=dops[i+1].rt2 &&
8442 branch_regs[i].regmap[hr]!=dops[i+1].rs1 && branch_regs[i].regmap[hr]!=dops[i+1].rs2 &&
57871462 8443 (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
8444 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
8445 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
37387d8b 8446 branch_regs[i].regmap[hr]!=map1 && branch_regs[i].regmap[hr]!=map2)
57871462 8447 {
8448 branch_regs[i].regmap[hr]=-1;
8449 branch_regs[i].regmap_entry[hr]=-1;
fe807a8a 8450 if (!dops[i].is_ujump)
57871462 8451 {
fe807a8a 8452 if (i < slen-2) {
57871462 8453 regmap_pre[i+2][hr]=-1;
79c75f1b 8454 regs[i+2].wasconst&=~(1<<hr);
57871462 8455 }
8456 }
8457 }
8458 }
8459 }
8460 else
8461 {
8462 // Non-branch
8463 if(i>0)
8464 {
37387d8b 8465 int map1 = -1, map2 = -1, temp=-1;
8466 if (dops[i].is_load || dops[i].is_store)
8467 map1 = ROREG;
8468 if (dops[i].is_store)
8469 map2 = INVCP;
8470 if (dops[i].itype==LOADLR || dops[i].itype==STORELR || dops[i].itype==C2LS)
8471 temp = FTEMP;
cf95b4f0 8472 if((regs[i].regmap[hr]&63)!=dops[i].rt1 && (regs[i].regmap[hr]&63)!=dops[i].rt2 &&
8473 regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 &&
37387d8b 8474 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2 &&
4b1c7cd1 8475 //(dops[i].itype!=SPAN||regs[i].regmap[hr]!=CCREG)
8476 regs[i].regmap[hr] != CCREG)
57871462 8477 {
cf95b4f0 8478 if(i<slen-1&&!dops[i].is_ds) {
ad49de89 8479 assert(regs[i].regmap[hr]<64);
afec9d44 8480 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]>0)
57871462 8481 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
57871462 8482 {
c43b5311 8483 SysPrintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
57871462 8484 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
8485 }
8486 regmap_pre[i+1][hr]=-1;
8487 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
79c75f1b 8488 regs[i+1].wasconst&=~(1<<hr);
57871462 8489 }
8490 regs[i].regmap[hr]=-1;
8491 regs[i].isconst&=~(1<<hr);
8492 }
8493 }
8494 }
3968e69e 8495 } // if needed
8496 } // for hr
57871462 8497 }
9f51b4b9 8498
57871462 8499 /* Pass 5 - Pre-allocate registers */
9f51b4b9 8500
57871462 8501 // If a register is allocated during a loop, try to allocate it for the
8502 // entire loop, if possible. This avoids loading/storing registers
8503 // inside of the loop.
9f51b4b9 8504
57871462 8505 signed char f_regmap[HOST_REGS];
8506 clear_all_regs(f_regmap);
8507 for(i=0;i<slen-1;i++)
8508 {
cf95b4f0 8509 if(dops[i].itype==UJUMP||dops[i].itype==CJUMP||dops[i].itype==SJUMP)
57871462 8510 {
9f51b4b9 8511 if(ba[i]>=start && ba[i]<(start+i*4))
cf95b4f0 8512 if(dops[i+1].itype==NOP||dops[i+1].itype==MOV||dops[i+1].itype==ALU
8513 ||dops[i+1].itype==SHIFTIMM||dops[i+1].itype==IMM16||dops[i+1].itype==LOAD
8514 ||dops[i+1].itype==STORE||dops[i+1].itype==STORELR||dops[i+1].itype==C1LS
8515 ||dops[i+1].itype==SHIFT||dops[i+1].itype==COP1
8516 ||dops[i+1].itype==COP2||dops[i+1].itype==C2LS||dops[i+1].itype==C2OP)
57871462 8517 {
8518 int t=(ba[i]-start)>>2;
fe807a8a 8519 if(t > 0 && !dops[t-1].is_jump) // loop_preload can't handle jumps into delay slots
cf95b4f0 8520 if(t<2||(dops[t-2].itype!=UJUMP&&dops[t-2].itype!=RJUMP)||dops[t-2].rt1!=31) // call/ret assumes no registers allocated
57871462 8521 for(hr=0;hr<HOST_REGS;hr++)
8522 {
7c3a5182 8523 if(regs[i].regmap[hr]>=0) {
b372a952 8524 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8525 // dealloc old register
8526 int n;
8527 for(n=0;n<HOST_REGS;n++)
8528 {
8529 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8530 }
8531 // and alloc new one
8532 f_regmap[hr]=regs[i].regmap[hr];
8533 }
8534 }
7c3a5182 8535 if(branch_regs[i].regmap[hr]>=0) {
b372a952 8536 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
8537 // dealloc old register
8538 int n;
8539 for(n=0;n<HOST_REGS;n++)
8540 {
8541 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
8542 }
8543 // and alloc new one
8544 f_regmap[hr]=branch_regs[i].regmap[hr];
8545 }
8546 }
cf95b4f0 8547 if(dops[i].ooo) {
9f51b4b9 8548 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
e1190b87 8549 f_regmap[hr]=branch_regs[i].regmap[hr];
8550 }else{
9f51b4b9 8551 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
57871462 8552 f_regmap[hr]=branch_regs[i].regmap[hr];
8553 }
8554 // Avoid dirty->clean transition
e1190b87 8555 #ifdef DESTRUCTIVE_WRITEBACK
57871462 8556 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
e1190b87 8557 #endif
8558 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
8559 // case above, however it's always a good idea. We can't hoist the
8560 // load if the register was already allocated, so there's no point
8561 // wasting time analyzing most of these cases. It only "succeeds"
8562 // when the mapping was different and the load can be replaced with
8563 // a mov, which is of negligible benefit. So such cases are
8564 // skipped below.
57871462 8565 if(f_regmap[hr]>0) {
198df76f 8566 if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
57871462 8567 int r=f_regmap[hr];
8568 for(j=t;j<=i;j++)
8569 {
8570 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
8571 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
00fa9369 8572 assert(r < 64);
57871462 8573 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
8574 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
8575 int k;
8576 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
8577 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
8578 if(r>63) {
8579 if(get_reg(regs[i].regmap,r&63)<0) break;
8580 if(get_reg(branch_regs[i].regmap,r&63)<0) break;
8581 }
8582 k=i;
8583 while(k>1&&regs[k-1].regmap[hr]==-1) {
e1190b87 8584 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
8585 //printf("no free regs for store %x\n",start+(k-1)*4);
8586 break;
57871462 8587 }
57871462 8588 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
8589 //printf("no-match due to different register\n");
8590 break;
8591 }
fe807a8a 8592 if (dops[k-2].is_jump) {
57871462 8593 //printf("no-match due to branch\n");
8594 break;
8595 }
8596 // call/ret fast path assumes no registers allocated
cf95b4f0 8597 if(k>2&&(dops[k-3].itype==UJUMP||dops[k-3].itype==RJUMP)&&dops[k-3].rt1==31) {
57871462 8598 break;
8599 }
ad49de89 8600 assert(r < 64);
57871462 8601 k--;
8602 }
57871462 8603 if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
8604 //printf("Extend r%d, %x ->\n",hr,start+k*4);
8605 while(k<i) {
8606 regs[k].regmap_entry[hr]=f_regmap[hr];
8607 regs[k].regmap[hr]=f_regmap[hr];
8608 regmap_pre[k+1][hr]=f_regmap[hr];
8609 regs[k].wasdirty&=~(1<<hr);
8610 regs[k].dirty&=~(1<<hr);
8611 regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
8612 regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
8613 regs[k].wasconst&=~(1<<hr);
8614 regs[k].isconst&=~(1<<hr);
8615 k++;
8616 }
8617 }
8618 else {
8619 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
8620 break;
8621 }
8622 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
8623 if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
8624 //printf("OK fill %x (r%d)\n",start+i*4,hr);
8625 regs[i].regmap_entry[hr]=f_regmap[hr];
8626 regs[i].regmap[hr]=f_regmap[hr];
8627 regs[i].wasdirty&=~(1<<hr);
8628 regs[i].dirty&=~(1<<hr);
8629 regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
8630 regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
8631 regs[i].wasconst&=~(1<<hr);
8632 regs[i].isconst&=~(1<<hr);
8633 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
8634 branch_regs[i].wasdirty&=~(1<<hr);
8635 branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
8636 branch_regs[i].regmap[hr]=f_regmap[hr];
8637 branch_regs[i].dirty&=~(1<<hr);
8638 branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
8639 branch_regs[i].wasconst&=~(1<<hr);
8640 branch_regs[i].isconst&=~(1<<hr);
fe807a8a 8641 if (!dops[i].is_ujump) {
57871462 8642 regmap_pre[i+2][hr]=f_regmap[hr];
8643 regs[i+2].wasdirty&=~(1<<hr);
8644 regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
57871462 8645 }
8646 }
8647 }
8648 for(k=t;k<j;k++) {
e1190b87 8649 // Alloc register clean at beginning of loop,
8650 // but may dirty it in pass 6
57871462 8651 regs[k].regmap_entry[hr]=f_regmap[hr];
8652 regs[k].regmap[hr]=f_regmap[hr];
57871462 8653 regs[k].dirty&=~(1<<hr);
8654 regs[k].wasconst&=~(1<<hr);
8655 regs[k].isconst&=~(1<<hr);
fe807a8a 8656 if (dops[k].is_jump) {
e1190b87 8657 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
8658 branch_regs[k].regmap[hr]=f_regmap[hr];
8659 branch_regs[k].dirty&=~(1<<hr);
8660 branch_regs[k].wasconst&=~(1<<hr);
8661 branch_regs[k].isconst&=~(1<<hr);
fe807a8a 8662 if (!dops[k].is_ujump) {
e1190b87 8663 regmap_pre[k+2][hr]=f_regmap[hr];
8664 regs[k+2].wasdirty&=~(1<<hr);
e1190b87 8665 }
8666 }
8667 else
8668 {
8669 regmap_pre[k+1][hr]=f_regmap[hr];
8670 regs[k+1].wasdirty&=~(1<<hr);
8671 }
57871462 8672 }
8673 if(regs[j].regmap[hr]==f_regmap[hr])
8674 regs[j].regmap_entry[hr]=f_regmap[hr];
8675 break;
8676 }
8677 if(j==i) break;
8678 if(regs[j].regmap[hr]>=0)
8679 break;
8680 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
8681 //printf("no-match due to different register\n");
8682 break;
8683 }
fe807a8a 8684 if (dops[j].is_ujump)
e1190b87 8685 {
8686 // Stop on unconditional branch
8687 break;
8688 }
cf95b4f0 8689 if(dops[j].itype==CJUMP||dops[j].itype==SJUMP)
e1190b87 8690 {
cf95b4f0 8691 if(dops[j].ooo) {
9f51b4b9 8692 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
e1190b87 8693 break;
8694 }else{
9f51b4b9 8695 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
e1190b87 8696 break;
8697 }
8698 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
8699 //printf("no-match due to different register (branch)\n");
57871462 8700 break;
8701 }
8702 }
e1190b87 8703 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
8704 //printf("No free regs for store %x\n",start+j*4);
8705 break;
8706 }
ad49de89 8707 assert(f_regmap[hr]<64);
57871462 8708 }
8709 }
8710 }
8711 }
8712 }
8713 }else{
198df76f 8714 // Non branch or undetermined branch target
57871462 8715 for(hr=0;hr<HOST_REGS;hr++)
8716 {
8717 if(hr!=EXCLUDE_REG) {
7c3a5182 8718 if(regs[i].regmap[hr]>=0) {
b372a952 8719 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8720 // dealloc old register
8721 int n;
8722 for(n=0;n<HOST_REGS;n++)
8723 {
8724 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8725 }
8726 // and alloc new one
8727 f_regmap[hr]=regs[i].regmap[hr];
8728 }
8729 }
57871462 8730 }
8731 }
8732 // Try to restore cycle count at branch targets
cf95b4f0 8733 if(dops[i].bt) {
57871462 8734 for(j=i;j<slen-1;j++) {
8735 if(regs[j].regmap[HOST_CCREG]!=-1) break;
e1190b87 8736 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
8737 //printf("no free regs for store %x\n",start+j*4);
8738 break;
57871462 8739 }
57871462 8740 }
8741 if(regs[j].regmap[HOST_CCREG]==CCREG) {
8742 int k=i;
8743 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
8744 while(k<j) {
8745 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8746 regs[k].regmap[HOST_CCREG]=CCREG;
8747 regmap_pre[k+1][HOST_CCREG]=CCREG;
8748 regs[k+1].wasdirty|=1<<HOST_CCREG;
8749 regs[k].dirty|=1<<HOST_CCREG;
8750 regs[k].wasconst&=~(1<<HOST_CCREG);
8751 regs[k].isconst&=~(1<<HOST_CCREG);
8752 k++;
8753 }
9f51b4b9 8754 regs[j].regmap_entry[HOST_CCREG]=CCREG;
57871462 8755 }
8756 // Work backwards from the branch target
8757 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
8758 {
8759 //printf("Extend backwards\n");
8760 int k;
8761 k=i;
8762 while(regs[k-1].regmap[HOST_CCREG]==-1) {
e1190b87 8763 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
8764 //printf("no free regs for store %x\n",start+(k-1)*4);
8765 break;
57871462 8766 }
57871462 8767 k--;
8768 }
8769 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
8770 //printf("Extend CC, %x ->\n",start+k*4);
8771 while(k<=i) {
8772 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8773 regs[k].regmap[HOST_CCREG]=CCREG;
8774 regmap_pre[k+1][HOST_CCREG]=CCREG;
8775 regs[k+1].wasdirty|=1<<HOST_CCREG;
8776 regs[k].dirty|=1<<HOST_CCREG;
8777 regs[k].wasconst&=~(1<<HOST_CCREG);
8778 regs[k].isconst&=~(1<<HOST_CCREG);
8779 k++;
8780 }
8781 }
8782 else {
8783 //printf("Fail Extend CC, %x ->\n",start+k*4);
8784 }
8785 }
8786 }
cf95b4f0 8787 if(dops[i].itype!=STORE&&dops[i].itype!=STORELR&&dops[i].itype!=C1LS&&dops[i].itype!=SHIFT&&
8788 dops[i].itype!=NOP&&dops[i].itype!=MOV&&dops[i].itype!=ALU&&dops[i].itype!=SHIFTIMM&&
8789 dops[i].itype!=IMM16&&dops[i].itype!=LOAD&&dops[i].itype!=COP1)
57871462 8790 {
8791 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
8792 }
8793 }
8794 }
9f51b4b9 8795
57871462 8796 // This allocates registers (if possible) one instruction prior
8797 // to use, which can avoid a load-use penalty on certain CPUs.
8798 for(i=0;i<slen-1;i++)
8799 {
fe807a8a 8800 if (!i || !dops[i-1].is_jump)
57871462 8801 {
cf95b4f0 8802 if(!dops[i+1].bt)
57871462 8803 {
cf95b4f0 8804 if(dops[i].itype==ALU||dops[i].itype==MOV||dops[i].itype==LOAD||dops[i].itype==SHIFTIMM||dops[i].itype==IMM16
8805 ||((dops[i].itype==COP1||dops[i].itype==COP2)&&dops[i].opcode2<3))
57871462 8806 {
cf95b4f0 8807 if(dops[i+1].rs1) {
8808 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs1))>=0)
57871462 8809 {
8810 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8811 {
8812 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8813 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8814 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8815 regs[i].isconst&=~(1<<hr);
8816 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8817 constmap[i][hr]=constmap[i+1][hr];
8818 regs[i+1].wasdirty&=~(1<<hr);
8819 regs[i].dirty&=~(1<<hr);
8820 }
8821 }
8822 }
cf95b4f0 8823 if(dops[i+1].rs2) {
8824 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs2))>=0)
57871462 8825 {
8826 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8827 {
8828 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8829 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8830 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8831 regs[i].isconst&=~(1<<hr);
8832 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8833 constmap[i][hr]=constmap[i+1][hr];
8834 regs[i+1].wasdirty&=~(1<<hr);
8835 regs[i].dirty&=~(1<<hr);
8836 }
8837 }
8838 }
198df76f 8839 // Preload target address for load instruction (non-constant)
cf95b4f0 8840 if(dops[i+1].itype==LOAD&&dops[i+1].rs1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8841 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rt1))>=0)
57871462 8842 {
8843 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8844 {
cf95b4f0 8845 regs[i].regmap[hr]=dops[i+1].rs1;
8846 regmap_pre[i+1][hr]=dops[i+1].rs1;
8847 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
57871462 8848 regs[i].isconst&=~(1<<hr);
8849 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8850 constmap[i][hr]=constmap[i+1][hr];
8851 regs[i+1].wasdirty&=~(1<<hr);
8852 regs[i].dirty&=~(1<<hr);
8853 }
8854 }
8855 }
9f51b4b9 8856 // Load source into target register
cf95b4f0 8857 if(dops[i+1].lt1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8858 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rt1))>=0)
57871462 8859 {
8860 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8861 {
cf95b4f0 8862 regs[i].regmap[hr]=dops[i+1].rs1;
8863 regmap_pre[i+1][hr]=dops[i+1].rs1;
8864 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
57871462 8865 regs[i].isconst&=~(1<<hr);
8866 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8867 constmap[i][hr]=constmap[i+1][hr];
8868 regs[i+1].wasdirty&=~(1<<hr);
8869 regs[i].dirty&=~(1<<hr);
8870 }
8871 }
8872 }
198df76f 8873 // Address for store instruction (non-constant)
cf95b4f0 8874 if(dops[i+1].itype==STORE||dops[i+1].itype==STORELR
8875 ||(dops[i+1].opcode&0x3b)==0x39||(dops[i+1].opcode&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
8876 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
57871462 8877 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
8878 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
8879 else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
8880 assert(hr>=0);
8881 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8882 {
cf95b4f0 8883 regs[i].regmap[hr]=dops[i+1].rs1;
8884 regmap_pre[i+1][hr]=dops[i+1].rs1;
8885 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
57871462 8886 regs[i].isconst&=~(1<<hr);
8887 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8888 constmap[i][hr]=constmap[i+1][hr];
8889 regs[i+1].wasdirty&=~(1<<hr);
8890 regs[i].dirty&=~(1<<hr);
8891 }
8892 }
8893 }
cf95b4f0 8894 if(dops[i+1].itype==LOADLR||(dops[i+1].opcode&0x3b)==0x31||(dops[i+1].opcode&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
8895 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
57871462 8896 int nr;
8897 hr=get_reg(regs[i+1].regmap,FTEMP);
8898 assert(hr>=0);
8899 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8900 {
cf95b4f0 8901 regs[i].regmap[hr]=dops[i+1].rs1;
8902 regmap_pre[i+1][hr]=dops[i+1].rs1;
8903 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
57871462 8904 regs[i].isconst&=~(1<<hr);
8905 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8906 constmap[i][hr]=constmap[i+1][hr];
8907 regs[i+1].wasdirty&=~(1<<hr);
8908 regs[i].dirty&=~(1<<hr);
8909 }
8910 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
8911 {
8912 // move it to another register
8913 regs[i+1].regmap[hr]=-1;
8914 regmap_pre[i+2][hr]=-1;
8915 regs[i+1].regmap[nr]=FTEMP;
8916 regmap_pre[i+2][nr]=FTEMP;
cf95b4f0 8917 regs[i].regmap[nr]=dops[i+1].rs1;
8918 regmap_pre[i+1][nr]=dops[i+1].rs1;
8919 regs[i+1].regmap_entry[nr]=dops[i+1].rs1;
57871462 8920 regs[i].isconst&=~(1<<nr);
8921 regs[i+1].isconst&=~(1<<nr);
8922 regs[i].dirty&=~(1<<nr);
8923 regs[i+1].wasdirty&=~(1<<nr);
8924 regs[i+1].dirty&=~(1<<nr);
8925 regs[i+2].wasdirty&=~(1<<nr);
8926 }
8927 }
8928 }
cf95b4f0 8929 if(dops[i+1].itype==LOAD||dops[i+1].itype==LOADLR||dops[i+1].itype==STORE||dops[i+1].itype==STORELR/*||dops[i+1].itype==C1LS||||dops[i+1].itype==C2LS*/) {
8930 if(dops[i+1].itype==LOAD)
8931 hr=get_reg(regs[i+1].regmap,dops[i+1].rt1);
8932 if(dops[i+1].itype==LOADLR||(dops[i+1].opcode&0x3b)==0x31||(dops[i+1].opcode&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
57871462 8933 hr=get_reg(regs[i+1].regmap,FTEMP);
cf95b4f0 8934 if(dops[i+1].itype==STORE||dops[i+1].itype==STORELR||(dops[i+1].opcode&0x3b)==0x39||(dops[i+1].opcode&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
57871462 8935 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
8936 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
8937 }
8938 if(hr>=0&&regs[i].regmap[hr]<0) {
cf95b4f0 8939 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
57871462 8940 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
8941 regs[i].regmap[hr]=AGEN1+((i+1)&1);
8942 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
8943 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
8944 regs[i].isconst&=~(1<<hr);
8945 regs[i+1].wasdirty&=~(1<<hr);
8946 regs[i].dirty&=~(1<<hr);
8947 }
8948 }
8949 }
8950 }
8951 }
8952 }
8953 }
9f51b4b9 8954
57871462 8955 /* Pass 6 - Optimize clean/dirty state */
8956 clean_registers(0,slen-1,1);
9f51b4b9 8957
57871462 8958 /* Pass 7 - Identify 32-bit registers */
04fd948a 8959 for (i=slen-1;i>=0;i--)
8960 {
cf95b4f0 8961 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
04fd948a 8962 {
8963 // Conditional branch
8964 if((source[i]>>16)!=0x1000&&i<slen-2) {
8965 // Mark this address as a branch target since it may be called
8966 // upon return from interrupt
cf95b4f0 8967 dops[i+2].bt=1;
04fd948a 8968 }
8969 }
8970 }
57871462 8971
cf95b4f0 8972 if(dops[slen-1].itype==SPAN) {
8973 dops[slen-1].bt=1; // Mark as a branch target so instruction can restart after exception
57871462 8974 }
4600ba03 8975
8976#ifdef DISASM
57871462 8977 /* Debug/disassembly */
57871462 8978 for(i=0;i<slen;i++)
8979 {
8980 printf("U:");
8981 int r;
8982 for(r=1;r<=CCREG;r++) {
8983 if((unneeded_reg[i]>>r)&1) {
8984 if(r==HIREG) printf(" HI");
8985 else if(r==LOREG) printf(" LO");
8986 else printf(" r%d",r);
8987 }
8988 }
57871462 8989 printf("\n");
8990 #if defined(__i386__) || defined(__x86_64__)
8991 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
8992 #endif
8993 #ifdef __arm__
8994 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
8995 #endif
7c3a5182 8996 #if defined(__i386__) || defined(__x86_64__)
57871462 8997 printf("needs: ");
8998 if(needed_reg[i]&1) printf("eax ");
8999 if((needed_reg[i]>>1)&1) printf("ecx ");
9000 if((needed_reg[i]>>2)&1) printf("edx ");
9001 if((needed_reg[i]>>3)&1) printf("ebx ");
9002 if((needed_reg[i]>>5)&1) printf("ebp ");
9003 if((needed_reg[i]>>6)&1) printf("esi ");
9004 if((needed_reg[i]>>7)&1) printf("edi ");
57871462 9005 printf("\n");
57871462 9006 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
9007 printf("dirty: ");
9008 if(regs[i].wasdirty&1) printf("eax ");
9009 if((regs[i].wasdirty>>1)&1) printf("ecx ");
9010 if((regs[i].wasdirty>>2)&1) printf("edx ");
9011 if((regs[i].wasdirty>>3)&1) printf("ebx ");
9012 if((regs[i].wasdirty>>5)&1) printf("ebp ");
9013 if((regs[i].wasdirty>>6)&1) printf("esi ");
9014 if((regs[i].wasdirty>>7)&1) printf("edi ");
9015 #endif
9016 #ifdef __arm__
9017 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
9018 printf("dirty: ");
9019 if(regs[i].wasdirty&1) printf("r0 ");
9020 if((regs[i].wasdirty>>1)&1) printf("r1 ");
9021 if((regs[i].wasdirty>>2)&1) printf("r2 ");
9022 if((regs[i].wasdirty>>3)&1) printf("r3 ");
9023 if((regs[i].wasdirty>>4)&1) printf("r4 ");
9024 if((regs[i].wasdirty>>5)&1) printf("r5 ");
9025 if((regs[i].wasdirty>>6)&1) printf("r6 ");
9026 if((regs[i].wasdirty>>7)&1) printf("r7 ");
9027 if((regs[i].wasdirty>>8)&1) printf("r8 ");
9028 if((regs[i].wasdirty>>9)&1) printf("r9 ");
9029 if((regs[i].wasdirty>>10)&1) printf("r10 ");
9030 if((regs[i].wasdirty>>12)&1) printf("r12 ");
9031 #endif
9032 printf("\n");
9033 disassemble_inst(i);
9034 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
9035 #if defined(__i386__) || defined(__x86_64__)
9036 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
9037 if(regs[i].dirty&1) printf("eax ");
9038 if((regs[i].dirty>>1)&1) printf("ecx ");
9039 if((regs[i].dirty>>2)&1) printf("edx ");
9040 if((regs[i].dirty>>3)&1) printf("ebx ");
9041 if((regs[i].dirty>>5)&1) printf("ebp ");
9042 if((regs[i].dirty>>6)&1) printf("esi ");
9043 if((regs[i].dirty>>7)&1) printf("edi ");
9044 #endif
9045 #ifdef __arm__
9046 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
9047 if(regs[i].dirty&1) printf("r0 ");
9048 if((regs[i].dirty>>1)&1) printf("r1 ");
9049 if((regs[i].dirty>>2)&1) printf("r2 ");
9050 if((regs[i].dirty>>3)&1) printf("r3 ");
9051 if((regs[i].dirty>>4)&1) printf("r4 ");
9052 if((regs[i].dirty>>5)&1) printf("r5 ");
9053 if((regs[i].dirty>>6)&1) printf("r6 ");
9054 if((regs[i].dirty>>7)&1) printf("r7 ");
9055 if((regs[i].dirty>>8)&1) printf("r8 ");
9056 if((regs[i].dirty>>9)&1) printf("r9 ");
9057 if((regs[i].dirty>>10)&1) printf("r10 ");
9058 if((regs[i].dirty>>12)&1) printf("r12 ");
9059 #endif
9060 printf("\n");
9061 if(regs[i].isconst) {
9062 printf("constants: ");
9063 #if defined(__i386__) || defined(__x86_64__)
643aeae3 9064 if(regs[i].isconst&1) printf("eax=%x ",(u_int)constmap[i][0]);
9065 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(u_int)constmap[i][1]);
9066 if((regs[i].isconst>>2)&1) printf("edx=%x ",(u_int)constmap[i][2]);
9067 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(u_int)constmap[i][3]);
9068 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(u_int)constmap[i][5]);
9069 if((regs[i].isconst>>6)&1) printf("esi=%x ",(u_int)constmap[i][6]);
9070 if((regs[i].isconst>>7)&1) printf("edi=%x ",(u_int)constmap[i][7]);
57871462 9071 #endif
7c3a5182 9072 #if defined(__arm__) || defined(__aarch64__)
643aeae3 9073 int r;
9074 for (r = 0; r < ARRAY_SIZE(constmap[i]); r++)
9075 if ((regs[i].isconst >> r) & 1)
9076 printf(" r%d=%x", r, (u_int)constmap[i][r]);
57871462 9077 #endif
9078 printf("\n");
9079 }
fe807a8a 9080 if(dops[i].is_jump) {
57871462 9081 #if defined(__i386__) || defined(__x86_64__)
9082 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
9083 if(branch_regs[i].dirty&1) printf("eax ");
9084 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
9085 if((branch_regs[i].dirty>>2)&1) printf("edx ");
9086 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
9087 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
9088 if((branch_regs[i].dirty>>6)&1) printf("esi ");
9089 if((branch_regs[i].dirty>>7)&1) printf("edi ");
9090 #endif
9091 #ifdef __arm__
9092 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
9093 if(branch_regs[i].dirty&1) printf("r0 ");
9094 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
9095 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
9096 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
9097 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
9098 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
9099 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
9100 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
9101 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
9102 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
9103 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
9104 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
9105 #endif
57871462 9106 }
9107 }
4600ba03 9108#endif // DISASM
57871462 9109
9110 /* Pass 8 - Assembly */
9111 linkcount=0;stubcount=0;
9112 ds=0;is_delayslot=0;
57871462 9113 u_int dirty_pre=0;
d148d265 9114 void *beginning=start_block();
57871462 9115 if((u_int)addr&1) {
9116 ds=1;
9117 pagespan_ds();
9118 }
df4dc2b1 9119 void *instr_addr0_override = NULL;
9ad4d757 9120
9ad4d757 9121 if (start == 0x80030000) {
3968e69e 9122 // nasty hack for the fastbios thing
96186eba 9123 // override block entry to this code
df4dc2b1 9124 instr_addr0_override = out;
9ad4d757 9125 emit_movimm(start,0);
96186eba 9126 // abuse io address var as a flag that we
9127 // have already returned here once
643aeae3 9128 emit_readword(&address,1);
9129 emit_writeword(0,&pcaddr);
9130 emit_writeword(0,&address);
9ad4d757 9131 emit_cmp(0,1);
3968e69e 9132 #ifdef __aarch64__
9133 emit_jeq(out + 4*2);
2a014d73 9134 emit_far_jump(new_dyna_leave);
3968e69e 9135 #else
643aeae3 9136 emit_jne(new_dyna_leave);
3968e69e 9137 #endif
9ad4d757 9138 }
57871462 9139 for(i=0;i<slen;i++)
9140 {
9141 //if(ds) printf("ds: ");
4600ba03 9142 disassemble_inst(i);
57871462 9143 if(ds) {
9144 ds=0; // Skip delay slot
cf95b4f0 9145 if(dops[i].bt) assem_debug("OOPS - branch into delay slot\n");
df4dc2b1 9146 instr_addr[i] = NULL;
57871462 9147 } else {
ffb0b9e0 9148 speculate_register_values(i);
57871462 9149 #ifndef DESTRUCTIVE_WRITEBACK
fe807a8a 9150 if (i < 2 || !dops[i-2].is_ujump)
57871462 9151 {
ad49de89 9152 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,unneeded_reg[i]);
57871462 9153 }
fe807a8a 9154 if((dops[i].itype==CJUMP||dops[i].itype==SJUMP)) {
f776eb14 9155 dirty_pre=branch_regs[i].dirty;
9156 }else{
f776eb14 9157 dirty_pre=regs[i].dirty;
9158 }
57871462 9159 #endif
9160 // write back
fe807a8a 9161 if (i < 2 || !dops[i-2].is_ujump)
57871462 9162 {
ad49de89 9163 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,unneeded_reg[i]);
57871462 9164 loop_preload(regmap_pre[i],regs[i].regmap_entry);
9165 }
9166 // branch target entry point
df4dc2b1 9167 instr_addr[i] = out;
57871462 9168 assem_debug("<->\n");
2330734f 9169 drc_dbg_emit_do_cmp(i, ccadj[i]);
dd114d7d 9170
57871462 9171 // load regs
9172 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
ad49de89 9173 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty);
cf95b4f0 9174 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i].rs1,dops[i].rs2);
57871462 9175 address_generation(i,&regs[i],regs[i].regmap_entry);
ad49de89 9176 load_consts(regmap_pre[i],regs[i].regmap,i);
fe807a8a 9177 if(dops[i].is_jump)
57871462 9178 {
9179 // Load the delay slot registers if necessary
cf95b4f0 9180 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2&&(dops[i+1].rs1!=dops[i].rt1||dops[i].rt1==0))
9181 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9182 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2&&(dops[i+1].rs2!=dops[i].rt1||dops[i].rt1==0))
9183 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
37387d8b 9184 if (ram_offset && (dops[i+1].is_load || dops[i+1].is_store))
9185 load_regs(regs[i].regmap_entry,regs[i].regmap,ROREG,ROREG);
9186 if (dops[i+1].is_store)
ad49de89 9187 load_regs(regs[i].regmap_entry,regs[i].regmap,INVCP,INVCP);
57871462 9188 }
9189 else if(i+1<slen)
9190 {
9191 // Preload registers for following instruction
cf95b4f0 9192 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2)
9193 if(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs1!=dops[i].rt2)
9194 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9195 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2)
9196 if(dops[i+1].rs2!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt2)
9197 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
57871462 9198 }
9199 // TODO: if(is_ooo(i)) address_generation(i+1);
37387d8b 9200 if (dops[i].itype == CJUMP)
ad49de89 9201 load_regs(regs[i].regmap_entry,regs[i].regmap,CCREG,CCREG);
37387d8b 9202 if (ram_offset && (dops[i].is_load || dops[i].is_store))
9203 load_regs(regs[i].regmap_entry,regs[i].regmap,ROREG,ROREG);
9204 if (dops[i].is_store)
ad49de89 9205 load_regs(regs[i].regmap_entry,regs[i].regmap,INVCP,INVCP);
2330734f 9206
9207 ds = assemble(i, &regs[i], ccadj[i]);
9208
fe807a8a 9209 if (dops[i].is_ujump)
57871462 9210 literal_pool(1024);
9211 else
9212 literal_pool_jumpover(256);
9213 }
9214 }
3d680478 9215
9216 assert(slen > 0);
cf95b4f0 9217 if (slen > 0 && dops[slen-1].itype == INTCALL) {
3d680478 9218 // no ending needed for this block since INTCALL never returns
9219 }
57871462 9220 // If the block did not end with an unconditional branch,
9221 // add a jump to the next instruction.
3d680478 9222 else if (i > 1) {
fe807a8a 9223 if (!dops[i-2].is_ujump && dops[i-1].itype != SPAN) {
9224 assert(!dops[i-1].is_jump);
57871462 9225 assert(i==slen);
cf95b4f0 9226 if(dops[i-2].itype!=CJUMP&&dops[i-2].itype!=SJUMP) {
ad49de89 9227 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
57871462 9228 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9229 emit_loadreg(CCREG,HOST_CCREG);
2330734f 9230 emit_addimm(HOST_CCREG, ccadj[i-1] + CLOCK_ADJUST(1), HOST_CCREG);
57871462 9231 }
fe807a8a 9232 else
57871462 9233 {
ad49de89 9234 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].dirty,start+i*4);
57871462 9235 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
9236 }
643aeae3 9237 add_to_linker(out,start+i*4,0);
57871462 9238 emit_jmp(0);
9239 }
9240 }
9241 else
9242 {
9243 assert(i>0);
fe807a8a 9244 assert(!dops[i-1].is_jump);
ad49de89 9245 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
57871462 9246 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9247 emit_loadreg(CCREG,HOST_CCREG);
2330734f 9248 emit_addimm(HOST_CCREG, ccadj[i-1] + CLOCK_ADJUST(1), HOST_CCREG);
643aeae3 9249 add_to_linker(out,start+i*4,0);
57871462 9250 emit_jmp(0);
9251 }
9252
9253 // TODO: delay slot stubs?
9254 // Stubs
9255 for(i=0;i<stubcount;i++)
9256 {
b14b6a8f 9257 switch(stubs[i].type)
57871462 9258 {
9259 case LOADB_STUB:
9260 case LOADH_STUB:
9261 case LOADW_STUB:
9262 case LOADD_STUB:
9263 case LOADBU_STUB:
9264 case LOADHU_STUB:
9265 do_readstub(i);break;
9266 case STOREB_STUB:
9267 case STOREH_STUB:
9268 case STOREW_STUB:
9269 case STORED_STUB:
9270 do_writestub(i);break;
9271 case CC_STUB:
9272 do_ccstub(i);break;
9273 case INVCODE_STUB:
9274 do_invstub(i);break;
9275 case FP_STUB:
9276 do_cop1stub(i);break;
9277 case STORELR_STUB:
9278 do_unalignedwritestub(i);break;
9279 }
9280 }
9281
9ad4d757 9282 if (instr_addr0_override)
9283 instr_addr[0] = instr_addr0_override;
9284
57871462 9285 /* Pass 9 - Linker */
9286 for(i=0;i<linkcount;i++)
9287 {
643aeae3 9288 assem_debug("%p -> %8x\n",link_addr[i].addr,link_addr[i].target);
57871462 9289 literal_pool(64);
643aeae3 9290 if (!link_addr[i].ext)
57871462 9291 {
643aeae3 9292 void *stub = out;
9293 void *addr = check_addr(link_addr[i].target);
9294 emit_extjump(link_addr[i].addr, link_addr[i].target);
9295 if (addr) {
9296 set_jump_target(link_addr[i].addr, addr);
3d680478 9297 add_jump_out(link_addr[i].target,stub);
57871462 9298 }
643aeae3 9299 else
9300 set_jump_target(link_addr[i].addr, stub);
57871462 9301 }
9302 else
9303 {
9304 // Internal branch
643aeae3 9305 int target=(link_addr[i].target-start)>>2;
57871462 9306 assert(target>=0&&target<slen);
9307 assert(instr_addr[target]);
9308 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
643aeae3 9309 //set_jump_target_fillslot(link_addr[i].addr,instr_addr[target],link_addr[i].ext>>1);
57871462 9310 //#else
643aeae3 9311 set_jump_target(link_addr[i].addr, instr_addr[target]);
57871462 9312 //#endif
9313 }
9314 }
3d680478 9315
9316 u_int source_len = slen*4;
cf95b4f0 9317 if (dops[slen-1].itype == INTCALL && source_len > 4)
3d680478 9318 // no need to treat the last instruction as compiled
9319 // as interpreter fully handles it
9320 source_len -= 4;
9321
9322 if ((u_char *)copy + source_len > (u_char *)shadow + sizeof(shadow))
9323 copy = shadow;
9324
57871462 9325 // External Branch Targets (jump_in)
57871462 9326 for(i=0;i<slen;i++)
9327 {
cf95b4f0 9328 if(dops[i].bt||i==0)
57871462 9329 {
9330 if(instr_addr[i]) // TODO - delay slots (=null)
9331 {
9332 u_int vaddr=start+i*4;
94d23bb9 9333 u_int page=get_page(vaddr);
9334 u_int vpage=get_vpage(vaddr);
57871462 9335 literal_pool(256);
57871462 9336 {
df4dc2b1 9337 assem_debug("%p (%d) <- %8x\n",instr_addr[i],i,start+i*4);
57871462 9338 assem_debug("jump_in: %x\n",start+i*4);
df4dc2b1 9339 ll_add(jump_dirty+vpage,vaddr,out);
3d680478 9340 void *entry_point = do_dirty_stub(i, source_len);
df4dc2b1 9341 ll_add_flags(jump_in+page,vaddr,state_rflags,entry_point);
57871462 9342 // If there was an existing entry in the hash table,
9343 // replace it with the new address.
9344 // Don't add new entries. We'll insert the
9345 // ones that actually get used in check_addr().
df4dc2b1 9346 struct ht_entry *ht_bin = hash_table_get(vaddr);
9347 if (ht_bin->vaddr[0] == vaddr)
9348 ht_bin->tcaddr[0] = entry_point;
9349 if (ht_bin->vaddr[1] == vaddr)
9350 ht_bin->tcaddr[1] = entry_point;
57871462 9351 }
57871462 9352 }
9353 }
9354 }
9355 // Write out the literal pool if necessary
9356 literal_pool(0);
9357 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
9358 // Align code
9359 if(((u_int)out)&7) emit_addnop(13);
9360 #endif
01d26796 9361 assert(out - (u_char *)beginning < MAX_OUTPUT_BLOCK_SIZE);
643aeae3 9362 //printf("shadow buffer: %p-%p\n",copy,(u_char *)copy+slen*4);
3d680478 9363 memcpy(copy, source, source_len);
9364 copy += source_len;
9f51b4b9 9365
d148d265 9366 end_block(beginning);
9f51b4b9 9367
57871462 9368 // If we're within 256K of the end of the buffer,
9369 // start over from the beginning. (Is 256K enough?)
2a014d73 9370 if (out > ndrc->translation_cache + sizeof(ndrc->translation_cache) - MAX_OUTPUT_BLOCK_SIZE)
9371 out = ndrc->translation_cache;
9f51b4b9 9372
57871462 9373 // Trap writes to any of the pages we compiled
9374 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
9375 invalid_code[i]=0;
57871462 9376 }
9be4ba64 9377 inv_code_start=inv_code_end=~0;
71e490c5 9378
b96d3df7 9379 // for PCSX we need to mark all mirrors too
b12c9fb8 9380 if(get_page(start)<(RAM_SIZE>>12))
9381 for(i=start>>12;i<=(start+slen*4)>>12;i++)
b96d3df7 9382 invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]=
9383 invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]=
9384 invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0;
9f51b4b9 9385
57871462 9386 /* Pass 10 - Free memory by expiring oldest blocks */
9f51b4b9 9387
2a014d73 9388 int end=(((out-ndrc->translation_cache)>>(TARGET_SIZE_2-16))+16384)&65535;
57871462 9389 while(expirep!=end)
9390 {
9391 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
943f42f3 9392 uintptr_t base_offs = ((uintptr_t)(expirep >> 13) << shift); // Base offset of this block
9393 uintptr_t base_offs_s = base_offs >> shift;
57871462 9394 inv_debug("EXP: Phase %d\n",expirep);
9395 switch((expirep>>11)&3)
9396 {
9397 case 0:
9398 // Clear jump_in and jump_dirty
943f42f3 9399 ll_remove_matching_addrs(jump_in+(expirep&2047),base_offs_s,shift);
9400 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base_offs_s,shift);
9401 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base_offs_s,shift);
9402 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base_offs_s,shift);
57871462 9403 break;
9404 case 1:
9405 // Clear pointers
943f42f3 9406 ll_kill_pointers(jump_out[expirep&2047],base_offs_s,shift);
9407 ll_kill_pointers(jump_out[(expirep&2047)+2048],base_offs_s,shift);
57871462 9408 break;
9409 case 2:
9410 // Clear hash table
9411 for(i=0;i<32;i++) {
df4dc2b1 9412 struct ht_entry *ht_bin = &hash_table[((expirep&2047)<<5)+i];
943f42f3 9413 uintptr_t o1 = (u_char *)ht_bin->tcaddr[1] - ndrc->translation_cache;
9414 uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
9415 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s) {
df4dc2b1 9416 inv_debug("EXP: Remove hash %x -> %p\n",ht_bin->vaddr[1],ht_bin->tcaddr[1]);
9417 ht_bin->vaddr[1] = -1;
9418 ht_bin->tcaddr[1] = NULL;
9419 }
943f42f3 9420 o1 = (u_char *)ht_bin->tcaddr[0] - ndrc->translation_cache;
9421 o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
9422 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s) {
df4dc2b1 9423 inv_debug("EXP: Remove hash %x -> %p\n",ht_bin->vaddr[0],ht_bin->tcaddr[0]);
9424 ht_bin->vaddr[0] = ht_bin->vaddr[1];
9425 ht_bin->tcaddr[0] = ht_bin->tcaddr[1];
9426 ht_bin->vaddr[1] = -1;
9427 ht_bin->tcaddr[1] = NULL;
57871462 9428 }
9429 }
9430 break;
9431 case 3:
9432 // Clear jump_out
9f51b4b9 9433 if((expirep&2047)==0)
dd3a91a1 9434 do_clear_cache();
943f42f3 9435 ll_remove_matching_addrs(jump_out+(expirep&2047),base_offs_s,shift);
9436 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base_offs_s,shift);
57871462 9437 break;
9438 }
9439 expirep=(expirep+1)&65535;
9440 }
37387d8b 9441#ifdef ASSEM_PRINT
9442 fflush(stdout);
9443#endif
57871462 9444 return 0;
9445}
b9b61529 9446
9447// vim:shiftwidth=2:expandtab
ARM optimized PCSX fork