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drc: do basic current block modification detection
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
CommitLineData
57871462 1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
20d507ba 3 * Copyright (C) 2009-2011 Ari64 *
57871462 4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21#include <stdlib.h>
22#include <stdint.h> //include for uint64_t
23#include <assert.h>
4600ba03 24#include <sys/mman.h>
57871462 25
3d624f89 26#include "emu_if.h" //emulator interface
57871462 27
4600ba03 28//#define DISASM
29//#define assem_debug printf
30//#define inv_debug printf
31#define assem_debug(...)
32#define inv_debug(...)
57871462 33
34#ifdef __i386__
35#include "assem_x86.h"
36#endif
37#ifdef __x86_64__
38#include "assem_x64.h"
39#endif
40#ifdef __arm__
41#include "assem_arm.h"
42#endif
43
44#define MAXBLOCK 4096
45#define MAX_OUTPUT_BLOCK_SIZE 262144
2573466a 46
57871462 47struct regstat
48{
49 signed char regmap_entry[HOST_REGS];
50 signed char regmap[HOST_REGS];
51 uint64_t was32;
52 uint64_t is32;
53 uint64_t wasdirty;
54 uint64_t dirty;
55 uint64_t u;
56 uint64_t uu;
57 u_int wasconst;
58 u_int isconst;
8575a877 59 u_int loadedconst; // host regs that have constants loaded
60 u_int waswritten; // MIPS regs that were used as store base before
57871462 61};
62
63struct ll_entry
64{
65 u_int vaddr;
66 u_int reg32;
67 void *addr;
68 struct ll_entry *next;
69};
70
71 u_int start;
72 u_int *source;
73 u_int pagelimit;
74 char insn[MAXBLOCK][10];
75 u_char itype[MAXBLOCK];
76 u_char opcode[MAXBLOCK];
77 u_char opcode2[MAXBLOCK];
78 u_char bt[MAXBLOCK];
79 u_char rs1[MAXBLOCK];
80 u_char rs2[MAXBLOCK];
81 u_char rt1[MAXBLOCK];
82 u_char rt2[MAXBLOCK];
83 u_char us1[MAXBLOCK];
84 u_char us2[MAXBLOCK];
85 u_char dep1[MAXBLOCK];
86 u_char dep2[MAXBLOCK];
87 u_char lt1[MAXBLOCK];
bedfea38 88 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
89 static uint64_t gte_rt[MAXBLOCK];
90 static uint64_t gte_unneeded[MAXBLOCK];
ffb0b9e0 91 static u_int smrv[32]; // speculated MIPS register values
92 static u_int smrv_strong; // mask or regs that are likely to have correct values
93 static u_int smrv_weak; // same, but somewhat less likely
94 static u_int smrv_strong_next; // same, but after current insn executes
95 static u_int smrv_weak_next;
57871462 96 int imm[MAXBLOCK];
97 u_int ba[MAXBLOCK];
98 char likely[MAXBLOCK];
99 char is_ds[MAXBLOCK];
e1190b87 100 char ooo[MAXBLOCK];
57871462 101 uint64_t unneeded_reg[MAXBLOCK];
102 uint64_t unneeded_reg_upper[MAXBLOCK];
103 uint64_t branch_unneeded_reg[MAXBLOCK];
104 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
105 uint64_t p32[MAXBLOCK];
106 uint64_t pr32[MAXBLOCK];
107 signed char regmap_pre[MAXBLOCK][HOST_REGS];
956f3129 108 static uint64_t current_constmap[HOST_REGS];
109 static uint64_t constmap[MAXBLOCK][HOST_REGS];
110 static struct regstat regs[MAXBLOCK];
111 static struct regstat branch_regs[MAXBLOCK];
e1190b87 112 signed char minimum_free_regs[MAXBLOCK];
57871462 113 u_int needed_reg[MAXBLOCK];
114 uint64_t requires_32bit[MAXBLOCK];
115 u_int wont_dirty[MAXBLOCK];
116 u_int will_dirty[MAXBLOCK];
117 int ccadj[MAXBLOCK];
118 int slen;
119 u_int instr_addr[MAXBLOCK];
120 u_int link_addr[MAXBLOCK][3];
121 int linkcount;
122 u_int stubs[MAXBLOCK*3][8];
123 int stubcount;
124 u_int literals[1024][2];
125 int literalcount;
126 int is_delayslot;
127 int cop1_usable;
128 u_char *out;
129 struct ll_entry *jump_in[4096];
130 struct ll_entry *jump_out[4096];
131 struct ll_entry *jump_dirty[4096];
132 u_int hash_table[65536][4] __attribute__((aligned(16)));
133 char shadow[1048576] __attribute__((aligned(16)));
134 void *copy;
135 int expirep;
af4ee1fe 136#ifndef PCSX
57871462 137 u_int using_tlb;
af4ee1fe 138#else
139 static const u_int using_tlb=0;
140#endif
2f546f9a 141 int new_dynarec_did_compile;
0ff8c62c 142 int new_dynarec_hacks;
57871462 143 u_int stop_after_jal;
144 extern u_char restore_candidate[512];
145 extern int cycle_count;
146
147 /* registers that may be allocated */
148 /* 1-31 gpr */
149#define HIREG 32 // hi
150#define LOREG 33 // lo
151#define FSREG 34 // FPU status (FCSR)
152#define CSREG 35 // Coprocessor status
153#define CCREG 36 // Cycle count
154#define INVCP 37 // Pointer to invalid_code
619e5ded 155#define MMREG 38 // Pointer to memory_map
156#define ROREG 39 // ram offset (if rdram!=0x80000000)
157#define TEMPREG 40
158#define FTEMP 40 // FPU temporary register
159#define PTEMP 41 // Prefetch temporary register
160#define TLREG 42 // TLB mapping offset
161#define RHASH 43 // Return address hash
162#define RHTBL 44 // Return address hash table address
163#define RTEMP 45 // JR/JALR address register
164#define MAXREG 45
165#define AGEN1 46 // Address generation temporary register
166#define AGEN2 47 // Address generation temporary register
167#define MGEN1 48 // Maptable address generation temporary register
168#define MGEN2 49 // Maptable address generation temporary register
169#define BTREG 50 // Branch target temporary register
57871462 170
171 /* instruction types */
172#define NOP 0 // No operation
173#define LOAD 1 // Load
174#define STORE 2 // Store
175#define LOADLR 3 // Unaligned load
176#define STORELR 4 // Unaligned store
177#define MOV 5 // Move
178#define ALU 6 // Arithmetic/logic
179#define MULTDIV 7 // Multiply/divide
180#define SHIFT 8 // Shift by register
181#define SHIFTIMM 9// Shift by immediate
182#define IMM16 10 // 16-bit immediate
183#define RJUMP 11 // Unconditional jump to register
184#define UJUMP 12 // Unconditional jump
185#define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
186#define SJUMP 14 // Conditional branch (regimm format)
187#define COP0 15 // Coprocessor 0
188#define COP1 16 // Coprocessor 1
189#define C1LS 17 // Coprocessor 1 load/store
190#define FJUMP 18 // Conditional branch (floating point)
191#define FLOAT 19 // Floating point unit
192#define FCONV 20 // Convert integer to float
193#define FCOMP 21 // Floating point compare (sets FSREG)
194#define SYSCALL 22// SYSCALL
195#define OTHER 23 // Other
196#define SPAN 24 // Branch/delay slot spans 2 pages
197#define NI 25 // Not implemented
7139f3c8 198#define HLECALL 26// PCSX fake opcodes for HLE
b9b61529 199#define COP2 27 // Coprocessor 2 move
200#define C2LS 28 // Coprocessor 2 load/store
201#define C2OP 29 // Coprocessor 2 operation
1e973cb0 202#define INTCALL 30// Call interpreter to handle rare corner cases
57871462 203
204 /* stubs */
205#define CC_STUB 1
206#define FP_STUB 2
207#define LOADB_STUB 3
208#define LOADH_STUB 4
209#define LOADW_STUB 5
210#define LOADD_STUB 6
211#define LOADBU_STUB 7
212#define LOADHU_STUB 8
213#define STOREB_STUB 9
214#define STOREH_STUB 10
215#define STOREW_STUB 11
216#define STORED_STUB 12
217#define STORELR_STUB 13
218#define INVCODE_STUB 14
219
220 /* branch codes */
221#define TAKEN 1
222#define NOTTAKEN 2
223#define NULLDS 3
224
225// asm linkage
226int new_recompile_block(int addr);
227void *get_addr_ht(u_int vaddr);
228void invalidate_block(u_int block);
229void invalidate_addr(u_int addr);
230void remove_hash(int vaddr);
231void jump_vaddr();
232void dyna_linker();
233void dyna_linker_ds();
234void verify_code();
235void verify_code_vm();
236void verify_code_ds();
237void cc_interrupt();
238void fp_exception();
239void fp_exception_ds();
240void jump_syscall();
7139f3c8 241void jump_syscall_hle();
57871462 242void jump_eret();
7139f3c8 243void jump_hlecall();
1e973cb0 244void jump_intcall();
7139f3c8 245void new_dyna_leave();
57871462 246
247// TLB
248void TLBWI_new();
249void TLBWR_new();
250void read_nomem_new();
251void read_nomemb_new();
252void read_nomemh_new();
253void read_nomemd_new();
254void write_nomem_new();
255void write_nomemb_new();
256void write_nomemh_new();
257void write_nomemd_new();
258void write_rdram_new();
259void write_rdramb_new();
260void write_rdramh_new();
261void write_rdramd_new();
262extern u_int memory_map[1048576];
263
264// Needed by assembler
265void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
266void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
267void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
268void load_all_regs(signed char i_regmap[]);
269void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
270void load_regs_entry(int t);
271void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
272
273int tracedebug=0;
274
275//#define DEBUG_CYCLE_COUNT 1
276
4e9dcd7f 277int cycle_multiplier; // 100 for 1.0
278
279static int CLOCK_ADJUST(int x)
280{
281 int s=(x>>31)|1;
282 return (x * cycle_multiplier + s * 50) / 100;
283}
284
94d23bb9 285static void tlb_hacks()
57871462 286{
94d23bb9 287#ifndef DISABLE_TLB
57871462 288 // Goldeneye hack
289 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
290 {
291 u_int addr;
292 int n;
293 switch (ROM_HEADER->Country_code&0xFF)
294 {
295 case 0x45: // U
296 addr=0x34b30;
297 break;
298 case 0x4A: // J
299 addr=0x34b70;
300 break;
301 case 0x50: // E
302 addr=0x329f0;
303 break;
304 default:
305 // Unknown country code
306 addr=0;
307 break;
308 }
309 u_int rom_addr=(u_int)rom;
310 #ifdef ROM_COPY
311 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
312 // in the lower 4G of memory to use this hack. Copy it if necessary.
313 if((void *)rom>(void *)0xffffffff) {
314 munmap(ROM_COPY, 67108864);
315 if(mmap(ROM_COPY, 12582912,
316 PROT_READ | PROT_WRITE,
317 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
318 -1, 0) <= 0) {printf("mmap() failed\n");}
319 memcpy(ROM_COPY,rom,12582912);
320 rom_addr=(u_int)ROM_COPY;
321 }
322 #endif
323 if(addr) {
324 for(n=0x7F000;n<0x80000;n++) {
325 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
326 }
327 }
328 }
94d23bb9 329#endif
57871462 330}
331
94d23bb9 332static u_int get_page(u_int vaddr)
57871462 333{
0ce47d46 334#ifndef PCSX
57871462 335 u_int page=(vaddr^0x80000000)>>12;
0ce47d46 336#else
337 u_int page=vaddr&~0xe0000000;
338 if (page < 0x1000000)
339 page &= ~0x0e00000; // RAM mirrors
340 page>>=12;
341#endif
94d23bb9 342#ifndef DISABLE_TLB
57871462 343 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
94d23bb9 344#endif
57871462 345 if(page>2048) page=2048+(page&2047);
94d23bb9 346 return page;
347}
348
d25604ca 349#ifndef PCSX
94d23bb9 350static u_int get_vpage(u_int vaddr)
351{
352 u_int vpage=(vaddr^0x80000000)>>12;
353#ifndef DISABLE_TLB
57871462 354 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
94d23bb9 355#endif
57871462 356 if(vpage>2048) vpage=2048+(vpage&2047);
94d23bb9 357 return vpage;
358}
d25604ca 359#else
360// no virtual mem in PCSX
361static u_int get_vpage(u_int vaddr)
362{
363 return get_page(vaddr);
364}
365#endif
94d23bb9 366
367// Get address from virtual address
368// This is called from the recompiled JR/JALR instructions
369void *get_addr(u_int vaddr)
370{
371 u_int page=get_page(vaddr);
372 u_int vpage=get_vpage(vaddr);
57871462 373 struct ll_entry *head;
374 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
375 head=jump_in[page];
376 while(head!=NULL) {
377 if(head->vaddr==vaddr&&head->reg32==0) {
378 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
379 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
380 ht_bin[3]=ht_bin[1];
381 ht_bin[2]=ht_bin[0];
382 ht_bin[1]=(int)head->addr;
383 ht_bin[0]=vaddr;
384 return head->addr;
385 }
386 head=head->next;
387 }
388 head=jump_dirty[vpage];
389 while(head!=NULL) {
390 if(head->vaddr==vaddr&&head->reg32==0) {
391 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
392 // Don't restore blocks which are about to expire from the cache
393 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
394 if(verify_dirty(head->addr)) {
395 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
396 invalid_code[vaddr>>12]=0;
9be4ba64 397 inv_code_start=inv_code_end=~0;
63cb0298 398#ifndef DISABLE_TLB
57871462 399 memory_map[vaddr>>12]|=0x40000000;
63cb0298 400#endif
57871462 401 if(vpage<2048) {
94d23bb9 402#ifndef DISABLE_TLB
57871462 403 if(tlb_LUT_r[vaddr>>12]) {
404 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
405 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
406 }
94d23bb9 407#endif
57871462 408 restore_candidate[vpage>>3]|=1<<(vpage&7);
409 }
410 else restore_candidate[page>>3]|=1<<(page&7);
411 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
412 if(ht_bin[0]==vaddr) {
413 ht_bin[1]=(int)head->addr; // Replace existing entry
414 }
415 else
416 {
417 ht_bin[3]=ht_bin[1];
418 ht_bin[2]=ht_bin[0];
419 ht_bin[1]=(int)head->addr;
420 ht_bin[0]=vaddr;
421 }
422 return head->addr;
423 }
424 }
425 head=head->next;
426 }
427 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
428 int r=new_recompile_block(vaddr);
429 if(r==0) return get_addr(vaddr);
430 // Execute in unmapped page, generate pagefault execption
431 Status|=2;
432 Cause=(vaddr<<31)|0x8;
433 EPC=(vaddr&1)?vaddr-5:vaddr;
434 BadVAddr=(vaddr&~1);
435 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
436 EntryHi=BadVAddr&0xFFFFE000;
437 return get_addr_ht(0x80000000);
438}
439// Look up address in hash table first
440void *get_addr_ht(u_int vaddr)
441{
442 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
443 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
444 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
445 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
446 return get_addr(vaddr);
447}
448
449void *get_addr_32(u_int vaddr,u_int flags)
450{
7139f3c8 451#ifdef FORCE32
452 return get_addr(vaddr);
560e4a12 453#else
57871462 454 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
455 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
456 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
457 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
94d23bb9 458 u_int page=get_page(vaddr);
459 u_int vpage=get_vpage(vaddr);
57871462 460 struct ll_entry *head;
461 head=jump_in[page];
462 while(head!=NULL) {
463 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
464 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
465 if(head->reg32==0) {
466 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
467 if(ht_bin[0]==-1) {
468 ht_bin[1]=(int)head->addr;
469 ht_bin[0]=vaddr;
470 }else if(ht_bin[2]==-1) {
471 ht_bin[3]=(int)head->addr;
472 ht_bin[2]=vaddr;
473 }
474 //ht_bin[3]=ht_bin[1];
475 //ht_bin[2]=ht_bin[0];
476 //ht_bin[1]=(int)head->addr;
477 //ht_bin[0]=vaddr;
478 }
479 return head->addr;
480 }
481 head=head->next;
482 }
483 head=jump_dirty[vpage];
484 while(head!=NULL) {
485 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
486 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
487 // Don't restore blocks which are about to expire from the cache
488 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
489 if(verify_dirty(head->addr)) {
490 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
491 invalid_code[vaddr>>12]=0;
9be4ba64 492 inv_code_start=inv_code_end=~0;
57871462 493 memory_map[vaddr>>12]|=0x40000000;
494 if(vpage<2048) {
94d23bb9 495#ifndef DISABLE_TLB
57871462 496 if(tlb_LUT_r[vaddr>>12]) {
497 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
498 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
499 }
94d23bb9 500#endif
57871462 501 restore_candidate[vpage>>3]|=1<<(vpage&7);
502 }
503 else restore_candidate[page>>3]|=1<<(page&7);
504 if(head->reg32==0) {
505 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
506 if(ht_bin[0]==-1) {
507 ht_bin[1]=(int)head->addr;
508 ht_bin[0]=vaddr;
509 }else if(ht_bin[2]==-1) {
510 ht_bin[3]=(int)head->addr;
511 ht_bin[2]=vaddr;
512 }
513 //ht_bin[3]=ht_bin[1];
514 //ht_bin[2]=ht_bin[0];
515 //ht_bin[1]=(int)head->addr;
516 //ht_bin[0]=vaddr;
517 }
518 return head->addr;
519 }
520 }
521 head=head->next;
522 }
523 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
524 int r=new_recompile_block(vaddr);
525 if(r==0) return get_addr(vaddr);
526 // Execute in unmapped page, generate pagefault execption
527 Status|=2;
528 Cause=(vaddr<<31)|0x8;
529 EPC=(vaddr&1)?vaddr-5:vaddr;
530 BadVAddr=(vaddr&~1);
531 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
532 EntryHi=BadVAddr&0xFFFFE000;
533 return get_addr_ht(0x80000000);
560e4a12 534#endif
57871462 535}
536
537void clear_all_regs(signed char regmap[])
538{
539 int hr;
540 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
541}
542
543signed char get_reg(signed char regmap[],int r)
544{
545 int hr;
546 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
547 return -1;
548}
549
550// Find a register that is available for two consecutive cycles
551signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
552{
553 int hr;
554 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
555 return -1;
556}
557
558int count_free_regs(signed char regmap[])
559{
560 int count=0;
561 int hr;
562 for(hr=0;hr<HOST_REGS;hr++)
563 {
564 if(hr!=EXCLUDE_REG) {
565 if(regmap[hr]<0) count++;
566 }
567 }
568 return count;
569}
570
571void dirty_reg(struct regstat *cur,signed char reg)
572{
573 int hr;
574 if(!reg) return;
575 for (hr=0;hr<HOST_REGS;hr++) {
576 if((cur->regmap[hr]&63)==reg) {
577 cur->dirty|=1<<hr;
578 }
579 }
580}
581
582// If we dirty the lower half of a 64 bit register which is now being
583// sign-extended, we need to dump the upper half.
584// Note: Do this only after completion of the instruction, because
585// some instructions may need to read the full 64-bit value even if
586// overwriting it (eg SLTI, DSRA32).
587static void flush_dirty_uppers(struct regstat *cur)
588{
589 int hr,reg;
590 for (hr=0;hr<HOST_REGS;hr++) {
591 if((cur->dirty>>hr)&1) {
592 reg=cur->regmap[hr];
593 if(reg>=64)
594 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
595 }
596 }
597}
598
599void set_const(struct regstat *cur,signed char reg,uint64_t value)
600{
601 int hr;
602 if(!reg) return;
603 for (hr=0;hr<HOST_REGS;hr++) {
604 if(cur->regmap[hr]==reg) {
605 cur->isconst|=1<<hr;
956f3129 606 current_constmap[hr]=value;
57871462 607 }
608 else if((cur->regmap[hr]^64)==reg) {
609 cur->isconst|=1<<hr;
956f3129 610 current_constmap[hr]=value>>32;
57871462 611 }
612 }
613}
614
615void clear_const(struct regstat *cur,signed char reg)
616{
617 int hr;
618 if(!reg) return;
619 for (hr=0;hr<HOST_REGS;hr++) {
620 if((cur->regmap[hr]&63)==reg) {
621 cur->isconst&=~(1<<hr);
622 }
623 }
624}
625
626int is_const(struct regstat *cur,signed char reg)
627{
628 int hr;
79c75f1b 629 if(reg<0) return 0;
57871462 630 if(!reg) return 1;
631 for (hr=0;hr<HOST_REGS;hr++) {
632 if((cur->regmap[hr]&63)==reg) {
633 return (cur->isconst>>hr)&1;
634 }
635 }
636 return 0;
637}
638uint64_t get_const(struct regstat *cur,signed char reg)
639{
640 int hr;
641 if(!reg) return 0;
642 for (hr=0;hr<HOST_REGS;hr++) {
643 if(cur->regmap[hr]==reg) {
956f3129 644 return current_constmap[hr];
57871462 645 }
646 }
647 printf("Unknown constant in r%d\n",reg);
648 exit(1);
649}
650
651// Least soon needed registers
652// Look at the next ten instructions and see which registers
653// will be used. Try not to reallocate these.
654void lsn(u_char hsn[], int i, int *preferred_reg)
655{
656 int j;
657 int b=-1;
658 for(j=0;j<9;j++)
659 {
660 if(i+j>=slen) {
661 j=slen-i-1;
662 break;
663 }
664 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
665 {
666 // Don't go past an unconditonal jump
667 j++;
668 break;
669 }
670 }
671 for(;j>=0;j--)
672 {
673 if(rs1[i+j]) hsn[rs1[i+j]]=j;
674 if(rs2[i+j]) hsn[rs2[i+j]]=j;
675 if(rt1[i+j]) hsn[rt1[i+j]]=j;
676 if(rt2[i+j]) hsn[rt2[i+j]]=j;
677 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
678 // Stores can allocate zero
679 hsn[rs1[i+j]]=j;
680 hsn[rs2[i+j]]=j;
681 }
682 // On some architectures stores need invc_ptr
683 #if defined(HOST_IMM8)
b9b61529 684 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
57871462 685 hsn[INVCP]=j;
686 }
687 #endif
688 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
689 {
690 hsn[CCREG]=j;
691 b=j;
692 }
693 }
694 if(b>=0)
695 {
696 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
697 {
698 // Follow first branch
699 int t=(ba[i+b]-start)>>2;
700 j=7-b;if(t+j>=slen) j=slen-t-1;
701 for(;j>=0;j--)
702 {
703 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
704 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
705 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
706 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
707 }
708 }
709 // TODO: preferred register based on backward branch
710 }
711 // Delay slot should preferably not overwrite branch conditions or cycle count
712 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
713 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
714 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
715 hsn[CCREG]=1;
716 // ...or hash tables
717 hsn[RHASH]=1;
718 hsn[RHTBL]=1;
719 }
720 // Coprocessor load/store needs FTEMP, even if not declared
b9b61529 721 if(itype[i]==C1LS||itype[i]==C2LS) {
57871462 722 hsn[FTEMP]=0;
723 }
724 // Load L/R also uses FTEMP as a temporary register
725 if(itype[i]==LOADLR) {
726 hsn[FTEMP]=0;
727 }
b7918751 728 // Also SWL/SWR/SDL/SDR
729 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
57871462 730 hsn[FTEMP]=0;
731 }
732 // Don't remove the TLB registers either
b9b61529 733 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
57871462 734 hsn[TLREG]=0;
735 }
736 // Don't remove the miniht registers
737 if(itype[i]==UJUMP||itype[i]==RJUMP)
738 {
739 hsn[RHASH]=0;
740 hsn[RHTBL]=0;
741 }
742}
743
744// We only want to allocate registers if we're going to use them again soon
745int needed_again(int r, int i)
746{
747 int j;
748 int b=-1;
749 int rn=10;
57871462 750
751 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
752 {
753 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
754 return 0; // Don't need any registers if exiting the block
755 }
756 for(j=0;j<9;j++)
757 {
758 if(i+j>=slen) {
759 j=slen-i-1;
760 break;
761 }
762 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
763 {
764 // Don't go past an unconditonal jump
765 j++;
766 break;
767 }
1e973cb0 768 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
57871462 769 {
770 break;
771 }
772 }
773 for(;j>=1;j--)
774 {
775 if(rs1[i+j]==r) rn=j;
776 if(rs2[i+j]==r) rn=j;
777 if((unneeded_reg[i+j]>>r)&1) rn=10;
778 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
779 {
780 b=j;
781 }
782 }
783 /*
784 if(b>=0)
785 {
786 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
787 {
788 // Follow first branch
789 int o=rn;
790 int t=(ba[i+b]-start)>>2;
791 j=7-b;if(t+j>=slen) j=slen-t-1;
792 for(;j>=0;j--)
793 {
794 if(!((unneeded_reg[t+j]>>r)&1)) {
795 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
796 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
797 }
798 else rn=o;
799 }
800 }
801 }*/
b7217e13 802 if(rn<10) return 1;
57871462 803 return 0;
804}
805
806// Try to match register allocations at the end of a loop with those
807// at the beginning
808int loop_reg(int i, int r, int hr)
809{
810 int j,k;
811 for(j=0;j<9;j++)
812 {
813 if(i+j>=slen) {
814 j=slen-i-1;
815 break;
816 }
817 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
818 {
819 // Don't go past an unconditonal jump
820 j++;
821 break;
822 }
823 }
824 k=0;
825 if(i>0){
826 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
827 k--;
828 }
829 for(;k<j;k++)
830 {
831 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
832 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
833 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
834 {
835 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
836 {
837 int t=(ba[i+k]-start)>>2;
838 int reg=get_reg(regs[t].regmap_entry,r);
839 if(reg>=0) return reg;
840 //reg=get_reg(regs[t+1].regmap_entry,r);
841 //if(reg>=0) return reg;
842 }
843 }
844 }
845 return hr;
846}
847
848
849// Allocate every register, preserving source/target regs
850void alloc_all(struct regstat *cur,int i)
851{
852 int hr;
853
854 for(hr=0;hr<HOST_REGS;hr++) {
855 if(hr!=EXCLUDE_REG) {
856 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
857 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
858 {
859 cur->regmap[hr]=-1;
860 cur->dirty&=~(1<<hr);
861 }
862 // Don't need zeros
863 if((cur->regmap[hr]&63)==0)
864 {
865 cur->regmap[hr]=-1;
866 cur->dirty&=~(1<<hr);
867 }
868 }
869 }
870}
871
4600ba03 872#ifndef FORCE32
57871462 873void div64(int64_t dividend,int64_t divisor)
874{
875 lo=dividend/divisor;
876 hi=dividend%divisor;
877 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
878 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
879}
880void divu64(uint64_t dividend,uint64_t divisor)
881{
882 lo=dividend/divisor;
883 hi=dividend%divisor;
884 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
885 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
886}
887
888void mult64(uint64_t m1,uint64_t m2)
889{
890 unsigned long long int op1, op2, op3, op4;
891 unsigned long long int result1, result2, result3, result4;
892 unsigned long long int temp1, temp2, temp3, temp4;
893 int sign = 0;
894
895 if (m1 < 0)
896 {
897 op2 = -m1;
898 sign = 1 - sign;
899 }
900 else op2 = m1;
901 if (m2 < 0)
902 {
903 op4 = -m2;
904 sign = 1 - sign;
905 }
906 else op4 = m2;
907
908 op1 = op2 & 0xFFFFFFFF;
909 op2 = (op2 >> 32) & 0xFFFFFFFF;
910 op3 = op4 & 0xFFFFFFFF;
911 op4 = (op4 >> 32) & 0xFFFFFFFF;
912
913 temp1 = op1 * op3;
914 temp2 = (temp1 >> 32) + op1 * op4;
915 temp3 = op2 * op3;
916 temp4 = (temp3 >> 32) + op2 * op4;
917
918 result1 = temp1 & 0xFFFFFFFF;
919 result2 = temp2 + (temp3 & 0xFFFFFFFF);
920 result3 = (result2 >> 32) + temp4;
921 result4 = (result3 >> 32);
922
923 lo = result1 | (result2 << 32);
924 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
925 if (sign)
926 {
927 hi = ~hi;
928 if (!lo) hi++;
929 else lo = ~lo + 1;
930 }
931}
932
933void multu64(uint64_t m1,uint64_t m2)
934{
935 unsigned long long int op1, op2, op3, op4;
936 unsigned long long int result1, result2, result3, result4;
937 unsigned long long int temp1, temp2, temp3, temp4;
938
939 op1 = m1 & 0xFFFFFFFF;
940 op2 = (m1 >> 32) & 0xFFFFFFFF;
941 op3 = m2 & 0xFFFFFFFF;
942 op4 = (m2 >> 32) & 0xFFFFFFFF;
943
944 temp1 = op1 * op3;
945 temp2 = (temp1 >> 32) + op1 * op4;
946 temp3 = op2 * op3;
947 temp4 = (temp3 >> 32) + op2 * op4;
948
949 result1 = temp1 & 0xFFFFFFFF;
950 result2 = temp2 + (temp3 & 0xFFFFFFFF);
951 result3 = (result2 >> 32) + temp4;
952 result4 = (result3 >> 32);
953
954 lo = result1 | (result2 << 32);
955 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
956
957 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
958 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
959}
960
961uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
962{
963 if(bits) {
964 original<<=64-bits;
965 original>>=64-bits;
966 loaded<<=bits;
967 original|=loaded;
968 }
969 else original=loaded;
970 return original;
971}
972uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
973{
974 if(bits^56) {
975 original>>=64-(bits^56);
976 original<<=64-(bits^56);
977 loaded>>=bits^56;
978 original|=loaded;
979 }
980 else original=loaded;
981 return original;
982}
4600ba03 983#endif
57871462 984
985#ifdef __i386__
986#include "assem_x86.c"
987#endif
988#ifdef __x86_64__
989#include "assem_x64.c"
990#endif
991#ifdef __arm__
992#include "assem_arm.c"
993#endif
994
995// Add virtual address mapping to linked list
996void ll_add(struct ll_entry **head,int vaddr,void *addr)
997{
998 struct ll_entry *new_entry;
999 new_entry=malloc(sizeof(struct ll_entry));
1000 assert(new_entry!=NULL);
1001 new_entry->vaddr=vaddr;
1002 new_entry->reg32=0;
1003 new_entry->addr=addr;
1004 new_entry->next=*head;
1005 *head=new_entry;
1006}
1007
1008// Add virtual address mapping for 32-bit compiled block
1009void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
1010{
7139f3c8 1011 ll_add(head,vaddr,addr);
1012#ifndef FORCE32
1013 (*head)->reg32=reg32;
1014#endif
57871462 1015}
1016
1017// Check if an address is already compiled
1018// but don't return addresses which are about to expire from the cache
1019void *check_addr(u_int vaddr)
1020{
1021 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
1022 if(ht_bin[0]==vaddr) {
1023 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1024 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
1025 }
1026 if(ht_bin[2]==vaddr) {
1027 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1028 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1029 }
94d23bb9 1030 u_int page=get_page(vaddr);
57871462 1031 struct ll_entry *head;
1032 head=jump_in[page];
1033 while(head!=NULL) {
1034 if(head->vaddr==vaddr&&head->reg32==0) {
1035 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1036 // Update existing entry with current address
1037 if(ht_bin[0]==vaddr) {
1038 ht_bin[1]=(int)head->addr;
1039 return head->addr;
1040 }
1041 if(ht_bin[2]==vaddr) {
1042 ht_bin[3]=(int)head->addr;
1043 return head->addr;
1044 }
1045 // Insert into hash table with low priority.
1046 // Don't evict existing entries, as they are probably
1047 // addresses that are being accessed frequently.
1048 if(ht_bin[0]==-1) {
1049 ht_bin[1]=(int)head->addr;
1050 ht_bin[0]=vaddr;
1051 }else if(ht_bin[2]==-1) {
1052 ht_bin[3]=(int)head->addr;
1053 ht_bin[2]=vaddr;
1054 }
1055 return head->addr;
1056 }
1057 }
1058 head=head->next;
1059 }
1060 return 0;
1061}
1062
1063void remove_hash(int vaddr)
1064{
1065 //printf("remove hash: %x\n",vaddr);
1066 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1067 if(ht_bin[2]==vaddr) {
1068 ht_bin[2]=ht_bin[3]=-1;
1069 }
1070 if(ht_bin[0]==vaddr) {
1071 ht_bin[0]=ht_bin[2];
1072 ht_bin[1]=ht_bin[3];
1073 ht_bin[2]=ht_bin[3]=-1;
1074 }
1075}
1076
1077void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1078{
1079 struct ll_entry *next;
1080 while(*head) {
1081 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1082 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1083 {
1084 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1085 remove_hash((*head)->vaddr);
1086 next=(*head)->next;
1087 free(*head);
1088 *head=next;
1089 }
1090 else
1091 {
1092 head=&((*head)->next);
1093 }
1094 }
1095}
1096
1097// Remove all entries from linked list
1098void ll_clear(struct ll_entry **head)
1099{
1100 struct ll_entry *cur;
1101 struct ll_entry *next;
1102 if(cur=*head) {
1103 *head=0;
1104 while(cur) {
1105 next=cur->next;
1106 free(cur);
1107 cur=next;
1108 }
1109 }
1110}
1111
1112// Dereference the pointers and remove if it matches
1113void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1114{
1115 while(head) {
1116 int ptr=get_pointer(head->addr);
1117 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1118 if(((ptr>>shift)==(addr>>shift)) ||
1119 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1120 {
5088bb70 1121 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
f76eeef9 1122 u_int host_addr=(u_int)kill_pointer(head->addr);
dd3a91a1 1123 #ifdef __arm__
1124 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1125 #endif
57871462 1126 }
1127 head=head->next;
1128 }
1129}
1130
1131// This is called when we write to a compiled block (see do_invstub)
f76eeef9 1132void invalidate_page(u_int page)
57871462 1133{
57871462 1134 struct ll_entry *head;
1135 struct ll_entry *next;
1136 head=jump_in[page];
1137 jump_in[page]=0;
1138 while(head!=NULL) {
1139 inv_debug("INVALIDATE: %x\n",head->vaddr);
1140 remove_hash(head->vaddr);
1141 next=head->next;
1142 free(head);
1143 head=next;
1144 }
1145 head=jump_out[page];
1146 jump_out[page]=0;
1147 while(head!=NULL) {
1148 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
f76eeef9 1149 u_int host_addr=(u_int)kill_pointer(head->addr);
dd3a91a1 1150 #ifdef __arm__
1151 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1152 #endif
57871462 1153 next=head->next;
1154 free(head);
1155 head=next;
1156 }
57871462 1157}
9be4ba64 1158
1159static void invalidate_block_range(u_int block, u_int first, u_int last)
57871462 1160{
94d23bb9 1161 u_int page=get_page(block<<12);
57871462 1162 //printf("first=%d last=%d\n",first,last);
f76eeef9 1163 invalidate_page(page);
57871462 1164 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1165 assert(last<page+5);
1166 // Invalidate the adjacent pages if a block crosses a 4K boundary
1167 while(first<page) {
1168 invalidate_page(first);
1169 first++;
1170 }
1171 for(first=page+1;first<last;first++) {
1172 invalidate_page(first);
1173 }
dd3a91a1 1174 #ifdef __arm__
1175 do_clear_cache();
1176 #endif
57871462 1177
1178 // Don't trap writes
1179 invalid_code[block]=1;
94d23bb9 1180#ifndef DISABLE_TLB
57871462 1181 // If there is a valid TLB entry for this page, remove write protect
1182 if(tlb_LUT_w[block]) {
1183 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1184 // CHECK: Is this right?
1185 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1186 u_int real_block=tlb_LUT_w[block]>>12;
1187 invalid_code[real_block]=1;
1188 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1189 }
1190 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
94d23bb9 1191#endif
f76eeef9 1192
57871462 1193 #ifdef USE_MINI_HT
1194 memset(mini_ht,-1,sizeof(mini_ht));
1195 #endif
1196}
9be4ba64 1197
1198void invalidate_block(u_int block)
1199{
1200 u_int page=get_page(block<<12);
1201 u_int vpage=get_vpage(block<<12);
1202 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1203 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1204 u_int first,last;
1205 first=last=page;
1206 struct ll_entry *head;
1207 head=jump_dirty[vpage];
1208 //printf("page=%d vpage=%d\n",page,vpage);
1209 while(head!=NULL) {
1210 u_int start,end;
1211 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1212 get_bounds((int)head->addr,&start,&end);
1213 //printf("start: %x end: %x\n",start,end);
1214 if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
1215 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1216 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1217 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1218 }
1219 }
1220#ifndef DISABLE_TLB
1221 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1222 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1223 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1224 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1225 }
1226 }
1227#endif
1228 }
1229 head=head->next;
1230 }
1231 invalidate_block_range(block,first,last);
1232}
1233
57871462 1234void invalidate_addr(u_int addr)
1235{
9be4ba64 1236#ifdef PCSX
1237 //static int rhits;
1238 // this check is done by the caller
1239 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
d25604ca 1240 u_int page=get_vpage(addr);
9be4ba64 1241 if(page<2048) { // RAM
1242 struct ll_entry *head;
1243 u_int addr_min=~0, addr_max=0;
1244 int mask=RAM_SIZE-1;
1245 int pg1;
1246 inv_code_start=addr&~0xfff;
1247 inv_code_end=addr|0xfff;
1248 pg1=page;
1249 if (pg1>0) {
1250 // must check previous page too because of spans..
1251 pg1--;
1252 inv_code_start-=0x1000;
1253 }
1254 for(;pg1<=page;pg1++) {
1255 for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
1256 u_int start,end;
1257 get_bounds((int)head->addr,&start,&end);
1258 if((start&mask)<=(addr&mask)&&(addr&mask)<(end&mask)) {
1259 if(start<addr_min) addr_min=start;
1260 if(end>addr_max) addr_max=end;
1261 }
1262 else if(addr<start) {
1263 if(start<inv_code_end)
1264 inv_code_end=start-1;
1265 }
1266 else {
1267 if(end>inv_code_start)
1268 inv_code_start=end;
1269 }
1270 }
1271 }
1272 if (addr_min!=~0) {
1273 inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1274 inv_code_start=inv_code_end=~0;
1275 invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1276 return;
1277 }
1278 else {
d25604ca 1279 inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);
9be4ba64 1280 return;
d25604ca 1281 }
9be4ba64 1282 }
1283#endif
57871462 1284 invalidate_block(addr>>12);
1285}
9be4ba64 1286
dd3a91a1 1287// This is called when loading a save state.
1288// Anything could have changed, so invalidate everything.
57871462 1289void invalidate_all_pages()
1290{
1291 u_int page,n;
1292 for(page=0;page<4096;page++)
1293 invalidate_page(page);
1294 for(page=0;page<1048576;page++)
1295 if(!invalid_code[page]) {
1296 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1297 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1298 }
1299 #ifdef __arm__
1300 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1301 #endif
1302 #ifdef USE_MINI_HT
1303 memset(mini_ht,-1,sizeof(mini_ht));
1304 #endif
94d23bb9 1305 #ifndef DISABLE_TLB
57871462 1306 // TLB
1307 for(page=0;page<0x100000;page++) {
1308 if(tlb_LUT_r[page]) {
1309 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1310 if(!tlb_LUT_w[page]||!invalid_code[page])
1311 memory_map[page]|=0x40000000; // Write protect
1312 }
1313 else memory_map[page]=-1;
1314 if(page==0x80000) page=0xC0000;
1315 }
1316 tlb_hacks();
94d23bb9 1317 #endif
57871462 1318}
1319
1320// Add an entry to jump_out after making a link
1321void add_link(u_int vaddr,void *src)
1322{
94d23bb9 1323 u_int page=get_page(vaddr);
57871462 1324 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
76f71c27 1325 int *ptr=(int *)(src+4);
1326 assert((*ptr&0x0fff0000)==0x059f0000);
57871462 1327 ll_add(jump_out+page,vaddr,src);
1328 //int ptr=get_pointer(src);
1329 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1330}
1331
1332// If a code block was found to be unmodified (bit was set in
1333// restore_candidate) and it remains unmodified (bit is clear
1334// in invalid_code) then move the entries for that 4K page from
1335// the dirty list to the clean list.
1336void clean_blocks(u_int page)
1337{
1338 struct ll_entry *head;
1339 inv_debug("INV: clean_blocks page=%d\n",page);
1340 head=jump_dirty[page];
1341 while(head!=NULL) {
1342 if(!invalid_code[head->vaddr>>12]) {
1343 // Don't restore blocks which are about to expire from the cache
1344 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1345 u_int start,end;
1346 if(verify_dirty((int)head->addr)) {
1347 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1348 u_int i;
1349 u_int inv=0;
1350 get_bounds((int)head->addr,&start,&end);
4cb76aa4 1351 if(start-(u_int)rdram<RAM_SIZE) {
57871462 1352 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1353 inv|=invalid_code[i];
1354 }
1355 }
63cb0298 1356#ifndef DISABLE_TLB
57871462 1357 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1358 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1359 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1360 if(addr<start||addr>=end) inv=1;
1361 }
63cb0298 1362#endif
4cb76aa4 1363 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
57871462 1364 inv=1;
1365 }
1366 if(!inv) {
1367 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1368 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1369 u_int ppage=page;
94d23bb9 1370#ifndef DISABLE_TLB
57871462 1371 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
94d23bb9 1372#endif
57871462 1373 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1374 //printf("page=%x, addr=%x\n",page,head->vaddr);
1375 //assert(head->vaddr>>12==(page|0x80000));
1376 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1377 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1378 if(!head->reg32) {
1379 if(ht_bin[0]==head->vaddr) {
1380 ht_bin[1]=(int)clean_addr; // Replace existing entry
1381 }
1382 if(ht_bin[2]==head->vaddr) {
1383 ht_bin[3]=(int)clean_addr; // Replace existing entry
1384 }
1385 }
1386 }
1387 }
1388 }
1389 }
1390 }
1391 head=head->next;
1392 }
1393}
1394
1395
1396void mov_alloc(struct regstat *current,int i)
1397{
1398 // Note: Don't need to actually alloc the source registers
1399 if((~current->is32>>rs1[i])&1) {
1400 //alloc_reg64(current,i,rs1[i]);
1401 alloc_reg64(current,i,rt1[i]);
1402 current->is32&=~(1LL<<rt1[i]);
1403 } else {
1404 //alloc_reg(current,i,rs1[i]);
1405 alloc_reg(current,i,rt1[i]);
1406 current->is32|=(1LL<<rt1[i]);
1407 }
1408 clear_const(current,rs1[i]);
1409 clear_const(current,rt1[i]);
1410 dirty_reg(current,rt1[i]);
1411}
1412
1413void shiftimm_alloc(struct regstat *current,int i)
1414{
57871462 1415 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1416 {
1417 if(rt1[i]) {
1418 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1419 else lt1[i]=rs1[i];
1420 alloc_reg(current,i,rt1[i]);
1421 current->is32|=1LL<<rt1[i];
1422 dirty_reg(current,rt1[i]);
dc49e339 1423 if(is_const(current,rs1[i])) {
1424 int v=get_const(current,rs1[i]);
1425 if(opcode2[i]==0x00) set_const(current,rt1[i],v<<imm[i]);
1426 if(opcode2[i]==0x02) set_const(current,rt1[i],(u_int)v>>imm[i]);
1427 if(opcode2[i]==0x03) set_const(current,rt1[i],v>>imm[i]);
1428 }
1429 else clear_const(current,rt1[i]);
57871462 1430 }
1431 }
dc49e339 1432 else
1433 {
1434 clear_const(current,rs1[i]);
1435 clear_const(current,rt1[i]);
1436 }
1437
57871462 1438 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1439 {
1440 if(rt1[i]) {
1441 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1442 alloc_reg64(current,i,rt1[i]);
1443 current->is32&=~(1LL<<rt1[i]);
1444 dirty_reg(current,rt1[i]);
1445 }
1446 }
1447 if(opcode2[i]==0x3c) // DSLL32
1448 {
1449 if(rt1[i]) {
1450 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1451 alloc_reg64(current,i,rt1[i]);
1452 current->is32&=~(1LL<<rt1[i]);
1453 dirty_reg(current,rt1[i]);
1454 }
1455 }
1456 if(opcode2[i]==0x3e) // DSRL32
1457 {
1458 if(rt1[i]) {
1459 alloc_reg64(current,i,rs1[i]);
1460 if(imm[i]==32) {
1461 alloc_reg64(current,i,rt1[i]);
1462 current->is32&=~(1LL<<rt1[i]);
1463 } else {
1464 alloc_reg(current,i,rt1[i]);
1465 current->is32|=1LL<<rt1[i];
1466 }
1467 dirty_reg(current,rt1[i]);
1468 }
1469 }
1470 if(opcode2[i]==0x3f) // DSRA32
1471 {
1472 if(rt1[i]) {
1473 alloc_reg64(current,i,rs1[i]);
1474 alloc_reg(current,i,rt1[i]);
1475 current->is32|=1LL<<rt1[i];
1476 dirty_reg(current,rt1[i]);
1477 }
1478 }
1479}
1480
1481void shift_alloc(struct regstat *current,int i)
1482{
1483 if(rt1[i]) {
1484 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1485 {
1486 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1487 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1488 alloc_reg(current,i,rt1[i]);
e1190b87 1489 if(rt1[i]==rs2[i]) {
1490 alloc_reg_temp(current,i,-1);
1491 minimum_free_regs[i]=1;
1492 }
57871462 1493 current->is32|=1LL<<rt1[i];
1494 } else { // DSLLV/DSRLV/DSRAV
1495 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1496 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1497 alloc_reg64(current,i,rt1[i]);
1498 current->is32&=~(1LL<<rt1[i]);
1499 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
e1190b87 1500 {
57871462 1501 alloc_reg_temp(current,i,-1);
e1190b87 1502 minimum_free_regs[i]=1;
1503 }
57871462 1504 }
1505 clear_const(current,rs1[i]);
1506 clear_const(current,rs2[i]);
1507 clear_const(current,rt1[i]);
1508 dirty_reg(current,rt1[i]);
1509 }
1510}
1511
1512void alu_alloc(struct regstat *current,int i)
1513{
1514 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1515 if(rt1[i]) {
1516 if(rs1[i]&&rs2[i]) {
1517 alloc_reg(current,i,rs1[i]);
1518 alloc_reg(current,i,rs2[i]);
1519 }
1520 else {
1521 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1522 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1523 }
1524 alloc_reg(current,i,rt1[i]);
1525 }
1526 current->is32|=1LL<<rt1[i];
1527 }
1528 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1529 if(rt1[i]) {
1530 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1531 {
1532 alloc_reg64(current,i,rs1[i]);
1533 alloc_reg64(current,i,rs2[i]);
1534 alloc_reg(current,i,rt1[i]);
1535 } else {
1536 alloc_reg(current,i,rs1[i]);
1537 alloc_reg(current,i,rs2[i]);
1538 alloc_reg(current,i,rt1[i]);
1539 }
1540 }
1541 current->is32|=1LL<<rt1[i];
1542 }
1543 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1544 if(rt1[i]) {
1545 if(rs1[i]&&rs2[i]) {
1546 alloc_reg(current,i,rs1[i]);
1547 alloc_reg(current,i,rs2[i]);
1548 }
1549 else
1550 {
1551 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1552 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1553 }
1554 alloc_reg(current,i,rt1[i]);
1555 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1556 {
1557 if(!((current->uu>>rt1[i])&1)) {
1558 alloc_reg64(current,i,rt1[i]);
1559 }
1560 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1561 if(rs1[i]&&rs2[i]) {
1562 alloc_reg64(current,i,rs1[i]);
1563 alloc_reg64(current,i,rs2[i]);
1564 }
1565 else
1566 {
1567 // Is is really worth it to keep 64-bit values in registers?
1568 #ifdef NATIVE_64BIT
1569 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1570 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1571 #endif
1572 }
1573 }
1574 current->is32&=~(1LL<<rt1[i]);
1575 } else {
1576 current->is32|=1LL<<rt1[i];
1577 }
1578 }
1579 }
1580 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1581 if(rt1[i]) {
1582 if(rs1[i]&&rs2[i]) {
1583 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1584 alloc_reg64(current,i,rs1[i]);
1585 alloc_reg64(current,i,rs2[i]);
1586 alloc_reg64(current,i,rt1[i]);
1587 } else {
1588 alloc_reg(current,i,rs1[i]);
1589 alloc_reg(current,i,rs2[i]);
1590 alloc_reg(current,i,rt1[i]);
1591 }
1592 }
1593 else {
1594 alloc_reg(current,i,rt1[i]);
1595 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1596 // DADD used as move, or zeroing
1597 // If we have a 64-bit source, then make the target 64 bits too
1598 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1599 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1600 alloc_reg64(current,i,rt1[i]);
1601 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1602 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1603 alloc_reg64(current,i,rt1[i]);
1604 }
1605 if(opcode2[i]>=0x2e&&rs2[i]) {
1606 // DSUB used as negation - 64-bit result
1607 // If we have a 32-bit register, extend it to 64 bits
1608 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1609 alloc_reg64(current,i,rt1[i]);
1610 }
1611 }
1612 }
1613 if(rs1[i]&&rs2[i]) {
1614 current->is32&=~(1LL<<rt1[i]);
1615 } else if(rs1[i]) {
1616 current->is32&=~(1LL<<rt1[i]);
1617 if((current->is32>>rs1[i])&1)
1618 current->is32|=1LL<<rt1[i];
1619 } else if(rs2[i]) {
1620 current->is32&=~(1LL<<rt1[i]);
1621 if((current->is32>>rs2[i])&1)
1622 current->is32|=1LL<<rt1[i];
1623 } else {
1624 current->is32|=1LL<<rt1[i];
1625 }
1626 }
1627 }
1628 clear_const(current,rs1[i]);
1629 clear_const(current,rs2[i]);
1630 clear_const(current,rt1[i]);
1631 dirty_reg(current,rt1[i]);
1632}
1633
1634void imm16_alloc(struct regstat *current,int i)
1635{
1636 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1637 else lt1[i]=rs1[i];
1638 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1639 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1640 current->is32&=~(1LL<<rt1[i]);
1641 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1642 // TODO: Could preserve the 32-bit flag if the immediate is zero
1643 alloc_reg64(current,i,rt1[i]);
1644 alloc_reg64(current,i,rs1[i]);
1645 }
1646 clear_const(current,rs1[i]);
1647 clear_const(current,rt1[i]);
1648 }
1649 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1650 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1651 current->is32|=1LL<<rt1[i];
1652 clear_const(current,rs1[i]);
1653 clear_const(current,rt1[i]);
1654 }
1655 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1656 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1657 if(rs1[i]!=rt1[i]) {
1658 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1659 alloc_reg64(current,i,rt1[i]);
1660 current->is32&=~(1LL<<rt1[i]);
1661 }
1662 }
1663 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1664 if(is_const(current,rs1[i])) {
1665 int v=get_const(current,rs1[i]);
1666 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1667 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1668 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1669 }
1670 else clear_const(current,rt1[i]);
1671 }
1672 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1673 if(is_const(current,rs1[i])) {
1674 int v=get_const(current,rs1[i]);
1675 set_const(current,rt1[i],v+imm[i]);
1676 }
1677 else clear_const(current,rt1[i]);
1678 current->is32|=1LL<<rt1[i];
1679 }
1680 else {
1681 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1682 current->is32|=1LL<<rt1[i];
1683 }
1684 dirty_reg(current,rt1[i]);
1685}
1686
1687void load_alloc(struct regstat *current,int i)
1688{
1689 clear_const(current,rt1[i]);
1690 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1691 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1692 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
373d1d07 1693 if(rt1[i]&&!((current->u>>rt1[i])&1)) {
57871462 1694 alloc_reg(current,i,rt1[i]);
373d1d07 1695 assert(get_reg(current->regmap,rt1[i])>=0);
57871462 1696 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1697 {
1698 current->is32&=~(1LL<<rt1[i]);
1699 alloc_reg64(current,i,rt1[i]);
1700 }
1701 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1702 {
1703 current->is32&=~(1LL<<rt1[i]);
1704 alloc_reg64(current,i,rt1[i]);
1705 alloc_all(current,i);
1706 alloc_reg64(current,i,FTEMP);
e1190b87 1707 minimum_free_regs[i]=HOST_REGS;
57871462 1708 }
1709 else current->is32|=1LL<<rt1[i];
1710 dirty_reg(current,rt1[i]);
1711 // If using TLB, need a register for pointer to the mapping table
1712 if(using_tlb) alloc_reg(current,i,TLREG);
1713 // LWL/LWR need a temporary register for the old value
1714 if(opcode[i]==0x22||opcode[i]==0x26)
1715 {
1716 alloc_reg(current,i,FTEMP);
1717 alloc_reg_temp(current,i,-1);
e1190b87 1718 minimum_free_regs[i]=1;
57871462 1719 }
1720 }
1721 else
1722 {
373d1d07 1723 // Load to r0 or unneeded register (dummy load)
57871462 1724 // but we still need a register to calculate the address
535d208a 1725 if(opcode[i]==0x22||opcode[i]==0x26)
1726 {
1727 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1728 }
373d1d07 1729 // If using TLB, need a register for pointer to the mapping table
1730 if(using_tlb) alloc_reg(current,i,TLREG);
57871462 1731 alloc_reg_temp(current,i,-1);
e1190b87 1732 minimum_free_regs[i]=1;
535d208a 1733 if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1734 {
1735 alloc_all(current,i);
1736 alloc_reg64(current,i,FTEMP);
e1190b87 1737 minimum_free_regs[i]=HOST_REGS;
535d208a 1738 }
57871462 1739 }
1740}
1741
1742void store_alloc(struct regstat *current,int i)
1743{
1744 clear_const(current,rs2[i]);
1745 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1746 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1747 alloc_reg(current,i,rs2[i]);
1748 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1749 alloc_reg64(current,i,rs2[i]);
1750 if(rs2[i]) alloc_reg(current,i,FTEMP);
1751 }
1752 // If using TLB, need a register for pointer to the mapping table
1753 if(using_tlb) alloc_reg(current,i,TLREG);
1754 #if defined(HOST_IMM8)
1755 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1756 else alloc_reg(current,i,INVCP);
1757 #endif
b7918751 1758 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
57871462 1759 alloc_reg(current,i,FTEMP);
1760 }
1761 // We need a temporary register for address generation
1762 alloc_reg_temp(current,i,-1);
e1190b87 1763 minimum_free_regs[i]=1;
57871462 1764}
1765
1766void c1ls_alloc(struct regstat *current,int i)
1767{
1768 //clear_const(current,rs1[i]); // FIXME
1769 clear_const(current,rt1[i]);
1770 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1771 alloc_reg(current,i,CSREG); // Status
1772 alloc_reg(current,i,FTEMP);
1773 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1774 alloc_reg64(current,i,FTEMP);
1775 }
1776 // If using TLB, need a register for pointer to the mapping table
1777 if(using_tlb) alloc_reg(current,i,TLREG);
1778 #if defined(HOST_IMM8)
1779 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1780 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1781 alloc_reg(current,i,INVCP);
1782 #endif
1783 // We need a temporary register for address generation
1784 alloc_reg_temp(current,i,-1);
1785}
1786
b9b61529 1787void c2ls_alloc(struct regstat *current,int i)
1788{
1789 clear_const(current,rt1[i]);
1790 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1791 alloc_reg(current,i,FTEMP);
1792 // If using TLB, need a register for pointer to the mapping table
1793 if(using_tlb) alloc_reg(current,i,TLREG);
1794 #if defined(HOST_IMM8)
1795 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1796 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1797 alloc_reg(current,i,INVCP);
1798 #endif
1799 // We need a temporary register for address generation
1800 alloc_reg_temp(current,i,-1);
e1190b87 1801 minimum_free_regs[i]=1;
b9b61529 1802}
1803
57871462 1804#ifndef multdiv_alloc
1805void multdiv_alloc(struct regstat *current,int i)
1806{
1807 // case 0x18: MULT
1808 // case 0x19: MULTU
1809 // case 0x1A: DIV
1810 // case 0x1B: DIVU
1811 // case 0x1C: DMULT
1812 // case 0x1D: DMULTU
1813 // case 0x1E: DDIV
1814 // case 0x1F: DDIVU
1815 clear_const(current,rs1[i]);
1816 clear_const(current,rs2[i]);
1817 if(rs1[i]&&rs2[i])
1818 {
1819 if((opcode2[i]&4)==0) // 32-bit
1820 {
1821 current->u&=~(1LL<<HIREG);
1822 current->u&=~(1LL<<LOREG);
1823 alloc_reg(current,i,HIREG);
1824 alloc_reg(current,i,LOREG);
1825 alloc_reg(current,i,rs1[i]);
1826 alloc_reg(current,i,rs2[i]);
1827 current->is32|=1LL<<HIREG;
1828 current->is32|=1LL<<LOREG;
1829 dirty_reg(current,HIREG);
1830 dirty_reg(current,LOREG);
1831 }
1832 else // 64-bit
1833 {
1834 current->u&=~(1LL<<HIREG);
1835 current->u&=~(1LL<<LOREG);
1836 current->uu&=~(1LL<<HIREG);
1837 current->uu&=~(1LL<<LOREG);
1838 alloc_reg64(current,i,HIREG);
1839 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1840 alloc_reg64(current,i,rs1[i]);
1841 alloc_reg64(current,i,rs2[i]);
1842 alloc_all(current,i);
1843 current->is32&=~(1LL<<HIREG);
1844 current->is32&=~(1LL<<LOREG);
1845 dirty_reg(current,HIREG);
1846 dirty_reg(current,LOREG);
e1190b87 1847 minimum_free_regs[i]=HOST_REGS;
57871462 1848 }
1849 }
1850 else
1851 {
1852 // Multiply by zero is zero.
1853 // MIPS does not have a divide by zero exception.
1854 // The result is undefined, we return zero.
1855 alloc_reg(current,i,HIREG);
1856 alloc_reg(current,i,LOREG);
1857 current->is32|=1LL<<HIREG;
1858 current->is32|=1LL<<LOREG;
1859 dirty_reg(current,HIREG);
1860 dirty_reg(current,LOREG);
1861 }
1862}
1863#endif
1864
1865void cop0_alloc(struct regstat *current,int i)
1866{
1867 if(opcode2[i]==0) // MFC0
1868 {
1869 if(rt1[i]) {
1870 clear_const(current,rt1[i]);
1871 alloc_all(current,i);
1872 alloc_reg(current,i,rt1[i]);
1873 current->is32|=1LL<<rt1[i];
1874 dirty_reg(current,rt1[i]);
1875 }
1876 }
1877 else if(opcode2[i]==4) // MTC0
1878 {
1879 if(rs1[i]){
1880 clear_const(current,rs1[i]);
1881 alloc_reg(current,i,rs1[i]);
1882 alloc_all(current,i);
1883 }
1884 else {
1885 alloc_all(current,i); // FIXME: Keep r0
1886 current->u&=~1LL;
1887 alloc_reg(current,i,0);
1888 }
1889 }
1890 else
1891 {
1892 // TLBR/TLBWI/TLBWR/TLBP/ERET
1893 assert(opcode2[i]==0x10);
1894 alloc_all(current,i);
1895 }
e1190b87 1896 minimum_free_regs[i]=HOST_REGS;
57871462 1897}
1898
1899void cop1_alloc(struct regstat *current,int i)
1900{
1901 alloc_reg(current,i,CSREG); // Load status
1902 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1903 {
7de557a6 1904 if(rt1[i]){
1905 clear_const(current,rt1[i]);
1906 if(opcode2[i]==1) {
1907 alloc_reg64(current,i,rt1[i]); // DMFC1
1908 current->is32&=~(1LL<<rt1[i]);
1909 }else{
1910 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1911 current->is32|=1LL<<rt1[i];
1912 }
1913 dirty_reg(current,rt1[i]);
57871462 1914 }
57871462 1915 alloc_reg_temp(current,i,-1);
1916 }
1917 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1918 {
1919 if(rs1[i]){
1920 clear_const(current,rs1[i]);
1921 if(opcode2[i]==5)
1922 alloc_reg64(current,i,rs1[i]); // DMTC1
1923 else
1924 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1925 alloc_reg_temp(current,i,-1);
1926 }
1927 else {
1928 current->u&=~1LL;
1929 alloc_reg(current,i,0);
1930 alloc_reg_temp(current,i,-1);
1931 }
1932 }
e1190b87 1933 minimum_free_regs[i]=1;
57871462 1934}
1935void fconv_alloc(struct regstat *current,int i)
1936{
1937 alloc_reg(current,i,CSREG); // Load status
1938 alloc_reg_temp(current,i,-1);
e1190b87 1939 minimum_free_regs[i]=1;
57871462 1940}
1941void float_alloc(struct regstat *current,int i)
1942{
1943 alloc_reg(current,i,CSREG); // Load status
1944 alloc_reg_temp(current,i,-1);
e1190b87 1945 minimum_free_regs[i]=1;
57871462 1946}
b9b61529 1947void c2op_alloc(struct regstat *current,int i)
1948{
1949 alloc_reg_temp(current,i,-1);
1950}
57871462 1951void fcomp_alloc(struct regstat *current,int i)
1952{
1953 alloc_reg(current,i,CSREG); // Load status
1954 alloc_reg(current,i,FSREG); // Load flags
1955 dirty_reg(current,FSREG); // Flag will be modified
1956 alloc_reg_temp(current,i,-1);
e1190b87 1957 minimum_free_regs[i]=1;
57871462 1958}
1959
1960void syscall_alloc(struct regstat *current,int i)
1961{
1962 alloc_cc(current,i);
1963 dirty_reg(current,CCREG);
1964 alloc_all(current,i);
e1190b87 1965 minimum_free_regs[i]=HOST_REGS;
57871462 1966 current->isconst=0;
1967}
1968
1969void delayslot_alloc(struct regstat *current,int i)
1970{
1971 switch(itype[i]) {
1972 case UJUMP:
1973 case CJUMP:
1974 case SJUMP:
1975 case RJUMP:
1976 case FJUMP:
1977 case SYSCALL:
7139f3c8 1978 case HLECALL:
57871462 1979 case SPAN:
1980 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1981 printf("Disabled speculative precompilation\n");
1982 stop_after_jal=1;
1983 break;
1984 case IMM16:
1985 imm16_alloc(current,i);
1986 break;
1987 case LOAD:
1988 case LOADLR:
1989 load_alloc(current,i);
1990 break;
1991 case STORE:
1992 case STORELR:
1993 store_alloc(current,i);
1994 break;
1995 case ALU:
1996 alu_alloc(current,i);
1997 break;
1998 case SHIFT:
1999 shift_alloc(current,i);
2000 break;
2001 case MULTDIV:
2002 multdiv_alloc(current,i);
2003 break;
2004 case SHIFTIMM:
2005 shiftimm_alloc(current,i);
2006 break;
2007 case MOV:
2008 mov_alloc(current,i);
2009 break;
2010 case COP0:
2011 cop0_alloc(current,i);
2012 break;
2013 case COP1:
b9b61529 2014 case COP2:
57871462 2015 cop1_alloc(current,i);
2016 break;
2017 case C1LS:
2018 c1ls_alloc(current,i);
2019 break;
b9b61529 2020 case C2LS:
2021 c2ls_alloc(current,i);
2022 break;
57871462 2023 case FCONV:
2024 fconv_alloc(current,i);
2025 break;
2026 case FLOAT:
2027 float_alloc(current,i);
2028 break;
2029 case FCOMP:
2030 fcomp_alloc(current,i);
2031 break;
b9b61529 2032 case C2OP:
2033 c2op_alloc(current,i);
2034 break;
57871462 2035 }
2036}
2037
2038// Special case where a branch and delay slot span two pages in virtual memory
2039static void pagespan_alloc(struct regstat *current,int i)
2040{
2041 current->isconst=0;
2042 current->wasconst=0;
2043 regs[i].wasconst=0;
e1190b87 2044 minimum_free_regs[i]=HOST_REGS;
57871462 2045 alloc_all(current,i);
2046 alloc_cc(current,i);
2047 dirty_reg(current,CCREG);
2048 if(opcode[i]==3) // JAL
2049 {
2050 alloc_reg(current,i,31);
2051 dirty_reg(current,31);
2052 }
2053 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
2054 {
2055 alloc_reg(current,i,rs1[i]);
5067f341 2056 if (rt1[i]!=0) {
2057 alloc_reg(current,i,rt1[i]);
2058 dirty_reg(current,rt1[i]);
57871462 2059 }
2060 }
2061 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
2062 {
2063 if(rs1[i]) alloc_reg(current,i,rs1[i]);
2064 if(rs2[i]) alloc_reg(current,i,rs2[i]);
2065 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
2066 {
2067 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2068 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
2069 }
2070 }
2071 else
2072 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
2073 {
2074 if(rs1[i]) alloc_reg(current,i,rs1[i]);
2075 if(!((current->is32>>rs1[i])&1))
2076 {
2077 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2078 }
2079 }
2080 else
2081 if(opcode[i]==0x11) // BC1
2082 {
2083 alloc_reg(current,i,FSREG);
2084 alloc_reg(current,i,CSREG);
2085 }
2086 //else ...
2087}
2088
2089add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
2090{
2091 stubs[stubcount][0]=type;
2092 stubs[stubcount][1]=addr;
2093 stubs[stubcount][2]=retaddr;
2094 stubs[stubcount][3]=a;
2095 stubs[stubcount][4]=b;
2096 stubs[stubcount][5]=c;
2097 stubs[stubcount][6]=d;
2098 stubs[stubcount][7]=e;
2099 stubcount++;
2100}
2101
2102// Write out a single register
2103void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2104{
2105 int hr;
2106 for(hr=0;hr<HOST_REGS;hr++) {
2107 if(hr!=EXCLUDE_REG) {
2108 if((regmap[hr]&63)==r) {
2109 if((dirty>>hr)&1) {
2110 if(regmap[hr]<64) {
2111 emit_storereg(r,hr);
24385cae 2112#ifndef FORCE32
57871462 2113 if((is32>>regmap[hr])&1) {
2114 emit_sarimm(hr,31,hr);
2115 emit_storereg(r|64,hr);
2116 }
24385cae 2117#endif
57871462 2118 }else{
2119 emit_storereg(r|64,hr);
2120 }
2121 }
2122 }
2123 }
2124 }
2125}
2126
2127int mchecksum()
2128{
2129 //if(!tracedebug) return 0;
2130 int i;
2131 int sum=0;
2132 for(i=0;i<2097152;i++) {
2133 unsigned int temp=sum;
2134 sum<<=1;
2135 sum|=(~temp)>>31;
2136 sum^=((u_int *)rdram)[i];
2137 }
2138 return sum;
2139}
2140int rchecksum()
2141{
2142 int i;
2143 int sum=0;
2144 for(i=0;i<64;i++)
2145 sum^=((u_int *)reg)[i];
2146 return sum;
2147}
57871462 2148void rlist()
2149{
2150 int i;
2151 printf("TRACE: ");
2152 for(i=0;i<32;i++)
2153 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2154 printf("\n");
3d624f89 2155#ifndef DISABLE_COP1
57871462 2156 printf("TRACE: ");
2157 for(i=0;i<32;i++)
2158 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2159 printf("\n");
3d624f89 2160#endif
57871462 2161}
2162
2163void enabletrace()
2164{
2165 tracedebug=1;
2166}
2167
2168void memdebug(int i)
2169{
2170 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2171 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2172 //rlist();
2173 //if(tracedebug) {
2174 //if(Count>=-2084597794) {
2175 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2176 //if(0) {
2177 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2178 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2179 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2180 rlist();
2181 #ifdef __i386__
2182 printf("TRACE: %x\n",(&i)[-1]);
2183 #endif
2184 #ifdef __arm__
2185 int j;
2186 printf("TRACE: %x \n",(&j)[10]);
2187 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2188 #endif
2189 //fflush(stdout);
2190 }
2191 //printf("TRACE: %x\n",(&i)[-1]);
2192}
2193
2194void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2195{
2196 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2197}
2198
2199void alu_assemble(int i,struct regstat *i_regs)
2200{
2201 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2202 if(rt1[i]) {
2203 signed char s1,s2,t;
2204 t=get_reg(i_regs->regmap,rt1[i]);
2205 if(t>=0) {
2206 s1=get_reg(i_regs->regmap,rs1[i]);
2207 s2=get_reg(i_regs->regmap,rs2[i]);
2208 if(rs1[i]&&rs2[i]) {
2209 assert(s1>=0);
2210 assert(s2>=0);
2211 if(opcode2[i]&2) emit_sub(s1,s2,t);
2212 else emit_add(s1,s2,t);
2213 }
2214 else if(rs1[i]) {
2215 if(s1>=0) emit_mov(s1,t);
2216 else emit_loadreg(rs1[i],t);
2217 }
2218 else if(rs2[i]) {
2219 if(s2>=0) {
2220 if(opcode2[i]&2) emit_neg(s2,t);
2221 else emit_mov(s2,t);
2222 }
2223 else {
2224 emit_loadreg(rs2[i],t);
2225 if(opcode2[i]&2) emit_neg(t,t);
2226 }
2227 }
2228 else emit_zeroreg(t);
2229 }
2230 }
2231 }
2232 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2233 if(rt1[i]) {
2234 signed char s1l,s2l,s1h,s2h,tl,th;
2235 tl=get_reg(i_regs->regmap,rt1[i]);
2236 th=get_reg(i_regs->regmap,rt1[i]|64);
2237 if(tl>=0) {
2238 s1l=get_reg(i_regs->regmap,rs1[i]);
2239 s2l=get_reg(i_regs->regmap,rs2[i]);
2240 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2241 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2242 if(rs1[i]&&rs2[i]) {
2243 assert(s1l>=0);
2244 assert(s2l>=0);
2245 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2246 else emit_adds(s1l,s2l,tl);
2247 if(th>=0) {
2248 #ifdef INVERTED_CARRY
2249 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2250 #else
2251 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2252 #endif
2253 else emit_add(s1h,s2h,th);
2254 }
2255 }
2256 else if(rs1[i]) {
2257 if(s1l>=0) emit_mov(s1l,tl);
2258 else emit_loadreg(rs1[i],tl);
2259 if(th>=0) {
2260 if(s1h>=0) emit_mov(s1h,th);
2261 else emit_loadreg(rs1[i]|64,th);
2262 }
2263 }
2264 else if(rs2[i]) {
2265 if(s2l>=0) {
2266 if(opcode2[i]&2) emit_negs(s2l,tl);
2267 else emit_mov(s2l,tl);
2268 }
2269 else {
2270 emit_loadreg(rs2[i],tl);
2271 if(opcode2[i]&2) emit_negs(tl,tl);
2272 }
2273 if(th>=0) {
2274 #ifdef INVERTED_CARRY
2275 if(s2h>=0) emit_mov(s2h,th);
2276 else emit_loadreg(rs2[i]|64,th);
2277 if(opcode2[i]&2) {
2278 emit_adcimm(-1,th); // x86 has inverted carry flag
2279 emit_not(th,th);
2280 }
2281 #else
2282 if(opcode2[i]&2) {
2283 if(s2h>=0) emit_rscimm(s2h,0,th);
2284 else {
2285 emit_loadreg(rs2[i]|64,th);
2286 emit_rscimm(th,0,th);
2287 }
2288 }else{
2289 if(s2h>=0) emit_mov(s2h,th);
2290 else emit_loadreg(rs2[i]|64,th);
2291 }
2292 #endif
2293 }
2294 }
2295 else {
2296 emit_zeroreg(tl);
2297 if(th>=0) emit_zeroreg(th);
2298 }
2299 }
2300 }
2301 }
2302 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2303 if(rt1[i]) {
2304 signed char s1l,s1h,s2l,s2h,t;
2305 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2306 {
2307 t=get_reg(i_regs->regmap,rt1[i]);
2308 //assert(t>=0);
2309 if(t>=0) {
2310 s1l=get_reg(i_regs->regmap,rs1[i]);
2311 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2312 s2l=get_reg(i_regs->regmap,rs2[i]);
2313 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2314 if(rs2[i]==0) // rx<r0
2315 {
2316 assert(s1h>=0);
2317 if(opcode2[i]==0x2a) // SLT
2318 emit_shrimm(s1h,31,t);
2319 else // SLTU (unsigned can not be less than zero)
2320 emit_zeroreg(t);
2321 }
2322 else if(rs1[i]==0) // r0<rx
2323 {
2324 assert(s2h>=0);
2325 if(opcode2[i]==0x2a) // SLT
2326 emit_set_gz64_32(s2h,s2l,t);
2327 else // SLTU (set if not zero)
2328 emit_set_nz64_32(s2h,s2l,t);
2329 }
2330 else {
2331 assert(s1l>=0);assert(s1h>=0);
2332 assert(s2l>=0);assert(s2h>=0);
2333 if(opcode2[i]==0x2a) // SLT
2334 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2335 else // SLTU
2336 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2337 }
2338 }
2339 } else {
2340 t=get_reg(i_regs->regmap,rt1[i]);
2341 //assert(t>=0);
2342 if(t>=0) {
2343 s1l=get_reg(i_regs->regmap,rs1[i]);
2344 s2l=get_reg(i_regs->regmap,rs2[i]);
2345 if(rs2[i]==0) // rx<r0
2346 {
2347 assert(s1l>=0);
2348 if(opcode2[i]==0x2a) // SLT
2349 emit_shrimm(s1l,31,t);
2350 else // SLTU (unsigned can not be less than zero)
2351 emit_zeroreg(t);
2352 }
2353 else if(rs1[i]==0) // r0<rx
2354 {
2355 assert(s2l>=0);
2356 if(opcode2[i]==0x2a) // SLT
2357 emit_set_gz32(s2l,t);
2358 else // SLTU (set if not zero)
2359 emit_set_nz32(s2l,t);
2360 }
2361 else{
2362 assert(s1l>=0);assert(s2l>=0);
2363 if(opcode2[i]==0x2a) // SLT
2364 emit_set_if_less32(s1l,s2l,t);
2365 else // SLTU
2366 emit_set_if_carry32(s1l,s2l,t);
2367 }
2368 }
2369 }
2370 }
2371 }
2372 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2373 if(rt1[i]) {
2374 signed char s1l,s1h,s2l,s2h,th,tl;
2375 tl=get_reg(i_regs->regmap,rt1[i]);
2376 th=get_reg(i_regs->regmap,rt1[i]|64);
2377 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2378 {
2379 assert(tl>=0);
2380 if(tl>=0) {
2381 s1l=get_reg(i_regs->regmap,rs1[i]);
2382 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2383 s2l=get_reg(i_regs->regmap,rs2[i]);
2384 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2385 if(rs1[i]&&rs2[i]) {
2386 assert(s1l>=0);assert(s1h>=0);
2387 assert(s2l>=0);assert(s2h>=0);
2388 if(opcode2[i]==0x24) { // AND
2389 emit_and(s1l,s2l,tl);
2390 emit_and(s1h,s2h,th);
2391 } else
2392 if(opcode2[i]==0x25) { // OR
2393 emit_or(s1l,s2l,tl);
2394 emit_or(s1h,s2h,th);
2395 } else
2396 if(opcode2[i]==0x26) { // XOR
2397 emit_xor(s1l,s2l,tl);
2398 emit_xor(s1h,s2h,th);
2399 } else
2400 if(opcode2[i]==0x27) { // NOR
2401 emit_or(s1l,s2l,tl);
2402 emit_or(s1h,s2h,th);
2403 emit_not(tl,tl);
2404 emit_not(th,th);
2405 }
2406 }
2407 else
2408 {
2409 if(opcode2[i]==0x24) { // AND
2410 emit_zeroreg(tl);
2411 emit_zeroreg(th);
2412 } else
2413 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2414 if(rs1[i]){
2415 if(s1l>=0) emit_mov(s1l,tl);
2416 else emit_loadreg(rs1[i],tl);
2417 if(s1h>=0) emit_mov(s1h,th);
2418 else emit_loadreg(rs1[i]|64,th);
2419 }
2420 else
2421 if(rs2[i]){
2422 if(s2l>=0) emit_mov(s2l,tl);
2423 else emit_loadreg(rs2[i],tl);
2424 if(s2h>=0) emit_mov(s2h,th);
2425 else emit_loadreg(rs2[i]|64,th);
2426 }
2427 else{
2428 emit_zeroreg(tl);
2429 emit_zeroreg(th);
2430 }
2431 } else
2432 if(opcode2[i]==0x27) { // NOR
2433 if(rs1[i]){
2434 if(s1l>=0) emit_not(s1l,tl);
2435 else{
2436 emit_loadreg(rs1[i],tl);
2437 emit_not(tl,tl);
2438 }
2439 if(s1h>=0) emit_not(s1h,th);
2440 else{
2441 emit_loadreg(rs1[i]|64,th);
2442 emit_not(th,th);
2443 }
2444 }
2445 else
2446 if(rs2[i]){
2447 if(s2l>=0) emit_not(s2l,tl);
2448 else{
2449 emit_loadreg(rs2[i],tl);
2450 emit_not(tl,tl);
2451 }
2452 if(s2h>=0) emit_not(s2h,th);
2453 else{
2454 emit_loadreg(rs2[i]|64,th);
2455 emit_not(th,th);
2456 }
2457 }
2458 else {
2459 emit_movimm(-1,tl);
2460 emit_movimm(-1,th);
2461 }
2462 }
2463 }
2464 }
2465 }
2466 else
2467 {
2468 // 32 bit
2469 if(tl>=0) {
2470 s1l=get_reg(i_regs->regmap,rs1[i]);
2471 s2l=get_reg(i_regs->regmap,rs2[i]);
2472 if(rs1[i]&&rs2[i]) {
2473 assert(s1l>=0);
2474 assert(s2l>=0);
2475 if(opcode2[i]==0x24) { // AND
2476 emit_and(s1l,s2l,tl);
2477 } else
2478 if(opcode2[i]==0x25) { // OR
2479 emit_or(s1l,s2l,tl);
2480 } else
2481 if(opcode2[i]==0x26) { // XOR
2482 emit_xor(s1l,s2l,tl);
2483 } else
2484 if(opcode2[i]==0x27) { // NOR
2485 emit_or(s1l,s2l,tl);
2486 emit_not(tl,tl);
2487 }
2488 }
2489 else
2490 {
2491 if(opcode2[i]==0x24) { // AND
2492 emit_zeroreg(tl);
2493 } else
2494 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2495 if(rs1[i]){
2496 if(s1l>=0) emit_mov(s1l,tl);
2497 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2498 }
2499 else
2500 if(rs2[i]){
2501 if(s2l>=0) emit_mov(s2l,tl);
2502 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2503 }
2504 else emit_zeroreg(tl);
2505 } else
2506 if(opcode2[i]==0x27) { // NOR
2507 if(rs1[i]){
2508 if(s1l>=0) emit_not(s1l,tl);
2509 else {
2510 emit_loadreg(rs1[i],tl);
2511 emit_not(tl,tl);
2512 }
2513 }
2514 else
2515 if(rs2[i]){
2516 if(s2l>=0) emit_not(s2l,tl);
2517 else {
2518 emit_loadreg(rs2[i],tl);
2519 emit_not(tl,tl);
2520 }
2521 }
2522 else emit_movimm(-1,tl);
2523 }
2524 }
2525 }
2526 }
2527 }
2528 }
2529}
2530
2531void imm16_assemble(int i,struct regstat *i_regs)
2532{
2533 if (opcode[i]==0x0f) { // LUI
2534 if(rt1[i]) {
2535 signed char t;
2536 t=get_reg(i_regs->regmap,rt1[i]);
2537 //assert(t>=0);
2538 if(t>=0) {
2539 if(!((i_regs->isconst>>t)&1))
2540 emit_movimm(imm[i]<<16,t);
2541 }
2542 }
2543 }
2544 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2545 if(rt1[i]) {
2546 signed char s,t;
2547 t=get_reg(i_regs->regmap,rt1[i]);
2548 s=get_reg(i_regs->regmap,rs1[i]);
2549 if(rs1[i]) {
2550 //assert(t>=0);
2551 //assert(s>=0);
2552 if(t>=0) {
2553 if(!((i_regs->isconst>>t)&1)) {
2554 if(s<0) {
2555 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2556 emit_addimm(t,imm[i],t);
2557 }else{
2558 if(!((i_regs->wasconst>>s)&1))
2559 emit_addimm(s,imm[i],t);
2560 else
2561 emit_movimm(constmap[i][s]+imm[i],t);
2562 }
2563 }
2564 }
2565 } else {
2566 if(t>=0) {
2567 if(!((i_regs->isconst>>t)&1))
2568 emit_movimm(imm[i],t);
2569 }
2570 }
2571 }
2572 }
2573 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2574 if(rt1[i]) {
2575 signed char sh,sl,th,tl;
2576 th=get_reg(i_regs->regmap,rt1[i]|64);
2577 tl=get_reg(i_regs->regmap,rt1[i]);
2578 sh=get_reg(i_regs->regmap,rs1[i]|64);
2579 sl=get_reg(i_regs->regmap,rs1[i]);
2580 if(tl>=0) {
2581 if(rs1[i]) {
2582 assert(sh>=0);
2583 assert(sl>=0);
2584 if(th>=0) {
2585 emit_addimm64_32(sh,sl,imm[i],th,tl);
2586 }
2587 else {
2588 emit_addimm(sl,imm[i],tl);
2589 }
2590 } else {
2591 emit_movimm(imm[i],tl);
2592 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2593 }
2594 }
2595 }
2596 }
2597 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2598 if(rt1[i]) {
2599 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2600 signed char sh,sl,t;
2601 t=get_reg(i_regs->regmap,rt1[i]);
2602 sh=get_reg(i_regs->regmap,rs1[i]|64);
2603 sl=get_reg(i_regs->regmap,rs1[i]);
2604 //assert(t>=0);
2605 if(t>=0) {
2606 if(rs1[i]>0) {
2607 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2608 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2609 if(opcode[i]==0x0a) { // SLTI
2610 if(sl<0) {
2611 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2612 emit_slti32(t,imm[i],t);
2613 }else{
2614 emit_slti32(sl,imm[i],t);
2615 }
2616 }
2617 else { // SLTIU
2618 if(sl<0) {
2619 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2620 emit_sltiu32(t,imm[i],t);
2621 }else{
2622 emit_sltiu32(sl,imm[i],t);
2623 }
2624 }
2625 }else{ // 64-bit
2626 assert(sl>=0);
2627 if(opcode[i]==0x0a) // SLTI
2628 emit_slti64_32(sh,sl,imm[i],t);
2629 else // SLTIU
2630 emit_sltiu64_32(sh,sl,imm[i],t);
2631 }
2632 }else{
2633 // SLTI(U) with r0 is just stupid,
2634 // nonetheless examples can be found
2635 if(opcode[i]==0x0a) // SLTI
2636 if(0<imm[i]) emit_movimm(1,t);
2637 else emit_zeroreg(t);
2638 else // SLTIU
2639 {
2640 if(imm[i]) emit_movimm(1,t);
2641 else emit_zeroreg(t);
2642 }
2643 }
2644 }
2645 }
2646 }
2647 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2648 if(rt1[i]) {
2649 signed char sh,sl,th,tl;
2650 th=get_reg(i_regs->regmap,rt1[i]|64);
2651 tl=get_reg(i_regs->regmap,rt1[i]);
2652 sh=get_reg(i_regs->regmap,rs1[i]|64);
2653 sl=get_reg(i_regs->regmap,rs1[i]);
2654 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2655 if(opcode[i]==0x0c) //ANDI
2656 {
2657 if(rs1[i]) {
2658 if(sl<0) {
2659 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2660 emit_andimm(tl,imm[i],tl);
2661 }else{
2662 if(!((i_regs->wasconst>>sl)&1))
2663 emit_andimm(sl,imm[i],tl);
2664 else
2665 emit_movimm(constmap[i][sl]&imm[i],tl);
2666 }
2667 }
2668 else
2669 emit_zeroreg(tl);
2670 if(th>=0) emit_zeroreg(th);
2671 }
2672 else
2673 {
2674 if(rs1[i]) {
2675 if(sl<0) {
2676 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2677 }
2678 if(th>=0) {
2679 if(sh<0) {
2680 emit_loadreg(rs1[i]|64,th);
2681 }else{
2682 emit_mov(sh,th);
2683 }
2684 }
2685 if(opcode[i]==0x0d) //ORI
2686 if(sl<0) {
2687 emit_orimm(tl,imm[i],tl);
2688 }else{
2689 if(!((i_regs->wasconst>>sl)&1))
2690 emit_orimm(sl,imm[i],tl);
2691 else
2692 emit_movimm(constmap[i][sl]|imm[i],tl);
2693 }
2694 if(opcode[i]==0x0e) //XORI
2695 if(sl<0) {
2696 emit_xorimm(tl,imm[i],tl);
2697 }else{
2698 if(!((i_regs->wasconst>>sl)&1))
2699 emit_xorimm(sl,imm[i],tl);
2700 else
2701 emit_movimm(constmap[i][sl]^imm[i],tl);
2702 }
2703 }
2704 else {
2705 emit_movimm(imm[i],tl);
2706 if(th>=0) emit_zeroreg(th);
2707 }
2708 }
2709 }
2710 }
2711 }
2712}
2713
2714void shiftimm_assemble(int i,struct regstat *i_regs)
2715{
2716 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2717 {
2718 if(rt1[i]) {
2719 signed char s,t;
2720 t=get_reg(i_regs->regmap,rt1[i]);
2721 s=get_reg(i_regs->regmap,rs1[i]);
2722 //assert(t>=0);
dc49e339 2723 if(t>=0&&!((i_regs->isconst>>t)&1)){
57871462 2724 if(rs1[i]==0)
2725 {
2726 emit_zeroreg(t);
2727 }
2728 else
2729 {
2730 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2731 if(imm[i]) {
2732 if(opcode2[i]==0) // SLL
2733 {
2734 emit_shlimm(s<0?t:s,imm[i],t);
2735 }
2736 if(opcode2[i]==2) // SRL
2737 {
2738 emit_shrimm(s<0?t:s,imm[i],t);
2739 }
2740 if(opcode2[i]==3) // SRA
2741 {
2742 emit_sarimm(s<0?t:s,imm[i],t);
2743 }
2744 }else{
2745 // Shift by zero
2746 if(s>=0 && s!=t) emit_mov(s,t);
2747 }
2748 }
2749 }
2750 //emit_storereg(rt1[i],t); //DEBUG
2751 }
2752 }
2753 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2754 {
2755 if(rt1[i]) {
2756 signed char sh,sl,th,tl;
2757 th=get_reg(i_regs->regmap,rt1[i]|64);
2758 tl=get_reg(i_regs->regmap,rt1[i]);
2759 sh=get_reg(i_regs->regmap,rs1[i]|64);
2760 sl=get_reg(i_regs->regmap,rs1[i]);
2761 if(tl>=0) {
2762 if(rs1[i]==0)
2763 {
2764 emit_zeroreg(tl);
2765 if(th>=0) emit_zeroreg(th);
2766 }
2767 else
2768 {
2769 assert(sl>=0);
2770 assert(sh>=0);
2771 if(imm[i]) {
2772 if(opcode2[i]==0x38) // DSLL
2773 {
2774 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2775 emit_shlimm(sl,imm[i],tl);
2776 }
2777 if(opcode2[i]==0x3a) // DSRL
2778 {
2779 emit_shrdimm(sl,sh,imm[i],tl);
2780 if(th>=0) emit_shrimm(sh,imm[i],th);
2781 }
2782 if(opcode2[i]==0x3b) // DSRA
2783 {
2784 emit_shrdimm(sl,sh,imm[i],tl);
2785 if(th>=0) emit_sarimm(sh,imm[i],th);
2786 }
2787 }else{
2788 // Shift by zero
2789 if(sl!=tl) emit_mov(sl,tl);
2790 if(th>=0&&sh!=th) emit_mov(sh,th);
2791 }
2792 }
2793 }
2794 }
2795 }
2796 if(opcode2[i]==0x3c) // DSLL32
2797 {
2798 if(rt1[i]) {
2799 signed char sl,tl,th;
2800 tl=get_reg(i_regs->regmap,rt1[i]);
2801 th=get_reg(i_regs->regmap,rt1[i]|64);
2802 sl=get_reg(i_regs->regmap,rs1[i]);
2803 if(th>=0||tl>=0){
2804 assert(tl>=0);
2805 assert(th>=0);
2806 assert(sl>=0);
2807 emit_mov(sl,th);
2808 emit_zeroreg(tl);
2809 if(imm[i]>32)
2810 {
2811 emit_shlimm(th,imm[i]&31,th);
2812 }
2813 }
2814 }
2815 }
2816 if(opcode2[i]==0x3e) // DSRL32
2817 {
2818 if(rt1[i]) {
2819 signed char sh,tl,th;
2820 tl=get_reg(i_regs->regmap,rt1[i]);
2821 th=get_reg(i_regs->regmap,rt1[i]|64);
2822 sh=get_reg(i_regs->regmap,rs1[i]|64);
2823 if(tl>=0){
2824 assert(sh>=0);
2825 emit_mov(sh,tl);
2826 if(th>=0) emit_zeroreg(th);
2827 if(imm[i]>32)
2828 {
2829 emit_shrimm(tl,imm[i]&31,tl);
2830 }
2831 }
2832 }
2833 }
2834 if(opcode2[i]==0x3f) // DSRA32
2835 {
2836 if(rt1[i]) {
2837 signed char sh,tl;
2838 tl=get_reg(i_regs->regmap,rt1[i]);
2839 sh=get_reg(i_regs->regmap,rs1[i]|64);
2840 if(tl>=0){
2841 assert(sh>=0);
2842 emit_mov(sh,tl);
2843 if(imm[i]>32)
2844 {
2845 emit_sarimm(tl,imm[i]&31,tl);
2846 }
2847 }
2848 }
2849 }
2850}
2851
2852#ifndef shift_assemble
2853void shift_assemble(int i,struct regstat *i_regs)
2854{
2855 printf("Need shift_assemble for this architecture.\n");
2856 exit(1);
2857}
2858#endif
2859
2860void load_assemble(int i,struct regstat *i_regs)
2861{
2862 int s,th,tl,addr,map=-1;
2863 int offset;
2864 int jaddr=0;
5bf843dc 2865 int memtarget=0,c=0;
b1570849 2866 int fastload_reg_override=0;
57871462 2867 u_int hr,reglist=0;
2868 th=get_reg(i_regs->regmap,rt1[i]|64);
2869 tl=get_reg(i_regs->regmap,rt1[i]);
2870 s=get_reg(i_regs->regmap,rs1[i]);
2871 offset=imm[i];
2872 for(hr=0;hr<HOST_REGS;hr++) {
2873 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2874 }
2875 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2876 if(s>=0) {
2877 c=(i_regs->wasconst>>s)&1;
af4ee1fe 2878 if (c) {
2879 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2880 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2881 }
57871462 2882 }
57871462 2883 //printf("load_assemble: c=%d\n",c);
2884 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2885 // FIXME: Even if the load is a NOP, we should check for pagefaults...
5bf843dc 2886#ifdef PCSX
f18c0f46 2887 if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2888 ||rt1[i]==0) {
5bf843dc 2889 // could be FIFO, must perform the read
f18c0f46 2890 // ||dummy read
5bf843dc 2891 assem_debug("(forced read)\n");
2892 tl=get_reg(i_regs->regmap,-1);
2893 assert(tl>=0);
5bf843dc 2894 }
f18c0f46 2895#endif
5bf843dc 2896 if(offset||s<0||c) addr=tl;
2897 else addr=s;
535d208a 2898 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2899 if(tl>=0) {
2900 //printf("load_assemble: c=%d\n",c);
2901 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2902 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2903 reglist&=~(1<<tl);
2904 if(th>=0) reglist&=~(1<<th);
2905 if(!using_tlb) {
2906 if(!c) {
2907 #ifdef RAM_OFFSET
2908 map=get_reg(i_regs->regmap,ROREG);
2909 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2910 #endif
57871462 2911//#define R29_HACK 1
535d208a 2912 #ifdef R29_HACK
2913 // Strmnnrmn's speed hack
2914 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2915 #endif
2916 {
ffb0b9e0 2917 jaddr=emit_fastpath_cmp_jump(i,addr,&fastload_reg_override);
57871462 2918 }
535d208a 2919 }
2920 }else{ // using tlb
2921 int x=0;
2922 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2923 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2924 map=get_reg(i_regs->regmap,TLREG);
2925 assert(map>=0);
ea3d2e6e 2926 reglist&=~(1<<map);
535d208a 2927 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2928 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2929 }
2930 int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2931 if (opcode[i]==0x20) { // LB
2932 if(!c||memtarget) {
2933 if(!dummy) {
57871462 2934 #ifdef HOST_IMM_ADDR32
2935 if(c)
2936 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2937 else
2938 #endif
2939 {
2940 //emit_xorimm(addr,3,tl);
2941 //gen_tlb_addr_r(tl,map);
2942 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
535d208a 2943 int x=0,a=tl;
2002a1db 2944#ifdef BIG_ENDIAN_MIPS
57871462 2945 if(!c) emit_xorimm(addr,3,tl);
2946 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2947#else
535d208a 2948 if(!c) a=addr;
dadf55f2 2949#endif
b1570849 2950 if(fastload_reg_override) a=fastload_reg_override;
2951
535d208a 2952 emit_movsbl_indexed_tlb(x,a,map,tl);
57871462 2953 }
57871462 2954 }
535d208a 2955 if(jaddr)
2956 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2957 }
535d208a 2958 else
2959 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2960 }
2961 if (opcode[i]==0x21) { // LH
2962 if(!c||memtarget) {
2963 if(!dummy) {
57871462 2964 #ifdef HOST_IMM_ADDR32
2965 if(c)
2966 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2967 else
2968 #endif
2969 {
535d208a 2970 int x=0,a=tl;
2002a1db 2971#ifdef BIG_ENDIAN_MIPS
57871462 2972 if(!c) emit_xorimm(addr,2,tl);
2973 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2974#else
535d208a 2975 if(!c) a=addr;
dadf55f2 2976#endif
b1570849 2977 if(fastload_reg_override) a=fastload_reg_override;
57871462 2978 //#ifdef
2979 //emit_movswl_indexed_tlb(x,tl,map,tl);
2980 //else
2981 if(map>=0) {
535d208a 2982 gen_tlb_addr_r(a,map);
2983 emit_movswl_indexed(x,a,tl);
2984 }else{
2985 #ifdef RAM_OFFSET
2986 emit_movswl_indexed(x,a,tl);
2987 #else
2988 emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2989 #endif
2990 }
57871462 2991 }
57871462 2992 }
535d208a 2993 if(jaddr)
2994 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2995 }
535d208a 2996 else
2997 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2998 }
2999 if (opcode[i]==0x23) { // LW
3000 if(!c||memtarget) {
3001 if(!dummy) {
dadf55f2 3002 int a=addr;
b1570849 3003 if(fastload_reg_override) a=fastload_reg_override;
57871462 3004 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3005 #ifdef HOST_IMM_ADDR32
3006 if(c)
3007 emit_readword_tlb(constmap[i][s]+offset,map,tl);
3008 else
3009 #endif
dadf55f2 3010 emit_readword_indexed_tlb(0,a,map,tl);
57871462 3011 }
535d208a 3012 if(jaddr)
3013 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 3014 }
535d208a 3015 else
3016 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3017 }
3018 if (opcode[i]==0x24) { // LBU
3019 if(!c||memtarget) {
3020 if(!dummy) {
57871462 3021 #ifdef HOST_IMM_ADDR32
3022 if(c)
3023 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
3024 else
3025 #endif
3026 {
3027 //emit_xorimm(addr,3,tl);
3028 //gen_tlb_addr_r(tl,map);
3029 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
535d208a 3030 int x=0,a=tl;
2002a1db 3031#ifdef BIG_ENDIAN_MIPS
57871462 3032 if(!c) emit_xorimm(addr,3,tl);
3033 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 3034#else
535d208a 3035 if(!c) a=addr;
dadf55f2 3036#endif
b1570849 3037 if(fastload_reg_override) a=fastload_reg_override;
3038
535d208a 3039 emit_movzbl_indexed_tlb(x,a,map,tl);
57871462 3040 }
57871462 3041 }
535d208a 3042 if(jaddr)
3043 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 3044 }
535d208a 3045 else
3046 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3047 }
3048 if (opcode[i]==0x25) { // LHU
3049 if(!c||memtarget) {
3050 if(!dummy) {
57871462 3051 #ifdef HOST_IMM_ADDR32
3052 if(c)
3053 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
3054 else
3055 #endif
3056 {
535d208a 3057 int x=0,a=tl;
2002a1db 3058#ifdef BIG_ENDIAN_MIPS
57871462 3059 if(!c) emit_xorimm(addr,2,tl);
3060 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 3061#else
535d208a 3062 if(!c) a=addr;
dadf55f2 3063#endif
b1570849 3064 if(fastload_reg_override) a=fastload_reg_override;
57871462 3065 //#ifdef
3066 //emit_movzwl_indexed_tlb(x,tl,map,tl);
3067 //#else
3068 if(map>=0) {
535d208a 3069 gen_tlb_addr_r(a,map);
3070 emit_movzwl_indexed(x,a,tl);
3071 }else{
3072 #ifdef RAM_OFFSET
3073 emit_movzwl_indexed(x,a,tl);
3074 #else
3075 emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
3076 #endif
3077 }
57871462 3078 }
3079 }
535d208a 3080 if(jaddr)
3081 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 3082 }
535d208a 3083 else
3084 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3085 }
3086 if (opcode[i]==0x27) { // LWU
3087 assert(th>=0);
3088 if(!c||memtarget) {
3089 if(!dummy) {
dadf55f2 3090 int a=addr;
b1570849 3091 if(fastload_reg_override) a=fastload_reg_override;
57871462 3092 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3093 #ifdef HOST_IMM_ADDR32
3094 if(c)
3095 emit_readword_tlb(constmap[i][s]+offset,map,tl);
3096 else
3097 #endif
dadf55f2 3098 emit_readword_indexed_tlb(0,a,map,tl);
57871462 3099 }
535d208a 3100 if(jaddr)
3101 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3102 }
3103 else {
3104 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
57871462 3105 }
535d208a 3106 emit_zeroreg(th);
3107 }
3108 if (opcode[i]==0x37) { // LD
3109 if(!c||memtarget) {
3110 if(!dummy) {
dadf55f2 3111 int a=addr;
b1570849 3112 if(fastload_reg_override) a=fastload_reg_override;
57871462 3113 //gen_tlb_addr_r(tl,map);
3114 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3115 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3116 #ifdef HOST_IMM_ADDR32
3117 if(c)
3118 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3119 else
3120 #endif
dadf55f2 3121 emit_readdword_indexed_tlb(0,a,map,th,tl);
57871462 3122 }
535d208a 3123 if(jaddr)
3124 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 3125 }
535d208a 3126 else
3127 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
57871462 3128 }
535d208a 3129 }
3130 //emit_storereg(rt1[i],tl); // DEBUG
57871462 3131 //if(opcode[i]==0x23)
3132 //if(opcode[i]==0x24)
3133 //if(opcode[i]==0x23||opcode[i]==0x24)
3134 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3135 {
3136 //emit_pusha();
3137 save_regs(0x100f);
3138 emit_readword((int)&last_count,ECX);
3139 #ifdef __i386__
3140 if(get_reg(i_regs->regmap,CCREG)<0)
3141 emit_loadreg(CCREG,HOST_CCREG);
3142 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3143 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3144 emit_writeword(HOST_CCREG,(int)&Count);
3145 #endif
3146 #ifdef __arm__
3147 if(get_reg(i_regs->regmap,CCREG)<0)
3148 emit_loadreg(CCREG,0);
3149 else
3150 emit_mov(HOST_CCREG,0);
3151 emit_add(0,ECX,0);
3152 emit_addimm(0,2*ccadj[i],0);
3153 emit_writeword(0,(int)&Count);
3154 #endif
3155 emit_call((int)memdebug);
3156 //emit_popa();
3157 restore_regs(0x100f);
3158 }/**/
3159}
3160
3161#ifndef loadlr_assemble
3162void loadlr_assemble(int i,struct regstat *i_regs)
3163{
3164 printf("Need loadlr_assemble for this architecture.\n");
3165 exit(1);
3166}
3167#endif
3168
3169void store_assemble(int i,struct regstat *i_regs)
3170{
3171 int s,th,tl,map=-1;
3172 int addr,temp;
3173 int offset;
3174 int jaddr=0,jaddr2,type;
666a299d 3175 int memtarget=0,c=0;
57871462 3176 int agr=AGEN1+(i&1);
b1570849 3177 int faststore_reg_override=0;
57871462 3178 u_int hr,reglist=0;
3179 th=get_reg(i_regs->regmap,rs2[i]|64);
3180 tl=get_reg(i_regs->regmap,rs2[i]);
3181 s=get_reg(i_regs->regmap,rs1[i]);
3182 temp=get_reg(i_regs->regmap,agr);
3183 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3184 offset=imm[i];
3185 if(s>=0) {
3186 c=(i_regs->wasconst>>s)&1;
af4ee1fe 3187 if(c) {
3188 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3189 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3190 }
57871462 3191 }
3192 assert(tl>=0);
3193 assert(temp>=0);
3194 for(hr=0;hr<HOST_REGS;hr++) {
3195 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3196 }
3197 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3198 if(offset||s<0||c) addr=temp;
3199 else addr=s;
3200 if(!using_tlb) {
3201 if(!c) {
ffb0b9e0 3202 #ifndef PCSX
57871462 3203 #ifdef R29_HACK
3204 // Strmnnrmn's speed hack
4cb76aa4 3205 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
57871462 3206 #endif
4cb76aa4 3207 emit_cmpimm(addr,RAM_SIZE);
57871462 3208 #ifdef DESTRUCTIVE_SHIFT
3209 if(s==addr) emit_mov(s,temp);
3210 #endif
3211 #ifdef R29_HACK
dadf55f2 3212 memtarget=1;
4cb76aa4 3213 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
57871462 3214 #endif
3215 {
3216 jaddr=(int)out;
3217 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3218 // Hint to branch predictor that the branch is unlikely to be taken
3219 if(rs1[i]>=28)
3220 emit_jno_unlikely(0);
3221 else
3222 #endif
3223 emit_jno(0);
3224 }
ffb0b9e0 3225 #else
3226 jaddr=emit_fastpath_cmp_jump(i,addr,&faststore_reg_override);
3227 #endif
57871462 3228 }
3229 }else{ // using tlb
3230 int x=0;
3231 if (opcode[i]==0x28) x=3; // SB
3232 if (opcode[i]==0x29) x=2; // SH
3233 map=get_reg(i_regs->regmap,TLREG);
3234 assert(map>=0);
ea3d2e6e 3235 reglist&=~(1<<map);
57871462 3236 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3237 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3238 }
3239
3240 if (opcode[i]==0x28) { // SB
3241 if(!c||memtarget) {
97a238a6 3242 int x=0,a=temp;
2002a1db 3243#ifdef BIG_ENDIAN_MIPS
57871462 3244 if(!c) emit_xorimm(addr,3,temp);
3245 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 3246#else
97a238a6 3247 if(!c) a=addr;
dadf55f2 3248#endif
b1570849 3249 if(faststore_reg_override) a=faststore_reg_override;
57871462 3250 //gen_tlb_addr_w(temp,map);
3251 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
97a238a6 3252 emit_writebyte_indexed_tlb(tl,x,a,map,a);
57871462 3253 }
3254 type=STOREB_STUB;
3255 }
3256 if (opcode[i]==0x29) { // SH
3257 if(!c||memtarget) {
97a238a6 3258 int x=0,a=temp;
2002a1db 3259#ifdef BIG_ENDIAN_MIPS
57871462 3260 if(!c) emit_xorimm(addr,2,temp);
3261 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 3262#else
97a238a6 3263 if(!c) a=addr;
dadf55f2 3264#endif
b1570849 3265 if(faststore_reg_override) a=faststore_reg_override;
57871462 3266 //#ifdef
3267 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3268 //#else
3269 if(map>=0) {
97a238a6 3270 gen_tlb_addr_w(a,map);
3271 emit_writehword_indexed(tl,x,a);
57871462 3272 }else
97a238a6 3273 emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
57871462 3274 }
3275 type=STOREH_STUB;
3276 }
3277 if (opcode[i]==0x2B) { // SW
dadf55f2 3278 if(!c||memtarget) {
3279 int a=addr;
b1570849 3280 if(faststore_reg_override) a=faststore_reg_override;
57871462 3281 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
dadf55f2 3282 emit_writeword_indexed_tlb(tl,0,a,map,temp);
3283 }
57871462 3284 type=STOREW_STUB;
3285 }
3286 if (opcode[i]==0x3F) { // SD
3287 if(!c||memtarget) {
dadf55f2 3288 int a=addr;
b1570849 3289 if(faststore_reg_override) a=faststore_reg_override;
57871462 3290 if(rs2[i]) {
3291 assert(th>=0);
3292 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3293 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
dadf55f2 3294 emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
57871462 3295 }else{
3296 // Store zero
3297 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3298 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
dadf55f2 3299 emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
57871462 3300 }
3301 }
3302 type=STORED_STUB;
3303 }
b96d3df7 3304#ifdef PCSX
3305 if(jaddr) {
3306 // PCSX store handlers don't check invcode again
3307 reglist|=1<<addr;
3308 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3309 jaddr=0;
3310 }
3311#endif
0ff8c62c 3312 if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
57871462 3313 if(!c||memtarget) {
3314 #ifdef DESTRUCTIVE_SHIFT
3315 // The x86 shift operation is 'destructive'; it overwrites the
3316 // source register, so we need to make a copy first and use that.
3317 addr=temp;
3318 #endif
3319 #if defined(HOST_IMM8)
3320 int ir=get_reg(i_regs->regmap,INVCP);
3321 assert(ir>=0);
3322 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3323 #else
3324 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3325 #endif
0bbd1454 3326 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3327 emit_callne(invalidate_addr_reg[addr]);
3328 #else
57871462 3329 jaddr2=(int)out;
3330 emit_jne(0);
3331 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
0bbd1454 3332 #endif
57871462 3333 }
3334 }
7a518516 3335 u_int addr_val=constmap[i][s]+offset;
3eaa7048 3336 if(jaddr) {
3337 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3338 } else if(c&&!memtarget) {
7a518516 3339 inline_writestub(type,i,addr_val,i_regs->regmap,rs2[i],ccadj[i],reglist);
3340 }
3341 // basic current block modification detection..
3342 // not looking back as that should be in mips cache already
3343 if(c&&start+i*4<addr_val&&addr_val<start+slen*4) {
3344 printf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4);
3345 assert(i_regs->regmap==regs[i].regmap); // not delay slot
3346 if(i_regs->regmap==regs[i].regmap) {
3347 load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
3348 wb_dirtys(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty);
3349 emit_movimm(start+i*4+4,0);
3350 emit_writeword(0,(int)&pcaddr);
3351 emit_jmp((int)do_interrupt);
3352 }
3eaa7048 3353 }
57871462 3354 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3355 //if(opcode[i]==0x2B || opcode[i]==0x28)
3356 //if(opcode[i]==0x2B || opcode[i]==0x29)
3357 //if(opcode[i]==0x2B)
3358 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3359 {
28d74ee8 3360 #ifdef __i386__
3361 emit_pusha();
3362 #endif
3363 #ifdef __arm__
57871462 3364 save_regs(0x100f);
28d74ee8 3365 #endif
57871462 3366 emit_readword((int)&last_count,ECX);
3367 #ifdef __i386__
3368 if(get_reg(i_regs->regmap,CCREG)<0)
3369 emit_loadreg(CCREG,HOST_CCREG);
3370 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3371 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3372 emit_writeword(HOST_CCREG,(int)&Count);
3373 #endif
3374 #ifdef __arm__
3375 if(get_reg(i_regs->regmap,CCREG)<0)
3376 emit_loadreg(CCREG,0);
3377 else
3378 emit_mov(HOST_CCREG,0);
3379 emit_add(0,ECX,0);
3380 emit_addimm(0,2*ccadj[i],0);
3381 emit_writeword(0,(int)&Count);
3382 #endif
3383 emit_call((int)memdebug);
28d74ee8 3384 #ifdef __i386__
3385 emit_popa();
3386 #endif
3387 #ifdef __arm__
57871462 3388 restore_regs(0x100f);
28d74ee8 3389 #endif
57871462 3390 }/**/
3391}
3392
3393void storelr_assemble(int i,struct regstat *i_regs)
3394{
3395 int s,th,tl;
3396 int temp;
3397 int temp2;
3398 int offset;
3399 int jaddr=0,jaddr2;
3400 int case1,case2,case3;
3401 int done0,done1,done2;
af4ee1fe 3402 int memtarget=0,c=0;
fab5d06d 3403 int agr=AGEN1+(i&1);
57871462 3404 u_int hr,reglist=0;
3405 th=get_reg(i_regs->regmap,rs2[i]|64);
3406 tl=get_reg(i_regs->regmap,rs2[i]);
3407 s=get_reg(i_regs->regmap,rs1[i]);
fab5d06d 3408 temp=get_reg(i_regs->regmap,agr);
3409 if(temp<0) temp=get_reg(i_regs->regmap,-1);
57871462 3410 offset=imm[i];
3411 if(s>=0) {
3412 c=(i_regs->isconst>>s)&1;
af4ee1fe 3413 if(c) {
3414 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3415 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3416 }
57871462 3417 }
3418 assert(tl>=0);
3419 for(hr=0;hr<HOST_REGS;hr++) {
3420 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3421 }
535d208a 3422 assert(temp>=0);
3423 if(!using_tlb) {
3424 if(!c) {
3425 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3426 if(!offset&&s!=temp) emit_mov(s,temp);
3427 jaddr=(int)out;
3428 emit_jno(0);
3429 }
3430 else
3431 {
3432 if(!memtarget||!rs1[i]) {
57871462 3433 jaddr=(int)out;
3434 emit_jmp(0);
3435 }
57871462 3436 }
535d208a 3437 #ifdef RAM_OFFSET
3438 int map=get_reg(i_regs->regmap,ROREG);
3439 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3440 gen_tlb_addr_w(temp,map);
3441 #else
3442 if((u_int)rdram!=0x80000000)
3443 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3444 #endif
3445 }else{ // using tlb
3446 int map=get_reg(i_regs->regmap,TLREG);
3447 assert(map>=0);
ea3d2e6e 3448 reglist&=~(1<<map);
535d208a 3449 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3450 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3451 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3452 if(!jaddr&&!memtarget) {
3453 jaddr=(int)out;
3454 emit_jmp(0);
57871462 3455 }
535d208a 3456 gen_tlb_addr_w(temp,map);
3457 }
3458
3459 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3460 temp2=get_reg(i_regs->regmap,FTEMP);
3461 if(!rs2[i]) temp2=th=tl;
3462 }
57871462 3463
2002a1db 3464#ifndef BIG_ENDIAN_MIPS
3465 emit_xorimm(temp,3,temp);
3466#endif
535d208a 3467 emit_testimm(temp,2);
3468 case2=(int)out;
3469 emit_jne(0);
3470 emit_testimm(temp,1);
3471 case1=(int)out;
3472 emit_jne(0);
3473 // 0
3474 if (opcode[i]==0x2A) { // SWL
3475 emit_writeword_indexed(tl,0,temp);
3476 }
3477 if (opcode[i]==0x2E) { // SWR
3478 emit_writebyte_indexed(tl,3,temp);
3479 }
3480 if (opcode[i]==0x2C) { // SDL
3481 emit_writeword_indexed(th,0,temp);
3482 if(rs2[i]) emit_mov(tl,temp2);
3483 }
3484 if (opcode[i]==0x2D) { // SDR
3485 emit_writebyte_indexed(tl,3,temp);
3486 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3487 }
3488 done0=(int)out;
3489 emit_jmp(0);
3490 // 1
3491 set_jump_target(case1,(int)out);
3492 if (opcode[i]==0x2A) { // SWL
3493 // Write 3 msb into three least significant bytes
3494 if(rs2[i]) emit_rorimm(tl,8,tl);
3495 emit_writehword_indexed(tl,-1,temp);
3496 if(rs2[i]) emit_rorimm(tl,16,tl);
3497 emit_writebyte_indexed(tl,1,temp);
3498 if(rs2[i]) emit_rorimm(tl,8,tl);
3499 }
3500 if (opcode[i]==0x2E) { // SWR
3501 // Write two lsb into two most significant bytes
3502 emit_writehword_indexed(tl,1,temp);
3503 }
3504 if (opcode[i]==0x2C) { // SDL
3505 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3506 // Write 3 msb into three least significant bytes
3507 if(rs2[i]) emit_rorimm(th,8,th);
3508 emit_writehword_indexed(th,-1,temp);
3509 if(rs2[i]) emit_rorimm(th,16,th);
3510 emit_writebyte_indexed(th,1,temp);
3511 if(rs2[i]) emit_rorimm(th,8,th);
3512 }
3513 if (opcode[i]==0x2D) { // SDR
3514 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3515 // Write two lsb into two most significant bytes
3516 emit_writehword_indexed(tl,1,temp);
3517 }
3518 done1=(int)out;
3519 emit_jmp(0);
3520 // 2
3521 set_jump_target(case2,(int)out);
3522 emit_testimm(temp,1);
3523 case3=(int)out;
3524 emit_jne(0);
3525 if (opcode[i]==0x2A) { // SWL
3526 // Write two msb into two least significant bytes
3527 if(rs2[i]) emit_rorimm(tl,16,tl);
3528 emit_writehword_indexed(tl,-2,temp);
3529 if(rs2[i]) emit_rorimm(tl,16,tl);
3530 }
3531 if (opcode[i]==0x2E) { // SWR
3532 // Write 3 lsb into three most significant bytes
3533 emit_writebyte_indexed(tl,-1,temp);
3534 if(rs2[i]) emit_rorimm(tl,8,tl);
3535 emit_writehword_indexed(tl,0,temp);
3536 if(rs2[i]) emit_rorimm(tl,24,tl);
3537 }
3538 if (opcode[i]==0x2C) { // SDL
3539 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3540 // Write two msb into two least significant bytes
3541 if(rs2[i]) emit_rorimm(th,16,th);
3542 emit_writehword_indexed(th,-2,temp);
3543 if(rs2[i]) emit_rorimm(th,16,th);
3544 }
3545 if (opcode[i]==0x2D) { // SDR
3546 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3547 // Write 3 lsb into three most significant bytes
3548 emit_writebyte_indexed(tl,-1,temp);
3549 if(rs2[i]) emit_rorimm(tl,8,tl);
3550 emit_writehword_indexed(tl,0,temp);
3551 if(rs2[i]) emit_rorimm(tl,24,tl);
3552 }
3553 done2=(int)out;
3554 emit_jmp(0);
3555 // 3
3556 set_jump_target(case3,(int)out);
3557 if (opcode[i]==0x2A) { // SWL
3558 // Write msb into least significant byte
3559 if(rs2[i]) emit_rorimm(tl,24,tl);
3560 emit_writebyte_indexed(tl,-3,temp);
3561 if(rs2[i]) emit_rorimm(tl,8,tl);
3562 }
3563 if (opcode[i]==0x2E) { // SWR
3564 // Write entire word
3565 emit_writeword_indexed(tl,-3,temp);
3566 }
3567 if (opcode[i]==0x2C) { // SDL
3568 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3569 // Write msb into least significant byte
3570 if(rs2[i]) emit_rorimm(th,24,th);
3571 emit_writebyte_indexed(th,-3,temp);
3572 if(rs2[i]) emit_rorimm(th,8,th);
3573 }
3574 if (opcode[i]==0x2D) { // SDR
3575 if(rs2[i]) emit_mov(th,temp2);
3576 // Write entire word
3577 emit_writeword_indexed(tl,-3,temp);
3578 }
3579 set_jump_target(done0,(int)out);
3580 set_jump_target(done1,(int)out);
3581 set_jump_target(done2,(int)out);
3582 if (opcode[i]==0x2C) { // SDL
3583 emit_testimm(temp,4);
57871462 3584 done0=(int)out;
57871462 3585 emit_jne(0);
535d208a 3586 emit_andimm(temp,~3,temp);
3587 emit_writeword_indexed(temp2,4,temp);
3588 set_jump_target(done0,(int)out);
3589 }
3590 if (opcode[i]==0x2D) { // SDR
3591 emit_testimm(temp,4);
3592 done0=(int)out;
3593 emit_jeq(0);
3594 emit_andimm(temp,~3,temp);
3595 emit_writeword_indexed(temp2,-4,temp);
57871462 3596 set_jump_target(done0,(int)out);
57871462 3597 }
535d208a 3598 if(!c||!memtarget)
3599 add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
0ff8c62c 3600 if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
535d208a 3601 #ifdef RAM_OFFSET
3602 int map=get_reg(i_regs->regmap,ROREG);
3603 if(map<0) map=HOST_TEMPREG;
3604 gen_orig_addr_w(temp,map);
3605 #else
57871462 3606 emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
535d208a 3607 #endif
57871462 3608 #if defined(HOST_IMM8)
3609 int ir=get_reg(i_regs->regmap,INVCP);
3610 assert(ir>=0);
3611 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3612 #else
3613 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3614 #endif
535d208a 3615 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3616 emit_callne(invalidate_addr_reg[temp]);
3617 #else
57871462 3618 jaddr2=(int)out;
3619 emit_jne(0);
3620 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
535d208a 3621 #endif
57871462 3622 }
3623 /*
3624 emit_pusha();
3625 //save_regs(0x100f);
3626 emit_readword((int)&last_count,ECX);
3627 if(get_reg(i_regs->regmap,CCREG)<0)
3628 emit_loadreg(CCREG,HOST_CCREG);
3629 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3630 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3631 emit_writeword(HOST_CCREG,(int)&Count);
3632 emit_call((int)memdebug);
3633 emit_popa();
3634 //restore_regs(0x100f);
3635 /**/
3636}
3637
3638void c1ls_assemble(int i,struct regstat *i_regs)
3639{
3d624f89 3640#ifndef DISABLE_COP1
57871462 3641 int s,th,tl;
3642 int temp,ar;
3643 int map=-1;
3644 int offset;
3645 int c=0;
3646 int jaddr,jaddr2=0,jaddr3,type;
3647 int agr=AGEN1+(i&1);
3648 u_int hr,reglist=0;
3649 th=get_reg(i_regs->regmap,FTEMP|64);
3650 tl=get_reg(i_regs->regmap,FTEMP);
3651 s=get_reg(i_regs->regmap,rs1[i]);
3652 temp=get_reg(i_regs->regmap,agr);
3653 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3654 offset=imm[i];
3655 assert(tl>=0);
3656 assert(rs1[i]>0);
3657 assert(temp>=0);
3658 for(hr=0;hr<HOST_REGS;hr++) {
3659 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3660 }
3661 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3662 if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3663 {
3664 // Loads use a temporary register which we need to save
3665 reglist|=1<<temp;
3666 }
3667 if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3668 ar=temp;
3669 else // LWC1/LDC1
3670 ar=tl;
3671 //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3672 //else c=(i_regs->wasconst>>s)&1;
3673 if(s>=0) c=(i_regs->wasconst>>s)&1;
3674 // Check cop1 unusable
3675 if(!cop1_usable) {
3676 signed char rs=get_reg(i_regs->regmap,CSREG);
3677 assert(rs>=0);
3678 emit_testimm(rs,0x20000000);
3679 jaddr=(int)out;
3680 emit_jeq(0);
3681 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3682 cop1_usable=1;
3683 }
3684 if (opcode[i]==0x39) { // SWC1 (get float address)
3685 emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],tl);
3686 }
3687 if (opcode[i]==0x3D) { // SDC1 (get double address)
3688 emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],tl);
3689 }
3690 // Generate address + offset
3691 if(!using_tlb) {
3692 if(!c)
4cb76aa4 3693 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
57871462 3694 }
3695 else
3696 {
3697 map=get_reg(i_regs->regmap,TLREG);
3698 assert(map>=0);
ea3d2e6e 3699 reglist&=~(1<<map);
57871462 3700 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3701 map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3702 }
3703 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3704 map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3705 }
3706 }
3707 if (opcode[i]==0x39) { // SWC1 (read float)
3708 emit_readword_indexed(0,tl,tl);
3709 }
3710 if (opcode[i]==0x3D) { // SDC1 (read double)
3711 emit_readword_indexed(4,tl,th);
3712 emit_readword_indexed(0,tl,tl);
3713 }
3714 if (opcode[i]==0x31) { // LWC1 (get target address)
3715 emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],temp);
3716 }
3717 if (opcode[i]==0x35) { // LDC1 (get target address)
3718 emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],temp);
3719 }
3720 if(!using_tlb) {
3721 if(!c) {
3722 jaddr2=(int)out;
3723 emit_jno(0);
3724 }
4cb76aa4 3725 else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
57871462 3726 jaddr2=(int)out;
3727 emit_jmp(0); // inline_readstub/inline_writestub? Very rare case
3728 }
3729 #ifdef DESTRUCTIVE_SHIFT
3730 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3731 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3732 }
3733 #endif
3734 }else{
3735 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3736 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3737 }
3738 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3739 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3740 }
3741 }
3742 if (opcode[i]==0x31) { // LWC1
3743 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3744 //gen_tlb_addr_r(ar,map);
3745 //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3746 #ifdef HOST_IMM_ADDR32
3747 if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3748 else
3749 #endif
3750 emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3751 type=LOADW_STUB;
3752 }
3753 if (opcode[i]==0x35) { // LDC1
3754 assert(th>=0);
3755 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3756 //gen_tlb_addr_r(ar,map);
3757 //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3758 //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3759 #ifdef HOST_IMM_ADDR32
3760 if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3761 else
3762 #endif
3763 emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3764 type=LOADD_STUB;
3765 }
3766 if (opcode[i]==0x39) { // SWC1
3767 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3768 emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3769 type=STOREW_STUB;
3770 }
3771 if (opcode[i]==0x3D) { // SDC1
3772 assert(th>=0);
3773 //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3774 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3775 emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3776 type=STORED_STUB;
3777 }
0ff8c62c 3778 if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
57871462 3779 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3780 #ifndef DESTRUCTIVE_SHIFT
3781 temp=offset||c||s<0?ar:s;
3782 #endif
3783 #if defined(HOST_IMM8)
3784 int ir=get_reg(i_regs->regmap,INVCP);
3785 assert(ir>=0);
3786 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3787 #else
3788 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3789 #endif
0bbd1454 3790 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3791 emit_callne(invalidate_addr_reg[temp]);
3792 #else
57871462 3793 jaddr3=(int)out;
3794 emit_jne(0);
3795 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
0bbd1454 3796 #endif
57871462 3797 }
3798 }
3799 if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3800 if (opcode[i]==0x31) { // LWC1 (write float)
3801 emit_writeword_indexed(tl,0,temp);
3802 }
3803 if (opcode[i]==0x35) { // LDC1 (write double)
3804 emit_writeword_indexed(th,4,temp);
3805 emit_writeword_indexed(tl,0,temp);
3806 }
3807 //if(opcode[i]==0x39)
3808 /*if(opcode[i]==0x39||opcode[i]==0x31)
3809 {
3810 emit_pusha();
3811 emit_readword((int)&last_count,ECX);
3812 if(get_reg(i_regs->regmap,CCREG)<0)
3813 emit_loadreg(CCREG,HOST_CCREG);
3814 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3815 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3816 emit_writeword(HOST_CCREG,(int)&Count);
3817 emit_call((int)memdebug);
3818 emit_popa();
3819 }/**/
3d624f89 3820#else
3821 cop1_unusable(i, i_regs);
3822#endif
57871462 3823}
3824
b9b61529 3825void c2ls_assemble(int i,struct regstat *i_regs)
3826{
3827 int s,tl;
3828 int ar;
3829 int offset;
1fd1aceb 3830 int memtarget=0,c=0;
c2e3bd42 3831 int jaddr2=0,jaddr3,type;
b9b61529 3832 int agr=AGEN1+(i&1);
ffb0b9e0 3833 int fastio_reg_override=0;
b9b61529 3834 u_int hr,reglist=0;
3835 u_int copr=(source[i]>>16)&0x1f;
3836 s=get_reg(i_regs->regmap,rs1[i]);
3837 tl=get_reg(i_regs->regmap,FTEMP);
3838 offset=imm[i];
3839 assert(rs1[i]>0);
3840 assert(tl>=0);
3841 assert(!using_tlb);
3842
3843 for(hr=0;hr<HOST_REGS;hr++) {
3844 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3845 }
3846 if(i_regs->regmap[HOST_CCREG]==CCREG)
3847 reglist&=~(1<<HOST_CCREG);
3848
3849 // get the address
3850 if (opcode[i]==0x3a) { // SWC2
3851 ar=get_reg(i_regs->regmap,agr);
3852 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3853 reglist|=1<<ar;
3854 } else { // LWC2
3855 ar=tl;
3856 }
1fd1aceb 3857 if(s>=0) c=(i_regs->wasconst>>s)&1;
3858 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
b9b61529 3859 if (!offset&&!c&&s>=0) ar=s;
3860 assert(ar>=0);
3861
3862 if (opcode[i]==0x3a) { // SWC2
3863 cop2_get_dreg(copr,tl,HOST_TEMPREG);
1fd1aceb 3864 type=STOREW_STUB;
b9b61529 3865 }
1fd1aceb 3866 else
b9b61529 3867 type=LOADW_STUB;
1fd1aceb 3868
3869 if(c&&!memtarget) {
3870 jaddr2=(int)out;
3871 emit_jmp(0); // inline_readstub/inline_writestub?
b9b61529 3872 }
1fd1aceb 3873 else {
3874 if(!c) {
ffb0b9e0 3875 jaddr2=emit_fastpath_cmp_jump(i,ar,&fastio_reg_override);
1fd1aceb 3876 }
3877 if (opcode[i]==0x32) { // LWC2
3878 #ifdef HOST_IMM_ADDR32
3879 if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3880 else
3881 #endif
ffb0b9e0 3882 int a=ar;
3883 if(fastio_reg_override) a=fastio_reg_override;
3884 emit_readword_indexed(0,a,tl);
1fd1aceb 3885 }
3886 if (opcode[i]==0x3a) { // SWC2
3887 #ifdef DESTRUCTIVE_SHIFT
3888 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3889 #endif
ffb0b9e0 3890 int a=ar;
3891 if(fastio_reg_override) a=fastio_reg_override;
3892 emit_writeword_indexed(tl,0,a);
1fd1aceb 3893 }
b9b61529 3894 }
3895 if(jaddr2)
3896 add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
0ff8c62c 3897 if(opcode[i]==0x3a) // SWC2
3898 if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
b9b61529 3899#if defined(HOST_IMM8)
3900 int ir=get_reg(i_regs->regmap,INVCP);
3901 assert(ir>=0);
3902 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3903#else
3904 emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3905#endif
0bbd1454 3906 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3907 emit_callne(invalidate_addr_reg[ar]);
3908 #else
b9b61529 3909 jaddr3=(int)out;
3910 emit_jne(0);
3911 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
0bbd1454 3912 #endif
b9b61529 3913 }
3914 if (opcode[i]==0x32) { // LWC2
3915 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3916 }
3917}
3918
57871462 3919#ifndef multdiv_assemble
3920void multdiv_assemble(int i,struct regstat *i_regs)
3921{
3922 printf("Need multdiv_assemble for this architecture.\n");
3923 exit(1);
3924}
3925#endif
3926
3927void mov_assemble(int i,struct regstat *i_regs)
3928{
3929 //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3930 //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
57871462 3931 if(rt1[i]) {
3932 signed char sh,sl,th,tl;
3933 th=get_reg(i_regs->regmap,rt1[i]|64);
3934 tl=get_reg(i_regs->regmap,rt1[i]);
3935 //assert(tl>=0);
3936 if(tl>=0) {
3937 sh=get_reg(i_regs->regmap,rs1[i]|64);
3938 sl=get_reg(i_regs->regmap,rs1[i]);
3939 if(sl>=0) emit_mov(sl,tl);
3940 else emit_loadreg(rs1[i],tl);
3941 if(th>=0) {
3942 if(sh>=0) emit_mov(sh,th);
3943 else emit_loadreg(rs1[i]|64,th);
3944 }
3945 }
3946 }
3947}
3948
3949#ifndef fconv_assemble
3950void fconv_assemble(int i,struct regstat *i_regs)
3951{
3952 printf("Need fconv_assemble for this architecture.\n");
3953 exit(1);
3954}
3955#endif
3956
3957#if 0
3958void float_assemble(int i,struct regstat *i_regs)
3959{
3960 printf("Need float_assemble for this architecture.\n");
3961 exit(1);
3962}
3963#endif
3964
3965void syscall_assemble(int i,struct regstat *i_regs)
3966{
3967 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3968 assert(ccreg==HOST_CCREG);
3969 assert(!is_delayslot);
3970 emit_movimm(start+i*4,EAX); // Get PC
2573466a 3971 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
7139f3c8 3972 emit_jmp((int)jump_syscall_hle); // XXX
3973}
3974
3975void hlecall_assemble(int i,struct regstat *i_regs)
3976{
3977 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3978 assert(ccreg==HOST_CCREG);
3979 assert(!is_delayslot);
3980 emit_movimm(start+i*4+4,0); // Get PC
67ba0fb4 3981 emit_movimm((int)psxHLEt[source[i]&7],1);
2573466a 3982 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // XXX
67ba0fb4 3983 emit_jmp((int)jump_hlecall);
57871462 3984}
3985
1e973cb0 3986void intcall_assemble(int i,struct regstat *i_regs)
3987{
3988 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3989 assert(ccreg==HOST_CCREG);
3990 assert(!is_delayslot);
3991 emit_movimm(start+i*4,0); // Get PC
2573466a 3992 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
1e973cb0 3993 emit_jmp((int)jump_intcall);
3994}
3995
57871462 3996void ds_assemble(int i,struct regstat *i_regs)
3997{
ffb0b9e0 3998 speculate_register_values(i);
57871462 3999 is_delayslot=1;
4000 switch(itype[i]) {
4001 case ALU:
4002 alu_assemble(i,i_regs);break;
4003 case IMM16:
4004 imm16_assemble(i,i_regs);break;
4005 case SHIFT:
4006 shift_assemble(i,i_regs);break;
4007 case SHIFTIMM:
4008 shiftimm_assemble(i,i_regs);break;
4009 case LOAD:
4010 load_assemble(i,i_regs);break;
4011 case LOADLR:
4012 loadlr_assemble(i,i_regs);break;
4013 case STORE:
4014 store_assemble(i,i_regs);break;
4015 case STORELR:
4016 storelr_assemble(i,i_regs);break;
4017 case COP0:
4018 cop0_assemble(i,i_regs);break;
4019 case COP1:
4020 cop1_assemble(i,i_regs);break;
4021 case C1LS:
4022 c1ls_assemble(i,i_regs);break;
b9b61529 4023 case COP2:
4024 cop2_assemble(i,i_regs);break;
4025 case C2LS:
4026 c2ls_assemble(i,i_regs);break;
4027 case C2OP:
4028 c2op_assemble(i,i_regs);break;
57871462 4029 case FCONV:
4030 fconv_assemble(i,i_regs);break;
4031 case FLOAT:
4032 float_assemble(i,i_regs);break;
4033 case FCOMP:
4034 fcomp_assemble(i,i_regs);break;
4035 case MULTDIV:
4036 multdiv_assemble(i,i_regs);break;
4037 case MOV:
4038 mov_assemble(i,i_regs);break;
4039 case SYSCALL:
7139f3c8 4040 case HLECALL:
1e973cb0 4041 case INTCALL:
57871462 4042 case SPAN:
4043 case UJUMP:
4044 case RJUMP:
4045 case CJUMP:
4046 case SJUMP:
4047 case FJUMP:
4048 printf("Jump in the delay slot. This is probably a bug.\n");
4049 }
4050 is_delayslot=0;
4051}
4052
4053// Is the branch target a valid internal jump?
4054int internal_branch(uint64_t i_is32,int addr)
4055{
4056 if(addr&1) return 0; // Indirect (register) jump
4057 if(addr>=start && addr<start+slen*4-4)
4058 {
4059 int t=(addr-start)>>2;
4060 // Delay slots are not valid branch targets
4061 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4062 // 64 -> 32 bit transition requires a recompile
4063 /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
4064 {
4065 if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
4066 else printf("optimizable: yes\n");
4067 }*/
4068 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
a28c6ce8 4069#ifndef FORCE32
57871462 4070 if(requires_32bit[t]&~i_is32) return 0;
a28c6ce8 4071 else
4072#endif
4073 return 1;
57871462 4074 }
4075 return 0;
4076}
4077
4078#ifndef wb_invalidate
4079void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
4080 uint64_t u,uint64_t uu)
4081{
4082 int hr;
4083 for(hr=0;hr<HOST_REGS;hr++) {
4084 if(hr!=EXCLUDE_REG) {
4085 if(pre[hr]!=entry[hr]) {
4086 if(pre[hr]>=0) {
4087 if((dirty>>hr)&1) {
4088 if(get_reg(entry,pre[hr])<0) {
4089 if(pre[hr]<64) {
4090 if(!((u>>pre[hr])&1)) {
4091 emit_storereg(pre[hr],hr);
4092 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
4093 emit_sarimm(hr,31,hr);
4094 emit_storereg(pre[hr]|64,hr);
4095 }
4096 }
4097 }else{
4098 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
4099 emit_storereg(pre[hr],hr);
4100 }
4101 }
4102 }
4103 }
4104 }
4105 }
4106 }
4107 }
4108 // Move from one register to another (no writeback)
4109 for(hr=0;hr<HOST_REGS;hr++) {
4110 if(hr!=EXCLUDE_REG) {
4111 if(pre[hr]!=entry[hr]) {
4112 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
4113 int nr;
4114 if((nr=get_reg(entry,pre[hr]))>=0) {
4115 emit_mov(hr,nr);
4116 }
4117 }
4118 }
4119 }
4120 }
4121}
4122#endif
4123
4124// Load the specified registers
4125// This only loads the registers given as arguments because
4126// we don't want to load things that will be overwritten
4127void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
4128{
4129 int hr;
4130 // Load 32-bit regs
4131 for(hr=0;hr<HOST_REGS;hr++) {
4132 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4133 if(entry[hr]!=regmap[hr]) {
4134 if(regmap[hr]==rs1||regmap[hr]==rs2)
4135 {
4136 if(regmap[hr]==0) {
4137 emit_zeroreg(hr);
4138 }
4139 else
4140 {
4141 emit_loadreg(regmap[hr],hr);
4142 }
4143 }
4144 }
4145 }
4146 }
4147 //Load 64-bit regs
4148 for(hr=0;hr<HOST_REGS;hr++) {
4149 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4150 if(entry[hr]!=regmap[hr]) {
4151 if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
4152 {
4153 assert(regmap[hr]!=64);
4154 if((is32>>(regmap[hr]&63))&1) {
4155 int lr=get_reg(regmap,regmap[hr]-64);
4156 if(lr>=0)
4157 emit_sarimm(lr,31,hr);
4158 else
4159 emit_loadreg(regmap[hr],hr);
4160 }
4161 else
4162 {
4163 emit_loadreg(regmap[hr],hr);
4164 }
4165 }
4166 }
4167 }
4168 }
4169}
4170
4171// Load registers prior to the start of a loop
4172// so that they are not loaded within the loop
4173static void loop_preload(signed char pre[],signed char entry[])
4174{
4175 int hr;
4176 for(hr=0;hr<HOST_REGS;hr++) {
4177 if(hr!=EXCLUDE_REG) {
4178 if(pre[hr]!=entry[hr]) {
4179 if(entry[hr]>=0) {
4180 if(get_reg(pre,entry[hr])<0) {
4181 assem_debug("loop preload:\n");
4182 //printf("loop preload: %d\n",hr);
4183 if(entry[hr]==0) {
4184 emit_zeroreg(hr);
4185 }
4186 else if(entry[hr]<TEMPREG)
4187 {
4188 emit_loadreg(entry[hr],hr);
4189 }
4190 else if(entry[hr]-64<TEMPREG)
4191 {
4192 emit_loadreg(entry[hr],hr);
4193 }
4194 }
4195 }
4196 }
4197 }
4198 }
4199}
4200
4201// Generate address for load/store instruction
b9b61529 4202// goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
57871462 4203void address_generation(int i,struct regstat *i_regs,signed char entry[])
4204{
b9b61529 4205 if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
5194fb95 4206 int ra=-1;
57871462 4207 int agr=AGEN1+(i&1);
4208 int mgr=MGEN1+(i&1);
4209 if(itype[i]==LOAD) {
4210 ra=get_reg(i_regs->regmap,rt1[i]);
535d208a 4211 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4212 assert(ra>=0);
57871462 4213 }
4214 if(itype[i]==LOADLR) {
4215 ra=get_reg(i_regs->regmap,FTEMP);
4216 }
4217 if(itype[i]==STORE||itype[i]==STORELR) {
4218 ra=get_reg(i_regs->regmap,agr);
4219 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4220 }
b9b61529 4221 if(itype[i]==C1LS||itype[i]==C2LS) {
4222 if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
57871462 4223 ra=get_reg(i_regs->regmap,FTEMP);
1fd1aceb 4224 else { // SWC1/SDC1/SWC2/SDC2
57871462 4225 ra=get_reg(i_regs->regmap,agr);
4226 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4227 }
4228 }
4229 int rs=get_reg(i_regs->regmap,rs1[i]);
4230 int rm=get_reg(i_regs->regmap,TLREG);
4231 if(ra>=0) {
4232 int offset=imm[i];
4233 int c=(i_regs->wasconst>>rs)&1;
4234 if(rs1[i]==0) {
4235 // Using r0 as a base address
4236 /*if(rm>=0) {
4237 if(!entry||entry[rm]!=mgr) {
4238 generate_map_const(offset,rm);
4239 } // else did it in the previous cycle
4240 }*/
4241 if(!entry||entry[ra]!=agr) {
4242 if (opcode[i]==0x22||opcode[i]==0x26) {
4243 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4244 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4245 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4246 }else{
4247 emit_movimm(offset,ra);
4248 }
4249 } // else did it in the previous cycle
4250 }
4251 else if(rs<0) {
4252 if(!entry||entry[ra]!=rs1[i])
4253 emit_loadreg(rs1[i],ra);
4254 //if(!entry||entry[ra]!=rs1[i])
4255 // printf("poor load scheduling!\n");
4256 }
4257 else if(c) {
63cb0298 4258#ifndef DISABLE_TLB
57871462 4259 if(rm>=0) {
4260 if(!entry||entry[rm]!=mgr) {
b9b61529 4261 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
57871462 4262 // Stores to memory go thru the mapper to detect self-modifying
4263 // code, loads don't.
4264 if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
4cb76aa4 4265 (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
57871462 4266 generate_map_const(constmap[i][rs]+offset,rm);
4267 }else{
4268 if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
4269 generate_map_const(constmap[i][rs]+offset,rm);
4270 }
4271 }
4272 }
63cb0298 4273#endif
57871462 4274 if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
4275 if(!entry||entry[ra]!=agr) {
4276 if (opcode[i]==0x22||opcode[i]==0x26) {
4277 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4278 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4279 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4280 }else{
4281 #ifdef HOST_IMM_ADDR32
b9b61529 4282 if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
57871462 4283 (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4284 #endif
4285 emit_movimm(constmap[i][rs]+offset,ra);
8575a877 4286 regs[i].loadedconst|=1<<ra;
57871462 4287 }
4288 } // else did it in the previous cycle
4289 } // else load_consts already did it
4290 }
4291 if(offset&&!c&&rs1[i]) {
4292 if(rs>=0) {
4293 emit_addimm(rs,offset,ra);
4294 }else{
4295 emit_addimm(ra,offset,ra);
4296 }
4297 }
4298 }
4299 }
4300 // Preload constants for next instruction
b9b61529 4301 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
57871462 4302 int agr,ra;
63cb0298 4303 #if !defined(HOST_IMM_ADDR32) && !defined(DISABLE_TLB)
57871462 4304 // Mapper entry
4305 agr=MGEN1+((i+1)&1);
4306 ra=get_reg(i_regs->regmap,agr);
4307 if(ra>=0) {
4308 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4309 int offset=imm[i+1];
4310 int c=(regs[i+1].wasconst>>rs)&1;
4311 if(c) {
b9b61529 4312 if(itype[i+1]==STORE||itype[i+1]==STORELR
4313 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
57871462 4314 // Stores to memory go thru the mapper to detect self-modifying
4315 // code, loads don't.
4316 if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4cb76aa4 4317 (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
57871462 4318 generate_map_const(constmap[i+1][rs]+offset,ra);
4319 }else{
4320 if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4321 generate_map_const(constmap[i+1][rs]+offset,ra);
4322 }
4323 }
4324 /*else if(rs1[i]==0) {
4325 generate_map_const(offset,ra);
4326 }*/
4327 }
4328 #endif
4329 // Actual address
4330 agr=AGEN1+((i+1)&1);
4331 ra=get_reg(i_regs->regmap,agr);
4332 if(ra>=0) {
4333 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4334 int offset=imm[i+1];
4335 int c=(regs[i+1].wasconst>>rs)&1;
4336 if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4337 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4338 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4339 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4340 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4341 }else{
4342 #ifdef HOST_IMM_ADDR32
b9b61529 4343 if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
57871462 4344 (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4345 #endif
4346 emit_movimm(constmap[i+1][rs]+offset,ra);
8575a877 4347 regs[i+1].loadedconst|=1<<ra;
57871462 4348 }
4349 }
4350 else if(rs1[i+1]==0) {
4351 // Using r0 as a base address
4352 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4353 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4354 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4355 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4356 }else{
4357 emit_movimm(offset,ra);
4358 }
4359 }
4360 }
4361 }
4362}
4363
4364int get_final_value(int hr, int i, int *value)
4365{
4366 int reg=regs[i].regmap[hr];
4367 while(i<slen-1) {
4368 if(regs[i+1].regmap[hr]!=reg) break;
4369 if(!((regs[i+1].isconst>>hr)&1)) break;
4370 if(bt[i+1]) break;
4371 i++;
4372 }
4373 if(i<slen-1) {
4374 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4375 *value=constmap[i][hr];
4376 return 1;
4377 }
4378 if(!bt[i+1]) {
4379 if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4380 // Load in delay slot, out-of-order execution
4381 if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4382 {
4383 #ifdef HOST_IMM_ADDR32
4384 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4385 #endif
4386 // Precompute load address
4387 *value=constmap[i][hr]+imm[i+2];
4388 return 1;
4389 }
4390 }
4391 if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4392 {
4393 #ifdef HOST_IMM_ADDR32
4394 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4395 #endif
4396 // Precompute load address
4397 *value=constmap[i][hr]+imm[i+1];
4398 //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4399 return 1;
4400 }
4401 }
4402 }
4403 *value=constmap[i][hr];
4404 //printf("c=%x\n",(int)constmap[i][hr]);
4405 if(i==slen-1) return 1;
4406 if(reg<64) {
4407 return !((unneeded_reg[i+1]>>reg)&1);
4408 }else{
4409 return !((unneeded_reg_upper[i+1]>>reg)&1);
4410 }
4411}
4412
4413// Load registers with known constants
4414void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4415{
8575a877 4416 int hr,hr2;
4417 // propagate loaded constant flags
4418 if(i==0||bt[i])
4419 regs[i].loadedconst=0;
4420 else {
4421 for(hr=0;hr<HOST_REGS;hr++) {
4422 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((regs[i-1].isconst>>hr)&1)&&pre[hr]==regmap[hr]
4423 &&regmap[hr]==regs[i-1].regmap[hr]&&((regs[i-1].loadedconst>>hr)&1))
4424 {
4425 regs[i].loadedconst|=1<<hr;
4426 }
4427 }
4428 }
57871462 4429 // Load 32-bit regs
4430 for(hr=0;hr<HOST_REGS;hr++) {
4431 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4432 //if(entry[hr]!=regmap[hr]) {
8575a877 4433 if(!((regs[i].loadedconst>>hr)&1)) {
57871462 4434 if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
8575a877 4435 int value,similar=0;
57871462 4436 if(get_final_value(hr,i,&value)) {
8575a877 4437 // see if some other register has similar value
4438 for(hr2=0;hr2<HOST_REGS;hr2++) {
4439 if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
4440 if(is_similar_value(value,constmap[i][hr2])) {
4441 similar=1;
4442 break;
4443 }
4444 }
4445 }
4446 if(similar) {
4447 int value2;
4448 if(get_final_value(hr2,i,&value2)) // is this needed?
4449 emit_movimm_from(value2,hr2,value,hr);
4450 else
4451 emit_movimm(value,hr);
4452 }
4453 else if(value==0) {
57871462 4454 emit_zeroreg(hr);
4455 }
4456 else {
4457 emit_movimm(value,hr);
4458 }
4459 }
8575a877 4460 regs[i].loadedconst|=1<<hr;
57871462 4461 }
4462 }
4463 }
4464 }
4465 // Load 64-bit regs
4466 for(hr=0;hr<HOST_REGS;hr++) {
4467 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4468 //if(entry[hr]!=regmap[hr]) {
4469 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4470 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4471 if((is32>>(regmap[hr]&63))&1) {
4472 int lr=get_reg(regmap,regmap[hr]-64);
4473 assert(lr>=0);
4474 emit_sarimm(lr,31,hr);
4475 }
4476 else
4477 {
4478 int value;
4479 if(get_final_value(hr,i,&value)) {
4480 if(value==0) {
4481 emit_zeroreg(hr);
4482 }
4483 else {
4484 emit_movimm(value,hr);
4485 }
4486 }
4487 }
4488 }
4489 }
4490 }
4491 }
4492}
4493void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4494{
4495 int hr;
4496 // Load 32-bit regs
4497 for(hr=0;hr<HOST_REGS;hr++) {
4498 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4499 if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4500 int value=constmap[i][hr];
4501 if(value==0) {
4502 emit_zeroreg(hr);
4503 }
4504 else {
4505 emit_movimm(value,hr);
4506 }
4507 }
4508 }
4509 }
4510 // Load 64-bit regs
4511 for(hr=0;hr<HOST_REGS;hr++) {
4512 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4513 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4514 if((is32>>(regmap[hr]&63))&1) {
4515 int lr=get_reg(regmap,regmap[hr]-64);
4516 assert(lr>=0);
4517 emit_sarimm(lr,31,hr);
4518 }
4519 else
4520 {
4521 int value=constmap[i][hr];
4522 if(value==0) {
4523 emit_zeroreg(hr);
4524 }
4525 else {
4526 emit_movimm(value,hr);
4527 }
4528 }
4529 }
4530 }
4531 }
4532}
4533
4534// Write out all dirty registers (except cycle count)
4535void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4536{
4537 int hr;
4538 for(hr=0;hr<HOST_REGS;hr++) {
4539 if(hr!=EXCLUDE_REG) {
4540 if(i_regmap[hr]>0) {
4541 if(i_regmap[hr]!=CCREG) {
4542 if((i_dirty>>hr)&1) {
4543 if(i_regmap[hr]<64) {
4544 emit_storereg(i_regmap[hr],hr);
24385cae 4545#ifndef FORCE32
57871462 4546 if( ((i_is32>>i_regmap[hr])&1) ) {
4547 #ifdef DESTRUCTIVE_WRITEBACK
4548 emit_sarimm(hr,31,hr);
4549 emit_storereg(i_regmap[hr]|64,hr);
4550 #else
4551 emit_sarimm(hr,31,HOST_TEMPREG);
4552 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4553 #endif
4554 }
24385cae 4555#endif
57871462 4556 }else{
4557 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4558 emit_storereg(i_regmap[hr],hr);
4559 }
4560 }
4561 }
4562 }
4563 }
4564 }
4565 }
4566}
4567// Write out dirty registers that we need to reload (pair with load_needed_regs)
4568// This writes the registers not written by store_regs_bt
4569void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4570{
4571 int hr;
4572 int t=(addr-start)>>2;
4573 for(hr=0;hr<HOST_REGS;hr++) {
4574 if(hr!=EXCLUDE_REG) {
4575 if(i_regmap[hr]>0) {
4576 if(i_regmap[hr]!=CCREG) {
4577 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4578 if((i_dirty>>hr)&1) {
4579 if(i_regmap[hr]<64) {
4580 emit_storereg(i_regmap[hr],hr);
24385cae 4581#ifndef FORCE32
57871462 4582 if( ((i_is32>>i_regmap[hr])&1) ) {
4583 #ifdef DESTRUCTIVE_WRITEBACK
4584 emit_sarimm(hr,31,hr);
4585 emit_storereg(i_regmap[hr]|64,hr);
4586 #else
4587 emit_sarimm(hr,31,HOST_TEMPREG);
4588 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4589 #endif
4590 }
24385cae 4591#endif
57871462 4592 }else{
4593 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4594 emit_storereg(i_regmap[hr],hr);
4595 }
4596 }
4597 }
4598 }
4599 }
4600 }
4601 }
4602 }
4603}
4604
4605// Load all registers (except cycle count)
4606void load_all_regs(signed char i_regmap[])
4607{
4608 int hr;
4609 for(hr=0;hr<HOST_REGS;hr++) {
4610 if(hr!=EXCLUDE_REG) {
4611 if(i_regmap[hr]==0) {
4612 emit_zeroreg(hr);
4613 }
4614 else
ea3d2e6e 4615 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
57871462 4616 {
4617 emit_loadreg(i_regmap[hr],hr);
4618 }
4619 }
4620 }
4621}
4622
4623// Load all current registers also needed by next instruction
4624void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4625{
4626 int hr;
4627 for(hr=0;hr<HOST_REGS;hr++) {
4628 if(hr!=EXCLUDE_REG) {
4629 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4630 if(i_regmap[hr]==0) {
4631 emit_zeroreg(hr);
4632 }
4633 else
ea3d2e6e 4634 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
57871462 4635 {
4636 emit_loadreg(i_regmap[hr],hr);
4637 }
4638 }
4639 }
4640 }
4641}
4642
4643// Load all regs, storing cycle count if necessary
4644void load_regs_entry(int t)
4645{
4646 int hr;
2573466a 4647 if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
4648 else if(ccadj[t]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST(ccadj[t]),HOST_CCREG);
57871462 4649 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4650 emit_storereg(CCREG,HOST_CCREG);
4651 }
4652 // Load 32-bit regs
4653 for(hr=0;hr<HOST_REGS;hr++) {
ea3d2e6e 4654 if(regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
57871462 4655 if(regs[t].regmap_entry[hr]==0) {
4656 emit_zeroreg(hr);
4657 }
4658 else if(regs[t].regmap_entry[hr]!=CCREG)
4659 {
4660 emit_loadreg(regs[t].regmap_entry[hr],hr);
4661 }
4662 }
4663 }
4664 // Load 64-bit regs
4665 for(hr=0;hr<HOST_REGS;hr++) {
ea3d2e6e 4666 if(regs[t].regmap_entry[hr]>=64&&regs[t].regmap_entry[hr]<TEMPREG+64) {
57871462 4667 assert(regs[t].regmap_entry[hr]!=64);
4668 if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4669 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4670 if(lr<0) {
4671 emit_loadreg(regs[t].regmap_entry[hr],hr);
4672 }
4673 else
4674 {
4675 emit_sarimm(lr,31,hr);
4676 }
4677 }
4678 else
4679 {
4680 emit_loadreg(regs[t].regmap_entry[hr],hr);
4681 }
4682 }
4683 }
4684}
4685
4686// Store dirty registers prior to branch
4687void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4688{
4689 if(internal_branch(i_is32,addr))
4690 {
4691 int t=(addr-start)>>2;
4692 int hr;
4693 for(hr=0;hr<HOST_REGS;hr++) {
4694 if(hr!=EXCLUDE_REG) {
4695 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4696 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4697 if((i_dirty>>hr)&1) {
4698 if(i_regmap[hr]<64) {
4699 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4700 emit_storereg(i_regmap[hr],hr);
4701 if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4702 #ifdef DESTRUCTIVE_WRITEBACK
4703 emit_sarimm(hr,31,hr);
4704 emit_storereg(i_regmap[hr]|64,hr);
4705 #else
4706 emit_sarimm(hr,31,HOST_TEMPREG);
4707 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4708 #endif
4709 }
4710 }
4711 }else{
4712 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4713 emit_storereg(i_regmap[hr],hr);
4714 }
4715 }
4716 }
4717 }
4718 }
4719 }
4720 }
4721 }
4722 else
4723 {
4724 // Branch out of this block, write out all dirty regs
4725 wb_dirtys(i_regmap,i_is32,i_dirty);
4726 }
4727}
4728
4729// Load all needed registers for branch target
4730void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4731{
4732 //if(addr>=start && addr<(start+slen*4))
4733 if(internal_branch(i_is32,addr))
4734 {
4735 int t=(addr-start)>>2;
4736 int hr;
4737 // Store the cycle count before loading something else
4738 if(i_regmap[HOST_CCREG]!=CCREG) {
4739 assert(i_regmap[HOST_CCREG]==-1);
4740 }
4741 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4742 emit_storereg(CCREG,HOST_CCREG);
4743 }
4744 // Load 32-bit regs
4745 for(hr=0;hr<HOST_REGS;hr++) {
ea3d2e6e 4746 if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
57871462 4747 #ifdef DESTRUCTIVE_WRITEBACK
4748 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4749 #else
4750 if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4751 #endif
4752 if(regs[t].regmap_entry[hr]==0) {
4753 emit_zeroreg(hr);
4754 }
4755 else if(regs[t].regmap_entry[hr]!=CCREG)
4756 {
4757 emit_loadreg(regs[t].regmap_entry[hr],hr);
4758 }
4759 }
4760 }
4761 }
4762 //Load 64-bit regs
4763 for(hr=0;hr<HOST_REGS;hr++) {
ea3d2e6e 4764 if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=64&&regs[t].regmap_entry[hr]<TEMPREG+64) {
57871462 4765 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4766 assert(regs[t].regmap_entry[hr]!=64);
4767 if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4768 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4769 if(lr<0) {
4770 emit_loadreg(regs[t].regmap_entry[hr],hr);
4771 }
4772 else
4773 {
4774 emit_sarimm(lr,31,hr);
4775 }
4776 }
4777 else
4778 {
4779 emit_loadreg(regs[t].regmap_entry[hr],hr);
4780 }
4781 }
4782 else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4783 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4784 assert(lr>=0);
4785 emit_sarimm(lr,31,hr);
4786 }
4787 }
4788 }
4789 }
4790}
4791
4792int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4793{
4794 if(addr>=start && addr<start+slen*4-4)
4795 {
4796 int t=(addr-start)>>2;
4797 int hr;
4798 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4799 for(hr=0;hr<HOST_REGS;hr++)
4800 {
4801 if(hr!=EXCLUDE_REG)
4802 {
4803 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4804 {
ea3d2e6e 4805 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
57871462 4806 {
4807 return 0;
4808 }
4809 else
4810 if((i_dirty>>hr)&1)
4811 {
ea3d2e6e 4812 if(i_regmap[hr]<TEMPREG)
57871462 4813 {
4814 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4815 return 0;
4816 }
ea3d2e6e 4817 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
57871462 4818 {
4819 if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4820 return 0;
4821 }
4822 }
4823 }
4824 else // Same register but is it 32-bit or dirty?
4825 if(i_regmap[hr]>=0)
4826 {
4827 if(!((regs[t].dirty>>hr)&1))
4828 {
4829 if((i_dirty>>hr)&1)
4830 {
4831 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4832 {
4833 //printf("%x: dirty no match\n",addr);
4834 return 0;
4835 }
4836 }
4837 }
4838 if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4839 {
4840 //printf("%x: is32 no match\n",addr);
4841 return 0;
4842 }
4843 }
4844 }
4845 }
4846 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
a28c6ce8 4847#ifndef FORCE32
57871462 4848 if(requires_32bit[t]&~i_is32) return 0;
a28c6ce8 4849#endif
57871462 4850 // Delay slots are not valid branch targets
4851 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4852 // Delay slots require additional processing, so do not match
4853 if(is_ds[t]) return 0;
4854 }
4855 else
4856 {
4857 int hr;
4858 for(hr=0;hr<HOST_REGS;hr++)
4859 {
4860 if(hr!=EXCLUDE_REG)
4861 {
4862 if(i_regmap[hr]>=0)
4863 {
4864 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4865 {
4866 if((i_dirty>>hr)&1)
4867 {
4868 return 0;
4869 }
4870 }
4871 }
4872 }
4873 }
4874 }
4875 return 1;
4876}
4877
4878// Used when a branch jumps into the delay slot of another branch
4879void ds_assemble_entry(int i)
4880{
4881 int t=(ba[i]-start)>>2;
4882 if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4883 assem_debug("Assemble delay slot at %x\n",ba[i]);
4884 assem_debug("<->\n");
4885 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
4886 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4887 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4888 address_generation(t,&regs[t],regs[t].regmap_entry);
b9b61529 4889 if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
57871462 4890 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4891 cop1_usable=0;
4892 is_delayslot=0;
4893 switch(itype[t]) {
4894 case ALU:
4895 alu_assemble(t,&regs[t]);break;
4896 case IMM16:
4897 imm16_assemble(t,&regs[t]);break;
4898 case SHIFT:
4899 shift_assemble(t,&regs[t]);break;
4900 case SHIFTIMM:
4901 shiftimm_assemble(t,&regs[t]);break;
4902 case LOAD:
4903 load_assemble(t,&regs[t]);break;
4904 case LOADLR:
4905 loadlr_assemble(t,&regs[t]);break;
4906 case STORE:
4907 store_assemble(t,&regs[t]);break;
4908 case STORELR:
4909 storelr_assemble(t,&regs[t]);break;
4910 case COP0:
4911 cop0_assemble(t,&regs[t]);break;
4912 case COP1:
4913 cop1_assemble(t,&regs[t]);break;
4914 case C1LS:
4915 c1ls_assemble(t,&regs[t]);break;
b9b61529 4916 case COP2:
4917 cop2_assemble(t,&regs[t]);break;
4918 case C2LS:
4919 c2ls_assemble(t,&regs[t]);break;
4920 case C2OP:
4921 c2op_assemble(t,&regs[t]);break;
57871462 4922 case FCONV:
4923 fconv_assemble(t,&regs[t]);break;
4924 case FLOAT:
4925 float_assemble(t,&regs[t]);break;
4926 case FCOMP:
4927 fcomp_assemble(t,&regs[t]);break;
4928 case MULTDIV:
4929 multdiv_assemble(t,&regs[t]);break;
4930 case MOV:
4931 mov_assemble(t,&regs[t]);break;
4932 case SYSCALL:
7139f3c8 4933 case HLECALL:
1e973cb0 4934 case INTCALL:
57871462 4935 case SPAN:
4936 case UJUMP:
4937 case RJUMP:
4938 case CJUMP:
4939 case SJUMP:
4940 case FJUMP:
4941 printf("Jump in the delay slot. This is probably a bug.\n");
4942 }
4943 store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4944 load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4945 if(internal_branch(regs[t].is32,ba[i]+4))
4946 assem_debug("branch: internal\n");
4947 else
4948 assem_debug("branch: external\n");
4949 assert(internal_branch(regs[t].is32,ba[i]+4));
4950 add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4951 emit_jmp(0);
4952}
4953
4954void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4955{
4956 int count;
4957 int jaddr;
4958 int idle=0;
4959 if(itype[i]==RJUMP)
4960 {
4961 *adj=0;
4962 }
4963 //if(ba[i]>=start && ba[i]<(start+slen*4))
4964 if(internal_branch(branch_regs[i].is32,ba[i]))
4965 {
4966 int t=(ba[i]-start)>>2;
4967 if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4968 else *adj=ccadj[t];
4969 }
4970 else
4971 {
4972 *adj=0;
4973 }
4974 count=ccadj[i];
4975 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4976 // Idle loop
4977 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4978 idle=(int)out;
4979 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4980 emit_andimm(HOST_CCREG,3,HOST_CCREG);
4981 jaddr=(int)out;
4982 emit_jmp(0);
4983 }
4984 else if(*adj==0||invert) {
2573466a 4985 emit_addimm_and_set_flags(CLOCK_ADJUST(count+2),HOST_CCREG);
57871462 4986 jaddr=(int)out;
4987 emit_jns(0);
4988 }
4989 else
4990 {
2573466a 4991 emit_cmpimm(HOST_CCREG,-CLOCK_ADJUST(count+2));
57871462 4992 jaddr=(int)out;
4993 emit_jns(0);
4994 }
4995 add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4996}
4997
4998void do_ccstub(int n)
4999{
5000 literal_pool(256);
5001 assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
5002 set_jump_target(stubs[n][1],(int)out);
5003 int i=stubs[n][4];
5004 if(stubs[n][6]==NULLDS) {
5005 // Delay slot instruction is nullified ("likely" branch)
5006 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
5007 }
5008 else if(stubs[n][6]!=TAKEN) {
5009 wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
5010 }
5011 else {
5012 if(internal_branch(branch_regs[i].is32,ba[i]))
5013 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5014 }
5015 if(stubs[n][5]!=-1)
5016 {
5017 // Save PC as return address
5018 emit_movimm(stubs[n][5],EAX);
5019 emit_writeword(EAX,(int)&pcaddr);
5020 }
5021 else
5022 {
5023 // Return address depends on which way the branch goes
5024 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
5025 {
5026 int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5027 int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5028 int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5029 int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5030 if(rs1[i]==0)
5031 {
5032 s1l=s2l;s1h=s2h;
5033 s2l=s2h=-1;
5034 }
5035 else if(rs2[i]==0)
5036 {
5037 s2l=s2h=-1;
5038 }
5039 if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
5040 s1h=s2h=-1;
5041 }
5042 assert(s1l>=0);
5043 #ifdef DESTRUCTIVE_WRITEBACK
5044 if(rs1[i]) {
5045 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
5046 emit_loadreg(rs1[i],s1l);
5047 }
5048 else {
5049 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
5050 emit_loadreg(rs2[i],s1l);
5051 }
5052 if(s2l>=0)
5053 if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
5054 emit_loadreg(rs2[i],s2l);
5055 #endif
5056 int hr=0;
5194fb95 5057 int addr=-1,alt=-1,ntaddr=-1;
57871462 5058 while(hr<HOST_REGS)
5059 {
5060 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5061 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5062 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5063 {
5064 addr=hr++;break;
5065 }
5066 hr++;
5067 }
5068 while(hr<HOST_REGS)
5069 {
5070 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5071 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5072 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5073 {
5074 alt=hr++;break;
5075 }
5076 hr++;
5077 }
5078 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
5079 {
5080 while(hr<HOST_REGS)
5081 {
5082 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5083 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5084 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5085 {
5086 ntaddr=hr;break;
5087 }
5088 hr++;
5089 }
5090 assert(hr<HOST_REGS);
5091 }
5092 if((opcode[i]&0x2f)==4) // BEQ
5093 {
5094 #ifdef HAVE_CMOV_IMM
5095 if(s1h<0) {
5096 if(s2l>=0) emit_cmp(s1l,s2l);
5097 else emit_test(s1l,s1l);
5098 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5099 }
5100 else
5101 #endif
5102 {
5103 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5104 if(s1h>=0) {
5105 if(s2h>=0) emit_cmp(s1h,s2h);
5106 else emit_test(s1h,s1h);
5107 emit_cmovne_reg(alt,addr);
5108 }
5109 if(s2l>=0) emit_cmp(s1l,s2l);
5110 else emit_test(s1l,s1l);
5111 emit_cmovne_reg(alt,addr);
5112 }
5113 }
5114 if((opcode[i]&0x2f)==5) // BNE
5115 {
5116 #ifdef HAVE_CMOV_IMM
5117 if(s1h<0) {
5118 if(s2l>=0) emit_cmp(s1l,s2l);
5119 else emit_test(s1l,s1l);
5120 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5121 }
5122 else
5123 #endif
5124 {
5125 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5126 if(s1h>=0) {
5127 if(s2h>=0) emit_cmp(s1h,s2h);
5128 else emit_test(s1h,s1h);
5129 emit_cmovne_reg(alt,addr);
5130 }
5131 if(s2l>=0) emit_cmp(s1l,s2l);
5132 else emit_test(s1l,s1l);
5133 emit_cmovne_reg(alt,addr);
5134 }
5135 }
5136 if((opcode[i]&0x2f)==6) // BLEZ
5137 {
5138 //emit_movimm(ba[i],alt);
5139 //emit_movimm(start+i*4+8,addr);
5140 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5141 emit_cmpimm(s1l,1);
5142 if(s1h>=0) emit_mov(addr,ntaddr);
5143 emit_cmovl_reg(alt,addr);
5144 if(s1h>=0) {
5145 emit_test(s1h,s1h);
5146 emit_cmovne_reg(ntaddr,addr);
5147 emit_cmovs_reg(alt,addr);
5148 }
5149 }
5150 if((opcode[i]&0x2f)==7) // BGTZ
5151 {
5152 //emit_movimm(ba[i],addr);
5153 //emit_movimm(start+i*4+8,ntaddr);
5154 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5155 emit_cmpimm(s1l,1);
5156 if(s1h>=0) emit_mov(addr,alt);
5157 emit_cmovl_reg(ntaddr,addr);
5158 if(s1h>=0) {
5159 emit_test(s1h,s1h);
5160 emit_cmovne_reg(alt,addr);
5161 emit_cmovs_reg(ntaddr,addr);
5162 }
5163 }
5164 if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
5165 {
5166 //emit_movimm(ba[i],alt);
5167 //emit_movimm(start+i*4+8,addr);
5168 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5169 if(s1h>=0) emit_test(s1h,s1h);
5170 else emit_test(s1l,s1l);
5171 emit_cmovs_reg(alt,addr);
5172 }
5173 if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
5174 {
5175 //emit_movimm(ba[i],addr);
5176 //emit_movimm(start+i*4+8,alt);
5177 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5178 if(s1h>=0) emit_test(s1h,s1h);
5179 else emit_test(s1l,s1l);
5180 emit_cmovs_reg(alt,addr);
5181 }
5182 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
5183 if(source[i]&0x10000) // BC1T
5184 {
5185 //emit_movimm(ba[i],alt);
5186 //emit_movimm(start+i*4+8,addr);
5187 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5188 emit_testimm(s1l,0x800000);
5189 emit_cmovne_reg(alt,addr);
5190 }
5191 else // BC1F
5192 {
5193 //emit_movimm(ba[i],addr);
5194 //emit_movimm(start+i*4+8,alt);
5195 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5196 emit_testimm(s1l,0x800000);
5197 emit_cmovne_reg(alt,addr);
5198 }
5199 }
5200 emit_writeword(addr,(int)&pcaddr);
5201 }
5202 else
5203 if(itype[i]==RJUMP)
5204 {
5205 int r=get_reg(branch_regs[i].regmap,rs1[i]);
5206 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5207 r=get_reg(branch_regs[i].regmap,RTEMP);
5208 }
5209 emit_writeword(r,(int)&pcaddr);
5210 }
5211 else {printf("Unknown branch type in do_ccstub\n");exit(1);}
5212 }
5213 // Update cycle count
5214 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
2573466a 5215 if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG);
57871462 5216 emit_call((int)cc_interrupt);
2573466a 5217 if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG);
57871462 5218 if(stubs[n][6]==TAKEN) {
5219 if(internal_branch(branch_regs[i].is32,ba[i]))
5220 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
5221 else if(itype[i]==RJUMP) {
5222 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5223 emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5224 else
5225 emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
5226 }
5227 }else if(stubs[n][6]==NOTTAKEN) {
5228 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5229 else load_all_regs(branch_regs[i].regmap);
5230 }else if(stubs[n][6]==NULLDS) {
5231 // Delay slot instruction is nullified ("likely" branch)
5232 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5233 else load_all_regs(regs[i].regmap);
5234 }else{
5235 load_all_regs(branch_regs[i].regmap);
5236 }
5237 emit_jmp(stubs[n][2]); // return address
5238
5239 /* This works but uses a lot of memory...
5240 emit_readword((int)&last_count,ECX);
5241 emit_add(HOST_CCREG,ECX,EAX);
5242 emit_writeword(EAX,(int)&Count);
5243 emit_call((int)gen_interupt);
5244 emit_readword((int)&Count,HOST_CCREG);
5245 emit_readword((int)&next_interupt,EAX);
5246 emit_readword((int)&pending_exception,EBX);
5247 emit_writeword(EAX,(int)&last_count);
5248 emit_sub(HOST_CCREG,EAX,HOST_CCREG);
5249 emit_test(EBX,EBX);
5250 int jne_instr=(int)out;
5251 emit_jne(0);
5252 if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
5253 load_all_regs(branch_regs[i].regmap);
5254 emit_jmp(stubs[n][2]); // return address
5255 set_jump_target(jne_instr,(int)out);
5256 emit_readword((int)&pcaddr,EAX);
5257 // Call get_addr_ht instead of doing the hash table here.
5258 // This code is executed infrequently and takes up a lot of space
5259 // so smaller is better.
5260 emit_storereg(CCREG,HOST_CCREG);
5261 emit_pushreg(EAX);
5262 emit_call((int)get_addr_ht);
5263 emit_loadreg(CCREG,HOST_CCREG);
5264 emit_addimm(ESP,4,ESP);
5265 emit_jmpreg(EAX);*/
5266}
5267
5268add_to_linker(int addr,int target,int ext)
5269{
5270 link_addr[linkcount][0]=addr;
5271 link_addr[linkcount][1]=target;
5272 link_addr[linkcount][2]=ext;
5273 linkcount++;
5274}
5275
eba830cd 5276static void ujump_assemble_write_ra(int i)
5277{
5278 int rt;
5279 unsigned int return_address;
5280 rt=get_reg(branch_regs[i].regmap,31);
5281 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5282 //assert(rt>=0);
5283 return_address=start+i*4+8;
5284 if(rt>=0) {
5285 #ifdef USE_MINI_HT
5286 if(internal_branch(branch_regs[i].is32,return_address)&&rt1[i+1]!=31) {
5287 int temp=-1; // note: must be ds-safe
5288 #ifdef HOST_TEMPREG
5289 temp=HOST_TEMPREG;
5290 #endif
5291 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5292 else emit_movimm(return_address,rt);
5293 }
5294 else
5295 #endif
5296 {
5297 #ifdef REG_PREFETCH
5298 if(temp>=0)
5299 {
5300 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5301 }
5302 #endif
5303 emit_movimm(return_address,rt); // PC into link register
5304 #ifdef IMM_PREFETCH
5305 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5306 #endif
5307 }
5308 }
5309}
5310
57871462 5311void ujump_assemble(int i,struct regstat *i_regs)
5312{
5313 signed char *i_regmap=i_regs->regmap;
eba830cd 5314 int ra_done=0;
57871462 5315 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5316 address_generation(i+1,i_regs,regs[i].regmap_entry);
5317 #ifdef REG_PREFETCH
5318 int temp=get_reg(branch_regs[i].regmap,PTEMP);
5319 if(rt1[i]==31&&temp>=0)
5320 {
5321 int return_address=start+i*4+8;
5322 if(get_reg(branch_regs[i].regmap,31)>0)
5323 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5324 }
5325 #endif
eba830cd 5326 if(rt1[i]==31&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5327 ujump_assemble_write_ra(i); // writeback ra for DS
5328 ra_done=1;
57871462 5329 }
4ef8f67d 5330 ds_assemble(i+1,i_regs);
5331 uint64_t bc_unneeded=branch_regs[i].u;
5332 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5333 bc_unneeded|=1|(1LL<<rt1[i]);
5334 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5335 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5336 bc_unneeded,bc_unneeded_upper);
5337 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
eba830cd 5338 if(!ra_done&&rt1[i]==31)
5339 ujump_assemble_write_ra(i);
57871462 5340 int cc,adj;
5341 cc=get_reg(branch_regs[i].regmap,CCREG);
5342 assert(cc==HOST_CCREG);
5343 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5344 #ifdef REG_PREFETCH
5345 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5346 #endif
5347 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
2573466a 5348 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
57871462 5349 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5350 if(internal_branch(branch_regs[i].is32,ba[i]))
5351 assem_debug("branch: internal\n");
5352 else
5353 assem_debug("branch: external\n");
5354 if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5355 ds_assemble_entry(i);
5356 }
5357 else {
5358 add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5359 emit_jmp(0);
5360 }
5361}
5362
eba830cd 5363static void rjump_assemble_write_ra(int i)
5364{
5365 int rt,return_address;
5366 assert(rt1[i+1]!=rt1[i]);
5367 assert(rt2[i+1]!=rt1[i]);
5368 rt=get_reg(branch_regs[i].regmap,rt1[i]);
5369 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5370 assert(rt>=0);
5371 return_address=start+i*4+8;
5372 #ifdef REG_PREFETCH
5373 if(temp>=0)
5374 {
5375 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5376 }
5377 #endif
5378 emit_movimm(return_address,rt); // PC into link register
5379 #ifdef IMM_PREFETCH
5380 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5381 #endif
5382}
5383
57871462 5384void rjump_assemble(int i,struct regstat *i_regs)
5385{
5386 signed char *i_regmap=i_regs->regmap;
5387 int temp;
5388 int rs,cc,adj;
eba830cd 5389 int ra_done=0;
57871462 5390 rs=get_reg(branch_regs[i].regmap,rs1[i]);
5391 assert(rs>=0);
5392 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5393 // Delay slot abuse, make a copy of the branch address register
5394 temp=get_reg(branch_regs[i].regmap,RTEMP);
5395 assert(temp>=0);
5396 assert(regs[i].regmap[temp]==RTEMP);
5397 emit_mov(rs,temp);
5398 rs=temp;
5399 }
5400 address_generation(i+1,i_regs,regs[i].regmap_entry);
5401 #ifdef REG_PREFETCH
5402 if(rt1[i]==31)
5403 {
5404 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5405 int return_address=start+i*4+8;
5406 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5407 }
5408 }
5409 #endif
5410 #ifdef USE_MINI_HT
5411 if(rs1[i]==31) {
5412 int rh=get_reg(regs[i].regmap,RHASH);
5413 if(rh>=0) do_preload_rhash(rh);
5414 }
5415 #endif
eba830cd 5416 if(rt1[i]!=0&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5417 rjump_assemble_write_ra(i);
5418 ra_done=1;
57871462 5419 }
d5910d5d 5420 ds_assemble(i+1,i_regs);
5421 uint64_t bc_unneeded=branch_regs[i].u;
5422 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5423 bc_unneeded|=1|(1LL<<rt1[i]);
5424 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5425 bc_unneeded&=~(1LL<<rs1[i]);
5426 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5427 bc_unneeded,bc_unneeded_upper);
5428 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
eba830cd 5429 if(!ra_done&&rt1[i]!=0)
5430 rjump_assemble_write_ra(i);
57871462 5431 cc=get_reg(branch_regs[i].regmap,CCREG);
5432 assert(cc==HOST_CCREG);
5433 #ifdef USE_MINI_HT
5434 int rh=get_reg(branch_regs[i].regmap,RHASH);
5435 int ht=get_reg(branch_regs[i].regmap,RHTBL);
5436 if(rs1[i]==31) {
5437 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5438 do_preload_rhtbl(ht);
5439 do_rhash(rs,rh);
5440 }
5441 #endif
5442 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5443 #ifdef DESTRUCTIVE_WRITEBACK
5444 if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5445 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5446 emit_loadreg(rs1[i],rs);
5447 }
5448 }
5449 #endif
5450 #ifdef REG_PREFETCH
5451 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5452 #endif
5453 #ifdef USE_MINI_HT
5454 if(rs1[i]==31) {
5455 do_miniht_load(ht,rh);
5456 }
5457 #endif
5458 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5459 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5460 //assert(adj==0);
2573466a 5461 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
57871462 5462 add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
911f2d55 5463#ifdef PCSX
5464 if(itype[i+1]==COP0&&(source[i+1]&0x3f)==0x10)
5465 // special case for RFE
5466 emit_jmp(0);
5467 else
5468#endif
57871462 5469 emit_jns(0);
5470 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5471 #ifdef USE_MINI_HT
5472 if(rs1[i]==31) {
5473 do_miniht_jump(rs,rh,ht);
5474 }
5475 else
5476 #endif
5477 {
5478 //if(rs!=EAX) emit_mov(rs,EAX);
5479 //emit_jmp((int)jump_vaddr_eax);
5480 emit_jmp(jump_vaddr_reg[rs]);
5481 }
5482 /* Check hash table
5483 temp=!rs;
5484 emit_mov(rs,temp);
5485 emit_shrimm(rs,16,rs);
5486 emit_xor(temp,rs,rs);
5487 emit_movzwl_reg(rs,rs);
5488 emit_shlimm(rs,4,rs);
5489 emit_cmpmem_indexed((int)hash_table,rs,temp);
5490 emit_jne((int)out+14);
5491 emit_readword_indexed((int)hash_table+4,rs,rs);
5492 emit_jmpreg(rs);
5493 emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5494 emit_addimm_no_flags(8,rs);
5495 emit_jeq((int)out-17);
5496 // No hit on hash table, call compiler
5497 emit_pushreg(temp);
5498//DEBUG >
5499#ifdef DEBUG_CYCLE_COUNT
5500 emit_readword((int)&last_count,ECX);
5501 emit_add(HOST_CCREG,ECX,HOST_CCREG);
5502 emit_readword((int)&next_interupt,ECX);
5503 emit_writeword(HOST_CCREG,(int)&Count);
5504 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5505 emit_writeword(ECX,(int)&last_count);
5506#endif
5507//DEBUG <
5508 emit_storereg(CCREG,HOST_CCREG);
5509 emit_call((int)get_addr);
5510 emit_loadreg(CCREG,HOST_CCREG);
5511 emit_addimm(ESP,4,ESP);
5512 emit_jmpreg(EAX);*/
5513 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5514 if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5515 #endif
5516}
5517
5518void cjump_assemble(int i,struct regstat *i_regs)
5519{
5520 signed char *i_regmap=i_regs->regmap;
5521 int cc;
5522 int match;
5523 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5524 assem_debug("match=%d\n",match);
5525 int s1h,s1l,s2h,s2l;
5526 int prev_cop1_usable=cop1_usable;
5527 int unconditional=0,nop=0;
5528 int only32=0;
57871462 5529 int invert=0;
5530 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5531 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 5532 if(!match) invert=1;
5533 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5534 if(i>(ba[i]-start)>>2) invert=1;
5535 #endif
e1190b87 5536
5537 if(ooo[i]) {
57871462 5538 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5539 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5540 s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5541 s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5542 }
5543 else {
5544 s1l=get_reg(i_regmap,rs1[i]);
5545 s1h=get_reg(i_regmap,rs1[i]|64);
5546 s2l=get_reg(i_regmap,rs2[i]);
5547 s2h=get_reg(i_regmap,rs2[i]|64);
5548 }
5549 if(rs1[i]==0&&rs2[i]==0)
5550 {
5551 if(opcode[i]&1) nop=1;
5552 else unconditional=1;
5553 //assert(opcode[i]!=5);
5554 //assert(opcode[i]!=7);
5555 //assert(opcode[i]!=0x15);
5556 //assert(opcode[i]!=0x17);
5557 }
5558 else if(rs1[i]==0)
5559 {
5560 s1l=s2l;s1h=s2h;
5561 s2l=s2h=-1;
5562 only32=(regs[i].was32>>rs2[i])&1;
5563 }
5564 else if(rs2[i]==0)
5565 {
5566 s2l=s2h=-1;
5567 only32=(regs[i].was32>>rs1[i])&1;
5568 }
5569 else {
5570 only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5571 }
5572
e1190b87 5573 if(ooo[i]) {
57871462 5574 // Out of order execution (delay slot first)
5575 //printf("OOOE\n");
5576 address_generation(i+1,i_regs,regs[i].regmap_entry);
5577 ds_assemble(i+1,i_regs);
5578 int adj;
5579 uint64_t bc_unneeded=branch_regs[i].u;
5580 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5581 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5582 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5583 bc_unneeded|=1;
5584 bc_unneeded_upper|=1;
5585 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5586 bc_unneeded,bc_unneeded_upper);
5587 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5588 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5589 cc=get_reg(branch_regs[i].regmap,CCREG);
5590 assert(cc==HOST_CCREG);
5591 if(unconditional)
5592 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5593 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5594 //assem_debug("cycle count (adj)\n");
5595 if(unconditional) {
5596 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5597 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
2573466a 5598 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
57871462 5599 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5600 if(internal)
5601 assem_debug("branch: internal\n");
5602 else
5603 assem_debug("branch: external\n");
5604 if(internal&&is_ds[(ba[i]-start)>>2]) {
5605 ds_assemble_entry(i);
5606 }
5607 else {
5608 add_to_linker((int)out,ba[i],internal);
5609 emit_jmp(0);
5610 }
5611 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5612 if(((u_int)out)&7) emit_addnop(0);
5613 #endif
5614 }
5615 }
5616 else if(nop) {
2573466a 5617 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
57871462 5618 int jaddr=(int)out;
5619 emit_jns(0);
5620 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5621 }
5622 else {
5623 int taken=0,nottaken=0,nottaken1=0;
5624 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
2573466a 5625 if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
57871462 5626 if(!only32)
5627 {
5628 assert(s1h>=0);
5629 if(opcode[i]==4) // BEQ
5630 {
5631 if(s2h>=0) emit_cmp(s1h,s2h);
5632 else emit_test(s1h,s1h);
5633 nottaken1=(int)out;
5634 emit_jne(1);
5635 }
5636 if(opcode[i]==5) // BNE
5637 {
5638 if(s2h>=0) emit_cmp(s1h,s2h);
5639 else emit_test(s1h,s1h);
5640 if(invert) taken=(int)out;
5641 else add_to_linker((int)out,ba[i],internal);
5642 emit_jne(0);
5643 }
5644 if(opcode[i]==6) // BLEZ
5645 {
5646 emit_test(s1h,s1h);
5647 if(invert) taken=(int)out;
5648 else add_to_linker((int)out,ba[i],internal);
5649 emit_js(0);
5650 nottaken1=(int)out;
5651 emit_jne(1);
5652 }
5653 if(opcode[i]==7) // BGTZ
5654 {
5655 emit_test(s1h,s1h);
5656 nottaken1=(int)out;
5657 emit_js(1);
5658 if(invert) taken=(int)out;
5659 else add_to_linker((int)out,ba[i],internal);
5660 emit_jne(0);
5661 }
5662 } // if(!only32)
5663
5664 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5665 assert(s1l>=0);
5666 if(opcode[i]==4) // BEQ
5667 {
5668 if(s2l>=0) emit_cmp(s1l,s2l);
5669 else emit_test(s1l,s1l);
5670 if(invert){
5671 nottaken=(int)out;
5672 emit_jne(1);
5673 }else{
5674 add_to_linker((int)out,ba[i],internal);
5675 emit_jeq(0);
5676 }
5677 }
5678 if(opcode[i]==5) // BNE
5679 {
5680 if(s2l>=0) emit_cmp(s1l,s2l);
5681 else emit_test(s1l,s1l);
5682 if(invert){
5683 nottaken=(int)out;
5684 emit_jeq(1);
5685 }else{
5686 add_to_linker((int)out,ba[i],internal);
5687 emit_jne(0);
5688 }
5689 }
5690 if(opcode[i]==6) // BLEZ
5691 {
5692 emit_cmpimm(s1l,1);
5693 if(invert){
5694 nottaken=(int)out;
5695 emit_jge(1);
5696 }else{
5697 add_to_linker((int)out,ba[i],internal);
5698 emit_jl(0);
5699 }
5700 }
5701 if(opcode[i]==7) // BGTZ
5702 {
5703 emit_cmpimm(s1l,1);
5704 if(invert){
5705 nottaken=(int)out;
5706 emit_jl(1);
5707 }else{
5708 add_to_linker((int)out,ba[i],internal);
5709 emit_jge(0);
5710 }
5711 }
5712 if(invert) {
5713 if(taken) set_jump_target(taken,(int)out);
5714 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5715 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5716 if(adj) {
2573466a 5717 emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
57871462 5718 add_to_linker((int)out,ba[i],internal);
5719 }else{
5720 emit_addnop(13);
5721 add_to_linker((int)out,ba[i],internal*2);
5722 }
5723 emit_jmp(0);
5724 }else
5725 #endif
5726 {
2573466a 5727 if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
57871462 5728 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5729 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5730 if(internal)
5731 assem_debug("branch: internal\n");
5732 else
5733 assem_debug("branch: external\n");
5734 if(internal&&is_ds[(ba[i]-start)>>2]) {
5735 ds_assemble_entry(i);
5736 }
5737 else {
5738 add_to_linker((int)out,ba[i],internal);
5739 emit_jmp(0);
5740 }
5741 }
5742 set_jump_target(nottaken,(int)out);
5743 }
5744
5745 if(nottaken1) set_jump_target(nottaken1,(int)out);
5746 if(adj) {
2573466a 5747 if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
57871462 5748 }
5749 } // (!unconditional)
5750 } // if(ooo)
5751 else
5752 {
5753 // In-order execution (branch first)
5754 //if(likely[i]) printf("IOL\n");
5755 //else
5756 //printf("IOE\n");
5757 int taken=0,nottaken=0,nottaken1=0;
5758 if(!unconditional&&!nop) {
5759 if(!only32)
5760 {
5761 assert(s1h>=0);
5762 if((opcode[i]&0x2f)==4) // BEQ
5763 {
5764 if(s2h>=0) emit_cmp(s1h,s2h);
5765 else emit_test(s1h,s1h);
5766 nottaken1=(int)out;
5767 emit_jne(2);
5768 }
5769 if((opcode[i]&0x2f)==5) // BNE
5770 {
5771 if(s2h>=0) emit_cmp(s1h,s2h);
5772 else emit_test(s1h,s1h);
5773 taken=(int)out;
5774 emit_jne(1);
5775 }
5776 if((opcode[i]&0x2f)==6) // BLEZ
5777 {
5778 emit_test(s1h,s1h);
5779 taken=(int)out;
5780 emit_js(1);
5781 nottaken1=(int)out;
5782 emit_jne(2);
5783 }
5784 if((opcode[i]&0x2f)==7) // BGTZ
5785 {
5786 emit_test(s1h,s1h);
5787 nottaken1=(int)out;
5788 emit_js(2);
5789 taken=(int)out;
5790 emit_jne(1);
5791 }
5792 } // if(!only32)
5793
5794 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5795 assert(s1l>=0);
5796 if((opcode[i]&0x2f)==4) // BEQ
5797 {
5798 if(s2l>=0) emit_cmp(s1l,s2l);
5799 else emit_test(s1l,s1l);
5800 nottaken=(int)out;
5801 emit_jne(2);
5802 }
5803 if((opcode[i]&0x2f)==5) // BNE
5804 {
5805 if(s2l>=0) emit_cmp(s1l,s2l);
5806 else emit_test(s1l,s1l);
5807 nottaken=(int)out;
5808 emit_jeq(2);
5809 }
5810 if((opcode[i]&0x2f)==6) // BLEZ
5811 {
5812 emit_cmpimm(s1l,1);
5813 nottaken=(int)out;
5814 emit_jge(2);
5815 }
5816 if((opcode[i]&0x2f)==7) // BGTZ
5817 {
5818 emit_cmpimm(s1l,1);
5819 nottaken=(int)out;
5820 emit_jl(2);
5821 }
5822 } // if(!unconditional)
5823 int adj;
5824 uint64_t ds_unneeded=branch_regs[i].u;
5825 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5826 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5827 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5828 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5829 ds_unneeded|=1;
5830 ds_unneeded_upper|=1;
5831 // branch taken
5832 if(!nop) {
5833 if(taken) set_jump_target(taken,(int)out);
5834 assem_debug("1:\n");
5835 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5836 ds_unneeded,ds_unneeded_upper);
5837 // load regs
5838 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5839 address_generation(i+1,&branch_regs[i],0);
5840 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5841 ds_assemble(i+1,&branch_regs[i]);
5842 cc=get_reg(branch_regs[i].regmap,CCREG);
5843 if(cc==-1) {
5844 emit_loadreg(CCREG,cc=HOST_CCREG);
5845 // CHECK: Is the following instruction (fall thru) allocated ok?
5846 }
5847 assert(cc==HOST_CCREG);
5848 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5849 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5850 assem_debug("cycle count (adj)\n");
2573466a 5851 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
57871462 5852 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5853 if(internal)
5854 assem_debug("branch: internal\n");
5855 else
5856 assem_debug("branch: external\n");
5857 if(internal&&is_ds[(ba[i]-start)>>2]) {
5858 ds_assemble_entry(i);
5859 }
5860 else {
5861 add_to_linker((int)out,ba[i],internal);
5862 emit_jmp(0);
5863 }
5864 }
5865 // branch not taken
5866 cop1_usable=prev_cop1_usable;
5867 if(!unconditional) {
5868 if(nottaken1) set_jump_target(nottaken1,(int)out);
5869 set_jump_target(nottaken,(int)out);
5870 assem_debug("2:\n");
5871 if(!likely[i]) {
5872 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5873 ds_unneeded,ds_unneeded_upper);
5874 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5875 address_generation(i+1,&branch_regs[i],0);
5876 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5877 ds_assemble(i+1,&branch_regs[i]);
5878 }
5879 cc=get_reg(branch_regs[i].regmap,CCREG);
5880 if(cc==-1&&!likely[i]) {
5881 // Cycle count isn't in a register, temporarily load it then write it out
5882 emit_loadreg(CCREG,HOST_CCREG);
2573466a 5883 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
57871462 5884 int jaddr=(int)out;
5885 emit_jns(0);
5886 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5887 emit_storereg(CCREG,HOST_CCREG);
5888 }
5889 else{
5890 cc=get_reg(i_regmap,CCREG);
5891 assert(cc==HOST_CCREG);
2573466a 5892 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
57871462 5893 int jaddr=(int)out;
5894 emit_jns(0);
5895 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5896 }
5897 }
5898 }
5899}
5900
5901void sjump_assemble(int i,struct regstat *i_regs)
5902{
5903 signed char *i_regmap=i_regs->regmap;
5904 int cc;
5905 int match;
5906 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5907 assem_debug("smatch=%d\n",match);
5908 int s1h,s1l;
5909 int prev_cop1_usable=cop1_usable;
5910 int unconditional=0,nevertaken=0;
5911 int only32=0;
57871462 5912 int invert=0;
5913 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5914 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 5915 if(!match) invert=1;
5916 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5917 if(i>(ba[i]-start)>>2) invert=1;
5918 #endif
5919
5920 //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
df894a3a 5921 //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
57871462 5922
e1190b87 5923 if(ooo[i]) {
57871462 5924 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5925 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5926 }
5927 else {
5928 s1l=get_reg(i_regmap,rs1[i]);
5929 s1h=get_reg(i_regmap,rs1[i]|64);
5930 }
5931 if(rs1[i]==0)
5932 {
5933 if(opcode2[i]&1) unconditional=1;
5934 else nevertaken=1;
5935 // These are never taken (r0 is never less than zero)
5936 //assert(opcode2[i]!=0);
5937 //assert(opcode2[i]!=2);
5938 //assert(opcode2[i]!=0x10);
5939 //assert(opcode2[i]!=0x12);
5940 }
5941 else {
5942 only32=(regs[i].was32>>rs1[i])&1;
5943 }
5944
e1190b87 5945 if(ooo[i]) {
57871462 5946 // Out of order execution (delay slot first)
5947 //printf("OOOE\n");
5948 address_generation(i+1,i_regs,regs[i].regmap_entry);
5949 ds_assemble(i+1,i_regs);
5950 int adj;
5951 uint64_t bc_unneeded=branch_regs[i].u;
5952 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5953 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5954 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5955 bc_unneeded|=1;
5956 bc_unneeded_upper|=1;
5957 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5958 bc_unneeded,bc_unneeded_upper);
5959 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5960 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5961 if(rt1[i]==31) {
5962 int rt,return_address;
57871462 5963 rt=get_reg(branch_regs[i].regmap,31);
5964 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5965 if(rt>=0) {
5966 // Save the PC even if the branch is not taken
5967 return_address=start+i*4+8;
5968 emit_movimm(return_address,rt); // PC into link register
5969 #ifdef IMM_PREFETCH
5970 if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5971 #endif
5972 }
5973 }
5974 cc=get_reg(branch_regs[i].regmap,CCREG);
5975 assert(cc==HOST_CCREG);
5976 if(unconditional)
5977 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5978 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5979 assem_debug("cycle count (adj)\n");
5980 if(unconditional) {
5981 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5982 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
2573466a 5983 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
57871462 5984 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5985 if(internal)
5986 assem_debug("branch: internal\n");
5987 else
5988 assem_debug("branch: external\n");
5989 if(internal&&is_ds[(ba[i]-start)>>2]) {
5990 ds_assemble_entry(i);
5991 }
5992 else {
5993 add_to_linker((int)out,ba[i],internal);
5994 emit_jmp(0);
5995 }
5996 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5997 if(((u_int)out)&7) emit_addnop(0);
5998 #endif
5999 }
6000 }
6001 else if(nevertaken) {
2573466a 6002 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
57871462 6003 int jaddr=(int)out;
6004 emit_jns(0);
6005 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6006 }
6007 else {
6008 int nottaken=0;
6009 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
2573466a 6010 if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
57871462 6011 if(!only32)
6012 {
6013 assert(s1h>=0);
df894a3a 6014 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
57871462 6015 {
6016 emit_test(s1h,s1h);
6017 if(invert){
6018 nottaken=(int)out;
6019 emit_jns(1);
6020 }else{
6021 add_to_linker((int)out,ba[i],internal);
6022 emit_js(0);
6023 }
6024 }
df894a3a 6025 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
57871462 6026 {
6027 emit_test(s1h,s1h);
6028 if(invert){
6029 nottaken=(int)out;
6030 emit_js(1);
6031 }else{
6032 add_to_linker((int)out,ba[i],internal);
6033 emit_jns(0);
6034 }
6035 }
6036 } // if(!only32)
6037 else
6038 {
6039 assert(s1l>=0);
df894a3a 6040 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
57871462 6041 {
6042 emit_test(s1l,s1l);
6043 if(invert){
6044 nottaken=(int)out;
6045 emit_jns(1);
6046 }else{
6047 add_to_linker((int)out,ba[i],internal);
6048 emit_js(0);
6049 }
6050 }
df894a3a 6051 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
57871462 6052 {
6053 emit_test(s1l,s1l);
6054 if(invert){
6055 nottaken=(int)out;
6056 emit_js(1);
6057 }else{
6058 add_to_linker((int)out,ba[i],internal);
6059 emit_jns(0);
6060 }
6061 }
6062 } // if(!only32)
6063
6064 if(invert) {
6065 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6066 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
6067 if(adj) {
2573466a 6068 emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
57871462 6069 add_to_linker((int)out,ba[i],internal);
6070 }else{
6071 emit_addnop(13);
6072 add_to_linker((int)out,ba[i],internal*2);
6073 }
6074 emit_jmp(0);
6075 }else
6076 #endif
6077 {
2573466a 6078 if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
57871462 6079 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6080 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6081 if(internal)
6082 assem_debug("branch: internal\n");
6083 else
6084 assem_debug("branch: external\n");
6085 if(internal&&is_ds[(ba[i]-start)>>2]) {
6086 ds_assemble_entry(i);
6087 }
6088 else {
6089 add_to_linker((int)out,ba[i],internal);
6090 emit_jmp(0);
6091 }
6092 }
6093 set_jump_target(nottaken,(int)out);
6094 }
6095
6096 if(adj) {
2573466a 6097 if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
57871462 6098 }
6099 } // (!unconditional)
6100 } // if(ooo)
6101 else
6102 {
6103 // In-order execution (branch first)
6104 //printf("IOE\n");
6105 int nottaken=0;
a6491170 6106 if(rt1[i]==31) {
6107 int rt,return_address;
a6491170 6108 rt=get_reg(branch_regs[i].regmap,31);
6109 if(rt>=0) {
6110 // Save the PC even if the branch is not taken
6111 return_address=start+i*4+8;
6112 emit_movimm(return_address,rt); // PC into link register
6113 #ifdef IMM_PREFETCH
6114 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
6115 #endif
6116 }
6117 }
57871462 6118 if(!unconditional) {
6119 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6120 if(!only32)
6121 {
6122 assert(s1h>=0);
a6491170 6123 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
57871462 6124 {
6125 emit_test(s1h,s1h);
6126 nottaken=(int)out;
6127 emit_jns(1);
6128 }
a6491170 6129 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
57871462 6130 {
6131 emit_test(s1h,s1h);
6132 nottaken=(int)out;
6133 emit_js(1);
6134 }
6135 } // if(!only32)
6136 else
6137 {
6138 assert(s1l>=0);
a6491170 6139 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
57871462 6140 {
6141 emit_test(s1l,s1l);
6142 nottaken=(int)out;
6143 emit_jns(1);
6144 }
a6491170 6145 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
57871462 6146 {
6147 emit_test(s1l,s1l);
6148 nottaken=(int)out;
6149 emit_js(1);
6150 }
6151 }
6152 } // if(!unconditional)
6153 int adj;
6154 uint64_t ds_unneeded=branch_regs[i].u;
6155 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6156 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6157 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6158 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6159 ds_unneeded|=1;
6160 ds_unneeded_upper|=1;
6161 // branch taken
6162 if(!nevertaken) {
6163 //assem_debug("1:\n");
6164 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6165 ds_unneeded,ds_unneeded_upper);
6166 // load regs
6167 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6168 address_generation(i+1,&branch_regs[i],0);
6169 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6170 ds_assemble(i+1,&branch_regs[i]);
6171 cc=get_reg(branch_regs[i].regmap,CCREG);
6172 if(cc==-1) {
6173 emit_loadreg(CCREG,cc=HOST_CCREG);
6174 // CHECK: Is the following instruction (fall thru) allocated ok?
6175 }
6176 assert(cc==HOST_CCREG);
6177 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6178 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6179 assem_debug("cycle count (adj)\n");
2573466a 6180 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
57871462 6181 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6182 if(internal)
6183 assem_debug("branch: internal\n");
6184 else
6185 assem_debug("branch: external\n");
6186 if(internal&&is_ds[(ba[i]-start)>>2]) {
6187 ds_assemble_entry(i);
6188 }
6189 else {
6190 add_to_linker((int)out,ba[i],internal);
6191 emit_jmp(0);
6192 }
6193 }
6194 // branch not taken
6195 cop1_usable=prev_cop1_usable;
6196 if(!unconditional) {
6197 set_jump_target(nottaken,(int)out);
6198 assem_debug("1:\n");
6199 if(!likely[i]) {
6200 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6201 ds_unneeded,ds_unneeded_upper);
6202 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6203 address_generation(i+1,&branch_regs[i],0);
6204 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6205 ds_assemble(i+1,&branch_regs[i]);
6206 }
6207 cc=get_reg(branch_regs[i].regmap,CCREG);
6208 if(cc==-1&&!likely[i]) {
6209 // Cycle count isn't in a register, temporarily load it then write it out
6210 emit_loadreg(CCREG,HOST_CCREG);
2573466a 6211 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
57871462 6212 int jaddr=(int)out;
6213 emit_jns(0);
6214 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6215 emit_storereg(CCREG,HOST_CCREG);
6216 }
6217 else{
6218 cc=get_reg(i_regmap,CCREG);
6219 assert(cc==HOST_CCREG);
2573466a 6220 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
57871462 6221 int jaddr=(int)out;
6222 emit_jns(0);
6223 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6224 }
6225 }
6226 }
6227}
6228
6229void fjump_assemble(int i,struct regstat *i_regs)
6230{
6231 signed char *i_regmap=i_regs->regmap;
6232 int cc;
6233 int match;
6234 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6235 assem_debug("fmatch=%d\n",match);
6236 int fs,cs;
6237 int eaddr;
57871462 6238 int invert=0;
6239 int internal=internal_branch(branch_regs[i].is32,ba[i]);
6240 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 6241 if(!match) invert=1;
6242 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6243 if(i>(ba[i]-start)>>2) invert=1;
6244 #endif
6245
e1190b87 6246 if(ooo[i]) {
57871462 6247 fs=get_reg(branch_regs[i].regmap,FSREG);
6248 address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
6249 }
6250 else {
6251 fs=get_reg(i_regmap,FSREG);
6252 }
6253
6254 // Check cop1 unusable
6255 if(!cop1_usable) {
6256 cs=get_reg(i_regmap,CSREG);
6257 assert(cs>=0);
6258 emit_testimm(cs,0x20000000);
6259 eaddr=(int)out;
6260 emit_jeq(0);
6261 add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
6262 cop1_usable=1;
6263 }
6264
e1190b87 6265 if(ooo[i]) {
57871462 6266 // Out of order execution (delay slot first)
6267 //printf("OOOE\n");
6268 ds_assemble(i+1,i_regs);
6269 int adj;
6270 uint64_t bc_unneeded=branch_regs[i].u;
6271 uint64_t bc_unneeded_upper=branch_regs[i].uu;
6272 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6273 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
6274 bc_unneeded|=1;
6275 bc_unneeded_upper|=1;
6276 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6277 bc_unneeded,bc_unneeded_upper);
6278 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
6279 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6280 cc=get_reg(branch_regs[i].regmap,CCREG);
6281 assert(cc==HOST_CCREG);
6282 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6283 assem_debug("cycle count (adj)\n");
6284 if(1) {
6285 int nottaken=0;
2573466a 6286 if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
57871462 6287 if(1) {
6288 assert(fs>=0);
6289 emit_testimm(fs,0x800000);
6290 if(source[i]&0x10000) // BC1T
6291 {
6292 if(invert){
6293 nottaken=(int)out;
6294 emit_jeq(1);
6295 }else{
6296 add_to_linker((int)out,ba[i],internal);
6297 emit_jne(0);
6298 }
6299 }
6300 else // BC1F
6301 if(invert){
6302 nottaken=(int)out;
6303 emit_jne(1);
6304 }else{
6305 add_to_linker((int)out,ba[i],internal);
6306 emit_jeq(0);
6307 }
6308 {
6309 }
6310 } // if(!only32)
6311
6312 if(invert) {
2573466a 6313 if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
57871462 6314 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6315 else if(match) emit_addnop(13);
6316 #endif
6317 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6318 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6319 if(internal)
6320 assem_debug("branch: internal\n");
6321 else
6322 assem_debug("branch: external\n");
6323 if(internal&&is_ds[(ba[i]-start)>>2]) {
6324 ds_assemble_entry(i);
6325 }
6326 else {
6327 add_to_linker((int)out,ba[i],internal);
6328 emit_jmp(0);
6329 }
6330 set_jump_target(nottaken,(int)out);
6331 }
6332
6333 if(adj) {
2573466a 6334 if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
57871462 6335 }
6336 } // (!unconditional)
6337 } // if(ooo)
6338 else
6339 {
6340 // In-order execution (branch first)
6341 //printf("IOE\n");
6342 int nottaken=0;
6343 if(1) {
6344 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6345 if(1) {
6346 assert(fs>=0);
6347 emit_testimm(fs,0x800000);
6348 if(source[i]&0x10000) // BC1T
6349 {
6350 nottaken=(int)out;
6351 emit_jeq(1);
6352 }
6353 else // BC1F
6354 {
6355 nottaken=(int)out;
6356 emit_jne(1);
6357 }
6358 }
6359 } // if(!unconditional)
6360 int adj;
6361 uint64_t ds_unneeded=branch_regs[i].u;
6362 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6363 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6364 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6365 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6366 ds_unneeded|=1;
6367 ds_unneeded_upper|=1;
6368 // branch taken
6369 //assem_debug("1:\n");
6370 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6371 ds_unneeded,ds_unneeded_upper);
6372 // load regs
6373 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6374 address_generation(i+1,&branch_regs[i],0);
6375 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6376 ds_assemble(i+1,&branch_regs[i]);
6377 cc=get_reg(branch_regs[i].regmap,CCREG);
6378 if(cc==-1) {
6379 emit_loadreg(CCREG,cc=HOST_CCREG);
6380 // CHECK: Is the following instruction (fall thru) allocated ok?
6381 }
6382 assert(cc==HOST_CCREG);
6383 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6384 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6385 assem_debug("cycle count (adj)\n");
2573466a 6386 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
57871462 6387 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6388 if(internal)
6389 assem_debug("branch: internal\n");
6390 else
6391 assem_debug("branch: external\n");
6392 if(internal&&is_ds[(ba[i]-start)>>2]) {
6393 ds_assemble_entry(i);
6394 }
6395 else {
6396 add_to_linker((int)out,ba[i],internal);
6397 emit_jmp(0);
6398 }
6399
6400 // branch not taken
6401 if(1) { // <- FIXME (don't need this)
6402 set_jump_target(nottaken,(int)out);
6403 assem_debug("1:\n");
6404 if(!likely[i]) {
6405 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6406 ds_unneeded,ds_unneeded_upper);
6407 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6408 address_generation(i+1,&branch_regs[i],0);
6409 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6410 ds_assemble(i+1,&branch_regs[i]);
6411 }
6412 cc=get_reg(branch_regs[i].regmap,CCREG);
6413 if(cc==-1&&!likely[i]) {
6414 // Cycle count isn't in a register, temporarily load it then write it out
6415 emit_loadreg(CCREG,HOST_CCREG);
2573466a 6416 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
57871462 6417 int jaddr=(int)out;
6418 emit_jns(0);
6419 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6420 emit_storereg(CCREG,HOST_CCREG);
6421 }
6422 else{
6423 cc=get_reg(i_regmap,CCREG);
6424 assert(cc==HOST_CCREG);
2573466a 6425 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
57871462 6426 int jaddr=(int)out;
6427 emit_jns(0);
6428 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6429 }
6430 }
6431 }
6432}
6433
6434static void pagespan_assemble(int i,struct regstat *i_regs)
6435{
6436 int s1l=get_reg(i_regs->regmap,rs1[i]);
6437 int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6438 int s2l=get_reg(i_regs->regmap,rs2[i]);
6439 int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6440 void *nt_branch=NULL;
6441 int taken=0;
6442 int nottaken=0;
6443 int unconditional=0;
6444 if(rs1[i]==0)
6445 {
6446 s1l=s2l;s1h=s2h;
6447 s2l=s2h=-1;
6448 }
6449 else if(rs2[i]==0)
6450 {
6451 s2l=s2h=-1;
6452 }
6453 if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6454 s1h=s2h=-1;
6455 }
6456 int hr=0;
6457 int addr,alt,ntaddr;
6458 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6459 else {
6460 while(hr<HOST_REGS)
6461 {
6462 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6463 (i_regs->regmap[hr]&63)!=rs1[i] &&
6464 (i_regs->regmap[hr]&63)!=rs2[i] )
6465 {
6466 addr=hr++;break;
6467 }
6468 hr++;
6469 }
6470 }
6471 while(hr<HOST_REGS)
6472 {
6473 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6474 (i_regs->regmap[hr]&63)!=rs1[i] &&
6475 (i_regs->regmap[hr]&63)!=rs2[i] )
6476 {
6477 alt=hr++;break;
6478 }
6479 hr++;
6480 }
6481 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6482 {
6483 while(hr<HOST_REGS)
6484 {
6485 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6486 (i_regs->regmap[hr]&63)!=rs1[i] &&
6487 (i_regs->regmap[hr]&63)!=rs2[i] )
6488 {
6489 ntaddr=hr;break;
6490 }
6491 hr++;
6492 }
6493 }
6494 assert(hr<HOST_REGS);
6495 if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6496 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6497 }
2573466a 6498 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
57871462 6499 if(opcode[i]==2) // J
6500 {
6501 unconditional=1;
6502 }
6503 if(opcode[i]==3) // JAL
6504 {
6505 // TODO: mini_ht
6506 int rt=get_reg(i_regs->regmap,31);
6507 emit_movimm(start+i*4+8,rt);
6508 unconditional=1;
6509 }
6510 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6511 {
6512 emit_mov(s1l,addr);
6513 if(opcode2[i]==9) // JALR
6514 {
5067f341 6515 int rt=get_reg(i_regs->regmap,rt1[i]);
57871462 6516 emit_movimm(start+i*4+8,rt);
6517 }
6518 }
6519 if((opcode[i]&0x3f)==4) // BEQ
6520 {
6521 if(rs1[i]==rs2[i])
6522 {
6523 unconditional=1;
6524 }
6525 else
6526 #ifdef HAVE_CMOV_IMM
6527 if(s1h<0) {
6528 if(s2l>=0) emit_cmp(s1l,s2l);
6529 else emit_test(s1l,s1l);
6530 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6531 }
6532 else
6533 #endif
6534 {
6535 assert(s1l>=0);
6536 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6537 if(s1h>=0) {
6538 if(s2h>=0) emit_cmp(s1h,s2h);
6539 else emit_test(s1h,s1h);
6540 emit_cmovne_reg(alt,addr);
6541 }
6542 if(s2l>=0) emit_cmp(s1l,s2l);
6543 else emit_test(s1l,s1l);
6544 emit_cmovne_reg(alt,addr);
6545 }
6546 }
6547 if((opcode[i]&0x3f)==5) // BNE
6548 {
6549 #ifdef HAVE_CMOV_IMM
6550 if(s1h<0) {
6551 if(s2l>=0) emit_cmp(s1l,s2l);
6552 else emit_test(s1l,s1l);
6553 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6554 }
6555 else
6556 #endif
6557 {
6558 assert(s1l>=0);
6559 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6560 if(s1h>=0) {
6561 if(s2h>=0) emit_cmp(s1h,s2h);
6562 else emit_test(s1h,s1h);
6563 emit_cmovne_reg(alt,addr);
6564 }
6565 if(s2l>=0) emit_cmp(s1l,s2l);
6566 else emit_test(s1l,s1l);
6567 emit_cmovne_reg(alt,addr);
6568 }
6569 }
6570 if((opcode[i]&0x3f)==0x14) // BEQL
6571 {
6572 if(s1h>=0) {
6573 if(s2h>=0) emit_cmp(s1h,s2h);
6574 else emit_test(s1h,s1h);
6575 nottaken=(int)out;
6576 emit_jne(0);
6577 }
6578 if(s2l>=0) emit_cmp(s1l,s2l);
6579 else emit_test(s1l,s1l);
6580 if(nottaken) set_jump_target(nottaken,(int)out);
6581 nottaken=(int)out;
6582 emit_jne(0);
6583 }
6584 if((opcode[i]&0x3f)==0x15) // BNEL
6585 {
6586 if(s1h>=0) {
6587 if(s2h>=0) emit_cmp(s1h,s2h);
6588 else emit_test(s1h,s1h);
6589 taken=(int)out;
6590 emit_jne(0);
6591 }
6592 if(s2l>=0) emit_cmp(s1l,s2l);
6593 else emit_test(s1l,s1l);
6594 nottaken=(int)out;
6595 emit_jeq(0);
6596 if(taken) set_jump_target(taken,(int)out);
6597 }
6598 if((opcode[i]&0x3f)==6) // BLEZ
6599 {
6600 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6601 emit_cmpimm(s1l,1);
6602 if(s1h>=0) emit_mov(addr,ntaddr);
6603 emit_cmovl_reg(alt,addr);
6604 if(s1h>=0) {
6605 emit_test(s1h,s1h);
6606 emit_cmovne_reg(ntaddr,addr);
6607 emit_cmovs_reg(alt,addr);
6608 }
6609 }
6610 if((opcode[i]&0x3f)==7) // BGTZ
6611 {
6612 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6613 emit_cmpimm(s1l,1);
6614 if(s1h>=0) emit_mov(addr,alt);
6615 emit_cmovl_reg(ntaddr,addr);
6616 if(s1h>=0) {
6617 emit_test(s1h,s1h);
6618 emit_cmovne_reg(alt,addr);
6619 emit_cmovs_reg(ntaddr,addr);
6620 }
6621 }
6622 if((opcode[i]&0x3f)==0x16) // BLEZL
6623 {
6624 assert((opcode[i]&0x3f)!=0x16);
6625 }
6626 if((opcode[i]&0x3f)==0x17) // BGTZL
6627 {
6628 assert((opcode[i]&0x3f)!=0x17);
6629 }
6630 assert(opcode[i]!=1); // BLTZ/BGEZ
6631
6632 //FIXME: Check CSREG
6633 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6634 if((source[i]&0x30000)==0) // BC1F
6635 {
6636 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6637 emit_testimm(s1l,0x800000);
6638 emit_cmovne_reg(alt,addr);
6639 }
6640 if((source[i]&0x30000)==0x10000) // BC1T
6641 {
6642 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6643 emit_testimm(s1l,0x800000);
6644 emit_cmovne_reg(alt,addr);
6645 }
6646 if((source[i]&0x30000)==0x20000) // BC1FL
6647 {
6648 emit_testimm(s1l,0x800000);
6649 nottaken=(int)out;
6650 emit_jne(0);
6651 }
6652 if((source[i]&0x30000)==0x30000) // BC1TL
6653 {
6654 emit_testimm(s1l,0x800000);
6655 nottaken=(int)out;
6656 emit_jeq(0);
6657 }
6658 }
6659
6660 assert(i_regs->regmap[HOST_CCREG]==CCREG);
6661 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6662 if(likely[i]||unconditional)
6663 {
6664 emit_movimm(ba[i],HOST_BTREG);
6665 }
6666 else if(addr!=HOST_BTREG)
6667 {
6668 emit_mov(addr,HOST_BTREG);
6669 }
6670 void *branch_addr=out;
6671 emit_jmp(0);
6672 int target_addr=start+i*4+5;
6673 void *stub=out;
6674 void *compiled_target_addr=check_addr(target_addr);
6675 emit_extjump_ds((int)branch_addr,target_addr);
6676 if(compiled_target_addr) {
6677 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6678 add_link(target_addr,stub);
6679 }
6680 else set_jump_target((int)branch_addr,(int)stub);
6681 if(likely[i]) {
6682 // Not-taken path
6683 set_jump_target((int)nottaken,(int)out);
6684 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6685 void *branch_addr=out;
6686 emit_jmp(0);
6687 int target_addr=start+i*4+8;
6688 void *stub=out;
6689 void *compiled_target_addr=check_addr(target_addr);
6690 emit_extjump_ds((int)branch_addr,target_addr);
6691 if(compiled_target_addr) {
6692 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6693 add_link(target_addr,stub);
6694 }
6695 else set_jump_target((int)branch_addr,(int)stub);
6696 }
6697}
6698
6699// Assemble the delay slot for the above
6700static void pagespan_ds()
6701{
6702 assem_debug("initial delay slot:\n");
6703 u_int vaddr=start+1;
94d23bb9 6704 u_int page=get_page(vaddr);
6705 u_int vpage=get_vpage(vaddr);
57871462 6706 ll_add(jump_dirty+vpage,vaddr,(void *)out);
6707 do_dirty_stub_ds();
6708 ll_add(jump_in+page,vaddr,(void *)out);
6709 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6710 if(regs[0].regmap[HOST_CCREG]!=CCREG)
6711 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6712 if(regs[0].regmap[HOST_BTREG]!=BTREG)
6713 emit_writeword(HOST_BTREG,(int)&branch_target);
6714 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6715 address_generation(0,&regs[0],regs[0].regmap_entry);
b9b61529 6716 if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
57871462 6717 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6718 cop1_usable=0;
6719 is_delayslot=0;
6720 switch(itype[0]) {
6721 case ALU:
6722 alu_assemble(0,&regs[0]);break;
6723 case IMM16:
6724 imm16_assemble(0,&regs[0]);break;
6725 case SHIFT:
6726 shift_assemble(0,&regs[0]);break;
6727 case SHIFTIMM:
6728 shiftimm_assemble(0,&regs[0]);break;
6729 case LOAD:
6730 load_assemble(0,&regs[0]);break;
6731 case LOADLR:
6732 loadlr_assemble(0,&regs[0]);break;
6733 case STORE:
6734 store_assemble(0,&regs[0]);break;
6735 case STORELR:
6736 storelr_assemble(0,&regs[0]);break;
6737 case COP0:
6738 cop0_assemble(0,&regs[0]);break;
6739 case COP1:
6740 cop1_assemble(0,&regs[0]);break;
6741 case C1LS:
6742 c1ls_assemble(0,&regs[0]);break;
b9b61529 6743 case COP2:
6744 cop2_assemble(0,&regs[0]);break;
6745 case C2LS:
6746 c2ls_assemble(0,&regs[0]);break;
6747 case C2OP:
6748 c2op_assemble(0,&regs[0]);break;
57871462 6749 case FCONV:
6750 fconv_assemble(0,&regs[0]);break;
6751 case FLOAT:
6752 float_assemble(0,&regs[0]);break;
6753 case FCOMP:
6754 fcomp_assemble(0,&regs[0]);break;
6755 case MULTDIV:
6756 multdiv_assemble(0,&regs[0]);break;
6757 case MOV:
6758 mov_assemble(0,&regs[0]);break;
6759 case SYSCALL:
7139f3c8 6760 case HLECALL:
1e973cb0 6761 case INTCALL:
57871462 6762 case SPAN:
6763 case UJUMP:
6764 case RJUMP:
6765 case CJUMP:
6766 case SJUMP:
6767 case FJUMP:
6768 printf("Jump in the delay slot. This is probably a bug.\n");
6769 }
6770 int btaddr=get_reg(regs[0].regmap,BTREG);
6771 if(btaddr<0) {
6772 btaddr=get_reg(regs[0].regmap,-1);
6773 emit_readword((int)&branch_target,btaddr);
6774 }
6775 assert(btaddr!=HOST_CCREG);
6776 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6777#ifdef HOST_IMM8
6778 emit_movimm(start+4,HOST_TEMPREG);
6779 emit_cmp(btaddr,HOST_TEMPREG);
6780#else
6781 emit_cmpimm(btaddr,start+4);
6782#endif
6783 int branch=(int)out;
6784 emit_jeq(0);
6785 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6786 emit_jmp(jump_vaddr_reg[btaddr]);
6787 set_jump_target(branch,(int)out);
6788 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6789 load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6790}
6791
6792// Basic liveness analysis for MIPS registers
6793void unneeded_registers(int istart,int iend,int r)
6794{
6795 int i;
bedfea38 6796 uint64_t u,uu,gte_u,b,bu,gte_bu;
0ff8c62c 6797 uint64_t temp_u,temp_uu,temp_gte_u=0;
57871462 6798 uint64_t tdep;
0ff8c62c 6799 uint64_t gte_u_unknown=0;
6800 if(new_dynarec_hacks&NDHACK_GTE_UNNEEDED)
6801 gte_u_unknown=~0ll;
57871462 6802 if(iend==slen-1) {
6803 u=1;uu=1;
0ff8c62c 6804 gte_u=gte_u_unknown;
57871462 6805 }else{
6806 u=unneeded_reg[iend+1];
6807 uu=unneeded_reg_upper[iend+1];
6808 u=1;uu=1;
0ff8c62c 6809 gte_u=gte_unneeded[iend+1];
57871462 6810 }
bedfea38 6811
57871462 6812 for (i=iend;i>=istart;i--)
6813 {
6814 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6815 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6816 {
6817 // If subroutine call, flag return address as a possible branch target
6818 if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6819
6820 if(ba[i]<start || ba[i]>=(start+slen*4))
6821 {
6822 // Branch out of this block, flush all regs
6823 u=1;
6824 uu=1;
0ff8c62c 6825 gte_u=gte_u_unknown;
57871462 6826 /* Hexagon hack
6827 if(itype[i]==UJUMP&&rt1[i]==31)
6828 {
6829 uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6830 }
6831 if(itype[i]==RJUMP&&rs1[i]==31)
6832 {
6833 uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6834 }
4cb76aa4 6835 if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
57871462 6836 if(itype[i]==UJUMP&&rt1[i]==31)
6837 {
6838 //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6839 uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6840 }
6841 if(itype[i]==RJUMP&&rs1[i]==31)
6842 {
6843 //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6844 uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6845 }
6846 }*/
6847 branch_unneeded_reg[i]=u;
6848 branch_unneeded_reg_upper[i]=uu;
6849 // Merge in delay slot
6850 tdep=(~uu>>rt1[i+1])&1;
6851 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6852 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6853 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6854 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6855 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6856 u|=1;uu|=1;
bedfea38 6857 gte_u|=gte_rt[i+1];
6858 gte_u&=~gte_rs[i+1];
57871462 6859 // If branch is "likely" (and conditional)
6860 // then we skip the delay slot on the fall-thru path
6861 if(likely[i]) {
6862 if(i<slen-1) {
6863 u&=unneeded_reg[i+2];
6864 uu&=unneeded_reg_upper[i+2];
bedfea38 6865 gte_u&=gte_unneeded[i+2];
57871462 6866 }
6867 else
6868 {
6869 u=1;
6870 uu=1;
0ff8c62c 6871 gte_u=gte_u_unknown;
57871462 6872 }
6873 }
6874 }
6875 else
6876 {
6877 // Internal branch, flag target
6878 bt[(ba[i]-start)>>2]=1;
6879 if(ba[i]<=start+i*4) {
6880 // Backward branch
6881 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6882 {
6883 // Unconditional branch
6884 temp_u=1;temp_uu=1;
bedfea38 6885 temp_gte_u=0;
57871462 6886 } else {
6887 // Conditional branch (not taken case)
6888 temp_u=unneeded_reg[i+2];
6889 temp_uu=unneeded_reg_upper[i+2];
bedfea38 6890 temp_gte_u&=gte_unneeded[i+2];
57871462 6891 }
6892 // Merge in delay slot
6893 tdep=(~temp_uu>>rt1[i+1])&1;
6894 temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6895 temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6896 temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6897 temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6898 temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6899 temp_u|=1;temp_uu|=1;
bedfea38 6900 temp_gte_u|=gte_rt[i+1];
6901 temp_gte_u&=~gte_rs[i+1];
57871462 6902 // If branch is "likely" (and conditional)
6903 // then we skip the delay slot on the fall-thru path
6904 if(likely[i]) {
6905 if(i<slen-1) {
6906 temp_u&=unneeded_reg[i+2];
6907 temp_uu&=unneeded_reg_upper[i+2];
bedfea38 6908 temp_gte_u&=gte_unneeded[i+2];
57871462 6909 }
6910 else
6911 {
6912 temp_u=1;
6913 temp_uu=1;
0ff8c62c 6914 temp_gte_u=gte_u_unknown;
57871462 6915 }
6916 }
6917 tdep=(~temp_uu>>rt1[i])&1;
6918 temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6919 temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6920 temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6921 temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6922 temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6923 temp_u|=1;temp_uu|=1;
bedfea38 6924 temp_gte_u|=gte_rt[i];
6925 temp_gte_u&=~gte_rs[i];
57871462 6926 unneeded_reg[i]=temp_u;
6927 unneeded_reg_upper[i]=temp_uu;
bedfea38 6928 gte_unneeded[i]=temp_gte_u;
57871462 6929 // Only go three levels deep. This recursion can take an
6930 // excessive amount of time if there are a lot of nested loops.
6931 if(r<2) {
6932 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6933 }else{
6934 unneeded_reg[(ba[i]-start)>>2]=1;
6935 unneeded_reg_upper[(ba[i]-start)>>2]=1;
0ff8c62c 6936 gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown;
57871462 6937 }
6938 } /*else*/ if(1) {
6939 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6940 {
6941 // Unconditional branch
6942 u=unneeded_reg[(ba[i]-start)>>2];
6943 uu=unneeded_reg_upper[(ba[i]-start)>>2];
bedfea38 6944 gte_u=gte_unneeded[(ba[i]-start)>>2];
57871462 6945 branch_unneeded_reg[i]=u;
6946 branch_unneeded_reg_upper[i]=uu;
6947 //u=1;
6948 //uu=1;
6949 //branch_unneeded_reg[i]=u;
6950 //branch_unneeded_reg_upper[i]=uu;
6951 // Merge in delay slot
6952 tdep=(~uu>>rt1[i+1])&1;
6953 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6954 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6955 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6956 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6957 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6958 u|=1;uu|=1;
bedfea38 6959 gte_u|=gte_rt[i+1];
6960 gte_u&=~gte_rs[i+1];
57871462 6961 } else {
6962 // Conditional branch
6963 b=unneeded_reg[(ba[i]-start)>>2];
6964 bu=unneeded_reg_upper[(ba[i]-start)>>2];
bedfea38 6965 gte_bu=gte_unneeded[(ba[i]-start)>>2];
57871462 6966 branch_unneeded_reg[i]=b;
6967 branch_unneeded_reg_upper[i]=bu;
6968 //b=1;
6969 //bu=1;
6970 //branch_unneeded_reg[i]=b;
6971 //branch_unneeded_reg_upper[i]=bu;
6972 // Branch delay slot
6973 tdep=(~uu>>rt1[i+1])&1;
6974 b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6975 bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6976 b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6977 bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6978 bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6979 b|=1;bu|=1;
bedfea38 6980 gte_bu|=gte_rt[i+1];
6981 gte_bu&=~gte_rs[i+1];
57871462 6982 // If branch is "likely" then we skip the
6983 // delay slot on the fall-thru path
6984 if(likely[i]) {
6985 u=b;
6986 uu=bu;
bedfea38 6987 gte_u=gte_bu;
57871462 6988 if(i<slen-1) {
6989 u&=unneeded_reg[i+2];
6990 uu&=unneeded_reg_upper[i+2];
bedfea38 6991 gte_u&=gte_unneeded[i+2];
57871462 6992 //u=1;
6993 //uu=1;
6994 }
6995 } else {
6996 u&=b;
6997 uu&=bu;
bedfea38 6998 gte_u&=gte_bu;
57871462 6999 //u=1;
7000 //uu=1;
7001 }
7002 if(i<slen-1) {
7003 branch_unneeded_reg[i]&=unneeded_reg[i+2];
7004 branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
7005 //branch_unneeded_reg[i]=1;
7006 //branch_unneeded_reg_upper[i]=1;
7007 } else {
7008 branch_unneeded_reg[i]=1;
7009 branch_unneeded_reg_upper[i]=1;
7010 }
7011 }
7012 }
7013 }
7014 }
1e973cb0 7015 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 7016 {
7017 // SYSCALL instruction (software interrupt)
7018 u=1;
7019 uu=1;
7020 }
7021 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7022 {
7023 // ERET instruction (return from interrupt)
7024 u=1;
7025 uu=1;
7026 }
7027 //u=uu=1; // DEBUG
7028 tdep=(~uu>>rt1[i])&1;
7029 // Written registers are unneeded
7030 u|=1LL<<rt1[i];
7031 u|=1LL<<rt2[i];
7032 uu|=1LL<<rt1[i];
7033 uu|=1LL<<rt2[i];
bedfea38 7034 gte_u|=gte_rt[i];
57871462 7035 // Accessed registers are needed
7036 u&=~(1LL<<rs1[i]);
7037 u&=~(1LL<<rs2[i]);
7038 uu&=~(1LL<<us1[i]);
7039 uu&=~(1LL<<us2[i]);
bedfea38 7040 gte_u&=~gte_rs[i];
eaa11918 7041 if(gte_rs[i]&&rt1[i]&&(unneeded_reg[i+1]&(1ll<<rt1[i])))
cbbd8dd7 7042 gte_u|=gte_rs[i]&gte_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded
57871462 7043 // Source-target dependencies
7044 uu&=~(tdep<<dep1[i]);
7045 uu&=~(tdep<<dep2[i]);
7046 // R0 is always unneeded
7047 u|=1;uu|=1;
7048 // Save it
7049 unneeded_reg[i]=u;
7050 unneeded_reg_upper[i]=uu;
bedfea38 7051 gte_unneeded[i]=gte_u;
57871462 7052 /*
7053 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
7054 printf("U:");
7055 int r;
7056 for(r=1;r<=CCREG;r++) {
7057 if((unneeded_reg[i]>>r)&1) {
7058 if(r==HIREG) printf(" HI");
7059 else if(r==LOREG) printf(" LO");
7060 else printf(" r%d",r);
7061 }
7062 }
7063 printf(" UU:");
7064 for(r=1;r<=CCREG;r++) {
7065 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
7066 if(r==HIREG) printf(" HI");
7067 else if(r==LOREG) printf(" LO");
7068 else printf(" r%d",r);
7069 }
7070 }
7071 printf("\n");*/
7072 }
252c20fc 7073#ifdef FORCE32
7074 for (i=iend;i>=istart;i--)
7075 {
7076 unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
7077 }
7078#endif
57871462 7079}
7080
7081// Identify registers which are likely to contain 32-bit values
7082// This is used to predict whether any branches will jump to a
7083// location with 64-bit values in registers.
7084static void provisional_32bit()
7085{
7086 int i,j;
7087 uint64_t is32=1;
7088 uint64_t lastbranch=1;
7089
7090 for(i=0;i<slen;i++)
7091 {
7092 if(i>0) {
7093 if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
7094 if(i>1) is32=lastbranch;
7095 else is32=1;
7096 }
7097 }
7098 if(i>1)
7099 {
7100 if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
7101 if(likely[i-2]) {
7102 if(i>2) is32=lastbranch;
7103 else is32=1;
7104 }
7105 }
7106 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
7107 {
7108 if(rs1[i-2]==0||rs2[i-2]==0)
7109 {
7110 if(rs1[i-2]) {
7111 is32|=1LL<<rs1[i-2];
7112 }
7113 if(rs2[i-2]) {
7114 is32|=1LL<<rs2[i-2];
7115 }
7116 }
7117 }
7118 }
7119 // If something jumps here with 64-bit values
7120 // then promote those registers to 64 bits
7121 if(bt[i])
7122 {
7123 uint64_t temp_is32=is32;
7124 for(j=i-1;j>=0;j--)
7125 {
7126 if(ba[j]==start+i*4)
7127 //temp_is32&=branch_regs[j].is32;
7128 temp_is32&=p32[j];
7129 }
7130 for(j=i;j<slen;j++)
7131 {
7132 if(ba[j]==start+i*4)
7133 temp_is32=1;
7134 }
7135 is32=temp_is32;
7136 }
7137 int type=itype[i];
7138 int op=opcode[i];
7139 int op2=opcode2[i];
7140 int rt=rt1[i];
7141 int s1=rs1[i];
7142 int s2=rs2[i];
7143 if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
7144 // Branches don't write registers, consider the delay slot instead.
7145 type=itype[i+1];
7146 op=opcode[i+1];
7147 op2=opcode2[i+1];
7148 rt=rt1[i+1];
7149 s1=rs1[i+1];
7150 s2=rs2[i+1];
7151 lastbranch=is32;
7152 }
7153 switch(type) {
7154 case LOAD:
7155 if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
7156 opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
7157 is32&=~(1LL<<rt);
7158 else
7159 is32|=1LL<<rt;
7160 break;
7161 case STORE:
7162 case STORELR:
7163 break;
7164 case LOADLR:
7165 if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
7166 if(op==0x22) is32|=1LL<<rt; // LWL
7167 break;
7168 case IMM16:
7169 if (op==0x08||op==0x09|| // ADDI/ADDIU
7170 op==0x0a||op==0x0b|| // SLTI/SLTIU
7171 op==0x0c|| // ANDI
7172 op==0x0f) // LUI
7173 {
7174 is32|=1LL<<rt;
7175 }
7176 if(op==0x18||op==0x19) { // DADDI/DADDIU
7177 is32&=~(1LL<<rt);
7178 //if(imm[i]==0)
7179 // is32|=((is32>>s1)&1LL)<<rt;
7180 }
7181 if(op==0x0d||op==0x0e) { // ORI/XORI
7182 uint64_t sr=((is32>>s1)&1LL);
7183 is32&=~(1LL<<rt);
7184 is32|=sr<<rt;
7185 }
7186 break;
7187 case UJUMP:
7188 break;
7189 case RJUMP:
7190 break;
7191 case CJUMP:
7192 break;
7193 case SJUMP:
7194 break;
7195 case FJUMP:
7196 break;
7197 case ALU:
7198 if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
7199 is32|=1LL<<rt;
7200 }
7201 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
7202 is32|=1LL<<rt;
7203 }
7204 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
7205 uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
7206 is32&=~(1LL<<rt);
7207 is32|=sr<<rt;
7208 }
7209 else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
7210 if(s1==0&&s2==0) {
7211 is32|=1LL<<rt;
7212 }
7213 else if(s2==0) {
7214 uint64_t sr=((is32>>s1)&1LL);
7215 is32&=~(1LL<<rt);
7216 is32|=sr<<rt;
7217 }
7218 else if(s1==0) {
7219 uint64_t sr=((is32>>s2)&1LL);
7220 is32&=~(1LL<<rt);
7221 is32|=sr<<rt;
7222 }
7223 else {
7224 is32&=~(1LL<<rt);
7225 }
7226 }
7227 else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
7228 if(s1==0&&s2==0) {
7229 is32|=1LL<<rt;
7230 }
7231 else if(s2==0) {
7232 uint64_t sr=((is32>>s1)&1LL);
7233 is32&=~(1LL<<rt);
7234 is32|=sr<<rt;
7235 }
7236 else {
7237 is32&=~(1LL<<rt);
7238 }
7239 }
7240 break;
7241 case MULTDIV:
7242 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
7243 is32&=~((1LL<<HIREG)|(1LL<<LOREG));
7244 }
7245 else {
7246 is32|=(1LL<<HIREG)|(1LL<<LOREG);
7247 }
7248 break;
7249 case MOV:
7250 {
7251 uint64_t sr=((is32>>s1)&1LL);
7252 is32&=~(1LL<<rt);
7253 is32|=sr<<rt;
7254 }
7255 break;
7256 case SHIFT:
7257 if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
7258 else is32|=1LL<<rt; // SLLV/SRLV/SRAV
7259 break;
7260 case SHIFTIMM:
7261 is32|=1LL<<rt;
7262 // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
7263 if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
7264 break;
7265 case COP0:
7266 if(op2==0) is32|=1LL<<rt; // MFC0
7267 break;
7268 case COP1:
b9b61529 7269 case COP2:
57871462 7270 if(op2==0) is32|=1LL<<rt; // MFC1
7271 if(op2==1) is32&=~(1LL<<rt); // DMFC1
7272 if(op2==2) is32|=1LL<<rt; // CFC1
7273 break;
7274 case C1LS:
b9b61529 7275 case C2LS:
57871462 7276 break;
7277 case FLOAT:
7278 case FCONV:
7279 break;
7280 case FCOMP:
7281 break;
b9b61529 7282 case C2OP:
57871462 7283 case SYSCALL:
7139f3c8 7284 case HLECALL:
57871462 7285 break;
7286 default:
7287 break;
7288 }
7289 is32|=1;
7290 p32[i]=is32;
7291
7292 if(i>0)
7293 {
7294 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
7295 {
7296 if(rt1[i-1]==31) // JAL/JALR
7297 {
7298 // Subroutine call will return here, don't alloc any registers
7299 is32=1;
7300 }
7301 else if(i+1<slen)
7302 {
7303 // Internal branch will jump here, match registers to caller
7304 is32=0x3FFFFFFFFLL;
7305 }
7306 }
7307 }
7308 }
7309}
7310
7311// Identify registers which may be assumed to contain 32-bit values
7312// and where optimizations will rely on this.
7313// This is used to determine whether backward branches can safely
7314// jump to a location with 64-bit values in registers.
7315static void provisional_r32()
7316{
7317 u_int r32=0;
7318 int i;
7319
7320 for (i=slen-1;i>=0;i--)
7321 {
7322 int hr;
7323 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7324 {
7325 if(ba[i]<start || ba[i]>=(start+slen*4))
7326 {
7327 // Branch out of this block, don't need anything
7328 r32=0;
7329 }
7330 else
7331 {
7332 // Internal branch
7333 // Need whatever matches the target
7334 // (and doesn't get overwritten by the delay slot instruction)
7335 r32=0;
7336 int t=(ba[i]-start)>>2;
7337 if(ba[i]>start+i*4) {
7338 // Forward branch
7339 //if(!(requires_32bit[t]&~regs[i].was32))
7340 // r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7341 if(!(pr32[t]&~regs[i].was32))
7342 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7343 }else{
7344 // Backward branch
7345 if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
7346 r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7347 }
7348 }
7349 // Conditional branch may need registers for following instructions
7350 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7351 {
7352 if(i<slen-2) {
7353 //r32|=requires_32bit[i+2];
7354 r32|=pr32[i+2];
7355 r32&=regs[i].was32;
7356 // Mark this address as a branch target since it may be called
7357 // upon return from interrupt
7358 //bt[i+2]=1;
7359 }
7360 }
7361 // Merge in delay slot
7362 if(!likely[i]) {
7363 // These are overwritten unless the branch is "likely"
7364 // and the delay slot is nullified if not taken
7365 r32&=~(1LL<<rt1[i+1]);
7366 r32&=~(1LL<<rt2[i+1]);
7367 }
7368 // Assume these are needed (delay slot)
7369 if(us1[i+1]>0)
7370 {
7371 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7372 }
7373 if(us2[i+1]>0)
7374 {
7375 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7376 }
7377 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7378 {
7379 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7380 }
7381 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7382 {
7383 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7384 }
7385 }
1e973cb0 7386 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 7387 {
7388 // SYSCALL instruction (software interrupt)
7389 r32=0;
7390 }
7391 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7392 {
7393 // ERET instruction (return from interrupt)
7394 r32=0;
7395 }
7396 // Check 32 bits
7397 r32&=~(1LL<<rt1[i]);
7398 r32&=~(1LL<<rt2[i]);
7399 if(us1[i]>0)
7400 {
7401 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7402 }
7403 if(us2[i]>0)
7404 {
7405 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7406 }
7407 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7408 {
7409 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7410 }
7411 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7412 {
7413 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7414 }
7415 //requires_32bit[i]=r32;
7416 pr32[i]=r32;
7417
7418 // Dirty registers which are 32-bit, require 32-bit input
7419 // as they will be written as 32-bit values
7420 for(hr=0;hr<HOST_REGS;hr++)
7421 {
7422 if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
7423 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7424 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7425 pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7426 //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7427 }
7428 }
7429 }
7430 }
7431}
7432
7433// Write back dirty registers as soon as we will no longer modify them,
7434// so that we don't end up with lots of writes at the branches.
7435void clean_registers(int istart,int iend,int wr)
7436{
7437 int i;
7438 int r;
7439 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7440 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7441 if(iend==slen-1) {
7442 will_dirty_i=will_dirty_next=0;
7443 wont_dirty_i=wont_dirty_next=0;
7444 }else{
7445 will_dirty_i=will_dirty_next=will_dirty[iend+1];
7446 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7447 }
7448 for (i=iend;i>=istart;i--)
7449 {
7450 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7451 {
7452 if(ba[i]<start || ba[i]>=(start+slen*4))
7453 {
7454 // Branch out of this block, flush all regs
7455 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7456 {
7457 // Unconditional branch
7458 will_dirty_i=0;
7459 wont_dirty_i=0;
7460 // Merge in delay slot (will dirty)
7461 for(r=0;r<HOST_REGS;r++) {
7462 if(r!=EXCLUDE_REG) {
7463 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7464 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7465 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7466 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7467 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7468 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7469 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7470 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7471 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7472 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7473 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7474 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7475 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7476 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7477 }
7478 }
7479 }
7480 else
7481 {
7482 // Conditional branch
7483 will_dirty_i=0;
7484 wont_dirty_i=wont_dirty_next;
7485 // Merge in delay slot (will dirty)
7486 for(r=0;r<HOST_REGS;r++) {
7487 if(r!=EXCLUDE_REG) {
7488 if(!likely[i]) {
7489 // Might not dirty if likely branch is not taken
7490 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7491 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7492 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7493 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7494 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7495 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7496 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7497 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7498 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7499 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7500 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7501 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7502 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7503 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7504 }
7505 }
7506 }
7507 }
7508 // Merge in delay slot (wont dirty)
7509 for(r=0;r<HOST_REGS;r++) {
7510 if(r!=EXCLUDE_REG) {
7511 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7512 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7513 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7514 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7515 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7516 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7517 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7518 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7519 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7520 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7521 }
7522 }
7523 if(wr) {
7524 #ifndef DESTRUCTIVE_WRITEBACK
7525 branch_regs[i].dirty&=wont_dirty_i;
7526 #endif
7527 branch_regs[i].dirty|=will_dirty_i;
7528 }
7529 }
7530 else
7531 {
7532 // Internal branch
7533 if(ba[i]<=start+i*4) {
7534 // Backward branch
7535 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7536 {
7537 // Unconditional branch
7538 temp_will_dirty=0;
7539 temp_wont_dirty=0;
7540 // Merge in delay slot (will dirty)
7541 for(r=0;r<HOST_REGS;r++) {
7542 if(r!=EXCLUDE_REG) {
7543 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7544 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7545 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7546 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7547 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7548 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7549 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7550 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7551 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7552 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7553 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7554 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7555 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7556 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7557 }
7558 }
7559 } else {
7560 // Conditional branch (not taken case)
7561 temp_will_dirty=will_dirty_next;
7562 temp_wont_dirty=wont_dirty_next;
7563 // Merge in delay slot (will dirty)
7564 for(r=0;r<HOST_REGS;r++) {
7565 if(r!=EXCLUDE_REG) {
7566 if(!likely[i]) {
7567 // Will not dirty if likely branch is not taken
7568 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7569 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7570 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7571 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7572 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7573 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7574 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7575 //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7576 //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7577 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7578 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7579 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7580 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7581 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7582 }
7583 }
7584 }
7585 }
7586 // Merge in delay slot (wont dirty)
7587 for(r=0;r<HOST_REGS;r++) {
7588 if(r!=EXCLUDE_REG) {
7589 if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7590 if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7591 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7592 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7593 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7594 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7595 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7596 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7597 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7598 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7599 }
7600 }
7601 // Deal with changed mappings
7602 if(i<iend) {
7603 for(r=0;r<HOST_REGS;r++) {
7604 if(r!=EXCLUDE_REG) {
7605 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7606 temp_will_dirty&=~(1<<r);
7607 temp_wont_dirty&=~(1<<r);
7608 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7609 temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7610 temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7611 } else {
7612 temp_will_dirty|=1<<r;
7613 temp_wont_dirty|=1<<r;
7614 }
7615 }
7616 }
7617 }
7618 }
7619 if(wr) {
7620 will_dirty[i]=temp_will_dirty;
7621 wont_dirty[i]=temp_wont_dirty;
7622 clean_registers((ba[i]-start)>>2,i-1,0);
7623 }else{
7624 // Limit recursion. It can take an excessive amount
7625 // of time if there are a lot of nested loops.
7626 will_dirty[(ba[i]-start)>>2]=0;
7627 wont_dirty[(ba[i]-start)>>2]=-1;
7628 }
7629 }
7630 /*else*/ if(1)
7631 {
7632 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7633 {
7634 // Unconditional branch
7635 will_dirty_i=0;
7636 wont_dirty_i=0;
7637 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7638 for(r=0;r<HOST_REGS;r++) {
7639 if(r!=EXCLUDE_REG) {
7640 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7641 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7642 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7643 }
e3234ecf 7644 if(branch_regs[i].regmap[r]>=0) {
7645 will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7646 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7647 }
57871462 7648 }
7649 }
7650 //}
7651 // Merge in delay slot
7652 for(r=0;r<HOST_REGS;r++) {
7653 if(r!=EXCLUDE_REG) {
7654 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7655 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7656 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7657 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7658 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7659 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7660 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7661 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7662 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7663 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7664 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7665 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7666 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7667 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7668 }
7669 }
7670 } else {
7671 // Conditional branch
7672 will_dirty_i=will_dirty_next;
7673 wont_dirty_i=wont_dirty_next;
7674 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7675 for(r=0;r<HOST_REGS;r++) {
7676 if(r!=EXCLUDE_REG) {
e3234ecf 7677 signed char target_reg=branch_regs[i].regmap[r];
7678 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
57871462 7679 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7680 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7681 }
e3234ecf 7682 else if(target_reg>=0) {
7683 will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7684 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
57871462 7685 }
7686 // Treat delay slot as part of branch too
7687 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7688 will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7689 wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7690 }
7691 else
7692 {
7693 will_dirty[i+1]&=~(1<<r);
7694 }*/
7695 }
7696 }
7697 //}
7698 // Merge in delay slot
7699 for(r=0;r<HOST_REGS;r++) {
7700 if(r!=EXCLUDE_REG) {
7701 if(!likely[i]) {
7702 // Might not dirty if likely branch is not taken
7703 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7704 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7705 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7706 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7707 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7708 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7709 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7710 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7711 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7712 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7713 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7714 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7715 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7716 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7717 }
7718 }
7719 }
7720 }
e3234ecf 7721 // Merge in delay slot (won't dirty)
57871462 7722 for(r=0;r<HOST_REGS;r++) {
7723 if(r!=EXCLUDE_REG) {
7724 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7725 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7726 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7727 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7728 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7729 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7730 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7731 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7732 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7733 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7734 }
7735 }
7736 if(wr) {
7737 #ifndef DESTRUCTIVE_WRITEBACK
7738 branch_regs[i].dirty&=wont_dirty_i;
7739 #endif
7740 branch_regs[i].dirty|=will_dirty_i;
7741 }
7742 }
7743 }
7744 }
1e973cb0 7745 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 7746 {
7747 // SYSCALL instruction (software interrupt)
7748 will_dirty_i=0;
7749 wont_dirty_i=0;
7750 }
7751 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7752 {
7753 // ERET instruction (return from interrupt)
7754 will_dirty_i=0;
7755 wont_dirty_i=0;
7756 }
7757 will_dirty_next=will_dirty_i;
7758 wont_dirty_next=wont_dirty_i;
7759 for(r=0;r<HOST_REGS;r++) {
7760 if(r!=EXCLUDE_REG) {
7761 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7762 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7763 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7764 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7765 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7766 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7767 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7768 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7769 if(i>istart) {
7770 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7771 {
7772 // Don't store a register immediately after writing it,
7773 // may prevent dual-issue.
7774 if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7775 if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7776 }
7777 }
7778 }
7779 }
7780 // Save it
7781 will_dirty[i]=will_dirty_i;
7782 wont_dirty[i]=wont_dirty_i;
7783 // Mark registers that won't be dirtied as not dirty
7784 if(wr) {
7785 /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7786 for(r=0;r<HOST_REGS;r++) {
7787 if((will_dirty_i>>r)&1) {
7788 printf(" r%d",r);
7789 }
7790 }
7791 printf("\n");*/
7792
7793 //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7794 regs[i].dirty|=will_dirty_i;
7795 #ifndef DESTRUCTIVE_WRITEBACK
7796 regs[i].dirty&=wont_dirty_i;
7797 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7798 {
7799 if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7800 for(r=0;r<HOST_REGS;r++) {
7801 if(r!=EXCLUDE_REG) {
7802 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7803 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7804 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7805 }
7806 }
7807 }
7808 }
7809 else
7810 {
7811 if(i<iend) {
7812 for(r=0;r<HOST_REGS;r++) {
7813 if(r!=EXCLUDE_REG) {
7814 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7815 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7816 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7817 }
7818 }
7819 }
7820 }
7821 #endif
7822 //}
7823 }
7824 // Deal with changed mappings
7825 temp_will_dirty=will_dirty_i;
7826 temp_wont_dirty=wont_dirty_i;
7827 for(r=0;r<HOST_REGS;r++) {
7828 if(r!=EXCLUDE_REG) {
7829 int nr;
7830 if(regs[i].regmap[r]==regmap_pre[i][r]) {
7831 if(wr) {
7832 #ifndef DESTRUCTIVE_WRITEBACK
7833 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7834 #endif
7835 regs[i].wasdirty|=will_dirty_i&(1<<r);
7836 }
7837 }
f776eb14 7838 else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
57871462 7839 // Register moved to a different register
7840 will_dirty_i&=~(1<<r);
7841 wont_dirty_i&=~(1<<r);
7842 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7843 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7844 if(wr) {
7845 #ifndef DESTRUCTIVE_WRITEBACK
7846 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7847 #endif
7848 regs[i].wasdirty|=will_dirty_i&(1<<r);
7849 }
7850 }
7851 else {
7852 will_dirty_i&=~(1<<r);
7853 wont_dirty_i&=~(1<<r);
7854 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7855 will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7856 wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7857 } else {
7858 wont_dirty_i|=1<<r;
7859 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7860 }
7861 }
7862 }
7863 }
7864 }
7865}
7866
4600ba03 7867#ifdef DISASM
57871462 7868 /* disassembly */
7869void disassemble_inst(int i)
7870{
7871 if (bt[i]) printf("*"); else printf(" ");
7872 switch(itype[i]) {
7873 case UJUMP:
7874 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7875 case CJUMP:
7876 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7877 case SJUMP:
7878 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7879 case FJUMP:
7880 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7881 case RJUMP:
74426039 7882 if (opcode[i]==0x9&&rt1[i]!=31)
5067f341 7883 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7884 else
7885 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7886 break;
57871462 7887 case SPAN:
7888 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7889 case IMM16:
7890 if(opcode[i]==0xf) //LUI
7891 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7892 else
7893 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7894 break;
7895 case LOAD:
7896 case LOADLR:
7897 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7898 break;
7899 case STORE:
7900 case STORELR:
7901 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7902 break;
7903 case ALU:
7904 case SHIFT:
7905 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7906 break;
7907 case MULTDIV:
7908 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7909 break;
7910 case SHIFTIMM:
7911 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7912 break;
7913 case MOV:
7914 if((opcode2[i]&0x1d)==0x10)
7915 printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7916 else if((opcode2[i]&0x1d)==0x11)
7917 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7918 else
7919 printf (" %x: %s\n",start+i*4,insn[i]);
7920 break;
7921 case COP0:
7922 if(opcode2[i]==0)
7923 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7924 else if(opcode2[i]==4)
7925 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7926 else printf (" %x: %s\n",start+i*4,insn[i]);
7927 break;
7928 case COP1:
7929 if(opcode2[i]<3)
7930 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7931 else if(opcode2[i]>3)
7932 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7933 else printf (" %x: %s\n",start+i*4,insn[i]);
7934 break;
b9b61529 7935 case COP2:
7936 if(opcode2[i]<3)
7937 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7938 else if(opcode2[i]>3)
7939 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7940 else printf (" %x: %s\n",start+i*4,insn[i]);
7941 break;
57871462 7942 case C1LS:
7943 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7944 break;
b9b61529 7945 case C2LS:
7946 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7947 break;
1e973cb0 7948 case INTCALL:
7949 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
7950 break;
57871462 7951 default:
7952 //printf (" %s %8x\n",insn[i],source[i]);
7953 printf (" %x: %s\n",start+i*4,insn[i]);
7954 }
7955}
4600ba03 7956#else
7957static void disassemble_inst(int i) {}
7958#endif // DISASM
57871462 7959
dc990066 7960// clear the state completely, instead of just marking
7961// things invalid like invalidate_all_pages() does
7962void new_dynarec_clear_full()
57871462 7963{
57871462 7964 int n;
35775df7 7965 out=(u_char *)BASE_ADDR;
7966 memset(invalid_code,1,sizeof(invalid_code));
7967 memset(hash_table,0xff,sizeof(hash_table));
57871462 7968 memset(mini_ht,-1,sizeof(mini_ht));
7969 memset(restore_candidate,0,sizeof(restore_candidate));
dc990066 7970 memset(shadow,0,sizeof(shadow));
57871462 7971 copy=shadow;
7972 expirep=16384; // Expiry pointer, +2 blocks
7973 pending_exception=0;
7974 literalcount=0;
57871462 7975 stop_after_jal=0;
9be4ba64 7976 inv_code_start=inv_code_end=~0;
57871462 7977 // TLB
af4ee1fe 7978#ifndef DISABLE_TLB
57871462 7979 using_tlb=0;
7980 for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7981 memory_map[n]=-1;
7982 for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7983 memory_map[n]=((u_int)rdram-0x80000000)>>2;
7984 for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7985 memory_map[n]=-1;
63cb0298 7986#endif
dc990066 7987 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7988 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7989 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7990}
7991
7992void new_dynarec_init()
7993{
7994 printf("Init new dynarec\n");
7995 out=(u_char *)BASE_ADDR;
7996 if (mmap (out, 1<<TARGET_SIZE_2,
7997 PROT_READ | PROT_WRITE | PROT_EXEC,
7998 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
7999 -1, 0) <= 0) {printf("mmap() failed\n");}
8000#ifdef MUPEN64
8001 rdword=&readmem_dword;
8002 fake_pc.f.r.rs=&readmem_dword;
8003 fake_pc.f.r.rt=&readmem_dword;
8004 fake_pc.f.r.rd=&readmem_dword;
8005#endif
8006 int n;
2573466a 8007 cycle_multiplier=200;
dc990066 8008 new_dynarec_clear_full();
8009#ifdef HOST_IMM8
8010 // Copy this into local area so we don't have to put it in every literal pool
8011 invc_ptr=invalid_code;
8012#endif
24385cae 8013#ifdef MUPEN64
57871462 8014 for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
8015 writemem[n] = write_nomem_new;
8016 writememb[n] = write_nomemb_new;
8017 writememh[n] = write_nomemh_new;
24385cae 8018#ifndef FORCE32
57871462 8019 writememd[n] = write_nomemd_new;
24385cae 8020#endif
57871462 8021 readmem[n] = read_nomem_new;
8022 readmemb[n] = read_nomemb_new;
8023 readmemh[n] = read_nomemh_new;
24385cae 8024#ifndef FORCE32
57871462 8025 readmemd[n] = read_nomemd_new;
24385cae 8026#endif
57871462 8027 }
8028 for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
8029 writemem[n] = write_rdram_new;
8030 writememb[n] = write_rdramb_new;
8031 writememh[n] = write_rdramh_new;
24385cae 8032#ifndef FORCE32
57871462 8033 writememd[n] = write_rdramd_new;
24385cae 8034#endif
57871462 8035 }
8036 for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
8037 writemem[n] = write_nomem_new;
8038 writememb[n] = write_nomemb_new;
8039 writememh[n] = write_nomemh_new;
24385cae 8040#ifndef FORCE32
57871462 8041 writememd[n] = write_nomemd_new;
24385cae 8042#endif
57871462 8043 readmem[n] = read_nomem_new;
8044 readmemb[n] = read_nomemb_new;
8045 readmemh[n] = read_nomemh_new;
24385cae 8046#ifndef FORCE32
57871462 8047 readmemd[n] = read_nomemd_new;
24385cae 8048#endif
57871462 8049 }
24385cae 8050#endif
57871462 8051 tlb_hacks();
8052 arch_init();
8053}
8054
8055void new_dynarec_cleanup()
8056{
8057 int n;
8058 if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
8059 for(n=0;n<4096;n++) ll_clear(jump_in+n);
8060 for(n=0;n<4096;n++) ll_clear(jump_out+n);
8061 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
8062 #ifdef ROM_COPY
8063 if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
8064 #endif
8065}
8066
8067int new_recompile_block(int addr)
8068{
8069/*
8070 if(addr==0x800cd050) {
8071 int block;
8072 for(block=0x80000;block<0x80800;block++) invalidate_block(block);
8073 int n;
8074 for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
8075 }
8076*/
8077 //if(Count==365117028) tracedebug=1;
8078 assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
8079 //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
8080 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
8081 //if(debug)
8082 //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
8083 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
8084 /*if(Count>=312978186) {
8085 rlist();
8086 }*/
8087 //rlist();
8088 start = (u_int)addr&~3;
8089 //assert(((u_int)addr&1)==0);
2f546f9a 8090 new_dynarec_did_compile=1;
7139f3c8 8091#ifdef PCSX
9ad4d757 8092 if (Config.HLE && start == 0x80001000) // hlecall
560e4a12 8093 {
7139f3c8 8094 // XXX: is this enough? Maybe check hleSoftCall?
bb5285ef 8095 u_int beginning=(u_int)out;
7139f3c8 8096 u_int page=get_page(start);
7139f3c8 8097 invalid_code[start>>12]=0;
8098 emit_movimm(start,0);
8099 emit_writeword(0,(int)&pcaddr);
bb5285ef 8100 emit_jmp((int)new_dyna_leave);
15776b68 8101 literal_pool(0);
bb5285ef 8102#ifdef __arm__
8103 __clear_cache((void *)beginning,out);
8104#endif
9ad4d757 8105 ll_add(jump_in+page,start,(void *)beginning);
7139f3c8 8106 return 0;
8107 }
560e4a12 8108 else if ((u_int)addr < 0x00200000 ||
8109 (0xa0000000 <= addr && addr < 0xa0200000)) {
7139f3c8 8110 // used for BIOS calls mostly?
560e4a12 8111 source = (u_int *)((u_int)rdram+(start&0x1fffff));
8112 pagelimit = (addr&0xa0000000)|0x00200000;
8113 }
8114 else if (!Config.HLE && (
8115/* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
8116 (0xbfc00000 <= addr && addr < 0xbfc80000))) {
8117 // BIOS
8118 source = (u_int *)((u_int)psxR+(start&0x7ffff));
8119 pagelimit = (addr&0xfff00000)|0x80000;
7139f3c8 8120 }
8121 else
8122#endif
3d624f89 8123#ifdef MUPEN64
57871462 8124 if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
8125 source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
8126 pagelimit = 0xa4001000;
8127 }
3d624f89 8128 else
8129#endif
4cb76aa4 8130 if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
57871462 8131 source = (u_int *)((u_int)rdram+start-0x80000000);
4cb76aa4 8132 pagelimit = 0x80000000+RAM_SIZE;
57871462 8133 }
90ae6d4e 8134#ifndef DISABLE_TLB
57871462 8135 else if ((signed int)addr >= (signed int)0xC0000000) {
8136 //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
8137 //if(tlb_LUT_r[start>>12])
8138 //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
8139 if((signed int)memory_map[start>>12]>=0) {
8140 source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
8141 pagelimit=(start+4096)&0xFFFFF000;
8142 int map=memory_map[start>>12];
8143 int i;
8144 for(i=0;i<5;i++) {
8145 //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
8146 if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
8147 }
8148 assem_debug("pagelimit=%x\n",pagelimit);
8149 assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
8150 }
8151 else {
8152 assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
8153 //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
560e4a12 8154 return -1; // Caller will invoke exception handler
57871462 8155 }
8156 //printf("source= %x\n",(int)source);
8157 }
90ae6d4e 8158#endif
57871462 8159 else {
8160 printf("Compile at bogus memory address: %x \n", (int)addr);
8161 exit(1);
8162 }
8163
8164 /* Pass 1: disassemble */
8165 /* Pass 2: register dependencies, branch targets */
8166 /* Pass 3: register allocation */
8167 /* Pass 4: branch dependencies */
8168 /* Pass 5: pre-alloc */
8169 /* Pass 6: optimize clean/dirty state */
8170 /* Pass 7: flag 32-bit registers */
8171 /* Pass 8: assembly */
8172 /* Pass 9: linker */
8173 /* Pass 10: garbage collection / free memory */
8174
8175 int i,j;
8176 int done=0;
8177 unsigned int type,op,op2;
8178
8179 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
8180
8181 /* Pass 1 disassembly */
8182
8183 for(i=0;!done;i++) {
e1190b87 8184 bt[i]=0;likely[i]=0;ooo[i]=0;op2=0;
8185 minimum_free_regs[i]=0;
57871462 8186 opcode[i]=op=source[i]>>26;
8187 switch(op)
8188 {
8189 case 0x00: strcpy(insn[i],"special"); type=NI;
8190 op2=source[i]&0x3f;
8191 switch(op2)
8192 {
8193 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
8194 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
8195 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
8196 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
8197 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
8198 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
8199 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
8200 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
8201 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
8202 case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
8203 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
8204 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
8205 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
8206 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
8207 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
57871462 8208 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
8209 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
8210 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
8211 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
57871462 8212 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
8213 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
8214 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
8215 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
8216 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
8217 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
8218 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
8219 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
8220 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
8221 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
57871462 8222 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
8223 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
8224 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
8225 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
8226 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
8227 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
7f2607ea 8228#ifndef FORCE32
8229 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
8230 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
8231 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
8232 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
8233 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
8234 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
8235 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
8236 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
8237 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
8238 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
8239 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
57871462 8240 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
8241 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
8242 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
8243 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
8244 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
8245 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
7f2607ea 8246#endif
57871462 8247 }
8248 break;
8249 case 0x01: strcpy(insn[i],"regimm"); type=NI;
8250 op2=(source[i]>>16)&0x1f;
8251 switch(op2)
8252 {
8253 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
8254 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
8255 case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
8256 case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
8257 case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
8258 case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
8259 case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
8260 case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
8261 case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
8262 case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
8263 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
8264 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
8265 case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
8266 case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
8267 }
8268 break;
8269 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
8270 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
8271 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
8272 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
8273 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
8274 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
8275 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
8276 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
8277 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
8278 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
8279 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
8280 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
8281 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
8282 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
8283 case 0x10: strcpy(insn[i],"cop0"); type=NI;
8284 op2=(source[i]>>21)&0x1f;
8285 switch(op2)
8286 {
8287 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
8288 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
8289 case 0x10: strcpy(insn[i],"tlb"); type=NI;
8290 switch(source[i]&0x3f)
8291 {
8292 case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
8293 case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
8294 case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
8295 case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
576bbd8f 8296#ifdef PCSX
8297 case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
8298#else
57871462 8299 case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
576bbd8f 8300#endif
57871462 8301 }
8302 }
8303 break;
8304 case 0x11: strcpy(insn[i],"cop1"); type=NI;
8305 op2=(source[i]>>21)&0x1f;
8306 switch(op2)
8307 {
8308 case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
8309 case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
8310 case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
8311 case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
8312 case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
8313 case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
8314 case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
8315 switch((source[i]>>16)&0x3)
8316 {
8317 case 0x00: strcpy(insn[i],"BC1F"); break;
8318 case 0x01: strcpy(insn[i],"BC1T"); break;
8319 case 0x02: strcpy(insn[i],"BC1FL"); break;
8320 case 0x03: strcpy(insn[i],"BC1TL"); break;
8321 }
8322 break;
8323 case 0x10: strcpy(insn[i],"C1.S"); type=NI;
8324 switch(source[i]&0x3f)
8325 {
8326 case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
8327 case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
8328 case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
8329 case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
8330 case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
8331 case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
8332 case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
8333 case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
8334 case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
8335 case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
8336 case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
8337 case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
8338 case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
8339 case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
8340 case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
8341 case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
8342 case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
8343 case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
8344 case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
8345 case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
8346 case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
8347 case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
8348 case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
8349 case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
8350 case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
8351 case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
8352 case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
8353 case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
8354 case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
8355 case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
8356 case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
8357 case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
8358 case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
8359 case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
8360 case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
8361 }
8362 break;
8363 case 0x11: strcpy(insn[i],"C1.D"); type=NI;
8364 switch(source[i]&0x3f)
8365 {
8366 case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
8367 case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
8368 case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
8369 case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
8370 case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
8371 case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
8372 case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
8373 case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
8374 case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
8375 case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
8376 case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
8377 case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
8378 case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
8379 case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
8380 case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
8381 case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
8382 case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
8383 case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
8384 case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
8385 case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
8386 case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
8387 case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
8388 case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
8389 case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
8390 case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
8391 case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
8392 case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
8393 case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
8394 case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
8395 case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
8396 case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8397 case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8398 case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8399 case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8400 case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8401 }
8402 break;
8403 case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8404 switch(source[i]&0x3f)
8405 {
8406 case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8407 case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8408 }
8409 break;
8410 case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8411 switch(source[i]&0x3f)
8412 {
8413 case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8414 case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8415 }
8416 break;
8417 }
8418 break;
909168d6 8419#ifndef FORCE32
57871462 8420 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8421 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8422 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8423 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8424 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8425 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8426 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8427 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
996cc15d 8428#endif
57871462 8429 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8430 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8431 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8432 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8433 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8434 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8435 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
64bd6f82 8436#ifndef FORCE32
57871462 8437 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
64bd6f82 8438#endif
57871462 8439 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8440 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8441 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8442 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
996cc15d 8443#ifndef FORCE32
57871462 8444 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8445 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
996cc15d 8446#endif
57871462 8447 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8448 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8449 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8450 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
996cc15d 8451#ifndef FORCE32
57871462 8452 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8453 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8454 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
996cc15d 8455#endif
57871462 8456 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8457 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
996cc15d 8458#ifndef FORCE32
57871462 8459 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8460 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8461 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
996cc15d 8462#endif
b9b61529 8463#ifdef PCSX
8464 case 0x12: strcpy(insn[i],"COP2"); type=NI;
8465 op2=(source[i]>>21)&0x1f;
bedfea38 8466 //if (op2 & 0x10) {
8467 if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
c7abc864 8468 if (gte_handlers[source[i]&0x3f]!=NULL) {
bedfea38 8469 if (gte_regnames[source[i]&0x3f]!=NULL)
8470 strcpy(insn[i],gte_regnames[source[i]&0x3f]);
8471 else
8472 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
c7abc864 8473 type=C2OP;
8474 }
8475 }
8476 else switch(op2)
b9b61529 8477 {
8478 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8479 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8480 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8481 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
b9b61529 8482 }
8483 break;
8484 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8485 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8486 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8487#endif
90ae6d4e 8488 default: strcpy(insn[i],"???"); type=NI;
75dec299 8489 printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
90ae6d4e 8490 break;
57871462 8491 }
8492 itype[i]=type;
8493 opcode2[i]=op2;
8494 /* Get registers/immediates */
8495 lt1[i]=0;
8496 us1[i]=0;
8497 us2[i]=0;
8498 dep1[i]=0;
8499 dep2[i]=0;
bedfea38 8500 gte_rs[i]=gte_rt[i]=0;
57871462 8501 switch(type) {
8502 case LOAD:
8503 rs1[i]=(source[i]>>21)&0x1f;
8504 rs2[i]=0;
8505 rt1[i]=(source[i]>>16)&0x1f;
8506 rt2[i]=0;
8507 imm[i]=(short)source[i];
8508 break;
8509 case STORE:
8510 case STORELR:
8511 rs1[i]=(source[i]>>21)&0x1f;
8512 rs2[i]=(source[i]>>16)&0x1f;
8513 rt1[i]=0;
8514 rt2[i]=0;
8515 imm[i]=(short)source[i];
8516 if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8517 break;
8518 case LOADLR:
8519 // LWL/LWR only load part of the register,
8520 // therefore the target register must be treated as a source too
8521 rs1[i]=(source[i]>>21)&0x1f;
8522 rs2[i]=(source[i]>>16)&0x1f;
8523 rt1[i]=(source[i]>>16)&0x1f;
8524 rt2[i]=0;
8525 imm[i]=(short)source[i];
8526 if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8527 if(op==0x26) dep1[i]=rt1[i]; // LWR
8528 break;
8529 case IMM16:
8530 if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8531 else rs1[i]=(source[i]>>21)&0x1f;
8532 rs2[i]=0;
8533 rt1[i]=(source[i]>>16)&0x1f;
8534 rt2[i]=0;
8535 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8536 imm[i]=(unsigned short)source[i];
8537 }else{
8538 imm[i]=(short)source[i];
8539 }
8540 if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8541 if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8542 if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8543 break;
8544 case UJUMP:
8545 rs1[i]=0;
8546 rs2[i]=0;
8547 rt1[i]=0;
8548 rt2[i]=0;
8549 // The JAL instruction writes to r31.
8550 if (op&1) {
8551 rt1[i]=31;
8552 }
8553 rs2[i]=CCREG;
8554 break;
8555 case RJUMP:
8556 rs1[i]=(source[i]>>21)&0x1f;
8557 rs2[i]=0;
8558 rt1[i]=0;
8559 rt2[i]=0;
5067f341 8560 // The JALR instruction writes to rd.
57871462 8561 if (op2&1) {
5067f341 8562 rt1[i]=(source[i]>>11)&0x1f;
57871462 8563 }
8564 rs2[i]=CCREG;
8565 break;
8566 case CJUMP:
8567 rs1[i]=(source[i]>>21)&0x1f;
8568 rs2[i]=(source[i]>>16)&0x1f;
8569 rt1[i]=0;
8570 rt2[i]=0;
8571 if(op&2) { // BGTZ/BLEZ
8572 rs2[i]=0;
8573 }
8574 us1[i]=rs1[i];
8575 us2[i]=rs2[i];
8576 likely[i]=op>>4;
8577 break;
8578 case SJUMP:
8579 rs1[i]=(source[i]>>21)&0x1f;
8580 rs2[i]=CCREG;
8581 rt1[i]=0;
8582 rt2[i]=0;
8583 us1[i]=rs1[i];
8584 if(op2&0x10) { // BxxAL
8585 rt1[i]=31;
8586 // NOTE: If the branch is not taken, r31 is still overwritten
8587 }
8588 likely[i]=(op2&2)>>1;
8589 break;
8590 case FJUMP:
8591 rs1[i]=FSREG;
8592 rs2[i]=CSREG;
8593 rt1[i]=0;
8594 rt2[i]=0;
8595 likely[i]=((source[i])>>17)&1;
8596 break;
8597 case ALU:
8598 rs1[i]=(source[i]>>21)&0x1f; // source
8599 rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8600 rt1[i]=(source[i]>>11)&0x1f; // destination
8601 rt2[i]=0;
8602 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8603 us1[i]=rs1[i];us2[i]=rs2[i];
8604 }
8605 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8606 dep1[i]=rs1[i];dep2[i]=rs2[i];
8607 }
8608 else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8609 dep1[i]=rs1[i];dep2[i]=rs2[i];
8610 }
8611 break;
8612 case MULTDIV:
8613 rs1[i]=(source[i]>>21)&0x1f; // source
8614 rs2[i]=(source[i]>>16)&0x1f; // divisor
8615 rt1[i]=HIREG;
8616 rt2[i]=LOREG;
8617 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8618 us1[i]=rs1[i];us2[i]=rs2[i];
8619 }
8620 break;
8621 case MOV:
8622 rs1[i]=0;
8623 rs2[i]=0;
8624 rt1[i]=0;
8625 rt2[i]=0;
8626 if(op2==0x10) rs1[i]=HIREG; // MFHI
8627 if(op2==0x11) rt1[i]=HIREG; // MTHI
8628 if(op2==0x12) rs1[i]=LOREG; // MFLO
8629 if(op2==0x13) rt1[i]=LOREG; // MTLO
8630 if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8631 if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8632 dep1[i]=rs1[i];
8633 break;
8634 case SHIFT:
8635 rs1[i]=(source[i]>>16)&0x1f; // target of shift
8636 rs2[i]=(source[i]>>21)&0x1f; // shift amount
8637 rt1[i]=(source[i]>>11)&0x1f; // destination
8638 rt2[i]=0;
8639 // DSLLV/DSRLV/DSRAV are 64-bit
8640 if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8641 break;
8642 case SHIFTIMM:
8643 rs1[i]=(source[i]>>16)&0x1f;
8644 rs2[i]=0;
8645 rt1[i]=(source[i]>>11)&0x1f;
8646 rt2[i]=0;
8647 imm[i]=(source[i]>>6)&0x1f;
8648 // DSxx32 instructions
8649 if(op2>=0x3c) imm[i]|=0x20;
8650 // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8651 if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8652 break;
8653 case COP0:
8654 rs1[i]=0;
8655 rs2[i]=0;
8656 rt1[i]=0;
8657 rt2[i]=0;
8658 if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8659 if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8660 if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8661 if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8662 break;
8663 case COP1:
8664 rs1[i]=0;
8665 rs2[i]=0;
8666 rt1[i]=0;
8667 rt2[i]=0;
8668 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8669 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8670 if(op2==5) us1[i]=rs1[i]; // DMTC1
8671 rs2[i]=CSREG;
8672 break;
bedfea38 8673 case COP2:
8674 rs1[i]=0;
8675 rs2[i]=0;
8676 rt1[i]=0;
8677 rt2[i]=0;
8678 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC2/CFC2
8679 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC2/CTC2
8680 rs2[i]=CSREG;
8681 int gr=(source[i]>>11)&0x1F;
8682 switch(op2)
8683 {
8684 case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
8685 case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
0ff8c62c 8686 case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2
bedfea38 8687 case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
8688 }
8689 break;
57871462 8690 case C1LS:
8691 rs1[i]=(source[i]>>21)&0x1F;
8692 rs2[i]=CSREG;
8693 rt1[i]=0;
8694 rt2[i]=0;
8695 imm[i]=(short)source[i];
8696 break;
b9b61529 8697 case C2LS:
8698 rs1[i]=(source[i]>>21)&0x1F;
8699 rs2[i]=0;
8700 rt1[i]=0;
8701 rt2[i]=0;
8702 imm[i]=(short)source[i];
bedfea38 8703 if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
8704 else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
8705 break;
8706 case C2OP:
8707 rs1[i]=0;
8708 rs2[i]=0;
8709 rt1[i]=0;
8710 rt2[i]=0;
2167bef6 8711 gte_rs[i]=gte_reg_reads[source[i]&0x3f];
8712 gte_rt[i]=gte_reg_writes[source[i]&0x3f];
8713 gte_rt[i]|=1ll<<63; // every op changes flags
587a5b1c 8714 if((source[i]&0x3f)==GTE_MVMVA) {
8715 int v = (source[i] >> 15) & 3;
8716 gte_rs[i]&=~0xe3fll;
8717 if(v==3) gte_rs[i]|=0xe00ll;
8718 else gte_rs[i]|=3ll<<(v*2);
8719 }
b9b61529 8720 break;
57871462 8721 case FLOAT:
8722 case FCONV:
8723 rs1[i]=0;
8724 rs2[i]=CSREG;
8725 rt1[i]=0;
8726 rt2[i]=0;
8727 break;
8728 case FCOMP:
8729 rs1[i]=FSREG;
8730 rs2[i]=CSREG;
8731 rt1[i]=FSREG;
8732 rt2[i]=0;
8733 break;
8734 case SYSCALL:
7139f3c8 8735 case HLECALL:
1e973cb0 8736 case INTCALL:
57871462 8737 rs1[i]=CCREG;
8738 rs2[i]=0;
8739 rt1[i]=0;
8740 rt2[i]=0;
8741 break;
8742 default:
8743 rs1[i]=0;
8744 rs2[i]=0;
8745 rt1[i]=0;
8746 rt2[i]=0;
8747 }
8748 /* Calculate branch target addresses */
8749 if(type==UJUMP)
8750 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8751 else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8752 ba[i]=start+i*4+8; // Ignore never taken branch
8753 else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8754 ba[i]=start+i*4+8; // Ignore never taken branch
8755 else if(type==CJUMP||type==SJUMP||type==FJUMP)
8756 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8757 else ba[i]=-1;
26869094 8758#ifdef PCSX
3e535354 8759 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
8760 int do_in_intrp=0;
8761 // branch in delay slot?
8762 if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
8763 // don't handle first branch and call interpreter if it's hit
8764 printf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
8765 do_in_intrp=1;
8766 }
8767 // basic load delay detection
8768 else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&rt1[i]!=0) {
8769 int t=(ba[i-1]-start)/4;
8770 if(0 <= t && t < i &&(rt1[i]==rs1[t]||rt1[i]==rs2[t])&&itype[t]!=CJUMP&&itype[t]!=SJUMP) {
8771 // jump target wants DS result - potential load delay effect
8772 printf("load delay @%08x (%08x)\n", addr + i*4, addr);
8773 do_in_intrp=1;
8774 bt[t+1]=1; // expected return from interpreter
8775 }
8776 else if(i>=2&&rt1[i-2]==2&&rt1[i]==2&&rs1[i]!=2&&rs2[i]!=2&&rs1[i-1]!=2&&rs2[i-1]!=2&&
8777 !(i>=3&&(itype[i-3]==RJUMP||itype[i-3]==UJUMP||itype[i-3]==CJUMP||itype[i-3]==SJUMP))) {
8778 // v0 overwrite like this is a sign of trouble, bail out
8779 printf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
8780 do_in_intrp=1;
8781 }
8782 }
3e535354 8783 if(do_in_intrp) {
8784 rs1[i-1]=CCREG;
8785 rs2[i-1]=rt1[i-1]=rt2[i-1]=0;
26869094 8786 ba[i-1]=-1;
8787 itype[i-1]=INTCALL;
8788 done=2;
3e535354 8789 i--; // don't compile the DS
26869094 8790 }
3e535354 8791 }
26869094 8792#endif
3e535354 8793 /* Is this the end of the block? */
8794 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
5067f341 8795 if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
1e973cb0 8796 done=2;
57871462 8797 }
8798 else {
8799 if(stop_after_jal) done=1;
8800 // Stop on BREAK
8801 if((source[i+1]&0xfc00003f)==0x0d) done=1;
8802 }
8803 // Don't recompile stuff that's already compiled
8804 if(check_addr(start+i*4+4)) done=1;
8805 // Don't get too close to the limit
8806 if(i>MAXBLOCK/2) done=1;
8807 }
75dec299 8808 if(itype[i]==SYSCALL&&stop_after_jal) done=1;
1e973cb0 8809 if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
8810 if(done==2) {
8811 // Does the block continue due to a branch?
8812 for(j=i-1;j>=0;j--)
8813 {
2a706964 8814 if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
1e973cb0 8815 if(ba[j]==start+i*4+4) done=j=0;
8816 if(ba[j]==start+i*4+8) done=j=0;
8817 }
8818 }
75dec299 8819 //assert(i<MAXBLOCK-1);
57871462 8820 if(start+i*4==pagelimit-4) done=1;
8821 assert(start+i*4<pagelimit);
8822 if (i==MAXBLOCK-1) done=1;
8823 // Stop if we're compiling junk
8824 if(itype[i]==NI&&opcode[i]==0x11) {
8825 done=stop_after_jal=1;
8826 printf("Disabled speculative precompilation\n");
8827 }
8828 }
8829 slen=i;
8830 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8831 if(start+i*4==pagelimit) {
8832 itype[i-1]=SPAN;
8833 }
8834 }
8835 assert(slen>0);
8836
8837 /* Pass 2 - Register dependencies and branch targets */
8838
8839 unneeded_registers(0,slen-1,0);
8840
8841 /* Pass 3 - Register allocation */
8842
8843 struct regstat current; // Current register allocations/status
8844 current.is32=1;
8845 current.dirty=0;
8846 current.u=unneeded_reg[0];
8847 current.uu=unneeded_reg_upper[0];
8848 clear_all_regs(current.regmap);
8849 alloc_reg(&current,0,CCREG);
8850 dirty_reg(&current,CCREG);
8851 current.isconst=0;
8852 current.wasconst=0;
27727b63 8853 current.waswritten=0;
57871462 8854 int ds=0;
8855 int cc=0;
5194fb95 8856 int hr=-1;
6ebf4adf 8857
8858#ifndef FORCE32
57871462 8859 provisional_32bit();
6ebf4adf 8860#endif
57871462 8861 if((u_int)addr&1) {
8862 // First instruction is delay slot
8863 cc=-1;
8864 bt[1]=1;
8865 ds=1;
8866 unneeded_reg[0]=1;
8867 unneeded_reg_upper[0]=1;
8868 current.regmap[HOST_BTREG]=BTREG;
8869 }
8870
8871 for(i=0;i<slen;i++)
8872 {
8873 if(bt[i])
8874 {
8875 int hr;
8876 for(hr=0;hr<HOST_REGS;hr++)
8877 {
8878 // Is this really necessary?
8879 if(current.regmap[hr]==0) current.regmap[hr]=-1;
8880 }
8881 current.isconst=0;
27727b63 8882 current.waswritten=0;
57871462 8883 }
8884 if(i>1)
8885 {
8886 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8887 {
8888 if(rs1[i-2]==0||rs2[i-2]==0)
8889 {
8890 if(rs1[i-2]) {
8891 current.is32|=1LL<<rs1[i-2];
8892 int hr=get_reg(current.regmap,rs1[i-2]|64);
8893 if(hr>=0) current.regmap[hr]=-1;
8894 }
8895 if(rs2[i-2]) {
8896 current.is32|=1LL<<rs2[i-2];
8897 int hr=get_reg(current.regmap,rs2[i-2]|64);
8898 if(hr>=0) current.regmap[hr]=-1;
8899 }
8900 }
8901 }
8902 }
6ebf4adf 8903#ifndef FORCE32
57871462 8904 // If something jumps here with 64-bit values
8905 // then promote those registers to 64 bits
8906 if(bt[i])
8907 {
8908 uint64_t temp_is32=current.is32;
8909 for(j=i-1;j>=0;j--)
8910 {
8911 if(ba[j]==start+i*4)
8912 temp_is32&=branch_regs[j].is32;
8913 }
8914 for(j=i;j<slen;j++)
8915 {
8916 if(ba[j]==start+i*4)
8917 //temp_is32=1;
8918 temp_is32&=p32[j];
8919 }
8920 if(temp_is32!=current.is32) {
8921 //printf("dumping 32-bit regs (%x)\n",start+i*4);
311301dc 8922 #ifndef DESTRUCTIVE_WRITEBACK
8923 if(ds)
8924 #endif
57871462 8925 for(hr=0;hr<HOST_REGS;hr++)
8926 {
8927 int r=current.regmap[hr];
8928 if(r>0&&r<64)
8929 {
8930 if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8931 temp_is32|=1LL<<r;
8932 //printf("restore %d\n",r);
8933 }
8934 }
8935 }
57871462 8936 current.is32=temp_is32;
8937 }
8938 }
6ebf4adf 8939#else
24385cae 8940 current.is32=-1LL;
8941#endif
8942
57871462 8943 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8944 regs[i].wasconst=current.isconst;
8945 regs[i].was32=current.is32;
8946 regs[i].wasdirty=current.dirty;
8575a877 8947 regs[i].loadedconst=0;
6ebf4adf 8948 #if defined(DESTRUCTIVE_WRITEBACK) && !defined(FORCE32)
57871462 8949 // To change a dirty register from 32 to 64 bits, we must write
8950 // it out during the previous cycle (for branches, 2 cycles)
8951 if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8952 {
8953 uint64_t temp_is32=current.is32;
8954 for(j=i-1;j>=0;j--)
8955 {
8956 if(ba[j]==start+i*4+4)
8957 temp_is32&=branch_regs[j].is32;
8958 }
8959 for(j=i;j<slen;j++)
8960 {
8961 if(ba[j]==start+i*4+4)
8962 //temp_is32=1;
8963 temp_is32&=p32[j];
8964 }
8965 if(temp_is32!=current.is32) {
8966 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8967 for(hr=0;hr<HOST_REGS;hr++)
8968 {
8969 int r=current.regmap[hr];
8970 if(r>0)
8971 {
8972 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8973 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
8974 {
8975 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
8976 {
8977 //printf("dump %d/r%d\n",hr,r);
8978 current.regmap[hr]=-1;
8979 if(get_reg(current.regmap,r|64)>=0)
8980 current.regmap[get_reg(current.regmap,r|64)]=-1;
8981 }
8982 }
8983 }
8984 }
8985 }
8986 }
8987 }
8988 else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
8989 {
8990 uint64_t temp_is32=current.is32;
8991 for(j=i-1;j>=0;j--)
8992 {
8993 if(ba[j]==start+i*4+8)
8994 temp_is32&=branch_regs[j].is32;
8995 }
8996 for(j=i;j<slen;j++)
8997 {
8998 if(ba[j]==start+i*4+8)
8999 //temp_is32=1;
9000 temp_is32&=p32[j];
9001 }
9002 if(temp_is32!=current.is32) {
9003 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
9004 for(hr=0;hr<HOST_REGS;hr++)
9005 {
9006 int r=current.regmap[hr];
9007 if(r>0)
9008 {
9009 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
9010 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
9011 {
9012 //printf("dump %d/r%d\n",hr,r);
9013 current.regmap[hr]=-1;
9014 if(get_reg(current.regmap,r|64)>=0)
9015 current.regmap[get_reg(current.regmap,r|64)]=-1;
9016 }
9017 }
9018 }
9019 }
9020 }
9021 }
9022 #endif
9023 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9024 if(i+1<slen) {
9025 current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9026 current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9027 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9028 current.u|=1;
9029 current.uu|=1;
9030 } else {
9031 current.u=1;
9032 current.uu=1;
9033 }
9034 } else {
9035 if(i+1<slen) {
9036 current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
9037 current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9038 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9039 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
9040 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9041 current.u|=1;
9042 current.uu|=1;
9043 } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
9044 }
9045 is_ds[i]=ds;
9046 if(ds) {
9047 ds=0; // Skip delay slot, already allocated as part of branch
9048 // ...but we need to alloc it in case something jumps here
9049 if(i+1<slen) {
9050 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
9051 current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
9052 }else{
9053 current.u=branch_unneeded_reg[i-1];
9054 current.uu=branch_unneeded_reg_upper[i-1];
9055 }
9056 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
9057 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9058 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9059 current.u|=1;
9060 current.uu|=1;
9061 struct regstat temp;
9062 memcpy(&temp,&current,sizeof(current));
9063 temp.wasdirty=temp.dirty;
9064 temp.was32=temp.is32;
9065 // TODO: Take into account unconditional branches, as below
9066 delayslot_alloc(&temp,i);
9067 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
9068 regs[i].wasdirty=temp.wasdirty;
9069 regs[i].was32=temp.was32;
9070 regs[i].dirty=temp.dirty;
9071 regs[i].is32=temp.is32;
9072 regs[i].isconst=0;
9073 regs[i].wasconst=0;
9074 current.isconst=0;
9075 // Create entry (branch target) regmap
9076 for(hr=0;hr<HOST_REGS;hr++)
9077 {
9078 int r=temp.regmap[hr];
9079 if(r>=0) {
9080 if(r!=regmap_pre[i][hr]) {
9081 regs[i].regmap_entry[hr]=-1;
9082 }
9083 else
9084 {
9085 if(r<64){
9086 if((current.u>>r)&1) {
9087 regs[i].regmap_entry[hr]=-1;
9088 regs[i].regmap[hr]=-1;
9089 //Don't clear regs in the delay slot as the branch might need them
9090 //current.regmap[hr]=-1;
9091 }else
9092 regs[i].regmap_entry[hr]=r;
9093 }
9094 else {
9095 if((current.uu>>(r&63))&1) {
9096 regs[i].regmap_entry[hr]=-1;
9097 regs[i].regmap[hr]=-1;
9098 //Don't clear regs in the delay slot as the branch might need them
9099 //current.regmap[hr]=-1;
9100 }else
9101 regs[i].regmap_entry[hr]=r;
9102 }
9103 }
9104 } else {
9105 // First instruction expects CCREG to be allocated
9106 if(i==0&&hr==HOST_CCREG)
9107 regs[i].regmap_entry[hr]=CCREG;
9108 else
9109 regs[i].regmap_entry[hr]=-1;
9110 }
9111 }
9112 }
9113 else { // Not delay slot
9114 switch(itype[i]) {
9115 case UJUMP:
9116 //current.isconst=0; // DEBUG
9117 //current.wasconst=0; // DEBUG
9118 //regs[i].wasconst=0; // DEBUG
9119 clear_const(&current,rt1[i]);
9120 alloc_cc(&current,i);
9121 dirty_reg(&current,CCREG);
9122 if (rt1[i]==31) {
9123 alloc_reg(&current,i,31);
9124 dirty_reg(&current,31);
4ef8f67d 9125 //assert(rs1[i+1]!=31&&rs2[i+1]!=31);
9126 //assert(rt1[i+1]!=rt1[i]);
57871462 9127 #ifdef REG_PREFETCH
9128 alloc_reg(&current,i,PTEMP);
9129 #endif
9130 //current.is32|=1LL<<rt1[i];
9131 }
269bb29a 9132 ooo[i]=1;
9133 delayslot_alloc(&current,i+1);
57871462 9134 //current.isconst=0; // DEBUG
9135 ds=1;
9136 //printf("i=%d, isconst=%x\n",i,current.isconst);
9137 break;
9138 case RJUMP:
9139 //current.isconst=0;
9140 //current.wasconst=0;
9141 //regs[i].wasconst=0;
9142 clear_const(&current,rs1[i]);
9143 clear_const(&current,rt1[i]);
9144 alloc_cc(&current,i);
9145 dirty_reg(&current,CCREG);
9146 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
9147 alloc_reg(&current,i,rs1[i]);
5067f341 9148 if (rt1[i]!=0) {
9149 alloc_reg(&current,i,rt1[i]);
9150 dirty_reg(&current,rt1[i]);
68b3faee 9151 assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
076655d1 9152 assert(rt1[i+1]!=rt1[i]);
57871462 9153 #ifdef REG_PREFETCH
9154 alloc_reg(&current,i,PTEMP);
9155 #endif
9156 }
9157 #ifdef USE_MINI_HT
9158 if(rs1[i]==31) { // JALR
9159 alloc_reg(&current,i,RHASH);
9160 #ifndef HOST_IMM_ADDR32
9161 alloc_reg(&current,i,RHTBL);
9162 #endif
9163 }
9164 #endif
9165 delayslot_alloc(&current,i+1);
9166 } else {
9167 // The delay slot overwrites our source register,
9168 // allocate a temporary register to hold the old value.
9169 current.isconst=0;
9170 current.wasconst=0;
9171 regs[i].wasconst=0;
9172 delayslot_alloc(&current,i+1);
9173 current.isconst=0;
9174 alloc_reg(&current,i,RTEMP);
9175 }
9176 //current.isconst=0; // DEBUG
e1190b87 9177 ooo[i]=1;
57871462 9178 ds=1;
9179 break;
9180 case CJUMP:
9181 //current.isconst=0;
9182 //current.wasconst=0;
9183 //regs[i].wasconst=0;
9184 clear_const(&current,rs1[i]);
9185 clear_const(&current,rs2[i]);
9186 if((opcode[i]&0x3E)==4) // BEQ/BNE
9187 {
9188 alloc_cc(&current,i);
9189 dirty_reg(&current,CCREG);
9190 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9191 if(rs2[i]) alloc_reg(&current,i,rs2[i]);
9192 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9193 {
9194 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9195 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
9196 }
9197 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
9198 (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
9199 // The delay slot overwrites one of our conditions.
9200 // Allocate the branch condition registers instead.
57871462 9201 current.isconst=0;
9202 current.wasconst=0;
9203 regs[i].wasconst=0;
9204 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9205 if(rs2[i]) alloc_reg(&current,i,rs2[i]);
9206 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9207 {
9208 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9209 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
9210 }
9211 }
e1190b87 9212 else
9213 {
9214 ooo[i]=1;
9215 delayslot_alloc(&current,i+1);
9216 }
57871462 9217 }
9218 else
9219 if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
9220 {
9221 alloc_cc(&current,i);
9222 dirty_reg(&current,CCREG);
9223 alloc_reg(&current,i,rs1[i]);
9224 if(!(current.is32>>rs1[i]&1))
9225 {
9226 alloc_reg64(&current,i,rs1[i]);
9227 }
9228 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
9229 // The delay slot overwrites one of our conditions.
9230 // Allocate the branch condition registers instead.
57871462 9231 current.isconst=0;
9232 current.wasconst=0;
9233 regs[i].wasconst=0;
9234 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9235 if(!((current.is32>>rs1[i])&1))
9236 {
9237 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9238 }
9239 }
e1190b87 9240 else
9241 {
9242 ooo[i]=1;
9243 delayslot_alloc(&current,i+1);
9244 }
57871462 9245 }
9246 else
9247 // Don't alloc the delay slot yet because we might not execute it
9248 if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
9249 {
9250 current.isconst=0;
9251 current.wasconst=0;
9252 regs[i].wasconst=0;
9253 alloc_cc(&current,i);
9254 dirty_reg(&current,CCREG);
9255 alloc_reg(&current,i,rs1[i]);
9256 alloc_reg(&current,i,rs2[i]);
9257 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9258 {
9259 alloc_reg64(&current,i,rs1[i]);
9260 alloc_reg64(&current,i,rs2[i]);
9261 }
9262 }
9263 else
9264 if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
9265 {
9266 current.isconst=0;
9267 current.wasconst=0;
9268 regs[i].wasconst=0;
9269 alloc_cc(&current,i);
9270 dirty_reg(&current,CCREG);
9271 alloc_reg(&current,i,rs1[i]);
9272 if(!(current.is32>>rs1[i]&1))
9273 {
9274 alloc_reg64(&current,i,rs1[i]);
9275 }
9276 }
9277 ds=1;
9278 //current.isconst=0;
9279 break;
9280 case SJUMP:
9281 //current.isconst=0;
9282 //current.wasconst=0;
9283 //regs[i].wasconst=0;
9284 clear_const(&current,rs1[i]);
9285 clear_const(&current,rt1[i]);
9286 //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
9287 if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
9288 {
9289 alloc_cc(&current,i);
9290 dirty_reg(&current,CCREG);
9291 alloc_reg(&current,i,rs1[i]);
9292 if(!(current.is32>>rs1[i]&1))
9293 {
9294 alloc_reg64(&current,i,rs1[i]);
9295 }
9296 if (rt1[i]==31) { // BLTZAL/BGEZAL
9297 alloc_reg(&current,i,31);
9298 dirty_reg(&current,31);
57871462 9299 //#ifdef REG_PREFETCH
9300 //alloc_reg(&current,i,PTEMP);
9301 //#endif
9302 //current.is32|=1LL<<rt1[i];
9303 }
e1190b87 9304 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) // The delay slot overwrites the branch condition.
9305 ||(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))) { // DS touches $ra
57871462 9306 // Allocate the branch condition registers instead.
57871462 9307 current.isconst=0;
9308 current.wasconst=0;
9309 regs[i].wasconst=0;
9310 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9311 if(!((current.is32>>rs1[i])&1))
9312 {
9313 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9314 }
9315 }
e1190b87 9316 else
9317 {
9318 ooo[i]=1;
9319 delayslot_alloc(&current,i+1);
9320 }
57871462 9321 }
9322 else
9323 // Don't alloc the delay slot yet because we might not execute it
9324 if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
9325 {
9326 current.isconst=0;
9327 current.wasconst=0;
9328 regs[i].wasconst=0;
9329 alloc_cc(&current,i);
9330 dirty_reg(&current,CCREG);
9331 alloc_reg(&current,i,rs1[i]);
9332 if(!(current.is32>>rs1[i]&1))
9333 {
9334 alloc_reg64(&current,i,rs1[i]);
9335 }
9336 }
9337 ds=1;
9338 //current.isconst=0;
9339 break;
9340 case FJUMP:
9341 current.isconst=0;
9342 current.wasconst=0;
9343 regs[i].wasconst=0;
9344 if(likely[i]==0) // BC1F/BC1T
9345 {
9346 // TODO: Theoretically we can run out of registers here on x86.
9347 // The delay slot can allocate up to six, and we need to check
9348 // CSREG before executing the delay slot. Possibly we can drop
9349 // the cycle count and then reload it after checking that the
9350 // FPU is in a usable state, or don't do out-of-order execution.
9351 alloc_cc(&current,i);
9352 dirty_reg(&current,CCREG);
9353 alloc_reg(&current,i,FSREG);
9354 alloc_reg(&current,i,CSREG);
9355 if(itype[i+1]==FCOMP) {
9356 // The delay slot overwrites the branch condition.
9357 // Allocate the branch condition registers instead.
57871462 9358 alloc_cc(&current,i);
9359 dirty_reg(&current,CCREG);
9360 alloc_reg(&current,i,CSREG);
9361 alloc_reg(&current,i,FSREG);
9362 }
9363 else {
e1190b87 9364 ooo[i]=1;
57871462 9365 delayslot_alloc(&current,i+1);
9366 alloc_reg(&current,i+1,CSREG);
9367 }
9368 }
9369 else
9370 // Don't alloc the delay slot yet because we might not execute it
9371 if(likely[i]) // BC1FL/BC1TL
9372 {
9373 alloc_cc(&current,i);
9374 dirty_reg(&current,CCREG);
9375 alloc_reg(&current,i,CSREG);
9376 alloc_reg(&current,i,FSREG);
9377 }
9378 ds=1;
9379 current.isconst=0;
9380 break;
9381 case IMM16:
9382 imm16_alloc(&current,i);
9383 break;
9384 case LOAD:
9385 case LOADLR:
9386 load_alloc(&current,i);
9387 break;
9388 case STORE:
9389 case STORELR:
9390 store_alloc(&current,i);
9391 break;
9392 case ALU:
9393 alu_alloc(&current,i);
9394 break;
9395 case SHIFT:
9396 shift_alloc(&current,i);
9397 break;
9398 case MULTDIV:
9399 multdiv_alloc(&current,i);
9400 break;
9401 case SHIFTIMM:
9402 shiftimm_alloc(&current,i);
9403 break;
9404 case MOV:
9405 mov_alloc(&current,i);
9406 break;
9407 case COP0:
9408 cop0_alloc(&current,i);
9409 break;
9410 case COP1:
b9b61529 9411 case COP2:
57871462 9412 cop1_alloc(&current,i);
9413 break;
9414 case C1LS:
9415 c1ls_alloc(&current,i);
9416 break;
b9b61529 9417 case C2LS:
9418 c2ls_alloc(&current,i);
9419 break;
9420 case C2OP:
9421 c2op_alloc(&current,i);
9422 break;
57871462 9423 case FCONV:
9424 fconv_alloc(&current,i);
9425 break;
9426 case FLOAT:
9427 float_alloc(&current,i);
9428 break;
9429 case FCOMP:
9430 fcomp_alloc(&current,i);
9431 break;
9432 case SYSCALL:
7139f3c8 9433 case HLECALL:
1e973cb0 9434 case INTCALL:
57871462 9435 syscall_alloc(&current,i);
9436 break;
9437 case SPAN:
9438 pagespan_alloc(&current,i);
9439 break;
9440 }
9441
9442 // Drop the upper half of registers that have become 32-bit
9443 current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
9444 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9445 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9446 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9447 current.uu|=1;
9448 } else {
9449 current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
9450 current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9451 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9452 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9453 current.uu|=1;
9454 }
9455
9456 // Create entry (branch target) regmap
9457 for(hr=0;hr<HOST_REGS;hr++)
9458 {
9459 int r,or,er;
9460 r=current.regmap[hr];
9461 if(r>=0) {
9462 if(r!=regmap_pre[i][hr]) {
9463 // TODO: delay slot (?)
9464 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9465 if(or<0||(r&63)>=TEMPREG){
9466 regs[i].regmap_entry[hr]=-1;
9467 }
9468 else
9469 {
9470 // Just move it to a different register
9471 regs[i].regmap_entry[hr]=r;
9472 // If it was dirty before, it's still dirty
9473 if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r&63);
9474 }
9475 }
9476 else
9477 {
9478 // Unneeded
9479 if(r==0){
9480 regs[i].regmap_entry[hr]=0;
9481 }
9482 else
9483 if(r<64){
9484 if((current.u>>r)&1) {
9485 regs[i].regmap_entry[hr]=-1;
9486 //regs[i].regmap[hr]=-1;
9487 current.regmap[hr]=-1;
9488 }else
9489 regs[i].regmap_entry[hr]=r;
9490 }
9491 else {
9492 if((current.uu>>(r&63))&1) {
9493 regs[i].regmap_entry[hr]=-1;
9494 //regs[i].regmap[hr]=-1;
9495 current.regmap[hr]=-1;
9496 }else
9497 regs[i].regmap_entry[hr]=r;
9498 }
9499 }
9500 } else {
9501 // Branches expect CCREG to be allocated at the target
9502 if(regmap_pre[i][hr]==CCREG)
9503 regs[i].regmap_entry[hr]=CCREG;
9504 else
9505 regs[i].regmap_entry[hr]=-1;
9506 }
9507 }
9508 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9509 }
27727b63 9510
9511 if(i>0&&(itype[i-1]==STORE||itype[i-1]==STORELR||(itype[i-1]==C2LS&&opcode[i-1]==0x3a))&&(u_int)imm[i-1]<0x800)
9512 current.waswritten|=1<<rs1[i-1];
9513 current.waswritten&=~(1<<rt1[i]);
9514 current.waswritten&=~(1<<rt2[i]);
9515 if((itype[i]==STORE||itype[i]==STORELR||(itype[i]==C2LS&&opcode[i]==0x3a))&&(u_int)imm[i]>=0x800)
9516 current.waswritten&=~(1<<rs1[i]);
9517
57871462 9518 /* Branch post-alloc */
9519 if(i>0)
9520 {
9521 current.was32=current.is32;
9522 current.wasdirty=current.dirty;
9523 switch(itype[i-1]) {
9524 case UJUMP:
9525 memcpy(&branch_regs[i-1],&current,sizeof(current));
9526 branch_regs[i-1].isconst=0;
9527 branch_regs[i-1].wasconst=0;
9528 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9529 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9530 alloc_cc(&branch_regs[i-1],i-1);
9531 dirty_reg(&branch_regs[i-1],CCREG);
9532 if(rt1[i-1]==31) { // JAL
9533 alloc_reg(&branch_regs[i-1],i-1,31);
9534 dirty_reg(&branch_regs[i-1],31);
9535 branch_regs[i-1].is32|=1LL<<31;
9536 }
9537 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
956f3129 9538 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
57871462 9539 break;
9540 case RJUMP:
9541 memcpy(&branch_regs[i-1],&current,sizeof(current));
9542 branch_regs[i-1].isconst=0;
9543 branch_regs[i-1].wasconst=0;
9544 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9545 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9546 alloc_cc(&branch_regs[i-1],i-1);
9547 dirty_reg(&branch_regs[i-1],CCREG);
9548 alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
5067f341 9549 if(rt1[i-1]!=0) { // JALR
9550 alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9551 dirty_reg(&branch_regs[i-1],rt1[i-1]);
9552 branch_regs[i-1].is32|=1LL<<rt1[i-1];
57871462 9553 }
9554 #ifdef USE_MINI_HT
9555 if(rs1[i-1]==31) { // JALR
9556 alloc_reg(&branch_regs[i-1],i-1,RHASH);
9557 #ifndef HOST_IMM_ADDR32
9558 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9559 #endif
9560 }
9561 #endif
9562 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
956f3129 9563 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
57871462 9564 break;
9565 case CJUMP:
9566 if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9567 {
9568 alloc_cc(&current,i-1);
9569 dirty_reg(&current,CCREG);
9570 if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9571 (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9572 // The delay slot overwrote one of our conditions
9573 // Delay slot goes after the test (in order)
9574 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9575 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9576 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9577 current.u|=1;
9578 current.uu|=1;
9579 delayslot_alloc(&current,i);
9580 current.isconst=0;
9581 }
9582 else
9583 {
9584 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9585 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9586 // Alloc the branch condition registers
9587 if(rs1[i-1]) alloc_reg(&current,i-1,rs1[i-1]);
9588 if(rs2[i-1]) alloc_reg(&current,i-1,rs2[i-1]);
9589 if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9590 {
9591 if(rs1[i-1]) alloc_reg64(&current,i-1,rs1[i-1]);
9592 if(rs2[i-1]) alloc_reg64(&current,i-1,rs2[i-1]);
9593 }
9594 }
9595 memcpy(&branch_regs[i-1],&current,sizeof(current));
9596 branch_regs[i-1].isconst=0;
9597 branch_regs[i-1].wasconst=0;
9598 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
956f3129 9599 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
57871462 9600 }
9601 else
9602 if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9603 {
9604 alloc_cc(&current,i-1);
9605 dirty_reg(&current,CCREG);
9606 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9607 // The delay slot overwrote the branch condition
9608 // Delay slot goes after the test (in order)
9609 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9610 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9611 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9612 current.u|=1;
9613 current.uu|=1;
9614 delayslot_alloc(&current,i);
9615 current.isconst=0;
9616 }
9617 else
9618 {
9619 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9620 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9621 // Alloc the branch condition register
9622 alloc_reg(&current,i-1,rs1[i-1]);
9623 if(!(current.is32>>rs1[i-1]&1))
9624 {
9625 alloc_reg64(&current,i-1,rs1[i-1]);
9626 }
9627 }
9628 memcpy(&branch_regs[i-1],&current,sizeof(current));
9629 branch_regs[i-1].isconst=0;
9630 branch_regs[i-1].wasconst=0;
9631 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
956f3129 9632 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
57871462 9633 }
9634 else
9635 // Alloc the delay slot in case the branch is taken
9636 if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9637 {
9638 memcpy(&branch_regs[i-1],&current,sizeof(current));
9639 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9640 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9641 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9642 alloc_cc(&branch_regs[i-1],i);
9643 dirty_reg(&branch_regs[i-1],CCREG);
9644 delayslot_alloc(&branch_regs[i-1],i);
9645 branch_regs[i-1].isconst=0;
9646 alloc_reg(&current,i,CCREG); // Not taken path
9647 dirty_reg(&current,CCREG);
9648 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9649 }
9650 else
9651 if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9652 {
9653 memcpy(&branch_regs[i-1],&current,sizeof(current));
9654 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9655 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9656 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9657 alloc_cc(&branch_regs[i-1],i);
9658 dirty_reg(&branch_regs[i-1],CCREG);
9659 delayslot_alloc(&branch_regs[i-1],i);
9660 branch_regs[i-1].isconst=0;
9661 alloc_reg(&current,i,CCREG); // Not taken path
9662 dirty_reg(&current,CCREG);
9663 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9664 }
9665 break;
9666 case SJUMP:
9667 //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9668 if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9669 {
9670 alloc_cc(&current,i-1);
9671 dirty_reg(&current,CCREG);
9672 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9673 // The delay slot overwrote the branch condition
9674 // Delay slot goes after the test (in order)
9675 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9676 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9677 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9678 current.u|=1;
9679 current.uu|=1;
9680 delayslot_alloc(&current,i);
9681 current.isconst=0;
9682 }
9683 else
9684 {
9685 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9686 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9687 // Alloc the branch condition register
9688 alloc_reg(&current,i-1,rs1[i-1]);
9689 if(!(current.is32>>rs1[i-1]&1))
9690 {
9691 alloc_reg64(&current,i-1,rs1[i-1]);
9692 }
9693 }
9694 memcpy(&branch_regs[i-1],&current,sizeof(current));
9695 branch_regs[i-1].isconst=0;
9696 branch_regs[i-1].wasconst=0;
9697 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
956f3129 9698 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
57871462 9699 }
9700 else
9701 // Alloc the delay slot in case the branch is taken
9702 if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9703 {
9704 memcpy(&branch_regs[i-1],&current,sizeof(current));
9705 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9706 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9707 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9708 alloc_cc(&branch_regs[i-1],i);
9709 dirty_reg(&branch_regs[i-1],CCREG);
9710 delayslot_alloc(&branch_regs[i-1],i);
9711 branch_regs[i-1].isconst=0;
9712 alloc_reg(&current,i,CCREG); // Not taken path
9713 dirty_reg(&current,CCREG);
9714 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9715 }
9716 // FIXME: BLTZAL/BGEZAL
9717 if(opcode2[i-1]&0x10) { // BxxZAL
9718 alloc_reg(&branch_regs[i-1],i-1,31);
9719 dirty_reg(&branch_regs[i-1],31);
9720 branch_regs[i-1].is32|=1LL<<31;
9721 }
9722 break;
9723 case FJUMP:
9724 if(likely[i-1]==0) // BC1F/BC1T
9725 {
9726 alloc_cc(&current,i-1);
9727 dirty_reg(&current,CCREG);
9728 if(itype[i]==FCOMP) {
9729 // The delay slot overwrote the branch condition
9730 // Delay slot goes after the test (in order)
9731 delayslot_alloc(&current,i);
9732 current.isconst=0;
9733 }
9734 else
9735 {
9736 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9737 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9738 // Alloc the branch condition register
9739 alloc_reg(&current,i-1,FSREG);
9740 }
9741 memcpy(&branch_regs[i-1],&current,sizeof(current));
9742 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9743 }
9744 else // BC1FL/BC1TL
9745 {
9746 // Alloc the delay slot in case the branch is taken
9747 memcpy(&branch_regs[i-1],&current,sizeof(current));
9748 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9749 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9750 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9751 alloc_cc(&branch_regs[i-1],i);
9752 dirty_reg(&branch_regs[i-1],CCREG);
9753 delayslot_alloc(&branch_regs[i-1],i);
9754 branch_regs[i-1].isconst=0;
9755 alloc_reg(&current,i,CCREG); // Not taken path
9756 dirty_reg(&current,CCREG);
9757 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9758 }
9759 break;
9760 }
9761
9762 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9763 {
9764 if(rt1[i-1]==31) // JAL/JALR
9765 {
9766 // Subroutine call will return here, don't alloc any registers
9767 current.is32=1;
9768 current.dirty=0;
9769 clear_all_regs(current.regmap);
9770 alloc_reg(&current,i,CCREG);
9771 dirty_reg(&current,CCREG);
9772 }
9773 else if(i+1<slen)
9774 {
9775 // Internal branch will jump here, match registers to caller
9776 current.is32=0x3FFFFFFFFLL;
9777 current.dirty=0;
9778 clear_all_regs(current.regmap);
9779 alloc_reg(&current,i,CCREG);
9780 dirty_reg(&current,CCREG);
9781 for(j=i-1;j>=0;j--)
9782 {
9783 if(ba[j]==start+i*4+4) {
9784 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9785 current.is32=branch_regs[j].is32;
9786 current.dirty=branch_regs[j].dirty;
9787 break;
9788 }
9789 }
9790 while(j>=0) {
9791 if(ba[j]==start+i*4+4) {
9792 for(hr=0;hr<HOST_REGS;hr++) {
9793 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9794 current.regmap[hr]=-1;
9795 }
9796 current.is32&=branch_regs[j].is32;
9797 current.dirty&=branch_regs[j].dirty;
9798 }
9799 }
9800 j--;
9801 }
9802 }
9803 }
9804 }
9805
9806 // Count cycles in between branches
9807 ccadj[i]=cc;
7139f3c8 9808 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
57871462 9809 {
9810 cc=0;
9811 }
19776aef 9812#if defined(PCSX) && !defined(DRC_DBG)
054175e9 9813 else if(itype[i]==C2OP&&gte_cycletab[source[i]&0x3f]>2)
9814 {
9815 // GTE runs in parallel until accessed, divide by 2 for a rough guess
9816 cc+=gte_cycletab[source[i]&0x3f]/2;
9817 }
fb407447 9818 else if(/*itype[i]==LOAD||*/itype[i]==STORE||itype[i]==C1LS) // load causes weird timing issues
9819 {
9820 cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
9821 }
9822 else if(itype[i]==C2LS)
9823 {
9824 cc+=4;
9825 }
9826#endif
57871462 9827 else
9828 {
9829 cc++;
9830 }
9831
9832 flush_dirty_uppers(&current);
9833 if(!is_ds[i]) {
9834 regs[i].is32=current.is32;
9835 regs[i].dirty=current.dirty;
9836 regs[i].isconst=current.isconst;
956f3129 9837 memcpy(constmap[i],current_constmap,sizeof(current_constmap));
57871462 9838 }
9839 for(hr=0;hr<HOST_REGS;hr++) {
9840 if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
9841 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9842 regs[i].wasconst&=~(1<<hr);
9843 }
9844 }
9845 }
9846 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
27727b63 9847 regs[i].waswritten=current.waswritten;
57871462 9848 }
9849
9850 /* Pass 4 - Cull unused host registers */
9851
9852 uint64_t nr=0;
9853
9854 for (i=slen-1;i>=0;i--)
9855 {
9856 int hr;
9857 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9858 {
9859 if(ba[i]<start || ba[i]>=(start+slen*4))
9860 {
9861 // Branch out of this block, don't need anything
9862 nr=0;
9863 }
9864 else
9865 {
9866 // Internal branch
9867 // Need whatever matches the target
9868 nr=0;
9869 int t=(ba[i]-start)>>2;
9870 for(hr=0;hr<HOST_REGS;hr++)
9871 {
9872 if(regs[i].regmap_entry[hr]>=0) {
9873 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9874 }
9875 }
9876 }
9877 // Conditional branch may need registers for following instructions
9878 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9879 {
9880 if(i<slen-2) {
9881 nr|=needed_reg[i+2];
9882 for(hr=0;hr<HOST_REGS;hr++)
9883 {
9884 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9885 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9886 }
9887 }
9888 }
9889 // Don't need stuff which is overwritten
f5955059 9890 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9891 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
57871462 9892 // Merge in delay slot
9893 for(hr=0;hr<HOST_REGS;hr++)
9894 {
9895 if(!likely[i]) {
9896 // These are overwritten unless the branch is "likely"
9897 // and the delay slot is nullified if not taken
9898 if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9899 if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9900 }
9901 if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9902 if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9903 if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9904 if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9905 if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9906 if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9907 if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9908 if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9909 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9910 if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9911 if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9912 }
9913 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9914 if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9915 if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9916 }
b9b61529 9917 if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
57871462 9918 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9919 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9920 }
9921 }
9922 }
1e973cb0 9923 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 9924 {
9925 // SYSCALL instruction (software interrupt)
9926 nr=0;
9927 }
9928 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9929 {
9930 // ERET instruction (return from interrupt)
9931 nr=0;
9932 }
9933 else // Non-branch
9934 {
9935 if(i<slen-1) {
9936 for(hr=0;hr<HOST_REGS;hr++) {
9937 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9938 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9939 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9940 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9941 }
9942 }
9943 }
9944 for(hr=0;hr<HOST_REGS;hr++)
9945 {
9946 // Overwritten registers are not needed
9947 if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9948 if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9949 if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9950 // Source registers are needed
9951 if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9952 if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9953 if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9954 if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9955 if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9956 if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9957 if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9958 if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9959 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9960 if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9961 if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9962 }
9963 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
9964 if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9965 if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9966 }
b9b61529 9967 if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
57871462 9968 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9969 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9970 }
9971 // Don't store a register immediately after writing it,
9972 // may prevent dual-issue.
9973 // But do so if this is a branch target, otherwise we
9974 // might have to load the register before the branch.
9975 if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
9976 if((regmap_pre[i][hr]>0&&regmap_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
9977 (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
9978 if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9979 if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9980 }
9981 if((regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
9982 (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
9983 if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9984 if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9985 }
9986 }
9987 }
9988 // Cycle count is needed at branches. Assume it is needed at the target too.
9989 if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
9990 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9991 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9992 }
9993 // Save it
9994 needed_reg[i]=nr;
9995
9996 // Deallocate unneeded registers
9997 for(hr=0;hr<HOST_REGS;hr++)
9998 {
9999 if(!((nr>>hr)&1)) {
10000 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
10001 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
10002 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
10003 (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
10004 {
10005 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10006 {
10007 if(likely[i]) {
10008 regs[i].regmap[hr]=-1;
10009 regs[i].isconst&=~(1<<hr);
79c75f1b 10010 if(i<slen-2) {
10011 regmap_pre[i+2][hr]=-1;
10012 regs[i+2].wasconst&=~(1<<hr);
10013 }
57871462 10014 }
10015 }
10016 }
10017 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10018 {
10019 int d1=0,d2=0,map=0,temp=0;
10020 if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
10021 {
10022 d1=dep1[i+1];
10023 d2=dep2[i+1];
10024 }
10025 if(using_tlb) {
10026 if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
10027 itype[i+1]==STORE || itype[i+1]==STORELR ||
b9b61529 10028 itype[i+1]==C1LS || itype[i+1]==C2LS)
57871462 10029 map=TLREG;
10030 } else
b9b61529 10031 if(itype[i+1]==STORE || itype[i+1]==STORELR ||
10032 (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
57871462 10033 map=INVCP;
10034 }
10035 if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
b9b61529 10036 itype[i+1]==C1LS || itype[i+1]==C2LS)
57871462 10037 temp=FTEMP;
10038 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
10039 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
10040 (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
10041 (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
10042 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
10043 regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
10044 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
10045 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
10046 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
10047 regs[i].regmap[hr]!=map )
10048 {
10049 regs[i].regmap[hr]=-1;
10050 regs[i].isconst&=~(1<<hr);
10051 if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
10052 (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
10053 (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
10054 (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
10055 (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
10056 branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
10057 (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
10058 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
10059 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
10060 branch_regs[i].regmap[hr]!=map)
10061 {
10062 branch_regs[i].regmap[hr]=-1;
10063 branch_regs[i].regmap_entry[hr]=-1;
10064 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10065 {
10066 if(!likely[i]&&i<slen-2) {
10067 regmap_pre[i+2][hr]=-1;
79c75f1b 10068 regs[i+2].wasconst&=~(1<<hr);
57871462 10069 }
10070 }
10071 }
10072 }
10073 }
10074 else
10075 {
10076 // Non-branch
10077 if(i>0)
10078 {
10079 int d1=0,d2=0,map=-1,temp=-1;
10080 if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
10081 {
10082 d1=dep1[i];
10083 d2=dep2[i];
10084 }
10085 if(using_tlb) {
10086 if(itype[i]==LOAD || itype[i]==LOADLR ||
10087 itype[i]==STORE || itype[i]==STORELR ||
b9b61529 10088 itype[i]==C1LS || itype[i]==C2LS)
57871462 10089 map=TLREG;
b9b61529 10090 } else if(itype[i]==STORE || itype[i]==STORELR ||
10091 (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
57871462 10092 map=INVCP;
10093 }
10094 if(itype[i]==LOADLR || itype[i]==STORELR ||
b9b61529 10095 itype[i]==C1LS || itype[i]==C2LS)
57871462 10096 temp=FTEMP;
10097 if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
10098 (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
10099 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
10100 regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
10101 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
10102 (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
10103 {
10104 if(i<slen-1&&!is_ds[i]) {
10105 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
10106 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
10107 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
10108 {
10109 printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
10110 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
10111 }
10112 regmap_pre[i+1][hr]=-1;
10113 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
79c75f1b 10114 regs[i+1].wasconst&=~(1<<hr);
57871462 10115 }
10116 regs[i].regmap[hr]=-1;
10117 regs[i].isconst&=~(1<<hr);
10118 }
10119 }
10120 }
10121 }
10122 }
10123 }
10124
10125 /* Pass 5 - Pre-allocate registers */
10126
10127 // If a register is allocated during a loop, try to allocate it for the
10128 // entire loop, if possible. This avoids loading/storing registers
10129 // inside of the loop.
198df76f 10130
57871462 10131 signed char f_regmap[HOST_REGS];
10132 clear_all_regs(f_regmap);
10133 for(i=0;i<slen-1;i++)
10134 {
10135 if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10136 {
10137 if(ba[i]>=start && ba[i]<(start+i*4))
10138 if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
10139 ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
10140 ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
10141 ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
b9b61529 10142 ||itype[i+1]==FCOMP||itype[i+1]==FCONV
10143 ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
57871462 10144 {
10145 int t=(ba[i]-start)>>2;
10146 if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
198df76f 10147 if(t<2||(itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||rt1[t-2]!=31) // call/ret assumes no registers allocated
57871462 10148 for(hr=0;hr<HOST_REGS;hr++)
10149 {
10150 if(regs[i].regmap[hr]>64) {
10151 if(!((regs[i].dirty>>hr)&1))
10152 f_regmap[hr]=regs[i].regmap[hr];
10153 else f_regmap[hr]=-1;
10154 }
b372a952 10155 else if(regs[i].regmap[hr]>=0) {
10156 if(f_regmap[hr]!=regs[i].regmap[hr]) {
10157 // dealloc old register
10158 int n;
10159 for(n=0;n<HOST_REGS;n++)
10160 {
10161 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10162 }
10163 // and alloc new one
10164 f_regmap[hr]=regs[i].regmap[hr];
10165 }
10166 }
57871462 10167 if(branch_regs[i].regmap[hr]>64) {
10168 if(!((branch_regs[i].dirty>>hr)&1))
10169 f_regmap[hr]=branch_regs[i].regmap[hr];
10170 else f_regmap[hr]=-1;
10171 }
b372a952 10172 else if(branch_regs[i].regmap[hr]>=0) {
10173 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
10174 // dealloc old register
10175 int n;
10176 for(n=0;n<HOST_REGS;n++)
10177 {
10178 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
10179 }
10180 // and alloc new one
10181 f_regmap[hr]=branch_regs[i].regmap[hr];
10182 }
10183 }
e1190b87 10184 if(ooo[i]) {
10185 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
10186 f_regmap[hr]=branch_regs[i].regmap[hr];
10187 }else{
10188 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
57871462 10189 f_regmap[hr]=branch_regs[i].regmap[hr];
10190 }
10191 // Avoid dirty->clean transition
e1190b87 10192 #ifdef DESTRUCTIVE_WRITEBACK
57871462 10193 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
e1190b87 10194 #endif
10195 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
10196 // case above, however it's always a good idea. We can't hoist the
10197 // load if the register was already allocated, so there's no point
10198 // wasting time analyzing most of these cases. It only "succeeds"
10199 // when the mapping was different and the load can be replaced with
10200 // a mov, which is of negligible benefit. So such cases are
10201 // skipped below.
57871462 10202 if(f_regmap[hr]>0) {
198df76f 10203 if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
57871462 10204 int r=f_regmap[hr];
10205 for(j=t;j<=i;j++)
10206 {
10207 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10208 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
10209 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
10210 if(r>63) {
10211 // NB This can exclude the case where the upper-half
10212 // register is lower numbered than the lower-half
10213 // register. Not sure if it's worth fixing...
10214 if(get_reg(regs[j].regmap,r&63)<0) break;
e1190b87 10215 if(get_reg(regs[j].regmap_entry,r&63)<0) break;
57871462 10216 if(regs[j].is32&(1LL<<(r&63))) break;
10217 }
10218 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
10219 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10220 int k;
10221 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
10222 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
10223 if(r>63) {
10224 if(get_reg(regs[i].regmap,r&63)<0) break;
10225 if(get_reg(branch_regs[i].regmap,r&63)<0) break;
10226 }
10227 k=i;
10228 while(k>1&&regs[k-1].regmap[hr]==-1) {
e1190b87 10229 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10230 //printf("no free regs for store %x\n",start+(k-1)*4);
10231 break;
57871462 10232 }
57871462 10233 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
10234 //printf("no-match due to different register\n");
10235 break;
10236 }
10237 if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
10238 //printf("no-match due to branch\n");
10239 break;
10240 }
10241 // call/ret fast path assumes no registers allocated
198df76f 10242 if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)&&rt1[k-3]==31) {
57871462 10243 break;
10244 }
10245 if(r>63) {
10246 // NB This can exclude the case where the upper-half
10247 // register is lower numbered than the lower-half
10248 // register. Not sure if it's worth fixing...
10249 if(get_reg(regs[k-1].regmap,r&63)<0) break;
10250 if(regs[k-1].is32&(1LL<<(r&63))) break;
10251 }
10252 k--;
10253 }
10254 if(i<slen-1) {
10255 if((regs[k].is32&(1LL<<f_regmap[hr]))!=
10256 (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
10257 //printf("bad match after branch\n");
10258 break;
10259 }
10260 }
10261 if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
10262 //printf("Extend r%d, %x ->\n",hr,start+k*4);
10263 while(k<i) {
10264 regs[k].regmap_entry[hr]=f_regmap[hr];
10265 regs[k].regmap[hr]=f_regmap[hr];
10266 regmap_pre[k+1][hr]=f_regmap[hr];
10267 regs[k].wasdirty&=~(1<<hr);
10268 regs[k].dirty&=~(1<<hr);
10269 regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
10270 regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
10271 regs[k].wasconst&=~(1<<hr);
10272 regs[k].isconst&=~(1<<hr);
10273 k++;
10274 }
10275 }
10276 else {
10277 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
10278 break;
10279 }
10280 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
10281 if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
10282 //printf("OK fill %x (r%d)\n",start+i*4,hr);
10283 regs[i].regmap_entry[hr]=f_regmap[hr];
10284 regs[i].regmap[hr]=f_regmap[hr];
10285 regs[i].wasdirty&=~(1<<hr);
10286 regs[i].dirty&=~(1<<hr);
10287 regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
10288 regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
10289 regs[i].wasconst&=~(1<<hr);
10290 regs[i].isconst&=~(1<<hr);
10291 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
10292 branch_regs[i].wasdirty&=~(1<<hr);
10293 branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
10294 branch_regs[i].regmap[hr]=f_regmap[hr];
10295 branch_regs[i].dirty&=~(1<<hr);
10296 branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
10297 branch_regs[i].wasconst&=~(1<<hr);
10298 branch_regs[i].isconst&=~(1<<hr);
10299 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
10300 regmap_pre[i+2][hr]=f_regmap[hr];
10301 regs[i+2].wasdirty&=~(1<<hr);
10302 regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
10303 assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
10304 (regs[i+2].was32&(1LL<<f_regmap[hr])));
10305 }
10306 }
10307 }
10308 for(k=t;k<j;k++) {
e1190b87 10309 // Alloc register clean at beginning of loop,
10310 // but may dirty it in pass 6
57871462 10311 regs[k].regmap_entry[hr]=f_regmap[hr];
10312 regs[k].regmap[hr]=f_regmap[hr];
57871462 10313 regs[k].dirty&=~(1<<hr);
10314 regs[k].wasconst&=~(1<<hr);
10315 regs[k].isconst&=~(1<<hr);
e1190b87 10316 if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) {
10317 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
10318 branch_regs[k].regmap[hr]=f_regmap[hr];
10319 branch_regs[k].dirty&=~(1<<hr);
10320 branch_regs[k].wasconst&=~(1<<hr);
10321 branch_regs[k].isconst&=~(1<<hr);
10322 if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
10323 regmap_pre[k+2][hr]=f_regmap[hr];
10324 regs[k+2].wasdirty&=~(1<<hr);
10325 assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))==
10326 (regs[k+2].was32&(1LL<<f_regmap[hr])));
10327 }
10328 }
10329 else
10330 {
10331 regmap_pre[k+1][hr]=f_regmap[hr];
10332 regs[k+1].wasdirty&=~(1<<hr);
10333 }
57871462 10334 }
10335 if(regs[j].regmap[hr]==f_regmap[hr])
10336 regs[j].regmap_entry[hr]=f_regmap[hr];
10337 break;
10338 }
10339 if(j==i) break;
10340 if(regs[j].regmap[hr]>=0)
10341 break;
10342 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
10343 //printf("no-match due to different register\n");
10344 break;
10345 }
10346 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
10347 //printf("32/64 mismatch %x %d\n",start+j*4,hr);
10348 break;
10349 }
e1190b87 10350 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10351 {
10352 // Stop on unconditional branch
10353 break;
10354 }
10355 if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
10356 {
10357 if(ooo[j]) {
10358 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
10359 break;
10360 }else{
10361 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
10362 break;
10363 }
10364 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
10365 //printf("no-match due to different register (branch)\n");
57871462 10366 break;
10367 }
10368 }
e1190b87 10369 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10370 //printf("No free regs for store %x\n",start+j*4);
10371 break;
10372 }
57871462 10373 if(f_regmap[hr]>=64) {
10374 if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
10375 break;
10376 }
10377 else
10378 {
10379 if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
10380 break;
10381 }
10382 }
10383 }
10384 }
10385 }
10386 }
10387 }
10388 }
10389 }else{
198df76f 10390 // Non branch or undetermined branch target
57871462 10391 for(hr=0;hr<HOST_REGS;hr++)
10392 {
10393 if(hr!=EXCLUDE_REG) {
10394 if(regs[i].regmap[hr]>64) {
10395 if(!((regs[i].dirty>>hr)&1))
10396 f_regmap[hr]=regs[i].regmap[hr];
10397 }
b372a952 10398 else if(regs[i].regmap[hr]>=0) {
10399 if(f_regmap[hr]!=regs[i].regmap[hr]) {
10400 // dealloc old register
10401 int n;
10402 for(n=0;n<HOST_REGS;n++)
10403 {
10404 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10405 }
10406 // and alloc new one
10407 f_regmap[hr]=regs[i].regmap[hr];
10408 }
10409 }
57871462 10410 }
10411 }
10412 // Try to restore cycle count at branch targets
10413 if(bt[i]) {
10414 for(j=i;j<slen-1;j++) {
10415 if(regs[j].regmap[HOST_CCREG]!=-1) break;
e1190b87 10416 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10417 //printf("no free regs for store %x\n",start+j*4);
10418 break;
57871462 10419 }
57871462 10420 }
10421 if(regs[j].regmap[HOST_CCREG]==CCREG) {
10422 int k=i;
10423 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
10424 while(k<j) {
10425 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10426 regs[k].regmap[HOST_CCREG]=CCREG;
10427 regmap_pre[k+1][HOST_CCREG]=CCREG;
10428 regs[k+1].wasdirty|=1<<HOST_CCREG;
10429 regs[k].dirty|=1<<HOST_CCREG;
10430 regs[k].wasconst&=~(1<<HOST_CCREG);
10431 regs[k].isconst&=~(1<<HOST_CCREG);
10432 k++;
10433 }
10434 regs[j].regmap_entry[HOST_CCREG]=CCREG;
10435 }
10436 // Work backwards from the branch target
10437 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
10438 {
10439 //printf("Extend backwards\n");
10440 int k;
10441 k=i;
10442 while(regs[k-1].regmap[HOST_CCREG]==-1) {
e1190b87 10443 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10444 //printf("no free regs for store %x\n",start+(k-1)*4);
10445 break;
57871462 10446 }
57871462 10447 k--;
10448 }
10449 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
10450 //printf("Extend CC, %x ->\n",start+k*4);
10451 while(k<=i) {
10452 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10453 regs[k].regmap[HOST_CCREG]=CCREG;
10454 regmap_pre[k+1][HOST_CCREG]=CCREG;
10455 regs[k+1].wasdirty|=1<<HOST_CCREG;
10456 regs[k].dirty|=1<<HOST_CCREG;
10457 regs[k].wasconst&=~(1<<HOST_CCREG);
10458 regs[k].isconst&=~(1<<HOST_CCREG);
10459 k++;
10460 }
10461 }
10462 else {
10463 //printf("Fail Extend CC, %x ->\n",start+k*4);
10464 }
10465 }
10466 }
10467 if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
10468 itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
10469 itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
e1190b87 10470 itype[i]!=FCONV&&itype[i]!=FCOMP)
57871462 10471 {
10472 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
10473 }
10474 }
10475 }
10476
d61de97e 10477 // Cache memory offset or tlb map pointer if a register is available
10478 #ifndef HOST_IMM_ADDR32
10479 #ifndef RAM_OFFSET
10480 if(using_tlb)
10481 #endif
10482 {
10483 int earliest_available[HOST_REGS];
10484 int loop_start[HOST_REGS];
10485 int score[HOST_REGS];
10486 int end[HOST_REGS];
10487 int reg=using_tlb?MMREG:ROREG;
10488
10489 // Init
10490 for(hr=0;hr<HOST_REGS;hr++) {
10491 score[hr]=0;earliest_available[hr]=0;
10492 loop_start[hr]=MAXBLOCK;
10493 }
10494 for(i=0;i<slen-1;i++)
10495 {
10496 // Can't do anything if no registers are available
10497 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i]) {
10498 for(hr=0;hr<HOST_REGS;hr++) {
10499 score[hr]=0;earliest_available[hr]=i+1;
10500 loop_start[hr]=MAXBLOCK;
10501 }
10502 }
10503 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10504 if(!ooo[i]) {
10505 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) {
10506 for(hr=0;hr<HOST_REGS;hr++) {
10507 score[hr]=0;earliest_available[hr]=i+1;
10508 loop_start[hr]=MAXBLOCK;
10509 }
10510 }
198df76f 10511 }else{
10512 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) {
10513 for(hr=0;hr<HOST_REGS;hr++) {
10514 score[hr]=0;earliest_available[hr]=i+1;
10515 loop_start[hr]=MAXBLOCK;
10516 }
10517 }
d61de97e 10518 }
10519 }
10520 // Mark unavailable registers
10521 for(hr=0;hr<HOST_REGS;hr++) {
10522 if(regs[i].regmap[hr]>=0) {
10523 score[hr]=0;earliest_available[hr]=i+1;
10524 loop_start[hr]=MAXBLOCK;
10525 }
10526 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10527 if(branch_regs[i].regmap[hr]>=0) {
10528 score[hr]=0;earliest_available[hr]=i+2;
10529 loop_start[hr]=MAXBLOCK;
10530 }
10531 }
10532 }
10533 // No register allocations after unconditional jumps
10534 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10535 {
10536 for(hr=0;hr<HOST_REGS;hr++) {
10537 score[hr]=0;earliest_available[hr]=i+2;
10538 loop_start[hr]=MAXBLOCK;
10539 }
10540 i++; // Skip delay slot too
10541 //printf("skip delay slot: %x\n",start+i*4);
10542 }
10543 else
10544 // Possible match
10545 if(itype[i]==LOAD||itype[i]==LOADLR||
10546 itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) {
10547 for(hr=0;hr<HOST_REGS;hr++) {
10548 if(hr!=EXCLUDE_REG) {
10549 end[hr]=i-1;
10550 for(j=i;j<slen-1;j++) {
10551 if(regs[j].regmap[hr]>=0) break;
10552 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10553 if(branch_regs[j].regmap[hr]>=0) break;
10554 if(ooo[j]) {
10555 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) break;
10556 }else{
10557 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) break;
10558 }
10559 }
10560 else if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) break;
10561 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10562 int t=(ba[j]-start)>>2;
10563 if(t<j&&t>=earliest_available[hr]) {
198df76f 10564 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) { // call/ret assumes no registers allocated
10565 // Score a point for hoisting loop invariant
10566 if(t<loop_start[hr]) loop_start[hr]=t;
10567 //printf("set loop_start: i=%x j=%x (%x)\n",start+i*4,start+j*4,start+t*4);
10568 score[hr]++;
10569 end[hr]=j;
10570 }
d61de97e 10571 }
10572 else if(t<j) {
10573 if(regs[t].regmap[hr]==reg) {
10574 // Score a point if the branch target matches this register
10575 score[hr]++;
10576 end[hr]=j;
10577 }
10578 }
10579 if(itype[j+1]==LOAD||itype[j+1]==LOADLR||
10580 itype[j+1]==STORE||itype[j+1]==STORELR||itype[j+1]==C1LS) {
10581 score[hr]++;
10582 end[hr]=j;
10583 }
10584 }
10585 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10586 {
10587 // Stop on unconditional branch
10588 break;
10589 }
10590 else
10591 if(itype[j]==LOAD||itype[j]==LOADLR||
10592 itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS) {
10593 score[hr]++;
10594 end[hr]=j;
10595 }
10596 }
10597 }
10598 }
10599 // Find highest score and allocate that register
10600 int maxscore=0;
10601 for(hr=0;hr<HOST_REGS;hr++) {
10602 if(hr!=EXCLUDE_REG) {
10603 if(score[hr]>score[maxscore]) {
10604 maxscore=hr;
10605 //printf("highest score: %d %d (%x->%x)\n",score[hr],hr,start+i*4,start+end[hr]*4);
10606 }
10607 }
10608 }
10609 if(score[maxscore]>1)
10610 {
10611 if(i<loop_start[maxscore]) loop_start[maxscore]=i;
10612 for(j=loop_start[maxscore];j<slen&&j<=end[maxscore];j++) {
10613 //if(regs[j].regmap[maxscore]>=0) {printf("oops: %x %x was %d=%d\n",loop_start[maxscore]*4+start,j*4+start,maxscore,regs[j].regmap[maxscore]);}
10614 assert(regs[j].regmap[maxscore]<0);
10615 if(j>loop_start[maxscore]) regs[j].regmap_entry[maxscore]=reg;
10616 regs[j].regmap[maxscore]=reg;
10617 regs[j].dirty&=~(1<<maxscore);
10618 regs[j].wasconst&=~(1<<maxscore);
10619 regs[j].isconst&=~(1<<maxscore);
10620 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10621 branch_regs[j].regmap[maxscore]=reg;
10622 branch_regs[j].wasdirty&=~(1<<maxscore);
10623 branch_regs[j].dirty&=~(1<<maxscore);
10624 branch_regs[j].wasconst&=~(1<<maxscore);
10625 branch_regs[j].isconst&=~(1<<maxscore);
10626 if(itype[j]!=RJUMP&&itype[j]!=UJUMP&&(source[j]>>16)!=0x1000) {
10627 regmap_pre[j+2][maxscore]=reg;
10628 regs[j+2].wasdirty&=~(1<<maxscore);
10629 }
10630 // loop optimization (loop_preload)
10631 int t=(ba[j]-start)>>2;
198df76f 10632 if(t==loop_start[maxscore]) {
10633 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) // call/ret assumes no registers allocated
10634 regs[t].regmap_entry[maxscore]=reg;
10635 }
d61de97e 10636 }
10637 else
10638 {
10639 if(j<1||(itype[j-1]!=RJUMP&&itype[j-1]!=UJUMP&&itype[j-1]!=CJUMP&&itype[j-1]!=SJUMP&&itype[j-1]!=FJUMP)) {
10640 regmap_pre[j+1][maxscore]=reg;
10641 regs[j+1].wasdirty&=~(1<<maxscore);
10642 }
10643 }
10644 }
10645 i=j-1;
10646 if(itype[j-1]==RJUMP||itype[j-1]==UJUMP||itype[j-1]==CJUMP||itype[j-1]==SJUMP||itype[j-1]==FJUMP) i++; // skip delay slot
10647 for(hr=0;hr<HOST_REGS;hr++) {
10648 score[hr]=0;earliest_available[hr]=i+i;
10649 loop_start[hr]=MAXBLOCK;
10650 }
10651 }
10652 }
10653 }
10654 }
10655 #endif
10656
57871462 10657 // This allocates registers (if possible) one instruction prior
10658 // to use, which can avoid a load-use penalty on certain CPUs.
10659 for(i=0;i<slen-1;i++)
10660 {
10661 if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10662 {
10663 if(!bt[i+1])
10664 {
b9b61529 10665 if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
10666 ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
57871462 10667 {
10668 if(rs1[i+1]) {
10669 if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10670 {
10671 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10672 {
10673 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10674 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10675 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10676 regs[i].isconst&=~(1<<hr);
10677 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10678 constmap[i][hr]=constmap[i+1][hr];
10679 regs[i+1].wasdirty&=~(1<<hr);
10680 regs[i].dirty&=~(1<<hr);
10681 }
10682 }
10683 }
10684 if(rs2[i+1]) {
10685 if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10686 {
10687 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10688 {
10689 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10690 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10691 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10692 regs[i].isconst&=~(1<<hr);
10693 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10694 constmap[i][hr]=constmap[i+1][hr];
10695 regs[i+1].wasdirty&=~(1<<hr);
10696 regs[i].dirty&=~(1<<hr);
10697 }
10698 }
10699 }
198df76f 10700 // Preload target address for load instruction (non-constant)
57871462 10701 if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10702 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10703 {
10704 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10705 {
10706 regs[i].regmap[hr]=rs1[i+1];
10707 regmap_pre[i+1][hr]=rs1[i+1];
10708 regs[i+1].regmap_entry[hr]=rs1[i+1];
10709 regs[i].isconst&=~(1<<hr);
10710 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10711 constmap[i][hr]=constmap[i+1][hr];
10712 regs[i+1].wasdirty&=~(1<<hr);
10713 regs[i].dirty&=~(1<<hr);
10714 }
10715 }
10716 }
198df76f 10717 // Load source into target register
57871462 10718 if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10719 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10720 {
10721 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10722 {
10723 regs[i].regmap[hr]=rs1[i+1];
10724 regmap_pre[i+1][hr]=rs1[i+1];
10725 regs[i+1].regmap_entry[hr]=rs1[i+1];
10726 regs[i].isconst&=~(1<<hr);
10727 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10728 constmap[i][hr]=constmap[i+1][hr];
10729 regs[i+1].wasdirty&=~(1<<hr);
10730 regs[i].dirty&=~(1<<hr);
10731 }
10732 }
10733 }
198df76f 10734 // Preload map address
57871462 10735 #ifndef HOST_IMM_ADDR32
b9b61529 10736 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
57871462 10737 hr=get_reg(regs[i+1].regmap,TLREG);
10738 if(hr>=0) {
10739 int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10740 if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10741 int nr;
10742 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10743 {
10744 regs[i].regmap[hr]=MGEN1+((i+1)&1);
10745 regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10746 regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10747 regs[i].isconst&=~(1<<hr);
10748 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10749 constmap[i][hr]=constmap[i+1][hr];
10750 regs[i+1].wasdirty&=~(1<<hr);
10751 regs[i].dirty&=~(1<<hr);
10752 }
10753 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10754 {
10755 // move it to another register
10756 regs[i+1].regmap[hr]=-1;
10757 regmap_pre[i+2][hr]=-1;
10758 regs[i+1].regmap[nr]=TLREG;
10759 regmap_pre[i+2][nr]=TLREG;
10760 regs[i].regmap[nr]=MGEN1+((i+1)&1);
10761 regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10762 regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10763 regs[i].isconst&=~(1<<nr);
10764 regs[i+1].isconst&=~(1<<nr);
10765 regs[i].dirty&=~(1<<nr);
10766 regs[i+1].wasdirty&=~(1<<nr);
10767 regs[i+1].dirty&=~(1<<nr);
10768 regs[i+2].wasdirty&=~(1<<nr);
10769 }
10770 }
10771 }
10772 }
10773 #endif
198df76f 10774 // Address for store instruction (non-constant)
b9b61529 10775 if(itype[i+1]==STORE||itype[i+1]==STORELR
10776 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
57871462 10777 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10778 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10779 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10780 else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10781 assert(hr>=0);
10782 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10783 {
10784 regs[i].regmap[hr]=rs1[i+1];
10785 regmap_pre[i+1][hr]=rs1[i+1];
10786 regs[i+1].regmap_entry[hr]=rs1[i+1];
10787 regs[i].isconst&=~(1<<hr);
10788 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10789 constmap[i][hr]=constmap[i+1][hr];
10790 regs[i+1].wasdirty&=~(1<<hr);
10791 regs[i].dirty&=~(1<<hr);
10792 }
10793 }
10794 }
b9b61529 10795 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
57871462 10796 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10797 int nr;
10798 hr=get_reg(regs[i+1].regmap,FTEMP);
10799 assert(hr>=0);
10800 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10801 {
10802 regs[i].regmap[hr]=rs1[i+1];
10803 regmap_pre[i+1][hr]=rs1[i+1];
10804 regs[i+1].regmap_entry[hr]=rs1[i+1];
10805 regs[i].isconst&=~(1<<hr);
10806 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10807 constmap[i][hr]=constmap[i+1][hr];
10808 regs[i+1].wasdirty&=~(1<<hr);
10809 regs[i].dirty&=~(1<<hr);
10810 }
10811 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10812 {
10813 // move it to another register
10814 regs[i+1].regmap[hr]=-1;
10815 regmap_pre[i+2][hr]=-1;
10816 regs[i+1].regmap[nr]=FTEMP;
10817 regmap_pre[i+2][nr]=FTEMP;
10818 regs[i].regmap[nr]=rs1[i+1];
10819 regmap_pre[i+1][nr]=rs1[i+1];
10820 regs[i+1].regmap_entry[nr]=rs1[i+1];
10821 regs[i].isconst&=~(1<<nr);
10822 regs[i+1].isconst&=~(1<<nr);
10823 regs[i].dirty&=~(1<<nr);
10824 regs[i+1].wasdirty&=~(1<<nr);
10825 regs[i+1].dirty&=~(1<<nr);
10826 regs[i+2].wasdirty&=~(1<<nr);
10827 }
10828 }
10829 }
b9b61529 10830 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
57871462 10831 if(itype[i+1]==LOAD)
10832 hr=get_reg(regs[i+1].regmap,rt1[i+1]);
b9b61529 10833 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
57871462 10834 hr=get_reg(regs[i+1].regmap,FTEMP);
b9b61529 10835 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
57871462 10836 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10837 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10838 }
10839 if(hr>=0&&regs[i].regmap[hr]<0) {
10840 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10841 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10842 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10843 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10844 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10845 regs[i].isconst&=~(1<<hr);
10846 regs[i+1].wasdirty&=~(1<<hr);
10847 regs[i].dirty&=~(1<<hr);
10848 }
10849 }
10850 }
10851 }
10852 }
10853 }
10854 }
10855
10856 /* Pass 6 - Optimize clean/dirty state */
10857 clean_registers(0,slen-1,1);
10858
10859 /* Pass 7 - Identify 32-bit registers */
a28c6ce8 10860#ifndef FORCE32
57871462 10861 provisional_r32();
10862
10863 u_int r32=0;
10864
10865 for (i=slen-1;i>=0;i--)
10866 {
10867 int hr;
10868 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10869 {
10870 if(ba[i]<start || ba[i]>=(start+slen*4))
10871 {
10872 // Branch out of this block, don't need anything
10873 r32=0;
10874 }
10875 else
10876 {
10877 // Internal branch
10878 // Need whatever matches the target
10879 // (and doesn't get overwritten by the delay slot instruction)
10880 r32=0;
10881 int t=(ba[i]-start)>>2;
10882 if(ba[i]>start+i*4) {
10883 // Forward branch
10884 if(!(requires_32bit[t]&~regs[i].was32))
10885 r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10886 }else{
10887 // Backward branch
10888 //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10889 // r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10890 if(!(pr32[t]&~regs[i].was32))
10891 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10892 }
10893 }
10894 // Conditional branch may need registers for following instructions
10895 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10896 {
10897 if(i<slen-2) {
10898 r32|=requires_32bit[i+2];
10899 r32&=regs[i].was32;
10900 // Mark this address as a branch target since it may be called
10901 // upon return from interrupt
10902 bt[i+2]=1;
10903 }
10904 }
10905 // Merge in delay slot
10906 if(!likely[i]) {
10907 // These are overwritten unless the branch is "likely"
10908 // and the delay slot is nullified if not taken
10909 r32&=~(1LL<<rt1[i+1]);
10910 r32&=~(1LL<<rt2[i+1]);
10911 }
10912 // Assume these are needed (delay slot)
10913 if(us1[i+1]>0)
10914 {
10915 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10916 }
10917 if(us2[i+1]>0)
10918 {
10919 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10920 }
10921 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10922 {
10923 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10924 }
10925 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10926 {
10927 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10928 }
10929 }
1e973cb0 10930 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 10931 {
10932 // SYSCALL instruction (software interrupt)
10933 r32=0;
10934 }
10935 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10936 {
10937 // ERET instruction (return from interrupt)
10938 r32=0;
10939 }
10940 // Check 32 bits
10941 r32&=~(1LL<<rt1[i]);
10942 r32&=~(1LL<<rt2[i]);
10943 if(us1[i]>0)
10944 {
10945 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10946 }
10947 if(us2[i]>0)
10948 {
10949 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10950 }
10951 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
10952 {
10953 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
10954 }
10955 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
10956 {
10957 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
10958 }
10959 requires_32bit[i]=r32;
10960
10961 // Dirty registers which are 32-bit, require 32-bit input
10962 // as they will be written as 32-bit values
10963 for(hr=0;hr<HOST_REGS;hr++)
10964 {
10965 if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
10966 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
10967 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
10968 requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
10969 }
10970 }
10971 }
10972 //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
10973 }
04fd948a 10974#else
10975 for (i=slen-1;i>=0;i--)
10976 {
10977 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10978 {
10979 // Conditional branch
10980 if((source[i]>>16)!=0x1000&&i<slen-2) {
10981 // Mark this address as a branch target since it may be called
10982 // upon return from interrupt
10983 bt[i+2]=1;
10984 }
10985 }
10986 }
a28c6ce8 10987#endif
57871462 10988
10989 if(itype[slen-1]==SPAN) {
10990 bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
10991 }
4600ba03 10992
10993#ifdef DISASM
57871462 10994 /* Debug/disassembly */
57871462 10995 for(i=0;i<slen;i++)
10996 {
10997 printf("U:");
10998 int r;
10999 for(r=1;r<=CCREG;r++) {
11000 if((unneeded_reg[i]>>r)&1) {
11001 if(r==HIREG) printf(" HI");
11002 else if(r==LOREG) printf(" LO");
11003 else printf(" r%d",r);
11004 }
11005 }
90ae6d4e 11006#ifndef FORCE32
57871462 11007 printf(" UU:");
11008 for(r=1;r<=CCREG;r++) {
11009 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
11010 if(r==HIREG) printf(" HI");
11011 else if(r==LOREG) printf(" LO");
11012 else printf(" r%d",r);
11013 }
11014 }
11015 printf(" 32:");
11016 for(r=0;r<=CCREG;r++) {
11017 //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
11018 if((regs[i].was32>>r)&1) {
11019 if(r==CCREG) printf(" CC");
11020 else if(r==HIREG) printf(" HI");
11021 else if(r==LOREG) printf(" LO");
11022 else printf(" r%d",r);
11023 }
11024 }
90ae6d4e 11025#endif
57871462 11026 printf("\n");
11027 #if defined(__i386__) || defined(__x86_64__)
11028 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
11029 #endif
11030 #ifdef __arm__
11031 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
11032 #endif
11033 printf("needs: ");
11034 if(needed_reg[i]&1) printf("eax ");
11035 if((needed_reg[i]>>1)&1) printf("ecx ");
11036 if((needed_reg[i]>>2)&1) printf("edx ");
11037 if((needed_reg[i]>>3)&1) printf("ebx ");
11038 if((needed_reg[i]>>5)&1) printf("ebp ");
11039 if((needed_reg[i]>>6)&1) printf("esi ");
11040 if((needed_reg[i]>>7)&1) printf("edi ");
11041 printf("r:");
11042 for(r=0;r<=CCREG;r++) {
11043 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
11044 if((requires_32bit[i]>>r)&1) {
11045 if(r==CCREG) printf(" CC");
11046 else if(r==HIREG) printf(" HI");
11047 else if(r==LOREG) printf(" LO");
11048 else printf(" r%d",r);
11049 }
11050 }
11051 printf("\n");
11052 /*printf("pr:");
11053 for(r=0;r<=CCREG;r++) {
11054 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
11055 if((pr32[i]>>r)&1) {
11056 if(r==CCREG) printf(" CC");
11057 else if(r==HIREG) printf(" HI");
11058 else if(r==LOREG) printf(" LO");
11059 else printf(" r%d",r);
11060 }
11061 }
11062 if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
11063 printf("\n");*/
11064 #if defined(__i386__) || defined(__x86_64__)
11065 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
11066 printf("dirty: ");
11067 if(regs[i].wasdirty&1) printf("eax ");
11068 if((regs[i].wasdirty>>1)&1) printf("ecx ");
11069 if((regs[i].wasdirty>>2)&1) printf("edx ");
11070 if((regs[i].wasdirty>>3)&1) printf("ebx ");
11071 if((regs[i].wasdirty>>5)&1) printf("ebp ");
11072 if((regs[i].wasdirty>>6)&1) printf("esi ");
11073 if((regs[i].wasdirty>>7)&1) printf("edi ");
11074 #endif
11075 #ifdef __arm__
11076 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
11077 printf("dirty: ");
11078 if(regs[i].wasdirty&1) printf("r0 ");
11079 if((regs[i].wasdirty>>1)&1) printf("r1 ");
11080 if((regs[i].wasdirty>>2)&1) printf("r2 ");
11081 if((regs[i].wasdirty>>3)&1) printf("r3 ");
11082 if((regs[i].wasdirty>>4)&1) printf("r4 ");
11083 if((regs[i].wasdirty>>5)&1) printf("r5 ");
11084 if((regs[i].wasdirty>>6)&1) printf("r6 ");
11085 if((regs[i].wasdirty>>7)&1) printf("r7 ");
11086 if((regs[i].wasdirty>>8)&1) printf("r8 ");
11087 if((regs[i].wasdirty>>9)&1) printf("r9 ");
11088 if((regs[i].wasdirty>>10)&1) printf("r10 ");
11089 if((regs[i].wasdirty>>12)&1) printf("r12 ");
11090 #endif
11091 printf("\n");
11092 disassemble_inst(i);
11093 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
11094 #if defined(__i386__) || defined(__x86_64__)
11095 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
11096 if(regs[i].dirty&1) printf("eax ");
11097 if((regs[i].dirty>>1)&1) printf("ecx ");
11098 if((regs[i].dirty>>2)&1) printf("edx ");
11099 if((regs[i].dirty>>3)&1) printf("ebx ");
11100 if((regs[i].dirty>>5)&1) printf("ebp ");
11101 if((regs[i].dirty>>6)&1) printf("esi ");
11102 if((regs[i].dirty>>7)&1) printf("edi ");
11103 #endif
11104 #ifdef __arm__
11105 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
11106 if(regs[i].dirty&1) printf("r0 ");
11107 if((regs[i].dirty>>1)&1) printf("r1 ");
11108 if((regs[i].dirty>>2)&1) printf("r2 ");
11109 if((regs[i].dirty>>3)&1) printf("r3 ");
11110 if((regs[i].dirty>>4)&1) printf("r4 ");
11111 if((regs[i].dirty>>5)&1) printf("r5 ");
11112 if((regs[i].dirty>>6)&1) printf("r6 ");
11113 if((regs[i].dirty>>7)&1) printf("r7 ");
11114 if((regs[i].dirty>>8)&1) printf("r8 ");
11115 if((regs[i].dirty>>9)&1) printf("r9 ");
11116 if((regs[i].dirty>>10)&1) printf("r10 ");
11117 if((regs[i].dirty>>12)&1) printf("r12 ");
11118 #endif
11119 printf("\n");
11120 if(regs[i].isconst) {
11121 printf("constants: ");
11122 #if defined(__i386__) || defined(__x86_64__)
11123 if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
11124 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
11125 if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
11126 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
11127 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
11128 if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
11129 if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
11130 #endif
11131 #ifdef __arm__
11132 if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
11133 if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
11134 if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
11135 if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
11136 if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
11137 if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
11138 if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
11139 if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
11140 if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
11141 if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
11142 if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
11143 if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
11144 #endif
11145 printf("\n");
11146 }
90ae6d4e 11147#ifndef FORCE32
57871462 11148 printf(" 32:");
11149 for(r=0;r<=CCREG;r++) {
11150 if((regs[i].is32>>r)&1) {
11151 if(r==CCREG) printf(" CC");
11152 else if(r==HIREG) printf(" HI");
11153 else if(r==LOREG) printf(" LO");
11154 else printf(" r%d",r);
11155 }
11156 }
11157 printf("\n");
90ae6d4e 11158#endif
57871462 11159 /*printf(" p32:");
11160 for(r=0;r<=CCREG;r++) {
11161 if((p32[i]>>r)&1) {
11162 if(r==CCREG) printf(" CC");
11163 else if(r==HIREG) printf(" HI");
11164 else if(r==LOREG) printf(" LO");
11165 else printf(" r%d",r);
11166 }
11167 }
11168 if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
11169 else printf("\n");*/
11170 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
11171 #if defined(__i386__) || defined(__x86_64__)
11172 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
11173 if(branch_regs[i].dirty&1) printf("eax ");
11174 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
11175 if((branch_regs[i].dirty>>2)&1) printf("edx ");
11176 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
11177 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
11178 if((branch_regs[i].dirty>>6)&1) printf("esi ");
11179 if((branch_regs[i].dirty>>7)&1) printf("edi ");
11180 #endif
11181 #ifdef __arm__
11182 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
11183 if(branch_regs[i].dirty&1) printf("r0 ");
11184 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
11185 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
11186 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
11187 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
11188 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
11189 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
11190 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
11191 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
11192 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
11193 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
11194 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
11195 #endif
90ae6d4e 11196#ifndef FORCE32
57871462 11197 printf(" 32:");
11198 for(r=0;r<=CCREG;r++) {
11199 if((branch_regs[i].is32>>r)&1) {
11200 if(r==CCREG) printf(" CC");
11201 else if(r==HIREG) printf(" HI");
11202 else if(r==LOREG) printf(" LO");
11203 else printf(" r%d",r);
11204 }
11205 }
11206 printf("\n");
90ae6d4e 11207#endif
57871462 11208 }
11209 }
4600ba03 11210#endif // DISASM
57871462 11211
11212 /* Pass 8 - Assembly */
11213 linkcount=0;stubcount=0;
11214 ds=0;is_delayslot=0;
11215 cop1_usable=0;
11216 uint64_t is32_pre=0;
11217 u_int dirty_pre=0;
11218 u_int beginning=(u_int)out;
11219 if((u_int)addr&1) {
11220 ds=1;
11221 pagespan_ds();
11222 }
9ad4d757 11223 u_int instr_addr0_override=0;
11224
11225#ifdef PCSX
11226 if (start == 0x80030000) {
11227 // nasty hack for fastbios thing
96186eba 11228 // override block entry to this code
9ad4d757 11229 instr_addr0_override=(u_int)out;
11230 emit_movimm(start,0);
96186eba 11231 // abuse io address var as a flag that we
11232 // have already returned here once
11233 emit_readword((int)&address,1);
9ad4d757 11234 emit_writeword(0,(int)&pcaddr);
96186eba 11235 emit_writeword(0,(int)&address);
9ad4d757 11236 emit_cmp(0,1);
11237 emit_jne((int)new_dyna_leave);
11238 }
11239#endif
57871462 11240 for(i=0;i<slen;i++)
11241 {
11242 //if(ds) printf("ds: ");
4600ba03 11243 disassemble_inst(i);
57871462 11244 if(ds) {
11245 ds=0; // Skip delay slot
11246 if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
11247 instr_addr[i]=0;
11248 } else {
ffb0b9e0 11249 speculate_register_values(i);
57871462 11250 #ifndef DESTRUCTIVE_WRITEBACK
11251 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11252 {
11253 wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
11254 unneeded_reg[i],unneeded_reg_upper[i]);
11255 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
11256 unneeded_reg[i],unneeded_reg_upper[i]);
11257 }
f776eb14 11258 if((itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)&&!likely[i]) {
11259 is32_pre=branch_regs[i].is32;
11260 dirty_pre=branch_regs[i].dirty;
11261 }else{
11262 is32_pre=regs[i].is32;
11263 dirty_pre=regs[i].dirty;
11264 }
57871462 11265 #endif
11266 // write back
11267 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11268 {
11269 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
11270 unneeded_reg[i],unneeded_reg_upper[i]);
11271 loop_preload(regmap_pre[i],regs[i].regmap_entry);
11272 }
11273 // branch target entry point
11274 instr_addr[i]=(u_int)out;
11275 assem_debug("<->\n");
11276 // load regs
11277 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
11278 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
11279 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
11280 address_generation(i,&regs[i],regs[i].regmap_entry);
11281 load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
11282 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
11283 {
11284 // Load the delay slot registers if necessary
4ef8f67d 11285 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i]&&(rs1[i+1]!=rt1[i]||rt1[i]==0))
57871462 11286 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
4ef8f67d 11287 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i]&&(rs2[i+1]!=rt1[i]||rt1[i]==0))
57871462 11288 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
b9b61529 11289 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
57871462 11290 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11291 }
11292 else if(i+1<slen)
11293 {
11294 // Preload registers for following instruction
11295 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
11296 if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
11297 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11298 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
11299 if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
11300 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11301 }
11302 // TODO: if(is_ooo(i)) address_generation(i+1);
11303 if(itype[i]==CJUMP||itype[i]==FJUMP)
11304 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
b9b61529 11305 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
57871462 11306 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11307 if(bt[i]) cop1_usable=0;
11308 // assemble
11309 switch(itype[i]) {
11310 case ALU:
11311 alu_assemble(i,&regs[i]);break;
11312 case IMM16:
11313 imm16_assemble(i,&regs[i]);break;
11314 case SHIFT:
11315 shift_assemble(i,&regs[i]);break;
11316 case SHIFTIMM:
11317 shiftimm_assemble(i,&regs[i]);break;
11318 case LOAD:
11319 load_assemble(i,&regs[i]);break;
11320 case LOADLR:
11321 loadlr_assemble(i,&regs[i]);break;
11322 case STORE:
11323 store_assemble(i,&regs[i]);break;
11324 case STORELR:
11325 storelr_assemble(i,&regs[i]);break;
11326 case COP0:
11327 cop0_assemble(i,&regs[i]);break;
11328 case COP1:
11329 cop1_assemble(i,&regs[i]);break;
11330 case C1LS:
11331 c1ls_assemble(i,&regs[i]);break;
b9b61529 11332 case COP2:
11333 cop2_assemble(i,&regs[i]);break;
11334 case C2LS:
11335 c2ls_assemble(i,&regs[i]);break;
11336 case C2OP:
11337 c2op_assemble(i,&regs[i]);break;
57871462 11338 case FCONV:
11339 fconv_assemble(i,&regs[i]);break;
11340 case FLOAT:
11341 float_assemble(i,&regs[i]);break;
11342 case FCOMP:
11343 fcomp_assemble(i,&regs[i]);break;
11344 case MULTDIV:
11345 multdiv_assemble(i,&regs[i]);break;
11346 case MOV:
11347 mov_assemble(i,&regs[i]);break;
11348 case SYSCALL:
11349 syscall_assemble(i,&regs[i]);break;
7139f3c8 11350 case HLECALL:
11351 hlecall_assemble(i,&regs[i]);break;
1e973cb0 11352 case INTCALL:
11353 intcall_assemble(i,&regs[i]);break;
57871462 11354 case UJUMP:
11355 ujump_assemble(i,&regs[i]);ds=1;break;
11356 case RJUMP:
11357 rjump_assemble(i,&regs[i]);ds=1;break;
11358 case CJUMP:
11359 cjump_assemble(i,&regs[i]);ds=1;break;
11360 case SJUMP:
11361 sjump_assemble(i,&regs[i]);ds=1;break;
11362 case FJUMP:
11363 fjump_assemble(i,&regs[i]);ds=1;break;
11364 case SPAN:
11365 pagespan_assemble(i,&regs[i]);break;
11366 }
11367 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
11368 literal_pool(1024);
11369 else
11370 literal_pool_jumpover(256);
11371 }
11372 }
11373 //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
11374 // If the block did not end with an unconditional branch,
11375 // add a jump to the next instruction.
11376 if(i>1) {
11377 if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
11378 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11379 assert(i==slen);
11380 if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
11381 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11382 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11383 emit_loadreg(CCREG,HOST_CCREG);
2573466a 11384 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
57871462 11385 }
11386 else if(!likely[i-2])
11387 {
11388 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
11389 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
11390 }
11391 else
11392 {
11393 store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
11394 assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
11395 }
11396 add_to_linker((int)out,start+i*4,0);
11397 emit_jmp(0);
11398 }
11399 }
11400 else
11401 {
11402 assert(i>0);
11403 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11404 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11405 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11406 emit_loadreg(CCREG,HOST_CCREG);
2573466a 11407 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
57871462 11408 add_to_linker((int)out,start+i*4,0);
11409 emit_jmp(0);
11410 }
11411
11412 // TODO: delay slot stubs?
11413 // Stubs
11414 for(i=0;i<stubcount;i++)
11415 {
11416 switch(stubs[i][0])
11417 {
11418 case LOADB_STUB:
11419 case LOADH_STUB:
11420 case LOADW_STUB:
11421 case LOADD_STUB:
11422 case LOADBU_STUB:
11423 case LOADHU_STUB:
11424 do_readstub(i);break;
11425 case STOREB_STUB:
11426 case STOREH_STUB:
11427 case STOREW_STUB:
11428 case STORED_STUB:
11429 do_writestub(i);break;
11430 case CC_STUB:
11431 do_ccstub(i);break;
11432 case INVCODE_STUB:
11433 do_invstub(i);break;
11434 case FP_STUB:
11435 do_cop1stub(i);break;
11436 case STORELR_STUB:
11437 do_unalignedwritestub(i);break;
11438 }
11439 }
11440
9ad4d757 11441 if (instr_addr0_override)
11442 instr_addr[0] = instr_addr0_override;
11443
57871462 11444 /* Pass 9 - Linker */
11445 for(i=0;i<linkcount;i++)
11446 {
11447 assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
11448 literal_pool(64);
11449 if(!link_addr[i][2])
11450 {
11451 void *stub=out;
11452 void *addr=check_addr(link_addr[i][1]);
11453 emit_extjump(link_addr[i][0],link_addr[i][1]);
11454 if(addr) {
11455 set_jump_target(link_addr[i][0],(int)addr);
11456 add_link(link_addr[i][1],stub);
11457 }
11458 else set_jump_target(link_addr[i][0],(int)stub);
11459 }
11460 else
11461 {
11462 // Internal branch
11463 int target=(link_addr[i][1]-start)>>2;
11464 assert(target>=0&&target<slen);
11465 assert(instr_addr[target]);
11466 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11467 //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
11468 //#else
11469 set_jump_target(link_addr[i][0],instr_addr[target]);
11470 //#endif
11471 }
11472 }
11473 // External Branch Targets (jump_in)
11474 if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
11475 for(i=0;i<slen;i++)
11476 {
11477 if(bt[i]||i==0)
11478 {
11479 if(instr_addr[i]) // TODO - delay slots (=null)
11480 {
11481 u_int vaddr=start+i*4;
94d23bb9 11482 u_int page=get_page(vaddr);
11483 u_int vpage=get_vpage(vaddr);
57871462 11484 literal_pool(256);
11485 //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
a28c6ce8 11486#ifndef FORCE32
57871462 11487 if(!requires_32bit[i])
a28c6ce8 11488#else
11489 if(1)
11490#endif
57871462 11491 {
11492 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11493 assem_debug("jump_in: %x\n",start+i*4);
11494 ll_add(jump_dirty+vpage,vaddr,(void *)out);
11495 int entry_point=do_dirty_stub(i);
11496 ll_add(jump_in+page,vaddr,(void *)entry_point);
11497 // If there was an existing entry in the hash table,
11498 // replace it with the new address.
11499 // Don't add new entries. We'll insert the
11500 // ones that actually get used in check_addr().
11501 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
11502 if(ht_bin[0]==vaddr) {
11503 ht_bin[1]=entry_point;
11504 }
11505 if(ht_bin[2]==vaddr) {
11506 ht_bin[3]=entry_point;
11507 }
11508 }
11509 else
11510 {
11511 u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
11512 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11513 assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
11514 //int entry_point=(int)out;
11515 ////assem_debug("entry_point: %x\n",entry_point);
11516 //load_regs_entry(i);
11517 //if(entry_point==(int)out)
11518 // entry_point=instr_addr[i];
11519 //else
11520 // emit_jmp(instr_addr[i]);
11521 //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11522 ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
11523 int entry_point=do_dirty_stub(i);
11524 ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11525 }
11526 }
11527 }
11528 }
11529 // Write out the literal pool if necessary
11530 literal_pool(0);
11531 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11532 // Align code
11533 if(((u_int)out)&7) emit_addnop(13);
11534 #endif
11535 assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
11536 //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
11537 memcpy(copy,source,slen*4);
11538 copy+=slen*4;
11539
11540 #ifdef __arm__
11541 __clear_cache((void *)beginning,out);
11542 #endif
11543
11544 // If we're within 256K of the end of the buffer,
11545 // start over from the beginning. (Is 256K enough?)
11546 if((int)out>BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
11547
11548 // Trap writes to any of the pages we compiled
11549 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
11550 invalid_code[i]=0;
90ae6d4e 11551#ifndef DISABLE_TLB
57871462 11552 memory_map[i]|=0x40000000;
11553 if((signed int)start>=(signed int)0xC0000000) {
11554 assert(using_tlb);
11555 j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
11556 invalid_code[j]=0;
11557 memory_map[j]|=0x40000000;
11558 //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
11559 }
90ae6d4e 11560#endif
57871462 11561 }
9be4ba64 11562 inv_code_start=inv_code_end=~0;
b12c9fb8 11563#ifdef PCSX
b96d3df7 11564 // for PCSX we need to mark all mirrors too
b12c9fb8 11565 if(get_page(start)<(RAM_SIZE>>12))
11566 for(i=start>>12;i<=(start+slen*4)>>12;i++)
b96d3df7 11567 invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]=
11568 invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]=
11569 invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0;
b12c9fb8 11570#endif
57871462 11571
11572 /* Pass 10 - Free memory by expiring oldest blocks */
11573
11574 int end=((((int)out-BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
11575 while(expirep!=end)
11576 {
11577 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
11578 int base=BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
11579 inv_debug("EXP: Phase %d\n",expirep);
11580 switch((expirep>>11)&3)
11581 {
11582 case 0:
11583 // Clear jump_in and jump_dirty
11584 ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
11585 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
11586 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
11587 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
11588 break;
11589 case 1:
11590 // Clear pointers
11591 ll_kill_pointers(jump_out[expirep&2047],base,shift);
11592 ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
11593 break;
11594 case 2:
11595 // Clear hash table
11596 for(i=0;i<32;i++) {
11597 int *ht_bin=hash_table[((expirep&2047)<<5)+i];
11598 if((ht_bin[3]>>shift)==(base>>shift) ||
11599 ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11600 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
11601 ht_bin[2]=ht_bin[3]=-1;
11602 }
11603 if((ht_bin[1]>>shift)==(base>>shift) ||
11604 ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11605 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
11606 ht_bin[0]=ht_bin[2];
11607 ht_bin[1]=ht_bin[3];
11608 ht_bin[2]=ht_bin[3]=-1;
11609 }
11610 }
11611 break;
11612 case 3:
11613 // Clear jump_out
dd3a91a1 11614 #ifdef __arm__
11615 if((expirep&2047)==0)
11616 do_clear_cache();
11617 #endif
57871462 11618 ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
11619 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
11620 break;
11621 }
11622 expirep=(expirep+1)&65535;
11623 }
11624 return 0;
11625}
b9b61529 11626
11627// vim:shiftwidth=2:expandtab
ARM optimized PCSX fork