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drc: fix CCREG loading
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
CommitLineData
57871462 1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
20d507ba 3 * Copyright (C) 2009-2011 Ari64 *
57871462 4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21#include <stdlib.h>
22#include <stdint.h> //include for uint64_t
23#include <assert.h>
d848b60a 24#include <errno.h>
4600ba03 25#include <sys/mman.h>
d148d265 26#ifdef __MACH__
27#include <libkern/OSCacheControl.h>
28#endif
1e212a25 29#ifdef _3DS
30#include <3ds_utils.h>
31#endif
32#ifdef VITA
33#include <psp2/kernel/sysmem.h>
34static int sceBlock;
35#endif
57871462 36
d148d265 37#include "new_dynarec_config.h"
3968e69e 38#include "../psxhle.h"
39#include "../psxinterpreter.h"
81dbbf4c 40#include "../gte.h"
41#include "emu_if.h" // emulator interface
57871462 42
d1e4ebd9 43#define noinline __attribute__((noinline,noclone))
b14b6a8f 44#ifndef ARRAY_SIZE
45#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
46#endif
e3c6bdb5 47#ifndef min
48#define min(a, b) ((b) < (a) ? (b) : (a))
49#endif
32631e6a 50#ifndef max
51#define max(a, b) ((b) > (a) ? (b) : (a))
52#endif
b14b6a8f 53
4600ba03 54//#define DISASM
32631e6a 55//#define ASSEM_PRINT
56
57#ifdef ASSEM_PRINT
58#define assem_debug printf
59#else
4600ba03 60#define assem_debug(...)
32631e6a 61#endif
62//#define inv_debug printf
4600ba03 63#define inv_debug(...)
57871462 64
65#ifdef __i386__
66#include "assem_x86.h"
67#endif
68#ifdef __x86_64__
69#include "assem_x64.h"
70#endif
71#ifdef __arm__
72#include "assem_arm.h"
73#endif
be516ebe 74#ifdef __aarch64__
75#include "assem_arm64.h"
76#endif
57871462 77
81dbbf4c 78#define RAM_SIZE 0x200000
57871462 79#define MAXBLOCK 4096
80#define MAX_OUTPUT_BLOCK_SIZE 262144
2573466a 81
2a014d73 82struct ndrc_mem
83{
84 u_char translation_cache[1 << TARGET_SIZE_2];
85 struct
86 {
87 struct tramp_insns ops[2048 / sizeof(struct tramp_insns)];
88 const void *f[2048 / sizeof(void *)];
89 } tramp;
90};
91
92#ifdef BASE_ADDR_DYNAMIC
93static struct ndrc_mem *ndrc;
94#else
95static struct ndrc_mem ndrc_ __attribute__((aligned(4096)));
96static struct ndrc_mem *ndrc = &ndrc_;
97#endif
98
b14b6a8f 99// stubs
100enum stub_type {
101 CC_STUB = 1,
102 FP_STUB = 2,
103 LOADB_STUB = 3,
104 LOADH_STUB = 4,
105 LOADW_STUB = 5,
106 LOADD_STUB = 6,
107 LOADBU_STUB = 7,
108 LOADHU_STUB = 8,
109 STOREB_STUB = 9,
110 STOREH_STUB = 10,
111 STOREW_STUB = 11,
112 STORED_STUB = 12,
113 STORELR_STUB = 13,
114 INVCODE_STUB = 14,
115};
116
57871462 117struct regstat
118{
2330734f 119 signed char regmap_entry[HOST_REGS]; // pre-insn + loop preloaded regs?
57871462 120 signed char regmap[HOST_REGS];
57871462 121 uint64_t wasdirty;
122 uint64_t dirty;
123 uint64_t u;
57871462 124 u_int wasconst;
125 u_int isconst;
8575a877 126 u_int loadedconst; // host regs that have constants loaded
127 u_int waswritten; // MIPS regs that were used as store base before
57871462 128};
129
de5a60c3 130// note: asm depends on this layout
57871462 131struct ll_entry
132{
133 u_int vaddr;
de5a60c3 134 u_int reg_sv_flags;
57871462 135 void *addr;
136 struct ll_entry *next;
137};
138
df4dc2b1 139struct ht_entry
140{
141 u_int vaddr[2];
142 void *tcaddr[2];
143};
144
b14b6a8f 145struct code_stub
146{
147 enum stub_type type;
148 void *addr;
149 void *retaddr;
150 u_int a;
151 uintptr_t b;
152 uintptr_t c;
153 u_int d;
154 u_int e;
155};
156
643aeae3 157struct link_entry
158{
159 void *addr;
160 u_int target;
161 u_int ext;
162};
163
cf95b4f0 164static struct decoded_insn
165{
166 u_char itype;
167 u_char opcode;
168 u_char opcode2;
169 u_char rs1;
170 u_char rs2;
171 u_char rt1;
172 u_char rt2;
173 u_char lt1;
174 u_char bt:1;
cf95b4f0 175 u_char ooo:1;
176 u_char is_ds:1;
fe807a8a 177 u_char is_jump:1;
178 u_char is_ujump:1;
37387d8b 179 u_char is_load:1;
180 u_char is_store:1;
cf95b4f0 181} dops[MAXBLOCK];
182
e2b5e7aa 183 // used by asm:
184 u_char *out;
df4dc2b1 185 struct ht_entry hash_table[65536] __attribute__((aligned(16)));
e2b5e7aa 186 struct ll_entry *jump_in[4096] __attribute__((aligned(16)));
187 struct ll_entry *jump_dirty[4096];
188
189 static struct ll_entry *jump_out[4096];
190 static u_int start;
191 static u_int *source;
192 static char insn[MAXBLOCK][10];
bedfea38 193 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
194 static uint64_t gte_rt[MAXBLOCK];
195 static uint64_t gte_unneeded[MAXBLOCK];
ffb0b9e0 196 static u_int smrv[32]; // speculated MIPS register values
197 static u_int smrv_strong; // mask or regs that are likely to have correct values
198 static u_int smrv_weak; // same, but somewhat less likely
199 static u_int smrv_strong_next; // same, but after current insn executes
200 static u_int smrv_weak_next;
e2b5e7aa 201 static int imm[MAXBLOCK];
202 static u_int ba[MAXBLOCK];
e2b5e7aa 203 static uint64_t unneeded_reg[MAXBLOCK];
e2b5e7aa 204 static uint64_t branch_unneeded_reg[MAXBLOCK];
2330734f 205 // pre-instruction [i], excluding loop-preload regs?
206 static signed char regmap_pre[MAXBLOCK][HOST_REGS];
40fca85b 207 // contains 'real' consts at [i] insn, but may differ from what's actually
208 // loaded in host reg as 'final' value is always loaded, see get_final_value()
209 static uint32_t current_constmap[HOST_REGS];
210 static uint32_t constmap[MAXBLOCK][HOST_REGS];
956f3129 211 static struct regstat regs[MAXBLOCK];
212 static struct regstat branch_regs[MAXBLOCK];
e2b5e7aa 213 static signed char minimum_free_regs[MAXBLOCK];
214 static u_int needed_reg[MAXBLOCK];
215 static u_int wont_dirty[MAXBLOCK];
216 static u_int will_dirty[MAXBLOCK];
217 static int ccadj[MAXBLOCK];
218 static int slen;
df4dc2b1 219 static void *instr_addr[MAXBLOCK];
643aeae3 220 static struct link_entry link_addr[MAXBLOCK];
e2b5e7aa 221 static int linkcount;
b14b6a8f 222 static struct code_stub stubs[MAXBLOCK*3];
e2b5e7aa 223 static int stubcount;
224 static u_int literals[1024][2];
225 static int literalcount;
226 static int is_delayslot;
e2b5e7aa 227 static char shadow[1048576] __attribute__((aligned(16)));
228 static void *copy;
229 static int expirep;
230 static u_int stop_after_jal;
39b71d9a 231 static u_int f1_hack; // 0 - off, ~0 - capture address, else addr
e2b5e7aa 232
233 int new_dynarec_hacks;
d62c125a 234 int new_dynarec_hacks_pergame;
32631e6a 235 int new_dynarec_hacks_old;
e2b5e7aa 236 int new_dynarec_did_compile;
687b4580 237
d62c125a 238 #define HACK_ENABLED(x) ((new_dynarec_hacks | new_dynarec_hacks_pergame) & (x))
239
687b4580 240 extern int cycle_count; // ... until end of the timeslice, counts -N -> 0
241 extern int last_count; // last absolute target, often = next_interupt
242 extern int pcaddr;
243 extern int pending_exception;
244 extern int branch_target;
37387d8b 245 extern uintptr_t ram_offset;
d1e4ebd9 246 extern uintptr_t mini_ht[32][2];
57871462 247 extern u_char restore_candidate[512];
57871462 248
249 /* registers that may be allocated */
250 /* 1-31 gpr */
7c3a5182 251#define LOREG 32 // lo
252#define HIREG 33 // hi
00fa9369 253//#define FSREG 34 // FPU status (FCSR)
57871462 254#define CSREG 35 // Coprocessor status
255#define CCREG 36 // Cycle count
256#define INVCP 37 // Pointer to invalid_code
1edfcc68 257//#define MMREG 38 // Pointer to memory_map
37387d8b 258#define ROREG 39 // ram offset (if rdram!=0x80000000)
619e5ded 259#define TEMPREG 40
260#define FTEMP 40 // FPU temporary register
261#define PTEMP 41 // Prefetch temporary register
1edfcc68 262//#define TLREG 42 // TLB mapping offset
619e5ded 263#define RHASH 43 // Return address hash
264#define RHTBL 44 // Return address hash table address
265#define RTEMP 45 // JR/JALR address register
266#define MAXREG 45
267#define AGEN1 46 // Address generation temporary register
1edfcc68 268//#define AGEN2 47 // Address generation temporary register
269//#define MGEN1 48 // Maptable address generation temporary register
270//#define MGEN2 49 // Maptable address generation temporary register
619e5ded 271#define BTREG 50 // Branch target temporary register
57871462 272
273 /* instruction types */
274#define NOP 0 // No operation
275#define LOAD 1 // Load
276#define STORE 2 // Store
277#define LOADLR 3 // Unaligned load
278#define STORELR 4 // Unaligned store
9f51b4b9 279#define MOV 5 // Move
57871462 280#define ALU 6 // Arithmetic/logic
281#define MULTDIV 7 // Multiply/divide
282#define SHIFT 8 // Shift by register
283#define SHIFTIMM 9// Shift by immediate
284#define IMM16 10 // 16-bit immediate
285#define RJUMP 11 // Unconditional jump to register
286#define UJUMP 12 // Unconditional jump
287#define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
288#define SJUMP 14 // Conditional branch (regimm format)
289#define COP0 15 // Coprocessor 0
290#define COP1 16 // Coprocessor 1
291#define C1LS 17 // Coprocessor 1 load/store
ad49de89 292//#define FJUMP 18 // Conditional branch (floating point)
00fa9369 293//#define FLOAT 19 // Floating point unit
294//#define FCONV 20 // Convert integer to float
295//#define FCOMP 21 // Floating point compare (sets FSREG)
57871462 296#define SYSCALL 22// SYSCALL
297#define OTHER 23 // Other
298#define SPAN 24 // Branch/delay slot spans 2 pages
299#define NI 25 // Not implemented
7139f3c8 300#define HLECALL 26// PCSX fake opcodes for HLE
b9b61529 301#define COP2 27 // Coprocessor 2 move
302#define C2LS 28 // Coprocessor 2 load/store
303#define C2OP 29 // Coprocessor 2 operation
1e973cb0 304#define INTCALL 30// Call interpreter to handle rare corner cases
57871462 305
57871462 306 /* branch codes */
307#define TAKEN 1
308#define NOTTAKEN 2
309#define NULLDS 3
310
7c3a5182 311#define DJT_1 (void *)1l // no function, just a label in assem_debug log
312#define DJT_2 (void *)2l
313
57871462 314// asm linkage
3968e69e 315int new_recompile_block(u_int addr);
57871462 316void *get_addr_ht(u_int vaddr);
317void invalidate_block(u_int block);
318void invalidate_addr(u_int addr);
319void remove_hash(int vaddr);
57871462 320void dyna_linker();
321void dyna_linker_ds();
322void verify_code();
57871462 323void verify_code_ds();
324void cc_interrupt();
325void fp_exception();
326void fp_exception_ds();
3968e69e 327void jump_to_new_pc();
81dbbf4c 328void call_gteStall();
7139f3c8 329void new_dyna_leave();
57871462 330
57871462 331// Needed by assembler
2330734f 332static void wb_register(signed char r, const signed char regmap[], uint64_t dirty);
333static void wb_dirtys(const signed char i_regmap[], uint64_t i_dirty);
334static void wb_needed_dirtys(const signed char i_regmap[], uint64_t i_dirty, int addr);
335static void load_all_regs(const signed char i_regmap[]);
336static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[]);
e2b5e7aa 337static void load_regs_entry(int t);
2330734f 338static void load_all_consts(const signed char regmap[], u_int dirty, int i);
81dbbf4c 339static u_int get_host_reglist(const signed char *regmap);
e2b5e7aa 340
3968e69e 341static int verify_dirty(const u_int *ptr);
e2b5e7aa 342static int get_final_value(int hr, int i, int *value);
b14b6a8f 343static void add_stub(enum stub_type type, void *addr, void *retaddr,
344 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e);
345static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
81dbbf4c 346 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist);
643aeae3 347static void add_to_linker(void *addr, u_int target, int ext);
37387d8b 348static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs,
349 int addr, int *offset_reg, int *addr_reg_override);
687b4580 350static void *get_direct_memhandler(void *table, u_int addr,
351 enum stub_type type, uintptr_t *addr_host);
32631e6a 352static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist);
687b4580 353static void pass_args(int a0, int a1);
2a014d73 354static void emit_far_jump(const void *f);
355static void emit_far_call(const void *f);
57871462 356
d148d265 357static void mprotect_w_x(void *start, void *end, int is_x)
358{
359#ifdef NO_WRITE_EXEC
1e212a25 360 #if defined(VITA)
361 // *Open* enables write on all memory that was
362 // allocated by sceKernelAllocMemBlockForVM()?
363 if (is_x)
364 sceKernelCloseVMDomain();
365 else
366 sceKernelOpenVMDomain();
367 #else
d148d265 368 u_long mstart = (u_long)start & ~4095ul;
369 u_long mend = (u_long)end;
370 if (mprotect((void *)mstart, mend - mstart,
371 PROT_READ | (is_x ? PROT_EXEC : PROT_WRITE)) != 0)
372 SysPrintf("mprotect(%c) failed: %s\n", is_x ? 'x' : 'w', strerror(errno));
1e212a25 373 #endif
d148d265 374#endif
375}
376
377static void start_tcache_write(void *start, void *end)
378{
379 mprotect_w_x(start, end, 0);
380}
381
382static void end_tcache_write(void *start, void *end)
383{
919981d0 384#if defined(__arm__) || defined(__aarch64__)
d148d265 385 size_t len = (char *)end - (char *)start;
386 #if defined(__BLACKBERRY_QNX__)
387 msync(start, len, MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE);
388 #elif defined(__MACH__)
389 sys_cache_control(kCacheFunctionPrepareForExecution, start, len);
390 #elif defined(VITA)
1e212a25 391 sceKernelSyncVMDomain(sceBlock, start, len);
392 #elif defined(_3DS)
393 ctr_flush_invalidate_cache();
919981d0 394 #elif defined(__aarch64__)
395 // as of 2021, __clear_cache() is still broken on arm64
396 // so here is a custom one :(
397 clear_cache_arm64(start, end);
d148d265 398 #else
399 __clear_cache(start, end);
400 #endif
401 (void)len;
402#endif
403
404 mprotect_w_x(start, end, 1);
405}
406
407static void *start_block(void)
408{
409 u_char *end = out + MAX_OUTPUT_BLOCK_SIZE;
2a014d73 410 if (end > ndrc->translation_cache + sizeof(ndrc->translation_cache))
411 end = ndrc->translation_cache + sizeof(ndrc->translation_cache);
d148d265 412 start_tcache_write(out, end);
413 return out;
414}
415
416static void end_block(void *start)
417{
418 end_tcache_write(start, out);
419}
420
919981d0 421// also takes care of w^x mappings when patching code
422static u_int needs_clear_cache[1<<(TARGET_SIZE_2-17)];
423
424static void mark_clear_cache(void *target)
425{
426 uintptr_t offset = (u_char *)target - ndrc->translation_cache;
427 u_int mask = 1u << ((offset >> 12) & 31);
428 if (!(needs_clear_cache[offset >> 17] & mask)) {
429 char *start = (char *)((uintptr_t)target & ~4095l);
430 start_tcache_write(start, start + 4095);
431 needs_clear_cache[offset >> 17] |= mask;
432 }
433}
434
435// Clearing the cache is rather slow on ARM Linux, so mark the areas
436// that need to be cleared, and then only clear these areas once.
437static void do_clear_cache(void)
438{
439 int i, j;
440 for (i = 0; i < (1<<(TARGET_SIZE_2-17)); i++)
441 {
442 u_int bitmap = needs_clear_cache[i];
443 if (!bitmap)
444 continue;
445 for (j = 0; j < 32; j++)
446 {
447 u_char *start, *end;
448 if (!(bitmap & (1<<j)))
449 continue;
450
451 start = ndrc->translation_cache + i*131072 + j*4096;
452 end = start + 4095;
453 for (j++; j < 32; j++) {
454 if (!(bitmap & (1<<j)))
455 break;
456 end += 4096;
457 }
458 end_tcache_write(start, end);
459 }
460 needs_clear_cache[i] = 0;
461 }
462}
463
57871462 464//#define DEBUG_CYCLE_COUNT 1
465
b6e87b2b 466#define NO_CYCLE_PENALTY_THR 12
467
26bd3dad 468int cycle_multiplier = CYCLE_MULT_DEFAULT; // 100 for 1.0
a3203cf4 469int cycle_multiplier_override;
32631e6a 470int cycle_multiplier_old;
4e9dcd7f 471
472static int CLOCK_ADJUST(int x)
473{
26bd3dad 474 int m = cycle_multiplier_override && cycle_multiplier == CYCLE_MULT_DEFAULT
a3203cf4 475 ? cycle_multiplier_override : cycle_multiplier;
4e9dcd7f 476 int s=(x>>31)|1;
a3203cf4 477 return (x * m + s * 50) / 100;
4e9dcd7f 478}
479
4919de1e 480static int ds_writes_rjump_rs(int i)
481{
cf95b4f0 482 return dops[i].rs1 != 0 && (dops[i].rs1 == dops[i+1].rt1 || dops[i].rs1 == dops[i+1].rt2);
4919de1e 483}
484
94d23bb9 485static u_int get_page(u_int vaddr)
57871462 486{
0ce47d46 487 u_int page=vaddr&~0xe0000000;
488 if (page < 0x1000000)
489 page &= ~0x0e00000; // RAM mirrors
490 page>>=12;
57871462 491 if(page>2048) page=2048+(page&2047);
94d23bb9 492 return page;
493}
494
d25604ca 495// no virtual mem in PCSX
496static u_int get_vpage(u_int vaddr)
497{
498 return get_page(vaddr);
499}
94d23bb9 500
df4dc2b1 501static struct ht_entry *hash_table_get(u_int vaddr)
502{
503 return &hash_table[((vaddr>>16)^vaddr)&0xFFFF];
504}
505
506static void hash_table_add(struct ht_entry *ht_bin, u_int vaddr, void *tcaddr)
507{
508 ht_bin->vaddr[1] = ht_bin->vaddr[0];
509 ht_bin->tcaddr[1] = ht_bin->tcaddr[0];
510 ht_bin->vaddr[0] = vaddr;
511 ht_bin->tcaddr[0] = tcaddr;
512}
513
514// some messy ari64's code, seems to rely on unsigned 32bit overflow
515static int doesnt_expire_soon(void *tcaddr)
516{
517 u_int diff = (u_int)((u_char *)tcaddr - out) << (32-TARGET_SIZE_2);
518 return diff > (u_int)(0x60000000 + (MAX_OUTPUT_BLOCK_SIZE << (32-TARGET_SIZE_2)));
519}
520
94d23bb9 521// Get address from virtual address
522// This is called from the recompiled JR/JALR instructions
d1e4ebd9 523void noinline *get_addr(u_int vaddr)
94d23bb9 524{
525 u_int page=get_page(vaddr);
526 u_int vpage=get_vpage(vaddr);
57871462 527 struct ll_entry *head;
528 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
529 head=jump_in[page];
530 while(head!=NULL) {
de5a60c3 531 if(head->vaddr==vaddr) {
643aeae3 532 //printf("TRACE: count=%d next=%d (get_addr match %x: %p)\n",Count,next_interupt,vaddr,head->addr);
df4dc2b1 533 hash_table_add(hash_table_get(vaddr), vaddr, head->addr);
57871462 534 return head->addr;
535 }
536 head=head->next;
537 }
538 head=jump_dirty[vpage];
539 while(head!=NULL) {
de5a60c3 540 if(head->vaddr==vaddr) {
643aeae3 541 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %p)\n",Count,next_interupt,vaddr,head->addr);
57871462 542 // Don't restore blocks which are about to expire from the cache
df4dc2b1 543 if (doesnt_expire_soon(head->addr))
544 if (verify_dirty(head->addr)) {
57871462 545 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
546 invalid_code[vaddr>>12]=0;
9be4ba64 547 inv_code_start=inv_code_end=~0;
57871462 548 if(vpage<2048) {
57871462 549 restore_candidate[vpage>>3]|=1<<(vpage&7);
550 }
551 else restore_candidate[page>>3]|=1<<(page&7);
df4dc2b1 552 struct ht_entry *ht_bin = hash_table_get(vaddr);
553 if (ht_bin->vaddr[0] == vaddr)
554 ht_bin->tcaddr[0] = head->addr; // Replace existing entry
57871462 555 else
df4dc2b1 556 hash_table_add(ht_bin, vaddr, head->addr);
557
57871462 558 return head->addr;
559 }
560 }
561 head=head->next;
562 }
563 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
564 int r=new_recompile_block(vaddr);
565 if(r==0) return get_addr(vaddr);
566 // Execute in unmapped page, generate pagefault execption
567 Status|=2;
568 Cause=(vaddr<<31)|0x8;
569 EPC=(vaddr&1)?vaddr-5:vaddr;
570 BadVAddr=(vaddr&~1);
571 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
572 EntryHi=BadVAddr&0xFFFFE000;
573 return get_addr_ht(0x80000000);
574}
575// Look up address in hash table first
576void *get_addr_ht(u_int vaddr)
577{
578 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
df4dc2b1 579 const struct ht_entry *ht_bin = hash_table_get(vaddr);
580 if (ht_bin->vaddr[0] == vaddr) return ht_bin->tcaddr[0];
581 if (ht_bin->vaddr[1] == vaddr) return ht_bin->tcaddr[1];
57871462 582 return get_addr(vaddr);
583}
584
57871462 585void clear_all_regs(signed char regmap[])
586{
587 int hr;
588 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
589}
590
d1e4ebd9 591static signed char get_reg(const signed char regmap[],int r)
57871462 592{
593 int hr;
594 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
595 return -1;
596}
597
598// Find a register that is available for two consecutive cycles
d1e4ebd9 599static signed char get_reg2(signed char regmap1[], const signed char regmap2[], int r)
57871462 600{
601 int hr;
602 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
603 return -1;
604}
605
606int count_free_regs(signed char regmap[])
607{
608 int count=0;
609 int hr;
610 for(hr=0;hr<HOST_REGS;hr++)
611 {
612 if(hr!=EXCLUDE_REG) {
613 if(regmap[hr]<0) count++;
614 }
615 }
616 return count;
617}
618
619void dirty_reg(struct regstat *cur,signed char reg)
620{
621 int hr;
622 if(!reg) return;
623 for (hr=0;hr<HOST_REGS;hr++) {
624 if((cur->regmap[hr]&63)==reg) {
625 cur->dirty|=1<<hr;
626 }
627 }
628}
629
40fca85b 630static void set_const(struct regstat *cur, signed char reg, uint32_t value)
57871462 631{
632 int hr;
633 if(!reg) return;
634 for (hr=0;hr<HOST_REGS;hr++) {
635 if(cur->regmap[hr]==reg) {
636 cur->isconst|=1<<hr;
956f3129 637 current_constmap[hr]=value;
57871462 638 }
57871462 639 }
640}
641
40fca85b 642static void clear_const(struct regstat *cur, signed char reg)
57871462 643{
644 int hr;
645 if(!reg) return;
646 for (hr=0;hr<HOST_REGS;hr++) {
647 if((cur->regmap[hr]&63)==reg) {
648 cur->isconst&=~(1<<hr);
649 }
650 }
651}
652
40fca85b 653static int is_const(struct regstat *cur, signed char reg)
57871462 654{
655 int hr;
79c75f1b 656 if(reg<0) return 0;
57871462 657 if(!reg) return 1;
658 for (hr=0;hr<HOST_REGS;hr++) {
659 if((cur->regmap[hr]&63)==reg) {
660 return (cur->isconst>>hr)&1;
661 }
662 }
663 return 0;
664}
40fca85b 665
666static uint32_t get_const(struct regstat *cur, signed char reg)
57871462 667{
668 int hr;
669 if(!reg) return 0;
670 for (hr=0;hr<HOST_REGS;hr++) {
671 if(cur->regmap[hr]==reg) {
956f3129 672 return current_constmap[hr];
57871462 673 }
674 }
c43b5311 675 SysPrintf("Unknown constant in r%d\n",reg);
7c3a5182 676 abort();
57871462 677}
678
679// Least soon needed registers
680// Look at the next ten instructions and see which registers
681// will be used. Try not to reallocate these.
682void lsn(u_char hsn[], int i, int *preferred_reg)
683{
684 int j;
685 int b=-1;
686 for(j=0;j<9;j++)
687 {
688 if(i+j>=slen) {
689 j=slen-i-1;
690 break;
691 }
fe807a8a 692 if (dops[i+j].is_ujump)
57871462 693 {
694 // Don't go past an unconditonal jump
695 j++;
696 break;
697 }
698 }
699 for(;j>=0;j--)
700 {
cf95b4f0 701 if(dops[i+j].rs1) hsn[dops[i+j].rs1]=j;
702 if(dops[i+j].rs2) hsn[dops[i+j].rs2]=j;
703 if(dops[i+j].rt1) hsn[dops[i+j].rt1]=j;
704 if(dops[i+j].rt2) hsn[dops[i+j].rt2]=j;
705 if(dops[i+j].itype==STORE || dops[i+j].itype==STORELR) {
57871462 706 // Stores can allocate zero
cf95b4f0 707 hsn[dops[i+j].rs1]=j;
708 hsn[dops[i+j].rs2]=j;
57871462 709 }
37387d8b 710 if (ram_offset && (dops[i+j].is_load || dops[i+j].is_store))
711 hsn[ROREG] = j;
57871462 712 // On some architectures stores need invc_ptr
713 #if defined(HOST_IMM8)
37387d8b 714 if (dops[i+j].is_store)
715 hsn[INVCP] = j;
57871462 716 #endif
cf95b4f0 717 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
57871462 718 {
719 hsn[CCREG]=j;
720 b=j;
721 }
722 }
723 if(b>=0)
724 {
725 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
726 {
727 // Follow first branch
728 int t=(ba[i+b]-start)>>2;
729 j=7-b;if(t+j>=slen) j=slen-t-1;
730 for(;j>=0;j--)
731 {
cf95b4f0 732 if(dops[t+j].rs1) if(hsn[dops[t+j].rs1]>j+b+2) hsn[dops[t+j].rs1]=j+b+2;
733 if(dops[t+j].rs2) if(hsn[dops[t+j].rs2]>j+b+2) hsn[dops[t+j].rs2]=j+b+2;
734 //if(dops[t+j].rt1) if(hsn[dops[t+j].rt1]>j+b+2) hsn[dops[t+j].rt1]=j+b+2;
735 //if(dops[t+j].rt2) if(hsn[dops[t+j].rt2]>j+b+2) hsn[dops[t+j].rt2]=j+b+2;
57871462 736 }
737 }
738 // TODO: preferred register based on backward branch
739 }
740 // Delay slot should preferably not overwrite branch conditions or cycle count
fe807a8a 741 if (i > 0 && dops[i-1].is_jump) {
cf95b4f0 742 if(dops[i-1].rs1) if(hsn[dops[i-1].rs1]>1) hsn[dops[i-1].rs1]=1;
743 if(dops[i-1].rs2) if(hsn[dops[i-1].rs2]>1) hsn[dops[i-1].rs2]=1;
57871462 744 hsn[CCREG]=1;
745 // ...or hash tables
746 hsn[RHASH]=1;
747 hsn[RHTBL]=1;
748 }
749 // Coprocessor load/store needs FTEMP, even if not declared
37387d8b 750 if(dops[i].itype==C2LS) {
57871462 751 hsn[FTEMP]=0;
752 }
753 // Load L/R also uses FTEMP as a temporary register
cf95b4f0 754 if(dops[i].itype==LOADLR) {
57871462 755 hsn[FTEMP]=0;
756 }
b7918751 757 // Also SWL/SWR/SDL/SDR
cf95b4f0 758 if(dops[i].opcode==0x2a||dops[i].opcode==0x2e||dops[i].opcode==0x2c||dops[i].opcode==0x2d) {
57871462 759 hsn[FTEMP]=0;
760 }
57871462 761 // Don't remove the miniht registers
cf95b4f0 762 if(dops[i].itype==UJUMP||dops[i].itype==RJUMP)
57871462 763 {
764 hsn[RHASH]=0;
765 hsn[RHTBL]=0;
766 }
767}
768
769// We only want to allocate registers if we're going to use them again soon
770int needed_again(int r, int i)
771{
772 int j;
773 int b=-1;
774 int rn=10;
9f51b4b9 775
fe807a8a 776 if (i > 0 && dops[i-1].is_ujump)
57871462 777 {
778 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
779 return 0; // Don't need any registers if exiting the block
780 }
781 for(j=0;j<9;j++)
782 {
783 if(i+j>=slen) {
784 j=slen-i-1;
785 break;
786 }
fe807a8a 787 if (dops[i+j].is_ujump)
57871462 788 {
789 // Don't go past an unconditonal jump
790 j++;
791 break;
792 }
cf95b4f0 793 if(dops[i+j].itype==SYSCALL||dops[i+j].itype==HLECALL||dops[i+j].itype==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
57871462 794 {
795 break;
796 }
797 }
798 for(;j>=1;j--)
799 {
cf95b4f0 800 if(dops[i+j].rs1==r) rn=j;
801 if(dops[i+j].rs2==r) rn=j;
57871462 802 if((unneeded_reg[i+j]>>r)&1) rn=10;
cf95b4f0 803 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
57871462 804 {
805 b=j;
806 }
807 }
b7217e13 808 if(rn<10) return 1;
581335b0 809 (void)b;
57871462 810 return 0;
811}
812
813// Try to match register allocations at the end of a loop with those
814// at the beginning
815int loop_reg(int i, int r, int hr)
816{
817 int j,k;
818 for(j=0;j<9;j++)
819 {
820 if(i+j>=slen) {
821 j=slen-i-1;
822 break;
823 }
fe807a8a 824 if (dops[i+j].is_ujump)
57871462 825 {
826 // Don't go past an unconditonal jump
827 j++;
828 break;
829 }
830 }
831 k=0;
832 if(i>0){
cf95b4f0 833 if(dops[i-1].itype==UJUMP||dops[i-1].itype==CJUMP||dops[i-1].itype==SJUMP)
57871462 834 k--;
835 }
836 for(;k<j;k++)
837 {
00fa9369 838 assert(r < 64);
839 if((unneeded_reg[i+k]>>r)&1) return hr;
cf95b4f0 840 if(i+k>=0&&(dops[i+k].itype==UJUMP||dops[i+k].itype==CJUMP||dops[i+k].itype==SJUMP))
57871462 841 {
842 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
843 {
844 int t=(ba[i+k]-start)>>2;
845 int reg=get_reg(regs[t].regmap_entry,r);
846 if(reg>=0) return reg;
847 //reg=get_reg(regs[t+1].regmap_entry,r);
848 //if(reg>=0) return reg;
849 }
850 }
851 }
852 return hr;
853}
854
855
856// Allocate every register, preserving source/target regs
857void alloc_all(struct regstat *cur,int i)
858{
859 int hr;
9f51b4b9 860
57871462 861 for(hr=0;hr<HOST_REGS;hr++) {
862 if(hr!=EXCLUDE_REG) {
cf95b4f0 863 if(((cur->regmap[hr]&63)!=dops[i].rs1)&&((cur->regmap[hr]&63)!=dops[i].rs2)&&
864 ((cur->regmap[hr]&63)!=dops[i].rt1)&&((cur->regmap[hr]&63)!=dops[i].rt2))
57871462 865 {
866 cur->regmap[hr]=-1;
867 cur->dirty&=~(1<<hr);
868 }
869 // Don't need zeros
870 if((cur->regmap[hr]&63)==0)
871 {
872 cur->regmap[hr]=-1;
873 cur->dirty&=~(1<<hr);
874 }
875 }
876 }
877}
878
d1e4ebd9 879#ifndef NDEBUG
880static int host_tempreg_in_use;
881
882static void host_tempreg_acquire(void)
883{
884 assert(!host_tempreg_in_use);
885 host_tempreg_in_use = 1;
886}
887
888static void host_tempreg_release(void)
889{
890 host_tempreg_in_use = 0;
891}
892#else
893static void host_tempreg_acquire(void) {}
894static void host_tempreg_release(void) {}
895#endif
896
32631e6a 897#ifdef ASSEM_PRINT
8062d65a 898extern void gen_interupt();
899extern void do_insn_cmp();
d1e4ebd9 900#define FUNCNAME(f) { f, " " #f }
8062d65a 901static const struct {
d1e4ebd9 902 void *addr;
8062d65a 903 const char *name;
904} function_names[] = {
905 FUNCNAME(cc_interrupt),
906 FUNCNAME(gen_interupt),
907 FUNCNAME(get_addr_ht),
908 FUNCNAME(get_addr),
909 FUNCNAME(jump_handler_read8),
910 FUNCNAME(jump_handler_read16),
911 FUNCNAME(jump_handler_read32),
912 FUNCNAME(jump_handler_write8),
913 FUNCNAME(jump_handler_write16),
914 FUNCNAME(jump_handler_write32),
915 FUNCNAME(invalidate_addr),
3968e69e 916 FUNCNAME(jump_to_new_pc),
81dbbf4c 917 FUNCNAME(call_gteStall),
8062d65a 918 FUNCNAME(new_dyna_leave),
919 FUNCNAME(pcsx_mtc0),
920 FUNCNAME(pcsx_mtc0_ds),
32631e6a 921#ifdef DRC_DBG
8062d65a 922 FUNCNAME(do_insn_cmp),
32631e6a 923#endif
3968e69e 924#ifdef __arm__
925 FUNCNAME(verify_code),
926#endif
8062d65a 927};
928
d1e4ebd9 929static const char *func_name(const void *a)
8062d65a 930{
931 int i;
932 for (i = 0; i < sizeof(function_names)/sizeof(function_names[0]); i++)
933 if (function_names[i].addr == a)
934 return function_names[i].name;
935 return "";
936}
937#else
938#define func_name(x) ""
939#endif
940
57871462 941#ifdef __i386__
942#include "assem_x86.c"
943#endif
944#ifdef __x86_64__
945#include "assem_x64.c"
946#endif
947#ifdef __arm__
948#include "assem_arm.c"
949#endif
be516ebe 950#ifdef __aarch64__
951#include "assem_arm64.c"
952#endif
57871462 953
2a014d73 954static void *get_trampoline(const void *f)
955{
956 size_t i;
957
958 for (i = 0; i < ARRAY_SIZE(ndrc->tramp.f); i++) {
959 if (ndrc->tramp.f[i] == f || ndrc->tramp.f[i] == NULL)
960 break;
961 }
962 if (i == ARRAY_SIZE(ndrc->tramp.f)) {
963 SysPrintf("trampoline table is full, last func %p\n", f);
964 abort();
965 }
966 if (ndrc->tramp.f[i] == NULL) {
967 start_tcache_write(&ndrc->tramp.f[i], &ndrc->tramp.f[i + 1]);
968 ndrc->tramp.f[i] = f;
969 end_tcache_write(&ndrc->tramp.f[i], &ndrc->tramp.f[i + 1]);
970 }
971 return &ndrc->tramp.ops[i];
972}
973
974static void emit_far_jump(const void *f)
975{
976 if (can_jump_or_call(f)) {
977 emit_jmp(f);
978 return;
979 }
980
981 f = get_trampoline(f);
982 emit_jmp(f);
983}
984
985static void emit_far_call(const void *f)
986{
987 if (can_jump_or_call(f)) {
988 emit_call(f);
989 return;
990 }
991
992 f = get_trampoline(f);
993 emit_call(f);
994}
995
57871462 996// Add virtual address mapping to linked list
997void ll_add(struct ll_entry **head,int vaddr,void *addr)
998{
999 struct ll_entry *new_entry;
1000 new_entry=malloc(sizeof(struct ll_entry));
1001 assert(new_entry!=NULL);
1002 new_entry->vaddr=vaddr;
de5a60c3 1003 new_entry->reg_sv_flags=0;
57871462 1004 new_entry->addr=addr;
1005 new_entry->next=*head;
1006 *head=new_entry;
1007}
1008
de5a60c3 1009void ll_add_flags(struct ll_entry **head,int vaddr,u_int reg_sv_flags,void *addr)
57871462 1010{
7139f3c8 1011 ll_add(head,vaddr,addr);
de5a60c3 1012 (*head)->reg_sv_flags=reg_sv_flags;
57871462 1013}
1014
1015// Check if an address is already compiled
1016// but don't return addresses which are about to expire from the cache
1017void *check_addr(u_int vaddr)
1018{
df4dc2b1 1019 struct ht_entry *ht_bin = hash_table_get(vaddr);
1020 size_t i;
b14b6a8f 1021 for (i = 0; i < ARRAY_SIZE(ht_bin->vaddr); i++) {
df4dc2b1 1022 if (ht_bin->vaddr[i] == vaddr)
1023 if (doesnt_expire_soon((u_char *)ht_bin->tcaddr[i] - MAX_OUTPUT_BLOCK_SIZE))
1024 if (isclean(ht_bin->tcaddr[i]))
1025 return ht_bin->tcaddr[i];
57871462 1026 }
94d23bb9 1027 u_int page=get_page(vaddr);
57871462 1028 struct ll_entry *head;
1029 head=jump_in[page];
df4dc2b1 1030 while (head != NULL) {
1031 if (head->vaddr == vaddr) {
1032 if (doesnt_expire_soon(head->addr)) {
57871462 1033 // Update existing entry with current address
df4dc2b1 1034 if (ht_bin->vaddr[0] == vaddr) {
1035 ht_bin->tcaddr[0] = head->addr;
57871462 1036 return head->addr;
1037 }
df4dc2b1 1038 if (ht_bin->vaddr[1] == vaddr) {
1039 ht_bin->tcaddr[1] = head->addr;
57871462 1040 return head->addr;
1041 }
1042 // Insert into hash table with low priority.
1043 // Don't evict existing entries, as they are probably
1044 // addresses that are being accessed frequently.
df4dc2b1 1045 if (ht_bin->vaddr[0] == -1) {
1046 ht_bin->vaddr[0] = vaddr;
1047 ht_bin->tcaddr[0] = head->addr;
1048 }
1049 else if (ht_bin->vaddr[1] == -1) {
1050 ht_bin->vaddr[1] = vaddr;
1051 ht_bin->tcaddr[1] = head->addr;
57871462 1052 }
1053 return head->addr;
1054 }
1055 }
1056 head=head->next;
1057 }
1058 return 0;
1059}
1060
1061void remove_hash(int vaddr)
1062{
1063 //printf("remove hash: %x\n",vaddr);
df4dc2b1 1064 struct ht_entry *ht_bin = hash_table_get(vaddr);
1065 if (ht_bin->vaddr[1] == vaddr) {
1066 ht_bin->vaddr[1] = -1;
1067 ht_bin->tcaddr[1] = NULL;
57871462 1068 }
df4dc2b1 1069 if (ht_bin->vaddr[0] == vaddr) {
1070 ht_bin->vaddr[0] = ht_bin->vaddr[1];
1071 ht_bin->tcaddr[0] = ht_bin->tcaddr[1];
1072 ht_bin->vaddr[1] = -1;
1073 ht_bin->tcaddr[1] = NULL;
57871462 1074 }
1075}
1076
943f42f3 1077static void ll_remove_matching_addrs(struct ll_entry **head,
1078 uintptr_t base_offs_s, int shift)
57871462 1079{
1080 struct ll_entry *next;
1081 while(*head) {
943f42f3 1082 uintptr_t o1 = (u_char *)(*head)->addr - ndrc->translation_cache;
1083 uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
1084 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s)
57871462 1085 {
643aeae3 1086 inv_debug("EXP: Remove pointer to %p (%x)\n",(*head)->addr,(*head)->vaddr);
57871462 1087 remove_hash((*head)->vaddr);
1088 next=(*head)->next;
1089 free(*head);
1090 *head=next;
1091 }
1092 else
1093 {
1094 head=&((*head)->next);
1095 }
1096 }
1097}
1098
1099// Remove all entries from linked list
1100void ll_clear(struct ll_entry **head)
1101{
1102 struct ll_entry *cur;
1103 struct ll_entry *next;
581335b0 1104 if((cur=*head)) {
57871462 1105 *head=0;
1106 while(cur) {
1107 next=cur->next;
1108 free(cur);
1109 cur=next;
1110 }
1111 }
1112}
1113
1114// Dereference the pointers and remove if it matches
943f42f3 1115static void ll_kill_pointers(struct ll_entry *head,
1116 uintptr_t base_offs_s, int shift)
57871462 1117{
1118 while(head) {
943f42f3 1119 u_char *ptr = get_pointer(head->addr);
1120 uintptr_t o1 = ptr - ndrc->translation_cache;
1121 uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
1122 inv_debug("EXP: Lookup pointer to %p at %p (%x)\n",ptr,head->addr,head->vaddr);
1123 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s)
57871462 1124 {
643aeae3 1125 inv_debug("EXP: Kill pointer at %p (%x)\n",head->addr,head->vaddr);
d148d265 1126 void *host_addr=find_extjump_insn(head->addr);
919981d0 1127 mark_clear_cache(host_addr);
df4dc2b1 1128 set_jump_target(host_addr, head->addr);
57871462 1129 }
1130 head=head->next;
1131 }
1132}
1133
1134// This is called when we write to a compiled block (see do_invstub)
d1e4ebd9 1135static void invalidate_page(u_int page)
57871462 1136{
57871462 1137 struct ll_entry *head;
1138 struct ll_entry *next;
1139 head=jump_in[page];
1140 jump_in[page]=0;
1141 while(head!=NULL) {
1142 inv_debug("INVALIDATE: %x\n",head->vaddr);
1143 remove_hash(head->vaddr);
1144 next=head->next;
1145 free(head);
1146 head=next;
1147 }
1148 head=jump_out[page];
1149 jump_out[page]=0;
1150 while(head!=NULL) {
643aeae3 1151 inv_debug("INVALIDATE: kill pointer to %x (%p)\n",head->vaddr,head->addr);
d148d265 1152 void *host_addr=find_extjump_insn(head->addr);
919981d0 1153 mark_clear_cache(host_addr);
3d680478 1154 set_jump_target(host_addr, head->addr); // point back to dyna_linker
57871462 1155 next=head->next;
1156 free(head);
1157 head=next;
1158 }
57871462 1159}
9be4ba64 1160
1161static void invalidate_block_range(u_int block, u_int first, u_int last)
57871462 1162{
94d23bb9 1163 u_int page=get_page(block<<12);
57871462 1164 //printf("first=%d last=%d\n",first,last);
f76eeef9 1165 invalidate_page(page);
57871462 1166 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1167 assert(last<page+5);
1168 // Invalidate the adjacent pages if a block crosses a 4K boundary
1169 while(first<page) {
1170 invalidate_page(first);
1171 first++;
1172 }
1173 for(first=page+1;first<last;first++) {
1174 invalidate_page(first);
1175 }
919981d0 1176 do_clear_cache();
9f51b4b9 1177
57871462 1178 // Don't trap writes
1179 invalid_code[block]=1;
f76eeef9 1180
57871462 1181 #ifdef USE_MINI_HT
1182 memset(mini_ht,-1,sizeof(mini_ht));
1183 #endif
1184}
9be4ba64 1185
1186void invalidate_block(u_int block)
1187{
1188 u_int page=get_page(block<<12);
1189 u_int vpage=get_vpage(block<<12);
1190 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1191 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1192 u_int first,last;
1193 first=last=page;
1194 struct ll_entry *head;
1195 head=jump_dirty[vpage];
1196 //printf("page=%d vpage=%d\n",page,vpage);
1197 while(head!=NULL) {
9be4ba64 1198 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
01d26796 1199 u_char *start, *end;
1200 get_bounds(head->addr, &start, &end);
1201 //printf("start: %p end: %p\n", start, end);
1202 if (page < 2048 && start >= rdram && end < rdram+RAM_SIZE) {
1203 if (((start-rdram)>>12) <= page && ((end-1-rdram)>>12) >= page) {
1204 if ((((start-rdram)>>12)&2047) < first) first = ((start-rdram)>>12)&2047;
1205 if ((((end-1-rdram)>>12)&2047) > last) last = ((end-1-rdram)>>12)&2047;
9be4ba64 1206 }
1207 }
9be4ba64 1208 }
1209 head=head->next;
1210 }
1211 invalidate_block_range(block,first,last);
1212}
1213
57871462 1214void invalidate_addr(u_int addr)
1215{
9be4ba64 1216 //static int rhits;
1217 // this check is done by the caller
1218 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
d25604ca 1219 u_int page=get_vpage(addr);
9be4ba64 1220 if(page<2048) { // RAM
1221 struct ll_entry *head;
1222 u_int addr_min=~0, addr_max=0;
4a35de07 1223 u_int mask=RAM_SIZE-1;
1224 u_int addr_main=0x80000000|(addr&mask);
9be4ba64 1225 int pg1;
4a35de07 1226 inv_code_start=addr_main&~0xfff;
1227 inv_code_end=addr_main|0xfff;
9be4ba64 1228 pg1=page;
1229 if (pg1>0) {
1230 // must check previous page too because of spans..
1231 pg1--;
1232 inv_code_start-=0x1000;
1233 }
1234 for(;pg1<=page;pg1++) {
1235 for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
01d26796 1236 u_char *start_h, *end_h;
1237 u_int start, end;
1238 get_bounds(head->addr, &start_h, &end_h);
1239 start = (uintptr_t)start_h - ram_offset;
1240 end = (uintptr_t)end_h - ram_offset;
4a35de07 1241 if(start<=addr_main&&addr_main<end) {
9be4ba64 1242 if(start<addr_min) addr_min=start;
1243 if(end>addr_max) addr_max=end;
1244 }
4a35de07 1245 else if(addr_main<start) {
9be4ba64 1246 if(start<inv_code_end)
1247 inv_code_end=start-1;
1248 }
1249 else {
1250 if(end>inv_code_start)
1251 inv_code_start=end;
1252 }
1253 }
1254 }
1255 if (addr_min!=~0) {
1256 inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1257 inv_code_start=inv_code_end=~0;
1258 invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1259 return;
1260 }
1261 else {
4a35de07 1262 inv_code_start=(addr&~mask)|(inv_code_start&mask);
1263 inv_code_end=(addr&~mask)|(inv_code_end&mask);
d25604ca 1264 inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);
9be4ba64 1265 return;
d25604ca 1266 }
9be4ba64 1267 }
57871462 1268 invalidate_block(addr>>12);
1269}
9be4ba64 1270
dd3a91a1 1271// This is called when loading a save state.
1272// Anything could have changed, so invalidate everything.
919981d0 1273void invalidate_all_pages(void)
57871462 1274{
581335b0 1275 u_int page;
57871462 1276 for(page=0;page<4096;page++)
1277 invalidate_page(page);
1278 for(page=0;page<1048576;page++)
1279 if(!invalid_code[page]) {
1280 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1281 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1282 }
57871462 1283 #ifdef USE_MINI_HT
1284 memset(mini_ht,-1,sizeof(mini_ht));
1285 #endif
919981d0 1286 do_clear_cache();
57871462 1287}
1288
d1e4ebd9 1289static void do_invstub(int n)
1290{
1291 literal_pool(20);
1292 u_int reglist=stubs[n].a;
1293 set_jump_target(stubs[n].addr, out);
1294 save_regs(reglist);
1295 if(stubs[n].b!=0) emit_mov(stubs[n].b,0);
2a014d73 1296 emit_far_call(invalidate_addr);
d1e4ebd9 1297 restore_regs(reglist);
1298 emit_jmp(stubs[n].retaddr); // return address
1299}
1300
57871462 1301// Add an entry to jump_out after making a link
d1e4ebd9 1302// src should point to code by emit_extjump2()
3d680478 1303void add_jump_out(u_int vaddr,void *src)
57871462 1304{
94d23bb9 1305 u_int page=get_page(vaddr);
3d680478 1306 inv_debug("add_jump_out: %p -> %x (%d)\n",src,vaddr,page);
d1e4ebd9 1307 check_extjump2(src);
57871462 1308 ll_add(jump_out+page,vaddr,src);
3d680478 1309 //inv_debug("add_jump_out: to %p\n",get_pointer(src));
57871462 1310}
1311
1312// If a code block was found to be unmodified (bit was set in
1313// restore_candidate) and it remains unmodified (bit is clear
1314// in invalid_code) then move the entries for that 4K page from
1315// the dirty list to the clean list.
1316void clean_blocks(u_int page)
1317{
1318 struct ll_entry *head;
1319 inv_debug("INV: clean_blocks page=%d\n",page);
1320 head=jump_dirty[page];
1321 while(head!=NULL) {
1322 if(!invalid_code[head->vaddr>>12]) {
1323 // Don't restore blocks which are about to expire from the cache
df4dc2b1 1324 if (doesnt_expire_soon(head->addr)) {
581335b0 1325 if(verify_dirty(head->addr)) {
01d26796 1326 u_char *start, *end;
643aeae3 1327 //printf("Possibly Restore %x (%p)\n",head->vaddr, head->addr);
57871462 1328 u_int i;
1329 u_int inv=0;
01d26796 1330 get_bounds(head->addr, &start, &end);
1331 if (start - rdram < RAM_SIZE) {
1332 for (i = (start-rdram+0x80000000)>>12; i <= (end-1-rdram+0x80000000)>>12; i++) {
57871462 1333 inv|=invalid_code[i];
1334 }
1335 }
4cb76aa4 1336 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
57871462 1337 inv=1;
1338 }
1339 if(!inv) {
df4dc2b1 1340 void *clean_addr = get_clean_addr(head->addr);
1341 if (doesnt_expire_soon(clean_addr)) {
57871462 1342 u_int ppage=page;
643aeae3 1343 inv_debug("INV: Restored %x (%p/%p)\n",head->vaddr, head->addr, clean_addr);
57871462 1344 //printf("page=%x, addr=%x\n",page,head->vaddr);
1345 //assert(head->vaddr>>12==(page|0x80000));
de5a60c3 1346 ll_add_flags(jump_in+ppage,head->vaddr,head->reg_sv_flags,clean_addr);
df4dc2b1 1347 struct ht_entry *ht_bin = hash_table_get(head->vaddr);
1348 if (ht_bin->vaddr[0] == head->vaddr)
1349 ht_bin->tcaddr[0] = clean_addr; // Replace existing entry
1350 if (ht_bin->vaddr[1] == head->vaddr)
1351 ht_bin->tcaddr[1] = clean_addr; // Replace existing entry
57871462 1352 }
1353 }
1354 }
1355 }
1356 }
1357 head=head->next;
1358 }
1359}
1360
8062d65a 1361/* Register allocation */
1362
1363// Note: registers are allocated clean (unmodified state)
1364// if you intend to modify the register, you must call dirty_reg().
1365static void alloc_reg(struct regstat *cur,int i,signed char reg)
1366{
1367 int r,hr;
b7ec323c 1368 int preferred_reg = PREFERRED_REG_FIRST
1369 + reg % (PREFERRED_REG_LAST - PREFERRED_REG_FIRST + 1);
1370 if (reg == CCREG) preferred_reg = HOST_CCREG;
1371 if (reg == PTEMP || reg == FTEMP) preferred_reg = 12;
1372 assert(PREFERRED_REG_FIRST != EXCLUDE_REG && EXCLUDE_REG != HOST_REGS);
8062d65a 1373
1374 // Don't allocate unused registers
1375 if((cur->u>>reg)&1) return;
1376
1377 // see if it's already allocated
1378 for(hr=0;hr<HOST_REGS;hr++)
1379 {
1380 if(cur->regmap[hr]==reg) return;
1381 }
1382
1383 // Keep the same mapping if the register was already allocated in a loop
1384 preferred_reg = loop_reg(i,reg,preferred_reg);
1385
1386 // Try to allocate the preferred register
1387 if(cur->regmap[preferred_reg]==-1) {
1388 cur->regmap[preferred_reg]=reg;
1389 cur->dirty&=~(1<<preferred_reg);
1390 cur->isconst&=~(1<<preferred_reg);
1391 return;
1392 }
1393 r=cur->regmap[preferred_reg];
1394 assert(r < 64);
1395 if((cur->u>>r)&1) {
1396 cur->regmap[preferred_reg]=reg;
1397 cur->dirty&=~(1<<preferred_reg);
1398 cur->isconst&=~(1<<preferred_reg);
1399 return;
1400 }
1401
1402 // Clear any unneeded registers
1403 // We try to keep the mapping consistent, if possible, because it
1404 // makes branches easier (especially loops). So we try to allocate
1405 // first (see above) before removing old mappings. If this is not
1406 // possible then go ahead and clear out the registers that are no
1407 // longer needed.
1408 for(hr=0;hr<HOST_REGS;hr++)
1409 {
1410 r=cur->regmap[hr];
1411 if(r>=0) {
1412 assert(r < 64);
1413 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
1414 }
1415 }
b7ec323c 1416
8062d65a 1417 // Try to allocate any available register, but prefer
1418 // registers that have not been used recently.
b7ec323c 1419 if (i > 0) {
1420 for (hr = PREFERRED_REG_FIRST; ; ) {
1421 if (cur->regmap[hr] < 0) {
1422 int oldreg = regs[i-1].regmap[hr];
1423 if (oldreg < 0 || (oldreg != dops[i-1].rs1 && oldreg != dops[i-1].rs2
1424 && oldreg != dops[i-1].rt1 && oldreg != dops[i-1].rt2))
1425 {
8062d65a 1426 cur->regmap[hr]=reg;
1427 cur->dirty&=~(1<<hr);
1428 cur->isconst&=~(1<<hr);
1429 return;
1430 }
1431 }
b7ec323c 1432 hr++;
1433 if (hr == EXCLUDE_REG)
1434 hr++;
1435 if (hr == HOST_REGS)
1436 hr = 0;
1437 if (hr == PREFERRED_REG_FIRST)
1438 break;
8062d65a 1439 }
1440 }
b7ec323c 1441
8062d65a 1442 // Try to allocate any available register
b7ec323c 1443 for (hr = PREFERRED_REG_FIRST; ; ) {
1444 if (cur->regmap[hr] < 0) {
8062d65a 1445 cur->regmap[hr]=reg;
1446 cur->dirty&=~(1<<hr);
1447 cur->isconst&=~(1<<hr);
1448 return;
1449 }
b7ec323c 1450 hr++;
1451 if (hr == EXCLUDE_REG)
1452 hr++;
1453 if (hr == HOST_REGS)
1454 hr = 0;
1455 if (hr == PREFERRED_REG_FIRST)
1456 break;
8062d65a 1457 }
1458
1459 // Ok, now we have to evict someone
1460 // Pick a register we hopefully won't need soon
1461 u_char hsn[MAXREG+1];
1462 memset(hsn,10,sizeof(hsn));
1463 int j;
1464 lsn(hsn,i,&preferred_reg);
1465 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
1466 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
1467 if(i>0) {
1468 // Don't evict the cycle count at entry points, otherwise the entry
1469 // stub will have to write it.
cf95b4f0 1470 if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2;
fe807a8a 1471 if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2;
8062d65a 1472 for(j=10;j>=3;j--)
1473 {
1474 // Alloc preferred register if available
1475 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
1476 for(hr=0;hr<HOST_REGS;hr++) {
1477 // Evict both parts of a 64-bit register
1478 if((cur->regmap[hr]&63)==r) {
1479 cur->regmap[hr]=-1;
1480 cur->dirty&=~(1<<hr);
1481 cur->isconst&=~(1<<hr);
1482 }
1483 }
1484 cur->regmap[preferred_reg]=reg;
1485 return;
1486 }
1487 for(r=1;r<=MAXREG;r++)
1488 {
cf95b4f0 1489 if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) {
8062d65a 1490 for(hr=0;hr<HOST_REGS;hr++) {
1491 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
1492 if(cur->regmap[hr]==r) {
1493 cur->regmap[hr]=reg;
1494 cur->dirty&=~(1<<hr);
1495 cur->isconst&=~(1<<hr);
1496 return;
1497 }
1498 }
1499 }
1500 }
1501 }
1502 }
1503 }
1504 for(j=10;j>=0;j--)
1505 {
1506 for(r=1;r<=MAXREG;r++)
1507 {
1508 if(hsn[r]==j) {
8062d65a 1509 for(hr=0;hr<HOST_REGS;hr++) {
1510 if(cur->regmap[hr]==r) {
1511 cur->regmap[hr]=reg;
1512 cur->dirty&=~(1<<hr);
1513 cur->isconst&=~(1<<hr);
1514 return;
1515 }
1516 }
1517 }
1518 }
1519 }
7c3a5182 1520 SysPrintf("This shouldn't happen (alloc_reg)");abort();
8062d65a 1521}
1522
1523// Allocate a temporary register. This is done without regard to
1524// dirty status or whether the register we request is on the unneeded list
1525// Note: This will only allocate one register, even if called multiple times
1526static void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
1527{
1528 int r,hr;
1529 int preferred_reg = -1;
1530
1531 // see if it's already allocated
1532 for(hr=0;hr<HOST_REGS;hr++)
1533 {
1534 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==reg) return;
1535 }
1536
1537 // Try to allocate any available register
1538 for(hr=HOST_REGS-1;hr>=0;hr--) {
1539 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
1540 cur->regmap[hr]=reg;
1541 cur->dirty&=~(1<<hr);
1542 cur->isconst&=~(1<<hr);
1543 return;
1544 }
1545 }
1546
1547 // Find an unneeded register
1548 for(hr=HOST_REGS-1;hr>=0;hr--)
1549 {
1550 r=cur->regmap[hr];
1551 if(r>=0) {
1552 assert(r < 64);
1553 if((cur->u>>r)&1) {
1554 if(i==0||((unneeded_reg[i-1]>>r)&1)) {
1555 cur->regmap[hr]=reg;
1556 cur->dirty&=~(1<<hr);
1557 cur->isconst&=~(1<<hr);
1558 return;
1559 }
1560 }
1561 }
1562 }
1563
1564 // Ok, now we have to evict someone
1565 // Pick a register we hopefully won't need soon
1566 // TODO: we might want to follow unconditional jumps here
1567 // TODO: get rid of dupe code and make this into a function
1568 u_char hsn[MAXREG+1];
1569 memset(hsn,10,sizeof(hsn));
1570 int j;
1571 lsn(hsn,i,&preferred_reg);
1572 //printf("hsn: %d %d %d %d %d %d %d\n",hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
1573 if(i>0) {
1574 // Don't evict the cycle count at entry points, otherwise the entry
1575 // stub will have to write it.
cf95b4f0 1576 if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2;
fe807a8a 1577 if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2;
8062d65a 1578 for(j=10;j>=3;j--)
1579 {
1580 for(r=1;r<=MAXREG;r++)
1581 {
cf95b4f0 1582 if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) {
8062d65a 1583 for(hr=0;hr<HOST_REGS;hr++) {
1584 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
1585 if(cur->regmap[hr]==r) {
1586 cur->regmap[hr]=reg;
1587 cur->dirty&=~(1<<hr);
1588 cur->isconst&=~(1<<hr);
1589 return;
1590 }
1591 }
1592 }
1593 }
1594 }
1595 }
1596 }
1597 for(j=10;j>=0;j--)
1598 {
1599 for(r=1;r<=MAXREG;r++)
1600 {
1601 if(hsn[r]==j) {
8062d65a 1602 for(hr=0;hr<HOST_REGS;hr++) {
1603 if(cur->regmap[hr]==r) {
1604 cur->regmap[hr]=reg;
1605 cur->dirty&=~(1<<hr);
1606 cur->isconst&=~(1<<hr);
1607 return;
1608 }
1609 }
1610 }
1611 }
1612 }
7c3a5182 1613 SysPrintf("This shouldn't happen");abort();
8062d65a 1614}
1615
ad49de89 1616static void mov_alloc(struct regstat *current,int i)
57871462 1617{
cf95b4f0 1618 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) {
9a3ccfeb 1619 alloc_cc(current,i); // for stalls
1620 dirty_reg(current,CCREG);
32631e6a 1621 }
1622
57871462 1623 // Note: Don't need to actually alloc the source registers
cf95b4f0 1624 //alloc_reg(current,i,dops[i].rs1);
1625 alloc_reg(current,i,dops[i].rt1);
ad49de89 1626
cf95b4f0 1627 clear_const(current,dops[i].rs1);
1628 clear_const(current,dops[i].rt1);
1629 dirty_reg(current,dops[i].rt1);
57871462 1630}
1631
ad49de89 1632static void shiftimm_alloc(struct regstat *current,int i)
57871462 1633{
cf95b4f0 1634 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
57871462 1635 {
cf95b4f0 1636 if(dops[i].rt1) {
1637 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1638 else dops[i].lt1=dops[i].rs1;
1639 alloc_reg(current,i,dops[i].rt1);
1640 dirty_reg(current,dops[i].rt1);
1641 if(is_const(current,dops[i].rs1)) {
1642 int v=get_const(current,dops[i].rs1);
1643 if(dops[i].opcode2==0x00) set_const(current,dops[i].rt1,v<<imm[i]);
1644 if(dops[i].opcode2==0x02) set_const(current,dops[i].rt1,(u_int)v>>imm[i]);
1645 if(dops[i].opcode2==0x03) set_const(current,dops[i].rt1,v>>imm[i]);
dc49e339 1646 }
cf95b4f0 1647 else clear_const(current,dops[i].rt1);
57871462 1648 }
1649 }
dc49e339 1650 else
1651 {
cf95b4f0 1652 clear_const(current,dops[i].rs1);
1653 clear_const(current,dops[i].rt1);
dc49e339 1654 }
1655
cf95b4f0 1656 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
57871462 1657 {
9c45ca93 1658 assert(0);
57871462 1659 }
cf95b4f0 1660 if(dops[i].opcode2==0x3c) // DSLL32
57871462 1661 {
9c45ca93 1662 assert(0);
57871462 1663 }
cf95b4f0 1664 if(dops[i].opcode2==0x3e) // DSRL32
57871462 1665 {
9c45ca93 1666 assert(0);
57871462 1667 }
cf95b4f0 1668 if(dops[i].opcode2==0x3f) // DSRA32
57871462 1669 {
9c45ca93 1670 assert(0);
57871462 1671 }
1672}
1673
ad49de89 1674static void shift_alloc(struct regstat *current,int i)
57871462 1675{
cf95b4f0 1676 if(dops[i].rt1) {
1677 if(dops[i].opcode2<=0x07) // SLLV/SRLV/SRAV
57871462 1678 {
cf95b4f0 1679 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
1680 if(dops[i].rs2) alloc_reg(current,i,dops[i].rs2);
1681 alloc_reg(current,i,dops[i].rt1);
1682 if(dops[i].rt1==dops[i].rs2) {
e1190b87 1683 alloc_reg_temp(current,i,-1);
1684 minimum_free_regs[i]=1;
1685 }
57871462 1686 } else { // DSLLV/DSRLV/DSRAV
00fa9369 1687 assert(0);
57871462 1688 }
cf95b4f0 1689 clear_const(current,dops[i].rs1);
1690 clear_const(current,dops[i].rs2);
1691 clear_const(current,dops[i].rt1);
1692 dirty_reg(current,dops[i].rt1);
57871462 1693 }
1694}
1695
ad49de89 1696static void alu_alloc(struct regstat *current,int i)
57871462 1697{
cf95b4f0 1698 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
1699 if(dops[i].rt1) {
1700 if(dops[i].rs1&&dops[i].rs2) {
1701 alloc_reg(current,i,dops[i].rs1);
1702 alloc_reg(current,i,dops[i].rs2);
57871462 1703 }
1704 else {
cf95b4f0 1705 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1706 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
57871462 1707 }
cf95b4f0 1708 alloc_reg(current,i,dops[i].rt1);
57871462 1709 }
57871462 1710 }
cf95b4f0 1711 if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
1712 if(dops[i].rt1) {
1713 alloc_reg(current,i,dops[i].rs1);
1714 alloc_reg(current,i,dops[i].rs2);
1715 alloc_reg(current,i,dops[i].rt1);
57871462 1716 }
57871462 1717 }
cf95b4f0 1718 if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
1719 if(dops[i].rt1) {
1720 if(dops[i].rs1&&dops[i].rs2) {
1721 alloc_reg(current,i,dops[i].rs1);
1722 alloc_reg(current,i,dops[i].rs2);
57871462 1723 }
1724 else
1725 {
cf95b4f0 1726 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1727 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
57871462 1728 }
cf95b4f0 1729 alloc_reg(current,i,dops[i].rt1);
57871462 1730 }
1731 }
cf95b4f0 1732 if(dops[i].opcode2>=0x2c&&dops[i].opcode2<=0x2f) { // DADD/DADDU/DSUB/DSUBU
00fa9369 1733 assert(0);
57871462 1734 }
cf95b4f0 1735 clear_const(current,dops[i].rs1);
1736 clear_const(current,dops[i].rs2);
1737 clear_const(current,dops[i].rt1);
1738 dirty_reg(current,dops[i].rt1);
57871462 1739}
1740
ad49de89 1741static void imm16_alloc(struct regstat *current,int i)
57871462 1742{
cf95b4f0 1743 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1744 else dops[i].lt1=dops[i].rs1;
1745 if(dops[i].rt1) alloc_reg(current,i,dops[i].rt1);
1746 if(dops[i].opcode==0x18||dops[i].opcode==0x19) { // DADDI/DADDIU
00fa9369 1747 assert(0);
57871462 1748 }
cf95b4f0 1749 else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
1750 clear_const(current,dops[i].rs1);
1751 clear_const(current,dops[i].rt1);
57871462 1752 }
cf95b4f0 1753 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
1754 if(is_const(current,dops[i].rs1)) {
1755 int v=get_const(current,dops[i].rs1);
1756 if(dops[i].opcode==0x0c) set_const(current,dops[i].rt1,v&imm[i]);
1757 if(dops[i].opcode==0x0d) set_const(current,dops[i].rt1,v|imm[i]);
1758 if(dops[i].opcode==0x0e) set_const(current,dops[i].rt1,v^imm[i]);
57871462 1759 }
cf95b4f0 1760 else clear_const(current,dops[i].rt1);
57871462 1761 }
cf95b4f0 1762 else if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
1763 if(is_const(current,dops[i].rs1)) {
1764 int v=get_const(current,dops[i].rs1);
1765 set_const(current,dops[i].rt1,v+imm[i]);
57871462 1766 }
cf95b4f0 1767 else clear_const(current,dops[i].rt1);
57871462 1768 }
1769 else {
cf95b4f0 1770 set_const(current,dops[i].rt1,imm[i]<<16); // LUI
57871462 1771 }
cf95b4f0 1772 dirty_reg(current,dops[i].rt1);
57871462 1773}
1774
ad49de89 1775static void load_alloc(struct regstat *current,int i)
57871462 1776{
cf95b4f0 1777 clear_const(current,dops[i].rt1);
1778 //if(dops[i].rs1!=dops[i].rt1&&needed_again(dops[i].rs1,i)) clear_const(current,dops[i].rs1); // Does this help or hurt?
1779 if(!dops[i].rs1) current->u&=~1LL; // Allow allocating r0 if it's the source register
37387d8b 1780 if (needed_again(dops[i].rs1, i))
1781 alloc_reg(current, i, dops[i].rs1);
1782 if (ram_offset)
1783 alloc_reg(current, i, ROREG);
cf95b4f0 1784 if(dops[i].rt1&&!((current->u>>dops[i].rt1)&1)) {
1785 alloc_reg(current,i,dops[i].rt1);
1786 assert(get_reg(current->regmap,dops[i].rt1)>=0);
1787 if(dops[i].opcode==0x27||dops[i].opcode==0x37) // LWU/LD
57871462 1788 {
ad49de89 1789 assert(0);
57871462 1790 }
cf95b4f0 1791 else if(dops[i].opcode==0x1A||dops[i].opcode==0x1B) // LDL/LDR
57871462 1792 {
ad49de89 1793 assert(0);
57871462 1794 }
cf95b4f0 1795 dirty_reg(current,dops[i].rt1);
57871462 1796 // LWL/LWR need a temporary register for the old value
cf95b4f0 1797 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
57871462 1798 {
1799 alloc_reg(current,i,FTEMP);
1800 alloc_reg_temp(current,i,-1);
e1190b87 1801 minimum_free_regs[i]=1;
57871462 1802 }
1803 }
1804 else
1805 {
373d1d07 1806 // Load to r0 or unneeded register (dummy load)
57871462 1807 // but we still need a register to calculate the address
cf95b4f0 1808 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
535d208a 1809 {
1810 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1811 }
57871462 1812 alloc_reg_temp(current,i,-1);
e1190b87 1813 minimum_free_regs[i]=1;
cf95b4f0 1814 if(dops[i].opcode==0x1A||dops[i].opcode==0x1B) // LDL/LDR
535d208a 1815 {
ad49de89 1816 assert(0);
535d208a 1817 }
57871462 1818 }
1819}
1820
1821void store_alloc(struct regstat *current,int i)
1822{
cf95b4f0 1823 clear_const(current,dops[i].rs2);
1824 if(!(dops[i].rs2)) current->u&=~1LL; // Allow allocating r0 if necessary
1825 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1826 alloc_reg(current,i,dops[i].rs2);
1827 if(dops[i].opcode==0x2c||dops[i].opcode==0x2d||dops[i].opcode==0x3f) { // 64-bit SDL/SDR/SD
ad49de89 1828 assert(0);
57871462 1829 }
37387d8b 1830 if (ram_offset)
1831 alloc_reg(current, i, ROREG);
57871462 1832 #if defined(HOST_IMM8)
1833 // On CPUs without 32-bit immediates we need a pointer to invalid_code
37387d8b 1834 alloc_reg(current, i, INVCP);
57871462 1835 #endif
cf95b4f0 1836 if(dops[i].opcode==0x2a||dops[i].opcode==0x2e||dops[i].opcode==0x2c||dops[i].opcode==0x2d) { // SWL/SWL/SDL/SDR
57871462 1837 alloc_reg(current,i,FTEMP);
1838 }
1839 // We need a temporary register for address generation
1840 alloc_reg_temp(current,i,-1);
e1190b87 1841 minimum_free_regs[i]=1;
57871462 1842}
1843
1844void c1ls_alloc(struct regstat *current,int i)
1845{
cf95b4f0 1846 clear_const(current,dops[i].rt1);
57871462 1847 alloc_reg(current,i,CSREG); // Status
57871462 1848}
1849
b9b61529 1850void c2ls_alloc(struct regstat *current,int i)
1851{
cf95b4f0 1852 clear_const(current,dops[i].rt1);
1853 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
b9b61529 1854 alloc_reg(current,i,FTEMP);
37387d8b 1855 if (ram_offset)
1856 alloc_reg(current, i, ROREG);
b9b61529 1857 #if defined(HOST_IMM8)
1858 // On CPUs without 32-bit immediates we need a pointer to invalid_code
37387d8b 1859 if (dops[i].opcode == 0x3a) // SWC2
b9b61529 1860 alloc_reg(current,i,INVCP);
1861 #endif
1862 // We need a temporary register for address generation
1863 alloc_reg_temp(current,i,-1);
e1190b87 1864 minimum_free_regs[i]=1;
b9b61529 1865}
1866
57871462 1867#ifndef multdiv_alloc
1868void multdiv_alloc(struct regstat *current,int i)
1869{
1870 // case 0x18: MULT
1871 // case 0x19: MULTU
1872 // case 0x1A: DIV
1873 // case 0x1B: DIVU
1874 // case 0x1C: DMULT
1875 // case 0x1D: DMULTU
1876 // case 0x1E: DDIV
1877 // case 0x1F: DDIVU
cf95b4f0 1878 clear_const(current,dops[i].rs1);
1879 clear_const(current,dops[i].rs2);
32631e6a 1880 alloc_cc(current,i); // for stalls
cf95b4f0 1881 if(dops[i].rs1&&dops[i].rs2)
57871462 1882 {
cf95b4f0 1883 if((dops[i].opcode2&4)==0) // 32-bit
57871462 1884 {
1885 current->u&=~(1LL<<HIREG);
1886 current->u&=~(1LL<<LOREG);
1887 alloc_reg(current,i,HIREG);
1888 alloc_reg(current,i,LOREG);
cf95b4f0 1889 alloc_reg(current,i,dops[i].rs1);
1890 alloc_reg(current,i,dops[i].rs2);
57871462 1891 dirty_reg(current,HIREG);
1892 dirty_reg(current,LOREG);
1893 }
1894 else // 64-bit
1895 {
00fa9369 1896 assert(0);
57871462 1897 }
1898 }
1899 else
1900 {
1901 // Multiply by zero is zero.
1902 // MIPS does not have a divide by zero exception.
1903 // The result is undefined, we return zero.
1904 alloc_reg(current,i,HIREG);
1905 alloc_reg(current,i,LOREG);
57871462 1906 dirty_reg(current,HIREG);
1907 dirty_reg(current,LOREG);
1908 }
1909}
1910#endif
1911
1912void cop0_alloc(struct regstat *current,int i)
1913{
cf95b4f0 1914 if(dops[i].opcode2==0) // MFC0
57871462 1915 {
cf95b4f0 1916 if(dops[i].rt1) {
1917 clear_const(current,dops[i].rt1);
57871462 1918 alloc_all(current,i);
cf95b4f0 1919 alloc_reg(current,i,dops[i].rt1);
1920 dirty_reg(current,dops[i].rt1);
57871462 1921 }
1922 }
cf95b4f0 1923 else if(dops[i].opcode2==4) // MTC0
57871462 1924 {
cf95b4f0 1925 if(dops[i].rs1){
1926 clear_const(current,dops[i].rs1);
1927 alloc_reg(current,i,dops[i].rs1);
57871462 1928 alloc_all(current,i);
1929 }
1930 else {
1931 alloc_all(current,i); // FIXME: Keep r0
1932 current->u&=~1LL;
1933 alloc_reg(current,i,0);
1934 }
1935 }
1936 else
1937 {
1938 // TLBR/TLBWI/TLBWR/TLBP/ERET
cf95b4f0 1939 assert(dops[i].opcode2==0x10);
57871462 1940 alloc_all(current,i);
1941 }
e1190b87 1942 minimum_free_regs[i]=HOST_REGS;
57871462 1943}
1944
81dbbf4c 1945static void cop2_alloc(struct regstat *current,int i)
57871462 1946{
cf95b4f0 1947 if (dops[i].opcode2 < 3) // MFC2/CFC2
57871462 1948 {
81dbbf4c 1949 alloc_cc(current,i); // for stalls
1950 dirty_reg(current,CCREG);
cf95b4f0 1951 if(dops[i].rt1){
1952 clear_const(current,dops[i].rt1);
1953 alloc_reg(current,i,dops[i].rt1);
1954 dirty_reg(current,dops[i].rt1);
57871462 1955 }
57871462 1956 }
cf95b4f0 1957 else if (dops[i].opcode2 > 3) // MTC2/CTC2
57871462 1958 {
cf95b4f0 1959 if(dops[i].rs1){
1960 clear_const(current,dops[i].rs1);
1961 alloc_reg(current,i,dops[i].rs1);
57871462 1962 }
1963 else {
1964 current->u&=~1LL;
1965 alloc_reg(current,i,0);
57871462 1966 }
1967 }
81dbbf4c 1968 alloc_reg_temp(current,i,-1);
e1190b87 1969 minimum_free_regs[i]=1;
57871462 1970}
00fa9369 1971
b9b61529 1972void c2op_alloc(struct regstat *current,int i)
1973{
81dbbf4c 1974 alloc_cc(current,i); // for stalls
1975 dirty_reg(current,CCREG);
b9b61529 1976 alloc_reg_temp(current,i,-1);
1977}
57871462 1978
1979void syscall_alloc(struct regstat *current,int i)
1980{
1981 alloc_cc(current,i);
1982 dirty_reg(current,CCREG);
1983 alloc_all(current,i);
e1190b87 1984 minimum_free_regs[i]=HOST_REGS;
57871462 1985 current->isconst=0;
1986}
1987
1988void delayslot_alloc(struct regstat *current,int i)
1989{
cf95b4f0 1990 switch(dops[i].itype) {
57871462 1991 case UJUMP:
1992 case CJUMP:
1993 case SJUMP:
1994 case RJUMP:
57871462 1995 case SYSCALL:
7139f3c8 1996 case HLECALL:
57871462 1997 case SPAN:
7c3a5182 1998 assem_debug("jump in the delay slot. this shouldn't happen.\n");//abort();
c43b5311 1999 SysPrintf("Disabled speculative precompilation\n");
57871462 2000 stop_after_jal=1;
2001 break;
2002 case IMM16:
2003 imm16_alloc(current,i);
2004 break;
2005 case LOAD:
2006 case LOADLR:
2007 load_alloc(current,i);
2008 break;
2009 case STORE:
2010 case STORELR:
2011 store_alloc(current,i);
2012 break;
2013 case ALU:
2014 alu_alloc(current,i);
2015 break;
2016 case SHIFT:
2017 shift_alloc(current,i);
2018 break;
2019 case MULTDIV:
2020 multdiv_alloc(current,i);
2021 break;
2022 case SHIFTIMM:
2023 shiftimm_alloc(current,i);
2024 break;
2025 case MOV:
2026 mov_alloc(current,i);
2027 break;
2028 case COP0:
2029 cop0_alloc(current,i);
2030 break;
2031 case COP1:
81dbbf4c 2032 break;
b9b61529 2033 case COP2:
81dbbf4c 2034 cop2_alloc(current,i);
57871462 2035 break;
2036 case C1LS:
2037 c1ls_alloc(current,i);
2038 break;
b9b61529 2039 case C2LS:
2040 c2ls_alloc(current,i);
2041 break;
b9b61529 2042 case C2OP:
2043 c2op_alloc(current,i);
2044 break;
57871462 2045 }
2046}
2047
2048// Special case where a branch and delay slot span two pages in virtual memory
2049static void pagespan_alloc(struct regstat *current,int i)
2050{
2051 current->isconst=0;
2052 current->wasconst=0;
2053 regs[i].wasconst=0;
e1190b87 2054 minimum_free_regs[i]=HOST_REGS;
57871462 2055 alloc_all(current,i);
2056 alloc_cc(current,i);
2057 dirty_reg(current,CCREG);
cf95b4f0 2058 if(dops[i].opcode==3) // JAL
57871462 2059 {
2060 alloc_reg(current,i,31);
2061 dirty_reg(current,31);
2062 }
cf95b4f0 2063 if(dops[i].opcode==0&&(dops[i].opcode2&0x3E)==8) // JR/JALR
57871462 2064 {
cf95b4f0 2065 alloc_reg(current,i,dops[i].rs1);
2066 if (dops[i].rt1!=0) {
2067 alloc_reg(current,i,dops[i].rt1);
2068 dirty_reg(current,dops[i].rt1);
57871462 2069 }
2070 }
cf95b4f0 2071 if((dops[i].opcode&0x2E)==4) // BEQ/BNE/BEQL/BNEL
57871462 2072 {
cf95b4f0 2073 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
2074 if(dops[i].rs2) alloc_reg(current,i,dops[i].rs2);
57871462 2075 }
2076 else
cf95b4f0 2077 if((dops[i].opcode&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
57871462 2078 {
cf95b4f0 2079 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
57871462 2080 }
57871462 2081 //else ...
2082}
2083
b14b6a8f 2084static void add_stub(enum stub_type type, void *addr, void *retaddr,
2085 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e)
2086{
d1e4ebd9 2087 assert(stubcount < ARRAY_SIZE(stubs));
b14b6a8f 2088 stubs[stubcount].type = type;
2089 stubs[stubcount].addr = addr;
2090 stubs[stubcount].retaddr = retaddr;
2091 stubs[stubcount].a = a;
2092 stubs[stubcount].b = b;
2093 stubs[stubcount].c = c;
2094 stubs[stubcount].d = d;
2095 stubs[stubcount].e = e;
57871462 2096 stubcount++;
2097}
2098
b14b6a8f 2099static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
81dbbf4c 2100 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist)
b14b6a8f 2101{
2102 add_stub(type, addr, retaddr, i, addr_reg, (uintptr_t)i_regs, ccadj, reglist);
2103}
2104
57871462 2105// Write out a single register
2330734f 2106static void wb_register(signed char r, const signed char regmap[], uint64_t dirty)
57871462 2107{
2108 int hr;
2109 for(hr=0;hr<HOST_REGS;hr++) {
2110 if(hr!=EXCLUDE_REG) {
2111 if((regmap[hr]&63)==r) {
2112 if((dirty>>hr)&1) {
ad49de89 2113 assert(regmap[hr]<64);
2114 emit_storereg(r,hr);
57871462 2115 }
2116 }
2117 }
2118 }
2119}
2120
8062d65a 2121static void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t u)
2122{
2123 //if(dirty_pre==dirty) return;
2124 int hr,reg;
2125 for(hr=0;hr<HOST_REGS;hr++) {
2126 if(hr!=EXCLUDE_REG) {
2127 reg=pre[hr];
2128 if(((~u)>>(reg&63))&1) {
2129 if(reg>0) {
2130 if(((dirty_pre&~dirty)>>hr)&1) {
2131 if(reg>0&&reg<34) {
2132 emit_storereg(reg,hr);
2133 }
2134 else if(reg>=64) {
2135 assert(0);
2136 }
2137 }
2138 }
2139 }
2140 }
2141 }
2142}
2143
687b4580 2144// trashes r2
2145static void pass_args(int a0, int a1)
2146{
2147 if(a0==1&&a1==0) {
2148 // must swap
2149 emit_mov(a0,2); emit_mov(a1,1); emit_mov(2,0);
2150 }
2151 else if(a0!=0&&a1==0) {
2152 emit_mov(a1,1);
2153 if (a0>=0) emit_mov(a0,0);
2154 }
2155 else {
2156 if(a0>=0&&a0!=0) emit_mov(a0,0);
2157 if(a1>=0&&a1!=1) emit_mov(a1,1);
2158 }
2159}
2160
2330734f 2161static void alu_assemble(int i, const struct regstat *i_regs)
57871462 2162{
cf95b4f0 2163 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
2164 if(dops[i].rt1) {
57871462 2165 signed char s1,s2,t;
cf95b4f0 2166 t=get_reg(i_regs->regmap,dops[i].rt1);
57871462 2167 if(t>=0) {
cf95b4f0 2168 s1=get_reg(i_regs->regmap,dops[i].rs1);
2169 s2=get_reg(i_regs->regmap,dops[i].rs2);
2170 if(dops[i].rs1&&dops[i].rs2) {
57871462 2171 assert(s1>=0);
2172 assert(s2>=0);
cf95b4f0 2173 if(dops[i].opcode2&2) emit_sub(s1,s2,t);
57871462 2174 else emit_add(s1,s2,t);
2175 }
cf95b4f0 2176 else if(dops[i].rs1) {
57871462 2177 if(s1>=0) emit_mov(s1,t);
cf95b4f0 2178 else emit_loadreg(dops[i].rs1,t);
57871462 2179 }
cf95b4f0 2180 else if(dops[i].rs2) {
57871462 2181 if(s2>=0) {
cf95b4f0 2182 if(dops[i].opcode2&2) emit_neg(s2,t);
57871462 2183 else emit_mov(s2,t);
2184 }
2185 else {
cf95b4f0 2186 emit_loadreg(dops[i].rs2,t);
2187 if(dops[i].opcode2&2) emit_neg(t,t);
57871462 2188 }
2189 }
2190 else emit_zeroreg(t);
2191 }
2192 }
2193 }
cf95b4f0 2194 if(dops[i].opcode2>=0x2c&&dops[i].opcode2<=0x2f) { // DADD/DADDU/DSUB/DSUBU
00fa9369 2195 assert(0);
57871462 2196 }
cf95b4f0 2197 if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
2198 if(dops[i].rt1) {
ad49de89 2199 signed char s1l,s2l,t;
57871462 2200 {
cf95b4f0 2201 t=get_reg(i_regs->regmap,dops[i].rt1);
57871462 2202 //assert(t>=0);
2203 if(t>=0) {
cf95b4f0 2204 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2205 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2206 if(dops[i].rs2==0) // rx<r0
57871462 2207 {
cf95b4f0 2208 if(dops[i].opcode2==0x2a&&dops[i].rs1!=0) { // SLT
06e425d7 2209 assert(s1l>=0);
57871462 2210 emit_shrimm(s1l,31,t);
06e425d7 2211 }
2212 else // SLTU (unsigned can not be less than zero, 0<0)
57871462 2213 emit_zeroreg(t);
2214 }
cf95b4f0 2215 else if(dops[i].rs1==0) // r0<rx
57871462 2216 {
2217 assert(s2l>=0);
cf95b4f0 2218 if(dops[i].opcode2==0x2a) // SLT
57871462 2219 emit_set_gz32(s2l,t);
2220 else // SLTU (set if not zero)
2221 emit_set_nz32(s2l,t);
2222 }
2223 else{
2224 assert(s1l>=0);assert(s2l>=0);
cf95b4f0 2225 if(dops[i].opcode2==0x2a) // SLT
57871462 2226 emit_set_if_less32(s1l,s2l,t);
2227 else // SLTU
2228 emit_set_if_carry32(s1l,s2l,t);
2229 }
2230 }
2231 }
2232 }
2233 }
cf95b4f0 2234 if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
2235 if(dops[i].rt1) {
ad49de89 2236 signed char s1l,s2l,tl;
cf95b4f0 2237 tl=get_reg(i_regs->regmap,dops[i].rt1);
57871462 2238 {
57871462 2239 if(tl>=0) {
cf95b4f0 2240 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2241 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2242 if(dops[i].rs1&&dops[i].rs2) {
57871462 2243 assert(s1l>=0);
2244 assert(s2l>=0);
cf95b4f0 2245 if(dops[i].opcode2==0x24) { // AND
57871462 2246 emit_and(s1l,s2l,tl);
2247 } else
cf95b4f0 2248 if(dops[i].opcode2==0x25) { // OR
57871462 2249 emit_or(s1l,s2l,tl);
2250 } else
cf95b4f0 2251 if(dops[i].opcode2==0x26) { // XOR
57871462 2252 emit_xor(s1l,s2l,tl);
2253 } else
cf95b4f0 2254 if(dops[i].opcode2==0x27) { // NOR
57871462 2255 emit_or(s1l,s2l,tl);
2256 emit_not(tl,tl);
2257 }
2258 }
2259 else
2260 {
cf95b4f0 2261 if(dops[i].opcode2==0x24) { // AND
57871462 2262 emit_zeroreg(tl);
2263 } else
cf95b4f0 2264 if(dops[i].opcode2==0x25||dops[i].opcode2==0x26) { // OR/XOR
2265 if(dops[i].rs1){
57871462 2266 if(s1l>=0) emit_mov(s1l,tl);
cf95b4f0 2267 else emit_loadreg(dops[i].rs1,tl); // CHECK: regmap_entry?
57871462 2268 }
2269 else
cf95b4f0 2270 if(dops[i].rs2){
57871462 2271 if(s2l>=0) emit_mov(s2l,tl);
cf95b4f0 2272 else emit_loadreg(dops[i].rs2,tl); // CHECK: regmap_entry?
57871462 2273 }
2274 else emit_zeroreg(tl);
2275 } else
cf95b4f0 2276 if(dops[i].opcode2==0x27) { // NOR
2277 if(dops[i].rs1){
57871462 2278 if(s1l>=0) emit_not(s1l,tl);
2279 else {
cf95b4f0 2280 emit_loadreg(dops[i].rs1,tl);
57871462 2281 emit_not(tl,tl);
2282 }
2283 }
2284 else
cf95b4f0 2285 if(dops[i].rs2){
57871462 2286 if(s2l>=0) emit_not(s2l,tl);
2287 else {
cf95b4f0 2288 emit_loadreg(dops[i].rs2,tl);
57871462 2289 emit_not(tl,tl);
2290 }
2291 }
2292 else emit_movimm(-1,tl);
2293 }
2294 }
2295 }
2296 }
2297 }
2298 }
2299}
2300
2330734f 2301static void imm16_assemble(int i, const struct regstat *i_regs)
57871462 2302{
cf95b4f0 2303 if (dops[i].opcode==0x0f) { // LUI
2304 if(dops[i].rt1) {
57871462 2305 signed char t;
cf95b4f0 2306 t=get_reg(i_regs->regmap,dops[i].rt1);
57871462 2307 //assert(t>=0);
2308 if(t>=0) {
2309 if(!((i_regs->isconst>>t)&1))
2310 emit_movimm(imm[i]<<16,t);
2311 }
2312 }
2313 }
cf95b4f0 2314 if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
2315 if(dops[i].rt1) {
57871462 2316 signed char s,t;
cf95b4f0 2317 t=get_reg(i_regs->regmap,dops[i].rt1);
2318 s=get_reg(i_regs->regmap,dops[i].rs1);
2319 if(dops[i].rs1) {
57871462 2320 //assert(t>=0);
2321 //assert(s>=0);
2322 if(t>=0) {
2323 if(!((i_regs->isconst>>t)&1)) {
2324 if(s<0) {
cf95b4f0 2325 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
57871462 2326 emit_addimm(t,imm[i],t);
2327 }else{
2328 if(!((i_regs->wasconst>>s)&1))
2329 emit_addimm(s,imm[i],t);
2330 else
2331 emit_movimm(constmap[i][s]+imm[i],t);
2332 }
2333 }
2334 }
2335 } else {
2336 if(t>=0) {
2337 if(!((i_regs->isconst>>t)&1))
2338 emit_movimm(imm[i],t);
2339 }
2340 }
2341 }
2342 }
cf95b4f0 2343 if(dops[i].opcode==0x18||dops[i].opcode==0x19) { // DADDI/DADDIU
2344 if(dops[i].rt1) {
7c3a5182 2345 signed char sl,tl;
cf95b4f0 2346 tl=get_reg(i_regs->regmap,dops[i].rt1);
2347 sl=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2348 if(tl>=0) {
cf95b4f0 2349 if(dops[i].rs1) {
57871462 2350 assert(sl>=0);
7c3a5182 2351 emit_addimm(sl,imm[i],tl);
57871462 2352 } else {
2353 emit_movimm(imm[i],tl);
57871462 2354 }
2355 }
2356 }
2357 }
cf95b4f0 2358 else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
2359 if(dops[i].rt1) {
2360 //assert(dops[i].rs1!=0); // r0 might be valid, but it's probably a bug
ad49de89 2361 signed char sl,t;
cf95b4f0 2362 t=get_reg(i_regs->regmap,dops[i].rt1);
2363 sl=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2364 //assert(t>=0);
2365 if(t>=0) {
cf95b4f0 2366 if(dops[i].rs1>0) {
2367 if(dops[i].opcode==0x0a) { // SLTI
57871462 2368 if(sl<0) {
cf95b4f0 2369 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
57871462 2370 emit_slti32(t,imm[i],t);
2371 }else{
2372 emit_slti32(sl,imm[i],t);
2373 }
2374 }
2375 else { // SLTIU
2376 if(sl<0) {
cf95b4f0 2377 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
57871462 2378 emit_sltiu32(t,imm[i],t);
2379 }else{
2380 emit_sltiu32(sl,imm[i],t);
2381 }
2382 }
57871462 2383 }else{
2384 // SLTI(U) with r0 is just stupid,
2385 // nonetheless examples can be found
cf95b4f0 2386 if(dops[i].opcode==0x0a) // SLTI
57871462 2387 if(0<imm[i]) emit_movimm(1,t);
2388 else emit_zeroreg(t);
2389 else // SLTIU
2390 {
2391 if(imm[i]) emit_movimm(1,t);
2392 else emit_zeroreg(t);
2393 }
2394 }
2395 }
2396 }
2397 }
cf95b4f0 2398 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
2399 if(dops[i].rt1) {
7c3a5182 2400 signed char sl,tl;
cf95b4f0 2401 tl=get_reg(i_regs->regmap,dops[i].rt1);
2402 sl=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2403 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
cf95b4f0 2404 if(dops[i].opcode==0x0c) //ANDI
57871462 2405 {
cf95b4f0 2406 if(dops[i].rs1) {
57871462 2407 if(sl<0) {
cf95b4f0 2408 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
57871462 2409 emit_andimm(tl,imm[i],tl);
2410 }else{
2411 if(!((i_regs->wasconst>>sl)&1))
2412 emit_andimm(sl,imm[i],tl);
2413 else
2414 emit_movimm(constmap[i][sl]&imm[i],tl);
2415 }
2416 }
2417 else
2418 emit_zeroreg(tl);
57871462 2419 }
2420 else
2421 {
cf95b4f0 2422 if(dops[i].rs1) {
57871462 2423 if(sl<0) {
cf95b4f0 2424 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
57871462 2425 }
cf95b4f0 2426 if(dops[i].opcode==0x0d) { // ORI
581335b0 2427 if(sl<0) {
2428 emit_orimm(tl,imm[i],tl);
2429 }else{
2430 if(!((i_regs->wasconst>>sl)&1))
2431 emit_orimm(sl,imm[i],tl);
2432 else
2433 emit_movimm(constmap[i][sl]|imm[i],tl);
2434 }
57871462 2435 }
cf95b4f0 2436 if(dops[i].opcode==0x0e) { // XORI
581335b0 2437 if(sl<0) {
2438 emit_xorimm(tl,imm[i],tl);
2439 }else{
2440 if(!((i_regs->wasconst>>sl)&1))
2441 emit_xorimm(sl,imm[i],tl);
2442 else
2443 emit_movimm(constmap[i][sl]^imm[i],tl);
2444 }
57871462 2445 }
2446 }
2447 else {
2448 emit_movimm(imm[i],tl);
57871462 2449 }
2450 }
2451 }
2452 }
2453 }
2454}
2455
2330734f 2456static void shiftimm_assemble(int i, const struct regstat *i_regs)
57871462 2457{
cf95b4f0 2458 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
57871462 2459 {
cf95b4f0 2460 if(dops[i].rt1) {
57871462 2461 signed char s,t;
cf95b4f0 2462 t=get_reg(i_regs->regmap,dops[i].rt1);
2463 s=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2464 //assert(t>=0);
dc49e339 2465 if(t>=0&&!((i_regs->isconst>>t)&1)){
cf95b4f0 2466 if(dops[i].rs1==0)
57871462 2467 {
2468 emit_zeroreg(t);
2469 }
2470 else
2471 {
cf95b4f0 2472 if(s<0&&i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
57871462 2473 if(imm[i]) {
cf95b4f0 2474 if(dops[i].opcode2==0) // SLL
57871462 2475 {
2476 emit_shlimm(s<0?t:s,imm[i],t);
2477 }
cf95b4f0 2478 if(dops[i].opcode2==2) // SRL
57871462 2479 {
2480 emit_shrimm(s<0?t:s,imm[i],t);
2481 }
cf95b4f0 2482 if(dops[i].opcode2==3) // SRA
57871462 2483 {
2484 emit_sarimm(s<0?t:s,imm[i],t);
2485 }
2486 }else{
2487 // Shift by zero
2488 if(s>=0 && s!=t) emit_mov(s,t);
2489 }
2490 }
2491 }
cf95b4f0 2492 //emit_storereg(dops[i].rt1,t); //DEBUG
57871462 2493 }
2494 }
cf95b4f0 2495 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
57871462 2496 {
9c45ca93 2497 assert(0);
57871462 2498 }
cf95b4f0 2499 if(dops[i].opcode2==0x3c) // DSLL32
57871462 2500 {
9c45ca93 2501 assert(0);
57871462 2502 }
cf95b4f0 2503 if(dops[i].opcode2==0x3e) // DSRL32
57871462 2504 {
9c45ca93 2505 assert(0);
57871462 2506 }
cf95b4f0 2507 if(dops[i].opcode2==0x3f) // DSRA32
57871462 2508 {
9c45ca93 2509 assert(0);
57871462 2510 }
2511}
2512
2513#ifndef shift_assemble
2330734f 2514static void shift_assemble(int i, const struct regstat *i_regs)
57871462 2515{
3968e69e 2516 signed char s,t,shift;
cf95b4f0 2517 if (dops[i].rt1 == 0)
3968e69e 2518 return;
cf95b4f0 2519 assert(dops[i].opcode2<=0x07); // SLLV/SRLV/SRAV
2520 t = get_reg(i_regs->regmap, dops[i].rt1);
2521 s = get_reg(i_regs->regmap, dops[i].rs1);
2522 shift = get_reg(i_regs->regmap, dops[i].rs2);
3968e69e 2523 if (t < 0)
2524 return;
2525
cf95b4f0 2526 if(dops[i].rs1==0)
3968e69e 2527 emit_zeroreg(t);
cf95b4f0 2528 else if(dops[i].rs2==0) {
3968e69e 2529 assert(s>=0);
2530 if(s!=t) emit_mov(s,t);
2531 }
2532 else {
2533 host_tempreg_acquire();
2534 emit_andimm(shift,31,HOST_TEMPREG);
cf95b4f0 2535 switch(dops[i].opcode2) {
3968e69e 2536 case 4: // SLLV
2537 emit_shl(s,HOST_TEMPREG,t);
2538 break;
2539 case 6: // SRLV
2540 emit_shr(s,HOST_TEMPREG,t);
2541 break;
2542 case 7: // SRAV
2543 emit_sar(s,HOST_TEMPREG,t);
2544 break;
2545 default:
2546 assert(0);
2547 }
2548 host_tempreg_release();
2549 }
57871462 2550}
3968e69e 2551
57871462 2552#endif
2553
8062d65a 2554enum {
2555 MTYPE_8000 = 0,
2556 MTYPE_8020,
2557 MTYPE_0000,
2558 MTYPE_A000,
2559 MTYPE_1F80,
2560};
2561
2562static int get_ptr_mem_type(u_int a)
2563{
2564 if(a < 0x00200000) {
2565 if(a<0x1000&&((start>>20)==0xbfc||(start>>24)==0xa0))
2566 // return wrong, must use memhandler for BIOS self-test to pass
2567 // 007 does similar stuff from a00 mirror, weird stuff
2568 return MTYPE_8000;
2569 return MTYPE_0000;
2570 }
2571 if(0x1f800000 <= a && a < 0x1f801000)
2572 return MTYPE_1F80;
2573 if(0x80200000 <= a && a < 0x80800000)
2574 return MTYPE_8020;
2575 if(0xa0000000 <= a && a < 0xa0200000)
2576 return MTYPE_A000;
2577 return MTYPE_8000;
2578}
2579
37387d8b 2580static int get_ro_reg(const struct regstat *i_regs, int host_tempreg_free)
2581{
2582 int r = get_reg(i_regs->regmap, ROREG);
2583 if (r < 0 && host_tempreg_free) {
2584 host_tempreg_acquire();
2585 emit_loadreg(ROREG, r = HOST_TEMPREG);
2586 }
2587 if (r < 0)
2588 abort();
2589 return r;
2590}
2591
2592static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs,
2593 int addr, int *offset_reg, int *addr_reg_override)
8062d65a 2594{
2595 void *jaddr = NULL;
37387d8b 2596 int type = 0;
2597 int mr = dops[i].rs1;
2598 *offset_reg = -1;
8062d65a 2599 if(((smrv_strong|smrv_weak)>>mr)&1) {
2600 type=get_ptr_mem_type(smrv[mr]);
2601 //printf("set %08x @%08x r%d %d\n", smrv[mr], start+i*4, mr, type);
2602 }
2603 else {
2604 // use the mirror we are running on
2605 type=get_ptr_mem_type(start);
2606 //printf("set nospec @%08x r%d %d\n", start+i*4, mr, type);
2607 }
2608
2609 if(type==MTYPE_8020) { // RAM 80200000+ mirror
d1e4ebd9 2610 host_tempreg_acquire();
8062d65a 2611 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
2612 addr=*addr_reg_override=HOST_TEMPREG;
2613 type=0;
2614 }
2615 else if(type==MTYPE_0000) { // RAM 0 mirror
d1e4ebd9 2616 host_tempreg_acquire();
8062d65a 2617 emit_orimm(addr,0x80000000,HOST_TEMPREG);
2618 addr=*addr_reg_override=HOST_TEMPREG;
2619 type=0;
2620 }
2621 else if(type==MTYPE_A000) { // RAM A mirror
d1e4ebd9 2622 host_tempreg_acquire();
8062d65a 2623 emit_andimm(addr,~0x20000000,HOST_TEMPREG);
2624 addr=*addr_reg_override=HOST_TEMPREG;
2625 type=0;
2626 }
2627 else if(type==MTYPE_1F80) { // scratchpad
2628 if (psxH == (void *)0x1f800000) {
d1e4ebd9 2629 host_tempreg_acquire();
3968e69e 2630 emit_xorimm(addr,0x1f800000,HOST_TEMPREG);
8062d65a 2631 emit_cmpimm(HOST_TEMPREG,0x1000);
d1e4ebd9 2632 host_tempreg_release();
8062d65a 2633 jaddr=out;
2634 emit_jc(0);
2635 }
2636 else {
2637 // do the usual RAM check, jump will go to the right handler
2638 type=0;
2639 }
2640 }
2641
37387d8b 2642 if (type == 0) // need ram check
8062d65a 2643 {
2644 emit_cmpimm(addr,RAM_SIZE);
37387d8b 2645 jaddr = out;
8062d65a 2646 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2647 // Hint to branch predictor that the branch is unlikely to be taken
37387d8b 2648 if (dops[i].rs1 >= 28)
8062d65a 2649 emit_jno_unlikely(0);
2650 else
2651 #endif
2652 emit_jno(0);
37387d8b 2653 if (ram_offset != 0)
2654 *offset_reg = get_ro_reg(i_regs, 0);
8062d65a 2655 }
2656
2657 return jaddr;
2658}
2659
687b4580 2660// return memhandler, or get directly accessable address and return 0
2661static void *get_direct_memhandler(void *table, u_int addr,
2662 enum stub_type type, uintptr_t *addr_host)
2663{
c979e8c2 2664 uintptr_t msb = 1ull << (sizeof(uintptr_t)*8 - 1);
687b4580 2665 uintptr_t l1, l2 = 0;
2666 l1 = ((uintptr_t *)table)[addr>>12];
c979e8c2 2667 if (!(l1 & msb)) {
687b4580 2668 uintptr_t v = l1 << 1;
2669 *addr_host = v + addr;
2670 return NULL;
2671 }
2672 else {
2673 l1 <<= 1;
2674 if (type == LOADB_STUB || type == LOADBU_STUB || type == STOREB_STUB)
2675 l2 = ((uintptr_t *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)];
2676 else if (type == LOADH_STUB || type == LOADHU_STUB || type == STOREH_STUB)
c979e8c2 2677 l2 = ((uintptr_t *)l1)[0x1000/4 + (addr&0xfff)/2];
687b4580 2678 else
c979e8c2 2679 l2 = ((uintptr_t *)l1)[(addr&0xfff)/4];
2680 if (!(l2 & msb)) {
687b4580 2681 uintptr_t v = l2 << 1;
2682 *addr_host = v + (addr&0xfff);
2683 return NULL;
2684 }
2685 return (void *)(l2 << 1);
2686 }
2687}
2688
81dbbf4c 2689static u_int get_host_reglist(const signed char *regmap)
2690{
2691 u_int reglist = 0, hr;
2692 for (hr = 0; hr < HOST_REGS; hr++) {
2693 if (hr != EXCLUDE_REG && regmap[hr] >= 0)
2694 reglist |= 1 << hr;
2695 }
2696 return reglist;
2697}
2698
2699static u_int reglist_exclude(u_int reglist, int r1, int r2)
2700{
2701 if (r1 >= 0)
2702 reglist &= ~(1u << r1);
2703 if (r2 >= 0)
2704 reglist &= ~(1u << r2);
2705 return reglist;
2706}
2707
e3c6bdb5 2708// find a temp caller-saved register not in reglist (so assumed to be free)
2709static int reglist_find_free(u_int reglist)
2710{
2711 u_int free_regs = ~reglist & CALLER_SAVE_REGS;
2712 if (free_regs == 0)
2713 return -1;
2714 return __builtin_ctz(free_regs);
2715}
2716
37387d8b 2717static void do_load_word(int a, int rt, int offset_reg)
2718{
2719 if (offset_reg >= 0)
2720 emit_ldr_dualindexed(offset_reg, a, rt);
2721 else
2722 emit_readword_indexed(0, a, rt);
2723}
2724
2725static void do_store_word(int a, int ofs, int rt, int offset_reg, int preseve_a)
2726{
2727 if (offset_reg < 0) {
2728 emit_writeword_indexed(rt, ofs, a);
2729 return;
2730 }
2731 if (ofs != 0)
2732 emit_addimm(a, ofs, a);
2733 emit_str_dualindexed(offset_reg, a, rt);
2734 if (ofs != 0 && preseve_a)
2735 emit_addimm(a, -ofs, a);
2736}
2737
2738static void do_store_hword(int a, int ofs, int rt, int offset_reg, int preseve_a)
2739{
2740 if (offset_reg < 0) {
2741 emit_writehword_indexed(rt, ofs, a);
2742 return;
2743 }
2744 if (ofs != 0)
2745 emit_addimm(a, ofs, a);
2746 emit_strh_dualindexed(offset_reg, a, rt);
2747 if (ofs != 0 && preseve_a)
2748 emit_addimm(a, -ofs, a);
2749}
2750
2751static void do_store_byte(int a, int rt, int offset_reg)
2752{
2753 if (offset_reg >= 0)
2754 emit_strb_dualindexed(offset_reg, a, rt);
2755 else
2756 emit_writebyte_indexed(rt, 0, a);
2757}
2758
2330734f 2759static void load_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 2760{
7c3a5182 2761 int s,tl,addr;
57871462 2762 int offset;
b14b6a8f 2763 void *jaddr=0;
5bf843dc 2764 int memtarget=0,c=0;
37387d8b 2765 int offset_reg = -1;
2766 int fastio_reg_override = -1;
81dbbf4c 2767 u_int reglist=get_host_reglist(i_regs->regmap);
cf95b4f0 2768 tl=get_reg(i_regs->regmap,dops[i].rt1);
2769 s=get_reg(i_regs->regmap,dops[i].rs1);
57871462 2770 offset=imm[i];
57871462 2771 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2772 if(s>=0) {
2773 c=(i_regs->wasconst>>s)&1;
af4ee1fe 2774 if (c) {
2775 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
af4ee1fe 2776 }
57871462 2777 }
57871462 2778 //printf("load_assemble: c=%d\n",c);
643aeae3 2779 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
57871462 2780 // FIXME: Even if the load is a NOP, we should check for pagefaults...
581335b0 2781 if((tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80))
cf95b4f0 2782 ||dops[i].rt1==0) {
5bf843dc 2783 // could be FIFO, must perform the read
f18c0f46 2784 // ||dummy read
5bf843dc 2785 assem_debug("(forced read)\n");
2786 tl=get_reg(i_regs->regmap,-1);
2787 assert(tl>=0);
5bf843dc 2788 }
2789 if(offset||s<0||c) addr=tl;
2790 else addr=s;
535d208a 2791 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2792 if(tl>=0) {
2793 //printf("load_assemble: c=%d\n",c);
643aeae3 2794 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
535d208a 2795 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2796 reglist&=~(1<<tl);
1edfcc68 2797 if(!c) {
1edfcc68 2798 #ifdef R29_HACK
2799 // Strmnnrmn's speed hack
cf95b4f0 2800 if(dops[i].rs1!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
1edfcc68 2801 #endif
2802 {
37387d8b 2803 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
2804 &offset_reg, &fastio_reg_override);
535d208a 2805 }
1edfcc68 2806 }
37387d8b 2807 else if (ram_offset && memtarget) {
2808 offset_reg = get_ro_reg(i_regs, 0);
535d208a 2809 }
cf95b4f0 2810 int dummy=(dops[i].rt1==0)||(tl!=get_reg(i_regs->regmap,dops[i].rt1)); // ignore loads to r0 and unneeded reg
37387d8b 2811 switch (dops[i].opcode) {
2812 case 0x20: // LB
535d208a 2813 if(!c||memtarget) {
2814 if(!dummy) {
37387d8b 2815 int a = tl;
2816 if (!c) a = addr;
2817 if (fastio_reg_override >= 0)
2818 a = fastio_reg_override;
b1570849 2819
37387d8b 2820 if (offset_reg >= 0)
2821 emit_ldrsb_dualindexed(offset_reg, a, tl);
2822 else
2823 emit_movsbl_indexed(0, a, tl);
57871462 2824 }
535d208a 2825 if(jaddr)
2330734f 2826 add_stub_r(LOADB_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 2827 }
535d208a 2828 else
2330734f 2829 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 2830 break;
2831 case 0x21: // LH
535d208a 2832 if(!c||memtarget) {
2833 if(!dummy) {
37387d8b 2834 int a = tl;
2835 if (!c) a = addr;
2836 if (fastio_reg_override >= 0)
2837 a = fastio_reg_override;
2838 if (offset_reg >= 0)
2839 emit_ldrsh_dualindexed(offset_reg, a, tl);
2840 else
2841 emit_movswl_indexed(0, a, tl);
57871462 2842 }
535d208a 2843 if(jaddr)
2330734f 2844 add_stub_r(LOADH_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 2845 }
535d208a 2846 else
2330734f 2847 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 2848 break;
2849 case 0x23: // LW
535d208a 2850 if(!c||memtarget) {
2851 if(!dummy) {
37387d8b 2852 int a = addr;
2853 if (fastio_reg_override >= 0)
2854 a = fastio_reg_override;
2855 do_load_word(a, tl, offset_reg);
57871462 2856 }
535d208a 2857 if(jaddr)
2330734f 2858 add_stub_r(LOADW_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 2859 }
535d208a 2860 else
2330734f 2861 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 2862 break;
2863 case 0x24: // LBU
535d208a 2864 if(!c||memtarget) {
2865 if(!dummy) {
37387d8b 2866 int a = tl;
2867 if (!c) a = addr;
2868 if (fastio_reg_override >= 0)
2869 a = fastio_reg_override;
b1570849 2870
37387d8b 2871 if (offset_reg >= 0)
2872 emit_ldrb_dualindexed(offset_reg, a, tl);
2873 else
2874 emit_movzbl_indexed(0, a, tl);
57871462 2875 }
535d208a 2876 if(jaddr)
2330734f 2877 add_stub_r(LOADBU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 2878 }
535d208a 2879 else
2330734f 2880 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 2881 break;
2882 case 0x25: // LHU
535d208a 2883 if(!c||memtarget) {
2884 if(!dummy) {
37387d8b 2885 int a = tl;
2886 if(!c) a = addr;
2887 if (fastio_reg_override >= 0)
2888 a = fastio_reg_override;
2889 if (offset_reg >= 0)
2890 emit_ldrh_dualindexed(offset_reg, a, tl);
2891 else
2892 emit_movzwl_indexed(0, a, tl);
57871462 2893 }
535d208a 2894 if(jaddr)
2330734f 2895 add_stub_r(LOADHU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
57871462 2896 }
535d208a 2897 else
2330734f 2898 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
37387d8b 2899 break;
2900 case 0x27: // LWU
2901 case 0x37: // LD
2902 default:
9c45ca93 2903 assert(0);
57871462 2904 }
535d208a 2905 }
37387d8b 2906 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
d1e4ebd9 2907 host_tempreg_release();
57871462 2908}
2909
2910#ifndef loadlr_assemble
2330734f 2911static void loadlr_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 2912{
3968e69e 2913 int s,tl,temp,temp2,addr;
2914 int offset;
2915 void *jaddr=0;
2916 int memtarget=0,c=0;
37387d8b 2917 int offset_reg = -1;
2918 int fastio_reg_override = -1;
81dbbf4c 2919 u_int reglist=get_host_reglist(i_regs->regmap);
cf95b4f0 2920 tl=get_reg(i_regs->regmap,dops[i].rt1);
2921 s=get_reg(i_regs->regmap,dops[i].rs1);
3968e69e 2922 temp=get_reg(i_regs->regmap,-1);
2923 temp2=get_reg(i_regs->regmap,FTEMP);
2924 addr=get_reg(i_regs->regmap,AGEN1+(i&1));
2925 assert(addr<0);
2926 offset=imm[i];
3968e69e 2927 reglist|=1<<temp;
2928 if(offset||s<0||c) addr=temp2;
2929 else addr=s;
2930 if(s>=0) {
2931 c=(i_regs->wasconst>>s)&1;
2932 if(c) {
2933 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2934 }
2935 }
2936 if(!c) {
2937 emit_shlimm(addr,3,temp);
cf95b4f0 2938 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
3968e69e 2939 emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR
2940 }else{
2941 emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR
2942 }
37387d8b 2943 jaddr = emit_fastpath_cmp_jump(i, i_regs, temp2,
2944 &offset_reg, &fastio_reg_override);
3968e69e 2945 }
2946 else {
37387d8b 2947 if (ram_offset && memtarget) {
2948 offset_reg = get_ro_reg(i_regs, 0);
3968e69e 2949 }
cf95b4f0 2950 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
3968e69e 2951 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
2952 }else{
2953 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
2954 }
2955 }
cf95b4f0 2956 if (dops[i].opcode==0x22||dops[i].opcode==0x26) { // LWL/LWR
3968e69e 2957 if(!c||memtarget) {
37387d8b 2958 int a = temp2;
2959 if (fastio_reg_override >= 0)
2960 a = fastio_reg_override;
2961 do_load_word(a, temp2, offset_reg);
2962 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
2963 host_tempreg_release();
2330734f 2964 if(jaddr) add_stub_r(LOADW_STUB,jaddr,out,i,temp2,i_regs,ccadj_,reglist);
3968e69e 2965 }
2966 else
2330734f 2967 inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj_,reglist);
cf95b4f0 2968 if(dops[i].rt1) {
3968e69e 2969 assert(tl>=0);
2970 emit_andimm(temp,24,temp);
cf95b4f0 2971 if (dops[i].opcode==0x22) // LWL
3968e69e 2972 emit_xorimm(temp,24,temp);
2973 host_tempreg_acquire();
2974 emit_movimm(-1,HOST_TEMPREG);
cf95b4f0 2975 if (dops[i].opcode==0x26) {
3968e69e 2976 emit_shr(temp2,temp,temp2);
2977 emit_bic_lsr(tl,HOST_TEMPREG,temp,tl);
2978 }else{
2979 emit_shl(temp2,temp,temp2);
2980 emit_bic_lsl(tl,HOST_TEMPREG,temp,tl);
2981 }
2982 host_tempreg_release();
2983 emit_or(temp2,tl,tl);
2984 }
cf95b4f0 2985 //emit_storereg(dops[i].rt1,tl); // DEBUG
3968e69e 2986 }
cf95b4f0 2987 if (dops[i].opcode==0x1A||dops[i].opcode==0x1B) { // LDL/LDR
3968e69e 2988 assert(0);
2989 }
57871462 2990}
2991#endif
2992
2330734f 2993static void store_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 2994{
9c45ca93 2995 int s,tl;
57871462 2996 int addr,temp;
2997 int offset;
b14b6a8f 2998 void *jaddr=0;
37387d8b 2999 enum stub_type type=0;
666a299d 3000 int memtarget=0,c=0;
57871462 3001 int agr=AGEN1+(i&1);
37387d8b 3002 int offset_reg = -1;
3003 int fastio_reg_override = -1;
81dbbf4c 3004 u_int reglist=get_host_reglist(i_regs->regmap);
cf95b4f0 3005 tl=get_reg(i_regs->regmap,dops[i].rs2);
3006 s=get_reg(i_regs->regmap,dops[i].rs1);
57871462 3007 temp=get_reg(i_regs->regmap,agr);
3008 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3009 offset=imm[i];
3010 if(s>=0) {
3011 c=(i_regs->wasconst>>s)&1;
af4ee1fe 3012 if(c) {
3013 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
af4ee1fe 3014 }
57871462 3015 }
3016 assert(tl>=0);
3017 assert(temp>=0);
57871462 3018 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3019 if(offset||s<0||c) addr=temp;
3020 else addr=s;
37387d8b 3021 if (!c) {
3022 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
3023 &offset_reg, &fastio_reg_override);
1edfcc68 3024 }
37387d8b 3025 else if (ram_offset && memtarget) {
3026 offset_reg = get_ro_reg(i_regs, 0);
57871462 3027 }
3028
37387d8b 3029 switch (dops[i].opcode) {
3030 case 0x28: // SB
57871462 3031 if(!c||memtarget) {
37387d8b 3032 int a = temp;
3033 if (!c) a = addr;
3034 if (fastio_reg_override >= 0)
3035 a = fastio_reg_override;
3036 do_store_byte(a, tl, offset_reg);
3037 }
3038 type = STOREB_STUB;
3039 break;
3040 case 0x29: // SH
57871462 3041 if(!c||memtarget) {
37387d8b 3042 int a = temp;
3043 if (!c) a = addr;
3044 if (fastio_reg_override >= 0)
3045 a = fastio_reg_override;
3046 do_store_hword(a, 0, tl, offset_reg, 1);
3047 }
3048 type = STOREH_STUB;
3049 break;
3050 case 0x2B: // SW
dadf55f2 3051 if(!c||memtarget) {
37387d8b 3052 int a = addr;
3053 if (fastio_reg_override >= 0)
3054 a = fastio_reg_override;
3055 do_store_word(a, 0, tl, offset_reg, 1);
3056 }
3057 type = STOREW_STUB;
3058 break;
3059 case 0x3F: // SD
3060 default:
9c45ca93 3061 assert(0);
57871462 3062 }
37387d8b 3063 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
d1e4ebd9 3064 host_tempreg_release();
b96d3df7 3065 if(jaddr) {
3066 // PCSX store handlers don't check invcode again
3067 reglist|=1<<addr;
2330734f 3068 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist);
b96d3df7 3069 jaddr=0;
3070 }
cf95b4f0 3071 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
57871462 3072 if(!c||memtarget) {
3073 #ifdef DESTRUCTIVE_SHIFT
3074 // The x86 shift operation is 'destructive'; it overwrites the
3075 // source register, so we need to make a copy first and use that.
3076 addr=temp;
3077 #endif
3078 #if defined(HOST_IMM8)
3079 int ir=get_reg(i_regs->regmap,INVCP);
3080 assert(ir>=0);
3081 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3082 #else
643aeae3 3083 emit_cmpmem_indexedsr12_imm(invalid_code,addr,1);
57871462 3084 #endif
0bbd1454 3085 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3086 emit_callne(invalidate_addr_reg[addr]);
3087 #else
b14b6a8f 3088 void *jaddr2 = out;
57871462 3089 emit_jne(0);
b14b6a8f 3090 add_stub(INVCODE_STUB,jaddr2,out,reglist|(1<<HOST_CCREG),addr,0,0,0);
0bbd1454 3091 #endif
57871462 3092 }
3093 }
7a518516 3094 u_int addr_val=constmap[i][s]+offset;
3eaa7048 3095 if(jaddr) {
2330734f 3096 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3eaa7048 3097 } else if(c&&!memtarget) {
2330734f 3098 inline_writestub(type,i,addr_val,i_regs->regmap,dops[i].rs2,ccadj_,reglist);
7a518516 3099 }
3100 // basic current block modification detection..
3101 // not looking back as that should be in mips cache already
3968e69e 3102 // (see Spyro2 title->attract mode)
7a518516 3103 if(c&&start+i*4<addr_val&&addr_val<start+slen*4) {
c43b5311 3104 SysPrintf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4);
7a518516 3105 assert(i_regs->regmap==regs[i].regmap); // not delay slot
3106 if(i_regs->regmap==regs[i].regmap) {
ad49de89 3107 load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
3108 wb_dirtys(regs[i].regmap_entry,regs[i].wasdirty);
7a518516 3109 emit_movimm(start+i*4+4,0);
643aeae3 3110 emit_writeword(0,&pcaddr);
d1e4ebd9 3111 emit_addimm(HOST_CCREG,2,HOST_CCREG);
2a014d73 3112 emit_far_call(get_addr_ht);
d1e4ebd9 3113 emit_jmpreg(0);
7a518516 3114 }
3eaa7048 3115 }
57871462 3116}
3117
2330734f 3118static void storelr_assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 3119{
9c45ca93 3120 int s,tl;
57871462 3121 int temp;
57871462 3122 int offset;
b14b6a8f 3123 void *jaddr=0;
37387d8b 3124 void *case1, *case23, *case3;
df4dc2b1 3125 void *done0, *done1, *done2;
af4ee1fe 3126 int memtarget=0,c=0;
fab5d06d 3127 int agr=AGEN1+(i&1);
37387d8b 3128 int offset_reg = -1;
81dbbf4c 3129 u_int reglist=get_host_reglist(i_regs->regmap);
cf95b4f0 3130 tl=get_reg(i_regs->regmap,dops[i].rs2);
3131 s=get_reg(i_regs->regmap,dops[i].rs1);
fab5d06d 3132 temp=get_reg(i_regs->regmap,agr);
3133 if(temp<0) temp=get_reg(i_regs->regmap,-1);
57871462 3134 offset=imm[i];
3135 if(s>=0) {
3136 c=(i_regs->isconst>>s)&1;
af4ee1fe 3137 if(c) {
3138 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
af4ee1fe 3139 }
57871462 3140 }
3141 assert(tl>=0);
535d208a 3142 assert(temp>=0);
1edfcc68 3143 if(!c) {
3144 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3145 if(!offset&&s!=temp) emit_mov(s,temp);
b14b6a8f 3146 jaddr=out;
1edfcc68 3147 emit_jno(0);
3148 }
3149 else
3150 {
cf95b4f0 3151 if(!memtarget||!dops[i].rs1) {
b14b6a8f 3152 jaddr=out;
535d208a 3153 emit_jmp(0);
57871462 3154 }
535d208a 3155 }
37387d8b 3156 if (ram_offset)
3157 offset_reg = get_ro_reg(i_regs, 0);
535d208a 3158
cf95b4f0 3159 if (dops[i].opcode==0x2C||dops[i].opcode==0x2D) { // SDL/SDR
9c45ca93 3160 assert(0);
535d208a 3161 }
57871462 3162
535d208a 3163 emit_testimm(temp,2);
37387d8b 3164 case23=out;
535d208a 3165 emit_jne(0);
3166 emit_testimm(temp,1);
df4dc2b1 3167 case1=out;
535d208a 3168 emit_jne(0);
3169 // 0
37387d8b 3170 if (dops[i].opcode == 0x2A) { // SWL
3171 // Write msb into least significant byte
3172 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
3173 do_store_byte(temp, tl, offset_reg);
3174 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
535d208a 3175 }
37387d8b 3176 else if (dops[i].opcode == 0x2E) { // SWR
3177 // Write entire word
3178 do_store_word(temp, 0, tl, offset_reg, 1);
535d208a 3179 }
37387d8b 3180 done0 = out;
535d208a 3181 emit_jmp(0);
3182 // 1
df4dc2b1 3183 set_jump_target(case1, out);
37387d8b 3184 if (dops[i].opcode == 0x2A) { // SWL
3185 // Write two msb into two least significant bytes
3186 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3187 do_store_hword(temp, -1, tl, offset_reg, 0);
3188 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
535d208a 3189 }
37387d8b 3190 else if (dops[i].opcode == 0x2E) { // SWR
3191 // Write 3 lsb into three most significant bytes
3192 do_store_byte(temp, tl, offset_reg);
3193 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3194 do_store_hword(temp, 1, tl, offset_reg, 0);
3195 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
535d208a 3196 }
df4dc2b1 3197 done1=out;
535d208a 3198 emit_jmp(0);
37387d8b 3199 // 2,3
3200 set_jump_target(case23, out);
535d208a 3201 emit_testimm(temp,1);
37387d8b 3202 case3 = out;
535d208a 3203 emit_jne(0);
37387d8b 3204 // 2
cf95b4f0 3205 if (dops[i].opcode==0x2A) { // SWL
37387d8b 3206 // Write 3 msb into three least significant bytes
3207 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3208 do_store_hword(temp, -2, tl, offset_reg, 1);
3209 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3210 do_store_byte(temp, tl, offset_reg);
3211 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
535d208a 3212 }
37387d8b 3213 else if (dops[i].opcode == 0x2E) { // SWR
3214 // Write two lsb into two most significant bytes
3215 do_store_hword(temp, 0, tl, offset_reg, 1);
535d208a 3216 }
37387d8b 3217 done2 = out;
535d208a 3218 emit_jmp(0);
3219 // 3
df4dc2b1 3220 set_jump_target(case3, out);
37387d8b 3221 if (dops[i].opcode == 0x2A) { // SWL
3222 do_store_word(temp, -3, tl, offset_reg, 0);
535d208a 3223 }
37387d8b 3224 else if (dops[i].opcode == 0x2E) { // SWR
3225 do_store_byte(temp, tl, offset_reg);
535d208a 3226 }
df4dc2b1 3227 set_jump_target(done0, out);
3228 set_jump_target(done1, out);
3229 set_jump_target(done2, out);
37387d8b 3230 if (offset_reg == HOST_TEMPREG)
3231 host_tempreg_release();
535d208a 3232 if(!c||!memtarget)
2330734f 3233 add_stub_r(STORELR_STUB,jaddr,out,i,temp,i_regs,ccadj_,reglist);
cf95b4f0 3234 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
57871462 3235 #if defined(HOST_IMM8)
3236 int ir=get_reg(i_regs->regmap,INVCP);
3237 assert(ir>=0);
3238 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3239 #else
643aeae3 3240 emit_cmpmem_indexedsr12_imm(invalid_code,temp,1);
57871462 3241 #endif
535d208a 3242 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3243 emit_callne(invalidate_addr_reg[temp]);
3244 #else
b14b6a8f 3245 void *jaddr2 = out;
57871462 3246 emit_jne(0);
b14b6a8f 3247 add_stub(INVCODE_STUB,jaddr2,out,reglist|(1<<HOST_CCREG),temp,0,0,0);
535d208a 3248 #endif
57871462 3249 }
57871462 3250}
3251
2330734f 3252static void cop0_assemble(int i, const struct regstat *i_regs, int ccadj_)
8062d65a 3253{
cf95b4f0 3254 if(dops[i].opcode2==0) // MFC0
8062d65a 3255 {
cf95b4f0 3256 signed char t=get_reg(i_regs->regmap,dops[i].rt1);
8062d65a 3257 u_int copr=(source[i]>>11)&0x1f;
3258 //assert(t>=0); // Why does this happen? OOT is weird
cf95b4f0 3259 if(t>=0&&dops[i].rt1!=0) {
8062d65a 3260 emit_readword(&reg_cop0[copr],t);
3261 }
3262 }
cf95b4f0 3263 else if(dops[i].opcode2==4) // MTC0
8062d65a 3264 {
cf95b4f0 3265 signed char s=get_reg(i_regs->regmap,dops[i].rs1);
8062d65a 3266 char copr=(source[i]>>11)&0x1f;
3267 assert(s>=0);
cf95b4f0 3268 wb_register(dops[i].rs1,i_regs->regmap,i_regs->dirty);
8062d65a 3269 if(copr==9||copr==11||copr==12||copr==13) {
3270 emit_readword(&last_count,HOST_TEMPREG);
3271 emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
3272 emit_add(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
2330734f 3273 emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG);
8062d65a 3274 emit_writeword(HOST_CCREG,&Count);
3275 }
3276 // What a mess. The status register (12) can enable interrupts,
3277 // so needs a special case to handle a pending interrupt.
3278 // The interrupt must be taken immediately, because a subsequent
3279 // instruction might disable interrupts again.
3280 if(copr==12||copr==13) {
3281 if (is_delayslot) {
3282 // burn cycles to cause cc_interrupt, which will
3283 // reschedule next_interupt. Relies on CCREG from above.
3284 assem_debug("MTC0 DS %d\n", copr);
3285 emit_writeword(HOST_CCREG,&last_count);
3286 emit_movimm(0,HOST_CCREG);
3287 emit_storereg(CCREG,HOST_CCREG);
cf95b4f0 3288 emit_loadreg(dops[i].rs1,1);
8062d65a 3289 emit_movimm(copr,0);
2a014d73 3290 emit_far_call(pcsx_mtc0_ds);
cf95b4f0 3291 emit_loadreg(dops[i].rs1,s);
8062d65a 3292 return;
3293 }
3294 emit_movimm(start+i*4+4,HOST_TEMPREG);
3295 emit_writeword(HOST_TEMPREG,&pcaddr);
3296 emit_movimm(0,HOST_TEMPREG);
3297 emit_writeword(HOST_TEMPREG,&pending_exception);
3298 }
8062d65a 3299 if(s==HOST_CCREG)
cf95b4f0 3300 emit_loadreg(dops[i].rs1,1);
8062d65a 3301 else if(s!=1)
3302 emit_mov(s,1);
3303 emit_movimm(copr,0);
2a014d73 3304 emit_far_call(pcsx_mtc0);
8062d65a 3305 if(copr==9||copr==11||copr==12||copr==13) {
3306 emit_readword(&Count,HOST_CCREG);
3307 emit_readword(&next_interupt,HOST_TEMPREG);
2330734f 3308 emit_addimm(HOST_CCREG,-ccadj_,HOST_CCREG);
8062d65a 3309 emit_sub(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
3310 emit_writeword(HOST_TEMPREG,&last_count);
3311 emit_storereg(CCREG,HOST_CCREG);
3312 }
3313 if(copr==12||copr==13) {
3314 assert(!is_delayslot);
3315 emit_readword(&pending_exception,14);
3316 emit_test(14,14);
d1e4ebd9 3317 void *jaddr = out;
3318 emit_jeq(0);
3319 emit_readword(&pcaddr, 0);
3320 emit_addimm(HOST_CCREG,2,HOST_CCREG);
2a014d73 3321 emit_far_call(get_addr_ht);
d1e4ebd9 3322 emit_jmpreg(0);
3323 set_jump_target(jaddr, out);
8062d65a 3324 }
cf95b4f0 3325 emit_loadreg(dops[i].rs1,s);
8062d65a 3326 }
3327 else
3328 {
cf95b4f0 3329 assert(dops[i].opcode2==0x10);
8062d65a 3330 //if((source[i]&0x3f)==0x10) // RFE
3331 {
3332 emit_readword(&Status,0);
3333 emit_andimm(0,0x3c,1);
3334 emit_andimm(0,~0xf,0);
3335 emit_orrshr_imm(1,2,0);
3336 emit_writeword(0,&Status);
3337 }
3338 }
3339}
3340
2330734f 3341static void cop1_unusable(int i, const struct regstat *i_regs)
8062d65a 3342{
3343 // XXX: should just just do the exception instead
3344 //if(!cop1_usable)
3345 {
3346 void *jaddr=out;
3347 emit_jmp(0);
3348 add_stub_r(FP_STUB,jaddr,out,i,0,i_regs,is_delayslot,0);
3349 }
3350}
3351
2330734f 3352static void cop1_assemble(int i, const struct regstat *i_regs)
8062d65a 3353{
3354 cop1_unusable(i, i_regs);
3355}
3356
2330734f 3357static void c1ls_assemble(int i, const struct regstat *i_regs)
57871462 3358{
3d624f89 3359 cop1_unusable(i, i_regs);
57871462 3360}
3361
8062d65a 3362// FP_STUB
3363static void do_cop1stub(int n)
3364{
3365 literal_pool(256);
3366 assem_debug("do_cop1stub %x\n",start+stubs[n].a*4);
3367 set_jump_target(stubs[n].addr, out);
3368 int i=stubs[n].a;
3369// int rs=stubs[n].b;
3370 struct regstat *i_regs=(struct regstat *)stubs[n].c;
3371 int ds=stubs[n].d;
3372 if(!ds) {
3373 load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
3374 //if(i_regs!=&regs[i]) printf("oops: regs[i]=%x i_regs=%x",(int)&regs[i],(int)i_regs);
3375 }
3376 //else {printf("fp exception in delay slot\n");}
3377 wb_dirtys(i_regs->regmap_entry,i_regs->wasdirty);
3378 if(regs[i].regmap_entry[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
3379 emit_movimm(start+(i-ds)*4,EAX); // Get PC
2330734f 3380 emit_addimm(HOST_CCREG,ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
2a014d73 3381 emit_far_jump(ds?fp_exception_ds:fp_exception);
8062d65a 3382}
3383
e3c6bdb5 3384static int cop2_is_stalling_op(int i, int *cycles)
3385{
cf95b4f0 3386 if (dops[i].opcode == 0x3a) { // SWC2
e3c6bdb5 3387 *cycles = 0;
3388 return 1;
3389 }
cf95b4f0 3390 if (dops[i].itype == COP2 && (dops[i].opcode2 == 0 || dops[i].opcode2 == 2)) { // MFC2/CFC2
e3c6bdb5 3391 *cycles = 0;
3392 return 1;
3393 }
cf95b4f0 3394 if (dops[i].itype == C2OP) {
e3c6bdb5 3395 *cycles = gte_cycletab[source[i] & 0x3f];
3396 return 1;
3397 }
3398 // ... what about MTC2/CTC2/LWC2?
3399 return 0;
3400}
3401
3402#if 0
3403static void log_gte_stall(int stall, u_int cycle)
3404{
3405 if ((u_int)stall <= 44)
3406 printf("x stall %2d %u\n", stall, cycle + last_count);
e3c6bdb5 3407}
3408
3409static void emit_log_gte_stall(int i, int stall, u_int reglist)
3410{
3411 save_regs(reglist);
3412 if (stall > 0)
3413 emit_movimm(stall, 0);
3414 else
3415 emit_mov(HOST_TEMPREG, 0);
2330734f 3416 emit_addimm(HOST_CCREG, ccadj[i], 1);
e3c6bdb5 3417 emit_far_call(log_gte_stall);
3418 restore_regs(reglist);
3419}
3420#endif
3421
32631e6a 3422static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist)
81dbbf4c 3423{
e3c6bdb5 3424 int j = i, other_gte_op_cycles = -1, stall = -MAXBLOCK, cycles_passed;
3425 int rtmp = reglist_find_free(reglist);
3426
32631e6a 3427 if (HACK_ENABLED(NDHACK_NO_STALLS))
81dbbf4c 3428 return;
81dbbf4c 3429 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3430 // happens occasionally... cc evicted? Don't bother then
3431 //printf("no cc %08x\n", start + i*4);
3432 return;
3433 }
cf95b4f0 3434 if (!dops[i].bt) {
e3c6bdb5 3435 for (j = i - 1; j >= 0; j--) {
cf95b4f0 3436 //if (dops[j].is_ds) break;
3437 if (cop2_is_stalling_op(j, &other_gte_op_cycles) || dops[j].bt)
e3c6bdb5 3438 break;
2330734f 3439 if (j > 0 && ccadj[j - 1] > ccadj[j])
3440 break;
e3c6bdb5 3441 }
32631e6a 3442 j = max(j, 0);
e3c6bdb5 3443 }
2330734f 3444 cycles_passed = ccadj[i] - ccadj[j];
e3c6bdb5 3445 if (other_gte_op_cycles >= 0)
3446 stall = other_gte_op_cycles - cycles_passed;
3447 else if (cycles_passed >= 44)
3448 stall = 0; // can't stall
3449 if (stall == -MAXBLOCK && rtmp >= 0) {
3450 // unknown stall, do the expensive runtime check
32631e6a 3451 assem_debug("; cop2_do_stall_check\n");
e3c6bdb5 3452#if 0 // too slow
3453 save_regs(reglist);
3454 emit_movimm(gte_cycletab[op], 0);
2330734f 3455 emit_addimm(HOST_CCREG, ccadj[i], 1);
e3c6bdb5 3456 emit_far_call(call_gteStall);
3457 restore_regs(reglist);
3458#else
3459 host_tempreg_acquire();
3460 emit_readword(&psxRegs.gteBusyCycle, rtmp);
2330734f 3461 emit_addimm(rtmp, -ccadj[i], rtmp);
e3c6bdb5 3462 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3463 emit_cmpimm(HOST_TEMPREG, 44);
3464 emit_cmovb_reg(rtmp, HOST_CCREG);
3465 //emit_log_gte_stall(i, 0, reglist);
3466 host_tempreg_release();
3467#endif
3468 }
3469 else if (stall > 0) {
3470 //emit_log_gte_stall(i, stall, reglist);
3471 emit_addimm(HOST_CCREG, stall, HOST_CCREG);
3472 }
3473
3474 // save gteBusyCycle, if needed
3475 if (gte_cycletab[op] == 0)
3476 return;
3477 other_gte_op_cycles = -1;
3478 for (j = i + 1; j < slen; j++) {
3479 if (cop2_is_stalling_op(j, &other_gte_op_cycles))
3480 break;
fe807a8a 3481 if (dops[j].is_jump) {
e3c6bdb5 3482 // check ds
3483 if (j + 1 < slen && cop2_is_stalling_op(j + 1, &other_gte_op_cycles))
3484 j++;
3485 break;
3486 }
3487 }
3488 if (other_gte_op_cycles >= 0)
3489 // will handle stall when assembling that op
3490 return;
2330734f 3491 cycles_passed = ccadj[min(j, slen -1)] - ccadj[i];
e3c6bdb5 3492 if (cycles_passed >= 44)
3493 return;
3494 assem_debug("; save gteBusyCycle\n");
3495 host_tempreg_acquire();
3496#if 0
3497 emit_readword(&last_count, HOST_TEMPREG);
3498 emit_add(HOST_TEMPREG, HOST_CCREG, HOST_TEMPREG);
2330734f 3499 emit_addimm(HOST_TEMPREG, ccadj[i], HOST_TEMPREG);
e3c6bdb5 3500 emit_addimm(HOST_TEMPREG, gte_cycletab[op]), HOST_TEMPREG);
3501 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3502#else
2330734f 3503 emit_addimm(HOST_CCREG, ccadj[i] + gte_cycletab[op], HOST_TEMPREG);
e3c6bdb5 3504 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3505#endif
3506 host_tempreg_release();
81dbbf4c 3507}
3508
32631e6a 3509static int is_mflohi(int i)
3510{
cf95b4f0 3511 return (dops[i].itype == MOV && (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG));
32631e6a 3512}
3513
3514static int check_multdiv(int i, int *cycles)
3515{
cf95b4f0 3516 if (dops[i].itype != MULTDIV)
32631e6a 3517 return 0;
cf95b4f0 3518 if (dops[i].opcode2 == 0x18 || dops[i].opcode2 == 0x19) // MULT(U)
32631e6a 3519 *cycles = 11; // approx from 7 11 14
3520 else
3521 *cycles = 37;
3522 return 1;
3523}
3524
2330734f 3525static void multdiv_prepare_stall(int i, const struct regstat *i_regs, int ccadj_)
32631e6a 3526{
3527 int j, found = 0, c = 0;
3528 if (HACK_ENABLED(NDHACK_NO_STALLS))
3529 return;
3530 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3531 // happens occasionally... cc evicted? Don't bother then
3532 return;
3533 }
3534 for (j = i + 1; j < slen; j++) {
cf95b4f0 3535 if (dops[j].bt)
32631e6a 3536 break;
3537 if ((found = is_mflohi(j)))
3538 break;
fe807a8a 3539 if (dops[j].is_jump) {
32631e6a 3540 // check ds
3541 if (j + 1 < slen && (found = is_mflohi(j + 1)))
3542 j++;
3543 break;
3544 }
3545 }
3546 if (found)
3547 // handle all in multdiv_do_stall()
3548 return;
3549 check_multdiv(i, &c);
3550 assert(c > 0);
3551 assem_debug("; muldiv prepare stall %d\n", c);
3552 host_tempreg_acquire();
2330734f 3553 emit_addimm(HOST_CCREG, ccadj_ + c, HOST_TEMPREG);
32631e6a 3554 emit_writeword(HOST_TEMPREG, &psxRegs.muldivBusyCycle);
3555 host_tempreg_release();
3556}
3557
3558static void multdiv_do_stall(int i, const struct regstat *i_regs)
3559{
3560 int j, known_cycles = 0;
3561 u_int reglist = get_host_reglist(i_regs->regmap);
3562 int rtmp = get_reg(i_regs->regmap, -1);
3563 if (rtmp < 0)
3564 rtmp = reglist_find_free(reglist);
3565 if (HACK_ENABLED(NDHACK_NO_STALLS))
3566 return;
3567 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG || rtmp < 0) {
3568 // happens occasionally... cc evicted? Don't bother then
3569 //printf("no cc/rtmp %08x\n", start + i*4);
3570 return;
3571 }
cf95b4f0 3572 if (!dops[i].bt) {
32631e6a 3573 for (j = i - 1; j >= 0; j--) {
cf95b4f0 3574 if (dops[j].is_ds) break;
2330734f 3575 if (check_multdiv(j, &known_cycles))
32631e6a 3576 break;
3577 if (is_mflohi(j))
3578 // already handled by this op
3579 return;
2330734f 3580 if (dops[j].bt || (j > 0 && ccadj[j - 1] > ccadj[j]))
3581 break;
32631e6a 3582 }
3583 j = max(j, 0);
3584 }
3585 if (known_cycles > 0) {
2330734f 3586 known_cycles -= ccadj[i] - ccadj[j];
32631e6a 3587 assem_debug("; muldiv stall resolved %d\n", known_cycles);
3588 if (known_cycles > 0)
3589 emit_addimm(HOST_CCREG, known_cycles, HOST_CCREG);
3590 return;
3591 }
3592 assem_debug("; muldiv stall unresolved\n");
3593 host_tempreg_acquire();
3594 emit_readword(&psxRegs.muldivBusyCycle, rtmp);
2330734f 3595 emit_addimm(rtmp, -ccadj[i], rtmp);
32631e6a 3596 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3597 emit_cmpimm(HOST_TEMPREG, 37);
3598 emit_cmovb_reg(rtmp, HOST_CCREG);
3599 //emit_log_gte_stall(i, 0, reglist);
3600 host_tempreg_release();
3601}
3602
8062d65a 3603static void cop2_get_dreg(u_int copr,signed char tl,signed char temp)
3604{
3605 switch (copr) {
3606 case 1:
3607 case 3:
3608 case 5:
3609 case 8:
3610 case 9:
3611 case 10:
3612 case 11:
3613 emit_readword(&reg_cop2d[copr],tl);
3614 emit_signextend16(tl,tl);
3615 emit_writeword(tl,&reg_cop2d[copr]); // hmh
3616 break;
3617 case 7:
3618 case 16:
3619 case 17:
3620 case 18:
3621 case 19:
3622 emit_readword(&reg_cop2d[copr],tl);
3623 emit_andimm(tl,0xffff,tl);
3624 emit_writeword(tl,&reg_cop2d[copr]);
3625 break;
3626 case 15:
3627 emit_readword(&reg_cop2d[14],tl); // SXY2
3628 emit_writeword(tl,&reg_cop2d[copr]);
3629 break;
3630 case 28:
3631 case 29:
3968e69e 3632 c2op_mfc2_29_assemble(tl,temp);
8062d65a 3633 break;
3634 default:
3635 emit_readword(&reg_cop2d[copr],tl);
3636 break;
3637 }
3638}
3639
3640static void cop2_put_dreg(u_int copr,signed char sl,signed char temp)
3641{
3642 switch (copr) {
3643 case 15:
3644 emit_readword(&reg_cop2d[13],temp); // SXY1
3645 emit_writeword(sl,&reg_cop2d[copr]);
3646 emit_writeword(temp,&reg_cop2d[12]); // SXY0
3647 emit_readword(&reg_cop2d[14],temp); // SXY2
3648 emit_writeword(sl,&reg_cop2d[14]);
3649 emit_writeword(temp,&reg_cop2d[13]); // SXY1
3650 break;
3651 case 28:
3652 emit_andimm(sl,0x001f,temp);
3653 emit_shlimm(temp,7,temp);
3654 emit_writeword(temp,&reg_cop2d[9]);
3655 emit_andimm(sl,0x03e0,temp);
3656 emit_shlimm(temp,2,temp);
3657 emit_writeword(temp,&reg_cop2d[10]);
3658 emit_andimm(sl,0x7c00,temp);
3659 emit_shrimm(temp,3,temp);
3660 emit_writeword(temp,&reg_cop2d[11]);
3661 emit_writeword(sl,&reg_cop2d[28]);
3662 break;
3663 case 30:
3968e69e 3664 emit_xorsar_imm(sl,sl,31,temp);
be516ebe 3665#if defined(HAVE_ARMV5) || defined(__aarch64__)
8062d65a 3666 emit_clz(temp,temp);
3667#else
3668 emit_movs(temp,HOST_TEMPREG);
3669 emit_movimm(0,temp);
3670 emit_jeq((int)out+4*4);
3671 emit_addpl_imm(temp,1,temp);
3672 emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG);
3673 emit_jns((int)out-2*4);
3674#endif
3675 emit_writeword(sl,&reg_cop2d[30]);
3676 emit_writeword(temp,&reg_cop2d[31]);
3677 break;
3678 case 31:
3679 break;
3680 default:
3681 emit_writeword(sl,&reg_cop2d[copr]);
3682 break;
3683 }
3684}
3685
2330734f 3686static void c2ls_assemble(int i, const struct regstat *i_regs, int ccadj_)
b9b61529 3687{
3688 int s,tl;
3689 int ar;
3690 int offset;
1fd1aceb 3691 int memtarget=0,c=0;
b14b6a8f 3692 void *jaddr2=NULL;
3693 enum stub_type type;
b9b61529 3694 int agr=AGEN1+(i&1);
37387d8b 3695 int offset_reg = -1;
3696 int fastio_reg_override = -1;
81dbbf4c 3697 u_int reglist=get_host_reglist(i_regs->regmap);
b9b61529 3698 u_int copr=(source[i]>>16)&0x1f;
cf95b4f0 3699 s=get_reg(i_regs->regmap,dops[i].rs1);
b9b61529 3700 tl=get_reg(i_regs->regmap,FTEMP);
3701 offset=imm[i];
cf95b4f0 3702 assert(dops[i].rs1>0);
b9b61529 3703 assert(tl>=0);
b9b61529 3704
b9b61529 3705 if(i_regs->regmap[HOST_CCREG]==CCREG)
3706 reglist&=~(1<<HOST_CCREG);
3707
3708 // get the address
cf95b4f0 3709 if (dops[i].opcode==0x3a) { // SWC2
b9b61529 3710 ar=get_reg(i_regs->regmap,agr);
3711 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3712 reglist|=1<<ar;
3713 } else { // LWC2
3714 ar=tl;
3715 }
1fd1aceb 3716 if(s>=0) c=(i_regs->wasconst>>s)&1;
3717 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
b9b61529 3718 if (!offset&&!c&&s>=0) ar=s;
3719 assert(ar>=0);
3720
32631e6a 3721 cop2_do_stall_check(0, i, i_regs, reglist);
3722
cf95b4f0 3723 if (dops[i].opcode==0x3a) { // SWC2
3968e69e 3724 cop2_get_dreg(copr,tl,-1);
1fd1aceb 3725 type=STOREW_STUB;
b9b61529 3726 }
1fd1aceb 3727 else
b9b61529 3728 type=LOADW_STUB;
1fd1aceb 3729
3730 if(c&&!memtarget) {
b14b6a8f 3731 jaddr2=out;
1fd1aceb 3732 emit_jmp(0); // inline_readstub/inline_writestub?
b9b61529 3733 }
1fd1aceb 3734 else {
3735 if(!c) {
37387d8b 3736 jaddr2 = emit_fastpath_cmp_jump(i, i_regs, ar,
3737 &offset_reg, &fastio_reg_override);
3738 }
3739 else if (ram_offset && memtarget) {
3740 offset_reg = get_ro_reg(i_regs, 0);
3741 }
3742 switch (dops[i].opcode) {
3743 case 0x32: { // LWC2
3744 int a = ar;
3745 if (fastio_reg_override >= 0)
3746 a = fastio_reg_override;
3747 do_load_word(a, tl, offset_reg);
3748 break;
1fd1aceb 3749 }
37387d8b 3750 case 0x3a: { // SWC2
1fd1aceb 3751 #ifdef DESTRUCTIVE_SHIFT
3752 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3753 #endif
37387d8b 3754 int a = ar;
3755 if (fastio_reg_override >= 0)
3756 a = fastio_reg_override;
3757 do_store_word(a, 0, tl, offset_reg, 1);
3758 break;
3759 }
3760 default:
3761 assert(0);
1fd1aceb 3762 }
b9b61529 3763 }
37387d8b 3764 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
d1e4ebd9 3765 host_tempreg_release();
b9b61529 3766 if(jaddr2)
2330734f 3767 add_stub_r(type,jaddr2,out,i,ar,i_regs,ccadj_,reglist);
cf95b4f0 3768 if(dops[i].opcode==0x3a) // SWC2
3769 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
b9b61529 3770#if defined(HOST_IMM8)
3771 int ir=get_reg(i_regs->regmap,INVCP);
3772 assert(ir>=0);
3773 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3774#else
643aeae3 3775 emit_cmpmem_indexedsr12_imm(invalid_code,ar,1);
b9b61529 3776#endif
0bbd1454 3777 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3778 emit_callne(invalidate_addr_reg[ar]);
3779 #else
b14b6a8f 3780 void *jaddr3 = out;
b9b61529 3781 emit_jne(0);
b14b6a8f 3782 add_stub(INVCODE_STUB,jaddr3,out,reglist|(1<<HOST_CCREG),ar,0,0,0);
0bbd1454 3783 #endif
b9b61529 3784 }
cf95b4f0 3785 if (dops[i].opcode==0x32) { // LWC2
d1e4ebd9 3786 host_tempreg_acquire();
b9b61529 3787 cop2_put_dreg(copr,tl,HOST_TEMPREG);
d1e4ebd9 3788 host_tempreg_release();
b9b61529 3789 }
3790}
3791
81dbbf4c 3792static void cop2_assemble(int i, const struct regstat *i_regs)
8062d65a 3793{
81dbbf4c 3794 u_int copr = (source[i]>>11) & 0x1f;
3795 signed char temp = get_reg(i_regs->regmap, -1);
3796
32631e6a 3797 if (!HACK_ENABLED(NDHACK_NO_STALLS)) {
3798 u_int reglist = reglist_exclude(get_host_reglist(i_regs->regmap), temp, -1);
cf95b4f0 3799 if (dops[i].opcode2 == 0 || dops[i].opcode2 == 2) { // MFC2/CFC2
3800 signed char tl = get_reg(i_regs->regmap, dops[i].rt1);
32631e6a 3801 reglist = reglist_exclude(reglist, tl, -1);
81dbbf4c 3802 }
32631e6a 3803 cop2_do_stall_check(0, i, i_regs, reglist);
81dbbf4c 3804 }
cf95b4f0 3805 if (dops[i].opcode2==0) { // MFC2
3806 signed char tl=get_reg(i_regs->regmap,dops[i].rt1);
3807 if(tl>=0&&dops[i].rt1!=0)
8062d65a 3808 cop2_get_dreg(copr,tl,temp);
3809 }
cf95b4f0 3810 else if (dops[i].opcode2==4) { // MTC2
3811 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
8062d65a 3812 cop2_put_dreg(copr,sl,temp);
3813 }
cf95b4f0 3814 else if (dops[i].opcode2==2) // CFC2
8062d65a 3815 {
cf95b4f0 3816 signed char tl=get_reg(i_regs->regmap,dops[i].rt1);
3817 if(tl>=0&&dops[i].rt1!=0)
8062d65a 3818 emit_readword(&reg_cop2c[copr],tl);
3819 }
cf95b4f0 3820 else if (dops[i].opcode2==6) // CTC2
8062d65a 3821 {
cf95b4f0 3822 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
8062d65a 3823 switch(copr) {
3824 case 4:
3825 case 12:
3826 case 20:
3827 case 26:
3828 case 27:
3829 case 29:
3830 case 30:
3831 emit_signextend16(sl,temp);
3832 break;
3833 case 31:
3968e69e 3834 c2op_ctc2_31_assemble(sl,temp);
8062d65a 3835 break;
3836 default:
3837 temp=sl;
3838 break;
3839 }
3840 emit_writeword(temp,&reg_cop2c[copr]);
3841 assert(sl>=0);
3842 }
3843}
3844
3968e69e 3845static void do_unalignedwritestub(int n)
3846{
3847 assem_debug("do_unalignedwritestub %x\n",start+stubs[n].a*4);
3848 literal_pool(256);
3849 set_jump_target(stubs[n].addr, out);
3850
3851 int i=stubs[n].a;
3852 struct regstat *i_regs=(struct regstat *)stubs[n].c;
3853 int addr=stubs[n].b;
3854 u_int reglist=stubs[n].e;
3855 signed char *i_regmap=i_regs->regmap;
3856 int temp2=get_reg(i_regmap,FTEMP);
3857 int rt;
cf95b4f0 3858 rt=get_reg(i_regmap,dops[i].rs2);
3968e69e 3859 assert(rt>=0);
3860 assert(addr>=0);
cf95b4f0 3861 assert(dops[i].opcode==0x2a||dops[i].opcode==0x2e); // SWL/SWR only implemented
3968e69e 3862 reglist|=(1<<addr);
3863 reglist&=~(1<<temp2);
3864
3968e69e 3865 // don't bother with it and call write handler
3866 save_regs(reglist);
3867 pass_args(addr,rt);
3868 int cc=get_reg(i_regmap,CCREG);
3869 if(cc<0)
3870 emit_loadreg(CCREG,2);
2330734f 3871 emit_addimm(cc<0?2:cc,(int)stubs[n].d+1,2);
cf95b4f0 3872 emit_far_call((dops[i].opcode==0x2a?jump_handle_swl:jump_handle_swr));
2330734f 3873 emit_addimm(0,-((int)stubs[n].d+1),cc<0?2:cc);
3968e69e 3874 if(cc<0)
3875 emit_storereg(CCREG,2);
3876 restore_regs(reglist);
3877 emit_jmp(stubs[n].retaddr); // return address
3968e69e 3878}
3879
57871462 3880#ifndef multdiv_assemble
3881void multdiv_assemble(int i,struct regstat *i_regs)
3882{
3883 printf("Need multdiv_assemble for this architecture.\n");
7c3a5182 3884 abort();
57871462 3885}
3886#endif
3887
2330734f 3888static void mov_assemble(int i, const struct regstat *i_regs)
57871462 3889{
cf95b4f0 3890 //if(dops[i].opcode2==0x10||dops[i].opcode2==0x12) { // MFHI/MFLO
3891 //if(dops[i].opcode2==0x11||dops[i].opcode2==0x13) { // MTHI/MTLO
3892 if(dops[i].rt1) {
7c3a5182 3893 signed char sl,tl;
cf95b4f0 3894 tl=get_reg(i_regs->regmap,dops[i].rt1);
57871462 3895 //assert(tl>=0);
3896 if(tl>=0) {
cf95b4f0 3897 sl=get_reg(i_regs->regmap,dops[i].rs1);
57871462 3898 if(sl>=0) emit_mov(sl,tl);
cf95b4f0 3899 else emit_loadreg(dops[i].rs1,tl);
57871462 3900 }
3901 }
cf95b4f0 3902 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) // MFHI/MFLO
32631e6a 3903 multdiv_do_stall(i, i_regs);
57871462 3904}
3905
3968e69e 3906// call interpreter, exception handler, things that change pc/regs/cycles ...
2330734f 3907static void call_c_cpu_handler(int i, const struct regstat *i_regs, int ccadj_, u_int pc, void *func)
57871462 3908{
3909 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3910 assert(ccreg==HOST_CCREG);
3911 assert(!is_delayslot);
581335b0 3912 (void)ccreg;
3968e69e 3913
3914 emit_movimm(pc,3); // Get PC
3915 emit_readword(&last_count,2);
3916 emit_writeword(3,&psxRegs.pc);
2330734f 3917 emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG);
3968e69e 3918 emit_add(2,HOST_CCREG,2);
3919 emit_writeword(2,&psxRegs.cycle);
2a014d73 3920 emit_far_call(func);
3921 emit_far_jump(jump_to_new_pc);
3968e69e 3922}
3923
2330734f 3924static void syscall_assemble(int i, const struct regstat *i_regs, int ccadj_)
3968e69e 3925{
3926 emit_movimm(0x20,0); // cause code
3927 emit_movimm(0,1); // not in delay slot
2330734f 3928 call_c_cpu_handler(i, i_regs, ccadj_, start+i*4, psxException);
7139f3c8 3929}
3930
2330734f 3931static void hlecall_assemble(int i, const struct regstat *i_regs, int ccadj_)
7139f3c8 3932{
3968e69e 3933 void *hlefunc = psxNULL;
dd79da89 3934 uint32_t hleCode = source[i] & 0x03ffffff;
3968e69e 3935 if (hleCode < ARRAY_SIZE(psxHLEt))
3936 hlefunc = psxHLEt[hleCode];
3937
2330734f 3938 call_c_cpu_handler(i, i_regs, ccadj_, start + i*4+4, hlefunc);
57871462 3939}
3940
2330734f 3941static void intcall_assemble(int i, const struct regstat *i_regs, int ccadj_)
1e973cb0 3942{
2330734f 3943 call_c_cpu_handler(i, i_regs, ccadj_, start + i*4, execI);
1e973cb0 3944}
3945
8062d65a 3946static void speculate_mov(int rs,int rt)
3947{
3948 if(rt!=0) {
3949 smrv_strong_next|=1<<rt;
3950 smrv[rt]=smrv[rs];
3951 }
3952}
3953
3954static void speculate_mov_weak(int rs,int rt)
3955{
3956 if(rt!=0) {
3957 smrv_weak_next|=1<<rt;
3958 smrv[rt]=smrv[rs];
3959 }
3960}
3961
3962static void speculate_register_values(int i)
3963{
3964 if(i==0) {
3965 memcpy(smrv,psxRegs.GPR.r,sizeof(smrv));
3966 // gp,sp are likely to stay the same throughout the block
3967 smrv_strong_next=(1<<28)|(1<<29)|(1<<30);
3968 smrv_weak_next=~smrv_strong_next;
3969 //printf(" llr %08x\n", smrv[4]);
3970 }
3971 smrv_strong=smrv_strong_next;
3972 smrv_weak=smrv_weak_next;
cf95b4f0 3973 switch(dops[i].itype) {
8062d65a 3974 case ALU:
cf95b4f0 3975 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
3976 else if((smrv_strong>>dops[i].rs2)&1) speculate_mov(dops[i].rs2,dops[i].rt1);
3977 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
3978 else if((smrv_weak>>dops[i].rs2)&1) speculate_mov_weak(dops[i].rs2,dops[i].rt1);
8062d65a 3979 else {
cf95b4f0 3980 smrv_strong_next&=~(1<<dops[i].rt1);
3981 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 3982 }
3983 break;
3984 case SHIFTIMM:
cf95b4f0 3985 smrv_strong_next&=~(1<<dops[i].rt1);
3986 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 3987 // fallthrough
3988 case IMM16:
cf95b4f0 3989 if(dops[i].rt1&&is_const(&regs[i],dops[i].rt1)) {
3990 int value,hr=get_reg(regs[i].regmap,dops[i].rt1);
8062d65a 3991 if(hr>=0) {
3992 if(get_final_value(hr,i,&value))
cf95b4f0 3993 smrv[dops[i].rt1]=value;
3994 else smrv[dops[i].rt1]=constmap[i][hr];
3995 smrv_strong_next|=1<<dops[i].rt1;
8062d65a 3996 }
3997 }
3998 else {
cf95b4f0 3999 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
4000 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
8062d65a 4001 }
4002 break;
4003 case LOAD:
cf95b4f0 4004 if(start<0x2000&&(dops[i].rt1==26||(smrv[dops[i].rt1]>>24)==0xa0)) {
8062d65a 4005 // special case for BIOS
cf95b4f0 4006 smrv[dops[i].rt1]=0xa0000000;
4007 smrv_strong_next|=1<<dops[i].rt1;
8062d65a 4008 break;
4009 }
4010 // fallthrough
4011 case SHIFT:
4012 case LOADLR:
4013 case MOV:
cf95b4f0 4014 smrv_strong_next&=~(1<<dops[i].rt1);
4015 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4016 break;
4017 case COP0:
4018 case COP2:
cf95b4f0 4019 if(dops[i].opcode2==0||dops[i].opcode2==2) { // MFC/CFC
4020 smrv_strong_next&=~(1<<dops[i].rt1);
4021 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4022 }
4023 break;
4024 case C2LS:
cf95b4f0 4025 if (dops[i].opcode==0x32) { // LWC2
4026 smrv_strong_next&=~(1<<dops[i].rt1);
4027 smrv_weak_next&=~(1<<dops[i].rt1);
8062d65a 4028 }
4029 break;
4030 }
4031#if 0
4032 int r=4;
4033 printf("x %08x %08x %d %d c %08x %08x\n",smrv[r],start+i*4,
4034 ((smrv_strong>>r)&1),(smrv_weak>>r)&1,regs[i].isconst,regs[i].wasconst);
4035#endif
4036}
4037
2330734f 4038static void ujump_assemble(int i, const struct regstat *i_regs);
4039static void rjump_assemble(int i, const struct regstat *i_regs);
4040static void cjump_assemble(int i, const struct regstat *i_regs);
4041static void sjump_assemble(int i, const struct regstat *i_regs);
4042static void pagespan_assemble(int i, const struct regstat *i_regs);
4043
4044static int assemble(int i, const struct regstat *i_regs, int ccadj_)
57871462 4045{
2330734f 4046 int ds = 0;
4047 switch (dops[i].itype) {
57871462 4048 case ALU:
2330734f 4049 alu_assemble(i, i_regs);
4050 break;
57871462 4051 case IMM16:
2330734f 4052 imm16_assemble(i, i_regs);
4053 break;
57871462 4054 case SHIFT:
2330734f 4055 shift_assemble(i, i_regs);
4056 break;
57871462 4057 case SHIFTIMM:
2330734f 4058 shiftimm_assemble(i, i_regs);
4059 break;
57871462 4060 case LOAD:
2330734f 4061 load_assemble(i, i_regs, ccadj_);
4062 break;
57871462 4063 case LOADLR:
2330734f 4064 loadlr_assemble(i, i_regs, ccadj_);
4065 break;
57871462 4066 case STORE:
2330734f 4067 store_assemble(i, i_regs, ccadj_);
4068 break;
57871462 4069 case STORELR:
2330734f 4070 storelr_assemble(i, i_regs, ccadj_);
4071 break;
57871462 4072 case COP0:
2330734f 4073 cop0_assemble(i, i_regs, ccadj_);
4074 break;
57871462 4075 case COP1:
2330734f 4076 cop1_assemble(i, i_regs);
4077 break;
57871462 4078 case C1LS:
2330734f 4079 c1ls_assemble(i, i_regs);
4080 break;
b9b61529 4081 case COP2:
2330734f 4082 cop2_assemble(i, i_regs);
4083 break;
b9b61529 4084 case C2LS:
2330734f 4085 c2ls_assemble(i, i_regs, ccadj_);
4086 break;
b9b61529 4087 case C2OP:
2330734f 4088 c2op_assemble(i, i_regs);
4089 break;
57871462 4090 case MULTDIV:
2330734f 4091 multdiv_assemble(i, i_regs);
4092 multdiv_prepare_stall(i, i_regs, ccadj_);
32631e6a 4093 break;
57871462 4094 case MOV:
2330734f 4095 mov_assemble(i, i_regs);
4096 break;
4097 case SYSCALL:
4098 syscall_assemble(i, i_regs, ccadj_);
4099 break;
4100 case HLECALL:
4101 hlecall_assemble(i, i_regs, ccadj_);
4102 break;
4103 case INTCALL:
4104 intcall_assemble(i, i_regs, ccadj_);
4105 break;
4106 case UJUMP:
4107 ujump_assemble(i, i_regs);
4108 ds = 1;
4109 break;
4110 case RJUMP:
4111 rjump_assemble(i, i_regs);
4112 ds = 1;
4113 break;
4114 case CJUMP:
4115 cjump_assemble(i, i_regs);
4116 ds = 1;
4117 break;
4118 case SJUMP:
4119 sjump_assemble(i, i_regs);
4120 ds = 1;
4121 break;
4122 case SPAN:
4123 pagespan_assemble(i, i_regs);
4124 break;
4125 case OTHER:
4126 case NI:
4127 // not handled, just skip
4128 break;
4129 default:
4130 assert(0);
4131 }
4132 return ds;
4133}
4134
4135static void ds_assemble(int i, const struct regstat *i_regs)
4136{
4137 speculate_register_values(i);
4138 is_delayslot = 1;
4139 switch (dops[i].itype) {
57871462 4140 case SYSCALL:
7139f3c8 4141 case HLECALL:
1e973cb0 4142 case INTCALL:
57871462 4143 case SPAN:
4144 case UJUMP:
4145 case RJUMP:
4146 case CJUMP:
4147 case SJUMP:
c43b5311 4148 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
2330734f 4149 break;
4150 default:
4151 assemble(i, i_regs, ccadj[i]);
57871462 4152 }
2330734f 4153 is_delayslot = 0;
57871462 4154}
4155
4156// Is the branch target a valid internal jump?
ad49de89 4157static int internal_branch(int addr)
57871462 4158{
4159 if(addr&1) return 0; // Indirect (register) jump
4160 if(addr>=start && addr<start+slen*4-4)
4161 {
71e490c5 4162 return 1;
57871462 4163 }
4164 return 0;
4165}
4166
ad49de89 4167static void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t u)
57871462 4168{
4169 int hr;
4170 for(hr=0;hr<HOST_REGS;hr++) {
4171 if(hr!=EXCLUDE_REG) {
4172 if(pre[hr]!=entry[hr]) {
4173 if(pre[hr]>=0) {
4174 if((dirty>>hr)&1) {
4175 if(get_reg(entry,pre[hr])<0) {
00fa9369 4176 assert(pre[hr]<64);
4177 if(!((u>>pre[hr])&1))
4178 emit_storereg(pre[hr],hr);
57871462 4179 }
4180 }
4181 }
4182 }
4183 }
4184 }
4185 // Move from one register to another (no writeback)
4186 for(hr=0;hr<HOST_REGS;hr++) {
4187 if(hr!=EXCLUDE_REG) {
4188 if(pre[hr]!=entry[hr]) {
4189 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
4190 int nr;
4191 if((nr=get_reg(entry,pre[hr]))>=0) {
4192 emit_mov(hr,nr);
4193 }
4194 }
4195 }
4196 }
4197 }
4198}
57871462 4199
4200// Load the specified registers
4201// This only loads the registers given as arguments because
4202// we don't want to load things that will be overwritten
ad49de89 4203static void load_regs(signed char entry[],signed char regmap[],int rs1,int rs2)
57871462 4204{
4205 int hr;
4206 // Load 32-bit regs
4207 for(hr=0;hr<HOST_REGS;hr++) {
4208 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4209 if(entry[hr]!=regmap[hr]) {
4210 if(regmap[hr]==rs1||regmap[hr]==rs2)
4211 {
4212 if(regmap[hr]==0) {
4213 emit_zeroreg(hr);
4214 }
4215 else
4216 {
4217 emit_loadreg(regmap[hr],hr);
4218 }
4219 }
4220 }
4221 }
4222 }
57871462 4223}
4224
4225// Load registers prior to the start of a loop
4226// so that they are not loaded within the loop
4227static void loop_preload(signed char pre[],signed char entry[])
4228{
4229 int hr;
4230 for(hr=0;hr<HOST_REGS;hr++) {
4231 if(hr!=EXCLUDE_REG) {
4232 if(pre[hr]!=entry[hr]) {
4233 if(entry[hr]>=0) {
4234 if(get_reg(pre,entry[hr])<0) {
4235 assem_debug("loop preload:\n");
4236 //printf("loop preload: %d\n",hr);
4237 if(entry[hr]==0) {
4238 emit_zeroreg(hr);
4239 }
4240 else if(entry[hr]<TEMPREG)
4241 {
4242 emit_loadreg(entry[hr],hr);
4243 }
4244 else if(entry[hr]-64<TEMPREG)
4245 {
4246 emit_loadreg(entry[hr],hr);
4247 }
4248 }
4249 }
4250 }
4251 }
4252 }
4253}
4254
4255// Generate address for load/store instruction
b9b61529 4256// goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
2330734f 4257void address_generation(int i, const struct regstat *i_regs, signed char entry[])
57871462 4258{
37387d8b 4259 if (dops[i].is_load || dops[i].is_store) {
5194fb95 4260 int ra=-1;
57871462 4261 int agr=AGEN1+(i&1);
cf95b4f0 4262 if(dops[i].itype==LOAD) {
4263 ra=get_reg(i_regs->regmap,dops[i].rt1);
9f51b4b9 4264 if(ra<0) ra=get_reg(i_regs->regmap,-1);
535d208a 4265 assert(ra>=0);
57871462 4266 }
cf95b4f0 4267 if(dops[i].itype==LOADLR) {
57871462 4268 ra=get_reg(i_regs->regmap,FTEMP);
4269 }
cf95b4f0 4270 if(dops[i].itype==STORE||dops[i].itype==STORELR) {
57871462 4271 ra=get_reg(i_regs->regmap,agr);
4272 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4273 }
37387d8b 4274 if(dops[i].itype==C2LS) {
cf95b4f0 4275 if ((dops[i].opcode&0x3b)==0x31||(dops[i].opcode&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
57871462 4276 ra=get_reg(i_regs->regmap,FTEMP);
1fd1aceb 4277 else { // SWC1/SDC1/SWC2/SDC2
57871462 4278 ra=get_reg(i_regs->regmap,agr);
4279 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4280 }
4281 }
cf95b4f0 4282 int rs=get_reg(i_regs->regmap,dops[i].rs1);
57871462 4283 if(ra>=0) {
4284 int offset=imm[i];
4285 int c=(i_regs->wasconst>>rs)&1;
cf95b4f0 4286 if(dops[i].rs1==0) {
57871462 4287 // Using r0 as a base address
57871462 4288 if(!entry||entry[ra]!=agr) {
cf95b4f0 4289 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
57871462 4290 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
cf95b4f0 4291 }else if (dops[i].opcode==0x1a||dops[i].opcode==0x1b) {
57871462 4292 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4293 }else{
4294 emit_movimm(offset,ra);
4295 }
4296 } // else did it in the previous cycle
4297 }
4298 else if(rs<0) {
cf95b4f0 4299 if(!entry||entry[ra]!=dops[i].rs1)
4300 emit_loadreg(dops[i].rs1,ra);
4301 //if(!entry||entry[ra]!=dops[i].rs1)
57871462 4302 // printf("poor load scheduling!\n");
4303 }
4304 else if(c) {
cf95b4f0 4305 if(dops[i].rs1!=dops[i].rt1||dops[i].itype!=LOAD) {
57871462 4306 if(!entry||entry[ra]!=agr) {
cf95b4f0 4307 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
57871462 4308 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
cf95b4f0 4309 }else if (dops[i].opcode==0x1a||dops[i].opcode==0x1b) {
57871462 4310 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4311 }else{
57871462 4312 emit_movimm(constmap[i][rs]+offset,ra);
8575a877 4313 regs[i].loadedconst|=1<<ra;
57871462 4314 }
4315 } // else did it in the previous cycle
4316 } // else load_consts already did it
4317 }
cf95b4f0 4318 if(offset&&!c&&dops[i].rs1) {
57871462 4319 if(rs>=0) {
4320 emit_addimm(rs,offset,ra);
4321 }else{
4322 emit_addimm(ra,offset,ra);
4323 }
4324 }
4325 }
4326 }
4327 // Preload constants for next instruction
37387d8b 4328 if (dops[i+1].is_load || dops[i+1].is_store) {
57871462 4329 int agr,ra;
57871462 4330 // Actual address
4331 agr=AGEN1+((i+1)&1);
4332 ra=get_reg(i_regs->regmap,agr);
4333 if(ra>=0) {
cf95b4f0 4334 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
57871462 4335 int offset=imm[i+1];
4336 int c=(regs[i+1].wasconst>>rs)&1;
cf95b4f0 4337 if(c&&(dops[i+1].rs1!=dops[i+1].rt1||dops[i+1].itype!=LOAD)) {
4338 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
57871462 4339 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
cf95b4f0 4340 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
57871462 4341 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4342 }else{
57871462 4343 emit_movimm(constmap[i+1][rs]+offset,ra);
8575a877 4344 regs[i+1].loadedconst|=1<<ra;
57871462 4345 }
4346 }
cf95b4f0 4347 else if(dops[i+1].rs1==0) {
57871462 4348 // Using r0 as a base address
cf95b4f0 4349 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
57871462 4350 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
cf95b4f0 4351 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
57871462 4352 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4353 }else{
4354 emit_movimm(offset,ra);
4355 }
4356 }
4357 }
4358 }
4359}
4360
e2b5e7aa 4361static int get_final_value(int hr, int i, int *value)
57871462 4362{
4363 int reg=regs[i].regmap[hr];
4364 while(i<slen-1) {
4365 if(regs[i+1].regmap[hr]!=reg) break;
4366 if(!((regs[i+1].isconst>>hr)&1)) break;
cf95b4f0 4367 if(dops[i+1].bt) break;
57871462 4368 i++;
4369 }
4370 if(i<slen-1) {
fe807a8a 4371 if (dops[i].is_jump) {
57871462 4372 *value=constmap[i][hr];
4373 return 1;
4374 }
cf95b4f0 4375 if(!dops[i+1].bt) {
fe807a8a 4376 if (dops[i+1].is_jump) {
57871462 4377 // Load in delay slot, out-of-order execution
cf95b4f0 4378 if(dops[i+2].itype==LOAD&&dops[i+2].rs1==reg&&dops[i+2].rt1==reg&&((regs[i+1].wasconst>>hr)&1))
57871462 4379 {
57871462 4380 // Precompute load address
4381 *value=constmap[i][hr]+imm[i+2];
4382 return 1;
4383 }
4384 }
cf95b4f0 4385 if(dops[i+1].itype==LOAD&&dops[i+1].rs1==reg&&dops[i+1].rt1==reg)
57871462 4386 {
57871462 4387 // Precompute load address
4388 *value=constmap[i][hr]+imm[i+1];
643aeae3 4389 //printf("c=%x imm=%lx\n",(long)constmap[i][hr],imm[i+1]);
57871462 4390 return 1;
4391 }
4392 }
4393 }
4394 *value=constmap[i][hr];
643aeae3 4395 //printf("c=%lx\n",(long)constmap[i][hr]);
57871462 4396 if(i==slen-1) return 1;
00fa9369 4397 assert(reg < 64);
4398 return !((unneeded_reg[i+1]>>reg)&1);
57871462 4399}
4400
4401// Load registers with known constants
ad49de89 4402static void load_consts(signed char pre[],signed char regmap[],int i)
57871462 4403{
8575a877 4404 int hr,hr2;
4405 // propagate loaded constant flags
cf95b4f0 4406 if(i==0||dops[i].bt)
8575a877 4407 regs[i].loadedconst=0;
4408 else {
4409 for(hr=0;hr<HOST_REGS;hr++) {
4410 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((regs[i-1].isconst>>hr)&1)&&pre[hr]==regmap[hr]
4411 &&regmap[hr]==regs[i-1].regmap[hr]&&((regs[i-1].loadedconst>>hr)&1))
4412 {
4413 regs[i].loadedconst|=1<<hr;
4414 }
4415 }
4416 }
57871462 4417 // Load 32-bit regs
4418 for(hr=0;hr<HOST_REGS;hr++) {
4419 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4420 //if(entry[hr]!=regmap[hr]) {
8575a877 4421 if(!((regs[i].loadedconst>>hr)&1)) {
ad49de89 4422 assert(regmap[hr]<64);
4423 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>0) {
8575a877 4424 int value,similar=0;
57871462 4425 if(get_final_value(hr,i,&value)) {
8575a877 4426 // see if some other register has similar value
4427 for(hr2=0;hr2<HOST_REGS;hr2++) {
4428 if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
4429 if(is_similar_value(value,constmap[i][hr2])) {
4430 similar=1;
4431 break;
4432 }
4433 }
4434 }
4435 if(similar) {
4436 int value2;
4437 if(get_final_value(hr2,i,&value2)) // is this needed?
4438 emit_movimm_from(value2,hr2,value,hr);
4439 else
4440 emit_movimm(value,hr);
4441 }
4442 else if(value==0) {
57871462 4443 emit_zeroreg(hr);
4444 }
4445 else {
4446 emit_movimm(value,hr);
4447 }
4448 }
8575a877 4449 regs[i].loadedconst|=1<<hr;
57871462 4450 }
4451 }
4452 }
4453 }
57871462 4454}
ad49de89 4455
2330734f 4456static void load_all_consts(const signed char regmap[], u_int dirty, int i)
57871462 4457{
4458 int hr;
4459 // Load 32-bit regs
4460 for(hr=0;hr<HOST_REGS;hr++) {
4461 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
ad49de89 4462 assert(regmap[hr] < 64);
4463 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>0) {
57871462 4464 int value=constmap[i][hr];
4465 if(value==0) {
4466 emit_zeroreg(hr);
4467 }
4468 else {
4469 emit_movimm(value,hr);
4470 }
4471 }
4472 }
4473 }
57871462 4474}
4475
4476// Write out all dirty registers (except cycle count)
2330734f 4477static void wb_dirtys(const signed char i_regmap[], uint64_t i_dirty)
57871462 4478{
4479 int hr;
4480 for(hr=0;hr<HOST_REGS;hr++) {
4481 if(hr!=EXCLUDE_REG) {
4482 if(i_regmap[hr]>0) {
4483 if(i_regmap[hr]!=CCREG) {
4484 if((i_dirty>>hr)&1) {
00fa9369 4485 assert(i_regmap[hr]<64);
4486 emit_storereg(i_regmap[hr],hr);
57871462 4487 }
4488 }
4489 }
4490 }
4491 }
4492}
ad49de89 4493
57871462 4494// Write out dirty registers that we need to reload (pair with load_needed_regs)
4495// This writes the registers not written by store_regs_bt
2330734f 4496static void wb_needed_dirtys(const signed char i_regmap[], uint64_t i_dirty, int addr)
57871462 4497{
4498 int hr;
4499 int t=(addr-start)>>2;
4500 for(hr=0;hr<HOST_REGS;hr++) {
4501 if(hr!=EXCLUDE_REG) {
4502 if(i_regmap[hr]>0) {
4503 if(i_regmap[hr]!=CCREG) {
ad49de89 4504 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1)) {
57871462 4505 if((i_dirty>>hr)&1) {
00fa9369 4506 assert(i_regmap[hr]<64);
4507 emit_storereg(i_regmap[hr],hr);
57871462 4508 }
4509 }
4510 }
4511 }
4512 }
4513 }
4514}
4515
4516// Load all registers (except cycle count)
2330734f 4517static void load_all_regs(const signed char i_regmap[])
57871462 4518{
4519 int hr;
4520 for(hr=0;hr<HOST_REGS;hr++) {
4521 if(hr!=EXCLUDE_REG) {
4522 if(i_regmap[hr]==0) {
4523 emit_zeroreg(hr);
4524 }
4525 else
ea3d2e6e 4526 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
57871462 4527 {
4528 emit_loadreg(i_regmap[hr],hr);
4529 }
4530 }
4531 }
4532}
4533
4534// Load all current registers also needed by next instruction
2330734f 4535static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[])
57871462 4536{
4537 int hr;
4538 for(hr=0;hr<HOST_REGS;hr++) {
4539 if(hr!=EXCLUDE_REG) {
4540 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4541 if(i_regmap[hr]==0) {
4542 emit_zeroreg(hr);
4543 }
4544 else
ea3d2e6e 4545 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
57871462 4546 {
4547 emit_loadreg(i_regmap[hr],hr);
4548 }
4549 }
4550 }
4551 }
4552}
4553
4554// Load all regs, storing cycle count if necessary
2330734f 4555static void load_regs_entry(int t)
57871462 4556{
4557 int hr;
cf95b4f0 4558 if(dops[t].is_ds) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
2330734f 4559 else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t],HOST_CCREG);
57871462 4560 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4561 emit_storereg(CCREG,HOST_CCREG);
4562 }
4563 // Load 32-bit regs
4564 for(hr=0;hr<HOST_REGS;hr++) {
ea3d2e6e 4565 if(regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
57871462 4566 if(regs[t].regmap_entry[hr]==0) {
4567 emit_zeroreg(hr);
4568 }
4569 else if(regs[t].regmap_entry[hr]!=CCREG)
4570 {
4571 emit_loadreg(regs[t].regmap_entry[hr],hr);
4572 }
4573 }
4574 }
57871462 4575}
4576
4577// Store dirty registers prior to branch
ad49de89 4578void store_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
57871462 4579{
ad49de89 4580 if(internal_branch(addr))
57871462 4581 {
4582 int t=(addr-start)>>2;
4583 int hr;
4584 for(hr=0;hr<HOST_REGS;hr++) {
4585 if(hr!=EXCLUDE_REG) {
4586 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
ad49de89 4587 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1)) {
57871462 4588 if((i_dirty>>hr)&1) {
00fa9369 4589 assert(i_regmap[hr]<64);
4590 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4591 emit_storereg(i_regmap[hr],hr);
57871462 4592 }
4593 }
4594 }
4595 }
4596 }
4597 }
4598 else
4599 {
4600 // Branch out of this block, write out all dirty regs
ad49de89 4601 wb_dirtys(i_regmap,i_dirty);
57871462 4602 }
4603}
4604
4605// Load all needed registers for branch target
ad49de89 4606static void load_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
57871462 4607{
4608 //if(addr>=start && addr<(start+slen*4))
ad49de89 4609 if(internal_branch(addr))
57871462 4610 {
4611 int t=(addr-start)>>2;
4612 int hr;
4613 // Store the cycle count before loading something else
4614 if(i_regmap[HOST_CCREG]!=CCREG) {
4615 assert(i_regmap[HOST_CCREG]==-1);
4616 }
4617 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4618 emit_storereg(CCREG,HOST_CCREG);
4619 }
4620 // Load 32-bit regs
4621 for(hr=0;hr<HOST_REGS;hr++) {
ea3d2e6e 4622 if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
00fa9369 4623 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
57871462 4624 if(regs[t].regmap_entry[hr]==0) {
4625 emit_zeroreg(hr);
4626 }
4627 else if(regs[t].regmap_entry[hr]!=CCREG)
4628 {
4629 emit_loadreg(regs[t].regmap_entry[hr],hr);
4630 }
4631 }
4632 }
4633 }
57871462 4634 }
4635}
4636
ad49de89 4637static int match_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
57871462 4638{
4639 if(addr>=start && addr<start+slen*4-4)
4640 {
4641 int t=(addr-start)>>2;
4642 int hr;
4643 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4644 for(hr=0;hr<HOST_REGS;hr++)
4645 {
4646 if(hr!=EXCLUDE_REG)
4647 {
4648 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4649 {
ea3d2e6e 4650 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
57871462 4651 {
4652 return 0;
4653 }
9f51b4b9 4654 else
57871462 4655 if((i_dirty>>hr)&1)
4656 {
ea3d2e6e 4657 if(i_regmap[hr]<TEMPREG)
57871462 4658 {
4659 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4660 return 0;
4661 }
ea3d2e6e 4662 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
57871462 4663 {
00fa9369 4664 assert(0);
57871462 4665 }
4666 }
4667 }
4668 else // Same register but is it 32-bit or dirty?
4669 if(i_regmap[hr]>=0)
4670 {
4671 if(!((regs[t].dirty>>hr)&1))
4672 {
4673 if((i_dirty>>hr)&1)
4674 {
4675 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4676 {
4677 //printf("%x: dirty no match\n",addr);
4678 return 0;
4679 }
4680 }
4681 }
57871462 4682 }
4683 }
4684 }
57871462 4685 // Delay slots are not valid branch targets
fe807a8a 4686 //if(t>0&&(dops[t-1].is_jump) return 0;
57871462 4687 // Delay slots require additional processing, so do not match
cf95b4f0 4688 if(dops[t].is_ds) return 0;
57871462 4689 }
4690 else
4691 {
4692 int hr;
4693 for(hr=0;hr<HOST_REGS;hr++)
4694 {
4695 if(hr!=EXCLUDE_REG)
4696 {
4697 if(i_regmap[hr]>=0)
4698 {
4699 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4700 {
4701 if((i_dirty>>hr)&1)
4702 {
4703 return 0;
4704 }
4705 }
4706 }
4707 }
4708 }
4709 }
4710 return 1;
4711}
4712
dd114d7d 4713#ifdef DRC_DBG
2330734f 4714static void drc_dbg_emit_do_cmp(int i, int ccadj_)
dd114d7d 4715{
4716 extern void do_insn_cmp();
3968e69e 4717 //extern int cycle;
81dbbf4c 4718 u_int hr, reglist = get_host_reglist(regs[i].regmap);
dd114d7d 4719
40fca85b 4720 assem_debug("//do_insn_cmp %08x\n", start+i*4);
dd114d7d 4721 save_regs(reglist);
40fca85b 4722 // write out changed consts to match the interpreter
cf95b4f0 4723 if (i > 0 && !dops[i].bt) {
40fca85b 4724 for (hr = 0; hr < HOST_REGS; hr++) {
2330734f 4725 int reg = regs[i].regmap_entry[hr]; // regs[i-1].regmap[hr];
40fca85b 4726 if (hr == EXCLUDE_REG || reg < 0)
4727 continue;
4728 if (!((regs[i-1].isconst >> hr) & 1))
4729 continue;
4730 if (i > 1 && reg == regs[i-2].regmap[hr] && constmap[i-1][hr] == constmap[i-2][hr])
4731 continue;
4732 emit_movimm(constmap[i-1][hr],0);
4733 emit_storereg(reg, 0);
4734 }
4735 }
dd114d7d 4736 emit_movimm(start+i*4,0);
643aeae3 4737 emit_writeword(0,&pcaddr);
2330734f 4738 int cc = get_reg(regs[i].regmap_entry, CCREG);
4739 if (cc < 0)
4740 emit_loadreg(CCREG, cc = 0);
4741 emit_addimm(cc, ccadj_, 0);
4742 emit_writeword(0, &psxRegs.cycle);
2a014d73 4743 emit_far_call(do_insn_cmp);
643aeae3 4744 //emit_readword(&cycle,0);
dd114d7d 4745 //emit_addimm(0,2,0);
643aeae3 4746 //emit_writeword(0,&cycle);
3968e69e 4747 (void)get_reg2;
dd114d7d 4748 restore_regs(reglist);
40fca85b 4749 assem_debug("\\\\do_insn_cmp\n");
dd114d7d 4750}
4751#else
2330734f 4752#define drc_dbg_emit_do_cmp(x,y)
dd114d7d 4753#endif
4754
57871462 4755// Used when a branch jumps into the delay slot of another branch
7c3a5182 4756static void ds_assemble_entry(int i)
57871462 4757{
2330734f 4758 int t = (ba[i] - start) >> 2;
4759 int ccadj_ = -CLOCK_ADJUST(1);
df4dc2b1 4760 if (!instr_addr[t])
4761 instr_addr[t] = out;
57871462 4762 assem_debug("Assemble delay slot at %x\n",ba[i]);
4763 assem_debug("<->\n");
2330734f 4764 drc_dbg_emit_do_cmp(t, ccadj_);
57871462 4765 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
ad49de89 4766 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty);
cf95b4f0 4767 load_regs(regs[t].regmap_entry,regs[t].regmap,dops[t].rs1,dops[t].rs2);
57871462 4768 address_generation(t,&regs[t],regs[t].regmap_entry);
37387d8b 4769 if (ram_offset && (dops[t].is_load || dops[t].is_store))
4770 load_regs(regs[t].regmap_entry,regs[t].regmap,ROREG,ROREG);
4771 if (dops[t].is_store)
ad49de89 4772 load_regs(regs[t].regmap_entry,regs[t].regmap,INVCP,INVCP);
57871462 4773 is_delayslot=0;
2330734f 4774 switch (dops[t].itype) {
57871462 4775 case SYSCALL:
7139f3c8 4776 case HLECALL:
1e973cb0 4777 case INTCALL:
57871462 4778 case SPAN:
4779 case UJUMP:
4780 case RJUMP:
4781 case CJUMP:
4782 case SJUMP:
c43b5311 4783 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
2330734f 4784 break;
4785 default:
4786 assemble(t, &regs[t], ccadj_);
57871462 4787 }
ad49de89 4788 store_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4);
4789 load_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4);
4790 if(internal_branch(ba[i]+4))
57871462 4791 assem_debug("branch: internal\n");
4792 else
4793 assem_debug("branch: external\n");
ad49de89 4794 assert(internal_branch(ba[i]+4));
4795 add_to_linker(out,ba[i]+4,internal_branch(ba[i]+4));
57871462 4796 emit_jmp(0);
4797}
4798
7c3a5182 4799static void emit_extjump(void *addr, u_int target)
4800{
4801 emit_extjump2(addr, target, dyna_linker);
4802}
4803
4804static void emit_extjump_ds(void *addr, u_int target)
4805{
4806 emit_extjump2(addr, target, dyna_linker_ds);
4807}
4808
d1e4ebd9 4809// Load 2 immediates optimizing for small code size
4810static void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
4811{
4812 emit_movimm(imm1,rt1);
4813 emit_movimm_from(imm1,rt1,imm2,rt2);
4814}
4815
2330734f 4816static void do_cc(int i, const signed char i_regmap[], int *adj,
4817 int addr, int taken, int invert)
57871462 4818{
2330734f 4819 int count, count_plus2;
b14b6a8f 4820 void *jaddr;
4821 void *idle=NULL;
b6e87b2b 4822 int t=0;
cf95b4f0 4823 if(dops[i].itype==RJUMP)
57871462 4824 {
4825 *adj=0;
4826 }
4827 //if(ba[i]>=start && ba[i]<(start+slen*4))
ad49de89 4828 if(internal_branch(ba[i]))
57871462 4829 {
b6e87b2b 4830 t=(ba[i]-start)>>2;
2330734f 4831 if(dops[t].is_ds) *adj=-CLOCK_ADJUST(1); // Branch into delay slot adds an extra cycle
57871462 4832 else *adj=ccadj[t];
4833 }
4834 else
4835 {
4836 *adj=0;
4837 }
2330734f 4838 count = ccadj[i];
4839 count_plus2 = count + CLOCK_ADJUST(2);
57871462 4840 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4841 // Idle loop
4842 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
b14b6a8f 4843 idle=out;
57871462 4844 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4845 emit_andimm(HOST_CCREG,3,HOST_CCREG);
b14b6a8f 4846 jaddr=out;
57871462 4847 emit_jmp(0);
4848 }
4849 else if(*adj==0||invert) {
2330734f 4850 int cycles = count_plus2;
b6e87b2b 4851 // faster loop HACK
bb4f300c 4852#if 0
b6e87b2b 4853 if (t&&*adj) {
4854 int rel=t-i;
4855 if(-NO_CYCLE_PENALTY_THR<rel&&rel<0)
2330734f 4856 cycles=*adj+count+2-*adj;
b6e87b2b 4857 }
bb4f300c 4858#endif
2330734f 4859 emit_addimm_and_set_flags(cycles, HOST_CCREG);
4860 jaddr = out;
57871462 4861 emit_jns(0);
4862 }
4863 else
4864 {
2330734f 4865 emit_cmpimm(HOST_CCREG, -count_plus2);
4866 jaddr = out;
57871462 4867 emit_jns(0);
4868 }
2330734f 4869 add_stub(CC_STUB,jaddr,idle?idle:out,(*adj==0||invert||idle)?0:count_plus2,i,addr,taken,0);
57871462 4870}
4871
b14b6a8f 4872static void do_ccstub(int n)
57871462 4873{
4874 literal_pool(256);
d1e4ebd9 4875 assem_debug("do_ccstub %x\n",start+(u_int)stubs[n].b*4);
b14b6a8f 4876 set_jump_target(stubs[n].addr, out);
4877 int i=stubs[n].b;
4878 if(stubs[n].d==NULLDS) {
57871462 4879 // Delay slot instruction is nullified ("likely" branch)
ad49de89 4880 wb_dirtys(regs[i].regmap,regs[i].dirty);
57871462 4881 }
b14b6a8f 4882 else if(stubs[n].d!=TAKEN) {
ad49de89 4883 wb_dirtys(branch_regs[i].regmap,branch_regs[i].dirty);
57871462 4884 }
4885 else {
ad49de89 4886 if(internal_branch(ba[i]))
4887 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 4888 }
b14b6a8f 4889 if(stubs[n].c!=-1)
57871462 4890 {
4891 // Save PC as return address
b14b6a8f 4892 emit_movimm(stubs[n].c,EAX);
643aeae3 4893 emit_writeword(EAX,&pcaddr);
57871462 4894 }
4895 else
4896 {
4897 // Return address depends on which way the branch goes
cf95b4f0 4898 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
57871462 4899 {
cf95b4f0 4900 int s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
4901 int s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
4902 if(dops[i].rs1==0)
57871462 4903 {
ad49de89 4904 s1l=s2l;
4905 s2l=-1;
57871462 4906 }
cf95b4f0 4907 else if(dops[i].rs2==0)
57871462 4908 {
ad49de89 4909 s2l=-1;
57871462 4910 }
4911 assert(s1l>=0);
4912 #ifdef DESTRUCTIVE_WRITEBACK
cf95b4f0 4913 if(dops[i].rs1) {
ad49de89 4914 if((branch_regs[i].dirty>>s1l)&&1)
cf95b4f0 4915 emit_loadreg(dops[i].rs1,s1l);
9f51b4b9 4916 }
57871462 4917 else {
ad49de89 4918 if((branch_regs[i].dirty>>s1l)&1)
cf95b4f0 4919 emit_loadreg(dops[i].rs2,s1l);
57871462 4920 }
4921 if(s2l>=0)
ad49de89 4922 if((branch_regs[i].dirty>>s2l)&1)
cf95b4f0 4923 emit_loadreg(dops[i].rs2,s2l);
57871462 4924 #endif
4925 int hr=0;
5194fb95 4926 int addr=-1,alt=-1,ntaddr=-1;
57871462 4927 while(hr<HOST_REGS)
4928 {
4929 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
cf95b4f0 4930 (branch_regs[i].regmap[hr]&63)!=dops[i].rs1 &&
4931 (branch_regs[i].regmap[hr]&63)!=dops[i].rs2 )
57871462 4932 {
4933 addr=hr++;break;
4934 }
4935 hr++;
4936 }
4937 while(hr<HOST_REGS)
4938 {
4939 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
cf95b4f0 4940 (branch_regs[i].regmap[hr]&63)!=dops[i].rs1 &&
4941 (branch_regs[i].regmap[hr]&63)!=dops[i].rs2 )
57871462 4942 {
4943 alt=hr++;break;
4944 }
4945 hr++;
4946 }
cf95b4f0 4947 if((dops[i].opcode&0x2E)==6) // BLEZ/BGTZ needs another register
57871462 4948 {
4949 while(hr<HOST_REGS)
4950 {
4951 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
cf95b4f0 4952 (branch_regs[i].regmap[hr]&63)!=dops[i].rs1 &&
4953 (branch_regs[i].regmap[hr]&63)!=dops[i].rs2 )
57871462 4954 {
4955 ntaddr=hr;break;
4956 }
4957 hr++;
4958 }
4959 assert(hr<HOST_REGS);
4960 }
cf95b4f0 4961 if((dops[i].opcode&0x2f)==4) // BEQ
57871462 4962 {
4963 #ifdef HAVE_CMOV_IMM
ad49de89 4964 if(s2l>=0) emit_cmp(s1l,s2l);
4965 else emit_test(s1l,s1l);
4966 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
4967 #else
4968 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4969 if(s2l>=0) emit_cmp(s1l,s2l);
4970 else emit_test(s1l,s1l);
4971 emit_cmovne_reg(alt,addr);
57871462 4972 #endif
57871462 4973 }
cf95b4f0 4974 if((dops[i].opcode&0x2f)==5) // BNE
57871462 4975 {
4976 #ifdef HAVE_CMOV_IMM
ad49de89 4977 if(s2l>=0) emit_cmp(s1l,s2l);
4978 else emit_test(s1l,s1l);
4979 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
4980 #else
4981 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
4982 if(s2l>=0) emit_cmp(s1l,s2l);
4983 else emit_test(s1l,s1l);
4984 emit_cmovne_reg(alt,addr);
57871462 4985 #endif
57871462 4986 }
cf95b4f0 4987 if((dops[i].opcode&0x2f)==6) // BLEZ
57871462 4988 {
4989 //emit_movimm(ba[i],alt);
4990 //emit_movimm(start+i*4+8,addr);
4991 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4992 emit_cmpimm(s1l,1);
57871462 4993 emit_cmovl_reg(alt,addr);
57871462 4994 }
cf95b4f0 4995 if((dops[i].opcode&0x2f)==7) // BGTZ
57871462 4996 {
4997 //emit_movimm(ba[i],addr);
4998 //emit_movimm(start+i*4+8,ntaddr);
4999 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5000 emit_cmpimm(s1l,1);
57871462 5001 emit_cmovl_reg(ntaddr,addr);
57871462 5002 }
cf95b4f0 5003 if((dops[i].opcode==1)&&(dops[i].opcode2&0x2D)==0) // BLTZ
57871462 5004 {
5005 //emit_movimm(ba[i],alt);
5006 //emit_movimm(start+i*4+8,addr);
5007 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
ad49de89 5008 emit_test(s1l,s1l);
57871462 5009 emit_cmovs_reg(alt,addr);
5010 }
cf95b4f0 5011 if((dops[i].opcode==1)&&(dops[i].opcode2&0x2D)==1) // BGEZ
57871462 5012 {
5013 //emit_movimm(ba[i],addr);
5014 //emit_movimm(start+i*4+8,alt);
5015 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
ad49de89 5016 emit_test(s1l,s1l);
57871462 5017 emit_cmovs_reg(alt,addr);
5018 }
cf95b4f0 5019 if(dops[i].opcode==0x11 && dops[i].opcode2==0x08 ) {
57871462 5020 if(source[i]&0x10000) // BC1T
5021 {
5022 //emit_movimm(ba[i],alt);
5023 //emit_movimm(start+i*4+8,addr);
5024 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5025 emit_testimm(s1l,0x800000);
5026 emit_cmovne_reg(alt,addr);
5027 }
5028 else // BC1F
5029 {
5030 //emit_movimm(ba[i],addr);
5031 //emit_movimm(start+i*4+8,alt);
5032 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5033 emit_testimm(s1l,0x800000);
5034 emit_cmovne_reg(alt,addr);
5035 }
5036 }
643aeae3 5037 emit_writeword(addr,&pcaddr);
57871462 5038 }
5039 else
cf95b4f0 5040 if(dops[i].itype==RJUMP)
57871462 5041 {
cf95b4f0 5042 int r=get_reg(branch_regs[i].regmap,dops[i].rs1);
4919de1e 5043 if (ds_writes_rjump_rs(i)) {
57871462 5044 r=get_reg(branch_regs[i].regmap,RTEMP);
5045 }
643aeae3 5046 emit_writeword(r,&pcaddr);
57871462 5047 }
7c3a5182 5048 else {SysPrintf("Unknown branch type in do_ccstub\n");abort();}
57871462 5049 }
5050 // Update cycle count
5051 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
2330734f 5052 if(stubs[n].a) emit_addimm(HOST_CCREG,(int)stubs[n].a,HOST_CCREG);
2a014d73 5053 emit_far_call(cc_interrupt);
2330734f 5054 if(stubs[n].a) emit_addimm(HOST_CCREG,-(int)stubs[n].a,HOST_CCREG);
b14b6a8f 5055 if(stubs[n].d==TAKEN) {
ad49de89 5056 if(internal_branch(ba[i]))
57871462 5057 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
cf95b4f0 5058 else if(dops[i].itype==RJUMP) {
57871462 5059 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
643aeae3 5060 emit_readword(&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
57871462 5061 else
cf95b4f0 5062 emit_loadreg(dops[i].rs1,get_reg(branch_regs[i].regmap,dops[i].rs1));
57871462 5063 }
b14b6a8f 5064 }else if(stubs[n].d==NOTTAKEN) {
57871462 5065 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5066 else load_all_regs(branch_regs[i].regmap);
b14b6a8f 5067 }else if(stubs[n].d==NULLDS) {
57871462 5068 // Delay slot instruction is nullified ("likely" branch)
5069 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5070 else load_all_regs(regs[i].regmap);
5071 }else{
5072 load_all_regs(branch_regs[i].regmap);
5073 }
d1e4ebd9 5074 if (stubs[n].retaddr)
5075 emit_jmp(stubs[n].retaddr);
5076 else
5077 do_jump_vaddr(stubs[n].e);
57871462 5078}
5079
643aeae3 5080static void add_to_linker(void *addr, u_int target, int ext)
57871462 5081{
643aeae3 5082 assert(linkcount < ARRAY_SIZE(link_addr));
5083 link_addr[linkcount].addr = addr;
5084 link_addr[linkcount].target = target;
5085 link_addr[linkcount].ext = ext;
57871462 5086 linkcount++;
5087}
5088
eba830cd 5089static void ujump_assemble_write_ra(int i)
5090{
5091 int rt;
5092 unsigned int return_address;
5093 rt=get_reg(branch_regs[i].regmap,31);
5094 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5095 //assert(rt>=0);
5096 return_address=start+i*4+8;
5097 if(rt>=0) {
5098 #ifdef USE_MINI_HT
cf95b4f0 5099 if(internal_branch(return_address)&&dops[i+1].rt1!=31) {
eba830cd 5100 int temp=-1; // note: must be ds-safe
5101 #ifdef HOST_TEMPREG
5102 temp=HOST_TEMPREG;
5103 #endif
5104 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5105 else emit_movimm(return_address,rt);
5106 }
5107 else
5108 #endif
5109 {
5110 #ifdef REG_PREFETCH
9f51b4b9 5111 if(temp>=0)
eba830cd 5112 {
643aeae3 5113 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
eba830cd 5114 }
5115 #endif
5116 emit_movimm(return_address,rt); // PC into link register
5117 #ifdef IMM_PREFETCH
df4dc2b1 5118 emit_prefetch(hash_table_get(return_address));
eba830cd 5119 #endif
5120 }
5121 }
5122}
5123
2330734f 5124static void ujump_assemble(int i, const struct regstat *i_regs)
57871462 5125{
eba830cd 5126 int ra_done=0;
57871462 5127 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5128 address_generation(i+1,i_regs,regs[i].regmap_entry);
5129 #ifdef REG_PREFETCH
5130 int temp=get_reg(branch_regs[i].regmap,PTEMP);
cf95b4f0 5131 if(dops[i].rt1==31&&temp>=0)
57871462 5132 {
581335b0 5133 signed char *i_regmap=i_regs->regmap;
57871462 5134 int return_address=start+i*4+8;
9f51b4b9 5135 if(get_reg(branch_regs[i].regmap,31)>0)
643aeae3 5136 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
57871462 5137 }
5138 #endif
cf95b4f0 5139 if(dops[i].rt1==31&&(dops[i].rt1==dops[i+1].rs1||dops[i].rt1==dops[i+1].rs2)) {
eba830cd 5140 ujump_assemble_write_ra(i); // writeback ra for DS
5141 ra_done=1;
57871462 5142 }
4ef8f67d 5143 ds_assemble(i+1,i_regs);
5144 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5145 bc_unneeded|=1|(1LL<<dops[i].rt1);
ad49de89 5146 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5147 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
cf95b4f0 5148 if(!ra_done&&dops[i].rt1==31)
eba830cd 5149 ujump_assemble_write_ra(i);
57871462 5150 int cc,adj;
5151 cc=get_reg(branch_regs[i].regmap,CCREG);
5152 assert(cc==HOST_CCREG);
ad49de89 5153 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5154 #ifdef REG_PREFETCH
cf95b4f0 5155 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
57871462 5156 #endif
5157 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
2330734f 5158 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
ad49de89 5159 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5160 if(internal_branch(ba[i]))
57871462 5161 assem_debug("branch: internal\n");
5162 else
5163 assem_debug("branch: external\n");
cf95b4f0 5164 if (internal_branch(ba[i]) && dops[(ba[i]-start)>>2].is_ds) {
57871462 5165 ds_assemble_entry(i);
5166 }
5167 else {
ad49de89 5168 add_to_linker(out,ba[i],internal_branch(ba[i]));
57871462 5169 emit_jmp(0);
5170 }
5171}
5172
eba830cd 5173static void rjump_assemble_write_ra(int i)
5174{
5175 int rt,return_address;
cf95b4f0 5176 assert(dops[i+1].rt1!=dops[i].rt1);
5177 assert(dops[i+1].rt2!=dops[i].rt1);
5178 rt=get_reg(branch_regs[i].regmap,dops[i].rt1);
eba830cd 5179 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5180 assert(rt>=0);
5181 return_address=start+i*4+8;
5182 #ifdef REG_PREFETCH
9f51b4b9 5183 if(temp>=0)
eba830cd 5184 {
643aeae3 5185 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
eba830cd 5186 }
5187 #endif
5188 emit_movimm(return_address,rt); // PC into link register
5189 #ifdef IMM_PREFETCH
df4dc2b1 5190 emit_prefetch(hash_table_get(return_address));
eba830cd 5191 #endif
5192}
5193
2330734f 5194static void rjump_assemble(int i, const struct regstat *i_regs)
57871462 5195{
57871462 5196 int temp;
581335b0 5197 int rs,cc;
eba830cd 5198 int ra_done=0;
cf95b4f0 5199 rs=get_reg(branch_regs[i].regmap,dops[i].rs1);
57871462 5200 assert(rs>=0);
4919de1e 5201 if (ds_writes_rjump_rs(i)) {
57871462 5202 // Delay slot abuse, make a copy of the branch address register
5203 temp=get_reg(branch_regs[i].regmap,RTEMP);
5204 assert(temp>=0);
5205 assert(regs[i].regmap[temp]==RTEMP);
5206 emit_mov(rs,temp);
5207 rs=temp;
5208 }
5209 address_generation(i+1,i_regs,regs[i].regmap_entry);
5210 #ifdef REG_PREFETCH
cf95b4f0 5211 if(dops[i].rt1==31)
57871462 5212 {
5213 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
581335b0 5214 signed char *i_regmap=i_regs->regmap;
57871462 5215 int return_address=start+i*4+8;
643aeae3 5216 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
57871462 5217 }
5218 }
5219 #endif
5220 #ifdef USE_MINI_HT
cf95b4f0 5221 if(dops[i].rs1==31) {
57871462 5222 int rh=get_reg(regs[i].regmap,RHASH);
5223 if(rh>=0) do_preload_rhash(rh);
5224 }
5225 #endif
cf95b4f0 5226 if(dops[i].rt1!=0&&(dops[i].rt1==dops[i+1].rs1||dops[i].rt1==dops[i+1].rs2)) {
eba830cd 5227 rjump_assemble_write_ra(i);
5228 ra_done=1;
57871462 5229 }
d5910d5d 5230 ds_assemble(i+1,i_regs);
5231 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5232 bc_unneeded|=1|(1LL<<dops[i].rt1);
5233 bc_unneeded&=~(1LL<<dops[i].rs1);
ad49de89 5234 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
cf95b4f0 5235 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,CCREG);
5236 if(!ra_done&&dops[i].rt1!=0)
eba830cd 5237 rjump_assemble_write_ra(i);
57871462 5238 cc=get_reg(branch_regs[i].regmap,CCREG);
5239 assert(cc==HOST_CCREG);
581335b0 5240 (void)cc;
57871462 5241 #ifdef USE_MINI_HT
5242 int rh=get_reg(branch_regs[i].regmap,RHASH);
5243 int ht=get_reg(branch_regs[i].regmap,RHTBL);
cf95b4f0 5244 if(dops[i].rs1==31) {
57871462 5245 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5246 do_preload_rhtbl(ht);
5247 do_rhash(rs,rh);
5248 }
5249 #endif
ad49de89 5250 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
57871462 5251 #ifdef DESTRUCTIVE_WRITEBACK
ad49de89 5252 if((branch_regs[i].dirty>>rs)&1) {
cf95b4f0 5253 if(dops[i].rs1!=dops[i+1].rt1&&dops[i].rs1!=dops[i+1].rt2) {
5254 emit_loadreg(dops[i].rs1,rs);
57871462 5255 }
5256 }
5257 #endif
5258 #ifdef REG_PREFETCH
cf95b4f0 5259 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
57871462 5260 #endif
5261 #ifdef USE_MINI_HT
cf95b4f0 5262 if(dops[i].rs1==31) {
57871462 5263 do_miniht_load(ht,rh);
5264 }
5265 #endif
5266 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5267 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5268 //assert(adj==0);
2330734f 5269 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
d1e4ebd9 5270 add_stub(CC_STUB,out,NULL,0,i,-1,TAKEN,rs);
cf95b4f0 5271 if(dops[i+1].itype==COP0&&(source[i+1]&0x3f)==0x10)
911f2d55 5272 // special case for RFE
5273 emit_jmp(0);
5274 else
71e490c5 5275 emit_jns(0);
ad49de89 5276 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
57871462 5277 #ifdef USE_MINI_HT
cf95b4f0 5278 if(dops[i].rs1==31) {
57871462 5279 do_miniht_jump(rs,rh,ht);
5280 }
5281 else
5282 #endif
5283 {
d1e4ebd9 5284 do_jump_vaddr(rs);
57871462 5285 }
57871462 5286 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
cf95b4f0 5287 if(dops[i].rt1!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
57871462 5288 #endif
5289}
5290
2330734f 5291static void cjump_assemble(int i, const struct regstat *i_regs)
57871462 5292{
2330734f 5293 const signed char *i_regmap = i_regs->regmap;
57871462 5294 int cc;
5295 int match;
ad49de89 5296 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5297 assem_debug("match=%d\n",match);
ad49de89 5298 int s1l,s2l;
57871462 5299 int unconditional=0,nop=0;
57871462 5300 int invert=0;
ad49de89 5301 int internal=internal_branch(ba[i]);
57871462 5302 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 5303 if(!match) invert=1;
5304 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5305 if(i>(ba[i]-start)>>2) invert=1;
5306 #endif
3968e69e 5307 #ifdef __aarch64__
5308 invert=1; // because of near cond. branches
5309 #endif
9f51b4b9 5310
cf95b4f0 5311 if(dops[i].ooo) {
5312 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5313 s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
57871462 5314 }
5315 else {
cf95b4f0 5316 s1l=get_reg(i_regmap,dops[i].rs1);
5317 s2l=get_reg(i_regmap,dops[i].rs2);
57871462 5318 }
cf95b4f0 5319 if(dops[i].rs1==0&&dops[i].rs2==0)
57871462 5320 {
cf95b4f0 5321 if(dops[i].opcode&1) nop=1;
57871462 5322 else unconditional=1;
cf95b4f0 5323 //assert(dops[i].opcode!=5);
5324 //assert(dops[i].opcode!=7);
5325 //assert(dops[i].opcode!=0x15);
5326 //assert(dops[i].opcode!=0x17);
57871462 5327 }
cf95b4f0 5328 else if(dops[i].rs1==0)
57871462 5329 {
ad49de89 5330 s1l=s2l;
5331 s2l=-1;
57871462 5332 }
cf95b4f0 5333 else if(dops[i].rs2==0)
57871462 5334 {
ad49de89 5335 s2l=-1;
57871462 5336 }
5337
cf95b4f0 5338 if(dops[i].ooo) {
57871462 5339 // Out of order execution (delay slot first)
5340 //printf("OOOE\n");
5341 address_generation(i+1,i_regs,regs[i].regmap_entry);
5342 ds_assemble(i+1,i_regs);
5343 int adj;
5344 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5345 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 5346 bc_unneeded|=1;
ad49de89 5347 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
cf95b4f0 5348 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs2);
ad49de89 5349 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
57871462 5350 cc=get_reg(branch_regs[i].regmap,CCREG);
5351 assert(cc==HOST_CCREG);
9f51b4b9 5352 if(unconditional)
ad49de89 5353 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5354 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5355 //assem_debug("cycle count (adj)\n");
5356 if(unconditional) {
5357 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5358 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
2330734f 5359 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
ad49de89 5360 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5361 if(internal)
5362 assem_debug("branch: internal\n");
5363 else
5364 assem_debug("branch: external\n");
cf95b4f0 5365 if (internal && dops[(ba[i]-start)>>2].is_ds) {
57871462 5366 ds_assemble_entry(i);
5367 }
5368 else {
643aeae3 5369 add_to_linker(out,ba[i],internal);
57871462 5370 emit_jmp(0);
5371 }
5372 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5373 if(((u_int)out)&7) emit_addnop(0);
5374 #endif
5375 }
5376 }
5377 else if(nop) {
2330734f 5378 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
b14b6a8f 5379 void *jaddr=out;
57871462 5380 emit_jns(0);
b14b6a8f 5381 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5382 }
5383 else {
df4dc2b1 5384 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
57871462 5385 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
2330734f 5386 if(adj&&!invert) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
9f51b4b9 5387
57871462 5388 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5389 assert(s1l>=0);
cf95b4f0 5390 if(dops[i].opcode==4) // BEQ
57871462 5391 {
5392 if(s2l>=0) emit_cmp(s1l,s2l);
5393 else emit_test(s1l,s1l);
5394 if(invert){
df4dc2b1 5395 nottaken=out;
7c3a5182 5396 emit_jne(DJT_1);
57871462 5397 }else{
643aeae3 5398 add_to_linker(out,ba[i],internal);
57871462 5399 emit_jeq(0);
5400 }
5401 }
cf95b4f0 5402 if(dops[i].opcode==5) // BNE
57871462 5403 {
5404 if(s2l>=0) emit_cmp(s1l,s2l);
5405 else emit_test(s1l,s1l);
5406 if(invert){
df4dc2b1 5407 nottaken=out;
7c3a5182 5408 emit_jeq(DJT_1);
57871462 5409 }else{
643aeae3 5410 add_to_linker(out,ba[i],internal);
57871462 5411 emit_jne(0);
5412 }
5413 }
cf95b4f0 5414 if(dops[i].opcode==6) // BLEZ
57871462 5415 {
5416 emit_cmpimm(s1l,1);
5417 if(invert){
df4dc2b1 5418 nottaken=out;
7c3a5182 5419 emit_jge(DJT_1);
57871462 5420 }else{
643aeae3 5421 add_to_linker(out,ba[i],internal);
57871462 5422 emit_jl(0);
5423 }
5424 }
cf95b4f0 5425 if(dops[i].opcode==7) // BGTZ
57871462 5426 {
5427 emit_cmpimm(s1l,1);
5428 if(invert){
df4dc2b1 5429 nottaken=out;
7c3a5182 5430 emit_jl(DJT_1);
57871462 5431 }else{
643aeae3 5432 add_to_linker(out,ba[i],internal);
57871462 5433 emit_jge(0);
5434 }
5435 }
5436 if(invert) {
df4dc2b1 5437 if(taken) set_jump_target(taken, out);
57871462 5438 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
cf95b4f0 5439 if (match && (!internal || !dops[(ba[i]-start)>>2].is_ds)) {
57871462 5440 if(adj) {
2330734f 5441 emit_addimm(cc,-adj,cc);
643aeae3 5442 add_to_linker(out,ba[i],internal);
57871462 5443 }else{
5444 emit_addnop(13);
643aeae3 5445 add_to_linker(out,ba[i],internal*2);
57871462 5446 }
5447 emit_jmp(0);
5448 }else
5449 #endif
5450 {
2330734f 5451 if(adj) emit_addimm(cc,-adj,cc);
ad49de89 5452 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5453 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5454 if(internal)
5455 assem_debug("branch: internal\n");
5456 else
5457 assem_debug("branch: external\n");
cf95b4f0 5458 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
57871462 5459 ds_assemble_entry(i);
5460 }
5461 else {
643aeae3 5462 add_to_linker(out,ba[i],internal);
57871462 5463 emit_jmp(0);
5464 }
5465 }
df4dc2b1 5466 set_jump_target(nottaken, out);
57871462 5467 }
5468
df4dc2b1 5469 if(nottaken1) set_jump_target(nottaken1, out);
57871462 5470 if(adj) {
2330734f 5471 if(!invert) emit_addimm(cc,adj,cc);
57871462 5472 }
5473 } // (!unconditional)
5474 } // if(ooo)
5475 else
5476 {
5477 // In-order execution (branch first)
df4dc2b1 5478 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
57871462 5479 if(!unconditional&&!nop) {
57871462 5480 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5481 assert(s1l>=0);
cf95b4f0 5482 if((dops[i].opcode&0x2f)==4) // BEQ
57871462 5483 {
5484 if(s2l>=0) emit_cmp(s1l,s2l);
5485 else emit_test(s1l,s1l);
df4dc2b1 5486 nottaken=out;
7c3a5182 5487 emit_jne(DJT_2);
57871462 5488 }
cf95b4f0 5489 if((dops[i].opcode&0x2f)==5) // BNE
57871462 5490 {
5491 if(s2l>=0) emit_cmp(s1l,s2l);
5492 else emit_test(s1l,s1l);
df4dc2b1 5493 nottaken=out;
7c3a5182 5494 emit_jeq(DJT_2);
57871462 5495 }
cf95b4f0 5496 if((dops[i].opcode&0x2f)==6) // BLEZ
57871462 5497 {
5498 emit_cmpimm(s1l,1);
df4dc2b1 5499 nottaken=out;
7c3a5182 5500 emit_jge(DJT_2);
57871462 5501 }
cf95b4f0 5502 if((dops[i].opcode&0x2f)==7) // BGTZ
57871462 5503 {
5504 emit_cmpimm(s1l,1);
df4dc2b1 5505 nottaken=out;
7c3a5182 5506 emit_jl(DJT_2);
57871462 5507 }
5508 } // if(!unconditional)
5509 int adj;
5510 uint64_t ds_unneeded=branch_regs[i].u;
cf95b4f0 5511 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
57871462 5512 ds_unneeded|=1;
57871462 5513 // branch taken
5514 if(!nop) {
df4dc2b1 5515 if(taken) set_jump_target(taken, out);
57871462 5516 assem_debug("1:\n");
ad49de89 5517 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
57871462 5518 // load regs
cf95b4f0 5519 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
57871462 5520 address_generation(i+1,&branch_regs[i],0);
37387d8b 5521 if (ram_offset)
5522 load_regs(regs[i].regmap,branch_regs[i].regmap,ROREG,ROREG);
ad49de89 5523 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
57871462 5524 ds_assemble(i+1,&branch_regs[i]);
5525 cc=get_reg(branch_regs[i].regmap,CCREG);
5526 if(cc==-1) {
5527 emit_loadreg(CCREG,cc=HOST_CCREG);
5528 // CHECK: Is the following instruction (fall thru) allocated ok?
5529 }
5530 assert(cc==HOST_CCREG);
ad49de89 5531 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5532 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5533 assem_debug("cycle count (adj)\n");
2330734f 5534 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
ad49de89 5535 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5536 if(internal)
5537 assem_debug("branch: internal\n");
5538 else
5539 assem_debug("branch: external\n");
cf95b4f0 5540 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
57871462 5541 ds_assemble_entry(i);
5542 }
5543 else {
643aeae3 5544 add_to_linker(out,ba[i],internal);
57871462 5545 emit_jmp(0);
5546 }
5547 }
5548 // branch not taken
57871462 5549 if(!unconditional) {
df4dc2b1 5550 if(nottaken1) set_jump_target(nottaken1, out);
5551 set_jump_target(nottaken, out);
57871462 5552 assem_debug("2:\n");
fe807a8a 5553 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
37387d8b 5554 // load regs
fe807a8a 5555 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5556 address_generation(i+1,&branch_regs[i],0);
37387d8b 5557 if (ram_offset)
5558 load_regs(regs[i].regmap,branch_regs[i].regmap,ROREG,ROREG);
5559 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
fe807a8a 5560 ds_assemble(i+1,&branch_regs[i]);
57871462 5561 cc=get_reg(branch_regs[i].regmap,CCREG);
fe807a8a 5562 if (cc == -1) {
57871462 5563 // Cycle count isn't in a register, temporarily load it then write it out
5564 emit_loadreg(CCREG,HOST_CCREG);
2330734f 5565 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
b14b6a8f 5566 void *jaddr=out;
57871462 5567 emit_jns(0);
b14b6a8f 5568 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5569 emit_storereg(CCREG,HOST_CCREG);
5570 }
5571 else{
5572 cc=get_reg(i_regmap,CCREG);
5573 assert(cc==HOST_CCREG);
2330734f 5574 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
b14b6a8f 5575 void *jaddr=out;
57871462 5576 emit_jns(0);
fe807a8a 5577 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5578 }
5579 }
5580 }
5581}
5582
2330734f 5583static void sjump_assemble(int i, const struct regstat *i_regs)
57871462 5584{
2330734f 5585 const signed char *i_regmap = i_regs->regmap;
57871462 5586 int cc;
5587 int match;
ad49de89 5588 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5589 assem_debug("smatch=%d\n",match);
ad49de89 5590 int s1l;
57871462 5591 int unconditional=0,nevertaken=0;
57871462 5592 int invert=0;
ad49de89 5593 int internal=internal_branch(ba[i]);
57871462 5594 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 5595 if(!match) invert=1;
5596 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5597 if(i>(ba[i]-start)>>2) invert=1;
5598 #endif
3968e69e 5599 #ifdef __aarch64__
5600 invert=1; // because of near cond. branches
5601 #endif
57871462 5602
cf95b4f0 5603 //if(dops[i].opcode2>=0x10) return; // FIXME (BxxZAL)
5604 //assert(dops[i].opcode2<0x10||dops[i].rs1==0); // FIXME (BxxZAL)
57871462 5605
cf95b4f0 5606 if(dops[i].ooo) {
5607 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
57871462 5608 }
5609 else {
cf95b4f0 5610 s1l=get_reg(i_regmap,dops[i].rs1);
57871462 5611 }
cf95b4f0 5612 if(dops[i].rs1==0)
57871462 5613 {
cf95b4f0 5614 if(dops[i].opcode2&1) unconditional=1;
57871462 5615 else nevertaken=1;
5616 // These are never taken (r0 is never less than zero)
cf95b4f0 5617 //assert(dops[i].opcode2!=0);
5618 //assert(dops[i].opcode2!=2);
5619 //assert(dops[i].opcode2!=0x10);
5620 //assert(dops[i].opcode2!=0x12);
57871462 5621 }
57871462 5622
cf95b4f0 5623 if(dops[i].ooo) {
57871462 5624 // Out of order execution (delay slot first)
5625 //printf("OOOE\n");
5626 address_generation(i+1,i_regs,regs[i].regmap_entry);
5627 ds_assemble(i+1,i_regs);
5628 int adj;
5629 uint64_t bc_unneeded=branch_regs[i].u;
cf95b4f0 5630 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 5631 bc_unneeded|=1;
ad49de89 5632 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
cf95b4f0 5633 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs1);
ad49de89 5634 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
cf95b4f0 5635 if(dops[i].rt1==31) {
57871462 5636 int rt,return_address;
57871462 5637 rt=get_reg(branch_regs[i].regmap,31);
5638 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5639 if(rt>=0) {
5640 // Save the PC even if the branch is not taken
5641 return_address=start+i*4+8;
5642 emit_movimm(return_address,rt); // PC into link register
5643 #ifdef IMM_PREFETCH
df4dc2b1 5644 if(!nevertaken) emit_prefetch(hash_table_get(return_address));
57871462 5645 #endif
5646 }
5647 }
5648 cc=get_reg(branch_regs[i].regmap,CCREG);
5649 assert(cc==HOST_CCREG);
9f51b4b9 5650 if(unconditional)
ad49de89 5651 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5652 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5653 assem_debug("cycle count (adj)\n");
5654 if(unconditional) {
5655 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5656 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
2330734f 5657 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
ad49de89 5658 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5659 if(internal)
5660 assem_debug("branch: internal\n");
5661 else
5662 assem_debug("branch: external\n");
cf95b4f0 5663 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
57871462 5664 ds_assemble_entry(i);
5665 }
5666 else {
643aeae3 5667 add_to_linker(out,ba[i],internal);
57871462 5668 emit_jmp(0);
5669 }
5670 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5671 if(((u_int)out)&7) emit_addnop(0);
5672 #endif
5673 }
5674 }
5675 else if(nevertaken) {
2330734f 5676 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
b14b6a8f 5677 void *jaddr=out;
57871462 5678 emit_jns(0);
b14b6a8f 5679 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5680 }
5681 else {
df4dc2b1 5682 void *nottaken = NULL;
57871462 5683 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
2330734f 5684 if(adj&&!invert) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
57871462 5685 {
5686 assert(s1l>=0);
cf95b4f0 5687 if((dops[i].opcode2&0xf)==0) // BLTZ/BLTZAL
57871462 5688 {
5689 emit_test(s1l,s1l);
5690 if(invert){
df4dc2b1 5691 nottaken=out;
7c3a5182 5692 emit_jns(DJT_1);
57871462 5693 }else{
643aeae3 5694 add_to_linker(out,ba[i],internal);
57871462 5695 emit_js(0);
5696 }
5697 }
cf95b4f0 5698 if((dops[i].opcode2&0xf)==1) // BGEZ/BLTZAL
57871462 5699 {
5700 emit_test(s1l,s1l);
5701 if(invert){
df4dc2b1 5702 nottaken=out;
7c3a5182 5703 emit_js(DJT_1);
57871462 5704 }else{
643aeae3 5705 add_to_linker(out,ba[i],internal);
57871462 5706 emit_jns(0);
5707 }
5708 }
ad49de89 5709 }
9f51b4b9 5710
57871462 5711 if(invert) {
5712 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
cf95b4f0 5713 if (match && (!internal || !dops[(ba[i] - start) >> 2].is_ds)) {
57871462 5714 if(adj) {
2330734f 5715 emit_addimm(cc,-adj,cc);
643aeae3 5716 add_to_linker(out,ba[i],internal);
57871462 5717 }else{
5718 emit_addnop(13);
643aeae3 5719 add_to_linker(out,ba[i],internal*2);
57871462 5720 }
5721 emit_jmp(0);
5722 }else
5723 #endif
5724 {
2330734f 5725 if(adj) emit_addimm(cc,-adj,cc);
ad49de89 5726 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5727 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5728 if(internal)
5729 assem_debug("branch: internal\n");
5730 else
5731 assem_debug("branch: external\n");
cf95b4f0 5732 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
57871462 5733 ds_assemble_entry(i);
5734 }
5735 else {
643aeae3 5736 add_to_linker(out,ba[i],internal);
57871462 5737 emit_jmp(0);
5738 }
5739 }
df4dc2b1 5740 set_jump_target(nottaken, out);
57871462 5741 }
5742
5743 if(adj) {
2330734f 5744 if(!invert) emit_addimm(cc,adj,cc);
57871462 5745 }
5746 } // (!unconditional)
5747 } // if(ooo)
5748 else
5749 {
5750 // In-order execution (branch first)
5751 //printf("IOE\n");
df4dc2b1 5752 void *nottaken = NULL;
cf95b4f0 5753 if(dops[i].rt1==31) {
a6491170 5754 int rt,return_address;
a6491170 5755 rt=get_reg(branch_regs[i].regmap,31);
5756 if(rt>=0) {
5757 // Save the PC even if the branch is not taken
5758 return_address=start+i*4+8;
5759 emit_movimm(return_address,rt); // PC into link register
5760 #ifdef IMM_PREFETCH
df4dc2b1 5761 emit_prefetch(hash_table_get(return_address));
a6491170 5762 #endif
5763 }
5764 }
57871462 5765 if(!unconditional) {
5766 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
57871462 5767 assert(s1l>=0);
cf95b4f0 5768 if((dops[i].opcode2&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
57871462 5769 {
5770 emit_test(s1l,s1l);
df4dc2b1 5771 nottaken=out;
7c3a5182 5772 emit_jns(DJT_1);
57871462 5773 }
cf95b4f0 5774 if((dops[i].opcode2&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
57871462 5775 {
5776 emit_test(s1l,s1l);
df4dc2b1 5777 nottaken=out;
7c3a5182 5778 emit_js(DJT_1);
57871462 5779 }
57871462 5780 } // if(!unconditional)
5781 int adj;
5782 uint64_t ds_unneeded=branch_regs[i].u;
cf95b4f0 5783 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
57871462 5784 ds_unneeded|=1;
57871462 5785 // branch taken
5786 if(!nevertaken) {
5787 //assem_debug("1:\n");
ad49de89 5788 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
57871462 5789 // load regs
cf95b4f0 5790 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
57871462 5791 address_generation(i+1,&branch_regs[i],0);
37387d8b 5792 if (ram_offset)
5793 load_regs(regs[i].regmap,branch_regs[i].regmap,ROREG,ROREG);
ad49de89 5794 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
57871462 5795 ds_assemble(i+1,&branch_regs[i]);
5796 cc=get_reg(branch_regs[i].regmap,CCREG);
5797 if(cc==-1) {
5798 emit_loadreg(CCREG,cc=HOST_CCREG);
5799 // CHECK: Is the following instruction (fall thru) allocated ok?
5800 }
5801 assert(cc==HOST_CCREG);
ad49de89 5802 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5803 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5804 assem_debug("cycle count (adj)\n");
2330734f 5805 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
ad49de89 5806 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
57871462 5807 if(internal)
5808 assem_debug("branch: internal\n");
5809 else
5810 assem_debug("branch: external\n");
cf95b4f0 5811 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
57871462 5812 ds_assemble_entry(i);
5813 }
5814 else {
643aeae3 5815 add_to_linker(out,ba[i],internal);
57871462 5816 emit_jmp(0);
5817 }
5818 }
5819 // branch not taken
57871462 5820 if(!unconditional) {
df4dc2b1 5821 set_jump_target(nottaken, out);
57871462 5822 assem_debug("1:\n");
fe807a8a 5823 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5824 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5825 address_generation(i+1,&branch_regs[i],0);
5826 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
5827 ds_assemble(i+1,&branch_regs[i]);
57871462 5828 cc=get_reg(branch_regs[i].regmap,CCREG);
fe807a8a 5829 if (cc == -1) {
57871462 5830 // Cycle count isn't in a register, temporarily load it then write it out
5831 emit_loadreg(CCREG,HOST_CCREG);
2330734f 5832 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
b14b6a8f 5833 void *jaddr=out;
57871462 5834 emit_jns(0);
b14b6a8f 5835 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5836 emit_storereg(CCREG,HOST_CCREG);
5837 }
5838 else{
5839 cc=get_reg(i_regmap,CCREG);
5840 assert(cc==HOST_CCREG);
2330734f 5841 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
b14b6a8f 5842 void *jaddr=out;
57871462 5843 emit_jns(0);
fe807a8a 5844 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
57871462 5845 }
5846 }
5847 }
5848}
5849
2330734f 5850static void pagespan_assemble(int i, const struct regstat *i_regs)
57871462 5851{
cf95b4f0 5852 int s1l=get_reg(i_regs->regmap,dops[i].rs1);
5853 int s2l=get_reg(i_regs->regmap,dops[i].rs2);
df4dc2b1 5854 void *taken = NULL;
5855 void *nottaken = NULL;
57871462 5856 int unconditional=0;
cf95b4f0 5857 if(dops[i].rs1==0)
57871462 5858 {
ad49de89 5859 s1l=s2l;
5860 s2l=-1;
57871462 5861 }
cf95b4f0 5862 else if(dops[i].rs2==0)
57871462 5863 {
ad49de89 5864 s2l=-1;
57871462 5865 }
5866 int hr=0;
581335b0 5867 int addr=-1,alt=-1,ntaddr=-1;
57871462 5868 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
5869 else {
5870 while(hr<HOST_REGS)
5871 {
5872 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
cf95b4f0 5873 (i_regs->regmap[hr]&63)!=dops[i].rs1 &&
5874 (i_regs->regmap[hr]&63)!=dops[i].rs2 )
57871462 5875 {
5876 addr=hr++;break;
5877 }
5878 hr++;
5879 }
5880 }
5881 while(hr<HOST_REGS)
5882 {
5883 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
cf95b4f0 5884 (i_regs->regmap[hr]&63)!=dops[i].rs1 &&
5885 (i_regs->regmap[hr]&63)!=dops[i].rs2 )
57871462 5886 {
5887 alt=hr++;break;
5888 }
5889 hr++;
5890 }
cf95b4f0 5891 if((dops[i].opcode&0x2E)==6) // BLEZ/BGTZ needs another register
57871462 5892 {
5893 while(hr<HOST_REGS)
5894 {
5895 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
cf95b4f0 5896 (i_regs->regmap[hr]&63)!=dops[i].rs1 &&
5897 (i_regs->regmap[hr]&63)!=dops[i].rs2 )
57871462 5898 {
5899 ntaddr=hr;break;
5900 }
5901 hr++;
5902 }
5903 }
5904 assert(hr<HOST_REGS);
cf95b4f0 5905 if((dops[i].opcode&0x2e)==4||dops[i].opcode==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
ad49de89 5906 load_regs(regs[i].regmap_entry,regs[i].regmap,CCREG,CCREG);
57871462 5907 }
2330734f 5908 emit_addimm(HOST_CCREG, ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
cf95b4f0 5909 if(dops[i].opcode==2) // J
57871462 5910 {
5911 unconditional=1;
5912 }
cf95b4f0 5913 if(dops[i].opcode==3) // JAL
57871462 5914 {
5915 // TODO: mini_ht
5916 int rt=get_reg(i_regs->regmap,31);
5917 emit_movimm(start+i*4+8,rt);
5918 unconditional=1;
5919 }
cf95b4f0 5920 if(dops[i].opcode==0&&(dops[i].opcode2&0x3E)==8) // JR/JALR
57871462 5921 {
5922 emit_mov(s1l,addr);
cf95b4f0 5923 if(dops[i].opcode2==9) // JALR
57871462 5924 {
cf95b4f0 5925 int rt=get_reg(i_regs->regmap,dops[i].rt1);
57871462 5926 emit_movimm(start+i*4+8,rt);
5927 }
5928 }
cf95b4f0 5929 if((dops[i].opcode&0x3f)==4) // BEQ
57871462 5930 {
cf95b4f0 5931 if(dops[i].rs1==dops[i].rs2)
57871462 5932 {
5933 unconditional=1;
5934 }
5935 else
5936 #ifdef HAVE_CMOV_IMM
ad49de89 5937 if(1) {
57871462 5938 if(s2l>=0) emit_cmp(s1l,s2l);
5939 else emit_test(s1l,s1l);
5940 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5941 }
5942 else
5943 #endif
5944 {
5945 assert(s1l>=0);
5946 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
57871462 5947 if(s2l>=0) emit_cmp(s1l,s2l);
5948 else emit_test(s1l,s1l);
5949 emit_cmovne_reg(alt,addr);
5950 }
5951 }
cf95b4f0 5952 if((dops[i].opcode&0x3f)==5) // BNE
57871462 5953 {
5954 #ifdef HAVE_CMOV_IMM
ad49de89 5955 if(s2l>=0) emit_cmp(s1l,s2l);
5956 else emit_test(s1l,s1l);
5957 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5958 #else
5959 assert(s1l>=0);
5960 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5961 if(s2l>=0) emit_cmp(s1l,s2l);
5962 else emit_test(s1l,s1l);
5963 emit_cmovne_reg(alt,addr);
57871462 5964 #endif
57871462 5965 }
cf95b4f0 5966 if((dops[i].opcode&0x3f)==0x14) // BEQL
57871462 5967 {
57871462 5968 if(s2l>=0) emit_cmp(s1l,s2l);
5969 else emit_test(s1l,s1l);
df4dc2b1 5970 if(nottaken) set_jump_target(nottaken, out);
5971 nottaken=out;
57871462 5972 emit_jne(0);
5973 }
cf95b4f0 5974 if((dops[i].opcode&0x3f)==0x15) // BNEL
57871462 5975 {
57871462 5976 if(s2l>=0) emit_cmp(s1l,s2l);
5977 else emit_test(s1l,s1l);
df4dc2b1 5978 nottaken=out;
57871462 5979 emit_jeq(0);
df4dc2b1 5980 if(taken) set_jump_target(taken, out);
57871462 5981 }
cf95b4f0 5982 if((dops[i].opcode&0x3f)==6) // BLEZ
57871462 5983 {
5984 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5985 emit_cmpimm(s1l,1);
57871462 5986 emit_cmovl_reg(alt,addr);
57871462 5987 }
cf95b4f0 5988 if((dops[i].opcode&0x3f)==7) // BGTZ
57871462 5989 {
5990 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5991 emit_cmpimm(s1l,1);
57871462 5992 emit_cmovl_reg(ntaddr,addr);
57871462 5993 }
cf95b4f0 5994 if((dops[i].opcode&0x3f)==0x16) // BLEZL
57871462 5995 {
cf95b4f0 5996 assert((dops[i].opcode&0x3f)!=0x16);
57871462 5997 }
cf95b4f0 5998 if((dops[i].opcode&0x3f)==0x17) // BGTZL
57871462 5999 {
cf95b4f0 6000 assert((dops[i].opcode&0x3f)!=0x17);
57871462 6001 }
cf95b4f0 6002 assert(dops[i].opcode!=1); // BLTZ/BGEZ
57871462 6003
6004 //FIXME: Check CSREG
cf95b4f0 6005 if(dops[i].opcode==0x11 && dops[i].opcode2==0x08 ) {
57871462 6006 if((source[i]&0x30000)==0) // BC1F
6007 {
6008 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6009 emit_testimm(s1l,0x800000);
6010 emit_cmovne_reg(alt,addr);
6011 }
6012 if((source[i]&0x30000)==0x10000) // BC1T
6013 {
6014 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6015 emit_testimm(s1l,0x800000);
6016 emit_cmovne_reg(alt,addr);
6017 }
6018 if((source[i]&0x30000)==0x20000) // BC1FL
6019 {
6020 emit_testimm(s1l,0x800000);
df4dc2b1 6021 nottaken=out;
57871462 6022 emit_jne(0);
6023 }
6024 if((source[i]&0x30000)==0x30000) // BC1TL
6025 {
6026 emit_testimm(s1l,0x800000);
df4dc2b1 6027 nottaken=out;
57871462 6028 emit_jeq(0);
6029 }
6030 }
6031
6032 assert(i_regs->regmap[HOST_CCREG]==CCREG);
ad49de89 6033 wb_dirtys(regs[i].regmap,regs[i].dirty);
fe807a8a 6034 if(unconditional)
57871462 6035 {
6036 emit_movimm(ba[i],HOST_BTREG);
6037 }
6038 else if(addr!=HOST_BTREG)
6039 {
6040 emit_mov(addr,HOST_BTREG);
6041 }
6042 void *branch_addr=out;
6043 emit_jmp(0);
6044 int target_addr=start+i*4+5;
6045 void *stub=out;
6046 void *compiled_target_addr=check_addr(target_addr);
643aeae3 6047 emit_extjump_ds(branch_addr, target_addr);
57871462 6048 if(compiled_target_addr) {
df4dc2b1 6049 set_jump_target(branch_addr, compiled_target_addr);
3d680478 6050 add_jump_out(target_addr,stub);
57871462 6051 }
df4dc2b1 6052 else set_jump_target(branch_addr, stub);
57871462 6053}
6054
6055// Assemble the delay slot for the above
6056static void pagespan_ds()
6057{
6058 assem_debug("initial delay slot:\n");
6059 u_int vaddr=start+1;
94d23bb9 6060 u_int page=get_page(vaddr);
6061 u_int vpage=get_vpage(vaddr);
57871462 6062 ll_add(jump_dirty+vpage,vaddr,(void *)out);
3d680478 6063 do_dirty_stub_ds(slen*4);
57871462 6064 ll_add(jump_in+page,vaddr,(void *)out);
6065 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6066 if(regs[0].regmap[HOST_CCREG]!=CCREG)
ad49de89 6067 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty);
57871462 6068 if(regs[0].regmap[HOST_BTREG]!=BTREG)
643aeae3 6069 emit_writeword(HOST_BTREG,&branch_target);
cf95b4f0 6070 load_regs(regs[0].regmap_entry,regs[0].regmap,dops[0].rs1,dops[0].rs2);
57871462 6071 address_generation(0,&regs[0],regs[0].regmap_entry);
37387d8b 6072 if (ram_offset && (dops[0].is_load || dops[0].is_store))
6073 load_regs(regs[0].regmap_entry,regs[0].regmap,ROREG,ROREG);
6074 if (dops[0].is_store)
ad49de89 6075 load_regs(regs[0].regmap_entry,regs[0].regmap,INVCP,INVCP);
57871462 6076 is_delayslot=0;
2330734f 6077 switch (dops[0].itype) {
57871462 6078 case SYSCALL:
7139f3c8 6079 case HLECALL:
1e973cb0 6080 case INTCALL:
57871462 6081 case SPAN:
6082 case UJUMP:
6083 case RJUMP:
6084 case CJUMP:
6085 case SJUMP:
c43b5311 6086 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
2330734f 6087 break;
6088 default:
6089 assemble(0, &regs[0], 0);
57871462 6090 }
6091 int btaddr=get_reg(regs[0].regmap,BTREG);
6092 if(btaddr<0) {
6093 btaddr=get_reg(regs[0].regmap,-1);
643aeae3 6094 emit_readword(&branch_target,btaddr);
57871462 6095 }
6096 assert(btaddr!=HOST_CCREG);
6097 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6098#ifdef HOST_IMM8
d1e4ebd9 6099 host_tempreg_acquire();
57871462 6100 emit_movimm(start+4,HOST_TEMPREG);
6101 emit_cmp(btaddr,HOST_TEMPREG);
d1e4ebd9 6102 host_tempreg_release();
57871462 6103#else
6104 emit_cmpimm(btaddr,start+4);
6105#endif
df4dc2b1 6106 void *branch = out;
57871462 6107 emit_jeq(0);
ad49de89 6108 store_regs_bt(regs[0].regmap,regs[0].dirty,-1);
d1e4ebd9 6109 do_jump_vaddr(btaddr);
df4dc2b1 6110 set_jump_target(branch, out);
ad49de89 6111 store_regs_bt(regs[0].regmap,regs[0].dirty,start+4);
6112 load_regs_bt(regs[0].regmap,regs[0].dirty,start+4);
57871462 6113}
6114
6115// Basic liveness analysis for MIPS registers
6116void unneeded_registers(int istart,int iend,int r)
6117{
6118 int i;
00fa9369 6119 uint64_t u,gte_u,b,gte_b;
6120 uint64_t temp_u,temp_gte_u=0;
0ff8c62c 6121 uint64_t gte_u_unknown=0;
d62c125a 6122 if (HACK_ENABLED(NDHACK_GTE_UNNEEDED))
0ff8c62c 6123 gte_u_unknown=~0ll;
57871462 6124 if(iend==slen-1) {
00fa9369 6125 u=1;
0ff8c62c 6126 gte_u=gte_u_unknown;
57871462 6127 }else{
00fa9369 6128 //u=unneeded_reg[iend+1];
6129 u=1;
0ff8c62c 6130 gte_u=gte_unneeded[iend+1];
57871462 6131 }
bedfea38 6132
57871462 6133 for (i=iend;i>=istart;i--)
6134 {
6135 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
fe807a8a 6136 if(dops[i].is_jump)
57871462 6137 {
6138 // If subroutine call, flag return address as a possible branch target
cf95b4f0 6139 if(dops[i].rt1==31 && i<slen-2) dops[i+2].bt=1;
9f51b4b9 6140
57871462 6141 if(ba[i]<start || ba[i]>=(start+slen*4))
6142 {
6143 // Branch out of this block, flush all regs
6144 u=1;
0ff8c62c 6145 gte_u=gte_u_unknown;
57871462 6146 branch_unneeded_reg[i]=u;
57871462 6147 // Merge in delay slot
cf95b4f0 6148 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6149 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
00fa9369 6150 u|=1;
bedfea38 6151 gte_u|=gte_rt[i+1];
6152 gte_u&=~gte_rs[i+1];
57871462 6153 }
6154 else
6155 {
6156 // Internal branch, flag target
cf95b4f0 6157 dops[(ba[i]-start)>>2].bt=1;
57871462 6158 if(ba[i]<=start+i*4) {
6159 // Backward branch
fe807a8a 6160 if(dops[i].is_ujump)
57871462 6161 {
6162 // Unconditional branch
00fa9369 6163 temp_u=1;
bedfea38 6164 temp_gte_u=0;
57871462 6165 } else {
6166 // Conditional branch (not taken case)
6167 temp_u=unneeded_reg[i+2];
bedfea38 6168 temp_gte_u&=gte_unneeded[i+2];
57871462 6169 }
6170 // Merge in delay slot
cf95b4f0 6171 temp_u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6172 temp_u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
00fa9369 6173 temp_u|=1;
bedfea38 6174 temp_gte_u|=gte_rt[i+1];
6175 temp_gte_u&=~gte_rs[i+1];
cf95b4f0 6176 temp_u|=(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2);
6177 temp_u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
00fa9369 6178 temp_u|=1;
bedfea38 6179 temp_gte_u|=gte_rt[i];
6180 temp_gte_u&=~gte_rs[i];
57871462 6181 unneeded_reg[i]=temp_u;
bedfea38 6182 gte_unneeded[i]=temp_gte_u;
57871462 6183 // Only go three levels deep. This recursion can take an
6184 // excessive amount of time if there are a lot of nested loops.
6185 if(r<2) {
6186 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6187 }else{
6188 unneeded_reg[(ba[i]-start)>>2]=1;
0ff8c62c 6189 gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown;
57871462 6190 }
6191 } /*else*/ if(1) {
fe807a8a 6192 if (dops[i].is_ujump)
57871462 6193 {
6194 // Unconditional branch
6195 u=unneeded_reg[(ba[i]-start)>>2];
bedfea38 6196 gte_u=gte_unneeded[(ba[i]-start)>>2];
57871462 6197 branch_unneeded_reg[i]=u;
57871462 6198 // Merge in delay slot
cf95b4f0 6199 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6200 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
00fa9369 6201 u|=1;
bedfea38 6202 gte_u|=gte_rt[i+1];
6203 gte_u&=~gte_rs[i+1];
57871462 6204 } else {
6205 // Conditional branch
6206 b=unneeded_reg[(ba[i]-start)>>2];
00fa9369 6207 gte_b=gte_unneeded[(ba[i]-start)>>2];
57871462 6208 branch_unneeded_reg[i]=b;
57871462 6209 // Branch delay slot
cf95b4f0 6210 b|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6211 b&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
00fa9369 6212 b|=1;
6213 gte_b|=gte_rt[i+1];
6214 gte_b&=~gte_rs[i+1];
fe807a8a 6215 u&=b;
6216 gte_u&=gte_b;
57871462 6217 if(i<slen-1) {
6218 branch_unneeded_reg[i]&=unneeded_reg[i+2];
57871462 6219 } else {
6220 branch_unneeded_reg[i]=1;
57871462 6221 }
6222 }
6223 }
6224 }
6225 }
cf95b4f0 6226 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
57871462 6227 {
6228 // SYSCALL instruction (software interrupt)
6229 u=1;
57871462 6230 }
cf95b4f0 6231 else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
57871462 6232 {
6233 // ERET instruction (return from interrupt)
6234 u=1;
57871462 6235 }
00fa9369 6236 //u=1; // DEBUG
57871462 6237 // Written registers are unneeded
cf95b4f0 6238 u|=1LL<<dops[i].rt1;
6239 u|=1LL<<dops[i].rt2;
bedfea38 6240 gte_u|=gte_rt[i];
57871462 6241 // Accessed registers are needed
cf95b4f0 6242 u&=~(1LL<<dops[i].rs1);
6243 u&=~(1LL<<dops[i].rs2);
bedfea38 6244 gte_u&=~gte_rs[i];
cf95b4f0 6245 if(gte_rs[i]&&dops[i].rt1&&(unneeded_reg[i+1]&(1ll<<dops[i].rt1)))
cbbd8dd7 6246 gte_u|=gte_rs[i]&gte_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded
57871462 6247 // Source-target dependencies
57871462 6248 // R0 is always unneeded
00fa9369 6249 u|=1;
57871462 6250 // Save it
6251 unneeded_reg[i]=u;
bedfea38 6252 gte_unneeded[i]=gte_u;
57871462 6253 /*
6254 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6255 printf("U:");
6256 int r;
6257 for(r=1;r<=CCREG;r++) {
6258 if((unneeded_reg[i]>>r)&1) {
6259 if(r==HIREG) printf(" HI");
6260 else if(r==LOREG) printf(" LO");
6261 else printf(" r%d",r);
6262 }
6263 }
00fa9369 6264 printf("\n");
6265 */
252c20fc 6266 }
57871462 6267}
6268
71e490c5 6269// Write back dirty registers as soon as we will no longer modify them,
6270// so that we don't end up with lots of writes at the branches.
6271void clean_registers(int istart,int iend,int wr)
57871462 6272{
71e490c5 6273 int i;
6274 int r;
6275 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
6276 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
6277 if(iend==slen-1) {
6278 will_dirty_i=will_dirty_next=0;
6279 wont_dirty_i=wont_dirty_next=0;
6280 }else{
6281 will_dirty_i=will_dirty_next=will_dirty[iend+1];
6282 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
6283 }
6284 for (i=iend;i>=istart;i--)
57871462 6285 {
fe807a8a 6286 if(dops[i].is_jump)
57871462 6287 {
71e490c5 6288 if(ba[i]<start || ba[i]>=(start+slen*4))
57871462 6289 {
71e490c5 6290 // Branch out of this block, flush all regs
fe807a8a 6291 if (dops[i].is_ujump)
57871462 6292 {
6293 // Unconditional branch
6294 will_dirty_i=0;
6295 wont_dirty_i=0;
6296 // Merge in delay slot (will dirty)
6297 for(r=0;r<HOST_REGS;r++) {
6298 if(r!=EXCLUDE_REG) {
cf95b4f0 6299 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6300 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6301 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6302 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
57871462 6303 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6304 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6305 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
cf95b4f0 6306 if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6307 if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6308 if((regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6309 if((regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
57871462 6310 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6311 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6312 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6313 }
6314 }
6315 }
6316 else
6317 {
6318 // Conditional branch
6319 will_dirty_i=0;
6320 wont_dirty_i=wont_dirty_next;
6321 // Merge in delay slot (will dirty)
6322 for(r=0;r<HOST_REGS;r++) {
6323 if(r!=EXCLUDE_REG) {
fe807a8a 6324 if (1) { // !dops[i].likely) {
57871462 6325 // Might not dirty if likely branch is not taken
cf95b4f0 6326 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6327 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6328 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6329 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
57871462 6330 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6331 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
6332 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
cf95b4f0 6333 //if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6334 //if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6335 if((regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6336 if((regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
57871462 6337 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6338 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6339 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6340 }
6341 }
6342 }
6343 }
6344 // Merge in delay slot (wont dirty)
6345 for(r=0;r<HOST_REGS;r++) {
6346 if(r!=EXCLUDE_REG) {
cf95b4f0 6347 if((regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6348 if((regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
6349 if((regs[i].regmap[r]&63)==dops[i+1].rt1) wont_dirty_i|=1<<r;
6350 if((regs[i].regmap[r]&63)==dops[i+1].rt2) wont_dirty_i|=1<<r;
57871462 6351 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
cf95b4f0 6352 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6353 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
6354 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) wont_dirty_i|=1<<r;
6355 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) wont_dirty_i|=1<<r;
57871462 6356 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6357 }
6358 }
6359 if(wr) {
6360 #ifndef DESTRUCTIVE_WRITEBACK
6361 branch_regs[i].dirty&=wont_dirty_i;
6362 #endif
6363 branch_regs[i].dirty|=will_dirty_i;
6364 }
6365 }
6366 else
6367 {
6368 // Internal branch
6369 if(ba[i]<=start+i*4) {
6370 // Backward branch
fe807a8a 6371 if (dops[i].is_ujump)
57871462 6372 {
6373 // Unconditional branch
6374 temp_will_dirty=0;
6375 temp_wont_dirty=0;
6376 // Merge in delay slot (will dirty)
6377 for(r=0;r<HOST_REGS;r++) {
6378 if(r!=EXCLUDE_REG) {
cf95b4f0 6379 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) temp_will_dirty|=1<<r;
6380 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) temp_will_dirty|=1<<r;
6381 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) temp_will_dirty|=1<<r;
6382 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) temp_will_dirty|=1<<r;
57871462 6383 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6384 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6385 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
cf95b4f0 6386 if((regs[i].regmap[r]&63)==dops[i].rt1) temp_will_dirty|=1<<r;
6387 if((regs[i].regmap[r]&63)==dops[i].rt2) temp_will_dirty|=1<<r;
6388 if((regs[i].regmap[r]&63)==dops[i+1].rt1) temp_will_dirty|=1<<r;
6389 if((regs[i].regmap[r]&63)==dops[i+1].rt2) temp_will_dirty|=1<<r;
57871462 6390 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6391 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6392 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6393 }
6394 }
6395 } else {
6396 // Conditional branch (not taken case)
6397 temp_will_dirty=will_dirty_next;
6398 temp_wont_dirty=wont_dirty_next;
6399 // Merge in delay slot (will dirty)
6400 for(r=0;r<HOST_REGS;r++) {
6401 if(r!=EXCLUDE_REG) {
fe807a8a 6402 if (1) { // !dops[i].likely) {
57871462 6403 // Will not dirty if likely branch is not taken
cf95b4f0 6404 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) temp_will_dirty|=1<<r;
6405 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) temp_will_dirty|=1<<r;
6406 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) temp_will_dirty|=1<<r;
6407 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) temp_will_dirty|=1<<r;
57871462 6408 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6409 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
6410 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
cf95b4f0 6411 //if((regs[i].regmap[r]&63)==dops[i].rt1) temp_will_dirty|=1<<r;
6412 //if((regs[i].regmap[r]&63)==dops[i].rt2) temp_will_dirty|=1<<r;
6413 if((regs[i].regmap[r]&63)==dops[i+1].rt1) temp_will_dirty|=1<<r;
6414 if((regs[i].regmap[r]&63)==dops[i+1].rt2) temp_will_dirty|=1<<r;
57871462 6415 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6416 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6417 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6418 }
6419 }
6420 }
6421 }
6422 // Merge in delay slot (wont dirty)
6423 for(r=0;r<HOST_REGS;r++) {
6424 if(r!=EXCLUDE_REG) {
cf95b4f0 6425 if((regs[i].regmap[r]&63)==dops[i].rt1) temp_wont_dirty|=1<<r;
6426 if((regs[i].regmap[r]&63)==dops[i].rt2) temp_wont_dirty|=1<<r;
6427 if((regs[i].regmap[r]&63)==dops[i+1].rt1) temp_wont_dirty|=1<<r;
6428 if((regs[i].regmap[r]&63)==dops[i+1].rt2) temp_wont_dirty|=1<<r;
57871462 6429 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
cf95b4f0 6430 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) temp_wont_dirty|=1<<r;
6431 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) temp_wont_dirty|=1<<r;
6432 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) temp_wont_dirty|=1<<r;
6433 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) temp_wont_dirty|=1<<r;
57871462 6434 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
6435 }
6436 }
6437 // Deal with changed mappings
6438 if(i<iend) {
6439 for(r=0;r<HOST_REGS;r++) {
6440 if(r!=EXCLUDE_REG) {
6441 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
6442 temp_will_dirty&=~(1<<r);
6443 temp_wont_dirty&=~(1<<r);
6444 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
6445 temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6446 temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6447 } else {
6448 temp_will_dirty|=1<<r;
6449 temp_wont_dirty|=1<<r;
6450 }
6451 }
6452 }
6453 }
6454 }
6455 if(wr) {
6456 will_dirty[i]=temp_will_dirty;
6457 wont_dirty[i]=temp_wont_dirty;
6458 clean_registers((ba[i]-start)>>2,i-1,0);
6459 }else{
6460 // Limit recursion. It can take an excessive amount
6461 // of time if there are a lot of nested loops.
6462 will_dirty[(ba[i]-start)>>2]=0;
6463 wont_dirty[(ba[i]-start)>>2]=-1;
6464 }
6465 }
6466 /*else*/ if(1)
6467 {
fe807a8a 6468 if (dops[i].is_ujump)
57871462 6469 {
6470 // Unconditional branch
6471 will_dirty_i=0;
6472 wont_dirty_i=0;
6473 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
6474 for(r=0;r<HOST_REGS;r++) {
6475 if(r!=EXCLUDE_REG) {
6476 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
6477 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
6478 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
6479 }
e3234ecf 6480 if(branch_regs[i].regmap[r]>=0) {
6481 will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
6482 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
6483 }
57871462 6484 }
6485 }
6486 //}
6487 // Merge in delay slot
6488 for(r=0;r<HOST_REGS;r++) {
6489 if(r!=EXCLUDE_REG) {
cf95b4f0 6490 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6491 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6492 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6493 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
57871462 6494 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6495 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6496 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
cf95b4f0 6497 if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6498 if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6499 if((regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6500 if((regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
57871462 6501 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6502 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6503 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6504 }
6505 }
6506 } else {
6507 // Conditional branch
6508 will_dirty_i=will_dirty_next;
6509 wont_dirty_i=wont_dirty_next;
6510 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
6511 for(r=0;r<HOST_REGS;r++) {
6512 if(r!=EXCLUDE_REG) {
e3234ecf 6513 signed char target_reg=branch_regs[i].regmap[r];
6514 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
57871462 6515 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
6516 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
6517 }
e3234ecf 6518 else if(target_reg>=0) {
6519 will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
6520 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
57871462 6521 }
57871462 6522 }
6523 }
6524 //}
6525 // Merge in delay slot
6526 for(r=0;r<HOST_REGS;r++) {
6527 if(r!=EXCLUDE_REG) {
fe807a8a 6528 if (1) { // !dops[i].likely) {
57871462 6529 // Might not dirty if likely branch is not taken
cf95b4f0 6530 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6531 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6532 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6533 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
57871462 6534 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6535 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6536 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
cf95b4f0 6537 //if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6538 //if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6539 if((regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6540 if((regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
57871462 6541 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6542 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6543 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6544 }
6545 }
6546 }
6547 }
e3234ecf 6548 // Merge in delay slot (won't dirty)
57871462 6549 for(r=0;r<HOST_REGS;r++) {
6550 if(r!=EXCLUDE_REG) {
cf95b4f0 6551 if((regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6552 if((regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
6553 if((regs[i].regmap[r]&63)==dops[i+1].rt1) wont_dirty_i|=1<<r;
6554 if((regs[i].regmap[r]&63)==dops[i+1].rt2) wont_dirty_i|=1<<r;
57871462 6555 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
cf95b4f0 6556 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6557 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
6558 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) wont_dirty_i|=1<<r;
6559 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) wont_dirty_i|=1<<r;
57871462 6560 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6561 }
6562 }
6563 if(wr) {
6564 #ifndef DESTRUCTIVE_WRITEBACK
6565 branch_regs[i].dirty&=wont_dirty_i;
6566 #endif
6567 branch_regs[i].dirty|=will_dirty_i;
6568 }
6569 }
6570 }
6571 }
cf95b4f0 6572 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
57871462 6573 {
6574 // SYSCALL instruction (software interrupt)
6575 will_dirty_i=0;
6576 wont_dirty_i=0;
6577 }
cf95b4f0 6578 else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
57871462 6579 {
6580 // ERET instruction (return from interrupt)
6581 will_dirty_i=0;
6582 wont_dirty_i=0;
6583 }
6584 will_dirty_next=will_dirty_i;
6585 wont_dirty_next=wont_dirty_i;
6586 for(r=0;r<HOST_REGS;r++) {
6587 if(r!=EXCLUDE_REG) {
cf95b4f0 6588 if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6589 if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
57871462 6590 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6591 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6592 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
cf95b4f0 6593 if((regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6594 if((regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
57871462 6595 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6596 if(i>istart) {
fe807a8a 6597 if (!dops[i].is_jump)
57871462 6598 {
6599 // Don't store a register immediately after writing it,
6600 // may prevent dual-issue.
cf95b4f0 6601 if((regs[i].regmap[r]&63)==dops[i-1].rt1) wont_dirty_i|=1<<r;
6602 if((regs[i].regmap[r]&63)==dops[i-1].rt2) wont_dirty_i|=1<<r;
57871462 6603 }
6604 }
6605 }
6606 }
6607 // Save it
6608 will_dirty[i]=will_dirty_i;
6609 wont_dirty[i]=wont_dirty_i;
6610 // Mark registers that won't be dirtied as not dirty
6611 if(wr) {
57871462 6612 regs[i].dirty|=will_dirty_i;
6613 #ifndef DESTRUCTIVE_WRITEBACK
6614 regs[i].dirty&=wont_dirty_i;
fe807a8a 6615 if(dops[i].is_jump)
57871462 6616 {
fe807a8a 6617 if (i < iend-1 && !dops[i].is_ujump) {
57871462 6618 for(r=0;r<HOST_REGS;r++) {
6619 if(r!=EXCLUDE_REG) {
6620 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
6621 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
581335b0 6622 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
57871462 6623 }
6624 }
6625 }
6626 }
6627 else
6628 {
6629 if(i<iend) {
6630 for(r=0;r<HOST_REGS;r++) {
6631 if(r!=EXCLUDE_REG) {
6632 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
6633 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
581335b0 6634 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
57871462 6635 }
6636 }
6637 }
6638 }
6639 #endif
6640 //}
6641 }
6642 // Deal with changed mappings
6643 temp_will_dirty=will_dirty_i;
6644 temp_wont_dirty=wont_dirty_i;
6645 for(r=0;r<HOST_REGS;r++) {
6646 if(r!=EXCLUDE_REG) {
6647 int nr;
6648 if(regs[i].regmap[r]==regmap_pre[i][r]) {
6649 if(wr) {
6650 #ifndef DESTRUCTIVE_WRITEBACK
6651 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
6652 #endif
6653 regs[i].wasdirty|=will_dirty_i&(1<<r);
6654 }
6655 }
f776eb14 6656 else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
57871462 6657 // Register moved to a different register
6658 will_dirty_i&=~(1<<r);
6659 wont_dirty_i&=~(1<<r);
6660 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
6661 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
6662 if(wr) {
6663 #ifndef DESTRUCTIVE_WRITEBACK
6664 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
6665 #endif
6666 regs[i].wasdirty|=will_dirty_i&(1<<r);
6667 }
6668 }
6669 else {
6670 will_dirty_i&=~(1<<r);
6671 wont_dirty_i&=~(1<<r);
6672 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
6673 will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6674 wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6675 } else {
6676 wont_dirty_i|=1<<r;
581335b0 6677 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);assert(!((will_dirty>>r)&1));*/
57871462 6678 }
6679 }
6680 }
6681 }
6682 }
6683}
6684
4600ba03 6685#ifdef DISASM
57871462 6686 /* disassembly */
6687void disassemble_inst(int i)
6688{
cf95b4f0 6689 if (dops[i].bt) printf("*"); else printf(" ");
6690 switch(dops[i].itype) {
57871462 6691 case UJUMP:
6692 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
6693 case CJUMP:
cf95b4f0 6694 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2,i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
57871462 6695 case SJUMP:
cf95b4f0 6696 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
57871462 6697 case RJUMP:
cf95b4f0 6698 if (dops[i].opcode==0x9&&dops[i].rt1!=31)
6699 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1);
5067f341 6700 else
cf95b4f0 6701 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
5067f341 6702 break;
57871462 6703 case SPAN:
cf95b4f0 6704 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2,ba[i]);break;
57871462 6705 case IMM16:
cf95b4f0 6706 if(dops[i].opcode==0xf) //LUI
6707 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],dops[i].rt1,imm[i]&0xffff);
57871462 6708 else
cf95b4f0 6709 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
57871462 6710 break;
6711 case LOAD:
6712 case LOADLR:
cf95b4f0 6713 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
57871462 6714 break;
6715 case STORE:
6716 case STORELR:
cf95b4f0 6717 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rs2,dops[i].rs1,imm[i]);
57871462 6718 break;
6719 case ALU:
6720 case SHIFT:
cf95b4f0 6721 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,dops[i].rs2);
57871462 6722 break;
6723 case MULTDIV:
cf95b4f0 6724 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2);
57871462 6725 break;
6726 case SHIFTIMM:
cf95b4f0 6727 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
57871462 6728 break;
6729 case MOV:
cf95b4f0 6730 if((dops[i].opcode2&0x1d)==0x10)
6731 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rt1);
6732 else if((dops[i].opcode2&0x1d)==0x11)
6733 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
57871462 6734 else
6735 printf (" %x: %s\n",start+i*4,insn[i]);
6736 break;
6737 case COP0:
cf95b4f0 6738 if(dops[i].opcode2==0)
6739 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC0
6740 else if(dops[i].opcode2==4)
6741 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC0
57871462 6742 else printf (" %x: %s\n",start+i*4,insn[i]);
6743 break;
6744 case COP1:
cf95b4f0 6745 if(dops[i].opcode2<3)
6746 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC1
6747 else if(dops[i].opcode2>3)
6748 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC1
57871462 6749 else printf (" %x: %s\n",start+i*4,insn[i]);
6750 break;
b9b61529 6751 case COP2:
cf95b4f0 6752 if(dops[i].opcode2<3)
6753 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC2
6754 else if(dops[i].opcode2>3)
6755 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC2
b9b61529 6756 else printf (" %x: %s\n",start+i*4,insn[i]);
6757 break;
57871462 6758 case C1LS:
cf95b4f0 6759 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,imm[i]);
57871462 6760 break;
b9b61529 6761 case C2LS:
cf95b4f0 6762 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,imm[i]);
b9b61529 6763 break;
1e973cb0 6764 case INTCALL:
6765 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
6766 break;
57871462 6767 default:
6768 //printf (" %s %8x\n",insn[i],source[i]);
6769 printf (" %x: %s\n",start+i*4,insn[i]);
6770 }
6771}
4600ba03 6772#else
6773static void disassemble_inst(int i) {}
6774#endif // DISASM
57871462 6775
d848b60a 6776#define DRC_TEST_VAL 0x74657374
6777
be516ebe 6778static void new_dynarec_test(void)
d848b60a 6779{
be516ebe 6780 int (*testfunc)(void);
d148d265 6781 void *beginning;
be516ebe 6782 int ret[2];
6783 size_t i;
d148d265 6784
687b4580 6785 // check structure linkage
7c3a5182 6786 if ((u_char *)rcnts - (u_char *)&psxRegs != sizeof(psxRegs))
687b4580 6787 {
7c3a5182 6788 SysPrintf("linkage_arm* miscompilation/breakage detected.\n");
687b4580 6789 }
6790
be516ebe 6791 SysPrintf("testing if we can run recompiled code...\n");
6792 ((volatile u_int *)out)[0]++; // make cache dirty
6793
6794 for (i = 0; i < ARRAY_SIZE(ret); i++) {
2a014d73 6795 out = ndrc->translation_cache;
be516ebe 6796 beginning = start_block();
6797 emit_movimm(DRC_TEST_VAL + i, 0); // test
6798 emit_ret();
6799 literal_pool(0);
6800 end_block(beginning);
6801 testfunc = beginning;
6802 ret[i] = testfunc();
6803 }
6804
6805 if (ret[0] == DRC_TEST_VAL && ret[1] == DRC_TEST_VAL + 1)
d848b60a 6806 SysPrintf("test passed.\n");
6807 else
be516ebe 6808 SysPrintf("test failed, will likely crash soon (r=%08x %08x)\n", ret[0], ret[1]);
2a014d73 6809 out = ndrc->translation_cache;
d848b60a 6810}
6811
dc990066 6812// clear the state completely, instead of just marking
6813// things invalid like invalidate_all_pages() does
919981d0 6814void new_dynarec_clear_full(void)
57871462 6815{
57871462 6816 int n;
2a014d73 6817 out = ndrc->translation_cache;
35775df7 6818 memset(invalid_code,1,sizeof(invalid_code));
6819 memset(hash_table,0xff,sizeof(hash_table));
57871462 6820 memset(mini_ht,-1,sizeof(mini_ht));
6821 memset(restore_candidate,0,sizeof(restore_candidate));
dc990066 6822 memset(shadow,0,sizeof(shadow));
57871462 6823 copy=shadow;
6824 expirep=16384; // Expiry pointer, +2 blocks
6825 pending_exception=0;
6826 literalcount=0;
57871462 6827 stop_after_jal=0;
9be4ba64 6828 inv_code_start=inv_code_end=~0;
39b71d9a 6829 f1_hack=0;
57871462 6830 // TLB
dc990066 6831 for(n=0;n<4096;n++) ll_clear(jump_in+n);
6832 for(n=0;n<4096;n++) ll_clear(jump_out+n);
6833 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
32631e6a 6834
6835 cycle_multiplier_old = cycle_multiplier;
6836 new_dynarec_hacks_old = new_dynarec_hacks;
dc990066 6837}
6838
919981d0 6839void new_dynarec_init(void)
dc990066 6840{
d848b60a 6841 SysPrintf("Init new dynarec\n");
1e212a25 6842
2a014d73 6843#ifdef BASE_ADDR_DYNAMIC
1e212a25 6844 #ifdef VITA
6845 sceBlock = sceKernelAllocMemBlockForVM("code", 1 << TARGET_SIZE_2);
6846 if (sceBlock < 0)
6847 SysPrintf("sceKernelAllocMemBlockForVM failed\n");
2a014d73 6848 int ret = sceKernelGetMemBlockBase(sceBlock, (void **)&ndrc);
1e212a25 6849 if (ret < 0)
6850 SysPrintf("sceKernelGetMemBlockBase failed\n");
6851 #else
2a014d73 6852 uintptr_t desired_addr = 0;
6853 #ifdef __ELF__
6854 extern char _end;
6855 desired_addr = ((uintptr_t)&_end + 0xffffff) & ~0xffffffl;
6856 #endif
6857 ndrc = mmap((void *)desired_addr, sizeof(*ndrc),
1e212a25 6858 PROT_READ | PROT_WRITE | PROT_EXEC,
6859 MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
2a014d73 6860 if (ndrc == MAP_FAILED) {
d848b60a 6861 SysPrintf("mmap() failed: %s\n", strerror(errno));
1e212a25 6862 abort();
d848b60a 6863 }
1e212a25 6864 #endif
6865#else
6866 #ifndef NO_WRITE_EXEC
bdeade46 6867 // not all systems allow execute in data segment by default
2a014d73 6868 if (mprotect(ndrc, sizeof(ndrc->translation_cache) + sizeof(ndrc->tramp.ops),
6869 PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
d848b60a 6870 SysPrintf("mprotect() failed: %s\n", strerror(errno));
1e212a25 6871 #endif
dc990066 6872#endif
2a014d73 6873 out = ndrc->translation_cache;
2573466a 6874 cycle_multiplier=200;
dc990066 6875 new_dynarec_clear_full();
6876#ifdef HOST_IMM8
6877 // Copy this into local area so we don't have to put it in every literal pool
6878 invc_ptr=invalid_code;
6879#endif
57871462 6880 arch_init();
d848b60a 6881 new_dynarec_test();
01d26796 6882 ram_offset=(uintptr_t)rdram-0x80000000;
b105cf4f 6883 if (ram_offset!=0)
c43b5311 6884 SysPrintf("warning: RAM is not directly mapped, performance will suffer\n");
57871462 6885}
6886
919981d0 6887void new_dynarec_cleanup(void)
57871462 6888{
6889 int n;
2a014d73 6890#ifdef BASE_ADDR_DYNAMIC
1e212a25 6891 #ifdef VITA
6892 sceKernelFreeMemBlock(sceBlock);
6893 sceBlock = -1;
6894 #else
2a014d73 6895 if (munmap(ndrc, sizeof(*ndrc)) < 0)
1e212a25 6896 SysPrintf("munmap() failed\n");
bdeade46 6897 #endif
1e212a25 6898#endif
57871462 6899 for(n=0;n<4096;n++) ll_clear(jump_in+n);
6900 for(n=0;n<4096;n++) ll_clear(jump_out+n);
6901 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
6902 #ifdef ROM_COPY
c43b5311 6903 if (munmap (ROM_COPY, 67108864) < 0) {SysPrintf("munmap() failed\n");}
57871462 6904 #endif
6905}
6906
03f55e6b 6907static u_int *get_source_start(u_int addr, u_int *limit)
57871462 6908{
d62c125a 6909 if (!HACK_ENABLED(NDHACK_OVERRIDE_CYCLE_M))
a3203cf4 6910 cycle_multiplier_override = 0;
6911
03f55e6b 6912 if (addr < 0x00200000 ||
a3203cf4 6913 (0xa0000000 <= addr && addr < 0xa0200000))
6914 {
03f55e6b 6915 // used for BIOS calls mostly?
6916 *limit = (addr&0xa0000000)|0x00200000;
01d26796 6917 return (u_int *)(rdram + (addr&0x1fffff));
03f55e6b 6918 }
6919 else if (!Config.HLE && (
6920 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
a3203cf4 6921 (0xbfc00000 <= addr && addr < 0xbfc80000)))
6922 {
6923 // BIOS. The multiplier should be much higher as it's uncached 8bit mem,
6924 // but timings in PCSX are too tied to the interpreter's BIAS
d62c125a 6925 if (!HACK_ENABLED(NDHACK_OVERRIDE_CYCLE_M))
a3203cf4 6926 cycle_multiplier_override = 200;
6927
03f55e6b 6928 *limit = (addr & 0xfff00000) | 0x80000;
01d26796 6929 return (u_int *)((u_char *)psxR + (addr&0x7ffff));
03f55e6b 6930 }
6931 else if (addr >= 0x80000000 && addr < 0x80000000+RAM_SIZE) {
6932 *limit = (addr & 0x80600000) + 0x00200000;
01d26796 6933 return (u_int *)(rdram + (addr&0x1fffff));
03f55e6b 6934 }
581335b0 6935 return NULL;
03f55e6b 6936}
6937
6938static u_int scan_for_ret(u_int addr)
6939{
6940 u_int limit = 0;
6941 u_int *mem;
6942
6943 mem = get_source_start(addr, &limit);
6944 if (mem == NULL)
6945 return addr;
6946
6947 if (limit > addr + 0x1000)
6948 limit = addr + 0x1000;
6949 for (; addr < limit; addr += 4, mem++) {
6950 if (*mem == 0x03e00008) // jr $ra
6951 return addr + 8;
57871462 6952 }
581335b0 6953 return addr;
03f55e6b 6954}
6955
6956struct savestate_block {
6957 uint32_t addr;
6958 uint32_t regflags;
6959};
6960
6961static int addr_cmp(const void *p1_, const void *p2_)
6962{
6963 const struct savestate_block *p1 = p1_, *p2 = p2_;
6964 return p1->addr - p2->addr;
6965}
6966
6967int new_dynarec_save_blocks(void *save, int size)
6968{
6969 struct savestate_block *blocks = save;
6970 int maxcount = size / sizeof(blocks[0]);
6971 struct savestate_block tmp_blocks[1024];
6972 struct ll_entry *head;
6973 int p, s, d, o, bcnt;
6974 u_int addr;
6975
6976 o = 0;
b14b6a8f 6977 for (p = 0; p < ARRAY_SIZE(jump_in); p++) {
03f55e6b 6978 bcnt = 0;
6979 for (head = jump_in[p]; head != NULL; head = head->next) {
6980 tmp_blocks[bcnt].addr = head->vaddr;
6981 tmp_blocks[bcnt].regflags = head->reg_sv_flags;
6982 bcnt++;
6983 }
6984 if (bcnt < 1)
6985 continue;
6986 qsort(tmp_blocks, bcnt, sizeof(tmp_blocks[0]), addr_cmp);
6987
6988 addr = tmp_blocks[0].addr;
6989 for (s = d = 0; s < bcnt; s++) {
6990 if (tmp_blocks[s].addr < addr)
6991 continue;
6992 if (d == 0 || tmp_blocks[d-1].addr != tmp_blocks[s].addr)
6993 tmp_blocks[d++] = tmp_blocks[s];
6994 addr = scan_for_ret(tmp_blocks[s].addr);
6995 }
6996
6997 if (o + d > maxcount)
6998 d = maxcount - o;
6999 memcpy(&blocks[o], tmp_blocks, d * sizeof(blocks[0]));
7000 o += d;
7001 }
7002
7003 return o * sizeof(blocks[0]);
7004}
7005
7006void new_dynarec_load_blocks(const void *save, int size)
7007{
7008 const struct savestate_block *blocks = save;
7009 int count = size / sizeof(blocks[0]);
7010 u_int regs_save[32];
7011 uint32_t f;
7012 int i, b;
7013
7014 get_addr(psxRegs.pc);
7015
7016 // change GPRs for speculation to at least partially work..
7017 memcpy(regs_save, &psxRegs.GPR, sizeof(regs_save));
7018 for (i = 1; i < 32; i++)
7019 psxRegs.GPR.r[i] = 0x80000000;
7020
7021 for (b = 0; b < count; b++) {
7022 for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) {
7023 if (f & 1)
7024 psxRegs.GPR.r[i] = 0x1f800000;
7025 }
7026
7027 get_addr(blocks[b].addr);
7028
7029 for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) {
7030 if (f & 1)
7031 psxRegs.GPR.r[i] = 0x80000000;
7032 }
7033 }
7034
7035 memcpy(&psxRegs.GPR, regs_save, sizeof(regs_save));
7036}
7037
3968e69e 7038int new_recompile_block(u_int addr)
03f55e6b 7039{
7040 u_int pagelimit = 0;
7041 u_int state_rflags = 0;
7042 int i;
7043
1a4301c4 7044 assem_debug("NOTCOMPILED: addr = %x -> %p\n", addr, out);
57871462 7045 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
9f51b4b9 7046 //if(debug)
57871462 7047 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
03f55e6b 7048
7049 // this is just for speculation
7050 for (i = 1; i < 32; i++) {
7051 if ((psxRegs.GPR.r[i] & 0xffff0000) == 0x1f800000)
7052 state_rflags |= 1 << i;
7053 }
7054
57871462 7055 start = (u_int)addr&~3;
7c3a5182 7056 //assert(((u_int)addr&1)==0); // start-in-delay-slot flag
2f546f9a 7057 new_dynarec_did_compile=1;
9ad4d757 7058 if (Config.HLE && start == 0x80001000) // hlecall
560e4a12 7059 {
7139f3c8 7060 // XXX: is this enough? Maybe check hleSoftCall?
d148d265 7061 void *beginning=start_block();
7139f3c8 7062 u_int page=get_page(start);
d148d265 7063
7139f3c8 7064 invalid_code[start>>12]=0;
7065 emit_movimm(start,0);
643aeae3 7066 emit_writeword(0,&pcaddr);
2a014d73 7067 emit_far_jump(new_dyna_leave);
15776b68 7068 literal_pool(0);
d148d265 7069 end_block(beginning);
03f55e6b 7070 ll_add_flags(jump_in+page,start,state_rflags,(void *)beginning);
7139f3c8 7071 return 0;
7072 }
39b71d9a 7073 else if (f1_hack == ~0u || (f1_hack != 0 && start == f1_hack)) {
7074 void *beginning = start_block();
7075 u_int page = get_page(start);
7076 emit_readword(&psxRegs.GPR.n.sp, 0);
7077 emit_readptr(&mem_rtab, 1);
7078 emit_shrimm(0, 12, 2);
7079 emit_readptr_dualindexedx_ptrlen(1, 2, 1);
7080 emit_addimm(0, 0x18, 0);
7081 emit_adds_ptr(1, 1, 1);
7082 emit_ldr_dualindexed(1, 0, 0);
7083 emit_writeword(0, &psxRegs.GPR.r[26]); // lw k0, 0x18(sp)
7084 emit_far_call(get_addr_ht);
7085 emit_jmpreg(0); // jr k0
7086 literal_pool(0);
7087 end_block(beginning);
7088
7089 ll_add_flags(jump_in + page, start, state_rflags, beginning);
7090 SysPrintf("F1 hack to %08x\n", start);
7091 f1_hack = start;
7092 return 0;
7093 }
03f55e6b 7094
7095 source = get_source_start(start, &pagelimit);
7096 if (source == NULL) {
7097 SysPrintf("Compile at bogus memory address: %08x\n", addr);
7c3a5182 7098 abort();
57871462 7099 }
7100
7101 /* Pass 1: disassemble */
7102 /* Pass 2: register dependencies, branch targets */
7103 /* Pass 3: register allocation */
7104 /* Pass 4: branch dependencies */
7105 /* Pass 5: pre-alloc */
7106 /* Pass 6: optimize clean/dirty state */
7107 /* Pass 7: flag 32-bit registers */
7108 /* Pass 8: assembly */
7109 /* Pass 9: linker */
7110 /* Pass 10: garbage collection / free memory */
7111
03f55e6b 7112 int j;
57871462 7113 int done=0;
7114 unsigned int type,op,op2;
7115
7116 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
9f51b4b9 7117
57871462 7118 /* Pass 1 disassembly */
7119
7120 for(i=0;!done;i++) {
cf95b4f0 7121 dops[i].bt=0;
cf95b4f0 7122 dops[i].ooo=0;
7123 op2=0;
e1190b87 7124 minimum_free_regs[i]=0;
cf95b4f0 7125 dops[i].opcode=op=source[i]>>26;
57871462 7126 switch(op)
7127 {
7128 case 0x00: strcpy(insn[i],"special"); type=NI;
7129 op2=source[i]&0x3f;
7130 switch(op2)
7131 {
7132 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
7133 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
7134 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
7135 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
7136 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
7137 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
7138 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
7139 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
7140 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
7141 case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
7142 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
7143 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
7144 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
7145 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
7146 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
57871462 7147 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
7148 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
7149 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
7150 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
57871462 7151 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
7152 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
7153 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
7154 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
7155 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
7156 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
7157 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
7158 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
7159 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
7160 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
57871462 7161 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
7162 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
7163 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
7164 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
7165 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
7166 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
71e490c5 7167#if 0
7f2607ea 7168 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
7169 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
7170 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
7171 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
7172 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
7173 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
7174 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
7175 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
7176 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
7177 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
7178 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
57871462 7179 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
7180 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
7181 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
7182 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
7183 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
7184 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
7f2607ea 7185#endif
57871462 7186 }
7187 break;
7188 case 0x01: strcpy(insn[i],"regimm"); type=NI;
7189 op2=(source[i]>>16)&0x1f;
7190 switch(op2)
7191 {
7192 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
7193 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
4919de1e 7194 //case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
7195 //case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
7196 //case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
7197 //case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
7198 //case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
7199 //case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
7200 //case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
7201 //case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
57871462 7202 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
7203 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
4919de1e 7204 //case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
7205 //case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
57871462 7206 }
7207 break;
7208 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
7209 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
7210 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
7211 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
7212 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
7213 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
7214 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
7215 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
7216 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
7217 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
7218 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
7219 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
7220 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
7221 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
7222 case 0x10: strcpy(insn[i],"cop0"); type=NI;
7223 op2=(source[i]>>21)&0x1f;
7224 switch(op2)
7225 {
7226 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
00fa9369 7227 case 0x02: strcpy(insn[i],"CFC0"); type=COP0; break;
57871462 7228 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
00fa9369 7229 case 0x06: strcpy(insn[i],"CTC0"); type=COP0; break;
7230 case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
57871462 7231 }
7232 break;
00fa9369 7233 case 0x11: strcpy(insn[i],"cop1"); type=COP1;
57871462 7234 op2=(source[i]>>21)&0x1f;
57871462 7235 break;
71e490c5 7236#if 0
57871462 7237 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
7238 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
7239 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
7240 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
7241 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
7242 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
7243 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
7244 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
996cc15d 7245#endif
57871462 7246 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
7247 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
7248 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
7249 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
7250 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
7251 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
7252 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
71e490c5 7253#if 0
57871462 7254 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
64bd6f82 7255#endif
57871462 7256 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
7257 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
7258 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
7259 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
71e490c5 7260#if 0
57871462 7261 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
7262 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
996cc15d 7263#endif
57871462 7264 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
7265 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
7266 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
7267 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
71e490c5 7268#if 0
57871462 7269 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
7270 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
7271 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
996cc15d 7272#endif
57871462 7273 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
7274 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
71e490c5 7275#if 0
57871462 7276 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
7277 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
7278 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
996cc15d 7279#endif
b9b61529 7280 case 0x12: strcpy(insn[i],"COP2"); type=NI;
7281 op2=(source[i]>>21)&0x1f;
be516ebe 7282 //if (op2 & 0x10)
bedfea38 7283 if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
c7abc864 7284 if (gte_handlers[source[i]&0x3f]!=NULL) {
bedfea38 7285 if (gte_regnames[source[i]&0x3f]!=NULL)
7286 strcpy(insn[i],gte_regnames[source[i]&0x3f]);
7287 else
7288 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
c7abc864 7289 type=C2OP;
7290 }
7291 }
7292 else switch(op2)
b9b61529 7293 {
7294 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
7295 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
7296 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
7297 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
b9b61529 7298 }
7299 break;
7300 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
7301 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
7302 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
90ae6d4e 7303 default: strcpy(insn[i],"???"); type=NI;
c43b5311 7304 SysPrintf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
90ae6d4e 7305 break;
57871462 7306 }
cf95b4f0 7307 dops[i].itype=type;
7308 dops[i].opcode2=op2;
57871462 7309 /* Get registers/immediates */
cf95b4f0 7310 dops[i].lt1=0;
bedfea38 7311 gte_rs[i]=gte_rt[i]=0;
57871462 7312 switch(type) {
7313 case LOAD:
cf95b4f0 7314 dops[i].rs1=(source[i]>>21)&0x1f;
7315 dops[i].rs2=0;
7316 dops[i].rt1=(source[i]>>16)&0x1f;
7317 dops[i].rt2=0;
57871462 7318 imm[i]=(short)source[i];
7319 break;
7320 case STORE:
7321 case STORELR:
cf95b4f0 7322 dops[i].rs1=(source[i]>>21)&0x1f;
7323 dops[i].rs2=(source[i]>>16)&0x1f;
7324 dops[i].rt1=0;
7325 dops[i].rt2=0;
57871462 7326 imm[i]=(short)source[i];
57871462 7327 break;
7328 case LOADLR:
7329 // LWL/LWR only load part of the register,
7330 // therefore the target register must be treated as a source too
cf95b4f0 7331 dops[i].rs1=(source[i]>>21)&0x1f;
7332 dops[i].rs2=(source[i]>>16)&0x1f;
7333 dops[i].rt1=(source[i]>>16)&0x1f;
7334 dops[i].rt2=0;
57871462 7335 imm[i]=(short)source[i];
57871462 7336 break;
7337 case IMM16:
cf95b4f0 7338 if (op==0x0f) dops[i].rs1=0; // LUI instruction has no source register
7339 else dops[i].rs1=(source[i]>>21)&0x1f;
7340 dops[i].rs2=0;
7341 dops[i].rt1=(source[i]>>16)&0x1f;
7342 dops[i].rt2=0;
57871462 7343 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
7344 imm[i]=(unsigned short)source[i];
7345 }else{
7346 imm[i]=(short)source[i];
7347 }
57871462 7348 break;
7349 case UJUMP:
cf95b4f0 7350 dops[i].rs1=0;
7351 dops[i].rs2=0;
7352 dops[i].rt1=0;
7353 dops[i].rt2=0;
57871462 7354 // The JAL instruction writes to r31.
7355 if (op&1) {
cf95b4f0 7356 dops[i].rt1=31;
57871462 7357 }
cf95b4f0 7358 dops[i].rs2=CCREG;
57871462 7359 break;
7360 case RJUMP:
cf95b4f0 7361 dops[i].rs1=(source[i]>>21)&0x1f;
7362 dops[i].rs2=0;
7363 dops[i].rt1=0;
7364 dops[i].rt2=0;
5067f341 7365 // The JALR instruction writes to rd.
57871462 7366 if (op2&1) {
cf95b4f0 7367 dops[i].rt1=(source[i]>>11)&0x1f;
57871462 7368 }
cf95b4f0 7369 dops[i].rs2=CCREG;
57871462 7370 break;
7371 case CJUMP:
cf95b4f0 7372 dops[i].rs1=(source[i]>>21)&0x1f;
7373 dops[i].rs2=(source[i]>>16)&0x1f;
7374 dops[i].rt1=0;
7375 dops[i].rt2=0;
57871462 7376 if(op&2) { // BGTZ/BLEZ
cf95b4f0 7377 dops[i].rs2=0;
57871462 7378 }
57871462 7379 break;
7380 case SJUMP:
cf95b4f0 7381 dops[i].rs1=(source[i]>>21)&0x1f;
7382 dops[i].rs2=CCREG;
7383 dops[i].rt1=0;
7384 dops[i].rt2=0;
57871462 7385 if(op2&0x10) { // BxxAL
cf95b4f0 7386 dops[i].rt1=31;
57871462 7387 // NOTE: If the branch is not taken, r31 is still overwritten
7388 }
57871462 7389 break;
57871462 7390 case ALU:
cf95b4f0 7391 dops[i].rs1=(source[i]>>21)&0x1f; // source
7392 dops[i].rs2=(source[i]>>16)&0x1f; // subtract amount
7393 dops[i].rt1=(source[i]>>11)&0x1f; // destination
7394 dops[i].rt2=0;
57871462 7395 break;
7396 case MULTDIV:
cf95b4f0 7397 dops[i].rs1=(source[i]>>21)&0x1f; // source
7398 dops[i].rs2=(source[i]>>16)&0x1f; // divisor
7399 dops[i].rt1=HIREG;
7400 dops[i].rt2=LOREG;
57871462 7401 break;
7402 case MOV:
cf95b4f0 7403 dops[i].rs1=0;
7404 dops[i].rs2=0;
7405 dops[i].rt1=0;
7406 dops[i].rt2=0;
7407 if(op2==0x10) dops[i].rs1=HIREG; // MFHI
7408 if(op2==0x11) dops[i].rt1=HIREG; // MTHI
7409 if(op2==0x12) dops[i].rs1=LOREG; // MFLO
7410 if(op2==0x13) dops[i].rt1=LOREG; // MTLO
7411 if((op2&0x1d)==0x10) dops[i].rt1=(source[i]>>11)&0x1f; // MFxx
7412 if((op2&0x1d)==0x11) dops[i].rs1=(source[i]>>21)&0x1f; // MTxx
57871462 7413 break;
7414 case SHIFT:
cf95b4f0 7415 dops[i].rs1=(source[i]>>16)&0x1f; // target of shift
7416 dops[i].rs2=(source[i]>>21)&0x1f; // shift amount
7417 dops[i].rt1=(source[i]>>11)&0x1f; // destination
7418 dops[i].rt2=0;
57871462 7419 break;
7420 case SHIFTIMM:
cf95b4f0 7421 dops[i].rs1=(source[i]>>16)&0x1f;
7422 dops[i].rs2=0;
7423 dops[i].rt1=(source[i]>>11)&0x1f;
7424 dops[i].rt2=0;
57871462 7425 imm[i]=(source[i]>>6)&0x1f;
7426 // DSxx32 instructions
7427 if(op2>=0x3c) imm[i]|=0x20;
57871462 7428 break;
7429 case COP0:
cf95b4f0 7430 dops[i].rs1=0;
7431 dops[i].rs2=0;
7432 dops[i].rt1=0;
7433 dops[i].rt2=0;
7434 if(op2==0||op2==2) dops[i].rt1=(source[i]>>16)&0x1F; // MFC0/CFC0
7435 if(op2==4||op2==6) dops[i].rs1=(source[i]>>16)&0x1F; // MTC0/CTC0
7436 if(op2==4&&((source[i]>>11)&0x1f)==12) dops[i].rt2=CSREG; // Status
7437 if(op2==16) if((source[i]&0x3f)==0x18) dops[i].rs2=CCREG; // ERET
57871462 7438 break;
7439 case COP1:
cf95b4f0 7440 dops[i].rs1=0;
7441 dops[i].rs2=0;
7442 dops[i].rt1=0;
7443 dops[i].rt2=0;
7444 if(op2<3) dops[i].rt1=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
7445 if(op2>3) dops[i].rs1=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
7446 dops[i].rs2=CSREG;
57871462 7447 break;
bedfea38 7448 case COP2:
cf95b4f0 7449 dops[i].rs1=0;
7450 dops[i].rs2=0;
7451 dops[i].rt1=0;
7452 dops[i].rt2=0;
7453 if(op2<3) dops[i].rt1=(source[i]>>16)&0x1F; // MFC2/CFC2
7454 if(op2>3) dops[i].rs1=(source[i]>>16)&0x1F; // MTC2/CTC2
7455 dops[i].rs2=CSREG;
bedfea38 7456 int gr=(source[i]>>11)&0x1F;
7457 switch(op2)
7458 {
7459 case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
7460 case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
0ff8c62c 7461 case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2
bedfea38 7462 case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
7463 }
7464 break;
57871462 7465 case C1LS:
cf95b4f0 7466 dops[i].rs1=(source[i]>>21)&0x1F;
7467 dops[i].rs2=CSREG;
7468 dops[i].rt1=0;
7469 dops[i].rt2=0;
57871462 7470 imm[i]=(short)source[i];
7471 break;
b9b61529 7472 case C2LS:
cf95b4f0 7473 dops[i].rs1=(source[i]>>21)&0x1F;
7474 dops[i].rs2=0;
7475 dops[i].rt1=0;
7476 dops[i].rt2=0;
b9b61529 7477 imm[i]=(short)source[i];
bedfea38 7478 if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
7479 else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
7480 break;
7481 case C2OP:
cf95b4f0 7482 dops[i].rs1=0;
7483 dops[i].rs2=0;
7484 dops[i].rt1=0;
7485 dops[i].rt2=0;
2167bef6 7486 gte_rs[i]=gte_reg_reads[source[i]&0x3f];
7487 gte_rt[i]=gte_reg_writes[source[i]&0x3f];
7488 gte_rt[i]|=1ll<<63; // every op changes flags
587a5b1c 7489 if((source[i]&0x3f)==GTE_MVMVA) {
7490 int v = (source[i] >> 15) & 3;
7491 gte_rs[i]&=~0xe3fll;
7492 if(v==3) gte_rs[i]|=0xe00ll;
7493 else gte_rs[i]|=3ll<<(v*2);
7494 }
b9b61529 7495 break;
57871462 7496 case SYSCALL:
7139f3c8 7497 case HLECALL:
1e973cb0 7498 case INTCALL:
cf95b4f0 7499 dops[i].rs1=CCREG;
7500 dops[i].rs2=0;
7501 dops[i].rt1=0;
7502 dops[i].rt2=0;
57871462 7503 break;
7504 default:
cf95b4f0 7505 dops[i].rs1=0;
7506 dops[i].rs2=0;
7507 dops[i].rt1=0;
7508 dops[i].rt2=0;
57871462 7509 }
7510 /* Calculate branch target addresses */
7511 if(type==UJUMP)
7512 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
cf95b4f0 7513 else if(type==CJUMP&&dops[i].rs1==dops[i].rs2&&(op&1))
57871462 7514 ba[i]=start+i*4+8; // Ignore never taken branch
cf95b4f0 7515 else if(type==SJUMP&&dops[i].rs1==0&&!(op2&1))
57871462 7516 ba[i]=start+i*4+8; // Ignore never taken branch
ad49de89 7517 else if(type==CJUMP||type==SJUMP)
57871462 7518 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
7519 else ba[i]=-1;
4919de1e 7520
7521 /* simplify always (not)taken branches */
cf95b4f0 7522 if (type == CJUMP && dops[i].rs1 == dops[i].rs2) {
7523 dops[i].rs1 = dops[i].rs2 = 0;
4919de1e 7524 if (!(op & 1)) {
cf95b4f0 7525 dops[i].itype = type = UJUMP;
7526 dops[i].rs2 = CCREG;
4919de1e 7527 }
7528 }
cf95b4f0 7529 else if (type == SJUMP && dops[i].rs1 == 0 && (op2 & 1))
7530 dops[i].itype = type = UJUMP;
4919de1e 7531
fe807a8a 7532 dops[i].is_jump = (dops[i].itype == RJUMP || dops[i].itype == UJUMP || dops[i].itype == CJUMP || dops[i].itype == SJUMP);
7533 dops[i].is_ujump = (dops[i].itype == RJUMP || dops[i].itype == UJUMP); // || (source[i] >> 16) == 0x1000 // beq r0,r0
37387d8b 7534 dops[i].is_load = (dops[i].itype == LOAD || dops[i].itype == LOADLR || op == 0x32); // LWC2
7535 dops[i].is_store = (dops[i].itype == STORE || dops[i].itype == STORELR || op == 0x3a); // SWC2
fe807a8a 7536
4919de1e 7537 /* messy cases to just pass over to the interpreter */
fe807a8a 7538 if (i > 0 && dops[i-1].is_jump) {
3e535354 7539 int do_in_intrp=0;
7540 // branch in delay slot?
fe807a8a 7541 if (dops[i].is_jump) {
3e535354 7542 // don't handle first branch and call interpreter if it's hit
c43b5311 7543 SysPrintf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
3e535354 7544 do_in_intrp=1;
7545 }
7546 // basic load delay detection
cf95b4f0 7547 else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&dops[i].rt1!=0) {
3e535354 7548 int t=(ba[i-1]-start)/4;
cf95b4f0 7549 if(0 <= t && t < i &&(dops[i].rt1==dops[t].rs1||dops[i].rt1==dops[t].rs2)&&dops[t].itype!=CJUMP&&dops[t].itype!=SJUMP) {
3e535354 7550 // jump target wants DS result - potential load delay effect
c43b5311 7551 SysPrintf("load delay @%08x (%08x)\n", addr + i*4, addr);
3e535354 7552 do_in_intrp=1;
cf95b4f0 7553 dops[t+1].bt=1; // expected return from interpreter
3e535354 7554 }
cf95b4f0 7555 else if(i>=2&&dops[i-2].rt1==2&&dops[i].rt1==2&&dops[i].rs1!=2&&dops[i].rs2!=2&&dops[i-1].rs1!=2&&dops[i-1].rs2!=2&&
fe807a8a 7556 !(i>=3&&dops[i-3].is_jump)) {
3e535354 7557 // v0 overwrite like this is a sign of trouble, bail out
c43b5311 7558 SysPrintf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
3e535354 7559 do_in_intrp=1;
7560 }
7561 }
3e535354 7562 if(do_in_intrp) {
cf95b4f0 7563 dops[i-1].rs1=CCREG;
7564 dops[i-1].rs2=dops[i-1].rt1=dops[i-1].rt2=0;
26869094 7565 ba[i-1]=-1;
cf95b4f0 7566 dops[i-1].itype=INTCALL;
26869094 7567 done=2;
3e535354 7568 i--; // don't compile the DS
26869094 7569 }
3e535354 7570 }
4919de1e 7571
3e535354 7572 /* Is this the end of the block? */
fe807a8a 7573 if (i > 0 && dops[i-1].is_ujump) {
cf95b4f0 7574 if(dops[i-1].rt1==0) { // Continue past subroutine call (JAL)
1e973cb0 7575 done=2;
57871462 7576 }
7577 else {
7578 if(stop_after_jal) done=1;
7579 // Stop on BREAK
7580 if((source[i+1]&0xfc00003f)==0x0d) done=1;
7581 }
7582 // Don't recompile stuff that's already compiled
7583 if(check_addr(start+i*4+4)) done=1;
7584 // Don't get too close to the limit
7585 if(i>MAXBLOCK/2) done=1;
7586 }
cf95b4f0 7587 if(dops[i].itype==SYSCALL&&stop_after_jal) done=1;
7588 if(dops[i].itype==HLECALL||dops[i].itype==INTCALL) done=2;
1e973cb0 7589 if(done==2) {
7590 // Does the block continue due to a branch?
7591 for(j=i-1;j>=0;j--)
7592 {
2a706964 7593 if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
1e973cb0 7594 if(ba[j]==start+i*4+4) done=j=0;
7595 if(ba[j]==start+i*4+8) done=j=0;
7596 }
7597 }
75dec299 7598 //assert(i<MAXBLOCK-1);
57871462 7599 if(start+i*4==pagelimit-4) done=1;
7600 assert(start+i*4<pagelimit);
7601 if (i==MAXBLOCK-1) done=1;
7602 // Stop if we're compiling junk
cf95b4f0 7603 if(dops[i].itype==NI&&dops[i].opcode==0x11) {
57871462 7604 done=stop_after_jal=1;
c43b5311 7605 SysPrintf("Disabled speculative precompilation\n");
57871462 7606 }
7607 }
7608 slen=i;
fe807a8a 7609 if (dops[i-1].is_jump) {
57871462 7610 if(start+i*4==pagelimit) {
cf95b4f0 7611 dops[i-1].itype=SPAN;
57871462 7612 }
7613 }
7614 assert(slen>0);
7615
39b71d9a 7616 /* spacial hack(s) */
7617 if (i > 10 && source[i-1] == 0 && source[i-2] == 0x03e00008
7618 && source[i-4] == 0x8fbf0018 && source[i-6] == 0x00c0f809
7619 && dops[i-7].itype == STORE)
7620 {
7621 i = i-8;
7622 if (dops[i].itype == IMM16)
7623 i--;
7624 // swl r2, 15(r6); swr r2, 12(r6); sw r6, *; jalr r6
7625 if (dops[i].itype == STORELR && dops[i].rs1 == 6
7626 && dops[i-1].itype == STORELR && dops[i-1].rs1 == 6)
7627 {
7628 SysPrintf("F1 hack from %08x\n", start);
c979e8c2 7629 if (f1_hack == 0)
7630 f1_hack = ~0u;
39b71d9a 7631 }
7632 }
7633
57871462 7634 /* Pass 2 - Register dependencies and branch targets */
7635
7636 unneeded_registers(0,slen-1,0);
9f51b4b9 7637
57871462 7638 /* Pass 3 - Register allocation */
7639
7640 struct regstat current; // Current register allocations/status
57871462 7641 current.dirty=0;
7642 current.u=unneeded_reg[0];
57871462 7643 clear_all_regs(current.regmap);
7644 alloc_reg(&current,0,CCREG);
7645 dirty_reg(&current,CCREG);
7646 current.isconst=0;
7647 current.wasconst=0;
27727b63 7648 current.waswritten=0;
57871462 7649 int ds=0;
7650 int cc=0;
5194fb95 7651 int hr=-1;
6ebf4adf 7652
57871462 7653 if((u_int)addr&1) {
7654 // First instruction is delay slot
7655 cc=-1;
cf95b4f0 7656 dops[1].bt=1;
57871462 7657 ds=1;
7658 unneeded_reg[0]=1;
57871462 7659 current.regmap[HOST_BTREG]=BTREG;
7660 }
9f51b4b9 7661
57871462 7662 for(i=0;i<slen;i++)
7663 {
cf95b4f0 7664 if(dops[i].bt)
57871462 7665 {
7666 int hr;
7667 for(hr=0;hr<HOST_REGS;hr++)
7668 {
7669 // Is this really necessary?
7670 if(current.regmap[hr]==0) current.regmap[hr]=-1;
7671 }
7672 current.isconst=0;
27727b63 7673 current.waswritten=0;
57871462 7674 }
24385cae 7675
57871462 7676 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
7677 regs[i].wasconst=current.isconst;
57871462 7678 regs[i].wasdirty=current.dirty;
8575a877 7679 regs[i].loadedconst=0;
fe807a8a 7680 if (!dops[i].is_jump) {
57871462 7681 if(i+1<slen) {
cf95b4f0 7682 current.u=unneeded_reg[i+1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7683 current.u|=1;
57871462 7684 } else {
7685 current.u=1;
57871462 7686 }
7687 } else {
7688 if(i+1<slen) {
cf95b4f0 7689 current.u=branch_unneeded_reg[i]&~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7690 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7691 current.u|=1;
7c3a5182 7692 } else { SysPrintf("oops, branch at end of block with no delay slot\n");abort(); }
57871462 7693 }
cf95b4f0 7694 dops[i].is_ds=ds;
57871462 7695 if(ds) {
7696 ds=0; // Skip delay slot, already allocated as part of branch
7697 // ...but we need to alloc it in case something jumps here
7698 if(i+1<slen) {
7699 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
57871462 7700 }else{
7701 current.u=branch_unneeded_reg[i-1];
57871462 7702 }
cf95b4f0 7703 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 7704 current.u|=1;
57871462 7705 struct regstat temp;
7706 memcpy(&temp,&current,sizeof(current));
7707 temp.wasdirty=temp.dirty;
57871462 7708 // TODO: Take into account unconditional branches, as below
7709 delayslot_alloc(&temp,i);
7710 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
7711 regs[i].wasdirty=temp.wasdirty;
57871462 7712 regs[i].dirty=temp.dirty;
57871462 7713 regs[i].isconst=0;
7714 regs[i].wasconst=0;
7715 current.isconst=0;
7716 // Create entry (branch target) regmap
7717 for(hr=0;hr<HOST_REGS;hr++)
7718 {
7719 int r=temp.regmap[hr];
7720 if(r>=0) {
7721 if(r!=regmap_pre[i][hr]) {
7722 regs[i].regmap_entry[hr]=-1;
7723 }
7724 else
7725 {
7c3a5182 7726 assert(r < 64);
57871462 7727 if((current.u>>r)&1) {
7728 regs[i].regmap_entry[hr]=-1;
7729 regs[i].regmap[hr]=-1;
7730 //Don't clear regs in the delay slot as the branch might need them
7731 //current.regmap[hr]=-1;
7732 }else
7733 regs[i].regmap_entry[hr]=r;
57871462 7734 }
7735 } else {
7736 // First instruction expects CCREG to be allocated
9f51b4b9 7737 if(i==0&&hr==HOST_CCREG)
57871462 7738 regs[i].regmap_entry[hr]=CCREG;
7739 else
7740 regs[i].regmap_entry[hr]=-1;
7741 }
7742 }
7743 }
7744 else { // Not delay slot
cf95b4f0 7745 switch(dops[i].itype) {
57871462 7746 case UJUMP:
7747 //current.isconst=0; // DEBUG
7748 //current.wasconst=0; // DEBUG
7749 //regs[i].wasconst=0; // DEBUG
cf95b4f0 7750 clear_const(&current,dops[i].rt1);
57871462 7751 alloc_cc(&current,i);
7752 dirty_reg(&current,CCREG);
cf95b4f0 7753 if (dops[i].rt1==31) {
57871462 7754 alloc_reg(&current,i,31);
7755 dirty_reg(&current,31);
cf95b4f0 7756 //assert(dops[i+1].rs1!=31&&dops[i+1].rs2!=31);
7757 //assert(dops[i+1].rt1!=dops[i].rt1);
57871462 7758 #ifdef REG_PREFETCH
7759 alloc_reg(&current,i,PTEMP);
7760 #endif
57871462 7761 }
cf95b4f0 7762 dops[i].ooo=1;
269bb29a 7763 delayslot_alloc(&current,i+1);
57871462 7764 //current.isconst=0; // DEBUG
7765 ds=1;
7766 //printf("i=%d, isconst=%x\n",i,current.isconst);
7767 break;
7768 case RJUMP:
7769 //current.isconst=0;
7770 //current.wasconst=0;
7771 //regs[i].wasconst=0;
cf95b4f0 7772 clear_const(&current,dops[i].rs1);
7773 clear_const(&current,dops[i].rt1);
57871462 7774 alloc_cc(&current,i);
7775 dirty_reg(&current,CCREG);
4919de1e 7776 if (!ds_writes_rjump_rs(i)) {
cf95b4f0 7777 alloc_reg(&current,i,dops[i].rs1);
7778 if (dops[i].rt1!=0) {
7779 alloc_reg(&current,i,dops[i].rt1);
7780 dirty_reg(&current,dops[i].rt1);
7781 assert(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt1);
7782 assert(dops[i+1].rt1!=dops[i].rt1);
57871462 7783 #ifdef REG_PREFETCH
7784 alloc_reg(&current,i,PTEMP);
7785 #endif
7786 }
7787 #ifdef USE_MINI_HT
cf95b4f0 7788 if(dops[i].rs1==31) { // JALR
57871462 7789 alloc_reg(&current,i,RHASH);
57871462 7790 alloc_reg(&current,i,RHTBL);
57871462 7791 }
7792 #endif
7793 delayslot_alloc(&current,i+1);
7794 } else {
7795 // The delay slot overwrites our source register,
7796 // allocate a temporary register to hold the old value.
7797 current.isconst=0;
7798 current.wasconst=0;
7799 regs[i].wasconst=0;
7800 delayslot_alloc(&current,i+1);
7801 current.isconst=0;
7802 alloc_reg(&current,i,RTEMP);
7803 }
7804 //current.isconst=0; // DEBUG
cf95b4f0 7805 dops[i].ooo=1;
57871462 7806 ds=1;
7807 break;
7808 case CJUMP:
7809 //current.isconst=0;
7810 //current.wasconst=0;
7811 //regs[i].wasconst=0;
cf95b4f0 7812 clear_const(&current,dops[i].rs1);
7813 clear_const(&current,dops[i].rs2);
7814 if((dops[i].opcode&0x3E)==4) // BEQ/BNE
57871462 7815 {
7816 alloc_cc(&current,i);
7817 dirty_reg(&current,CCREG);
cf95b4f0 7818 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
7819 if(dops[i].rs2) alloc_reg(&current,i,dops[i].rs2);
7820 if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2))||
7821 (dops[i].rs2&&(dops[i].rs2==dops[i+1].rt1||dops[i].rs2==dops[i+1].rt2))) {
57871462 7822 // The delay slot overwrites one of our conditions.
7823 // Allocate the branch condition registers instead.
57871462 7824 current.isconst=0;
7825 current.wasconst=0;
7826 regs[i].wasconst=0;
cf95b4f0 7827 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
7828 if(dops[i].rs2) alloc_reg(&current,i,dops[i].rs2);
57871462 7829 }
e1190b87 7830 else
7831 {
cf95b4f0 7832 dops[i].ooo=1;
e1190b87 7833 delayslot_alloc(&current,i+1);
7834 }
57871462 7835 }
7836 else
cf95b4f0 7837 if((dops[i].opcode&0x3E)==6) // BLEZ/BGTZ
57871462 7838 {
7839 alloc_cc(&current,i);
7840 dirty_reg(&current,CCREG);
cf95b4f0 7841 alloc_reg(&current,i,dops[i].rs1);
7842 if(dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) {
57871462 7843 // The delay slot overwrites one of our conditions.
7844 // Allocate the branch condition registers instead.
57871462 7845 current.isconst=0;
7846 current.wasconst=0;
7847 regs[i].wasconst=0;
cf95b4f0 7848 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
57871462 7849 }
e1190b87 7850 else
7851 {
cf95b4f0 7852 dops[i].ooo=1;
e1190b87 7853 delayslot_alloc(&current,i+1);
7854 }
57871462 7855 }
7856 else
7857 // Don't alloc the delay slot yet because we might not execute it
cf95b4f0 7858 if((dops[i].opcode&0x3E)==0x14) // BEQL/BNEL
57871462 7859 {
7860 current.isconst=0;
7861 current.wasconst=0;
7862 regs[i].wasconst=0;
7863 alloc_cc(&current,i);
7864 dirty_reg(&current,CCREG);
cf95b4f0 7865 alloc_reg(&current,i,dops[i].rs1);
7866 alloc_reg(&current,i,dops[i].rs2);
57871462 7867 }
7868 else
cf95b4f0 7869 if((dops[i].opcode&0x3E)==0x16) // BLEZL/BGTZL
57871462 7870 {
7871 current.isconst=0;
7872 current.wasconst=0;
7873 regs[i].wasconst=0;
7874 alloc_cc(&current,i);
7875 dirty_reg(&current,CCREG);
cf95b4f0 7876 alloc_reg(&current,i,dops[i].rs1);
57871462 7877 }
7878 ds=1;
7879 //current.isconst=0;
7880 break;
7881 case SJUMP:
7882 //current.isconst=0;
7883 //current.wasconst=0;
7884 //regs[i].wasconst=0;
cf95b4f0 7885 clear_const(&current,dops[i].rs1);
7886 clear_const(&current,dops[i].rt1);
7887 //if((dops[i].opcode2&0x1E)==0x0) // BLTZ/BGEZ
7888 if((dops[i].opcode2&0x0E)==0x0) // BLTZ/BGEZ
57871462 7889 {
7890 alloc_cc(&current,i);
7891 dirty_reg(&current,CCREG);
cf95b4f0 7892 alloc_reg(&current,i,dops[i].rs1);
7893 if (dops[i].rt1==31) { // BLTZAL/BGEZAL
57871462 7894 alloc_reg(&current,i,31);
7895 dirty_reg(&current,31);
57871462 7896 //#ifdef REG_PREFETCH
7897 //alloc_reg(&current,i,PTEMP);
7898 //#endif
57871462 7899 }
cf95b4f0 7900 if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) // The delay slot overwrites the branch condition.
7901 ||(dops[i].rt1==31&&(dops[i+1].rs1==31||dops[i+1].rs2==31||dops[i+1].rt1==31||dops[i+1].rt2==31))) { // DS touches $ra
57871462 7902 // Allocate the branch condition registers instead.
57871462 7903 current.isconst=0;
7904 current.wasconst=0;
7905 regs[i].wasconst=0;
cf95b4f0 7906 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
57871462 7907 }
e1190b87 7908 else
7909 {
cf95b4f0 7910 dops[i].ooo=1;
e1190b87 7911 delayslot_alloc(&current,i+1);
7912 }
57871462 7913 }
7914 else
7915 // Don't alloc the delay slot yet because we might not execute it
cf95b4f0 7916 if((dops[i].opcode2&0x1E)==0x2) // BLTZL/BGEZL
57871462 7917 {
7918 current.isconst=0;
7919 current.wasconst=0;
7920 regs[i].wasconst=0;
7921 alloc_cc(&current,i);
7922 dirty_reg(&current,CCREG);
cf95b4f0 7923 alloc_reg(&current,i,dops[i].rs1);
57871462 7924 }
7925 ds=1;
7926 //current.isconst=0;
7927 break;
57871462 7928 case IMM16:
7929 imm16_alloc(&current,i);
7930 break;
7931 case LOAD:
7932 case LOADLR:
7933 load_alloc(&current,i);
7934 break;
7935 case STORE:
7936 case STORELR:
7937 store_alloc(&current,i);
7938 break;
7939 case ALU:
7940 alu_alloc(&current,i);
7941 break;
7942 case SHIFT:
7943 shift_alloc(&current,i);
7944 break;
7945 case MULTDIV:
7946 multdiv_alloc(&current,i);
7947 break;
7948 case SHIFTIMM:
7949 shiftimm_alloc(&current,i);
7950 break;
7951 case MOV:
7952 mov_alloc(&current,i);
7953 break;
7954 case COP0:
7955 cop0_alloc(&current,i);
7956 break;
7957 case COP1:
81dbbf4c 7958 break;
b9b61529 7959 case COP2:
81dbbf4c 7960 cop2_alloc(&current,i);
57871462 7961 break;
7962 case C1LS:
7963 c1ls_alloc(&current,i);
7964 break;
b9b61529 7965 case C2LS:
7966 c2ls_alloc(&current,i);
7967 break;
7968 case C2OP:
7969 c2op_alloc(&current,i);
7970 break;
57871462 7971 case SYSCALL:
7139f3c8 7972 case HLECALL:
1e973cb0 7973 case INTCALL:
57871462 7974 syscall_alloc(&current,i);
7975 break;
7976 case SPAN:
7977 pagespan_alloc(&current,i);
7978 break;
7979 }
9f51b4b9 7980
57871462 7981 // Create entry (branch target) regmap
7982 for(hr=0;hr<HOST_REGS;hr++)
7983 {
581335b0 7984 int r,or;
57871462 7985 r=current.regmap[hr];
7986 if(r>=0) {
7987 if(r!=regmap_pre[i][hr]) {
7988 // TODO: delay slot (?)
7989 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
7990 if(or<0||(r&63)>=TEMPREG){
7991 regs[i].regmap_entry[hr]=-1;
7992 }
7993 else
7994 {
7995 // Just move it to a different register
7996 regs[i].regmap_entry[hr]=r;
7997 // If it was dirty before, it's still dirty
7998 if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r&63);
7999 }
8000 }
8001 else
8002 {
8003 // Unneeded
8004 if(r==0){
8005 regs[i].regmap_entry[hr]=0;
8006 }
8007 else
7c3a5182 8008 {
8009 assert(r<64);
57871462 8010 if((current.u>>r)&1) {
8011 regs[i].regmap_entry[hr]=-1;
8012 //regs[i].regmap[hr]=-1;
8013 current.regmap[hr]=-1;
8014 }else
8015 regs[i].regmap_entry[hr]=r;
8016 }
57871462 8017 }
8018 } else {
8019 // Branches expect CCREG to be allocated at the target
9f51b4b9 8020 if(regmap_pre[i][hr]==CCREG)
57871462 8021 regs[i].regmap_entry[hr]=CCREG;
8022 else
8023 regs[i].regmap_entry[hr]=-1;
8024 }
8025 }
8026 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
8027 }
27727b63 8028
cf95b4f0 8029 if(i>0&&(dops[i-1].itype==STORE||dops[i-1].itype==STORELR||(dops[i-1].itype==C2LS&&dops[i-1].opcode==0x3a))&&(u_int)imm[i-1]<0x800)
8030 current.waswritten|=1<<dops[i-1].rs1;
8031 current.waswritten&=~(1<<dops[i].rt1);
8032 current.waswritten&=~(1<<dops[i].rt2);
8033 if((dops[i].itype==STORE||dops[i].itype==STORELR||(dops[i].itype==C2LS&&dops[i].opcode==0x3a))&&(u_int)imm[i]>=0x800)
8034 current.waswritten&=~(1<<dops[i].rs1);
27727b63 8035
57871462 8036 /* Branch post-alloc */
8037 if(i>0)
8038 {
57871462 8039 current.wasdirty=current.dirty;
cf95b4f0 8040 switch(dops[i-1].itype) {
57871462 8041 case UJUMP:
8042 memcpy(&branch_regs[i-1],&current,sizeof(current));
8043 branch_regs[i-1].isconst=0;
8044 branch_regs[i-1].wasconst=0;
cf95b4f0 8045 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
57871462 8046 alloc_cc(&branch_regs[i-1],i-1);
8047 dirty_reg(&branch_regs[i-1],CCREG);
cf95b4f0 8048 if(dops[i-1].rt1==31) { // JAL
57871462 8049 alloc_reg(&branch_regs[i-1],i-1,31);
8050 dirty_reg(&branch_regs[i-1],31);
57871462 8051 }
8052 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
40fca85b 8053 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 8054 break;
8055 case RJUMP:
8056 memcpy(&branch_regs[i-1],&current,sizeof(current));
8057 branch_regs[i-1].isconst=0;
8058 branch_regs[i-1].wasconst=0;
cf95b4f0 8059 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
57871462 8060 alloc_cc(&branch_regs[i-1],i-1);
8061 dirty_reg(&branch_regs[i-1],CCREG);
cf95b4f0 8062 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rs1);
8063 if(dops[i-1].rt1!=0) { // JALR
8064 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rt1);
8065 dirty_reg(&branch_regs[i-1],dops[i-1].rt1);
57871462 8066 }
8067 #ifdef USE_MINI_HT
cf95b4f0 8068 if(dops[i-1].rs1==31) { // JALR
57871462 8069 alloc_reg(&branch_regs[i-1],i-1,RHASH);
57871462 8070 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
57871462 8071 }
8072 #endif
8073 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
40fca85b 8074 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 8075 break;
8076 case CJUMP:
cf95b4f0 8077 if((dops[i-1].opcode&0x3E)==4) // BEQ/BNE
57871462 8078 {
8079 alloc_cc(&current,i-1);
8080 dirty_reg(&current,CCREG);
cf95b4f0 8081 if((dops[i-1].rs1&&(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2))||
8082 (dops[i-1].rs2&&(dops[i-1].rs2==dops[i].rt1||dops[i-1].rs2==dops[i].rt2))) {
57871462 8083 // The delay slot overwrote one of our conditions
8084 // Delay slot goes after the test (in order)
cf95b4f0 8085 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 8086 current.u|=1;
57871462 8087 delayslot_alloc(&current,i);
8088 current.isconst=0;
8089 }
8090 else
8091 {
cf95b4f0 8092 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
57871462 8093 // Alloc the branch condition registers
cf95b4f0 8094 if(dops[i-1].rs1) alloc_reg(&current,i-1,dops[i-1].rs1);
8095 if(dops[i-1].rs2) alloc_reg(&current,i-1,dops[i-1].rs2);
57871462 8096 }
8097 memcpy(&branch_regs[i-1],&current,sizeof(current));
8098 branch_regs[i-1].isconst=0;
8099 branch_regs[i-1].wasconst=0;
8100 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
40fca85b 8101 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 8102 }
8103 else
cf95b4f0 8104 if((dops[i-1].opcode&0x3E)==6) // BLEZ/BGTZ
57871462 8105 {
8106 alloc_cc(&current,i-1);
8107 dirty_reg(&current,CCREG);
cf95b4f0 8108 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
57871462 8109 // The delay slot overwrote the branch condition
8110 // Delay slot goes after the test (in order)
cf95b4f0 8111 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 8112 current.u|=1;
57871462 8113 delayslot_alloc(&current,i);
8114 current.isconst=0;
8115 }
8116 else
8117 {
cf95b4f0 8118 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
57871462 8119 // Alloc the branch condition register
cf95b4f0 8120 alloc_reg(&current,i-1,dops[i-1].rs1);
57871462 8121 }
8122 memcpy(&branch_regs[i-1],&current,sizeof(current));
8123 branch_regs[i-1].isconst=0;
8124 branch_regs[i-1].wasconst=0;
8125 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
40fca85b 8126 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 8127 }
8128 else
8129 // Alloc the delay slot in case the branch is taken
cf95b4f0 8130 if((dops[i-1].opcode&0x3E)==0x14) // BEQL/BNEL
57871462 8131 {
8132 memcpy(&branch_regs[i-1],&current,sizeof(current));
cf95b4f0 8133 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
57871462 8134 alloc_cc(&branch_regs[i-1],i);
8135 dirty_reg(&branch_regs[i-1],CCREG);
8136 delayslot_alloc(&branch_regs[i-1],i);
8137 branch_regs[i-1].isconst=0;
8138 alloc_reg(&current,i,CCREG); // Not taken path
8139 dirty_reg(&current,CCREG);
8140 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8141 }
8142 else
cf95b4f0 8143 if((dops[i-1].opcode&0x3E)==0x16) // BLEZL/BGTZL
57871462 8144 {
8145 memcpy(&branch_regs[i-1],&current,sizeof(current));
cf95b4f0 8146 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
57871462 8147 alloc_cc(&branch_regs[i-1],i);
8148 dirty_reg(&branch_regs[i-1],CCREG);
8149 delayslot_alloc(&branch_regs[i-1],i);
8150 branch_regs[i-1].isconst=0;
8151 alloc_reg(&current,i,CCREG); // Not taken path
8152 dirty_reg(&current,CCREG);
8153 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8154 }
8155 break;
8156 case SJUMP:
cf95b4f0 8157 //if((dops[i-1].opcode2&0x1E)==0) // BLTZ/BGEZ
8158 if((dops[i-1].opcode2&0x0E)==0) // BLTZ/BGEZ
57871462 8159 {
8160 alloc_cc(&current,i-1);
8161 dirty_reg(&current,CCREG);
cf95b4f0 8162 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
57871462 8163 // The delay slot overwrote the branch condition
8164 // Delay slot goes after the test (in order)
cf95b4f0 8165 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
57871462 8166 current.u|=1;
57871462 8167 delayslot_alloc(&current,i);
8168 current.isconst=0;
8169 }
8170 else
8171 {
cf95b4f0 8172 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
57871462 8173 // Alloc the branch condition register
cf95b4f0 8174 alloc_reg(&current,i-1,dops[i-1].rs1);
57871462 8175 }
8176 memcpy(&branch_regs[i-1],&current,sizeof(current));
8177 branch_regs[i-1].isconst=0;
8178 branch_regs[i-1].wasconst=0;
8179 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
40fca85b 8180 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
57871462 8181 }
8182 else
8183 // Alloc the delay slot in case the branch is taken
cf95b4f0 8184 if((dops[i-1].opcode2&0x1E)==2) // BLTZL/BGEZL
57871462 8185 {
8186 memcpy(&branch_regs[i-1],&current,sizeof(current));
cf95b4f0 8187 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
57871462 8188 alloc_cc(&branch_regs[i-1],i);
8189 dirty_reg(&branch_regs[i-1],CCREG);
8190 delayslot_alloc(&branch_regs[i-1],i);
8191 branch_regs[i-1].isconst=0;
8192 alloc_reg(&current,i,CCREG); // Not taken path
8193 dirty_reg(&current,CCREG);
8194 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8195 }
8196 // FIXME: BLTZAL/BGEZAL
cf95b4f0 8197 if(dops[i-1].opcode2&0x10) { // BxxZAL
57871462 8198 alloc_reg(&branch_regs[i-1],i-1,31);
8199 dirty_reg(&branch_regs[i-1],31);
57871462 8200 }
8201 break;
57871462 8202 }
8203
fe807a8a 8204 if (dops[i-1].is_ujump)
57871462 8205 {
cf95b4f0 8206 if(dops[i-1].rt1==31) // JAL/JALR
57871462 8207 {
8208 // Subroutine call will return here, don't alloc any registers
57871462 8209 current.dirty=0;
8210 clear_all_regs(current.regmap);
8211 alloc_reg(&current,i,CCREG);
8212 dirty_reg(&current,CCREG);
8213 }
8214 else if(i+1<slen)
8215 {
8216 // Internal branch will jump here, match registers to caller
57871462 8217 current.dirty=0;
8218 clear_all_regs(current.regmap);
8219 alloc_reg(&current,i,CCREG);
8220 dirty_reg(&current,CCREG);
8221 for(j=i-1;j>=0;j--)
8222 {
8223 if(ba[j]==start+i*4+4) {
8224 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
57871462 8225 current.dirty=branch_regs[j].dirty;
8226 break;
8227 }
8228 }
8229 while(j>=0) {
8230 if(ba[j]==start+i*4+4) {
8231 for(hr=0;hr<HOST_REGS;hr++) {
8232 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
8233 current.regmap[hr]=-1;
8234 }
57871462 8235 current.dirty&=branch_regs[j].dirty;
8236 }
8237 }
8238 j--;
8239 }
8240 }
8241 }
8242 }
8243
8244 // Count cycles in between branches
2330734f 8245 ccadj[i] = CLOCK_ADJUST(cc);
fe807a8a 8246 if (i > 0 && (dops[i-1].is_jump || dops[i].itype == SYSCALL || dops[i].itype == HLECALL))
57871462 8247 {
8248 cc=0;
8249 }
71e490c5 8250#if !defined(DRC_DBG)
cf95b4f0 8251 else if(dops[i].itype==C2OP&&gte_cycletab[source[i]&0x3f]>2)
054175e9 8252 {
81dbbf4c 8253 // this should really be removed since the real stalls have been implemented,
8254 // but doing so causes sizeable perf regression against the older version
8255 u_int gtec = gte_cycletab[source[i] & 0x3f];
32631e6a 8256 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? gtec/2 : 2;
fb407447 8257 }
cf95b4f0 8258 else if(i>1&&dops[i].itype==STORE&&dops[i-1].itype==STORE&&dops[i-2].itype==STORE&&!dops[i].bt)
5fdcbb5a 8259 {
8260 cc+=4;
8261 }
cf95b4f0 8262 else if(dops[i].itype==C2LS)
fb407447 8263 {
81dbbf4c 8264 // same as with C2OP
32631e6a 8265 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? 4 : 2;
fb407447 8266 }
8267#endif
57871462 8268 else
8269 {
8270 cc++;
8271 }
8272
cf95b4f0 8273 if(!dops[i].is_ds) {
57871462 8274 regs[i].dirty=current.dirty;
8275 regs[i].isconst=current.isconst;
40fca85b 8276 memcpy(constmap[i],current_constmap,sizeof(constmap[i]));
57871462 8277 }
8278 for(hr=0;hr<HOST_REGS;hr++) {
8279 if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
8280 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
8281 regs[i].wasconst&=~(1<<hr);
8282 }
8283 }
8284 }
8285 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
27727b63 8286 regs[i].waswritten=current.waswritten;
57871462 8287 }
9f51b4b9 8288
57871462 8289 /* Pass 4 - Cull unused host registers */
9f51b4b9 8290
57871462 8291 uint64_t nr=0;
9f51b4b9 8292
57871462 8293 for (i=slen-1;i>=0;i--)
8294 {
8295 int hr;
fe807a8a 8296 if(dops[i].is_jump)
57871462 8297 {
8298 if(ba[i]<start || ba[i]>=(start+slen*4))
8299 {
8300 // Branch out of this block, don't need anything
8301 nr=0;
8302 }
8303 else
8304 {
8305 // Internal branch
8306 // Need whatever matches the target
8307 nr=0;
8308 int t=(ba[i]-start)>>2;
8309 for(hr=0;hr<HOST_REGS;hr++)
8310 {
8311 if(regs[i].regmap_entry[hr]>=0) {
8312 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
8313 }
8314 }
8315 }
8316 // Conditional branch may need registers for following instructions
fe807a8a 8317 if (!dops[i].is_ujump)
57871462 8318 {
8319 if(i<slen-2) {
8320 nr|=needed_reg[i+2];
8321 for(hr=0;hr<HOST_REGS;hr++)
8322 {
8323 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
8324 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
8325 }
8326 }
8327 }
8328 // Don't need stuff which is overwritten
f5955059 8329 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
8330 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
57871462 8331 // Merge in delay slot
8332 for(hr=0;hr<HOST_REGS;hr++)
8333 {
fe807a8a 8334 if(dops[i+1].rt1&&dops[i+1].rt1==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8335 if(dops[i+1].rt2&&dops[i+1].rt2==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
cf95b4f0 8336 if(dops[i+1].rs1==regmap_pre[i][hr]) nr|=1<<hr;
8337 if(dops[i+1].rs2==regmap_pre[i][hr]) nr|=1<<hr;
8338 if(dops[i+1].rs1==regs[i].regmap_entry[hr]) nr|=1<<hr;
8339 if(dops[i+1].rs2==regs[i].regmap_entry[hr]) nr|=1<<hr;
37387d8b 8340 if(ram_offset && (dops[i+1].is_load || dops[i+1].is_store)) {
8341 if(regmap_pre[i][hr]==ROREG) nr|=1<<hr;
8342 if(regs[i].regmap_entry[hr]==ROREG) nr|=1<<hr;
8343 }
8344 if(dops[i+1].is_store) {
57871462 8345 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
8346 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
8347 }
8348 }
8349 }
cf95b4f0 8350 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
57871462 8351 {
8352 // SYSCALL instruction (software interrupt)
8353 nr=0;
8354 }
cf95b4f0 8355 else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
57871462 8356 {
8357 // ERET instruction (return from interrupt)
8358 nr=0;
8359 }
8360 else // Non-branch
8361 {
8362 if(i<slen-1) {
8363 for(hr=0;hr<HOST_REGS;hr++) {
8364 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
8365 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
8366 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
8367 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
8368 }
8369 }
8370 }
8371 for(hr=0;hr<HOST_REGS;hr++)
8372 {
8373 // Overwritten registers are not needed
cf95b4f0 8374 if(dops[i].rt1&&dops[i].rt1==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8375 if(dops[i].rt2&&dops[i].rt2==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
57871462 8376 if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8377 // Source registers are needed
cf95b4f0 8378 if(dops[i].rs1==regmap_pre[i][hr]) nr|=1<<hr;
8379 if(dops[i].rs2==regmap_pre[i][hr]) nr|=1<<hr;
8380 if(dops[i].rs1==regs[i].regmap_entry[hr]) nr|=1<<hr;
8381 if(dops[i].rs2==regs[i].regmap_entry[hr]) nr|=1<<hr;
37387d8b 8382 if(ram_offset && (dops[i].is_load || dops[i].is_store)) {
8383 if(regmap_pre[i][hr]==ROREG) nr|=1<<hr;
8384 if(regs[i].regmap_entry[hr]==ROREG) nr|=1<<hr;
8385 }
8386 if(dops[i].is_store) {
57871462 8387 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
8388 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
8389 }
8390 // Don't store a register immediately after writing it,
8391 // may prevent dual-issue.
8392 // But do so if this is a branch target, otherwise we
8393 // might have to load the register before the branch.
cf95b4f0 8394 if(i>0&&!dops[i].bt&&((regs[i].wasdirty>>hr)&1)) {
7c3a5182 8395 if((regmap_pre[i][hr]>0&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1))) {
cf95b4f0 8396 if(dops[i-1].rt1==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8397 if(dops[i-1].rt2==(regmap_pre[i][hr]&63)) nr|=1<<hr;
57871462 8398 }
7c3a5182 8399 if((regs[i].regmap_entry[hr]>0&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1))) {
cf95b4f0 8400 if(dops[i-1].rt1==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8401 if(dops[i-1].rt2==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
57871462 8402 }
8403 }
8404 }
8405 // Cycle count is needed at branches. Assume it is needed at the target too.
cf95b4f0 8406 if(i==0||dops[i].bt||dops[i].itype==CJUMP||dops[i].itype==SPAN) {
57871462 8407 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
8408 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
8409 }
8410 // Save it
8411 needed_reg[i]=nr;
9f51b4b9 8412
57871462 8413 // Deallocate unneeded registers
8414 for(hr=0;hr<HOST_REGS;hr++)
8415 {
8416 if(!((nr>>hr)&1)) {
8417 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
fe807a8a 8418 if(dops[i].is_jump)
57871462 8419 {
37387d8b 8420 int map1 = 0, map2 = 0, temp = 0; // or -1 ??
8421 if (dops[i+1].is_load || dops[i+1].is_store)
8422 map1 = ROREG;
8423 if (dops[i+1].is_store)
8424 map2 = INVCP;
8425 if(dops[i+1].itype==LOADLR || dops[i+1].itype==STORELR || dops[i+1].itype==C2LS)
8426 temp = FTEMP;
cf95b4f0 8427 if((regs[i].regmap[hr]&63)!=dops[i].rs1 && (regs[i].regmap[hr]&63)!=dops[i].rs2 &&
8428 (regs[i].regmap[hr]&63)!=dops[i].rt1 && (regs[i].regmap[hr]&63)!=dops[i].rt2 &&
8429 (regs[i].regmap[hr]&63)!=dops[i+1].rt1 && (regs[i].regmap[hr]&63)!=dops[i+1].rt2 &&
8430 regs[i].regmap[hr]!=dops[i+1].rs1 && regs[i].regmap[hr]!=dops[i+1].rs2 &&
57871462 8431 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
8432 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
8433 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
37387d8b 8434 regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2)
57871462 8435 {
8436 regs[i].regmap[hr]=-1;
8437 regs[i].isconst&=~(1<<hr);
cf95b4f0 8438 if((branch_regs[i].regmap[hr]&63)!=dops[i].rs1 && (branch_regs[i].regmap[hr]&63)!=dops[i].rs2 &&
8439 (branch_regs[i].regmap[hr]&63)!=dops[i].rt1 && (branch_regs[i].regmap[hr]&63)!=dops[i].rt2 &&
8440 (branch_regs[i].regmap[hr]&63)!=dops[i+1].rt1 && (branch_regs[i].regmap[hr]&63)!=dops[i+1].rt2 &&
8441 branch_regs[i].regmap[hr]!=dops[i+1].rs1 && branch_regs[i].regmap[hr]!=dops[i+1].rs2 &&
57871462 8442 (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
8443 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
8444 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
37387d8b 8445 branch_regs[i].regmap[hr]!=map1 && branch_regs[i].regmap[hr]!=map2)
57871462 8446 {
8447 branch_regs[i].regmap[hr]=-1;
8448 branch_regs[i].regmap_entry[hr]=-1;
fe807a8a 8449 if (!dops[i].is_ujump)
57871462 8450 {
fe807a8a 8451 if (i < slen-2) {
57871462 8452 regmap_pre[i+2][hr]=-1;
79c75f1b 8453 regs[i+2].wasconst&=~(1<<hr);
57871462 8454 }
8455 }
8456 }
8457 }
8458 }
8459 else
8460 {
8461 // Non-branch
8462 if(i>0)
8463 {
37387d8b 8464 int map1 = -1, map2 = -1, temp=-1;
8465 if (dops[i].is_load || dops[i].is_store)
8466 map1 = ROREG;
8467 if (dops[i].is_store)
8468 map2 = INVCP;
8469 if (dops[i].itype==LOADLR || dops[i].itype==STORELR || dops[i].itype==C2LS)
8470 temp = FTEMP;
cf95b4f0 8471 if((regs[i].regmap[hr]&63)!=dops[i].rt1 && (regs[i].regmap[hr]&63)!=dops[i].rt2 &&
8472 regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 &&
37387d8b 8473 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2 &&
4b1c7cd1 8474 //(dops[i].itype!=SPAN||regs[i].regmap[hr]!=CCREG)
8475 regs[i].regmap[hr] != CCREG)
57871462 8476 {
cf95b4f0 8477 if(i<slen-1&&!dops[i].is_ds) {
ad49de89 8478 assert(regs[i].regmap[hr]<64);
afec9d44 8479 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]>0)
57871462 8480 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
57871462 8481 {
c43b5311 8482 SysPrintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
57871462 8483 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
8484 }
8485 regmap_pre[i+1][hr]=-1;
8486 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
79c75f1b 8487 regs[i+1].wasconst&=~(1<<hr);
57871462 8488 }
8489 regs[i].regmap[hr]=-1;
8490 regs[i].isconst&=~(1<<hr);
8491 }
8492 }
8493 }
3968e69e 8494 } // if needed
8495 } // for hr
57871462 8496 }
9f51b4b9 8497
57871462 8498 /* Pass 5 - Pre-allocate registers */
9f51b4b9 8499
57871462 8500 // If a register is allocated during a loop, try to allocate it for the
8501 // entire loop, if possible. This avoids loading/storing registers
8502 // inside of the loop.
9f51b4b9 8503
57871462 8504 signed char f_regmap[HOST_REGS];
8505 clear_all_regs(f_regmap);
8506 for(i=0;i<slen-1;i++)
8507 {
cf95b4f0 8508 if(dops[i].itype==UJUMP||dops[i].itype==CJUMP||dops[i].itype==SJUMP)
57871462 8509 {
9f51b4b9 8510 if(ba[i]>=start && ba[i]<(start+i*4))
cf95b4f0 8511 if(dops[i+1].itype==NOP||dops[i+1].itype==MOV||dops[i+1].itype==ALU
8512 ||dops[i+1].itype==SHIFTIMM||dops[i+1].itype==IMM16||dops[i+1].itype==LOAD
8513 ||dops[i+1].itype==STORE||dops[i+1].itype==STORELR||dops[i+1].itype==C1LS
8514 ||dops[i+1].itype==SHIFT||dops[i+1].itype==COP1
8515 ||dops[i+1].itype==COP2||dops[i+1].itype==C2LS||dops[i+1].itype==C2OP)
57871462 8516 {
8517 int t=(ba[i]-start)>>2;
fe807a8a 8518 if(t > 0 && !dops[t-1].is_jump) // loop_preload can't handle jumps into delay slots
cf95b4f0 8519 if(t<2||(dops[t-2].itype!=UJUMP&&dops[t-2].itype!=RJUMP)||dops[t-2].rt1!=31) // call/ret assumes no registers allocated
57871462 8520 for(hr=0;hr<HOST_REGS;hr++)
8521 {
7c3a5182 8522 if(regs[i].regmap[hr]>=0) {
b372a952 8523 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8524 // dealloc old register
8525 int n;
8526 for(n=0;n<HOST_REGS;n++)
8527 {
8528 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8529 }
8530 // and alloc new one
8531 f_regmap[hr]=regs[i].regmap[hr];
8532 }
8533 }
7c3a5182 8534 if(branch_regs[i].regmap[hr]>=0) {
b372a952 8535 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
8536 // dealloc old register
8537 int n;
8538 for(n=0;n<HOST_REGS;n++)
8539 {
8540 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
8541 }
8542 // and alloc new one
8543 f_regmap[hr]=branch_regs[i].regmap[hr];
8544 }
8545 }
cf95b4f0 8546 if(dops[i].ooo) {
9f51b4b9 8547 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
e1190b87 8548 f_regmap[hr]=branch_regs[i].regmap[hr];
8549 }else{
9f51b4b9 8550 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
57871462 8551 f_regmap[hr]=branch_regs[i].regmap[hr];
8552 }
8553 // Avoid dirty->clean transition
e1190b87 8554 #ifdef DESTRUCTIVE_WRITEBACK
57871462 8555 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
e1190b87 8556 #endif
8557 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
8558 // case above, however it's always a good idea. We can't hoist the
8559 // load if the register was already allocated, so there's no point
8560 // wasting time analyzing most of these cases. It only "succeeds"
8561 // when the mapping was different and the load can be replaced with
8562 // a mov, which is of negligible benefit. So such cases are
8563 // skipped below.
57871462 8564 if(f_regmap[hr]>0) {
198df76f 8565 if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
57871462 8566 int r=f_regmap[hr];
8567 for(j=t;j<=i;j++)
8568 {
8569 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
8570 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
00fa9369 8571 assert(r < 64);
57871462 8572 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
8573 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
8574 int k;
8575 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
8576 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
8577 if(r>63) {
8578 if(get_reg(regs[i].regmap,r&63)<0) break;
8579 if(get_reg(branch_regs[i].regmap,r&63)<0) break;
8580 }
8581 k=i;
8582 while(k>1&&regs[k-1].regmap[hr]==-1) {
e1190b87 8583 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
8584 //printf("no free regs for store %x\n",start+(k-1)*4);
8585 break;
57871462 8586 }
57871462 8587 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
8588 //printf("no-match due to different register\n");
8589 break;
8590 }
fe807a8a 8591 if (dops[k-2].is_jump) {
57871462 8592 //printf("no-match due to branch\n");
8593 break;
8594 }
8595 // call/ret fast path assumes no registers allocated
cf95b4f0 8596 if(k>2&&(dops[k-3].itype==UJUMP||dops[k-3].itype==RJUMP)&&dops[k-3].rt1==31) {
57871462 8597 break;
8598 }
ad49de89 8599 assert(r < 64);
57871462 8600 k--;
8601 }
57871462 8602 if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
8603 //printf("Extend r%d, %x ->\n",hr,start+k*4);
8604 while(k<i) {
8605 regs[k].regmap_entry[hr]=f_regmap[hr];
8606 regs[k].regmap[hr]=f_regmap[hr];
8607 regmap_pre[k+1][hr]=f_regmap[hr];
8608 regs[k].wasdirty&=~(1<<hr);
8609 regs[k].dirty&=~(1<<hr);
8610 regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
8611 regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
8612 regs[k].wasconst&=~(1<<hr);
8613 regs[k].isconst&=~(1<<hr);
8614 k++;
8615 }
8616 }
8617 else {
8618 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
8619 break;
8620 }
8621 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
8622 if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
8623 //printf("OK fill %x (r%d)\n",start+i*4,hr);
8624 regs[i].regmap_entry[hr]=f_regmap[hr];
8625 regs[i].regmap[hr]=f_regmap[hr];
8626 regs[i].wasdirty&=~(1<<hr);
8627 regs[i].dirty&=~(1<<hr);
8628 regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
8629 regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
8630 regs[i].wasconst&=~(1<<hr);
8631 regs[i].isconst&=~(1<<hr);
8632 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
8633 branch_regs[i].wasdirty&=~(1<<hr);
8634 branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
8635 branch_regs[i].regmap[hr]=f_regmap[hr];
8636 branch_regs[i].dirty&=~(1<<hr);
8637 branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
8638 branch_regs[i].wasconst&=~(1<<hr);
8639 branch_regs[i].isconst&=~(1<<hr);
fe807a8a 8640 if (!dops[i].is_ujump) {
57871462 8641 regmap_pre[i+2][hr]=f_regmap[hr];
8642 regs[i+2].wasdirty&=~(1<<hr);
8643 regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
57871462 8644 }
8645 }
8646 }
8647 for(k=t;k<j;k++) {
e1190b87 8648 // Alloc register clean at beginning of loop,
8649 // but may dirty it in pass 6
57871462 8650 regs[k].regmap_entry[hr]=f_regmap[hr];
8651 regs[k].regmap[hr]=f_regmap[hr];
57871462 8652 regs[k].dirty&=~(1<<hr);
8653 regs[k].wasconst&=~(1<<hr);
8654 regs[k].isconst&=~(1<<hr);
fe807a8a 8655 if (dops[k].is_jump) {
e1190b87 8656 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
8657 branch_regs[k].regmap[hr]=f_regmap[hr];
8658 branch_regs[k].dirty&=~(1<<hr);
8659 branch_regs[k].wasconst&=~(1<<hr);
8660 branch_regs[k].isconst&=~(1<<hr);
fe807a8a 8661 if (!dops[k].is_ujump) {
e1190b87 8662 regmap_pre[k+2][hr]=f_regmap[hr];
8663 regs[k+2].wasdirty&=~(1<<hr);
e1190b87 8664 }
8665 }
8666 else
8667 {
8668 regmap_pre[k+1][hr]=f_regmap[hr];
8669 regs[k+1].wasdirty&=~(1<<hr);
8670 }
57871462 8671 }
8672 if(regs[j].regmap[hr]==f_regmap[hr])
8673 regs[j].regmap_entry[hr]=f_regmap[hr];
8674 break;
8675 }
8676 if(j==i) break;
8677 if(regs[j].regmap[hr]>=0)
8678 break;
8679 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
8680 //printf("no-match due to different register\n");
8681 break;
8682 }
fe807a8a 8683 if (dops[j].is_ujump)
e1190b87 8684 {
8685 // Stop on unconditional branch
8686 break;
8687 }
cf95b4f0 8688 if(dops[j].itype==CJUMP||dops[j].itype==SJUMP)
e1190b87 8689 {
cf95b4f0 8690 if(dops[j].ooo) {
9f51b4b9 8691 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
e1190b87 8692 break;
8693 }else{
9f51b4b9 8694 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
e1190b87 8695 break;
8696 }
8697 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
8698 //printf("no-match due to different register (branch)\n");
57871462 8699 break;
8700 }
8701 }
e1190b87 8702 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
8703 //printf("No free regs for store %x\n",start+j*4);
8704 break;
8705 }
ad49de89 8706 assert(f_regmap[hr]<64);
57871462 8707 }
8708 }
8709 }
8710 }
8711 }
8712 }else{
198df76f 8713 // Non branch or undetermined branch target
57871462 8714 for(hr=0;hr<HOST_REGS;hr++)
8715 {
8716 if(hr!=EXCLUDE_REG) {
7c3a5182 8717 if(regs[i].regmap[hr]>=0) {
b372a952 8718 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8719 // dealloc old register
8720 int n;
8721 for(n=0;n<HOST_REGS;n++)
8722 {
8723 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8724 }
8725 // and alloc new one
8726 f_regmap[hr]=regs[i].regmap[hr];
8727 }
8728 }
57871462 8729 }
8730 }
8731 // Try to restore cycle count at branch targets
cf95b4f0 8732 if(dops[i].bt) {
57871462 8733 for(j=i;j<slen-1;j++) {
8734 if(regs[j].regmap[HOST_CCREG]!=-1) break;
e1190b87 8735 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
8736 //printf("no free regs for store %x\n",start+j*4);
8737 break;
57871462 8738 }
57871462 8739 }
8740 if(regs[j].regmap[HOST_CCREG]==CCREG) {
8741 int k=i;
8742 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
8743 while(k<j) {
8744 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8745 regs[k].regmap[HOST_CCREG]=CCREG;
8746 regmap_pre[k+1][HOST_CCREG]=CCREG;
8747 regs[k+1].wasdirty|=1<<HOST_CCREG;
8748 regs[k].dirty|=1<<HOST_CCREG;
8749 regs[k].wasconst&=~(1<<HOST_CCREG);
8750 regs[k].isconst&=~(1<<HOST_CCREG);
8751 k++;
8752 }
9f51b4b9 8753 regs[j].regmap_entry[HOST_CCREG]=CCREG;
57871462 8754 }
8755 // Work backwards from the branch target
8756 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
8757 {
8758 //printf("Extend backwards\n");
8759 int k;
8760 k=i;
8761 while(regs[k-1].regmap[HOST_CCREG]==-1) {
e1190b87 8762 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
8763 //printf("no free regs for store %x\n",start+(k-1)*4);
8764 break;
57871462 8765 }
57871462 8766 k--;
8767 }
8768 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
8769 //printf("Extend CC, %x ->\n",start+k*4);
8770 while(k<=i) {
8771 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8772 regs[k].regmap[HOST_CCREG]=CCREG;
8773 regmap_pre[k+1][HOST_CCREG]=CCREG;
8774 regs[k+1].wasdirty|=1<<HOST_CCREG;
8775 regs[k].dirty|=1<<HOST_CCREG;
8776 regs[k].wasconst&=~(1<<HOST_CCREG);
8777 regs[k].isconst&=~(1<<HOST_CCREG);
8778 k++;
8779 }
8780 }
8781 else {
8782 //printf("Fail Extend CC, %x ->\n",start+k*4);
8783 }
8784 }
8785 }
cf95b4f0 8786 if(dops[i].itype!=STORE&&dops[i].itype!=STORELR&&dops[i].itype!=C1LS&&dops[i].itype!=SHIFT&&
8787 dops[i].itype!=NOP&&dops[i].itype!=MOV&&dops[i].itype!=ALU&&dops[i].itype!=SHIFTIMM&&
8788 dops[i].itype!=IMM16&&dops[i].itype!=LOAD&&dops[i].itype!=COP1)
57871462 8789 {
8790 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
8791 }
8792 }
8793 }
9f51b4b9 8794
57871462 8795 // This allocates registers (if possible) one instruction prior
8796 // to use, which can avoid a load-use penalty on certain CPUs.
8797 for(i=0;i<slen-1;i++)
8798 {
fe807a8a 8799 if (!i || !dops[i-1].is_jump)
57871462 8800 {
cf95b4f0 8801 if(!dops[i+1].bt)
57871462 8802 {
cf95b4f0 8803 if(dops[i].itype==ALU||dops[i].itype==MOV||dops[i].itype==LOAD||dops[i].itype==SHIFTIMM||dops[i].itype==IMM16
8804 ||((dops[i].itype==COP1||dops[i].itype==COP2)&&dops[i].opcode2<3))
57871462 8805 {
cf95b4f0 8806 if(dops[i+1].rs1) {
8807 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs1))>=0)
57871462 8808 {
8809 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8810 {
8811 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8812 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8813 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8814 regs[i].isconst&=~(1<<hr);
8815 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8816 constmap[i][hr]=constmap[i+1][hr];
8817 regs[i+1].wasdirty&=~(1<<hr);
8818 regs[i].dirty&=~(1<<hr);
8819 }
8820 }
8821 }
cf95b4f0 8822 if(dops[i+1].rs2) {
8823 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs2))>=0)
57871462 8824 {
8825 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8826 {
8827 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8828 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8829 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8830 regs[i].isconst&=~(1<<hr);
8831 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8832 constmap[i][hr]=constmap[i+1][hr];
8833 regs[i+1].wasdirty&=~(1<<hr);
8834 regs[i].dirty&=~(1<<hr);
8835 }
8836 }
8837 }
198df76f 8838 // Preload target address for load instruction (non-constant)
cf95b4f0 8839 if(dops[i+1].itype==LOAD&&dops[i+1].rs1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8840 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rt1))>=0)
57871462 8841 {
8842 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8843 {
cf95b4f0 8844 regs[i].regmap[hr]=dops[i+1].rs1;
8845 regmap_pre[i+1][hr]=dops[i+1].rs1;
8846 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
57871462 8847 regs[i].isconst&=~(1<<hr);
8848 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8849 constmap[i][hr]=constmap[i+1][hr];
8850 regs[i+1].wasdirty&=~(1<<hr);
8851 regs[i].dirty&=~(1<<hr);
8852 }
8853 }
8854 }
9f51b4b9 8855 // Load source into target register
cf95b4f0 8856 if(dops[i+1].lt1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8857 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rt1))>=0)
57871462 8858 {
8859 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8860 {
cf95b4f0 8861 regs[i].regmap[hr]=dops[i+1].rs1;
8862 regmap_pre[i+1][hr]=dops[i+1].rs1;
8863 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
57871462 8864 regs[i].isconst&=~(1<<hr);
8865 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8866 constmap[i][hr]=constmap[i+1][hr];
8867 regs[i+1].wasdirty&=~(1<<hr);
8868 regs[i].dirty&=~(1<<hr);
8869 }
8870 }
8871 }
198df76f 8872 // Address for store instruction (non-constant)
cf95b4f0 8873 if(dops[i+1].itype==STORE||dops[i+1].itype==STORELR
8874 ||(dops[i+1].opcode&0x3b)==0x39||(dops[i+1].opcode&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
8875 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
57871462 8876 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
8877 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
8878 else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
8879 assert(hr>=0);
8880 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8881 {
cf95b4f0 8882 regs[i].regmap[hr]=dops[i+1].rs1;
8883 regmap_pre[i+1][hr]=dops[i+1].rs1;
8884 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
57871462 8885 regs[i].isconst&=~(1<<hr);
8886 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8887 constmap[i][hr]=constmap[i+1][hr];
8888 regs[i+1].wasdirty&=~(1<<hr);
8889 regs[i].dirty&=~(1<<hr);
8890 }
8891 }
8892 }
cf95b4f0 8893 if(dops[i+1].itype==LOADLR||(dops[i+1].opcode&0x3b)==0x31||(dops[i+1].opcode&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
8894 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
57871462 8895 int nr;
8896 hr=get_reg(regs[i+1].regmap,FTEMP);
8897 assert(hr>=0);
8898 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8899 {
cf95b4f0 8900 regs[i].regmap[hr]=dops[i+1].rs1;
8901 regmap_pre[i+1][hr]=dops[i+1].rs1;
8902 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
57871462 8903 regs[i].isconst&=~(1<<hr);
8904 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8905 constmap[i][hr]=constmap[i+1][hr];
8906 regs[i+1].wasdirty&=~(1<<hr);
8907 regs[i].dirty&=~(1<<hr);
8908 }
8909 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
8910 {
8911 // move it to another register
8912 regs[i+1].regmap[hr]=-1;
8913 regmap_pre[i+2][hr]=-1;
8914 regs[i+1].regmap[nr]=FTEMP;
8915 regmap_pre[i+2][nr]=FTEMP;
cf95b4f0 8916 regs[i].regmap[nr]=dops[i+1].rs1;
8917 regmap_pre[i+1][nr]=dops[i+1].rs1;
8918 regs[i+1].regmap_entry[nr]=dops[i+1].rs1;
57871462 8919 regs[i].isconst&=~(1<<nr);
8920 regs[i+1].isconst&=~(1<<nr);
8921 regs[i].dirty&=~(1<<nr);
8922 regs[i+1].wasdirty&=~(1<<nr);
8923 regs[i+1].dirty&=~(1<<nr);
8924 regs[i+2].wasdirty&=~(1<<nr);
8925 }
8926 }
8927 }
cf95b4f0 8928 if(dops[i+1].itype==LOAD||dops[i+1].itype==LOADLR||dops[i+1].itype==STORE||dops[i+1].itype==STORELR/*||dops[i+1].itype==C1LS||||dops[i+1].itype==C2LS*/) {
8929 if(dops[i+1].itype==LOAD)
8930 hr=get_reg(regs[i+1].regmap,dops[i+1].rt1);
8931 if(dops[i+1].itype==LOADLR||(dops[i+1].opcode&0x3b)==0x31||(dops[i+1].opcode&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
57871462 8932 hr=get_reg(regs[i+1].regmap,FTEMP);
cf95b4f0 8933 if(dops[i+1].itype==STORE||dops[i+1].itype==STORELR||(dops[i+1].opcode&0x3b)==0x39||(dops[i+1].opcode&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
57871462 8934 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
8935 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
8936 }
8937 if(hr>=0&&regs[i].regmap[hr]<0) {
cf95b4f0 8938 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
57871462 8939 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
8940 regs[i].regmap[hr]=AGEN1+((i+1)&1);
8941 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
8942 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
8943 regs[i].isconst&=~(1<<hr);
8944 regs[i+1].wasdirty&=~(1<<hr);
8945 regs[i].dirty&=~(1<<hr);
8946 }
8947 }
8948 }
8949 }
8950 }
8951 }
8952 }
9f51b4b9 8953
57871462 8954 /* Pass 6 - Optimize clean/dirty state */
8955 clean_registers(0,slen-1,1);
9f51b4b9 8956
57871462 8957 /* Pass 7 - Identify 32-bit registers */
04fd948a 8958 for (i=slen-1;i>=0;i--)
8959 {
cf95b4f0 8960 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
04fd948a 8961 {
8962 // Conditional branch
8963 if((source[i]>>16)!=0x1000&&i<slen-2) {
8964 // Mark this address as a branch target since it may be called
8965 // upon return from interrupt
cf95b4f0 8966 dops[i+2].bt=1;
04fd948a 8967 }
8968 }
8969 }
57871462 8970
cf95b4f0 8971 if(dops[slen-1].itype==SPAN) {
8972 dops[slen-1].bt=1; // Mark as a branch target so instruction can restart after exception
57871462 8973 }
4600ba03 8974
8975#ifdef DISASM
57871462 8976 /* Debug/disassembly */
57871462 8977 for(i=0;i<slen;i++)
8978 {
8979 printf("U:");
8980 int r;
8981 for(r=1;r<=CCREG;r++) {
8982 if((unneeded_reg[i]>>r)&1) {
8983 if(r==HIREG) printf(" HI");
8984 else if(r==LOREG) printf(" LO");
8985 else printf(" r%d",r);
8986 }
8987 }
57871462 8988 printf("\n");
8989 #if defined(__i386__) || defined(__x86_64__)
8990 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
8991 #endif
8992 #ifdef __arm__
8993 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
8994 #endif
7c3a5182 8995 #if defined(__i386__) || defined(__x86_64__)
57871462 8996 printf("needs: ");
8997 if(needed_reg[i]&1) printf("eax ");
8998 if((needed_reg[i]>>1)&1) printf("ecx ");
8999 if((needed_reg[i]>>2)&1) printf("edx ");
9000 if((needed_reg[i]>>3)&1) printf("ebx ");
9001 if((needed_reg[i]>>5)&1) printf("ebp ");
9002 if((needed_reg[i]>>6)&1) printf("esi ");
9003 if((needed_reg[i]>>7)&1) printf("edi ");
57871462 9004 printf("\n");
57871462 9005 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
9006 printf("dirty: ");
9007 if(regs[i].wasdirty&1) printf("eax ");
9008 if((regs[i].wasdirty>>1)&1) printf("ecx ");
9009 if((regs[i].wasdirty>>2)&1) printf("edx ");
9010 if((regs[i].wasdirty>>3)&1) printf("ebx ");
9011 if((regs[i].wasdirty>>5)&1) printf("ebp ");
9012 if((regs[i].wasdirty>>6)&1) printf("esi ");
9013 if((regs[i].wasdirty>>7)&1) printf("edi ");
9014 #endif
9015 #ifdef __arm__
9016 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
9017 printf("dirty: ");
9018 if(regs[i].wasdirty&1) printf("r0 ");
9019 if((regs[i].wasdirty>>1)&1) printf("r1 ");
9020 if((regs[i].wasdirty>>2)&1) printf("r2 ");
9021 if((regs[i].wasdirty>>3)&1) printf("r3 ");
9022 if((regs[i].wasdirty>>4)&1) printf("r4 ");
9023 if((regs[i].wasdirty>>5)&1) printf("r5 ");
9024 if((regs[i].wasdirty>>6)&1) printf("r6 ");
9025 if((regs[i].wasdirty>>7)&1) printf("r7 ");
9026 if((regs[i].wasdirty>>8)&1) printf("r8 ");
9027 if((regs[i].wasdirty>>9)&1) printf("r9 ");
9028 if((regs[i].wasdirty>>10)&1) printf("r10 ");
9029 if((regs[i].wasdirty>>12)&1) printf("r12 ");
9030 #endif
9031 printf("\n");
9032 disassemble_inst(i);
9033 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
9034 #if defined(__i386__) || defined(__x86_64__)
9035 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
9036 if(regs[i].dirty&1) printf("eax ");
9037 if((regs[i].dirty>>1)&1) printf("ecx ");
9038 if((regs[i].dirty>>2)&1) printf("edx ");
9039 if((regs[i].dirty>>3)&1) printf("ebx ");
9040 if((regs[i].dirty>>5)&1) printf("ebp ");
9041 if((regs[i].dirty>>6)&1) printf("esi ");
9042 if((regs[i].dirty>>7)&1) printf("edi ");
9043 #endif
9044 #ifdef __arm__
9045 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
9046 if(regs[i].dirty&1) printf("r0 ");
9047 if((regs[i].dirty>>1)&1) printf("r1 ");
9048 if((regs[i].dirty>>2)&1) printf("r2 ");
9049 if((regs[i].dirty>>3)&1) printf("r3 ");
9050 if((regs[i].dirty>>4)&1) printf("r4 ");
9051 if((regs[i].dirty>>5)&1) printf("r5 ");
9052 if((regs[i].dirty>>6)&1) printf("r6 ");
9053 if((regs[i].dirty>>7)&1) printf("r7 ");
9054 if((regs[i].dirty>>8)&1) printf("r8 ");
9055 if((regs[i].dirty>>9)&1) printf("r9 ");
9056 if((regs[i].dirty>>10)&1) printf("r10 ");
9057 if((regs[i].dirty>>12)&1) printf("r12 ");
9058 #endif
9059 printf("\n");
9060 if(regs[i].isconst) {
9061 printf("constants: ");
9062 #if defined(__i386__) || defined(__x86_64__)
643aeae3 9063 if(regs[i].isconst&1) printf("eax=%x ",(u_int)constmap[i][0]);
9064 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(u_int)constmap[i][1]);
9065 if((regs[i].isconst>>2)&1) printf("edx=%x ",(u_int)constmap[i][2]);
9066 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(u_int)constmap[i][3]);
9067 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(u_int)constmap[i][5]);
9068 if((regs[i].isconst>>6)&1) printf("esi=%x ",(u_int)constmap[i][6]);
9069 if((regs[i].isconst>>7)&1) printf("edi=%x ",(u_int)constmap[i][7]);
57871462 9070 #endif
7c3a5182 9071 #if defined(__arm__) || defined(__aarch64__)
643aeae3 9072 int r;
9073 for (r = 0; r < ARRAY_SIZE(constmap[i]); r++)
9074 if ((regs[i].isconst >> r) & 1)
9075 printf(" r%d=%x", r, (u_int)constmap[i][r]);
57871462 9076 #endif
9077 printf("\n");
9078 }
fe807a8a 9079 if(dops[i].is_jump) {
57871462 9080 #if defined(__i386__) || defined(__x86_64__)
9081 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
9082 if(branch_regs[i].dirty&1) printf("eax ");
9083 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
9084 if((branch_regs[i].dirty>>2)&1) printf("edx ");
9085 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
9086 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
9087 if((branch_regs[i].dirty>>6)&1) printf("esi ");
9088 if((branch_regs[i].dirty>>7)&1) printf("edi ");
9089 #endif
9090 #ifdef __arm__
9091 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
9092 if(branch_regs[i].dirty&1) printf("r0 ");
9093 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
9094 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
9095 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
9096 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
9097 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
9098 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
9099 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
9100 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
9101 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
9102 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
9103 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
9104 #endif
57871462 9105 }
9106 }
4600ba03 9107#endif // DISASM
57871462 9108
9109 /* Pass 8 - Assembly */
9110 linkcount=0;stubcount=0;
9111 ds=0;is_delayslot=0;
57871462 9112 u_int dirty_pre=0;
d148d265 9113 void *beginning=start_block();
57871462 9114 if((u_int)addr&1) {
9115 ds=1;
9116 pagespan_ds();
9117 }
df4dc2b1 9118 void *instr_addr0_override = NULL;
9ad4d757 9119
9ad4d757 9120 if (start == 0x80030000) {
3968e69e 9121 // nasty hack for the fastbios thing
96186eba 9122 // override block entry to this code
df4dc2b1 9123 instr_addr0_override = out;
9ad4d757 9124 emit_movimm(start,0);
96186eba 9125 // abuse io address var as a flag that we
9126 // have already returned here once
643aeae3 9127 emit_readword(&address,1);
9128 emit_writeword(0,&pcaddr);
9129 emit_writeword(0,&address);
9ad4d757 9130 emit_cmp(0,1);
3968e69e 9131 #ifdef __aarch64__
9132 emit_jeq(out + 4*2);
2a014d73 9133 emit_far_jump(new_dyna_leave);
3968e69e 9134 #else
643aeae3 9135 emit_jne(new_dyna_leave);
3968e69e 9136 #endif
9ad4d757 9137 }
57871462 9138 for(i=0;i<slen;i++)
9139 {
9140 //if(ds) printf("ds: ");
4600ba03 9141 disassemble_inst(i);
57871462 9142 if(ds) {
9143 ds=0; // Skip delay slot
cf95b4f0 9144 if(dops[i].bt) assem_debug("OOPS - branch into delay slot\n");
df4dc2b1 9145 instr_addr[i] = NULL;
57871462 9146 } else {
ffb0b9e0 9147 speculate_register_values(i);
57871462 9148 #ifndef DESTRUCTIVE_WRITEBACK
fe807a8a 9149 if (i < 2 || !dops[i-2].is_ujump)
57871462 9150 {
ad49de89 9151 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,unneeded_reg[i]);
57871462 9152 }
fe807a8a 9153 if((dops[i].itype==CJUMP||dops[i].itype==SJUMP)) {
f776eb14 9154 dirty_pre=branch_regs[i].dirty;
9155 }else{
f776eb14 9156 dirty_pre=regs[i].dirty;
9157 }
57871462 9158 #endif
9159 // write back
fe807a8a 9160 if (i < 2 || !dops[i-2].is_ujump)
57871462 9161 {
ad49de89 9162 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,unneeded_reg[i]);
57871462 9163 loop_preload(regmap_pre[i],regs[i].regmap_entry);
9164 }
9165 // branch target entry point
df4dc2b1 9166 instr_addr[i] = out;
57871462 9167 assem_debug("<->\n");
2330734f 9168 drc_dbg_emit_do_cmp(i, ccadj[i]);
dd114d7d 9169
57871462 9170 // load regs
9171 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
ad49de89 9172 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty);
cf95b4f0 9173 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i].rs1,dops[i].rs2);
57871462 9174 address_generation(i,&regs[i],regs[i].regmap_entry);
ad49de89 9175 load_consts(regmap_pre[i],regs[i].regmap,i);
fe807a8a 9176 if(dops[i].is_jump)
57871462 9177 {
9178 // Load the delay slot registers if necessary
cf95b4f0 9179 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2&&(dops[i+1].rs1!=dops[i].rt1||dops[i].rt1==0))
9180 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9181 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2&&(dops[i+1].rs2!=dops[i].rt1||dops[i].rt1==0))
9182 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
37387d8b 9183 if (ram_offset && (dops[i+1].is_load || dops[i+1].is_store))
9184 load_regs(regs[i].regmap_entry,regs[i].regmap,ROREG,ROREG);
9185 if (dops[i+1].is_store)
ad49de89 9186 load_regs(regs[i].regmap_entry,regs[i].regmap,INVCP,INVCP);
57871462 9187 }
9188 else if(i+1<slen)
9189 {
9190 // Preload registers for following instruction
cf95b4f0 9191 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2)
9192 if(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs1!=dops[i].rt2)
9193 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9194 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2)
9195 if(dops[i+1].rs2!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt2)
9196 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
57871462 9197 }
9198 // TODO: if(is_ooo(i)) address_generation(i+1);
9a3ccfeb 9199 if (!dops[i].is_jump || dops[i].itype == CJUMP)
ad49de89 9200 load_regs(regs[i].regmap_entry,regs[i].regmap,CCREG,CCREG);
37387d8b 9201 if (ram_offset && (dops[i].is_load || dops[i].is_store))
9202 load_regs(regs[i].regmap_entry,regs[i].regmap,ROREG,ROREG);
9203 if (dops[i].is_store)
ad49de89 9204 load_regs(regs[i].regmap_entry,regs[i].regmap,INVCP,INVCP);
2330734f 9205
9206 ds = assemble(i, &regs[i], ccadj[i]);
9207
fe807a8a 9208 if (dops[i].is_ujump)
57871462 9209 literal_pool(1024);
9210 else
9211 literal_pool_jumpover(256);
9212 }
9213 }
3d680478 9214
9215 assert(slen > 0);
cf95b4f0 9216 if (slen > 0 && dops[slen-1].itype == INTCALL) {
3d680478 9217 // no ending needed for this block since INTCALL never returns
9218 }
57871462 9219 // If the block did not end with an unconditional branch,
9220 // add a jump to the next instruction.
3d680478 9221 else if (i > 1) {
fe807a8a 9222 if (!dops[i-2].is_ujump && dops[i-1].itype != SPAN) {
9223 assert(!dops[i-1].is_jump);
57871462 9224 assert(i==slen);
cf95b4f0 9225 if(dops[i-2].itype!=CJUMP&&dops[i-2].itype!=SJUMP) {
ad49de89 9226 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
57871462 9227 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9228 emit_loadreg(CCREG,HOST_CCREG);
2330734f 9229 emit_addimm(HOST_CCREG, ccadj[i-1] + CLOCK_ADJUST(1), HOST_CCREG);
57871462 9230 }
fe807a8a 9231 else
57871462 9232 {
ad49de89 9233 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].dirty,start+i*4);
57871462 9234 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
9235 }
643aeae3 9236 add_to_linker(out,start+i*4,0);
57871462 9237 emit_jmp(0);
9238 }
9239 }
9240 else
9241 {
9242 assert(i>0);
fe807a8a 9243 assert(!dops[i-1].is_jump);
ad49de89 9244 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
57871462 9245 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9246 emit_loadreg(CCREG,HOST_CCREG);
2330734f 9247 emit_addimm(HOST_CCREG, ccadj[i-1] + CLOCK_ADJUST(1), HOST_CCREG);
643aeae3 9248 add_to_linker(out,start+i*4,0);
57871462 9249 emit_jmp(0);
9250 }
9251
9252 // TODO: delay slot stubs?
9253 // Stubs
9254 for(i=0;i<stubcount;i++)
9255 {
b14b6a8f 9256 switch(stubs[i].type)
57871462 9257 {
9258 case LOADB_STUB:
9259 case LOADH_STUB:
9260 case LOADW_STUB:
9261 case LOADD_STUB:
9262 case LOADBU_STUB:
9263 case LOADHU_STUB:
9264 do_readstub(i);break;
9265 case STOREB_STUB:
9266 case STOREH_STUB:
9267 case STOREW_STUB:
9268 case STORED_STUB:
9269 do_writestub(i);break;
9270 case CC_STUB:
9271 do_ccstub(i);break;
9272 case INVCODE_STUB:
9273 do_invstub(i);break;
9274 case FP_STUB:
9275 do_cop1stub(i);break;
9276 case STORELR_STUB:
9277 do_unalignedwritestub(i);break;
9278 }
9279 }
9280
9ad4d757 9281 if (instr_addr0_override)
9282 instr_addr[0] = instr_addr0_override;
9283
57871462 9284 /* Pass 9 - Linker */
9285 for(i=0;i<linkcount;i++)
9286 {
643aeae3 9287 assem_debug("%p -> %8x\n",link_addr[i].addr,link_addr[i].target);
57871462 9288 literal_pool(64);
643aeae3 9289 if (!link_addr[i].ext)
57871462 9290 {
643aeae3 9291 void *stub = out;
9292 void *addr = check_addr(link_addr[i].target);
9293 emit_extjump(link_addr[i].addr, link_addr[i].target);
9294 if (addr) {
9295 set_jump_target(link_addr[i].addr, addr);
3d680478 9296 add_jump_out(link_addr[i].target,stub);
57871462 9297 }
643aeae3 9298 else
9299 set_jump_target(link_addr[i].addr, stub);
57871462 9300 }
9301 else
9302 {
9303 // Internal branch
643aeae3 9304 int target=(link_addr[i].target-start)>>2;
57871462 9305 assert(target>=0&&target<slen);
9306 assert(instr_addr[target]);
9307 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
643aeae3 9308 //set_jump_target_fillslot(link_addr[i].addr,instr_addr[target],link_addr[i].ext>>1);
57871462 9309 //#else
643aeae3 9310 set_jump_target(link_addr[i].addr, instr_addr[target]);
57871462 9311 //#endif
9312 }
9313 }
3d680478 9314
9315 u_int source_len = slen*4;
cf95b4f0 9316 if (dops[slen-1].itype == INTCALL && source_len > 4)
3d680478 9317 // no need to treat the last instruction as compiled
9318 // as interpreter fully handles it
9319 source_len -= 4;
9320
9321 if ((u_char *)copy + source_len > (u_char *)shadow + sizeof(shadow))
9322 copy = shadow;
9323
57871462 9324 // External Branch Targets (jump_in)
57871462 9325 for(i=0;i<slen;i++)
9326 {
cf95b4f0 9327 if(dops[i].bt||i==0)
57871462 9328 {
9329 if(instr_addr[i]) // TODO - delay slots (=null)
9330 {
9331 u_int vaddr=start+i*4;
94d23bb9 9332 u_int page=get_page(vaddr);
9333 u_int vpage=get_vpage(vaddr);
57871462 9334 literal_pool(256);
57871462 9335 {
df4dc2b1 9336 assem_debug("%p (%d) <- %8x\n",instr_addr[i],i,start+i*4);
57871462 9337 assem_debug("jump_in: %x\n",start+i*4);
df4dc2b1 9338 ll_add(jump_dirty+vpage,vaddr,out);
3d680478 9339 void *entry_point = do_dirty_stub(i, source_len);
df4dc2b1 9340 ll_add_flags(jump_in+page,vaddr,state_rflags,entry_point);
57871462 9341 // If there was an existing entry in the hash table,
9342 // replace it with the new address.
9343 // Don't add new entries. We'll insert the
9344 // ones that actually get used in check_addr().
df4dc2b1 9345 struct ht_entry *ht_bin = hash_table_get(vaddr);
9346 if (ht_bin->vaddr[0] == vaddr)
9347 ht_bin->tcaddr[0] = entry_point;
9348 if (ht_bin->vaddr[1] == vaddr)
9349 ht_bin->tcaddr[1] = entry_point;
57871462 9350 }
57871462 9351 }
9352 }
9353 }
9354 // Write out the literal pool if necessary
9355 literal_pool(0);
9356 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
9357 // Align code
9358 if(((u_int)out)&7) emit_addnop(13);
9359 #endif
01d26796 9360 assert(out - (u_char *)beginning < MAX_OUTPUT_BLOCK_SIZE);
643aeae3 9361 //printf("shadow buffer: %p-%p\n",copy,(u_char *)copy+slen*4);
3d680478 9362 memcpy(copy, source, source_len);
9363 copy += source_len;
9f51b4b9 9364
d148d265 9365 end_block(beginning);
9f51b4b9 9366
57871462 9367 // If we're within 256K of the end of the buffer,
9368 // start over from the beginning. (Is 256K enough?)
2a014d73 9369 if (out > ndrc->translation_cache + sizeof(ndrc->translation_cache) - MAX_OUTPUT_BLOCK_SIZE)
9370 out = ndrc->translation_cache;
9f51b4b9 9371
57871462 9372 // Trap writes to any of the pages we compiled
9373 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
9374 invalid_code[i]=0;
57871462 9375 }
9be4ba64 9376 inv_code_start=inv_code_end=~0;
71e490c5 9377
b96d3df7 9378 // for PCSX we need to mark all mirrors too
b12c9fb8 9379 if(get_page(start)<(RAM_SIZE>>12))
9380 for(i=start>>12;i<=(start+slen*4)>>12;i++)
b96d3df7 9381 invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]=
9382 invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]=
9383 invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0;
9f51b4b9 9384
57871462 9385 /* Pass 10 - Free memory by expiring oldest blocks */
9f51b4b9 9386
2a014d73 9387 int end=(((out-ndrc->translation_cache)>>(TARGET_SIZE_2-16))+16384)&65535;
57871462 9388 while(expirep!=end)
9389 {
9390 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
943f42f3 9391 uintptr_t base_offs = ((uintptr_t)(expirep >> 13) << shift); // Base offset of this block
9392 uintptr_t base_offs_s = base_offs >> shift;
57871462 9393 inv_debug("EXP: Phase %d\n",expirep);
9394 switch((expirep>>11)&3)
9395 {
9396 case 0:
9397 // Clear jump_in and jump_dirty
943f42f3 9398 ll_remove_matching_addrs(jump_in+(expirep&2047),base_offs_s,shift);
9399 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base_offs_s,shift);
9400 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base_offs_s,shift);
9401 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base_offs_s,shift);
57871462 9402 break;
9403 case 1:
9404 // Clear pointers
943f42f3 9405 ll_kill_pointers(jump_out[expirep&2047],base_offs_s,shift);
9406 ll_kill_pointers(jump_out[(expirep&2047)+2048],base_offs_s,shift);
57871462 9407 break;
9408 case 2:
9409 // Clear hash table
9410 for(i=0;i<32;i++) {
df4dc2b1 9411 struct ht_entry *ht_bin = &hash_table[((expirep&2047)<<5)+i];
943f42f3 9412 uintptr_t o1 = (u_char *)ht_bin->tcaddr[1] - ndrc->translation_cache;
9413 uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
9414 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s) {
df4dc2b1 9415 inv_debug("EXP: Remove hash %x -> %p\n",ht_bin->vaddr[1],ht_bin->tcaddr[1]);
9416 ht_bin->vaddr[1] = -1;
9417 ht_bin->tcaddr[1] = NULL;
9418 }
943f42f3 9419 o1 = (u_char *)ht_bin->tcaddr[0] - ndrc->translation_cache;
9420 o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
9421 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s) {
df4dc2b1 9422 inv_debug("EXP: Remove hash %x -> %p\n",ht_bin->vaddr[0],ht_bin->tcaddr[0]);
9423 ht_bin->vaddr[0] = ht_bin->vaddr[1];
9424 ht_bin->tcaddr[0] = ht_bin->tcaddr[1];
9425 ht_bin->vaddr[1] = -1;
9426 ht_bin->tcaddr[1] = NULL;
57871462 9427 }
9428 }
9429 break;
9430 case 3:
9431 // Clear jump_out
9f51b4b9 9432 if((expirep&2047)==0)
dd3a91a1 9433 do_clear_cache();
943f42f3 9434 ll_remove_matching_addrs(jump_out+(expirep&2047),base_offs_s,shift);
9435 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base_offs_s,shift);
57871462 9436 break;
9437 }
9438 expirep=(expirep+1)&65535;
9439 }
37387d8b 9440#ifdef ASSEM_PRINT
9441 fflush(stdout);
9442#endif
57871462 9443 return 0;
9444}
b9b61529 9445
9446// vim:shiftwidth=2:expandtab
ARM optimized PCSX fork