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drc: do modification check in smaller than page granularity
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
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57871462 1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
20d507ba 3 * Copyright (C) 2009-2011 Ari64 *
57871462 4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21#include <stdlib.h>
22#include <stdint.h> //include for uint64_t
23#include <assert.h>
24
3d624f89 25#include "emu_if.h" //emulator interface
57871462 26
27#include <sys/mman.h>
28
29#ifdef __i386__
30#include "assem_x86.h"
31#endif
32#ifdef __x86_64__
33#include "assem_x64.h"
34#endif
35#ifdef __arm__
36#include "assem_arm.h"
37#endif
38
39#define MAXBLOCK 4096
40#define MAX_OUTPUT_BLOCK_SIZE 262144
41#define CLOCK_DIVIDER 2
42
43struct regstat
44{
45 signed char regmap_entry[HOST_REGS];
46 signed char regmap[HOST_REGS];
47 uint64_t was32;
48 uint64_t is32;
49 uint64_t wasdirty;
50 uint64_t dirty;
51 uint64_t u;
52 uint64_t uu;
53 u_int wasconst;
54 u_int isconst;
55 uint64_t constmap[HOST_REGS];
56};
57
58struct ll_entry
59{
60 u_int vaddr;
61 u_int reg32;
62 void *addr;
63 struct ll_entry *next;
64};
65
66 u_int start;
67 u_int *source;
68 u_int pagelimit;
69 char insn[MAXBLOCK][10];
70 u_char itype[MAXBLOCK];
71 u_char opcode[MAXBLOCK];
72 u_char opcode2[MAXBLOCK];
73 u_char bt[MAXBLOCK];
74 u_char rs1[MAXBLOCK];
75 u_char rs2[MAXBLOCK];
76 u_char rt1[MAXBLOCK];
77 u_char rt2[MAXBLOCK];
78 u_char us1[MAXBLOCK];
79 u_char us2[MAXBLOCK];
80 u_char dep1[MAXBLOCK];
81 u_char dep2[MAXBLOCK];
82 u_char lt1[MAXBLOCK];
83 int imm[MAXBLOCK];
84 u_int ba[MAXBLOCK];
85 char likely[MAXBLOCK];
86 char is_ds[MAXBLOCK];
e1190b87 87 char ooo[MAXBLOCK];
57871462 88 uint64_t unneeded_reg[MAXBLOCK];
89 uint64_t unneeded_reg_upper[MAXBLOCK];
90 uint64_t branch_unneeded_reg[MAXBLOCK];
91 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
92 uint64_t p32[MAXBLOCK];
93 uint64_t pr32[MAXBLOCK];
94 signed char regmap_pre[MAXBLOCK][HOST_REGS];
95 signed char regmap[MAXBLOCK][HOST_REGS];
96 signed char regmap_entry[MAXBLOCK][HOST_REGS];
97 uint64_t constmap[MAXBLOCK][HOST_REGS];
57871462 98 struct regstat regs[MAXBLOCK];
99 struct regstat branch_regs[MAXBLOCK];
e1190b87 100 signed char minimum_free_regs[MAXBLOCK];
57871462 101 u_int needed_reg[MAXBLOCK];
102 uint64_t requires_32bit[MAXBLOCK];
103 u_int wont_dirty[MAXBLOCK];
104 u_int will_dirty[MAXBLOCK];
105 int ccadj[MAXBLOCK];
106 int slen;
107 u_int instr_addr[MAXBLOCK];
108 u_int link_addr[MAXBLOCK][3];
109 int linkcount;
110 u_int stubs[MAXBLOCK*3][8];
111 int stubcount;
112 u_int literals[1024][2];
113 int literalcount;
114 int is_delayslot;
115 int cop1_usable;
116 u_char *out;
117 struct ll_entry *jump_in[4096];
118 struct ll_entry *jump_out[4096];
119 struct ll_entry *jump_dirty[4096];
120 u_int hash_table[65536][4] __attribute__((aligned(16)));
121 char shadow[1048576] __attribute__((aligned(16)));
122 void *copy;
123 int expirep;
af4ee1fe 124#ifndef PCSX
57871462 125 u_int using_tlb;
af4ee1fe 126#else
127 static const u_int using_tlb=0;
128#endif
dadf55f2 129 static u_int sp_in_mirror;
57871462 130 u_int stop_after_jal;
131 extern u_char restore_candidate[512];
132 extern int cycle_count;
133
134 /* registers that may be allocated */
135 /* 1-31 gpr */
136#define HIREG 32 // hi
137#define LOREG 33 // lo
138#define FSREG 34 // FPU status (FCSR)
139#define CSREG 35 // Coprocessor status
140#define CCREG 36 // Cycle count
141#define INVCP 37 // Pointer to invalid_code
619e5ded 142#define MMREG 38 // Pointer to memory_map
143#define ROREG 39 // ram offset (if rdram!=0x80000000)
144#define TEMPREG 40
145#define FTEMP 40 // FPU temporary register
146#define PTEMP 41 // Prefetch temporary register
147#define TLREG 42 // TLB mapping offset
148#define RHASH 43 // Return address hash
149#define RHTBL 44 // Return address hash table address
150#define RTEMP 45 // JR/JALR address register
151#define MAXREG 45
152#define AGEN1 46 // Address generation temporary register
153#define AGEN2 47 // Address generation temporary register
154#define MGEN1 48 // Maptable address generation temporary register
155#define MGEN2 49 // Maptable address generation temporary register
156#define BTREG 50 // Branch target temporary register
57871462 157
158 /* instruction types */
159#define NOP 0 // No operation
160#define LOAD 1 // Load
161#define STORE 2 // Store
162#define LOADLR 3 // Unaligned load
163#define STORELR 4 // Unaligned store
164#define MOV 5 // Move
165#define ALU 6 // Arithmetic/logic
166#define MULTDIV 7 // Multiply/divide
167#define SHIFT 8 // Shift by register
168#define SHIFTIMM 9// Shift by immediate
169#define IMM16 10 // 16-bit immediate
170#define RJUMP 11 // Unconditional jump to register
171#define UJUMP 12 // Unconditional jump
172#define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
173#define SJUMP 14 // Conditional branch (regimm format)
174#define COP0 15 // Coprocessor 0
175#define COP1 16 // Coprocessor 1
176#define C1LS 17 // Coprocessor 1 load/store
177#define FJUMP 18 // Conditional branch (floating point)
178#define FLOAT 19 // Floating point unit
179#define FCONV 20 // Convert integer to float
180#define FCOMP 21 // Floating point compare (sets FSREG)
181#define SYSCALL 22// SYSCALL
182#define OTHER 23 // Other
183#define SPAN 24 // Branch/delay slot spans 2 pages
184#define NI 25 // Not implemented
7139f3c8 185#define HLECALL 26// PCSX fake opcodes for HLE
b9b61529 186#define COP2 27 // Coprocessor 2 move
187#define C2LS 28 // Coprocessor 2 load/store
188#define C2OP 29 // Coprocessor 2 operation
1e973cb0 189#define INTCALL 30// Call interpreter to handle rare corner cases
57871462 190
191 /* stubs */
192#define CC_STUB 1
193#define FP_STUB 2
194#define LOADB_STUB 3
195#define LOADH_STUB 4
196#define LOADW_STUB 5
197#define LOADD_STUB 6
198#define LOADBU_STUB 7
199#define LOADHU_STUB 8
200#define STOREB_STUB 9
201#define STOREH_STUB 10
202#define STOREW_STUB 11
203#define STORED_STUB 12
204#define STORELR_STUB 13
205#define INVCODE_STUB 14
206
207 /* branch codes */
208#define TAKEN 1
209#define NOTTAKEN 2
210#define NULLDS 3
211
212// asm linkage
213int new_recompile_block(int addr);
214void *get_addr_ht(u_int vaddr);
215void invalidate_block(u_int block);
216void invalidate_addr(u_int addr);
217void remove_hash(int vaddr);
218void jump_vaddr();
219void dyna_linker();
220void dyna_linker_ds();
221void verify_code();
222void verify_code_vm();
223void verify_code_ds();
224void cc_interrupt();
225void fp_exception();
226void fp_exception_ds();
227void jump_syscall();
7139f3c8 228void jump_syscall_hle();
57871462 229void jump_eret();
7139f3c8 230void jump_hlecall();
1e973cb0 231void jump_intcall();
7139f3c8 232void new_dyna_leave();
57871462 233
234// TLB
235void TLBWI_new();
236void TLBWR_new();
237void read_nomem_new();
238void read_nomemb_new();
239void read_nomemh_new();
240void read_nomemd_new();
241void write_nomem_new();
242void write_nomemb_new();
243void write_nomemh_new();
244void write_nomemd_new();
245void write_rdram_new();
246void write_rdramb_new();
247void write_rdramh_new();
248void write_rdramd_new();
249extern u_int memory_map[1048576];
250
251// Needed by assembler
252void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
253void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
254void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
255void load_all_regs(signed char i_regmap[]);
256void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
257void load_regs_entry(int t);
258void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
259
260int tracedebug=0;
261
262//#define DEBUG_CYCLE_COUNT 1
263
264void nullf() {}
265//#define assem_debug printf
266//#define inv_debug printf
267#define assem_debug nullf
268#define inv_debug nullf
269
94d23bb9 270static void tlb_hacks()
57871462 271{
94d23bb9 272#ifndef DISABLE_TLB
57871462 273 // Goldeneye hack
274 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
275 {
276 u_int addr;
277 int n;
278 switch (ROM_HEADER->Country_code&0xFF)
279 {
280 case 0x45: // U
281 addr=0x34b30;
282 break;
283 case 0x4A: // J
284 addr=0x34b70;
285 break;
286 case 0x50: // E
287 addr=0x329f0;
288 break;
289 default:
290 // Unknown country code
291 addr=0;
292 break;
293 }
294 u_int rom_addr=(u_int)rom;
295 #ifdef ROM_COPY
296 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
297 // in the lower 4G of memory to use this hack. Copy it if necessary.
298 if((void *)rom>(void *)0xffffffff) {
299 munmap(ROM_COPY, 67108864);
300 if(mmap(ROM_COPY, 12582912,
301 PROT_READ | PROT_WRITE,
302 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
303 -1, 0) <= 0) {printf("mmap() failed\n");}
304 memcpy(ROM_COPY,rom,12582912);
305 rom_addr=(u_int)ROM_COPY;
306 }
307 #endif
308 if(addr) {
309 for(n=0x7F000;n<0x80000;n++) {
310 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
311 }
312 }
313 }
94d23bb9 314#endif
57871462 315}
316
94d23bb9 317static u_int get_page(u_int vaddr)
57871462 318{
0ce47d46 319#ifndef PCSX
57871462 320 u_int page=(vaddr^0x80000000)>>12;
0ce47d46 321#else
322 u_int page=vaddr&~0xe0000000;
323 if (page < 0x1000000)
324 page &= ~0x0e00000; // RAM mirrors
325 page>>=12;
326#endif
94d23bb9 327#ifndef DISABLE_TLB
57871462 328 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
94d23bb9 329#endif
57871462 330 if(page>2048) page=2048+(page&2047);
94d23bb9 331 return page;
332}
333
334static u_int get_vpage(u_int vaddr)
335{
336 u_int vpage=(vaddr^0x80000000)>>12;
337#ifndef DISABLE_TLB
57871462 338 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
94d23bb9 339#endif
57871462 340 if(vpage>2048) vpage=2048+(vpage&2047);
94d23bb9 341 return vpage;
342}
343
344// Get address from virtual address
345// This is called from the recompiled JR/JALR instructions
346void *get_addr(u_int vaddr)
347{
348 u_int page=get_page(vaddr);
349 u_int vpage=get_vpage(vaddr);
57871462 350 struct ll_entry *head;
351 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
352 head=jump_in[page];
353 while(head!=NULL) {
354 if(head->vaddr==vaddr&&head->reg32==0) {
355 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
356 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
357 ht_bin[3]=ht_bin[1];
358 ht_bin[2]=ht_bin[0];
359 ht_bin[1]=(int)head->addr;
360 ht_bin[0]=vaddr;
361 return head->addr;
362 }
363 head=head->next;
364 }
365 head=jump_dirty[vpage];
366 while(head!=NULL) {
367 if(head->vaddr==vaddr&&head->reg32==0) {
368 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
369 // Don't restore blocks which are about to expire from the cache
370 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
371 if(verify_dirty(head->addr)) {
372 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
373 invalid_code[vaddr>>12]=0;
9be4ba64 374 inv_code_start=inv_code_end=~0;
57871462 375 memory_map[vaddr>>12]|=0x40000000;
376 if(vpage<2048) {
94d23bb9 377#ifndef DISABLE_TLB
57871462 378 if(tlb_LUT_r[vaddr>>12]) {
379 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
380 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
381 }
94d23bb9 382#endif
57871462 383 restore_candidate[vpage>>3]|=1<<(vpage&7);
384 }
385 else restore_candidate[page>>3]|=1<<(page&7);
386 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
387 if(ht_bin[0]==vaddr) {
388 ht_bin[1]=(int)head->addr; // Replace existing entry
389 }
390 else
391 {
392 ht_bin[3]=ht_bin[1];
393 ht_bin[2]=ht_bin[0];
394 ht_bin[1]=(int)head->addr;
395 ht_bin[0]=vaddr;
396 }
397 return head->addr;
398 }
399 }
400 head=head->next;
401 }
402 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
403 int r=new_recompile_block(vaddr);
404 if(r==0) return get_addr(vaddr);
405 // Execute in unmapped page, generate pagefault execption
406 Status|=2;
407 Cause=(vaddr<<31)|0x8;
408 EPC=(vaddr&1)?vaddr-5:vaddr;
409 BadVAddr=(vaddr&~1);
410 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
411 EntryHi=BadVAddr&0xFFFFE000;
412 return get_addr_ht(0x80000000);
413}
414// Look up address in hash table first
415void *get_addr_ht(u_int vaddr)
416{
417 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
418 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
419 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
420 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
421 return get_addr(vaddr);
422}
423
424void *get_addr_32(u_int vaddr,u_int flags)
425{
7139f3c8 426#ifdef FORCE32
427 return get_addr(vaddr);
560e4a12 428#else
57871462 429 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
430 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
431 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
432 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
94d23bb9 433 u_int page=get_page(vaddr);
434 u_int vpage=get_vpage(vaddr);
57871462 435 struct ll_entry *head;
436 head=jump_in[page];
437 while(head!=NULL) {
438 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
439 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
440 if(head->reg32==0) {
441 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
442 if(ht_bin[0]==-1) {
443 ht_bin[1]=(int)head->addr;
444 ht_bin[0]=vaddr;
445 }else if(ht_bin[2]==-1) {
446 ht_bin[3]=(int)head->addr;
447 ht_bin[2]=vaddr;
448 }
449 //ht_bin[3]=ht_bin[1];
450 //ht_bin[2]=ht_bin[0];
451 //ht_bin[1]=(int)head->addr;
452 //ht_bin[0]=vaddr;
453 }
454 return head->addr;
455 }
456 head=head->next;
457 }
458 head=jump_dirty[vpage];
459 while(head!=NULL) {
460 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
461 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
462 // Don't restore blocks which are about to expire from the cache
463 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
464 if(verify_dirty(head->addr)) {
465 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
466 invalid_code[vaddr>>12]=0;
9be4ba64 467 inv_code_start=inv_code_end=~0;
57871462 468 memory_map[vaddr>>12]|=0x40000000;
469 if(vpage<2048) {
94d23bb9 470#ifndef DISABLE_TLB
57871462 471 if(tlb_LUT_r[vaddr>>12]) {
472 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
473 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
474 }
94d23bb9 475#endif
57871462 476 restore_candidate[vpage>>3]|=1<<(vpage&7);
477 }
478 else restore_candidate[page>>3]|=1<<(page&7);
479 if(head->reg32==0) {
480 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
481 if(ht_bin[0]==-1) {
482 ht_bin[1]=(int)head->addr;
483 ht_bin[0]=vaddr;
484 }else if(ht_bin[2]==-1) {
485 ht_bin[3]=(int)head->addr;
486 ht_bin[2]=vaddr;
487 }
488 //ht_bin[3]=ht_bin[1];
489 //ht_bin[2]=ht_bin[0];
490 //ht_bin[1]=(int)head->addr;
491 //ht_bin[0]=vaddr;
492 }
493 return head->addr;
494 }
495 }
496 head=head->next;
497 }
498 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
499 int r=new_recompile_block(vaddr);
500 if(r==0) return get_addr(vaddr);
501 // Execute in unmapped page, generate pagefault execption
502 Status|=2;
503 Cause=(vaddr<<31)|0x8;
504 EPC=(vaddr&1)?vaddr-5:vaddr;
505 BadVAddr=(vaddr&~1);
506 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
507 EntryHi=BadVAddr&0xFFFFE000;
508 return get_addr_ht(0x80000000);
560e4a12 509#endif
57871462 510}
511
512void clear_all_regs(signed char regmap[])
513{
514 int hr;
515 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
516}
517
518signed char get_reg(signed char regmap[],int r)
519{
520 int hr;
521 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
522 return -1;
523}
524
525// Find a register that is available for two consecutive cycles
526signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
527{
528 int hr;
529 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
530 return -1;
531}
532
533int count_free_regs(signed char regmap[])
534{
535 int count=0;
536 int hr;
537 for(hr=0;hr<HOST_REGS;hr++)
538 {
539 if(hr!=EXCLUDE_REG) {
540 if(regmap[hr]<0) count++;
541 }
542 }
543 return count;
544}
545
546void dirty_reg(struct regstat *cur,signed char reg)
547{
548 int hr;
549 if(!reg) return;
550 for (hr=0;hr<HOST_REGS;hr++) {
551 if((cur->regmap[hr]&63)==reg) {
552 cur->dirty|=1<<hr;
553 }
554 }
555}
556
557// If we dirty the lower half of a 64 bit register which is now being
558// sign-extended, we need to dump the upper half.
559// Note: Do this only after completion of the instruction, because
560// some instructions may need to read the full 64-bit value even if
561// overwriting it (eg SLTI, DSRA32).
562static void flush_dirty_uppers(struct regstat *cur)
563{
564 int hr,reg;
565 for (hr=0;hr<HOST_REGS;hr++) {
566 if((cur->dirty>>hr)&1) {
567 reg=cur->regmap[hr];
568 if(reg>=64)
569 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
570 }
571 }
572}
573
574void set_const(struct regstat *cur,signed char reg,uint64_t value)
575{
576 int hr;
577 if(!reg) return;
578 for (hr=0;hr<HOST_REGS;hr++) {
579 if(cur->regmap[hr]==reg) {
580 cur->isconst|=1<<hr;
581 cur->constmap[hr]=value;
582 }
583 else if((cur->regmap[hr]^64)==reg) {
584 cur->isconst|=1<<hr;
585 cur->constmap[hr]=value>>32;
586 }
587 }
588}
589
590void clear_const(struct regstat *cur,signed char reg)
591{
592 int hr;
593 if(!reg) return;
594 for (hr=0;hr<HOST_REGS;hr++) {
595 if((cur->regmap[hr]&63)==reg) {
596 cur->isconst&=~(1<<hr);
597 }
598 }
599}
600
601int is_const(struct regstat *cur,signed char reg)
602{
603 int hr;
79c75f1b 604 if(reg<0) return 0;
57871462 605 if(!reg) return 1;
606 for (hr=0;hr<HOST_REGS;hr++) {
607 if((cur->regmap[hr]&63)==reg) {
608 return (cur->isconst>>hr)&1;
609 }
610 }
611 return 0;
612}
613uint64_t get_const(struct regstat *cur,signed char reg)
614{
615 int hr;
616 if(!reg) return 0;
617 for (hr=0;hr<HOST_REGS;hr++) {
618 if(cur->regmap[hr]==reg) {
619 return cur->constmap[hr];
620 }
621 }
622 printf("Unknown constant in r%d\n",reg);
623 exit(1);
624}
625
626// Least soon needed registers
627// Look at the next ten instructions and see which registers
628// will be used. Try not to reallocate these.
629void lsn(u_char hsn[], int i, int *preferred_reg)
630{
631 int j;
632 int b=-1;
633 for(j=0;j<9;j++)
634 {
635 if(i+j>=slen) {
636 j=slen-i-1;
637 break;
638 }
639 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
640 {
641 // Don't go past an unconditonal jump
642 j++;
643 break;
644 }
645 }
646 for(;j>=0;j--)
647 {
648 if(rs1[i+j]) hsn[rs1[i+j]]=j;
649 if(rs2[i+j]) hsn[rs2[i+j]]=j;
650 if(rt1[i+j]) hsn[rt1[i+j]]=j;
651 if(rt2[i+j]) hsn[rt2[i+j]]=j;
652 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
653 // Stores can allocate zero
654 hsn[rs1[i+j]]=j;
655 hsn[rs2[i+j]]=j;
656 }
657 // On some architectures stores need invc_ptr
658 #if defined(HOST_IMM8)
b9b61529 659 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
57871462 660 hsn[INVCP]=j;
661 }
662 #endif
663 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
664 {
665 hsn[CCREG]=j;
666 b=j;
667 }
668 }
669 if(b>=0)
670 {
671 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
672 {
673 // Follow first branch
674 int t=(ba[i+b]-start)>>2;
675 j=7-b;if(t+j>=slen) j=slen-t-1;
676 for(;j>=0;j--)
677 {
678 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
679 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
680 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
681 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
682 }
683 }
684 // TODO: preferred register based on backward branch
685 }
686 // Delay slot should preferably not overwrite branch conditions or cycle count
687 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
688 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
689 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
690 hsn[CCREG]=1;
691 // ...or hash tables
692 hsn[RHASH]=1;
693 hsn[RHTBL]=1;
694 }
695 // Coprocessor load/store needs FTEMP, even if not declared
b9b61529 696 if(itype[i]==C1LS||itype[i]==C2LS) {
57871462 697 hsn[FTEMP]=0;
698 }
699 // Load L/R also uses FTEMP as a temporary register
700 if(itype[i]==LOADLR) {
701 hsn[FTEMP]=0;
702 }
b7918751 703 // Also SWL/SWR/SDL/SDR
704 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
57871462 705 hsn[FTEMP]=0;
706 }
707 // Don't remove the TLB registers either
b9b61529 708 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
57871462 709 hsn[TLREG]=0;
710 }
711 // Don't remove the miniht registers
712 if(itype[i]==UJUMP||itype[i]==RJUMP)
713 {
714 hsn[RHASH]=0;
715 hsn[RHTBL]=0;
716 }
717}
718
719// We only want to allocate registers if we're going to use them again soon
720int needed_again(int r, int i)
721{
722 int j;
723 int b=-1;
724 int rn=10;
57871462 725
726 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
727 {
728 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
729 return 0; // Don't need any registers if exiting the block
730 }
731 for(j=0;j<9;j++)
732 {
733 if(i+j>=slen) {
734 j=slen-i-1;
735 break;
736 }
737 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
738 {
739 // Don't go past an unconditonal jump
740 j++;
741 break;
742 }
1e973cb0 743 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
57871462 744 {
745 break;
746 }
747 }
748 for(;j>=1;j--)
749 {
750 if(rs1[i+j]==r) rn=j;
751 if(rs2[i+j]==r) rn=j;
752 if((unneeded_reg[i+j]>>r)&1) rn=10;
753 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
754 {
755 b=j;
756 }
757 }
758 /*
759 if(b>=0)
760 {
761 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
762 {
763 // Follow first branch
764 int o=rn;
765 int t=(ba[i+b]-start)>>2;
766 j=7-b;if(t+j>=slen) j=slen-t-1;
767 for(;j>=0;j--)
768 {
769 if(!((unneeded_reg[t+j]>>r)&1)) {
770 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
771 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
772 }
773 else rn=o;
774 }
775 }
776 }*/
b7217e13 777 if(rn<10) return 1;
57871462 778 return 0;
779}
780
781// Try to match register allocations at the end of a loop with those
782// at the beginning
783int loop_reg(int i, int r, int hr)
784{
785 int j,k;
786 for(j=0;j<9;j++)
787 {
788 if(i+j>=slen) {
789 j=slen-i-1;
790 break;
791 }
792 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
793 {
794 // Don't go past an unconditonal jump
795 j++;
796 break;
797 }
798 }
799 k=0;
800 if(i>0){
801 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
802 k--;
803 }
804 for(;k<j;k++)
805 {
806 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
807 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
808 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
809 {
810 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
811 {
812 int t=(ba[i+k]-start)>>2;
813 int reg=get_reg(regs[t].regmap_entry,r);
814 if(reg>=0) return reg;
815 //reg=get_reg(regs[t+1].regmap_entry,r);
816 //if(reg>=0) return reg;
817 }
818 }
819 }
820 return hr;
821}
822
823
824// Allocate every register, preserving source/target regs
825void alloc_all(struct regstat *cur,int i)
826{
827 int hr;
828
829 for(hr=0;hr<HOST_REGS;hr++) {
830 if(hr!=EXCLUDE_REG) {
831 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
832 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
833 {
834 cur->regmap[hr]=-1;
835 cur->dirty&=~(1<<hr);
836 }
837 // Don't need zeros
838 if((cur->regmap[hr]&63)==0)
839 {
840 cur->regmap[hr]=-1;
841 cur->dirty&=~(1<<hr);
842 }
843 }
844 }
845}
846
847
848void div64(int64_t dividend,int64_t divisor)
849{
850 lo=dividend/divisor;
851 hi=dividend%divisor;
852 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
853 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
854}
855void divu64(uint64_t dividend,uint64_t divisor)
856{
857 lo=dividend/divisor;
858 hi=dividend%divisor;
859 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
860 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
861}
862
863void mult64(uint64_t m1,uint64_t m2)
864{
865 unsigned long long int op1, op2, op3, op4;
866 unsigned long long int result1, result2, result3, result4;
867 unsigned long long int temp1, temp2, temp3, temp4;
868 int sign = 0;
869
870 if (m1 < 0)
871 {
872 op2 = -m1;
873 sign = 1 - sign;
874 }
875 else op2 = m1;
876 if (m2 < 0)
877 {
878 op4 = -m2;
879 sign = 1 - sign;
880 }
881 else op4 = m2;
882
883 op1 = op2 & 0xFFFFFFFF;
884 op2 = (op2 >> 32) & 0xFFFFFFFF;
885 op3 = op4 & 0xFFFFFFFF;
886 op4 = (op4 >> 32) & 0xFFFFFFFF;
887
888 temp1 = op1 * op3;
889 temp2 = (temp1 >> 32) + op1 * op4;
890 temp3 = op2 * op3;
891 temp4 = (temp3 >> 32) + op2 * op4;
892
893 result1 = temp1 & 0xFFFFFFFF;
894 result2 = temp2 + (temp3 & 0xFFFFFFFF);
895 result3 = (result2 >> 32) + temp4;
896 result4 = (result3 >> 32);
897
898 lo = result1 | (result2 << 32);
899 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
900 if (sign)
901 {
902 hi = ~hi;
903 if (!lo) hi++;
904 else lo = ~lo + 1;
905 }
906}
907
908void multu64(uint64_t m1,uint64_t m2)
909{
910 unsigned long long int op1, op2, op3, op4;
911 unsigned long long int result1, result2, result3, result4;
912 unsigned long long int temp1, temp2, temp3, temp4;
913
914 op1 = m1 & 0xFFFFFFFF;
915 op2 = (m1 >> 32) & 0xFFFFFFFF;
916 op3 = m2 & 0xFFFFFFFF;
917 op4 = (m2 >> 32) & 0xFFFFFFFF;
918
919 temp1 = op1 * op3;
920 temp2 = (temp1 >> 32) + op1 * op4;
921 temp3 = op2 * op3;
922 temp4 = (temp3 >> 32) + op2 * op4;
923
924 result1 = temp1 & 0xFFFFFFFF;
925 result2 = temp2 + (temp3 & 0xFFFFFFFF);
926 result3 = (result2 >> 32) + temp4;
927 result4 = (result3 >> 32);
928
929 lo = result1 | (result2 << 32);
930 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
931
932 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
933 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
934}
935
936uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
937{
938 if(bits) {
939 original<<=64-bits;
940 original>>=64-bits;
941 loaded<<=bits;
942 original|=loaded;
943 }
944 else original=loaded;
945 return original;
946}
947uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
948{
949 if(bits^56) {
950 original>>=64-(bits^56);
951 original<<=64-(bits^56);
952 loaded>>=bits^56;
953 original|=loaded;
954 }
955 else original=loaded;
956 return original;
957}
958
959#ifdef __i386__
960#include "assem_x86.c"
961#endif
962#ifdef __x86_64__
963#include "assem_x64.c"
964#endif
965#ifdef __arm__
966#include "assem_arm.c"
967#endif
968
969// Add virtual address mapping to linked list
970void ll_add(struct ll_entry **head,int vaddr,void *addr)
971{
972 struct ll_entry *new_entry;
973 new_entry=malloc(sizeof(struct ll_entry));
974 assert(new_entry!=NULL);
975 new_entry->vaddr=vaddr;
976 new_entry->reg32=0;
977 new_entry->addr=addr;
978 new_entry->next=*head;
979 *head=new_entry;
980}
981
982// Add virtual address mapping for 32-bit compiled block
983void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
984{
7139f3c8 985 ll_add(head,vaddr,addr);
986#ifndef FORCE32
987 (*head)->reg32=reg32;
988#endif
57871462 989}
990
991// Check if an address is already compiled
992// but don't return addresses which are about to expire from the cache
993void *check_addr(u_int vaddr)
994{
995 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
996 if(ht_bin[0]==vaddr) {
997 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
998 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
999 }
1000 if(ht_bin[2]==vaddr) {
1001 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1002 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1003 }
94d23bb9 1004 u_int page=get_page(vaddr);
57871462 1005 struct ll_entry *head;
1006 head=jump_in[page];
1007 while(head!=NULL) {
1008 if(head->vaddr==vaddr&&head->reg32==0) {
1009 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1010 // Update existing entry with current address
1011 if(ht_bin[0]==vaddr) {
1012 ht_bin[1]=(int)head->addr;
1013 return head->addr;
1014 }
1015 if(ht_bin[2]==vaddr) {
1016 ht_bin[3]=(int)head->addr;
1017 return head->addr;
1018 }
1019 // Insert into hash table with low priority.
1020 // Don't evict existing entries, as they are probably
1021 // addresses that are being accessed frequently.
1022 if(ht_bin[0]==-1) {
1023 ht_bin[1]=(int)head->addr;
1024 ht_bin[0]=vaddr;
1025 }else if(ht_bin[2]==-1) {
1026 ht_bin[3]=(int)head->addr;
1027 ht_bin[2]=vaddr;
1028 }
1029 return head->addr;
1030 }
1031 }
1032 head=head->next;
1033 }
1034 return 0;
1035}
1036
1037void remove_hash(int vaddr)
1038{
1039 //printf("remove hash: %x\n",vaddr);
1040 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1041 if(ht_bin[2]==vaddr) {
1042 ht_bin[2]=ht_bin[3]=-1;
1043 }
1044 if(ht_bin[0]==vaddr) {
1045 ht_bin[0]=ht_bin[2];
1046 ht_bin[1]=ht_bin[3];
1047 ht_bin[2]=ht_bin[3]=-1;
1048 }
1049}
1050
1051void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1052{
1053 struct ll_entry *next;
1054 while(*head) {
1055 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1056 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1057 {
1058 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1059 remove_hash((*head)->vaddr);
1060 next=(*head)->next;
1061 free(*head);
1062 *head=next;
1063 }
1064 else
1065 {
1066 head=&((*head)->next);
1067 }
1068 }
1069}
1070
1071// Remove all entries from linked list
1072void ll_clear(struct ll_entry **head)
1073{
1074 struct ll_entry *cur;
1075 struct ll_entry *next;
1076 if(cur=*head) {
1077 *head=0;
1078 while(cur) {
1079 next=cur->next;
1080 free(cur);
1081 cur=next;
1082 }
1083 }
1084}
1085
1086// Dereference the pointers and remove if it matches
1087void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1088{
1089 while(head) {
1090 int ptr=get_pointer(head->addr);
1091 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1092 if(((ptr>>shift)==(addr>>shift)) ||
1093 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1094 {
5088bb70 1095 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
f76eeef9 1096 u_int host_addr=(u_int)kill_pointer(head->addr);
dd3a91a1 1097 #ifdef __arm__
1098 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1099 #endif
57871462 1100 }
1101 head=head->next;
1102 }
1103}
1104
1105// This is called when we write to a compiled block (see do_invstub)
f76eeef9 1106void invalidate_page(u_int page)
57871462 1107{
57871462 1108 struct ll_entry *head;
1109 struct ll_entry *next;
1110 head=jump_in[page];
1111 jump_in[page]=0;
1112 while(head!=NULL) {
1113 inv_debug("INVALIDATE: %x\n",head->vaddr);
1114 remove_hash(head->vaddr);
1115 next=head->next;
1116 free(head);
1117 head=next;
1118 }
1119 head=jump_out[page];
1120 jump_out[page]=0;
1121 while(head!=NULL) {
1122 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
f76eeef9 1123 u_int host_addr=(u_int)kill_pointer(head->addr);
dd3a91a1 1124 #ifdef __arm__
1125 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1126 #endif
57871462 1127 next=head->next;
1128 free(head);
1129 head=next;
1130 }
57871462 1131}
9be4ba64 1132
1133static void invalidate_block_range(u_int block, u_int first, u_int last)
57871462 1134{
94d23bb9 1135 u_int page=get_page(block<<12);
57871462 1136 //printf("first=%d last=%d\n",first,last);
f76eeef9 1137 invalidate_page(page);
57871462 1138 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1139 assert(last<page+5);
1140 // Invalidate the adjacent pages if a block crosses a 4K boundary
1141 while(first<page) {
1142 invalidate_page(first);
1143 first++;
1144 }
1145 for(first=page+1;first<last;first++) {
1146 invalidate_page(first);
1147 }
dd3a91a1 1148 #ifdef __arm__
1149 do_clear_cache();
1150 #endif
57871462 1151
1152 // Don't trap writes
1153 invalid_code[block]=1;
94d23bb9 1154#ifndef DISABLE_TLB
57871462 1155 // If there is a valid TLB entry for this page, remove write protect
1156 if(tlb_LUT_w[block]) {
1157 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1158 // CHECK: Is this right?
1159 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1160 u_int real_block=tlb_LUT_w[block]>>12;
1161 invalid_code[real_block]=1;
1162 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1163 }
1164 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
94d23bb9 1165#endif
f76eeef9 1166
57871462 1167 #ifdef USE_MINI_HT
1168 memset(mini_ht,-1,sizeof(mini_ht));
1169 #endif
1170}
9be4ba64 1171
1172void invalidate_block(u_int block)
1173{
1174 u_int page=get_page(block<<12);
1175 u_int vpage=get_vpage(block<<12);
1176 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1177 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1178 u_int first,last;
1179 first=last=page;
1180 struct ll_entry *head;
1181 head=jump_dirty[vpage];
1182 //printf("page=%d vpage=%d\n",page,vpage);
1183 while(head!=NULL) {
1184 u_int start,end;
1185 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1186 get_bounds((int)head->addr,&start,&end);
1187 //printf("start: %x end: %x\n",start,end);
1188 if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
1189 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1190 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1191 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1192 }
1193 }
1194#ifndef DISABLE_TLB
1195 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1196 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1197 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1198 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1199 }
1200 }
1201#endif
1202 }
1203 head=head->next;
1204 }
1205 invalidate_block_range(block,first,last);
1206}
1207
57871462 1208void invalidate_addr(u_int addr)
1209{
9be4ba64 1210#ifdef PCSX
1211 //static int rhits;
1212 // this check is done by the caller
1213 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
1214 u_int page=get_page(addr);
1215 if(page<2048) { // RAM
1216 struct ll_entry *head;
1217 u_int addr_min=~0, addr_max=0;
1218 int mask=RAM_SIZE-1;
1219 int pg1;
1220 inv_code_start=addr&~0xfff;
1221 inv_code_end=addr|0xfff;
1222 pg1=page;
1223 if (pg1>0) {
1224 // must check previous page too because of spans..
1225 pg1--;
1226 inv_code_start-=0x1000;
1227 }
1228 for(;pg1<=page;pg1++) {
1229 for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
1230 u_int start,end;
1231 get_bounds((int)head->addr,&start,&end);
1232 if((start&mask)<=(addr&mask)&&(addr&mask)<(end&mask)) {
1233 if(start<addr_min) addr_min=start;
1234 if(end>addr_max) addr_max=end;
1235 }
1236 else if(addr<start) {
1237 if(start<inv_code_end)
1238 inv_code_end=start-1;
1239 }
1240 else {
1241 if(end>inv_code_start)
1242 inv_code_start=end;
1243 }
1244 }
1245 }
1246 if (addr_min!=~0) {
1247 inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1248 inv_code_start=inv_code_end=~0;
1249 invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1250 return;
1251 }
1252 else {
1253 inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);//rhits);
1254 }
1255 //rhits=0;
1256 if(page!=0) // FIXME: don't know what's up with page 0 (Klonoa)
1257 return;
1258 }
1259#endif
57871462 1260 invalidate_block(addr>>12);
1261}
9be4ba64 1262
dd3a91a1 1263// This is called when loading a save state.
1264// Anything could have changed, so invalidate everything.
57871462 1265void invalidate_all_pages()
1266{
1267 u_int page,n;
1268 for(page=0;page<4096;page++)
1269 invalidate_page(page);
1270 for(page=0;page<1048576;page++)
1271 if(!invalid_code[page]) {
1272 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1273 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1274 }
1275 #ifdef __arm__
1276 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1277 #endif
1278 #ifdef USE_MINI_HT
1279 memset(mini_ht,-1,sizeof(mini_ht));
1280 #endif
94d23bb9 1281 #ifndef DISABLE_TLB
57871462 1282 // TLB
1283 for(page=0;page<0x100000;page++) {
1284 if(tlb_LUT_r[page]) {
1285 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1286 if(!tlb_LUT_w[page]||!invalid_code[page])
1287 memory_map[page]|=0x40000000; // Write protect
1288 }
1289 else memory_map[page]=-1;
1290 if(page==0x80000) page=0xC0000;
1291 }
1292 tlb_hacks();
94d23bb9 1293 #endif
57871462 1294}
1295
1296// Add an entry to jump_out after making a link
1297void add_link(u_int vaddr,void *src)
1298{
94d23bb9 1299 u_int page=get_page(vaddr);
57871462 1300 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
76f71c27 1301 int *ptr=(int *)(src+4);
1302 assert((*ptr&0x0fff0000)==0x059f0000);
57871462 1303 ll_add(jump_out+page,vaddr,src);
1304 //int ptr=get_pointer(src);
1305 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1306}
1307
1308// If a code block was found to be unmodified (bit was set in
1309// restore_candidate) and it remains unmodified (bit is clear
1310// in invalid_code) then move the entries for that 4K page from
1311// the dirty list to the clean list.
1312void clean_blocks(u_int page)
1313{
1314 struct ll_entry *head;
1315 inv_debug("INV: clean_blocks page=%d\n",page);
1316 head=jump_dirty[page];
1317 while(head!=NULL) {
1318 if(!invalid_code[head->vaddr>>12]) {
1319 // Don't restore blocks which are about to expire from the cache
1320 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1321 u_int start,end;
1322 if(verify_dirty((int)head->addr)) {
1323 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1324 u_int i;
1325 u_int inv=0;
1326 get_bounds((int)head->addr,&start,&end);
4cb76aa4 1327 if(start-(u_int)rdram<RAM_SIZE) {
57871462 1328 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1329 inv|=invalid_code[i];
1330 }
1331 }
1332 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1333 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1334 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1335 if(addr<start||addr>=end) inv=1;
1336 }
4cb76aa4 1337 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
57871462 1338 inv=1;
1339 }
1340 if(!inv) {
1341 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1342 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1343 u_int ppage=page;
94d23bb9 1344#ifndef DISABLE_TLB
57871462 1345 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
94d23bb9 1346#endif
57871462 1347 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1348 //printf("page=%x, addr=%x\n",page,head->vaddr);
1349 //assert(head->vaddr>>12==(page|0x80000));
1350 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1351 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1352 if(!head->reg32) {
1353 if(ht_bin[0]==head->vaddr) {
1354 ht_bin[1]=(int)clean_addr; // Replace existing entry
1355 }
1356 if(ht_bin[2]==head->vaddr) {
1357 ht_bin[3]=(int)clean_addr; // Replace existing entry
1358 }
1359 }
1360 }
1361 }
1362 }
1363 }
1364 }
1365 head=head->next;
1366 }
1367}
1368
1369
1370void mov_alloc(struct regstat *current,int i)
1371{
1372 // Note: Don't need to actually alloc the source registers
1373 if((~current->is32>>rs1[i])&1) {
1374 //alloc_reg64(current,i,rs1[i]);
1375 alloc_reg64(current,i,rt1[i]);
1376 current->is32&=~(1LL<<rt1[i]);
1377 } else {
1378 //alloc_reg(current,i,rs1[i]);
1379 alloc_reg(current,i,rt1[i]);
1380 current->is32|=(1LL<<rt1[i]);
1381 }
1382 clear_const(current,rs1[i]);
1383 clear_const(current,rt1[i]);
1384 dirty_reg(current,rt1[i]);
1385}
1386
1387void shiftimm_alloc(struct regstat *current,int i)
1388{
1389 clear_const(current,rs1[i]);
1390 clear_const(current,rt1[i]);
1391 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1392 {
1393 if(rt1[i]) {
1394 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1395 else lt1[i]=rs1[i];
1396 alloc_reg(current,i,rt1[i]);
1397 current->is32|=1LL<<rt1[i];
1398 dirty_reg(current,rt1[i]);
1399 }
1400 }
1401 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1402 {
1403 if(rt1[i]) {
1404 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1405 alloc_reg64(current,i,rt1[i]);
1406 current->is32&=~(1LL<<rt1[i]);
1407 dirty_reg(current,rt1[i]);
1408 }
1409 }
1410 if(opcode2[i]==0x3c) // DSLL32
1411 {
1412 if(rt1[i]) {
1413 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1414 alloc_reg64(current,i,rt1[i]);
1415 current->is32&=~(1LL<<rt1[i]);
1416 dirty_reg(current,rt1[i]);
1417 }
1418 }
1419 if(opcode2[i]==0x3e) // DSRL32
1420 {
1421 if(rt1[i]) {
1422 alloc_reg64(current,i,rs1[i]);
1423 if(imm[i]==32) {
1424 alloc_reg64(current,i,rt1[i]);
1425 current->is32&=~(1LL<<rt1[i]);
1426 } else {
1427 alloc_reg(current,i,rt1[i]);
1428 current->is32|=1LL<<rt1[i];
1429 }
1430 dirty_reg(current,rt1[i]);
1431 }
1432 }
1433 if(opcode2[i]==0x3f) // DSRA32
1434 {
1435 if(rt1[i]) {
1436 alloc_reg64(current,i,rs1[i]);
1437 alloc_reg(current,i,rt1[i]);
1438 current->is32|=1LL<<rt1[i];
1439 dirty_reg(current,rt1[i]);
1440 }
1441 }
1442}
1443
1444void shift_alloc(struct regstat *current,int i)
1445{
1446 if(rt1[i]) {
1447 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1448 {
1449 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1450 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1451 alloc_reg(current,i,rt1[i]);
e1190b87 1452 if(rt1[i]==rs2[i]) {
1453 alloc_reg_temp(current,i,-1);
1454 minimum_free_regs[i]=1;
1455 }
57871462 1456 current->is32|=1LL<<rt1[i];
1457 } else { // DSLLV/DSRLV/DSRAV
1458 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1459 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1460 alloc_reg64(current,i,rt1[i]);
1461 current->is32&=~(1LL<<rt1[i]);
1462 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
e1190b87 1463 {
57871462 1464 alloc_reg_temp(current,i,-1);
e1190b87 1465 minimum_free_regs[i]=1;
1466 }
57871462 1467 }
1468 clear_const(current,rs1[i]);
1469 clear_const(current,rs2[i]);
1470 clear_const(current,rt1[i]);
1471 dirty_reg(current,rt1[i]);
1472 }
1473}
1474
1475void alu_alloc(struct regstat *current,int i)
1476{
1477 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1478 if(rt1[i]) {
1479 if(rs1[i]&&rs2[i]) {
1480 alloc_reg(current,i,rs1[i]);
1481 alloc_reg(current,i,rs2[i]);
1482 }
1483 else {
1484 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1485 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1486 }
1487 alloc_reg(current,i,rt1[i]);
1488 }
1489 current->is32|=1LL<<rt1[i];
1490 }
1491 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1492 if(rt1[i]) {
1493 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1494 {
1495 alloc_reg64(current,i,rs1[i]);
1496 alloc_reg64(current,i,rs2[i]);
1497 alloc_reg(current,i,rt1[i]);
1498 } else {
1499 alloc_reg(current,i,rs1[i]);
1500 alloc_reg(current,i,rs2[i]);
1501 alloc_reg(current,i,rt1[i]);
1502 }
1503 }
1504 current->is32|=1LL<<rt1[i];
1505 }
1506 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1507 if(rt1[i]) {
1508 if(rs1[i]&&rs2[i]) {
1509 alloc_reg(current,i,rs1[i]);
1510 alloc_reg(current,i,rs2[i]);
1511 }
1512 else
1513 {
1514 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1515 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1516 }
1517 alloc_reg(current,i,rt1[i]);
1518 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1519 {
1520 if(!((current->uu>>rt1[i])&1)) {
1521 alloc_reg64(current,i,rt1[i]);
1522 }
1523 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1524 if(rs1[i]&&rs2[i]) {
1525 alloc_reg64(current,i,rs1[i]);
1526 alloc_reg64(current,i,rs2[i]);
1527 }
1528 else
1529 {
1530 // Is is really worth it to keep 64-bit values in registers?
1531 #ifdef NATIVE_64BIT
1532 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1533 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1534 #endif
1535 }
1536 }
1537 current->is32&=~(1LL<<rt1[i]);
1538 } else {
1539 current->is32|=1LL<<rt1[i];
1540 }
1541 }
1542 }
1543 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1544 if(rt1[i]) {
1545 if(rs1[i]&&rs2[i]) {
1546 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1547 alloc_reg64(current,i,rs1[i]);
1548 alloc_reg64(current,i,rs2[i]);
1549 alloc_reg64(current,i,rt1[i]);
1550 } else {
1551 alloc_reg(current,i,rs1[i]);
1552 alloc_reg(current,i,rs2[i]);
1553 alloc_reg(current,i,rt1[i]);
1554 }
1555 }
1556 else {
1557 alloc_reg(current,i,rt1[i]);
1558 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1559 // DADD used as move, or zeroing
1560 // If we have a 64-bit source, then make the target 64 bits too
1561 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1562 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1563 alloc_reg64(current,i,rt1[i]);
1564 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1565 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1566 alloc_reg64(current,i,rt1[i]);
1567 }
1568 if(opcode2[i]>=0x2e&&rs2[i]) {
1569 // DSUB used as negation - 64-bit result
1570 // If we have a 32-bit register, extend it to 64 bits
1571 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1572 alloc_reg64(current,i,rt1[i]);
1573 }
1574 }
1575 }
1576 if(rs1[i]&&rs2[i]) {
1577 current->is32&=~(1LL<<rt1[i]);
1578 } else if(rs1[i]) {
1579 current->is32&=~(1LL<<rt1[i]);
1580 if((current->is32>>rs1[i])&1)
1581 current->is32|=1LL<<rt1[i];
1582 } else if(rs2[i]) {
1583 current->is32&=~(1LL<<rt1[i]);
1584 if((current->is32>>rs2[i])&1)
1585 current->is32|=1LL<<rt1[i];
1586 } else {
1587 current->is32|=1LL<<rt1[i];
1588 }
1589 }
1590 }
1591 clear_const(current,rs1[i]);
1592 clear_const(current,rs2[i]);
1593 clear_const(current,rt1[i]);
1594 dirty_reg(current,rt1[i]);
1595}
1596
1597void imm16_alloc(struct regstat *current,int i)
1598{
1599 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1600 else lt1[i]=rs1[i];
1601 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1602 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1603 current->is32&=~(1LL<<rt1[i]);
1604 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1605 // TODO: Could preserve the 32-bit flag if the immediate is zero
1606 alloc_reg64(current,i,rt1[i]);
1607 alloc_reg64(current,i,rs1[i]);
1608 }
1609 clear_const(current,rs1[i]);
1610 clear_const(current,rt1[i]);
1611 }
1612 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1613 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1614 current->is32|=1LL<<rt1[i];
1615 clear_const(current,rs1[i]);
1616 clear_const(current,rt1[i]);
1617 }
1618 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1619 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1620 if(rs1[i]!=rt1[i]) {
1621 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1622 alloc_reg64(current,i,rt1[i]);
1623 current->is32&=~(1LL<<rt1[i]);
1624 }
1625 }
1626 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1627 if(is_const(current,rs1[i])) {
1628 int v=get_const(current,rs1[i]);
1629 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1630 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1631 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1632 }
1633 else clear_const(current,rt1[i]);
1634 }
1635 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1636 if(is_const(current,rs1[i])) {
1637 int v=get_const(current,rs1[i]);
1638 set_const(current,rt1[i],v+imm[i]);
1639 }
1640 else clear_const(current,rt1[i]);
1641 current->is32|=1LL<<rt1[i];
1642 }
1643 else {
1644 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1645 current->is32|=1LL<<rt1[i];
1646 }
1647 dirty_reg(current,rt1[i]);
1648}
1649
1650void load_alloc(struct regstat *current,int i)
1651{
1652 clear_const(current,rt1[i]);
1653 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1654 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1655 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
373d1d07 1656 if(rt1[i]&&!((current->u>>rt1[i])&1)) {
57871462 1657 alloc_reg(current,i,rt1[i]);
373d1d07 1658 assert(get_reg(current->regmap,rt1[i])>=0);
57871462 1659 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1660 {
1661 current->is32&=~(1LL<<rt1[i]);
1662 alloc_reg64(current,i,rt1[i]);
1663 }
1664 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1665 {
1666 current->is32&=~(1LL<<rt1[i]);
1667 alloc_reg64(current,i,rt1[i]);
1668 alloc_all(current,i);
1669 alloc_reg64(current,i,FTEMP);
e1190b87 1670 minimum_free_regs[i]=HOST_REGS;
57871462 1671 }
1672 else current->is32|=1LL<<rt1[i];
1673 dirty_reg(current,rt1[i]);
1674 // If using TLB, need a register for pointer to the mapping table
1675 if(using_tlb) alloc_reg(current,i,TLREG);
1676 // LWL/LWR need a temporary register for the old value
1677 if(opcode[i]==0x22||opcode[i]==0x26)
1678 {
1679 alloc_reg(current,i,FTEMP);
1680 alloc_reg_temp(current,i,-1);
e1190b87 1681 minimum_free_regs[i]=1;
57871462 1682 }
1683 }
1684 else
1685 {
373d1d07 1686 // Load to r0 or unneeded register (dummy load)
57871462 1687 // but we still need a register to calculate the address
535d208a 1688 if(opcode[i]==0x22||opcode[i]==0x26)
1689 {
1690 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1691 }
373d1d07 1692 // If using TLB, need a register for pointer to the mapping table
1693 if(using_tlb) alloc_reg(current,i,TLREG);
57871462 1694 alloc_reg_temp(current,i,-1);
e1190b87 1695 minimum_free_regs[i]=1;
535d208a 1696 if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1697 {
1698 alloc_all(current,i);
1699 alloc_reg64(current,i,FTEMP);
e1190b87 1700 minimum_free_regs[i]=HOST_REGS;
535d208a 1701 }
57871462 1702 }
1703}
1704
1705void store_alloc(struct regstat *current,int i)
1706{
1707 clear_const(current,rs2[i]);
1708 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1709 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1710 alloc_reg(current,i,rs2[i]);
1711 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1712 alloc_reg64(current,i,rs2[i]);
1713 if(rs2[i]) alloc_reg(current,i,FTEMP);
1714 }
1715 // If using TLB, need a register for pointer to the mapping table
1716 if(using_tlb) alloc_reg(current,i,TLREG);
1717 #if defined(HOST_IMM8)
1718 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1719 else alloc_reg(current,i,INVCP);
1720 #endif
b7918751 1721 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
57871462 1722 alloc_reg(current,i,FTEMP);
1723 }
1724 // We need a temporary register for address generation
1725 alloc_reg_temp(current,i,-1);
e1190b87 1726 minimum_free_regs[i]=1;
57871462 1727}
1728
1729void c1ls_alloc(struct regstat *current,int i)
1730{
1731 //clear_const(current,rs1[i]); // FIXME
1732 clear_const(current,rt1[i]);
1733 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1734 alloc_reg(current,i,CSREG); // Status
1735 alloc_reg(current,i,FTEMP);
1736 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1737 alloc_reg64(current,i,FTEMP);
1738 }
1739 // If using TLB, need a register for pointer to the mapping table
1740 if(using_tlb) alloc_reg(current,i,TLREG);
1741 #if defined(HOST_IMM8)
1742 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1743 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1744 alloc_reg(current,i,INVCP);
1745 #endif
1746 // We need a temporary register for address generation
1747 alloc_reg_temp(current,i,-1);
1748}
1749
b9b61529 1750void c2ls_alloc(struct regstat *current,int i)
1751{
1752 clear_const(current,rt1[i]);
1753 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1754 alloc_reg(current,i,FTEMP);
1755 // If using TLB, need a register for pointer to the mapping table
1756 if(using_tlb) alloc_reg(current,i,TLREG);
1757 #if defined(HOST_IMM8)
1758 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1759 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1760 alloc_reg(current,i,INVCP);
1761 #endif
1762 // We need a temporary register for address generation
1763 alloc_reg_temp(current,i,-1);
e1190b87 1764 minimum_free_regs[i]=1;
b9b61529 1765}
1766
57871462 1767#ifndef multdiv_alloc
1768void multdiv_alloc(struct regstat *current,int i)
1769{
1770 // case 0x18: MULT
1771 // case 0x19: MULTU
1772 // case 0x1A: DIV
1773 // case 0x1B: DIVU
1774 // case 0x1C: DMULT
1775 // case 0x1D: DMULTU
1776 // case 0x1E: DDIV
1777 // case 0x1F: DDIVU
1778 clear_const(current,rs1[i]);
1779 clear_const(current,rs2[i]);
1780 if(rs1[i]&&rs2[i])
1781 {
1782 if((opcode2[i]&4)==0) // 32-bit
1783 {
1784 current->u&=~(1LL<<HIREG);
1785 current->u&=~(1LL<<LOREG);
1786 alloc_reg(current,i,HIREG);
1787 alloc_reg(current,i,LOREG);
1788 alloc_reg(current,i,rs1[i]);
1789 alloc_reg(current,i,rs2[i]);
1790 current->is32|=1LL<<HIREG;
1791 current->is32|=1LL<<LOREG;
1792 dirty_reg(current,HIREG);
1793 dirty_reg(current,LOREG);
1794 }
1795 else // 64-bit
1796 {
1797 current->u&=~(1LL<<HIREG);
1798 current->u&=~(1LL<<LOREG);
1799 current->uu&=~(1LL<<HIREG);
1800 current->uu&=~(1LL<<LOREG);
1801 alloc_reg64(current,i,HIREG);
1802 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1803 alloc_reg64(current,i,rs1[i]);
1804 alloc_reg64(current,i,rs2[i]);
1805 alloc_all(current,i);
1806 current->is32&=~(1LL<<HIREG);
1807 current->is32&=~(1LL<<LOREG);
1808 dirty_reg(current,HIREG);
1809 dirty_reg(current,LOREG);
e1190b87 1810 minimum_free_regs[i]=HOST_REGS;
57871462 1811 }
1812 }
1813 else
1814 {
1815 // Multiply by zero is zero.
1816 // MIPS does not have a divide by zero exception.
1817 // The result is undefined, we return zero.
1818 alloc_reg(current,i,HIREG);
1819 alloc_reg(current,i,LOREG);
1820 current->is32|=1LL<<HIREG;
1821 current->is32|=1LL<<LOREG;
1822 dirty_reg(current,HIREG);
1823 dirty_reg(current,LOREG);
1824 }
1825}
1826#endif
1827
1828void cop0_alloc(struct regstat *current,int i)
1829{
1830 if(opcode2[i]==0) // MFC0
1831 {
1832 if(rt1[i]) {
1833 clear_const(current,rt1[i]);
1834 alloc_all(current,i);
1835 alloc_reg(current,i,rt1[i]);
1836 current->is32|=1LL<<rt1[i];
1837 dirty_reg(current,rt1[i]);
1838 }
1839 }
1840 else if(opcode2[i]==4) // MTC0
1841 {
1842 if(rs1[i]){
1843 clear_const(current,rs1[i]);
1844 alloc_reg(current,i,rs1[i]);
1845 alloc_all(current,i);
1846 }
1847 else {
1848 alloc_all(current,i); // FIXME: Keep r0
1849 current->u&=~1LL;
1850 alloc_reg(current,i,0);
1851 }
1852 }
1853 else
1854 {
1855 // TLBR/TLBWI/TLBWR/TLBP/ERET
1856 assert(opcode2[i]==0x10);
1857 alloc_all(current,i);
1858 }
e1190b87 1859 minimum_free_regs[i]=HOST_REGS;
57871462 1860}
1861
1862void cop1_alloc(struct regstat *current,int i)
1863{
1864 alloc_reg(current,i,CSREG); // Load status
1865 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1866 {
7de557a6 1867 if(rt1[i]){
1868 clear_const(current,rt1[i]);
1869 if(opcode2[i]==1) {
1870 alloc_reg64(current,i,rt1[i]); // DMFC1
1871 current->is32&=~(1LL<<rt1[i]);
1872 }else{
1873 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1874 current->is32|=1LL<<rt1[i];
1875 }
1876 dirty_reg(current,rt1[i]);
57871462 1877 }
57871462 1878 alloc_reg_temp(current,i,-1);
1879 }
1880 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1881 {
1882 if(rs1[i]){
1883 clear_const(current,rs1[i]);
1884 if(opcode2[i]==5)
1885 alloc_reg64(current,i,rs1[i]); // DMTC1
1886 else
1887 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1888 alloc_reg_temp(current,i,-1);
1889 }
1890 else {
1891 current->u&=~1LL;
1892 alloc_reg(current,i,0);
1893 alloc_reg_temp(current,i,-1);
1894 }
1895 }
e1190b87 1896 minimum_free_regs[i]=1;
57871462 1897}
1898void fconv_alloc(struct regstat *current,int i)
1899{
1900 alloc_reg(current,i,CSREG); // Load status
1901 alloc_reg_temp(current,i,-1);
e1190b87 1902 minimum_free_regs[i]=1;
57871462 1903}
1904void float_alloc(struct regstat *current,int i)
1905{
1906 alloc_reg(current,i,CSREG); // Load status
1907 alloc_reg_temp(current,i,-1);
e1190b87 1908 minimum_free_regs[i]=1;
57871462 1909}
b9b61529 1910void c2op_alloc(struct regstat *current,int i)
1911{
1912 alloc_reg_temp(current,i,-1);
1913}
57871462 1914void fcomp_alloc(struct regstat *current,int i)
1915{
1916 alloc_reg(current,i,CSREG); // Load status
1917 alloc_reg(current,i,FSREG); // Load flags
1918 dirty_reg(current,FSREG); // Flag will be modified
1919 alloc_reg_temp(current,i,-1);
e1190b87 1920 minimum_free_regs[i]=1;
57871462 1921}
1922
1923void syscall_alloc(struct regstat *current,int i)
1924{
1925 alloc_cc(current,i);
1926 dirty_reg(current,CCREG);
1927 alloc_all(current,i);
e1190b87 1928 minimum_free_regs[i]=HOST_REGS;
57871462 1929 current->isconst=0;
1930}
1931
1932void delayslot_alloc(struct regstat *current,int i)
1933{
1934 switch(itype[i]) {
1935 case UJUMP:
1936 case CJUMP:
1937 case SJUMP:
1938 case RJUMP:
1939 case FJUMP:
1940 case SYSCALL:
7139f3c8 1941 case HLECALL:
57871462 1942 case SPAN:
1943 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1944 printf("Disabled speculative precompilation\n");
1945 stop_after_jal=1;
1946 break;
1947 case IMM16:
1948 imm16_alloc(current,i);
1949 break;
1950 case LOAD:
1951 case LOADLR:
1952 load_alloc(current,i);
1953 break;
1954 case STORE:
1955 case STORELR:
1956 store_alloc(current,i);
1957 break;
1958 case ALU:
1959 alu_alloc(current,i);
1960 break;
1961 case SHIFT:
1962 shift_alloc(current,i);
1963 break;
1964 case MULTDIV:
1965 multdiv_alloc(current,i);
1966 break;
1967 case SHIFTIMM:
1968 shiftimm_alloc(current,i);
1969 break;
1970 case MOV:
1971 mov_alloc(current,i);
1972 break;
1973 case COP0:
1974 cop0_alloc(current,i);
1975 break;
1976 case COP1:
b9b61529 1977 case COP2:
57871462 1978 cop1_alloc(current,i);
1979 break;
1980 case C1LS:
1981 c1ls_alloc(current,i);
1982 break;
b9b61529 1983 case C2LS:
1984 c2ls_alloc(current,i);
1985 break;
57871462 1986 case FCONV:
1987 fconv_alloc(current,i);
1988 break;
1989 case FLOAT:
1990 float_alloc(current,i);
1991 break;
1992 case FCOMP:
1993 fcomp_alloc(current,i);
1994 break;
b9b61529 1995 case C2OP:
1996 c2op_alloc(current,i);
1997 break;
57871462 1998 }
1999}
2000
2001// Special case where a branch and delay slot span two pages in virtual memory
2002static void pagespan_alloc(struct regstat *current,int i)
2003{
2004 current->isconst=0;
2005 current->wasconst=0;
2006 regs[i].wasconst=0;
e1190b87 2007 minimum_free_regs[i]=HOST_REGS;
57871462 2008 alloc_all(current,i);
2009 alloc_cc(current,i);
2010 dirty_reg(current,CCREG);
2011 if(opcode[i]==3) // JAL
2012 {
2013 alloc_reg(current,i,31);
2014 dirty_reg(current,31);
2015 }
2016 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
2017 {
2018 alloc_reg(current,i,rs1[i]);
5067f341 2019 if (rt1[i]!=0) {
2020 alloc_reg(current,i,rt1[i]);
2021 dirty_reg(current,rt1[i]);
57871462 2022 }
2023 }
2024 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
2025 {
2026 if(rs1[i]) alloc_reg(current,i,rs1[i]);
2027 if(rs2[i]) alloc_reg(current,i,rs2[i]);
2028 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
2029 {
2030 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2031 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
2032 }
2033 }
2034 else
2035 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
2036 {
2037 if(rs1[i]) alloc_reg(current,i,rs1[i]);
2038 if(!((current->is32>>rs1[i])&1))
2039 {
2040 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2041 }
2042 }
2043 else
2044 if(opcode[i]==0x11) // BC1
2045 {
2046 alloc_reg(current,i,FSREG);
2047 alloc_reg(current,i,CSREG);
2048 }
2049 //else ...
2050}
2051
2052add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
2053{
2054 stubs[stubcount][0]=type;
2055 stubs[stubcount][1]=addr;
2056 stubs[stubcount][2]=retaddr;
2057 stubs[stubcount][3]=a;
2058 stubs[stubcount][4]=b;
2059 stubs[stubcount][5]=c;
2060 stubs[stubcount][6]=d;
2061 stubs[stubcount][7]=e;
2062 stubcount++;
2063}
2064
2065// Write out a single register
2066void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2067{
2068 int hr;
2069 for(hr=0;hr<HOST_REGS;hr++) {
2070 if(hr!=EXCLUDE_REG) {
2071 if((regmap[hr]&63)==r) {
2072 if((dirty>>hr)&1) {
2073 if(regmap[hr]<64) {
2074 emit_storereg(r,hr);
24385cae 2075#ifndef FORCE32
57871462 2076 if((is32>>regmap[hr])&1) {
2077 emit_sarimm(hr,31,hr);
2078 emit_storereg(r|64,hr);
2079 }
24385cae 2080#endif
57871462 2081 }else{
2082 emit_storereg(r|64,hr);
2083 }
2084 }
2085 }
2086 }
2087 }
2088}
2089
2090int mchecksum()
2091{
2092 //if(!tracedebug) return 0;
2093 int i;
2094 int sum=0;
2095 for(i=0;i<2097152;i++) {
2096 unsigned int temp=sum;
2097 sum<<=1;
2098 sum|=(~temp)>>31;
2099 sum^=((u_int *)rdram)[i];
2100 }
2101 return sum;
2102}
2103int rchecksum()
2104{
2105 int i;
2106 int sum=0;
2107 for(i=0;i<64;i++)
2108 sum^=((u_int *)reg)[i];
2109 return sum;
2110}
57871462 2111void rlist()
2112{
2113 int i;
2114 printf("TRACE: ");
2115 for(i=0;i<32;i++)
2116 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2117 printf("\n");
3d624f89 2118#ifndef DISABLE_COP1
57871462 2119 printf("TRACE: ");
2120 for(i=0;i<32;i++)
2121 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2122 printf("\n");
3d624f89 2123#endif
57871462 2124}
2125
2126void enabletrace()
2127{
2128 tracedebug=1;
2129}
2130
2131void memdebug(int i)
2132{
2133 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2134 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2135 //rlist();
2136 //if(tracedebug) {
2137 //if(Count>=-2084597794) {
2138 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2139 //if(0) {
2140 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2141 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2142 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2143 rlist();
2144 #ifdef __i386__
2145 printf("TRACE: %x\n",(&i)[-1]);
2146 #endif
2147 #ifdef __arm__
2148 int j;
2149 printf("TRACE: %x \n",(&j)[10]);
2150 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2151 #endif
2152 //fflush(stdout);
2153 }
2154 //printf("TRACE: %x\n",(&i)[-1]);
2155}
2156
2157void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2158{
2159 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2160}
2161
2162void alu_assemble(int i,struct regstat *i_regs)
2163{
2164 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2165 if(rt1[i]) {
2166 signed char s1,s2,t;
2167 t=get_reg(i_regs->regmap,rt1[i]);
2168 if(t>=0) {
2169 s1=get_reg(i_regs->regmap,rs1[i]);
2170 s2=get_reg(i_regs->regmap,rs2[i]);
2171 if(rs1[i]&&rs2[i]) {
2172 assert(s1>=0);
2173 assert(s2>=0);
2174 if(opcode2[i]&2) emit_sub(s1,s2,t);
2175 else emit_add(s1,s2,t);
2176 }
2177 else if(rs1[i]) {
2178 if(s1>=0) emit_mov(s1,t);
2179 else emit_loadreg(rs1[i],t);
2180 }
2181 else if(rs2[i]) {
2182 if(s2>=0) {
2183 if(opcode2[i]&2) emit_neg(s2,t);
2184 else emit_mov(s2,t);
2185 }
2186 else {
2187 emit_loadreg(rs2[i],t);
2188 if(opcode2[i]&2) emit_neg(t,t);
2189 }
2190 }
2191 else emit_zeroreg(t);
2192 }
2193 }
2194 }
2195 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2196 if(rt1[i]) {
2197 signed char s1l,s2l,s1h,s2h,tl,th;
2198 tl=get_reg(i_regs->regmap,rt1[i]);
2199 th=get_reg(i_regs->regmap,rt1[i]|64);
2200 if(tl>=0) {
2201 s1l=get_reg(i_regs->regmap,rs1[i]);
2202 s2l=get_reg(i_regs->regmap,rs2[i]);
2203 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2204 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2205 if(rs1[i]&&rs2[i]) {
2206 assert(s1l>=0);
2207 assert(s2l>=0);
2208 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2209 else emit_adds(s1l,s2l,tl);
2210 if(th>=0) {
2211 #ifdef INVERTED_CARRY
2212 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2213 #else
2214 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2215 #endif
2216 else emit_add(s1h,s2h,th);
2217 }
2218 }
2219 else if(rs1[i]) {
2220 if(s1l>=0) emit_mov(s1l,tl);
2221 else emit_loadreg(rs1[i],tl);
2222 if(th>=0) {
2223 if(s1h>=0) emit_mov(s1h,th);
2224 else emit_loadreg(rs1[i]|64,th);
2225 }
2226 }
2227 else if(rs2[i]) {
2228 if(s2l>=0) {
2229 if(opcode2[i]&2) emit_negs(s2l,tl);
2230 else emit_mov(s2l,tl);
2231 }
2232 else {
2233 emit_loadreg(rs2[i],tl);
2234 if(opcode2[i]&2) emit_negs(tl,tl);
2235 }
2236 if(th>=0) {
2237 #ifdef INVERTED_CARRY
2238 if(s2h>=0) emit_mov(s2h,th);
2239 else emit_loadreg(rs2[i]|64,th);
2240 if(opcode2[i]&2) {
2241 emit_adcimm(-1,th); // x86 has inverted carry flag
2242 emit_not(th,th);
2243 }
2244 #else
2245 if(opcode2[i]&2) {
2246 if(s2h>=0) emit_rscimm(s2h,0,th);
2247 else {
2248 emit_loadreg(rs2[i]|64,th);
2249 emit_rscimm(th,0,th);
2250 }
2251 }else{
2252 if(s2h>=0) emit_mov(s2h,th);
2253 else emit_loadreg(rs2[i]|64,th);
2254 }
2255 #endif
2256 }
2257 }
2258 else {
2259 emit_zeroreg(tl);
2260 if(th>=0) emit_zeroreg(th);
2261 }
2262 }
2263 }
2264 }
2265 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2266 if(rt1[i]) {
2267 signed char s1l,s1h,s2l,s2h,t;
2268 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2269 {
2270 t=get_reg(i_regs->regmap,rt1[i]);
2271 //assert(t>=0);
2272 if(t>=0) {
2273 s1l=get_reg(i_regs->regmap,rs1[i]);
2274 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2275 s2l=get_reg(i_regs->regmap,rs2[i]);
2276 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2277 if(rs2[i]==0) // rx<r0
2278 {
2279 assert(s1h>=0);
2280 if(opcode2[i]==0x2a) // SLT
2281 emit_shrimm(s1h,31,t);
2282 else // SLTU (unsigned can not be less than zero)
2283 emit_zeroreg(t);
2284 }
2285 else if(rs1[i]==0) // r0<rx
2286 {
2287 assert(s2h>=0);
2288 if(opcode2[i]==0x2a) // SLT
2289 emit_set_gz64_32(s2h,s2l,t);
2290 else // SLTU (set if not zero)
2291 emit_set_nz64_32(s2h,s2l,t);
2292 }
2293 else {
2294 assert(s1l>=0);assert(s1h>=0);
2295 assert(s2l>=0);assert(s2h>=0);
2296 if(opcode2[i]==0x2a) // SLT
2297 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2298 else // SLTU
2299 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2300 }
2301 }
2302 } else {
2303 t=get_reg(i_regs->regmap,rt1[i]);
2304 //assert(t>=0);
2305 if(t>=0) {
2306 s1l=get_reg(i_regs->regmap,rs1[i]);
2307 s2l=get_reg(i_regs->regmap,rs2[i]);
2308 if(rs2[i]==0) // rx<r0
2309 {
2310 assert(s1l>=0);
2311 if(opcode2[i]==0x2a) // SLT
2312 emit_shrimm(s1l,31,t);
2313 else // SLTU (unsigned can not be less than zero)
2314 emit_zeroreg(t);
2315 }
2316 else if(rs1[i]==0) // r0<rx
2317 {
2318 assert(s2l>=0);
2319 if(opcode2[i]==0x2a) // SLT
2320 emit_set_gz32(s2l,t);
2321 else // SLTU (set if not zero)
2322 emit_set_nz32(s2l,t);
2323 }
2324 else{
2325 assert(s1l>=0);assert(s2l>=0);
2326 if(opcode2[i]==0x2a) // SLT
2327 emit_set_if_less32(s1l,s2l,t);
2328 else // SLTU
2329 emit_set_if_carry32(s1l,s2l,t);
2330 }
2331 }
2332 }
2333 }
2334 }
2335 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2336 if(rt1[i]) {
2337 signed char s1l,s1h,s2l,s2h,th,tl;
2338 tl=get_reg(i_regs->regmap,rt1[i]);
2339 th=get_reg(i_regs->regmap,rt1[i]|64);
2340 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2341 {
2342 assert(tl>=0);
2343 if(tl>=0) {
2344 s1l=get_reg(i_regs->regmap,rs1[i]);
2345 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2346 s2l=get_reg(i_regs->regmap,rs2[i]);
2347 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2348 if(rs1[i]&&rs2[i]) {
2349 assert(s1l>=0);assert(s1h>=0);
2350 assert(s2l>=0);assert(s2h>=0);
2351 if(opcode2[i]==0x24) { // AND
2352 emit_and(s1l,s2l,tl);
2353 emit_and(s1h,s2h,th);
2354 } else
2355 if(opcode2[i]==0x25) { // OR
2356 emit_or(s1l,s2l,tl);
2357 emit_or(s1h,s2h,th);
2358 } else
2359 if(opcode2[i]==0x26) { // XOR
2360 emit_xor(s1l,s2l,tl);
2361 emit_xor(s1h,s2h,th);
2362 } else
2363 if(opcode2[i]==0x27) { // NOR
2364 emit_or(s1l,s2l,tl);
2365 emit_or(s1h,s2h,th);
2366 emit_not(tl,tl);
2367 emit_not(th,th);
2368 }
2369 }
2370 else
2371 {
2372 if(opcode2[i]==0x24) { // AND
2373 emit_zeroreg(tl);
2374 emit_zeroreg(th);
2375 } else
2376 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2377 if(rs1[i]){
2378 if(s1l>=0) emit_mov(s1l,tl);
2379 else emit_loadreg(rs1[i],tl);
2380 if(s1h>=0) emit_mov(s1h,th);
2381 else emit_loadreg(rs1[i]|64,th);
2382 }
2383 else
2384 if(rs2[i]){
2385 if(s2l>=0) emit_mov(s2l,tl);
2386 else emit_loadreg(rs2[i],tl);
2387 if(s2h>=0) emit_mov(s2h,th);
2388 else emit_loadreg(rs2[i]|64,th);
2389 }
2390 else{
2391 emit_zeroreg(tl);
2392 emit_zeroreg(th);
2393 }
2394 } else
2395 if(opcode2[i]==0x27) { // NOR
2396 if(rs1[i]){
2397 if(s1l>=0) emit_not(s1l,tl);
2398 else{
2399 emit_loadreg(rs1[i],tl);
2400 emit_not(tl,tl);
2401 }
2402 if(s1h>=0) emit_not(s1h,th);
2403 else{
2404 emit_loadreg(rs1[i]|64,th);
2405 emit_not(th,th);
2406 }
2407 }
2408 else
2409 if(rs2[i]){
2410 if(s2l>=0) emit_not(s2l,tl);
2411 else{
2412 emit_loadreg(rs2[i],tl);
2413 emit_not(tl,tl);
2414 }
2415 if(s2h>=0) emit_not(s2h,th);
2416 else{
2417 emit_loadreg(rs2[i]|64,th);
2418 emit_not(th,th);
2419 }
2420 }
2421 else {
2422 emit_movimm(-1,tl);
2423 emit_movimm(-1,th);
2424 }
2425 }
2426 }
2427 }
2428 }
2429 else
2430 {
2431 // 32 bit
2432 if(tl>=0) {
2433 s1l=get_reg(i_regs->regmap,rs1[i]);
2434 s2l=get_reg(i_regs->regmap,rs2[i]);
2435 if(rs1[i]&&rs2[i]) {
2436 assert(s1l>=0);
2437 assert(s2l>=0);
2438 if(opcode2[i]==0x24) { // AND
2439 emit_and(s1l,s2l,tl);
2440 } else
2441 if(opcode2[i]==0x25) { // OR
2442 emit_or(s1l,s2l,tl);
2443 } else
2444 if(opcode2[i]==0x26) { // XOR
2445 emit_xor(s1l,s2l,tl);
2446 } else
2447 if(opcode2[i]==0x27) { // NOR
2448 emit_or(s1l,s2l,tl);
2449 emit_not(tl,tl);
2450 }
2451 }
2452 else
2453 {
2454 if(opcode2[i]==0x24) { // AND
2455 emit_zeroreg(tl);
2456 } else
2457 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2458 if(rs1[i]){
2459 if(s1l>=0) emit_mov(s1l,tl);
2460 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2461 }
2462 else
2463 if(rs2[i]){
2464 if(s2l>=0) emit_mov(s2l,tl);
2465 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2466 }
2467 else emit_zeroreg(tl);
2468 } else
2469 if(opcode2[i]==0x27) { // NOR
2470 if(rs1[i]){
2471 if(s1l>=0) emit_not(s1l,tl);
2472 else {
2473 emit_loadreg(rs1[i],tl);
2474 emit_not(tl,tl);
2475 }
2476 }
2477 else
2478 if(rs2[i]){
2479 if(s2l>=0) emit_not(s2l,tl);
2480 else {
2481 emit_loadreg(rs2[i],tl);
2482 emit_not(tl,tl);
2483 }
2484 }
2485 else emit_movimm(-1,tl);
2486 }
2487 }
2488 }
2489 }
2490 }
2491 }
2492}
2493
2494void imm16_assemble(int i,struct regstat *i_regs)
2495{
2496 if (opcode[i]==0x0f) { // LUI
2497 if(rt1[i]) {
2498 signed char t;
2499 t=get_reg(i_regs->regmap,rt1[i]);
2500 //assert(t>=0);
2501 if(t>=0) {
2502 if(!((i_regs->isconst>>t)&1))
2503 emit_movimm(imm[i]<<16,t);
2504 }
2505 }
2506 }
2507 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2508 if(rt1[i]) {
2509 signed char s,t;
2510 t=get_reg(i_regs->regmap,rt1[i]);
2511 s=get_reg(i_regs->regmap,rs1[i]);
2512 if(rs1[i]) {
2513 //assert(t>=0);
2514 //assert(s>=0);
2515 if(t>=0) {
2516 if(!((i_regs->isconst>>t)&1)) {
2517 if(s<0) {
2518 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2519 emit_addimm(t,imm[i],t);
2520 }else{
2521 if(!((i_regs->wasconst>>s)&1))
2522 emit_addimm(s,imm[i],t);
2523 else
2524 emit_movimm(constmap[i][s]+imm[i],t);
2525 }
2526 }
2527 }
2528 } else {
2529 if(t>=0) {
2530 if(!((i_regs->isconst>>t)&1))
2531 emit_movimm(imm[i],t);
2532 }
2533 }
2534 }
2535 }
2536 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2537 if(rt1[i]) {
2538 signed char sh,sl,th,tl;
2539 th=get_reg(i_regs->regmap,rt1[i]|64);
2540 tl=get_reg(i_regs->regmap,rt1[i]);
2541 sh=get_reg(i_regs->regmap,rs1[i]|64);
2542 sl=get_reg(i_regs->regmap,rs1[i]);
2543 if(tl>=0) {
2544 if(rs1[i]) {
2545 assert(sh>=0);
2546 assert(sl>=0);
2547 if(th>=0) {
2548 emit_addimm64_32(sh,sl,imm[i],th,tl);
2549 }
2550 else {
2551 emit_addimm(sl,imm[i],tl);
2552 }
2553 } else {
2554 emit_movimm(imm[i],tl);
2555 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2556 }
2557 }
2558 }
2559 }
2560 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2561 if(rt1[i]) {
2562 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2563 signed char sh,sl,t;
2564 t=get_reg(i_regs->regmap,rt1[i]);
2565 sh=get_reg(i_regs->regmap,rs1[i]|64);
2566 sl=get_reg(i_regs->regmap,rs1[i]);
2567 //assert(t>=0);
2568 if(t>=0) {
2569 if(rs1[i]>0) {
2570 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2571 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2572 if(opcode[i]==0x0a) { // SLTI
2573 if(sl<0) {
2574 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2575 emit_slti32(t,imm[i],t);
2576 }else{
2577 emit_slti32(sl,imm[i],t);
2578 }
2579 }
2580 else { // SLTIU
2581 if(sl<0) {
2582 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2583 emit_sltiu32(t,imm[i],t);
2584 }else{
2585 emit_sltiu32(sl,imm[i],t);
2586 }
2587 }
2588 }else{ // 64-bit
2589 assert(sl>=0);
2590 if(opcode[i]==0x0a) // SLTI
2591 emit_slti64_32(sh,sl,imm[i],t);
2592 else // SLTIU
2593 emit_sltiu64_32(sh,sl,imm[i],t);
2594 }
2595 }else{
2596 // SLTI(U) with r0 is just stupid,
2597 // nonetheless examples can be found
2598 if(opcode[i]==0x0a) // SLTI
2599 if(0<imm[i]) emit_movimm(1,t);
2600 else emit_zeroreg(t);
2601 else // SLTIU
2602 {
2603 if(imm[i]) emit_movimm(1,t);
2604 else emit_zeroreg(t);
2605 }
2606 }
2607 }
2608 }
2609 }
2610 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2611 if(rt1[i]) {
2612 signed char sh,sl,th,tl;
2613 th=get_reg(i_regs->regmap,rt1[i]|64);
2614 tl=get_reg(i_regs->regmap,rt1[i]);
2615 sh=get_reg(i_regs->regmap,rs1[i]|64);
2616 sl=get_reg(i_regs->regmap,rs1[i]);
2617 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2618 if(opcode[i]==0x0c) //ANDI
2619 {
2620 if(rs1[i]) {
2621 if(sl<0) {
2622 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2623 emit_andimm(tl,imm[i],tl);
2624 }else{
2625 if(!((i_regs->wasconst>>sl)&1))
2626 emit_andimm(sl,imm[i],tl);
2627 else
2628 emit_movimm(constmap[i][sl]&imm[i],tl);
2629 }
2630 }
2631 else
2632 emit_zeroreg(tl);
2633 if(th>=0) emit_zeroreg(th);
2634 }
2635 else
2636 {
2637 if(rs1[i]) {
2638 if(sl<0) {
2639 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2640 }
2641 if(th>=0) {
2642 if(sh<0) {
2643 emit_loadreg(rs1[i]|64,th);
2644 }else{
2645 emit_mov(sh,th);
2646 }
2647 }
2648 if(opcode[i]==0x0d) //ORI
2649 if(sl<0) {
2650 emit_orimm(tl,imm[i],tl);
2651 }else{
2652 if(!((i_regs->wasconst>>sl)&1))
2653 emit_orimm(sl,imm[i],tl);
2654 else
2655 emit_movimm(constmap[i][sl]|imm[i],tl);
2656 }
2657 if(opcode[i]==0x0e) //XORI
2658 if(sl<0) {
2659 emit_xorimm(tl,imm[i],tl);
2660 }else{
2661 if(!((i_regs->wasconst>>sl)&1))
2662 emit_xorimm(sl,imm[i],tl);
2663 else
2664 emit_movimm(constmap[i][sl]^imm[i],tl);
2665 }
2666 }
2667 else {
2668 emit_movimm(imm[i],tl);
2669 if(th>=0) emit_zeroreg(th);
2670 }
2671 }
2672 }
2673 }
2674 }
2675}
2676
2677void shiftimm_assemble(int i,struct regstat *i_regs)
2678{
2679 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2680 {
2681 if(rt1[i]) {
2682 signed char s,t;
2683 t=get_reg(i_regs->regmap,rt1[i]);
2684 s=get_reg(i_regs->regmap,rs1[i]);
2685 //assert(t>=0);
2686 if(t>=0){
2687 if(rs1[i]==0)
2688 {
2689 emit_zeroreg(t);
2690 }
2691 else
2692 {
2693 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2694 if(imm[i]) {
2695 if(opcode2[i]==0) // SLL
2696 {
2697 emit_shlimm(s<0?t:s,imm[i],t);
2698 }
2699 if(opcode2[i]==2) // SRL
2700 {
2701 emit_shrimm(s<0?t:s,imm[i],t);
2702 }
2703 if(opcode2[i]==3) // SRA
2704 {
2705 emit_sarimm(s<0?t:s,imm[i],t);
2706 }
2707 }else{
2708 // Shift by zero
2709 if(s>=0 && s!=t) emit_mov(s,t);
2710 }
2711 }
2712 }
2713 //emit_storereg(rt1[i],t); //DEBUG
2714 }
2715 }
2716 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2717 {
2718 if(rt1[i]) {
2719 signed char sh,sl,th,tl;
2720 th=get_reg(i_regs->regmap,rt1[i]|64);
2721 tl=get_reg(i_regs->regmap,rt1[i]);
2722 sh=get_reg(i_regs->regmap,rs1[i]|64);
2723 sl=get_reg(i_regs->regmap,rs1[i]);
2724 if(tl>=0) {
2725 if(rs1[i]==0)
2726 {
2727 emit_zeroreg(tl);
2728 if(th>=0) emit_zeroreg(th);
2729 }
2730 else
2731 {
2732 assert(sl>=0);
2733 assert(sh>=0);
2734 if(imm[i]) {
2735 if(opcode2[i]==0x38) // DSLL
2736 {
2737 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2738 emit_shlimm(sl,imm[i],tl);
2739 }
2740 if(opcode2[i]==0x3a) // DSRL
2741 {
2742 emit_shrdimm(sl,sh,imm[i],tl);
2743 if(th>=0) emit_shrimm(sh,imm[i],th);
2744 }
2745 if(opcode2[i]==0x3b) // DSRA
2746 {
2747 emit_shrdimm(sl,sh,imm[i],tl);
2748 if(th>=0) emit_sarimm(sh,imm[i],th);
2749 }
2750 }else{
2751 // Shift by zero
2752 if(sl!=tl) emit_mov(sl,tl);
2753 if(th>=0&&sh!=th) emit_mov(sh,th);
2754 }
2755 }
2756 }
2757 }
2758 }
2759 if(opcode2[i]==0x3c) // DSLL32
2760 {
2761 if(rt1[i]) {
2762 signed char sl,tl,th;
2763 tl=get_reg(i_regs->regmap,rt1[i]);
2764 th=get_reg(i_regs->regmap,rt1[i]|64);
2765 sl=get_reg(i_regs->regmap,rs1[i]);
2766 if(th>=0||tl>=0){
2767 assert(tl>=0);
2768 assert(th>=0);
2769 assert(sl>=0);
2770 emit_mov(sl,th);
2771 emit_zeroreg(tl);
2772 if(imm[i]>32)
2773 {
2774 emit_shlimm(th,imm[i]&31,th);
2775 }
2776 }
2777 }
2778 }
2779 if(opcode2[i]==0x3e) // DSRL32
2780 {
2781 if(rt1[i]) {
2782 signed char sh,tl,th;
2783 tl=get_reg(i_regs->regmap,rt1[i]);
2784 th=get_reg(i_regs->regmap,rt1[i]|64);
2785 sh=get_reg(i_regs->regmap,rs1[i]|64);
2786 if(tl>=0){
2787 assert(sh>=0);
2788 emit_mov(sh,tl);
2789 if(th>=0) emit_zeroreg(th);
2790 if(imm[i]>32)
2791 {
2792 emit_shrimm(tl,imm[i]&31,tl);
2793 }
2794 }
2795 }
2796 }
2797 if(opcode2[i]==0x3f) // DSRA32
2798 {
2799 if(rt1[i]) {
2800 signed char sh,tl;
2801 tl=get_reg(i_regs->regmap,rt1[i]);
2802 sh=get_reg(i_regs->regmap,rs1[i]|64);
2803 if(tl>=0){
2804 assert(sh>=0);
2805 emit_mov(sh,tl);
2806 if(imm[i]>32)
2807 {
2808 emit_sarimm(tl,imm[i]&31,tl);
2809 }
2810 }
2811 }
2812 }
2813}
2814
2815#ifndef shift_assemble
2816void shift_assemble(int i,struct regstat *i_regs)
2817{
2818 printf("Need shift_assemble for this architecture.\n");
2819 exit(1);
2820}
2821#endif
2822
2823void load_assemble(int i,struct regstat *i_regs)
2824{
2825 int s,th,tl,addr,map=-1;
2826 int offset;
2827 int jaddr=0;
5bf843dc 2828 int memtarget=0,c=0;
b1570849 2829 int fastload_reg_override=0;
57871462 2830 u_int hr,reglist=0;
2831 th=get_reg(i_regs->regmap,rt1[i]|64);
2832 tl=get_reg(i_regs->regmap,rt1[i]);
2833 s=get_reg(i_regs->regmap,rs1[i]);
2834 offset=imm[i];
2835 for(hr=0;hr<HOST_REGS;hr++) {
2836 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2837 }
2838 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2839 if(s>=0) {
2840 c=(i_regs->wasconst>>s)&1;
af4ee1fe 2841 if (c) {
2842 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2843 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2844 }
57871462 2845 }
57871462 2846 //printf("load_assemble: c=%d\n",c);
2847 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2848 // FIXME: Even if the load is a NOP, we should check for pagefaults...
5bf843dc 2849#ifdef PCSX
f18c0f46 2850 if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2851 ||rt1[i]==0) {
5bf843dc 2852 // could be FIFO, must perform the read
f18c0f46 2853 // ||dummy read
5bf843dc 2854 assem_debug("(forced read)\n");
2855 tl=get_reg(i_regs->regmap,-1);
2856 assert(tl>=0);
5bf843dc 2857 }
f18c0f46 2858#endif
5bf843dc 2859 if(offset||s<0||c) addr=tl;
2860 else addr=s;
535d208a 2861 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2862 if(tl>=0) {
2863 //printf("load_assemble: c=%d\n",c);
2864 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2865 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2866 reglist&=~(1<<tl);
2867 if(th>=0) reglist&=~(1<<th);
2868 if(!using_tlb) {
2869 if(!c) {
2870 #ifdef RAM_OFFSET
2871 map=get_reg(i_regs->regmap,ROREG);
2872 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2873 #endif
57871462 2874//#define R29_HACK 1
535d208a 2875 #ifdef R29_HACK
2876 // Strmnnrmn's speed hack
2877 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2878 #endif
2879 {
dadf55f2 2880 #ifdef PCSX
2881 if(sp_in_mirror&&rs1[i]==29) {
2882 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
2883 emit_cmpimm(HOST_TEMPREG,RAM_SIZE);
b1570849 2884 fastload_reg_override=HOST_TEMPREG;
dadf55f2 2885 }
2886 else
2887 #endif
535d208a 2888 emit_cmpimm(addr,RAM_SIZE);
2889 jaddr=(int)out;
2890 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2891 // Hint to branch predictor that the branch is unlikely to be taken
2892 if(rs1[i]>=28)
2893 emit_jno_unlikely(0);
2894 else
57871462 2895 #endif
535d208a 2896 emit_jno(0);
57871462 2897 }
535d208a 2898 }
2899 }else{ // using tlb
2900 int x=0;
2901 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2902 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2903 map=get_reg(i_regs->regmap,TLREG);
2904 assert(map>=0);
ea3d2e6e 2905 reglist&=~(1<<map);
535d208a 2906 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2907 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2908 }
2909 int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2910 if (opcode[i]==0x20) { // LB
2911 if(!c||memtarget) {
2912 if(!dummy) {
57871462 2913 #ifdef HOST_IMM_ADDR32
2914 if(c)
2915 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2916 else
2917 #endif
2918 {
2919 //emit_xorimm(addr,3,tl);
2920 //gen_tlb_addr_r(tl,map);
2921 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
535d208a 2922 int x=0,a=tl;
2002a1db 2923#ifdef BIG_ENDIAN_MIPS
57871462 2924 if(!c) emit_xorimm(addr,3,tl);
2925 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2926#else
535d208a 2927 if(!c) a=addr;
dadf55f2 2928#endif
b1570849 2929 if(fastload_reg_override) a=fastload_reg_override;
2930
535d208a 2931 emit_movsbl_indexed_tlb(x,a,map,tl);
57871462 2932 }
57871462 2933 }
535d208a 2934 if(jaddr)
2935 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2936 }
535d208a 2937 else
2938 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2939 }
2940 if (opcode[i]==0x21) { // LH
2941 if(!c||memtarget) {
2942 if(!dummy) {
57871462 2943 #ifdef HOST_IMM_ADDR32
2944 if(c)
2945 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2946 else
2947 #endif
2948 {
535d208a 2949 int x=0,a=tl;
2002a1db 2950#ifdef BIG_ENDIAN_MIPS
57871462 2951 if(!c) emit_xorimm(addr,2,tl);
2952 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2953#else
535d208a 2954 if(!c) a=addr;
dadf55f2 2955#endif
b1570849 2956 if(fastload_reg_override) a=fastload_reg_override;
57871462 2957 //#ifdef
2958 //emit_movswl_indexed_tlb(x,tl,map,tl);
2959 //else
2960 if(map>=0) {
535d208a 2961 gen_tlb_addr_r(a,map);
2962 emit_movswl_indexed(x,a,tl);
2963 }else{
2964 #ifdef RAM_OFFSET
2965 emit_movswl_indexed(x,a,tl);
2966 #else
2967 emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2968 #endif
2969 }
57871462 2970 }
57871462 2971 }
535d208a 2972 if(jaddr)
2973 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2974 }
535d208a 2975 else
2976 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2977 }
2978 if (opcode[i]==0x23) { // LW
2979 if(!c||memtarget) {
2980 if(!dummy) {
dadf55f2 2981 int a=addr;
b1570849 2982 if(fastload_reg_override) a=fastload_reg_override;
57871462 2983 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2984 #ifdef HOST_IMM_ADDR32
2985 if(c)
2986 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2987 else
2988 #endif
dadf55f2 2989 emit_readword_indexed_tlb(0,a,map,tl);
57871462 2990 }
535d208a 2991 if(jaddr)
2992 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 2993 }
535d208a 2994 else
2995 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2996 }
2997 if (opcode[i]==0x24) { // LBU
2998 if(!c||memtarget) {
2999 if(!dummy) {
57871462 3000 #ifdef HOST_IMM_ADDR32
3001 if(c)
3002 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
3003 else
3004 #endif
3005 {
3006 //emit_xorimm(addr,3,tl);
3007 //gen_tlb_addr_r(tl,map);
3008 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
535d208a 3009 int x=0,a=tl;
2002a1db 3010#ifdef BIG_ENDIAN_MIPS
57871462 3011 if(!c) emit_xorimm(addr,3,tl);
3012 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 3013#else
535d208a 3014 if(!c) a=addr;
dadf55f2 3015#endif
b1570849 3016 if(fastload_reg_override) a=fastload_reg_override;
3017
535d208a 3018 emit_movzbl_indexed_tlb(x,a,map,tl);
57871462 3019 }
57871462 3020 }
535d208a 3021 if(jaddr)
3022 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 3023 }
535d208a 3024 else
3025 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3026 }
3027 if (opcode[i]==0x25) { // LHU
3028 if(!c||memtarget) {
3029 if(!dummy) {
57871462 3030 #ifdef HOST_IMM_ADDR32
3031 if(c)
3032 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
3033 else
3034 #endif
3035 {
535d208a 3036 int x=0,a=tl;
2002a1db 3037#ifdef BIG_ENDIAN_MIPS
57871462 3038 if(!c) emit_xorimm(addr,2,tl);
3039 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 3040#else
535d208a 3041 if(!c) a=addr;
dadf55f2 3042#endif
b1570849 3043 if(fastload_reg_override) a=fastload_reg_override;
57871462 3044 //#ifdef
3045 //emit_movzwl_indexed_tlb(x,tl,map,tl);
3046 //#else
3047 if(map>=0) {
535d208a 3048 gen_tlb_addr_r(a,map);
3049 emit_movzwl_indexed(x,a,tl);
3050 }else{
3051 #ifdef RAM_OFFSET
3052 emit_movzwl_indexed(x,a,tl);
3053 #else
3054 emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
3055 #endif
3056 }
57871462 3057 }
3058 }
535d208a 3059 if(jaddr)
3060 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 3061 }
535d208a 3062 else
3063 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3064 }
3065 if (opcode[i]==0x27) { // LWU
3066 assert(th>=0);
3067 if(!c||memtarget) {
3068 if(!dummy) {
dadf55f2 3069 int a=addr;
b1570849 3070 if(fastload_reg_override) a=fastload_reg_override;
57871462 3071 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3072 #ifdef HOST_IMM_ADDR32
3073 if(c)
3074 emit_readword_tlb(constmap[i][s]+offset,map,tl);
3075 else
3076 #endif
dadf55f2 3077 emit_readword_indexed_tlb(0,a,map,tl);
57871462 3078 }
535d208a 3079 if(jaddr)
3080 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3081 }
3082 else {
3083 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
57871462 3084 }
535d208a 3085 emit_zeroreg(th);
3086 }
3087 if (opcode[i]==0x37) { // LD
3088 if(!c||memtarget) {
3089 if(!dummy) {
dadf55f2 3090 int a=addr;
b1570849 3091 if(fastload_reg_override) a=fastload_reg_override;
57871462 3092 //gen_tlb_addr_r(tl,map);
3093 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3094 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3095 #ifdef HOST_IMM_ADDR32
3096 if(c)
3097 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3098 else
3099 #endif
dadf55f2 3100 emit_readdword_indexed_tlb(0,a,map,th,tl);
57871462 3101 }
535d208a 3102 if(jaddr)
3103 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
57871462 3104 }
535d208a 3105 else
3106 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
57871462 3107 }
535d208a 3108 }
3109 //emit_storereg(rt1[i],tl); // DEBUG
57871462 3110 //if(opcode[i]==0x23)
3111 //if(opcode[i]==0x24)
3112 //if(opcode[i]==0x23||opcode[i]==0x24)
3113 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3114 {
3115 //emit_pusha();
3116 save_regs(0x100f);
3117 emit_readword((int)&last_count,ECX);
3118 #ifdef __i386__
3119 if(get_reg(i_regs->regmap,CCREG)<0)
3120 emit_loadreg(CCREG,HOST_CCREG);
3121 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3122 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3123 emit_writeword(HOST_CCREG,(int)&Count);
3124 #endif
3125 #ifdef __arm__
3126 if(get_reg(i_regs->regmap,CCREG)<0)
3127 emit_loadreg(CCREG,0);
3128 else
3129 emit_mov(HOST_CCREG,0);
3130 emit_add(0,ECX,0);
3131 emit_addimm(0,2*ccadj[i],0);
3132 emit_writeword(0,(int)&Count);
3133 #endif
3134 emit_call((int)memdebug);
3135 //emit_popa();
3136 restore_regs(0x100f);
3137 }/**/
3138}
3139
3140#ifndef loadlr_assemble
3141void loadlr_assemble(int i,struct regstat *i_regs)
3142{
3143 printf("Need loadlr_assemble for this architecture.\n");
3144 exit(1);
3145}
3146#endif
3147
3148void store_assemble(int i,struct regstat *i_regs)
3149{
3150 int s,th,tl,map=-1;
3151 int addr,temp;
3152 int offset;
3153 int jaddr=0,jaddr2,type;
666a299d 3154 int memtarget=0,c=0;
57871462 3155 int agr=AGEN1+(i&1);
b1570849 3156 int faststore_reg_override=0;
57871462 3157 u_int hr,reglist=0;
3158 th=get_reg(i_regs->regmap,rs2[i]|64);
3159 tl=get_reg(i_regs->regmap,rs2[i]);
3160 s=get_reg(i_regs->regmap,rs1[i]);
3161 temp=get_reg(i_regs->regmap,agr);
3162 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3163 offset=imm[i];
3164 if(s>=0) {
3165 c=(i_regs->wasconst>>s)&1;
af4ee1fe 3166 if(c) {
3167 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3168 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3169 }
57871462 3170 }
3171 assert(tl>=0);
3172 assert(temp>=0);
3173 for(hr=0;hr<HOST_REGS;hr++) {
3174 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3175 }
3176 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3177 if(offset||s<0||c) addr=temp;
3178 else addr=s;
3179 if(!using_tlb) {
3180 if(!c) {
dadf55f2 3181 #ifdef PCSX
3182 if(sp_in_mirror&&rs1[i]==29) {
3183 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
3184 emit_cmpimm(HOST_TEMPREG,RAM_SIZE);
b1570849 3185 faststore_reg_override=HOST_TEMPREG;
dadf55f2 3186 }
3187 else
3188 #endif
57871462 3189 #ifdef R29_HACK
3190 // Strmnnrmn's speed hack
4cb76aa4 3191 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
57871462 3192 #endif
4cb76aa4 3193 emit_cmpimm(addr,RAM_SIZE);
57871462 3194 #ifdef DESTRUCTIVE_SHIFT
3195 if(s==addr) emit_mov(s,temp);
3196 #endif
3197 #ifdef R29_HACK
dadf55f2 3198 memtarget=1;
4cb76aa4 3199 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
57871462 3200 #endif
3201 {
3202 jaddr=(int)out;
3203 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3204 // Hint to branch predictor that the branch is unlikely to be taken
3205 if(rs1[i]>=28)
3206 emit_jno_unlikely(0);
3207 else
3208 #endif
3209 emit_jno(0);
3210 }
3211 }
3212 }else{ // using tlb
3213 int x=0;
3214 if (opcode[i]==0x28) x=3; // SB
3215 if (opcode[i]==0x29) x=2; // SH
3216 map=get_reg(i_regs->regmap,TLREG);
3217 assert(map>=0);
ea3d2e6e 3218 reglist&=~(1<<map);
57871462 3219 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3220 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3221 }
3222
3223 if (opcode[i]==0x28) { // SB
3224 if(!c||memtarget) {
97a238a6 3225 int x=0,a=temp;
2002a1db 3226#ifdef BIG_ENDIAN_MIPS
57871462 3227 if(!c) emit_xorimm(addr,3,temp);
3228 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 3229#else
97a238a6 3230 if(!c) a=addr;
dadf55f2 3231#endif
b1570849 3232 if(faststore_reg_override) a=faststore_reg_override;
57871462 3233 //gen_tlb_addr_w(temp,map);
3234 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
97a238a6 3235 emit_writebyte_indexed_tlb(tl,x,a,map,a);
57871462 3236 }
3237 type=STOREB_STUB;
3238 }
3239 if (opcode[i]==0x29) { // SH
3240 if(!c||memtarget) {
97a238a6 3241 int x=0,a=temp;
2002a1db 3242#ifdef BIG_ENDIAN_MIPS
57871462 3243 if(!c) emit_xorimm(addr,2,temp);
3244 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 3245#else
97a238a6 3246 if(!c) a=addr;
dadf55f2 3247#endif
b1570849 3248 if(faststore_reg_override) a=faststore_reg_override;
57871462 3249 //#ifdef
3250 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3251 //#else
3252 if(map>=0) {
97a238a6 3253 gen_tlb_addr_w(a,map);
3254 emit_writehword_indexed(tl,x,a);
57871462 3255 }else
97a238a6 3256 emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
57871462 3257 }
3258 type=STOREH_STUB;
3259 }
3260 if (opcode[i]==0x2B) { // SW
dadf55f2 3261 if(!c||memtarget) {
3262 int a=addr;
b1570849 3263 if(faststore_reg_override) a=faststore_reg_override;
57871462 3264 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
dadf55f2 3265 emit_writeword_indexed_tlb(tl,0,a,map,temp);
3266 }
57871462 3267 type=STOREW_STUB;
3268 }
3269 if (opcode[i]==0x3F) { // SD
3270 if(!c||memtarget) {
dadf55f2 3271 int a=addr;
b1570849 3272 if(faststore_reg_override) a=faststore_reg_override;
57871462 3273 if(rs2[i]) {
3274 assert(th>=0);
3275 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3276 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
dadf55f2 3277 emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
57871462 3278 }else{
3279 // Store zero
3280 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3281 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
dadf55f2 3282 emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
57871462 3283 }
3284 }
3285 type=STORED_STUB;
3286 }
57871462 3287 if(!using_tlb) {
3288 if(!c||memtarget) {
3289 #ifdef DESTRUCTIVE_SHIFT
3290 // The x86 shift operation is 'destructive'; it overwrites the
3291 // source register, so we need to make a copy first and use that.
3292 addr=temp;
3293 #endif
3294 #if defined(HOST_IMM8)
3295 int ir=get_reg(i_regs->regmap,INVCP);
3296 assert(ir>=0);
3297 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3298 #else
3299 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3300 #endif
0bbd1454 3301 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3302 emit_callne(invalidate_addr_reg[addr]);
3303 #else
57871462 3304 jaddr2=(int)out;
3305 emit_jne(0);
3306 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
0bbd1454 3307 #endif
57871462 3308 }
3309 }
3eaa7048 3310 if(jaddr) {
3311 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3312 } else if(c&&!memtarget) {
3313 inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3314 }
57871462 3315 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3316 //if(opcode[i]==0x2B || opcode[i]==0x28)
3317 //if(opcode[i]==0x2B || opcode[i]==0x29)
3318 //if(opcode[i]==0x2B)
3319 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3320 {
28d74ee8 3321 #ifdef __i386__
3322 emit_pusha();
3323 #endif
3324 #ifdef __arm__
57871462 3325 save_regs(0x100f);
28d74ee8 3326 #endif
57871462 3327 emit_readword((int)&last_count,ECX);
3328 #ifdef __i386__
3329 if(get_reg(i_regs->regmap,CCREG)<0)
3330 emit_loadreg(CCREG,HOST_CCREG);
3331 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3332 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3333 emit_writeword(HOST_CCREG,(int)&Count);
3334 #endif
3335 #ifdef __arm__
3336 if(get_reg(i_regs->regmap,CCREG)<0)
3337 emit_loadreg(CCREG,0);
3338 else
3339 emit_mov(HOST_CCREG,0);
3340 emit_add(0,ECX,0);
3341 emit_addimm(0,2*ccadj[i],0);
3342 emit_writeword(0,(int)&Count);
3343 #endif
3344 emit_call((int)memdebug);
28d74ee8 3345 #ifdef __i386__
3346 emit_popa();
3347 #endif
3348 #ifdef __arm__
57871462 3349 restore_regs(0x100f);
28d74ee8 3350 #endif
57871462 3351 }/**/
3352}
3353
3354void storelr_assemble(int i,struct regstat *i_regs)
3355{
3356 int s,th,tl;
3357 int temp;
3358 int temp2;
3359 int offset;
3360 int jaddr=0,jaddr2;
3361 int case1,case2,case3;
3362 int done0,done1,done2;
af4ee1fe 3363 int memtarget=0,c=0;
fab5d06d 3364 int agr=AGEN1+(i&1);
57871462 3365 u_int hr,reglist=0;
3366 th=get_reg(i_regs->regmap,rs2[i]|64);
3367 tl=get_reg(i_regs->regmap,rs2[i]);
3368 s=get_reg(i_regs->regmap,rs1[i]);
fab5d06d 3369 temp=get_reg(i_regs->regmap,agr);
3370 if(temp<0) temp=get_reg(i_regs->regmap,-1);
57871462 3371 offset=imm[i];
3372 if(s>=0) {
3373 c=(i_regs->isconst>>s)&1;
af4ee1fe 3374 if(c) {
3375 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3376 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3377 }
57871462 3378 }
3379 assert(tl>=0);
3380 for(hr=0;hr<HOST_REGS;hr++) {
3381 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3382 }
535d208a 3383 assert(temp>=0);
3384 if(!using_tlb) {
3385 if(!c) {
3386 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3387 if(!offset&&s!=temp) emit_mov(s,temp);
3388 jaddr=(int)out;
3389 emit_jno(0);
3390 }
3391 else
3392 {
3393 if(!memtarget||!rs1[i]) {
57871462 3394 jaddr=(int)out;
3395 emit_jmp(0);
3396 }
57871462 3397 }
535d208a 3398 #ifdef RAM_OFFSET
3399 int map=get_reg(i_regs->regmap,ROREG);
3400 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3401 gen_tlb_addr_w(temp,map);
3402 #else
3403 if((u_int)rdram!=0x80000000)
3404 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3405 #endif
3406 }else{ // using tlb
3407 int map=get_reg(i_regs->regmap,TLREG);
3408 assert(map>=0);
ea3d2e6e 3409 reglist&=~(1<<map);
535d208a 3410 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3411 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3412 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3413 if(!jaddr&&!memtarget) {
3414 jaddr=(int)out;
3415 emit_jmp(0);
57871462 3416 }
535d208a 3417 gen_tlb_addr_w(temp,map);
3418 }
3419
3420 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3421 temp2=get_reg(i_regs->regmap,FTEMP);
3422 if(!rs2[i]) temp2=th=tl;
3423 }
57871462 3424
2002a1db 3425#ifndef BIG_ENDIAN_MIPS
3426 emit_xorimm(temp,3,temp);
3427#endif
535d208a 3428 emit_testimm(temp,2);
3429 case2=(int)out;
3430 emit_jne(0);
3431 emit_testimm(temp,1);
3432 case1=(int)out;
3433 emit_jne(0);
3434 // 0
3435 if (opcode[i]==0x2A) { // SWL
3436 emit_writeword_indexed(tl,0,temp);
3437 }
3438 if (opcode[i]==0x2E) { // SWR
3439 emit_writebyte_indexed(tl,3,temp);
3440 }
3441 if (opcode[i]==0x2C) { // SDL
3442 emit_writeword_indexed(th,0,temp);
3443 if(rs2[i]) emit_mov(tl,temp2);
3444 }
3445 if (opcode[i]==0x2D) { // SDR
3446 emit_writebyte_indexed(tl,3,temp);
3447 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3448 }
3449 done0=(int)out;
3450 emit_jmp(0);
3451 // 1
3452 set_jump_target(case1,(int)out);
3453 if (opcode[i]==0x2A) { // SWL
3454 // Write 3 msb into three least significant bytes
3455 if(rs2[i]) emit_rorimm(tl,8,tl);
3456 emit_writehword_indexed(tl,-1,temp);
3457 if(rs2[i]) emit_rorimm(tl,16,tl);
3458 emit_writebyte_indexed(tl,1,temp);
3459 if(rs2[i]) emit_rorimm(tl,8,tl);
3460 }
3461 if (opcode[i]==0x2E) { // SWR
3462 // Write two lsb into two most significant bytes
3463 emit_writehword_indexed(tl,1,temp);
3464 }
3465 if (opcode[i]==0x2C) { // SDL
3466 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3467 // Write 3 msb into three least significant bytes
3468 if(rs2[i]) emit_rorimm(th,8,th);
3469 emit_writehword_indexed(th,-1,temp);
3470 if(rs2[i]) emit_rorimm(th,16,th);
3471 emit_writebyte_indexed(th,1,temp);
3472 if(rs2[i]) emit_rorimm(th,8,th);
3473 }
3474 if (opcode[i]==0x2D) { // SDR
3475 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3476 // Write two lsb into two most significant bytes
3477 emit_writehword_indexed(tl,1,temp);
3478 }
3479 done1=(int)out;
3480 emit_jmp(0);
3481 // 2
3482 set_jump_target(case2,(int)out);
3483 emit_testimm(temp,1);
3484 case3=(int)out;
3485 emit_jne(0);
3486 if (opcode[i]==0x2A) { // SWL
3487 // Write two msb into two least significant bytes
3488 if(rs2[i]) emit_rorimm(tl,16,tl);
3489 emit_writehword_indexed(tl,-2,temp);
3490 if(rs2[i]) emit_rorimm(tl,16,tl);
3491 }
3492 if (opcode[i]==0x2E) { // SWR
3493 // Write 3 lsb into three most significant bytes
3494 emit_writebyte_indexed(tl,-1,temp);
3495 if(rs2[i]) emit_rorimm(tl,8,tl);
3496 emit_writehword_indexed(tl,0,temp);
3497 if(rs2[i]) emit_rorimm(tl,24,tl);
3498 }
3499 if (opcode[i]==0x2C) { // SDL
3500 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3501 // Write two msb into two least significant bytes
3502 if(rs2[i]) emit_rorimm(th,16,th);
3503 emit_writehword_indexed(th,-2,temp);
3504 if(rs2[i]) emit_rorimm(th,16,th);
3505 }
3506 if (opcode[i]==0x2D) { // SDR
3507 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3508 // Write 3 lsb into three most significant bytes
3509 emit_writebyte_indexed(tl,-1,temp);
3510 if(rs2[i]) emit_rorimm(tl,8,tl);
3511 emit_writehword_indexed(tl,0,temp);
3512 if(rs2[i]) emit_rorimm(tl,24,tl);
3513 }
3514 done2=(int)out;
3515 emit_jmp(0);
3516 // 3
3517 set_jump_target(case3,(int)out);
3518 if (opcode[i]==0x2A) { // SWL
3519 // Write msb into least significant byte
3520 if(rs2[i]) emit_rorimm(tl,24,tl);
3521 emit_writebyte_indexed(tl,-3,temp);
3522 if(rs2[i]) emit_rorimm(tl,8,tl);
3523 }
3524 if (opcode[i]==0x2E) { // SWR
3525 // Write entire word
3526 emit_writeword_indexed(tl,-3,temp);
3527 }
3528 if (opcode[i]==0x2C) { // SDL
3529 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3530 // Write msb into least significant byte
3531 if(rs2[i]) emit_rorimm(th,24,th);
3532 emit_writebyte_indexed(th,-3,temp);
3533 if(rs2[i]) emit_rorimm(th,8,th);
3534 }
3535 if (opcode[i]==0x2D) { // SDR
3536 if(rs2[i]) emit_mov(th,temp2);
3537 // Write entire word
3538 emit_writeword_indexed(tl,-3,temp);
3539 }
3540 set_jump_target(done0,(int)out);
3541 set_jump_target(done1,(int)out);
3542 set_jump_target(done2,(int)out);
3543 if (opcode[i]==0x2C) { // SDL
3544 emit_testimm(temp,4);
57871462 3545 done0=(int)out;
57871462 3546 emit_jne(0);
535d208a 3547 emit_andimm(temp,~3,temp);
3548 emit_writeword_indexed(temp2,4,temp);
3549 set_jump_target(done0,(int)out);
3550 }
3551 if (opcode[i]==0x2D) { // SDR
3552 emit_testimm(temp,4);
3553 done0=(int)out;
3554 emit_jeq(0);
3555 emit_andimm(temp,~3,temp);
3556 emit_writeword_indexed(temp2,-4,temp);
57871462 3557 set_jump_target(done0,(int)out);
57871462 3558 }
535d208a 3559 if(!c||!memtarget)
3560 add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
57871462 3561 if(!using_tlb) {
535d208a 3562 #ifdef RAM_OFFSET
3563 int map=get_reg(i_regs->regmap,ROREG);
3564 if(map<0) map=HOST_TEMPREG;
3565 gen_orig_addr_w(temp,map);
3566 #else
57871462 3567 emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
535d208a 3568 #endif
57871462 3569 #if defined(HOST_IMM8)
3570 int ir=get_reg(i_regs->regmap,INVCP);
3571 assert(ir>=0);
3572 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3573 #else
3574 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3575 #endif
535d208a 3576 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3577 emit_callne(invalidate_addr_reg[temp]);
3578 #else
57871462 3579 jaddr2=(int)out;
3580 emit_jne(0);
3581 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
535d208a 3582 #endif
57871462 3583 }
3584 /*
3585 emit_pusha();
3586 //save_regs(0x100f);
3587 emit_readword((int)&last_count,ECX);
3588 if(get_reg(i_regs->regmap,CCREG)<0)
3589 emit_loadreg(CCREG,HOST_CCREG);
3590 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3591 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3592 emit_writeword(HOST_CCREG,(int)&Count);
3593 emit_call((int)memdebug);
3594 emit_popa();
3595 //restore_regs(0x100f);
3596 /**/
3597}
3598
3599void c1ls_assemble(int i,struct regstat *i_regs)
3600{
3d624f89 3601#ifndef DISABLE_COP1
57871462 3602 int s,th,tl;
3603 int temp,ar;
3604 int map=-1;
3605 int offset;
3606 int c=0;
3607 int jaddr,jaddr2=0,jaddr3,type;
3608 int agr=AGEN1+(i&1);
3609 u_int hr,reglist=0;
3610 th=get_reg(i_regs->regmap,FTEMP|64);
3611 tl=get_reg(i_regs->regmap,FTEMP);
3612 s=get_reg(i_regs->regmap,rs1[i]);
3613 temp=get_reg(i_regs->regmap,agr);
3614 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3615 offset=imm[i];
3616 assert(tl>=0);
3617 assert(rs1[i]>0);
3618 assert(temp>=0);
3619 for(hr=0;hr<HOST_REGS;hr++) {
3620 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3621 }
3622 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3623 if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3624 {
3625 // Loads use a temporary register which we need to save
3626 reglist|=1<<temp;
3627 }
3628 if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3629 ar=temp;
3630 else // LWC1/LDC1
3631 ar=tl;
3632 //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3633 //else c=(i_regs->wasconst>>s)&1;
3634 if(s>=0) c=(i_regs->wasconst>>s)&1;
3635 // Check cop1 unusable
3636 if(!cop1_usable) {
3637 signed char rs=get_reg(i_regs->regmap,CSREG);
3638 assert(rs>=0);
3639 emit_testimm(rs,0x20000000);
3640 jaddr=(int)out;
3641 emit_jeq(0);
3642 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3643 cop1_usable=1;
3644 }
3645 if (opcode[i]==0x39) { // SWC1 (get float address)
3646 emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],tl);
3647 }
3648 if (opcode[i]==0x3D) { // SDC1 (get double address)
3649 emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],tl);
3650 }
3651 // Generate address + offset
3652 if(!using_tlb) {
3653 if(!c)
4cb76aa4 3654 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
57871462 3655 }
3656 else
3657 {
3658 map=get_reg(i_regs->regmap,TLREG);
3659 assert(map>=0);
ea3d2e6e 3660 reglist&=~(1<<map);
57871462 3661 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3662 map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3663 }
3664 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3665 map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3666 }
3667 }
3668 if (opcode[i]==0x39) { // SWC1 (read float)
3669 emit_readword_indexed(0,tl,tl);
3670 }
3671 if (opcode[i]==0x3D) { // SDC1 (read double)
3672 emit_readword_indexed(4,tl,th);
3673 emit_readword_indexed(0,tl,tl);
3674 }
3675 if (opcode[i]==0x31) { // LWC1 (get target address)
3676 emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],temp);
3677 }
3678 if (opcode[i]==0x35) { // LDC1 (get target address)
3679 emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],temp);
3680 }
3681 if(!using_tlb) {
3682 if(!c) {
3683 jaddr2=(int)out;
3684 emit_jno(0);
3685 }
4cb76aa4 3686 else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
57871462 3687 jaddr2=(int)out;
3688 emit_jmp(0); // inline_readstub/inline_writestub? Very rare case
3689 }
3690 #ifdef DESTRUCTIVE_SHIFT
3691 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3692 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3693 }
3694 #endif
3695 }else{
3696 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3697 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3698 }
3699 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3700 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3701 }
3702 }
3703 if (opcode[i]==0x31) { // LWC1
3704 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3705 //gen_tlb_addr_r(ar,map);
3706 //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3707 #ifdef HOST_IMM_ADDR32
3708 if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3709 else
3710 #endif
3711 emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3712 type=LOADW_STUB;
3713 }
3714 if (opcode[i]==0x35) { // LDC1
3715 assert(th>=0);
3716 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3717 //gen_tlb_addr_r(ar,map);
3718 //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3719 //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3720 #ifdef HOST_IMM_ADDR32
3721 if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3722 else
3723 #endif
3724 emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3725 type=LOADD_STUB;
3726 }
3727 if (opcode[i]==0x39) { // SWC1
3728 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3729 emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3730 type=STOREW_STUB;
3731 }
3732 if (opcode[i]==0x3D) { // SDC1
3733 assert(th>=0);
3734 //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3735 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3736 emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3737 type=STORED_STUB;
3738 }
3739 if(!using_tlb) {
3740 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3741 #ifndef DESTRUCTIVE_SHIFT
3742 temp=offset||c||s<0?ar:s;
3743 #endif
3744 #if defined(HOST_IMM8)
3745 int ir=get_reg(i_regs->regmap,INVCP);
3746 assert(ir>=0);
3747 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3748 #else
3749 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3750 #endif
0bbd1454 3751 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3752 emit_callne(invalidate_addr_reg[temp]);
3753 #else
57871462 3754 jaddr3=(int)out;
3755 emit_jne(0);
3756 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
0bbd1454 3757 #endif
57871462 3758 }
3759 }
3760 if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3761 if (opcode[i]==0x31) { // LWC1 (write float)
3762 emit_writeword_indexed(tl,0,temp);
3763 }
3764 if (opcode[i]==0x35) { // LDC1 (write double)
3765 emit_writeword_indexed(th,4,temp);
3766 emit_writeword_indexed(tl,0,temp);
3767 }
3768 //if(opcode[i]==0x39)
3769 /*if(opcode[i]==0x39||opcode[i]==0x31)
3770 {
3771 emit_pusha();
3772 emit_readword((int)&last_count,ECX);
3773 if(get_reg(i_regs->regmap,CCREG)<0)
3774 emit_loadreg(CCREG,HOST_CCREG);
3775 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3776 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3777 emit_writeword(HOST_CCREG,(int)&Count);
3778 emit_call((int)memdebug);
3779 emit_popa();
3780 }/**/
3d624f89 3781#else
3782 cop1_unusable(i, i_regs);
3783#endif
57871462 3784}
3785
b9b61529 3786void c2ls_assemble(int i,struct regstat *i_regs)
3787{
3788 int s,tl;
3789 int ar;
3790 int offset;
1fd1aceb 3791 int memtarget=0,c=0;
c2e3bd42 3792 int jaddr2=0,jaddr3,type;
b9b61529 3793 int agr=AGEN1+(i&1);
3794 u_int hr,reglist=0;
3795 u_int copr=(source[i]>>16)&0x1f;
3796 s=get_reg(i_regs->regmap,rs1[i]);
3797 tl=get_reg(i_regs->regmap,FTEMP);
3798 offset=imm[i];
3799 assert(rs1[i]>0);
3800 assert(tl>=0);
3801 assert(!using_tlb);
3802
3803 for(hr=0;hr<HOST_REGS;hr++) {
3804 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3805 }
3806 if(i_regs->regmap[HOST_CCREG]==CCREG)
3807 reglist&=~(1<<HOST_CCREG);
3808
3809 // get the address
3810 if (opcode[i]==0x3a) { // SWC2
3811 ar=get_reg(i_regs->regmap,agr);
3812 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3813 reglist|=1<<ar;
3814 } else { // LWC2
3815 ar=tl;
3816 }
1fd1aceb 3817 if(s>=0) c=(i_regs->wasconst>>s)&1;
3818 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
b9b61529 3819 if (!offset&&!c&&s>=0) ar=s;
3820 assert(ar>=0);
3821
3822 if (opcode[i]==0x3a) { // SWC2
3823 cop2_get_dreg(copr,tl,HOST_TEMPREG);
1fd1aceb 3824 type=STOREW_STUB;
b9b61529 3825 }
1fd1aceb 3826 else
b9b61529 3827 type=LOADW_STUB;
1fd1aceb 3828
3829 if(c&&!memtarget) {
3830 jaddr2=(int)out;
3831 emit_jmp(0); // inline_readstub/inline_writestub?
b9b61529 3832 }
1fd1aceb 3833 else {
3834 if(!c) {
3835 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3836 jaddr2=(int)out;
3837 emit_jno(0);
3838 }
3839 if (opcode[i]==0x32) { // LWC2
3840 #ifdef HOST_IMM_ADDR32
3841 if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3842 else
3843 #endif
3844 emit_readword_indexed(0,ar,tl);
3845 }
3846 if (opcode[i]==0x3a) { // SWC2
3847 #ifdef DESTRUCTIVE_SHIFT
3848 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3849 #endif
3850 emit_writeword_indexed(tl,0,ar);
3851 }
b9b61529 3852 }
3853 if(jaddr2)
3854 add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3855 if (opcode[i]==0x3a) { // SWC2
3856#if defined(HOST_IMM8)
3857 int ir=get_reg(i_regs->regmap,INVCP);
3858 assert(ir>=0);
3859 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3860#else
3861 emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3862#endif
0bbd1454 3863 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3864 emit_callne(invalidate_addr_reg[ar]);
3865 #else
b9b61529 3866 jaddr3=(int)out;
3867 emit_jne(0);
3868 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
0bbd1454 3869 #endif
b9b61529 3870 }
3871 if (opcode[i]==0x32) { // LWC2
3872 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3873 }
3874}
3875
57871462 3876#ifndef multdiv_assemble
3877void multdiv_assemble(int i,struct regstat *i_regs)
3878{
3879 printf("Need multdiv_assemble for this architecture.\n");
3880 exit(1);
3881}
3882#endif
3883
3884void mov_assemble(int i,struct regstat *i_regs)
3885{
3886 //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3887 //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
57871462 3888 if(rt1[i]) {
3889 signed char sh,sl,th,tl;
3890 th=get_reg(i_regs->regmap,rt1[i]|64);
3891 tl=get_reg(i_regs->regmap,rt1[i]);
3892 //assert(tl>=0);
3893 if(tl>=0) {
3894 sh=get_reg(i_regs->regmap,rs1[i]|64);
3895 sl=get_reg(i_regs->regmap,rs1[i]);
3896 if(sl>=0) emit_mov(sl,tl);
3897 else emit_loadreg(rs1[i],tl);
3898 if(th>=0) {
3899 if(sh>=0) emit_mov(sh,th);
3900 else emit_loadreg(rs1[i]|64,th);
3901 }
3902 }
3903 }
3904}
3905
3906#ifndef fconv_assemble
3907void fconv_assemble(int i,struct regstat *i_regs)
3908{
3909 printf("Need fconv_assemble for this architecture.\n");
3910 exit(1);
3911}
3912#endif
3913
3914#if 0
3915void float_assemble(int i,struct regstat *i_regs)
3916{
3917 printf("Need float_assemble for this architecture.\n");
3918 exit(1);
3919}
3920#endif
3921
3922void syscall_assemble(int i,struct regstat *i_regs)
3923{
3924 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3925 assert(ccreg==HOST_CCREG);
3926 assert(!is_delayslot);
3927 emit_movimm(start+i*4,EAX); // Get PC
3928 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
7139f3c8 3929 emit_jmp((int)jump_syscall_hle); // XXX
3930}
3931
3932void hlecall_assemble(int i,struct regstat *i_regs)
3933{
3934 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3935 assert(ccreg==HOST_CCREG);
3936 assert(!is_delayslot);
3937 emit_movimm(start+i*4+4,0); // Get PC
67ba0fb4 3938 emit_movimm((int)psxHLEt[source[i]&7],1);
7139f3c8 3939 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // XXX
67ba0fb4 3940 emit_jmp((int)jump_hlecall);
57871462 3941}
3942
1e973cb0 3943void intcall_assemble(int i,struct regstat *i_regs)
3944{
3945 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3946 assert(ccreg==HOST_CCREG);
3947 assert(!is_delayslot);
3948 emit_movimm(start+i*4,0); // Get PC
3949 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3950 emit_jmp((int)jump_intcall);
3951}
3952
57871462 3953void ds_assemble(int i,struct regstat *i_regs)
3954{
3955 is_delayslot=1;
3956 switch(itype[i]) {
3957 case ALU:
3958 alu_assemble(i,i_regs);break;
3959 case IMM16:
3960 imm16_assemble(i,i_regs);break;
3961 case SHIFT:
3962 shift_assemble(i,i_regs);break;
3963 case SHIFTIMM:
3964 shiftimm_assemble(i,i_regs);break;
3965 case LOAD:
3966 load_assemble(i,i_regs);break;
3967 case LOADLR:
3968 loadlr_assemble(i,i_regs);break;
3969 case STORE:
3970 store_assemble(i,i_regs);break;
3971 case STORELR:
3972 storelr_assemble(i,i_regs);break;
3973 case COP0:
3974 cop0_assemble(i,i_regs);break;
3975 case COP1:
3976 cop1_assemble(i,i_regs);break;
3977 case C1LS:
3978 c1ls_assemble(i,i_regs);break;
b9b61529 3979 case COP2:
3980 cop2_assemble(i,i_regs);break;
3981 case C2LS:
3982 c2ls_assemble(i,i_regs);break;
3983 case C2OP:
3984 c2op_assemble(i,i_regs);break;
57871462 3985 case FCONV:
3986 fconv_assemble(i,i_regs);break;
3987 case FLOAT:
3988 float_assemble(i,i_regs);break;
3989 case FCOMP:
3990 fcomp_assemble(i,i_regs);break;
3991 case MULTDIV:
3992 multdiv_assemble(i,i_regs);break;
3993 case MOV:
3994 mov_assemble(i,i_regs);break;
3995 case SYSCALL:
7139f3c8 3996 case HLECALL:
1e973cb0 3997 case INTCALL:
57871462 3998 case SPAN:
3999 case UJUMP:
4000 case RJUMP:
4001 case CJUMP:
4002 case SJUMP:
4003 case FJUMP:
4004 printf("Jump in the delay slot. This is probably a bug.\n");
4005 }
4006 is_delayslot=0;
4007}
4008
4009// Is the branch target a valid internal jump?
4010int internal_branch(uint64_t i_is32,int addr)
4011{
4012 if(addr&1) return 0; // Indirect (register) jump
4013 if(addr>=start && addr<start+slen*4-4)
4014 {
4015 int t=(addr-start)>>2;
4016 // Delay slots are not valid branch targets
4017 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4018 // 64 -> 32 bit transition requires a recompile
4019 /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
4020 {
4021 if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
4022 else printf("optimizable: yes\n");
4023 }*/
4024 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
a28c6ce8 4025#ifndef FORCE32
57871462 4026 if(requires_32bit[t]&~i_is32) return 0;
a28c6ce8 4027 else
4028#endif
4029 return 1;
57871462 4030 }
4031 return 0;
4032}
4033
4034#ifndef wb_invalidate
4035void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
4036 uint64_t u,uint64_t uu)
4037{
4038 int hr;
4039 for(hr=0;hr<HOST_REGS;hr++) {
4040 if(hr!=EXCLUDE_REG) {
4041 if(pre[hr]!=entry[hr]) {
4042 if(pre[hr]>=0) {
4043 if((dirty>>hr)&1) {
4044 if(get_reg(entry,pre[hr])<0) {
4045 if(pre[hr]<64) {
4046 if(!((u>>pre[hr])&1)) {
4047 emit_storereg(pre[hr],hr);
4048 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
4049 emit_sarimm(hr,31,hr);
4050 emit_storereg(pre[hr]|64,hr);
4051 }
4052 }
4053 }else{
4054 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
4055 emit_storereg(pre[hr],hr);
4056 }
4057 }
4058 }
4059 }
4060 }
4061 }
4062 }
4063 }
4064 // Move from one register to another (no writeback)
4065 for(hr=0;hr<HOST_REGS;hr++) {
4066 if(hr!=EXCLUDE_REG) {
4067 if(pre[hr]!=entry[hr]) {
4068 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
4069 int nr;
4070 if((nr=get_reg(entry,pre[hr]))>=0) {
4071 emit_mov(hr,nr);
4072 }
4073 }
4074 }
4075 }
4076 }
4077}
4078#endif
4079
4080// Load the specified registers
4081// This only loads the registers given as arguments because
4082// we don't want to load things that will be overwritten
4083void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
4084{
4085 int hr;
4086 // Load 32-bit regs
4087 for(hr=0;hr<HOST_REGS;hr++) {
4088 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4089 if(entry[hr]!=regmap[hr]) {
4090 if(regmap[hr]==rs1||regmap[hr]==rs2)
4091 {
4092 if(regmap[hr]==0) {
4093 emit_zeroreg(hr);
4094 }
4095 else
4096 {
4097 emit_loadreg(regmap[hr],hr);
4098 }
4099 }
4100 }
4101 }
4102 }
4103 //Load 64-bit regs
4104 for(hr=0;hr<HOST_REGS;hr++) {
4105 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4106 if(entry[hr]!=regmap[hr]) {
4107 if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
4108 {
4109 assert(regmap[hr]!=64);
4110 if((is32>>(regmap[hr]&63))&1) {
4111 int lr=get_reg(regmap,regmap[hr]-64);
4112 if(lr>=0)
4113 emit_sarimm(lr,31,hr);
4114 else
4115 emit_loadreg(regmap[hr],hr);
4116 }
4117 else
4118 {
4119 emit_loadreg(regmap[hr],hr);
4120 }
4121 }
4122 }
4123 }
4124 }
4125}
4126
4127// Load registers prior to the start of a loop
4128// so that they are not loaded within the loop
4129static void loop_preload(signed char pre[],signed char entry[])
4130{
4131 int hr;
4132 for(hr=0;hr<HOST_REGS;hr++) {
4133 if(hr!=EXCLUDE_REG) {
4134 if(pre[hr]!=entry[hr]) {
4135 if(entry[hr]>=0) {
4136 if(get_reg(pre,entry[hr])<0) {
4137 assem_debug("loop preload:\n");
4138 //printf("loop preload: %d\n",hr);
4139 if(entry[hr]==0) {
4140 emit_zeroreg(hr);
4141 }
4142 else if(entry[hr]<TEMPREG)
4143 {
4144 emit_loadreg(entry[hr],hr);
4145 }
4146 else if(entry[hr]-64<TEMPREG)
4147 {
4148 emit_loadreg(entry[hr],hr);
4149 }
4150 }
4151 }
4152 }
4153 }
4154 }
4155}
4156
4157// Generate address for load/store instruction
b9b61529 4158// goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
57871462 4159void address_generation(int i,struct regstat *i_regs,signed char entry[])
4160{
b9b61529 4161 if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
5194fb95 4162 int ra=-1;
57871462 4163 int agr=AGEN1+(i&1);
4164 int mgr=MGEN1+(i&1);
4165 if(itype[i]==LOAD) {
4166 ra=get_reg(i_regs->regmap,rt1[i]);
535d208a 4167 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4168 assert(ra>=0);
57871462 4169 }
4170 if(itype[i]==LOADLR) {
4171 ra=get_reg(i_regs->regmap,FTEMP);
4172 }
4173 if(itype[i]==STORE||itype[i]==STORELR) {
4174 ra=get_reg(i_regs->regmap,agr);
4175 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4176 }
b9b61529 4177 if(itype[i]==C1LS||itype[i]==C2LS) {
4178 if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
57871462 4179 ra=get_reg(i_regs->regmap,FTEMP);
1fd1aceb 4180 else { // SWC1/SDC1/SWC2/SDC2
57871462 4181 ra=get_reg(i_regs->regmap,agr);
4182 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4183 }
4184 }
4185 int rs=get_reg(i_regs->regmap,rs1[i]);
4186 int rm=get_reg(i_regs->regmap,TLREG);
4187 if(ra>=0) {
4188 int offset=imm[i];
4189 int c=(i_regs->wasconst>>rs)&1;
4190 if(rs1[i]==0) {
4191 // Using r0 as a base address
4192 /*if(rm>=0) {
4193 if(!entry||entry[rm]!=mgr) {
4194 generate_map_const(offset,rm);
4195 } // else did it in the previous cycle
4196 }*/
4197 if(!entry||entry[ra]!=agr) {
4198 if (opcode[i]==0x22||opcode[i]==0x26) {
4199 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4200 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4201 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4202 }else{
4203 emit_movimm(offset,ra);
4204 }
4205 } // else did it in the previous cycle
4206 }
4207 else if(rs<0) {
4208 if(!entry||entry[ra]!=rs1[i])
4209 emit_loadreg(rs1[i],ra);
4210 //if(!entry||entry[ra]!=rs1[i])
4211 // printf("poor load scheduling!\n");
4212 }
4213 else if(c) {
4214 if(rm>=0) {
4215 if(!entry||entry[rm]!=mgr) {
b9b61529 4216 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
57871462 4217 // Stores to memory go thru the mapper to detect self-modifying
4218 // code, loads don't.
4219 if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
4cb76aa4 4220 (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
57871462 4221 generate_map_const(constmap[i][rs]+offset,rm);
4222 }else{
4223 if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
4224 generate_map_const(constmap[i][rs]+offset,rm);
4225 }
4226 }
4227 }
4228 if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
4229 if(!entry||entry[ra]!=agr) {
4230 if (opcode[i]==0x22||opcode[i]==0x26) {
4231 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4232 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4233 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4234 }else{
4235 #ifdef HOST_IMM_ADDR32
b9b61529 4236 if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
57871462 4237 (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4238 #endif
4239 emit_movimm(constmap[i][rs]+offset,ra);
4240 }
4241 } // else did it in the previous cycle
4242 } // else load_consts already did it
4243 }
4244 if(offset&&!c&&rs1[i]) {
4245 if(rs>=0) {
4246 emit_addimm(rs,offset,ra);
4247 }else{
4248 emit_addimm(ra,offset,ra);
4249 }
4250 }
4251 }
4252 }
4253 // Preload constants for next instruction
b9b61529 4254 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
57871462 4255 int agr,ra;
4256 #ifndef HOST_IMM_ADDR32
4257 // Mapper entry
4258 agr=MGEN1+((i+1)&1);
4259 ra=get_reg(i_regs->regmap,agr);
4260 if(ra>=0) {
4261 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4262 int offset=imm[i+1];
4263 int c=(regs[i+1].wasconst>>rs)&1;
4264 if(c) {
b9b61529 4265 if(itype[i+1]==STORE||itype[i+1]==STORELR
4266 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
57871462 4267 // Stores to memory go thru the mapper to detect self-modifying
4268 // code, loads don't.
4269 if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4cb76aa4 4270 (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
57871462 4271 generate_map_const(constmap[i+1][rs]+offset,ra);
4272 }else{
4273 if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4274 generate_map_const(constmap[i+1][rs]+offset,ra);
4275 }
4276 }
4277 /*else if(rs1[i]==0) {
4278 generate_map_const(offset,ra);
4279 }*/
4280 }
4281 #endif
4282 // Actual address
4283 agr=AGEN1+((i+1)&1);
4284 ra=get_reg(i_regs->regmap,agr);
4285 if(ra>=0) {
4286 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4287 int offset=imm[i+1];
4288 int c=(regs[i+1].wasconst>>rs)&1;
4289 if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4290 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4291 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4292 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4293 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4294 }else{
4295 #ifdef HOST_IMM_ADDR32
b9b61529 4296 if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
57871462 4297 (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4298 #endif
4299 emit_movimm(constmap[i+1][rs]+offset,ra);
4300 }
4301 }
4302 else if(rs1[i+1]==0) {
4303 // Using r0 as a base address
4304 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4305 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4306 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4307 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4308 }else{
4309 emit_movimm(offset,ra);
4310 }
4311 }
4312 }
4313 }
4314}
4315
4316int get_final_value(int hr, int i, int *value)
4317{
4318 int reg=regs[i].regmap[hr];
4319 while(i<slen-1) {
4320 if(regs[i+1].regmap[hr]!=reg) break;
4321 if(!((regs[i+1].isconst>>hr)&1)) break;
4322 if(bt[i+1]) break;
4323 i++;
4324 }
4325 if(i<slen-1) {
4326 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4327 *value=constmap[i][hr];
4328 return 1;
4329 }
4330 if(!bt[i+1]) {
4331 if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4332 // Load in delay slot, out-of-order execution
4333 if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4334 {
4335 #ifdef HOST_IMM_ADDR32
4336 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4337 #endif
4338 // Precompute load address
4339 *value=constmap[i][hr]+imm[i+2];
4340 return 1;
4341 }
4342 }
4343 if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4344 {
4345 #ifdef HOST_IMM_ADDR32
4346 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4347 #endif
4348 // Precompute load address
4349 *value=constmap[i][hr]+imm[i+1];
4350 //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4351 return 1;
4352 }
4353 }
4354 }
4355 *value=constmap[i][hr];
4356 //printf("c=%x\n",(int)constmap[i][hr]);
4357 if(i==slen-1) return 1;
4358 if(reg<64) {
4359 return !((unneeded_reg[i+1]>>reg)&1);
4360 }else{
4361 return !((unneeded_reg_upper[i+1]>>reg)&1);
4362 }
4363}
4364
4365// Load registers with known constants
4366void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4367{
4368 int hr;
4369 // Load 32-bit regs
4370 for(hr=0;hr<HOST_REGS;hr++) {
4371 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4372 //if(entry[hr]!=regmap[hr]) {
4373 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4374 if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4375 int value;
4376 if(get_final_value(hr,i,&value)) {
4377 if(value==0) {
4378 emit_zeroreg(hr);
4379 }
4380 else {
4381 emit_movimm(value,hr);
4382 }
4383 }
4384 }
4385 }
4386 }
4387 }
4388 // Load 64-bit regs
4389 for(hr=0;hr<HOST_REGS;hr++) {
4390 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4391 //if(entry[hr]!=regmap[hr]) {
4392 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4393 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4394 if((is32>>(regmap[hr]&63))&1) {
4395 int lr=get_reg(regmap,regmap[hr]-64);
4396 assert(lr>=0);
4397 emit_sarimm(lr,31,hr);
4398 }
4399 else
4400 {
4401 int value;
4402 if(get_final_value(hr,i,&value)) {
4403 if(value==0) {
4404 emit_zeroreg(hr);
4405 }
4406 else {
4407 emit_movimm(value,hr);
4408 }
4409 }
4410 }
4411 }
4412 }
4413 }
4414 }
4415}
4416void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4417{
4418 int hr;
4419 // Load 32-bit regs
4420 for(hr=0;hr<HOST_REGS;hr++) {
4421 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4422 if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4423 int value=constmap[i][hr];
4424 if(value==0) {
4425 emit_zeroreg(hr);
4426 }
4427 else {
4428 emit_movimm(value,hr);
4429 }
4430 }
4431 }
4432 }
4433 // Load 64-bit regs
4434 for(hr=0;hr<HOST_REGS;hr++) {
4435 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4436 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4437 if((is32>>(regmap[hr]&63))&1) {
4438 int lr=get_reg(regmap,regmap[hr]-64);
4439 assert(lr>=0);
4440 emit_sarimm(lr,31,hr);
4441 }
4442 else
4443 {
4444 int value=constmap[i][hr];
4445 if(value==0) {
4446 emit_zeroreg(hr);
4447 }
4448 else {
4449 emit_movimm(value,hr);
4450 }
4451 }
4452 }
4453 }
4454 }
4455}
4456
4457// Write out all dirty registers (except cycle count)
4458void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4459{
4460 int hr;
4461 for(hr=0;hr<HOST_REGS;hr++) {
4462 if(hr!=EXCLUDE_REG) {
4463 if(i_regmap[hr]>0) {
4464 if(i_regmap[hr]!=CCREG) {
4465 if((i_dirty>>hr)&1) {
4466 if(i_regmap[hr]<64) {
4467 emit_storereg(i_regmap[hr],hr);
24385cae 4468#ifndef FORCE32
57871462 4469 if( ((i_is32>>i_regmap[hr])&1) ) {
4470 #ifdef DESTRUCTIVE_WRITEBACK
4471 emit_sarimm(hr,31,hr);
4472 emit_storereg(i_regmap[hr]|64,hr);
4473 #else
4474 emit_sarimm(hr,31,HOST_TEMPREG);
4475 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4476 #endif
4477 }
24385cae 4478#endif
57871462 4479 }else{
4480 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4481 emit_storereg(i_regmap[hr],hr);
4482 }
4483 }
4484 }
4485 }
4486 }
4487 }
4488 }
4489}
4490// Write out dirty registers that we need to reload (pair with load_needed_regs)
4491// This writes the registers not written by store_regs_bt
4492void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4493{
4494 int hr;
4495 int t=(addr-start)>>2;
4496 for(hr=0;hr<HOST_REGS;hr++) {
4497 if(hr!=EXCLUDE_REG) {
4498 if(i_regmap[hr]>0) {
4499 if(i_regmap[hr]!=CCREG) {
4500 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4501 if((i_dirty>>hr)&1) {
4502 if(i_regmap[hr]<64) {
4503 emit_storereg(i_regmap[hr],hr);
24385cae 4504#ifndef FORCE32
57871462 4505 if( ((i_is32>>i_regmap[hr])&1) ) {
4506 #ifdef DESTRUCTIVE_WRITEBACK
4507 emit_sarimm(hr,31,hr);
4508 emit_storereg(i_regmap[hr]|64,hr);
4509 #else
4510 emit_sarimm(hr,31,HOST_TEMPREG);
4511 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4512 #endif
4513 }
24385cae 4514#endif
57871462 4515 }else{
4516 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4517 emit_storereg(i_regmap[hr],hr);
4518 }
4519 }
4520 }
4521 }
4522 }
4523 }
4524 }
4525 }
4526}
4527
4528// Load all registers (except cycle count)
4529void load_all_regs(signed char i_regmap[])
4530{
4531 int hr;
4532 for(hr=0;hr<HOST_REGS;hr++) {
4533 if(hr!=EXCLUDE_REG) {
4534 if(i_regmap[hr]==0) {
4535 emit_zeroreg(hr);
4536 }
4537 else
ea3d2e6e 4538 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
57871462 4539 {
4540 emit_loadreg(i_regmap[hr],hr);
4541 }
4542 }
4543 }
4544}
4545
4546// Load all current registers also needed by next instruction
4547void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4548{
4549 int hr;
4550 for(hr=0;hr<HOST_REGS;hr++) {
4551 if(hr!=EXCLUDE_REG) {
4552 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4553 if(i_regmap[hr]==0) {
4554 emit_zeroreg(hr);
4555 }
4556 else
ea3d2e6e 4557 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
57871462 4558 {
4559 emit_loadreg(i_regmap[hr],hr);
4560 }
4561 }
4562 }
4563 }
4564}
4565
4566// Load all regs, storing cycle count if necessary
4567void load_regs_entry(int t)
4568{
4569 int hr;
4570 if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER,HOST_CCREG);
4571 else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t]*CLOCK_DIVIDER,HOST_CCREG);
4572 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4573 emit_storereg(CCREG,HOST_CCREG);
4574 }
4575 // Load 32-bit regs
4576 for(hr=0;hr<HOST_REGS;hr++) {
ea3d2e6e 4577 if(regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
57871462 4578 if(regs[t].regmap_entry[hr]==0) {
4579 emit_zeroreg(hr);
4580 }
4581 else if(regs[t].regmap_entry[hr]!=CCREG)
4582 {
4583 emit_loadreg(regs[t].regmap_entry[hr],hr);
4584 }
4585 }
4586 }
4587 // Load 64-bit regs
4588 for(hr=0;hr<HOST_REGS;hr++) {
ea3d2e6e 4589 if(regs[t].regmap_entry[hr]>=64&&regs[t].regmap_entry[hr]<TEMPREG+64) {
57871462 4590 assert(regs[t].regmap_entry[hr]!=64);
4591 if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4592 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4593 if(lr<0) {
4594 emit_loadreg(regs[t].regmap_entry[hr],hr);
4595 }
4596 else
4597 {
4598 emit_sarimm(lr,31,hr);
4599 }
4600 }
4601 else
4602 {
4603 emit_loadreg(regs[t].regmap_entry[hr],hr);
4604 }
4605 }
4606 }
4607}
4608
4609// Store dirty registers prior to branch
4610void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4611{
4612 if(internal_branch(i_is32,addr))
4613 {
4614 int t=(addr-start)>>2;
4615 int hr;
4616 for(hr=0;hr<HOST_REGS;hr++) {
4617 if(hr!=EXCLUDE_REG) {
4618 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4619 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4620 if((i_dirty>>hr)&1) {
4621 if(i_regmap[hr]<64) {
4622 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4623 emit_storereg(i_regmap[hr],hr);
4624 if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4625 #ifdef DESTRUCTIVE_WRITEBACK
4626 emit_sarimm(hr,31,hr);
4627 emit_storereg(i_regmap[hr]|64,hr);
4628 #else
4629 emit_sarimm(hr,31,HOST_TEMPREG);
4630 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4631 #endif
4632 }
4633 }
4634 }else{
4635 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4636 emit_storereg(i_regmap[hr],hr);
4637 }
4638 }
4639 }
4640 }
4641 }
4642 }
4643 }
4644 }
4645 else
4646 {
4647 // Branch out of this block, write out all dirty regs
4648 wb_dirtys(i_regmap,i_is32,i_dirty);
4649 }
4650}
4651
4652// Load all needed registers for branch target
4653void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4654{
4655 //if(addr>=start && addr<(start+slen*4))
4656 if(internal_branch(i_is32,addr))
4657 {
4658 int t=(addr-start)>>2;
4659 int hr;
4660 // Store the cycle count before loading something else
4661 if(i_regmap[HOST_CCREG]!=CCREG) {
4662 assert(i_regmap[HOST_CCREG]==-1);
4663 }
4664 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4665 emit_storereg(CCREG,HOST_CCREG);
4666 }
4667 // Load 32-bit regs
4668 for(hr=0;hr<HOST_REGS;hr++) {
ea3d2e6e 4669 if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
57871462 4670 #ifdef DESTRUCTIVE_WRITEBACK
4671 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4672 #else
4673 if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4674 #endif
4675 if(regs[t].regmap_entry[hr]==0) {
4676 emit_zeroreg(hr);
4677 }
4678 else if(regs[t].regmap_entry[hr]!=CCREG)
4679 {
4680 emit_loadreg(regs[t].regmap_entry[hr],hr);
4681 }
4682 }
4683 }
4684 }
4685 //Load 64-bit regs
4686 for(hr=0;hr<HOST_REGS;hr++) {
ea3d2e6e 4687 if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=64&&regs[t].regmap_entry[hr]<TEMPREG+64) {
57871462 4688 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4689 assert(regs[t].regmap_entry[hr]!=64);
4690 if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4691 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4692 if(lr<0) {
4693 emit_loadreg(regs[t].regmap_entry[hr],hr);
4694 }
4695 else
4696 {
4697 emit_sarimm(lr,31,hr);
4698 }
4699 }
4700 else
4701 {
4702 emit_loadreg(regs[t].regmap_entry[hr],hr);
4703 }
4704 }
4705 else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4706 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4707 assert(lr>=0);
4708 emit_sarimm(lr,31,hr);
4709 }
4710 }
4711 }
4712 }
4713}
4714
4715int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4716{
4717 if(addr>=start && addr<start+slen*4-4)
4718 {
4719 int t=(addr-start)>>2;
4720 int hr;
4721 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4722 for(hr=0;hr<HOST_REGS;hr++)
4723 {
4724 if(hr!=EXCLUDE_REG)
4725 {
4726 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4727 {
ea3d2e6e 4728 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
57871462 4729 {
4730 return 0;
4731 }
4732 else
4733 if((i_dirty>>hr)&1)
4734 {
ea3d2e6e 4735 if(i_regmap[hr]<TEMPREG)
57871462 4736 {
4737 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4738 return 0;
4739 }
ea3d2e6e 4740 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
57871462 4741 {
4742 if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4743 return 0;
4744 }
4745 }
4746 }
4747 else // Same register but is it 32-bit or dirty?
4748 if(i_regmap[hr]>=0)
4749 {
4750 if(!((regs[t].dirty>>hr)&1))
4751 {
4752 if((i_dirty>>hr)&1)
4753 {
4754 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4755 {
4756 //printf("%x: dirty no match\n",addr);
4757 return 0;
4758 }
4759 }
4760 }
4761 if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4762 {
4763 //printf("%x: is32 no match\n",addr);
4764 return 0;
4765 }
4766 }
4767 }
4768 }
4769 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
a28c6ce8 4770#ifndef FORCE32
57871462 4771 if(requires_32bit[t]&~i_is32) return 0;
a28c6ce8 4772#endif
57871462 4773 // Delay slots are not valid branch targets
4774 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4775 // Delay slots require additional processing, so do not match
4776 if(is_ds[t]) return 0;
4777 }
4778 else
4779 {
4780 int hr;
4781 for(hr=0;hr<HOST_REGS;hr++)
4782 {
4783 if(hr!=EXCLUDE_REG)
4784 {
4785 if(i_regmap[hr]>=0)
4786 {
4787 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4788 {
4789 if((i_dirty>>hr)&1)
4790 {
4791 return 0;
4792 }
4793 }
4794 }
4795 }
4796 }
4797 }
4798 return 1;
4799}
4800
4801// Used when a branch jumps into the delay slot of another branch
4802void ds_assemble_entry(int i)
4803{
4804 int t=(ba[i]-start)>>2;
4805 if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4806 assem_debug("Assemble delay slot at %x\n",ba[i]);
4807 assem_debug("<->\n");
4808 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
4809 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4810 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4811 address_generation(t,&regs[t],regs[t].regmap_entry);
b9b61529 4812 if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
57871462 4813 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4814 cop1_usable=0;
4815 is_delayslot=0;
4816 switch(itype[t]) {
4817 case ALU:
4818 alu_assemble(t,&regs[t]);break;
4819 case IMM16:
4820 imm16_assemble(t,&regs[t]);break;
4821 case SHIFT:
4822 shift_assemble(t,&regs[t]);break;
4823 case SHIFTIMM:
4824 shiftimm_assemble(t,&regs[t]);break;
4825 case LOAD:
4826 load_assemble(t,&regs[t]);break;
4827 case LOADLR:
4828 loadlr_assemble(t,&regs[t]);break;
4829 case STORE:
4830 store_assemble(t,&regs[t]);break;
4831 case STORELR:
4832 storelr_assemble(t,&regs[t]);break;
4833 case COP0:
4834 cop0_assemble(t,&regs[t]);break;
4835 case COP1:
4836 cop1_assemble(t,&regs[t]);break;
4837 case C1LS:
4838 c1ls_assemble(t,&regs[t]);break;
b9b61529 4839 case COP2:
4840 cop2_assemble(t,&regs[t]);break;
4841 case C2LS:
4842 c2ls_assemble(t,&regs[t]);break;
4843 case C2OP:
4844 c2op_assemble(t,&regs[t]);break;
57871462 4845 case FCONV:
4846 fconv_assemble(t,&regs[t]);break;
4847 case FLOAT:
4848 float_assemble(t,&regs[t]);break;
4849 case FCOMP:
4850 fcomp_assemble(t,&regs[t]);break;
4851 case MULTDIV:
4852 multdiv_assemble(t,&regs[t]);break;
4853 case MOV:
4854 mov_assemble(t,&regs[t]);break;
4855 case SYSCALL:
7139f3c8 4856 case HLECALL:
1e973cb0 4857 case INTCALL:
57871462 4858 case SPAN:
4859 case UJUMP:
4860 case RJUMP:
4861 case CJUMP:
4862 case SJUMP:
4863 case FJUMP:
4864 printf("Jump in the delay slot. This is probably a bug.\n");
4865 }
4866 store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4867 load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4868 if(internal_branch(regs[t].is32,ba[i]+4))
4869 assem_debug("branch: internal\n");
4870 else
4871 assem_debug("branch: external\n");
4872 assert(internal_branch(regs[t].is32,ba[i]+4));
4873 add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4874 emit_jmp(0);
4875}
4876
4877void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4878{
4879 int count;
4880 int jaddr;
4881 int idle=0;
4882 if(itype[i]==RJUMP)
4883 {
4884 *adj=0;
4885 }
4886 //if(ba[i]>=start && ba[i]<(start+slen*4))
4887 if(internal_branch(branch_regs[i].is32,ba[i]))
4888 {
4889 int t=(ba[i]-start)>>2;
4890 if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4891 else *adj=ccadj[t];
4892 }
4893 else
4894 {
4895 *adj=0;
4896 }
4897 count=ccadj[i];
4898 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4899 // Idle loop
4900 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4901 idle=(int)out;
4902 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4903 emit_andimm(HOST_CCREG,3,HOST_CCREG);
4904 jaddr=(int)out;
4905 emit_jmp(0);
4906 }
4907 else if(*adj==0||invert) {
4908 emit_addimm_and_set_flags(CLOCK_DIVIDER*(count+2),HOST_CCREG);
4909 jaddr=(int)out;
4910 emit_jns(0);
4911 }
4912 else
4913 {
eeb1feeb 4914 emit_cmpimm(HOST_CCREG,-CLOCK_DIVIDER*(count+2));
57871462 4915 jaddr=(int)out;
4916 emit_jns(0);
4917 }
4918 add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4919}
4920
4921void do_ccstub(int n)
4922{
4923 literal_pool(256);
4924 assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
4925 set_jump_target(stubs[n][1],(int)out);
4926 int i=stubs[n][4];
4927 if(stubs[n][6]==NULLDS) {
4928 // Delay slot instruction is nullified ("likely" branch)
4929 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4930 }
4931 else if(stubs[n][6]!=TAKEN) {
4932 wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4933 }
4934 else {
4935 if(internal_branch(branch_regs[i].is32,ba[i]))
4936 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4937 }
4938 if(stubs[n][5]!=-1)
4939 {
4940 // Save PC as return address
4941 emit_movimm(stubs[n][5],EAX);
4942 emit_writeword(EAX,(int)&pcaddr);
4943 }
4944 else
4945 {
4946 // Return address depends on which way the branch goes
4947 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
4948 {
4949 int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4950 int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4951 int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4952 int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4953 if(rs1[i]==0)
4954 {
4955 s1l=s2l;s1h=s2h;
4956 s2l=s2h=-1;
4957 }
4958 else if(rs2[i]==0)
4959 {
4960 s2l=s2h=-1;
4961 }
4962 if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
4963 s1h=s2h=-1;
4964 }
4965 assert(s1l>=0);
4966 #ifdef DESTRUCTIVE_WRITEBACK
4967 if(rs1[i]) {
4968 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
4969 emit_loadreg(rs1[i],s1l);
4970 }
4971 else {
4972 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
4973 emit_loadreg(rs2[i],s1l);
4974 }
4975 if(s2l>=0)
4976 if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
4977 emit_loadreg(rs2[i],s2l);
4978 #endif
4979 int hr=0;
5194fb95 4980 int addr=-1,alt=-1,ntaddr=-1;
57871462 4981 while(hr<HOST_REGS)
4982 {
4983 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4984 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4985 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4986 {
4987 addr=hr++;break;
4988 }
4989 hr++;
4990 }
4991 while(hr<HOST_REGS)
4992 {
4993 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4994 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4995 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4996 {
4997 alt=hr++;break;
4998 }
4999 hr++;
5000 }
5001 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
5002 {
5003 while(hr<HOST_REGS)
5004 {
5005 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5006 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5007 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5008 {
5009 ntaddr=hr;break;
5010 }
5011 hr++;
5012 }
5013 assert(hr<HOST_REGS);
5014 }
5015 if((opcode[i]&0x2f)==4) // BEQ
5016 {
5017 #ifdef HAVE_CMOV_IMM
5018 if(s1h<0) {
5019 if(s2l>=0) emit_cmp(s1l,s2l);
5020 else emit_test(s1l,s1l);
5021 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5022 }
5023 else
5024 #endif
5025 {
5026 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5027 if(s1h>=0) {
5028 if(s2h>=0) emit_cmp(s1h,s2h);
5029 else emit_test(s1h,s1h);
5030 emit_cmovne_reg(alt,addr);
5031 }
5032 if(s2l>=0) emit_cmp(s1l,s2l);
5033 else emit_test(s1l,s1l);
5034 emit_cmovne_reg(alt,addr);
5035 }
5036 }
5037 if((opcode[i]&0x2f)==5) // BNE
5038 {
5039 #ifdef HAVE_CMOV_IMM
5040 if(s1h<0) {
5041 if(s2l>=0) emit_cmp(s1l,s2l);
5042 else emit_test(s1l,s1l);
5043 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5044 }
5045 else
5046 #endif
5047 {
5048 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5049 if(s1h>=0) {
5050 if(s2h>=0) emit_cmp(s1h,s2h);
5051 else emit_test(s1h,s1h);
5052 emit_cmovne_reg(alt,addr);
5053 }
5054 if(s2l>=0) emit_cmp(s1l,s2l);
5055 else emit_test(s1l,s1l);
5056 emit_cmovne_reg(alt,addr);
5057 }
5058 }
5059 if((opcode[i]&0x2f)==6) // BLEZ
5060 {
5061 //emit_movimm(ba[i],alt);
5062 //emit_movimm(start+i*4+8,addr);
5063 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5064 emit_cmpimm(s1l,1);
5065 if(s1h>=0) emit_mov(addr,ntaddr);
5066 emit_cmovl_reg(alt,addr);
5067 if(s1h>=0) {
5068 emit_test(s1h,s1h);
5069 emit_cmovne_reg(ntaddr,addr);
5070 emit_cmovs_reg(alt,addr);
5071 }
5072 }
5073 if((opcode[i]&0x2f)==7) // BGTZ
5074 {
5075 //emit_movimm(ba[i],addr);
5076 //emit_movimm(start+i*4+8,ntaddr);
5077 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5078 emit_cmpimm(s1l,1);
5079 if(s1h>=0) emit_mov(addr,alt);
5080 emit_cmovl_reg(ntaddr,addr);
5081 if(s1h>=0) {
5082 emit_test(s1h,s1h);
5083 emit_cmovne_reg(alt,addr);
5084 emit_cmovs_reg(ntaddr,addr);
5085 }
5086 }
5087 if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
5088 {
5089 //emit_movimm(ba[i],alt);
5090 //emit_movimm(start+i*4+8,addr);
5091 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5092 if(s1h>=0) emit_test(s1h,s1h);
5093 else emit_test(s1l,s1l);
5094 emit_cmovs_reg(alt,addr);
5095 }
5096 if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
5097 {
5098 //emit_movimm(ba[i],addr);
5099 //emit_movimm(start+i*4+8,alt);
5100 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5101 if(s1h>=0) emit_test(s1h,s1h);
5102 else emit_test(s1l,s1l);
5103 emit_cmovs_reg(alt,addr);
5104 }
5105 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
5106 if(source[i]&0x10000) // BC1T
5107 {
5108 //emit_movimm(ba[i],alt);
5109 //emit_movimm(start+i*4+8,addr);
5110 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5111 emit_testimm(s1l,0x800000);
5112 emit_cmovne_reg(alt,addr);
5113 }
5114 else // BC1F
5115 {
5116 //emit_movimm(ba[i],addr);
5117 //emit_movimm(start+i*4+8,alt);
5118 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5119 emit_testimm(s1l,0x800000);
5120 emit_cmovne_reg(alt,addr);
5121 }
5122 }
5123 emit_writeword(addr,(int)&pcaddr);
5124 }
5125 else
5126 if(itype[i]==RJUMP)
5127 {
5128 int r=get_reg(branch_regs[i].regmap,rs1[i]);
5129 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5130 r=get_reg(branch_regs[i].regmap,RTEMP);
5131 }
5132 emit_writeword(r,(int)&pcaddr);
5133 }
5134 else {printf("Unknown branch type in do_ccstub\n");exit(1);}
5135 }
5136 // Update cycle count
5137 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5138 if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
5139 emit_call((int)cc_interrupt);
5140 if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
5141 if(stubs[n][6]==TAKEN) {
5142 if(internal_branch(branch_regs[i].is32,ba[i]))
5143 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
5144 else if(itype[i]==RJUMP) {
5145 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5146 emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5147 else
5148 emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
5149 }
5150 }else if(stubs[n][6]==NOTTAKEN) {
5151 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5152 else load_all_regs(branch_regs[i].regmap);
5153 }else if(stubs[n][6]==NULLDS) {
5154 // Delay slot instruction is nullified ("likely" branch)
5155 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5156 else load_all_regs(regs[i].regmap);
5157 }else{
5158 load_all_regs(branch_regs[i].regmap);
5159 }
5160 emit_jmp(stubs[n][2]); // return address
5161
5162 /* This works but uses a lot of memory...
5163 emit_readword((int)&last_count,ECX);
5164 emit_add(HOST_CCREG,ECX,EAX);
5165 emit_writeword(EAX,(int)&Count);
5166 emit_call((int)gen_interupt);
5167 emit_readword((int)&Count,HOST_CCREG);
5168 emit_readword((int)&next_interupt,EAX);
5169 emit_readword((int)&pending_exception,EBX);
5170 emit_writeword(EAX,(int)&last_count);
5171 emit_sub(HOST_CCREG,EAX,HOST_CCREG);
5172 emit_test(EBX,EBX);
5173 int jne_instr=(int)out;
5174 emit_jne(0);
5175 if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
5176 load_all_regs(branch_regs[i].regmap);
5177 emit_jmp(stubs[n][2]); // return address
5178 set_jump_target(jne_instr,(int)out);
5179 emit_readword((int)&pcaddr,EAX);
5180 // Call get_addr_ht instead of doing the hash table here.
5181 // This code is executed infrequently and takes up a lot of space
5182 // so smaller is better.
5183 emit_storereg(CCREG,HOST_CCREG);
5184 emit_pushreg(EAX);
5185 emit_call((int)get_addr_ht);
5186 emit_loadreg(CCREG,HOST_CCREG);
5187 emit_addimm(ESP,4,ESP);
5188 emit_jmpreg(EAX);*/
5189}
5190
5191add_to_linker(int addr,int target,int ext)
5192{
5193 link_addr[linkcount][0]=addr;
5194 link_addr[linkcount][1]=target;
5195 link_addr[linkcount][2]=ext;
5196 linkcount++;
5197}
5198
eba830cd 5199static void ujump_assemble_write_ra(int i)
5200{
5201 int rt;
5202 unsigned int return_address;
5203 rt=get_reg(branch_regs[i].regmap,31);
5204 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5205 //assert(rt>=0);
5206 return_address=start+i*4+8;
5207 if(rt>=0) {
5208 #ifdef USE_MINI_HT
5209 if(internal_branch(branch_regs[i].is32,return_address)&&rt1[i+1]!=31) {
5210 int temp=-1; // note: must be ds-safe
5211 #ifdef HOST_TEMPREG
5212 temp=HOST_TEMPREG;
5213 #endif
5214 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5215 else emit_movimm(return_address,rt);
5216 }
5217 else
5218 #endif
5219 {
5220 #ifdef REG_PREFETCH
5221 if(temp>=0)
5222 {
5223 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5224 }
5225 #endif
5226 emit_movimm(return_address,rt); // PC into link register
5227 #ifdef IMM_PREFETCH
5228 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5229 #endif
5230 }
5231 }
5232}
5233
57871462 5234void ujump_assemble(int i,struct regstat *i_regs)
5235{
5236 signed char *i_regmap=i_regs->regmap;
eba830cd 5237 int ra_done=0;
57871462 5238 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5239 address_generation(i+1,i_regs,regs[i].regmap_entry);
5240 #ifdef REG_PREFETCH
5241 int temp=get_reg(branch_regs[i].regmap,PTEMP);
5242 if(rt1[i]==31&&temp>=0)
5243 {
5244 int return_address=start+i*4+8;
5245 if(get_reg(branch_regs[i].regmap,31)>0)
5246 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5247 }
5248 #endif
eba830cd 5249 if(rt1[i]==31&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5250 ujump_assemble_write_ra(i); // writeback ra for DS
5251 ra_done=1;
57871462 5252 }
4ef8f67d 5253 ds_assemble(i+1,i_regs);
5254 uint64_t bc_unneeded=branch_regs[i].u;
5255 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5256 bc_unneeded|=1|(1LL<<rt1[i]);
5257 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5258 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5259 bc_unneeded,bc_unneeded_upper);
5260 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
eba830cd 5261 if(!ra_done&&rt1[i]==31)
5262 ujump_assemble_write_ra(i);
57871462 5263 int cc,adj;
5264 cc=get_reg(branch_regs[i].regmap,CCREG);
5265 assert(cc==HOST_CCREG);
5266 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5267 #ifdef REG_PREFETCH
5268 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5269 #endif
5270 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5271 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5272 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5273 if(internal_branch(branch_regs[i].is32,ba[i]))
5274 assem_debug("branch: internal\n");
5275 else
5276 assem_debug("branch: external\n");
5277 if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5278 ds_assemble_entry(i);
5279 }
5280 else {
5281 add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5282 emit_jmp(0);
5283 }
5284}
5285
eba830cd 5286static void rjump_assemble_write_ra(int i)
5287{
5288 int rt,return_address;
5289 assert(rt1[i+1]!=rt1[i]);
5290 assert(rt2[i+1]!=rt1[i]);
5291 rt=get_reg(branch_regs[i].regmap,rt1[i]);
5292 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5293 assert(rt>=0);
5294 return_address=start+i*4+8;
5295 #ifdef REG_PREFETCH
5296 if(temp>=0)
5297 {
5298 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5299 }
5300 #endif
5301 emit_movimm(return_address,rt); // PC into link register
5302 #ifdef IMM_PREFETCH
5303 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5304 #endif
5305}
5306
57871462 5307void rjump_assemble(int i,struct regstat *i_regs)
5308{
5309 signed char *i_regmap=i_regs->regmap;
5310 int temp;
5311 int rs,cc,adj;
eba830cd 5312 int ra_done=0;
57871462 5313 rs=get_reg(branch_regs[i].regmap,rs1[i]);
5314 assert(rs>=0);
5315 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5316 // Delay slot abuse, make a copy of the branch address register
5317 temp=get_reg(branch_regs[i].regmap,RTEMP);
5318 assert(temp>=0);
5319 assert(regs[i].regmap[temp]==RTEMP);
5320 emit_mov(rs,temp);
5321 rs=temp;
5322 }
5323 address_generation(i+1,i_regs,regs[i].regmap_entry);
5324 #ifdef REG_PREFETCH
5325 if(rt1[i]==31)
5326 {
5327 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5328 int return_address=start+i*4+8;
5329 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5330 }
5331 }
5332 #endif
5333 #ifdef USE_MINI_HT
5334 if(rs1[i]==31) {
5335 int rh=get_reg(regs[i].regmap,RHASH);
5336 if(rh>=0) do_preload_rhash(rh);
5337 }
5338 #endif
eba830cd 5339 if(rt1[i]!=0&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5340 rjump_assemble_write_ra(i);
5341 ra_done=1;
57871462 5342 }
d5910d5d 5343 ds_assemble(i+1,i_regs);
5344 uint64_t bc_unneeded=branch_regs[i].u;
5345 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5346 bc_unneeded|=1|(1LL<<rt1[i]);
5347 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5348 bc_unneeded&=~(1LL<<rs1[i]);
5349 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5350 bc_unneeded,bc_unneeded_upper);
5351 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
eba830cd 5352 if(!ra_done&&rt1[i]!=0)
5353 rjump_assemble_write_ra(i);
57871462 5354 cc=get_reg(branch_regs[i].regmap,CCREG);
5355 assert(cc==HOST_CCREG);
5356 #ifdef USE_MINI_HT
5357 int rh=get_reg(branch_regs[i].regmap,RHASH);
5358 int ht=get_reg(branch_regs[i].regmap,RHTBL);
5359 if(rs1[i]==31) {
5360 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5361 do_preload_rhtbl(ht);
5362 do_rhash(rs,rh);
5363 }
5364 #endif
5365 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5366 #ifdef DESTRUCTIVE_WRITEBACK
5367 if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5368 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5369 emit_loadreg(rs1[i],rs);
5370 }
5371 }
5372 #endif
5373 #ifdef REG_PREFETCH
5374 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5375 #endif
5376 #ifdef USE_MINI_HT
5377 if(rs1[i]==31) {
5378 do_miniht_load(ht,rh);
5379 }
5380 #endif
5381 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5382 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5383 //assert(adj==0);
5384 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5385 add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5386 emit_jns(0);
5387 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5388 #ifdef USE_MINI_HT
5389 if(rs1[i]==31) {
5390 do_miniht_jump(rs,rh,ht);
5391 }
5392 else
5393 #endif
5394 {
5395 //if(rs!=EAX) emit_mov(rs,EAX);
5396 //emit_jmp((int)jump_vaddr_eax);
5397 emit_jmp(jump_vaddr_reg[rs]);
5398 }
5399 /* Check hash table
5400 temp=!rs;
5401 emit_mov(rs,temp);
5402 emit_shrimm(rs,16,rs);
5403 emit_xor(temp,rs,rs);
5404 emit_movzwl_reg(rs,rs);
5405 emit_shlimm(rs,4,rs);
5406 emit_cmpmem_indexed((int)hash_table,rs,temp);
5407 emit_jne((int)out+14);
5408 emit_readword_indexed((int)hash_table+4,rs,rs);
5409 emit_jmpreg(rs);
5410 emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5411 emit_addimm_no_flags(8,rs);
5412 emit_jeq((int)out-17);
5413 // No hit on hash table, call compiler
5414 emit_pushreg(temp);
5415//DEBUG >
5416#ifdef DEBUG_CYCLE_COUNT
5417 emit_readword((int)&last_count,ECX);
5418 emit_add(HOST_CCREG,ECX,HOST_CCREG);
5419 emit_readword((int)&next_interupt,ECX);
5420 emit_writeword(HOST_CCREG,(int)&Count);
5421 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5422 emit_writeword(ECX,(int)&last_count);
5423#endif
5424//DEBUG <
5425 emit_storereg(CCREG,HOST_CCREG);
5426 emit_call((int)get_addr);
5427 emit_loadreg(CCREG,HOST_CCREG);
5428 emit_addimm(ESP,4,ESP);
5429 emit_jmpreg(EAX);*/
5430 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5431 if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5432 #endif
5433}
5434
5435void cjump_assemble(int i,struct regstat *i_regs)
5436{
5437 signed char *i_regmap=i_regs->regmap;
5438 int cc;
5439 int match;
5440 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5441 assem_debug("match=%d\n",match);
5442 int s1h,s1l,s2h,s2l;
5443 int prev_cop1_usable=cop1_usable;
5444 int unconditional=0,nop=0;
5445 int only32=0;
57871462 5446 int invert=0;
5447 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5448 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 5449 if(!match) invert=1;
5450 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5451 if(i>(ba[i]-start)>>2) invert=1;
5452 #endif
e1190b87 5453
5454 if(ooo[i]) {
57871462 5455 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5456 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5457 s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5458 s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5459 }
5460 else {
5461 s1l=get_reg(i_regmap,rs1[i]);
5462 s1h=get_reg(i_regmap,rs1[i]|64);
5463 s2l=get_reg(i_regmap,rs2[i]);
5464 s2h=get_reg(i_regmap,rs2[i]|64);
5465 }
5466 if(rs1[i]==0&&rs2[i]==0)
5467 {
5468 if(opcode[i]&1) nop=1;
5469 else unconditional=1;
5470 //assert(opcode[i]!=5);
5471 //assert(opcode[i]!=7);
5472 //assert(opcode[i]!=0x15);
5473 //assert(opcode[i]!=0x17);
5474 }
5475 else if(rs1[i]==0)
5476 {
5477 s1l=s2l;s1h=s2h;
5478 s2l=s2h=-1;
5479 only32=(regs[i].was32>>rs2[i])&1;
5480 }
5481 else if(rs2[i]==0)
5482 {
5483 s2l=s2h=-1;
5484 only32=(regs[i].was32>>rs1[i])&1;
5485 }
5486 else {
5487 only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5488 }
5489
e1190b87 5490 if(ooo[i]) {
57871462 5491 // Out of order execution (delay slot first)
5492 //printf("OOOE\n");
5493 address_generation(i+1,i_regs,regs[i].regmap_entry);
5494 ds_assemble(i+1,i_regs);
5495 int adj;
5496 uint64_t bc_unneeded=branch_regs[i].u;
5497 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5498 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5499 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5500 bc_unneeded|=1;
5501 bc_unneeded_upper|=1;
5502 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5503 bc_unneeded,bc_unneeded_upper);
5504 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5505 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5506 cc=get_reg(branch_regs[i].regmap,CCREG);
5507 assert(cc==HOST_CCREG);
5508 if(unconditional)
5509 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5510 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5511 //assem_debug("cycle count (adj)\n");
5512 if(unconditional) {
5513 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5514 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5515 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5516 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5517 if(internal)
5518 assem_debug("branch: internal\n");
5519 else
5520 assem_debug("branch: external\n");
5521 if(internal&&is_ds[(ba[i]-start)>>2]) {
5522 ds_assemble_entry(i);
5523 }
5524 else {
5525 add_to_linker((int)out,ba[i],internal);
5526 emit_jmp(0);
5527 }
5528 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5529 if(((u_int)out)&7) emit_addnop(0);
5530 #endif
5531 }
5532 }
5533 else if(nop) {
5534 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5535 int jaddr=(int)out;
5536 emit_jns(0);
5537 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5538 }
5539 else {
5540 int taken=0,nottaken=0,nottaken1=0;
5541 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5542 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5543 if(!only32)
5544 {
5545 assert(s1h>=0);
5546 if(opcode[i]==4) // BEQ
5547 {
5548 if(s2h>=0) emit_cmp(s1h,s2h);
5549 else emit_test(s1h,s1h);
5550 nottaken1=(int)out;
5551 emit_jne(1);
5552 }
5553 if(opcode[i]==5) // BNE
5554 {
5555 if(s2h>=0) emit_cmp(s1h,s2h);
5556 else emit_test(s1h,s1h);
5557 if(invert) taken=(int)out;
5558 else add_to_linker((int)out,ba[i],internal);
5559 emit_jne(0);
5560 }
5561 if(opcode[i]==6) // BLEZ
5562 {
5563 emit_test(s1h,s1h);
5564 if(invert) taken=(int)out;
5565 else add_to_linker((int)out,ba[i],internal);
5566 emit_js(0);
5567 nottaken1=(int)out;
5568 emit_jne(1);
5569 }
5570 if(opcode[i]==7) // BGTZ
5571 {
5572 emit_test(s1h,s1h);
5573 nottaken1=(int)out;
5574 emit_js(1);
5575 if(invert) taken=(int)out;
5576 else add_to_linker((int)out,ba[i],internal);
5577 emit_jne(0);
5578 }
5579 } // if(!only32)
5580
5581 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5582 assert(s1l>=0);
5583 if(opcode[i]==4) // BEQ
5584 {
5585 if(s2l>=0) emit_cmp(s1l,s2l);
5586 else emit_test(s1l,s1l);
5587 if(invert){
5588 nottaken=(int)out;
5589 emit_jne(1);
5590 }else{
5591 add_to_linker((int)out,ba[i],internal);
5592 emit_jeq(0);
5593 }
5594 }
5595 if(opcode[i]==5) // BNE
5596 {
5597 if(s2l>=0) emit_cmp(s1l,s2l);
5598 else emit_test(s1l,s1l);
5599 if(invert){
5600 nottaken=(int)out;
5601 emit_jeq(1);
5602 }else{
5603 add_to_linker((int)out,ba[i],internal);
5604 emit_jne(0);
5605 }
5606 }
5607 if(opcode[i]==6) // BLEZ
5608 {
5609 emit_cmpimm(s1l,1);
5610 if(invert){
5611 nottaken=(int)out;
5612 emit_jge(1);
5613 }else{
5614 add_to_linker((int)out,ba[i],internal);
5615 emit_jl(0);
5616 }
5617 }
5618 if(opcode[i]==7) // BGTZ
5619 {
5620 emit_cmpimm(s1l,1);
5621 if(invert){
5622 nottaken=(int)out;
5623 emit_jl(1);
5624 }else{
5625 add_to_linker((int)out,ba[i],internal);
5626 emit_jge(0);
5627 }
5628 }
5629 if(invert) {
5630 if(taken) set_jump_target(taken,(int)out);
5631 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5632 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5633 if(adj) {
5634 emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5635 add_to_linker((int)out,ba[i],internal);
5636 }else{
5637 emit_addnop(13);
5638 add_to_linker((int)out,ba[i],internal*2);
5639 }
5640 emit_jmp(0);
5641 }else
5642 #endif
5643 {
5644 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5645 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5646 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5647 if(internal)
5648 assem_debug("branch: internal\n");
5649 else
5650 assem_debug("branch: external\n");
5651 if(internal&&is_ds[(ba[i]-start)>>2]) {
5652 ds_assemble_entry(i);
5653 }
5654 else {
5655 add_to_linker((int)out,ba[i],internal);
5656 emit_jmp(0);
5657 }
5658 }
5659 set_jump_target(nottaken,(int)out);
5660 }
5661
5662 if(nottaken1) set_jump_target(nottaken1,(int)out);
5663 if(adj) {
5664 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5665 }
5666 } // (!unconditional)
5667 } // if(ooo)
5668 else
5669 {
5670 // In-order execution (branch first)
5671 //if(likely[i]) printf("IOL\n");
5672 //else
5673 //printf("IOE\n");
5674 int taken=0,nottaken=0,nottaken1=0;
5675 if(!unconditional&&!nop) {
5676 if(!only32)
5677 {
5678 assert(s1h>=0);
5679 if((opcode[i]&0x2f)==4) // BEQ
5680 {
5681 if(s2h>=0) emit_cmp(s1h,s2h);
5682 else emit_test(s1h,s1h);
5683 nottaken1=(int)out;
5684 emit_jne(2);
5685 }
5686 if((opcode[i]&0x2f)==5) // BNE
5687 {
5688 if(s2h>=0) emit_cmp(s1h,s2h);
5689 else emit_test(s1h,s1h);
5690 taken=(int)out;
5691 emit_jne(1);
5692 }
5693 if((opcode[i]&0x2f)==6) // BLEZ
5694 {
5695 emit_test(s1h,s1h);
5696 taken=(int)out;
5697 emit_js(1);
5698 nottaken1=(int)out;
5699 emit_jne(2);
5700 }
5701 if((opcode[i]&0x2f)==7) // BGTZ
5702 {
5703 emit_test(s1h,s1h);
5704 nottaken1=(int)out;
5705 emit_js(2);
5706 taken=(int)out;
5707 emit_jne(1);
5708 }
5709 } // if(!only32)
5710
5711 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5712 assert(s1l>=0);
5713 if((opcode[i]&0x2f)==4) // BEQ
5714 {
5715 if(s2l>=0) emit_cmp(s1l,s2l);
5716 else emit_test(s1l,s1l);
5717 nottaken=(int)out;
5718 emit_jne(2);
5719 }
5720 if((opcode[i]&0x2f)==5) // BNE
5721 {
5722 if(s2l>=0) emit_cmp(s1l,s2l);
5723 else emit_test(s1l,s1l);
5724 nottaken=(int)out;
5725 emit_jeq(2);
5726 }
5727 if((opcode[i]&0x2f)==6) // BLEZ
5728 {
5729 emit_cmpimm(s1l,1);
5730 nottaken=(int)out;
5731 emit_jge(2);
5732 }
5733 if((opcode[i]&0x2f)==7) // BGTZ
5734 {
5735 emit_cmpimm(s1l,1);
5736 nottaken=(int)out;
5737 emit_jl(2);
5738 }
5739 } // if(!unconditional)
5740 int adj;
5741 uint64_t ds_unneeded=branch_regs[i].u;
5742 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5743 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5744 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5745 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5746 ds_unneeded|=1;
5747 ds_unneeded_upper|=1;
5748 // branch taken
5749 if(!nop) {
5750 if(taken) set_jump_target(taken,(int)out);
5751 assem_debug("1:\n");
5752 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5753 ds_unneeded,ds_unneeded_upper);
5754 // load regs
5755 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5756 address_generation(i+1,&branch_regs[i],0);
5757 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5758 ds_assemble(i+1,&branch_regs[i]);
5759 cc=get_reg(branch_regs[i].regmap,CCREG);
5760 if(cc==-1) {
5761 emit_loadreg(CCREG,cc=HOST_CCREG);
5762 // CHECK: Is the following instruction (fall thru) allocated ok?
5763 }
5764 assert(cc==HOST_CCREG);
5765 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5766 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5767 assem_debug("cycle count (adj)\n");
5768 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5769 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5770 if(internal)
5771 assem_debug("branch: internal\n");
5772 else
5773 assem_debug("branch: external\n");
5774 if(internal&&is_ds[(ba[i]-start)>>2]) {
5775 ds_assemble_entry(i);
5776 }
5777 else {
5778 add_to_linker((int)out,ba[i],internal);
5779 emit_jmp(0);
5780 }
5781 }
5782 // branch not taken
5783 cop1_usable=prev_cop1_usable;
5784 if(!unconditional) {
5785 if(nottaken1) set_jump_target(nottaken1,(int)out);
5786 set_jump_target(nottaken,(int)out);
5787 assem_debug("2:\n");
5788 if(!likely[i]) {
5789 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5790 ds_unneeded,ds_unneeded_upper);
5791 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5792 address_generation(i+1,&branch_regs[i],0);
5793 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5794 ds_assemble(i+1,&branch_regs[i]);
5795 }
5796 cc=get_reg(branch_regs[i].regmap,CCREG);
5797 if(cc==-1&&!likely[i]) {
5798 // Cycle count isn't in a register, temporarily load it then write it out
5799 emit_loadreg(CCREG,HOST_CCREG);
5800 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5801 int jaddr=(int)out;
5802 emit_jns(0);
5803 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5804 emit_storereg(CCREG,HOST_CCREG);
5805 }
5806 else{
5807 cc=get_reg(i_regmap,CCREG);
5808 assert(cc==HOST_CCREG);
5809 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5810 int jaddr=(int)out;
5811 emit_jns(0);
5812 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5813 }
5814 }
5815 }
5816}
5817
5818void sjump_assemble(int i,struct regstat *i_regs)
5819{
5820 signed char *i_regmap=i_regs->regmap;
5821 int cc;
5822 int match;
5823 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5824 assem_debug("smatch=%d\n",match);
5825 int s1h,s1l;
5826 int prev_cop1_usable=cop1_usable;
5827 int unconditional=0,nevertaken=0;
5828 int only32=0;
57871462 5829 int invert=0;
5830 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5831 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 5832 if(!match) invert=1;
5833 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5834 if(i>(ba[i]-start)>>2) invert=1;
5835 #endif
5836
5837 //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
df894a3a 5838 //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
57871462 5839
e1190b87 5840 if(ooo[i]) {
57871462 5841 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5842 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5843 }
5844 else {
5845 s1l=get_reg(i_regmap,rs1[i]);
5846 s1h=get_reg(i_regmap,rs1[i]|64);
5847 }
5848 if(rs1[i]==0)
5849 {
5850 if(opcode2[i]&1) unconditional=1;
5851 else nevertaken=1;
5852 // These are never taken (r0 is never less than zero)
5853 //assert(opcode2[i]!=0);
5854 //assert(opcode2[i]!=2);
5855 //assert(opcode2[i]!=0x10);
5856 //assert(opcode2[i]!=0x12);
5857 }
5858 else {
5859 only32=(regs[i].was32>>rs1[i])&1;
5860 }
5861
e1190b87 5862 if(ooo[i]) {
57871462 5863 // Out of order execution (delay slot first)
5864 //printf("OOOE\n");
5865 address_generation(i+1,i_regs,regs[i].regmap_entry);
5866 ds_assemble(i+1,i_regs);
5867 int adj;
5868 uint64_t bc_unneeded=branch_regs[i].u;
5869 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5870 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5871 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5872 bc_unneeded|=1;
5873 bc_unneeded_upper|=1;
5874 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5875 bc_unneeded,bc_unneeded_upper);
5876 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5877 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5878 if(rt1[i]==31) {
5879 int rt,return_address;
57871462 5880 rt=get_reg(branch_regs[i].regmap,31);
5881 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5882 if(rt>=0) {
5883 // Save the PC even if the branch is not taken
5884 return_address=start+i*4+8;
5885 emit_movimm(return_address,rt); // PC into link register
5886 #ifdef IMM_PREFETCH
5887 if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5888 #endif
5889 }
5890 }
5891 cc=get_reg(branch_regs[i].regmap,CCREG);
5892 assert(cc==HOST_CCREG);
5893 if(unconditional)
5894 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5895 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5896 assem_debug("cycle count (adj)\n");
5897 if(unconditional) {
5898 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5899 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5900 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5901 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5902 if(internal)
5903 assem_debug("branch: internal\n");
5904 else
5905 assem_debug("branch: external\n");
5906 if(internal&&is_ds[(ba[i]-start)>>2]) {
5907 ds_assemble_entry(i);
5908 }
5909 else {
5910 add_to_linker((int)out,ba[i],internal);
5911 emit_jmp(0);
5912 }
5913 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5914 if(((u_int)out)&7) emit_addnop(0);
5915 #endif
5916 }
5917 }
5918 else if(nevertaken) {
5919 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5920 int jaddr=(int)out;
5921 emit_jns(0);
5922 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5923 }
5924 else {
5925 int nottaken=0;
5926 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5927 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5928 if(!only32)
5929 {
5930 assert(s1h>=0);
df894a3a 5931 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
57871462 5932 {
5933 emit_test(s1h,s1h);
5934 if(invert){
5935 nottaken=(int)out;
5936 emit_jns(1);
5937 }else{
5938 add_to_linker((int)out,ba[i],internal);
5939 emit_js(0);
5940 }
5941 }
df894a3a 5942 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
57871462 5943 {
5944 emit_test(s1h,s1h);
5945 if(invert){
5946 nottaken=(int)out;
5947 emit_js(1);
5948 }else{
5949 add_to_linker((int)out,ba[i],internal);
5950 emit_jns(0);
5951 }
5952 }
5953 } // if(!only32)
5954 else
5955 {
5956 assert(s1l>=0);
df894a3a 5957 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
57871462 5958 {
5959 emit_test(s1l,s1l);
5960 if(invert){
5961 nottaken=(int)out;
5962 emit_jns(1);
5963 }else{
5964 add_to_linker((int)out,ba[i],internal);
5965 emit_js(0);
5966 }
5967 }
df894a3a 5968 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
57871462 5969 {
5970 emit_test(s1l,s1l);
5971 if(invert){
5972 nottaken=(int)out;
5973 emit_js(1);
5974 }else{
5975 add_to_linker((int)out,ba[i],internal);
5976 emit_jns(0);
5977 }
5978 }
5979 } // if(!only32)
5980
5981 if(invert) {
5982 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5983 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5984 if(adj) {
5985 emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5986 add_to_linker((int)out,ba[i],internal);
5987 }else{
5988 emit_addnop(13);
5989 add_to_linker((int)out,ba[i],internal*2);
5990 }
5991 emit_jmp(0);
5992 }else
5993 #endif
5994 {
5995 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5996 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5997 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5998 if(internal)
5999 assem_debug("branch: internal\n");
6000 else
6001 assem_debug("branch: external\n");
6002 if(internal&&is_ds[(ba[i]-start)>>2]) {
6003 ds_assemble_entry(i);
6004 }
6005 else {
6006 add_to_linker((int)out,ba[i],internal);
6007 emit_jmp(0);
6008 }
6009 }
6010 set_jump_target(nottaken,(int)out);
6011 }
6012
6013 if(adj) {
6014 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
6015 }
6016 } // (!unconditional)
6017 } // if(ooo)
6018 else
6019 {
6020 // In-order execution (branch first)
6021 //printf("IOE\n");
6022 int nottaken=0;
a6491170 6023 if(rt1[i]==31) {
6024 int rt,return_address;
a6491170 6025 rt=get_reg(branch_regs[i].regmap,31);
6026 if(rt>=0) {
6027 // Save the PC even if the branch is not taken
6028 return_address=start+i*4+8;
6029 emit_movimm(return_address,rt); // PC into link register
6030 #ifdef IMM_PREFETCH
6031 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
6032 #endif
6033 }
6034 }
57871462 6035 if(!unconditional) {
6036 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6037 if(!only32)
6038 {
6039 assert(s1h>=0);
a6491170 6040 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
57871462 6041 {
6042 emit_test(s1h,s1h);
6043 nottaken=(int)out;
6044 emit_jns(1);
6045 }
a6491170 6046 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
57871462 6047 {
6048 emit_test(s1h,s1h);
6049 nottaken=(int)out;
6050 emit_js(1);
6051 }
6052 } // if(!only32)
6053 else
6054 {
6055 assert(s1l>=0);
a6491170 6056 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
57871462 6057 {
6058 emit_test(s1l,s1l);
6059 nottaken=(int)out;
6060 emit_jns(1);
6061 }
a6491170 6062 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
57871462 6063 {
6064 emit_test(s1l,s1l);
6065 nottaken=(int)out;
6066 emit_js(1);
6067 }
6068 }
6069 } // if(!unconditional)
6070 int adj;
6071 uint64_t ds_unneeded=branch_regs[i].u;
6072 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6073 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6074 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6075 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6076 ds_unneeded|=1;
6077 ds_unneeded_upper|=1;
6078 // branch taken
6079 if(!nevertaken) {
6080 //assem_debug("1:\n");
6081 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6082 ds_unneeded,ds_unneeded_upper);
6083 // load regs
6084 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6085 address_generation(i+1,&branch_regs[i],0);
6086 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6087 ds_assemble(i+1,&branch_regs[i]);
6088 cc=get_reg(branch_regs[i].regmap,CCREG);
6089 if(cc==-1) {
6090 emit_loadreg(CCREG,cc=HOST_CCREG);
6091 // CHECK: Is the following instruction (fall thru) allocated ok?
6092 }
6093 assert(cc==HOST_CCREG);
6094 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6095 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6096 assem_debug("cycle count (adj)\n");
6097 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6098 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6099 if(internal)
6100 assem_debug("branch: internal\n");
6101 else
6102 assem_debug("branch: external\n");
6103 if(internal&&is_ds[(ba[i]-start)>>2]) {
6104 ds_assemble_entry(i);
6105 }
6106 else {
6107 add_to_linker((int)out,ba[i],internal);
6108 emit_jmp(0);
6109 }
6110 }
6111 // branch not taken
6112 cop1_usable=prev_cop1_usable;
6113 if(!unconditional) {
6114 set_jump_target(nottaken,(int)out);
6115 assem_debug("1:\n");
6116 if(!likely[i]) {
6117 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6118 ds_unneeded,ds_unneeded_upper);
6119 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6120 address_generation(i+1,&branch_regs[i],0);
6121 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6122 ds_assemble(i+1,&branch_regs[i]);
6123 }
6124 cc=get_reg(branch_regs[i].regmap,CCREG);
6125 if(cc==-1&&!likely[i]) {
6126 // Cycle count isn't in a register, temporarily load it then write it out
6127 emit_loadreg(CCREG,HOST_CCREG);
6128 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6129 int jaddr=(int)out;
6130 emit_jns(0);
6131 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6132 emit_storereg(CCREG,HOST_CCREG);
6133 }
6134 else{
6135 cc=get_reg(i_regmap,CCREG);
6136 assert(cc==HOST_CCREG);
6137 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6138 int jaddr=(int)out;
6139 emit_jns(0);
6140 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6141 }
6142 }
6143 }
6144}
6145
6146void fjump_assemble(int i,struct regstat *i_regs)
6147{
6148 signed char *i_regmap=i_regs->regmap;
6149 int cc;
6150 int match;
6151 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6152 assem_debug("fmatch=%d\n",match);
6153 int fs,cs;
6154 int eaddr;
57871462 6155 int invert=0;
6156 int internal=internal_branch(branch_regs[i].is32,ba[i]);
6157 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
57871462 6158 if(!match) invert=1;
6159 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6160 if(i>(ba[i]-start)>>2) invert=1;
6161 #endif
6162
e1190b87 6163 if(ooo[i]) {
57871462 6164 fs=get_reg(branch_regs[i].regmap,FSREG);
6165 address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
6166 }
6167 else {
6168 fs=get_reg(i_regmap,FSREG);
6169 }
6170
6171 // Check cop1 unusable
6172 if(!cop1_usable) {
6173 cs=get_reg(i_regmap,CSREG);
6174 assert(cs>=0);
6175 emit_testimm(cs,0x20000000);
6176 eaddr=(int)out;
6177 emit_jeq(0);
6178 add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
6179 cop1_usable=1;
6180 }
6181
e1190b87 6182 if(ooo[i]) {
57871462 6183 // Out of order execution (delay slot first)
6184 //printf("OOOE\n");
6185 ds_assemble(i+1,i_regs);
6186 int adj;
6187 uint64_t bc_unneeded=branch_regs[i].u;
6188 uint64_t bc_unneeded_upper=branch_regs[i].uu;
6189 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6190 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
6191 bc_unneeded|=1;
6192 bc_unneeded_upper|=1;
6193 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6194 bc_unneeded,bc_unneeded_upper);
6195 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
6196 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6197 cc=get_reg(branch_regs[i].regmap,CCREG);
6198 assert(cc==HOST_CCREG);
6199 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6200 assem_debug("cycle count (adj)\n");
6201 if(1) {
6202 int nottaken=0;
6203 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6204 if(1) {
6205 assert(fs>=0);
6206 emit_testimm(fs,0x800000);
6207 if(source[i]&0x10000) // BC1T
6208 {
6209 if(invert){
6210 nottaken=(int)out;
6211 emit_jeq(1);
6212 }else{
6213 add_to_linker((int)out,ba[i],internal);
6214 emit_jne(0);
6215 }
6216 }
6217 else // BC1F
6218 if(invert){
6219 nottaken=(int)out;
6220 emit_jne(1);
6221 }else{
6222 add_to_linker((int)out,ba[i],internal);
6223 emit_jeq(0);
6224 }
6225 {
6226 }
6227 } // if(!only32)
6228
6229 if(invert) {
6230 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
6231 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6232 else if(match) emit_addnop(13);
6233 #endif
6234 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6235 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6236 if(internal)
6237 assem_debug("branch: internal\n");
6238 else
6239 assem_debug("branch: external\n");
6240 if(internal&&is_ds[(ba[i]-start)>>2]) {
6241 ds_assemble_entry(i);
6242 }
6243 else {
6244 add_to_linker((int)out,ba[i],internal);
6245 emit_jmp(0);
6246 }
6247 set_jump_target(nottaken,(int)out);
6248 }
6249
6250 if(adj) {
6251 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
6252 }
6253 } // (!unconditional)
6254 } // if(ooo)
6255 else
6256 {
6257 // In-order execution (branch first)
6258 //printf("IOE\n");
6259 int nottaken=0;
6260 if(1) {
6261 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6262 if(1) {
6263 assert(fs>=0);
6264 emit_testimm(fs,0x800000);
6265 if(source[i]&0x10000) // BC1T
6266 {
6267 nottaken=(int)out;
6268 emit_jeq(1);
6269 }
6270 else // BC1F
6271 {
6272 nottaken=(int)out;
6273 emit_jne(1);
6274 }
6275 }
6276 } // if(!unconditional)
6277 int adj;
6278 uint64_t ds_unneeded=branch_regs[i].u;
6279 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6280 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6281 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6282 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6283 ds_unneeded|=1;
6284 ds_unneeded_upper|=1;
6285 // branch taken
6286 //assem_debug("1:\n");
6287 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6288 ds_unneeded,ds_unneeded_upper);
6289 // load regs
6290 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6291 address_generation(i+1,&branch_regs[i],0);
6292 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6293 ds_assemble(i+1,&branch_regs[i]);
6294 cc=get_reg(branch_regs[i].regmap,CCREG);
6295 if(cc==-1) {
6296 emit_loadreg(CCREG,cc=HOST_CCREG);
6297 // CHECK: Is the following instruction (fall thru) allocated ok?
6298 }
6299 assert(cc==HOST_CCREG);
6300 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6301 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6302 assem_debug("cycle count (adj)\n");
6303 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6304 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6305 if(internal)
6306 assem_debug("branch: internal\n");
6307 else
6308 assem_debug("branch: external\n");
6309 if(internal&&is_ds[(ba[i]-start)>>2]) {
6310 ds_assemble_entry(i);
6311 }
6312 else {
6313 add_to_linker((int)out,ba[i],internal);
6314 emit_jmp(0);
6315 }
6316
6317 // branch not taken
6318 if(1) { // <- FIXME (don't need this)
6319 set_jump_target(nottaken,(int)out);
6320 assem_debug("1:\n");
6321 if(!likely[i]) {
6322 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6323 ds_unneeded,ds_unneeded_upper);
6324 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6325 address_generation(i+1,&branch_regs[i],0);
6326 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6327 ds_assemble(i+1,&branch_regs[i]);
6328 }
6329 cc=get_reg(branch_regs[i].regmap,CCREG);
6330 if(cc==-1&&!likely[i]) {
6331 // Cycle count isn't in a register, temporarily load it then write it out
6332 emit_loadreg(CCREG,HOST_CCREG);
6333 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6334 int jaddr=(int)out;
6335 emit_jns(0);
6336 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6337 emit_storereg(CCREG,HOST_CCREG);
6338 }
6339 else{
6340 cc=get_reg(i_regmap,CCREG);
6341 assert(cc==HOST_CCREG);
6342 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6343 int jaddr=(int)out;
6344 emit_jns(0);
6345 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6346 }
6347 }
6348 }
6349}
6350
6351static void pagespan_assemble(int i,struct regstat *i_regs)
6352{
6353 int s1l=get_reg(i_regs->regmap,rs1[i]);
6354 int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6355 int s2l=get_reg(i_regs->regmap,rs2[i]);
6356 int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6357 void *nt_branch=NULL;
6358 int taken=0;
6359 int nottaken=0;
6360 int unconditional=0;
6361 if(rs1[i]==0)
6362 {
6363 s1l=s2l;s1h=s2h;
6364 s2l=s2h=-1;
6365 }
6366 else if(rs2[i]==0)
6367 {
6368 s2l=s2h=-1;
6369 }
6370 if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6371 s1h=s2h=-1;
6372 }
6373 int hr=0;
6374 int addr,alt,ntaddr;
6375 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6376 else {
6377 while(hr<HOST_REGS)
6378 {
6379 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6380 (i_regs->regmap[hr]&63)!=rs1[i] &&
6381 (i_regs->regmap[hr]&63)!=rs2[i] )
6382 {
6383 addr=hr++;break;
6384 }
6385 hr++;
6386 }
6387 }
6388 while(hr<HOST_REGS)
6389 {
6390 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6391 (i_regs->regmap[hr]&63)!=rs1[i] &&
6392 (i_regs->regmap[hr]&63)!=rs2[i] )
6393 {
6394 alt=hr++;break;
6395 }
6396 hr++;
6397 }
6398 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6399 {
6400 while(hr<HOST_REGS)
6401 {
6402 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6403 (i_regs->regmap[hr]&63)!=rs1[i] &&
6404 (i_regs->regmap[hr]&63)!=rs2[i] )
6405 {
6406 ntaddr=hr;break;
6407 }
6408 hr++;
6409 }
6410 }
6411 assert(hr<HOST_REGS);
6412 if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6413 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6414 }
6415 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6416 if(opcode[i]==2) // J
6417 {
6418 unconditional=1;
6419 }
6420 if(opcode[i]==3) // JAL
6421 {
6422 // TODO: mini_ht
6423 int rt=get_reg(i_regs->regmap,31);
6424 emit_movimm(start+i*4+8,rt);
6425 unconditional=1;
6426 }
6427 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6428 {
6429 emit_mov(s1l,addr);
6430 if(opcode2[i]==9) // JALR
6431 {
5067f341 6432 int rt=get_reg(i_regs->regmap,rt1[i]);
57871462 6433 emit_movimm(start+i*4+8,rt);
6434 }
6435 }
6436 if((opcode[i]&0x3f)==4) // BEQ
6437 {
6438 if(rs1[i]==rs2[i])
6439 {
6440 unconditional=1;
6441 }
6442 else
6443 #ifdef HAVE_CMOV_IMM
6444 if(s1h<0) {
6445 if(s2l>=0) emit_cmp(s1l,s2l);
6446 else emit_test(s1l,s1l);
6447 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6448 }
6449 else
6450 #endif
6451 {
6452 assert(s1l>=0);
6453 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6454 if(s1h>=0) {
6455 if(s2h>=0) emit_cmp(s1h,s2h);
6456 else emit_test(s1h,s1h);
6457 emit_cmovne_reg(alt,addr);
6458 }
6459 if(s2l>=0) emit_cmp(s1l,s2l);
6460 else emit_test(s1l,s1l);
6461 emit_cmovne_reg(alt,addr);
6462 }
6463 }
6464 if((opcode[i]&0x3f)==5) // BNE
6465 {
6466 #ifdef HAVE_CMOV_IMM
6467 if(s1h<0) {
6468 if(s2l>=0) emit_cmp(s1l,s2l);
6469 else emit_test(s1l,s1l);
6470 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6471 }
6472 else
6473 #endif
6474 {
6475 assert(s1l>=0);
6476 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6477 if(s1h>=0) {
6478 if(s2h>=0) emit_cmp(s1h,s2h);
6479 else emit_test(s1h,s1h);
6480 emit_cmovne_reg(alt,addr);
6481 }
6482 if(s2l>=0) emit_cmp(s1l,s2l);
6483 else emit_test(s1l,s1l);
6484 emit_cmovne_reg(alt,addr);
6485 }
6486 }
6487 if((opcode[i]&0x3f)==0x14) // BEQL
6488 {
6489 if(s1h>=0) {
6490 if(s2h>=0) emit_cmp(s1h,s2h);
6491 else emit_test(s1h,s1h);
6492 nottaken=(int)out;
6493 emit_jne(0);
6494 }
6495 if(s2l>=0) emit_cmp(s1l,s2l);
6496 else emit_test(s1l,s1l);
6497 if(nottaken) set_jump_target(nottaken,(int)out);
6498 nottaken=(int)out;
6499 emit_jne(0);
6500 }
6501 if((opcode[i]&0x3f)==0x15) // BNEL
6502 {
6503 if(s1h>=0) {
6504 if(s2h>=0) emit_cmp(s1h,s2h);
6505 else emit_test(s1h,s1h);
6506 taken=(int)out;
6507 emit_jne(0);
6508 }
6509 if(s2l>=0) emit_cmp(s1l,s2l);
6510 else emit_test(s1l,s1l);
6511 nottaken=(int)out;
6512 emit_jeq(0);
6513 if(taken) set_jump_target(taken,(int)out);
6514 }
6515 if((opcode[i]&0x3f)==6) // BLEZ
6516 {
6517 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6518 emit_cmpimm(s1l,1);
6519 if(s1h>=0) emit_mov(addr,ntaddr);
6520 emit_cmovl_reg(alt,addr);
6521 if(s1h>=0) {
6522 emit_test(s1h,s1h);
6523 emit_cmovne_reg(ntaddr,addr);
6524 emit_cmovs_reg(alt,addr);
6525 }
6526 }
6527 if((opcode[i]&0x3f)==7) // BGTZ
6528 {
6529 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6530 emit_cmpimm(s1l,1);
6531 if(s1h>=0) emit_mov(addr,alt);
6532 emit_cmovl_reg(ntaddr,addr);
6533 if(s1h>=0) {
6534 emit_test(s1h,s1h);
6535 emit_cmovne_reg(alt,addr);
6536 emit_cmovs_reg(ntaddr,addr);
6537 }
6538 }
6539 if((opcode[i]&0x3f)==0x16) // BLEZL
6540 {
6541 assert((opcode[i]&0x3f)!=0x16);
6542 }
6543 if((opcode[i]&0x3f)==0x17) // BGTZL
6544 {
6545 assert((opcode[i]&0x3f)!=0x17);
6546 }
6547 assert(opcode[i]!=1); // BLTZ/BGEZ
6548
6549 //FIXME: Check CSREG
6550 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6551 if((source[i]&0x30000)==0) // BC1F
6552 {
6553 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6554 emit_testimm(s1l,0x800000);
6555 emit_cmovne_reg(alt,addr);
6556 }
6557 if((source[i]&0x30000)==0x10000) // BC1T
6558 {
6559 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6560 emit_testimm(s1l,0x800000);
6561 emit_cmovne_reg(alt,addr);
6562 }
6563 if((source[i]&0x30000)==0x20000) // BC1FL
6564 {
6565 emit_testimm(s1l,0x800000);
6566 nottaken=(int)out;
6567 emit_jne(0);
6568 }
6569 if((source[i]&0x30000)==0x30000) // BC1TL
6570 {
6571 emit_testimm(s1l,0x800000);
6572 nottaken=(int)out;
6573 emit_jeq(0);
6574 }
6575 }
6576
6577 assert(i_regs->regmap[HOST_CCREG]==CCREG);
6578 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6579 if(likely[i]||unconditional)
6580 {
6581 emit_movimm(ba[i],HOST_BTREG);
6582 }
6583 else if(addr!=HOST_BTREG)
6584 {
6585 emit_mov(addr,HOST_BTREG);
6586 }
6587 void *branch_addr=out;
6588 emit_jmp(0);
6589 int target_addr=start+i*4+5;
6590 void *stub=out;
6591 void *compiled_target_addr=check_addr(target_addr);
6592 emit_extjump_ds((int)branch_addr,target_addr);
6593 if(compiled_target_addr) {
6594 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6595 add_link(target_addr,stub);
6596 }
6597 else set_jump_target((int)branch_addr,(int)stub);
6598 if(likely[i]) {
6599 // Not-taken path
6600 set_jump_target((int)nottaken,(int)out);
6601 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6602 void *branch_addr=out;
6603 emit_jmp(0);
6604 int target_addr=start+i*4+8;
6605 void *stub=out;
6606 void *compiled_target_addr=check_addr(target_addr);
6607 emit_extjump_ds((int)branch_addr,target_addr);
6608 if(compiled_target_addr) {
6609 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6610 add_link(target_addr,stub);
6611 }
6612 else set_jump_target((int)branch_addr,(int)stub);
6613 }
6614}
6615
6616// Assemble the delay slot for the above
6617static void pagespan_ds()
6618{
6619 assem_debug("initial delay slot:\n");
6620 u_int vaddr=start+1;
94d23bb9 6621 u_int page=get_page(vaddr);
6622 u_int vpage=get_vpage(vaddr);
57871462 6623 ll_add(jump_dirty+vpage,vaddr,(void *)out);
6624 do_dirty_stub_ds();
6625 ll_add(jump_in+page,vaddr,(void *)out);
6626 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6627 if(regs[0].regmap[HOST_CCREG]!=CCREG)
6628 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6629 if(regs[0].regmap[HOST_BTREG]!=BTREG)
6630 emit_writeword(HOST_BTREG,(int)&branch_target);
6631 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6632 address_generation(0,&regs[0],regs[0].regmap_entry);
b9b61529 6633 if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
57871462 6634 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6635 cop1_usable=0;
6636 is_delayslot=0;
6637 switch(itype[0]) {
6638 case ALU:
6639 alu_assemble(0,&regs[0]);break;
6640 case IMM16:
6641 imm16_assemble(0,&regs[0]);break;
6642 case SHIFT:
6643 shift_assemble(0,&regs[0]);break;
6644 case SHIFTIMM:
6645 shiftimm_assemble(0,&regs[0]);break;
6646 case LOAD:
6647 load_assemble(0,&regs[0]);break;
6648 case LOADLR:
6649 loadlr_assemble(0,&regs[0]);break;
6650 case STORE:
6651 store_assemble(0,&regs[0]);break;
6652 case STORELR:
6653 storelr_assemble(0,&regs[0]);break;
6654 case COP0:
6655 cop0_assemble(0,&regs[0]);break;
6656 case COP1:
6657 cop1_assemble(0,&regs[0]);break;
6658 case C1LS:
6659 c1ls_assemble(0,&regs[0]);break;
b9b61529 6660 case COP2:
6661 cop2_assemble(0,&regs[0]);break;
6662 case C2LS:
6663 c2ls_assemble(0,&regs[0]);break;
6664 case C2OP:
6665 c2op_assemble(0,&regs[0]);break;
57871462 6666 case FCONV:
6667 fconv_assemble(0,&regs[0]);break;
6668 case FLOAT:
6669 float_assemble(0,&regs[0]);break;
6670 case FCOMP:
6671 fcomp_assemble(0,&regs[0]);break;
6672 case MULTDIV:
6673 multdiv_assemble(0,&regs[0]);break;
6674 case MOV:
6675 mov_assemble(0,&regs[0]);break;
6676 case SYSCALL:
7139f3c8 6677 case HLECALL:
1e973cb0 6678 case INTCALL:
57871462 6679 case SPAN:
6680 case UJUMP:
6681 case RJUMP:
6682 case CJUMP:
6683 case SJUMP:
6684 case FJUMP:
6685 printf("Jump in the delay slot. This is probably a bug.\n");
6686 }
6687 int btaddr=get_reg(regs[0].regmap,BTREG);
6688 if(btaddr<0) {
6689 btaddr=get_reg(regs[0].regmap,-1);
6690 emit_readword((int)&branch_target,btaddr);
6691 }
6692 assert(btaddr!=HOST_CCREG);
6693 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6694#ifdef HOST_IMM8
6695 emit_movimm(start+4,HOST_TEMPREG);
6696 emit_cmp(btaddr,HOST_TEMPREG);
6697#else
6698 emit_cmpimm(btaddr,start+4);
6699#endif
6700 int branch=(int)out;
6701 emit_jeq(0);
6702 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6703 emit_jmp(jump_vaddr_reg[btaddr]);
6704 set_jump_target(branch,(int)out);
6705 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6706 load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6707}
6708
6709// Basic liveness analysis for MIPS registers
6710void unneeded_registers(int istart,int iend,int r)
6711{
6712 int i;
6713 uint64_t u,uu,b,bu;
6714 uint64_t temp_u,temp_uu;
6715 uint64_t tdep;
6716 if(iend==slen-1) {
6717 u=1;uu=1;
6718 }else{
6719 u=unneeded_reg[iend+1];
6720 uu=unneeded_reg_upper[iend+1];
6721 u=1;uu=1;
6722 }
6723 for (i=iend;i>=istart;i--)
6724 {
6725 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6726 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6727 {
6728 // If subroutine call, flag return address as a possible branch target
6729 if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6730
6731 if(ba[i]<start || ba[i]>=(start+slen*4))
6732 {
6733 // Branch out of this block, flush all regs
6734 u=1;
6735 uu=1;
6736 /* Hexagon hack
6737 if(itype[i]==UJUMP&&rt1[i]==31)
6738 {
6739 uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6740 }
6741 if(itype[i]==RJUMP&&rs1[i]==31)
6742 {
6743 uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6744 }
4cb76aa4 6745 if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
57871462 6746 if(itype[i]==UJUMP&&rt1[i]==31)
6747 {
6748 //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6749 uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6750 }
6751 if(itype[i]==RJUMP&&rs1[i]==31)
6752 {
6753 //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6754 uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6755 }
6756 }*/
6757 branch_unneeded_reg[i]=u;
6758 branch_unneeded_reg_upper[i]=uu;
6759 // Merge in delay slot
6760 tdep=(~uu>>rt1[i+1])&1;
6761 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6762 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6763 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6764 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6765 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6766 u|=1;uu|=1;
6767 // If branch is "likely" (and conditional)
6768 // then we skip the delay slot on the fall-thru path
6769 if(likely[i]) {
6770 if(i<slen-1) {
6771 u&=unneeded_reg[i+2];
6772 uu&=unneeded_reg_upper[i+2];
6773 }
6774 else
6775 {
6776 u=1;
6777 uu=1;
6778 }
6779 }
6780 }
6781 else
6782 {
6783 // Internal branch, flag target
6784 bt[(ba[i]-start)>>2]=1;
6785 if(ba[i]<=start+i*4) {
6786 // Backward branch
6787 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6788 {
6789 // Unconditional branch
6790 temp_u=1;temp_uu=1;
6791 } else {
6792 // Conditional branch (not taken case)
6793 temp_u=unneeded_reg[i+2];
6794 temp_uu=unneeded_reg_upper[i+2];
6795 }
6796 // Merge in delay slot
6797 tdep=(~temp_uu>>rt1[i+1])&1;
6798 temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6799 temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6800 temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6801 temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6802 temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6803 temp_u|=1;temp_uu|=1;
6804 // If branch is "likely" (and conditional)
6805 // then we skip the delay slot on the fall-thru path
6806 if(likely[i]) {
6807 if(i<slen-1) {
6808 temp_u&=unneeded_reg[i+2];
6809 temp_uu&=unneeded_reg_upper[i+2];
6810 }
6811 else
6812 {
6813 temp_u=1;
6814 temp_uu=1;
6815 }
6816 }
6817 tdep=(~temp_uu>>rt1[i])&1;
6818 temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6819 temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6820 temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6821 temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6822 temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6823 temp_u|=1;temp_uu|=1;
6824 unneeded_reg[i]=temp_u;
6825 unneeded_reg_upper[i]=temp_uu;
6826 // Only go three levels deep. This recursion can take an
6827 // excessive amount of time if there are a lot of nested loops.
6828 if(r<2) {
6829 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6830 }else{
6831 unneeded_reg[(ba[i]-start)>>2]=1;
6832 unneeded_reg_upper[(ba[i]-start)>>2]=1;
6833 }
6834 } /*else*/ if(1) {
6835 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6836 {
6837 // Unconditional branch
6838 u=unneeded_reg[(ba[i]-start)>>2];
6839 uu=unneeded_reg_upper[(ba[i]-start)>>2];
6840 branch_unneeded_reg[i]=u;
6841 branch_unneeded_reg_upper[i]=uu;
6842 //u=1;
6843 //uu=1;
6844 //branch_unneeded_reg[i]=u;
6845 //branch_unneeded_reg_upper[i]=uu;
6846 // Merge in delay slot
6847 tdep=(~uu>>rt1[i+1])&1;
6848 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6849 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6850 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6851 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6852 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6853 u|=1;uu|=1;
6854 } else {
6855 // Conditional branch
6856 b=unneeded_reg[(ba[i]-start)>>2];
6857 bu=unneeded_reg_upper[(ba[i]-start)>>2];
6858 branch_unneeded_reg[i]=b;
6859 branch_unneeded_reg_upper[i]=bu;
6860 //b=1;
6861 //bu=1;
6862 //branch_unneeded_reg[i]=b;
6863 //branch_unneeded_reg_upper[i]=bu;
6864 // Branch delay slot
6865 tdep=(~uu>>rt1[i+1])&1;
6866 b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6867 bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6868 b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6869 bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6870 bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6871 b|=1;bu|=1;
6872 // If branch is "likely" then we skip the
6873 // delay slot on the fall-thru path
6874 if(likely[i]) {
6875 u=b;
6876 uu=bu;
6877 if(i<slen-1) {
6878 u&=unneeded_reg[i+2];
6879 uu&=unneeded_reg_upper[i+2];
6880 //u=1;
6881 //uu=1;
6882 }
6883 } else {
6884 u&=b;
6885 uu&=bu;
6886 //u=1;
6887 //uu=1;
6888 }
6889 if(i<slen-1) {
6890 branch_unneeded_reg[i]&=unneeded_reg[i+2];
6891 branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6892 //branch_unneeded_reg[i]=1;
6893 //branch_unneeded_reg_upper[i]=1;
6894 } else {
6895 branch_unneeded_reg[i]=1;
6896 branch_unneeded_reg_upper[i]=1;
6897 }
6898 }
6899 }
6900 }
6901 }
1e973cb0 6902 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 6903 {
6904 // SYSCALL instruction (software interrupt)
6905 u=1;
6906 uu=1;
6907 }
6908 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6909 {
6910 // ERET instruction (return from interrupt)
6911 u=1;
6912 uu=1;
6913 }
6914 //u=uu=1; // DEBUG
6915 tdep=(~uu>>rt1[i])&1;
6916 // Written registers are unneeded
6917 u|=1LL<<rt1[i];
6918 u|=1LL<<rt2[i];
6919 uu|=1LL<<rt1[i];
6920 uu|=1LL<<rt2[i];
6921 // Accessed registers are needed
6922 u&=~(1LL<<rs1[i]);
6923 u&=~(1LL<<rs2[i]);
6924 uu&=~(1LL<<us1[i]);
6925 uu&=~(1LL<<us2[i]);
6926 // Source-target dependencies
6927 uu&=~(tdep<<dep1[i]);
6928 uu&=~(tdep<<dep2[i]);
6929 // R0 is always unneeded
6930 u|=1;uu|=1;
6931 // Save it
6932 unneeded_reg[i]=u;
6933 unneeded_reg_upper[i]=uu;
6934 /*
6935 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6936 printf("U:");
6937 int r;
6938 for(r=1;r<=CCREG;r++) {
6939 if((unneeded_reg[i]>>r)&1) {
6940 if(r==HIREG) printf(" HI");
6941 else if(r==LOREG) printf(" LO");
6942 else printf(" r%d",r);
6943 }
6944 }
6945 printf(" UU:");
6946 for(r=1;r<=CCREG;r++) {
6947 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
6948 if(r==HIREG) printf(" HI");
6949 else if(r==LOREG) printf(" LO");
6950 else printf(" r%d",r);
6951 }
6952 }
6953 printf("\n");*/
6954 }
252c20fc 6955#ifdef FORCE32
6956 for (i=iend;i>=istart;i--)
6957 {
6958 unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
6959 }
6960#endif
57871462 6961}
6962
6963// Identify registers which are likely to contain 32-bit values
6964// This is used to predict whether any branches will jump to a
6965// location with 64-bit values in registers.
6966static void provisional_32bit()
6967{
6968 int i,j;
6969 uint64_t is32=1;
6970 uint64_t lastbranch=1;
6971
6972 for(i=0;i<slen;i++)
6973 {
6974 if(i>0) {
6975 if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
6976 if(i>1) is32=lastbranch;
6977 else is32=1;
6978 }
6979 }
6980 if(i>1)
6981 {
6982 if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
6983 if(likely[i-2]) {
6984 if(i>2) is32=lastbranch;
6985 else is32=1;
6986 }
6987 }
6988 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
6989 {
6990 if(rs1[i-2]==0||rs2[i-2]==0)
6991 {
6992 if(rs1[i-2]) {
6993 is32|=1LL<<rs1[i-2];
6994 }
6995 if(rs2[i-2]) {
6996 is32|=1LL<<rs2[i-2];
6997 }
6998 }
6999 }
7000 }
7001 // If something jumps here with 64-bit values
7002 // then promote those registers to 64 bits
7003 if(bt[i])
7004 {
7005 uint64_t temp_is32=is32;
7006 for(j=i-1;j>=0;j--)
7007 {
7008 if(ba[j]==start+i*4)
7009 //temp_is32&=branch_regs[j].is32;
7010 temp_is32&=p32[j];
7011 }
7012 for(j=i;j<slen;j++)
7013 {
7014 if(ba[j]==start+i*4)
7015 temp_is32=1;
7016 }
7017 is32=temp_is32;
7018 }
7019 int type=itype[i];
7020 int op=opcode[i];
7021 int op2=opcode2[i];
7022 int rt=rt1[i];
7023 int s1=rs1[i];
7024 int s2=rs2[i];
7025 if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
7026 // Branches don't write registers, consider the delay slot instead.
7027 type=itype[i+1];
7028 op=opcode[i+1];
7029 op2=opcode2[i+1];
7030 rt=rt1[i+1];
7031 s1=rs1[i+1];
7032 s2=rs2[i+1];
7033 lastbranch=is32;
7034 }
7035 switch(type) {
7036 case LOAD:
7037 if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
7038 opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
7039 is32&=~(1LL<<rt);
7040 else
7041 is32|=1LL<<rt;
7042 break;
7043 case STORE:
7044 case STORELR:
7045 break;
7046 case LOADLR:
7047 if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
7048 if(op==0x22) is32|=1LL<<rt; // LWL
7049 break;
7050 case IMM16:
7051 if (op==0x08||op==0x09|| // ADDI/ADDIU
7052 op==0x0a||op==0x0b|| // SLTI/SLTIU
7053 op==0x0c|| // ANDI
7054 op==0x0f) // LUI
7055 {
7056 is32|=1LL<<rt;
7057 }
7058 if(op==0x18||op==0x19) { // DADDI/DADDIU
7059 is32&=~(1LL<<rt);
7060 //if(imm[i]==0)
7061 // is32|=((is32>>s1)&1LL)<<rt;
7062 }
7063 if(op==0x0d||op==0x0e) { // ORI/XORI
7064 uint64_t sr=((is32>>s1)&1LL);
7065 is32&=~(1LL<<rt);
7066 is32|=sr<<rt;
7067 }
7068 break;
7069 case UJUMP:
7070 break;
7071 case RJUMP:
7072 break;
7073 case CJUMP:
7074 break;
7075 case SJUMP:
7076 break;
7077 case FJUMP:
7078 break;
7079 case ALU:
7080 if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
7081 is32|=1LL<<rt;
7082 }
7083 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
7084 is32|=1LL<<rt;
7085 }
7086 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
7087 uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
7088 is32&=~(1LL<<rt);
7089 is32|=sr<<rt;
7090 }
7091 else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
7092 if(s1==0&&s2==0) {
7093 is32|=1LL<<rt;
7094 }
7095 else if(s2==0) {
7096 uint64_t sr=((is32>>s1)&1LL);
7097 is32&=~(1LL<<rt);
7098 is32|=sr<<rt;
7099 }
7100 else if(s1==0) {
7101 uint64_t sr=((is32>>s2)&1LL);
7102 is32&=~(1LL<<rt);
7103 is32|=sr<<rt;
7104 }
7105 else {
7106 is32&=~(1LL<<rt);
7107 }
7108 }
7109 else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
7110 if(s1==0&&s2==0) {
7111 is32|=1LL<<rt;
7112 }
7113 else if(s2==0) {
7114 uint64_t sr=((is32>>s1)&1LL);
7115 is32&=~(1LL<<rt);
7116 is32|=sr<<rt;
7117 }
7118 else {
7119 is32&=~(1LL<<rt);
7120 }
7121 }
7122 break;
7123 case MULTDIV:
7124 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
7125 is32&=~((1LL<<HIREG)|(1LL<<LOREG));
7126 }
7127 else {
7128 is32|=(1LL<<HIREG)|(1LL<<LOREG);
7129 }
7130 break;
7131 case MOV:
7132 {
7133 uint64_t sr=((is32>>s1)&1LL);
7134 is32&=~(1LL<<rt);
7135 is32|=sr<<rt;
7136 }
7137 break;
7138 case SHIFT:
7139 if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
7140 else is32|=1LL<<rt; // SLLV/SRLV/SRAV
7141 break;
7142 case SHIFTIMM:
7143 is32|=1LL<<rt;
7144 // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
7145 if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
7146 break;
7147 case COP0:
7148 if(op2==0) is32|=1LL<<rt; // MFC0
7149 break;
7150 case COP1:
b9b61529 7151 case COP2:
57871462 7152 if(op2==0) is32|=1LL<<rt; // MFC1
7153 if(op2==1) is32&=~(1LL<<rt); // DMFC1
7154 if(op2==2) is32|=1LL<<rt; // CFC1
7155 break;
7156 case C1LS:
b9b61529 7157 case C2LS:
57871462 7158 break;
7159 case FLOAT:
7160 case FCONV:
7161 break;
7162 case FCOMP:
7163 break;
b9b61529 7164 case C2OP:
57871462 7165 case SYSCALL:
7139f3c8 7166 case HLECALL:
57871462 7167 break;
7168 default:
7169 break;
7170 }
7171 is32|=1;
7172 p32[i]=is32;
7173
7174 if(i>0)
7175 {
7176 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
7177 {
7178 if(rt1[i-1]==31) // JAL/JALR
7179 {
7180 // Subroutine call will return here, don't alloc any registers
7181 is32=1;
7182 }
7183 else if(i+1<slen)
7184 {
7185 // Internal branch will jump here, match registers to caller
7186 is32=0x3FFFFFFFFLL;
7187 }
7188 }
7189 }
7190 }
7191}
7192
7193// Identify registers which may be assumed to contain 32-bit values
7194// and where optimizations will rely on this.
7195// This is used to determine whether backward branches can safely
7196// jump to a location with 64-bit values in registers.
7197static void provisional_r32()
7198{
7199 u_int r32=0;
7200 int i;
7201
7202 for (i=slen-1;i>=0;i--)
7203 {
7204 int hr;
7205 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7206 {
7207 if(ba[i]<start || ba[i]>=(start+slen*4))
7208 {
7209 // Branch out of this block, don't need anything
7210 r32=0;
7211 }
7212 else
7213 {
7214 // Internal branch
7215 // Need whatever matches the target
7216 // (and doesn't get overwritten by the delay slot instruction)
7217 r32=0;
7218 int t=(ba[i]-start)>>2;
7219 if(ba[i]>start+i*4) {
7220 // Forward branch
7221 //if(!(requires_32bit[t]&~regs[i].was32))
7222 // r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7223 if(!(pr32[t]&~regs[i].was32))
7224 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7225 }else{
7226 // Backward branch
7227 if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
7228 r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7229 }
7230 }
7231 // Conditional branch may need registers for following instructions
7232 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7233 {
7234 if(i<slen-2) {
7235 //r32|=requires_32bit[i+2];
7236 r32|=pr32[i+2];
7237 r32&=regs[i].was32;
7238 // Mark this address as a branch target since it may be called
7239 // upon return from interrupt
7240 //bt[i+2]=1;
7241 }
7242 }
7243 // Merge in delay slot
7244 if(!likely[i]) {
7245 // These are overwritten unless the branch is "likely"
7246 // and the delay slot is nullified if not taken
7247 r32&=~(1LL<<rt1[i+1]);
7248 r32&=~(1LL<<rt2[i+1]);
7249 }
7250 // Assume these are needed (delay slot)
7251 if(us1[i+1]>0)
7252 {
7253 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7254 }
7255 if(us2[i+1]>0)
7256 {
7257 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7258 }
7259 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7260 {
7261 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7262 }
7263 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7264 {
7265 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7266 }
7267 }
1e973cb0 7268 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 7269 {
7270 // SYSCALL instruction (software interrupt)
7271 r32=0;
7272 }
7273 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7274 {
7275 // ERET instruction (return from interrupt)
7276 r32=0;
7277 }
7278 // Check 32 bits
7279 r32&=~(1LL<<rt1[i]);
7280 r32&=~(1LL<<rt2[i]);
7281 if(us1[i]>0)
7282 {
7283 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7284 }
7285 if(us2[i]>0)
7286 {
7287 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7288 }
7289 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7290 {
7291 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7292 }
7293 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7294 {
7295 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7296 }
7297 //requires_32bit[i]=r32;
7298 pr32[i]=r32;
7299
7300 // Dirty registers which are 32-bit, require 32-bit input
7301 // as they will be written as 32-bit values
7302 for(hr=0;hr<HOST_REGS;hr++)
7303 {
7304 if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
7305 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7306 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7307 pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7308 //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7309 }
7310 }
7311 }
7312 }
7313}
7314
7315// Write back dirty registers as soon as we will no longer modify them,
7316// so that we don't end up with lots of writes at the branches.
7317void clean_registers(int istart,int iend,int wr)
7318{
7319 int i;
7320 int r;
7321 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7322 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7323 if(iend==slen-1) {
7324 will_dirty_i=will_dirty_next=0;
7325 wont_dirty_i=wont_dirty_next=0;
7326 }else{
7327 will_dirty_i=will_dirty_next=will_dirty[iend+1];
7328 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7329 }
7330 for (i=iend;i>=istart;i--)
7331 {
7332 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7333 {
7334 if(ba[i]<start || ba[i]>=(start+slen*4))
7335 {
7336 // Branch out of this block, flush all regs
7337 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7338 {
7339 // Unconditional branch
7340 will_dirty_i=0;
7341 wont_dirty_i=0;
7342 // Merge in delay slot (will dirty)
7343 for(r=0;r<HOST_REGS;r++) {
7344 if(r!=EXCLUDE_REG) {
7345 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7346 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7347 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7348 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7349 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7350 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7351 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7352 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7353 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7354 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7355 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7356 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7357 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7358 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7359 }
7360 }
7361 }
7362 else
7363 {
7364 // Conditional branch
7365 will_dirty_i=0;
7366 wont_dirty_i=wont_dirty_next;
7367 // Merge in delay slot (will dirty)
7368 for(r=0;r<HOST_REGS;r++) {
7369 if(r!=EXCLUDE_REG) {
7370 if(!likely[i]) {
7371 // Might not dirty if likely branch is not taken
7372 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7373 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7374 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7375 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7376 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7377 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7378 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7379 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7380 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7381 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7382 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7383 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7384 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7385 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7386 }
7387 }
7388 }
7389 }
7390 // Merge in delay slot (wont dirty)
7391 for(r=0;r<HOST_REGS;r++) {
7392 if(r!=EXCLUDE_REG) {
7393 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7394 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7395 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7396 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7397 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7398 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7399 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7400 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7401 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7402 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7403 }
7404 }
7405 if(wr) {
7406 #ifndef DESTRUCTIVE_WRITEBACK
7407 branch_regs[i].dirty&=wont_dirty_i;
7408 #endif
7409 branch_regs[i].dirty|=will_dirty_i;
7410 }
7411 }
7412 else
7413 {
7414 // Internal branch
7415 if(ba[i]<=start+i*4) {
7416 // Backward branch
7417 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7418 {
7419 // Unconditional branch
7420 temp_will_dirty=0;
7421 temp_wont_dirty=0;
7422 // Merge in delay slot (will dirty)
7423 for(r=0;r<HOST_REGS;r++) {
7424 if(r!=EXCLUDE_REG) {
7425 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7426 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7427 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7428 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7429 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7430 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7431 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7432 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7433 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7434 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7435 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7436 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7437 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7438 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7439 }
7440 }
7441 } else {
7442 // Conditional branch (not taken case)
7443 temp_will_dirty=will_dirty_next;
7444 temp_wont_dirty=wont_dirty_next;
7445 // Merge in delay slot (will dirty)
7446 for(r=0;r<HOST_REGS;r++) {
7447 if(r!=EXCLUDE_REG) {
7448 if(!likely[i]) {
7449 // Will not dirty if likely branch is not taken
7450 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7451 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7452 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7453 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7454 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7455 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7456 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7457 //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7458 //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7459 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7460 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7461 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7462 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7463 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7464 }
7465 }
7466 }
7467 }
7468 // Merge in delay slot (wont dirty)
7469 for(r=0;r<HOST_REGS;r++) {
7470 if(r!=EXCLUDE_REG) {
7471 if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7472 if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7473 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7474 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7475 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7476 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7477 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7478 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7479 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7480 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7481 }
7482 }
7483 // Deal with changed mappings
7484 if(i<iend) {
7485 for(r=0;r<HOST_REGS;r++) {
7486 if(r!=EXCLUDE_REG) {
7487 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7488 temp_will_dirty&=~(1<<r);
7489 temp_wont_dirty&=~(1<<r);
7490 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7491 temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7492 temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7493 } else {
7494 temp_will_dirty|=1<<r;
7495 temp_wont_dirty|=1<<r;
7496 }
7497 }
7498 }
7499 }
7500 }
7501 if(wr) {
7502 will_dirty[i]=temp_will_dirty;
7503 wont_dirty[i]=temp_wont_dirty;
7504 clean_registers((ba[i]-start)>>2,i-1,0);
7505 }else{
7506 // Limit recursion. It can take an excessive amount
7507 // of time if there are a lot of nested loops.
7508 will_dirty[(ba[i]-start)>>2]=0;
7509 wont_dirty[(ba[i]-start)>>2]=-1;
7510 }
7511 }
7512 /*else*/ if(1)
7513 {
7514 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7515 {
7516 // Unconditional branch
7517 will_dirty_i=0;
7518 wont_dirty_i=0;
7519 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7520 for(r=0;r<HOST_REGS;r++) {
7521 if(r!=EXCLUDE_REG) {
7522 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7523 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7524 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7525 }
e3234ecf 7526 if(branch_regs[i].regmap[r]>=0) {
7527 will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7528 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7529 }
57871462 7530 }
7531 }
7532 //}
7533 // Merge in delay slot
7534 for(r=0;r<HOST_REGS;r++) {
7535 if(r!=EXCLUDE_REG) {
7536 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7537 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7538 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7539 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7540 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7541 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7542 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7543 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7544 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7545 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7546 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7547 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7548 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7549 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7550 }
7551 }
7552 } else {
7553 // Conditional branch
7554 will_dirty_i=will_dirty_next;
7555 wont_dirty_i=wont_dirty_next;
7556 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7557 for(r=0;r<HOST_REGS;r++) {
7558 if(r!=EXCLUDE_REG) {
e3234ecf 7559 signed char target_reg=branch_regs[i].regmap[r];
7560 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
57871462 7561 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7562 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7563 }
e3234ecf 7564 else if(target_reg>=0) {
7565 will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7566 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
57871462 7567 }
7568 // Treat delay slot as part of branch too
7569 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7570 will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7571 wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7572 }
7573 else
7574 {
7575 will_dirty[i+1]&=~(1<<r);
7576 }*/
7577 }
7578 }
7579 //}
7580 // Merge in delay slot
7581 for(r=0;r<HOST_REGS;r++) {
7582 if(r!=EXCLUDE_REG) {
7583 if(!likely[i]) {
7584 // Might not dirty if likely branch is not taken
7585 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7586 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7587 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7588 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7589 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7590 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7591 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7592 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7593 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7594 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7595 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7596 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7597 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7598 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7599 }
7600 }
7601 }
7602 }
e3234ecf 7603 // Merge in delay slot (won't dirty)
57871462 7604 for(r=0;r<HOST_REGS;r++) {
7605 if(r!=EXCLUDE_REG) {
7606 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7607 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7608 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7609 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7610 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7611 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7612 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7613 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7614 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7615 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7616 }
7617 }
7618 if(wr) {
7619 #ifndef DESTRUCTIVE_WRITEBACK
7620 branch_regs[i].dirty&=wont_dirty_i;
7621 #endif
7622 branch_regs[i].dirty|=will_dirty_i;
7623 }
7624 }
7625 }
7626 }
1e973cb0 7627 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 7628 {
7629 // SYSCALL instruction (software interrupt)
7630 will_dirty_i=0;
7631 wont_dirty_i=0;
7632 }
7633 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7634 {
7635 // ERET instruction (return from interrupt)
7636 will_dirty_i=0;
7637 wont_dirty_i=0;
7638 }
7639 will_dirty_next=will_dirty_i;
7640 wont_dirty_next=wont_dirty_i;
7641 for(r=0;r<HOST_REGS;r++) {
7642 if(r!=EXCLUDE_REG) {
7643 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7644 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7645 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7646 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7647 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7648 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7649 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7650 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7651 if(i>istart) {
7652 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7653 {
7654 // Don't store a register immediately after writing it,
7655 // may prevent dual-issue.
7656 if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7657 if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7658 }
7659 }
7660 }
7661 }
7662 // Save it
7663 will_dirty[i]=will_dirty_i;
7664 wont_dirty[i]=wont_dirty_i;
7665 // Mark registers that won't be dirtied as not dirty
7666 if(wr) {
7667 /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7668 for(r=0;r<HOST_REGS;r++) {
7669 if((will_dirty_i>>r)&1) {
7670 printf(" r%d",r);
7671 }
7672 }
7673 printf("\n");*/
7674
7675 //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7676 regs[i].dirty|=will_dirty_i;
7677 #ifndef DESTRUCTIVE_WRITEBACK
7678 regs[i].dirty&=wont_dirty_i;
7679 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7680 {
7681 if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7682 for(r=0;r<HOST_REGS;r++) {
7683 if(r!=EXCLUDE_REG) {
7684 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7685 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7686 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7687 }
7688 }
7689 }
7690 }
7691 else
7692 {
7693 if(i<iend) {
7694 for(r=0;r<HOST_REGS;r++) {
7695 if(r!=EXCLUDE_REG) {
7696 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7697 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7698 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7699 }
7700 }
7701 }
7702 }
7703 #endif
7704 //}
7705 }
7706 // Deal with changed mappings
7707 temp_will_dirty=will_dirty_i;
7708 temp_wont_dirty=wont_dirty_i;
7709 for(r=0;r<HOST_REGS;r++) {
7710 if(r!=EXCLUDE_REG) {
7711 int nr;
7712 if(regs[i].regmap[r]==regmap_pre[i][r]) {
7713 if(wr) {
7714 #ifndef DESTRUCTIVE_WRITEBACK
7715 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7716 #endif
7717 regs[i].wasdirty|=will_dirty_i&(1<<r);
7718 }
7719 }
f776eb14 7720 else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
57871462 7721 // Register moved to a different register
7722 will_dirty_i&=~(1<<r);
7723 wont_dirty_i&=~(1<<r);
7724 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7725 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7726 if(wr) {
7727 #ifndef DESTRUCTIVE_WRITEBACK
7728 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7729 #endif
7730 regs[i].wasdirty|=will_dirty_i&(1<<r);
7731 }
7732 }
7733 else {
7734 will_dirty_i&=~(1<<r);
7735 wont_dirty_i&=~(1<<r);
7736 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7737 will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7738 wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7739 } else {
7740 wont_dirty_i|=1<<r;
7741 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7742 }
7743 }
7744 }
7745 }
7746 }
7747}
7748
7749 /* disassembly */
7750void disassemble_inst(int i)
7751{
7752 if (bt[i]) printf("*"); else printf(" ");
7753 switch(itype[i]) {
7754 case UJUMP:
7755 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7756 case CJUMP:
7757 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7758 case SJUMP:
7759 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7760 case FJUMP:
7761 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7762 case RJUMP:
74426039 7763 if (opcode[i]==0x9&&rt1[i]!=31)
5067f341 7764 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7765 else
7766 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7767 break;
57871462 7768 case SPAN:
7769 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7770 case IMM16:
7771 if(opcode[i]==0xf) //LUI
7772 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7773 else
7774 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7775 break;
7776 case LOAD:
7777 case LOADLR:
7778 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7779 break;
7780 case STORE:
7781 case STORELR:
7782 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7783 break;
7784 case ALU:
7785 case SHIFT:
7786 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7787 break;
7788 case MULTDIV:
7789 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7790 break;
7791 case SHIFTIMM:
7792 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7793 break;
7794 case MOV:
7795 if((opcode2[i]&0x1d)==0x10)
7796 printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7797 else if((opcode2[i]&0x1d)==0x11)
7798 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7799 else
7800 printf (" %x: %s\n",start+i*4,insn[i]);
7801 break;
7802 case COP0:
7803 if(opcode2[i]==0)
7804 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7805 else if(opcode2[i]==4)
7806 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7807 else printf (" %x: %s\n",start+i*4,insn[i]);
7808 break;
7809 case COP1:
7810 if(opcode2[i]<3)
7811 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7812 else if(opcode2[i]>3)
7813 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7814 else printf (" %x: %s\n",start+i*4,insn[i]);
7815 break;
b9b61529 7816 case COP2:
7817 if(opcode2[i]<3)
7818 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7819 else if(opcode2[i]>3)
7820 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7821 else printf (" %x: %s\n",start+i*4,insn[i]);
7822 break;
57871462 7823 case C1LS:
7824 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7825 break;
b9b61529 7826 case C2LS:
7827 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7828 break;
1e973cb0 7829 case INTCALL:
7830 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
7831 break;
57871462 7832 default:
7833 //printf (" %s %8x\n",insn[i],source[i]);
7834 printf (" %x: %s\n",start+i*4,insn[i]);
7835 }
7836}
7837
dc990066 7838// clear the state completely, instead of just marking
7839// things invalid like invalidate_all_pages() does
7840void new_dynarec_clear_full()
57871462 7841{
57871462 7842 int n;
35775df7 7843 out=(u_char *)BASE_ADDR;
7844 memset(invalid_code,1,sizeof(invalid_code));
7845 memset(hash_table,0xff,sizeof(hash_table));
57871462 7846 memset(mini_ht,-1,sizeof(mini_ht));
7847 memset(restore_candidate,0,sizeof(restore_candidate));
dc990066 7848 memset(shadow,0,sizeof(shadow));
57871462 7849 copy=shadow;
7850 expirep=16384; // Expiry pointer, +2 blocks
7851 pending_exception=0;
7852 literalcount=0;
57871462 7853 stop_after_jal=0;
9be4ba64 7854 inv_code_start=inv_code_end=~0;
57871462 7855 // TLB
af4ee1fe 7856#ifndef DISABLE_TLB
57871462 7857 using_tlb=0;
af4ee1fe 7858#endif
dadf55f2 7859 sp_in_mirror=0;
57871462 7860 for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7861 memory_map[n]=-1;
7862 for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7863 memory_map[n]=((u_int)rdram-0x80000000)>>2;
7864 for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7865 memory_map[n]=-1;
dc990066 7866 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7867 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7868 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7869}
7870
7871void new_dynarec_init()
7872{
7873 printf("Init new dynarec\n");
7874 out=(u_char *)BASE_ADDR;
7875 if (mmap (out, 1<<TARGET_SIZE_2,
7876 PROT_READ | PROT_WRITE | PROT_EXEC,
7877 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
7878 -1, 0) <= 0) {printf("mmap() failed\n");}
7879#ifdef MUPEN64
7880 rdword=&readmem_dword;
7881 fake_pc.f.r.rs=&readmem_dword;
7882 fake_pc.f.r.rt=&readmem_dword;
7883 fake_pc.f.r.rd=&readmem_dword;
7884#endif
7885 int n;
7886 new_dynarec_clear_full();
7887#ifdef HOST_IMM8
7888 // Copy this into local area so we don't have to put it in every literal pool
7889 invc_ptr=invalid_code;
7890#endif
24385cae 7891#ifdef MUPEN64
57871462 7892 for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
7893 writemem[n] = write_nomem_new;
7894 writememb[n] = write_nomemb_new;
7895 writememh[n] = write_nomemh_new;
24385cae 7896#ifndef FORCE32
57871462 7897 writememd[n] = write_nomemd_new;
24385cae 7898#endif
57871462 7899 readmem[n] = read_nomem_new;
7900 readmemb[n] = read_nomemb_new;
7901 readmemh[n] = read_nomemh_new;
24385cae 7902#ifndef FORCE32
57871462 7903 readmemd[n] = read_nomemd_new;
24385cae 7904#endif
57871462 7905 }
7906 for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
7907 writemem[n] = write_rdram_new;
7908 writememb[n] = write_rdramb_new;
7909 writememh[n] = write_rdramh_new;
24385cae 7910#ifndef FORCE32
57871462 7911 writememd[n] = write_rdramd_new;
24385cae 7912#endif
57871462 7913 }
7914 for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
7915 writemem[n] = write_nomem_new;
7916 writememb[n] = write_nomemb_new;
7917 writememh[n] = write_nomemh_new;
24385cae 7918#ifndef FORCE32
57871462 7919 writememd[n] = write_nomemd_new;
24385cae 7920#endif
57871462 7921 readmem[n] = read_nomem_new;
7922 readmemb[n] = read_nomemb_new;
7923 readmemh[n] = read_nomemh_new;
24385cae 7924#ifndef FORCE32
57871462 7925 readmemd[n] = read_nomemd_new;
24385cae 7926#endif
57871462 7927 }
24385cae 7928#endif
57871462 7929 tlb_hacks();
7930 arch_init();
7931}
7932
7933void new_dynarec_cleanup()
7934{
7935 int n;
7936 if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
7937 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7938 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7939 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7940 #ifdef ROM_COPY
7941 if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
7942 #endif
7943}
7944
7945int new_recompile_block(int addr)
7946{
7947/*
7948 if(addr==0x800cd050) {
7949 int block;
7950 for(block=0x80000;block<0x80800;block++) invalidate_block(block);
7951 int n;
7952 for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
7953 }
7954*/
7955 //if(Count==365117028) tracedebug=1;
7956 assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7957 //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7958 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
7959 //if(debug)
7960 //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
7961 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
7962 /*if(Count>=312978186) {
7963 rlist();
7964 }*/
7965 //rlist();
7966 start = (u_int)addr&~3;
7967 //assert(((u_int)addr&1)==0);
7139f3c8 7968#ifdef PCSX
dadf55f2 7969 if(!sp_in_mirror&&(signed int)(psxRegs.GPR.n.sp&0xffe00000)>0x80200000&&
7970 0x10000<=psxRegs.GPR.n.sp&&(psxRegs.GPR.n.sp&~0xe0e00000)<RAM_SIZE) {
c2e3bd42 7971 printf("SP hack enabled (%08x), @%08x\n", psxRegs.GPR.n.sp, psxRegs.pc);
dadf55f2 7972 sp_in_mirror=1;
7973 }
9ad4d757 7974 if (Config.HLE && start == 0x80001000) // hlecall
560e4a12 7975 {
7139f3c8 7976 // XXX: is this enough? Maybe check hleSoftCall?
bb5285ef 7977 u_int beginning=(u_int)out;
7139f3c8 7978 u_int page=get_page(start);
7139f3c8 7979 invalid_code[start>>12]=0;
7980 emit_movimm(start,0);
7981 emit_writeword(0,(int)&pcaddr);
bb5285ef 7982 emit_jmp((int)new_dyna_leave);
7983#ifdef __arm__
7984 __clear_cache((void *)beginning,out);
7985#endif
9ad4d757 7986 ll_add(jump_in+page,start,(void *)beginning);
7139f3c8 7987 return 0;
7988 }
560e4a12 7989 else if ((u_int)addr < 0x00200000 ||
7990 (0xa0000000 <= addr && addr < 0xa0200000)) {
7139f3c8 7991 // used for BIOS calls mostly?
560e4a12 7992 source = (u_int *)((u_int)rdram+(start&0x1fffff));
7993 pagelimit = (addr&0xa0000000)|0x00200000;
7994 }
7995 else if (!Config.HLE && (
7996/* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
7997 (0xbfc00000 <= addr && addr < 0xbfc80000))) {
7998 // BIOS
7999 source = (u_int *)((u_int)psxR+(start&0x7ffff));
8000 pagelimit = (addr&0xfff00000)|0x80000;
7139f3c8 8001 }
8002 else
8003#endif
3d624f89 8004#ifdef MUPEN64
57871462 8005 if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
8006 source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
8007 pagelimit = 0xa4001000;
8008 }
3d624f89 8009 else
8010#endif
4cb76aa4 8011 if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
57871462 8012 source = (u_int *)((u_int)rdram+start-0x80000000);
4cb76aa4 8013 pagelimit = 0x80000000+RAM_SIZE;
57871462 8014 }
90ae6d4e 8015#ifndef DISABLE_TLB
57871462 8016 else if ((signed int)addr >= (signed int)0xC0000000) {
8017 //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
8018 //if(tlb_LUT_r[start>>12])
8019 //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
8020 if((signed int)memory_map[start>>12]>=0) {
8021 source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
8022 pagelimit=(start+4096)&0xFFFFF000;
8023 int map=memory_map[start>>12];
8024 int i;
8025 for(i=0;i<5;i++) {
8026 //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
8027 if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
8028 }
8029 assem_debug("pagelimit=%x\n",pagelimit);
8030 assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
8031 }
8032 else {
8033 assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
8034 //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
560e4a12 8035 return -1; // Caller will invoke exception handler
57871462 8036 }
8037 //printf("source= %x\n",(int)source);
8038 }
90ae6d4e 8039#endif
57871462 8040 else {
8041 printf("Compile at bogus memory address: %x \n", (int)addr);
8042 exit(1);
8043 }
8044
8045 /* Pass 1: disassemble */
8046 /* Pass 2: register dependencies, branch targets */
8047 /* Pass 3: register allocation */
8048 /* Pass 4: branch dependencies */
8049 /* Pass 5: pre-alloc */
8050 /* Pass 6: optimize clean/dirty state */
8051 /* Pass 7: flag 32-bit registers */
8052 /* Pass 8: assembly */
8053 /* Pass 9: linker */
8054 /* Pass 10: garbage collection / free memory */
8055
8056 int i,j;
8057 int done=0;
8058 unsigned int type,op,op2;
8059
8060 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
8061
8062 /* Pass 1 disassembly */
8063
8064 for(i=0;!done;i++) {
e1190b87 8065 bt[i]=0;likely[i]=0;ooo[i]=0;op2=0;
8066 minimum_free_regs[i]=0;
57871462 8067 opcode[i]=op=source[i]>>26;
8068 switch(op)
8069 {
8070 case 0x00: strcpy(insn[i],"special"); type=NI;
8071 op2=source[i]&0x3f;
8072 switch(op2)
8073 {
8074 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
8075 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
8076 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
8077 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
8078 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
8079 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
8080 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
8081 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
8082 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
8083 case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
8084 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
8085 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
8086 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
8087 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
8088 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
57871462 8089 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
8090 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
8091 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
8092 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
57871462 8093 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
8094 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
8095 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
8096 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
8097 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
8098 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
8099 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
8100 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
8101 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
8102 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
57871462 8103 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
8104 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
8105 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
8106 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
8107 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
8108 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
7f2607ea 8109#ifndef FORCE32
8110 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
8111 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
8112 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
8113 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
8114 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
8115 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
8116 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
8117 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
8118 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
8119 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
8120 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
57871462 8121 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
8122 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
8123 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
8124 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
8125 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
8126 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
7f2607ea 8127#endif
57871462 8128 }
8129 break;
8130 case 0x01: strcpy(insn[i],"regimm"); type=NI;
8131 op2=(source[i]>>16)&0x1f;
8132 switch(op2)
8133 {
8134 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
8135 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
8136 case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
8137 case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
8138 case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
8139 case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
8140 case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
8141 case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
8142 case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
8143 case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
8144 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
8145 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
8146 case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
8147 case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
8148 }
8149 break;
8150 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
8151 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
8152 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
8153 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
8154 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
8155 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
8156 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
8157 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
8158 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
8159 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
8160 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
8161 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
8162 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
8163 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
8164 case 0x10: strcpy(insn[i],"cop0"); type=NI;
8165 op2=(source[i]>>21)&0x1f;
8166 switch(op2)
8167 {
8168 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
8169 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
8170 case 0x10: strcpy(insn[i],"tlb"); type=NI;
8171 switch(source[i]&0x3f)
8172 {
8173 case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
8174 case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
8175 case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
8176 case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
576bbd8f 8177#ifdef PCSX
8178 case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
8179#else
57871462 8180 case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
576bbd8f 8181#endif
57871462 8182 }
8183 }
8184 break;
8185 case 0x11: strcpy(insn[i],"cop1"); type=NI;
8186 op2=(source[i]>>21)&0x1f;
8187 switch(op2)
8188 {
8189 case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
8190 case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
8191 case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
8192 case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
8193 case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
8194 case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
8195 case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
8196 switch((source[i]>>16)&0x3)
8197 {
8198 case 0x00: strcpy(insn[i],"BC1F"); break;
8199 case 0x01: strcpy(insn[i],"BC1T"); break;
8200 case 0x02: strcpy(insn[i],"BC1FL"); break;
8201 case 0x03: strcpy(insn[i],"BC1TL"); break;
8202 }
8203 break;
8204 case 0x10: strcpy(insn[i],"C1.S"); type=NI;
8205 switch(source[i]&0x3f)
8206 {
8207 case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
8208 case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
8209 case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
8210 case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
8211 case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
8212 case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
8213 case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
8214 case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
8215 case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
8216 case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
8217 case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
8218 case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
8219 case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
8220 case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
8221 case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
8222 case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
8223 case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
8224 case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
8225 case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
8226 case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
8227 case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
8228 case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
8229 case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
8230 case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
8231 case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
8232 case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
8233 case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
8234 case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
8235 case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
8236 case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
8237 case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
8238 case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
8239 case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
8240 case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
8241 case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
8242 }
8243 break;
8244 case 0x11: strcpy(insn[i],"C1.D"); type=NI;
8245 switch(source[i]&0x3f)
8246 {
8247 case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
8248 case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
8249 case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
8250 case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
8251 case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
8252 case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
8253 case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
8254 case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
8255 case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
8256 case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
8257 case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
8258 case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
8259 case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
8260 case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
8261 case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
8262 case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
8263 case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
8264 case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
8265 case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
8266 case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
8267 case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
8268 case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
8269 case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
8270 case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
8271 case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
8272 case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
8273 case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
8274 case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
8275 case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
8276 case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
8277 case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8278 case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8279 case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8280 case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8281 case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8282 }
8283 break;
8284 case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8285 switch(source[i]&0x3f)
8286 {
8287 case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8288 case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8289 }
8290 break;
8291 case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8292 switch(source[i]&0x3f)
8293 {
8294 case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8295 case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8296 }
8297 break;
8298 }
8299 break;
909168d6 8300#ifndef FORCE32
57871462 8301 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8302 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8303 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8304 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8305 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8306 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8307 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8308 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
996cc15d 8309#endif
57871462 8310 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8311 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8312 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8313 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8314 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8315 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8316 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
64bd6f82 8317#ifndef FORCE32
57871462 8318 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
64bd6f82 8319#endif
57871462 8320 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8321 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8322 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8323 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
996cc15d 8324#ifndef FORCE32
57871462 8325 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8326 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
996cc15d 8327#endif
57871462 8328 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8329 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8330 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8331 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
996cc15d 8332#ifndef FORCE32
57871462 8333 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8334 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8335 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
996cc15d 8336#endif
57871462 8337 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8338 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
996cc15d 8339#ifndef FORCE32
57871462 8340 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8341 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8342 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
996cc15d 8343#endif
b9b61529 8344#ifdef PCSX
8345 case 0x12: strcpy(insn[i],"COP2"); type=NI;
c7abc864 8346 // note: COP MIPS-1 encoding differs from MIPS32
b9b61529 8347 op2=(source[i]>>21)&0x1f;
c7abc864 8348 if (source[i]&0x3f) {
8349 if (gte_handlers[source[i]&0x3f]!=NULL) {
8350 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8351 type=C2OP;
8352 }
8353 }
8354 else switch(op2)
b9b61529 8355 {
8356 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8357 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8358 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8359 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
b9b61529 8360 }
8361 break;
8362 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8363 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8364 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8365#endif
90ae6d4e 8366 default: strcpy(insn[i],"???"); type=NI;
75dec299 8367 printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
90ae6d4e 8368 break;
57871462 8369 }
8370 itype[i]=type;
8371 opcode2[i]=op2;
8372 /* Get registers/immediates */
8373 lt1[i]=0;
8374 us1[i]=0;
8375 us2[i]=0;
8376 dep1[i]=0;
8377 dep2[i]=0;
8378 switch(type) {
8379 case LOAD:
8380 rs1[i]=(source[i]>>21)&0x1f;
8381 rs2[i]=0;
8382 rt1[i]=(source[i]>>16)&0x1f;
8383 rt2[i]=0;
8384 imm[i]=(short)source[i];
8385 break;
8386 case STORE:
8387 case STORELR:
8388 rs1[i]=(source[i]>>21)&0x1f;
8389 rs2[i]=(source[i]>>16)&0x1f;
8390 rt1[i]=0;
8391 rt2[i]=0;
8392 imm[i]=(short)source[i];
8393 if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8394 break;
8395 case LOADLR:
8396 // LWL/LWR only load part of the register,
8397 // therefore the target register must be treated as a source too
8398 rs1[i]=(source[i]>>21)&0x1f;
8399 rs2[i]=(source[i]>>16)&0x1f;
8400 rt1[i]=(source[i]>>16)&0x1f;
8401 rt2[i]=0;
8402 imm[i]=(short)source[i];
8403 if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8404 if(op==0x26) dep1[i]=rt1[i]; // LWR
8405 break;
8406 case IMM16:
8407 if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8408 else rs1[i]=(source[i]>>21)&0x1f;
8409 rs2[i]=0;
8410 rt1[i]=(source[i]>>16)&0x1f;
8411 rt2[i]=0;
8412 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8413 imm[i]=(unsigned short)source[i];
8414 }else{
8415 imm[i]=(short)source[i];
8416 }
8417 if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8418 if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8419 if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8420 break;
8421 case UJUMP:
8422 rs1[i]=0;
8423 rs2[i]=0;
8424 rt1[i]=0;
8425 rt2[i]=0;
8426 // The JAL instruction writes to r31.
8427 if (op&1) {
8428 rt1[i]=31;
8429 }
8430 rs2[i]=CCREG;
8431 break;
8432 case RJUMP:
8433 rs1[i]=(source[i]>>21)&0x1f;
8434 rs2[i]=0;
8435 rt1[i]=0;
8436 rt2[i]=0;
5067f341 8437 // The JALR instruction writes to rd.
57871462 8438 if (op2&1) {
5067f341 8439 rt1[i]=(source[i]>>11)&0x1f;
57871462 8440 }
8441 rs2[i]=CCREG;
8442 break;
8443 case CJUMP:
8444 rs1[i]=(source[i]>>21)&0x1f;
8445 rs2[i]=(source[i]>>16)&0x1f;
8446 rt1[i]=0;
8447 rt2[i]=0;
8448 if(op&2) { // BGTZ/BLEZ
8449 rs2[i]=0;
8450 }
8451 us1[i]=rs1[i];
8452 us2[i]=rs2[i];
8453 likely[i]=op>>4;
8454 break;
8455 case SJUMP:
8456 rs1[i]=(source[i]>>21)&0x1f;
8457 rs2[i]=CCREG;
8458 rt1[i]=0;
8459 rt2[i]=0;
8460 us1[i]=rs1[i];
8461 if(op2&0x10) { // BxxAL
8462 rt1[i]=31;
8463 // NOTE: If the branch is not taken, r31 is still overwritten
8464 }
8465 likely[i]=(op2&2)>>1;
8466 break;
8467 case FJUMP:
8468 rs1[i]=FSREG;
8469 rs2[i]=CSREG;
8470 rt1[i]=0;
8471 rt2[i]=0;
8472 likely[i]=((source[i])>>17)&1;
8473 break;
8474 case ALU:
8475 rs1[i]=(source[i]>>21)&0x1f; // source
8476 rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8477 rt1[i]=(source[i]>>11)&0x1f; // destination
8478 rt2[i]=0;
8479 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8480 us1[i]=rs1[i];us2[i]=rs2[i];
8481 }
8482 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8483 dep1[i]=rs1[i];dep2[i]=rs2[i];
8484 }
8485 else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8486 dep1[i]=rs1[i];dep2[i]=rs2[i];
8487 }
8488 break;
8489 case MULTDIV:
8490 rs1[i]=(source[i]>>21)&0x1f; // source
8491 rs2[i]=(source[i]>>16)&0x1f; // divisor
8492 rt1[i]=HIREG;
8493 rt2[i]=LOREG;
8494 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8495 us1[i]=rs1[i];us2[i]=rs2[i];
8496 }
8497 break;
8498 case MOV:
8499 rs1[i]=0;
8500 rs2[i]=0;
8501 rt1[i]=0;
8502 rt2[i]=0;
8503 if(op2==0x10) rs1[i]=HIREG; // MFHI
8504 if(op2==0x11) rt1[i]=HIREG; // MTHI
8505 if(op2==0x12) rs1[i]=LOREG; // MFLO
8506 if(op2==0x13) rt1[i]=LOREG; // MTLO
8507 if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8508 if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8509 dep1[i]=rs1[i];
8510 break;
8511 case SHIFT:
8512 rs1[i]=(source[i]>>16)&0x1f; // target of shift
8513 rs2[i]=(source[i]>>21)&0x1f; // shift amount
8514 rt1[i]=(source[i]>>11)&0x1f; // destination
8515 rt2[i]=0;
8516 // DSLLV/DSRLV/DSRAV are 64-bit
8517 if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8518 break;
8519 case SHIFTIMM:
8520 rs1[i]=(source[i]>>16)&0x1f;
8521 rs2[i]=0;
8522 rt1[i]=(source[i]>>11)&0x1f;
8523 rt2[i]=0;
8524 imm[i]=(source[i]>>6)&0x1f;
8525 // DSxx32 instructions
8526 if(op2>=0x3c) imm[i]|=0x20;
8527 // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8528 if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8529 break;
8530 case COP0:
8531 rs1[i]=0;
8532 rs2[i]=0;
8533 rt1[i]=0;
8534 rt2[i]=0;
8535 if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8536 if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8537 if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8538 if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8539 break;
8540 case COP1:
b9b61529 8541 case COP2:
57871462 8542 rs1[i]=0;
8543 rs2[i]=0;
8544 rt1[i]=0;
8545 rt2[i]=0;
8546 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8547 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8548 if(op2==5) us1[i]=rs1[i]; // DMTC1
8549 rs2[i]=CSREG;
8550 break;
8551 case C1LS:
8552 rs1[i]=(source[i]>>21)&0x1F;
8553 rs2[i]=CSREG;
8554 rt1[i]=0;
8555 rt2[i]=0;
8556 imm[i]=(short)source[i];
8557 break;
b9b61529 8558 case C2LS:
8559 rs1[i]=(source[i]>>21)&0x1F;
8560 rs2[i]=0;
8561 rt1[i]=0;
8562 rt2[i]=0;
8563 imm[i]=(short)source[i];
8564 break;
57871462 8565 case FLOAT:
8566 case FCONV:
8567 rs1[i]=0;
8568 rs2[i]=CSREG;
8569 rt1[i]=0;
8570 rt2[i]=0;
8571 break;
8572 case FCOMP:
8573 rs1[i]=FSREG;
8574 rs2[i]=CSREG;
8575 rt1[i]=FSREG;
8576 rt2[i]=0;
8577 break;
8578 case SYSCALL:
7139f3c8 8579 case HLECALL:
1e973cb0 8580 case INTCALL:
57871462 8581 rs1[i]=CCREG;
8582 rs2[i]=0;
8583 rt1[i]=0;
8584 rt2[i]=0;
8585 break;
8586 default:
8587 rs1[i]=0;
8588 rs2[i]=0;
8589 rt1[i]=0;
8590 rt2[i]=0;
8591 }
8592 /* Calculate branch target addresses */
8593 if(type==UJUMP)
8594 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8595 else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8596 ba[i]=start+i*4+8; // Ignore never taken branch
8597 else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8598 ba[i]=start+i*4+8; // Ignore never taken branch
8599 else if(type==CJUMP||type==SJUMP||type==FJUMP)
8600 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8601 else ba[i]=-1;
26869094 8602#ifdef PCSX
3e535354 8603 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
8604 int do_in_intrp=0;
8605 // branch in delay slot?
8606 if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
8607 // don't handle first branch and call interpreter if it's hit
8608 printf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
8609 do_in_intrp=1;
8610 }
8611 // basic load delay detection
8612 else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&rt1[i]!=0) {
8613 int t=(ba[i-1]-start)/4;
8614 if(0 <= t && t < i &&(rt1[i]==rs1[t]||rt1[i]==rs2[t])&&itype[t]!=CJUMP&&itype[t]!=SJUMP) {
8615 // jump target wants DS result - potential load delay effect
8616 printf("load delay @%08x (%08x)\n", addr + i*4, addr);
8617 do_in_intrp=1;
8618 bt[t+1]=1; // expected return from interpreter
8619 }
8620 else if(i>=2&&rt1[i-2]==2&&rt1[i]==2&&rs1[i]!=2&&rs2[i]!=2&&rs1[i-1]!=2&&rs2[i-1]!=2&&
8621 !(i>=3&&(itype[i-3]==RJUMP||itype[i-3]==UJUMP||itype[i-3]==CJUMP||itype[i-3]==SJUMP))) {
8622 // v0 overwrite like this is a sign of trouble, bail out
8623 printf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
8624 do_in_intrp=1;
8625 }
8626 }
3e535354 8627 if(do_in_intrp) {
8628 rs1[i-1]=CCREG;
8629 rs2[i-1]=rt1[i-1]=rt2[i-1]=0;
26869094 8630 ba[i-1]=-1;
8631 itype[i-1]=INTCALL;
8632 done=2;
3e535354 8633 i--; // don't compile the DS
26869094 8634 }
3e535354 8635 }
26869094 8636#endif
3e535354 8637 /* Is this the end of the block? */
8638 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
5067f341 8639 if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
1e973cb0 8640 done=2;
57871462 8641 }
8642 else {
8643 if(stop_after_jal) done=1;
8644 // Stop on BREAK
8645 if((source[i+1]&0xfc00003f)==0x0d) done=1;
8646 }
8647 // Don't recompile stuff that's already compiled
8648 if(check_addr(start+i*4+4)) done=1;
8649 // Don't get too close to the limit
8650 if(i>MAXBLOCK/2) done=1;
8651 }
75dec299 8652 if(itype[i]==SYSCALL&&stop_after_jal) done=1;
1e973cb0 8653 if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
8654 if(done==2) {
8655 // Does the block continue due to a branch?
8656 for(j=i-1;j>=0;j--)
8657 {
2a706964 8658 if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
1e973cb0 8659 if(ba[j]==start+i*4+4) done=j=0;
8660 if(ba[j]==start+i*4+8) done=j=0;
8661 }
8662 }
75dec299 8663 //assert(i<MAXBLOCK-1);
57871462 8664 if(start+i*4==pagelimit-4) done=1;
8665 assert(start+i*4<pagelimit);
8666 if (i==MAXBLOCK-1) done=1;
8667 // Stop if we're compiling junk
8668 if(itype[i]==NI&&opcode[i]==0x11) {
8669 done=stop_after_jal=1;
8670 printf("Disabled speculative precompilation\n");
8671 }
8672 }
8673 slen=i;
8674 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8675 if(start+i*4==pagelimit) {
8676 itype[i-1]=SPAN;
8677 }
8678 }
8679 assert(slen>0);
8680
8681 /* Pass 2 - Register dependencies and branch targets */
8682
8683 unneeded_registers(0,slen-1,0);
8684
8685 /* Pass 3 - Register allocation */
8686
8687 struct regstat current; // Current register allocations/status
8688 current.is32=1;
8689 current.dirty=0;
8690 current.u=unneeded_reg[0];
8691 current.uu=unneeded_reg_upper[0];
8692 clear_all_regs(current.regmap);
8693 alloc_reg(&current,0,CCREG);
8694 dirty_reg(&current,CCREG);
8695 current.isconst=0;
8696 current.wasconst=0;
8697 int ds=0;
8698 int cc=0;
5194fb95 8699 int hr=-1;
6ebf4adf 8700
8701#ifndef FORCE32
57871462 8702 provisional_32bit();
6ebf4adf 8703#endif
57871462 8704 if((u_int)addr&1) {
8705 // First instruction is delay slot
8706 cc=-1;
8707 bt[1]=1;
8708 ds=1;
8709 unneeded_reg[0]=1;
8710 unneeded_reg_upper[0]=1;
8711 current.regmap[HOST_BTREG]=BTREG;
8712 }
8713
8714 for(i=0;i<slen;i++)
8715 {
8716 if(bt[i])
8717 {
8718 int hr;
8719 for(hr=0;hr<HOST_REGS;hr++)
8720 {
8721 // Is this really necessary?
8722 if(current.regmap[hr]==0) current.regmap[hr]=-1;
8723 }
8724 current.isconst=0;
8725 }
8726 if(i>1)
8727 {
8728 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8729 {
8730 if(rs1[i-2]==0||rs2[i-2]==0)
8731 {
8732 if(rs1[i-2]) {
8733 current.is32|=1LL<<rs1[i-2];
8734 int hr=get_reg(current.regmap,rs1[i-2]|64);
8735 if(hr>=0) current.regmap[hr]=-1;
8736 }
8737 if(rs2[i-2]) {
8738 current.is32|=1LL<<rs2[i-2];
8739 int hr=get_reg(current.regmap,rs2[i-2]|64);
8740 if(hr>=0) current.regmap[hr]=-1;
8741 }
8742 }
8743 }
8744 }
6ebf4adf 8745#ifndef FORCE32
57871462 8746 // If something jumps here with 64-bit values
8747 // then promote those registers to 64 bits
8748 if(bt[i])
8749 {
8750 uint64_t temp_is32=current.is32;
8751 for(j=i-1;j>=0;j--)
8752 {
8753 if(ba[j]==start+i*4)
8754 temp_is32&=branch_regs[j].is32;
8755 }
8756 for(j=i;j<slen;j++)
8757 {
8758 if(ba[j]==start+i*4)
8759 //temp_is32=1;
8760 temp_is32&=p32[j];
8761 }
8762 if(temp_is32!=current.is32) {
8763 //printf("dumping 32-bit regs (%x)\n",start+i*4);
311301dc 8764 #ifndef DESTRUCTIVE_WRITEBACK
8765 if(ds)
8766 #endif
57871462 8767 for(hr=0;hr<HOST_REGS;hr++)
8768 {
8769 int r=current.regmap[hr];
8770 if(r>0&&r<64)
8771 {
8772 if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8773 temp_is32|=1LL<<r;
8774 //printf("restore %d\n",r);
8775 }
8776 }
8777 }
57871462 8778 current.is32=temp_is32;
8779 }
8780 }
6ebf4adf 8781#else
24385cae 8782 current.is32=-1LL;
8783#endif
8784
57871462 8785 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8786 regs[i].wasconst=current.isconst;
8787 regs[i].was32=current.is32;
8788 regs[i].wasdirty=current.dirty;
6ebf4adf 8789 #if defined(DESTRUCTIVE_WRITEBACK) && !defined(FORCE32)
57871462 8790 // To change a dirty register from 32 to 64 bits, we must write
8791 // it out during the previous cycle (for branches, 2 cycles)
8792 if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8793 {
8794 uint64_t temp_is32=current.is32;
8795 for(j=i-1;j>=0;j--)
8796 {
8797 if(ba[j]==start+i*4+4)
8798 temp_is32&=branch_regs[j].is32;
8799 }
8800 for(j=i;j<slen;j++)
8801 {
8802 if(ba[j]==start+i*4+4)
8803 //temp_is32=1;
8804 temp_is32&=p32[j];
8805 }
8806 if(temp_is32!=current.is32) {
8807 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8808 for(hr=0;hr<HOST_REGS;hr++)
8809 {
8810 int r=current.regmap[hr];
8811 if(r>0)
8812 {
8813 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8814 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
8815 {
8816 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
8817 {
8818 //printf("dump %d/r%d\n",hr,r);
8819 current.regmap[hr]=-1;
8820 if(get_reg(current.regmap,r|64)>=0)
8821 current.regmap[get_reg(current.regmap,r|64)]=-1;
8822 }
8823 }
8824 }
8825 }
8826 }
8827 }
8828 }
8829 else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
8830 {
8831 uint64_t temp_is32=current.is32;
8832 for(j=i-1;j>=0;j--)
8833 {
8834 if(ba[j]==start+i*4+8)
8835 temp_is32&=branch_regs[j].is32;
8836 }
8837 for(j=i;j<slen;j++)
8838 {
8839 if(ba[j]==start+i*4+8)
8840 //temp_is32=1;
8841 temp_is32&=p32[j];
8842 }
8843 if(temp_is32!=current.is32) {
8844 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8845 for(hr=0;hr<HOST_REGS;hr++)
8846 {
8847 int r=current.regmap[hr];
8848 if(r>0)
8849 {
8850 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8851 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
8852 {
8853 //printf("dump %d/r%d\n",hr,r);
8854 current.regmap[hr]=-1;
8855 if(get_reg(current.regmap,r|64)>=0)
8856 current.regmap[get_reg(current.regmap,r|64)]=-1;
8857 }
8858 }
8859 }
8860 }
8861 }
8862 }
8863 #endif
8864 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8865 if(i+1<slen) {
8866 current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8867 current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8868 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8869 current.u|=1;
8870 current.uu|=1;
8871 } else {
8872 current.u=1;
8873 current.uu=1;
8874 }
8875 } else {
8876 if(i+1<slen) {
8877 current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
8878 current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8879 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8880 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8881 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8882 current.u|=1;
8883 current.uu|=1;
8884 } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
8885 }
8886 is_ds[i]=ds;
8887 if(ds) {
8888 ds=0; // Skip delay slot, already allocated as part of branch
8889 // ...but we need to alloc it in case something jumps here
8890 if(i+1<slen) {
8891 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
8892 current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
8893 }else{
8894 current.u=branch_unneeded_reg[i-1];
8895 current.uu=branch_unneeded_reg_upper[i-1];
8896 }
8897 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8898 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8899 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8900 current.u|=1;
8901 current.uu|=1;
8902 struct regstat temp;
8903 memcpy(&temp,&current,sizeof(current));
8904 temp.wasdirty=temp.dirty;
8905 temp.was32=temp.is32;
8906 // TODO: Take into account unconditional branches, as below
8907 delayslot_alloc(&temp,i);
8908 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
8909 regs[i].wasdirty=temp.wasdirty;
8910 regs[i].was32=temp.was32;
8911 regs[i].dirty=temp.dirty;
8912 regs[i].is32=temp.is32;
8913 regs[i].isconst=0;
8914 regs[i].wasconst=0;
8915 current.isconst=0;
8916 // Create entry (branch target) regmap
8917 for(hr=0;hr<HOST_REGS;hr++)
8918 {
8919 int r=temp.regmap[hr];
8920 if(r>=0) {
8921 if(r!=regmap_pre[i][hr]) {
8922 regs[i].regmap_entry[hr]=-1;
8923 }
8924 else
8925 {
8926 if(r<64){
8927 if((current.u>>r)&1) {
8928 regs[i].regmap_entry[hr]=-1;
8929 regs[i].regmap[hr]=-1;
8930 //Don't clear regs in the delay slot as the branch might need them
8931 //current.regmap[hr]=-1;
8932 }else
8933 regs[i].regmap_entry[hr]=r;
8934 }
8935 else {
8936 if((current.uu>>(r&63))&1) {
8937 regs[i].regmap_entry[hr]=-1;
8938 regs[i].regmap[hr]=-1;
8939 //Don't clear regs in the delay slot as the branch might need them
8940 //current.regmap[hr]=-1;
8941 }else
8942 regs[i].regmap_entry[hr]=r;
8943 }
8944 }
8945 } else {
8946 // First instruction expects CCREG to be allocated
8947 if(i==0&&hr==HOST_CCREG)
8948 regs[i].regmap_entry[hr]=CCREG;
8949 else
8950 regs[i].regmap_entry[hr]=-1;
8951 }
8952 }
8953 }
8954 else { // Not delay slot
8955 switch(itype[i]) {
8956 case UJUMP:
8957 //current.isconst=0; // DEBUG
8958 //current.wasconst=0; // DEBUG
8959 //regs[i].wasconst=0; // DEBUG
8960 clear_const(&current,rt1[i]);
8961 alloc_cc(&current,i);
8962 dirty_reg(&current,CCREG);
8963 if (rt1[i]==31) {
8964 alloc_reg(&current,i,31);
8965 dirty_reg(&current,31);
4ef8f67d 8966 //assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8967 //assert(rt1[i+1]!=rt1[i]);
57871462 8968 #ifdef REG_PREFETCH
8969 alloc_reg(&current,i,PTEMP);
8970 #endif
8971 //current.is32|=1LL<<rt1[i];
8972 }
269bb29a 8973 ooo[i]=1;
8974 delayslot_alloc(&current,i+1);
57871462 8975 //current.isconst=0; // DEBUG
8976 ds=1;
8977 //printf("i=%d, isconst=%x\n",i,current.isconst);
8978 break;
8979 case RJUMP:
8980 //current.isconst=0;
8981 //current.wasconst=0;
8982 //regs[i].wasconst=0;
8983 clear_const(&current,rs1[i]);
8984 clear_const(&current,rt1[i]);
8985 alloc_cc(&current,i);
8986 dirty_reg(&current,CCREG);
8987 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
8988 alloc_reg(&current,i,rs1[i]);
5067f341 8989 if (rt1[i]!=0) {
8990 alloc_reg(&current,i,rt1[i]);
8991 dirty_reg(&current,rt1[i]);
68b3faee 8992 assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
076655d1 8993 assert(rt1[i+1]!=rt1[i]);
57871462 8994 #ifdef REG_PREFETCH
8995 alloc_reg(&current,i,PTEMP);
8996 #endif
8997 }
8998 #ifdef USE_MINI_HT
8999 if(rs1[i]==31) { // JALR
9000 alloc_reg(&current,i,RHASH);
9001 #ifndef HOST_IMM_ADDR32
9002 alloc_reg(&current,i,RHTBL);
9003 #endif
9004 }
9005 #endif
9006 delayslot_alloc(&current,i+1);
9007 } else {
9008 // The delay slot overwrites our source register,
9009 // allocate a temporary register to hold the old value.
9010 current.isconst=0;
9011 current.wasconst=0;
9012 regs[i].wasconst=0;
9013 delayslot_alloc(&current,i+1);
9014 current.isconst=0;
9015 alloc_reg(&current,i,RTEMP);
9016 }
9017 //current.isconst=0; // DEBUG
e1190b87 9018 ooo[i]=1;
57871462 9019 ds=1;
9020 break;
9021 case CJUMP:
9022 //current.isconst=0;
9023 //current.wasconst=0;
9024 //regs[i].wasconst=0;
9025 clear_const(&current,rs1[i]);
9026 clear_const(&current,rs2[i]);
9027 if((opcode[i]&0x3E)==4) // BEQ/BNE
9028 {
9029 alloc_cc(&current,i);
9030 dirty_reg(&current,CCREG);
9031 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9032 if(rs2[i]) alloc_reg(&current,i,rs2[i]);
9033 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9034 {
9035 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9036 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
9037 }
9038 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
9039 (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
9040 // The delay slot overwrites one of our conditions.
9041 // Allocate the branch condition registers instead.
57871462 9042 current.isconst=0;
9043 current.wasconst=0;
9044 regs[i].wasconst=0;
9045 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9046 if(rs2[i]) alloc_reg(&current,i,rs2[i]);
9047 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9048 {
9049 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9050 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
9051 }
9052 }
e1190b87 9053 else
9054 {
9055 ooo[i]=1;
9056 delayslot_alloc(&current,i+1);
9057 }
57871462 9058 }
9059 else
9060 if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
9061 {
9062 alloc_cc(&current,i);
9063 dirty_reg(&current,CCREG);
9064 alloc_reg(&current,i,rs1[i]);
9065 if(!(current.is32>>rs1[i]&1))
9066 {
9067 alloc_reg64(&current,i,rs1[i]);
9068 }
9069 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
9070 // The delay slot overwrites one of our conditions.
9071 // Allocate the branch condition registers instead.
57871462 9072 current.isconst=0;
9073 current.wasconst=0;
9074 regs[i].wasconst=0;
9075 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9076 if(!((current.is32>>rs1[i])&1))
9077 {
9078 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9079 }
9080 }
e1190b87 9081 else
9082 {
9083 ooo[i]=1;
9084 delayslot_alloc(&current,i+1);
9085 }
57871462 9086 }
9087 else
9088 // Don't alloc the delay slot yet because we might not execute it
9089 if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
9090 {
9091 current.isconst=0;
9092 current.wasconst=0;
9093 regs[i].wasconst=0;
9094 alloc_cc(&current,i);
9095 dirty_reg(&current,CCREG);
9096 alloc_reg(&current,i,rs1[i]);
9097 alloc_reg(&current,i,rs2[i]);
9098 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9099 {
9100 alloc_reg64(&current,i,rs1[i]);
9101 alloc_reg64(&current,i,rs2[i]);
9102 }
9103 }
9104 else
9105 if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
9106 {
9107 current.isconst=0;
9108 current.wasconst=0;
9109 regs[i].wasconst=0;
9110 alloc_cc(&current,i);
9111 dirty_reg(&current,CCREG);
9112 alloc_reg(&current,i,rs1[i]);
9113 if(!(current.is32>>rs1[i]&1))
9114 {
9115 alloc_reg64(&current,i,rs1[i]);
9116 }
9117 }
9118 ds=1;
9119 //current.isconst=0;
9120 break;
9121 case SJUMP:
9122 //current.isconst=0;
9123 //current.wasconst=0;
9124 //regs[i].wasconst=0;
9125 clear_const(&current,rs1[i]);
9126 clear_const(&current,rt1[i]);
9127 //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
9128 if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
9129 {
9130 alloc_cc(&current,i);
9131 dirty_reg(&current,CCREG);
9132 alloc_reg(&current,i,rs1[i]);
9133 if(!(current.is32>>rs1[i]&1))
9134 {
9135 alloc_reg64(&current,i,rs1[i]);
9136 }
9137 if (rt1[i]==31) { // BLTZAL/BGEZAL
9138 alloc_reg(&current,i,31);
9139 dirty_reg(&current,31);
57871462 9140 //#ifdef REG_PREFETCH
9141 //alloc_reg(&current,i,PTEMP);
9142 //#endif
9143 //current.is32|=1LL<<rt1[i];
9144 }
e1190b87 9145 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) // The delay slot overwrites the branch condition.
9146 ||(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))) { // DS touches $ra
57871462 9147 // Allocate the branch condition registers instead.
57871462 9148 current.isconst=0;
9149 current.wasconst=0;
9150 regs[i].wasconst=0;
9151 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9152 if(!((current.is32>>rs1[i])&1))
9153 {
9154 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9155 }
9156 }
e1190b87 9157 else
9158 {
9159 ooo[i]=1;
9160 delayslot_alloc(&current,i+1);
9161 }
57871462 9162 }
9163 else
9164 // Don't alloc the delay slot yet because we might not execute it
9165 if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
9166 {
9167 current.isconst=0;
9168 current.wasconst=0;
9169 regs[i].wasconst=0;
9170 alloc_cc(&current,i);
9171 dirty_reg(&current,CCREG);
9172 alloc_reg(&current,i,rs1[i]);
9173 if(!(current.is32>>rs1[i]&1))
9174 {
9175 alloc_reg64(&current,i,rs1[i]);
9176 }
9177 }
9178 ds=1;
9179 //current.isconst=0;
9180 break;
9181 case FJUMP:
9182 current.isconst=0;
9183 current.wasconst=0;
9184 regs[i].wasconst=0;
9185 if(likely[i]==0) // BC1F/BC1T
9186 {
9187 // TODO: Theoretically we can run out of registers here on x86.
9188 // The delay slot can allocate up to six, and we need to check
9189 // CSREG before executing the delay slot. Possibly we can drop
9190 // the cycle count and then reload it after checking that the
9191 // FPU is in a usable state, or don't do out-of-order execution.
9192 alloc_cc(&current,i);
9193 dirty_reg(&current,CCREG);
9194 alloc_reg(&current,i,FSREG);
9195 alloc_reg(&current,i,CSREG);
9196 if(itype[i+1]==FCOMP) {
9197 // The delay slot overwrites the branch condition.
9198 // Allocate the branch condition registers instead.
57871462 9199 alloc_cc(&current,i);
9200 dirty_reg(&current,CCREG);
9201 alloc_reg(&current,i,CSREG);
9202 alloc_reg(&current,i,FSREG);
9203 }
9204 else {
e1190b87 9205 ooo[i]=1;
57871462 9206 delayslot_alloc(&current,i+1);
9207 alloc_reg(&current,i+1,CSREG);
9208 }
9209 }
9210 else
9211 // Don't alloc the delay slot yet because we might not execute it
9212 if(likely[i]) // BC1FL/BC1TL
9213 {
9214 alloc_cc(&current,i);
9215 dirty_reg(&current,CCREG);
9216 alloc_reg(&current,i,CSREG);
9217 alloc_reg(&current,i,FSREG);
9218 }
9219 ds=1;
9220 current.isconst=0;
9221 break;
9222 case IMM16:
9223 imm16_alloc(&current,i);
9224 break;
9225 case LOAD:
9226 case LOADLR:
9227 load_alloc(&current,i);
9228 break;
9229 case STORE:
9230 case STORELR:
9231 store_alloc(&current,i);
9232 break;
9233 case ALU:
9234 alu_alloc(&current,i);
9235 break;
9236 case SHIFT:
9237 shift_alloc(&current,i);
9238 break;
9239 case MULTDIV:
9240 multdiv_alloc(&current,i);
9241 break;
9242 case SHIFTIMM:
9243 shiftimm_alloc(&current,i);
9244 break;
9245 case MOV:
9246 mov_alloc(&current,i);
9247 break;
9248 case COP0:
9249 cop0_alloc(&current,i);
9250 break;
9251 case COP1:
b9b61529 9252 case COP2:
57871462 9253 cop1_alloc(&current,i);
9254 break;
9255 case C1LS:
9256 c1ls_alloc(&current,i);
9257 break;
b9b61529 9258 case C2LS:
9259 c2ls_alloc(&current,i);
9260 break;
9261 case C2OP:
9262 c2op_alloc(&current,i);
9263 break;
57871462 9264 case FCONV:
9265 fconv_alloc(&current,i);
9266 break;
9267 case FLOAT:
9268 float_alloc(&current,i);
9269 break;
9270 case FCOMP:
9271 fcomp_alloc(&current,i);
9272 break;
9273 case SYSCALL:
7139f3c8 9274 case HLECALL:
1e973cb0 9275 case INTCALL:
57871462 9276 syscall_alloc(&current,i);
9277 break;
9278 case SPAN:
9279 pagespan_alloc(&current,i);
9280 break;
9281 }
9282
9283 // Drop the upper half of registers that have become 32-bit
9284 current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
9285 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9286 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9287 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9288 current.uu|=1;
9289 } else {
9290 current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
9291 current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9292 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9293 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9294 current.uu|=1;
9295 }
9296
9297 // Create entry (branch target) regmap
9298 for(hr=0;hr<HOST_REGS;hr++)
9299 {
9300 int r,or,er;
9301 r=current.regmap[hr];
9302 if(r>=0) {
9303 if(r!=regmap_pre[i][hr]) {
9304 // TODO: delay slot (?)
9305 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9306 if(or<0||(r&63)>=TEMPREG){
9307 regs[i].regmap_entry[hr]=-1;
9308 }
9309 else
9310 {
9311 // Just move it to a different register
9312 regs[i].regmap_entry[hr]=r;
9313 // If it was dirty before, it's still dirty
9314 if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r&63);
9315 }
9316 }
9317 else
9318 {
9319 // Unneeded
9320 if(r==0){
9321 regs[i].regmap_entry[hr]=0;
9322 }
9323 else
9324 if(r<64){
9325 if((current.u>>r)&1) {
9326 regs[i].regmap_entry[hr]=-1;
9327 //regs[i].regmap[hr]=-1;
9328 current.regmap[hr]=-1;
9329 }else
9330 regs[i].regmap_entry[hr]=r;
9331 }
9332 else {
9333 if((current.uu>>(r&63))&1) {
9334 regs[i].regmap_entry[hr]=-1;
9335 //regs[i].regmap[hr]=-1;
9336 current.regmap[hr]=-1;
9337 }else
9338 regs[i].regmap_entry[hr]=r;
9339 }
9340 }
9341 } else {
9342 // Branches expect CCREG to be allocated at the target
9343 if(regmap_pre[i][hr]==CCREG)
9344 regs[i].regmap_entry[hr]=CCREG;
9345 else
9346 regs[i].regmap_entry[hr]=-1;
9347 }
9348 }
9349 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9350 }
9351 /* Branch post-alloc */
9352 if(i>0)
9353 {
9354 current.was32=current.is32;
9355 current.wasdirty=current.dirty;
9356 switch(itype[i-1]) {
9357 case UJUMP:
9358 memcpy(&branch_regs[i-1],&current,sizeof(current));
9359 branch_regs[i-1].isconst=0;
9360 branch_regs[i-1].wasconst=0;
9361 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9362 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9363 alloc_cc(&branch_regs[i-1],i-1);
9364 dirty_reg(&branch_regs[i-1],CCREG);
9365 if(rt1[i-1]==31) { // JAL
9366 alloc_reg(&branch_regs[i-1],i-1,31);
9367 dirty_reg(&branch_regs[i-1],31);
9368 branch_regs[i-1].is32|=1LL<<31;
9369 }
9370 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9371 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9372 break;
9373 case RJUMP:
9374 memcpy(&branch_regs[i-1],&current,sizeof(current));
9375 branch_regs[i-1].isconst=0;
9376 branch_regs[i-1].wasconst=0;
9377 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9378 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9379 alloc_cc(&branch_regs[i-1],i-1);
9380 dirty_reg(&branch_regs[i-1],CCREG);
9381 alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
5067f341 9382 if(rt1[i-1]!=0) { // JALR
9383 alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9384 dirty_reg(&branch_regs[i-1],rt1[i-1]);
9385 branch_regs[i-1].is32|=1LL<<rt1[i-1];
57871462 9386 }
9387 #ifdef USE_MINI_HT
9388 if(rs1[i-1]==31) { // JALR
9389 alloc_reg(&branch_regs[i-1],i-1,RHASH);
9390 #ifndef HOST_IMM_ADDR32
9391 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9392 #endif
9393 }
9394 #endif
9395 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9396 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9397 break;
9398 case CJUMP:
9399 if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9400 {
9401 alloc_cc(&current,i-1);
9402 dirty_reg(&current,CCREG);
9403 if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9404 (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9405 // The delay slot overwrote one of our conditions
9406 // Delay slot goes after the test (in order)
9407 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9408 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9409 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9410 current.u|=1;
9411 current.uu|=1;
9412 delayslot_alloc(&current,i);
9413 current.isconst=0;
9414 }
9415 else
9416 {
9417 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9418 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9419 // Alloc the branch condition registers
9420 if(rs1[i-1]) alloc_reg(&current,i-1,rs1[i-1]);
9421 if(rs2[i-1]) alloc_reg(&current,i-1,rs2[i-1]);
9422 if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9423 {
9424 if(rs1[i-1]) alloc_reg64(&current,i-1,rs1[i-1]);
9425 if(rs2[i-1]) alloc_reg64(&current,i-1,rs2[i-1]);
9426 }
9427 }
9428 memcpy(&branch_regs[i-1],&current,sizeof(current));
9429 branch_regs[i-1].isconst=0;
9430 branch_regs[i-1].wasconst=0;
9431 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9432 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9433 }
9434 else
9435 if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9436 {
9437 alloc_cc(&current,i-1);
9438 dirty_reg(&current,CCREG);
9439 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9440 // The delay slot overwrote the branch condition
9441 // Delay slot goes after the test (in order)
9442 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9443 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9444 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9445 current.u|=1;
9446 current.uu|=1;
9447 delayslot_alloc(&current,i);
9448 current.isconst=0;
9449 }
9450 else
9451 {
9452 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9453 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9454 // Alloc the branch condition register
9455 alloc_reg(&current,i-1,rs1[i-1]);
9456 if(!(current.is32>>rs1[i-1]&1))
9457 {
9458 alloc_reg64(&current,i-1,rs1[i-1]);
9459 }
9460 }
9461 memcpy(&branch_regs[i-1],&current,sizeof(current));
9462 branch_regs[i-1].isconst=0;
9463 branch_regs[i-1].wasconst=0;
9464 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9465 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9466 }
9467 else
9468 // Alloc the delay slot in case the branch is taken
9469 if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9470 {
9471 memcpy(&branch_regs[i-1],&current,sizeof(current));
9472 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9473 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9474 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9475 alloc_cc(&branch_regs[i-1],i);
9476 dirty_reg(&branch_regs[i-1],CCREG);
9477 delayslot_alloc(&branch_regs[i-1],i);
9478 branch_regs[i-1].isconst=0;
9479 alloc_reg(&current,i,CCREG); // Not taken path
9480 dirty_reg(&current,CCREG);
9481 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9482 }
9483 else
9484 if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9485 {
9486 memcpy(&branch_regs[i-1],&current,sizeof(current));
9487 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9488 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9489 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9490 alloc_cc(&branch_regs[i-1],i);
9491 dirty_reg(&branch_regs[i-1],CCREG);
9492 delayslot_alloc(&branch_regs[i-1],i);
9493 branch_regs[i-1].isconst=0;
9494 alloc_reg(&current,i,CCREG); // Not taken path
9495 dirty_reg(&current,CCREG);
9496 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9497 }
9498 break;
9499 case SJUMP:
9500 //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9501 if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9502 {
9503 alloc_cc(&current,i-1);
9504 dirty_reg(&current,CCREG);
9505 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9506 // The delay slot overwrote the branch condition
9507 // Delay slot goes after the test (in order)
9508 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9509 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9510 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9511 current.u|=1;
9512 current.uu|=1;
9513 delayslot_alloc(&current,i);
9514 current.isconst=0;
9515 }
9516 else
9517 {
9518 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9519 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9520 // Alloc the branch condition register
9521 alloc_reg(&current,i-1,rs1[i-1]);
9522 if(!(current.is32>>rs1[i-1]&1))
9523 {
9524 alloc_reg64(&current,i-1,rs1[i-1]);
9525 }
9526 }
9527 memcpy(&branch_regs[i-1],&current,sizeof(current));
9528 branch_regs[i-1].isconst=0;
9529 branch_regs[i-1].wasconst=0;
9530 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9531 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9532 }
9533 else
9534 // Alloc the delay slot in case the branch is taken
9535 if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9536 {
9537 memcpy(&branch_regs[i-1],&current,sizeof(current));
9538 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9539 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9540 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9541 alloc_cc(&branch_regs[i-1],i);
9542 dirty_reg(&branch_regs[i-1],CCREG);
9543 delayslot_alloc(&branch_regs[i-1],i);
9544 branch_regs[i-1].isconst=0;
9545 alloc_reg(&current,i,CCREG); // Not taken path
9546 dirty_reg(&current,CCREG);
9547 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9548 }
9549 // FIXME: BLTZAL/BGEZAL
9550 if(opcode2[i-1]&0x10) { // BxxZAL
9551 alloc_reg(&branch_regs[i-1],i-1,31);
9552 dirty_reg(&branch_regs[i-1],31);
9553 branch_regs[i-1].is32|=1LL<<31;
9554 }
9555 break;
9556 case FJUMP:
9557 if(likely[i-1]==0) // BC1F/BC1T
9558 {
9559 alloc_cc(&current,i-1);
9560 dirty_reg(&current,CCREG);
9561 if(itype[i]==FCOMP) {
9562 // The delay slot overwrote the branch condition
9563 // Delay slot goes after the test (in order)
9564 delayslot_alloc(&current,i);
9565 current.isconst=0;
9566 }
9567 else
9568 {
9569 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9570 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9571 // Alloc the branch condition register
9572 alloc_reg(&current,i-1,FSREG);
9573 }
9574 memcpy(&branch_regs[i-1],&current,sizeof(current));
9575 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9576 }
9577 else // BC1FL/BC1TL
9578 {
9579 // Alloc the delay slot in case the branch is taken
9580 memcpy(&branch_regs[i-1],&current,sizeof(current));
9581 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9582 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9583 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9584 alloc_cc(&branch_regs[i-1],i);
9585 dirty_reg(&branch_regs[i-1],CCREG);
9586 delayslot_alloc(&branch_regs[i-1],i);
9587 branch_regs[i-1].isconst=0;
9588 alloc_reg(&current,i,CCREG); // Not taken path
9589 dirty_reg(&current,CCREG);
9590 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9591 }
9592 break;
9593 }
9594
9595 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9596 {
9597 if(rt1[i-1]==31) // JAL/JALR
9598 {
9599 // Subroutine call will return here, don't alloc any registers
9600 current.is32=1;
9601 current.dirty=0;
9602 clear_all_regs(current.regmap);
9603 alloc_reg(&current,i,CCREG);
9604 dirty_reg(&current,CCREG);
9605 }
9606 else if(i+1<slen)
9607 {
9608 // Internal branch will jump here, match registers to caller
9609 current.is32=0x3FFFFFFFFLL;
9610 current.dirty=0;
9611 clear_all_regs(current.regmap);
9612 alloc_reg(&current,i,CCREG);
9613 dirty_reg(&current,CCREG);
9614 for(j=i-1;j>=0;j--)
9615 {
9616 if(ba[j]==start+i*4+4) {
9617 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9618 current.is32=branch_regs[j].is32;
9619 current.dirty=branch_regs[j].dirty;
9620 break;
9621 }
9622 }
9623 while(j>=0) {
9624 if(ba[j]==start+i*4+4) {
9625 for(hr=0;hr<HOST_REGS;hr++) {
9626 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9627 current.regmap[hr]=-1;
9628 }
9629 current.is32&=branch_regs[j].is32;
9630 current.dirty&=branch_regs[j].dirty;
9631 }
9632 }
9633 j--;
9634 }
9635 }
9636 }
9637 }
9638
9639 // Count cycles in between branches
9640 ccadj[i]=cc;
7139f3c8 9641 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
57871462 9642 {
9643 cc=0;
9644 }
fb407447 9645#ifdef PCSX
9646 else if(/*itype[i]==LOAD||*/itype[i]==STORE||itype[i]==C1LS) // load causes weird timing issues
9647 {
9648 cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
9649 }
9650 else if(itype[i]==C2LS)
9651 {
9652 cc+=4;
9653 }
9654#endif
57871462 9655 else
9656 {
9657 cc++;
9658 }
9659
9660 flush_dirty_uppers(&current);
9661 if(!is_ds[i]) {
9662 regs[i].is32=current.is32;
9663 regs[i].dirty=current.dirty;
9664 regs[i].isconst=current.isconst;
9665 memcpy(constmap[i],current.constmap,sizeof(current.constmap));
9666 }
9667 for(hr=0;hr<HOST_REGS;hr++) {
9668 if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
9669 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9670 regs[i].wasconst&=~(1<<hr);
9671 }
9672 }
9673 }
9674 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9675 }
9676
9677 /* Pass 4 - Cull unused host registers */
9678
9679 uint64_t nr=0;
9680
9681 for (i=slen-1;i>=0;i--)
9682 {
9683 int hr;
9684 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9685 {
9686 if(ba[i]<start || ba[i]>=(start+slen*4))
9687 {
9688 // Branch out of this block, don't need anything
9689 nr=0;
9690 }
9691 else
9692 {
9693 // Internal branch
9694 // Need whatever matches the target
9695 nr=0;
9696 int t=(ba[i]-start)>>2;
9697 for(hr=0;hr<HOST_REGS;hr++)
9698 {
9699 if(regs[i].regmap_entry[hr]>=0) {
9700 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9701 }
9702 }
9703 }
9704 // Conditional branch may need registers for following instructions
9705 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9706 {
9707 if(i<slen-2) {
9708 nr|=needed_reg[i+2];
9709 for(hr=0;hr<HOST_REGS;hr++)
9710 {
9711 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9712 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9713 }
9714 }
9715 }
9716 // Don't need stuff which is overwritten
f5955059 9717 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9718 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
57871462 9719 // Merge in delay slot
9720 for(hr=0;hr<HOST_REGS;hr++)
9721 {
9722 if(!likely[i]) {
9723 // These are overwritten unless the branch is "likely"
9724 // and the delay slot is nullified if not taken
9725 if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9726 if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9727 }
9728 if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9729 if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9730 if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9731 if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9732 if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9733 if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9734 if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9735 if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9736 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9737 if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9738 if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9739 }
9740 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9741 if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9742 if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9743 }
b9b61529 9744 if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
57871462 9745 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9746 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9747 }
9748 }
9749 }
1e973cb0 9750 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 9751 {
9752 // SYSCALL instruction (software interrupt)
9753 nr=0;
9754 }
9755 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9756 {
9757 // ERET instruction (return from interrupt)
9758 nr=0;
9759 }
9760 else // Non-branch
9761 {
9762 if(i<slen-1) {
9763 for(hr=0;hr<HOST_REGS;hr++) {
9764 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9765 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9766 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9767 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9768 }
9769 }
9770 }
9771 for(hr=0;hr<HOST_REGS;hr++)
9772 {
9773 // Overwritten registers are not needed
9774 if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9775 if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9776 if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9777 // Source registers are needed
9778 if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9779 if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9780 if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9781 if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9782 if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9783 if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9784 if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9785 if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9786 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9787 if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9788 if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9789 }
9790 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
9791 if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9792 if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9793 }
b9b61529 9794 if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
57871462 9795 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9796 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9797 }
9798 // Don't store a register immediately after writing it,
9799 // may prevent dual-issue.
9800 // But do so if this is a branch target, otherwise we
9801 // might have to load the register before the branch.
9802 if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
9803 if((regmap_pre[i][hr]>0&&regmap_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
9804 (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
9805 if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9806 if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9807 }
9808 if((regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
9809 (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
9810 if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9811 if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9812 }
9813 }
9814 }
9815 // Cycle count is needed at branches. Assume it is needed at the target too.
9816 if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
9817 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9818 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9819 }
9820 // Save it
9821 needed_reg[i]=nr;
9822
9823 // Deallocate unneeded registers
9824 for(hr=0;hr<HOST_REGS;hr++)
9825 {
9826 if(!((nr>>hr)&1)) {
9827 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
9828 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9829 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9830 (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
9831 {
9832 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9833 {
9834 if(likely[i]) {
9835 regs[i].regmap[hr]=-1;
9836 regs[i].isconst&=~(1<<hr);
79c75f1b 9837 if(i<slen-2) {
9838 regmap_pre[i+2][hr]=-1;
9839 regs[i+2].wasconst&=~(1<<hr);
9840 }
57871462 9841 }
9842 }
9843 }
9844 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9845 {
9846 int d1=0,d2=0,map=0,temp=0;
9847 if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
9848 {
9849 d1=dep1[i+1];
9850 d2=dep2[i+1];
9851 }
9852 if(using_tlb) {
9853 if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
9854 itype[i+1]==STORE || itype[i+1]==STORELR ||
b9b61529 9855 itype[i+1]==C1LS || itype[i+1]==C2LS)
57871462 9856 map=TLREG;
9857 } else
b9b61529 9858 if(itype[i+1]==STORE || itype[i+1]==STORELR ||
9859 (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
57871462 9860 map=INVCP;
9861 }
9862 if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
b9b61529 9863 itype[i+1]==C1LS || itype[i+1]==C2LS)
57871462 9864 temp=FTEMP;
9865 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9866 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9867 (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
9868 (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
9869 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9870 regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
9871 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
9872 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
9873 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
9874 regs[i].regmap[hr]!=map )
9875 {
9876 regs[i].regmap[hr]=-1;
9877 regs[i].isconst&=~(1<<hr);
9878 if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
9879 (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
9880 (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
9881 (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
9882 (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
9883 branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
9884 (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
9885 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
9886 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
9887 branch_regs[i].regmap[hr]!=map)
9888 {
9889 branch_regs[i].regmap[hr]=-1;
9890 branch_regs[i].regmap_entry[hr]=-1;
9891 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9892 {
9893 if(!likely[i]&&i<slen-2) {
9894 regmap_pre[i+2][hr]=-1;
79c75f1b 9895 regs[i+2].wasconst&=~(1<<hr);
57871462 9896 }
9897 }
9898 }
9899 }
9900 }
9901 else
9902 {
9903 // Non-branch
9904 if(i>0)
9905 {
9906 int d1=0,d2=0,map=-1,temp=-1;
9907 if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
9908 {
9909 d1=dep1[i];
9910 d2=dep2[i];
9911 }
9912 if(using_tlb) {
9913 if(itype[i]==LOAD || itype[i]==LOADLR ||
9914 itype[i]==STORE || itype[i]==STORELR ||
b9b61529 9915 itype[i]==C1LS || itype[i]==C2LS)
57871462 9916 map=TLREG;
b9b61529 9917 } else if(itype[i]==STORE || itype[i]==STORELR ||
9918 (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
57871462 9919 map=INVCP;
9920 }
9921 if(itype[i]==LOADLR || itype[i]==STORELR ||
b9b61529 9922 itype[i]==C1LS || itype[i]==C2LS)
57871462 9923 temp=FTEMP;
9924 if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9925 (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
9926 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9927 regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
9928 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
9929 (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
9930 {
9931 if(i<slen-1&&!is_ds[i]) {
9932 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
9933 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
9934 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
9935 {
9936 printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
9937 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
9938 }
9939 regmap_pre[i+1][hr]=-1;
9940 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
79c75f1b 9941 regs[i+1].wasconst&=~(1<<hr);
57871462 9942 }
9943 regs[i].regmap[hr]=-1;
9944 regs[i].isconst&=~(1<<hr);
9945 }
9946 }
9947 }
9948 }
9949 }
9950 }
9951
9952 /* Pass 5 - Pre-allocate registers */
9953
9954 // If a register is allocated during a loop, try to allocate it for the
9955 // entire loop, if possible. This avoids loading/storing registers
9956 // inside of the loop.
198df76f 9957
57871462 9958 signed char f_regmap[HOST_REGS];
9959 clear_all_regs(f_regmap);
9960 for(i=0;i<slen-1;i++)
9961 {
9962 if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9963 {
9964 if(ba[i]>=start && ba[i]<(start+i*4))
9965 if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
9966 ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
9967 ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
9968 ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
b9b61529 9969 ||itype[i+1]==FCOMP||itype[i+1]==FCONV
9970 ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
57871462 9971 {
9972 int t=(ba[i]-start)>>2;
9973 if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
198df76f 9974 if(t<2||(itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||rt1[t-2]!=31) // call/ret assumes no registers allocated
57871462 9975 for(hr=0;hr<HOST_REGS;hr++)
9976 {
9977 if(regs[i].regmap[hr]>64) {
9978 if(!((regs[i].dirty>>hr)&1))
9979 f_regmap[hr]=regs[i].regmap[hr];
9980 else f_regmap[hr]=-1;
9981 }
b372a952 9982 else if(regs[i].regmap[hr]>=0) {
9983 if(f_regmap[hr]!=regs[i].regmap[hr]) {
9984 // dealloc old register
9985 int n;
9986 for(n=0;n<HOST_REGS;n++)
9987 {
9988 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
9989 }
9990 // and alloc new one
9991 f_regmap[hr]=regs[i].regmap[hr];
9992 }
9993 }
57871462 9994 if(branch_regs[i].regmap[hr]>64) {
9995 if(!((branch_regs[i].dirty>>hr)&1))
9996 f_regmap[hr]=branch_regs[i].regmap[hr];
9997 else f_regmap[hr]=-1;
9998 }
b372a952 9999 else if(branch_regs[i].regmap[hr]>=0) {
10000 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
10001 // dealloc old register
10002 int n;
10003 for(n=0;n<HOST_REGS;n++)
10004 {
10005 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
10006 }
10007 // and alloc new one
10008 f_regmap[hr]=branch_regs[i].regmap[hr];
10009 }
10010 }
e1190b87 10011 if(ooo[i]) {
10012 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
10013 f_regmap[hr]=branch_regs[i].regmap[hr];
10014 }else{
10015 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
57871462 10016 f_regmap[hr]=branch_regs[i].regmap[hr];
10017 }
10018 // Avoid dirty->clean transition
e1190b87 10019 #ifdef DESTRUCTIVE_WRITEBACK
57871462 10020 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
e1190b87 10021 #endif
10022 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
10023 // case above, however it's always a good idea. We can't hoist the
10024 // load if the register was already allocated, so there's no point
10025 // wasting time analyzing most of these cases. It only "succeeds"
10026 // when the mapping was different and the load can be replaced with
10027 // a mov, which is of negligible benefit. So such cases are
10028 // skipped below.
57871462 10029 if(f_regmap[hr]>0) {
198df76f 10030 if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
57871462 10031 int r=f_regmap[hr];
10032 for(j=t;j<=i;j++)
10033 {
10034 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10035 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
10036 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
10037 if(r>63) {
10038 // NB This can exclude the case where the upper-half
10039 // register is lower numbered than the lower-half
10040 // register. Not sure if it's worth fixing...
10041 if(get_reg(regs[j].regmap,r&63)<0) break;
e1190b87 10042 if(get_reg(regs[j].regmap_entry,r&63)<0) break;
57871462 10043 if(regs[j].is32&(1LL<<(r&63))) break;
10044 }
10045 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
10046 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10047 int k;
10048 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
10049 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
10050 if(r>63) {
10051 if(get_reg(regs[i].regmap,r&63)<0) break;
10052 if(get_reg(branch_regs[i].regmap,r&63)<0) break;
10053 }
10054 k=i;
10055 while(k>1&&regs[k-1].regmap[hr]==-1) {
e1190b87 10056 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10057 //printf("no free regs for store %x\n",start+(k-1)*4);
10058 break;
57871462 10059 }
57871462 10060 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
10061 //printf("no-match due to different register\n");
10062 break;
10063 }
10064 if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
10065 //printf("no-match due to branch\n");
10066 break;
10067 }
10068 // call/ret fast path assumes no registers allocated
198df76f 10069 if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)&&rt1[k-3]==31) {
57871462 10070 break;
10071 }
10072 if(r>63) {
10073 // NB This can exclude the case where the upper-half
10074 // register is lower numbered than the lower-half
10075 // register. Not sure if it's worth fixing...
10076 if(get_reg(regs[k-1].regmap,r&63)<0) break;
10077 if(regs[k-1].is32&(1LL<<(r&63))) break;
10078 }
10079 k--;
10080 }
10081 if(i<slen-1) {
10082 if((regs[k].is32&(1LL<<f_regmap[hr]))!=
10083 (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
10084 //printf("bad match after branch\n");
10085 break;
10086 }
10087 }
10088 if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
10089 //printf("Extend r%d, %x ->\n",hr,start+k*4);
10090 while(k<i) {
10091 regs[k].regmap_entry[hr]=f_regmap[hr];
10092 regs[k].regmap[hr]=f_regmap[hr];
10093 regmap_pre[k+1][hr]=f_regmap[hr];
10094 regs[k].wasdirty&=~(1<<hr);
10095 regs[k].dirty&=~(1<<hr);
10096 regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
10097 regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
10098 regs[k].wasconst&=~(1<<hr);
10099 regs[k].isconst&=~(1<<hr);
10100 k++;
10101 }
10102 }
10103 else {
10104 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
10105 break;
10106 }
10107 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
10108 if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
10109 //printf("OK fill %x (r%d)\n",start+i*4,hr);
10110 regs[i].regmap_entry[hr]=f_regmap[hr];
10111 regs[i].regmap[hr]=f_regmap[hr];
10112 regs[i].wasdirty&=~(1<<hr);
10113 regs[i].dirty&=~(1<<hr);
10114 regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
10115 regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
10116 regs[i].wasconst&=~(1<<hr);
10117 regs[i].isconst&=~(1<<hr);
10118 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
10119 branch_regs[i].wasdirty&=~(1<<hr);
10120 branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
10121 branch_regs[i].regmap[hr]=f_regmap[hr];
10122 branch_regs[i].dirty&=~(1<<hr);
10123 branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
10124 branch_regs[i].wasconst&=~(1<<hr);
10125 branch_regs[i].isconst&=~(1<<hr);
10126 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
10127 regmap_pre[i+2][hr]=f_regmap[hr];
10128 regs[i+2].wasdirty&=~(1<<hr);
10129 regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
10130 assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
10131 (regs[i+2].was32&(1LL<<f_regmap[hr])));
10132 }
10133 }
10134 }
10135 for(k=t;k<j;k++) {
e1190b87 10136 // Alloc register clean at beginning of loop,
10137 // but may dirty it in pass 6
57871462 10138 regs[k].regmap_entry[hr]=f_regmap[hr];
10139 regs[k].regmap[hr]=f_regmap[hr];
57871462 10140 regs[k].dirty&=~(1<<hr);
10141 regs[k].wasconst&=~(1<<hr);
10142 regs[k].isconst&=~(1<<hr);
e1190b87 10143 if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) {
10144 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
10145 branch_regs[k].regmap[hr]=f_regmap[hr];
10146 branch_regs[k].dirty&=~(1<<hr);
10147 branch_regs[k].wasconst&=~(1<<hr);
10148 branch_regs[k].isconst&=~(1<<hr);
10149 if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
10150 regmap_pre[k+2][hr]=f_regmap[hr];
10151 regs[k+2].wasdirty&=~(1<<hr);
10152 assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))==
10153 (regs[k+2].was32&(1LL<<f_regmap[hr])));
10154 }
10155 }
10156 else
10157 {
10158 regmap_pre[k+1][hr]=f_regmap[hr];
10159 regs[k+1].wasdirty&=~(1<<hr);
10160 }
57871462 10161 }
10162 if(regs[j].regmap[hr]==f_regmap[hr])
10163 regs[j].regmap_entry[hr]=f_regmap[hr];
10164 break;
10165 }
10166 if(j==i) break;
10167 if(regs[j].regmap[hr]>=0)
10168 break;
10169 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
10170 //printf("no-match due to different register\n");
10171 break;
10172 }
10173 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
10174 //printf("32/64 mismatch %x %d\n",start+j*4,hr);
10175 break;
10176 }
e1190b87 10177 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10178 {
10179 // Stop on unconditional branch
10180 break;
10181 }
10182 if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
10183 {
10184 if(ooo[j]) {
10185 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
10186 break;
10187 }else{
10188 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
10189 break;
10190 }
10191 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
10192 //printf("no-match due to different register (branch)\n");
57871462 10193 break;
10194 }
10195 }
e1190b87 10196 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10197 //printf("No free regs for store %x\n",start+j*4);
10198 break;
10199 }
57871462 10200 if(f_regmap[hr]>=64) {
10201 if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
10202 break;
10203 }
10204 else
10205 {
10206 if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
10207 break;
10208 }
10209 }
10210 }
10211 }
10212 }
10213 }
10214 }
10215 }
10216 }else{
198df76f 10217 // Non branch or undetermined branch target
57871462 10218 for(hr=0;hr<HOST_REGS;hr++)
10219 {
10220 if(hr!=EXCLUDE_REG) {
10221 if(regs[i].regmap[hr]>64) {
10222 if(!((regs[i].dirty>>hr)&1))
10223 f_regmap[hr]=regs[i].regmap[hr];
10224 }
b372a952 10225 else if(regs[i].regmap[hr]>=0) {
10226 if(f_regmap[hr]!=regs[i].regmap[hr]) {
10227 // dealloc old register
10228 int n;
10229 for(n=0;n<HOST_REGS;n++)
10230 {
10231 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10232 }
10233 // and alloc new one
10234 f_regmap[hr]=regs[i].regmap[hr];
10235 }
10236 }
57871462 10237 }
10238 }
10239 // Try to restore cycle count at branch targets
10240 if(bt[i]) {
10241 for(j=i;j<slen-1;j++) {
10242 if(regs[j].regmap[HOST_CCREG]!=-1) break;
e1190b87 10243 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10244 //printf("no free regs for store %x\n",start+j*4);
10245 break;
57871462 10246 }
57871462 10247 }
10248 if(regs[j].regmap[HOST_CCREG]==CCREG) {
10249 int k=i;
10250 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
10251 while(k<j) {
10252 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10253 regs[k].regmap[HOST_CCREG]=CCREG;
10254 regmap_pre[k+1][HOST_CCREG]=CCREG;
10255 regs[k+1].wasdirty|=1<<HOST_CCREG;
10256 regs[k].dirty|=1<<HOST_CCREG;
10257 regs[k].wasconst&=~(1<<HOST_CCREG);
10258 regs[k].isconst&=~(1<<HOST_CCREG);
10259 k++;
10260 }
10261 regs[j].regmap_entry[HOST_CCREG]=CCREG;
10262 }
10263 // Work backwards from the branch target
10264 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
10265 {
10266 //printf("Extend backwards\n");
10267 int k;
10268 k=i;
10269 while(regs[k-1].regmap[HOST_CCREG]==-1) {
e1190b87 10270 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10271 //printf("no free regs for store %x\n",start+(k-1)*4);
10272 break;
57871462 10273 }
57871462 10274 k--;
10275 }
10276 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
10277 //printf("Extend CC, %x ->\n",start+k*4);
10278 while(k<=i) {
10279 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10280 regs[k].regmap[HOST_CCREG]=CCREG;
10281 regmap_pre[k+1][HOST_CCREG]=CCREG;
10282 regs[k+1].wasdirty|=1<<HOST_CCREG;
10283 regs[k].dirty|=1<<HOST_CCREG;
10284 regs[k].wasconst&=~(1<<HOST_CCREG);
10285 regs[k].isconst&=~(1<<HOST_CCREG);
10286 k++;
10287 }
10288 }
10289 else {
10290 //printf("Fail Extend CC, %x ->\n",start+k*4);
10291 }
10292 }
10293 }
10294 if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
10295 itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
10296 itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
e1190b87 10297 itype[i]!=FCONV&&itype[i]!=FCOMP)
57871462 10298 {
10299 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
10300 }
10301 }
10302 }
10303
d61de97e 10304 // Cache memory offset or tlb map pointer if a register is available
10305 #ifndef HOST_IMM_ADDR32
10306 #ifndef RAM_OFFSET
10307 if(using_tlb)
10308 #endif
10309 {
10310 int earliest_available[HOST_REGS];
10311 int loop_start[HOST_REGS];
10312 int score[HOST_REGS];
10313 int end[HOST_REGS];
10314 int reg=using_tlb?MMREG:ROREG;
10315
10316 // Init
10317 for(hr=0;hr<HOST_REGS;hr++) {
10318 score[hr]=0;earliest_available[hr]=0;
10319 loop_start[hr]=MAXBLOCK;
10320 }
10321 for(i=0;i<slen-1;i++)
10322 {
10323 // Can't do anything if no registers are available
10324 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i]) {
10325 for(hr=0;hr<HOST_REGS;hr++) {
10326 score[hr]=0;earliest_available[hr]=i+1;
10327 loop_start[hr]=MAXBLOCK;
10328 }
10329 }
10330 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10331 if(!ooo[i]) {
10332 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) {
10333 for(hr=0;hr<HOST_REGS;hr++) {
10334 score[hr]=0;earliest_available[hr]=i+1;
10335 loop_start[hr]=MAXBLOCK;
10336 }
10337 }
198df76f 10338 }else{
10339 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) {
10340 for(hr=0;hr<HOST_REGS;hr++) {
10341 score[hr]=0;earliest_available[hr]=i+1;
10342 loop_start[hr]=MAXBLOCK;
10343 }
10344 }
d61de97e 10345 }
10346 }
10347 // Mark unavailable registers
10348 for(hr=0;hr<HOST_REGS;hr++) {
10349 if(regs[i].regmap[hr]>=0) {
10350 score[hr]=0;earliest_available[hr]=i+1;
10351 loop_start[hr]=MAXBLOCK;
10352 }
10353 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10354 if(branch_regs[i].regmap[hr]>=0) {
10355 score[hr]=0;earliest_available[hr]=i+2;
10356 loop_start[hr]=MAXBLOCK;
10357 }
10358 }
10359 }
10360 // No register allocations after unconditional jumps
10361 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10362 {
10363 for(hr=0;hr<HOST_REGS;hr++) {
10364 score[hr]=0;earliest_available[hr]=i+2;
10365 loop_start[hr]=MAXBLOCK;
10366 }
10367 i++; // Skip delay slot too
10368 //printf("skip delay slot: %x\n",start+i*4);
10369 }
10370 else
10371 // Possible match
10372 if(itype[i]==LOAD||itype[i]==LOADLR||
10373 itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) {
10374 for(hr=0;hr<HOST_REGS;hr++) {
10375 if(hr!=EXCLUDE_REG) {
10376 end[hr]=i-1;
10377 for(j=i;j<slen-1;j++) {
10378 if(regs[j].regmap[hr]>=0) break;
10379 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10380 if(branch_regs[j].regmap[hr]>=0) break;
10381 if(ooo[j]) {
10382 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) break;
10383 }else{
10384 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) break;
10385 }
10386 }
10387 else if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) break;
10388 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10389 int t=(ba[j]-start)>>2;
10390 if(t<j&&t>=earliest_available[hr]) {
198df76f 10391 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) { // call/ret assumes no registers allocated
10392 // Score a point for hoisting loop invariant
10393 if(t<loop_start[hr]) loop_start[hr]=t;
10394 //printf("set loop_start: i=%x j=%x (%x)\n",start+i*4,start+j*4,start+t*4);
10395 score[hr]++;
10396 end[hr]=j;
10397 }
d61de97e 10398 }
10399 else if(t<j) {
10400 if(regs[t].regmap[hr]==reg) {
10401 // Score a point if the branch target matches this register
10402 score[hr]++;
10403 end[hr]=j;
10404 }
10405 }
10406 if(itype[j+1]==LOAD||itype[j+1]==LOADLR||
10407 itype[j+1]==STORE||itype[j+1]==STORELR||itype[j+1]==C1LS) {
10408 score[hr]++;
10409 end[hr]=j;
10410 }
10411 }
10412 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10413 {
10414 // Stop on unconditional branch
10415 break;
10416 }
10417 else
10418 if(itype[j]==LOAD||itype[j]==LOADLR||
10419 itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS) {
10420 score[hr]++;
10421 end[hr]=j;
10422 }
10423 }
10424 }
10425 }
10426 // Find highest score and allocate that register
10427 int maxscore=0;
10428 for(hr=0;hr<HOST_REGS;hr++) {
10429 if(hr!=EXCLUDE_REG) {
10430 if(score[hr]>score[maxscore]) {
10431 maxscore=hr;
10432 //printf("highest score: %d %d (%x->%x)\n",score[hr],hr,start+i*4,start+end[hr]*4);
10433 }
10434 }
10435 }
10436 if(score[maxscore]>1)
10437 {
10438 if(i<loop_start[maxscore]) loop_start[maxscore]=i;
10439 for(j=loop_start[maxscore];j<slen&&j<=end[maxscore];j++) {
10440 //if(regs[j].regmap[maxscore]>=0) {printf("oops: %x %x was %d=%d\n",loop_start[maxscore]*4+start,j*4+start,maxscore,regs[j].regmap[maxscore]);}
10441 assert(regs[j].regmap[maxscore]<0);
10442 if(j>loop_start[maxscore]) regs[j].regmap_entry[maxscore]=reg;
10443 regs[j].regmap[maxscore]=reg;
10444 regs[j].dirty&=~(1<<maxscore);
10445 regs[j].wasconst&=~(1<<maxscore);
10446 regs[j].isconst&=~(1<<maxscore);
10447 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10448 branch_regs[j].regmap[maxscore]=reg;
10449 branch_regs[j].wasdirty&=~(1<<maxscore);
10450 branch_regs[j].dirty&=~(1<<maxscore);
10451 branch_regs[j].wasconst&=~(1<<maxscore);
10452 branch_regs[j].isconst&=~(1<<maxscore);
10453 if(itype[j]!=RJUMP&&itype[j]!=UJUMP&&(source[j]>>16)!=0x1000) {
10454 regmap_pre[j+2][maxscore]=reg;
10455 regs[j+2].wasdirty&=~(1<<maxscore);
10456 }
10457 // loop optimization (loop_preload)
10458 int t=(ba[j]-start)>>2;
198df76f 10459 if(t==loop_start[maxscore]) {
10460 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) // call/ret assumes no registers allocated
10461 regs[t].regmap_entry[maxscore]=reg;
10462 }
d61de97e 10463 }
10464 else
10465 {
10466 if(j<1||(itype[j-1]!=RJUMP&&itype[j-1]!=UJUMP&&itype[j-1]!=CJUMP&&itype[j-1]!=SJUMP&&itype[j-1]!=FJUMP)) {
10467 regmap_pre[j+1][maxscore]=reg;
10468 regs[j+1].wasdirty&=~(1<<maxscore);
10469 }
10470 }
10471 }
10472 i=j-1;
10473 if(itype[j-1]==RJUMP||itype[j-1]==UJUMP||itype[j-1]==CJUMP||itype[j-1]==SJUMP||itype[j-1]==FJUMP) i++; // skip delay slot
10474 for(hr=0;hr<HOST_REGS;hr++) {
10475 score[hr]=0;earliest_available[hr]=i+i;
10476 loop_start[hr]=MAXBLOCK;
10477 }
10478 }
10479 }
10480 }
10481 }
10482 #endif
10483
57871462 10484 // This allocates registers (if possible) one instruction prior
10485 // to use, which can avoid a load-use penalty on certain CPUs.
10486 for(i=0;i<slen-1;i++)
10487 {
10488 if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10489 {
10490 if(!bt[i+1])
10491 {
b9b61529 10492 if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
10493 ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
57871462 10494 {
10495 if(rs1[i+1]) {
10496 if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10497 {
10498 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10499 {
10500 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10501 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10502 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10503 regs[i].isconst&=~(1<<hr);
10504 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10505 constmap[i][hr]=constmap[i+1][hr];
10506 regs[i+1].wasdirty&=~(1<<hr);
10507 regs[i].dirty&=~(1<<hr);
10508 }
10509 }
10510 }
10511 if(rs2[i+1]) {
10512 if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10513 {
10514 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10515 {
10516 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10517 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10518 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10519 regs[i].isconst&=~(1<<hr);
10520 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10521 constmap[i][hr]=constmap[i+1][hr];
10522 regs[i+1].wasdirty&=~(1<<hr);
10523 regs[i].dirty&=~(1<<hr);
10524 }
10525 }
10526 }
198df76f 10527 // Preload target address for load instruction (non-constant)
57871462 10528 if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10529 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10530 {
10531 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10532 {
10533 regs[i].regmap[hr]=rs1[i+1];
10534 regmap_pre[i+1][hr]=rs1[i+1];
10535 regs[i+1].regmap_entry[hr]=rs1[i+1];
10536 regs[i].isconst&=~(1<<hr);
10537 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10538 constmap[i][hr]=constmap[i+1][hr];
10539 regs[i+1].wasdirty&=~(1<<hr);
10540 regs[i].dirty&=~(1<<hr);
10541 }
10542 }
10543 }
198df76f 10544 // Load source into target register
57871462 10545 if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10546 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10547 {
10548 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10549 {
10550 regs[i].regmap[hr]=rs1[i+1];
10551 regmap_pre[i+1][hr]=rs1[i+1];
10552 regs[i+1].regmap_entry[hr]=rs1[i+1];
10553 regs[i].isconst&=~(1<<hr);
10554 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10555 constmap[i][hr]=constmap[i+1][hr];
10556 regs[i+1].wasdirty&=~(1<<hr);
10557 regs[i].dirty&=~(1<<hr);
10558 }
10559 }
10560 }
198df76f 10561 // Preload map address
57871462 10562 #ifndef HOST_IMM_ADDR32
b9b61529 10563 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
57871462 10564 hr=get_reg(regs[i+1].regmap,TLREG);
10565 if(hr>=0) {
10566 int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10567 if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10568 int nr;
10569 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10570 {
10571 regs[i].regmap[hr]=MGEN1+((i+1)&1);
10572 regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10573 regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10574 regs[i].isconst&=~(1<<hr);
10575 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10576 constmap[i][hr]=constmap[i+1][hr];
10577 regs[i+1].wasdirty&=~(1<<hr);
10578 regs[i].dirty&=~(1<<hr);
10579 }
10580 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10581 {
10582 // move it to another register
10583 regs[i+1].regmap[hr]=-1;
10584 regmap_pre[i+2][hr]=-1;
10585 regs[i+1].regmap[nr]=TLREG;
10586 regmap_pre[i+2][nr]=TLREG;
10587 regs[i].regmap[nr]=MGEN1+((i+1)&1);
10588 regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10589 regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10590 regs[i].isconst&=~(1<<nr);
10591 regs[i+1].isconst&=~(1<<nr);
10592 regs[i].dirty&=~(1<<nr);
10593 regs[i+1].wasdirty&=~(1<<nr);
10594 regs[i+1].dirty&=~(1<<nr);
10595 regs[i+2].wasdirty&=~(1<<nr);
10596 }
10597 }
10598 }
10599 }
10600 #endif
198df76f 10601 // Address for store instruction (non-constant)
b9b61529 10602 if(itype[i+1]==STORE||itype[i+1]==STORELR
10603 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
57871462 10604 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10605 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10606 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10607 else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10608 assert(hr>=0);
10609 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10610 {
10611 regs[i].regmap[hr]=rs1[i+1];
10612 regmap_pre[i+1][hr]=rs1[i+1];
10613 regs[i+1].regmap_entry[hr]=rs1[i+1];
10614 regs[i].isconst&=~(1<<hr);
10615 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10616 constmap[i][hr]=constmap[i+1][hr];
10617 regs[i+1].wasdirty&=~(1<<hr);
10618 regs[i].dirty&=~(1<<hr);
10619 }
10620 }
10621 }
b9b61529 10622 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
57871462 10623 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10624 int nr;
10625 hr=get_reg(regs[i+1].regmap,FTEMP);
10626 assert(hr>=0);
10627 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10628 {
10629 regs[i].regmap[hr]=rs1[i+1];
10630 regmap_pre[i+1][hr]=rs1[i+1];
10631 regs[i+1].regmap_entry[hr]=rs1[i+1];
10632 regs[i].isconst&=~(1<<hr);
10633 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10634 constmap[i][hr]=constmap[i+1][hr];
10635 regs[i+1].wasdirty&=~(1<<hr);
10636 regs[i].dirty&=~(1<<hr);
10637 }
10638 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10639 {
10640 // move it to another register
10641 regs[i+1].regmap[hr]=-1;
10642 regmap_pre[i+2][hr]=-1;
10643 regs[i+1].regmap[nr]=FTEMP;
10644 regmap_pre[i+2][nr]=FTEMP;
10645 regs[i].regmap[nr]=rs1[i+1];
10646 regmap_pre[i+1][nr]=rs1[i+1];
10647 regs[i+1].regmap_entry[nr]=rs1[i+1];
10648 regs[i].isconst&=~(1<<nr);
10649 regs[i+1].isconst&=~(1<<nr);
10650 regs[i].dirty&=~(1<<nr);
10651 regs[i+1].wasdirty&=~(1<<nr);
10652 regs[i+1].dirty&=~(1<<nr);
10653 regs[i+2].wasdirty&=~(1<<nr);
10654 }
10655 }
10656 }
b9b61529 10657 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
57871462 10658 if(itype[i+1]==LOAD)
10659 hr=get_reg(regs[i+1].regmap,rt1[i+1]);
b9b61529 10660 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
57871462 10661 hr=get_reg(regs[i+1].regmap,FTEMP);
b9b61529 10662 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
57871462 10663 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10664 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10665 }
10666 if(hr>=0&&regs[i].regmap[hr]<0) {
10667 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10668 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10669 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10670 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10671 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10672 regs[i].isconst&=~(1<<hr);
10673 regs[i+1].wasdirty&=~(1<<hr);
10674 regs[i].dirty&=~(1<<hr);
10675 }
10676 }
10677 }
10678 }
10679 }
10680 }
10681 }
10682
10683 /* Pass 6 - Optimize clean/dirty state */
10684 clean_registers(0,slen-1,1);
10685
10686 /* Pass 7 - Identify 32-bit registers */
a28c6ce8 10687#ifndef FORCE32
57871462 10688 provisional_r32();
10689
10690 u_int r32=0;
10691
10692 for (i=slen-1;i>=0;i--)
10693 {
10694 int hr;
10695 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10696 {
10697 if(ba[i]<start || ba[i]>=(start+slen*4))
10698 {
10699 // Branch out of this block, don't need anything
10700 r32=0;
10701 }
10702 else
10703 {
10704 // Internal branch
10705 // Need whatever matches the target
10706 // (and doesn't get overwritten by the delay slot instruction)
10707 r32=0;
10708 int t=(ba[i]-start)>>2;
10709 if(ba[i]>start+i*4) {
10710 // Forward branch
10711 if(!(requires_32bit[t]&~regs[i].was32))
10712 r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10713 }else{
10714 // Backward branch
10715 //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10716 // r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10717 if(!(pr32[t]&~regs[i].was32))
10718 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10719 }
10720 }
10721 // Conditional branch may need registers for following instructions
10722 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10723 {
10724 if(i<slen-2) {
10725 r32|=requires_32bit[i+2];
10726 r32&=regs[i].was32;
10727 // Mark this address as a branch target since it may be called
10728 // upon return from interrupt
10729 bt[i+2]=1;
10730 }
10731 }
10732 // Merge in delay slot
10733 if(!likely[i]) {
10734 // These are overwritten unless the branch is "likely"
10735 // and the delay slot is nullified if not taken
10736 r32&=~(1LL<<rt1[i+1]);
10737 r32&=~(1LL<<rt2[i+1]);
10738 }
10739 // Assume these are needed (delay slot)
10740 if(us1[i+1]>0)
10741 {
10742 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10743 }
10744 if(us2[i+1]>0)
10745 {
10746 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10747 }
10748 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10749 {
10750 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10751 }
10752 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10753 {
10754 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10755 }
10756 }
1e973cb0 10757 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
57871462 10758 {
10759 // SYSCALL instruction (software interrupt)
10760 r32=0;
10761 }
10762 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10763 {
10764 // ERET instruction (return from interrupt)
10765 r32=0;
10766 }
10767 // Check 32 bits
10768 r32&=~(1LL<<rt1[i]);
10769 r32&=~(1LL<<rt2[i]);
10770 if(us1[i]>0)
10771 {
10772 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10773 }
10774 if(us2[i]>0)
10775 {
10776 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10777 }
10778 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
10779 {
10780 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
10781 }
10782 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
10783 {
10784 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
10785 }
10786 requires_32bit[i]=r32;
10787
10788 // Dirty registers which are 32-bit, require 32-bit input
10789 // as they will be written as 32-bit values
10790 for(hr=0;hr<HOST_REGS;hr++)
10791 {
10792 if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
10793 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
10794 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
10795 requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
10796 }
10797 }
10798 }
10799 //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
10800 }
04fd948a 10801#else
10802 for (i=slen-1;i>=0;i--)
10803 {
10804 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10805 {
10806 // Conditional branch
10807 if((source[i]>>16)!=0x1000&&i<slen-2) {
10808 // Mark this address as a branch target since it may be called
10809 // upon return from interrupt
10810 bt[i+2]=1;
10811 }
10812 }
10813 }
a28c6ce8 10814#endif
57871462 10815
10816 if(itype[slen-1]==SPAN) {
10817 bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
10818 }
10819
10820 /* Debug/disassembly */
10821 if((void*)assem_debug==(void*)printf)
10822 for(i=0;i<slen;i++)
10823 {
10824 printf("U:");
10825 int r;
10826 for(r=1;r<=CCREG;r++) {
10827 if((unneeded_reg[i]>>r)&1) {
10828 if(r==HIREG) printf(" HI");
10829 else if(r==LOREG) printf(" LO");
10830 else printf(" r%d",r);
10831 }
10832 }
90ae6d4e 10833#ifndef FORCE32
57871462 10834 printf(" UU:");
10835 for(r=1;r<=CCREG;r++) {
10836 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
10837 if(r==HIREG) printf(" HI");
10838 else if(r==LOREG) printf(" LO");
10839 else printf(" r%d",r);
10840 }
10841 }
10842 printf(" 32:");
10843 for(r=0;r<=CCREG;r++) {
10844 //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10845 if((regs[i].was32>>r)&1) {
10846 if(r==CCREG) printf(" CC");
10847 else if(r==HIREG) printf(" HI");
10848 else if(r==LOREG) printf(" LO");
10849 else printf(" r%d",r);
10850 }
10851 }
90ae6d4e 10852#endif
57871462 10853 printf("\n");
10854 #if defined(__i386__) || defined(__x86_64__)
10855 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
10856 #endif
10857 #ifdef __arm__
10858 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
10859 #endif
10860 printf("needs: ");
10861 if(needed_reg[i]&1) printf("eax ");
10862 if((needed_reg[i]>>1)&1) printf("ecx ");
10863 if((needed_reg[i]>>2)&1) printf("edx ");
10864 if((needed_reg[i]>>3)&1) printf("ebx ");
10865 if((needed_reg[i]>>5)&1) printf("ebp ");
10866 if((needed_reg[i]>>6)&1) printf("esi ");
10867 if((needed_reg[i]>>7)&1) printf("edi ");
10868 printf("r:");
10869 for(r=0;r<=CCREG;r++) {
10870 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10871 if((requires_32bit[i]>>r)&1) {
10872 if(r==CCREG) printf(" CC");
10873 else if(r==HIREG) printf(" HI");
10874 else if(r==LOREG) printf(" LO");
10875 else printf(" r%d",r);
10876 }
10877 }
10878 printf("\n");
10879 /*printf("pr:");
10880 for(r=0;r<=CCREG;r++) {
10881 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10882 if((pr32[i]>>r)&1) {
10883 if(r==CCREG) printf(" CC");
10884 else if(r==HIREG) printf(" HI");
10885 else if(r==LOREG) printf(" LO");
10886 else printf(" r%d",r);
10887 }
10888 }
10889 if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
10890 printf("\n");*/
10891 #if defined(__i386__) || defined(__x86_64__)
10892 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
10893 printf("dirty: ");
10894 if(regs[i].wasdirty&1) printf("eax ");
10895 if((regs[i].wasdirty>>1)&1) printf("ecx ");
10896 if((regs[i].wasdirty>>2)&1) printf("edx ");
10897 if((regs[i].wasdirty>>3)&1) printf("ebx ");
10898 if((regs[i].wasdirty>>5)&1) printf("ebp ");
10899 if((regs[i].wasdirty>>6)&1) printf("esi ");
10900 if((regs[i].wasdirty>>7)&1) printf("edi ");
10901 #endif
10902 #ifdef __arm__
10903 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
10904 printf("dirty: ");
10905 if(regs[i].wasdirty&1) printf("r0 ");
10906 if((regs[i].wasdirty>>1)&1) printf("r1 ");
10907 if((regs[i].wasdirty>>2)&1) printf("r2 ");
10908 if((regs[i].wasdirty>>3)&1) printf("r3 ");
10909 if((regs[i].wasdirty>>4)&1) printf("r4 ");
10910 if((regs[i].wasdirty>>5)&1) printf("r5 ");
10911 if((regs[i].wasdirty>>6)&1) printf("r6 ");
10912 if((regs[i].wasdirty>>7)&1) printf("r7 ");
10913 if((regs[i].wasdirty>>8)&1) printf("r8 ");
10914 if((regs[i].wasdirty>>9)&1) printf("r9 ");
10915 if((regs[i].wasdirty>>10)&1) printf("r10 ");
10916 if((regs[i].wasdirty>>12)&1) printf("r12 ");
10917 #endif
10918 printf("\n");
10919 disassemble_inst(i);
10920 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
10921 #if defined(__i386__) || defined(__x86_64__)
10922 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
10923 if(regs[i].dirty&1) printf("eax ");
10924 if((regs[i].dirty>>1)&1) printf("ecx ");
10925 if((regs[i].dirty>>2)&1) printf("edx ");
10926 if((regs[i].dirty>>3)&1) printf("ebx ");
10927 if((regs[i].dirty>>5)&1) printf("ebp ");
10928 if((regs[i].dirty>>6)&1) printf("esi ");
10929 if((regs[i].dirty>>7)&1) printf("edi ");
10930 #endif
10931 #ifdef __arm__
10932 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
10933 if(regs[i].dirty&1) printf("r0 ");
10934 if((regs[i].dirty>>1)&1) printf("r1 ");
10935 if((regs[i].dirty>>2)&1) printf("r2 ");
10936 if((regs[i].dirty>>3)&1) printf("r3 ");
10937 if((regs[i].dirty>>4)&1) printf("r4 ");
10938 if((regs[i].dirty>>5)&1) printf("r5 ");
10939 if((regs[i].dirty>>6)&1) printf("r6 ");
10940 if((regs[i].dirty>>7)&1) printf("r7 ");
10941 if((regs[i].dirty>>8)&1) printf("r8 ");
10942 if((regs[i].dirty>>9)&1) printf("r9 ");
10943 if((regs[i].dirty>>10)&1) printf("r10 ");
10944 if((regs[i].dirty>>12)&1) printf("r12 ");
10945 #endif
10946 printf("\n");
10947 if(regs[i].isconst) {
10948 printf("constants: ");
10949 #if defined(__i386__) || defined(__x86_64__)
10950 if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
10951 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
10952 if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
10953 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
10954 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
10955 if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
10956 if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
10957 #endif
10958 #ifdef __arm__
10959 if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
10960 if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
10961 if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
10962 if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
10963 if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
10964 if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
10965 if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
10966 if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
10967 if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
10968 if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
10969 if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
10970 if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
10971 #endif
10972 printf("\n");
10973 }
90ae6d4e 10974#ifndef FORCE32
57871462 10975 printf(" 32:");
10976 for(r=0;r<=CCREG;r++) {
10977 if((regs[i].is32>>r)&1) {
10978 if(r==CCREG) printf(" CC");
10979 else if(r==HIREG) printf(" HI");
10980 else if(r==LOREG) printf(" LO");
10981 else printf(" r%d",r);
10982 }
10983 }
10984 printf("\n");
90ae6d4e 10985#endif
57871462 10986 /*printf(" p32:");
10987 for(r=0;r<=CCREG;r++) {
10988 if((p32[i]>>r)&1) {
10989 if(r==CCREG) printf(" CC");
10990 else if(r==HIREG) printf(" HI");
10991 else if(r==LOREG) printf(" LO");
10992 else printf(" r%d",r);
10993 }
10994 }
10995 if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
10996 else printf("\n");*/
10997 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10998 #if defined(__i386__) || defined(__x86_64__)
10999 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
11000 if(branch_regs[i].dirty&1) printf("eax ");
11001 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
11002 if((branch_regs[i].dirty>>2)&1) printf("edx ");
11003 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
11004 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
11005 if((branch_regs[i].dirty>>6)&1) printf("esi ");
11006 if((branch_regs[i].dirty>>7)&1) printf("edi ");
11007 #endif
11008 #ifdef __arm__
11009 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
11010 if(branch_regs[i].dirty&1) printf("r0 ");
11011 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
11012 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
11013 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
11014 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
11015 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
11016 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
11017 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
11018 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
11019 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
11020 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
11021 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
11022 #endif
90ae6d4e 11023#ifndef FORCE32
57871462 11024 printf(" 32:");
11025 for(r=0;r<=CCREG;r++) {
11026 if((branch_regs[i].is32>>r)&1) {
11027 if(r==CCREG) printf(" CC");
11028 else if(r==HIREG) printf(" HI");
11029 else if(r==LOREG) printf(" LO");
11030 else printf(" r%d",r);
11031 }
11032 }
11033 printf("\n");
90ae6d4e 11034#endif
57871462 11035 }
11036 }
11037
11038 /* Pass 8 - Assembly */
11039 linkcount=0;stubcount=0;
11040 ds=0;is_delayslot=0;
11041 cop1_usable=0;
11042 uint64_t is32_pre=0;
11043 u_int dirty_pre=0;
11044 u_int beginning=(u_int)out;
11045 if((u_int)addr&1) {
11046 ds=1;
11047 pagespan_ds();
11048 }
9ad4d757 11049 u_int instr_addr0_override=0;
11050
11051#ifdef PCSX
11052 if (start == 0x80030000) {
11053 // nasty hack for fastbios thing
96186eba 11054 // override block entry to this code
9ad4d757 11055 instr_addr0_override=(u_int)out;
11056 emit_movimm(start,0);
96186eba 11057 // abuse io address var as a flag that we
11058 // have already returned here once
11059 emit_readword((int)&address,1);
9ad4d757 11060 emit_writeword(0,(int)&pcaddr);
96186eba 11061 emit_writeword(0,(int)&address);
9ad4d757 11062 emit_cmp(0,1);
11063 emit_jne((int)new_dyna_leave);
11064 }
11065#endif
57871462 11066 for(i=0;i<slen;i++)
11067 {
11068 //if(ds) printf("ds: ");
11069 if((void*)assem_debug==(void*)printf) disassemble_inst(i);
11070 if(ds) {
11071 ds=0; // Skip delay slot
11072 if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
11073 instr_addr[i]=0;
11074 } else {
11075 #ifndef DESTRUCTIVE_WRITEBACK
11076 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11077 {
11078 wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
11079 unneeded_reg[i],unneeded_reg_upper[i]);
11080 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
11081 unneeded_reg[i],unneeded_reg_upper[i]);
11082 }
f776eb14 11083 if((itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)&&!likely[i]) {
11084 is32_pre=branch_regs[i].is32;
11085 dirty_pre=branch_regs[i].dirty;
11086 }else{
11087 is32_pre=regs[i].is32;
11088 dirty_pre=regs[i].dirty;
11089 }
57871462 11090 #endif
11091 // write back
11092 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11093 {
11094 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
11095 unneeded_reg[i],unneeded_reg_upper[i]);
11096 loop_preload(regmap_pre[i],regs[i].regmap_entry);
11097 }
11098 // branch target entry point
11099 instr_addr[i]=(u_int)out;
11100 assem_debug("<->\n");
11101 // load regs
11102 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
11103 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
11104 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
11105 address_generation(i,&regs[i],regs[i].regmap_entry);
11106 load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
11107 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
11108 {
11109 // Load the delay slot registers if necessary
4ef8f67d 11110 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i]&&(rs1[i+1]!=rt1[i]||rt1[i]==0))
57871462 11111 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
4ef8f67d 11112 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i]&&(rs2[i+1]!=rt1[i]||rt1[i]==0))
57871462 11113 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
b9b61529 11114 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
57871462 11115 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11116 }
11117 else if(i+1<slen)
11118 {
11119 // Preload registers for following instruction
11120 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
11121 if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
11122 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11123 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
11124 if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
11125 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11126 }
11127 // TODO: if(is_ooo(i)) address_generation(i+1);
11128 if(itype[i]==CJUMP||itype[i]==FJUMP)
11129 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
b9b61529 11130 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
57871462 11131 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11132 if(bt[i]) cop1_usable=0;
11133 // assemble
11134 switch(itype[i]) {
11135 case ALU:
11136 alu_assemble(i,&regs[i]);break;
11137 case IMM16:
11138 imm16_assemble(i,&regs[i]);break;
11139 case SHIFT:
11140 shift_assemble(i,&regs[i]);break;
11141 case SHIFTIMM:
11142 shiftimm_assemble(i,&regs[i]);break;
11143 case LOAD:
11144 load_assemble(i,&regs[i]);break;
11145 case LOADLR:
11146 loadlr_assemble(i,&regs[i]);break;
11147 case STORE:
11148 store_assemble(i,&regs[i]);break;
11149 case STORELR:
11150 storelr_assemble(i,&regs[i]);break;
11151 case COP0:
11152 cop0_assemble(i,&regs[i]);break;
11153 case COP1:
11154 cop1_assemble(i,&regs[i]);break;
11155 case C1LS:
11156 c1ls_assemble(i,&regs[i]);break;
b9b61529 11157 case COP2:
11158 cop2_assemble(i,&regs[i]);break;
11159 case C2LS:
11160 c2ls_assemble(i,&regs[i]);break;
11161 case C2OP:
11162 c2op_assemble(i,&regs[i]);break;
57871462 11163 case FCONV:
11164 fconv_assemble(i,&regs[i]);break;
11165 case FLOAT:
11166 float_assemble(i,&regs[i]);break;
11167 case FCOMP:
11168 fcomp_assemble(i,&regs[i]);break;
11169 case MULTDIV:
11170 multdiv_assemble(i,&regs[i]);break;
11171 case MOV:
11172 mov_assemble(i,&regs[i]);break;
11173 case SYSCALL:
11174 syscall_assemble(i,&regs[i]);break;
7139f3c8 11175 case HLECALL:
11176 hlecall_assemble(i,&regs[i]);break;
1e973cb0 11177 case INTCALL:
11178 intcall_assemble(i,&regs[i]);break;
57871462 11179 case UJUMP:
11180 ujump_assemble(i,&regs[i]);ds=1;break;
11181 case RJUMP:
11182 rjump_assemble(i,&regs[i]);ds=1;break;
11183 case CJUMP:
11184 cjump_assemble(i,&regs[i]);ds=1;break;
11185 case SJUMP:
11186 sjump_assemble(i,&regs[i]);ds=1;break;
11187 case FJUMP:
11188 fjump_assemble(i,&regs[i]);ds=1;break;
11189 case SPAN:
11190 pagespan_assemble(i,&regs[i]);break;
11191 }
11192 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
11193 literal_pool(1024);
11194 else
11195 literal_pool_jumpover(256);
11196 }
11197 }
11198 //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
11199 // If the block did not end with an unconditional branch,
11200 // add a jump to the next instruction.
11201 if(i>1) {
11202 if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
11203 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11204 assert(i==slen);
11205 if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
11206 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11207 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11208 emit_loadreg(CCREG,HOST_CCREG);
11209 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
11210 }
11211 else if(!likely[i-2])
11212 {
11213 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
11214 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
11215 }
11216 else
11217 {
11218 store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
11219 assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
11220 }
11221 add_to_linker((int)out,start+i*4,0);
11222 emit_jmp(0);
11223 }
11224 }
11225 else
11226 {
11227 assert(i>0);
11228 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11229 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11230 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11231 emit_loadreg(CCREG,HOST_CCREG);
11232 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
11233 add_to_linker((int)out,start+i*4,0);
11234 emit_jmp(0);
11235 }
11236
11237 // TODO: delay slot stubs?
11238 // Stubs
11239 for(i=0;i<stubcount;i++)
11240 {
11241 switch(stubs[i][0])
11242 {
11243 case LOADB_STUB:
11244 case LOADH_STUB:
11245 case LOADW_STUB:
11246 case LOADD_STUB:
11247 case LOADBU_STUB:
11248 case LOADHU_STUB:
11249 do_readstub(i);break;
11250 case STOREB_STUB:
11251 case STOREH_STUB:
11252 case STOREW_STUB:
11253 case STORED_STUB:
11254 do_writestub(i);break;
11255 case CC_STUB:
11256 do_ccstub(i);break;
11257 case INVCODE_STUB:
11258 do_invstub(i);break;
11259 case FP_STUB:
11260 do_cop1stub(i);break;
11261 case STORELR_STUB:
11262 do_unalignedwritestub(i);break;
11263 }
11264 }
11265
9ad4d757 11266 if (instr_addr0_override)
11267 instr_addr[0] = instr_addr0_override;
11268
57871462 11269 /* Pass 9 - Linker */
11270 for(i=0;i<linkcount;i++)
11271 {
11272 assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
11273 literal_pool(64);
11274 if(!link_addr[i][2])
11275 {
11276 void *stub=out;
11277 void *addr=check_addr(link_addr[i][1]);
11278 emit_extjump(link_addr[i][0],link_addr[i][1]);
11279 if(addr) {
11280 set_jump_target(link_addr[i][0],(int)addr);
11281 add_link(link_addr[i][1],stub);
11282 }
11283 else set_jump_target(link_addr[i][0],(int)stub);
11284 }
11285 else
11286 {
11287 // Internal branch
11288 int target=(link_addr[i][1]-start)>>2;
11289 assert(target>=0&&target<slen);
11290 assert(instr_addr[target]);
11291 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11292 //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
11293 //#else
11294 set_jump_target(link_addr[i][0],instr_addr[target]);
11295 //#endif
11296 }
11297 }
11298 // External Branch Targets (jump_in)
11299 if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
11300 for(i=0;i<slen;i++)
11301 {
11302 if(bt[i]||i==0)
11303 {
11304 if(instr_addr[i]) // TODO - delay slots (=null)
11305 {
11306 u_int vaddr=start+i*4;
94d23bb9 11307 u_int page=get_page(vaddr);
11308 u_int vpage=get_vpage(vaddr);
57871462 11309 literal_pool(256);
11310 //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
a28c6ce8 11311#ifndef FORCE32
57871462 11312 if(!requires_32bit[i])
a28c6ce8 11313#else
11314 if(1)
11315#endif
57871462 11316 {
11317 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11318 assem_debug("jump_in: %x\n",start+i*4);
11319 ll_add(jump_dirty+vpage,vaddr,(void *)out);
11320 int entry_point=do_dirty_stub(i);
11321 ll_add(jump_in+page,vaddr,(void *)entry_point);
11322 // If there was an existing entry in the hash table,
11323 // replace it with the new address.
11324 // Don't add new entries. We'll insert the
11325 // ones that actually get used in check_addr().
11326 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
11327 if(ht_bin[0]==vaddr) {
11328 ht_bin[1]=entry_point;
11329 }
11330 if(ht_bin[2]==vaddr) {
11331 ht_bin[3]=entry_point;
11332 }
11333 }
11334 else
11335 {
11336 u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
11337 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11338 assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
11339 //int entry_point=(int)out;
11340 ////assem_debug("entry_point: %x\n",entry_point);
11341 //load_regs_entry(i);
11342 //if(entry_point==(int)out)
11343 // entry_point=instr_addr[i];
11344 //else
11345 // emit_jmp(instr_addr[i]);
11346 //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11347 ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
11348 int entry_point=do_dirty_stub(i);
11349 ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11350 }
11351 }
11352 }
11353 }
11354 // Write out the literal pool if necessary
11355 literal_pool(0);
11356 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11357 // Align code
11358 if(((u_int)out)&7) emit_addnop(13);
11359 #endif
11360 assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
11361 //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
11362 memcpy(copy,source,slen*4);
11363 copy+=slen*4;
11364
11365 #ifdef __arm__
11366 __clear_cache((void *)beginning,out);
11367 #endif
11368
11369 // If we're within 256K of the end of the buffer,
11370 // start over from the beginning. (Is 256K enough?)
11371 if((int)out>BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
11372
11373 // Trap writes to any of the pages we compiled
11374 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
11375 invalid_code[i]=0;
90ae6d4e 11376#ifndef DISABLE_TLB
57871462 11377 memory_map[i]|=0x40000000;
11378 if((signed int)start>=(signed int)0xC0000000) {
11379 assert(using_tlb);
11380 j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
11381 invalid_code[j]=0;
11382 memory_map[j]|=0x40000000;
11383 //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
11384 }
90ae6d4e 11385#endif
57871462 11386 }
9be4ba64 11387 inv_code_start=inv_code_end=~0;
b12c9fb8 11388#ifdef PCSX
11389 // PCSX maps all RAM mirror invalid_code tests to 0x80000000..0x80000000+RAM_SIZE
11390 if(get_page(start)<(RAM_SIZE>>12))
11391 for(i=start>>12;i<=(start+slen*4)>>12;i++)
11392 invalid_code[((u_int)0x80000000>>12)|i]=0;
11393#endif
57871462 11394
11395 /* Pass 10 - Free memory by expiring oldest blocks */
11396
11397 int end=((((int)out-BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
11398 while(expirep!=end)
11399 {
11400 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
11401 int base=BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
11402 inv_debug("EXP: Phase %d\n",expirep);
11403 switch((expirep>>11)&3)
11404 {
11405 case 0:
11406 // Clear jump_in and jump_dirty
11407 ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
11408 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
11409 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
11410 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
11411 break;
11412 case 1:
11413 // Clear pointers
11414 ll_kill_pointers(jump_out[expirep&2047],base,shift);
11415 ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
11416 break;
11417 case 2:
11418 // Clear hash table
11419 for(i=0;i<32;i++) {
11420 int *ht_bin=hash_table[((expirep&2047)<<5)+i];
11421 if((ht_bin[3]>>shift)==(base>>shift) ||
11422 ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11423 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
11424 ht_bin[2]=ht_bin[3]=-1;
11425 }
11426 if((ht_bin[1]>>shift)==(base>>shift) ||
11427 ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11428 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
11429 ht_bin[0]=ht_bin[2];
11430 ht_bin[1]=ht_bin[3];
11431 ht_bin[2]=ht_bin[3]=-1;
11432 }
11433 }
11434 break;
11435 case 3:
11436 // Clear jump_out
dd3a91a1 11437 #ifdef __arm__
11438 if((expirep&2047)==0)
11439 do_clear_cache();
11440 #endif
57871462 11441 ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
11442 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
11443 break;
11444 }
11445 expirep=(expirep+1)&65535;
11446 }
11447 return 0;
11448}
b9b61529 11449
11450// vim:shiftwidth=2:expandtab
ARM optimized PCSX fork