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drc: add forgotten __clear_cache
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
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57871462 1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2010 Ari64 *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21#include <stdlib.h>
22#include <stdint.h> //include for uint64_t
23#include <assert.h>
24
3d624f89 25#include "emu_if.h" //emulator interface
57871462 26
27#include <sys/mman.h>
28
29#ifdef __i386__
30#include "assem_x86.h"
31#endif
32#ifdef __x86_64__
33#include "assem_x64.h"
34#endif
35#ifdef __arm__
36#include "assem_arm.h"
37#endif
38
39#define MAXBLOCK 4096
40#define MAX_OUTPUT_BLOCK_SIZE 262144
41#define CLOCK_DIVIDER 2
42
43struct regstat
44{
45 signed char regmap_entry[HOST_REGS];
46 signed char regmap[HOST_REGS];
47 uint64_t was32;
48 uint64_t is32;
49 uint64_t wasdirty;
50 uint64_t dirty;
51 uint64_t u;
52 uint64_t uu;
53 u_int wasconst;
54 u_int isconst;
55 uint64_t constmap[HOST_REGS];
56};
57
58struct ll_entry
59{
60 u_int vaddr;
61 u_int reg32;
62 void *addr;
63 struct ll_entry *next;
64};
65
66 u_int start;
67 u_int *source;
68 u_int pagelimit;
69 char insn[MAXBLOCK][10];
70 u_char itype[MAXBLOCK];
71 u_char opcode[MAXBLOCK];
72 u_char opcode2[MAXBLOCK];
73 u_char bt[MAXBLOCK];
74 u_char rs1[MAXBLOCK];
75 u_char rs2[MAXBLOCK];
76 u_char rt1[MAXBLOCK];
77 u_char rt2[MAXBLOCK];
78 u_char us1[MAXBLOCK];
79 u_char us2[MAXBLOCK];
80 u_char dep1[MAXBLOCK];
81 u_char dep2[MAXBLOCK];
82 u_char lt1[MAXBLOCK];
83 int imm[MAXBLOCK];
84 u_int ba[MAXBLOCK];
85 char likely[MAXBLOCK];
86 char is_ds[MAXBLOCK];
87 uint64_t unneeded_reg[MAXBLOCK];
88 uint64_t unneeded_reg_upper[MAXBLOCK];
89 uint64_t branch_unneeded_reg[MAXBLOCK];
90 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
91 uint64_t p32[MAXBLOCK];
92 uint64_t pr32[MAXBLOCK];
93 signed char regmap_pre[MAXBLOCK][HOST_REGS];
94 signed char regmap[MAXBLOCK][HOST_REGS];
95 signed char regmap_entry[MAXBLOCK][HOST_REGS];
96 uint64_t constmap[MAXBLOCK][HOST_REGS];
97 uint64_t known_value[HOST_REGS];
98 u_int known_reg;
99 struct regstat regs[MAXBLOCK];
100 struct regstat branch_regs[MAXBLOCK];
101 u_int needed_reg[MAXBLOCK];
102 uint64_t requires_32bit[MAXBLOCK];
103 u_int wont_dirty[MAXBLOCK];
104 u_int will_dirty[MAXBLOCK];
105 int ccadj[MAXBLOCK];
106 int slen;
107 u_int instr_addr[MAXBLOCK];
108 u_int link_addr[MAXBLOCK][3];
109 int linkcount;
110 u_int stubs[MAXBLOCK*3][8];
111 int stubcount;
112 u_int literals[1024][2];
113 int literalcount;
114 int is_delayslot;
115 int cop1_usable;
116 u_char *out;
117 struct ll_entry *jump_in[4096];
118 struct ll_entry *jump_out[4096];
119 struct ll_entry *jump_dirty[4096];
120 u_int hash_table[65536][4] __attribute__((aligned(16)));
121 char shadow[1048576] __attribute__((aligned(16)));
122 void *copy;
123 int expirep;
124 u_int using_tlb;
125 u_int stop_after_jal;
126 extern u_char restore_candidate[512];
127 extern int cycle_count;
128
129 /* registers that may be allocated */
130 /* 1-31 gpr */
131#define HIREG 32 // hi
132#define LOREG 33 // lo
133#define FSREG 34 // FPU status (FCSR)
134#define CSREG 35 // Coprocessor status
135#define CCREG 36 // Cycle count
136#define INVCP 37 // Pointer to invalid_code
137#define TEMPREG 38
b9b61529 138#define FTEMP 38 // FPU/LDL/LDR temporary register
57871462 139#define PTEMP 39 // Prefetch temporary register
140#define TLREG 40 // TLB mapping offset
141#define RHASH 41 // Return address hash
142#define RHTBL 42 // Return address hash table address
143#define RTEMP 43 // JR/JALR address register
144#define MAXREG 43
145#define AGEN1 44 // Address generation temporary register
146#define AGEN2 45 // Address generation temporary register
147#define MGEN1 46 // Maptable address generation temporary register
148#define MGEN2 47 // Maptable address generation temporary register
149#define BTREG 48 // Branch target temporary register
150
151 /* instruction types */
152#define NOP 0 // No operation
153#define LOAD 1 // Load
154#define STORE 2 // Store
155#define LOADLR 3 // Unaligned load
156#define STORELR 4 // Unaligned store
157#define MOV 5 // Move
158#define ALU 6 // Arithmetic/logic
159#define MULTDIV 7 // Multiply/divide
160#define SHIFT 8 // Shift by register
161#define SHIFTIMM 9// Shift by immediate
162#define IMM16 10 // 16-bit immediate
163#define RJUMP 11 // Unconditional jump to register
164#define UJUMP 12 // Unconditional jump
165#define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
166#define SJUMP 14 // Conditional branch (regimm format)
167#define COP0 15 // Coprocessor 0
168#define COP1 16 // Coprocessor 1
169#define C1LS 17 // Coprocessor 1 load/store
170#define FJUMP 18 // Conditional branch (floating point)
171#define FLOAT 19 // Floating point unit
172#define FCONV 20 // Convert integer to float
173#define FCOMP 21 // Floating point compare (sets FSREG)
174#define SYSCALL 22// SYSCALL
175#define OTHER 23 // Other
176#define SPAN 24 // Branch/delay slot spans 2 pages
177#define NI 25 // Not implemented
7139f3c8 178#define HLECALL 26// PCSX fake opcodes for HLE
b9b61529 179#define COP2 27 // Coprocessor 2 move
180#define C2LS 28 // Coprocessor 2 load/store
181#define C2OP 29 // Coprocessor 2 operation
57871462 182
183 /* stubs */
184#define CC_STUB 1
185#define FP_STUB 2
186#define LOADB_STUB 3
187#define LOADH_STUB 4
188#define LOADW_STUB 5
189#define LOADD_STUB 6
190#define LOADBU_STUB 7
191#define LOADHU_STUB 8
192#define STOREB_STUB 9
193#define STOREH_STUB 10
194#define STOREW_STUB 11
195#define STORED_STUB 12
196#define STORELR_STUB 13
197#define INVCODE_STUB 14
198
199 /* branch codes */
200#define TAKEN 1
201#define NOTTAKEN 2
202#define NULLDS 3
203
204// asm linkage
205int new_recompile_block(int addr);
206void *get_addr_ht(u_int vaddr);
207void invalidate_block(u_int block);
208void invalidate_addr(u_int addr);
209void remove_hash(int vaddr);
210void jump_vaddr();
211void dyna_linker();
212void dyna_linker_ds();
213void verify_code();
214void verify_code_vm();
215void verify_code_ds();
216void cc_interrupt();
217void fp_exception();
218void fp_exception_ds();
219void jump_syscall();
7139f3c8 220void jump_syscall_hle();
57871462 221void jump_eret();
7139f3c8 222void jump_hlecall();
223void new_dyna_leave();
57871462 224
225// TLB
226void TLBWI_new();
227void TLBWR_new();
228void read_nomem_new();
229void read_nomemb_new();
230void read_nomemh_new();
231void read_nomemd_new();
232void write_nomem_new();
233void write_nomemb_new();
234void write_nomemh_new();
235void write_nomemd_new();
236void write_rdram_new();
237void write_rdramb_new();
238void write_rdramh_new();
239void write_rdramd_new();
240extern u_int memory_map[1048576];
241
242// Needed by assembler
243void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
244void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
245void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
246void load_all_regs(signed char i_regmap[]);
247void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
248void load_regs_entry(int t);
249void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
250
251int tracedebug=0;
252
253//#define DEBUG_CYCLE_COUNT 1
254
255void nullf() {}
256//#define assem_debug printf
257//#define inv_debug printf
258#define assem_debug nullf
259#define inv_debug nullf
260
94d23bb9 261static void tlb_hacks()
57871462 262{
94d23bb9 263#ifndef DISABLE_TLB
57871462 264 // Goldeneye hack
265 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
266 {
267 u_int addr;
268 int n;
269 switch (ROM_HEADER->Country_code&0xFF)
270 {
271 case 0x45: // U
272 addr=0x34b30;
273 break;
274 case 0x4A: // J
275 addr=0x34b70;
276 break;
277 case 0x50: // E
278 addr=0x329f0;
279 break;
280 default:
281 // Unknown country code
282 addr=0;
283 break;
284 }
285 u_int rom_addr=(u_int)rom;
286 #ifdef ROM_COPY
287 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
288 // in the lower 4G of memory to use this hack. Copy it if necessary.
289 if((void *)rom>(void *)0xffffffff) {
290 munmap(ROM_COPY, 67108864);
291 if(mmap(ROM_COPY, 12582912,
292 PROT_READ | PROT_WRITE,
293 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
294 -1, 0) <= 0) {printf("mmap() failed\n");}
295 memcpy(ROM_COPY,rom,12582912);
296 rom_addr=(u_int)ROM_COPY;
297 }
298 #endif
299 if(addr) {
300 for(n=0x7F000;n<0x80000;n++) {
301 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
302 }
303 }
304 }
94d23bb9 305#endif
57871462 306}
307
94d23bb9 308static u_int get_page(u_int vaddr)
57871462 309{
310 u_int page=(vaddr^0x80000000)>>12;
94d23bb9 311#ifndef DISABLE_TLB
57871462 312 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
94d23bb9 313#endif
57871462 314 if(page>2048) page=2048+(page&2047);
94d23bb9 315 return page;
316}
317
318static u_int get_vpage(u_int vaddr)
319{
320 u_int vpage=(vaddr^0x80000000)>>12;
321#ifndef DISABLE_TLB
57871462 322 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
94d23bb9 323#endif
57871462 324 if(vpage>2048) vpage=2048+(vpage&2047);
94d23bb9 325 return vpage;
326}
327
328// Get address from virtual address
329// This is called from the recompiled JR/JALR instructions
330void *get_addr(u_int vaddr)
331{
332 u_int page=get_page(vaddr);
333 u_int vpage=get_vpage(vaddr);
57871462 334 struct ll_entry *head;
335 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
336 head=jump_in[page];
337 while(head!=NULL) {
338 if(head->vaddr==vaddr&&head->reg32==0) {
339 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
340 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
341 ht_bin[3]=ht_bin[1];
342 ht_bin[2]=ht_bin[0];
343 ht_bin[1]=(int)head->addr;
344 ht_bin[0]=vaddr;
345 return head->addr;
346 }
347 head=head->next;
348 }
349 head=jump_dirty[vpage];
350 while(head!=NULL) {
351 if(head->vaddr==vaddr&&head->reg32==0) {
352 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
353 // Don't restore blocks which are about to expire from the cache
354 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
355 if(verify_dirty(head->addr)) {
356 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
357 invalid_code[vaddr>>12]=0;
358 memory_map[vaddr>>12]|=0x40000000;
359 if(vpage<2048) {
94d23bb9 360#ifndef DISABLE_TLB
57871462 361 if(tlb_LUT_r[vaddr>>12]) {
362 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
363 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
364 }
94d23bb9 365#endif
57871462 366 restore_candidate[vpage>>3]|=1<<(vpage&7);
367 }
368 else restore_candidate[page>>3]|=1<<(page&7);
369 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
370 if(ht_bin[0]==vaddr) {
371 ht_bin[1]=(int)head->addr; // Replace existing entry
372 }
373 else
374 {
375 ht_bin[3]=ht_bin[1];
376 ht_bin[2]=ht_bin[0];
377 ht_bin[1]=(int)head->addr;
378 ht_bin[0]=vaddr;
379 }
380 return head->addr;
381 }
382 }
383 head=head->next;
384 }
385 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
386 int r=new_recompile_block(vaddr);
387 if(r==0) return get_addr(vaddr);
388 // Execute in unmapped page, generate pagefault execption
389 Status|=2;
390 Cause=(vaddr<<31)|0x8;
391 EPC=(vaddr&1)?vaddr-5:vaddr;
392 BadVAddr=(vaddr&~1);
393 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
394 EntryHi=BadVAddr&0xFFFFE000;
395 return get_addr_ht(0x80000000);
396}
397// Look up address in hash table first
398void *get_addr_ht(u_int vaddr)
399{
400 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
401 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
402 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
403 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
404 return get_addr(vaddr);
405}
406
407void *get_addr_32(u_int vaddr,u_int flags)
408{
7139f3c8 409#ifdef FORCE32
410 return get_addr(vaddr);
411#endif
57871462 412 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
413 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
414 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
415 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
94d23bb9 416 u_int page=get_page(vaddr);
417 u_int vpage=get_vpage(vaddr);
57871462 418 struct ll_entry *head;
419 head=jump_in[page];
420 while(head!=NULL) {
421 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
422 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
423 if(head->reg32==0) {
424 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
425 if(ht_bin[0]==-1) {
426 ht_bin[1]=(int)head->addr;
427 ht_bin[0]=vaddr;
428 }else if(ht_bin[2]==-1) {
429 ht_bin[3]=(int)head->addr;
430 ht_bin[2]=vaddr;
431 }
432 //ht_bin[3]=ht_bin[1];
433 //ht_bin[2]=ht_bin[0];
434 //ht_bin[1]=(int)head->addr;
435 //ht_bin[0]=vaddr;
436 }
437 return head->addr;
438 }
439 head=head->next;
440 }
441 head=jump_dirty[vpage];
442 while(head!=NULL) {
443 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
444 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
445 // Don't restore blocks which are about to expire from the cache
446 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
447 if(verify_dirty(head->addr)) {
448 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
449 invalid_code[vaddr>>12]=0;
450 memory_map[vaddr>>12]|=0x40000000;
451 if(vpage<2048) {
94d23bb9 452#ifndef DISABLE_TLB
57871462 453 if(tlb_LUT_r[vaddr>>12]) {
454 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
455 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
456 }
94d23bb9 457#endif
57871462 458 restore_candidate[vpage>>3]|=1<<(vpage&7);
459 }
460 else restore_candidate[page>>3]|=1<<(page&7);
461 if(head->reg32==0) {
462 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
463 if(ht_bin[0]==-1) {
464 ht_bin[1]=(int)head->addr;
465 ht_bin[0]=vaddr;
466 }else if(ht_bin[2]==-1) {
467 ht_bin[3]=(int)head->addr;
468 ht_bin[2]=vaddr;
469 }
470 //ht_bin[3]=ht_bin[1];
471 //ht_bin[2]=ht_bin[0];
472 //ht_bin[1]=(int)head->addr;
473 //ht_bin[0]=vaddr;
474 }
475 return head->addr;
476 }
477 }
478 head=head->next;
479 }
480 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
481 int r=new_recompile_block(vaddr);
482 if(r==0) return get_addr(vaddr);
483 // Execute in unmapped page, generate pagefault execption
484 Status|=2;
485 Cause=(vaddr<<31)|0x8;
486 EPC=(vaddr&1)?vaddr-5:vaddr;
487 BadVAddr=(vaddr&~1);
488 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
489 EntryHi=BadVAddr&0xFFFFE000;
490 return get_addr_ht(0x80000000);
491}
492
493void clear_all_regs(signed char regmap[])
494{
495 int hr;
496 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
497}
498
499signed char get_reg(signed char regmap[],int r)
500{
501 int hr;
502 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
503 return -1;
504}
505
506// Find a register that is available for two consecutive cycles
507signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
508{
509 int hr;
510 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
511 return -1;
512}
513
514int count_free_regs(signed char regmap[])
515{
516 int count=0;
517 int hr;
518 for(hr=0;hr<HOST_REGS;hr++)
519 {
520 if(hr!=EXCLUDE_REG) {
521 if(regmap[hr]<0) count++;
522 }
523 }
524 return count;
525}
526
527void dirty_reg(struct regstat *cur,signed char reg)
528{
529 int hr;
530 if(!reg) return;
531 for (hr=0;hr<HOST_REGS;hr++) {
532 if((cur->regmap[hr]&63)==reg) {
533 cur->dirty|=1<<hr;
534 }
535 }
536}
537
538// If we dirty the lower half of a 64 bit register which is now being
539// sign-extended, we need to dump the upper half.
540// Note: Do this only after completion of the instruction, because
541// some instructions may need to read the full 64-bit value even if
542// overwriting it (eg SLTI, DSRA32).
543static void flush_dirty_uppers(struct regstat *cur)
544{
545 int hr,reg;
546 for (hr=0;hr<HOST_REGS;hr++) {
547 if((cur->dirty>>hr)&1) {
548 reg=cur->regmap[hr];
549 if(reg>=64)
550 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
551 }
552 }
553}
554
555void set_const(struct regstat *cur,signed char reg,uint64_t value)
556{
557 int hr;
558 if(!reg) return;
559 for (hr=0;hr<HOST_REGS;hr++) {
560 if(cur->regmap[hr]==reg) {
561 cur->isconst|=1<<hr;
562 cur->constmap[hr]=value;
563 }
564 else if((cur->regmap[hr]^64)==reg) {
565 cur->isconst|=1<<hr;
566 cur->constmap[hr]=value>>32;
567 }
568 }
569}
570
571void clear_const(struct regstat *cur,signed char reg)
572{
573 int hr;
574 if(!reg) return;
575 for (hr=0;hr<HOST_REGS;hr++) {
576 if((cur->regmap[hr]&63)==reg) {
577 cur->isconst&=~(1<<hr);
578 }
579 }
580}
581
582int is_const(struct regstat *cur,signed char reg)
583{
584 int hr;
585 if(!reg) return 1;
586 for (hr=0;hr<HOST_REGS;hr++) {
587 if((cur->regmap[hr]&63)==reg) {
588 return (cur->isconst>>hr)&1;
589 }
590 }
591 return 0;
592}
593uint64_t get_const(struct regstat *cur,signed char reg)
594{
595 int hr;
596 if(!reg) return 0;
597 for (hr=0;hr<HOST_REGS;hr++) {
598 if(cur->regmap[hr]==reg) {
599 return cur->constmap[hr];
600 }
601 }
602 printf("Unknown constant in r%d\n",reg);
603 exit(1);
604}
605
606// Least soon needed registers
607// Look at the next ten instructions and see which registers
608// will be used. Try not to reallocate these.
609void lsn(u_char hsn[], int i, int *preferred_reg)
610{
611 int j;
612 int b=-1;
613 for(j=0;j<9;j++)
614 {
615 if(i+j>=slen) {
616 j=slen-i-1;
617 break;
618 }
619 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
620 {
621 // Don't go past an unconditonal jump
622 j++;
623 break;
624 }
625 }
626 for(;j>=0;j--)
627 {
628 if(rs1[i+j]) hsn[rs1[i+j]]=j;
629 if(rs2[i+j]) hsn[rs2[i+j]]=j;
630 if(rt1[i+j]) hsn[rt1[i+j]]=j;
631 if(rt2[i+j]) hsn[rt2[i+j]]=j;
632 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
633 // Stores can allocate zero
634 hsn[rs1[i+j]]=j;
635 hsn[rs2[i+j]]=j;
636 }
637 // On some architectures stores need invc_ptr
638 #if defined(HOST_IMM8)
b9b61529 639 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
57871462 640 hsn[INVCP]=j;
641 }
642 #endif
643 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
644 {
645 hsn[CCREG]=j;
646 b=j;
647 }
648 }
649 if(b>=0)
650 {
651 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
652 {
653 // Follow first branch
654 int t=(ba[i+b]-start)>>2;
655 j=7-b;if(t+j>=slen) j=slen-t-1;
656 for(;j>=0;j--)
657 {
658 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
659 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
660 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
661 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
662 }
663 }
664 // TODO: preferred register based on backward branch
665 }
666 // Delay slot should preferably not overwrite branch conditions or cycle count
667 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
668 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
669 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
670 hsn[CCREG]=1;
671 // ...or hash tables
672 hsn[RHASH]=1;
673 hsn[RHTBL]=1;
674 }
675 // Coprocessor load/store needs FTEMP, even if not declared
b9b61529 676 if(itype[i]==C1LS||itype[i]==C2LS) {
57871462 677 hsn[FTEMP]=0;
678 }
679 // Load L/R also uses FTEMP as a temporary register
680 if(itype[i]==LOADLR) {
681 hsn[FTEMP]=0;
682 }
683 // Also 64-bit SDL/SDR
684 if(opcode[i]==0x2c||opcode[i]==0x2d) {
685 hsn[FTEMP]=0;
686 }
687 // Don't remove the TLB registers either
b9b61529 688 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
57871462 689 hsn[TLREG]=0;
690 }
691 // Don't remove the miniht registers
692 if(itype[i]==UJUMP||itype[i]==RJUMP)
693 {
694 hsn[RHASH]=0;
695 hsn[RHTBL]=0;
696 }
697}
698
699// We only want to allocate registers if we're going to use them again soon
700int needed_again(int r, int i)
701{
702 int j;
703 int b=-1;
704 int rn=10;
705 int hr;
706 u_char hsn[MAXREG+1];
707 int preferred_reg;
708
709 memset(hsn,10,sizeof(hsn));
710 lsn(hsn,i,&preferred_reg);
711
712 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
713 {
714 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
715 return 0; // Don't need any registers if exiting the block
716 }
717 for(j=0;j<9;j++)
718 {
719 if(i+j>=slen) {
720 j=slen-i-1;
721 break;
722 }
723 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
724 {
725 // Don't go past an unconditonal jump
726 j++;
727 break;
728 }
7139f3c8 729 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||((source[i+j]&0xfc00003f)==0x0d))
57871462 730 {
731 break;
732 }
733 }
734 for(;j>=1;j--)
735 {
736 if(rs1[i+j]==r) rn=j;
737 if(rs2[i+j]==r) rn=j;
738 if((unneeded_reg[i+j]>>r)&1) rn=10;
739 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
740 {
741 b=j;
742 }
743 }
744 /*
745 if(b>=0)
746 {
747 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
748 {
749 // Follow first branch
750 int o=rn;
751 int t=(ba[i+b]-start)>>2;
752 j=7-b;if(t+j>=slen) j=slen-t-1;
753 for(;j>=0;j--)
754 {
755 if(!((unneeded_reg[t+j]>>r)&1)) {
756 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
757 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
758 }
759 else rn=o;
760 }
761 }
762 }*/
763 for(hr=0;hr<HOST_REGS;hr++) {
764 if(hr!=EXCLUDE_REG) {
765 if(rn<hsn[hr]) return 1;
766 }
767 }
768 return 0;
769}
770
771// Try to match register allocations at the end of a loop with those
772// at the beginning
773int loop_reg(int i, int r, int hr)
774{
775 int j,k;
776 for(j=0;j<9;j++)
777 {
778 if(i+j>=slen) {
779 j=slen-i-1;
780 break;
781 }
782 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
783 {
784 // Don't go past an unconditonal jump
785 j++;
786 break;
787 }
788 }
789 k=0;
790 if(i>0){
791 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
792 k--;
793 }
794 for(;k<j;k++)
795 {
796 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
797 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
798 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
799 {
800 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
801 {
802 int t=(ba[i+k]-start)>>2;
803 int reg=get_reg(regs[t].regmap_entry,r);
804 if(reg>=0) return reg;
805 //reg=get_reg(regs[t+1].regmap_entry,r);
806 //if(reg>=0) return reg;
807 }
808 }
809 }
810 return hr;
811}
812
813
814// Allocate every register, preserving source/target regs
815void alloc_all(struct regstat *cur,int i)
816{
817 int hr;
818
819 for(hr=0;hr<HOST_REGS;hr++) {
820 if(hr!=EXCLUDE_REG) {
821 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
822 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
823 {
824 cur->regmap[hr]=-1;
825 cur->dirty&=~(1<<hr);
826 }
827 // Don't need zeros
828 if((cur->regmap[hr]&63)==0)
829 {
830 cur->regmap[hr]=-1;
831 cur->dirty&=~(1<<hr);
832 }
833 }
834 }
835}
836
837
838void div64(int64_t dividend,int64_t divisor)
839{
840 lo=dividend/divisor;
841 hi=dividend%divisor;
842 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
843 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
844}
845void divu64(uint64_t dividend,uint64_t divisor)
846{
847 lo=dividend/divisor;
848 hi=dividend%divisor;
849 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
850 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
851}
852
853void mult64(uint64_t m1,uint64_t m2)
854{
855 unsigned long long int op1, op2, op3, op4;
856 unsigned long long int result1, result2, result3, result4;
857 unsigned long long int temp1, temp2, temp3, temp4;
858 int sign = 0;
859
860 if (m1 < 0)
861 {
862 op2 = -m1;
863 sign = 1 - sign;
864 }
865 else op2 = m1;
866 if (m2 < 0)
867 {
868 op4 = -m2;
869 sign = 1 - sign;
870 }
871 else op4 = m2;
872
873 op1 = op2 & 0xFFFFFFFF;
874 op2 = (op2 >> 32) & 0xFFFFFFFF;
875 op3 = op4 & 0xFFFFFFFF;
876 op4 = (op4 >> 32) & 0xFFFFFFFF;
877
878 temp1 = op1 * op3;
879 temp2 = (temp1 >> 32) + op1 * op4;
880 temp3 = op2 * op3;
881 temp4 = (temp3 >> 32) + op2 * op4;
882
883 result1 = temp1 & 0xFFFFFFFF;
884 result2 = temp2 + (temp3 & 0xFFFFFFFF);
885 result3 = (result2 >> 32) + temp4;
886 result4 = (result3 >> 32);
887
888 lo = result1 | (result2 << 32);
889 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
890 if (sign)
891 {
892 hi = ~hi;
893 if (!lo) hi++;
894 else lo = ~lo + 1;
895 }
896}
897
898void multu64(uint64_t m1,uint64_t m2)
899{
900 unsigned long long int op1, op2, op3, op4;
901 unsigned long long int result1, result2, result3, result4;
902 unsigned long long int temp1, temp2, temp3, temp4;
903
904 op1 = m1 & 0xFFFFFFFF;
905 op2 = (m1 >> 32) & 0xFFFFFFFF;
906 op3 = m2 & 0xFFFFFFFF;
907 op4 = (m2 >> 32) & 0xFFFFFFFF;
908
909 temp1 = op1 * op3;
910 temp2 = (temp1 >> 32) + op1 * op4;
911 temp3 = op2 * op3;
912 temp4 = (temp3 >> 32) + op2 * op4;
913
914 result1 = temp1 & 0xFFFFFFFF;
915 result2 = temp2 + (temp3 & 0xFFFFFFFF);
916 result3 = (result2 >> 32) + temp4;
917 result4 = (result3 >> 32);
918
919 lo = result1 | (result2 << 32);
920 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
921
922 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
923 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
924}
925
926uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
927{
928 if(bits) {
929 original<<=64-bits;
930 original>>=64-bits;
931 loaded<<=bits;
932 original|=loaded;
933 }
934 else original=loaded;
935 return original;
936}
937uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
938{
939 if(bits^56) {
940 original>>=64-(bits^56);
941 original<<=64-(bits^56);
942 loaded>>=bits^56;
943 original|=loaded;
944 }
945 else original=loaded;
946 return original;
947}
948
949#ifdef __i386__
950#include "assem_x86.c"
951#endif
952#ifdef __x86_64__
953#include "assem_x64.c"
954#endif
955#ifdef __arm__
956#include "assem_arm.c"
957#endif
958
959// Add virtual address mapping to linked list
960void ll_add(struct ll_entry **head,int vaddr,void *addr)
961{
962 struct ll_entry *new_entry;
963 new_entry=malloc(sizeof(struct ll_entry));
964 assert(new_entry!=NULL);
965 new_entry->vaddr=vaddr;
966 new_entry->reg32=0;
967 new_entry->addr=addr;
968 new_entry->next=*head;
969 *head=new_entry;
970}
971
972// Add virtual address mapping for 32-bit compiled block
973void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
974{
7139f3c8 975 ll_add(head,vaddr,addr);
976#ifndef FORCE32
977 (*head)->reg32=reg32;
978#endif
57871462 979}
980
981// Check if an address is already compiled
982// but don't return addresses which are about to expire from the cache
983void *check_addr(u_int vaddr)
984{
985 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
986 if(ht_bin[0]==vaddr) {
987 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
988 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
989 }
990 if(ht_bin[2]==vaddr) {
991 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
992 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
993 }
94d23bb9 994 u_int page=get_page(vaddr);
57871462 995 struct ll_entry *head;
996 head=jump_in[page];
997 while(head!=NULL) {
998 if(head->vaddr==vaddr&&head->reg32==0) {
999 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1000 // Update existing entry with current address
1001 if(ht_bin[0]==vaddr) {
1002 ht_bin[1]=(int)head->addr;
1003 return head->addr;
1004 }
1005 if(ht_bin[2]==vaddr) {
1006 ht_bin[3]=(int)head->addr;
1007 return head->addr;
1008 }
1009 // Insert into hash table with low priority.
1010 // Don't evict existing entries, as they are probably
1011 // addresses that are being accessed frequently.
1012 if(ht_bin[0]==-1) {
1013 ht_bin[1]=(int)head->addr;
1014 ht_bin[0]=vaddr;
1015 }else if(ht_bin[2]==-1) {
1016 ht_bin[3]=(int)head->addr;
1017 ht_bin[2]=vaddr;
1018 }
1019 return head->addr;
1020 }
1021 }
1022 head=head->next;
1023 }
1024 return 0;
1025}
1026
1027void remove_hash(int vaddr)
1028{
1029 //printf("remove hash: %x\n",vaddr);
1030 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1031 if(ht_bin[2]==vaddr) {
1032 ht_bin[2]=ht_bin[3]=-1;
1033 }
1034 if(ht_bin[0]==vaddr) {
1035 ht_bin[0]=ht_bin[2];
1036 ht_bin[1]=ht_bin[3];
1037 ht_bin[2]=ht_bin[3]=-1;
1038 }
1039}
1040
1041void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1042{
1043 struct ll_entry *next;
1044 while(*head) {
1045 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1046 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1047 {
1048 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1049 remove_hash((*head)->vaddr);
1050 next=(*head)->next;
1051 free(*head);
1052 *head=next;
1053 }
1054 else
1055 {
1056 head=&((*head)->next);
1057 }
1058 }
1059}
1060
1061// Remove all entries from linked list
1062void ll_clear(struct ll_entry **head)
1063{
1064 struct ll_entry *cur;
1065 struct ll_entry *next;
1066 if(cur=*head) {
1067 *head=0;
1068 while(cur) {
1069 next=cur->next;
1070 free(cur);
1071 cur=next;
1072 }
1073 }
1074}
1075
1076// Dereference the pointers and remove if it matches
1077void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1078{
1079 while(head) {
1080 int ptr=get_pointer(head->addr);
1081 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1082 if(((ptr>>shift)==(addr>>shift)) ||
1083 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1084 {
1085 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1086 kill_pointer(head->addr);
1087 }
1088 head=head->next;
1089 }
1090}
1091
1092// This is called when we write to a compiled block (see do_invstub)
1093int invalidate_page(u_int page)
1094{
1095 int modified=0;
1096 struct ll_entry *head;
1097 struct ll_entry *next;
1098 head=jump_in[page];
1099 jump_in[page]=0;
1100 while(head!=NULL) {
1101 inv_debug("INVALIDATE: %x\n",head->vaddr);
1102 remove_hash(head->vaddr);
1103 next=head->next;
1104 free(head);
1105 head=next;
1106 }
1107 head=jump_out[page];
1108 jump_out[page]=0;
1109 while(head!=NULL) {
1110 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1111 kill_pointer(head->addr);
1112 modified=1;
1113 next=head->next;
1114 free(head);
1115 head=next;
1116 }
1117 return modified;
1118}
1119void invalidate_block(u_int block)
1120{
1121 int modified;
94d23bb9 1122 u_int page=get_page(block<<12);
1123 u_int vpage=get_vpage(block<<12);
57871462 1124 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1125 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1126 u_int first,last;
1127 first=last=page;
1128 struct ll_entry *head;
1129 head=jump_dirty[vpage];
1130 //printf("page=%d vpage=%d\n",page,vpage);
1131 while(head!=NULL) {
1132 u_int start,end;
1133 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1134 get_bounds((int)head->addr,&start,&end);
1135 //printf("start: %x end: %x\n",start,end);
1136 if(page<2048&&start>=0x80000000&&end<0x80800000) {
1137 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1138 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1139 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1140 }
1141 }
90ae6d4e 1142#ifndef DISABLE_TLB
57871462 1143 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1144 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1145 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1146 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1147 }
1148 }
90ae6d4e 1149#endif
57871462 1150 }
1151 head=head->next;
1152 }
1153 //printf("first=%d last=%d\n",first,last);
1154 modified=invalidate_page(page);
1155 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1156 assert(last<page+5);
1157 // Invalidate the adjacent pages if a block crosses a 4K boundary
1158 while(first<page) {
1159 invalidate_page(first);
1160 first++;
1161 }
1162 for(first=page+1;first<last;first++) {
1163 invalidate_page(first);
1164 }
1165
1166 // Don't trap writes
1167 invalid_code[block]=1;
94d23bb9 1168#ifndef DISABLE_TLB
57871462 1169 // If there is a valid TLB entry for this page, remove write protect
1170 if(tlb_LUT_w[block]) {
1171 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1172 // CHECK: Is this right?
1173 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1174 u_int real_block=tlb_LUT_w[block]>>12;
1175 invalid_code[real_block]=1;
1176 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1177 }
1178 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
94d23bb9 1179#endif
57871462 1180 #ifdef __arm__
1181 if(modified)
1182 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1183 #endif
1184 #ifdef USE_MINI_HT
1185 memset(mini_ht,-1,sizeof(mini_ht));
1186 #endif
1187}
1188void invalidate_addr(u_int addr)
1189{
1190 invalidate_block(addr>>12);
1191}
1192void invalidate_all_pages()
1193{
1194 u_int page,n;
1195 for(page=0;page<4096;page++)
1196 invalidate_page(page);
1197 for(page=0;page<1048576;page++)
1198 if(!invalid_code[page]) {
1199 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1200 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1201 }
1202 #ifdef __arm__
1203 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1204 #endif
1205 #ifdef USE_MINI_HT
1206 memset(mini_ht,-1,sizeof(mini_ht));
1207 #endif
94d23bb9 1208 #ifndef DISABLE_TLB
57871462 1209 // TLB
1210 for(page=0;page<0x100000;page++) {
1211 if(tlb_LUT_r[page]) {
1212 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1213 if(!tlb_LUT_w[page]||!invalid_code[page])
1214 memory_map[page]|=0x40000000; // Write protect
1215 }
1216 else memory_map[page]=-1;
1217 if(page==0x80000) page=0xC0000;
1218 }
1219 tlb_hacks();
94d23bb9 1220 #endif
57871462 1221}
1222
1223// Add an entry to jump_out after making a link
1224void add_link(u_int vaddr,void *src)
1225{
94d23bb9 1226 u_int page=get_page(vaddr);
57871462 1227 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1228 ll_add(jump_out+page,vaddr,src);
1229 //int ptr=get_pointer(src);
1230 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1231}
1232
1233// If a code block was found to be unmodified (bit was set in
1234// restore_candidate) and it remains unmodified (bit is clear
1235// in invalid_code) then move the entries for that 4K page from
1236// the dirty list to the clean list.
1237void clean_blocks(u_int page)
1238{
1239 struct ll_entry *head;
1240 inv_debug("INV: clean_blocks page=%d\n",page);
1241 head=jump_dirty[page];
1242 while(head!=NULL) {
1243 if(!invalid_code[head->vaddr>>12]) {
1244 // Don't restore blocks which are about to expire from the cache
1245 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1246 u_int start,end;
1247 if(verify_dirty((int)head->addr)) {
1248 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1249 u_int i;
1250 u_int inv=0;
1251 get_bounds((int)head->addr,&start,&end);
1252 if(start-(u_int)rdram<0x800000) {
1253 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1254 inv|=invalid_code[i];
1255 }
1256 }
1257 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1258 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1259 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1260 if(addr<start||addr>=end) inv=1;
1261 }
1262 else if((signed int)head->vaddr>=(signed int)0x80800000) {
1263 inv=1;
1264 }
1265 if(!inv) {
1266 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1267 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1268 u_int ppage=page;
94d23bb9 1269#ifndef DISABLE_TLB
57871462 1270 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
94d23bb9 1271#endif
57871462 1272 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1273 //printf("page=%x, addr=%x\n",page,head->vaddr);
1274 //assert(head->vaddr>>12==(page|0x80000));
1275 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1276 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1277 if(!head->reg32) {
1278 if(ht_bin[0]==head->vaddr) {
1279 ht_bin[1]=(int)clean_addr; // Replace existing entry
1280 }
1281 if(ht_bin[2]==head->vaddr) {
1282 ht_bin[3]=(int)clean_addr; // Replace existing entry
1283 }
1284 }
1285 }
1286 }
1287 }
1288 }
1289 }
1290 head=head->next;
1291 }
1292}
1293
1294
1295void mov_alloc(struct regstat *current,int i)
1296{
1297 // Note: Don't need to actually alloc the source registers
1298 if((~current->is32>>rs1[i])&1) {
1299 //alloc_reg64(current,i,rs1[i]);
1300 alloc_reg64(current,i,rt1[i]);
1301 current->is32&=~(1LL<<rt1[i]);
1302 } else {
1303 //alloc_reg(current,i,rs1[i]);
1304 alloc_reg(current,i,rt1[i]);
1305 current->is32|=(1LL<<rt1[i]);
1306 }
1307 clear_const(current,rs1[i]);
1308 clear_const(current,rt1[i]);
1309 dirty_reg(current,rt1[i]);
1310}
1311
1312void shiftimm_alloc(struct regstat *current,int i)
1313{
1314 clear_const(current,rs1[i]);
1315 clear_const(current,rt1[i]);
1316 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1317 {
1318 if(rt1[i]) {
1319 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1320 else lt1[i]=rs1[i];
1321 alloc_reg(current,i,rt1[i]);
1322 current->is32|=1LL<<rt1[i];
1323 dirty_reg(current,rt1[i]);
1324 }
1325 }
1326 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1327 {
1328 if(rt1[i]) {
1329 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1330 alloc_reg64(current,i,rt1[i]);
1331 current->is32&=~(1LL<<rt1[i]);
1332 dirty_reg(current,rt1[i]);
1333 }
1334 }
1335 if(opcode2[i]==0x3c) // DSLL32
1336 {
1337 if(rt1[i]) {
1338 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1339 alloc_reg64(current,i,rt1[i]);
1340 current->is32&=~(1LL<<rt1[i]);
1341 dirty_reg(current,rt1[i]);
1342 }
1343 }
1344 if(opcode2[i]==0x3e) // DSRL32
1345 {
1346 if(rt1[i]) {
1347 alloc_reg64(current,i,rs1[i]);
1348 if(imm[i]==32) {
1349 alloc_reg64(current,i,rt1[i]);
1350 current->is32&=~(1LL<<rt1[i]);
1351 } else {
1352 alloc_reg(current,i,rt1[i]);
1353 current->is32|=1LL<<rt1[i];
1354 }
1355 dirty_reg(current,rt1[i]);
1356 }
1357 }
1358 if(opcode2[i]==0x3f) // DSRA32
1359 {
1360 if(rt1[i]) {
1361 alloc_reg64(current,i,rs1[i]);
1362 alloc_reg(current,i,rt1[i]);
1363 current->is32|=1LL<<rt1[i];
1364 dirty_reg(current,rt1[i]);
1365 }
1366 }
1367}
1368
1369void shift_alloc(struct regstat *current,int i)
1370{
1371 if(rt1[i]) {
1372 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1373 {
1374 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1375 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1376 alloc_reg(current,i,rt1[i]);
1377 if(rt1[i]==rs2[i]) alloc_reg_temp(current,i,-1);
1378 current->is32|=1LL<<rt1[i];
1379 } else { // DSLLV/DSRLV/DSRAV
1380 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1381 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1382 alloc_reg64(current,i,rt1[i]);
1383 current->is32&=~(1LL<<rt1[i]);
1384 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1385 alloc_reg_temp(current,i,-1);
1386 }
1387 clear_const(current,rs1[i]);
1388 clear_const(current,rs2[i]);
1389 clear_const(current,rt1[i]);
1390 dirty_reg(current,rt1[i]);
1391 }
1392}
1393
1394void alu_alloc(struct regstat *current,int i)
1395{
1396 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1397 if(rt1[i]) {
1398 if(rs1[i]&&rs2[i]) {
1399 alloc_reg(current,i,rs1[i]);
1400 alloc_reg(current,i,rs2[i]);
1401 }
1402 else {
1403 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1404 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1405 }
1406 alloc_reg(current,i,rt1[i]);
1407 }
1408 current->is32|=1LL<<rt1[i];
1409 }
1410 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1411 if(rt1[i]) {
1412 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1413 {
1414 alloc_reg64(current,i,rs1[i]);
1415 alloc_reg64(current,i,rs2[i]);
1416 alloc_reg(current,i,rt1[i]);
1417 } else {
1418 alloc_reg(current,i,rs1[i]);
1419 alloc_reg(current,i,rs2[i]);
1420 alloc_reg(current,i,rt1[i]);
1421 }
1422 }
1423 current->is32|=1LL<<rt1[i];
1424 }
1425 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1426 if(rt1[i]) {
1427 if(rs1[i]&&rs2[i]) {
1428 alloc_reg(current,i,rs1[i]);
1429 alloc_reg(current,i,rs2[i]);
1430 }
1431 else
1432 {
1433 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1434 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1435 }
1436 alloc_reg(current,i,rt1[i]);
1437 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1438 {
1439 if(!((current->uu>>rt1[i])&1)) {
1440 alloc_reg64(current,i,rt1[i]);
1441 }
1442 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1443 if(rs1[i]&&rs2[i]) {
1444 alloc_reg64(current,i,rs1[i]);
1445 alloc_reg64(current,i,rs2[i]);
1446 }
1447 else
1448 {
1449 // Is is really worth it to keep 64-bit values in registers?
1450 #ifdef NATIVE_64BIT
1451 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1452 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1453 #endif
1454 }
1455 }
1456 current->is32&=~(1LL<<rt1[i]);
1457 } else {
1458 current->is32|=1LL<<rt1[i];
1459 }
1460 }
1461 }
1462 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1463 if(rt1[i]) {
1464 if(rs1[i]&&rs2[i]) {
1465 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1466 alloc_reg64(current,i,rs1[i]);
1467 alloc_reg64(current,i,rs2[i]);
1468 alloc_reg64(current,i,rt1[i]);
1469 } else {
1470 alloc_reg(current,i,rs1[i]);
1471 alloc_reg(current,i,rs2[i]);
1472 alloc_reg(current,i,rt1[i]);
1473 }
1474 }
1475 else {
1476 alloc_reg(current,i,rt1[i]);
1477 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1478 // DADD used as move, or zeroing
1479 // If we have a 64-bit source, then make the target 64 bits too
1480 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1481 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1482 alloc_reg64(current,i,rt1[i]);
1483 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1484 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1485 alloc_reg64(current,i,rt1[i]);
1486 }
1487 if(opcode2[i]>=0x2e&&rs2[i]) {
1488 // DSUB used as negation - 64-bit result
1489 // If we have a 32-bit register, extend it to 64 bits
1490 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1491 alloc_reg64(current,i,rt1[i]);
1492 }
1493 }
1494 }
1495 if(rs1[i]&&rs2[i]) {
1496 current->is32&=~(1LL<<rt1[i]);
1497 } else if(rs1[i]) {
1498 current->is32&=~(1LL<<rt1[i]);
1499 if((current->is32>>rs1[i])&1)
1500 current->is32|=1LL<<rt1[i];
1501 } else if(rs2[i]) {
1502 current->is32&=~(1LL<<rt1[i]);
1503 if((current->is32>>rs2[i])&1)
1504 current->is32|=1LL<<rt1[i];
1505 } else {
1506 current->is32|=1LL<<rt1[i];
1507 }
1508 }
1509 }
1510 clear_const(current,rs1[i]);
1511 clear_const(current,rs2[i]);
1512 clear_const(current,rt1[i]);
1513 dirty_reg(current,rt1[i]);
1514}
1515
1516void imm16_alloc(struct regstat *current,int i)
1517{
1518 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1519 else lt1[i]=rs1[i];
1520 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1521 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1522 current->is32&=~(1LL<<rt1[i]);
1523 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1524 // TODO: Could preserve the 32-bit flag if the immediate is zero
1525 alloc_reg64(current,i,rt1[i]);
1526 alloc_reg64(current,i,rs1[i]);
1527 }
1528 clear_const(current,rs1[i]);
1529 clear_const(current,rt1[i]);
1530 }
1531 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1532 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1533 current->is32|=1LL<<rt1[i];
1534 clear_const(current,rs1[i]);
1535 clear_const(current,rt1[i]);
1536 }
1537 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1538 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1539 if(rs1[i]!=rt1[i]) {
1540 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1541 alloc_reg64(current,i,rt1[i]);
1542 current->is32&=~(1LL<<rt1[i]);
1543 }
1544 }
1545 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1546 if(is_const(current,rs1[i])) {
1547 int v=get_const(current,rs1[i]);
1548 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1549 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1550 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1551 }
1552 else clear_const(current,rt1[i]);
1553 }
1554 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1555 if(is_const(current,rs1[i])) {
1556 int v=get_const(current,rs1[i]);
1557 set_const(current,rt1[i],v+imm[i]);
1558 }
1559 else clear_const(current,rt1[i]);
1560 current->is32|=1LL<<rt1[i];
1561 }
1562 else {
1563 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1564 current->is32|=1LL<<rt1[i];
1565 }
1566 dirty_reg(current,rt1[i]);
1567}
1568
1569void load_alloc(struct regstat *current,int i)
1570{
1571 clear_const(current,rt1[i]);
1572 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1573 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1574 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1575 if(rt1[i]) {
1576 alloc_reg(current,i,rt1[i]);
1577 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1578 {
1579 current->is32&=~(1LL<<rt1[i]);
1580 alloc_reg64(current,i,rt1[i]);
1581 }
1582 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1583 {
1584 current->is32&=~(1LL<<rt1[i]);
1585 alloc_reg64(current,i,rt1[i]);
1586 alloc_all(current,i);
1587 alloc_reg64(current,i,FTEMP);
1588 }
1589 else current->is32|=1LL<<rt1[i];
1590 dirty_reg(current,rt1[i]);
1591 // If using TLB, need a register for pointer to the mapping table
1592 if(using_tlb) alloc_reg(current,i,TLREG);
1593 // LWL/LWR need a temporary register for the old value
1594 if(opcode[i]==0x22||opcode[i]==0x26)
1595 {
1596 alloc_reg(current,i,FTEMP);
1597 alloc_reg_temp(current,i,-1);
1598 }
1599 }
1600 else
1601 {
1602 // Load to r0 (dummy load)
1603 // but we still need a register to calculate the address
1604 alloc_reg_temp(current,i,-1);
1605 }
1606}
1607
1608void store_alloc(struct regstat *current,int i)
1609{
1610 clear_const(current,rs2[i]);
1611 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1612 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1613 alloc_reg(current,i,rs2[i]);
1614 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1615 alloc_reg64(current,i,rs2[i]);
1616 if(rs2[i]) alloc_reg(current,i,FTEMP);
1617 }
1618 // If using TLB, need a register for pointer to the mapping table
1619 if(using_tlb) alloc_reg(current,i,TLREG);
1620 #if defined(HOST_IMM8)
1621 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1622 else alloc_reg(current,i,INVCP);
1623 #endif
1624 if(opcode[i]==0x2c||opcode[i]==0x2d) { // 64-bit SDL/SDR
1625 alloc_reg(current,i,FTEMP);
1626 }
1627 // We need a temporary register for address generation
1628 alloc_reg_temp(current,i,-1);
1629}
1630
1631void c1ls_alloc(struct regstat *current,int i)
1632{
1633 //clear_const(current,rs1[i]); // FIXME
1634 clear_const(current,rt1[i]);
1635 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1636 alloc_reg(current,i,CSREG); // Status
1637 alloc_reg(current,i,FTEMP);
1638 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1639 alloc_reg64(current,i,FTEMP);
1640 }
1641 // If using TLB, need a register for pointer to the mapping table
1642 if(using_tlb) alloc_reg(current,i,TLREG);
1643 #if defined(HOST_IMM8)
1644 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1645 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1646 alloc_reg(current,i,INVCP);
1647 #endif
1648 // We need a temporary register for address generation
1649 alloc_reg_temp(current,i,-1);
1650}
1651
b9b61529 1652void c2ls_alloc(struct regstat *current,int i)
1653{
1654 clear_const(current,rt1[i]);
1655 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1656 alloc_reg(current,i,FTEMP);
1657 // If using TLB, need a register for pointer to the mapping table
1658 if(using_tlb) alloc_reg(current,i,TLREG);
1659 #if defined(HOST_IMM8)
1660 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1661 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1662 alloc_reg(current,i,INVCP);
1663 #endif
1664 // We need a temporary register for address generation
1665 alloc_reg_temp(current,i,-1);
1666}
1667
57871462 1668#ifndef multdiv_alloc
1669void multdiv_alloc(struct regstat *current,int i)
1670{
1671 // case 0x18: MULT
1672 // case 0x19: MULTU
1673 // case 0x1A: DIV
1674 // case 0x1B: DIVU
1675 // case 0x1C: DMULT
1676 // case 0x1D: DMULTU
1677 // case 0x1E: DDIV
1678 // case 0x1F: DDIVU
1679 clear_const(current,rs1[i]);
1680 clear_const(current,rs2[i]);
1681 if(rs1[i]&&rs2[i])
1682 {
1683 if((opcode2[i]&4)==0) // 32-bit
1684 {
1685 current->u&=~(1LL<<HIREG);
1686 current->u&=~(1LL<<LOREG);
1687 alloc_reg(current,i,HIREG);
1688 alloc_reg(current,i,LOREG);
1689 alloc_reg(current,i,rs1[i]);
1690 alloc_reg(current,i,rs2[i]);
1691 current->is32|=1LL<<HIREG;
1692 current->is32|=1LL<<LOREG;
1693 dirty_reg(current,HIREG);
1694 dirty_reg(current,LOREG);
1695 }
1696 else // 64-bit
1697 {
1698 current->u&=~(1LL<<HIREG);
1699 current->u&=~(1LL<<LOREG);
1700 current->uu&=~(1LL<<HIREG);
1701 current->uu&=~(1LL<<LOREG);
1702 alloc_reg64(current,i,HIREG);
1703 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1704 alloc_reg64(current,i,rs1[i]);
1705 alloc_reg64(current,i,rs2[i]);
1706 alloc_all(current,i);
1707 current->is32&=~(1LL<<HIREG);
1708 current->is32&=~(1LL<<LOREG);
1709 dirty_reg(current,HIREG);
1710 dirty_reg(current,LOREG);
1711 }
1712 }
1713 else
1714 {
1715 // Multiply by zero is zero.
1716 // MIPS does not have a divide by zero exception.
1717 // The result is undefined, we return zero.
1718 alloc_reg(current,i,HIREG);
1719 alloc_reg(current,i,LOREG);
1720 current->is32|=1LL<<HIREG;
1721 current->is32|=1LL<<LOREG;
1722 dirty_reg(current,HIREG);
1723 dirty_reg(current,LOREG);
1724 }
1725}
1726#endif
1727
1728void cop0_alloc(struct regstat *current,int i)
1729{
1730 if(opcode2[i]==0) // MFC0
1731 {
1732 if(rt1[i]) {
1733 clear_const(current,rt1[i]);
1734 alloc_all(current,i);
1735 alloc_reg(current,i,rt1[i]);
1736 current->is32|=1LL<<rt1[i];
1737 dirty_reg(current,rt1[i]);
1738 }
1739 }
1740 else if(opcode2[i]==4) // MTC0
1741 {
1742 if(rs1[i]){
1743 clear_const(current,rs1[i]);
1744 alloc_reg(current,i,rs1[i]);
1745 alloc_all(current,i);
1746 }
1747 else {
1748 alloc_all(current,i); // FIXME: Keep r0
1749 current->u&=~1LL;
1750 alloc_reg(current,i,0);
1751 }
1752 }
1753 else
1754 {
1755 // TLBR/TLBWI/TLBWR/TLBP/ERET
1756 assert(opcode2[i]==0x10);
1757 alloc_all(current,i);
1758 }
1759}
1760
1761void cop1_alloc(struct regstat *current,int i)
1762{
1763 alloc_reg(current,i,CSREG); // Load status
1764 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1765 {
1766 assert(rt1[i]);
1767 clear_const(current,rt1[i]);
1768 if(opcode2[i]==1) {
1769 alloc_reg64(current,i,rt1[i]); // DMFC1
1770 current->is32&=~(1LL<<rt1[i]);
1771 }else{
1772 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1773 current->is32|=1LL<<rt1[i];
1774 }
1775 dirty_reg(current,rt1[i]);
1776 alloc_reg_temp(current,i,-1);
1777 }
1778 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1779 {
1780 if(rs1[i]){
1781 clear_const(current,rs1[i]);
1782 if(opcode2[i]==5)
1783 alloc_reg64(current,i,rs1[i]); // DMTC1
1784 else
1785 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1786 alloc_reg_temp(current,i,-1);
1787 }
1788 else {
1789 current->u&=~1LL;
1790 alloc_reg(current,i,0);
1791 alloc_reg_temp(current,i,-1);
1792 }
1793 }
1794}
1795void fconv_alloc(struct regstat *current,int i)
1796{
1797 alloc_reg(current,i,CSREG); // Load status
1798 alloc_reg_temp(current,i,-1);
1799}
1800void float_alloc(struct regstat *current,int i)
1801{
1802 alloc_reg(current,i,CSREG); // Load status
1803 alloc_reg_temp(current,i,-1);
1804}
b9b61529 1805void c2op_alloc(struct regstat *current,int i)
1806{
1807 alloc_reg_temp(current,i,-1);
1808}
57871462 1809void fcomp_alloc(struct regstat *current,int i)
1810{
1811 alloc_reg(current,i,CSREG); // Load status
1812 alloc_reg(current,i,FSREG); // Load flags
1813 dirty_reg(current,FSREG); // Flag will be modified
1814 alloc_reg_temp(current,i,-1);
1815}
1816
1817void syscall_alloc(struct regstat *current,int i)
1818{
1819 alloc_cc(current,i);
1820 dirty_reg(current,CCREG);
1821 alloc_all(current,i);
1822 current->isconst=0;
1823}
1824
1825void delayslot_alloc(struct regstat *current,int i)
1826{
1827 switch(itype[i]) {
1828 case UJUMP:
1829 case CJUMP:
1830 case SJUMP:
1831 case RJUMP:
1832 case FJUMP:
1833 case SYSCALL:
7139f3c8 1834 case HLECALL:
57871462 1835 case SPAN:
1836 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1837 printf("Disabled speculative precompilation\n");
1838 stop_after_jal=1;
1839 break;
1840 case IMM16:
1841 imm16_alloc(current,i);
1842 break;
1843 case LOAD:
1844 case LOADLR:
1845 load_alloc(current,i);
1846 break;
1847 case STORE:
1848 case STORELR:
1849 store_alloc(current,i);
1850 break;
1851 case ALU:
1852 alu_alloc(current,i);
1853 break;
1854 case SHIFT:
1855 shift_alloc(current,i);
1856 break;
1857 case MULTDIV:
1858 multdiv_alloc(current,i);
1859 break;
1860 case SHIFTIMM:
1861 shiftimm_alloc(current,i);
1862 break;
1863 case MOV:
1864 mov_alloc(current,i);
1865 break;
1866 case COP0:
1867 cop0_alloc(current,i);
1868 break;
1869 case COP1:
b9b61529 1870 case COP2:
57871462 1871 cop1_alloc(current,i);
1872 break;
1873 case C1LS:
1874 c1ls_alloc(current,i);
1875 break;
b9b61529 1876 case C2LS:
1877 c2ls_alloc(current,i);
1878 break;
57871462 1879 case FCONV:
1880 fconv_alloc(current,i);
1881 break;
1882 case FLOAT:
1883 float_alloc(current,i);
1884 break;
1885 case FCOMP:
1886 fcomp_alloc(current,i);
1887 break;
b9b61529 1888 case C2OP:
1889 c2op_alloc(current,i);
1890 break;
57871462 1891 }
1892}
1893
1894// Special case where a branch and delay slot span two pages in virtual memory
1895static void pagespan_alloc(struct regstat *current,int i)
1896{
1897 current->isconst=0;
1898 current->wasconst=0;
1899 regs[i].wasconst=0;
1900 alloc_all(current,i);
1901 alloc_cc(current,i);
1902 dirty_reg(current,CCREG);
1903 if(opcode[i]==3) // JAL
1904 {
1905 alloc_reg(current,i,31);
1906 dirty_reg(current,31);
1907 }
1908 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1909 {
1910 alloc_reg(current,i,rs1[i]);
5067f341 1911 if (rt1[i]!=0) {
1912 alloc_reg(current,i,rt1[i]);
1913 dirty_reg(current,rt1[i]);
57871462 1914 }
1915 }
1916 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1917 {
1918 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1919 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1920 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1921 {
1922 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1923 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1924 }
1925 }
1926 else
1927 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1928 {
1929 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1930 if(!((current->is32>>rs1[i])&1))
1931 {
1932 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1933 }
1934 }
1935 else
1936 if(opcode[i]==0x11) // BC1
1937 {
1938 alloc_reg(current,i,FSREG);
1939 alloc_reg(current,i,CSREG);
1940 }
1941 //else ...
1942}
1943
1944add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
1945{
1946 stubs[stubcount][0]=type;
1947 stubs[stubcount][1]=addr;
1948 stubs[stubcount][2]=retaddr;
1949 stubs[stubcount][3]=a;
1950 stubs[stubcount][4]=b;
1951 stubs[stubcount][5]=c;
1952 stubs[stubcount][6]=d;
1953 stubs[stubcount][7]=e;
1954 stubcount++;
1955}
1956
1957// Write out a single register
1958void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
1959{
1960 int hr;
1961 for(hr=0;hr<HOST_REGS;hr++) {
1962 if(hr!=EXCLUDE_REG) {
1963 if((regmap[hr]&63)==r) {
1964 if((dirty>>hr)&1) {
1965 if(regmap[hr]<64) {
1966 emit_storereg(r,hr);
24385cae 1967#ifndef FORCE32
57871462 1968 if((is32>>regmap[hr])&1) {
1969 emit_sarimm(hr,31,hr);
1970 emit_storereg(r|64,hr);
1971 }
24385cae 1972#endif
57871462 1973 }else{
1974 emit_storereg(r|64,hr);
1975 }
1976 }
1977 }
1978 }
1979 }
1980}
1981
1982int mchecksum()
1983{
1984 //if(!tracedebug) return 0;
1985 int i;
1986 int sum=0;
1987 for(i=0;i<2097152;i++) {
1988 unsigned int temp=sum;
1989 sum<<=1;
1990 sum|=(~temp)>>31;
1991 sum^=((u_int *)rdram)[i];
1992 }
1993 return sum;
1994}
1995int rchecksum()
1996{
1997 int i;
1998 int sum=0;
1999 for(i=0;i<64;i++)
2000 sum^=((u_int *)reg)[i];
2001 return sum;
2002}
57871462 2003void rlist()
2004{
2005 int i;
2006 printf("TRACE: ");
2007 for(i=0;i<32;i++)
2008 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2009 printf("\n");
3d624f89 2010#ifndef DISABLE_COP1
57871462 2011 printf("TRACE: ");
2012 for(i=0;i<32;i++)
2013 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2014 printf("\n");
3d624f89 2015#endif
57871462 2016}
2017
2018void enabletrace()
2019{
2020 tracedebug=1;
2021}
2022
2023void memdebug(int i)
2024{
2025 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2026 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2027 //rlist();
2028 //if(tracedebug) {
2029 //if(Count>=-2084597794) {
2030 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2031 //if(0) {
2032 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2033 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2034 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2035 rlist();
2036 #ifdef __i386__
2037 printf("TRACE: %x\n",(&i)[-1]);
2038 #endif
2039 #ifdef __arm__
2040 int j;
2041 printf("TRACE: %x \n",(&j)[10]);
2042 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2043 #endif
2044 //fflush(stdout);
2045 }
2046 //printf("TRACE: %x\n",(&i)[-1]);
2047}
2048
2049void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2050{
2051 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2052}
2053
2054void alu_assemble(int i,struct regstat *i_regs)
2055{
2056 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2057 if(rt1[i]) {
2058 signed char s1,s2,t;
2059 t=get_reg(i_regs->regmap,rt1[i]);
2060 if(t>=0) {
2061 s1=get_reg(i_regs->regmap,rs1[i]);
2062 s2=get_reg(i_regs->regmap,rs2[i]);
2063 if(rs1[i]&&rs2[i]) {
2064 assert(s1>=0);
2065 assert(s2>=0);
2066 if(opcode2[i]&2) emit_sub(s1,s2,t);
2067 else emit_add(s1,s2,t);
2068 }
2069 else if(rs1[i]) {
2070 if(s1>=0) emit_mov(s1,t);
2071 else emit_loadreg(rs1[i],t);
2072 }
2073 else if(rs2[i]) {
2074 if(s2>=0) {
2075 if(opcode2[i]&2) emit_neg(s2,t);
2076 else emit_mov(s2,t);
2077 }
2078 else {
2079 emit_loadreg(rs2[i],t);
2080 if(opcode2[i]&2) emit_neg(t,t);
2081 }
2082 }
2083 else emit_zeroreg(t);
2084 }
2085 }
2086 }
2087 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2088 if(rt1[i]) {
2089 signed char s1l,s2l,s1h,s2h,tl,th;
2090 tl=get_reg(i_regs->regmap,rt1[i]);
2091 th=get_reg(i_regs->regmap,rt1[i]|64);
2092 if(tl>=0) {
2093 s1l=get_reg(i_regs->regmap,rs1[i]);
2094 s2l=get_reg(i_regs->regmap,rs2[i]);
2095 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2096 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2097 if(rs1[i]&&rs2[i]) {
2098 assert(s1l>=0);
2099 assert(s2l>=0);
2100 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2101 else emit_adds(s1l,s2l,tl);
2102 if(th>=0) {
2103 #ifdef INVERTED_CARRY
2104 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2105 #else
2106 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2107 #endif
2108 else emit_add(s1h,s2h,th);
2109 }
2110 }
2111 else if(rs1[i]) {
2112 if(s1l>=0) emit_mov(s1l,tl);
2113 else emit_loadreg(rs1[i],tl);
2114 if(th>=0) {
2115 if(s1h>=0) emit_mov(s1h,th);
2116 else emit_loadreg(rs1[i]|64,th);
2117 }
2118 }
2119 else if(rs2[i]) {
2120 if(s2l>=0) {
2121 if(opcode2[i]&2) emit_negs(s2l,tl);
2122 else emit_mov(s2l,tl);
2123 }
2124 else {
2125 emit_loadreg(rs2[i],tl);
2126 if(opcode2[i]&2) emit_negs(tl,tl);
2127 }
2128 if(th>=0) {
2129 #ifdef INVERTED_CARRY
2130 if(s2h>=0) emit_mov(s2h,th);
2131 else emit_loadreg(rs2[i]|64,th);
2132 if(opcode2[i]&2) {
2133 emit_adcimm(-1,th); // x86 has inverted carry flag
2134 emit_not(th,th);
2135 }
2136 #else
2137 if(opcode2[i]&2) {
2138 if(s2h>=0) emit_rscimm(s2h,0,th);
2139 else {
2140 emit_loadreg(rs2[i]|64,th);
2141 emit_rscimm(th,0,th);
2142 }
2143 }else{
2144 if(s2h>=0) emit_mov(s2h,th);
2145 else emit_loadreg(rs2[i]|64,th);
2146 }
2147 #endif
2148 }
2149 }
2150 else {
2151 emit_zeroreg(tl);
2152 if(th>=0) emit_zeroreg(th);
2153 }
2154 }
2155 }
2156 }
2157 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2158 if(rt1[i]) {
2159 signed char s1l,s1h,s2l,s2h,t;
2160 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2161 {
2162 t=get_reg(i_regs->regmap,rt1[i]);
2163 //assert(t>=0);
2164 if(t>=0) {
2165 s1l=get_reg(i_regs->regmap,rs1[i]);
2166 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2167 s2l=get_reg(i_regs->regmap,rs2[i]);
2168 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2169 if(rs2[i]==0) // rx<r0
2170 {
2171 assert(s1h>=0);
2172 if(opcode2[i]==0x2a) // SLT
2173 emit_shrimm(s1h,31,t);
2174 else // SLTU (unsigned can not be less than zero)
2175 emit_zeroreg(t);
2176 }
2177 else if(rs1[i]==0) // r0<rx
2178 {
2179 assert(s2h>=0);
2180 if(opcode2[i]==0x2a) // SLT
2181 emit_set_gz64_32(s2h,s2l,t);
2182 else // SLTU (set if not zero)
2183 emit_set_nz64_32(s2h,s2l,t);
2184 }
2185 else {
2186 assert(s1l>=0);assert(s1h>=0);
2187 assert(s2l>=0);assert(s2h>=0);
2188 if(opcode2[i]==0x2a) // SLT
2189 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2190 else // SLTU
2191 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2192 }
2193 }
2194 } else {
2195 t=get_reg(i_regs->regmap,rt1[i]);
2196 //assert(t>=0);
2197 if(t>=0) {
2198 s1l=get_reg(i_regs->regmap,rs1[i]);
2199 s2l=get_reg(i_regs->regmap,rs2[i]);
2200 if(rs2[i]==0) // rx<r0
2201 {
2202 assert(s1l>=0);
2203 if(opcode2[i]==0x2a) // SLT
2204 emit_shrimm(s1l,31,t);
2205 else // SLTU (unsigned can not be less than zero)
2206 emit_zeroreg(t);
2207 }
2208 else if(rs1[i]==0) // r0<rx
2209 {
2210 assert(s2l>=0);
2211 if(opcode2[i]==0x2a) // SLT
2212 emit_set_gz32(s2l,t);
2213 else // SLTU (set if not zero)
2214 emit_set_nz32(s2l,t);
2215 }
2216 else{
2217 assert(s1l>=0);assert(s2l>=0);
2218 if(opcode2[i]==0x2a) // SLT
2219 emit_set_if_less32(s1l,s2l,t);
2220 else // SLTU
2221 emit_set_if_carry32(s1l,s2l,t);
2222 }
2223 }
2224 }
2225 }
2226 }
2227 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2228 if(rt1[i]) {
2229 signed char s1l,s1h,s2l,s2h,th,tl;
2230 tl=get_reg(i_regs->regmap,rt1[i]);
2231 th=get_reg(i_regs->regmap,rt1[i]|64);
2232 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2233 {
2234 assert(tl>=0);
2235 if(tl>=0) {
2236 s1l=get_reg(i_regs->regmap,rs1[i]);
2237 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2238 s2l=get_reg(i_regs->regmap,rs2[i]);
2239 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2240 if(rs1[i]&&rs2[i]) {
2241 assert(s1l>=0);assert(s1h>=0);
2242 assert(s2l>=0);assert(s2h>=0);
2243 if(opcode2[i]==0x24) { // AND
2244 emit_and(s1l,s2l,tl);
2245 emit_and(s1h,s2h,th);
2246 } else
2247 if(opcode2[i]==0x25) { // OR
2248 emit_or(s1l,s2l,tl);
2249 emit_or(s1h,s2h,th);
2250 } else
2251 if(opcode2[i]==0x26) { // XOR
2252 emit_xor(s1l,s2l,tl);
2253 emit_xor(s1h,s2h,th);
2254 } else
2255 if(opcode2[i]==0x27) { // NOR
2256 emit_or(s1l,s2l,tl);
2257 emit_or(s1h,s2h,th);
2258 emit_not(tl,tl);
2259 emit_not(th,th);
2260 }
2261 }
2262 else
2263 {
2264 if(opcode2[i]==0x24) { // AND
2265 emit_zeroreg(tl);
2266 emit_zeroreg(th);
2267 } else
2268 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2269 if(rs1[i]){
2270 if(s1l>=0) emit_mov(s1l,tl);
2271 else emit_loadreg(rs1[i],tl);
2272 if(s1h>=0) emit_mov(s1h,th);
2273 else emit_loadreg(rs1[i]|64,th);
2274 }
2275 else
2276 if(rs2[i]){
2277 if(s2l>=0) emit_mov(s2l,tl);
2278 else emit_loadreg(rs2[i],tl);
2279 if(s2h>=0) emit_mov(s2h,th);
2280 else emit_loadreg(rs2[i]|64,th);
2281 }
2282 else{
2283 emit_zeroreg(tl);
2284 emit_zeroreg(th);
2285 }
2286 } else
2287 if(opcode2[i]==0x27) { // NOR
2288 if(rs1[i]){
2289 if(s1l>=0) emit_not(s1l,tl);
2290 else{
2291 emit_loadreg(rs1[i],tl);
2292 emit_not(tl,tl);
2293 }
2294 if(s1h>=0) emit_not(s1h,th);
2295 else{
2296 emit_loadreg(rs1[i]|64,th);
2297 emit_not(th,th);
2298 }
2299 }
2300 else
2301 if(rs2[i]){
2302 if(s2l>=0) emit_not(s2l,tl);
2303 else{
2304 emit_loadreg(rs2[i],tl);
2305 emit_not(tl,tl);
2306 }
2307 if(s2h>=0) emit_not(s2h,th);
2308 else{
2309 emit_loadreg(rs2[i]|64,th);
2310 emit_not(th,th);
2311 }
2312 }
2313 else {
2314 emit_movimm(-1,tl);
2315 emit_movimm(-1,th);
2316 }
2317 }
2318 }
2319 }
2320 }
2321 else
2322 {
2323 // 32 bit
2324 if(tl>=0) {
2325 s1l=get_reg(i_regs->regmap,rs1[i]);
2326 s2l=get_reg(i_regs->regmap,rs2[i]);
2327 if(rs1[i]&&rs2[i]) {
2328 assert(s1l>=0);
2329 assert(s2l>=0);
2330 if(opcode2[i]==0x24) { // AND
2331 emit_and(s1l,s2l,tl);
2332 } else
2333 if(opcode2[i]==0x25) { // OR
2334 emit_or(s1l,s2l,tl);
2335 } else
2336 if(opcode2[i]==0x26) { // XOR
2337 emit_xor(s1l,s2l,tl);
2338 } else
2339 if(opcode2[i]==0x27) { // NOR
2340 emit_or(s1l,s2l,tl);
2341 emit_not(tl,tl);
2342 }
2343 }
2344 else
2345 {
2346 if(opcode2[i]==0x24) { // AND
2347 emit_zeroreg(tl);
2348 } else
2349 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2350 if(rs1[i]){
2351 if(s1l>=0) emit_mov(s1l,tl);
2352 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2353 }
2354 else
2355 if(rs2[i]){
2356 if(s2l>=0) emit_mov(s2l,tl);
2357 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2358 }
2359 else emit_zeroreg(tl);
2360 } else
2361 if(opcode2[i]==0x27) { // NOR
2362 if(rs1[i]){
2363 if(s1l>=0) emit_not(s1l,tl);
2364 else {
2365 emit_loadreg(rs1[i],tl);
2366 emit_not(tl,tl);
2367 }
2368 }
2369 else
2370 if(rs2[i]){
2371 if(s2l>=0) emit_not(s2l,tl);
2372 else {
2373 emit_loadreg(rs2[i],tl);
2374 emit_not(tl,tl);
2375 }
2376 }
2377 else emit_movimm(-1,tl);
2378 }
2379 }
2380 }
2381 }
2382 }
2383 }
2384}
2385
2386void imm16_assemble(int i,struct regstat *i_regs)
2387{
2388 if (opcode[i]==0x0f) { // LUI
2389 if(rt1[i]) {
2390 signed char t;
2391 t=get_reg(i_regs->regmap,rt1[i]);
2392 //assert(t>=0);
2393 if(t>=0) {
2394 if(!((i_regs->isconst>>t)&1))
2395 emit_movimm(imm[i]<<16,t);
2396 }
2397 }
2398 }
2399 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2400 if(rt1[i]) {
2401 signed char s,t;
2402 t=get_reg(i_regs->regmap,rt1[i]);
2403 s=get_reg(i_regs->regmap,rs1[i]);
2404 if(rs1[i]) {
2405 //assert(t>=0);
2406 //assert(s>=0);
2407 if(t>=0) {
2408 if(!((i_regs->isconst>>t)&1)) {
2409 if(s<0) {
2410 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2411 emit_addimm(t,imm[i],t);
2412 }else{
2413 if(!((i_regs->wasconst>>s)&1))
2414 emit_addimm(s,imm[i],t);
2415 else
2416 emit_movimm(constmap[i][s]+imm[i],t);
2417 }
2418 }
2419 }
2420 } else {
2421 if(t>=0) {
2422 if(!((i_regs->isconst>>t)&1))
2423 emit_movimm(imm[i],t);
2424 }
2425 }
2426 }
2427 }
2428 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2429 if(rt1[i]) {
2430 signed char sh,sl,th,tl;
2431 th=get_reg(i_regs->regmap,rt1[i]|64);
2432 tl=get_reg(i_regs->regmap,rt1[i]);
2433 sh=get_reg(i_regs->regmap,rs1[i]|64);
2434 sl=get_reg(i_regs->regmap,rs1[i]);
2435 if(tl>=0) {
2436 if(rs1[i]) {
2437 assert(sh>=0);
2438 assert(sl>=0);
2439 if(th>=0) {
2440 emit_addimm64_32(sh,sl,imm[i],th,tl);
2441 }
2442 else {
2443 emit_addimm(sl,imm[i],tl);
2444 }
2445 } else {
2446 emit_movimm(imm[i],tl);
2447 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2448 }
2449 }
2450 }
2451 }
2452 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2453 if(rt1[i]) {
2454 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2455 signed char sh,sl,t;
2456 t=get_reg(i_regs->regmap,rt1[i]);
2457 sh=get_reg(i_regs->regmap,rs1[i]|64);
2458 sl=get_reg(i_regs->regmap,rs1[i]);
2459 //assert(t>=0);
2460 if(t>=0) {
2461 if(rs1[i]>0) {
2462 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2463 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2464 if(opcode[i]==0x0a) { // SLTI
2465 if(sl<0) {
2466 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2467 emit_slti32(t,imm[i],t);
2468 }else{
2469 emit_slti32(sl,imm[i],t);
2470 }
2471 }
2472 else { // SLTIU
2473 if(sl<0) {
2474 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2475 emit_sltiu32(t,imm[i],t);
2476 }else{
2477 emit_sltiu32(sl,imm[i],t);
2478 }
2479 }
2480 }else{ // 64-bit
2481 assert(sl>=0);
2482 if(opcode[i]==0x0a) // SLTI
2483 emit_slti64_32(sh,sl,imm[i],t);
2484 else // SLTIU
2485 emit_sltiu64_32(sh,sl,imm[i],t);
2486 }
2487 }else{
2488 // SLTI(U) with r0 is just stupid,
2489 // nonetheless examples can be found
2490 if(opcode[i]==0x0a) // SLTI
2491 if(0<imm[i]) emit_movimm(1,t);
2492 else emit_zeroreg(t);
2493 else // SLTIU
2494 {
2495 if(imm[i]) emit_movimm(1,t);
2496 else emit_zeroreg(t);
2497 }
2498 }
2499 }
2500 }
2501 }
2502 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2503 if(rt1[i]) {
2504 signed char sh,sl,th,tl;
2505 th=get_reg(i_regs->regmap,rt1[i]|64);
2506 tl=get_reg(i_regs->regmap,rt1[i]);
2507 sh=get_reg(i_regs->regmap,rs1[i]|64);
2508 sl=get_reg(i_regs->regmap,rs1[i]);
2509 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2510 if(opcode[i]==0x0c) //ANDI
2511 {
2512 if(rs1[i]) {
2513 if(sl<0) {
2514 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2515 emit_andimm(tl,imm[i],tl);
2516 }else{
2517 if(!((i_regs->wasconst>>sl)&1))
2518 emit_andimm(sl,imm[i],tl);
2519 else
2520 emit_movimm(constmap[i][sl]&imm[i],tl);
2521 }
2522 }
2523 else
2524 emit_zeroreg(tl);
2525 if(th>=0) emit_zeroreg(th);
2526 }
2527 else
2528 {
2529 if(rs1[i]) {
2530 if(sl<0) {
2531 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2532 }
2533 if(th>=0) {
2534 if(sh<0) {
2535 emit_loadreg(rs1[i]|64,th);
2536 }else{
2537 emit_mov(sh,th);
2538 }
2539 }
2540 if(opcode[i]==0x0d) //ORI
2541 if(sl<0) {
2542 emit_orimm(tl,imm[i],tl);
2543 }else{
2544 if(!((i_regs->wasconst>>sl)&1))
2545 emit_orimm(sl,imm[i],tl);
2546 else
2547 emit_movimm(constmap[i][sl]|imm[i],tl);
2548 }
2549 if(opcode[i]==0x0e) //XORI
2550 if(sl<0) {
2551 emit_xorimm(tl,imm[i],tl);
2552 }else{
2553 if(!((i_regs->wasconst>>sl)&1))
2554 emit_xorimm(sl,imm[i],tl);
2555 else
2556 emit_movimm(constmap[i][sl]^imm[i],tl);
2557 }
2558 }
2559 else {
2560 emit_movimm(imm[i],tl);
2561 if(th>=0) emit_zeroreg(th);
2562 }
2563 }
2564 }
2565 }
2566 }
2567}
2568
2569void shiftimm_assemble(int i,struct regstat *i_regs)
2570{
2571 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2572 {
2573 if(rt1[i]) {
2574 signed char s,t;
2575 t=get_reg(i_regs->regmap,rt1[i]);
2576 s=get_reg(i_regs->regmap,rs1[i]);
2577 //assert(t>=0);
2578 if(t>=0){
2579 if(rs1[i]==0)
2580 {
2581 emit_zeroreg(t);
2582 }
2583 else
2584 {
2585 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2586 if(imm[i]) {
2587 if(opcode2[i]==0) // SLL
2588 {
2589 emit_shlimm(s<0?t:s,imm[i],t);
2590 }
2591 if(opcode2[i]==2) // SRL
2592 {
2593 emit_shrimm(s<0?t:s,imm[i],t);
2594 }
2595 if(opcode2[i]==3) // SRA
2596 {
2597 emit_sarimm(s<0?t:s,imm[i],t);
2598 }
2599 }else{
2600 // Shift by zero
2601 if(s>=0 && s!=t) emit_mov(s,t);
2602 }
2603 }
2604 }
2605 //emit_storereg(rt1[i],t); //DEBUG
2606 }
2607 }
2608 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2609 {
2610 if(rt1[i]) {
2611 signed char sh,sl,th,tl;
2612 th=get_reg(i_regs->regmap,rt1[i]|64);
2613 tl=get_reg(i_regs->regmap,rt1[i]);
2614 sh=get_reg(i_regs->regmap,rs1[i]|64);
2615 sl=get_reg(i_regs->regmap,rs1[i]);
2616 if(tl>=0) {
2617 if(rs1[i]==0)
2618 {
2619 emit_zeroreg(tl);
2620 if(th>=0) emit_zeroreg(th);
2621 }
2622 else
2623 {
2624 assert(sl>=0);
2625 assert(sh>=0);
2626 if(imm[i]) {
2627 if(opcode2[i]==0x38) // DSLL
2628 {
2629 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2630 emit_shlimm(sl,imm[i],tl);
2631 }
2632 if(opcode2[i]==0x3a) // DSRL
2633 {
2634 emit_shrdimm(sl,sh,imm[i],tl);
2635 if(th>=0) emit_shrimm(sh,imm[i],th);
2636 }
2637 if(opcode2[i]==0x3b) // DSRA
2638 {
2639 emit_shrdimm(sl,sh,imm[i],tl);
2640 if(th>=0) emit_sarimm(sh,imm[i],th);
2641 }
2642 }else{
2643 // Shift by zero
2644 if(sl!=tl) emit_mov(sl,tl);
2645 if(th>=0&&sh!=th) emit_mov(sh,th);
2646 }
2647 }
2648 }
2649 }
2650 }
2651 if(opcode2[i]==0x3c) // DSLL32
2652 {
2653 if(rt1[i]) {
2654 signed char sl,tl,th;
2655 tl=get_reg(i_regs->regmap,rt1[i]);
2656 th=get_reg(i_regs->regmap,rt1[i]|64);
2657 sl=get_reg(i_regs->regmap,rs1[i]);
2658 if(th>=0||tl>=0){
2659 assert(tl>=0);
2660 assert(th>=0);
2661 assert(sl>=0);
2662 emit_mov(sl,th);
2663 emit_zeroreg(tl);
2664 if(imm[i]>32)
2665 {
2666 emit_shlimm(th,imm[i]&31,th);
2667 }
2668 }
2669 }
2670 }
2671 if(opcode2[i]==0x3e) // DSRL32
2672 {
2673 if(rt1[i]) {
2674 signed char sh,tl,th;
2675 tl=get_reg(i_regs->regmap,rt1[i]);
2676 th=get_reg(i_regs->regmap,rt1[i]|64);
2677 sh=get_reg(i_regs->regmap,rs1[i]|64);
2678 if(tl>=0){
2679 assert(sh>=0);
2680 emit_mov(sh,tl);
2681 if(th>=0) emit_zeroreg(th);
2682 if(imm[i]>32)
2683 {
2684 emit_shrimm(tl,imm[i]&31,tl);
2685 }
2686 }
2687 }
2688 }
2689 if(opcode2[i]==0x3f) // DSRA32
2690 {
2691 if(rt1[i]) {
2692 signed char sh,tl;
2693 tl=get_reg(i_regs->regmap,rt1[i]);
2694 sh=get_reg(i_regs->regmap,rs1[i]|64);
2695 if(tl>=0){
2696 assert(sh>=0);
2697 emit_mov(sh,tl);
2698 if(imm[i]>32)
2699 {
2700 emit_sarimm(tl,imm[i]&31,tl);
2701 }
2702 }
2703 }
2704 }
2705}
2706
2707#ifndef shift_assemble
2708void shift_assemble(int i,struct regstat *i_regs)
2709{
2710 printf("Need shift_assemble for this architecture.\n");
2711 exit(1);
2712}
2713#endif
2714
2715void load_assemble(int i,struct regstat *i_regs)
2716{
2717 int s,th,tl,addr,map=-1;
2718 int offset;
2719 int jaddr=0;
2720 int memtarget,c=0;
2721 u_int hr,reglist=0;
2722 th=get_reg(i_regs->regmap,rt1[i]|64);
2723 tl=get_reg(i_regs->regmap,rt1[i]);
2724 s=get_reg(i_regs->regmap,rs1[i]);
2725 offset=imm[i];
2726 for(hr=0;hr<HOST_REGS;hr++) {
2727 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2728 }
2729 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2730 if(s>=0) {
2731 c=(i_regs->wasconst>>s)&1;
2732 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
2733 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2734 }
2735 if(offset||s<0||c) addr=tl;
2736 else addr=s;
2737 //printf("load_assemble: c=%d\n",c);
2738 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2739 // FIXME: Even if the load is a NOP, we should check for pagefaults...
2740 if(tl>=0) {
2741 //assert(tl>=0);
2742 //assert(rt1[i]);
2743 reglist&=~(1<<tl);
2744 if(th>=0) reglist&=~(1<<th);
2745 if(!using_tlb) {
2746 if(!c) {
2747//#define R29_HACK 1
2748 #ifdef R29_HACK
2749 // Strmnnrmn's speed hack
2750 if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
2751 #endif
2752 {
2753 emit_cmpimm(addr,0x800000);
2754 jaddr=(int)out;
2755 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2756 // Hint to branch predictor that the branch is unlikely to be taken
2757 if(rs1[i]>=28)
2758 emit_jno_unlikely(0);
2759 else
2760 #endif
2761 emit_jno(0);
2762 }
2763 }
2764 }else{ // using tlb
2765 int x=0;
2766 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2767 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2768 map=get_reg(i_regs->regmap,TLREG);
2769 assert(map>=0);
2770 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2771 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2772 }
2773 if (opcode[i]==0x20) { // LB
2774 if(!c||memtarget) {
2775 #ifdef HOST_IMM_ADDR32
2776 if(c)
2777 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2778 else
2779 #endif
2780 {
2781 //emit_xorimm(addr,3,tl);
2782 //gen_tlb_addr_r(tl,map);
2783 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2784 int x=0;
2002a1db 2785#ifdef BIG_ENDIAN_MIPS
57871462 2786 if(!c) emit_xorimm(addr,3,tl);
2787 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2788#else
2789 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2790 else if (tl!=addr) emit_mov(addr,tl);
2791#endif
57871462 2792 emit_movsbl_indexed_tlb(x,tl,map,tl);
2793 }
2794 if(jaddr)
2795 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2796 }
2797 else
2798 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2799 }
2800 if (opcode[i]==0x21) { // LH
2801 if(!c||memtarget) {
2802 #ifdef HOST_IMM_ADDR32
2803 if(c)
2804 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2805 else
2806 #endif
2807 {
2808 int x=0;
2002a1db 2809#ifdef BIG_ENDIAN_MIPS
57871462 2810 if(!c) emit_xorimm(addr,2,tl);
2811 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2812#else
2813 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2814 else if (tl!=addr) emit_mov(addr,tl);
2815#endif
57871462 2816 //#ifdef
2817 //emit_movswl_indexed_tlb(x,tl,map,tl);
2818 //else
2819 if(map>=0) {
2820 gen_tlb_addr_r(tl,map);
2821 emit_movswl_indexed(x,tl,tl);
2822 }else
2823 emit_movswl_indexed((int)rdram-0x80000000+x,tl,tl);
2824 }
2825 if(jaddr)
2826 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2827 }
2828 else
2829 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2830 }
2831 if (opcode[i]==0x23) { // LW
2832 if(!c||memtarget) {
2833 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2834 #ifdef HOST_IMM_ADDR32
2835 if(c)
2836 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2837 else
2838 #endif
2839 emit_readword_indexed_tlb(0,addr,map,tl);
2840 if(jaddr)
2841 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2842 }
2843 else
2844 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2845 }
2846 if (opcode[i]==0x24) { // LBU
2847 if(!c||memtarget) {
2848 #ifdef HOST_IMM_ADDR32
2849 if(c)
2850 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2851 else
2852 #endif
2853 {
2854 //emit_xorimm(addr,3,tl);
2855 //gen_tlb_addr_r(tl,map);
2856 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
2857 int x=0;
2002a1db 2858#ifdef BIG_ENDIAN_MIPS
57871462 2859 if(!c) emit_xorimm(addr,3,tl);
2860 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 2861#else
2862 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2863 else if (tl!=addr) emit_mov(addr,tl);
2864#endif
57871462 2865 emit_movzbl_indexed_tlb(x,tl,map,tl);
2866 }
2867 if(jaddr)
2868 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2869 }
2870 else
2871 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2872 }
2873 if (opcode[i]==0x25) { // LHU
2874 if(!c||memtarget) {
2875 #ifdef HOST_IMM_ADDR32
2876 if(c)
2877 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2878 else
2879 #endif
2880 {
2881 int x=0;
2002a1db 2882#ifdef BIG_ENDIAN_MIPS
57871462 2883 if(!c) emit_xorimm(addr,2,tl);
2884 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 2885#else
2886 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2887 else if (tl!=addr) emit_mov(addr,tl);
2888#endif
57871462 2889 //#ifdef
2890 //emit_movzwl_indexed_tlb(x,tl,map,tl);
2891 //#else
2892 if(map>=0) {
2893 gen_tlb_addr_r(tl,map);
2894 emit_movzwl_indexed(x,tl,tl);
2895 }else
2896 emit_movzwl_indexed((int)rdram-0x80000000+x,tl,tl);
2897 if(jaddr)
2898 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2899 }
2900 }
2901 else
2902 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2903 }
2904 if (opcode[i]==0x27) { // LWU
2905 assert(th>=0);
2906 if(!c||memtarget) {
2907 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2908 #ifdef HOST_IMM_ADDR32
2909 if(c)
2910 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2911 else
2912 #endif
2913 emit_readword_indexed_tlb(0,addr,map,tl);
2914 if(jaddr)
2915 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2916 }
2917 else {
2918 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2919 }
2920 emit_zeroreg(th);
2921 }
2922 if (opcode[i]==0x37) { // LD
2923 if(!c||memtarget) {
2924 //gen_tlb_addr_r(tl,map);
2925 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
2926 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
2927 #ifdef HOST_IMM_ADDR32
2928 if(c)
2929 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
2930 else
2931 #endif
2932 emit_readdword_indexed_tlb(0,addr,map,th,tl);
2933 if(jaddr)
2934 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2935 }
2936 else
2937 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2938 }
2939 //emit_storereg(rt1[i],tl); // DEBUG
2940 }
2941 //if(opcode[i]==0x23)
2942 //if(opcode[i]==0x24)
2943 //if(opcode[i]==0x23||opcode[i]==0x24)
2944 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
2945 {
2946 //emit_pusha();
2947 save_regs(0x100f);
2948 emit_readword((int)&last_count,ECX);
2949 #ifdef __i386__
2950 if(get_reg(i_regs->regmap,CCREG)<0)
2951 emit_loadreg(CCREG,HOST_CCREG);
2952 emit_add(HOST_CCREG,ECX,HOST_CCREG);
2953 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
2954 emit_writeword(HOST_CCREG,(int)&Count);
2955 #endif
2956 #ifdef __arm__
2957 if(get_reg(i_regs->regmap,CCREG)<0)
2958 emit_loadreg(CCREG,0);
2959 else
2960 emit_mov(HOST_CCREG,0);
2961 emit_add(0,ECX,0);
2962 emit_addimm(0,2*ccadj[i],0);
2963 emit_writeword(0,(int)&Count);
2964 #endif
2965 emit_call((int)memdebug);
2966 //emit_popa();
2967 restore_regs(0x100f);
2968 }/**/
2969}
2970
2971#ifndef loadlr_assemble
2972void loadlr_assemble(int i,struct regstat *i_regs)
2973{
2974 printf("Need loadlr_assemble for this architecture.\n");
2975 exit(1);
2976}
2977#endif
2978
2979void store_assemble(int i,struct regstat *i_regs)
2980{
2981 int s,th,tl,map=-1;
2982 int addr,temp;
2983 int offset;
2984 int jaddr=0,jaddr2,type;
666a299d 2985 int memtarget=0,c=0;
57871462 2986 int agr=AGEN1+(i&1);
2987 u_int hr,reglist=0;
2988 th=get_reg(i_regs->regmap,rs2[i]|64);
2989 tl=get_reg(i_regs->regmap,rs2[i]);
2990 s=get_reg(i_regs->regmap,rs1[i]);
2991 temp=get_reg(i_regs->regmap,agr);
2992 if(temp<0) temp=get_reg(i_regs->regmap,-1);
2993 offset=imm[i];
2994 if(s>=0) {
2995 c=(i_regs->wasconst>>s)&1;
2996 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
2997 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2998 }
2999 assert(tl>=0);
3000 assert(temp>=0);
3001 for(hr=0;hr<HOST_REGS;hr++) {
3002 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3003 }
3004 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3005 if(offset||s<0||c) addr=temp;
3006 else addr=s;
3007 if(!using_tlb) {
3008 if(!c) {
3009 #ifdef R29_HACK
3010 // Strmnnrmn's speed hack
3011 memtarget=1;
3012 if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
3013 #endif
3014 emit_cmpimm(addr,0x800000);
3015 #ifdef DESTRUCTIVE_SHIFT
3016 if(s==addr) emit_mov(s,temp);
3017 #endif
3018 #ifdef R29_HACK
3019 if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
3020 #endif
3021 {
3022 jaddr=(int)out;
3023 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3024 // Hint to branch predictor that the branch is unlikely to be taken
3025 if(rs1[i]>=28)
3026 emit_jno_unlikely(0);
3027 else
3028 #endif
3029 emit_jno(0);
3030 }
3031 }
3032 }else{ // using tlb
3033 int x=0;
3034 if (opcode[i]==0x28) x=3; // SB
3035 if (opcode[i]==0x29) x=2; // SH
3036 map=get_reg(i_regs->regmap,TLREG);
3037 assert(map>=0);
3038 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3039 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3040 }
3041
3042 if (opcode[i]==0x28) { // SB
3043 if(!c||memtarget) {
3044 int x=0;
2002a1db 3045#ifdef BIG_ENDIAN_MIPS
57871462 3046 if(!c) emit_xorimm(addr,3,temp);
3047 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2002a1db 3048#else
3049 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3050 else if (addr!=temp) emit_mov(addr,temp);
3051#endif
57871462 3052 //gen_tlb_addr_w(temp,map);
3053 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3054 emit_writebyte_indexed_tlb(tl,x,temp,map,temp);
3055 }
3056 type=STOREB_STUB;
3057 }
3058 if (opcode[i]==0x29) { // SH
3059 if(!c||memtarget) {
3060 int x=0;
2002a1db 3061#ifdef BIG_ENDIAN_MIPS
57871462 3062 if(!c) emit_xorimm(addr,2,temp);
3063 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2002a1db 3064#else
3065 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3066 else if (addr!=temp) emit_mov(addr,temp);
3067#endif
57871462 3068 //#ifdef
3069 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3070 //#else
3071 if(map>=0) {
3072 gen_tlb_addr_w(temp,map);
3073 emit_writehword_indexed(tl,x,temp);
3074 }else
3075 emit_writehword_indexed(tl,(int)rdram-0x80000000+x,temp);
3076 }
3077 type=STOREH_STUB;
3078 }
3079 if (opcode[i]==0x2B) { // SW
3080 if(!c||memtarget)
3081 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3082 emit_writeword_indexed_tlb(tl,0,addr,map,temp);
3083 type=STOREW_STUB;
3084 }
3085 if (opcode[i]==0x3F) { // SD
3086 if(!c||memtarget) {
3087 if(rs2[i]) {
3088 assert(th>=0);
3089 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3090 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3091 emit_writedword_indexed_tlb(th,tl,0,addr,map,temp);
3092 }else{
3093 // Store zero
3094 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3095 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3096 emit_writedword_indexed_tlb(tl,tl,0,addr,map,temp);
3097 }
3098 }
3099 type=STORED_STUB;
3100 }
666a299d 3101 if(!using_tlb&&(!c||memtarget))
3102 // addr could be a temp, make sure it survives STORE*_STUB
3103 reglist|=1<<addr;
57871462 3104 if(jaddr) {
3105 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3106 } else if(!memtarget) {
3107 inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3108 }
3109 if(!using_tlb) {
3110 if(!c||memtarget) {
3111 #ifdef DESTRUCTIVE_SHIFT
3112 // The x86 shift operation is 'destructive'; it overwrites the
3113 // source register, so we need to make a copy first and use that.
3114 addr=temp;
3115 #endif
3116 #if defined(HOST_IMM8)
3117 int ir=get_reg(i_regs->regmap,INVCP);
3118 assert(ir>=0);
3119 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3120 #else
3121 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3122 #endif
3123 jaddr2=(int)out;
3124 emit_jne(0);
3125 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3126 }
3127 }
3128 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3129 //if(opcode[i]==0x2B || opcode[i]==0x28)
3130 //if(opcode[i]==0x2B || opcode[i]==0x29)
3131 //if(opcode[i]==0x2B)
3132 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3133 {
3134 //emit_pusha();
3135 save_regs(0x100f);
3136 emit_readword((int)&last_count,ECX);
3137 #ifdef __i386__
3138 if(get_reg(i_regs->regmap,CCREG)<0)
3139 emit_loadreg(CCREG,HOST_CCREG);
3140 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3141 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3142 emit_writeword(HOST_CCREG,(int)&Count);
3143 #endif
3144 #ifdef __arm__
3145 if(get_reg(i_regs->regmap,CCREG)<0)
3146 emit_loadreg(CCREG,0);
3147 else
3148 emit_mov(HOST_CCREG,0);
3149 emit_add(0,ECX,0);
3150 emit_addimm(0,2*ccadj[i],0);
3151 emit_writeword(0,(int)&Count);
3152 #endif
3153 emit_call((int)memdebug);
3154 //emit_popa();
3155 restore_regs(0x100f);
3156 }/**/
3157}
3158
3159void storelr_assemble(int i,struct regstat *i_regs)
3160{
3161 int s,th,tl;
3162 int temp;
3163 int temp2;
3164 int offset;
3165 int jaddr=0,jaddr2;
3166 int case1,case2,case3;
3167 int done0,done1,done2;
3168 int memtarget,c=0;
3169 u_int hr,reglist=0;
3170 th=get_reg(i_regs->regmap,rs2[i]|64);
3171 tl=get_reg(i_regs->regmap,rs2[i]);
3172 s=get_reg(i_regs->regmap,rs1[i]);
3173 temp=get_reg(i_regs->regmap,-1);
3174 offset=imm[i];
3175 if(s>=0) {
3176 c=(i_regs->isconst>>s)&1;
3177 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
3178 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3179 }
3180 assert(tl>=0);
3181 for(hr=0;hr<HOST_REGS;hr++) {
3182 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3183 }
3184 if(tl>=0) {
3185 assert(temp>=0);
3186 if(!using_tlb) {
3187 if(!c) {
3188 emit_cmpimm(s<0||offset?temp:s,0x800000);
3189 if(!offset&&s!=temp) emit_mov(s,temp);
3190 jaddr=(int)out;
3191 emit_jno(0);
3192 }
3193 else
3194 {
3195 if(!memtarget||!rs1[i]) {
3196 jaddr=(int)out;
3197 emit_jmp(0);
3198 }
3199 }
3200 if((u_int)rdram!=0x80000000)
3201 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3202 }else{ // using tlb
3203 int map=get_reg(i_regs->regmap,TLREG);
3204 assert(map>=0);
3205 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3206 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3207 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3208 if(!jaddr&&!memtarget) {
3209 jaddr=(int)out;
3210 emit_jmp(0);
3211 }
3212 gen_tlb_addr_w(temp,map);
3213 }
3214
3215 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3216 temp2=get_reg(i_regs->regmap,FTEMP);
3217 if(!rs2[i]) temp2=th=tl;
3218 }
3219
2002a1db 3220#ifndef BIG_ENDIAN_MIPS
3221 emit_xorimm(temp,3,temp);
3222#endif
57871462 3223 emit_testimm(temp,2);
3224 case2=(int)out;
3225 emit_jne(0);
3226 emit_testimm(temp,1);
3227 case1=(int)out;
3228 emit_jne(0);
3229 // 0
3230 if (opcode[i]==0x2A) { // SWL
3231 emit_writeword_indexed(tl,0,temp);
3232 }
3233 if (opcode[i]==0x2E) { // SWR
3234 emit_writebyte_indexed(tl,3,temp);
3235 }
3236 if (opcode[i]==0x2C) { // SDL
3237 emit_writeword_indexed(th,0,temp);
3238 if(rs2[i]) emit_mov(tl,temp2);
3239 }
3240 if (opcode[i]==0x2D) { // SDR
3241 emit_writebyte_indexed(tl,3,temp);
3242 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3243 }
3244 done0=(int)out;
3245 emit_jmp(0);
3246 // 1
3247 set_jump_target(case1,(int)out);
3248 if (opcode[i]==0x2A) { // SWL
3249 // Write 3 msb into three least significant bytes
3250 if(rs2[i]) emit_rorimm(tl,8,tl);
3251 emit_writehword_indexed(tl,-1,temp);
3252 if(rs2[i]) emit_rorimm(tl,16,tl);
3253 emit_writebyte_indexed(tl,1,temp);
3254 if(rs2[i]) emit_rorimm(tl,8,tl);
3255 }
3256 if (opcode[i]==0x2E) { // SWR
3257 // Write two lsb into two most significant bytes
3258 emit_writehword_indexed(tl,1,temp);
3259 }
3260 if (opcode[i]==0x2C) { // SDL
3261 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3262 // Write 3 msb into three least significant bytes
3263 if(rs2[i]) emit_rorimm(th,8,th);
3264 emit_writehword_indexed(th,-1,temp);
3265 if(rs2[i]) emit_rorimm(th,16,th);
3266 emit_writebyte_indexed(th,1,temp);
3267 if(rs2[i]) emit_rorimm(th,8,th);
3268 }
3269 if (opcode[i]==0x2D) { // SDR
3270 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3271 // Write two lsb into two most significant bytes
3272 emit_writehword_indexed(tl,1,temp);
3273 }
3274 done1=(int)out;
3275 emit_jmp(0);
3276 // 2
3277 set_jump_target(case2,(int)out);
3278 emit_testimm(temp,1);
3279 case3=(int)out;
3280 emit_jne(0);
3281 if (opcode[i]==0x2A) { // SWL
3282 // Write two msb into two least significant bytes
3283 if(rs2[i]) emit_rorimm(tl,16,tl);
3284 emit_writehword_indexed(tl,-2,temp);
3285 if(rs2[i]) emit_rorimm(tl,16,tl);
3286 }
3287 if (opcode[i]==0x2E) { // SWR
3288 // Write 3 lsb into three most significant bytes
3289 emit_writebyte_indexed(tl,-1,temp);
3290 if(rs2[i]) emit_rorimm(tl,8,tl);
3291 emit_writehword_indexed(tl,0,temp);
3292 if(rs2[i]) emit_rorimm(tl,24,tl);
3293 }
3294 if (opcode[i]==0x2C) { // SDL
3295 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3296 // Write two msb into two least significant bytes
3297 if(rs2[i]) emit_rorimm(th,16,th);
3298 emit_writehword_indexed(th,-2,temp);
3299 if(rs2[i]) emit_rorimm(th,16,th);
3300 }
3301 if (opcode[i]==0x2D) { // SDR
3302 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3303 // Write 3 lsb into three most significant bytes
3304 emit_writebyte_indexed(tl,-1,temp);
3305 if(rs2[i]) emit_rorimm(tl,8,tl);
3306 emit_writehword_indexed(tl,0,temp);
3307 if(rs2[i]) emit_rorimm(tl,24,tl);
3308 }
3309 done2=(int)out;
3310 emit_jmp(0);
3311 // 3
3312 set_jump_target(case3,(int)out);
3313 if (opcode[i]==0x2A) { // SWL
3314 // Write msb into least significant byte
3315 if(rs2[i]) emit_rorimm(tl,24,tl);
3316 emit_writebyte_indexed(tl,-3,temp);
3317 if(rs2[i]) emit_rorimm(tl,8,tl);
3318 }
3319 if (opcode[i]==0x2E) { // SWR
3320 // Write entire word
3321 emit_writeword_indexed(tl,-3,temp);
3322 }
3323 if (opcode[i]==0x2C) { // SDL
3324 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3325 // Write msb into least significant byte
3326 if(rs2[i]) emit_rorimm(th,24,th);
3327 emit_writebyte_indexed(th,-3,temp);
3328 if(rs2[i]) emit_rorimm(th,8,th);
3329 }
3330 if (opcode[i]==0x2D) { // SDR
3331 if(rs2[i]) emit_mov(th,temp2);
3332 // Write entire word
3333 emit_writeword_indexed(tl,-3,temp);
3334 }
3335 set_jump_target(done0,(int)out);
3336 set_jump_target(done1,(int)out);
3337 set_jump_target(done2,(int)out);
3338 if (opcode[i]==0x2C) { // SDL
3339 emit_testimm(temp,4);
3340 done0=(int)out;
3341 emit_jne(0);
3342 emit_andimm(temp,~3,temp);
3343 emit_writeword_indexed(temp2,4,temp);
3344 set_jump_target(done0,(int)out);
3345 }
3346 if (opcode[i]==0x2D) { // SDR
3347 emit_testimm(temp,4);
3348 done0=(int)out;
3349 emit_jeq(0);
3350 emit_andimm(temp,~3,temp);
3351 emit_writeword_indexed(temp2,-4,temp);
3352 set_jump_target(done0,(int)out);
3353 }
3354 if(!c||!memtarget)
3355 add_stub(STORELR_STUB,jaddr,(int)out,0,(int)i_regs,rs2[i],ccadj[i],reglist);
3356 }
3357 if(!using_tlb) {
3358 emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3359 #if defined(HOST_IMM8)
3360 int ir=get_reg(i_regs->regmap,INVCP);
3361 assert(ir>=0);
3362 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3363 #else
3364 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3365 #endif
3366 jaddr2=(int)out;
3367 emit_jne(0);
3368 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3369 }
3370 /*
3371 emit_pusha();
3372 //save_regs(0x100f);
3373 emit_readword((int)&last_count,ECX);
3374 if(get_reg(i_regs->regmap,CCREG)<0)
3375 emit_loadreg(CCREG,HOST_CCREG);
3376 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3377 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3378 emit_writeword(HOST_CCREG,(int)&Count);
3379 emit_call((int)memdebug);
3380 emit_popa();
3381 //restore_regs(0x100f);
3382 /**/
3383}
3384
3385void c1ls_assemble(int i,struct regstat *i_regs)
3386{
3d624f89 3387#ifndef DISABLE_COP1
57871462 3388 int s,th,tl;
3389 int temp,ar;
3390 int map=-1;
3391 int offset;
3392 int c=0;
3393 int jaddr,jaddr2=0,jaddr3,type;
3394 int agr=AGEN1+(i&1);
3395 u_int hr,reglist=0;
3396 th=get_reg(i_regs->regmap,FTEMP|64);
3397 tl=get_reg(i_regs->regmap,FTEMP);
3398 s=get_reg(i_regs->regmap,rs1[i]);
3399 temp=get_reg(i_regs->regmap,agr);
3400 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3401 offset=imm[i];
3402 assert(tl>=0);
3403 assert(rs1[i]>0);
3404 assert(temp>=0);
3405 for(hr=0;hr<HOST_REGS;hr++) {
3406 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3407 }
3408 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3409 if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3410 {
3411 // Loads use a temporary register which we need to save
3412 reglist|=1<<temp;
3413 }
3414 if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3415 ar=temp;
3416 else // LWC1/LDC1
3417 ar=tl;
3418 //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3419 //else c=(i_regs->wasconst>>s)&1;
3420 if(s>=0) c=(i_regs->wasconst>>s)&1;
3421 // Check cop1 unusable
3422 if(!cop1_usable) {
3423 signed char rs=get_reg(i_regs->regmap,CSREG);
3424 assert(rs>=0);
3425 emit_testimm(rs,0x20000000);
3426 jaddr=(int)out;
3427 emit_jeq(0);
3428 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3429 cop1_usable=1;
3430 }
3431 if (opcode[i]==0x39) { // SWC1 (get float address)
3432 emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],tl);
3433 }
3434 if (opcode[i]==0x3D) { // SDC1 (get double address)
3435 emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],tl);
3436 }
3437 // Generate address + offset
3438 if(!using_tlb) {
3439 if(!c)
3440 emit_cmpimm(offset||c||s<0?ar:s,0x800000);
3441 }
3442 else
3443 {
3444 map=get_reg(i_regs->regmap,TLREG);
3445 assert(map>=0);
3446 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3447 map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3448 }
3449 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3450 map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3451 }
3452 }
3453 if (opcode[i]==0x39) { // SWC1 (read float)
3454 emit_readword_indexed(0,tl,tl);
3455 }
3456 if (opcode[i]==0x3D) { // SDC1 (read double)
3457 emit_readword_indexed(4,tl,th);
3458 emit_readword_indexed(0,tl,tl);
3459 }
3460 if (opcode[i]==0x31) { // LWC1 (get target address)
3461 emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],temp);
3462 }
3463 if (opcode[i]==0x35) { // LDC1 (get target address)
3464 emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],temp);
3465 }
3466 if(!using_tlb) {
3467 if(!c) {
3468 jaddr2=(int)out;
3469 emit_jno(0);
3470 }
3471 else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80800000) {
3472 jaddr2=(int)out;
3473 emit_jmp(0); // inline_readstub/inline_writestub? Very rare case
3474 }
3475 #ifdef DESTRUCTIVE_SHIFT
3476 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3477 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3478 }
3479 #endif
3480 }else{
3481 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3482 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3483 }
3484 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3485 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3486 }
3487 }
3488 if (opcode[i]==0x31) { // LWC1
3489 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3490 //gen_tlb_addr_r(ar,map);
3491 //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3492 #ifdef HOST_IMM_ADDR32
3493 if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3494 else
3495 #endif
3496 emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3497 type=LOADW_STUB;
3498 }
3499 if (opcode[i]==0x35) { // LDC1
3500 assert(th>=0);
3501 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3502 //gen_tlb_addr_r(ar,map);
3503 //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3504 //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3505 #ifdef HOST_IMM_ADDR32
3506 if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3507 else
3508 #endif
3509 emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3510 type=LOADD_STUB;
3511 }
3512 if (opcode[i]==0x39) { // SWC1
3513 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3514 emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3515 type=STOREW_STUB;
3516 }
3517 if (opcode[i]==0x3D) { // SDC1
3518 assert(th>=0);
3519 //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3520 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3521 emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3522 type=STORED_STUB;
3523 }
3524 if(!using_tlb) {
3525 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3526 #ifndef DESTRUCTIVE_SHIFT
3527 temp=offset||c||s<0?ar:s;
3528 #endif
3529 #if defined(HOST_IMM8)
3530 int ir=get_reg(i_regs->regmap,INVCP);
3531 assert(ir>=0);
3532 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3533 #else
3534 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3535 #endif
3536 jaddr3=(int)out;
3537 emit_jne(0);
3538 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3539 }
3540 }
3541 if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3542 if (opcode[i]==0x31) { // LWC1 (write float)
3543 emit_writeword_indexed(tl,0,temp);
3544 }
3545 if (opcode[i]==0x35) { // LDC1 (write double)
3546 emit_writeword_indexed(th,4,temp);
3547 emit_writeword_indexed(tl,0,temp);
3548 }
3549 //if(opcode[i]==0x39)
3550 /*if(opcode[i]==0x39||opcode[i]==0x31)
3551 {
3552 emit_pusha();
3553 emit_readword((int)&last_count,ECX);
3554 if(get_reg(i_regs->regmap,CCREG)<0)
3555 emit_loadreg(CCREG,HOST_CCREG);
3556 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3557 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3558 emit_writeword(HOST_CCREG,(int)&Count);
3559 emit_call((int)memdebug);
3560 emit_popa();
3561 }/**/
3d624f89 3562#else
3563 cop1_unusable(i, i_regs);
3564#endif
57871462 3565}
3566
b9b61529 3567void c2ls_assemble(int i,struct regstat *i_regs)
3568{
3569 int s,tl;
3570 int ar;
3571 int offset;
3572 int c=0;
3573 int jaddr,jaddr2=0,jaddr3,type;
3574 int agr=AGEN1+(i&1);
3575 u_int hr,reglist=0;
3576 u_int copr=(source[i]>>16)&0x1f;
3577 s=get_reg(i_regs->regmap,rs1[i]);
3578 tl=get_reg(i_regs->regmap,FTEMP);
3579 offset=imm[i];
3580 assert(rs1[i]>0);
3581 assert(tl>=0);
3582 assert(!using_tlb);
3583
3584 for(hr=0;hr<HOST_REGS;hr++) {
3585 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3586 }
3587 if(i_regs->regmap[HOST_CCREG]==CCREG)
3588 reglist&=~(1<<HOST_CCREG);
3589
3590 // get the address
3591 if (opcode[i]==0x3a) { // SWC2
3592 ar=get_reg(i_regs->regmap,agr);
3593 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3594 reglist|=1<<ar;
3595 } else { // LWC2
3596 ar=tl;
3597 }
3598 if (!offset&&!c&&s>=0) ar=s;
3599 assert(ar>=0);
3600
3601 if (opcode[i]==0x3a) { // SWC2
3602 cop2_get_dreg(copr,tl,HOST_TEMPREG);
3603 }
3604 if(s>=0) c=(i_regs->wasconst>>s)&1;
3605 if(!c) {
3606 emit_cmpimm(offset||c||s<0?ar:s,0x800000);
3607 jaddr2=(int)out;
3608 emit_jno(0);
3609 }
3610 else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80800000) {
3611 jaddr2=(int)out;
3612 emit_jmp(0); // inline_readstub/inline_writestub? Very rare case
3613 }
3614 if (opcode[i]==0x32) { // LWC2
3615 #ifdef HOST_IMM_ADDR32
3616 if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3617 else
3618 #endif
3619 emit_readword_indexed(0,ar,tl);
3620 type=LOADW_STUB;
3621 }
3622 if (opcode[i]==0x3a) { // SWC2
3623#ifdef DESTRUCTIVE_SHIFT
3624 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3625#endif
3626 emit_writeword_indexed(tl,0,ar);
3627 type=STOREW_STUB;
3628 }
3629 if(jaddr2)
3630 add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3631 if (opcode[i]==0x3a) { // SWC2
3632#if defined(HOST_IMM8)
3633 int ir=get_reg(i_regs->regmap,INVCP);
3634 assert(ir>=0);
3635 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3636#else
3637 emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3638#endif
3639 jaddr3=(int)out;
3640 emit_jne(0);
3641 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3642 }
3643 if (opcode[i]==0x32) { // LWC2
3644 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3645 }
3646}
3647
57871462 3648#ifndef multdiv_assemble
3649void multdiv_assemble(int i,struct regstat *i_regs)
3650{
3651 printf("Need multdiv_assemble for this architecture.\n");
3652 exit(1);
3653}
3654#endif
3655
3656void mov_assemble(int i,struct regstat *i_regs)
3657{
3658 //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3659 //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3660 assert(rt1[i]>0);
3661 if(rt1[i]) {
3662 signed char sh,sl,th,tl;
3663 th=get_reg(i_regs->regmap,rt1[i]|64);
3664 tl=get_reg(i_regs->regmap,rt1[i]);
3665 //assert(tl>=0);
3666 if(tl>=0) {
3667 sh=get_reg(i_regs->regmap,rs1[i]|64);
3668 sl=get_reg(i_regs->regmap,rs1[i]);
3669 if(sl>=0) emit_mov(sl,tl);
3670 else emit_loadreg(rs1[i],tl);
3671 if(th>=0) {
3672 if(sh>=0) emit_mov(sh,th);
3673 else emit_loadreg(rs1[i]|64,th);
3674 }
3675 }
3676 }
3677}
3678
3679#ifndef fconv_assemble
3680void fconv_assemble(int i,struct regstat *i_regs)
3681{
3682 printf("Need fconv_assemble for this architecture.\n");
3683 exit(1);
3684}
3685#endif
3686
3687#if 0
3688void float_assemble(int i,struct regstat *i_regs)
3689{
3690 printf("Need float_assemble for this architecture.\n");
3691 exit(1);
3692}
3693#endif
3694
3695void syscall_assemble(int i,struct regstat *i_regs)
3696{
3697 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3698 assert(ccreg==HOST_CCREG);
3699 assert(!is_delayslot);
3700 emit_movimm(start+i*4,EAX); // Get PC
3701 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
7139f3c8 3702 emit_jmp((int)jump_syscall_hle); // XXX
3703}
3704
3705void hlecall_assemble(int i,struct regstat *i_regs)
3706{
3707 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3708 assert(ccreg==HOST_CCREG);
3709 assert(!is_delayslot);
3710 emit_movimm(start+i*4+4,0); // Get PC
67ba0fb4 3711 emit_movimm((int)psxHLEt[source[i]&7],1);
7139f3c8 3712 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // XXX
67ba0fb4 3713 emit_jmp((int)jump_hlecall);
57871462 3714}
3715
3716void ds_assemble(int i,struct regstat *i_regs)
3717{
3718 is_delayslot=1;
3719 switch(itype[i]) {
3720 case ALU:
3721 alu_assemble(i,i_regs);break;
3722 case IMM16:
3723 imm16_assemble(i,i_regs);break;
3724 case SHIFT:
3725 shift_assemble(i,i_regs);break;
3726 case SHIFTIMM:
3727 shiftimm_assemble(i,i_regs);break;
3728 case LOAD:
3729 load_assemble(i,i_regs);break;
3730 case LOADLR:
3731 loadlr_assemble(i,i_regs);break;
3732 case STORE:
3733 store_assemble(i,i_regs);break;
3734 case STORELR:
3735 storelr_assemble(i,i_regs);break;
3736 case COP0:
3737 cop0_assemble(i,i_regs);break;
3738 case COP1:
3739 cop1_assemble(i,i_regs);break;
3740 case C1LS:
3741 c1ls_assemble(i,i_regs);break;
b9b61529 3742 case COP2:
3743 cop2_assemble(i,i_regs);break;
3744 case C2LS:
3745 c2ls_assemble(i,i_regs);break;
3746 case C2OP:
3747 c2op_assemble(i,i_regs);break;
57871462 3748 case FCONV:
3749 fconv_assemble(i,i_regs);break;
3750 case FLOAT:
3751 float_assemble(i,i_regs);break;
3752 case FCOMP:
3753 fcomp_assemble(i,i_regs);break;
3754 case MULTDIV:
3755 multdiv_assemble(i,i_regs);break;
3756 case MOV:
3757 mov_assemble(i,i_regs);break;
3758 case SYSCALL:
7139f3c8 3759 case HLECALL:
57871462 3760 case SPAN:
3761 case UJUMP:
3762 case RJUMP:
3763 case CJUMP:
3764 case SJUMP:
3765 case FJUMP:
3766 printf("Jump in the delay slot. This is probably a bug.\n");
3767 }
3768 is_delayslot=0;
3769}
3770
3771// Is the branch target a valid internal jump?
3772int internal_branch(uint64_t i_is32,int addr)
3773{
3774 if(addr&1) return 0; // Indirect (register) jump
3775 if(addr>=start && addr<start+slen*4-4)
3776 {
3777 int t=(addr-start)>>2;
3778 // Delay slots are not valid branch targets
3779 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
3780 // 64 -> 32 bit transition requires a recompile
3781 /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
3782 {
3783 if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
3784 else printf("optimizable: yes\n");
3785 }*/
3786 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
3787 if(requires_32bit[t]&~i_is32) return 0;
3788 else return 1;
3789 }
3790 return 0;
3791}
3792
3793#ifndef wb_invalidate
3794void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
3795 uint64_t u,uint64_t uu)
3796{
3797 int hr;
3798 for(hr=0;hr<HOST_REGS;hr++) {
3799 if(hr!=EXCLUDE_REG) {
3800 if(pre[hr]!=entry[hr]) {
3801 if(pre[hr]>=0) {
3802 if((dirty>>hr)&1) {
3803 if(get_reg(entry,pre[hr])<0) {
3804 if(pre[hr]<64) {
3805 if(!((u>>pre[hr])&1)) {
3806 emit_storereg(pre[hr],hr);
3807 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
3808 emit_sarimm(hr,31,hr);
3809 emit_storereg(pre[hr]|64,hr);
3810 }
3811 }
3812 }else{
3813 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
3814 emit_storereg(pre[hr],hr);
3815 }
3816 }
3817 }
3818 }
3819 }
3820 }
3821 }
3822 }
3823 // Move from one register to another (no writeback)
3824 for(hr=0;hr<HOST_REGS;hr++) {
3825 if(hr!=EXCLUDE_REG) {
3826 if(pre[hr]!=entry[hr]) {
3827 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
3828 int nr;
3829 if((nr=get_reg(entry,pre[hr]))>=0) {
3830 emit_mov(hr,nr);
3831 }
3832 }
3833 }
3834 }
3835 }
3836}
3837#endif
3838
3839// Load the specified registers
3840// This only loads the registers given as arguments because
3841// we don't want to load things that will be overwritten
3842void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
3843{
3844 int hr;
3845 // Load 32-bit regs
3846 for(hr=0;hr<HOST_REGS;hr++) {
3847 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
3848 if(entry[hr]!=regmap[hr]) {
3849 if(regmap[hr]==rs1||regmap[hr]==rs2)
3850 {
3851 if(regmap[hr]==0) {
3852 emit_zeroreg(hr);
3853 }
3854 else
3855 {
3856 emit_loadreg(regmap[hr],hr);
3857 }
3858 }
3859 }
3860 }
3861 }
3862 //Load 64-bit regs
3863 for(hr=0;hr<HOST_REGS;hr++) {
3864 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
3865 if(entry[hr]!=regmap[hr]) {
3866 if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
3867 {
3868 assert(regmap[hr]!=64);
3869 if((is32>>(regmap[hr]&63))&1) {
3870 int lr=get_reg(regmap,regmap[hr]-64);
3871 if(lr>=0)
3872 emit_sarimm(lr,31,hr);
3873 else
3874 emit_loadreg(regmap[hr],hr);
3875 }
3876 else
3877 {
3878 emit_loadreg(regmap[hr],hr);
3879 }
3880 }
3881 }
3882 }
3883 }
3884}
3885
3886// Load registers prior to the start of a loop
3887// so that they are not loaded within the loop
3888static void loop_preload(signed char pre[],signed char entry[])
3889{
3890 int hr;
3891 for(hr=0;hr<HOST_REGS;hr++) {
3892 if(hr!=EXCLUDE_REG) {
3893 if(pre[hr]!=entry[hr]) {
3894 if(entry[hr]>=0) {
3895 if(get_reg(pre,entry[hr])<0) {
3896 assem_debug("loop preload:\n");
3897 //printf("loop preload: %d\n",hr);
3898 if(entry[hr]==0) {
3899 emit_zeroreg(hr);
3900 }
3901 else if(entry[hr]<TEMPREG)
3902 {
3903 emit_loadreg(entry[hr],hr);
3904 }
3905 else if(entry[hr]-64<TEMPREG)
3906 {
3907 emit_loadreg(entry[hr],hr);
3908 }
3909 }
3910 }
3911 }
3912 }
3913 }
3914}
3915
3916// Generate address for load/store instruction
b9b61529 3917// goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
57871462 3918void address_generation(int i,struct regstat *i_regs,signed char entry[])
3919{
b9b61529 3920 if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
57871462 3921 int ra;
3922 int agr=AGEN1+(i&1);
3923 int mgr=MGEN1+(i&1);
3924 if(itype[i]==LOAD) {
3925 ra=get_reg(i_regs->regmap,rt1[i]);
3926 //if(rt1[i]) assert(ra>=0);
3927 }
3928 if(itype[i]==LOADLR) {
3929 ra=get_reg(i_regs->regmap,FTEMP);
3930 }
3931 if(itype[i]==STORE||itype[i]==STORELR) {
3932 ra=get_reg(i_regs->regmap,agr);
3933 if(ra<0) ra=get_reg(i_regs->regmap,-1);
3934 }
b9b61529 3935 if(itype[i]==C1LS||itype[i]==C2LS) {
3936 if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
57871462 3937 ra=get_reg(i_regs->regmap,FTEMP);
3938 else { // SWC1/SDC1
3939 ra=get_reg(i_regs->regmap,agr);
3940 if(ra<0) ra=get_reg(i_regs->regmap,-1);
3941 }
3942 }
3943 int rs=get_reg(i_regs->regmap,rs1[i]);
3944 int rm=get_reg(i_regs->regmap,TLREG);
3945 if(ra>=0) {
3946 int offset=imm[i];
3947 int c=(i_regs->wasconst>>rs)&1;
3948 if(rs1[i]==0) {
3949 // Using r0 as a base address
3950 /*if(rm>=0) {
3951 if(!entry||entry[rm]!=mgr) {
3952 generate_map_const(offset,rm);
3953 } // else did it in the previous cycle
3954 }*/
3955 if(!entry||entry[ra]!=agr) {
3956 if (opcode[i]==0x22||opcode[i]==0x26) {
3957 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
3958 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
3959 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
3960 }else{
3961 emit_movimm(offset,ra);
3962 }
3963 } // else did it in the previous cycle
3964 }
3965 else if(rs<0) {
3966 if(!entry||entry[ra]!=rs1[i])
3967 emit_loadreg(rs1[i],ra);
3968 //if(!entry||entry[ra]!=rs1[i])
3969 // printf("poor load scheduling!\n");
3970 }
3971 else if(c) {
3972 if(rm>=0) {
3973 if(!entry||entry[rm]!=mgr) {
b9b61529 3974 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
57871462 3975 // Stores to memory go thru the mapper to detect self-modifying
3976 // code, loads don't.
3977 if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
3978 (unsigned int)(constmap[i][rs]+offset)<0x80800000 )
3979 generate_map_const(constmap[i][rs]+offset,rm);
3980 }else{
3981 if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
3982 generate_map_const(constmap[i][rs]+offset,rm);
3983 }
3984 }
3985 }
3986 if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
3987 if(!entry||entry[ra]!=agr) {
3988 if (opcode[i]==0x22||opcode[i]==0x26) {
3989 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
3990 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
3991 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
3992 }else{
3993 #ifdef HOST_IMM_ADDR32
b9b61529 3994 if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
57871462 3995 (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
3996 #endif
3997 emit_movimm(constmap[i][rs]+offset,ra);
3998 }
3999 } // else did it in the previous cycle
4000 } // else load_consts already did it
4001 }
4002 if(offset&&!c&&rs1[i]) {
4003 if(rs>=0) {
4004 emit_addimm(rs,offset,ra);
4005 }else{
4006 emit_addimm(ra,offset,ra);
4007 }
4008 }
4009 }
4010 }
4011 // Preload constants for next instruction
b9b61529 4012 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
57871462 4013 int agr,ra;
4014 #ifndef HOST_IMM_ADDR32
4015 // Mapper entry
4016 agr=MGEN1+((i+1)&1);
4017 ra=get_reg(i_regs->regmap,agr);
4018 if(ra>=0) {
4019 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4020 int offset=imm[i+1];
4021 int c=(regs[i+1].wasconst>>rs)&1;
4022 if(c) {
b9b61529 4023 if(itype[i+1]==STORE||itype[i+1]==STORELR
4024 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
57871462 4025 // Stores to memory go thru the mapper to detect self-modifying
4026 // code, loads don't.
4027 if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4028 (unsigned int)(constmap[i+1][rs]+offset)<0x80800000 )
4029 generate_map_const(constmap[i+1][rs]+offset,ra);
4030 }else{
4031 if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4032 generate_map_const(constmap[i+1][rs]+offset,ra);
4033 }
4034 }
4035 /*else if(rs1[i]==0) {
4036 generate_map_const(offset,ra);
4037 }*/
4038 }
4039 #endif
4040 // Actual address
4041 agr=AGEN1+((i+1)&1);
4042 ra=get_reg(i_regs->regmap,agr);
4043 if(ra>=0) {
4044 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4045 int offset=imm[i+1];
4046 int c=(regs[i+1].wasconst>>rs)&1;
4047 if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4048 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4049 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4050 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4051 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4052 }else{
4053 #ifdef HOST_IMM_ADDR32
b9b61529 4054 if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
57871462 4055 (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4056 #endif
4057 emit_movimm(constmap[i+1][rs]+offset,ra);
4058 }
4059 }
4060 else if(rs1[i+1]==0) {
4061 // Using r0 as a base address
4062 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4063 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4064 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4065 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4066 }else{
4067 emit_movimm(offset,ra);
4068 }
4069 }
4070 }
4071 }
4072}
4073
4074int get_final_value(int hr, int i, int *value)
4075{
4076 int reg=regs[i].regmap[hr];
4077 while(i<slen-1) {
4078 if(regs[i+1].regmap[hr]!=reg) break;
4079 if(!((regs[i+1].isconst>>hr)&1)) break;
4080 if(bt[i+1]) break;
4081 i++;
4082 }
4083 if(i<slen-1) {
4084 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4085 *value=constmap[i][hr];
4086 return 1;
4087 }
4088 if(!bt[i+1]) {
4089 if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4090 // Load in delay slot, out-of-order execution
4091 if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4092 {
4093 #ifdef HOST_IMM_ADDR32
4094 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4095 #endif
4096 // Precompute load address
4097 *value=constmap[i][hr]+imm[i+2];
4098 return 1;
4099 }
4100 }
4101 if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4102 {
4103 #ifdef HOST_IMM_ADDR32
4104 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4105 #endif
4106 // Precompute load address
4107 *value=constmap[i][hr]+imm[i+1];
4108 //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4109 return 1;
4110 }
4111 }
4112 }
4113 *value=constmap[i][hr];
4114 //printf("c=%x\n",(int)constmap[i][hr]);
4115 if(i==slen-1) return 1;
4116 if(reg<64) {
4117 return !((unneeded_reg[i+1]>>reg)&1);
4118 }else{
4119 return !((unneeded_reg_upper[i+1]>>reg)&1);
4120 }
4121}
4122
4123// Load registers with known constants
4124void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4125{
4126 int hr;
4127 // Load 32-bit regs
4128 for(hr=0;hr<HOST_REGS;hr++) {
4129 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4130 //if(entry[hr]!=regmap[hr]) {
4131 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4132 if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4133 int value;
4134 if(get_final_value(hr,i,&value)) {
4135 if(value==0) {
4136 emit_zeroreg(hr);
4137 }
4138 else {
4139 emit_movimm(value,hr);
4140 }
4141 }
4142 }
4143 }
4144 }
4145 }
4146 // Load 64-bit regs
4147 for(hr=0;hr<HOST_REGS;hr++) {
4148 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4149 //if(entry[hr]!=regmap[hr]) {
4150 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4151 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4152 if((is32>>(regmap[hr]&63))&1) {
4153 int lr=get_reg(regmap,regmap[hr]-64);
4154 assert(lr>=0);
4155 emit_sarimm(lr,31,hr);
4156 }
4157 else
4158 {
4159 int value;
4160 if(get_final_value(hr,i,&value)) {
4161 if(value==0) {
4162 emit_zeroreg(hr);
4163 }
4164 else {
4165 emit_movimm(value,hr);
4166 }
4167 }
4168 }
4169 }
4170 }
4171 }
4172 }
4173}
4174void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4175{
4176 int hr;
4177 // Load 32-bit regs
4178 for(hr=0;hr<HOST_REGS;hr++) {
4179 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4180 if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4181 int value=constmap[i][hr];
4182 if(value==0) {
4183 emit_zeroreg(hr);
4184 }
4185 else {
4186 emit_movimm(value,hr);
4187 }
4188 }
4189 }
4190 }
4191 // Load 64-bit regs
4192 for(hr=0;hr<HOST_REGS;hr++) {
4193 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4194 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4195 if((is32>>(regmap[hr]&63))&1) {
4196 int lr=get_reg(regmap,regmap[hr]-64);
4197 assert(lr>=0);
4198 emit_sarimm(lr,31,hr);
4199 }
4200 else
4201 {
4202 int value=constmap[i][hr];
4203 if(value==0) {
4204 emit_zeroreg(hr);
4205 }
4206 else {
4207 emit_movimm(value,hr);
4208 }
4209 }
4210 }
4211 }
4212 }
4213}
4214
4215// Write out all dirty registers (except cycle count)
4216void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4217{
4218 int hr;
4219 for(hr=0;hr<HOST_REGS;hr++) {
4220 if(hr!=EXCLUDE_REG) {
4221 if(i_regmap[hr]>0) {
4222 if(i_regmap[hr]!=CCREG) {
4223 if((i_dirty>>hr)&1) {
4224 if(i_regmap[hr]<64) {
4225 emit_storereg(i_regmap[hr],hr);
24385cae 4226#ifndef FORCE32
57871462 4227 if( ((i_is32>>i_regmap[hr])&1) ) {
4228 #ifdef DESTRUCTIVE_WRITEBACK
4229 emit_sarimm(hr,31,hr);
4230 emit_storereg(i_regmap[hr]|64,hr);
4231 #else
4232 emit_sarimm(hr,31,HOST_TEMPREG);
4233 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4234 #endif
4235 }
24385cae 4236#endif
57871462 4237 }else{
4238 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4239 emit_storereg(i_regmap[hr],hr);
4240 }
4241 }
4242 }
4243 }
4244 }
4245 }
4246 }
4247}
4248// Write out dirty registers that we need to reload (pair with load_needed_regs)
4249// This writes the registers not written by store_regs_bt
4250void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4251{
4252 int hr;
4253 int t=(addr-start)>>2;
4254 for(hr=0;hr<HOST_REGS;hr++) {
4255 if(hr!=EXCLUDE_REG) {
4256 if(i_regmap[hr]>0) {
4257 if(i_regmap[hr]!=CCREG) {
4258 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4259 if((i_dirty>>hr)&1) {
4260 if(i_regmap[hr]<64) {
4261 emit_storereg(i_regmap[hr],hr);
24385cae 4262#ifndef FORCE32
57871462 4263 if( ((i_is32>>i_regmap[hr])&1) ) {
4264 #ifdef DESTRUCTIVE_WRITEBACK
4265 emit_sarimm(hr,31,hr);
4266 emit_storereg(i_regmap[hr]|64,hr);
4267 #else
4268 emit_sarimm(hr,31,HOST_TEMPREG);
4269 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4270 #endif
4271 }
24385cae 4272#endif
57871462 4273 }else{
4274 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4275 emit_storereg(i_regmap[hr],hr);
4276 }
4277 }
4278 }
4279 }
4280 }
4281 }
4282 }
4283 }
4284}
4285
4286// Load all registers (except cycle count)
4287void load_all_regs(signed char i_regmap[])
4288{
4289 int hr;
4290 for(hr=0;hr<HOST_REGS;hr++) {
4291 if(hr!=EXCLUDE_REG) {
4292 if(i_regmap[hr]==0) {
4293 emit_zeroreg(hr);
4294 }
4295 else
4296 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG)
4297 {
4298 emit_loadreg(i_regmap[hr],hr);
4299 }
4300 }
4301 }
4302}
4303
4304// Load all current registers also needed by next instruction
4305void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4306{
4307 int hr;
4308 for(hr=0;hr<HOST_REGS;hr++) {
4309 if(hr!=EXCLUDE_REG) {
4310 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4311 if(i_regmap[hr]==0) {
4312 emit_zeroreg(hr);
4313 }
4314 else
4315 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG)
4316 {
4317 emit_loadreg(i_regmap[hr],hr);
4318 }
4319 }
4320 }
4321 }
4322}
4323
4324// Load all regs, storing cycle count if necessary
4325void load_regs_entry(int t)
4326{
4327 int hr;
4328 if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER,HOST_CCREG);
4329 else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t]*CLOCK_DIVIDER,HOST_CCREG);
4330 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4331 emit_storereg(CCREG,HOST_CCREG);
4332 }
4333 // Load 32-bit regs
4334 for(hr=0;hr<HOST_REGS;hr++) {
4335 if(regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<64) {
4336 if(regs[t].regmap_entry[hr]==0) {
4337 emit_zeroreg(hr);
4338 }
4339 else if(regs[t].regmap_entry[hr]!=CCREG)
4340 {
4341 emit_loadreg(regs[t].regmap_entry[hr],hr);
4342 }
4343 }
4344 }
4345 // Load 64-bit regs
4346 for(hr=0;hr<HOST_REGS;hr++) {
4347 if(regs[t].regmap_entry[hr]>=64) {
4348 assert(regs[t].regmap_entry[hr]!=64);
4349 if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4350 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4351 if(lr<0) {
4352 emit_loadreg(regs[t].regmap_entry[hr],hr);
4353 }
4354 else
4355 {
4356 emit_sarimm(lr,31,hr);
4357 }
4358 }
4359 else
4360 {
4361 emit_loadreg(regs[t].regmap_entry[hr],hr);
4362 }
4363 }
4364 }
4365}
4366
4367// Store dirty registers prior to branch
4368void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4369{
4370 if(internal_branch(i_is32,addr))
4371 {
4372 int t=(addr-start)>>2;
4373 int hr;
4374 for(hr=0;hr<HOST_REGS;hr++) {
4375 if(hr!=EXCLUDE_REG) {
4376 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4377 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4378 if((i_dirty>>hr)&1) {
4379 if(i_regmap[hr]<64) {
4380 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4381 emit_storereg(i_regmap[hr],hr);
4382 if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4383 #ifdef DESTRUCTIVE_WRITEBACK
4384 emit_sarimm(hr,31,hr);
4385 emit_storereg(i_regmap[hr]|64,hr);
4386 #else
4387 emit_sarimm(hr,31,HOST_TEMPREG);
4388 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4389 #endif
4390 }
4391 }
4392 }else{
4393 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4394 emit_storereg(i_regmap[hr],hr);
4395 }
4396 }
4397 }
4398 }
4399 }
4400 }
4401 }
4402 }
4403 else
4404 {
4405 // Branch out of this block, write out all dirty regs
4406 wb_dirtys(i_regmap,i_is32,i_dirty);
4407 }
4408}
4409
4410// Load all needed registers for branch target
4411void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4412{
4413 //if(addr>=start && addr<(start+slen*4))
4414 if(internal_branch(i_is32,addr))
4415 {
4416 int t=(addr-start)>>2;
4417 int hr;
4418 // Store the cycle count before loading something else
4419 if(i_regmap[HOST_CCREG]!=CCREG) {
4420 assert(i_regmap[HOST_CCREG]==-1);
4421 }
4422 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4423 emit_storereg(CCREG,HOST_CCREG);
4424 }
4425 // Load 32-bit regs
4426 for(hr=0;hr<HOST_REGS;hr++) {
4427 if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<64) {
4428 #ifdef DESTRUCTIVE_WRITEBACK
4429 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4430 #else
4431 if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4432 #endif
4433 if(regs[t].regmap_entry[hr]==0) {
4434 emit_zeroreg(hr);
4435 }
4436 else if(regs[t].regmap_entry[hr]!=CCREG)
4437 {
4438 emit_loadreg(regs[t].regmap_entry[hr],hr);
4439 }
4440 }
4441 }
4442 }
4443 //Load 64-bit regs
4444 for(hr=0;hr<HOST_REGS;hr++) {
4445 if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=64) {
4446 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4447 assert(regs[t].regmap_entry[hr]!=64);
4448 if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4449 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4450 if(lr<0) {
4451 emit_loadreg(regs[t].regmap_entry[hr],hr);
4452 }
4453 else
4454 {
4455 emit_sarimm(lr,31,hr);
4456 }
4457 }
4458 else
4459 {
4460 emit_loadreg(regs[t].regmap_entry[hr],hr);
4461 }
4462 }
4463 else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4464 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4465 assert(lr>=0);
4466 emit_sarimm(lr,31,hr);
4467 }
4468 }
4469 }
4470 }
4471}
4472
4473int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4474{
4475 if(addr>=start && addr<start+slen*4-4)
4476 {
4477 int t=(addr-start)>>2;
4478 int hr;
4479 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4480 for(hr=0;hr<HOST_REGS;hr++)
4481 {
4482 if(hr!=EXCLUDE_REG)
4483 {
4484 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4485 {
4486 if(regs[t].regmap_entry[hr]!=-1)
4487 {
4488 return 0;
4489 }
4490 else
4491 if((i_dirty>>hr)&1)
4492 {
4493 if(i_regmap[hr]<64)
4494 {
4495 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4496 return 0;
4497 }
4498 else
4499 {
4500 if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4501 return 0;
4502 }
4503 }
4504 }
4505 else // Same register but is it 32-bit or dirty?
4506 if(i_regmap[hr]>=0)
4507 {
4508 if(!((regs[t].dirty>>hr)&1))
4509 {
4510 if((i_dirty>>hr)&1)
4511 {
4512 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4513 {
4514 //printf("%x: dirty no match\n",addr);
4515 return 0;
4516 }
4517 }
4518 }
4519 if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4520 {
4521 //printf("%x: is32 no match\n",addr);
4522 return 0;
4523 }
4524 }
4525 }
4526 }
4527 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4528 if(requires_32bit[t]&~i_is32) return 0;
4529 // Delay slots are not valid branch targets
4530 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4531 // Delay slots require additional processing, so do not match
4532 if(is_ds[t]) return 0;
4533 }
4534 else
4535 {
4536 int hr;
4537 for(hr=0;hr<HOST_REGS;hr++)
4538 {
4539 if(hr!=EXCLUDE_REG)
4540 {
4541 if(i_regmap[hr]>=0)
4542 {
4543 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4544 {
4545 if((i_dirty>>hr)&1)
4546 {
4547 return 0;
4548 }
4549 }
4550 }
4551 }
4552 }
4553 }
4554 return 1;
4555}
4556
4557// Used when a branch jumps into the delay slot of another branch
4558void ds_assemble_entry(int i)
4559{
4560 int t=(ba[i]-start)>>2;
4561 if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4562 assem_debug("Assemble delay slot at %x\n",ba[i]);
4563 assem_debug("<->\n");
4564 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
4565 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4566 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4567 address_generation(t,&regs[t],regs[t].regmap_entry);
b9b61529 4568 if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
57871462 4569 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4570 cop1_usable=0;
4571 is_delayslot=0;
4572 switch(itype[t]) {
4573 case ALU:
4574 alu_assemble(t,&regs[t]);break;
4575 case IMM16:
4576 imm16_assemble(t,&regs[t]);break;
4577 case SHIFT:
4578 shift_assemble(t,&regs[t]);break;
4579 case SHIFTIMM:
4580 shiftimm_assemble(t,&regs[t]);break;
4581 case LOAD:
4582 load_assemble(t,&regs[t]);break;
4583 case LOADLR:
4584 loadlr_assemble(t,&regs[t]);break;
4585 case STORE:
4586 store_assemble(t,&regs[t]);break;
4587 case STORELR:
4588 storelr_assemble(t,&regs[t]);break;
4589 case COP0:
4590 cop0_assemble(t,&regs[t]);break;
4591 case COP1:
4592 cop1_assemble(t,&regs[t]);break;
4593 case C1LS:
4594 c1ls_assemble(t,&regs[t]);break;
b9b61529 4595 case COP2:
4596 cop2_assemble(t,&regs[t]);break;
4597 case C2LS:
4598 c2ls_assemble(t,&regs[t]);break;
4599 case C2OP:
4600 c2op_assemble(t,&regs[t]);break;
57871462 4601 case FCONV:
4602 fconv_assemble(t,&regs[t]);break;
4603 case FLOAT:
4604 float_assemble(t,&regs[t]);break;
4605 case FCOMP:
4606 fcomp_assemble(t,&regs[t]);break;
4607 case MULTDIV:
4608 multdiv_assemble(t,&regs[t]);break;
4609 case MOV:
4610 mov_assemble(t,&regs[t]);break;
4611 case SYSCALL:
7139f3c8 4612 case HLECALL:
57871462 4613 case SPAN:
4614 case UJUMP:
4615 case RJUMP:
4616 case CJUMP:
4617 case SJUMP:
4618 case FJUMP:
4619 printf("Jump in the delay slot. This is probably a bug.\n");
4620 }
4621 store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4622 load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4623 if(internal_branch(regs[t].is32,ba[i]+4))
4624 assem_debug("branch: internal\n");
4625 else
4626 assem_debug("branch: external\n");
4627 assert(internal_branch(regs[t].is32,ba[i]+4));
4628 add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4629 emit_jmp(0);
4630}
4631
4632void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4633{
4634 int count;
4635 int jaddr;
4636 int idle=0;
4637 if(itype[i]==RJUMP)
4638 {
4639 *adj=0;
4640 }
4641 //if(ba[i]>=start && ba[i]<(start+slen*4))
4642 if(internal_branch(branch_regs[i].is32,ba[i]))
4643 {
4644 int t=(ba[i]-start)>>2;
4645 if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4646 else *adj=ccadj[t];
4647 }
4648 else
4649 {
4650 *adj=0;
4651 }
4652 count=ccadj[i];
4653 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4654 // Idle loop
4655 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4656 idle=(int)out;
4657 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4658 emit_andimm(HOST_CCREG,3,HOST_CCREG);
4659 jaddr=(int)out;
4660 emit_jmp(0);
4661 }
4662 else if(*adj==0||invert) {
4663 emit_addimm_and_set_flags(CLOCK_DIVIDER*(count+2),HOST_CCREG);
4664 jaddr=(int)out;
4665 emit_jns(0);
4666 }
4667 else
4668 {
4669 emit_cmpimm(HOST_CCREG,-2*(count+2));
4670 jaddr=(int)out;
4671 emit_jns(0);
4672 }
4673 add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4674}
4675
4676void do_ccstub(int n)
4677{
4678 literal_pool(256);
4679 assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
4680 set_jump_target(stubs[n][1],(int)out);
4681 int i=stubs[n][4];
4682 if(stubs[n][6]==NULLDS) {
4683 // Delay slot instruction is nullified ("likely" branch)
4684 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4685 }
4686 else if(stubs[n][6]!=TAKEN) {
4687 wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4688 }
4689 else {
4690 if(internal_branch(branch_regs[i].is32,ba[i]))
4691 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4692 }
4693 if(stubs[n][5]!=-1)
4694 {
4695 // Save PC as return address
4696 emit_movimm(stubs[n][5],EAX);
4697 emit_writeword(EAX,(int)&pcaddr);
4698 }
4699 else
4700 {
4701 // Return address depends on which way the branch goes
4702 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
4703 {
4704 int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4705 int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4706 int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4707 int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4708 if(rs1[i]==0)
4709 {
4710 s1l=s2l;s1h=s2h;
4711 s2l=s2h=-1;
4712 }
4713 else if(rs2[i]==0)
4714 {
4715 s2l=s2h=-1;
4716 }
4717 if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
4718 s1h=s2h=-1;
4719 }
4720 assert(s1l>=0);
4721 #ifdef DESTRUCTIVE_WRITEBACK
4722 if(rs1[i]) {
4723 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
4724 emit_loadreg(rs1[i],s1l);
4725 }
4726 else {
4727 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
4728 emit_loadreg(rs2[i],s1l);
4729 }
4730 if(s2l>=0)
4731 if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
4732 emit_loadreg(rs2[i],s2l);
4733 #endif
4734 int hr=0;
4735 int addr,alt,ntaddr;
4736 while(hr<HOST_REGS)
4737 {
4738 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4739 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4740 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4741 {
4742 addr=hr++;break;
4743 }
4744 hr++;
4745 }
4746 while(hr<HOST_REGS)
4747 {
4748 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4749 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4750 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4751 {
4752 alt=hr++;break;
4753 }
4754 hr++;
4755 }
4756 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
4757 {
4758 while(hr<HOST_REGS)
4759 {
4760 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4761 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4762 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4763 {
4764 ntaddr=hr;break;
4765 }
4766 hr++;
4767 }
4768 assert(hr<HOST_REGS);
4769 }
4770 if((opcode[i]&0x2f)==4) // BEQ
4771 {
4772 #ifdef HAVE_CMOV_IMM
4773 if(s1h<0) {
4774 if(s2l>=0) emit_cmp(s1l,s2l);
4775 else emit_test(s1l,s1l);
4776 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
4777 }
4778 else
4779 #endif
4780 {
4781 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4782 if(s1h>=0) {
4783 if(s2h>=0) emit_cmp(s1h,s2h);
4784 else emit_test(s1h,s1h);
4785 emit_cmovne_reg(alt,addr);
4786 }
4787 if(s2l>=0) emit_cmp(s1l,s2l);
4788 else emit_test(s1l,s1l);
4789 emit_cmovne_reg(alt,addr);
4790 }
4791 }
4792 if((opcode[i]&0x2f)==5) // BNE
4793 {
4794 #ifdef HAVE_CMOV_IMM
4795 if(s1h<0) {
4796 if(s2l>=0) emit_cmp(s1l,s2l);
4797 else emit_test(s1l,s1l);
4798 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
4799 }
4800 else
4801 #endif
4802 {
4803 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
4804 if(s1h>=0) {
4805 if(s2h>=0) emit_cmp(s1h,s2h);
4806 else emit_test(s1h,s1h);
4807 emit_cmovne_reg(alt,addr);
4808 }
4809 if(s2l>=0) emit_cmp(s1l,s2l);
4810 else emit_test(s1l,s1l);
4811 emit_cmovne_reg(alt,addr);
4812 }
4813 }
4814 if((opcode[i]&0x2f)==6) // BLEZ
4815 {
4816 //emit_movimm(ba[i],alt);
4817 //emit_movimm(start+i*4+8,addr);
4818 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4819 emit_cmpimm(s1l,1);
4820 if(s1h>=0) emit_mov(addr,ntaddr);
4821 emit_cmovl_reg(alt,addr);
4822 if(s1h>=0) {
4823 emit_test(s1h,s1h);
4824 emit_cmovne_reg(ntaddr,addr);
4825 emit_cmovs_reg(alt,addr);
4826 }
4827 }
4828 if((opcode[i]&0x2f)==7) // BGTZ
4829 {
4830 //emit_movimm(ba[i],addr);
4831 //emit_movimm(start+i*4+8,ntaddr);
4832 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
4833 emit_cmpimm(s1l,1);
4834 if(s1h>=0) emit_mov(addr,alt);
4835 emit_cmovl_reg(ntaddr,addr);
4836 if(s1h>=0) {
4837 emit_test(s1h,s1h);
4838 emit_cmovne_reg(alt,addr);
4839 emit_cmovs_reg(ntaddr,addr);
4840 }
4841 }
4842 if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
4843 {
4844 //emit_movimm(ba[i],alt);
4845 //emit_movimm(start+i*4+8,addr);
4846 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4847 if(s1h>=0) emit_test(s1h,s1h);
4848 else emit_test(s1l,s1l);
4849 emit_cmovs_reg(alt,addr);
4850 }
4851 if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
4852 {
4853 //emit_movimm(ba[i],addr);
4854 //emit_movimm(start+i*4+8,alt);
4855 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4856 if(s1h>=0) emit_test(s1h,s1h);
4857 else emit_test(s1l,s1l);
4858 emit_cmovs_reg(alt,addr);
4859 }
4860 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
4861 if(source[i]&0x10000) // BC1T
4862 {
4863 //emit_movimm(ba[i],alt);
4864 //emit_movimm(start+i*4+8,addr);
4865 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4866 emit_testimm(s1l,0x800000);
4867 emit_cmovne_reg(alt,addr);
4868 }
4869 else // BC1F
4870 {
4871 //emit_movimm(ba[i],addr);
4872 //emit_movimm(start+i*4+8,alt);
4873 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4874 emit_testimm(s1l,0x800000);
4875 emit_cmovne_reg(alt,addr);
4876 }
4877 }
4878 emit_writeword(addr,(int)&pcaddr);
4879 }
4880 else
4881 if(itype[i]==RJUMP)
4882 {
4883 int r=get_reg(branch_regs[i].regmap,rs1[i]);
4884 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
4885 r=get_reg(branch_regs[i].regmap,RTEMP);
4886 }
4887 emit_writeword(r,(int)&pcaddr);
4888 }
4889 else {printf("Unknown branch type in do_ccstub\n");exit(1);}
4890 }
4891 // Update cycle count
4892 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
4893 if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
4894 emit_call((int)cc_interrupt);
4895 if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
4896 if(stubs[n][6]==TAKEN) {
4897 if(internal_branch(branch_regs[i].is32,ba[i]))
4898 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
4899 else if(itype[i]==RJUMP) {
4900 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
4901 emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
4902 else
4903 emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
4904 }
4905 }else if(stubs[n][6]==NOTTAKEN) {
4906 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
4907 else load_all_regs(branch_regs[i].regmap);
4908 }else if(stubs[n][6]==NULLDS) {
4909 // Delay slot instruction is nullified ("likely" branch)
4910 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
4911 else load_all_regs(regs[i].regmap);
4912 }else{
4913 load_all_regs(branch_regs[i].regmap);
4914 }
4915 emit_jmp(stubs[n][2]); // return address
4916
4917 /* This works but uses a lot of memory...
4918 emit_readword((int)&last_count,ECX);
4919 emit_add(HOST_CCREG,ECX,EAX);
4920 emit_writeword(EAX,(int)&Count);
4921 emit_call((int)gen_interupt);
4922 emit_readword((int)&Count,HOST_CCREG);
4923 emit_readword((int)&next_interupt,EAX);
4924 emit_readword((int)&pending_exception,EBX);
4925 emit_writeword(EAX,(int)&last_count);
4926 emit_sub(HOST_CCREG,EAX,HOST_CCREG);
4927 emit_test(EBX,EBX);
4928 int jne_instr=(int)out;
4929 emit_jne(0);
4930 if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
4931 load_all_regs(branch_regs[i].regmap);
4932 emit_jmp(stubs[n][2]); // return address
4933 set_jump_target(jne_instr,(int)out);
4934 emit_readword((int)&pcaddr,EAX);
4935 // Call get_addr_ht instead of doing the hash table here.
4936 // This code is executed infrequently and takes up a lot of space
4937 // so smaller is better.
4938 emit_storereg(CCREG,HOST_CCREG);
4939 emit_pushreg(EAX);
4940 emit_call((int)get_addr_ht);
4941 emit_loadreg(CCREG,HOST_CCREG);
4942 emit_addimm(ESP,4,ESP);
4943 emit_jmpreg(EAX);*/
4944}
4945
4946add_to_linker(int addr,int target,int ext)
4947{
4948 link_addr[linkcount][0]=addr;
4949 link_addr[linkcount][1]=target;
4950 link_addr[linkcount][2]=ext;
4951 linkcount++;
4952}
4953
4954void ujump_assemble(int i,struct regstat *i_regs)
4955{
4956 signed char *i_regmap=i_regs->regmap;
4957 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
4958 address_generation(i+1,i_regs,regs[i].regmap_entry);
4959 #ifdef REG_PREFETCH
4960 int temp=get_reg(branch_regs[i].regmap,PTEMP);
4961 if(rt1[i]==31&&temp>=0)
4962 {
4963 int return_address=start+i*4+8;
4964 if(get_reg(branch_regs[i].regmap,31)>0)
4965 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
4966 }
4967 #endif
4968 ds_assemble(i+1,i_regs);
4969 uint64_t bc_unneeded=branch_regs[i].u;
4970 uint64_t bc_unneeded_upper=branch_regs[i].uu;
4971 bc_unneeded|=1|(1LL<<rt1[i]);
4972 bc_unneeded_upper|=1|(1LL<<rt1[i]);
4973 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
4974 bc_unneeded,bc_unneeded_upper);
4975 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
4976 if(rt1[i]==31) {
4977 int rt;
4978 unsigned int return_address;
4979 assert(rt1[i+1]!=31);
4980 assert(rt2[i+1]!=31);
4981 rt=get_reg(branch_regs[i].regmap,31);
4982 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
4983 //assert(rt>=0);
4984 return_address=start+i*4+8;
4985 if(rt>=0) {
4986 #ifdef USE_MINI_HT
4987 if(internal_branch(branch_regs[i].is32,return_address)) {
4988 int temp=rt+1;
4989 if(temp==EXCLUDE_REG||temp>=HOST_REGS||
4990 branch_regs[i].regmap[temp]>=0)
4991 {
4992 temp=get_reg(branch_regs[i].regmap,-1);
4993 }
4994 #ifdef HOST_TEMPREG
4995 if(temp<0) temp=HOST_TEMPREG;
4996 #endif
4997 if(temp>=0) do_miniht_insert(return_address,rt,temp);
4998 else emit_movimm(return_address,rt);
4999 }
5000 else
5001 #endif
5002 {
5003 #ifdef REG_PREFETCH
5004 if(temp>=0)
5005 {
5006 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5007 }
5008 #endif
5009 emit_movimm(return_address,rt); // PC into link register
5010 #ifdef IMM_PREFETCH
5011 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5012 #endif
5013 }
5014 }
5015 }
5016 int cc,adj;
5017 cc=get_reg(branch_regs[i].regmap,CCREG);
5018 assert(cc==HOST_CCREG);
5019 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5020 #ifdef REG_PREFETCH
5021 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5022 #endif
5023 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5024 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5025 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5026 if(internal_branch(branch_regs[i].is32,ba[i]))
5027 assem_debug("branch: internal\n");
5028 else
5029 assem_debug("branch: external\n");
5030 if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5031 ds_assemble_entry(i);
5032 }
5033 else {
5034 add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5035 emit_jmp(0);
5036 }
5037}
5038
5039void rjump_assemble(int i,struct regstat *i_regs)
5040{
5041 signed char *i_regmap=i_regs->regmap;
5042 int temp;
5043 int rs,cc,adj;
5044 rs=get_reg(branch_regs[i].regmap,rs1[i]);
5045 assert(rs>=0);
5046 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5047 // Delay slot abuse, make a copy of the branch address register
5048 temp=get_reg(branch_regs[i].regmap,RTEMP);
5049 assert(temp>=0);
5050 assert(regs[i].regmap[temp]==RTEMP);
5051 emit_mov(rs,temp);
5052 rs=temp;
5053 }
5054 address_generation(i+1,i_regs,regs[i].regmap_entry);
5055 #ifdef REG_PREFETCH
5056 if(rt1[i]==31)
5057 {
5058 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5059 int return_address=start+i*4+8;
5060 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5061 }
5062 }
5063 #endif
5064 #ifdef USE_MINI_HT
5065 if(rs1[i]==31) {
5066 int rh=get_reg(regs[i].regmap,RHASH);
5067 if(rh>=0) do_preload_rhash(rh);
5068 }
5069 #endif
5070 ds_assemble(i+1,i_regs);
5071 uint64_t bc_unneeded=branch_regs[i].u;
5072 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5073 bc_unneeded|=1|(1LL<<rt1[i]);
5074 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5075 bc_unneeded&=~(1LL<<rs1[i]);
5076 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5077 bc_unneeded,bc_unneeded_upper);
5078 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5067f341 5079 if(rt1[i]!=0) {
57871462 5080 int rt,return_address;
5067f341 5081 assert(rt1[i+1]!=rt1[i]);
5082 assert(rt2[i+1]!=rt1[i]);
5083 rt=get_reg(branch_regs[i].regmap,rt1[i]);
57871462 5084 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5085 assert(rt>=0);
5086 return_address=start+i*4+8;
5087 #ifdef REG_PREFETCH
5088 if(temp>=0)
5089 {
5090 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5091 }
5092 #endif
5093 emit_movimm(return_address,rt); // PC into link register
5094 #ifdef IMM_PREFETCH
5095 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5096 #endif
5097 }
5098 cc=get_reg(branch_regs[i].regmap,CCREG);
5099 assert(cc==HOST_CCREG);
5100 #ifdef USE_MINI_HT
5101 int rh=get_reg(branch_regs[i].regmap,RHASH);
5102 int ht=get_reg(branch_regs[i].regmap,RHTBL);
5103 if(rs1[i]==31) {
5104 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5105 do_preload_rhtbl(ht);
5106 do_rhash(rs,rh);
5107 }
5108 #endif
5109 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5110 #ifdef DESTRUCTIVE_WRITEBACK
5111 if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5112 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5113 emit_loadreg(rs1[i],rs);
5114 }
5115 }
5116 #endif
5117 #ifdef REG_PREFETCH
5118 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5119 #endif
5120 #ifdef USE_MINI_HT
5121 if(rs1[i]==31) {
5122 do_miniht_load(ht,rh);
5123 }
5124 #endif
5125 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5126 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5127 //assert(adj==0);
5128 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5129 add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5130 emit_jns(0);
5131 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5132 #ifdef USE_MINI_HT
5133 if(rs1[i]==31) {
5134 do_miniht_jump(rs,rh,ht);
5135 }
5136 else
5137 #endif
5138 {
5139 //if(rs!=EAX) emit_mov(rs,EAX);
5140 //emit_jmp((int)jump_vaddr_eax);
5141 emit_jmp(jump_vaddr_reg[rs]);
5142 }
5143 /* Check hash table
5144 temp=!rs;
5145 emit_mov(rs,temp);
5146 emit_shrimm(rs,16,rs);
5147 emit_xor(temp,rs,rs);
5148 emit_movzwl_reg(rs,rs);
5149 emit_shlimm(rs,4,rs);
5150 emit_cmpmem_indexed((int)hash_table,rs,temp);
5151 emit_jne((int)out+14);
5152 emit_readword_indexed((int)hash_table+4,rs,rs);
5153 emit_jmpreg(rs);
5154 emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5155 emit_addimm_no_flags(8,rs);
5156 emit_jeq((int)out-17);
5157 // No hit on hash table, call compiler
5158 emit_pushreg(temp);
5159//DEBUG >
5160#ifdef DEBUG_CYCLE_COUNT
5161 emit_readword((int)&last_count,ECX);
5162 emit_add(HOST_CCREG,ECX,HOST_CCREG);
5163 emit_readword((int)&next_interupt,ECX);
5164 emit_writeword(HOST_CCREG,(int)&Count);
5165 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5166 emit_writeword(ECX,(int)&last_count);
5167#endif
5168//DEBUG <
5169 emit_storereg(CCREG,HOST_CCREG);
5170 emit_call((int)get_addr);
5171 emit_loadreg(CCREG,HOST_CCREG);
5172 emit_addimm(ESP,4,ESP);
5173 emit_jmpreg(EAX);*/
5174 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5175 if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5176 #endif
5177}
5178
5179void cjump_assemble(int i,struct regstat *i_regs)
5180{
5181 signed char *i_regmap=i_regs->regmap;
5182 int cc;
5183 int match;
5184 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5185 assem_debug("match=%d\n",match);
5186 int s1h,s1l,s2h,s2l;
5187 int prev_cop1_usable=cop1_usable;
5188 int unconditional=0,nop=0;
5189 int only32=0;
5190 int ooo=1;
5191 int invert=0;
5192 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5193 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5194 if(likely[i]) ooo=0;
5195 if(!match) invert=1;
5196 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5197 if(i>(ba[i]-start)>>2) invert=1;
5198 #endif
5199
5200 if(ooo)
5201 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
5202 (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1])))
5203 {
5204 // Write-after-read dependency prevents out of order execution
5205 // First test branch condition, then execute delay slot, then branch
5206 ooo=0;
5207 }
5208
5209 if(ooo) {
5210 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5211 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5212 s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5213 s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5214 }
5215 else {
5216 s1l=get_reg(i_regmap,rs1[i]);
5217 s1h=get_reg(i_regmap,rs1[i]|64);
5218 s2l=get_reg(i_regmap,rs2[i]);
5219 s2h=get_reg(i_regmap,rs2[i]|64);
5220 }
5221 if(rs1[i]==0&&rs2[i]==0)
5222 {
5223 if(opcode[i]&1) nop=1;
5224 else unconditional=1;
5225 //assert(opcode[i]!=5);
5226 //assert(opcode[i]!=7);
5227 //assert(opcode[i]!=0x15);
5228 //assert(opcode[i]!=0x17);
5229 }
5230 else if(rs1[i]==0)
5231 {
5232 s1l=s2l;s1h=s2h;
5233 s2l=s2h=-1;
5234 only32=(regs[i].was32>>rs2[i])&1;
5235 }
5236 else if(rs2[i]==0)
5237 {
5238 s2l=s2h=-1;
5239 only32=(regs[i].was32>>rs1[i])&1;
5240 }
5241 else {
5242 only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5243 }
5244
5245 if(ooo) {
5246 // Out of order execution (delay slot first)
5247 //printf("OOOE\n");
5248 address_generation(i+1,i_regs,regs[i].regmap_entry);
5249 ds_assemble(i+1,i_regs);
5250 int adj;
5251 uint64_t bc_unneeded=branch_regs[i].u;
5252 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5253 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5254 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5255 bc_unneeded|=1;
5256 bc_unneeded_upper|=1;
5257 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5258 bc_unneeded,bc_unneeded_upper);
5259 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5260 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5261 cc=get_reg(branch_regs[i].regmap,CCREG);
5262 assert(cc==HOST_CCREG);
5263 if(unconditional)
5264 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5265 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5266 //assem_debug("cycle count (adj)\n");
5267 if(unconditional) {
5268 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5269 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5270 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5271 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5272 if(internal)
5273 assem_debug("branch: internal\n");
5274 else
5275 assem_debug("branch: external\n");
5276 if(internal&&is_ds[(ba[i]-start)>>2]) {
5277 ds_assemble_entry(i);
5278 }
5279 else {
5280 add_to_linker((int)out,ba[i],internal);
5281 emit_jmp(0);
5282 }
5283 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5284 if(((u_int)out)&7) emit_addnop(0);
5285 #endif
5286 }
5287 }
5288 else if(nop) {
5289 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5290 int jaddr=(int)out;
5291 emit_jns(0);
5292 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5293 }
5294 else {
5295 int taken=0,nottaken=0,nottaken1=0;
5296 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5297 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5298 if(!only32)
5299 {
5300 assert(s1h>=0);
5301 if(opcode[i]==4) // BEQ
5302 {
5303 if(s2h>=0) emit_cmp(s1h,s2h);
5304 else emit_test(s1h,s1h);
5305 nottaken1=(int)out;
5306 emit_jne(1);
5307 }
5308 if(opcode[i]==5) // BNE
5309 {
5310 if(s2h>=0) emit_cmp(s1h,s2h);
5311 else emit_test(s1h,s1h);
5312 if(invert) taken=(int)out;
5313 else add_to_linker((int)out,ba[i],internal);
5314 emit_jne(0);
5315 }
5316 if(opcode[i]==6) // BLEZ
5317 {
5318 emit_test(s1h,s1h);
5319 if(invert) taken=(int)out;
5320 else add_to_linker((int)out,ba[i],internal);
5321 emit_js(0);
5322 nottaken1=(int)out;
5323 emit_jne(1);
5324 }
5325 if(opcode[i]==7) // BGTZ
5326 {
5327 emit_test(s1h,s1h);
5328 nottaken1=(int)out;
5329 emit_js(1);
5330 if(invert) taken=(int)out;
5331 else add_to_linker((int)out,ba[i],internal);
5332 emit_jne(0);
5333 }
5334 } // if(!only32)
5335
5336 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5337 assert(s1l>=0);
5338 if(opcode[i]==4) // BEQ
5339 {
5340 if(s2l>=0) emit_cmp(s1l,s2l);
5341 else emit_test(s1l,s1l);
5342 if(invert){
5343 nottaken=(int)out;
5344 emit_jne(1);
5345 }else{
5346 add_to_linker((int)out,ba[i],internal);
5347 emit_jeq(0);
5348 }
5349 }
5350 if(opcode[i]==5) // BNE
5351 {
5352 if(s2l>=0) emit_cmp(s1l,s2l);
5353 else emit_test(s1l,s1l);
5354 if(invert){
5355 nottaken=(int)out;
5356 emit_jeq(1);
5357 }else{
5358 add_to_linker((int)out,ba[i],internal);
5359 emit_jne(0);
5360 }
5361 }
5362 if(opcode[i]==6) // BLEZ
5363 {
5364 emit_cmpimm(s1l,1);
5365 if(invert){
5366 nottaken=(int)out;
5367 emit_jge(1);
5368 }else{
5369 add_to_linker((int)out,ba[i],internal);
5370 emit_jl(0);
5371 }
5372 }
5373 if(opcode[i]==7) // BGTZ
5374 {
5375 emit_cmpimm(s1l,1);
5376 if(invert){
5377 nottaken=(int)out;
5378 emit_jl(1);
5379 }else{
5380 add_to_linker((int)out,ba[i],internal);
5381 emit_jge(0);
5382 }
5383 }
5384 if(invert) {
5385 if(taken) set_jump_target(taken,(int)out);
5386 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5387 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5388 if(adj) {
5389 emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5390 add_to_linker((int)out,ba[i],internal);
5391 }else{
5392 emit_addnop(13);
5393 add_to_linker((int)out,ba[i],internal*2);
5394 }
5395 emit_jmp(0);
5396 }else
5397 #endif
5398 {
5399 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5400 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5401 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5402 if(internal)
5403 assem_debug("branch: internal\n");
5404 else
5405 assem_debug("branch: external\n");
5406 if(internal&&is_ds[(ba[i]-start)>>2]) {
5407 ds_assemble_entry(i);
5408 }
5409 else {
5410 add_to_linker((int)out,ba[i],internal);
5411 emit_jmp(0);
5412 }
5413 }
5414 set_jump_target(nottaken,(int)out);
5415 }
5416
5417 if(nottaken1) set_jump_target(nottaken1,(int)out);
5418 if(adj) {
5419 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5420 }
5421 } // (!unconditional)
5422 } // if(ooo)
5423 else
5424 {
5425 // In-order execution (branch first)
5426 //if(likely[i]) printf("IOL\n");
5427 //else
5428 //printf("IOE\n");
5429 int taken=0,nottaken=0,nottaken1=0;
5430 if(!unconditional&&!nop) {
5431 if(!only32)
5432 {
5433 assert(s1h>=0);
5434 if((opcode[i]&0x2f)==4) // BEQ
5435 {
5436 if(s2h>=0) emit_cmp(s1h,s2h);
5437 else emit_test(s1h,s1h);
5438 nottaken1=(int)out;
5439 emit_jne(2);
5440 }
5441 if((opcode[i]&0x2f)==5) // BNE
5442 {
5443 if(s2h>=0) emit_cmp(s1h,s2h);
5444 else emit_test(s1h,s1h);
5445 taken=(int)out;
5446 emit_jne(1);
5447 }
5448 if((opcode[i]&0x2f)==6) // BLEZ
5449 {
5450 emit_test(s1h,s1h);
5451 taken=(int)out;
5452 emit_js(1);
5453 nottaken1=(int)out;
5454 emit_jne(2);
5455 }
5456 if((opcode[i]&0x2f)==7) // BGTZ
5457 {
5458 emit_test(s1h,s1h);
5459 nottaken1=(int)out;
5460 emit_js(2);
5461 taken=(int)out;
5462 emit_jne(1);
5463 }
5464 } // if(!only32)
5465
5466 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5467 assert(s1l>=0);
5468 if((opcode[i]&0x2f)==4) // BEQ
5469 {
5470 if(s2l>=0) emit_cmp(s1l,s2l);
5471 else emit_test(s1l,s1l);
5472 nottaken=(int)out;
5473 emit_jne(2);
5474 }
5475 if((opcode[i]&0x2f)==5) // BNE
5476 {
5477 if(s2l>=0) emit_cmp(s1l,s2l);
5478 else emit_test(s1l,s1l);
5479 nottaken=(int)out;
5480 emit_jeq(2);
5481 }
5482 if((opcode[i]&0x2f)==6) // BLEZ
5483 {
5484 emit_cmpimm(s1l,1);
5485 nottaken=(int)out;
5486 emit_jge(2);
5487 }
5488 if((opcode[i]&0x2f)==7) // BGTZ
5489 {
5490 emit_cmpimm(s1l,1);
5491 nottaken=(int)out;
5492 emit_jl(2);
5493 }
5494 } // if(!unconditional)
5495 int adj;
5496 uint64_t ds_unneeded=branch_regs[i].u;
5497 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5498 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5499 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5500 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5501 ds_unneeded|=1;
5502 ds_unneeded_upper|=1;
5503 // branch taken
5504 if(!nop) {
5505 if(taken) set_jump_target(taken,(int)out);
5506 assem_debug("1:\n");
5507 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5508 ds_unneeded,ds_unneeded_upper);
5509 // load regs
5510 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5511 address_generation(i+1,&branch_regs[i],0);
5512 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5513 ds_assemble(i+1,&branch_regs[i]);
5514 cc=get_reg(branch_regs[i].regmap,CCREG);
5515 if(cc==-1) {
5516 emit_loadreg(CCREG,cc=HOST_CCREG);
5517 // CHECK: Is the following instruction (fall thru) allocated ok?
5518 }
5519 assert(cc==HOST_CCREG);
5520 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5521 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5522 assem_debug("cycle count (adj)\n");
5523 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5524 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5525 if(internal)
5526 assem_debug("branch: internal\n");
5527 else
5528 assem_debug("branch: external\n");
5529 if(internal&&is_ds[(ba[i]-start)>>2]) {
5530 ds_assemble_entry(i);
5531 }
5532 else {
5533 add_to_linker((int)out,ba[i],internal);
5534 emit_jmp(0);
5535 }
5536 }
5537 // branch not taken
5538 cop1_usable=prev_cop1_usable;
5539 if(!unconditional) {
5540 if(nottaken1) set_jump_target(nottaken1,(int)out);
5541 set_jump_target(nottaken,(int)out);
5542 assem_debug("2:\n");
5543 if(!likely[i]) {
5544 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5545 ds_unneeded,ds_unneeded_upper);
5546 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5547 address_generation(i+1,&branch_regs[i],0);
5548 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5549 ds_assemble(i+1,&branch_regs[i]);
5550 }
5551 cc=get_reg(branch_regs[i].regmap,CCREG);
5552 if(cc==-1&&!likely[i]) {
5553 // Cycle count isn't in a register, temporarily load it then write it out
5554 emit_loadreg(CCREG,HOST_CCREG);
5555 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5556 int jaddr=(int)out;
5557 emit_jns(0);
5558 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5559 emit_storereg(CCREG,HOST_CCREG);
5560 }
5561 else{
5562 cc=get_reg(i_regmap,CCREG);
5563 assert(cc==HOST_CCREG);
5564 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5565 int jaddr=(int)out;
5566 emit_jns(0);
5567 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5568 }
5569 }
5570 }
5571}
5572
5573void sjump_assemble(int i,struct regstat *i_regs)
5574{
5575 signed char *i_regmap=i_regs->regmap;
5576 int cc;
5577 int match;
5578 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5579 assem_debug("smatch=%d\n",match);
5580 int s1h,s1l;
5581 int prev_cop1_usable=cop1_usable;
5582 int unconditional=0,nevertaken=0;
5583 int only32=0;
5584 int ooo=1;
5585 int invert=0;
5586 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5587 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5588 if(likely[i]) ooo=0;
5589 if(!match) invert=1;
5590 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5591 if(i>(ba[i]-start)>>2) invert=1;
5592 #endif
5593
5594 //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
5595 assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
5596
5597 if(ooo)
5598 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))
5599 {
5600 // Write-after-read dependency prevents out of order execution
5601 // First test branch condition, then execute delay slot, then branch
5602 ooo=0;
5603 }
5604 // TODO: Conditional branches w/link must execute in-order so that
5605 // condition test and write to r31 occur before cycle count test
5606
5607 if(ooo) {
5608 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5609 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5610 }
5611 else {
5612 s1l=get_reg(i_regmap,rs1[i]);
5613 s1h=get_reg(i_regmap,rs1[i]|64);
5614 }
5615 if(rs1[i]==0)
5616 {
5617 if(opcode2[i]&1) unconditional=1;
5618 else nevertaken=1;
5619 // These are never taken (r0 is never less than zero)
5620 //assert(opcode2[i]!=0);
5621 //assert(opcode2[i]!=2);
5622 //assert(opcode2[i]!=0x10);
5623 //assert(opcode2[i]!=0x12);
5624 }
5625 else {
5626 only32=(regs[i].was32>>rs1[i])&1;
5627 }
5628
5629 if(ooo) {
5630 // Out of order execution (delay slot first)
5631 //printf("OOOE\n");
5632 address_generation(i+1,i_regs,regs[i].regmap_entry);
5633 ds_assemble(i+1,i_regs);
5634 int adj;
5635 uint64_t bc_unneeded=branch_regs[i].u;
5636 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5637 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5638 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5639 bc_unneeded|=1;
5640 bc_unneeded_upper|=1;
5641 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5642 bc_unneeded,bc_unneeded_upper);
5643 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5644 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5645 if(rt1[i]==31) {
5646 int rt,return_address;
5647 assert(rt1[i+1]!=31);
5648 assert(rt2[i+1]!=31);
5649 rt=get_reg(branch_regs[i].regmap,31);
5650 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5651 if(rt>=0) {
5652 // Save the PC even if the branch is not taken
5653 return_address=start+i*4+8;
5654 emit_movimm(return_address,rt); // PC into link register
5655 #ifdef IMM_PREFETCH
5656 if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5657 #endif
5658 }
5659 }
5660 cc=get_reg(branch_regs[i].regmap,CCREG);
5661 assert(cc==HOST_CCREG);
5662 if(unconditional)
5663 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5664 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5665 assem_debug("cycle count (adj)\n");
5666 if(unconditional) {
5667 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5668 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5669 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5670 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5671 if(internal)
5672 assem_debug("branch: internal\n");
5673 else
5674 assem_debug("branch: external\n");
5675 if(internal&&is_ds[(ba[i]-start)>>2]) {
5676 ds_assemble_entry(i);
5677 }
5678 else {
5679 add_to_linker((int)out,ba[i],internal);
5680 emit_jmp(0);
5681 }
5682 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5683 if(((u_int)out)&7) emit_addnop(0);
5684 #endif
5685 }
5686 }
5687 else if(nevertaken) {
5688 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5689 int jaddr=(int)out;
5690 emit_jns(0);
5691 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5692 }
5693 else {
5694 int nottaken=0;
5695 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5696 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5697 if(!only32)
5698 {
5699 assert(s1h>=0);
5700 if(opcode2[i]==0) // BLTZ
5701 {
5702 emit_test(s1h,s1h);
5703 if(invert){
5704 nottaken=(int)out;
5705 emit_jns(1);
5706 }else{
5707 add_to_linker((int)out,ba[i],internal);
5708 emit_js(0);
5709 }
5710 }
5711 if(opcode2[i]==1) // BGEZ
5712 {
5713 emit_test(s1h,s1h);
5714 if(invert){
5715 nottaken=(int)out;
5716 emit_js(1);
5717 }else{
5718 add_to_linker((int)out,ba[i],internal);
5719 emit_jns(0);
5720 }
5721 }
5722 } // if(!only32)
5723 else
5724 {
5725 assert(s1l>=0);
5726 if(opcode2[i]==0) // BLTZ
5727 {
5728 emit_test(s1l,s1l);
5729 if(invert){
5730 nottaken=(int)out;
5731 emit_jns(1);
5732 }else{
5733 add_to_linker((int)out,ba[i],internal);
5734 emit_js(0);
5735 }
5736 }
5737 if(opcode2[i]==1) // BGEZ
5738 {
5739 emit_test(s1l,s1l);
5740 if(invert){
5741 nottaken=(int)out;
5742 emit_js(1);
5743 }else{
5744 add_to_linker((int)out,ba[i],internal);
5745 emit_jns(0);
5746 }
5747 }
5748 } // if(!only32)
5749
5750 if(invert) {
5751 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5752 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5753 if(adj) {
5754 emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5755 add_to_linker((int)out,ba[i],internal);
5756 }else{
5757 emit_addnop(13);
5758 add_to_linker((int)out,ba[i],internal*2);
5759 }
5760 emit_jmp(0);
5761 }else
5762 #endif
5763 {
5764 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5765 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5766 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5767 if(internal)
5768 assem_debug("branch: internal\n");
5769 else
5770 assem_debug("branch: external\n");
5771 if(internal&&is_ds[(ba[i]-start)>>2]) {
5772 ds_assemble_entry(i);
5773 }
5774 else {
5775 add_to_linker((int)out,ba[i],internal);
5776 emit_jmp(0);
5777 }
5778 }
5779 set_jump_target(nottaken,(int)out);
5780 }
5781
5782 if(adj) {
5783 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5784 }
5785 } // (!unconditional)
5786 } // if(ooo)
5787 else
5788 {
5789 // In-order execution (branch first)
5790 //printf("IOE\n");
5791 int nottaken=0;
5792 if(!unconditional) {
5793 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5794 if(!only32)
5795 {
5796 assert(s1h>=0);
5797 if((opcode2[i]&0x1d)==0) // BLTZ/BLTZL
5798 {
5799 emit_test(s1h,s1h);
5800 nottaken=(int)out;
5801 emit_jns(1);
5802 }
5803 if((opcode2[i]&0x1d)==1) // BGEZ/BGEZL
5804 {
5805 emit_test(s1h,s1h);
5806 nottaken=(int)out;
5807 emit_js(1);
5808 }
5809 } // if(!only32)
5810 else
5811 {
5812 assert(s1l>=0);
5813 if((opcode2[i]&0x1d)==0) // BLTZ/BLTZL
5814 {
5815 emit_test(s1l,s1l);
5816 nottaken=(int)out;
5817 emit_jns(1);
5818 }
5819 if((opcode2[i]&0x1d)==1) // BGEZ/BGEZL
5820 {
5821 emit_test(s1l,s1l);
5822 nottaken=(int)out;
5823 emit_js(1);
5824 }
5825 }
5826 } // if(!unconditional)
5827 int adj;
5828 uint64_t ds_unneeded=branch_regs[i].u;
5829 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5830 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5831 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5832 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5833 ds_unneeded|=1;
5834 ds_unneeded_upper|=1;
5835 // branch taken
5836 if(!nevertaken) {
5837 //assem_debug("1:\n");
5838 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5839 ds_unneeded,ds_unneeded_upper);
5840 // load regs
5841 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5842 address_generation(i+1,&branch_regs[i],0);
5843 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5844 ds_assemble(i+1,&branch_regs[i]);
5845 cc=get_reg(branch_regs[i].regmap,CCREG);
5846 if(cc==-1) {
5847 emit_loadreg(CCREG,cc=HOST_CCREG);
5848 // CHECK: Is the following instruction (fall thru) allocated ok?
5849 }
5850 assert(cc==HOST_CCREG);
5851 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5852 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5853 assem_debug("cycle count (adj)\n");
5854 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5855 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5856 if(internal)
5857 assem_debug("branch: internal\n");
5858 else
5859 assem_debug("branch: external\n");
5860 if(internal&&is_ds[(ba[i]-start)>>2]) {
5861 ds_assemble_entry(i);
5862 }
5863 else {
5864 add_to_linker((int)out,ba[i],internal);
5865 emit_jmp(0);
5866 }
5867 }
5868 // branch not taken
5869 cop1_usable=prev_cop1_usable;
5870 if(!unconditional) {
5871 set_jump_target(nottaken,(int)out);
5872 assem_debug("1:\n");
5873 if(!likely[i]) {
5874 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5875 ds_unneeded,ds_unneeded_upper);
5876 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5877 address_generation(i+1,&branch_regs[i],0);
5878 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5879 ds_assemble(i+1,&branch_regs[i]);
5880 }
5881 cc=get_reg(branch_regs[i].regmap,CCREG);
5882 if(cc==-1&&!likely[i]) {
5883 // Cycle count isn't in a register, temporarily load it then write it out
5884 emit_loadreg(CCREG,HOST_CCREG);
5885 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5886 int jaddr=(int)out;
5887 emit_jns(0);
5888 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5889 emit_storereg(CCREG,HOST_CCREG);
5890 }
5891 else{
5892 cc=get_reg(i_regmap,CCREG);
5893 assert(cc==HOST_CCREG);
5894 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5895 int jaddr=(int)out;
5896 emit_jns(0);
5897 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5898 }
5899 }
5900 }
5901}
5902
5903void fjump_assemble(int i,struct regstat *i_regs)
5904{
5905 signed char *i_regmap=i_regs->regmap;
5906 int cc;
5907 int match;
5908 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5909 assem_debug("fmatch=%d\n",match);
5910 int fs,cs;
5911 int eaddr;
5912 int ooo=1;
5913 int invert=0;
5914 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5915 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5916 if(likely[i]) ooo=0;
5917 if(!match) invert=1;
5918 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5919 if(i>(ba[i]-start)>>2) invert=1;
5920 #endif
5921
5922 if(ooo)
5923 if(itype[i+1]==FCOMP)
5924 {
5925 // Write-after-read dependency prevents out of order execution
5926 // First test branch condition, then execute delay slot, then branch
5927 ooo=0;
5928 }
5929
5930 if(ooo) {
5931 fs=get_reg(branch_regs[i].regmap,FSREG);
5932 address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
5933 }
5934 else {
5935 fs=get_reg(i_regmap,FSREG);
5936 }
5937
5938 // Check cop1 unusable
5939 if(!cop1_usable) {
5940 cs=get_reg(i_regmap,CSREG);
5941 assert(cs>=0);
5942 emit_testimm(cs,0x20000000);
5943 eaddr=(int)out;
5944 emit_jeq(0);
5945 add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
5946 cop1_usable=1;
5947 }
5948
5949 if(ooo) {
5950 // Out of order execution (delay slot first)
5951 //printf("OOOE\n");
5952 ds_assemble(i+1,i_regs);
5953 int adj;
5954 uint64_t bc_unneeded=branch_regs[i].u;
5955 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5956 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5957 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5958 bc_unneeded|=1;
5959 bc_unneeded_upper|=1;
5960 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5961 bc_unneeded,bc_unneeded_upper);
5962 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5963 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5964 cc=get_reg(branch_regs[i].regmap,CCREG);
5965 assert(cc==HOST_CCREG);
5966 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5967 assem_debug("cycle count (adj)\n");
5968 if(1) {
5969 int nottaken=0;
5970 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5971 if(1) {
5972 assert(fs>=0);
5973 emit_testimm(fs,0x800000);
5974 if(source[i]&0x10000) // BC1T
5975 {
5976 if(invert){
5977 nottaken=(int)out;
5978 emit_jeq(1);
5979 }else{
5980 add_to_linker((int)out,ba[i],internal);
5981 emit_jne(0);
5982 }
5983 }
5984 else // BC1F
5985 if(invert){
5986 nottaken=(int)out;
5987 emit_jne(1);
5988 }else{
5989 add_to_linker((int)out,ba[i],internal);
5990 emit_jeq(0);
5991 }
5992 {
5993 }
5994 } // if(!only32)
5995
5996 if(invert) {
5997 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5998 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5999 else if(match) emit_addnop(13);
6000 #endif
6001 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6002 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6003 if(internal)
6004 assem_debug("branch: internal\n");
6005 else
6006 assem_debug("branch: external\n");
6007 if(internal&&is_ds[(ba[i]-start)>>2]) {
6008 ds_assemble_entry(i);
6009 }
6010 else {
6011 add_to_linker((int)out,ba[i],internal);
6012 emit_jmp(0);
6013 }
6014 set_jump_target(nottaken,(int)out);
6015 }
6016
6017 if(adj) {
6018 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
6019 }
6020 } // (!unconditional)
6021 } // if(ooo)
6022 else
6023 {
6024 // In-order execution (branch first)
6025 //printf("IOE\n");
6026 int nottaken=0;
6027 if(1) {
6028 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6029 if(1) {
6030 assert(fs>=0);
6031 emit_testimm(fs,0x800000);
6032 if(source[i]&0x10000) // BC1T
6033 {
6034 nottaken=(int)out;
6035 emit_jeq(1);
6036 }
6037 else // BC1F
6038 {
6039 nottaken=(int)out;
6040 emit_jne(1);
6041 }
6042 }
6043 } // if(!unconditional)
6044 int adj;
6045 uint64_t ds_unneeded=branch_regs[i].u;
6046 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6047 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6048 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6049 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6050 ds_unneeded|=1;
6051 ds_unneeded_upper|=1;
6052 // branch taken
6053 //assem_debug("1:\n");
6054 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6055 ds_unneeded,ds_unneeded_upper);
6056 // load regs
6057 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6058 address_generation(i+1,&branch_regs[i],0);
6059 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6060 ds_assemble(i+1,&branch_regs[i]);
6061 cc=get_reg(branch_regs[i].regmap,CCREG);
6062 if(cc==-1) {
6063 emit_loadreg(CCREG,cc=HOST_CCREG);
6064 // CHECK: Is the following instruction (fall thru) allocated ok?
6065 }
6066 assert(cc==HOST_CCREG);
6067 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6068 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6069 assem_debug("cycle count (adj)\n");
6070 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6071 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6072 if(internal)
6073 assem_debug("branch: internal\n");
6074 else
6075 assem_debug("branch: external\n");
6076 if(internal&&is_ds[(ba[i]-start)>>2]) {
6077 ds_assemble_entry(i);
6078 }
6079 else {
6080 add_to_linker((int)out,ba[i],internal);
6081 emit_jmp(0);
6082 }
6083
6084 // branch not taken
6085 if(1) { // <- FIXME (don't need this)
6086 set_jump_target(nottaken,(int)out);
6087 assem_debug("1:\n");
6088 if(!likely[i]) {
6089 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6090 ds_unneeded,ds_unneeded_upper);
6091 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6092 address_generation(i+1,&branch_regs[i],0);
6093 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6094 ds_assemble(i+1,&branch_regs[i]);
6095 }
6096 cc=get_reg(branch_regs[i].regmap,CCREG);
6097 if(cc==-1&&!likely[i]) {
6098 // Cycle count isn't in a register, temporarily load it then write it out
6099 emit_loadreg(CCREG,HOST_CCREG);
6100 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6101 int jaddr=(int)out;
6102 emit_jns(0);
6103 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6104 emit_storereg(CCREG,HOST_CCREG);
6105 }
6106 else{
6107 cc=get_reg(i_regmap,CCREG);
6108 assert(cc==HOST_CCREG);
6109 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6110 int jaddr=(int)out;
6111 emit_jns(0);
6112 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6113 }
6114 }
6115 }
6116}
6117
6118static void pagespan_assemble(int i,struct regstat *i_regs)
6119{
6120 int s1l=get_reg(i_regs->regmap,rs1[i]);
6121 int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6122 int s2l=get_reg(i_regs->regmap,rs2[i]);
6123 int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6124 void *nt_branch=NULL;
6125 int taken=0;
6126 int nottaken=0;
6127 int unconditional=0;
6128 if(rs1[i]==0)
6129 {
6130 s1l=s2l;s1h=s2h;
6131 s2l=s2h=-1;
6132 }
6133 else if(rs2[i]==0)
6134 {
6135 s2l=s2h=-1;
6136 }
6137 if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6138 s1h=s2h=-1;
6139 }
6140 int hr=0;
6141 int addr,alt,ntaddr;
6142 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6143 else {
6144 while(hr<HOST_REGS)
6145 {
6146 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6147 (i_regs->regmap[hr]&63)!=rs1[i] &&
6148 (i_regs->regmap[hr]&63)!=rs2[i] )
6149 {
6150 addr=hr++;break;
6151 }
6152 hr++;
6153 }
6154 }
6155 while(hr<HOST_REGS)
6156 {
6157 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6158 (i_regs->regmap[hr]&63)!=rs1[i] &&
6159 (i_regs->regmap[hr]&63)!=rs2[i] )
6160 {
6161 alt=hr++;break;
6162 }
6163 hr++;
6164 }
6165 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6166 {
6167 while(hr<HOST_REGS)
6168 {
6169 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6170 (i_regs->regmap[hr]&63)!=rs1[i] &&
6171 (i_regs->regmap[hr]&63)!=rs2[i] )
6172 {
6173 ntaddr=hr;break;
6174 }
6175 hr++;
6176 }
6177 }
6178 assert(hr<HOST_REGS);
6179 if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6180 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6181 }
6182 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6183 if(opcode[i]==2) // J
6184 {
6185 unconditional=1;
6186 }
6187 if(opcode[i]==3) // JAL
6188 {
6189 // TODO: mini_ht
6190 int rt=get_reg(i_regs->regmap,31);
6191 emit_movimm(start+i*4+8,rt);
6192 unconditional=1;
6193 }
6194 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6195 {
6196 emit_mov(s1l,addr);
6197 if(opcode2[i]==9) // JALR
6198 {
5067f341 6199 int rt=get_reg(i_regs->regmap,rt1[i]);
57871462 6200 emit_movimm(start+i*4+8,rt);
6201 }
6202 }
6203 if((opcode[i]&0x3f)==4) // BEQ
6204 {
6205 if(rs1[i]==rs2[i])
6206 {
6207 unconditional=1;
6208 }
6209 else
6210 #ifdef HAVE_CMOV_IMM
6211 if(s1h<0) {
6212 if(s2l>=0) emit_cmp(s1l,s2l);
6213 else emit_test(s1l,s1l);
6214 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6215 }
6216 else
6217 #endif
6218 {
6219 assert(s1l>=0);
6220 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6221 if(s1h>=0) {
6222 if(s2h>=0) emit_cmp(s1h,s2h);
6223 else emit_test(s1h,s1h);
6224 emit_cmovne_reg(alt,addr);
6225 }
6226 if(s2l>=0) emit_cmp(s1l,s2l);
6227 else emit_test(s1l,s1l);
6228 emit_cmovne_reg(alt,addr);
6229 }
6230 }
6231 if((opcode[i]&0x3f)==5) // BNE
6232 {
6233 #ifdef HAVE_CMOV_IMM
6234 if(s1h<0) {
6235 if(s2l>=0) emit_cmp(s1l,s2l);
6236 else emit_test(s1l,s1l);
6237 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6238 }
6239 else
6240 #endif
6241 {
6242 assert(s1l>=0);
6243 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6244 if(s1h>=0) {
6245 if(s2h>=0) emit_cmp(s1h,s2h);
6246 else emit_test(s1h,s1h);
6247 emit_cmovne_reg(alt,addr);
6248 }
6249 if(s2l>=0) emit_cmp(s1l,s2l);
6250 else emit_test(s1l,s1l);
6251 emit_cmovne_reg(alt,addr);
6252 }
6253 }
6254 if((opcode[i]&0x3f)==0x14) // BEQL
6255 {
6256 if(s1h>=0) {
6257 if(s2h>=0) emit_cmp(s1h,s2h);
6258 else emit_test(s1h,s1h);
6259 nottaken=(int)out;
6260 emit_jne(0);
6261 }
6262 if(s2l>=0) emit_cmp(s1l,s2l);
6263 else emit_test(s1l,s1l);
6264 if(nottaken) set_jump_target(nottaken,(int)out);
6265 nottaken=(int)out;
6266 emit_jne(0);
6267 }
6268 if((opcode[i]&0x3f)==0x15) // BNEL
6269 {
6270 if(s1h>=0) {
6271 if(s2h>=0) emit_cmp(s1h,s2h);
6272 else emit_test(s1h,s1h);
6273 taken=(int)out;
6274 emit_jne(0);
6275 }
6276 if(s2l>=0) emit_cmp(s1l,s2l);
6277 else emit_test(s1l,s1l);
6278 nottaken=(int)out;
6279 emit_jeq(0);
6280 if(taken) set_jump_target(taken,(int)out);
6281 }
6282 if((opcode[i]&0x3f)==6) // BLEZ
6283 {
6284 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6285 emit_cmpimm(s1l,1);
6286 if(s1h>=0) emit_mov(addr,ntaddr);
6287 emit_cmovl_reg(alt,addr);
6288 if(s1h>=0) {
6289 emit_test(s1h,s1h);
6290 emit_cmovne_reg(ntaddr,addr);
6291 emit_cmovs_reg(alt,addr);
6292 }
6293 }
6294 if((opcode[i]&0x3f)==7) // BGTZ
6295 {
6296 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6297 emit_cmpimm(s1l,1);
6298 if(s1h>=0) emit_mov(addr,alt);
6299 emit_cmovl_reg(ntaddr,addr);
6300 if(s1h>=0) {
6301 emit_test(s1h,s1h);
6302 emit_cmovne_reg(alt,addr);
6303 emit_cmovs_reg(ntaddr,addr);
6304 }
6305 }
6306 if((opcode[i]&0x3f)==0x16) // BLEZL
6307 {
6308 assert((opcode[i]&0x3f)!=0x16);
6309 }
6310 if((opcode[i]&0x3f)==0x17) // BGTZL
6311 {
6312 assert((opcode[i]&0x3f)!=0x17);
6313 }
6314 assert(opcode[i]!=1); // BLTZ/BGEZ
6315
6316 //FIXME: Check CSREG
6317 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6318 if((source[i]&0x30000)==0) // BC1F
6319 {
6320 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6321 emit_testimm(s1l,0x800000);
6322 emit_cmovne_reg(alt,addr);
6323 }
6324 if((source[i]&0x30000)==0x10000) // BC1T
6325 {
6326 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6327 emit_testimm(s1l,0x800000);
6328 emit_cmovne_reg(alt,addr);
6329 }
6330 if((source[i]&0x30000)==0x20000) // BC1FL
6331 {
6332 emit_testimm(s1l,0x800000);
6333 nottaken=(int)out;
6334 emit_jne(0);
6335 }
6336 if((source[i]&0x30000)==0x30000) // BC1TL
6337 {
6338 emit_testimm(s1l,0x800000);
6339 nottaken=(int)out;
6340 emit_jeq(0);
6341 }
6342 }
6343
6344 assert(i_regs->regmap[HOST_CCREG]==CCREG);
6345 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6346 if(likely[i]||unconditional)
6347 {
6348 emit_movimm(ba[i],HOST_BTREG);
6349 }
6350 else if(addr!=HOST_BTREG)
6351 {
6352 emit_mov(addr,HOST_BTREG);
6353 }
6354 void *branch_addr=out;
6355 emit_jmp(0);
6356 int target_addr=start+i*4+5;
6357 void *stub=out;
6358 void *compiled_target_addr=check_addr(target_addr);
6359 emit_extjump_ds((int)branch_addr,target_addr);
6360 if(compiled_target_addr) {
6361 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6362 add_link(target_addr,stub);
6363 }
6364 else set_jump_target((int)branch_addr,(int)stub);
6365 if(likely[i]) {
6366 // Not-taken path
6367 set_jump_target((int)nottaken,(int)out);
6368 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6369 void *branch_addr=out;
6370 emit_jmp(0);
6371 int target_addr=start+i*4+8;
6372 void *stub=out;
6373 void *compiled_target_addr=check_addr(target_addr);
6374 emit_extjump_ds((int)branch_addr,target_addr);
6375 if(compiled_target_addr) {
6376 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6377 add_link(target_addr,stub);
6378 }
6379 else set_jump_target((int)branch_addr,(int)stub);
6380 }
6381}
6382
6383// Assemble the delay slot for the above
6384static void pagespan_ds()
6385{
6386 assem_debug("initial delay slot:\n");
6387 u_int vaddr=start+1;
94d23bb9 6388 u_int page=get_page(vaddr);
6389 u_int vpage=get_vpage(vaddr);
57871462 6390 ll_add(jump_dirty+vpage,vaddr,(void *)out);
6391 do_dirty_stub_ds();
6392 ll_add(jump_in+page,vaddr,(void *)out);
6393 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6394 if(regs[0].regmap[HOST_CCREG]!=CCREG)
6395 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6396 if(regs[0].regmap[HOST_BTREG]!=BTREG)
6397 emit_writeword(HOST_BTREG,(int)&branch_target);
6398 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6399 address_generation(0,&regs[0],regs[0].regmap_entry);
b9b61529 6400 if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
57871462 6401 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6402 cop1_usable=0;
6403 is_delayslot=0;
6404 switch(itype[0]) {
6405 case ALU:
6406 alu_assemble(0,&regs[0]);break;
6407 case IMM16:
6408 imm16_assemble(0,&regs[0]);break;
6409 case SHIFT:
6410 shift_assemble(0,&regs[0]);break;
6411 case SHIFTIMM:
6412 shiftimm_assemble(0,&regs[0]);break;
6413 case LOAD:
6414 load_assemble(0,&regs[0]);break;
6415 case LOADLR:
6416 loadlr_assemble(0,&regs[0]);break;
6417 case STORE:
6418 store_assemble(0,&regs[0]);break;
6419 case STORELR:
6420 storelr_assemble(0,&regs[0]);break;
6421 case COP0:
6422 cop0_assemble(0,&regs[0]);break;
6423 case COP1:
6424 cop1_assemble(0,&regs[0]);break;
6425 case C1LS:
6426 c1ls_assemble(0,&regs[0]);break;
b9b61529 6427 case COP2:
6428 cop2_assemble(0,&regs[0]);break;
6429 case C2LS:
6430 c2ls_assemble(0,&regs[0]);break;
6431 case C2OP:
6432 c2op_assemble(0,&regs[0]);break;
57871462 6433 case FCONV:
6434 fconv_assemble(0,&regs[0]);break;
6435 case FLOAT:
6436 float_assemble(0,&regs[0]);break;
6437 case FCOMP:
6438 fcomp_assemble(0,&regs[0]);break;
6439 case MULTDIV:
6440 multdiv_assemble(0,&regs[0]);break;
6441 case MOV:
6442 mov_assemble(0,&regs[0]);break;
6443 case SYSCALL:
7139f3c8 6444 case HLECALL:
57871462 6445 case SPAN:
6446 case UJUMP:
6447 case RJUMP:
6448 case CJUMP:
6449 case SJUMP:
6450 case FJUMP:
6451 printf("Jump in the delay slot. This is probably a bug.\n");
6452 }
6453 int btaddr=get_reg(regs[0].regmap,BTREG);
6454 if(btaddr<0) {
6455 btaddr=get_reg(regs[0].regmap,-1);
6456 emit_readword((int)&branch_target,btaddr);
6457 }
6458 assert(btaddr!=HOST_CCREG);
6459 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6460#ifdef HOST_IMM8
6461 emit_movimm(start+4,HOST_TEMPREG);
6462 emit_cmp(btaddr,HOST_TEMPREG);
6463#else
6464 emit_cmpimm(btaddr,start+4);
6465#endif
6466 int branch=(int)out;
6467 emit_jeq(0);
6468 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6469 emit_jmp(jump_vaddr_reg[btaddr]);
6470 set_jump_target(branch,(int)out);
6471 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6472 load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6473}
6474
6475// Basic liveness analysis for MIPS registers
6476void unneeded_registers(int istart,int iend,int r)
6477{
6478 int i;
6479 uint64_t u,uu,b,bu;
6480 uint64_t temp_u,temp_uu;
6481 uint64_t tdep;
6482 if(iend==slen-1) {
6483 u=1;uu=1;
6484 }else{
6485 u=unneeded_reg[iend+1];
6486 uu=unneeded_reg_upper[iend+1];
6487 u=1;uu=1;
6488 }
6489 for (i=iend;i>=istart;i--)
6490 {
6491 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6492 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6493 {
6494 // If subroutine call, flag return address as a possible branch target
6495 if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6496
6497 if(ba[i]<start || ba[i]>=(start+slen*4))
6498 {
6499 // Branch out of this block, flush all regs
6500 u=1;
6501 uu=1;
6502 /* Hexagon hack
6503 if(itype[i]==UJUMP&&rt1[i]==31)
6504 {
6505 uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6506 }
6507 if(itype[i]==RJUMP&&rs1[i]==31)
6508 {
6509 uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6510 }
6511 if(start>0x80000400&&start<0x80800000) {
6512 if(itype[i]==UJUMP&&rt1[i]==31)
6513 {
6514 //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6515 uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6516 }
6517 if(itype[i]==RJUMP&&rs1[i]==31)
6518 {
6519 //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6520 uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6521 }
6522 }*/
6523 branch_unneeded_reg[i]=u;
6524 branch_unneeded_reg_upper[i]=uu;
6525 // Merge in delay slot
6526 tdep=(~uu>>rt1[i+1])&1;
6527 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6528 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6529 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6530 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6531 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6532 u|=1;uu|=1;
6533 // If branch is "likely" (and conditional)
6534 // then we skip the delay slot on the fall-thru path
6535 if(likely[i]) {
6536 if(i<slen-1) {
6537 u&=unneeded_reg[i+2];
6538 uu&=unneeded_reg_upper[i+2];
6539 }
6540 else
6541 {
6542 u=1;
6543 uu=1;
6544 }
6545 }
6546 }
6547 else
6548 {
6549 // Internal branch, flag target
6550 bt[(ba[i]-start)>>2]=1;
6551 if(ba[i]<=start+i*4) {
6552 // Backward branch
6553 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6554 {
6555 // Unconditional branch
6556 temp_u=1;temp_uu=1;
6557 } else {
6558 // Conditional branch (not taken case)
6559 temp_u=unneeded_reg[i+2];
6560 temp_uu=unneeded_reg_upper[i+2];
6561 }
6562 // Merge in delay slot
6563 tdep=(~temp_uu>>rt1[i+1])&1;
6564 temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6565 temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6566 temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6567 temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6568 temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6569 temp_u|=1;temp_uu|=1;
6570 // If branch is "likely" (and conditional)
6571 // then we skip the delay slot on the fall-thru path
6572 if(likely[i]) {
6573 if(i<slen-1) {
6574 temp_u&=unneeded_reg[i+2];
6575 temp_uu&=unneeded_reg_upper[i+2];
6576 }
6577 else
6578 {
6579 temp_u=1;
6580 temp_uu=1;
6581 }
6582 }
6583 tdep=(~temp_uu>>rt1[i])&1;
6584 temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6585 temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6586 temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6587 temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6588 temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6589 temp_u|=1;temp_uu|=1;
6590 unneeded_reg[i]=temp_u;
6591 unneeded_reg_upper[i]=temp_uu;
6592 // Only go three levels deep. This recursion can take an
6593 // excessive amount of time if there are a lot of nested loops.
6594 if(r<2) {
6595 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6596 }else{
6597 unneeded_reg[(ba[i]-start)>>2]=1;
6598 unneeded_reg_upper[(ba[i]-start)>>2]=1;
6599 }
6600 } /*else*/ if(1) {
6601 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6602 {
6603 // Unconditional branch
6604 u=unneeded_reg[(ba[i]-start)>>2];
6605 uu=unneeded_reg_upper[(ba[i]-start)>>2];
6606 branch_unneeded_reg[i]=u;
6607 branch_unneeded_reg_upper[i]=uu;
6608 //u=1;
6609 //uu=1;
6610 //branch_unneeded_reg[i]=u;
6611 //branch_unneeded_reg_upper[i]=uu;
6612 // Merge in delay slot
6613 tdep=(~uu>>rt1[i+1])&1;
6614 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6615 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6616 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6617 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6618 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6619 u|=1;uu|=1;
6620 } else {
6621 // Conditional branch
6622 b=unneeded_reg[(ba[i]-start)>>2];
6623 bu=unneeded_reg_upper[(ba[i]-start)>>2];
6624 branch_unneeded_reg[i]=b;
6625 branch_unneeded_reg_upper[i]=bu;
6626 //b=1;
6627 //bu=1;
6628 //branch_unneeded_reg[i]=b;
6629 //branch_unneeded_reg_upper[i]=bu;
6630 // Branch delay slot
6631 tdep=(~uu>>rt1[i+1])&1;
6632 b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6633 bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6634 b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6635 bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6636 bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6637 b|=1;bu|=1;
6638 // If branch is "likely" then we skip the
6639 // delay slot on the fall-thru path
6640 if(likely[i]) {
6641 u=b;
6642 uu=bu;
6643 if(i<slen-1) {
6644 u&=unneeded_reg[i+2];
6645 uu&=unneeded_reg_upper[i+2];
6646 //u=1;
6647 //uu=1;
6648 }
6649 } else {
6650 u&=b;
6651 uu&=bu;
6652 //u=1;
6653 //uu=1;
6654 }
6655 if(i<slen-1) {
6656 branch_unneeded_reg[i]&=unneeded_reg[i+2];
6657 branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6658 //branch_unneeded_reg[i]=1;
6659 //branch_unneeded_reg_upper[i]=1;
6660 } else {
6661 branch_unneeded_reg[i]=1;
6662 branch_unneeded_reg_upper[i]=1;
6663 }
6664 }
6665 }
6666 }
6667 }
7139f3c8 6668 else if(itype[i]==SYSCALL||itype[i]==HLECALL)
57871462 6669 {
6670 // SYSCALL instruction (software interrupt)
6671 u=1;
6672 uu=1;
6673 }
6674 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6675 {
6676 // ERET instruction (return from interrupt)
6677 u=1;
6678 uu=1;
6679 }
6680 //u=uu=1; // DEBUG
6681 tdep=(~uu>>rt1[i])&1;
6682 // Written registers are unneeded
6683 u|=1LL<<rt1[i];
6684 u|=1LL<<rt2[i];
6685 uu|=1LL<<rt1[i];
6686 uu|=1LL<<rt2[i];
6687 // Accessed registers are needed
6688 u&=~(1LL<<rs1[i]);
6689 u&=~(1LL<<rs2[i]);
6690 uu&=~(1LL<<us1[i]);
6691 uu&=~(1LL<<us2[i]);
6692 // Source-target dependencies
6693 uu&=~(tdep<<dep1[i]);
6694 uu&=~(tdep<<dep2[i]);
6695 // R0 is always unneeded
6696 u|=1;uu|=1;
6697 // Save it
6698 unneeded_reg[i]=u;
6699 unneeded_reg_upper[i]=uu;
6700 /*
6701 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6702 printf("U:");
6703 int r;
6704 for(r=1;r<=CCREG;r++) {
6705 if((unneeded_reg[i]>>r)&1) {
6706 if(r==HIREG) printf(" HI");
6707 else if(r==LOREG) printf(" LO");
6708 else printf(" r%d",r);
6709 }
6710 }
6711 printf(" UU:");
6712 for(r=1;r<=CCREG;r++) {
6713 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
6714 if(r==HIREG) printf(" HI");
6715 else if(r==LOREG) printf(" LO");
6716 else printf(" r%d",r);
6717 }
6718 }
6719 printf("\n");*/
6720 }
252c20fc 6721#ifdef FORCE32
6722 for (i=iend;i>=istart;i--)
6723 {
6724 unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
6725 }
6726#endif
57871462 6727}
6728
6729// Identify registers which are likely to contain 32-bit values
6730// This is used to predict whether any branches will jump to a
6731// location with 64-bit values in registers.
6732static void provisional_32bit()
6733{
6734 int i,j;
6735 uint64_t is32=1;
6736 uint64_t lastbranch=1;
6737
6738 for(i=0;i<slen;i++)
6739 {
6740 if(i>0) {
6741 if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
6742 if(i>1) is32=lastbranch;
6743 else is32=1;
6744 }
6745 }
6746 if(i>1)
6747 {
6748 if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
6749 if(likely[i-2]) {
6750 if(i>2) is32=lastbranch;
6751 else is32=1;
6752 }
6753 }
6754 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
6755 {
6756 if(rs1[i-2]==0||rs2[i-2]==0)
6757 {
6758 if(rs1[i-2]) {
6759 is32|=1LL<<rs1[i-2];
6760 }
6761 if(rs2[i-2]) {
6762 is32|=1LL<<rs2[i-2];
6763 }
6764 }
6765 }
6766 }
6767 // If something jumps here with 64-bit values
6768 // then promote those registers to 64 bits
6769 if(bt[i])
6770 {
6771 uint64_t temp_is32=is32;
6772 for(j=i-1;j>=0;j--)
6773 {
6774 if(ba[j]==start+i*4)
6775 //temp_is32&=branch_regs[j].is32;
6776 temp_is32&=p32[j];
6777 }
6778 for(j=i;j<slen;j++)
6779 {
6780 if(ba[j]==start+i*4)
6781 temp_is32=1;
6782 }
6783 is32=temp_is32;
6784 }
6785 int type=itype[i];
6786 int op=opcode[i];
6787 int op2=opcode2[i];
6788 int rt=rt1[i];
6789 int s1=rs1[i];
6790 int s2=rs2[i];
6791 if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
6792 // Branches don't write registers, consider the delay slot instead.
6793 type=itype[i+1];
6794 op=opcode[i+1];
6795 op2=opcode2[i+1];
6796 rt=rt1[i+1];
6797 s1=rs1[i+1];
6798 s2=rs2[i+1];
6799 lastbranch=is32;
6800 }
6801 switch(type) {
6802 case LOAD:
6803 if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
6804 opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
6805 is32&=~(1LL<<rt);
6806 else
6807 is32|=1LL<<rt;
6808 break;
6809 case STORE:
6810 case STORELR:
6811 break;
6812 case LOADLR:
6813 if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
6814 if(op==0x22) is32|=1LL<<rt; // LWL
6815 break;
6816 case IMM16:
6817 if (op==0x08||op==0x09|| // ADDI/ADDIU
6818 op==0x0a||op==0x0b|| // SLTI/SLTIU
6819 op==0x0c|| // ANDI
6820 op==0x0f) // LUI
6821 {
6822 is32|=1LL<<rt;
6823 }
6824 if(op==0x18||op==0x19) { // DADDI/DADDIU
6825 is32&=~(1LL<<rt);
6826 //if(imm[i]==0)
6827 // is32|=((is32>>s1)&1LL)<<rt;
6828 }
6829 if(op==0x0d||op==0x0e) { // ORI/XORI
6830 uint64_t sr=((is32>>s1)&1LL);
6831 is32&=~(1LL<<rt);
6832 is32|=sr<<rt;
6833 }
6834 break;
6835 case UJUMP:
6836 break;
6837 case RJUMP:
6838 break;
6839 case CJUMP:
6840 break;
6841 case SJUMP:
6842 break;
6843 case FJUMP:
6844 break;
6845 case ALU:
6846 if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
6847 is32|=1LL<<rt;
6848 }
6849 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
6850 is32|=1LL<<rt;
6851 }
6852 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
6853 uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
6854 is32&=~(1LL<<rt);
6855 is32|=sr<<rt;
6856 }
6857 else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
6858 if(s1==0&&s2==0) {
6859 is32|=1LL<<rt;
6860 }
6861 else if(s2==0) {
6862 uint64_t sr=((is32>>s1)&1LL);
6863 is32&=~(1LL<<rt);
6864 is32|=sr<<rt;
6865 }
6866 else if(s1==0) {
6867 uint64_t sr=((is32>>s2)&1LL);
6868 is32&=~(1LL<<rt);
6869 is32|=sr<<rt;
6870 }
6871 else {
6872 is32&=~(1LL<<rt);
6873 }
6874 }
6875 else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
6876 if(s1==0&&s2==0) {
6877 is32|=1LL<<rt;
6878 }
6879 else if(s2==0) {
6880 uint64_t sr=((is32>>s1)&1LL);
6881 is32&=~(1LL<<rt);
6882 is32|=sr<<rt;
6883 }
6884 else {
6885 is32&=~(1LL<<rt);
6886 }
6887 }
6888 break;
6889 case MULTDIV:
6890 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
6891 is32&=~((1LL<<HIREG)|(1LL<<LOREG));
6892 }
6893 else {
6894 is32|=(1LL<<HIREG)|(1LL<<LOREG);
6895 }
6896 break;
6897 case MOV:
6898 {
6899 uint64_t sr=((is32>>s1)&1LL);
6900 is32&=~(1LL<<rt);
6901 is32|=sr<<rt;
6902 }
6903 break;
6904 case SHIFT:
6905 if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
6906 else is32|=1LL<<rt; // SLLV/SRLV/SRAV
6907 break;
6908 case SHIFTIMM:
6909 is32|=1LL<<rt;
6910 // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
6911 if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
6912 break;
6913 case COP0:
6914 if(op2==0) is32|=1LL<<rt; // MFC0
6915 break;
6916 case COP1:
b9b61529 6917 case COP2:
57871462 6918 if(op2==0) is32|=1LL<<rt; // MFC1
6919 if(op2==1) is32&=~(1LL<<rt); // DMFC1
6920 if(op2==2) is32|=1LL<<rt; // CFC1
6921 break;
6922 case C1LS:
b9b61529 6923 case C2LS:
57871462 6924 break;
6925 case FLOAT:
6926 case FCONV:
6927 break;
6928 case FCOMP:
6929 break;
b9b61529 6930 case C2OP:
57871462 6931 case SYSCALL:
7139f3c8 6932 case HLECALL:
57871462 6933 break;
6934 default:
6935 break;
6936 }
6937 is32|=1;
6938 p32[i]=is32;
6939
6940 if(i>0)
6941 {
6942 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
6943 {
6944 if(rt1[i-1]==31) // JAL/JALR
6945 {
6946 // Subroutine call will return here, don't alloc any registers
6947 is32=1;
6948 }
6949 else if(i+1<slen)
6950 {
6951 // Internal branch will jump here, match registers to caller
6952 is32=0x3FFFFFFFFLL;
6953 }
6954 }
6955 }
6956 }
6957}
6958
6959// Identify registers which may be assumed to contain 32-bit values
6960// and where optimizations will rely on this.
6961// This is used to determine whether backward branches can safely
6962// jump to a location with 64-bit values in registers.
6963static void provisional_r32()
6964{
6965 u_int r32=0;
6966 int i;
6967
6968 for (i=slen-1;i>=0;i--)
6969 {
6970 int hr;
6971 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6972 {
6973 if(ba[i]<start || ba[i]>=(start+slen*4))
6974 {
6975 // Branch out of this block, don't need anything
6976 r32=0;
6977 }
6978 else
6979 {
6980 // Internal branch
6981 // Need whatever matches the target
6982 // (and doesn't get overwritten by the delay slot instruction)
6983 r32=0;
6984 int t=(ba[i]-start)>>2;
6985 if(ba[i]>start+i*4) {
6986 // Forward branch
6987 //if(!(requires_32bit[t]&~regs[i].was32))
6988 // r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
6989 if(!(pr32[t]&~regs[i].was32))
6990 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
6991 }else{
6992 // Backward branch
6993 if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
6994 r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
6995 }
6996 }
6997 // Conditional branch may need registers for following instructions
6998 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
6999 {
7000 if(i<slen-2) {
7001 //r32|=requires_32bit[i+2];
7002 r32|=pr32[i+2];
7003 r32&=regs[i].was32;
7004 // Mark this address as a branch target since it may be called
7005 // upon return from interrupt
7006 //bt[i+2]=1;
7007 }
7008 }
7009 // Merge in delay slot
7010 if(!likely[i]) {
7011 // These are overwritten unless the branch is "likely"
7012 // and the delay slot is nullified if not taken
7013 r32&=~(1LL<<rt1[i+1]);
7014 r32&=~(1LL<<rt2[i+1]);
7015 }
7016 // Assume these are needed (delay slot)
7017 if(us1[i+1]>0)
7018 {
7019 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7020 }
7021 if(us2[i+1]>0)
7022 {
7023 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7024 }
7025 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7026 {
7027 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7028 }
7029 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7030 {
7031 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7032 }
7033 }
7139f3c8 7034 else if(itype[i]==SYSCALL||itype[i]==HLECALL)
57871462 7035 {
7036 // SYSCALL instruction (software interrupt)
7037 r32=0;
7038 }
7039 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7040 {
7041 // ERET instruction (return from interrupt)
7042 r32=0;
7043 }
7044 // Check 32 bits
7045 r32&=~(1LL<<rt1[i]);
7046 r32&=~(1LL<<rt2[i]);
7047 if(us1[i]>0)
7048 {
7049 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7050 }
7051 if(us2[i]>0)
7052 {
7053 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7054 }
7055 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7056 {
7057 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7058 }
7059 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7060 {
7061 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7062 }
7063 //requires_32bit[i]=r32;
7064 pr32[i]=r32;
7065
7066 // Dirty registers which are 32-bit, require 32-bit input
7067 // as they will be written as 32-bit values
7068 for(hr=0;hr<HOST_REGS;hr++)
7069 {
7070 if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
7071 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7072 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7073 pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7074 //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7075 }
7076 }
7077 }
7078 }
7079}
7080
7081// Write back dirty registers as soon as we will no longer modify them,
7082// so that we don't end up with lots of writes at the branches.
7083void clean_registers(int istart,int iend,int wr)
7084{
7085 int i;
7086 int r;
7087 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7088 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7089 if(iend==slen-1) {
7090 will_dirty_i=will_dirty_next=0;
7091 wont_dirty_i=wont_dirty_next=0;
7092 }else{
7093 will_dirty_i=will_dirty_next=will_dirty[iend+1];
7094 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7095 }
7096 for (i=iend;i>=istart;i--)
7097 {
7098 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7099 {
7100 if(ba[i]<start || ba[i]>=(start+slen*4))
7101 {
7102 // Branch out of this block, flush all regs
7103 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7104 {
7105 // Unconditional branch
7106 will_dirty_i=0;
7107 wont_dirty_i=0;
7108 // Merge in delay slot (will dirty)
7109 for(r=0;r<HOST_REGS;r++) {
7110 if(r!=EXCLUDE_REG) {
7111 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7112 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7113 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7114 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7115 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7116 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7117 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7118 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7119 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7120 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7121 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7122 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7123 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7124 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7125 }
7126 }
7127 }
7128 else
7129 {
7130 // Conditional branch
7131 will_dirty_i=0;
7132 wont_dirty_i=wont_dirty_next;
7133 // Merge in delay slot (will dirty)
7134 for(r=0;r<HOST_REGS;r++) {
7135 if(r!=EXCLUDE_REG) {
7136 if(!likely[i]) {
7137 // Might not dirty if likely branch is not taken
7138 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7139 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7140 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7141 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7142 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7143 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7144 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7145 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7146 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7147 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7148 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7149 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7150 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7151 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7152 }
7153 }
7154 }
7155 }
7156 // Merge in delay slot (wont dirty)
7157 for(r=0;r<HOST_REGS;r++) {
7158 if(r!=EXCLUDE_REG) {
7159 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7160 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7161 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7162 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7163 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7164 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7165 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7166 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7167 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7168 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7169 }
7170 }
7171 if(wr) {
7172 #ifndef DESTRUCTIVE_WRITEBACK
7173 branch_regs[i].dirty&=wont_dirty_i;
7174 #endif
7175 branch_regs[i].dirty|=will_dirty_i;
7176 }
7177 }
7178 else
7179 {
7180 // Internal branch
7181 if(ba[i]<=start+i*4) {
7182 // Backward branch
7183 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7184 {
7185 // Unconditional branch
7186 temp_will_dirty=0;
7187 temp_wont_dirty=0;
7188 // Merge in delay slot (will dirty)
7189 for(r=0;r<HOST_REGS;r++) {
7190 if(r!=EXCLUDE_REG) {
7191 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7192 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7193 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7194 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7195 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7196 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7197 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7198 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7199 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7200 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7201 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7202 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7203 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7204 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7205 }
7206 }
7207 } else {
7208 // Conditional branch (not taken case)
7209 temp_will_dirty=will_dirty_next;
7210 temp_wont_dirty=wont_dirty_next;
7211 // Merge in delay slot (will dirty)
7212 for(r=0;r<HOST_REGS;r++) {
7213 if(r!=EXCLUDE_REG) {
7214 if(!likely[i]) {
7215 // Will not dirty if likely branch is not taken
7216 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7217 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7218 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7219 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7220 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7221 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7222 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7223 //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7224 //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7225 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7226 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7227 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7228 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7229 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7230 }
7231 }
7232 }
7233 }
7234 // Merge in delay slot (wont dirty)
7235 for(r=0;r<HOST_REGS;r++) {
7236 if(r!=EXCLUDE_REG) {
7237 if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7238 if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7239 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7240 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7241 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7242 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7243 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7244 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7245 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7246 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7247 }
7248 }
7249 // Deal with changed mappings
7250 if(i<iend) {
7251 for(r=0;r<HOST_REGS;r++) {
7252 if(r!=EXCLUDE_REG) {
7253 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7254 temp_will_dirty&=~(1<<r);
7255 temp_wont_dirty&=~(1<<r);
7256 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7257 temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7258 temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7259 } else {
7260 temp_will_dirty|=1<<r;
7261 temp_wont_dirty|=1<<r;
7262 }
7263 }
7264 }
7265 }
7266 }
7267 if(wr) {
7268 will_dirty[i]=temp_will_dirty;
7269 wont_dirty[i]=temp_wont_dirty;
7270 clean_registers((ba[i]-start)>>2,i-1,0);
7271 }else{
7272 // Limit recursion. It can take an excessive amount
7273 // of time if there are a lot of nested loops.
7274 will_dirty[(ba[i]-start)>>2]=0;
7275 wont_dirty[(ba[i]-start)>>2]=-1;
7276 }
7277 }
7278 /*else*/ if(1)
7279 {
7280 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7281 {
7282 // Unconditional branch
7283 will_dirty_i=0;
7284 wont_dirty_i=0;
7285 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7286 for(r=0;r<HOST_REGS;r++) {
7287 if(r!=EXCLUDE_REG) {
7288 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7289 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7290 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7291 }
7292 }
7293 }
7294 //}
7295 // Merge in delay slot
7296 for(r=0;r<HOST_REGS;r++) {
7297 if(r!=EXCLUDE_REG) {
7298 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7299 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7300 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7301 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7302 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7303 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7304 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7305 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7306 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7307 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7308 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7309 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7310 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7311 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7312 }
7313 }
7314 } else {
7315 // Conditional branch
7316 will_dirty_i=will_dirty_next;
7317 wont_dirty_i=wont_dirty_next;
7318 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7319 for(r=0;r<HOST_REGS;r++) {
7320 if(r!=EXCLUDE_REG) {
7321 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7322 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7323 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7324 }
7325 else
7326 {
7327 will_dirty_i&=~(1<<r);
7328 }
7329 // Treat delay slot as part of branch too
7330 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7331 will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7332 wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7333 }
7334 else
7335 {
7336 will_dirty[i+1]&=~(1<<r);
7337 }*/
7338 }
7339 }
7340 //}
7341 // Merge in delay slot
7342 for(r=0;r<HOST_REGS;r++) {
7343 if(r!=EXCLUDE_REG) {
7344 if(!likely[i]) {
7345 // Might not dirty if likely branch is not taken
7346 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7347 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7348 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7349 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7350 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7351 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7352 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7353 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7354 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7355 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7356 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7357 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7358 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7359 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7360 }
7361 }
7362 }
7363 }
7364 // Merge in delay slot
7365 for(r=0;r<HOST_REGS;r++) {
7366 if(r!=EXCLUDE_REG) {
7367 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7368 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7369 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7370 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7371 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7372 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7373 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7374 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7375 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7376 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7377 }
7378 }
7379 if(wr) {
7380 #ifndef DESTRUCTIVE_WRITEBACK
7381 branch_regs[i].dirty&=wont_dirty_i;
7382 #endif
7383 branch_regs[i].dirty|=will_dirty_i;
7384 }
7385 }
7386 }
7387 }
7139f3c8 7388 else if(itype[i]==SYSCALL||itype[i]==HLECALL)
57871462 7389 {
7390 // SYSCALL instruction (software interrupt)
7391 will_dirty_i=0;
7392 wont_dirty_i=0;
7393 }
7394 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7395 {
7396 // ERET instruction (return from interrupt)
7397 will_dirty_i=0;
7398 wont_dirty_i=0;
7399 }
7400 will_dirty_next=will_dirty_i;
7401 wont_dirty_next=wont_dirty_i;
7402 for(r=0;r<HOST_REGS;r++) {
7403 if(r!=EXCLUDE_REG) {
7404 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7405 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7406 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7407 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7408 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7409 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7410 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7411 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7412 if(i>istart) {
7413 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7414 {
7415 // Don't store a register immediately after writing it,
7416 // may prevent dual-issue.
7417 if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7418 if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7419 }
7420 }
7421 }
7422 }
7423 // Save it
7424 will_dirty[i]=will_dirty_i;
7425 wont_dirty[i]=wont_dirty_i;
7426 // Mark registers that won't be dirtied as not dirty
7427 if(wr) {
7428 /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7429 for(r=0;r<HOST_REGS;r++) {
7430 if((will_dirty_i>>r)&1) {
7431 printf(" r%d",r);
7432 }
7433 }
7434 printf("\n");*/
7435
7436 //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7437 regs[i].dirty|=will_dirty_i;
7438 #ifndef DESTRUCTIVE_WRITEBACK
7439 regs[i].dirty&=wont_dirty_i;
7440 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7441 {
7442 if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7443 for(r=0;r<HOST_REGS;r++) {
7444 if(r!=EXCLUDE_REG) {
7445 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7446 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7447 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7448 }
7449 }
7450 }
7451 }
7452 else
7453 {
7454 if(i<iend) {
7455 for(r=0;r<HOST_REGS;r++) {
7456 if(r!=EXCLUDE_REG) {
7457 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7458 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7459 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7460 }
7461 }
7462 }
7463 }
7464 #endif
7465 //}
7466 }
7467 // Deal with changed mappings
7468 temp_will_dirty=will_dirty_i;
7469 temp_wont_dirty=wont_dirty_i;
7470 for(r=0;r<HOST_REGS;r++) {
7471 if(r!=EXCLUDE_REG) {
7472 int nr;
7473 if(regs[i].regmap[r]==regmap_pre[i][r]) {
7474 if(wr) {
7475 #ifndef DESTRUCTIVE_WRITEBACK
7476 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7477 #endif
7478 regs[i].wasdirty|=will_dirty_i&(1<<r);
7479 }
7480 }
7481 else if((nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7482 // Register moved to a different register
7483 will_dirty_i&=~(1<<r);
7484 wont_dirty_i&=~(1<<r);
7485 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7486 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7487 if(wr) {
7488 #ifndef DESTRUCTIVE_WRITEBACK
7489 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7490 #endif
7491 regs[i].wasdirty|=will_dirty_i&(1<<r);
7492 }
7493 }
7494 else {
7495 will_dirty_i&=~(1<<r);
7496 wont_dirty_i&=~(1<<r);
7497 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7498 will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7499 wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7500 } else {
7501 wont_dirty_i|=1<<r;
7502 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7503 }
7504 }
7505 }
7506 }
7507 }
7508}
7509
7510 /* disassembly */
7511void disassemble_inst(int i)
7512{
7513 if (bt[i]) printf("*"); else printf(" ");
7514 switch(itype[i]) {
7515 case UJUMP:
7516 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7517 case CJUMP:
7518 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7519 case SJUMP:
7520 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7521 case FJUMP:
7522 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7523 case RJUMP:
5067f341 7524 if (rt1[i]!=31)
7525 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7526 else
7527 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7528 break;
57871462 7529 case SPAN:
7530 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7531 case IMM16:
7532 if(opcode[i]==0xf) //LUI
7533 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7534 else
7535 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7536 break;
7537 case LOAD:
7538 case LOADLR:
7539 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7540 break;
7541 case STORE:
7542 case STORELR:
7543 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7544 break;
7545 case ALU:
7546 case SHIFT:
7547 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7548 break;
7549 case MULTDIV:
7550 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7551 break;
7552 case SHIFTIMM:
7553 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7554 break;
7555 case MOV:
7556 if((opcode2[i]&0x1d)==0x10)
7557 printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7558 else if((opcode2[i]&0x1d)==0x11)
7559 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7560 else
7561 printf (" %x: %s\n",start+i*4,insn[i]);
7562 break;
7563 case COP0:
7564 if(opcode2[i]==0)
7565 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7566 else if(opcode2[i]==4)
7567 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7568 else printf (" %x: %s\n",start+i*4,insn[i]);
7569 break;
7570 case COP1:
7571 if(opcode2[i]<3)
7572 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7573 else if(opcode2[i]>3)
7574 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7575 else printf (" %x: %s\n",start+i*4,insn[i]);
7576 break;
b9b61529 7577 case COP2:
7578 if(opcode2[i]<3)
7579 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7580 else if(opcode2[i]>3)
7581 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7582 else printf (" %x: %s\n",start+i*4,insn[i]);
7583 break;
57871462 7584 case C1LS:
7585 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7586 break;
b9b61529 7587 case C2LS:
7588 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7589 break;
57871462 7590 default:
7591 //printf (" %s %8x\n",insn[i],source[i]);
7592 printf (" %x: %s\n",start+i*4,insn[i]);
7593 }
7594}
7595
7596void new_dynarec_init()
7597{
7598 printf("Init new dynarec\n");
7599 out=(u_char *)BASE_ADDR;
7600 if (mmap (out, 1<<TARGET_SIZE_2,
7601 PROT_READ | PROT_WRITE | PROT_EXEC,
7602 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
7603 -1, 0) <= 0) {printf("mmap() failed\n");}
3d624f89 7604#ifdef MUPEN64
57871462 7605 rdword=&readmem_dword;
7606 fake_pc.f.r.rs=&readmem_dword;
7607 fake_pc.f.r.rt=&readmem_dword;
7608 fake_pc.f.r.rd=&readmem_dword;
3d624f89 7609#endif
57871462 7610 int n;
7611 for(n=0x80000;n<0x80800;n++)
7612 invalid_code[n]=1;
7613 for(n=0;n<65536;n++)
7614 hash_table[n][0]=hash_table[n][2]=-1;
7615 memset(mini_ht,-1,sizeof(mini_ht));
7616 memset(restore_candidate,0,sizeof(restore_candidate));
7617 copy=shadow;
7618 expirep=16384; // Expiry pointer, +2 blocks
7619 pending_exception=0;
7620 literalcount=0;
7621#ifdef HOST_IMM8
7622 // Copy this into local area so we don't have to put it in every literal pool
7623 invc_ptr=invalid_code;
7624#endif
7625 stop_after_jal=0;
7626 // TLB
7627 using_tlb=0;
7628 for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7629 memory_map[n]=-1;
7630 for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7631 memory_map[n]=((u_int)rdram-0x80000000)>>2;
7632 for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7633 memory_map[n]=-1;
24385cae 7634#ifdef MUPEN64
57871462 7635 for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
7636 writemem[n] = write_nomem_new;
7637 writememb[n] = write_nomemb_new;
7638 writememh[n] = write_nomemh_new;
24385cae 7639#ifndef FORCE32
57871462 7640 writememd[n] = write_nomemd_new;
24385cae 7641#endif
57871462 7642 readmem[n] = read_nomem_new;
7643 readmemb[n] = read_nomemb_new;
7644 readmemh[n] = read_nomemh_new;
24385cae 7645#ifndef FORCE32
57871462 7646 readmemd[n] = read_nomemd_new;
24385cae 7647#endif
57871462 7648 }
7649 for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
7650 writemem[n] = write_rdram_new;
7651 writememb[n] = write_rdramb_new;
7652 writememh[n] = write_rdramh_new;
24385cae 7653#ifndef FORCE32
57871462 7654 writememd[n] = write_rdramd_new;
24385cae 7655#endif
57871462 7656 }
7657 for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
7658 writemem[n] = write_nomem_new;
7659 writememb[n] = write_nomemb_new;
7660 writememh[n] = write_nomemh_new;
24385cae 7661#ifndef FORCE32
57871462 7662 writememd[n] = write_nomemd_new;
24385cae 7663#endif
57871462 7664 readmem[n] = read_nomem_new;
7665 readmemb[n] = read_nomemb_new;
7666 readmemh[n] = read_nomemh_new;
24385cae 7667#ifndef FORCE32
57871462 7668 readmemd[n] = read_nomemd_new;
24385cae 7669#endif
57871462 7670 }
24385cae 7671#endif
57871462 7672 tlb_hacks();
7673 arch_init();
7674}
7675
7676void new_dynarec_cleanup()
7677{
7678 int n;
7679 if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
7680 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7681 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7682 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7683 #ifdef ROM_COPY
7684 if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
7685 #endif
7686}
7687
7688int new_recompile_block(int addr)
7689{
7690/*
7691 if(addr==0x800cd050) {
7692 int block;
7693 for(block=0x80000;block<0x80800;block++) invalidate_block(block);
7694 int n;
7695 for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
7696 }
7697*/
7698 //if(Count==365117028) tracedebug=1;
7699 assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7700 //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7701 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
7702 //if(debug)
7703 //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
7704 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
7705 /*if(Count>=312978186) {
7706 rlist();
7707 }*/
7708 //rlist();
7709 start = (u_int)addr&~3;
7710 //assert(((u_int)addr&1)==0);
7139f3c8 7711#ifdef PCSX
7712 if (Config.HLE && start == 0x80001000) {
7713 // XXX: is this enough? Maybe check hleSoftCall?
bb5285ef 7714 u_int beginning=(u_int)out;
7139f3c8 7715 u_int page=get_page(start);
7716 ll_add(jump_in+page,start,out);
7717 invalid_code[start>>12]=0;
7718 emit_movimm(start,0);
7719 emit_writeword(0,(int)&pcaddr);
bb5285ef 7720 emit_jmp((int)new_dyna_leave);
7721#ifdef __arm__
7722 __clear_cache((void *)beginning,out);
7723#endif
7139f3c8 7724 return 0;
7725 }
7726 else if ((u_int)addr < 0x00200000) {
7727 // used for BIOS calls mostly?
7728 source = (u_int *)((u_int)rdram+start-0);
7729 pagelimit = 0x00200000;
7730 }
7731 else
7732#endif
3d624f89 7733#ifdef MUPEN64
57871462 7734 if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
7735 source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
7736 pagelimit = 0xa4001000;
7737 }
3d624f89 7738 else
7739#endif
7740 if ((int)addr >= 0x80000000 && (int)addr < 0x80800000) {
57871462 7741 source = (u_int *)((u_int)rdram+start-0x80000000);
7742 pagelimit = 0x80800000;
7743 }
90ae6d4e 7744#ifndef DISABLE_TLB
57871462 7745 else if ((signed int)addr >= (signed int)0xC0000000) {
7746 //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
7747 //if(tlb_LUT_r[start>>12])
7748 //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
7749 if((signed int)memory_map[start>>12]>=0) {
7750 source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
7751 pagelimit=(start+4096)&0xFFFFF000;
7752 int map=memory_map[start>>12];
7753 int i;
7754 for(i=0;i<5;i++) {
7755 //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
7756 if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
7757 }
7758 assem_debug("pagelimit=%x\n",pagelimit);
7759 assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
7760 }
7761 else {
7762 assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
7763 //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
7764 return 1; // Caller will invoke exception handler
7765 }
7766 //printf("source= %x\n",(int)source);
7767 }
90ae6d4e 7768#endif
57871462 7769 else {
7770 printf("Compile at bogus memory address: %x \n", (int)addr);
7771 exit(1);
7772 }
7773
7774 /* Pass 1: disassemble */
7775 /* Pass 2: register dependencies, branch targets */
7776 /* Pass 3: register allocation */
7777 /* Pass 4: branch dependencies */
7778 /* Pass 5: pre-alloc */
7779 /* Pass 6: optimize clean/dirty state */
7780 /* Pass 7: flag 32-bit registers */
7781 /* Pass 8: assembly */
7782 /* Pass 9: linker */
7783 /* Pass 10: garbage collection / free memory */
7784
7785 int i,j;
7786 int done=0;
7787 unsigned int type,op,op2;
7788
7789 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
7790
7791 /* Pass 1 disassembly */
7792
7793 for(i=0;!done;i++) {
7794 bt[i]=0;likely[i]=0;op2=0;
7795 opcode[i]=op=source[i]>>26;
7796 switch(op)
7797 {
7798 case 0x00: strcpy(insn[i],"special"); type=NI;
7799 op2=source[i]&0x3f;
7800 switch(op2)
7801 {
7802 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
7803 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
7804 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
7805 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
7806 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
7807 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
7808 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
7809 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
7810 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
7811 case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
7812 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
7813 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
7814 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
7815 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
7816 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
7817 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
7818 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
7819 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
7820 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
7821 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
7822 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
7823 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
7824 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
7825 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
7826 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
7827 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
7828 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
7829 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
7830 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
7831 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
7832 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
7833 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
7834 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
7835 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
7836 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
7837 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
7838 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
7839 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
7840 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
7841 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
7842 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
7843 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
7844 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
7845 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
7846 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
7847 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
7848 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
7849 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
7850 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
7851 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
7852 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
7853 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
7854 }
7855 break;
7856 case 0x01: strcpy(insn[i],"regimm"); type=NI;
7857 op2=(source[i]>>16)&0x1f;
7858 switch(op2)
7859 {
7860 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
7861 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
7862 case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
7863 case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
7864 case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
7865 case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
7866 case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
7867 case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
7868 case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
7869 case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
7870 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
7871 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
7872 case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
7873 case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
7874 }
7875 break;
7876 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
7877 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
7878 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
7879 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
7880 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
7881 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
7882 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
7883 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
7884 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
7885 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
7886 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
7887 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
7888 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
7889 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
7890 case 0x10: strcpy(insn[i],"cop0"); type=NI;
7891 op2=(source[i]>>21)&0x1f;
7892 switch(op2)
7893 {
7894 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
7895 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
7896 case 0x10: strcpy(insn[i],"tlb"); type=NI;
7897 switch(source[i]&0x3f)
7898 {
7899 case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
7900 case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
7901 case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
7902 case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
7903 case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
7904 }
7905 }
7906 break;
7907 case 0x11: strcpy(insn[i],"cop1"); type=NI;
7908 op2=(source[i]>>21)&0x1f;
7909 switch(op2)
7910 {
7911 case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
7912 case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
7913 case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
7914 case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
7915 case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
7916 case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
7917 case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
7918 switch((source[i]>>16)&0x3)
7919 {
7920 case 0x00: strcpy(insn[i],"BC1F"); break;
7921 case 0x01: strcpy(insn[i],"BC1T"); break;
7922 case 0x02: strcpy(insn[i],"BC1FL"); break;
7923 case 0x03: strcpy(insn[i],"BC1TL"); break;
7924 }
7925 break;
7926 case 0x10: strcpy(insn[i],"C1.S"); type=NI;
7927 switch(source[i]&0x3f)
7928 {
7929 case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
7930 case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
7931 case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
7932 case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
7933 case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
7934 case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
7935 case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
7936 case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
7937 case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
7938 case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
7939 case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
7940 case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
7941 case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
7942 case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
7943 case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
7944 case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
7945 case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
7946 case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
7947 case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
7948 case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
7949 case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
7950 case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
7951 case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
7952 case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
7953 case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
7954 case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
7955 case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
7956 case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
7957 case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
7958 case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
7959 case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
7960 case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
7961 case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
7962 case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
7963 case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
7964 }
7965 break;
7966 case 0x11: strcpy(insn[i],"C1.D"); type=NI;
7967 switch(source[i]&0x3f)
7968 {
7969 case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
7970 case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
7971 case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
7972 case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
7973 case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
7974 case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
7975 case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
7976 case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
7977 case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
7978 case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
7979 case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
7980 case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
7981 case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
7982 case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
7983 case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
7984 case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
7985 case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
7986 case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
7987 case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
7988 case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
7989 case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
7990 case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
7991 case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
7992 case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
7993 case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
7994 case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
7995 case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
7996 case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
7997 case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
7998 case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
7999 case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8000 case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8001 case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8002 case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8003 case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8004 }
8005 break;
8006 case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8007 switch(source[i]&0x3f)
8008 {
8009 case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8010 case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8011 }
8012 break;
8013 case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8014 switch(source[i]&0x3f)
8015 {
8016 case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8017 case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8018 }
8019 break;
8020 }
8021 break;
8022 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8023 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8024 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8025 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8026 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8027 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8028 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8029 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
8030 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8031 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8032 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8033 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8034 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8035 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8036 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
8037 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
8038 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8039 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8040 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8041 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
8042 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8043 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
8044 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8045 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8046 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8047 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
8048 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8049 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8050 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
8051 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8052 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
8053 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8054 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8055 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
b9b61529 8056#ifdef PCSX
8057 case 0x12: strcpy(insn[i],"COP2"); type=NI;
8058 op2=(source[i]>>21)&0x1f;
8059 switch(op2)
8060 {
8061 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8062 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8063 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8064 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
8065 default:
8066 if (gte_handlers[source[i]&0x3f]!=NULL) {
8067 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8068 type=C2OP;
8069 }
8070 break;
8071 }
8072 break;
8073 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8074 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8075 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8076#endif
90ae6d4e 8077 default: strcpy(insn[i],"???"); type=NI;
7139f3c8 8078 printf("NI %08x @%08x\n", source[i], addr + i*4);
90ae6d4e 8079 break;
57871462 8080 }
8081 itype[i]=type;
8082 opcode2[i]=op2;
8083 /* Get registers/immediates */
8084 lt1[i]=0;
8085 us1[i]=0;
8086 us2[i]=0;
8087 dep1[i]=0;
8088 dep2[i]=0;
8089 switch(type) {
8090 case LOAD:
8091 rs1[i]=(source[i]>>21)&0x1f;
8092 rs2[i]=0;
8093 rt1[i]=(source[i]>>16)&0x1f;
8094 rt2[i]=0;
8095 imm[i]=(short)source[i];
8096 break;
8097 case STORE:
8098 case STORELR:
8099 rs1[i]=(source[i]>>21)&0x1f;
8100 rs2[i]=(source[i]>>16)&0x1f;
8101 rt1[i]=0;
8102 rt2[i]=0;
8103 imm[i]=(short)source[i];
8104 if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8105 break;
8106 case LOADLR:
8107 // LWL/LWR only load part of the register,
8108 // therefore the target register must be treated as a source too
8109 rs1[i]=(source[i]>>21)&0x1f;
8110 rs2[i]=(source[i]>>16)&0x1f;
8111 rt1[i]=(source[i]>>16)&0x1f;
8112 rt2[i]=0;
8113 imm[i]=(short)source[i];
8114 if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8115 if(op==0x26) dep1[i]=rt1[i]; // LWR
8116 break;
8117 case IMM16:
8118 if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8119 else rs1[i]=(source[i]>>21)&0x1f;
8120 rs2[i]=0;
8121 rt1[i]=(source[i]>>16)&0x1f;
8122 rt2[i]=0;
8123 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8124 imm[i]=(unsigned short)source[i];
8125 }else{
8126 imm[i]=(short)source[i];
8127 }
8128 if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8129 if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8130 if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8131 break;
8132 case UJUMP:
8133 rs1[i]=0;
8134 rs2[i]=0;
8135 rt1[i]=0;
8136 rt2[i]=0;
8137 // The JAL instruction writes to r31.
8138 if (op&1) {
8139 rt1[i]=31;
8140 }
8141 rs2[i]=CCREG;
8142 break;
8143 case RJUMP:
8144 rs1[i]=(source[i]>>21)&0x1f;
8145 rs2[i]=0;
8146 rt1[i]=0;
8147 rt2[i]=0;
5067f341 8148 // The JALR instruction writes to rd.
57871462 8149 if (op2&1) {
5067f341 8150 rt1[i]=(source[i]>>11)&0x1f;
57871462 8151 }
8152 rs2[i]=CCREG;
8153 break;
8154 case CJUMP:
8155 rs1[i]=(source[i]>>21)&0x1f;
8156 rs2[i]=(source[i]>>16)&0x1f;
8157 rt1[i]=0;
8158 rt2[i]=0;
8159 if(op&2) { // BGTZ/BLEZ
8160 rs2[i]=0;
8161 }
8162 us1[i]=rs1[i];
8163 us2[i]=rs2[i];
8164 likely[i]=op>>4;
8165 break;
8166 case SJUMP:
8167 rs1[i]=(source[i]>>21)&0x1f;
8168 rs2[i]=CCREG;
8169 rt1[i]=0;
8170 rt2[i]=0;
8171 us1[i]=rs1[i];
8172 if(op2&0x10) { // BxxAL
8173 rt1[i]=31;
8174 // NOTE: If the branch is not taken, r31 is still overwritten
8175 }
8176 likely[i]=(op2&2)>>1;
8177 break;
8178 case FJUMP:
8179 rs1[i]=FSREG;
8180 rs2[i]=CSREG;
8181 rt1[i]=0;
8182 rt2[i]=0;
8183 likely[i]=((source[i])>>17)&1;
8184 break;
8185 case ALU:
8186 rs1[i]=(source[i]>>21)&0x1f; // source
8187 rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8188 rt1[i]=(source[i]>>11)&0x1f; // destination
8189 rt2[i]=0;
8190 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8191 us1[i]=rs1[i];us2[i]=rs2[i];
8192 }
8193 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8194 dep1[i]=rs1[i];dep2[i]=rs2[i];
8195 }
8196 else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8197 dep1[i]=rs1[i];dep2[i]=rs2[i];
8198 }
8199 break;
8200 case MULTDIV:
8201 rs1[i]=(source[i]>>21)&0x1f; // source
8202 rs2[i]=(source[i]>>16)&0x1f; // divisor
8203 rt1[i]=HIREG;
8204 rt2[i]=LOREG;
8205 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8206 us1[i]=rs1[i];us2[i]=rs2[i];
8207 }
8208 break;
8209 case MOV:
8210 rs1[i]=0;
8211 rs2[i]=0;
8212 rt1[i]=0;
8213 rt2[i]=0;
8214 if(op2==0x10) rs1[i]=HIREG; // MFHI
8215 if(op2==0x11) rt1[i]=HIREG; // MTHI
8216 if(op2==0x12) rs1[i]=LOREG; // MFLO
8217 if(op2==0x13) rt1[i]=LOREG; // MTLO
8218 if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8219 if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8220 dep1[i]=rs1[i];
8221 break;
8222 case SHIFT:
8223 rs1[i]=(source[i]>>16)&0x1f; // target of shift
8224 rs2[i]=(source[i]>>21)&0x1f; // shift amount
8225 rt1[i]=(source[i]>>11)&0x1f; // destination
8226 rt2[i]=0;
8227 // DSLLV/DSRLV/DSRAV are 64-bit
8228 if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8229 break;
8230 case SHIFTIMM:
8231 rs1[i]=(source[i]>>16)&0x1f;
8232 rs2[i]=0;
8233 rt1[i]=(source[i]>>11)&0x1f;
8234 rt2[i]=0;
8235 imm[i]=(source[i]>>6)&0x1f;
8236 // DSxx32 instructions
8237 if(op2>=0x3c) imm[i]|=0x20;
8238 // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8239 if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8240 break;
8241 case COP0:
8242 rs1[i]=0;
8243 rs2[i]=0;
8244 rt1[i]=0;
8245 rt2[i]=0;
8246 if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8247 if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8248 if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8249 if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8250 break;
8251 case COP1:
b9b61529 8252 case COP2:
57871462 8253 rs1[i]=0;
8254 rs2[i]=0;
8255 rt1[i]=0;
8256 rt2[i]=0;
8257 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8258 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8259 if(op2==5) us1[i]=rs1[i]; // DMTC1
8260 rs2[i]=CSREG;
8261 break;
8262 case C1LS:
8263 rs1[i]=(source[i]>>21)&0x1F;
8264 rs2[i]=CSREG;
8265 rt1[i]=0;
8266 rt2[i]=0;
8267 imm[i]=(short)source[i];
8268 break;
b9b61529 8269 case C2LS:
8270 rs1[i]=(source[i]>>21)&0x1F;
8271 rs2[i]=0;
8272 rt1[i]=0;
8273 rt2[i]=0;
8274 imm[i]=(short)source[i];
8275 break;
57871462 8276 case FLOAT:
8277 case FCONV:
8278 rs1[i]=0;
8279 rs2[i]=CSREG;
8280 rt1[i]=0;
8281 rt2[i]=0;
8282 break;
8283 case FCOMP:
8284 rs1[i]=FSREG;
8285 rs2[i]=CSREG;
8286 rt1[i]=FSREG;
8287 rt2[i]=0;
8288 break;
8289 case SYSCALL:
7139f3c8 8290 case HLECALL:
57871462 8291 rs1[i]=CCREG;
8292 rs2[i]=0;
8293 rt1[i]=0;
8294 rt2[i]=0;
8295 break;
8296 default:
8297 rs1[i]=0;
8298 rs2[i]=0;
8299 rt1[i]=0;
8300 rt2[i]=0;
8301 }
8302 /* Calculate branch target addresses */
8303 if(type==UJUMP)
8304 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8305 else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8306 ba[i]=start+i*4+8; // Ignore never taken branch
8307 else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8308 ba[i]=start+i*4+8; // Ignore never taken branch
8309 else if(type==CJUMP||type==SJUMP||type==FJUMP)
8310 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8311 else ba[i]=-1;
8312 /* Is this the end of the block? */
8313 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
5067f341 8314 if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
57871462 8315 done=1;
8316 // Does the block continue due to a branch?
8317 for(j=i-1;j>=0;j--)
8318 {
8319 if(ba[j]==start+i*4+4) done=j=0;
8320 if(ba[j]==start+i*4+8) done=j=0;
8321 }
8322 }
8323 else {
8324 if(stop_after_jal) done=1;
8325 // Stop on BREAK
8326 if((source[i+1]&0xfc00003f)==0x0d) done=1;
8327 }
8328 // Don't recompile stuff that's already compiled
8329 if(check_addr(start+i*4+4)) done=1;
8330 // Don't get too close to the limit
8331 if(i>MAXBLOCK/2) done=1;
8332 }
8333 if(i>0&&itype[i-1]==SYSCALL&&stop_after_jal) done=1;
7139f3c8 8334 if(itype[i-1]==HLECALL) done=1;
57871462 8335 assert(i<MAXBLOCK-1);
8336 if(start+i*4==pagelimit-4) done=1;
8337 assert(start+i*4<pagelimit);
8338 if (i==MAXBLOCK-1) done=1;
8339 // Stop if we're compiling junk
8340 if(itype[i]==NI&&opcode[i]==0x11) {
8341 done=stop_after_jal=1;
8342 printf("Disabled speculative precompilation\n");
8343 }
8344 }
8345 slen=i;
8346 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8347 if(start+i*4==pagelimit) {
8348 itype[i-1]=SPAN;
8349 }
8350 }
8351 assert(slen>0);
8352
8353 /* Pass 2 - Register dependencies and branch targets */
8354
8355 unneeded_registers(0,slen-1,0);
8356
8357 /* Pass 3 - Register allocation */
8358
8359 struct regstat current; // Current register allocations/status
8360 current.is32=1;
8361 current.dirty=0;
8362 current.u=unneeded_reg[0];
8363 current.uu=unneeded_reg_upper[0];
8364 clear_all_regs(current.regmap);
8365 alloc_reg(&current,0,CCREG);
8366 dirty_reg(&current,CCREG);
8367 current.isconst=0;
8368 current.wasconst=0;
8369 int ds=0;
8370 int cc=0;
8371 int hr;
8372
8373 provisional_32bit();
8374
8375 if((u_int)addr&1) {
8376 // First instruction is delay slot
8377 cc=-1;
8378 bt[1]=1;
8379 ds=1;
8380 unneeded_reg[0]=1;
8381 unneeded_reg_upper[0]=1;
8382 current.regmap[HOST_BTREG]=BTREG;
8383 }
8384
8385 for(i=0;i<slen;i++)
8386 {
8387 if(bt[i])
8388 {
8389 int hr;
8390 for(hr=0;hr<HOST_REGS;hr++)
8391 {
8392 // Is this really necessary?
8393 if(current.regmap[hr]==0) current.regmap[hr]=-1;
8394 }
8395 current.isconst=0;
8396 }
8397 if(i>1)
8398 {
8399 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8400 {
8401 if(rs1[i-2]==0||rs2[i-2]==0)
8402 {
8403 if(rs1[i-2]) {
8404 current.is32|=1LL<<rs1[i-2];
8405 int hr=get_reg(current.regmap,rs1[i-2]|64);
8406 if(hr>=0) current.regmap[hr]=-1;
8407 }
8408 if(rs2[i-2]) {
8409 current.is32|=1LL<<rs2[i-2];
8410 int hr=get_reg(current.regmap,rs2[i-2]|64);
8411 if(hr>=0) current.regmap[hr]=-1;
8412 }
8413 }
8414 }
8415 }
8416 // If something jumps here with 64-bit values
8417 // then promote those registers to 64 bits
8418 if(bt[i])
8419 {
8420 uint64_t temp_is32=current.is32;
8421 for(j=i-1;j>=0;j--)
8422 {
8423 if(ba[j]==start+i*4)
8424 temp_is32&=branch_regs[j].is32;
8425 }
8426 for(j=i;j<slen;j++)
8427 {
8428 if(ba[j]==start+i*4)
8429 //temp_is32=1;
8430 temp_is32&=p32[j];
8431 }
8432 if(temp_is32!=current.is32) {
8433 //printf("dumping 32-bit regs (%x)\n",start+i*4);
8434 #ifdef DESTRUCTIVE_WRITEBACK
8435 for(hr=0;hr<HOST_REGS;hr++)
8436 {
8437 int r=current.regmap[hr];
8438 if(r>0&&r<64)
8439 {
8440 if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8441 temp_is32|=1LL<<r;
8442 //printf("restore %d\n",r);
8443 }
8444 }
8445 }
8446 #endif
8447 current.is32=temp_is32;
8448 }
8449 }
24385cae 8450#ifdef FORCE32
8451 memset(p32, 0xff, sizeof(p32));
8452 current.is32=-1LL;
8453#endif
8454
57871462 8455 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8456 regs[i].wasconst=current.isconst;
8457 regs[i].was32=current.is32;
8458 regs[i].wasdirty=current.dirty;
8459 #ifdef DESTRUCTIVE_WRITEBACK
8460 // To change a dirty register from 32 to 64 bits, we must write
8461 // it out during the previous cycle (for branches, 2 cycles)
8462 if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8463 {
8464 uint64_t temp_is32=current.is32;
8465 for(j=i-1;j>=0;j--)
8466 {
8467 if(ba[j]==start+i*4+4)
8468 temp_is32&=branch_regs[j].is32;
8469 }
8470 for(j=i;j<slen;j++)
8471 {
8472 if(ba[j]==start+i*4+4)
8473 //temp_is32=1;
8474 temp_is32&=p32[j];
8475 }
8476 if(temp_is32!=current.is32) {
8477 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8478 for(hr=0;hr<HOST_REGS;hr++)
8479 {
8480 int r=current.regmap[hr];
8481 if(r>0)
8482 {
8483 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8484 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
8485 {
8486 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
8487 {
8488 //printf("dump %d/r%d\n",hr,r);
8489 current.regmap[hr]=-1;
8490 if(get_reg(current.regmap,r|64)>=0)
8491 current.regmap[get_reg(current.regmap,r|64)]=-1;
8492 }
8493 }
8494 }
8495 }
8496 }
8497 }
8498 }
8499 else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
8500 {
8501 uint64_t temp_is32=current.is32;
8502 for(j=i-1;j>=0;j--)
8503 {
8504 if(ba[j]==start+i*4+8)
8505 temp_is32&=branch_regs[j].is32;
8506 }
8507 for(j=i;j<slen;j++)
8508 {
8509 if(ba[j]==start+i*4+8)
8510 //temp_is32=1;
8511 temp_is32&=p32[j];
8512 }
8513 if(temp_is32!=current.is32) {
8514 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8515 for(hr=0;hr<HOST_REGS;hr++)
8516 {
8517 int r=current.regmap[hr];
8518 if(r>0)
8519 {
8520 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8521 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
8522 {
8523 //printf("dump %d/r%d\n",hr,r);
8524 current.regmap[hr]=-1;
8525 if(get_reg(current.regmap,r|64)>=0)
8526 current.regmap[get_reg(current.regmap,r|64)]=-1;
8527 }
8528 }
8529 }
8530 }
8531 }
8532 }
8533 #endif
8534 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8535 if(i+1<slen) {
8536 current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8537 current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8538 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8539 current.u|=1;
8540 current.uu|=1;
8541 } else {
8542 current.u=1;
8543 current.uu=1;
8544 }
8545 } else {
8546 if(i+1<slen) {
8547 current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
8548 current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8549 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8550 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8551 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8552 current.u|=1;
8553 current.uu|=1;
8554 } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
8555 }
8556 is_ds[i]=ds;
8557 if(ds) {
8558 ds=0; // Skip delay slot, already allocated as part of branch
8559 // ...but we need to alloc it in case something jumps here
8560 if(i+1<slen) {
8561 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
8562 current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
8563 }else{
8564 current.u=branch_unneeded_reg[i-1];
8565 current.uu=branch_unneeded_reg_upper[i-1];
8566 }
8567 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8568 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8569 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8570 current.u|=1;
8571 current.uu|=1;
8572 struct regstat temp;
8573 memcpy(&temp,&current,sizeof(current));
8574 temp.wasdirty=temp.dirty;
8575 temp.was32=temp.is32;
8576 // TODO: Take into account unconditional branches, as below
8577 delayslot_alloc(&temp,i);
8578 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
8579 regs[i].wasdirty=temp.wasdirty;
8580 regs[i].was32=temp.was32;
8581 regs[i].dirty=temp.dirty;
8582 regs[i].is32=temp.is32;
8583 regs[i].isconst=0;
8584 regs[i].wasconst=0;
8585 current.isconst=0;
8586 // Create entry (branch target) regmap
8587 for(hr=0;hr<HOST_REGS;hr++)
8588 {
8589 int r=temp.regmap[hr];
8590 if(r>=0) {
8591 if(r!=regmap_pre[i][hr]) {
8592 regs[i].regmap_entry[hr]=-1;
8593 }
8594 else
8595 {
8596 if(r<64){
8597 if((current.u>>r)&1) {
8598 regs[i].regmap_entry[hr]=-1;
8599 regs[i].regmap[hr]=-1;
8600 //Don't clear regs in the delay slot as the branch might need them
8601 //current.regmap[hr]=-1;
8602 }else
8603 regs[i].regmap_entry[hr]=r;
8604 }
8605 else {
8606 if((current.uu>>(r&63))&1) {
8607 regs[i].regmap_entry[hr]=-1;
8608 regs[i].regmap[hr]=-1;
8609 //Don't clear regs in the delay slot as the branch might need them
8610 //current.regmap[hr]=-1;
8611 }else
8612 regs[i].regmap_entry[hr]=r;
8613 }
8614 }
8615 } else {
8616 // First instruction expects CCREG to be allocated
8617 if(i==0&&hr==HOST_CCREG)
8618 regs[i].regmap_entry[hr]=CCREG;
8619 else
8620 regs[i].regmap_entry[hr]=-1;
8621 }
8622 }
8623 }
8624 else { // Not delay slot
8625 switch(itype[i]) {
8626 case UJUMP:
8627 //current.isconst=0; // DEBUG
8628 //current.wasconst=0; // DEBUG
8629 //regs[i].wasconst=0; // DEBUG
8630 clear_const(&current,rt1[i]);
8631 alloc_cc(&current,i);
8632 dirty_reg(&current,CCREG);
8633 if (rt1[i]==31) {
8634 alloc_reg(&current,i,31);
8635 dirty_reg(&current,31);
8636 assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8637 #ifdef REG_PREFETCH
8638 alloc_reg(&current,i,PTEMP);
8639 #endif
8640 //current.is32|=1LL<<rt1[i];
8641 }
8642 delayslot_alloc(&current,i+1);
8643 //current.isconst=0; // DEBUG
8644 ds=1;
8645 //printf("i=%d, isconst=%x\n",i,current.isconst);
8646 break;
8647 case RJUMP:
8648 //current.isconst=0;
8649 //current.wasconst=0;
8650 //regs[i].wasconst=0;
8651 clear_const(&current,rs1[i]);
8652 clear_const(&current,rt1[i]);
8653 alloc_cc(&current,i);
8654 dirty_reg(&current,CCREG);
8655 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
8656 alloc_reg(&current,i,rs1[i]);
5067f341 8657 if (rt1[i]!=0) {
8658 alloc_reg(&current,i,rt1[i]);
8659 dirty_reg(&current,rt1[i]);
57871462 8660 assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8661 #ifdef REG_PREFETCH
8662 alloc_reg(&current,i,PTEMP);
8663 #endif
8664 }
8665 #ifdef USE_MINI_HT
8666 if(rs1[i]==31) { // JALR
8667 alloc_reg(&current,i,RHASH);
8668 #ifndef HOST_IMM_ADDR32
8669 alloc_reg(&current,i,RHTBL);
8670 #endif
8671 }
8672 #endif
8673 delayslot_alloc(&current,i+1);
8674 } else {
8675 // The delay slot overwrites our source register,
8676 // allocate a temporary register to hold the old value.
8677 current.isconst=0;
8678 current.wasconst=0;
8679 regs[i].wasconst=0;
8680 delayslot_alloc(&current,i+1);
8681 current.isconst=0;
8682 alloc_reg(&current,i,RTEMP);
8683 }
8684 //current.isconst=0; // DEBUG
8685 ds=1;
8686 break;
8687 case CJUMP:
8688 //current.isconst=0;
8689 //current.wasconst=0;
8690 //regs[i].wasconst=0;
8691 clear_const(&current,rs1[i]);
8692 clear_const(&current,rs2[i]);
8693 if((opcode[i]&0x3E)==4) // BEQ/BNE
8694 {
8695 alloc_cc(&current,i);
8696 dirty_reg(&current,CCREG);
8697 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8698 if(rs2[i]) alloc_reg(&current,i,rs2[i]);
8699 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8700 {
8701 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8702 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
8703 }
8704 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
8705 (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
8706 // The delay slot overwrites one of our conditions.
8707 // Allocate the branch condition registers instead.
8708 // Note that such a sequence of instructions could
8709 // be considered a bug since the branch can not be
8710 // re-executed if an exception occurs.
8711 current.isconst=0;
8712 current.wasconst=0;
8713 regs[i].wasconst=0;
8714 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8715 if(rs2[i]) alloc_reg(&current,i,rs2[i]);
8716 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8717 {
8718 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8719 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
8720 }
8721 }
8722 else delayslot_alloc(&current,i+1);
8723 }
8724 else
8725 if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
8726 {
8727 alloc_cc(&current,i);
8728 dirty_reg(&current,CCREG);
8729 alloc_reg(&current,i,rs1[i]);
8730 if(!(current.is32>>rs1[i]&1))
8731 {
8732 alloc_reg64(&current,i,rs1[i]);
8733 }
8734 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
8735 // The delay slot overwrites one of our conditions.
8736 // Allocate the branch condition registers instead.
8737 // Note that such a sequence of instructions could
8738 // be considered a bug since the branch can not be
8739 // re-executed if an exception occurs.
8740 current.isconst=0;
8741 current.wasconst=0;
8742 regs[i].wasconst=0;
8743 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8744 if(!((current.is32>>rs1[i])&1))
8745 {
8746 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8747 }
8748 }
8749 else delayslot_alloc(&current,i+1);
8750 }
8751 else
8752 // Don't alloc the delay slot yet because we might not execute it
8753 if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
8754 {
8755 current.isconst=0;
8756 current.wasconst=0;
8757 regs[i].wasconst=0;
8758 alloc_cc(&current,i);
8759 dirty_reg(&current,CCREG);
8760 alloc_reg(&current,i,rs1[i]);
8761 alloc_reg(&current,i,rs2[i]);
8762 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8763 {
8764 alloc_reg64(&current,i,rs1[i]);
8765 alloc_reg64(&current,i,rs2[i]);
8766 }
8767 }
8768 else
8769 if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
8770 {
8771 current.isconst=0;
8772 current.wasconst=0;
8773 regs[i].wasconst=0;
8774 alloc_cc(&current,i);
8775 dirty_reg(&current,CCREG);
8776 alloc_reg(&current,i,rs1[i]);
8777 if(!(current.is32>>rs1[i]&1))
8778 {
8779 alloc_reg64(&current,i,rs1[i]);
8780 }
8781 }
8782 ds=1;
8783 //current.isconst=0;
8784 break;
8785 case SJUMP:
8786 //current.isconst=0;
8787 //current.wasconst=0;
8788 //regs[i].wasconst=0;
8789 clear_const(&current,rs1[i]);
8790 clear_const(&current,rt1[i]);
8791 //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
8792 if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
8793 {
8794 alloc_cc(&current,i);
8795 dirty_reg(&current,CCREG);
8796 alloc_reg(&current,i,rs1[i]);
8797 if(!(current.is32>>rs1[i]&1))
8798 {
8799 alloc_reg64(&current,i,rs1[i]);
8800 }
8801 if (rt1[i]==31) { // BLTZAL/BGEZAL
8802 alloc_reg(&current,i,31);
8803 dirty_reg(&current,31);
8804 assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8805 //#ifdef REG_PREFETCH
8806 //alloc_reg(&current,i,PTEMP);
8807 //#endif
8808 //current.is32|=1LL<<rt1[i];
8809 }
8810 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
8811 // The delay slot overwrites the branch condition.
8812 // Allocate the branch condition registers instead.
8813 // Note that such a sequence of instructions could
8814 // be considered a bug since the branch can not be
8815 // re-executed if an exception occurs.
8816 current.isconst=0;
8817 current.wasconst=0;
8818 regs[i].wasconst=0;
8819 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8820 if(!((current.is32>>rs1[i])&1))
8821 {
8822 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8823 }
8824 }
8825 else delayslot_alloc(&current,i+1);
8826 }
8827 else
8828 // Don't alloc the delay slot yet because we might not execute it
8829 if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
8830 {
8831 current.isconst=0;
8832 current.wasconst=0;
8833 regs[i].wasconst=0;
8834 alloc_cc(&current,i);
8835 dirty_reg(&current,CCREG);
8836 alloc_reg(&current,i,rs1[i]);
8837 if(!(current.is32>>rs1[i]&1))
8838 {
8839 alloc_reg64(&current,i,rs1[i]);
8840 }
8841 }
8842 ds=1;
8843 //current.isconst=0;
8844 break;
8845 case FJUMP:
8846 current.isconst=0;
8847 current.wasconst=0;
8848 regs[i].wasconst=0;
8849 if(likely[i]==0) // BC1F/BC1T
8850 {
8851 // TODO: Theoretically we can run out of registers here on x86.
8852 // The delay slot can allocate up to six, and we need to check
8853 // CSREG before executing the delay slot. Possibly we can drop
8854 // the cycle count and then reload it after checking that the
8855 // FPU is in a usable state, or don't do out-of-order execution.
8856 alloc_cc(&current,i);
8857 dirty_reg(&current,CCREG);
8858 alloc_reg(&current,i,FSREG);
8859 alloc_reg(&current,i,CSREG);
8860 if(itype[i+1]==FCOMP) {
8861 // The delay slot overwrites the branch condition.
8862 // Allocate the branch condition registers instead.
8863 // Note that such a sequence of instructions could
8864 // be considered a bug since the branch can not be
8865 // re-executed if an exception occurs.
8866 alloc_cc(&current,i);
8867 dirty_reg(&current,CCREG);
8868 alloc_reg(&current,i,CSREG);
8869 alloc_reg(&current,i,FSREG);
8870 }
8871 else {
8872 delayslot_alloc(&current,i+1);
8873 alloc_reg(&current,i+1,CSREG);
8874 }
8875 }
8876 else
8877 // Don't alloc the delay slot yet because we might not execute it
8878 if(likely[i]) // BC1FL/BC1TL
8879 {
8880 alloc_cc(&current,i);
8881 dirty_reg(&current,CCREG);
8882 alloc_reg(&current,i,CSREG);
8883 alloc_reg(&current,i,FSREG);
8884 }
8885 ds=1;
8886 current.isconst=0;
8887 break;
8888 case IMM16:
8889 imm16_alloc(&current,i);
8890 break;
8891 case LOAD:
8892 case LOADLR:
8893 load_alloc(&current,i);
8894 break;
8895 case STORE:
8896 case STORELR:
8897 store_alloc(&current,i);
8898 break;
8899 case ALU:
8900 alu_alloc(&current,i);
8901 break;
8902 case SHIFT:
8903 shift_alloc(&current,i);
8904 break;
8905 case MULTDIV:
8906 multdiv_alloc(&current,i);
8907 break;
8908 case SHIFTIMM:
8909 shiftimm_alloc(&current,i);
8910 break;
8911 case MOV:
8912 mov_alloc(&current,i);
8913 break;
8914 case COP0:
8915 cop0_alloc(&current,i);
8916 break;
8917 case COP1:
b9b61529 8918 case COP2:
57871462 8919 cop1_alloc(&current,i);
8920 break;
8921 case C1LS:
8922 c1ls_alloc(&current,i);
8923 break;
b9b61529 8924 case C2LS:
8925 c2ls_alloc(&current,i);
8926 break;
8927 case C2OP:
8928 c2op_alloc(&current,i);
8929 break;
57871462 8930 case FCONV:
8931 fconv_alloc(&current,i);
8932 break;
8933 case FLOAT:
8934 float_alloc(&current,i);
8935 break;
8936 case FCOMP:
8937 fcomp_alloc(&current,i);
8938 break;
8939 case SYSCALL:
7139f3c8 8940 case HLECALL:
57871462 8941 syscall_alloc(&current,i);
8942 break;
8943 case SPAN:
8944 pagespan_alloc(&current,i);
8945 break;
8946 }
8947
8948 // Drop the upper half of registers that have become 32-bit
8949 current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
8950 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8951 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8952 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8953 current.uu|=1;
8954 } else {
8955 current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
8956 current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8957 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8958 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8959 current.uu|=1;
8960 }
8961
8962 // Create entry (branch target) regmap
8963 for(hr=0;hr<HOST_REGS;hr++)
8964 {
8965 int r,or,er;
8966 r=current.regmap[hr];
8967 if(r>=0) {
8968 if(r!=regmap_pre[i][hr]) {
8969 // TODO: delay slot (?)
8970 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
8971 if(or<0||(r&63)>=TEMPREG){
8972 regs[i].regmap_entry[hr]=-1;
8973 }
8974 else
8975 {
8976 // Just move it to a different register
8977 regs[i].regmap_entry[hr]=r;
8978 // If it was dirty before, it's still dirty
8979 if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r&63);
8980 }
8981 }
8982 else
8983 {
8984 // Unneeded
8985 if(r==0){
8986 regs[i].regmap_entry[hr]=0;
8987 }
8988 else
8989 if(r<64){
8990 if((current.u>>r)&1) {
8991 regs[i].regmap_entry[hr]=-1;
8992 //regs[i].regmap[hr]=-1;
8993 current.regmap[hr]=-1;
8994 }else
8995 regs[i].regmap_entry[hr]=r;
8996 }
8997 else {
8998 if((current.uu>>(r&63))&1) {
8999 regs[i].regmap_entry[hr]=-1;
9000 //regs[i].regmap[hr]=-1;
9001 current.regmap[hr]=-1;
9002 }else
9003 regs[i].regmap_entry[hr]=r;
9004 }
9005 }
9006 } else {
9007 // Branches expect CCREG to be allocated at the target
9008 if(regmap_pre[i][hr]==CCREG)
9009 regs[i].regmap_entry[hr]=CCREG;
9010 else
9011 regs[i].regmap_entry[hr]=-1;
9012 }
9013 }
9014 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9015 }
9016 /* Branch post-alloc */
9017 if(i>0)
9018 {
9019 current.was32=current.is32;
9020 current.wasdirty=current.dirty;
9021 switch(itype[i-1]) {
9022 case UJUMP:
9023 memcpy(&branch_regs[i-1],&current,sizeof(current));
9024 branch_regs[i-1].isconst=0;
9025 branch_regs[i-1].wasconst=0;
9026 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9027 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9028 alloc_cc(&branch_regs[i-1],i-1);
9029 dirty_reg(&branch_regs[i-1],CCREG);
9030 if(rt1[i-1]==31) { // JAL
9031 alloc_reg(&branch_regs[i-1],i-1,31);
9032 dirty_reg(&branch_regs[i-1],31);
9033 branch_regs[i-1].is32|=1LL<<31;
9034 }
9035 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9036 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9037 break;
9038 case RJUMP:
9039 memcpy(&branch_regs[i-1],&current,sizeof(current));
9040 branch_regs[i-1].isconst=0;
9041 branch_regs[i-1].wasconst=0;
9042 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9043 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9044 alloc_cc(&branch_regs[i-1],i-1);
9045 dirty_reg(&branch_regs[i-1],CCREG);
9046 alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
5067f341 9047 if(rt1[i-1]!=0) { // JALR
9048 alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9049 dirty_reg(&branch_regs[i-1],rt1[i-1]);
9050 branch_regs[i-1].is32|=1LL<<rt1[i-1];
57871462 9051 }
9052 #ifdef USE_MINI_HT
9053 if(rs1[i-1]==31) { // JALR
9054 alloc_reg(&branch_regs[i-1],i-1,RHASH);
9055 #ifndef HOST_IMM_ADDR32
9056 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9057 #endif
9058 }
9059 #endif
9060 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9061 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9062 break;
9063 case CJUMP:
9064 if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9065 {
9066 alloc_cc(&current,i-1);
9067 dirty_reg(&current,CCREG);
9068 if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9069 (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9070 // The delay slot overwrote one of our conditions
9071 // Delay slot goes after the test (in order)
9072 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9073 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9074 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9075 current.u|=1;
9076 current.uu|=1;
9077 delayslot_alloc(&current,i);
9078 current.isconst=0;
9079 }
9080 else
9081 {
9082 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9083 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9084 // Alloc the branch condition registers
9085 if(rs1[i-1]) alloc_reg(&current,i-1,rs1[i-1]);
9086 if(rs2[i-1]) alloc_reg(&current,i-1,rs2[i-1]);
9087 if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9088 {
9089 if(rs1[i-1]) alloc_reg64(&current,i-1,rs1[i-1]);
9090 if(rs2[i-1]) alloc_reg64(&current,i-1,rs2[i-1]);
9091 }
9092 }
9093 memcpy(&branch_regs[i-1],&current,sizeof(current));
9094 branch_regs[i-1].isconst=0;
9095 branch_regs[i-1].wasconst=0;
9096 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9097 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9098 }
9099 else
9100 if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9101 {
9102 alloc_cc(&current,i-1);
9103 dirty_reg(&current,CCREG);
9104 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9105 // The delay slot overwrote the branch condition
9106 // Delay slot goes after the test (in order)
9107 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9108 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9109 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9110 current.u|=1;
9111 current.uu|=1;
9112 delayslot_alloc(&current,i);
9113 current.isconst=0;
9114 }
9115 else
9116 {
9117 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9118 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9119 // Alloc the branch condition register
9120 alloc_reg(&current,i-1,rs1[i-1]);
9121 if(!(current.is32>>rs1[i-1]&1))
9122 {
9123 alloc_reg64(&current,i-1,rs1[i-1]);
9124 }
9125 }
9126 memcpy(&branch_regs[i-1],&current,sizeof(current));
9127 branch_regs[i-1].isconst=0;
9128 branch_regs[i-1].wasconst=0;
9129 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9130 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9131 }
9132 else
9133 // Alloc the delay slot in case the branch is taken
9134 if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9135 {
9136 memcpy(&branch_regs[i-1],&current,sizeof(current));
9137 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9138 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9139 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9140 alloc_cc(&branch_regs[i-1],i);
9141 dirty_reg(&branch_regs[i-1],CCREG);
9142 delayslot_alloc(&branch_regs[i-1],i);
9143 branch_regs[i-1].isconst=0;
9144 alloc_reg(&current,i,CCREG); // Not taken path
9145 dirty_reg(&current,CCREG);
9146 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9147 }
9148 else
9149 if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9150 {
9151 memcpy(&branch_regs[i-1],&current,sizeof(current));
9152 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9153 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9154 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9155 alloc_cc(&branch_regs[i-1],i);
9156 dirty_reg(&branch_regs[i-1],CCREG);
9157 delayslot_alloc(&branch_regs[i-1],i);
9158 branch_regs[i-1].isconst=0;
9159 alloc_reg(&current,i,CCREG); // Not taken path
9160 dirty_reg(&current,CCREG);
9161 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9162 }
9163 break;
9164 case SJUMP:
9165 //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9166 if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9167 {
9168 alloc_cc(&current,i-1);
9169 dirty_reg(&current,CCREG);
9170 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9171 // The delay slot overwrote the branch condition
9172 // Delay slot goes after the test (in order)
9173 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9174 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9175 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9176 current.u|=1;
9177 current.uu|=1;
9178 delayslot_alloc(&current,i);
9179 current.isconst=0;
9180 }
9181 else
9182 {
9183 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9184 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9185 // Alloc the branch condition register
9186 alloc_reg(&current,i-1,rs1[i-1]);
9187 if(!(current.is32>>rs1[i-1]&1))
9188 {
9189 alloc_reg64(&current,i-1,rs1[i-1]);
9190 }
9191 }
9192 memcpy(&branch_regs[i-1],&current,sizeof(current));
9193 branch_regs[i-1].isconst=0;
9194 branch_regs[i-1].wasconst=0;
9195 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9196 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9197 }
9198 else
9199 // Alloc the delay slot in case the branch is taken
9200 if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9201 {
9202 memcpy(&branch_regs[i-1],&current,sizeof(current));
9203 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9204 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9205 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9206 alloc_cc(&branch_regs[i-1],i);
9207 dirty_reg(&branch_regs[i-1],CCREG);
9208 delayslot_alloc(&branch_regs[i-1],i);
9209 branch_regs[i-1].isconst=0;
9210 alloc_reg(&current,i,CCREG); // Not taken path
9211 dirty_reg(&current,CCREG);
9212 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9213 }
9214 // FIXME: BLTZAL/BGEZAL
9215 if(opcode2[i-1]&0x10) { // BxxZAL
9216 alloc_reg(&branch_regs[i-1],i-1,31);
9217 dirty_reg(&branch_regs[i-1],31);
9218 branch_regs[i-1].is32|=1LL<<31;
9219 }
9220 break;
9221 case FJUMP:
9222 if(likely[i-1]==0) // BC1F/BC1T
9223 {
9224 alloc_cc(&current,i-1);
9225 dirty_reg(&current,CCREG);
9226 if(itype[i]==FCOMP) {
9227 // The delay slot overwrote the branch condition
9228 // Delay slot goes after the test (in order)
9229 delayslot_alloc(&current,i);
9230 current.isconst=0;
9231 }
9232 else
9233 {
9234 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9235 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9236 // Alloc the branch condition register
9237 alloc_reg(&current,i-1,FSREG);
9238 }
9239 memcpy(&branch_regs[i-1],&current,sizeof(current));
9240 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9241 }
9242 else // BC1FL/BC1TL
9243 {
9244 // Alloc the delay slot in case the branch is taken
9245 memcpy(&branch_regs[i-1],&current,sizeof(current));
9246 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9247 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9248 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9249 alloc_cc(&branch_regs[i-1],i);
9250 dirty_reg(&branch_regs[i-1],CCREG);
9251 delayslot_alloc(&branch_regs[i-1],i);
9252 branch_regs[i-1].isconst=0;
9253 alloc_reg(&current,i,CCREG); // Not taken path
9254 dirty_reg(&current,CCREG);
9255 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9256 }
9257 break;
9258 }
9259
9260 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9261 {
9262 if(rt1[i-1]==31) // JAL/JALR
9263 {
9264 // Subroutine call will return here, don't alloc any registers
9265 current.is32=1;
9266 current.dirty=0;
9267 clear_all_regs(current.regmap);
9268 alloc_reg(&current,i,CCREG);
9269 dirty_reg(&current,CCREG);
9270 }
9271 else if(i+1<slen)
9272 {
9273 // Internal branch will jump here, match registers to caller
9274 current.is32=0x3FFFFFFFFLL;
9275 current.dirty=0;
9276 clear_all_regs(current.regmap);
9277 alloc_reg(&current,i,CCREG);
9278 dirty_reg(&current,CCREG);
9279 for(j=i-1;j>=0;j--)
9280 {
9281 if(ba[j]==start+i*4+4) {
9282 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9283 current.is32=branch_regs[j].is32;
9284 current.dirty=branch_regs[j].dirty;
9285 break;
9286 }
9287 }
9288 while(j>=0) {
9289 if(ba[j]==start+i*4+4) {
9290 for(hr=0;hr<HOST_REGS;hr++) {
9291 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9292 current.regmap[hr]=-1;
9293 }
9294 current.is32&=branch_regs[j].is32;
9295 current.dirty&=branch_regs[j].dirty;
9296 }
9297 }
9298 j--;
9299 }
9300 }
9301 }
9302 }
9303
9304 // Count cycles in between branches
9305 ccadj[i]=cc;
7139f3c8 9306 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
57871462 9307 {
9308 cc=0;
9309 }
9310 else
9311 {
9312 cc++;
9313 }
9314
9315 flush_dirty_uppers(&current);
9316 if(!is_ds[i]) {
9317 regs[i].is32=current.is32;
9318 regs[i].dirty=current.dirty;
9319 regs[i].isconst=current.isconst;
9320 memcpy(constmap[i],current.constmap,sizeof(current.constmap));
9321 }
9322 for(hr=0;hr<HOST_REGS;hr++) {
9323 if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
9324 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9325 regs[i].wasconst&=~(1<<hr);
9326 }
9327 }
9328 }
9329 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9330 }
9331
9332 /* Pass 4 - Cull unused host registers */
9333
9334 uint64_t nr=0;
9335
9336 for (i=slen-1;i>=0;i--)
9337 {
9338 int hr;
9339 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9340 {
9341 if(ba[i]<start || ba[i]>=(start+slen*4))
9342 {
9343 // Branch out of this block, don't need anything
9344 nr=0;
9345 }
9346 else
9347 {
9348 // Internal branch
9349 // Need whatever matches the target
9350 nr=0;
9351 int t=(ba[i]-start)>>2;
9352 for(hr=0;hr<HOST_REGS;hr++)
9353 {
9354 if(regs[i].regmap_entry[hr]>=0) {
9355 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9356 }
9357 }
9358 }
9359 // Conditional branch may need registers for following instructions
9360 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9361 {
9362 if(i<slen-2) {
9363 nr|=needed_reg[i+2];
9364 for(hr=0;hr<HOST_REGS;hr++)
9365 {
9366 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9367 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9368 }
9369 }
9370 }
9371 // Don't need stuff which is overwritten
9372 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9373 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9374 // Merge in delay slot
9375 for(hr=0;hr<HOST_REGS;hr++)
9376 {
9377 if(!likely[i]) {
9378 // These are overwritten unless the branch is "likely"
9379 // and the delay slot is nullified if not taken
9380 if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9381 if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9382 }
9383 if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9384 if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9385 if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9386 if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9387 if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9388 if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9389 if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9390 if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9391 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9392 if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9393 if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9394 }
9395 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9396 if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9397 if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9398 }
b9b61529 9399 if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
57871462 9400 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9401 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9402 }
9403 }
9404 }
7139f3c8 9405 else if(itype[i]==SYSCALL||itype[i]==HLECALL)
57871462 9406 {
9407 // SYSCALL instruction (software interrupt)
9408 nr=0;
9409 }
9410 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9411 {
9412 // ERET instruction (return from interrupt)
9413 nr=0;
9414 }
9415 else // Non-branch
9416 {
9417 if(i<slen-1) {
9418 for(hr=0;hr<HOST_REGS;hr++) {
9419 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9420 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9421 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9422 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9423 }
9424 }
9425 }
9426 for(hr=0;hr<HOST_REGS;hr++)
9427 {
9428 // Overwritten registers are not needed
9429 if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9430 if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9431 if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9432 // Source registers are needed
9433 if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9434 if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9435 if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9436 if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9437 if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9438 if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9439 if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9440 if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9441 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9442 if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9443 if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9444 }
9445 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
9446 if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9447 if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9448 }
b9b61529 9449 if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
57871462 9450 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9451 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9452 }
9453 // Don't store a register immediately after writing it,
9454 // may prevent dual-issue.
9455 // But do so if this is a branch target, otherwise we
9456 // might have to load the register before the branch.
9457 if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
9458 if((regmap_pre[i][hr]>0&&regmap_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
9459 (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
9460 if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9461 if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9462 }
9463 if((regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
9464 (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
9465 if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9466 if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9467 }
9468 }
9469 }
9470 // Cycle count is needed at branches. Assume it is needed at the target too.
9471 if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
9472 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9473 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9474 }
9475 // Save it
9476 needed_reg[i]=nr;
9477
9478 // Deallocate unneeded registers
9479 for(hr=0;hr<HOST_REGS;hr++)
9480 {
9481 if(!((nr>>hr)&1)) {
9482 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
9483 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9484 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9485 (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
9486 {
9487 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9488 {
9489 if(likely[i]) {
9490 regs[i].regmap[hr]=-1;
9491 regs[i].isconst&=~(1<<hr);
9492 if(i<slen-2) regmap_pre[i+2][hr]=-1;
9493 }
9494 }
9495 }
9496 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9497 {
9498 int d1=0,d2=0,map=0,temp=0;
9499 if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
9500 {
9501 d1=dep1[i+1];
9502 d2=dep2[i+1];
9503 }
9504 if(using_tlb) {
9505 if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
9506 itype[i+1]==STORE || itype[i+1]==STORELR ||
b9b61529 9507 itype[i+1]==C1LS || itype[i+1]==C2LS)
57871462 9508 map=TLREG;
9509 } else
b9b61529 9510 if(itype[i+1]==STORE || itype[i+1]==STORELR ||
9511 (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
57871462 9512 map=INVCP;
9513 }
9514 if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
b9b61529 9515 itype[i+1]==C1LS || itype[i+1]==C2LS)
57871462 9516 temp=FTEMP;
9517 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9518 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9519 (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
9520 (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
9521 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9522 regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
9523 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
9524 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
9525 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
9526 regs[i].regmap[hr]!=map )
9527 {
9528 regs[i].regmap[hr]=-1;
9529 regs[i].isconst&=~(1<<hr);
9530 if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
9531 (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
9532 (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
9533 (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
9534 (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
9535 branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
9536 (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
9537 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
9538 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
9539 branch_regs[i].regmap[hr]!=map)
9540 {
9541 branch_regs[i].regmap[hr]=-1;
9542 branch_regs[i].regmap_entry[hr]=-1;
9543 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9544 {
9545 if(!likely[i]&&i<slen-2) {
9546 regmap_pre[i+2][hr]=-1;
9547 }
9548 }
9549 }
9550 }
9551 }
9552 else
9553 {
9554 // Non-branch
9555 if(i>0)
9556 {
9557 int d1=0,d2=0,map=-1,temp=-1;
9558 if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
9559 {
9560 d1=dep1[i];
9561 d2=dep2[i];
9562 }
9563 if(using_tlb) {
9564 if(itype[i]==LOAD || itype[i]==LOADLR ||
9565 itype[i]==STORE || itype[i]==STORELR ||
b9b61529 9566 itype[i]==C1LS || itype[i]==C2LS)
57871462 9567 map=TLREG;
b9b61529 9568 } else if(itype[i]==STORE || itype[i]==STORELR ||
9569 (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
57871462 9570 map=INVCP;
9571 }
9572 if(itype[i]==LOADLR || itype[i]==STORELR ||
b9b61529 9573 itype[i]==C1LS || itype[i]==C2LS)
57871462 9574 temp=FTEMP;
9575 if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9576 (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
9577 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9578 regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
9579 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
9580 (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
9581 {
9582 if(i<slen-1&&!is_ds[i]) {
9583 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
9584 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
9585 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
9586 {
9587 printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
9588 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
9589 }
9590 regmap_pre[i+1][hr]=-1;
9591 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
9592 }
9593 regs[i].regmap[hr]=-1;
9594 regs[i].isconst&=~(1<<hr);
9595 }
9596 }
9597 }
9598 }
9599 }
9600 }
9601
9602 /* Pass 5 - Pre-allocate registers */
9603
9604 // If a register is allocated during a loop, try to allocate it for the
9605 // entire loop, if possible. This avoids loading/storing registers
9606 // inside of the loop.
9607
9608 signed char f_regmap[HOST_REGS];
9609 clear_all_regs(f_regmap);
9610 for(i=0;i<slen-1;i++)
9611 {
9612 if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9613 {
9614 if(ba[i]>=start && ba[i]<(start+i*4))
9615 if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
9616 ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
9617 ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
9618 ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
b9b61529 9619 ||itype[i+1]==FCOMP||itype[i+1]==FCONV
9620 ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
57871462 9621 {
9622 int t=(ba[i]-start)>>2;
9623 if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
9624 if(t<2||(itype[t-2]!=UJUMP)) // call/ret assumes no registers allocated
9625 for(hr=0;hr<HOST_REGS;hr++)
9626 {
9627 if(regs[i].regmap[hr]>64) {
9628 if(!((regs[i].dirty>>hr)&1))
9629 f_regmap[hr]=regs[i].regmap[hr];
9630 else f_regmap[hr]=-1;
9631 }
9632 else if(regs[i].regmap[hr]>=0) f_regmap[hr]=regs[i].regmap[hr];
9633 if(branch_regs[i].regmap[hr]>64) {
9634 if(!((branch_regs[i].dirty>>hr)&1))
9635 f_regmap[hr]=branch_regs[i].regmap[hr];
9636 else f_regmap[hr]=-1;
9637 }
9638 else if(branch_regs[i].regmap[hr]>=0) f_regmap[hr]=branch_regs[i].regmap[hr];
9639 if(itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
9640 ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
b9b61529 9641 ||itype[i+1]==FCOMP||itype[i+1]==FCONV
9642 ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
57871462 9643 {
9644 // Test both in case the delay slot is ooo,
9645 // could be done better...
9646 if(count_free_regs(branch_regs[i].regmap)<2
9647 ||count_free_regs(regs[i].regmap)<2)
9648 f_regmap[hr]=branch_regs[i].regmap[hr];
9649 }
9650 // Avoid dirty->clean transition
9651 // #ifdef DESTRUCTIVE_WRITEBACK here?
9652 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
9653 if(f_regmap[hr]>0) {
9654 if(regs[t].regmap_entry[hr]<0) {
9655 int r=f_regmap[hr];
9656 for(j=t;j<=i;j++)
9657 {
9658 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9659 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
9660 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
9661 if(r>63) {
9662 // NB This can exclude the case where the upper-half
9663 // register is lower numbered than the lower-half
9664 // register. Not sure if it's worth fixing...
9665 if(get_reg(regs[j].regmap,r&63)<0) break;
9666 if(regs[j].is32&(1LL<<(r&63))) break;
9667 }
9668 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
9669 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9670 int k;
9671 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
9672 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
9673 if(r>63) {
9674 if(get_reg(regs[i].regmap,r&63)<0) break;
9675 if(get_reg(branch_regs[i].regmap,r&63)<0) break;
9676 }
9677 k=i;
9678 while(k>1&&regs[k-1].regmap[hr]==-1) {
9679 if(itype[k-1]==STORE||itype[k-1]==STORELR
9680 ||itype[k-1]==C1LS||itype[k-1]==SHIFT||itype[k-1]==COP1
b9b61529 9681 ||itype[k-1]==FLOAT||itype[k-1]==FCONV||itype[k-1]==FCOMP
9682 ||itype[k-1]==COP2||itype[k-1]==C2LS||itype[k-1]==C2OP) {
57871462 9683 if(count_free_regs(regs[k-1].regmap)<2) {
9684 //printf("no free regs for store %x\n",start+(k-1)*4);
9685 break;
9686 }
9687 }
9688 else
9689 if(itype[k-1]!=NOP&&itype[k-1]!=MOV&&itype[k-1]!=ALU&&itype[k-1]!=SHIFTIMM&&itype[k-1]!=IMM16&&itype[k-1]!=LOAD) break;
9690 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
9691 //printf("no-match due to different register\n");
9692 break;
9693 }
9694 if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
9695 //printf("no-match due to branch\n");
9696 break;
9697 }
9698 // call/ret fast path assumes no registers allocated
9699 if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)) {
9700 break;
9701 }
9702 if(r>63) {
9703 // NB This can exclude the case where the upper-half
9704 // register is lower numbered than the lower-half
9705 // register. Not sure if it's worth fixing...
9706 if(get_reg(regs[k-1].regmap,r&63)<0) break;
9707 if(regs[k-1].is32&(1LL<<(r&63))) break;
9708 }
9709 k--;
9710 }
9711 if(i<slen-1) {
9712 if((regs[k].is32&(1LL<<f_regmap[hr]))!=
9713 (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
9714 //printf("bad match after branch\n");
9715 break;
9716 }
9717 }
9718 if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
9719 //printf("Extend r%d, %x ->\n",hr,start+k*4);
9720 while(k<i) {
9721 regs[k].regmap_entry[hr]=f_regmap[hr];
9722 regs[k].regmap[hr]=f_regmap[hr];
9723 regmap_pre[k+1][hr]=f_regmap[hr];
9724 regs[k].wasdirty&=~(1<<hr);
9725 regs[k].dirty&=~(1<<hr);
9726 regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
9727 regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
9728 regs[k].wasconst&=~(1<<hr);
9729 regs[k].isconst&=~(1<<hr);
9730 k++;
9731 }
9732 }
9733 else {
9734 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
9735 break;
9736 }
9737 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
9738 if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
9739 //printf("OK fill %x (r%d)\n",start+i*4,hr);
9740 regs[i].regmap_entry[hr]=f_regmap[hr];
9741 regs[i].regmap[hr]=f_regmap[hr];
9742 regs[i].wasdirty&=~(1<<hr);
9743 regs[i].dirty&=~(1<<hr);
9744 regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
9745 regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
9746 regs[i].wasconst&=~(1<<hr);
9747 regs[i].isconst&=~(1<<hr);
9748 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
9749 branch_regs[i].wasdirty&=~(1<<hr);
9750 branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
9751 branch_regs[i].regmap[hr]=f_regmap[hr];
9752 branch_regs[i].dirty&=~(1<<hr);
9753 branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
9754 branch_regs[i].wasconst&=~(1<<hr);
9755 branch_regs[i].isconst&=~(1<<hr);
9756 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
9757 regmap_pre[i+2][hr]=f_regmap[hr];
9758 regs[i+2].wasdirty&=~(1<<hr);
9759 regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
9760 assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
9761 (regs[i+2].was32&(1LL<<f_regmap[hr])));
9762 }
9763 }
9764 }
9765 for(k=t;k<j;k++) {
9766 regs[k].regmap_entry[hr]=f_regmap[hr];
9767 regs[k].regmap[hr]=f_regmap[hr];
9768 regmap_pre[k+1][hr]=f_regmap[hr];
9769 regs[k+1].wasdirty&=~(1<<hr);
9770 regs[k].dirty&=~(1<<hr);
9771 regs[k].wasconst&=~(1<<hr);
9772 regs[k].isconst&=~(1<<hr);
9773 }
9774 if(regs[j].regmap[hr]==f_regmap[hr])
9775 regs[j].regmap_entry[hr]=f_regmap[hr];
9776 break;
9777 }
9778 if(j==i) break;
9779 if(regs[j].regmap[hr]>=0)
9780 break;
9781 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
9782 //printf("no-match due to different register\n");
9783 break;
9784 }
9785 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
9786 //printf("32/64 mismatch %x %d\n",start+j*4,hr);
9787 break;
9788 }
9789 if(itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS
9790 ||itype[j]==SHIFT||itype[j]==COP1||itype[j]==FLOAT
b9b61529 9791 ||itype[j]==FCOMP||itype[j]==FCONV
9792 ||itype[j]==COP2||itype[j]==C2LS||itype[j]==C2OP) {
57871462 9793 if(count_free_regs(regs[j].regmap)<2) {
9794 //printf("No free regs for store %x\n",start+j*4);
9795 break;
9796 }
9797 }
9798 else if(itype[j]!=NOP&&itype[j]!=MOV&&itype[j]!=ALU&&itype[j]!=SHIFTIMM&&itype[j]!=IMM16&&itype[j]!=LOAD) break;
9799 if(f_regmap[hr]>=64) {
9800 if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
9801 break;
9802 }
9803 else
9804 {
9805 if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
9806 break;
9807 }
9808 }
9809 }
9810 }
9811 }
9812 }
9813 }
9814 }
9815 }else{
9816 int count=0;
9817 for(hr=0;hr<HOST_REGS;hr++)
9818 {
9819 if(hr!=EXCLUDE_REG) {
9820 if(regs[i].regmap[hr]>64) {
9821 if(!((regs[i].dirty>>hr)&1))
9822 f_regmap[hr]=regs[i].regmap[hr];
9823 }
9824 else if(regs[i].regmap[hr]>=0) f_regmap[hr]=regs[i].regmap[hr];
9825 else if(regs[i].regmap[hr]<0) count++;
9826 }
9827 }
9828 // Try to restore cycle count at branch targets
9829 if(bt[i]) {
9830 for(j=i;j<slen-1;j++) {
9831 if(regs[j].regmap[HOST_CCREG]!=-1) break;
9832 if(itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS
9833 ||itype[j]==SHIFT||itype[j]==COP1||itype[j]==FLOAT
b9b61529 9834 ||itype[j]==FCOMP||itype[j]==FCONV
9835 ||itype[j]==COP2||itype[j]==C2LS||itype[j]==C2OP) {
57871462 9836 if(count_free_regs(regs[j].regmap)<2) {
9837 //printf("no free regs for store %x\n",start+j*4);
9838 break;
9839 }
9840 }
9841 else
9842 if(itype[j]!=NOP&&itype[j]!=MOV&&itype[j]!=ALU&&itype[j]!=SHIFTIMM&&itype[j]!=IMM16&&itype[j]!=LOAD) break;
9843 }
9844 if(regs[j].regmap[HOST_CCREG]==CCREG) {
9845 int k=i;
9846 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
9847 while(k<j) {
9848 regs[k].regmap_entry[HOST_CCREG]=CCREG;
9849 regs[k].regmap[HOST_CCREG]=CCREG;
9850 regmap_pre[k+1][HOST_CCREG]=CCREG;
9851 regs[k+1].wasdirty|=1<<HOST_CCREG;
9852 regs[k].dirty|=1<<HOST_CCREG;
9853 regs[k].wasconst&=~(1<<HOST_CCREG);
9854 regs[k].isconst&=~(1<<HOST_CCREG);
9855 k++;
9856 }
9857 regs[j].regmap_entry[HOST_CCREG]=CCREG;
9858 }
9859 // Work backwards from the branch target
9860 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
9861 {
9862 //printf("Extend backwards\n");
9863 int k;
9864 k=i;
9865 while(regs[k-1].regmap[HOST_CCREG]==-1) {
9866 if(itype[k-1]==STORE||itype[k-1]==STORELR||itype[k-1]==C1LS
9867 ||itype[k-1]==SHIFT||itype[k-1]==COP1||itype[k-1]==FLOAT
b9b61529 9868 ||itype[k-1]==FCONV||itype[k-1]==FCOMP
9869 ||itype[k-1]==COP2||itype[k-1]==C2LS||itype[k-1]==C2OP) {
57871462 9870 if(count_free_regs(regs[k-1].regmap)<2) {
9871 //printf("no free regs for store %x\n",start+(k-1)*4);
9872 break;
9873 }
9874 }
9875 else
9876 if(itype[k-1]!=NOP&&itype[k-1]!=MOV&&itype[k-1]!=ALU&&itype[k-1]!=SHIFTIMM&&itype[k-1]!=IMM16&&itype[k-1]!=LOAD) break;
9877 k--;
9878 }
9879 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
9880 //printf("Extend CC, %x ->\n",start+k*4);
9881 while(k<=i) {
9882 regs[k].regmap_entry[HOST_CCREG]=CCREG;
9883 regs[k].regmap[HOST_CCREG]=CCREG;
9884 regmap_pre[k+1][HOST_CCREG]=CCREG;
9885 regs[k+1].wasdirty|=1<<HOST_CCREG;
9886 regs[k].dirty|=1<<HOST_CCREG;
9887 regs[k].wasconst&=~(1<<HOST_CCREG);
9888 regs[k].isconst&=~(1<<HOST_CCREG);
9889 k++;
9890 }
9891 }
9892 else {
9893 //printf("Fail Extend CC, %x ->\n",start+k*4);
9894 }
9895 }
9896 }
9897 if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
9898 itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
9899 itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
b9b61529 9900 itype[i]!=FCONV&&itype[i]!=FCOMP&&
9901 itype[i]!=COP2&&itype[i]!=C2LS&&itype[i]!=C2OP)
57871462 9902 {
9903 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
9904 }
9905 }
9906 }
9907
9908 // This allocates registers (if possible) one instruction prior
9909 // to use, which can avoid a load-use penalty on certain CPUs.
9910 for(i=0;i<slen-1;i++)
9911 {
9912 if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
9913 {
9914 if(!bt[i+1])
9915 {
b9b61529 9916 if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
9917 ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
57871462 9918 {
9919 if(rs1[i+1]) {
9920 if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
9921 {
9922 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
9923 {
9924 regs[i].regmap[hr]=regs[i+1].regmap[hr];
9925 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
9926 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
9927 regs[i].isconst&=~(1<<hr);
9928 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9929 constmap[i][hr]=constmap[i+1][hr];
9930 regs[i+1].wasdirty&=~(1<<hr);
9931 regs[i].dirty&=~(1<<hr);
9932 }
9933 }
9934 }
9935 if(rs2[i+1]) {
9936 if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
9937 {
9938 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
9939 {
9940 regs[i].regmap[hr]=regs[i+1].regmap[hr];
9941 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
9942 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
9943 regs[i].isconst&=~(1<<hr);
9944 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9945 constmap[i][hr]=constmap[i+1][hr];
9946 regs[i+1].wasdirty&=~(1<<hr);
9947 regs[i].dirty&=~(1<<hr);
9948 }
9949 }
9950 }
9951 if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
9952 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
9953 {
9954 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
9955 {
9956 regs[i].regmap[hr]=rs1[i+1];
9957 regmap_pre[i+1][hr]=rs1[i+1];
9958 regs[i+1].regmap_entry[hr]=rs1[i+1];
9959 regs[i].isconst&=~(1<<hr);
9960 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9961 constmap[i][hr]=constmap[i+1][hr];
9962 regs[i+1].wasdirty&=~(1<<hr);
9963 regs[i].dirty&=~(1<<hr);
9964 }
9965 }
9966 }
9967 if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
9968 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
9969 {
9970 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
9971 {
9972 regs[i].regmap[hr]=rs1[i+1];
9973 regmap_pre[i+1][hr]=rs1[i+1];
9974 regs[i+1].regmap_entry[hr]=rs1[i+1];
9975 regs[i].isconst&=~(1<<hr);
9976 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9977 constmap[i][hr]=constmap[i+1][hr];
9978 regs[i+1].wasdirty&=~(1<<hr);
9979 regs[i].dirty&=~(1<<hr);
9980 }
9981 }
9982 }
9983 #ifndef HOST_IMM_ADDR32
b9b61529 9984 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
57871462 9985 hr=get_reg(regs[i+1].regmap,TLREG);
9986 if(hr>=0) {
9987 int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
9988 if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
9989 int nr;
9990 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
9991 {
9992 regs[i].regmap[hr]=MGEN1+((i+1)&1);
9993 regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
9994 regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
9995 regs[i].isconst&=~(1<<hr);
9996 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9997 constmap[i][hr]=constmap[i+1][hr];
9998 regs[i+1].wasdirty&=~(1<<hr);
9999 regs[i].dirty&=~(1<<hr);
10000 }
10001 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10002 {
10003 // move it to another register
10004 regs[i+1].regmap[hr]=-1;
10005 regmap_pre[i+2][hr]=-1;
10006 regs[i+1].regmap[nr]=TLREG;
10007 regmap_pre[i+2][nr]=TLREG;
10008 regs[i].regmap[nr]=MGEN1+((i+1)&1);
10009 regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10010 regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10011 regs[i].isconst&=~(1<<nr);
10012 regs[i+1].isconst&=~(1<<nr);
10013 regs[i].dirty&=~(1<<nr);
10014 regs[i+1].wasdirty&=~(1<<nr);
10015 regs[i+1].dirty&=~(1<<nr);
10016 regs[i+2].wasdirty&=~(1<<nr);
10017 }
10018 }
10019 }
10020 }
10021 #endif
b9b61529 10022 if(itype[i+1]==STORE||itype[i+1]==STORELR
10023 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
57871462 10024 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10025 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10026 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10027 else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10028 assert(hr>=0);
10029 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10030 {
10031 regs[i].regmap[hr]=rs1[i+1];
10032 regmap_pre[i+1][hr]=rs1[i+1];
10033 regs[i+1].regmap_entry[hr]=rs1[i+1];
10034 regs[i].isconst&=~(1<<hr);
10035 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10036 constmap[i][hr]=constmap[i+1][hr];
10037 regs[i+1].wasdirty&=~(1<<hr);
10038 regs[i].dirty&=~(1<<hr);
10039 }
10040 }
10041 }
b9b61529 10042 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
57871462 10043 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10044 int nr;
10045 hr=get_reg(regs[i+1].regmap,FTEMP);
10046 assert(hr>=0);
10047 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10048 {
10049 regs[i].regmap[hr]=rs1[i+1];
10050 regmap_pre[i+1][hr]=rs1[i+1];
10051 regs[i+1].regmap_entry[hr]=rs1[i+1];
10052 regs[i].isconst&=~(1<<hr);
10053 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10054 constmap[i][hr]=constmap[i+1][hr];
10055 regs[i+1].wasdirty&=~(1<<hr);
10056 regs[i].dirty&=~(1<<hr);
10057 }
10058 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10059 {
10060 // move it to another register
10061 regs[i+1].regmap[hr]=-1;
10062 regmap_pre[i+2][hr]=-1;
10063 regs[i+1].regmap[nr]=FTEMP;
10064 regmap_pre[i+2][nr]=FTEMP;
10065 regs[i].regmap[nr]=rs1[i+1];
10066 regmap_pre[i+1][nr]=rs1[i+1];
10067 regs[i+1].regmap_entry[nr]=rs1[i+1];
10068 regs[i].isconst&=~(1<<nr);
10069 regs[i+1].isconst&=~(1<<nr);
10070 regs[i].dirty&=~(1<<nr);
10071 regs[i+1].wasdirty&=~(1<<nr);
10072 regs[i+1].dirty&=~(1<<nr);
10073 regs[i+2].wasdirty&=~(1<<nr);
10074 }
10075 }
10076 }
b9b61529 10077 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
57871462 10078 if(itype[i+1]==LOAD)
10079 hr=get_reg(regs[i+1].regmap,rt1[i+1]);
b9b61529 10080 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
57871462 10081 hr=get_reg(regs[i+1].regmap,FTEMP);
b9b61529 10082 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
57871462 10083 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10084 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10085 }
10086 if(hr>=0&&regs[i].regmap[hr]<0) {
10087 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10088 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10089 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10090 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10091 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10092 regs[i].isconst&=~(1<<hr);
10093 regs[i+1].wasdirty&=~(1<<hr);
10094 regs[i].dirty&=~(1<<hr);
10095 }
10096 }
10097 }
10098 }
10099 }
10100 }
10101 }
10102
10103 /* Pass 6 - Optimize clean/dirty state */
10104 clean_registers(0,slen-1,1);
10105
10106 /* Pass 7 - Identify 32-bit registers */
10107
10108 provisional_r32();
10109
10110 u_int r32=0;
10111
10112 for (i=slen-1;i>=0;i--)
10113 {
10114 int hr;
10115 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10116 {
10117 if(ba[i]<start || ba[i]>=(start+slen*4))
10118 {
10119 // Branch out of this block, don't need anything
10120 r32=0;
10121 }
10122 else
10123 {
10124 // Internal branch
10125 // Need whatever matches the target
10126 // (and doesn't get overwritten by the delay slot instruction)
10127 r32=0;
10128 int t=(ba[i]-start)>>2;
10129 if(ba[i]>start+i*4) {
10130 // Forward branch
10131 if(!(requires_32bit[t]&~regs[i].was32))
10132 r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10133 }else{
10134 // Backward branch
10135 //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10136 // r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10137 if(!(pr32[t]&~regs[i].was32))
10138 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10139 }
10140 }
10141 // Conditional branch may need registers for following instructions
10142 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10143 {
10144 if(i<slen-2) {
10145 r32|=requires_32bit[i+2];
10146 r32&=regs[i].was32;
10147 // Mark this address as a branch target since it may be called
10148 // upon return from interrupt
10149 bt[i+2]=1;
10150 }
10151 }
10152 // Merge in delay slot
10153 if(!likely[i]) {
10154 // These are overwritten unless the branch is "likely"
10155 // and the delay slot is nullified if not taken
10156 r32&=~(1LL<<rt1[i+1]);
10157 r32&=~(1LL<<rt2[i+1]);
10158 }
10159 // Assume these are needed (delay slot)
10160 if(us1[i+1]>0)
10161 {
10162 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10163 }
10164 if(us2[i+1]>0)
10165 {
10166 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10167 }
10168 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10169 {
10170 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10171 }
10172 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10173 {
10174 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10175 }
10176 }
7139f3c8 10177 else if(itype[i]==SYSCALL||itype[i]==HLECALL)
57871462 10178 {
10179 // SYSCALL instruction (software interrupt)
10180 r32=0;
10181 }
10182 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10183 {
10184 // ERET instruction (return from interrupt)
10185 r32=0;
10186 }
10187 // Check 32 bits
10188 r32&=~(1LL<<rt1[i]);
10189 r32&=~(1LL<<rt2[i]);
10190 if(us1[i]>0)
10191 {
10192 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10193 }
10194 if(us2[i]>0)
10195 {
10196 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10197 }
10198 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
10199 {
10200 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
10201 }
10202 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
10203 {
10204 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
10205 }
10206 requires_32bit[i]=r32;
10207
10208 // Dirty registers which are 32-bit, require 32-bit input
10209 // as they will be written as 32-bit values
10210 for(hr=0;hr<HOST_REGS;hr++)
10211 {
10212 if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
10213 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
10214 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
10215 requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
10216 }
10217 }
10218 }
10219 //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
10220 }
10221
10222 if(itype[slen-1]==SPAN) {
10223 bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
10224 }
10225
10226 /* Debug/disassembly */
10227 if((void*)assem_debug==(void*)printf)
10228 for(i=0;i<slen;i++)
10229 {
10230 printf("U:");
10231 int r;
10232 for(r=1;r<=CCREG;r++) {
10233 if((unneeded_reg[i]>>r)&1) {
10234 if(r==HIREG) printf(" HI");
10235 else if(r==LOREG) printf(" LO");
10236 else printf(" r%d",r);
10237 }
10238 }
90ae6d4e 10239#ifndef FORCE32
57871462 10240 printf(" UU:");
10241 for(r=1;r<=CCREG;r++) {
10242 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
10243 if(r==HIREG) printf(" HI");
10244 else if(r==LOREG) printf(" LO");
10245 else printf(" r%d",r);
10246 }
10247 }
10248 printf(" 32:");
10249 for(r=0;r<=CCREG;r++) {
10250 //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10251 if((regs[i].was32>>r)&1) {
10252 if(r==CCREG) printf(" CC");
10253 else if(r==HIREG) printf(" HI");
10254 else if(r==LOREG) printf(" LO");
10255 else printf(" r%d",r);
10256 }
10257 }
90ae6d4e 10258#endif
57871462 10259 printf("\n");
10260 #if defined(__i386__) || defined(__x86_64__)
10261 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
10262 #endif
10263 #ifdef __arm__
10264 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
10265 #endif
10266 printf("needs: ");
10267 if(needed_reg[i]&1) printf("eax ");
10268 if((needed_reg[i]>>1)&1) printf("ecx ");
10269 if((needed_reg[i]>>2)&1) printf("edx ");
10270 if((needed_reg[i]>>3)&1) printf("ebx ");
10271 if((needed_reg[i]>>5)&1) printf("ebp ");
10272 if((needed_reg[i]>>6)&1) printf("esi ");
10273 if((needed_reg[i]>>7)&1) printf("edi ");
10274 printf("r:");
10275 for(r=0;r<=CCREG;r++) {
10276 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10277 if((requires_32bit[i]>>r)&1) {
10278 if(r==CCREG) printf(" CC");
10279 else if(r==HIREG) printf(" HI");
10280 else if(r==LOREG) printf(" LO");
10281 else printf(" r%d",r);
10282 }
10283 }
10284 printf("\n");
10285 /*printf("pr:");
10286 for(r=0;r<=CCREG;r++) {
10287 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10288 if((pr32[i]>>r)&1) {
10289 if(r==CCREG) printf(" CC");
10290 else if(r==HIREG) printf(" HI");
10291 else if(r==LOREG) printf(" LO");
10292 else printf(" r%d",r);
10293 }
10294 }
10295 if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
10296 printf("\n");*/
10297 #if defined(__i386__) || defined(__x86_64__)
10298 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
10299 printf("dirty: ");
10300 if(regs[i].wasdirty&1) printf("eax ");
10301 if((regs[i].wasdirty>>1)&1) printf("ecx ");
10302 if((regs[i].wasdirty>>2)&1) printf("edx ");
10303 if((regs[i].wasdirty>>3)&1) printf("ebx ");
10304 if((regs[i].wasdirty>>5)&1) printf("ebp ");
10305 if((regs[i].wasdirty>>6)&1) printf("esi ");
10306 if((regs[i].wasdirty>>7)&1) printf("edi ");
10307 #endif
10308 #ifdef __arm__
10309 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
10310 printf("dirty: ");
10311 if(regs[i].wasdirty&1) printf("r0 ");
10312 if((regs[i].wasdirty>>1)&1) printf("r1 ");
10313 if((regs[i].wasdirty>>2)&1) printf("r2 ");
10314 if((regs[i].wasdirty>>3)&1) printf("r3 ");
10315 if((regs[i].wasdirty>>4)&1) printf("r4 ");
10316 if((regs[i].wasdirty>>5)&1) printf("r5 ");
10317 if((regs[i].wasdirty>>6)&1) printf("r6 ");
10318 if((regs[i].wasdirty>>7)&1) printf("r7 ");
10319 if((regs[i].wasdirty>>8)&1) printf("r8 ");
10320 if((regs[i].wasdirty>>9)&1) printf("r9 ");
10321 if((regs[i].wasdirty>>10)&1) printf("r10 ");
10322 if((regs[i].wasdirty>>12)&1) printf("r12 ");
10323 #endif
10324 printf("\n");
10325 disassemble_inst(i);
10326 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
10327 #if defined(__i386__) || defined(__x86_64__)
10328 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
10329 if(regs[i].dirty&1) printf("eax ");
10330 if((regs[i].dirty>>1)&1) printf("ecx ");
10331 if((regs[i].dirty>>2)&1) printf("edx ");
10332 if((regs[i].dirty>>3)&1) printf("ebx ");
10333 if((regs[i].dirty>>5)&1) printf("ebp ");
10334 if((regs[i].dirty>>6)&1) printf("esi ");
10335 if((regs[i].dirty>>7)&1) printf("edi ");
10336 #endif
10337 #ifdef __arm__
10338 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
10339 if(regs[i].dirty&1) printf("r0 ");
10340 if((regs[i].dirty>>1)&1) printf("r1 ");
10341 if((regs[i].dirty>>2)&1) printf("r2 ");
10342 if((regs[i].dirty>>3)&1) printf("r3 ");
10343 if((regs[i].dirty>>4)&1) printf("r4 ");
10344 if((regs[i].dirty>>5)&1) printf("r5 ");
10345 if((regs[i].dirty>>6)&1) printf("r6 ");
10346 if((regs[i].dirty>>7)&1) printf("r7 ");
10347 if((regs[i].dirty>>8)&1) printf("r8 ");
10348 if((regs[i].dirty>>9)&1) printf("r9 ");
10349 if((regs[i].dirty>>10)&1) printf("r10 ");
10350 if((regs[i].dirty>>12)&1) printf("r12 ");
10351 #endif
10352 printf("\n");
10353 if(regs[i].isconst) {
10354 printf("constants: ");
10355 #if defined(__i386__) || defined(__x86_64__)
10356 if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
10357 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
10358 if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
10359 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
10360 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
10361 if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
10362 if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
10363 #endif
10364 #ifdef __arm__
10365 if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
10366 if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
10367 if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
10368 if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
10369 if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
10370 if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
10371 if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
10372 if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
10373 if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
10374 if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
10375 if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
10376 if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
10377 #endif
10378 printf("\n");
10379 }
90ae6d4e 10380#ifndef FORCE32
57871462 10381 printf(" 32:");
10382 for(r=0;r<=CCREG;r++) {
10383 if((regs[i].is32>>r)&1) {
10384 if(r==CCREG) printf(" CC");
10385 else if(r==HIREG) printf(" HI");
10386 else if(r==LOREG) printf(" LO");
10387 else printf(" r%d",r);
10388 }
10389 }
10390 printf("\n");
90ae6d4e 10391#endif
57871462 10392 /*printf(" p32:");
10393 for(r=0;r<=CCREG;r++) {
10394 if((p32[i]>>r)&1) {
10395 if(r==CCREG) printf(" CC");
10396 else if(r==HIREG) printf(" HI");
10397 else if(r==LOREG) printf(" LO");
10398 else printf(" r%d",r);
10399 }
10400 }
10401 if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
10402 else printf("\n");*/
10403 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10404 #if defined(__i386__) || defined(__x86_64__)
10405 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
10406 if(branch_regs[i].dirty&1) printf("eax ");
10407 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
10408 if((branch_regs[i].dirty>>2)&1) printf("edx ");
10409 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
10410 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
10411 if((branch_regs[i].dirty>>6)&1) printf("esi ");
10412 if((branch_regs[i].dirty>>7)&1) printf("edi ");
10413 #endif
10414 #ifdef __arm__
10415 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
10416 if(branch_regs[i].dirty&1) printf("r0 ");
10417 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
10418 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
10419 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
10420 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
10421 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
10422 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
10423 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
10424 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
10425 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
10426 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
10427 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
10428 #endif
90ae6d4e 10429#ifndef FORCE32
57871462 10430 printf(" 32:");
10431 for(r=0;r<=CCREG;r++) {
10432 if((branch_regs[i].is32>>r)&1) {
10433 if(r==CCREG) printf(" CC");
10434 else if(r==HIREG) printf(" HI");
10435 else if(r==LOREG) printf(" LO");
10436 else printf(" r%d",r);
10437 }
10438 }
10439 printf("\n");
90ae6d4e 10440#endif
57871462 10441 }
10442 }
10443
10444 /* Pass 8 - Assembly */
10445 linkcount=0;stubcount=0;
10446 ds=0;is_delayslot=0;
10447 cop1_usable=0;
10448 uint64_t is32_pre=0;
10449 u_int dirty_pre=0;
10450 u_int beginning=(u_int)out;
10451 if((u_int)addr&1) {
10452 ds=1;
10453 pagespan_ds();
10454 }
10455 for(i=0;i<slen;i++)
10456 {
10457 //if(ds) printf("ds: ");
10458 if((void*)assem_debug==(void*)printf) disassemble_inst(i);
10459 if(ds) {
10460 ds=0; // Skip delay slot
10461 if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
10462 instr_addr[i]=0;
10463 } else {
10464 #ifndef DESTRUCTIVE_WRITEBACK
10465 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10466 {
10467 wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
10468 unneeded_reg[i],unneeded_reg_upper[i]);
10469 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
10470 unneeded_reg[i],unneeded_reg_upper[i]);
10471 }
10472 is32_pre=regs[i].is32;
10473 dirty_pre=regs[i].dirty;
10474 #endif
10475 // write back
10476 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10477 {
10478 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
10479 unneeded_reg[i],unneeded_reg_upper[i]);
10480 loop_preload(regmap_pre[i],regs[i].regmap_entry);
10481 }
10482 // branch target entry point
10483 instr_addr[i]=(u_int)out;
10484 assem_debug("<->\n");
10485 // load regs
10486 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
10487 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
10488 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
10489 address_generation(i,&regs[i],regs[i].regmap_entry);
10490 load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
10491 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10492 {
10493 // Load the delay slot registers if necessary
10494 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10495 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10496 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10497 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
b9b61529 10498 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
57871462 10499 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10500 }
10501 else if(i+1<slen)
10502 {
10503 // Preload registers for following instruction
10504 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10505 if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
10506 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10507 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10508 if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
10509 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
10510 }
10511 // TODO: if(is_ooo(i)) address_generation(i+1);
10512 if(itype[i]==CJUMP||itype[i]==FJUMP)
10513 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
b9b61529 10514 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
57871462 10515 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10516 if(bt[i]) cop1_usable=0;
10517 // assemble
10518 switch(itype[i]) {
10519 case ALU:
10520 alu_assemble(i,&regs[i]);break;
10521 case IMM16:
10522 imm16_assemble(i,&regs[i]);break;
10523 case SHIFT:
10524 shift_assemble(i,&regs[i]);break;
10525 case SHIFTIMM:
10526 shiftimm_assemble(i,&regs[i]);break;
10527 case LOAD:
10528 load_assemble(i,&regs[i]);break;
10529 case LOADLR:
10530 loadlr_assemble(i,&regs[i]);break;
10531 case STORE:
10532 store_assemble(i,&regs[i]);break;
10533 case STORELR:
10534 storelr_assemble(i,&regs[i]);break;
10535 case COP0:
10536 cop0_assemble(i,&regs[i]);break;
10537 case COP1:
10538 cop1_assemble(i,&regs[i]);break;
10539 case C1LS:
10540 c1ls_assemble(i,&regs[i]);break;
b9b61529 10541 case COP2:
10542 cop2_assemble(i,&regs[i]);break;
10543 case C2LS:
10544 c2ls_assemble(i,&regs[i]);break;
10545 case C2OP:
10546 c2op_assemble(i,&regs[i]);break;
57871462 10547 case FCONV:
10548 fconv_assemble(i,&regs[i]);break;
10549 case FLOAT:
10550 float_assemble(i,&regs[i]);break;
10551 case FCOMP:
10552 fcomp_assemble(i,&regs[i]);break;
10553 case MULTDIV:
10554 multdiv_assemble(i,&regs[i]);break;
10555 case MOV:
10556 mov_assemble(i,&regs[i]);break;
10557 case SYSCALL:
10558 syscall_assemble(i,&regs[i]);break;
7139f3c8 10559 case HLECALL:
10560 hlecall_assemble(i,&regs[i]);break;
57871462 10561 case UJUMP:
10562 ujump_assemble(i,&regs[i]);ds=1;break;
10563 case RJUMP:
10564 rjump_assemble(i,&regs[i]);ds=1;break;
10565 case CJUMP:
10566 cjump_assemble(i,&regs[i]);ds=1;break;
10567 case SJUMP:
10568 sjump_assemble(i,&regs[i]);ds=1;break;
10569 case FJUMP:
10570 fjump_assemble(i,&regs[i]);ds=1;break;
10571 case SPAN:
10572 pagespan_assemble(i,&regs[i]);break;
10573 }
10574 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10575 literal_pool(1024);
10576 else
10577 literal_pool_jumpover(256);
10578 }
10579 }
10580 //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
10581 // If the block did not end with an unconditional branch,
10582 // add a jump to the next instruction.
10583 if(i>1) {
10584 if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
10585 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10586 assert(i==slen);
10587 if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
10588 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10589 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10590 emit_loadreg(CCREG,HOST_CCREG);
10591 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10592 }
10593 else if(!likely[i-2])
10594 {
10595 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
10596 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
10597 }
10598 else
10599 {
10600 store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
10601 assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
10602 }
10603 add_to_linker((int)out,start+i*4,0);
10604 emit_jmp(0);
10605 }
10606 }
10607 else
10608 {
10609 assert(i>0);
10610 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10611 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10612 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10613 emit_loadreg(CCREG,HOST_CCREG);
10614 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10615 add_to_linker((int)out,start+i*4,0);
10616 emit_jmp(0);
10617 }
10618
10619 // TODO: delay slot stubs?
10620 // Stubs
10621 for(i=0;i<stubcount;i++)
10622 {
10623 switch(stubs[i][0])
10624 {
10625 case LOADB_STUB:
10626 case LOADH_STUB:
10627 case LOADW_STUB:
10628 case LOADD_STUB:
10629 case LOADBU_STUB:
10630 case LOADHU_STUB:
10631 do_readstub(i);break;
10632 case STOREB_STUB:
10633 case STOREH_STUB:
10634 case STOREW_STUB:
10635 case STORED_STUB:
10636 do_writestub(i);break;
10637 case CC_STUB:
10638 do_ccstub(i);break;
10639 case INVCODE_STUB:
10640 do_invstub(i);break;
10641 case FP_STUB:
10642 do_cop1stub(i);break;
10643 case STORELR_STUB:
10644 do_unalignedwritestub(i);break;
10645 }
10646 }
10647
10648 /* Pass 9 - Linker */
10649 for(i=0;i<linkcount;i++)
10650 {
10651 assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
10652 literal_pool(64);
10653 if(!link_addr[i][2])
10654 {
10655 void *stub=out;
10656 void *addr=check_addr(link_addr[i][1]);
10657 emit_extjump(link_addr[i][0],link_addr[i][1]);
10658 if(addr) {
10659 set_jump_target(link_addr[i][0],(int)addr);
10660 add_link(link_addr[i][1],stub);
10661 }
10662 else set_jump_target(link_addr[i][0],(int)stub);
10663 }
10664 else
10665 {
10666 // Internal branch
10667 int target=(link_addr[i][1]-start)>>2;
10668 assert(target>=0&&target<slen);
10669 assert(instr_addr[target]);
10670 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10671 //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
10672 //#else
10673 set_jump_target(link_addr[i][0],instr_addr[target]);
10674 //#endif
10675 }
10676 }
10677 // External Branch Targets (jump_in)
10678 if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
10679 for(i=0;i<slen;i++)
10680 {
10681 if(bt[i]||i==0)
10682 {
10683 if(instr_addr[i]) // TODO - delay slots (=null)
10684 {
10685 u_int vaddr=start+i*4;
94d23bb9 10686 u_int page=get_page(vaddr);
10687 u_int vpage=get_vpage(vaddr);
57871462 10688 literal_pool(256);
10689 //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
10690 if(!requires_32bit[i])
10691 {
10692 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
10693 assem_debug("jump_in: %x\n",start+i*4);
10694 ll_add(jump_dirty+vpage,vaddr,(void *)out);
10695 int entry_point=do_dirty_stub(i);
10696 ll_add(jump_in+page,vaddr,(void *)entry_point);
10697 // If there was an existing entry in the hash table,
10698 // replace it with the new address.
10699 // Don't add new entries. We'll insert the
10700 // ones that actually get used in check_addr().
10701 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
10702 if(ht_bin[0]==vaddr) {
10703 ht_bin[1]=entry_point;
10704 }
10705 if(ht_bin[2]==vaddr) {
10706 ht_bin[3]=entry_point;
10707 }
10708 }
10709 else
10710 {
10711 u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
10712 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
10713 assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
10714 //int entry_point=(int)out;
10715 ////assem_debug("entry_point: %x\n",entry_point);
10716 //load_regs_entry(i);
10717 //if(entry_point==(int)out)
10718 // entry_point=instr_addr[i];
10719 //else
10720 // emit_jmp(instr_addr[i]);
10721 //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
10722 ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
10723 int entry_point=do_dirty_stub(i);
10724 ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
10725 }
10726 }
10727 }
10728 }
10729 // Write out the literal pool if necessary
10730 literal_pool(0);
10731 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10732 // Align code
10733 if(((u_int)out)&7) emit_addnop(13);
10734 #endif
10735 assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
10736 //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
10737 memcpy(copy,source,slen*4);
10738 copy+=slen*4;
10739
10740 #ifdef __arm__
10741 __clear_cache((void *)beginning,out);
10742 #endif
10743
10744 // If we're within 256K of the end of the buffer,
10745 // start over from the beginning. (Is 256K enough?)
10746 if((int)out>BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
10747
10748 // Trap writes to any of the pages we compiled
10749 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
10750 invalid_code[i]=0;
90ae6d4e 10751#ifndef DISABLE_TLB
57871462 10752 memory_map[i]|=0x40000000;
10753 if((signed int)start>=(signed int)0xC0000000) {
10754 assert(using_tlb);
10755 j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
10756 invalid_code[j]=0;
10757 memory_map[j]|=0x40000000;
10758 //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
10759 }
90ae6d4e 10760#endif
57871462 10761 }
10762
10763 /* Pass 10 - Free memory by expiring oldest blocks */
10764
10765 int end=((((int)out-BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
10766 while(expirep!=end)
10767 {
10768 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
10769 int base=BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
10770 inv_debug("EXP: Phase %d\n",expirep);
10771 switch((expirep>>11)&3)
10772 {
10773 case 0:
10774 // Clear jump_in and jump_dirty
10775 ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
10776 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
10777 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
10778 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
10779 break;
10780 case 1:
10781 // Clear pointers
10782 ll_kill_pointers(jump_out[expirep&2047],base,shift);
10783 ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
10784 break;
10785 case 2:
10786 // Clear hash table
10787 for(i=0;i<32;i++) {
10788 int *ht_bin=hash_table[((expirep&2047)<<5)+i];
10789 if((ht_bin[3]>>shift)==(base>>shift) ||
10790 ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
10791 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
10792 ht_bin[2]=ht_bin[3]=-1;
10793 }
10794 if((ht_bin[1]>>shift)==(base>>shift) ||
10795 ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
10796 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
10797 ht_bin[0]=ht_bin[2];
10798 ht_bin[1]=ht_bin[3];
10799 ht_bin[2]=ht_bin[3]=-1;
10800 }
10801 }
10802 break;
10803 case 3:
10804 // Clear jump_out
10805 #ifdef __arm__
10806 if((expirep&2047)==0)
10807 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
10808 #endif
10809 ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
10810 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
10811 break;
10812 }
10813 expirep=(expirep+1)&65535;
10814 }
10815 return 0;
10816}
b9b61529 10817
10818// vim:shiftwidth=2:expandtab
ARM optimized PCSX fork