[pcsx_rearmed.git] / libpcsxcore / new_dynarec / pcsxmem.c

/*
 * (C) Gražvydas "notaz" Ignotas, 2010-2011
 *
 * This work is licensed under the terms of GNU GPL version 2 or later.
 * See the COPYING file in the top-level directory.
 */

#include <stdio.h>
#include <sys/mman.h>
#include "../psxhw.h"
#include "../cdrom.h"
#include "../mdec.h"
#include "emu_if.h"
#include "pcsxmem.h"

//#define memprintf printf
#define memprintf(...)

static u32 *mem_readtab;
static u32 *mem_writetab;
static u32 mem_iortab[(1+2+4) * 0x1000 / 4];
static u32 mem_iowtab[(1+2+4) * 0x1000 / 4];
static u32 mem_ffwtab[(1+2+4) * 0x1000 / 4];
//static u32 mem_unmrtab[(1+2+4) * 0x1000 / 4];
static u32 mem_unmwtab[(1+2+4) * 0x1000 / 4];

static void map_item(u32 *out, const void *h, u32 flag)
{
	u32 hv = (u32)h;
	if (hv & 1)
		fprintf(stderr, "%p has LSB set\n", h);
	*out = (hv >> 1) | (flag << 31);
}

// size must be power of 2, at least 4k
#define map_l1_mem(tab, i, addr, size, base) \
	map_item(&tab[((addr)>>12) + i], (u8 *)(base) - (u32)(addr) - ((i << 12) & ~(size - 1)), 0)

#define IOMEM32(a) (((a) & 0xfff) / 4)
#define IOMEM16(a) (0x1000/4 + (((a) & 0xfff) / 2))
#define IOMEM8(a)  (0x1000/4 + 0x1000/2 + ((a) & 0xfff))

static u8 unmapped_mem[0x1000];

u32 read_mem_dummy()
{
	return 0;
}

static void write_mem_dummy(u32 data)
{
	memprintf("unmapped w %08x, %08x @%08x %u\n", address, data, psxRegs.pc, psxRegs.cycle);
}

/* IO handlers */
static u32 io_read_sio16()
{
	return sioRead8() | (sioRead8() << 8);
}

static u32 io_read_sio32()
{
	return sioRead8() | (sioRead8() << 8) | (sioRead8() << 16) | (sioRead8() << 24);
}

static void io_write_sio16(u32 value)
{
	sioWrite8((unsigned char)value);
	sioWrite8((unsigned char)(value>>8));
}

static void io_write_sio32(u32 value)
{
	sioWrite8((unsigned char)value);
	sioWrite8((unsigned char)(value >>  8));
	sioWrite8((unsigned char)(value >> 16));
	sioWrite8((unsigned char)(value >> 24));
}

static void map_rcnt_rcount0(u32 mode)
{
	if (mode & 0x01) { // gate
		map_item(&mem_iortab[IOMEM32(0x1100)], &psxH[0x1000], 0);
		map_item(&mem_iortab[IOMEM16(0x1100)], &psxH[0x1000], 0);
	}
	else if (mode & 0x100) { // pixel clock
		map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m1, 1);
		map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m1, 1);
	}
	else {
		map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m0, 1);
		map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m0, 1);
	}
}

static void map_rcnt_rcount1(u32 mode)
{
	if (mode & 0x01) { // gate
		map_item(&mem_iortab[IOMEM32(0x1110)], &psxH[0x1000], 0);
		map_item(&mem_iortab[IOMEM16(0x1110)], &psxH[0x1000], 0);
	}
	else if (mode & 0x100) { // hcnt
		map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m1, 1);
		map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m1, 1);
	}
	else {
		map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m0, 1);
		map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m0, 1);
	}
}

static void map_rcnt_rcount2(u32 mode)
{
	if (mode & 0x01) { // gate
		map_item(&mem_iortab[IOMEM32(0x1120)], &psxH[0x1000], 0);
		map_item(&mem_iortab[IOMEM16(0x1120)], &psxH[0x1000], 0);
	}
	else if (mode & 0x200) { // clk/8
		map_item(&mem_iortab[IOMEM32(0x1120)], rcnt2_read_count_m1, 1);
		map_item(&mem_iortab[IOMEM16(0x1120)], rcnt2_read_count_m1, 1);
	}
	else {
		map_item(&mem_iortab[IOMEM32(0x1120)], rcnt2_read_count_m0, 1);
		map_item(&mem_iortab[IOMEM16(0x1120)], rcnt2_read_count_m0, 1);
	}
}

#define make_rcnt_funcs(i) \
static u32 io_rcnt_read_count##i()  { return psxRcntRcount(i); } \
static u32 io_rcnt_read_mode##i()   { return psxRcntRmode(i); } \
static u32 io_rcnt_read_target##i() { return psxRcntRtarget(i); } \
static void io_rcnt_write_count##i(u32 val)  { psxRcntWcount(i, val & 0xffff); } \
static void io_rcnt_write_mode##i(u32 val)   { psxRcntWmode(i, val); map_rcnt_rcount##i(val); } \
static void io_rcnt_write_target##i(u32 val) { psxRcntWtarget(i, val & 0xffff); }

make_rcnt_funcs(0)
make_rcnt_funcs(1)
make_rcnt_funcs(2)

static void io_write_ireg16(u32 value)
{
	if (Config.Sio) psxHu16ref(0x1070) |= 0x80;
	if (Config.SpuIrq) psxHu16ref(0x1070) |= 0x200;
	psxHu16ref(0x1070) &= psxHu16(0x1074) & value;
}

static void io_write_imask16(u32 value)
{
	psxHu16ref(0x1074) = value;
	if (psxHu16ref(0x1070) & value)
		new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
}

static void io_write_ireg32(u32 value)
{
	if (Config.Sio) psxHu32ref(0x1070) |= 0x80;
	if (Config.SpuIrq) psxHu32ref(0x1070) |= 0x200;
	psxHu32ref(0x1070) &= psxHu32(0x1074) & value;
}

static void io_write_imask32(u32 value)
{
	psxHu32ref(0x1074) = value;
	if (psxHu32ref(0x1070) & value)
		new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
}

static void io_write_dma_icr32(u32 value)
{
	u32 tmp = value & 0x00ff803f;
	tmp |= (SWAPu32(HW_DMA_ICR) & ~value) & 0x7f000000;
	if ((tmp & HW_DMA_ICR_GLOBAL_ENABLE && tmp & 0x7f000000)
	    || tmp & HW_DMA_ICR_BUS_ERROR) {
		if (!(SWAPu32(HW_DMA_ICR) & HW_DMA_ICR_IRQ_SENT))
			psxHu32ref(0x1070) |= SWAP32(8);
		tmp |= HW_DMA_ICR_IRQ_SENT;
	}
	HW_DMA_ICR = SWAPu32(tmp);
}

#define make_dma_func(n) \
static void io_write_chcr##n(u32 value) \
{ \
	HW_DMA##n##_CHCR = value; \
	if (value & 0x01000000 && HW_DMA_PCR & (8 << (n * 4))) { \
		psxDma##n(HW_DMA##n##_MADR, HW_DMA##n##_BCR, value); \
	} \
}

make_dma_func(0)
make_dma_func(1)
make_dma_func(2)
make_dma_func(3)
make_dma_func(4)
make_dma_func(6)

static void io_spu_write16(u32 value)
{
	// meh
	SPU_writeRegister(address, value);
}

static void io_spu_write32(u32 value)
{
	SPUwriteRegister wfunc = SPU_writeRegister;
	u32 a = address;

	wfunc(a, value & 0xffff);
	wfunc(a + 2, value >> 16);
}

static void map_ram_write(void)
{
	int i;

	for (i = 0; i < (0x800000 >> 12); i++) {
		map_l1_mem(mem_writetab, i, 0x80000000, 0x200000, psxM);
		map_l1_mem(mem_writetab, i, 0x00000000, 0x200000, psxM);
		map_l1_mem(mem_writetab, i, 0xa0000000, 0x200000, psxM);
	}
}

static void unmap_ram_write(void)
{
	int i;

	for (i = 0; i < (0x800000 >> 12); i++) {
		map_item(&mem_writetab[0x80000|i], mem_unmwtab, 1);
		map_item(&mem_writetab[0x00000|i], mem_unmwtab, 1);
		map_item(&mem_writetab[0xa0000|i], mem_unmwtab, 1);
	}
}

static void write_biu(u32 value)
{
	memprintf("write_biu %08x, %08x @%08x %u\n", address, value, psxRegs.pc, psxRegs.cycle);

	if (address != 0xfffe0130)
		return;

	switch (value) {
	case 0x800: case 0x804:
		unmap_ram_write();
		break;
	case 0: case 0x1e988:
		map_ram_write();
		break;
	default:
		printf("write_biu: unexpected val: %08x\n", value);
		break;
	}
}

void new_dyna_pcsx_mem_load_state(void)
{
	map_rcnt_rcount0(rcnts[0].mode);
	map_rcnt_rcount1(rcnts[1].mode);
	map_rcnt_rcount2(rcnts[2].mode);
}

int pcsxmem_is_handler_dynamic(u_int addr)
{
	if ((addr & 0xfffff000) != 0x1f801000)
		return 0;

	addr &= 0xffff;
	return addr == 0x1100 || addr == 0x1110 || addr == 0x1120;
}

void new_dyna_pcsx_mem_init(void)
{
	int i;

	// have to map these further to keep tcache close to .text
	mem_readtab = mmap((void *)0x08000000, 0x200000 * 4, PROT_READ | PROT_WRITE,
		MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
	if (mem_readtab == MAP_FAILED) {
		fprintf(stderr, "failed to map mem tables\n");
		exit(1);
	}
	mem_writetab = mem_readtab + 0x100000;

	// 1st level lookup:
	//   0: direct mem
	//   1: use 2nd lookup
	// 2nd level lookup:
	//   0: direct mem variable
	//   1: memhandler

	// default/unmapped memhandlers
	for (i = 0; i < 0x100000; i++) {
		//map_item(&mem_readtab[i], mem_unmrtab, 1);
		map_l1_mem(mem_readtab, i, 0, 0x1000, unmapped_mem);
		map_item(&mem_writetab[i], mem_unmwtab, 1);
	}

	// RAM and it's mirrors
	for (i = 0; i < (0x800000 >> 12); i++) {
		map_l1_mem(mem_readtab,  i, 0x80000000, 0x200000, psxM);
		map_l1_mem(mem_readtab,  i, 0x00000000, 0x200000, psxM);
		map_l1_mem(mem_readtab,  i, 0xa0000000, 0x200000, psxM);
	}
	map_ram_write();

	// BIOS and it's mirrors
	for (i = 0; i < (0x80000 >> 12); i++) {
		map_l1_mem(mem_readtab, i, 0x1fc00000, 0x80000, psxR);
		map_l1_mem(mem_readtab, i, 0xbfc00000, 0x80000, psxR);
	}

	// scratchpad
	map_l1_mem(mem_readtab, 0, 0x1f800000, 0x1000, psxH);
	map_l1_mem(mem_writetab, 0, 0x1f800000, 0x1000, psxH);

	// I/O
	map_item(&mem_readtab[0x1f801000 >> 12], mem_iortab, 1);
	map_item(&mem_writetab[0x1f801000 >> 12], mem_iowtab, 1);

	// L2
	// unmapped tables
	for (i = 0; i < (1+2+4) * 0x1000 / 4; i++)
		map_item(&mem_unmwtab[i], write_mem_dummy, 1);

	// fill IO tables
	for (i = 0; i < 0x1000/4; i++) {
		map_item(&mem_iortab[i], &psxH[0x1000], 0);
		map_item(&mem_iowtab[i], &psxH[0x1000], 0);
	}
	for (; i < 0x1000/4 + 0x1000/2; i++) {
		map_item(&mem_iortab[i], &psxH[0x1000], 0);
		map_item(&mem_iowtab[i], &psxH[0x1000], 0);
	}
	for (; i < 0x1000/4 + 0x1000/2 + 0x1000; i++) {
		map_item(&mem_iortab[i], &psxH[0x1000], 0);
		map_item(&mem_iowtab[i], &psxH[0x1000], 0);
	}

	map_item(&mem_iortab[IOMEM32(0x1040)], io_read_sio32, 1);
	map_item(&mem_iortab[IOMEM32(0x1100)], io_rcnt_read_count0, 1);
	map_item(&mem_iortab[IOMEM32(0x1104)], io_rcnt_read_mode0, 1);
	map_item(&mem_iortab[IOMEM32(0x1108)], io_rcnt_read_target0, 1);
	map_item(&mem_iortab[IOMEM32(0x1110)], io_rcnt_read_count1, 1);
	map_item(&mem_iortab[IOMEM32(0x1114)], io_rcnt_read_mode1, 1);
	map_item(&mem_iortab[IOMEM32(0x1118)], io_rcnt_read_target1, 1);
	map_item(&mem_iortab[IOMEM32(0x1120)], io_rcnt_read_count2, 1);
	map_item(&mem_iortab[IOMEM32(0x1124)], io_rcnt_read_mode2, 1);
	map_item(&mem_iortab[IOMEM32(0x1128)], io_rcnt_read_target2, 1);
//	map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1);
//	map_item(&mem_iortab[IOMEM32(0x1814)], GPU_readStatus, 1);
	map_item(&mem_iortab[IOMEM32(0x1820)], mdecRead0, 1);
	map_item(&mem_iortab[IOMEM32(0x1824)], mdecRead1, 1);

	map_item(&mem_iortab[IOMEM16(0x1040)], io_read_sio16, 1);
	map_item(&mem_iortab[IOMEM16(0x1044)], sioReadStat16, 1);
	map_item(&mem_iortab[IOMEM16(0x1048)], sioReadMode16, 1);
	map_item(&mem_iortab[IOMEM16(0x104a)], sioReadCtrl16, 1);
	map_item(&mem_iortab[IOMEM16(0x104e)], sioReadBaud16, 1);
	map_item(&mem_iortab[IOMEM16(0x1100)], io_rcnt_read_count0, 1);
	map_item(&mem_iortab[IOMEM16(0x1104)], io_rcnt_read_mode0, 1);
	map_item(&mem_iortab[IOMEM16(0x1108)], io_rcnt_read_target0, 1);
	map_item(&mem_iortab[IOMEM16(0x1110)], io_rcnt_read_count1, 1);
	map_item(&mem_iortab[IOMEM16(0x1114)], io_rcnt_read_mode1, 1);
	map_item(&mem_iortab[IOMEM16(0x1118)], io_rcnt_read_target1, 1);
	map_item(&mem_iortab[IOMEM16(0x1120)], io_rcnt_read_count2, 1);
	map_item(&mem_iortab[IOMEM16(0x1124)], io_rcnt_read_mode2, 1);
	map_item(&mem_iortab[IOMEM16(0x1128)], io_rcnt_read_target2, 1);

	map_item(&mem_iortab[IOMEM8(0x1040)], sioRead8, 1);
	map_item(&mem_iortab[IOMEM8(0x1800)], cdrRead0, 1);
	map_item(&mem_iortab[IOMEM8(0x1801)], cdrRead1, 1);
	map_item(&mem_iortab[IOMEM8(0x1802)], cdrRead2, 1);
	map_item(&mem_iortab[IOMEM8(0x1803)], cdrRead3, 1);

	// write(u32 data)
	map_item(&mem_iowtab[IOMEM32(0x1040)], io_write_sio32, 1);
	map_item(&mem_iowtab[IOMEM32(0x1070)], io_write_ireg32, 1);
	map_item(&mem_iowtab[IOMEM32(0x1074)], io_write_imask32, 1);
	map_item(&mem_iowtab[IOMEM32(0x1088)], io_write_chcr0, 1);
	map_item(&mem_iowtab[IOMEM32(0x1098)], io_write_chcr1, 1);
	map_item(&mem_iowtab[IOMEM32(0x10a8)], io_write_chcr2, 1);
	map_item(&mem_iowtab[IOMEM32(0x10b8)], io_write_chcr3, 1);
	map_item(&mem_iowtab[IOMEM32(0x10c8)], io_write_chcr4, 1);
	map_item(&mem_iowtab[IOMEM32(0x10e8)], io_write_chcr6, 1);
	map_item(&mem_iowtab[IOMEM32(0x10f4)], io_write_dma_icr32, 1);
	map_item(&mem_iowtab[IOMEM32(0x1100)], io_rcnt_write_count0, 1);
	map_item(&mem_iowtab[IOMEM32(0x1104)], io_rcnt_write_mode0, 1);
	map_item(&mem_iowtab[IOMEM32(0x1108)], io_rcnt_write_target0, 1);
	map_item(&mem_iowtab[IOMEM32(0x1110)], io_rcnt_write_count1, 1);
	map_item(&mem_iowtab[IOMEM32(0x1114)], io_rcnt_write_mode1, 1);
	map_item(&mem_iowtab[IOMEM32(0x1118)], io_rcnt_write_target1, 1);
	map_item(&mem_iowtab[IOMEM32(0x1120)], io_rcnt_write_count2, 1);
	map_item(&mem_iowtab[IOMEM32(0x1124)], io_rcnt_write_mode2, 1);
	map_item(&mem_iowtab[IOMEM32(0x1128)], io_rcnt_write_target2, 1);
//	map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1);
//	map_item(&mem_iowtab[IOMEM32(0x1814)], GPU_writeStatus, 1);
	map_item(&mem_iowtab[IOMEM32(0x1820)], mdecWrite0, 1);
	map_item(&mem_iowtab[IOMEM32(0x1824)], mdecWrite1, 1);

	map_item(&mem_iowtab[IOMEM16(0x1040)], io_write_sio16, 1);
	map_item(&mem_iowtab[IOMEM16(0x1044)], sioWriteStat16, 1);
	map_item(&mem_iowtab[IOMEM16(0x1048)], sioWriteMode16, 1);
	map_item(&mem_iowtab[IOMEM16(0x104a)], sioWriteCtrl16, 1);
	map_item(&mem_iowtab[IOMEM16(0x104e)], sioWriteBaud16, 1);
	map_item(&mem_iowtab[IOMEM16(0x1070)], io_write_ireg16, 1);
	map_item(&mem_iowtab[IOMEM16(0x1074)], io_write_imask16, 1);
	map_item(&mem_iowtab[IOMEM16(0x1100)], io_rcnt_write_count0, 1);
	map_item(&mem_iowtab[IOMEM16(0x1104)], io_rcnt_write_mode0, 1);
	map_item(&mem_iowtab[IOMEM16(0x1108)], io_rcnt_write_target0, 1);
	map_item(&mem_iowtab[IOMEM16(0x1110)], io_rcnt_write_count1, 1);
	map_item(&mem_iowtab[IOMEM16(0x1114)], io_rcnt_write_mode1, 1);
	map_item(&mem_iowtab[IOMEM16(0x1118)], io_rcnt_write_target1, 1);
	map_item(&mem_iowtab[IOMEM16(0x1120)], io_rcnt_write_count2, 1);
	map_item(&mem_iowtab[IOMEM16(0x1124)], io_rcnt_write_mode2, 1);
	map_item(&mem_iowtab[IOMEM16(0x1128)], io_rcnt_write_target2, 1);

	map_item(&mem_iowtab[IOMEM8(0x1040)], sioWrite8, 1);
	map_item(&mem_iowtab[IOMEM8(0x1800)], cdrWrite0, 1);
	map_item(&mem_iowtab[IOMEM8(0x1801)], cdrWrite1, 1);
	map_item(&mem_iowtab[IOMEM8(0x1802)], cdrWrite2, 1);
	map_item(&mem_iowtab[IOMEM8(0x1803)], cdrWrite3, 1);

	for (i = 0x1c00; i < 0x1e00; i += 2) {
		map_item(&mem_iowtab[IOMEM16(i)], io_spu_write16, 1);
		map_item(&mem_iowtab[IOMEM32(i)], io_spu_write32, 1);
	}

	// misc
	map_item(&mem_writetab[0xfffe0130 >> 12], mem_ffwtab, 1);
	for (i = 0; i < 0x1000/4 + 0x1000/2 + 0x1000; i++)
		map_item(&mem_ffwtab[i], write_biu, 1);

	mem_rtab = mem_readtab;
	mem_wtab = mem_writetab;

	new_dyna_pcsx_mem_load_state();
}

void new_dyna_pcsx_mem_reset(void)
{
	int i;

	// plugins might change so update the pointers
	map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1);
	map_item(&mem_iortab[IOMEM32(0x1814)], GPU_readStatus, 1);

	for (i = 0x1c00; i < 0x1e00; i += 2)
		map_item(&mem_iortab[IOMEM16(i)], SPU_readRegister, 1);

	map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1);
	map_item(&mem_iowtab[IOMEM32(0x1814)], GPU_writeStatus, 1);
}
Commit	Line	Data
7e605697	1	/*
274c4243	2	* (C) Gražvydas "notaz" Ignotas, 2010-2011
7e605697	3	*
	4	* This work is licensed under the terms of GNU GPL version 2 or later.
	5	* See the COPYING file in the top-level directory.
	6	*/
	7
	8	#include <stdio.h>
c6c3b1b3	9	#include <sys/mman.h>
7e605697	10	#include "../psxhw.h"
	11	#include "../cdrom.h"
	12	#include "../mdec.h"
	13	#include "emu_if.h"
	14	#include "pcsxmem.h"
	15
	16	//#define memprintf printf
	17	#define memprintf(...)
	18
b1be1eee	19	static u32 *mem_readtab;
	20	static u32 *mem_writetab;
	21	static u32 mem_iortab[(1+2+4) * 0x1000 / 4];
	22	static u32 mem_iowtab[(1+2+4) * 0x1000 / 4];
	23	static u32 mem_ffwtab[(1+2+4) * 0x1000 / 4];
	24	//static u32 mem_unmrtab[(1+2+4) * 0x1000 / 4];
	25	static u32 mem_unmwtab[(1+2+4) * 0x1000 / 4];
	26
	27	static void map_item(u32 out, const void h, u32 flag)
	28	{
	29	u32 hv = (u32)h;
	30	if (hv & 1)
	31	fprintf(stderr, "%p has LSB set\n", h);
	32	*out = (hv >> 1) \| (flag << 31);
	33	}
	34
	35	// size must be power of 2, at least 4k
	36	#define map_l1_mem(tab, i, addr, size, base) \
	37	map_item(&tab[((addr)>>12) + i], (u8 *)(base) - (u32)(addr) - ((i << 12) & ~(size - 1)), 0)
	38
	39	#define IOMEM32(a) (((a) & 0xfff) / 4)
	40	#define IOMEM16(a) (0x1000/4 + (((a) & 0xfff) / 2))
	41	#define IOMEM8(a) (0x1000/4 + 0x1000/2 + ((a) & 0xfff))
	42
c6c3b1b3	43	static u8 unmapped_mem[0x1000];
7a481d40	44
63cb0298	45	u32 read_mem_dummy()
7e605697	46	{
63cb0298	47	return 0;
7e605697	48	}
7e605697	49
b96d3df7	50	static void write_mem_dummy(u32 data)
7e605697	51	{
b96d3df7	52	memprintf("unmapped w %08x, %08x @%08x %u\n", address, data, psxRegs.pc, psxRegs.cycle);
7e605697	53	}
7e605697	54
7e605697	55	/* IO handlers */
	56	static u32 io_read_sio16()
	57	{
	58	return sioRead8() \| (sioRead8() << 8);
	59	}
	60
	61	static u32 io_read_sio32()
	62	{
	63	return sioRead8() \| (sioRead8() << 8) \| (sioRead8() << 16) \| (sioRead8() << 24);
	64	}
	65
	66	static void io_write_sio16(u32 value)
	67	{
	68	sioWrite8((unsigned char)value);
	69	sioWrite8((unsigned char)(value>>8));
	70	}
	71
	72	static void io_write_sio32(u32 value)
	73	{
	74	sioWrite8((unsigned char)value);
b96d3df7	75	sioWrite8((unsigned char)(value >> 8));
	76	sioWrite8((unsigned char)(value >> 16));
	77	sioWrite8((unsigned char)(value >> 24));
7e605697	78	}
7e605697	79
b1be1eee	80	static void map_rcnt_rcount0(u32 mode)
	81	{
	82	if (mode & 0x01) { // gate
	83	map_item(&mem_iortab[IOMEM32(0x1100)], &psxH[0x1000], 0);
	84	map_item(&mem_iortab[IOMEM16(0x1100)], &psxH[0x1000], 0);
	85	}
	86	else if (mode & 0x100) { // pixel clock
	87	map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m1, 1);
	88	map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m1, 1);
	89	}
	90	else {
	91	map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m0, 1);
	92	map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m0, 1);
	93	}
	94	}
	95
	96	static void map_rcnt_rcount1(u32 mode)
	97	{
	98	if (mode & 0x01) { // gate
	99	map_item(&mem_iortab[IOMEM32(0x1110)], &psxH[0x1000], 0);
	100	map_item(&mem_iortab[IOMEM16(0x1110)], &psxH[0x1000], 0);
	101	}
	102	else if (mode & 0x100) { // hcnt
	103	map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m1, 1);
	104	map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m1, 1);
	105	}
	106	else {
	107	map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m0, 1);
	108	map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m0, 1);
	109	}
	110	}
	111
	112	static void map_rcnt_rcount2(u32 mode)
	113	{
	114	if (mode & 0x01) { // gate
	115	map_item(&mem_iortab[IOMEM32(0x1120)], &psxH[0x1000], 0);
	116	map_item(&mem_iortab[IOMEM16(0x1120)], &psxH[0x1000], 0);
	117	}
	118	else if (mode & 0x200) { // clk/8
	119	map_item(&mem_iortab[IOMEM32(0x1120)], rcnt2_read_count_m1, 1);
	120	map_item(&mem_iortab[IOMEM16(0x1120)], rcnt2_read_count_m1, 1);
	121	}
	122	else {
	123	map_item(&mem_iortab[IOMEM32(0x1120)], rcnt2_read_count_m0, 1);
	124	map_item(&mem_iortab[IOMEM16(0x1120)], rcnt2_read_count_m0, 1);
	125	}
	126	}
	127
7e605697	128	#define make_rcnt_funcs(i) \
	129	static u32 io_rcnt_read_count##i() { return psxRcntRcount(i); } \
	130	static u32 io_rcnt_read_mode##i() { return psxRcntRmode(i); } \
	131	static u32 io_rcnt_read_target##i() { return psxRcntRtarget(i); } \
	132	static void io_rcnt_write_count##i(u32 val) { psxRcntWcount(i, val & 0xffff); } \
b1be1eee	133	static void io_rcnt_write_mode##i(u32 val) { psxRcntWmode(i, val); map_rcnt_rcount##i(val); } \
7e605697	134	static void io_rcnt_write_target##i(u32 val) { psxRcntWtarget(i, val & 0xffff); }
	135
	136	make_rcnt_funcs(0)
	137	make_rcnt_funcs(1)
	138	make_rcnt_funcs(2)
	139
	140	static void io_write_ireg16(u32 value)
	141	{
	142	if (Config.Sio) psxHu16ref(0x1070) \|= 0x80;
	143	if (Config.SpuIrq) psxHu16ref(0x1070) \|= 0x200;
	144	psxHu16ref(0x1070) &= psxHu16(0x1074) & value;
	145	}
	146
	147	static void io_write_imask16(u32 value)
	148	{
	149	psxHu16ref(0x1074) = value;
	150	if (psxHu16ref(0x1070) & value)
d28b54b1	151	new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
7e605697	152	}
	153
	154	static void io_write_ireg32(u32 value)
	155	{
	156	if (Config.Sio) psxHu32ref(0x1070) \|= 0x80;
	157	if (Config.SpuIrq) psxHu32ref(0x1070) \|= 0x200;
	158	psxHu32ref(0x1070) &= psxHu32(0x1074) & value;
	159	}
	160
	161	static void io_write_imask32(u32 value)
	162	{
	163	psxHu32ref(0x1074) = value;
	164	if (psxHu32ref(0x1070) & value)
d28b54b1	165	new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
7e605697	166	}
	167
	168	static void io_write_dma_icr32(u32 value)
	169	{
1f77c863	170	u32 tmp = value & 0x00ff803f;
	171	tmp \|= (SWAPu32(HW_DMA_ICR) & ~value) & 0x7f000000;
	172	if ((tmp & HW_DMA_ICR_GLOBAL_ENABLE && tmp & 0x7f000000)
	173	\|\| tmp & HW_DMA_ICR_BUS_ERROR) {
	174	if (!(SWAPu32(HW_DMA_ICR) & HW_DMA_ICR_IRQ_SENT))
	175	psxHu32ref(0x1070) \|= SWAP32(8);
	176	tmp \|= HW_DMA_ICR_IRQ_SENT;
	177	}
	178	HW_DMA_ICR = SWAPu32(tmp);
7e605697	179	}
	180
	181	#define make_dma_func(n) \
	182	static void io_write_chcr##n(u32 value) \
	183	{ \
	184	HW_DMA##n##_CHCR = value; \
	185	if (value & 0x01000000 && HW_DMA_PCR & (8 << (n * 4))) { \
	186	psxDma##n(HW_DMA##n##_MADR, HW_DMA##n##_BCR, value); \
	187	} \
	188	}
	189
	190	make_dma_func(0)
	191	make_dma_func(1)
	192	make_dma_func(2)
	193	make_dma_func(3)
	194	make_dma_func(4)
	195	make_dma_func(6)
	196
b96d3df7	197	static void io_spu_write16(u32 value)
	198	{
	199	// meh
	200	SPU_writeRegister(address, value);
	201	}
	202
	203	static void io_spu_write32(u32 value)
	204	{
	205	SPUwriteRegister wfunc = SPU_writeRegister;
	206	u32 a = address;
	207
	208	wfunc(a, value & 0xffff);
	209	wfunc(a + 2, value >> 16);
	210	}
	211
b96d3df7	212	static void map_ram_write(void)
	213	{
	214	int i;
	215
	216	for (i = 0; i < (0x800000 >> 12); i++) {
	217	map_l1_mem(mem_writetab, i, 0x80000000, 0x200000, psxM);
	218	map_l1_mem(mem_writetab, i, 0x00000000, 0x200000, psxM);
	219	map_l1_mem(mem_writetab, i, 0xa0000000, 0x200000, psxM);
	220	}
	221	}
	222
	223	static void unmap_ram_write(void)
	224	{
	225	int i;
	226
	227	for (i = 0; i < (0x800000 >> 12); i++) {
	228	map_item(&mem_writetab[0x80000\|i], mem_unmwtab, 1);
	229	map_item(&mem_writetab[0x00000\|i], mem_unmwtab, 1);
	230	map_item(&mem_writetab[0xa0000\|i], mem_unmwtab, 1);
	231	}
	232	}
	233
	234	static void write_biu(u32 value)
	235	{
	236	memprintf("write_biu %08x, %08x @%08x %u\n", address, value, psxRegs.pc, psxRegs.cycle);
	237
	238	if (address != 0xfffe0130)
	239	return;
	240
	241	switch (value) {
	242	case 0x800: case 0x804:
	243	unmap_ram_write();
	244	break;
	245	case 0: case 0x1e988:
	246	map_ram_write();
	247	break;
	248	default:
	249	printf("write_biu: unexpected val: %08x\n", value);
	250	break;
	251	}
	252	}
	253
b1be1eee	254	void new_dyna_pcsx_mem_load_state(void)
	255	{
	256	map_rcnt_rcount0(rcnts[0].mode);
	257	map_rcnt_rcount1(rcnts[1].mode);
	258	map_rcnt_rcount2(rcnts[2].mode);
	259	}
	260
	261	int pcsxmem_is_handler_dynamic(u_int addr)
	262	{
	263	if ((addr & 0xfffff000) != 0x1f801000)
	264	return 0;
	265
	266	addr &= 0xffff;
	267	return addr == 0x1100 \|\| addr == 0x1110 \|\| addr == 0x1120;
	268	}
	269
7e605697	270	void new_dyna_pcsx_mem_init(void)
	271	{
	272	int i;
63cb0298	273
c6c3b1b3	274	// have to map these further to keep tcache close to .text
	275	mem_readtab = mmap((void )0x08000000, 0x200000 4, PROT_READ \| PROT_WRITE,
	276	MAP_FIXED \| MAP_PRIVATE \| MAP_ANONYMOUS, -1, 0);
	277	if (mem_readtab == MAP_FAILED) {
	278	fprintf(stderr, "failed to map mem tables\n");
	279	exit(1);
	280	}
	281	mem_writetab = mem_readtab + 0x100000;
	282
	283	// 1st level lookup:
	284	// 0: direct mem
	285	// 1: use 2nd lookup
	286	// 2nd level lookup:
	287	// 0: direct mem variable
	288	// 1: memhandler
	289
	290	// default/unmapped memhandlers
	291	for (i = 0; i < 0x100000; i++) {
	292	//map_item(&mem_readtab[i], mem_unmrtab, 1);
	293	map_l1_mem(mem_readtab, i, 0, 0x1000, unmapped_mem);
	294	map_item(&mem_writetab[i], mem_unmwtab, 1);
	295	}
	296
	297	// RAM and it's mirrors
	298	for (i = 0; i < (0x800000 >> 12); i++) {
	299	map_l1_mem(mem_readtab, i, 0x80000000, 0x200000, psxM);
c6c3b1b3	300	map_l1_mem(mem_readtab, i, 0x00000000, 0x200000, psxM);
c6c3b1b3	301	map_l1_mem(mem_readtab, i, 0xa0000000, 0x200000, psxM);
c6c3b1b3	302	}
b96d3df7	303	map_ram_write();
c6c3b1b3	304
	305	// BIOS and it's mirrors
	306	for (i = 0; i < (0x80000 >> 12); i++) {
	307	map_l1_mem(mem_readtab, i, 0x1fc00000, 0x80000, psxR);
	308	map_l1_mem(mem_readtab, i, 0xbfc00000, 0x80000, psxR);
	309	}
	310
	311	// scratchpad
	312	map_l1_mem(mem_readtab, 0, 0x1f800000, 0x1000, psxH);
	313	map_l1_mem(mem_writetab, 0, 0x1f800000, 0x1000, psxH);
	314
	315	// I/O
	316	map_item(&mem_readtab[0x1f801000 >> 12], mem_iortab, 1);
	317	map_item(&mem_writetab[0x1f801000 >> 12], mem_iowtab, 1);
7e605697	318
c6c3b1b3	319	// L2
c6c3b1b3	320	// unmapped tables
b96d3df7	321	for (i = 0; i < (1+2+4) * 0x1000 / 4; i++)
c6c3b1b3	322	map_item(&mem_unmwtab[i], write_mem_dummy, 1);
	323
	324	// fill IO tables
	325	for (i = 0; i < 0x1000/4; i++) {
	326	map_item(&mem_iortab[i], &psxH[0x1000], 0);
	327	map_item(&mem_iowtab[i], &psxH[0x1000], 0);
	328	}
	329	for (; i < 0x1000/4 + 0x1000/2; i++) {
	330	map_item(&mem_iortab[i], &psxH[0x1000], 0);
	331	map_item(&mem_iowtab[i], &psxH[0x1000], 0);
	332	}
	333	for (; i < 0x1000/4 + 0x1000/2 + 0x1000; i++) {
	334	map_item(&mem_iortab[i], &psxH[0x1000], 0);
	335	map_item(&mem_iowtab[i], &psxH[0x1000], 0);
	336	}
	337
	338	map_item(&mem_iortab[IOMEM32(0x1040)], io_read_sio32, 1);
	339	map_item(&mem_iortab[IOMEM32(0x1100)], io_rcnt_read_count0, 1);
	340	map_item(&mem_iortab[IOMEM32(0x1104)], io_rcnt_read_mode0, 1);
	341	map_item(&mem_iortab[IOMEM32(0x1108)], io_rcnt_read_target0, 1);
	342	map_item(&mem_iortab[IOMEM32(0x1110)], io_rcnt_read_count1, 1);
	343	map_item(&mem_iortab[IOMEM32(0x1114)], io_rcnt_read_mode1, 1);
	344	map_item(&mem_iortab[IOMEM32(0x1118)], io_rcnt_read_target1, 1);
	345	map_item(&mem_iortab[IOMEM32(0x1120)], io_rcnt_read_count2, 1);
	346	map_item(&mem_iortab[IOMEM32(0x1124)], io_rcnt_read_mode2, 1);
	347	map_item(&mem_iortab[IOMEM32(0x1128)], io_rcnt_read_target2, 1);
	348	// map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1);
	349	// map_item(&mem_iortab[IOMEM32(0x1814)], GPU_readStatus, 1);
	350	map_item(&mem_iortab[IOMEM32(0x1820)], mdecRead0, 1);
	351	map_item(&mem_iortab[IOMEM32(0x1824)], mdecRead1, 1);
	352
	353	map_item(&mem_iortab[IOMEM16(0x1040)], io_read_sio16, 1);
	354	map_item(&mem_iortab[IOMEM16(0x1044)], sioReadStat16, 1);
	355	map_item(&mem_iortab[IOMEM16(0x1048)], sioReadMode16, 1);
	356	map_item(&mem_iortab[IOMEM16(0x104a)], sioReadCtrl16, 1);
	357	map_item(&mem_iortab[IOMEM16(0x104e)], sioReadBaud16, 1);
	358	map_item(&mem_iortab[IOMEM16(0x1100)], io_rcnt_read_count0, 1);
	359	map_item(&mem_iortab[IOMEM16(0x1104)], io_rcnt_read_mode0, 1);
	360	map_item(&mem_iortab[IOMEM16(0x1108)], io_rcnt_read_target0, 1);
	361	map_item(&mem_iortab[IOMEM16(0x1110)], io_rcnt_read_count1, 1);
	362	map_item(&mem_iortab[IOMEM16(0x1114)], io_rcnt_read_mode1, 1);
	363	map_item(&mem_iortab[IOMEM16(0x1118)], io_rcnt_read_target1, 1);
	364	map_item(&mem_iortab[IOMEM16(0x1120)], io_rcnt_read_count2, 1);
	365	map_item(&mem_iortab[IOMEM16(0x1124)], io_rcnt_read_mode2, 1);
	366	map_item(&mem_iortab[IOMEM16(0x1128)], io_rcnt_read_target2, 1);
	367
	368	map_item(&mem_iortab[IOMEM8(0x1040)], sioRead8, 1);
	369	map_item(&mem_iortab[IOMEM8(0x1800)], cdrRead0, 1);
	370	map_item(&mem_iortab[IOMEM8(0x1801)], cdrRead1, 1);
	371	map_item(&mem_iortab[IOMEM8(0x1802)], cdrRead2, 1);
	372	map_item(&mem_iortab[IOMEM8(0x1803)], cdrRead3, 1);
	373
b96d3df7	374	// write(u32 data)
	375	map_item(&mem_iowtab[IOMEM32(0x1040)], io_write_sio32, 1);
	376	map_item(&mem_iowtab[IOMEM32(0x1070)], io_write_ireg32, 1);
	377	map_item(&mem_iowtab[IOMEM32(0x1074)], io_write_imask32, 1);
	378	map_item(&mem_iowtab[IOMEM32(0x1088)], io_write_chcr0, 1);
	379	map_item(&mem_iowtab[IOMEM32(0x1098)], io_write_chcr1, 1);
	380	map_item(&mem_iowtab[IOMEM32(0x10a8)], io_write_chcr2, 1);
	381	map_item(&mem_iowtab[IOMEM32(0x10b8)], io_write_chcr3, 1);
	382	map_item(&mem_iowtab[IOMEM32(0x10c8)], io_write_chcr4, 1);
	383	map_item(&mem_iowtab[IOMEM32(0x10e8)], io_write_chcr6, 1);
	384	map_item(&mem_iowtab[IOMEM32(0x10f4)], io_write_dma_icr32, 1);
	385	map_item(&mem_iowtab[IOMEM32(0x1100)], io_rcnt_write_count0, 1);
	386	map_item(&mem_iowtab[IOMEM32(0x1104)], io_rcnt_write_mode0, 1);
	387	map_item(&mem_iowtab[IOMEM32(0x1108)], io_rcnt_write_target0, 1);
	388	map_item(&mem_iowtab[IOMEM32(0x1110)], io_rcnt_write_count1, 1);
	389	map_item(&mem_iowtab[IOMEM32(0x1114)], io_rcnt_write_mode1, 1);
	390	map_item(&mem_iowtab[IOMEM32(0x1118)], io_rcnt_write_target1, 1);
	391	map_item(&mem_iowtab[IOMEM32(0x1120)], io_rcnt_write_count2, 1);
	392	map_item(&mem_iowtab[IOMEM32(0x1124)], io_rcnt_write_mode2, 1);
	393	map_item(&mem_iowtab[IOMEM32(0x1128)], io_rcnt_write_target2, 1);
	394	// map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1);
	395	// map_item(&mem_iowtab[IOMEM32(0x1814)], GPU_writeStatus, 1);
	396	map_item(&mem_iowtab[IOMEM32(0x1820)], mdecWrite0, 1);
	397	map_item(&mem_iowtab[IOMEM32(0x1824)], mdecWrite1, 1);
	398
	399	map_item(&mem_iowtab[IOMEM16(0x1040)], io_write_sio16, 1);
	400	map_item(&mem_iowtab[IOMEM16(0x1044)], sioWriteStat16, 1);
	401	map_item(&mem_iowtab[IOMEM16(0x1048)], sioWriteMode16, 1);
	402	map_item(&mem_iowtab[IOMEM16(0x104a)], sioWriteCtrl16, 1);
	403	map_item(&mem_iowtab[IOMEM16(0x104e)], sioWriteBaud16, 1);
	404	map_item(&mem_iowtab[IOMEM16(0x1070)], io_write_ireg16, 1);
	405	map_item(&mem_iowtab[IOMEM16(0x1074)], io_write_imask16, 1);
	406	map_item(&mem_iowtab[IOMEM16(0x1100)], io_rcnt_write_count0, 1);
	407	map_item(&mem_iowtab[IOMEM16(0x1104)], io_rcnt_write_mode0, 1);
	408	map_item(&mem_iowtab[IOMEM16(0x1108)], io_rcnt_write_target0, 1);
	409	map_item(&mem_iowtab[IOMEM16(0x1110)], io_rcnt_write_count1, 1);
	410	map_item(&mem_iowtab[IOMEM16(0x1114)], io_rcnt_write_mode1, 1);
	411	map_item(&mem_iowtab[IOMEM16(0x1118)], io_rcnt_write_target1, 1);
	412	map_item(&mem_iowtab[IOMEM16(0x1120)], io_rcnt_write_count2, 1);
	413	map_item(&mem_iowtab[IOMEM16(0x1124)], io_rcnt_write_mode2, 1);
	414	map_item(&mem_iowtab[IOMEM16(0x1128)], io_rcnt_write_target2, 1);
	415
	416	map_item(&mem_iowtab[IOMEM8(0x1040)], sioWrite8, 1);
	417	map_item(&mem_iowtab[IOMEM8(0x1800)], cdrWrite0, 1);
	418	map_item(&mem_iowtab[IOMEM8(0x1801)], cdrWrite1, 1);
	419	map_item(&mem_iowtab[IOMEM8(0x1802)], cdrWrite2, 1);
	420	map_item(&mem_iowtab[IOMEM8(0x1803)], cdrWrite3, 1);
	421
	422	for (i = 0x1c00; i < 0x1e00; i += 2) {
	423	map_item(&mem_iowtab[IOMEM16(i)], io_spu_write16, 1);
	424	map_item(&mem_iowtab[IOMEM32(i)], io_spu_write32, 1);
	425	}
	426
	427	// misc
	428	map_item(&mem_writetab[0xfffe0130 >> 12], mem_ffwtab, 1);
	429	for (i = 0; i < 0x1000/4 + 0x1000/2 + 0x1000; i++)
	430	map_item(&mem_ffwtab[i], write_biu, 1);
	431
c6c3b1b3	432	mem_rtab = mem_readtab;
c6c3b1b3	433	mem_wtab = mem_writetab;
b1be1eee	434
b1be1eee	435	new_dyna_pcsx_mem_load_state();
7e605697	436	}
	437
	438	void new_dyna_pcsx_mem_reset(void)
	439	{
c6c3b1b3	440	int i;
c6c3b1b3	441
7e605697	442	// plugins might change so update the pointers
c6c3b1b3	443	map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1);
	444	map_item(&mem_iortab[IOMEM32(0x1814)], GPU_readStatus, 1);
	445
	446	for (i = 0x1c00; i < 0x1e00; i += 2)
	447	map_item(&mem_iortab[IOMEM16(i)], SPU_readRegister, 1);
	448
b96d3df7	449	map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1);
b96d3df7	450	map_item(&mem_iowtab[IOMEM32(0x1814)], GPU_writeStatus, 1);
7e605697	451	}