[pcsx_rearmed.git] / libpcsxcore / new_dynarec / pcsxmem.c

/*
 * (C) Gražvydas "notaz" Ignotas, 2010-2011
 *
 * This work is licensed under the terms of GNU GPL version 2 or later.
 * See the COPYING file in the top-level directory.
 */

#include <stdio.h>
#include "../psxhw.h"
#include "../cdrom.h"
#include "../mdec.h"
#include "emu_if.h"
#include "pcsxmem.h"

//#define memprintf printf
#define memprintf(...)

int pcsx_ram_is_ro;

static void read_mem8()
{
	memprintf("ari64_read_mem8  %08x @%08x %u\n", address, psxRegs.pc, psxRegs.cycle);
	readmem_word = psxMemRead8(address) & 0xff;
}

static void read_mem16()
{
	memprintf("ari64_read_mem16 %08x @%08x %u\n", address, psxRegs.pc, psxRegs.cycle);
	readmem_word = psxMemRead16(address) & 0xffff;
}

static void read_mem32()
{
	memprintf("ari64_read_mem32 %08x @%08x %u\n", address, psxRegs.pc, psxRegs.cycle);
	readmem_word = psxMemRead32(address);
}

static void write_mem8()
{
	memprintf("ari64_write_mem8  %08x,       %02x @%08x %u\n", address, byte, psxRegs.pc, psxRegs.cycle);
	psxMemWrite8(address, byte);
}

static void write_mem16()
{
	memprintf("ari64_write_mem16 %08x,     %04x @%08x %u\n", address, hword, psxRegs.pc, psxRegs.cycle);
	psxMemWrite16(address, hword);
}

static void write_mem32()
{
	memprintf("ari64_write_mem32 %08x, %08x @%08x %u\n", address, word, psxRegs.pc, psxRegs.cycle);
	psxMemWrite32(address, word);
}

static void read_mem_dummy()
{
	readmem_word = 0;
}

static void write_mem_dummy()
{
}

extern void ari_read_ram8();
extern void ari_read_ram16();
extern void ari_read_ram32();
extern void ari_read_ram_mirror8();
extern void ari_read_ram_mirror16();
extern void ari_read_ram_mirror32();
extern void ari_write_ram8();
extern void ari_write_ram16();
extern void ari_write_ram32();
extern void ari_write_ram_mirror8();
extern void ari_write_ram_mirror16();
extern void ari_write_ram_mirror32();
extern void ari_write_ram_mirror_ro32();
extern void ari_read_bios8();
extern void ari_read_bios16();
extern void ari_read_bios32();
extern void ari_read_io8();
extern void ari_read_io16();
extern void ari_read_io32();
extern void ari_write_io8();
extern void ari_write_io16();
extern void ari_write_io32();

void (*readmem[0x10000])();
void (*readmemb[0x10000])();
void (*readmemh[0x10000])();
void (*writemem[0x10000])();
void (*writememb[0x10000])();
void (*writememh[0x10000])();

static void write_biu()
{
	memprintf("write_biu %08x, %08x @%08x %u\n", address, word, psxRegs.pc, psxRegs.cycle);

	if (address != 0xfffe0130)
		return;

	switch (word) {
	case 0x800: case 0x804:
		pcsx_ram_is_ro = 1;
		break;
	case 0: case 0x1e988:
		pcsx_ram_is_ro = 0;
		break;
	default:
		memprintf("write_biu: unexpected val: %08x\n", word);
		break;
	}
}

/* IO handlers */
static u32 io_read_sio16()
{
	return sioRead8() | (sioRead8() << 8);
}

static u32 io_read_sio32()
{
	return sioRead8() | (sioRead8() << 8) | (sioRead8() << 16) | (sioRead8() << 24);
}

static void io_write_sio16(u32 value)
{
	sioWrite8((unsigned char)value);
	sioWrite8((unsigned char)(value>>8));
}

static void io_write_sio32(u32 value)
{
	sioWrite8((unsigned char)value);
	sioWrite8((unsigned char)((value&0xff) >>  8));
	sioWrite8((unsigned char)((value&0xff) >> 16));
	sioWrite8((unsigned char)((value&0xff) >> 24));
}

#define make_rcnt_funcs(i) \
static u32 io_rcnt_read_count##i()  { return psxRcntRcount(i); } \
static u32 io_rcnt_read_mode##i()   { return psxRcntRmode(i); } \
static u32 io_rcnt_read_target##i() { return psxRcntRtarget(i); } \
static void io_rcnt_write_count##i(u32 val)  { psxRcntWcount(i, val & 0xffff); } \
static void io_rcnt_write_mode##i(u32 val)   { psxRcntWmode(i, val); } \
static void io_rcnt_write_target##i(u32 val) { psxRcntWtarget(i, val & 0xffff); }

make_rcnt_funcs(0)
make_rcnt_funcs(1)
make_rcnt_funcs(2)

static void io_write_ireg16(u32 value)
{
	if (Config.Sio) psxHu16ref(0x1070) |= 0x80;
	if (Config.SpuIrq) psxHu16ref(0x1070) |= 0x200;
	psxHu16ref(0x1070) &= psxHu16(0x1074) & value;
}

static void io_write_imask16(u32 value)
{
	psxHu16ref(0x1074) = value;
	if (psxHu16ref(0x1070) & value)
		new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
}

static void io_write_ireg32(u32 value)
{
	if (Config.Sio) psxHu32ref(0x1070) |= 0x80;
	if (Config.SpuIrq) psxHu32ref(0x1070) |= 0x200;
	psxHu32ref(0x1070) &= psxHu32(0x1074) & value;
}

static void io_write_imask32(u32 value)
{
	psxHu32ref(0x1074) = value;
	if (psxHu32ref(0x1070) & value)
		new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
}

static void io_write_dma_icr32(u32 value)
{
	u32 tmp = ~value & HW_DMA_ICR;
	HW_DMA_ICR = ((tmp ^ value) & 0xffffff) ^ tmp;
}

#define make_dma_func(n) \
static void io_write_chcr##n(u32 value) \
{ \
	HW_DMA##n##_CHCR = value; \
	if (value & 0x01000000 && HW_DMA_PCR & (8 << (n * 4))) { \
		psxDma##n(HW_DMA##n##_MADR, HW_DMA##n##_BCR, value); \
	} \
}

make_dma_func(0)
make_dma_func(1)
make_dma_func(2)
make_dma_func(3)
make_dma_func(4)
make_dma_func(6)

/* IO tables for 1000-1880 */
#define IOADR8(a)  ((a) & 0xfff)
#define IOADR16(a) (((a) & 0xfff) >> 1)
#define IOADR32(a) (((a) & 0xfff) >> 2)

static const void *io_read8 [0x880] = {
	[IOADR8(0x1040)] = sioRead8,
	[IOADR8(0x1800)] = cdrRead0,
	[IOADR8(0x1801)] = cdrRead1,
	[IOADR8(0x1802)] = cdrRead2,
	[IOADR8(0x1803)] = cdrRead3,
};
static const void *io_read16[0x880/2] = {
	[IOADR16(0x1040)] = io_read_sio16,
	[IOADR16(0x1044)] = sioReadStat16,
	[IOADR16(0x1048)] = sioReadMode16,
	[IOADR16(0x104a)] = sioReadCtrl16,
	[IOADR16(0x104e)] = sioReadBaud16,
	[IOADR16(0x1100)] = io_rcnt_read_count0,
	[IOADR16(0x1104)] = io_rcnt_read_mode0,
	[IOADR16(0x1108)] = io_rcnt_read_target0,
	[IOADR16(0x1110)] = io_rcnt_read_count1,
	[IOADR16(0x1114)] = io_rcnt_read_mode1,
	[IOADR16(0x1118)] = io_rcnt_read_target1,
	[IOADR16(0x1120)] = io_rcnt_read_count2,
	[IOADR16(0x1124)] = io_rcnt_read_mode2,
	[IOADR16(0x1128)] = io_rcnt_read_target2,
};
static const void *io_read32[0x880/4] = {
	[IOADR32(0x1040)] = io_read_sio32,
	[IOADR32(0x1100)] = io_rcnt_read_count0,
	[IOADR32(0x1104)] = io_rcnt_read_mode0,
	[IOADR32(0x1108)] = io_rcnt_read_target0,
	[IOADR32(0x1110)] = io_rcnt_read_count1,
	[IOADR32(0x1114)] = io_rcnt_read_mode1,
	[IOADR32(0x1118)] = io_rcnt_read_target1,
	[IOADR32(0x1120)] = io_rcnt_read_count2,
	[IOADR32(0x1124)] = io_rcnt_read_mode2,
	[IOADR32(0x1128)] = io_rcnt_read_target2,
//	[IOADR32(0x1810)] = GPU_readData,
//	[IOADR32(0x1814)] = GPU_readStatus,
	[IOADR32(0x1820)] = mdecRead0,
	[IOADR32(0x1824)] = mdecRead1,
};
// write(u32 val)
static const void *io_write8 [0x880] = {
	[IOADR8(0x1040)] = sioWrite8,
	[IOADR8(0x1800)] = cdrWrite0,
	[IOADR8(0x1801)] = cdrWrite1,
	[IOADR8(0x1802)] = cdrWrite2,
	[IOADR8(0x1803)] = cdrWrite3,
};
static const void *io_write16[0x880/2] = {
	[IOADR16(0x1040)] = io_write_sio16,
	[IOADR16(0x1044)] = sioWriteStat16,
	[IOADR16(0x1048)] = sioWriteMode16,
	[IOADR16(0x104a)] = sioWriteCtrl16,
	[IOADR16(0x104e)] = sioWriteBaud16,
	[IOADR16(0x1070)] = io_write_ireg16,
	[IOADR16(0x1074)] = io_write_imask16,
	[IOADR16(0x1100)] = io_rcnt_write_count0,
	[IOADR16(0x1104)] = io_rcnt_write_mode0,
	[IOADR16(0x1108)] = io_rcnt_write_target0,
	[IOADR16(0x1110)] = io_rcnt_write_count1,
	[IOADR16(0x1114)] = io_rcnt_write_mode1,
	[IOADR16(0x1118)] = io_rcnt_write_target1,
	[IOADR16(0x1120)] = io_rcnt_write_count2,
	[IOADR16(0x1124)] = io_rcnt_write_mode2,
	[IOADR16(0x1128)] = io_rcnt_write_target2,
};
static const void *io_write32[0x880/4] = {
	[IOADR32(0x1040)] = io_write_sio32,
	[IOADR32(0x1070)] = io_write_ireg32,
	[IOADR32(0x1074)] = io_write_imask32,
	[IOADR32(0x1088)] = io_write_chcr0,
	[IOADR32(0x1098)] = io_write_chcr1,
	[IOADR32(0x10a8)] = io_write_chcr2,
	[IOADR32(0x10b8)] = io_write_chcr3,
	[IOADR32(0x10c8)] = io_write_chcr4,
	[IOADR32(0x10e8)] = io_write_chcr6,
	[IOADR32(0x10f4)] = io_write_dma_icr32,
	[IOADR32(0x1100)] = io_rcnt_write_count0,
	[IOADR32(0x1104)] = io_rcnt_write_mode0,
	[IOADR32(0x1108)] = io_rcnt_write_target0,
	[IOADR32(0x1110)] = io_rcnt_write_count1,
	[IOADR32(0x1114)] = io_rcnt_write_mode1,
	[IOADR32(0x1118)] = io_rcnt_write_target1,
	[IOADR32(0x1120)] = io_rcnt_write_count2,
	[IOADR32(0x1124)] = io_rcnt_write_mode2,
	[IOADR32(0x1128)] = io_rcnt_write_target2,
//	[IOADR32(0x1810)] = GPU_writeData,
//	[IOADR32(0x1814)] = GPU_writeStatus,
	[IOADR32(0x1820)] = mdecWrite0,
	[IOADR32(0x1824)] = mdecWrite1,
};

// this has to be in .bss to link into dynarec_local
struct {
	void *tab_read8;
	void *tab_read16;
	void *tab_read32;
	void *tab_write8;
	void *tab_write16;
	void *tab_write32;
	void *spu_readf;
	void *spu_writef;
} nd_pcsx_io;

void new_dyna_pcsx_mem_init(void)
{
	int i;

	// default/unmapped handlers
	for (i = 0; i < 0x10000; i++) {
		readmemb[i] = read_mem8;
		readmemh[i] = read_mem16;
		readmem[i] = read_mem32;
		writememb[i] = write_mem8;
		writememh[i] = write_mem16;
		writemem[i] = write_mem32;
#if 1
		readmemb[i] = readmemh[i] = readmem[i] = read_mem_dummy;
		writememb[i] = writememh[i] = writemem[i] = write_mem_dummy;
#endif
	}

#if 1
	// RAM mirrors
	for (i = 0; i < 0x80; i++) {
		readmemb[i] = readmemb[0x8000|i] = readmemb[0xa000|i] = ari_read_ram_mirror8;
		readmemh[i] = readmemh[0x8000|i] = readmemh[0xa000|i] = ari_read_ram_mirror16;
		readmem[i]  = readmem [0x8000|i] = readmem [0xa000|i] = ari_read_ram_mirror32;
		writememb[i] = writememb[0x8000|i] = writememb[0xa000|i] = ari_write_ram_mirror8;
		writememh[i] = writememh[0x8000|i] = writememh[0xa000|i] = ari_write_ram_mirror16;
		writemem[i]  = writemem [0x8000|i] = writemem [0xa000|i] = ari_write_ram_mirror32;
	}

	// stupid BIOS RAM check
	writemem[0] = ari_write_ram_mirror_ro32;
	pcsx_ram_is_ro = 0;

	// RAM direct
	for (i = 0x8000; i < 0x8020; i++) {
		readmemb[i] = ari_read_ram8;
		readmemh[i] = ari_read_ram16;
		readmem[i] = ari_read_ram32;
	}

	// BIOS and it's mirrors
	for (i = 0x1fc0; i < 0x1fc8; i++) {
		readmemb[i] = readmemb[0x8000|i] = readmemb[0xa000|i] = ari_read_bios8;
		readmemh[i] = readmemh[0x8000|i] = readmemh[0xa000|i] = ari_read_bios16;
		readmem[i]  = readmem[0x8000|i]  = readmem[0xa000|i]  = ari_read_bios32;
	}

	// I/O
	readmemb[0x1f80] = ari_read_io8;
	readmemh[0x1f80] = ari_read_io16;
	readmem[0x1f80]  = ari_read_io32;
	writememb[0x1f80] = ari_write_io8;
	writememh[0x1f80] = ari_write_io16;
	writemem[0x1f80]  = ari_write_io32;

	writemem[0xfffe] = write_biu;
#endif

	// fill IO tables
	nd_pcsx_io.tab_read8 = io_read8;
	nd_pcsx_io.tab_read16 = io_read16;
	nd_pcsx_io.tab_read32 = io_read32;
	nd_pcsx_io.tab_write8 = io_write8;
	nd_pcsx_io.tab_write16 = io_write16;
	nd_pcsx_io.tab_write32 = io_write32;
}

void new_dyna_pcsx_mem_reset(void)
{
	// plugins might change so update the pointers
	nd_pcsx_io.spu_readf = SPU_readRegister;
	nd_pcsx_io.spu_writef = SPU_writeRegister;

	io_read32[IOADR32(0x1810)] = GPU_readData;
	io_read32[IOADR32(0x1814)] = GPU_readStatus;
	io_write32[IOADR32(0x1810)] = GPU_writeData;
	io_write32[IOADR32(0x1814)] = GPU_writeStatus;
}
Commit	Line	Data
7e605697	1	/*
274c4243	2	* (C) Gražvydas "notaz" Ignotas, 2010-2011
7e605697	3	*
	4	* This work is licensed under the terms of GNU GPL version 2 or later.
	5	* See the COPYING file in the top-level directory.
	6	*/
	7
	8	#include <stdio.h>
	9	#include "../psxhw.h"
	10	#include "../cdrom.h"
	11	#include "../mdec.h"
	12	#include "emu_if.h"
	13	#include "pcsxmem.h"
	14
	15	//#define memprintf printf
	16	#define memprintf(...)
	17
274c4243	18	int pcsx_ram_is_ro;
7a481d40	19
7e605697	20	static void read_mem8()
	21	{
	22	memprintf("ari64_read_mem8 %08x @%08x %u\n", address, psxRegs.pc, psxRegs.cycle);
	23	readmem_word = psxMemRead8(address) & 0xff;
	24	}
	25
	26	static void read_mem16()
	27	{
	28	memprintf("ari64_read_mem16 %08x @%08x %u\n", address, psxRegs.pc, psxRegs.cycle);
	29	readmem_word = psxMemRead16(address) & 0xffff;
	30	}
	31
	32	static void read_mem32()
	33	{
	34	memprintf("ari64_read_mem32 %08x @%08x %u\n", address, psxRegs.pc, psxRegs.cycle);
	35	readmem_word = psxMemRead32(address);
	36	}
	37
	38	static void write_mem8()
	39	{
	40	memprintf("ari64_write_mem8 %08x, %02x @%08x %u\n", address, byte, psxRegs.pc, psxRegs.cycle);
	41	psxMemWrite8(address, byte);
	42	}
	43
	44	static void write_mem16()
	45	{
	46	memprintf("ari64_write_mem16 %08x, %04x @%08x %u\n", address, hword, psxRegs.pc, psxRegs.cycle);
	47	psxMemWrite16(address, hword);
	48	}
	49
	50	static void write_mem32()
	51	{
	52	memprintf("ari64_write_mem32 %08x, %08x @%08x %u\n", address, word, psxRegs.pc, psxRegs.cycle);
	53	psxMemWrite32(address, word);
	54	}
	55
	56	static void read_mem_dummy()
	57	{
	58	readmem_word = 0;
	59	}
	60
	61	static void write_mem_dummy()
	62	{
	63	}
	64
	65	extern void ari_read_ram8();
	66	extern void ari_read_ram16();
	67	extern void ari_read_ram32();
	68	extern void ari_read_ram_mirror8();
	69	extern void ari_read_ram_mirror16();
	70	extern void ari_read_ram_mirror32();
	71	extern void ari_write_ram8();
	72	extern void ari_write_ram16();
	73	extern void ari_write_ram32();
	74	extern void ari_write_ram_mirror8();
	75	extern void ari_write_ram_mirror16();
	76	extern void ari_write_ram_mirror32();
274c4243	77	extern void ari_write_ram_mirror_ro32();
a06c1d6e	78	extern void ari_read_bios8();
	79	extern void ari_read_bios16();
	80	extern void ari_read_bios32();
7e605697	81	extern void ari_read_io8();
	82	extern void ari_read_io16();
	83	extern void ari_read_io32();
	84	extern void ari_write_io8();
	85	extern void ari_write_io16();
	86	extern void ari_write_io32();
	87
	88	void (*readmem[0x10000])();
	89	void (*readmemb[0x10000])();
	90	void (*readmemh[0x10000])();
	91	void (*writemem[0x10000])();
	92	void (*writememb[0x10000])();
	93	void (*writememh[0x10000])();
	94
7a481d40	95	static void write_biu()
	96	{
	97	memprintf("write_biu %08x, %08x @%08x %u\n", address, word, psxRegs.pc, psxRegs.cycle);
	98
	99	if (address != 0xfffe0130)
	100	return;
	101
	102	switch (word) {
	103	case 0x800: case 0x804:
274c4243	104	pcsx_ram_is_ro = 1;
7a481d40	105	break;
7a481d40	106	case 0: case 0x1e988:
274c4243	107	pcsx_ram_is_ro = 0;
7a481d40	108	break;
	109	default:
	110	memprintf("write_biu: unexpected val: %08x\n", word);
	111	break;
	112	}
	113	}
	114
7e605697	115	/* IO handlers */
	116	static u32 io_read_sio16()
	117	{
	118	return sioRead8() \| (sioRead8() << 8);
	119	}
	120
	121	static u32 io_read_sio32()
	122	{
	123	return sioRead8() \| (sioRead8() << 8) \| (sioRead8() << 16) \| (sioRead8() << 24);
	124	}
	125
	126	static void io_write_sio16(u32 value)
	127	{
	128	sioWrite8((unsigned char)value);
	129	sioWrite8((unsigned char)(value>>8));
	130	}
	131
	132	static void io_write_sio32(u32 value)
	133	{
	134	sioWrite8((unsigned char)value);
	135	sioWrite8((unsigned char)((value&0xff) >> 8));
	136	sioWrite8((unsigned char)((value&0xff) >> 16));
	137	sioWrite8((unsigned char)((value&0xff) >> 24));
	138	}
	139
	140	#define make_rcnt_funcs(i) \
	141	static u32 io_rcnt_read_count##i() { return psxRcntRcount(i); } \
	142	static u32 io_rcnt_read_mode##i() { return psxRcntRmode(i); } \
	143	static u32 io_rcnt_read_target##i() { return psxRcntRtarget(i); } \
	144	static void io_rcnt_write_count##i(u32 val) { psxRcntWcount(i, val & 0xffff); } \
	145	static void io_rcnt_write_mode##i(u32 val) { psxRcntWmode(i, val); } \
	146	static void io_rcnt_write_target##i(u32 val) { psxRcntWtarget(i, val & 0xffff); }
	147
	148	make_rcnt_funcs(0)
	149	make_rcnt_funcs(1)
	150	make_rcnt_funcs(2)
	151
	152	static void io_write_ireg16(u32 value)
	153	{
	154	if (Config.Sio) psxHu16ref(0x1070) \|= 0x80;
	155	if (Config.SpuIrq) psxHu16ref(0x1070) \|= 0x200;
	156	psxHu16ref(0x1070) &= psxHu16(0x1074) & value;
	157	}
	158
	159	static void io_write_imask16(u32 value)
	160	{
	161	psxHu16ref(0x1074) = value;
	162	if (psxHu16ref(0x1070) & value)
d28b54b1	163	new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
7e605697	164	}
	165
	166	static void io_write_ireg32(u32 value)
	167	{
	168	if (Config.Sio) psxHu32ref(0x1070) \|= 0x80;
	169	if (Config.SpuIrq) psxHu32ref(0x1070) \|= 0x200;
	170	psxHu32ref(0x1070) &= psxHu32(0x1074) & value;
	171	}
	172
	173	static void io_write_imask32(u32 value)
	174	{
	175	psxHu32ref(0x1074) = value;
	176	if (psxHu32ref(0x1070) & value)
d28b54b1	177	new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
7e605697	178	}
	179
	180	static void io_write_dma_icr32(u32 value)
	181	{
	182	u32 tmp = ~value & HW_DMA_ICR;
	183	HW_DMA_ICR = ((tmp ^ value) & 0xffffff) ^ tmp;
	184	}
	185
	186	#define make_dma_func(n) \
	187	static void io_write_chcr##n(u32 value) \
	188	{ \
	189	HW_DMA##n##_CHCR = value; \
	190	if (value & 0x01000000 && HW_DMA_PCR & (8 << (n * 4))) { \
	191	psxDma##n(HW_DMA##n##_MADR, HW_DMA##n##_BCR, value); \
	192	} \
	193	}
	194
	195	make_dma_func(0)
	196	make_dma_func(1)
	197	make_dma_func(2)
	198	make_dma_func(3)
	199	make_dma_func(4)
	200	make_dma_func(6)
	201
	202	/* IO tables for 1000-1880 */
	203	#define IOADR8(a) ((a) & 0xfff)
	204	#define IOADR16(a) (((a) & 0xfff) >> 1)
	205	#define IOADR32(a) (((a) & 0xfff) >> 2)
	206
	207	static const void *io_read8 [0x880] = {
	208	[IOADR8(0x1040)] = sioRead8,
	209	[IOADR8(0x1800)] = cdrRead0,
	210	[IOADR8(0x1801)] = cdrRead1,
	211	[IOADR8(0x1802)] = cdrRead2,
	212	[IOADR8(0x1803)] = cdrRead3,
	213	};
	214	static const void *io_read16[0x880/2] = {
	215	[IOADR16(0x1040)] = io_read_sio16,
	216	[IOADR16(0x1044)] = sioReadStat16,
	217	[IOADR16(0x1048)] = sioReadMode16,
	218	[IOADR16(0x104a)] = sioReadCtrl16,
	219	[IOADR16(0x104e)] = sioReadBaud16,
	220	[IOADR16(0x1100)] = io_rcnt_read_count0,
	221	[IOADR16(0x1104)] = io_rcnt_read_mode0,
	222	[IOADR16(0x1108)] = io_rcnt_read_target0,
	223	[IOADR16(0x1110)] = io_rcnt_read_count1,
	224	[IOADR16(0x1114)] = io_rcnt_read_mode1,
	225	[IOADR16(0x1118)] = io_rcnt_read_target1,
	226	[IOADR16(0x1120)] = io_rcnt_read_count2,
	227	[IOADR16(0x1124)] = io_rcnt_read_mode2,
	228	[IOADR16(0x1128)] = io_rcnt_read_target2,
	229	};
	230	static const void *io_read32[0x880/4] = {
	231	[IOADR32(0x1040)] = io_read_sio32,
	232	[IOADR32(0x1100)] = io_rcnt_read_count0,
	233	[IOADR32(0x1104)] = io_rcnt_read_mode0,
	234	[IOADR32(0x1108)] = io_rcnt_read_target0,
	235	[IOADR32(0x1110)] = io_rcnt_read_count1,
	236	[IOADR32(0x1114)] = io_rcnt_read_mode1,
	237	[IOADR32(0x1118)] = io_rcnt_read_target1,
	238	[IOADR32(0x1120)] = io_rcnt_read_count2,
	239	[IOADR32(0x1124)] = io_rcnt_read_mode2,
	240	[IOADR32(0x1128)] = io_rcnt_read_target2,
	241	// [IOADR32(0x1810)] = GPU_readData,
242	// [IOADR32(0x1814)] = GPU_readStatus,
243	[IOADR32(0x1820)] = mdecRead0,
244	[IOADR32(0x1824)] = mdecRead1,
245	};
246	// write(u32 val)
247	static const void *io_write8 [0x880] = {
248	[IOADR8(0x1040)] = sioWrite8,
249	[IOADR8(0x1800)] = cdrWrite0,
250	[IOADR8(0x1801)] = cdrWrite1,
251	[IOADR8(0x1802)] = cdrWrite2,
252	[IOADR8(0x1803)] = cdrWrite3,
253	};
254	static const void *io_write16[0x880/2] = {
255	[IOADR16(0x1040)] = io_write_sio16,
256	[IOADR16(0x1044)] = sioWriteStat16,
257	[IOADR16(0x1048)] = sioWriteMode16,
258	[IOADR16(0x104a)] = sioWriteCtrl16,
259	[IOADR16(0x104e)] = sioWriteBaud16,
260	[IOADR16(0x1070)] = io_write_ireg16,
261	[IOADR16(0x1074)] = io_write_imask16,
262	[IOADR16(0x1100)] = io_rcnt_write_count0,
263	[IOADR16(0x1104)] = io_rcnt_write_mode0,
264	[IOADR16(0x1108)] = io_rcnt_write_target0,
265	[IOADR16(0x1110)] = io_rcnt_write_count1,
266	[IOADR16(0x1114)] = io_rcnt_write_mode1,
267	[IOADR16(0x1118)] = io_rcnt_write_target1,
268	[IOADR16(0x1120)] = io_rcnt_write_count2,
269	[IOADR16(0x1124)] = io_rcnt_write_mode2,
270	[IOADR16(0x1128)] = io_rcnt_write_target2,
271	};
272	static const void *io_write32[0x880/4] = {
273	[IOADR32(0x1040)] = io_write_sio32,
274	[IOADR32(0x1070)] = io_write_ireg32,
275	[IOADR32(0x1074)] = io_write_imask32,
276	[IOADR32(0x1088)] = io_write_chcr0,
277	[IOADR32(0x1098)] = io_write_chcr1,
278	[IOADR32(0x10a8)] = io_write_chcr2,
279	[IOADR32(0x10b8)] = io_write_chcr3,
280	[IOADR32(0x10c8)] = io_write_chcr4,
281	[IOADR32(0x10e8)] = io_write_chcr6,
282	[IOADR32(0x10f4)] = io_write_dma_icr32,
283	[IOADR32(0x1100)] = io_rcnt_write_count0,
284	[IOADR32(0x1104)] = io_rcnt_write_mode0,
285	[IOADR32(0x1108)] = io_rcnt_write_target0,
286	[IOADR32(0x1110)] = io_rcnt_write_count1,
287	[IOADR32(0x1114)] = io_rcnt_write_mode1,
288	[IOADR32(0x1118)] = io_rcnt_write_target1,
289	[IOADR32(0x1120)] = io_rcnt_write_count2,
290	[IOADR32(0x1124)] = io_rcnt_write_mode2,
291	[IOADR32(0x1128)] = io_rcnt_write_target2,
292	// [IOADR32(0x1810)] = GPU_writeData,
293	// [IOADR32(0x1814)] = GPU_writeStatus,
294	[IOADR32(0x1820)] = mdecWrite0,
295	[IOADR32(0x1824)] = mdecWrite1,
296	};
297
298	// this has to be in .bss to link into dynarec_local
299	struct {
300	void *tab_read8;
301	void *tab_read16;
302	void *tab_read32;
303	void *tab_write8;
304	void *tab_write16;
305	void *tab_write32;
306	void *spu_readf;
307	void *spu_writef;
308	} nd_pcsx_io;
309
310	void new_dyna_pcsx_mem_init(void)
311	{
312	int i;
313
314	// default/unmapped handlers
315	for (i = 0; i < 0x10000; i++) {
316	readmemb[i] = read_mem8;
317	readmemh[i] = read_mem16;
318	readmem[i] = read_mem32;
319	writememb[i] = write_mem8;
320	writememh[i] = write_mem16;
321	writemem[i] = write_mem32;
322	#if 1
323	readmemb[i] = readmemh[i] = readmem[i] = read_mem_dummy;
a06c1d6e	324	writememb[i] = writememh[i] = writemem[i] = write_mem_dummy;
7e605697	325	#endif
	326	}
	327
	328	#if 1
	329	// RAM mirrors
	330	for (i = 0; i < 0x80; i++) {
	331	readmemb[i] = readmemb[0x8000\|i] = readmemb[0xa000\|i] = ari_read_ram_mirror8;
	332	readmemh[i] = readmemh[0x8000\|i] = readmemh[0xa000\|i] = ari_read_ram_mirror16;
	333	readmem[i] = readmem [0x8000\|i] = readmem [0xa000\|i] = ari_read_ram_mirror32;
	334	writememb[i] = writememb[0x8000\|i] = writememb[0xa000\|i] = ari_write_ram_mirror8;
	335	writememh[i] = writememh[0x8000\|i] = writememh[0xa000\|i] = ari_write_ram_mirror16;
	336	writemem[i] = writemem [0x8000\|i] = writemem [0xa000\|i] = ari_write_ram_mirror32;
	337	}
	338
7a481d40	339	// stupid BIOS RAM check
274c4243	340	writemem[0] = ari_write_ram_mirror_ro32;
274c4243	341	pcsx_ram_is_ro = 0;
7a481d40	342
7e605697	343	// RAM direct
	344	for (i = 0x8000; i < 0x8020; i++) {
	345	readmemb[i] = ari_read_ram8;
	346	readmemh[i] = ari_read_ram16;
	347	readmem[i] = ari_read_ram32;
7e605697	348	}
7e605697	349
a06c1d6e	350	// BIOS and it's mirrors
	351	for (i = 0x1fc0; i < 0x1fc8; i++) {
	352	readmemb[i] = readmemb[0x8000\|i] = readmemb[0xa000\|i] = ari_read_bios8;
	353	readmemh[i] = readmemh[0x8000\|i] = readmemh[0xa000\|i] = ari_read_bios16;
	354	readmem[i] = readmem[0x8000\|i] = readmem[0xa000\|i] = ari_read_bios32;
	355	}
	356
7e605697	357	// I/O
	358	readmemb[0x1f80] = ari_read_io8;
	359	readmemh[0x1f80] = ari_read_io16;
	360	readmem[0x1f80] = ari_read_io32;
	361	writememb[0x1f80] = ari_write_io8;
	362	writememh[0x1f80] = ari_write_io16;
	363	writemem[0x1f80] = ari_write_io32;
	364
7a481d40	365	writemem[0xfffe] = write_biu;
7e605697	366	#endif
	367
	368	// fill IO tables
	369	nd_pcsx_io.tab_read8 = io_read8;
	370	nd_pcsx_io.tab_read16 = io_read16;
	371	nd_pcsx_io.tab_read32 = io_read32;
	372	nd_pcsx_io.tab_write8 = io_write8;
	373	nd_pcsx_io.tab_write16 = io_write16;
	374	nd_pcsx_io.tab_write32 = io_write32;
	375	}
	376
	377	void new_dyna_pcsx_mem_reset(void)
	378	{
	379	// plugins might change so update the pointers
	380	nd_pcsx_io.spu_readf = SPU_readRegister;
	381	nd_pcsx_io.spu_writef = SPU_writeRegister;
	382
	383	io_read32[IOADR32(0x1810)] = GPU_readData;
	384	io_read32[IOADR32(0x1814)] = GPU_readStatus;
	385	io_write32[IOADR32(0x1810)] = GPU_writeData;
	386	io_write32[IOADR32(0x1814)] = GPU_writeStatus;
	387	}
	388