[pcsx_rearmed.git] / libpcsxcore / new_dynarec / pcsxmem.c

/*
 * (C) Gražvydas "notaz" Ignotas, 2010-2011
 *
 * This work is licensed under the terms of GNU GPL version 2 or later.
 * See the COPYING file in the top-level directory.
 */

#include <stdio.h>
#include <sys/mman.h>
#include "../psxhw.h"
#include "../cdrom.h"
#include "../mdec.h"
#include "../gpu.h"
#include "emu_if.h"
#include "pcsxmem.h"

//#define memprintf printf
#define memprintf(...)

static u32 *mem_readtab;
static u32 *mem_writetab;
static u32 mem_iortab[(1+2+4) * 0x1000 / 4];
static u32 mem_iowtab[(1+2+4) * 0x1000 / 4];
static u32 mem_ffwtab[(1+2+4) * 0x1000 / 4];
//static u32 mem_unmrtab[(1+2+4) * 0x1000 / 4];
static u32 mem_unmwtab[(1+2+4) * 0x1000 / 4];

static void map_item(u32 *out, const void *h, u32 flag)
{
	u32 hv = (u32)h;
	if (hv & 1)
		fprintf(stderr, "%p has LSB set\n", h);
	*out = (hv >> 1) | (flag << 31);
}

// size must be power of 2, at least 4k
#define map_l1_mem(tab, i, addr, size, base) \
	map_item(&tab[((addr)>>12) + i], (u8 *)(base) - (u32)(addr) - ((i << 12) & ~(size - 1)), 0)

#define IOMEM32(a) (((a) & 0xfff) / 4)
#define IOMEM16(a) (0x1000/4 + (((a) & 0xfff) / 2))
#define IOMEM8(a)  (0x1000/4 + 0x1000/2 + ((a) & 0xfff))

u8 zero_mem[0x1000];

u32 read_mem_dummy()
{
	return 0;
}

static void write_mem_dummy(u32 data)
{
	memprintf("unmapped w %08x, %08x @%08x %u\n", address, data, psxRegs.pc, psxRegs.cycle);
}

/* IO handlers */
static u32 io_read_sio16()
{
	return sioRead8() | (sioRead8() << 8);
}

static u32 io_read_sio32()
{
	return sioRead8() | (sioRead8() << 8) | (sioRead8() << 16) | (sioRead8() << 24);
}

static void io_write_sio16(u32 value)
{
	sioWrite8((unsigned char)value);
	sioWrite8((unsigned char)(value>>8));
}

static void io_write_sio32(u32 value)
{
	sioWrite8((unsigned char)value);
	sioWrite8((unsigned char)(value >>  8));
	sioWrite8((unsigned char)(value >> 16));
	sioWrite8((unsigned char)(value >> 24));
}

#ifndef DRC_DBG

static void map_rcnt_rcount0(u32 mode)
{
	if (mode & 0x100) { // pixel clock
		map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m1, 1);
		map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m1, 1);
	}
	else {
		map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m0, 1);
		map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m0, 1);
	}
}

static void map_rcnt_rcount1(u32 mode)
{
	if (mode & 0x100) { // hcnt
		map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m1, 1);
		map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m1, 1);
	}
	else {
		map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m0, 1);
		map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m0, 1);
	}
}

static void map_rcnt_rcount2(u32 mode)
{
	if (mode & 0x01) { // gate
		map_item(&mem_iortab[IOMEM32(0x1120)], &psxH[0x1000], 0);
		map_item(&mem_iortab[IOMEM16(0x1120)], &psxH[0x1000], 0);
	}
	else if (mode & 0x200) { // clk/8
		map_item(&mem_iortab[IOMEM32(0x1120)], rcnt2_read_count_m1, 1);
		map_item(&mem_iortab[IOMEM16(0x1120)], rcnt2_read_count_m1, 1);
	}
	else {
		map_item(&mem_iortab[IOMEM32(0x1120)], rcnt2_read_count_m0, 1);
		map_item(&mem_iortab[IOMEM16(0x1120)], rcnt2_read_count_m0, 1);
	}
}

#else
#define map_rcnt_rcount0(mode)
#define map_rcnt_rcount1(mode)
#define map_rcnt_rcount2(mode)
#endif

#define make_rcnt_funcs(i) \
static u32 io_rcnt_read_count##i()  { return psxRcntRcount(i); } \
static u32 io_rcnt_read_mode##i()   { return psxRcntRmode(i); } \
static u32 io_rcnt_read_target##i() { return psxRcntRtarget(i); } \
static void io_rcnt_write_count##i(u32 val)  { psxRcntWcount(i, val & 0xffff); } \
static void io_rcnt_write_mode##i(u32 val)   { psxRcntWmode(i, val); map_rcnt_rcount##i(val); } \
static void io_rcnt_write_target##i(u32 val) { psxRcntWtarget(i, val & 0xffff); }

make_rcnt_funcs(0)
make_rcnt_funcs(1)
make_rcnt_funcs(2)

static void io_write_ireg16(u32 value)
{
	if (Config.Sio) psxHu16ref(0x1070) |= 0x80;
	if (Config.SpuIrq) psxHu16ref(0x1070) |= 0x200;
	psxHu16ref(0x1070) &= psxHu16(0x1074) & value;
}

static void io_write_imask16(u32 value)
{
	psxHu16ref(0x1074) = value;
	if (psxHu16ref(0x1070) & value)
		new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
}

static void io_write_ireg32(u32 value)
{
	if (Config.Sio) psxHu32ref(0x1070) |= 0x80;
	if (Config.SpuIrq) psxHu32ref(0x1070) |= 0x200;
	psxHu32ref(0x1070) &= psxHu32(0x1074) & value;
}

static void io_write_imask32(u32 value)
{
	psxHu32ref(0x1074) = value;
	if (psxHu32ref(0x1070) & value)
		new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
}

static void io_write_dma_icr32(u32 value)
{
	u32 tmp = value & 0x00ff803f;
	tmp |= (SWAPu32(HW_DMA_ICR) & ~value) & 0x7f000000;
	if ((tmp & HW_DMA_ICR_GLOBAL_ENABLE && tmp & 0x7f000000)
	    || tmp & HW_DMA_ICR_BUS_ERROR) {
		if (!(SWAPu32(HW_DMA_ICR) & HW_DMA_ICR_IRQ_SENT))
			psxHu32ref(0x1070) |= SWAP32(8);
		tmp |= HW_DMA_ICR_IRQ_SENT;
	}
	HW_DMA_ICR = SWAPu32(tmp);
}

#define make_dma_func(n) \
static void io_write_chcr##n(u32 value) \
{ \
	HW_DMA##n##_CHCR = value; \
	if (value & 0x01000000 && HW_DMA_PCR & (8 << (n * 4))) { \
		psxDma##n(HW_DMA##n##_MADR, HW_DMA##n##_BCR, value); \
	} \
}

make_dma_func(0)
make_dma_func(1)
make_dma_func(2)
make_dma_func(3)
make_dma_func(4)
make_dma_func(6)

static void io_spu_write16(u32 value)
{
	// meh
	SPU_writeRegister(address, value);
}

static void io_spu_write32(u32 value)
{
	SPUwriteRegister wfunc = SPU_writeRegister;
	u32 a = address;

	wfunc(a, value & 0xffff);
	wfunc(a + 2, value >> 16);
}

static u32 io_gpu_read_status(void)
{
	// meh2, syncing for img bit, might want to avoid it..
	gpuSyncPluginSR();
	return HW_GPU_STATUS;
}

static void io_gpu_write_status(u32 value)
{
	GPU_writeStatus(value);
	gpuSyncPluginSR();
}

static void map_ram_write(void)
{
	int i;

	for (i = 0; i < (0x800000 >> 12); i++) {
		map_l1_mem(mem_writetab, i, 0x80000000, 0x200000, psxM);
		map_l1_mem(mem_writetab, i, 0x00000000, 0x200000, psxM);
		map_l1_mem(mem_writetab, i, 0xa0000000, 0x200000, psxM);
	}
}

static void unmap_ram_write(void)
{
	int i;

	for (i = 0; i < (0x800000 >> 12); i++) {
		map_item(&mem_writetab[0x80000|i], mem_unmwtab, 1);
		map_item(&mem_writetab[0x00000|i], mem_unmwtab, 1);
		map_item(&mem_writetab[0xa0000|i], mem_unmwtab, 1);
	}
}

static void write_biu(u32 value)
{
	memprintf("write_biu %08x, %08x @%08x %u\n", address, value, psxRegs.pc, psxRegs.cycle);

	if (address != 0xfffe0130)
		return;

	switch (value) {
	case 0x800: case 0x804:
		unmap_ram_write();
		break;
	case 0: case 0x1e988:
		map_ram_write();
		break;
	default:
		printf("write_biu: unexpected val: %08x\n", value);
		break;
	}
}

void new_dyna_pcsx_mem_load_state(void)
{
	map_rcnt_rcount0(rcnts[0].mode);
	map_rcnt_rcount1(rcnts[1].mode);
	map_rcnt_rcount2(rcnts[2].mode);
}

int pcsxmem_is_handler_dynamic(u_int addr)
{
	if ((addr & 0xfffff000) != 0x1f801000)
		return 0;

	addr &= 0xffff;
	return addr == 0x1100 || addr == 0x1110 || addr == 0x1120;
}

void new_dyna_pcsx_mem_init(void)
{
	int i;

	// have to map these further to keep tcache close to .text
	mem_readtab = mmap((void *)0x08000000, 0x200000 * 4, PROT_READ | PROT_WRITE,
		MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
	if (mem_readtab == MAP_FAILED) {
		fprintf(stderr, "failed to map mem tables\n");
		exit(1);
	}
	mem_writetab = mem_readtab + 0x100000;

	// 1st level lookup:
	//   0: direct mem
	//   1: use 2nd lookup
	// 2nd level lookup:
	//   0: direct mem variable
	//   1: memhandler

	// default/unmapped memhandlers
	for (i = 0; i < 0x100000; i++) {
		//map_item(&mem_readtab[i], mem_unmrtab, 1);
		map_l1_mem(mem_readtab, i, 0, 0x1000, zero_mem);
		map_item(&mem_writetab[i], mem_unmwtab, 1);
	}

	// RAM and it's mirrors
	for (i = 0; i < (0x800000 >> 12); i++) {
		map_l1_mem(mem_readtab,  i, 0x80000000, 0x200000, psxM);
		map_l1_mem(mem_readtab,  i, 0x00000000, 0x200000, psxM);
		map_l1_mem(mem_readtab,  i, 0xa0000000, 0x200000, psxM);
	}
	map_ram_write();

	// BIOS and it's mirrors
	for (i = 0; i < (0x80000 >> 12); i++) {
		map_l1_mem(mem_readtab, i, 0x1fc00000, 0x80000, psxR);
		map_l1_mem(mem_readtab, i, 0xbfc00000, 0x80000, psxR);
	}

	// scratchpad
	map_l1_mem(mem_readtab, 0, 0x1f800000, 0x1000, psxH);
	map_l1_mem(mem_writetab, 0, 0x1f800000, 0x1000, psxH);

	// I/O
	map_item(&mem_readtab[0x1f801000 >> 12], mem_iortab, 1);
	map_item(&mem_writetab[0x1f801000 >> 12], mem_iowtab, 1);

	// L2
	// unmapped tables
	for (i = 0; i < (1+2+4) * 0x1000 / 4; i++)
		map_item(&mem_unmwtab[i], write_mem_dummy, 1);

	// fill IO tables
	for (i = 0; i < 0x1000/4; i++) {
		map_item(&mem_iortab[i], &psxH[0x1000], 0);
		map_item(&mem_iowtab[i], &psxH[0x1000], 0);
	}
	for (; i < 0x1000/4 + 0x1000/2; i++) {
		map_item(&mem_iortab[i], &psxH[0x1000], 0);
		map_item(&mem_iowtab[i], &psxH[0x1000], 0);
	}
	for (; i < 0x1000/4 + 0x1000/2 + 0x1000; i++) {
		map_item(&mem_iortab[i], &psxH[0x1000], 0);
		map_item(&mem_iowtab[i], &psxH[0x1000], 0);
	}

	map_item(&mem_iortab[IOMEM32(0x1040)], io_read_sio32, 1);
	map_item(&mem_iortab[IOMEM32(0x1100)], io_rcnt_read_count0, 1);
	map_item(&mem_iortab[IOMEM32(0x1104)], io_rcnt_read_mode0, 1);
	map_item(&mem_iortab[IOMEM32(0x1108)], io_rcnt_read_target0, 1);
	map_item(&mem_iortab[IOMEM32(0x1110)], io_rcnt_read_count1, 1);
	map_item(&mem_iortab[IOMEM32(0x1114)], io_rcnt_read_mode1, 1);
	map_item(&mem_iortab[IOMEM32(0x1118)], io_rcnt_read_target1, 1);
	map_item(&mem_iortab[IOMEM32(0x1120)], io_rcnt_read_count2, 1);
	map_item(&mem_iortab[IOMEM32(0x1124)], io_rcnt_read_mode2, 1);
	map_item(&mem_iortab[IOMEM32(0x1128)], io_rcnt_read_target2, 1);
//	map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1);
	map_item(&mem_iortab[IOMEM32(0x1814)], io_gpu_read_status, 1);
	map_item(&mem_iortab[IOMEM32(0x1820)], mdecRead0, 1);
	map_item(&mem_iortab[IOMEM32(0x1824)], mdecRead1, 1);

	map_item(&mem_iortab[IOMEM16(0x1040)], io_read_sio16, 1);
	map_item(&mem_iortab[IOMEM16(0x1044)], sioReadStat16, 1);
	map_item(&mem_iortab[IOMEM16(0x1048)], sioReadMode16, 1);
	map_item(&mem_iortab[IOMEM16(0x104a)], sioReadCtrl16, 1);
	map_item(&mem_iortab[IOMEM16(0x104e)], sioReadBaud16, 1);
	map_item(&mem_iortab[IOMEM16(0x1100)], io_rcnt_read_count0, 1);
	map_item(&mem_iortab[IOMEM16(0x1104)], io_rcnt_read_mode0, 1);
	map_item(&mem_iortab[IOMEM16(0x1108)], io_rcnt_read_target0, 1);
	map_item(&mem_iortab[IOMEM16(0x1110)], io_rcnt_read_count1, 1);
	map_item(&mem_iortab[IOMEM16(0x1114)], io_rcnt_read_mode1, 1);
	map_item(&mem_iortab[IOMEM16(0x1118)], io_rcnt_read_target1, 1);
	map_item(&mem_iortab[IOMEM16(0x1120)], io_rcnt_read_count2, 1);
	map_item(&mem_iortab[IOMEM16(0x1124)], io_rcnt_read_mode2, 1);
	map_item(&mem_iortab[IOMEM16(0x1128)], io_rcnt_read_target2, 1);

	map_item(&mem_iortab[IOMEM8(0x1040)], sioRead8, 1);
	map_item(&mem_iortab[IOMEM8(0x1800)], cdrRead0, 1);
	map_item(&mem_iortab[IOMEM8(0x1801)], cdrRead1, 1);
	map_item(&mem_iortab[IOMEM8(0x1802)], cdrRead2, 1);
	map_item(&mem_iortab[IOMEM8(0x1803)], cdrRead3, 1);

	// write(u32 data)
	map_item(&mem_iowtab[IOMEM32(0x1040)], io_write_sio32, 1);
	map_item(&mem_iowtab[IOMEM32(0x1070)], io_write_ireg32, 1);
	map_item(&mem_iowtab[IOMEM32(0x1074)], io_write_imask32, 1);
	map_item(&mem_iowtab[IOMEM32(0x1088)], io_write_chcr0, 1);
	map_item(&mem_iowtab[IOMEM32(0x1098)], io_write_chcr1, 1);
	map_item(&mem_iowtab[IOMEM32(0x10a8)], io_write_chcr2, 1);
	map_item(&mem_iowtab[IOMEM32(0x10b8)], io_write_chcr3, 1);
	map_item(&mem_iowtab[IOMEM32(0x10c8)], io_write_chcr4, 1);
	map_item(&mem_iowtab[IOMEM32(0x10e8)], io_write_chcr6, 1);
	map_item(&mem_iowtab[IOMEM32(0x10f4)], io_write_dma_icr32, 1);
	map_item(&mem_iowtab[IOMEM32(0x1100)], io_rcnt_write_count0, 1);
	map_item(&mem_iowtab[IOMEM32(0x1104)], io_rcnt_write_mode0, 1);
	map_item(&mem_iowtab[IOMEM32(0x1108)], io_rcnt_write_target0, 1);
	map_item(&mem_iowtab[IOMEM32(0x1110)], io_rcnt_write_count1, 1);
	map_item(&mem_iowtab[IOMEM32(0x1114)], io_rcnt_write_mode1, 1);
	map_item(&mem_iowtab[IOMEM32(0x1118)], io_rcnt_write_target1, 1);
	map_item(&mem_iowtab[IOMEM32(0x1120)], io_rcnt_write_count2, 1);
	map_item(&mem_iowtab[IOMEM32(0x1124)], io_rcnt_write_mode2, 1);
	map_item(&mem_iowtab[IOMEM32(0x1128)], io_rcnt_write_target2, 1);
//	map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1);
	map_item(&mem_iowtab[IOMEM32(0x1814)], io_gpu_write_status, 1);
	map_item(&mem_iowtab[IOMEM32(0x1820)], mdecWrite0, 1);
	map_item(&mem_iowtab[IOMEM32(0x1824)], mdecWrite1, 1);

	map_item(&mem_iowtab[IOMEM16(0x1040)], io_write_sio16, 1);
	map_item(&mem_iowtab[IOMEM16(0x1044)], sioWriteStat16, 1);
	map_item(&mem_iowtab[IOMEM16(0x1048)], sioWriteMode16, 1);
	map_item(&mem_iowtab[IOMEM16(0x104a)], sioWriteCtrl16, 1);
	map_item(&mem_iowtab[IOMEM16(0x104e)], sioWriteBaud16, 1);
	map_item(&mem_iowtab[IOMEM16(0x1070)], io_write_ireg16, 1);
	map_item(&mem_iowtab[IOMEM16(0x1074)], io_write_imask16, 1);
	map_item(&mem_iowtab[IOMEM16(0x1100)], io_rcnt_write_count0, 1);
	map_item(&mem_iowtab[IOMEM16(0x1104)], io_rcnt_write_mode0, 1);
	map_item(&mem_iowtab[IOMEM16(0x1108)], io_rcnt_write_target0, 1);
	map_item(&mem_iowtab[IOMEM16(0x1110)], io_rcnt_write_count1, 1);
	map_item(&mem_iowtab[IOMEM16(0x1114)], io_rcnt_write_mode1, 1);
	map_item(&mem_iowtab[IOMEM16(0x1118)], io_rcnt_write_target1, 1);
	map_item(&mem_iowtab[IOMEM16(0x1120)], io_rcnt_write_count2, 1);
	map_item(&mem_iowtab[IOMEM16(0x1124)], io_rcnt_write_mode2, 1);
	map_item(&mem_iowtab[IOMEM16(0x1128)], io_rcnt_write_target2, 1);

	map_item(&mem_iowtab[IOMEM8(0x1040)], sioWrite8, 1);
	map_item(&mem_iowtab[IOMEM8(0x1800)], cdrWrite0, 1);
	map_item(&mem_iowtab[IOMEM8(0x1801)], cdrWrite1, 1);
	map_item(&mem_iowtab[IOMEM8(0x1802)], cdrWrite2, 1);
	map_item(&mem_iowtab[IOMEM8(0x1803)], cdrWrite3, 1);

	for (i = 0x1c00; i < 0x1e00; i += 2) {
		map_item(&mem_iowtab[IOMEM16(i)], io_spu_write16, 1);
		map_item(&mem_iowtab[IOMEM32(i)], io_spu_write32, 1);
	}

	// misc
	map_item(&mem_writetab[0xfffe0130 >> 12], mem_ffwtab, 1);
	for (i = 0; i < 0x1000/4 + 0x1000/2 + 0x1000; i++)
		map_item(&mem_ffwtab[i], write_biu, 1);

	mem_rtab = mem_readtab;
	mem_wtab = mem_writetab;

	new_dyna_pcsx_mem_load_state();
}

void new_dyna_pcsx_mem_reset(void)
{
	int i;

	// plugins might change so update the pointers
	map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1);

	for (i = 0x1c00; i < 0x1e00; i += 2)
		map_item(&mem_iortab[IOMEM16(i)], SPU_readRegister, 1);

	map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1);
}
Commit	Line	Data
7e605697	1	/*
274c4243	2	* (C) Gražvydas "notaz" Ignotas, 2010-2011
7e605697	3	*
	4	* This work is licensed under the terms of GNU GPL version 2 or later.
	5	* See the COPYING file in the top-level directory.
	6	*/
	7
	8	#include <stdio.h>
c6c3b1b3	9	#include <sys/mman.h>
7e605697	10	#include "../psxhw.h"
	11	#include "../cdrom.h"
	12	#include "../mdec.h"
ddbaf678	13	#include "../gpu.h"
7e605697	14	#include "emu_if.h"
	15	#include "pcsxmem.h"
	16
	17	//#define memprintf printf
	18	#define memprintf(...)
	19
b1be1eee	20	static u32 *mem_readtab;
	21	static u32 *mem_writetab;
	22	static u32 mem_iortab[(1+2+4) * 0x1000 / 4];
	23	static u32 mem_iowtab[(1+2+4) * 0x1000 / 4];
	24	static u32 mem_ffwtab[(1+2+4) * 0x1000 / 4];
	25	//static u32 mem_unmrtab[(1+2+4) * 0x1000 / 4];
	26	static u32 mem_unmwtab[(1+2+4) * 0x1000 / 4];
	27
	28	static void map_item(u32 out, const void h, u32 flag)
	29	{
	30	u32 hv = (u32)h;
	31	if (hv & 1)
	32	fprintf(stderr, "%p has LSB set\n", h);
	33	*out = (hv >> 1) \| (flag << 31);
	34	}
	35
	36	// size must be power of 2, at least 4k
	37	#define map_l1_mem(tab, i, addr, size, base) \
	38	map_item(&tab[((addr)>>12) + i], (u8 *)(base) - (u32)(addr) - ((i << 12) & ~(size - 1)), 0)
	39
	40	#define IOMEM32(a) (((a) & 0xfff) / 4)
	41	#define IOMEM16(a) (0x1000/4 + (((a) & 0xfff) / 2))
	42	#define IOMEM8(a) (0x1000/4 + 0x1000/2 + ((a) & 0xfff))
	43
054175e9	44	u8 zero_mem[0x1000];
7a481d40	45
63cb0298	46	u32 read_mem_dummy()
7e605697	47	{
63cb0298	48	return 0;
7e605697	49	}
7e605697	50
b96d3df7	51	static void write_mem_dummy(u32 data)
7e605697	52	{
b96d3df7	53	memprintf("unmapped w %08x, %08x @%08x %u\n", address, data, psxRegs.pc, psxRegs.cycle);
7e605697	54	}
7e605697	55
7e605697	56	/* IO handlers */
	57	static u32 io_read_sio16()
	58	{
	59	return sioRead8() \| (sioRead8() << 8);
	60	}
	61
	62	static u32 io_read_sio32()
	63	{
	64	return sioRead8() \| (sioRead8() << 8) \| (sioRead8() << 16) \| (sioRead8() << 24);
	65	}
	66
	67	static void io_write_sio16(u32 value)
	68	{
	69	sioWrite8((unsigned char)value);
	70	sioWrite8((unsigned char)(value>>8));
	71	}
	72
	73	static void io_write_sio32(u32 value)
	74	{
	75	sioWrite8((unsigned char)value);
b96d3df7	76	sioWrite8((unsigned char)(value >> 8));
	77	sioWrite8((unsigned char)(value >> 16));
	78	sioWrite8((unsigned char)(value >> 24));
7e605697	79	}
7e605697	80
19776aef	81	#ifndef DRC_DBG
19776aef	82
b1be1eee	83	static void map_rcnt_rcount0(u32 mode)
b1be1eee	84	{
59fb0bb4	85	if (mode & 0x100) { // pixel clock
b1be1eee	86	map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m1, 1);
	87	map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m1, 1);
	88	}
	89	else {
	90	map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m0, 1);
	91	map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m0, 1);
	92	}
	93	}
	94
	95	static void map_rcnt_rcount1(u32 mode)
	96	{
59fb0bb4	97	if (mode & 0x100) { // hcnt
b1be1eee	98	map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m1, 1);
	99	map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m1, 1);
	100	}
	101	else {
	102	map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m0, 1);
	103	map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m0, 1);
	104	}
	105	}
	106
	107	static void map_rcnt_rcount2(u32 mode)
	108	{
	109	if (mode & 0x01) { // gate
	110	map_item(&mem_iortab[IOMEM32(0x1120)], &psxH[0x1000], 0);
	111	map_item(&mem_iortab[IOMEM16(0x1120)], &psxH[0x1000], 0);
	112	}
	113	else if (mode & 0x200) { // clk/8
	114	map_item(&mem_iortab[IOMEM32(0x1120)], rcnt2_read_count_m1, 1);
	115	map_item(&mem_iortab[IOMEM16(0x1120)], rcnt2_read_count_m1, 1);
	116	}
	117	else {
	118	map_item(&mem_iortab[IOMEM32(0x1120)], rcnt2_read_count_m0, 1);
	119	map_item(&mem_iortab[IOMEM16(0x1120)], rcnt2_read_count_m0, 1);
	120	}
	121	}
	122
19776aef	123	#else
	124	#define map_rcnt_rcount0(mode)
	125	#define map_rcnt_rcount1(mode)
	126	#define map_rcnt_rcount2(mode)
	127	#endif
	128
7e605697	129	#define make_rcnt_funcs(i) \
	130	static u32 io_rcnt_read_count##i() { return psxRcntRcount(i); } \
	131	static u32 io_rcnt_read_mode##i() { return psxRcntRmode(i); } \
	132	static u32 io_rcnt_read_target##i() { return psxRcntRtarget(i); } \
	133	static void io_rcnt_write_count##i(u32 val) { psxRcntWcount(i, val & 0xffff); } \
b1be1eee	134	static void io_rcnt_write_mode##i(u32 val) { psxRcntWmode(i, val); map_rcnt_rcount##i(val); } \
7e605697	135	static void io_rcnt_write_target##i(u32 val) { psxRcntWtarget(i, val & 0xffff); }
	136
	137	make_rcnt_funcs(0)
	138	make_rcnt_funcs(1)
	139	make_rcnt_funcs(2)
	140
	141	static void io_write_ireg16(u32 value)
	142	{
	143	if (Config.Sio) psxHu16ref(0x1070) \|= 0x80;
	144	if (Config.SpuIrq) psxHu16ref(0x1070) \|= 0x200;
	145	psxHu16ref(0x1070) &= psxHu16(0x1074) & value;
	146	}
	147
	148	static void io_write_imask16(u32 value)
	149	{
	150	psxHu16ref(0x1074) = value;
	151	if (psxHu16ref(0x1070) & value)
d28b54b1	152	new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
7e605697	153	}
	154
	155	static void io_write_ireg32(u32 value)
	156	{
	157	if (Config.Sio) psxHu32ref(0x1070) \|= 0x80;
	158	if (Config.SpuIrq) psxHu32ref(0x1070) \|= 0x200;
	159	psxHu32ref(0x1070) &= psxHu32(0x1074) & value;
	160	}
	161
	162	static void io_write_imask32(u32 value)
	163	{
	164	psxHu32ref(0x1074) = value;
	165	if (psxHu32ref(0x1070) & value)
d28b54b1	166	new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
7e605697	167	}
	168
	169	static void io_write_dma_icr32(u32 value)
	170	{
1f77c863	171	u32 tmp = value & 0x00ff803f;
	172	tmp \|= (SWAPu32(HW_DMA_ICR) & ~value) & 0x7f000000;
	173	if ((tmp & HW_DMA_ICR_GLOBAL_ENABLE && tmp & 0x7f000000)
	174	\|\| tmp & HW_DMA_ICR_BUS_ERROR) {
	175	if (!(SWAPu32(HW_DMA_ICR) & HW_DMA_ICR_IRQ_SENT))
	176	psxHu32ref(0x1070) \|= SWAP32(8);
	177	tmp \|= HW_DMA_ICR_IRQ_SENT;
	178	}
	179	HW_DMA_ICR = SWAPu32(tmp);
7e605697	180	}
	181
	182	#define make_dma_func(n) \
	183	static void io_write_chcr##n(u32 value) \
	184	{ \
	185	HW_DMA##n##_CHCR = value; \
	186	if (value & 0x01000000 && HW_DMA_PCR & (8 << (n * 4))) { \
	187	psxDma##n(HW_DMA##n##_MADR, HW_DMA##n##_BCR, value); \
	188	} \
	189	}
	190
	191	make_dma_func(0)
	192	make_dma_func(1)
	193	make_dma_func(2)
	194	make_dma_func(3)
	195	make_dma_func(4)
	196	make_dma_func(6)
	197
b96d3df7	198	static void io_spu_write16(u32 value)
	199	{
	200	// meh
	201	SPU_writeRegister(address, value);
	202	}
	203
	204	static void io_spu_write32(u32 value)
	205	{
	206	SPUwriteRegister wfunc = SPU_writeRegister;
	207	u32 a = address;
	208
	209	wfunc(a, value & 0xffff);
	210	wfunc(a + 2, value >> 16);
	211	}
	212
ddbaf678	213	static u32 io_gpu_read_status(void)
	214	{
	215	// meh2, syncing for img bit, might want to avoid it..
	216	gpuSyncPluginSR();
	217	return HW_GPU_STATUS;
	218	}
	219
	220	static void io_gpu_write_status(u32 value)
	221	{
	222	GPU_writeStatus(value);
	223	gpuSyncPluginSR();
	224	}
	225
b96d3df7	226	static void map_ram_write(void)
	227	{
	228	int i;
	229
	230	for (i = 0; i < (0x800000 >> 12); i++) {
	231	map_l1_mem(mem_writetab, i, 0x80000000, 0x200000, psxM);
	232	map_l1_mem(mem_writetab, i, 0x00000000, 0x200000, psxM);
	233	map_l1_mem(mem_writetab, i, 0xa0000000, 0x200000, psxM);
	234	}
	235	}
	236
	237	static void unmap_ram_write(void)
	238	{
	239	int i;
	240
	241	for (i = 0; i < (0x800000 >> 12); i++) {
	242	map_item(&mem_writetab[0x80000\|i], mem_unmwtab, 1);
	243	map_item(&mem_writetab[0x00000\|i], mem_unmwtab, 1);
	244	map_item(&mem_writetab[0xa0000\|i], mem_unmwtab, 1);
	245	}
	246	}
	247
	248	static void write_biu(u32 value)
	249	{
	250	memprintf("write_biu %08x, %08x @%08x %u\n", address, value, psxRegs.pc, psxRegs.cycle);
	251
	252	if (address != 0xfffe0130)
	253	return;
	254
	255	switch (value) {
	256	case 0x800: case 0x804:
	257	unmap_ram_write();
	258	break;
	259	case 0: case 0x1e988:
	260	map_ram_write();
	261	break;
	262	default:
	263	printf("write_biu: unexpected val: %08x\n", value);
	264	break;
	265	}
	266	}
	267
b1be1eee	268	void new_dyna_pcsx_mem_load_state(void)
	269	{
	270	map_rcnt_rcount0(rcnts[0].mode);
	271	map_rcnt_rcount1(rcnts[1].mode);
	272	map_rcnt_rcount2(rcnts[2].mode);
	273	}
	274
	275	int pcsxmem_is_handler_dynamic(u_int addr)
	276	{
	277	if ((addr & 0xfffff000) != 0x1f801000)
	278	return 0;
	279
	280	addr &= 0xffff;
	281	return addr == 0x1100 \|\| addr == 0x1110 \|\| addr == 0x1120;
	282	}
	283
7e605697	284	void new_dyna_pcsx_mem_init(void)
	285	{
	286	int i;
63cb0298	287
c6c3b1b3	288	// have to map these further to keep tcache close to .text
	289	mem_readtab = mmap((void )0x08000000, 0x200000 4, PROT_READ \| PROT_WRITE,
	290	MAP_FIXED \| MAP_PRIVATE \| MAP_ANONYMOUS, -1, 0);
	291	if (mem_readtab == MAP_FAILED) {
	292	fprintf(stderr, "failed to map mem tables\n");
	293	exit(1);
	294	}
	295	mem_writetab = mem_readtab + 0x100000;
	296
	297	// 1st level lookup:
	298	// 0: direct mem
	299	// 1: use 2nd lookup
	300	// 2nd level lookup:
	301	// 0: direct mem variable
	302	// 1: memhandler
	303
	304	// default/unmapped memhandlers
	305	for (i = 0; i < 0x100000; i++) {
	306	//map_item(&mem_readtab[i], mem_unmrtab, 1);
054175e9	307	map_l1_mem(mem_readtab, i, 0, 0x1000, zero_mem);
c6c3b1b3	308	map_item(&mem_writetab[i], mem_unmwtab, 1);
	309	}
	310
	311	// RAM and it's mirrors
	312	for (i = 0; i < (0x800000 >> 12); i++) {
	313	map_l1_mem(mem_readtab, i, 0x80000000, 0x200000, psxM);
c6c3b1b3	314	map_l1_mem(mem_readtab, i, 0x00000000, 0x200000, psxM);
c6c3b1b3	315	map_l1_mem(mem_readtab, i, 0xa0000000, 0x200000, psxM);
c6c3b1b3	316	}
b96d3df7	317	map_ram_write();
c6c3b1b3	318
	319	// BIOS and it's mirrors
	320	for (i = 0; i < (0x80000 >> 12); i++) {
	321	map_l1_mem(mem_readtab, i, 0x1fc00000, 0x80000, psxR);
	322	map_l1_mem(mem_readtab, i, 0xbfc00000, 0x80000, psxR);
	323	}
	324
	325	// scratchpad
	326	map_l1_mem(mem_readtab, 0, 0x1f800000, 0x1000, psxH);
	327	map_l1_mem(mem_writetab, 0, 0x1f800000, 0x1000, psxH);
	328
	329	// I/O
	330	map_item(&mem_readtab[0x1f801000 >> 12], mem_iortab, 1);
	331	map_item(&mem_writetab[0x1f801000 >> 12], mem_iowtab, 1);
7e605697	332
c6c3b1b3	333	// L2
c6c3b1b3	334	// unmapped tables
b96d3df7	335	for (i = 0; i < (1+2+4) * 0x1000 / 4; i++)
c6c3b1b3	336	map_item(&mem_unmwtab[i], write_mem_dummy, 1);
	337
	338	// fill IO tables
	339	for (i = 0; i < 0x1000/4; i++) {
	340	map_item(&mem_iortab[i], &psxH[0x1000], 0);
	341	map_item(&mem_iowtab[i], &psxH[0x1000], 0);
	342	}
	343	for (; i < 0x1000/4 + 0x1000/2; i++) {
	344	map_item(&mem_iortab[i], &psxH[0x1000], 0);
	345	map_item(&mem_iowtab[i], &psxH[0x1000], 0);
	346	}
	347	for (; i < 0x1000/4 + 0x1000/2 + 0x1000; i++) {
	348	map_item(&mem_iortab[i], &psxH[0x1000], 0);
	349	map_item(&mem_iowtab[i], &psxH[0x1000], 0);
	350	}
	351
	352	map_item(&mem_iortab[IOMEM32(0x1040)], io_read_sio32, 1);
	353	map_item(&mem_iortab[IOMEM32(0x1100)], io_rcnt_read_count0, 1);
	354	map_item(&mem_iortab[IOMEM32(0x1104)], io_rcnt_read_mode0, 1);
	355	map_item(&mem_iortab[IOMEM32(0x1108)], io_rcnt_read_target0, 1);
	356	map_item(&mem_iortab[IOMEM32(0x1110)], io_rcnt_read_count1, 1);
	357	map_item(&mem_iortab[IOMEM32(0x1114)], io_rcnt_read_mode1, 1);
	358	map_item(&mem_iortab[IOMEM32(0x1118)], io_rcnt_read_target1, 1);
	359	map_item(&mem_iortab[IOMEM32(0x1120)], io_rcnt_read_count2, 1);
	360	map_item(&mem_iortab[IOMEM32(0x1124)], io_rcnt_read_mode2, 1);
	361	map_item(&mem_iortab[IOMEM32(0x1128)], io_rcnt_read_target2, 1);
	362	// map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1);
ddbaf678	363	map_item(&mem_iortab[IOMEM32(0x1814)], io_gpu_read_status, 1);
c6c3b1b3	364	map_item(&mem_iortab[IOMEM32(0x1820)], mdecRead0, 1);
	365	map_item(&mem_iortab[IOMEM32(0x1824)], mdecRead1, 1);
	366
	367	map_item(&mem_iortab[IOMEM16(0x1040)], io_read_sio16, 1);
	368	map_item(&mem_iortab[IOMEM16(0x1044)], sioReadStat16, 1);
	369	map_item(&mem_iortab[IOMEM16(0x1048)], sioReadMode16, 1);
	370	map_item(&mem_iortab[IOMEM16(0x104a)], sioReadCtrl16, 1);
	371	map_item(&mem_iortab[IOMEM16(0x104e)], sioReadBaud16, 1);
	372	map_item(&mem_iortab[IOMEM16(0x1100)], io_rcnt_read_count0, 1);
	373	map_item(&mem_iortab[IOMEM16(0x1104)], io_rcnt_read_mode0, 1);
	374	map_item(&mem_iortab[IOMEM16(0x1108)], io_rcnt_read_target0, 1);
	375	map_item(&mem_iortab[IOMEM16(0x1110)], io_rcnt_read_count1, 1);
	376	map_item(&mem_iortab[IOMEM16(0x1114)], io_rcnt_read_mode1, 1);
	377	map_item(&mem_iortab[IOMEM16(0x1118)], io_rcnt_read_target1, 1);
	378	map_item(&mem_iortab[IOMEM16(0x1120)], io_rcnt_read_count2, 1);
	379	map_item(&mem_iortab[IOMEM16(0x1124)], io_rcnt_read_mode2, 1);
	380	map_item(&mem_iortab[IOMEM16(0x1128)], io_rcnt_read_target2, 1);
	381
	382	map_item(&mem_iortab[IOMEM8(0x1040)], sioRead8, 1);
	383	map_item(&mem_iortab[IOMEM8(0x1800)], cdrRead0, 1);
	384	map_item(&mem_iortab[IOMEM8(0x1801)], cdrRead1, 1);
	385	map_item(&mem_iortab[IOMEM8(0x1802)], cdrRead2, 1);
	386	map_item(&mem_iortab[IOMEM8(0x1803)], cdrRead3, 1);
	387
b96d3df7	388	// write(u32 data)
	389	map_item(&mem_iowtab[IOMEM32(0x1040)], io_write_sio32, 1);
	390	map_item(&mem_iowtab[IOMEM32(0x1070)], io_write_ireg32, 1);
	391	map_item(&mem_iowtab[IOMEM32(0x1074)], io_write_imask32, 1);
	392	map_item(&mem_iowtab[IOMEM32(0x1088)], io_write_chcr0, 1);
	393	map_item(&mem_iowtab[IOMEM32(0x1098)], io_write_chcr1, 1);
	394	map_item(&mem_iowtab[IOMEM32(0x10a8)], io_write_chcr2, 1);
	395	map_item(&mem_iowtab[IOMEM32(0x10b8)], io_write_chcr3, 1);
	396	map_item(&mem_iowtab[IOMEM32(0x10c8)], io_write_chcr4, 1);
	397	map_item(&mem_iowtab[IOMEM32(0x10e8)], io_write_chcr6, 1);
	398	map_item(&mem_iowtab[IOMEM32(0x10f4)], io_write_dma_icr32, 1);
	399	map_item(&mem_iowtab[IOMEM32(0x1100)], io_rcnt_write_count0, 1);
	400	map_item(&mem_iowtab[IOMEM32(0x1104)], io_rcnt_write_mode0, 1);
	401	map_item(&mem_iowtab[IOMEM32(0x1108)], io_rcnt_write_target0, 1);
	402	map_item(&mem_iowtab[IOMEM32(0x1110)], io_rcnt_write_count1, 1);
	403	map_item(&mem_iowtab[IOMEM32(0x1114)], io_rcnt_write_mode1, 1);
	404	map_item(&mem_iowtab[IOMEM32(0x1118)], io_rcnt_write_target1, 1);
	405	map_item(&mem_iowtab[IOMEM32(0x1120)], io_rcnt_write_count2, 1);
	406	map_item(&mem_iowtab[IOMEM32(0x1124)], io_rcnt_write_mode2, 1);
	407	map_item(&mem_iowtab[IOMEM32(0x1128)], io_rcnt_write_target2, 1);
	408	// map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1);
ddbaf678	409	map_item(&mem_iowtab[IOMEM32(0x1814)], io_gpu_write_status, 1);
b96d3df7	410	map_item(&mem_iowtab[IOMEM32(0x1820)], mdecWrite0, 1);
	411	map_item(&mem_iowtab[IOMEM32(0x1824)], mdecWrite1, 1);
	412
	413	map_item(&mem_iowtab[IOMEM16(0x1040)], io_write_sio16, 1);
	414	map_item(&mem_iowtab[IOMEM16(0x1044)], sioWriteStat16, 1);
	415	map_item(&mem_iowtab[IOMEM16(0x1048)], sioWriteMode16, 1);
	416	map_item(&mem_iowtab[IOMEM16(0x104a)], sioWriteCtrl16, 1);
	417	map_item(&mem_iowtab[IOMEM16(0x104e)], sioWriteBaud16, 1);
	418	map_item(&mem_iowtab[IOMEM16(0x1070)], io_write_ireg16, 1);
	419	map_item(&mem_iowtab[IOMEM16(0x1074)], io_write_imask16, 1);
	420	map_item(&mem_iowtab[IOMEM16(0x1100)], io_rcnt_write_count0, 1);
	421	map_item(&mem_iowtab[IOMEM16(0x1104)], io_rcnt_write_mode0, 1);
	422	map_item(&mem_iowtab[IOMEM16(0x1108)], io_rcnt_write_target0, 1);
	423	map_item(&mem_iowtab[IOMEM16(0x1110)], io_rcnt_write_count1, 1);
	424	map_item(&mem_iowtab[IOMEM16(0x1114)], io_rcnt_write_mode1, 1);
	425	map_item(&mem_iowtab[IOMEM16(0x1118)], io_rcnt_write_target1, 1);
	426	map_item(&mem_iowtab[IOMEM16(0x1120)], io_rcnt_write_count2, 1);
	427	map_item(&mem_iowtab[IOMEM16(0x1124)], io_rcnt_write_mode2, 1);
	428	map_item(&mem_iowtab[IOMEM16(0x1128)], io_rcnt_write_target2, 1);
	429
	430	map_item(&mem_iowtab[IOMEM8(0x1040)], sioWrite8, 1);
	431	map_item(&mem_iowtab[IOMEM8(0x1800)], cdrWrite0, 1);
	432	map_item(&mem_iowtab[IOMEM8(0x1801)], cdrWrite1, 1);
	433	map_item(&mem_iowtab[IOMEM8(0x1802)], cdrWrite2, 1);
	434	map_item(&mem_iowtab[IOMEM8(0x1803)], cdrWrite3, 1);
	435
	436	for (i = 0x1c00; i < 0x1e00; i += 2) {
	437	map_item(&mem_iowtab[IOMEM16(i)], io_spu_write16, 1);
	438	map_item(&mem_iowtab[IOMEM32(i)], io_spu_write32, 1);
	439	}
	440
	441	// misc
	442	map_item(&mem_writetab[0xfffe0130 >> 12], mem_ffwtab, 1);
	443	for (i = 0; i < 0x1000/4 + 0x1000/2 + 0x1000; i++)
	444	map_item(&mem_ffwtab[i], write_biu, 1);
	445
c6c3b1b3	446	mem_rtab = mem_readtab;
c6c3b1b3	447	mem_wtab = mem_writetab;
b1be1eee	448
b1be1eee	449	new_dyna_pcsx_mem_load_state();
7e605697	450	}
	451
	452	void new_dyna_pcsx_mem_reset(void)
	453	{
c6c3b1b3	454	int i;
c6c3b1b3	455
7e605697	456	// plugins might change so update the pointers
c6c3b1b3	457	map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1);
c6c3b1b3	458
	459	for (i = 0x1c00; i < 0x1e00; i += 2)
	460	map_item(&mem_iortab[IOMEM16(i)], SPU_readRegister, 1);
	461
b96d3df7	462	map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1);
7e605697	463	}