[pcsx_rearmed.git] / libpcsxcore / ppc / ppc_mnemonics.h

// ppc_mnemonics.h

#define INSTR		(*(ppcPtr)++)

/* Link register related */
#define MFLR(REG) \
	{int _reg = (REG); \
        INSTR = (0x7C0802A6 | (_reg << 21));}

#define MTLR(REG) \
	{int _reg = (REG); \
        INSTR = (0x7C0803A6 | (_reg << 21));}

#define MTCTR(REG) \
	{int _reg = (REG); \
        INSTR = (0x7C0903A6 | (_reg << 21));}

#define BLR() \
	{INSTR = (0x4E800020);}

#define BGTLR() \
	{INSTR = (0x4D810020);}


/* Load ops */
#define LI(REG, IMM) \
	{int _reg = (REG); \
        INSTR = (0x38000000 | (_reg << 21) | ((IMM) & 0xffff));}

#define LIS(REG_DST, IMM) \
	{int _dst = (REG_DST); \
        INSTR = (0x3C000000 | (_dst << 21) | ((IMM) & 0xffff));}

#define LWZ(REG_DST, OFFSET, REG) \
	{int _reg = (REG); int _dst=(REG_DST); \
        INSTR = (0x80000000 | (_dst << 21) | (_reg << 16) | ((OFFSET) & 0xffff));}

#define LWZX(REG_DST, REG, REG_OFF) \
	{int _reg = (REG), _off = (REG_OFF); int _dst=(REG_DST); \
        INSTR = (0x7C00002E | (_dst << 21) | (_reg << 16) | (_off << 11));}

#define LWBRX(REG_DST, REG, REG_OFF) \
	{int _reg = (REG), _off = (REG_OFF); int _dst=(REG_DST); \
        INSTR = (0x7C00042C | (_dst << 21) | (_reg << 16) | (_off << 11));}

#define LHZ(REG_DST, OFFSET, REG) \
	{int _reg = (REG); int _dst=(REG_DST); \
        INSTR = (0xA0000000 | (_dst << 21) | (_reg << 16) | ((OFFSET) & 0xffff));}

#define LHA(REG_DST, OFFSET, REG) \
	{int _reg = (REG); int _dst=(REG_DST); \
        INSTR = (0xA8000000 | (_dst << 21) | (_reg << 16) | ((OFFSET) & 0xffff));}

#define LHBRX(REG_DST, REG, REG_OFF) \
	{int _reg = (REG), _off = (REG_OFF); int _dst=(REG_DST); \
        INSTR = (0x7C00062C | (_dst << 21) | (_reg << 16) | (_off << 11));}

#define LBZ(REG_DST, OFFSET, REG) \
	{int _reg = (REG); int _dst=(REG_DST); \
        INSTR = (0x88000000 | (_dst << 21) | (_reg << 16) | ((OFFSET) & 0xffff));}

#define LMW(REG_DST, OFFSET, REG) \
	{int _reg = (REG); int _dst=(REG_DST); \
        INSTR = (0xB8000000 | (_dst << 21) | (_reg << 16) | ((OFFSET) & 0xffff));}


/* Store ops */
#define STMW(REG_SRC, OFFSET, REG) \
	{int _reg = (REG), _src=(REG_SRC); \
        INSTR = (0xBC000000 | (_src << 21) | (_reg << 16) | ((OFFSET) & 0xffff));}

#define STW(REG_SRC, OFFSET, REG) \
	{int _reg = (REG), _src=(REG_SRC); \
        INSTR = (0x90000000 | (_src << 21) | (_reg << 16) | ((OFFSET) & 0xffff));}

#define STWBRX(REG_SRC, REG, REG_OFF) \
	{int _reg = (REG), _src=(REG_SRC), _off = (REG_OFF); \
        INSTR = (0x7C00052C | (_src << 21) | (_reg << 16) | (_off << 11));}

#define STH(REG_SRC, OFFSET, REG) \
	{int _reg = (REG), _src=(REG_SRC); \
        INSTR = (0xB0000000 | (_src << 21) | (_reg << 16) | ((OFFSET) & 0xffff));}

#define STHBRX(REG_SRC, REG, REG_OFF) \
	{int _reg = (REG), _src=(REG_SRC), _off = (REG_OFF); \
        INSTR = (0x7C00072C | (_src << 21) | (_reg << 16) | (_off << 11));}

#define STB(REG_SRC, OFFSET, REG) \
	{int _reg = (REG), _src=(REG_SRC); \
        INSTR = (0x98000000 | (_src << 21) | (_reg << 16) | ((OFFSET) & 0xffff));}

#define STWU(REG_SRC, OFFSET, REG) \
	{int _reg = (REG), _src=(REG_SRC); \
        INSTR = (0x94000000 | (_src << 21) | (_reg << 16) | ((OFFSET) & 0xffff));}


/* Arithmic ops */
#define ADDI(REG_DST, REG_SRC, IMM) \
	{int _src = (REG_SRC); int _dst=(REG_DST); \
        INSTR = (0x38000000 | (_dst << 21) | (_src << 16) | ((IMM) & 0xffff));}

#define ADDIS(REG_DST, REG_SRC, IMM) \
	{int _src = (REG_SRC); int _dst=(REG_DST); \
        INSTR = (0x3C000000 | (_dst << 21) | (_src << 16) | ((IMM) & 0xffff));}

#define MR(REG_DST, REG_SRC) \
	{int __src = (REG_SRC); int __dst=(REG_DST); \
        if (__src != __dst) {ADDI(__dst, __src, 0)}}

#define ADD(REG_DST, REG1, REG2) \
	{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
        INSTR = (0x7C000214 | (_dst << 21) | (_reg1 << 16) |  (_reg2 << 11));}

#define ADDO(REG_DST, REG1, REG2) \
	{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
        INSTR = (0x7C000614 | (_dst << 21) | (_reg1 << 16) |  (_reg2 << 11));}

#define ADDEO(REG_DST, REG1, REG2) \
	{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
        INSTR = (0x7C000514 | (_dst << 21) | (_reg1 << 16) |  (_reg2 << 11));}

#define ADDE(REG_DST, REG1, REG2) \
	{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
        INSTR = (0x7C000114 | (_dst << 21) | (_reg1 << 16) |  (_reg2 << 11));}

#define ADDCO(REG_DST, REG1, REG2) \
	{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
        INSTR = (0x7C000414 | (_dst << 21) | (_reg1 << 16) |  (_reg2 << 11));}

#define ADDIC(REG_DST, REG_SRC, IMM) \
	{int _src = (REG_SRC); int _dst=(REG_DST); \
        INSTR = (0x30000000 | (_dst << 21) | (_src << 16) | ((IMM) & 0xffff));}

#define ADDIC_(REG_DST, REG_SRC, IMM) \
	{int _src = (REG_SRC); int _dst=(REG_DST); \
        INSTR = (0x34000000 | (_dst << 21) | (_src << 16) | ((IMM) & 0xffff));}

#define ADDZE(REG_DST, REG_SRC) \
	{int _src = (REG_SRC); int _dst=(REG_DST); \
        INSTR = (0x7C000194 | (_dst << 21) | (_src << 16));}

#define SUBF(REG_DST, REG1, REG2) \
	{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
        INSTR = (0x7C000050 | (_dst << 21) | (_reg1 << 16) |  (_reg2 << 11));}

#define SUBFO(REG_DST, REG1, REG2) \
	{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
        INSTR = (0x7C000450 | (_dst << 21) | (_reg1 << 16) |  (_reg2 << 11));}

#define SUBFC(REG_DST, REG1, REG2) \
	{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
        INSTR = (0x7C000010 | (_dst << 21) | (_reg1 << 16) |  (_reg2 << 11));}

#define SUBFE(REG_DST, REG1, REG2) \
	{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
        INSTR = (0x7C000110 | (_dst << 21) | (_reg1 << 16) |  (_reg2 << 11));}

#define SUBFCO(REG_DST, REG1, REG2) \
	{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
        INSTR = (0x7C000410 | (_dst << 21) | (_reg1 << 16) |  (_reg2 << 11));}

#define SUBFCO_(REG_DST, REG1, REG2) \
	{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
        INSTR = (0x7C000411 | (_dst << 21) | (_reg1 << 16) |  (_reg2 << 11));}

#define SUB(REG_DST, REG1, REG2) \
	{SUBF(REG_DST, REG2, REG1)}

#define SUBO(REG_DST, REG1, REG2) \
	{SUBFO(REG_DST, REG2, REG1)}

#define SUBCO(REG_DST, REG1, REG2) \
	{SUBFCO(REG_DST, REG2, REG1)}

#define SUBCO_(REG_DST, REG1, REG2) \
	{SUBFCO_(REG_DST, REG2, REG1)}

#define SRAWI(REG_DST, REG_SRC, SHIFT) \
	{int _src = (REG_SRC); int _dst=(REG_DST); \
        INSTR = (0x7C000670 | (_src << 21) | (_dst << 16) | (SHIFT << 11));}

#define MULHW(REG_DST, REG1, REG2) \
	{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
        INSTR = (0x7C000096 | (_dst << 21) | (_reg1 << 16) |  (_reg2 << 11));}

#define MULLW(REG_DST, REG1, REG2) \
	{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
        INSTR = (0x7C0001D6 | (_dst << 21) | (_reg1 << 16) |  (_reg2 << 11));}

#define MULHWU(REG_DST, REG1, REG2) \
	{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
        INSTR = (0x7C000016 | (_dst << 21) | (_reg1 << 16) |  (_reg2 << 11));}

#define MULLI(REG_DST, REG_SRC, IMM) \
	{int _src = (REG_SRC); int _dst=(REG_DST); \
        INSTR = (0x1C000000 | (_dst << 21) | (_src << 16) | ((IMM) & 0xffff));}

#define DIVW(REG_DST, REG1, REG2) \
	{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
        INSTR = (0x7C0003D6 | (_dst << 21) | (_reg1 << 16) |  (_reg2 << 11));}

#define DIVWU(REG_DST, REG1, REG2) \
	{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
        INSTR = (0x7C000396 | (_dst << 21) | (_reg1 << 16) |  (_reg2 << 11));}


/* Branch ops */
#define B_FROM(VAR) VAR = ppcPtr
#define B_DST(VAR) *VAR = *VAR | (((s16)((u32)ppcPtr - (u32)VAR)) & 0xfffc)

#define B(DST) \
	{INSTR = (0x48000000 | (((s32)(((DST)+1)<<2)) & 0x3fffffc));}

#define B_L(VAR) \
	{B_FROM(VAR); INSTR = (0x48000000);}

#define BA(DST) \
	{INSTR = (0x48000002 | ((s32)((DST) & 0x3fffffc)));}

#define BLA(DST) \
	{INSTR = (0x48000003 | ((s32)((DST) & 0x3fffffc)));}

#define BNS(DST) \
	{INSTR = (0x40830000 | (((s16)(((DST)+1)<<2)) & 0xfffc));}

#define BNE(DST) \
	{INSTR = (0x40820000 | (((s16)(((DST)+1)<<2)) & 0xfffc));}

#define BNE_L(VAR) \
	{B_FROM(VAR); INSTR = (0x40820000);}

#define BEQ(DST) \
	{INSTR = (0x41820000 | (((s16)(((DST)+1)<<2)) & 0xfffc));}

#define BEQ_L(VAR) \
	{B_FROM(VAR); INSTR = (0x41820000);}

#define BLT(DST) \
	{INSTR = (0x41800000 | (((s16)(((DST)+1)<<2)) & 0xfffc));}

#define BLT_L(VAR) \
	{B_FROM(VAR); INSTR = (0x41800000);}

#define BGT(DST) \
	{INSTR = (0x41810000 | (((s16)(((DST)+1)<<2)) & 0xfffc));}

#define BGT_L(VAR) \
	{B_FROM(VAR); INSTR = (0x41810000);}

#define BGE(DST) \
	{INSTR = (0x40800000 | (((s16)(((DST)+1)<<2)) & 0xfffc));}

#define BGE_L(VAR) \
	{B_FROM(VAR); INSTR = (0x40800000);}

#define BLE(DST) \
	{INSTR = (0x40810000 | (((s16)(((DST)+1)<<2)) & 0xfffc));}

#define BLE_L(VAR) \
	{B_FROM(VAR); INSTR = (0x40810000);}

#define BCTRL() \
	{INSTR = (0x4E800421);}

#define BCTR() \
	{INSTR = (0x4E800420);}


/* compare ops */
#define CMPLWI(REG, IMM) \
	{int _reg = (REG); \
        INSTR = (0x28000000 | (_reg << 16) | ((IMM) & 0xffff));}

#define CMPLWI2(REG, IMM) \
	{int _reg = (REG); \
        INSTR = (0x29000000 | (_reg << 16) | ((IMM) & 0xffff));}

#define CMPLWI7(REG, IMM) \
	{int _reg = (REG); \
        INSTR = (0x2B800000 | (_reg << 16) | ((IMM) & 0xffff));}

#define CMPLW(REG1, REG2) \
	{int _reg1 = (REG1), _reg2 = (REG2); \
        INSTR = (0x7C000040 | (_reg1 << 16) | (_reg2 << 11));}

#define CMPLW1(REG1, REG2) \
	{int _reg1 = (REG1), _reg2 = (REG2); \
        INSTR = (0x7C800040 | (_reg1 << 16) | (_reg2 << 11));}

#define CMPLW2(REG1, REG2) \
	{int _reg1 = (REG1), _reg2 = (REG2); \
        INSTR = (0x7D000040 | (_reg1 << 16) | (_reg2 << 11));}

#define CMPW(REG1, REG2) \
	{int _reg1 = (REG1), _reg2 = (REG2); \
        INSTR = (0x7C000000 | (_reg1 << 16) | (_reg2 << 11));}

#define CMPW1(REG1, REG2) \
	{int _reg1 = (REG1), _reg2 = (REG2); \
        INSTR = (0x7C800000 | (_reg1 << 16) | (_reg2 << 11));}

#define CMPW2(REG1, REG2) \
	{int _reg1 = (REG1), _reg2 = (REG2); \
        INSTR = (0x7D000000 | (_reg1 << 16) | (_reg2 << 11));}

#define CMPWI(REG, IMM) \
	{int _reg = (REG); \
        INSTR = (0x2C000000 | (_reg << 16) | ((IMM) & 0xffff));}

#define CMPWI2(REG, IMM) \
	{int _reg = (REG); \
        INSTR = (0x2D000000 | (_reg << 16) | ((IMM) & 0xffff));}

#define MTCRF(MASK, REG) \
	{int _reg = (REG); \
        INSTR = (0x7C000120 | (_reg << 21) | (((MASK)&0xff)<<12));}

#define MFCR(REG) \
	{int _reg = (REG); \
        INSTR = (0x7C000026 | (_reg << 21));}

#define CROR(CR_DST, CR1, CR2) \
	{INSTR = (0x4C000382 | ((CR_DST) << 21) | ((CR1) << 16) |  ((CR2) << 11));}

#define CRXOR(CR_DST, CR1, CR2) \
	{INSTR = (0x4C000182 | ((CR_DST) << 21) | ((CR1) << 16) |  ((CR2) << 11));}

#define CRNAND(CR_DST, CR1, CR2) \
	{INSTR = (0x4C0001C2 | ((CR_DST) << 21) | ((CR1) << 16) |  ((CR2) << 11));}

#define CRANDC(CR_DST, CR1, CR2) \
	{INSTR = (0x4C000102 | ((CR_DST) << 21) | ((CR1) << 16) |  ((CR2) << 11));}


/* shift ops */
#define RLWINM(REG_DST, REG_SRC, SHIFT, START, END) \
	{int _src = (REG_SRC); int _dst = (REG_DST); \
        INSTR = (0x54000000 | (_src << 21) | (_dst << 16) | (SHIFT << 11) | (START << 6) | (END << 1));}

#define RLWINM_(REG_DST, REG_SRC, SHIFT, START, END) \
	{int _src = (REG_SRC); int _dst = (REG_DST); \
        INSTR = (0x54000001 | (_src << 21) | (_dst << 16) | (SHIFT << 11) | (START << 6) | (END << 1));}

#define CLRRWI(REG_DST, REG_SRC, LEN) \
	RLWINM(REG_DST, REG_SRC, 0, 0, 31-LEN)

#define SLWI(REG_DST, REG_SRC, SHIFT) \
	{int _shift = (SHIFT); \
        if (_shift==0) {MR(REG_DST, REG_SRC)} else \
        {RLWINM(REG_DST, REG_SRC, _shift, 0, 31-_shift)}}

#define SRWI(REG_DST, REG_SRC, SHIFT) \
	{int _shift = (SHIFT); \
        if (_shift==0) {MR(REG_DST, REG_SRC)} else \
        RLWINM(REG_DST, REG_SRC, 32-_shift, _shift, 31)}

#define SLW(REG_DST, REG_SRC, REG_SHIFT) \
	{int _src = (REG_SRC), _shift = (REG_SHIFT); int _dst = (REG_DST); \
        INSTR = (0x7C000030 | (_src << 21) | (_dst << 16) | (_shift << 11));}

#define SRW(REG_DST, REG_SRC, REG_SHIFT) \
	{int _src = (REG_SRC), _shift = (REG_SHIFT); int _dst = (REG_DST); \
        INSTR = (0x7C000430 | (_src << 21) | (_dst << 16) | (_shift << 11));}

#define SRAW(REG_DST, REG_SRC, REG_SHIFT) \
	{int _src = (REG_SRC), _shift = (REG_SHIFT); int _dst = (REG_DST); \
        INSTR = (0x7C000630 | (_src << 21) | (_dst << 16) | (_shift << 11));}

#define SRAWI(REG_DST, REG_SRC, SHIFT) \
	{int _src = (REG_SRC); int _dst = (REG_DST); int _shift = (SHIFT); \
        if (_shift==0) {MR(REG_DST, REG_SRC)} else \
        INSTR = (0x7C000670 | (_src << 21) | (_dst << 16) | (_shift << 11));}

#define RLWNM(REG_DST, REG_SRC, REG_SHIFT, START, END) \
	{int _src = (REG_SRC), _shift = (REG_SHIFT); int _dst = (REG_DST); \
        INSTR = (0x5C000000 | (_src << 21) | (_dst << 16) | (_shift << 11) | (START << 6) | (END << 1));}

/* other ops */
#define ORI(REG_DST, REG_SRC, IMM) \
	{int _src = (REG_SRC), _imm = (IMM); int _dst = (REG_DST); \
        if (!((_imm == 0) && ((_src^_dst) == 0))) \
        INSTR = (0x60000000 | (_src << 21) | (_dst << 16) | (_imm & 0xffff));}

#define ORIS(REG_DST, REG_SRC, IMM) \
	{int _src = (REG_SRC), _imm = (IMM); int _dst = (REG_DST); \
        if (!((_imm == 0) && ((_src^_dst) == 0))) \
        INSTR = (0x64000000 | (_src << 21) | (_dst << 16) | (_imm & 0xffff));}

#define OR(REG_DST, REG1, REG2) \
	{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
        INSTR = (0x7C000378 | (_reg1 << 21) | (_dst << 16) | (_reg2 << 11));}

#define OR_(REG_DST, REG1, REG2) \
	{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
        INSTR = (0x7C000379 | (_reg1 << 21) | (_dst << 16) | (_reg2 << 11));}

#define XORI(REG_DST, REG_SRC, IMM) \
	{int _src = (REG_SRC); int _dst=(REG_DST); \
        INSTR = (0x68000000 | (_src << 21) | (_dst << 16) | ((IMM) & 0xffff));}

#define XOR(REG_DST, REG1, REG2) \
	{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
        INSTR = (0x7C000278 | (_reg1 << 21) | (_dst << 16) | (_reg2 << 11));}

#define XOR_(REG_DST, REG1, REG2) \
	{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
        INSTR = (0x7C000279 | (_reg1 << 21) | (_dst << 16) | (_reg2 << 11));}

#define ANDI_(REG_DST, REG_SRC, IMM) \
	{int _src = (REG_SRC); int _dst=(REG_DST); \
        INSTR = (0x70000000 | (_src << 21) | (_dst << 16) | ((IMM) & 0xffff));}

#define AND(REG_DST, REG1, REG2) \
	{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
        INSTR = (0x7C000038 | (_reg1 << 21) | (_dst << 16) | (_reg2 << 11));}

#define NOR(REG_DST, REG1, REG2) \
	{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
        INSTR = (0x7C0000f8 | (_reg1 << 21) | (_dst << 16) | (_reg2 << 11));}

#define NEG(REG_DST, REG_SRC) \
	{int _src = (REG_SRC); int _dst=(REG_DST); \
        INSTR = (0x7C0000D0 | (_dst << 21) | (_src << 16));}

#define NOP() \
	{INSTR = 0x60000000;}

#define MCRXR(CR_DST) \
	{INSTR = (0x7C000400 | (CR_DST << 23));}

#define EXTSB(REG_DST, REG_SRC) \
	{int _src = (REG_SRC); int _dst=(REG_DST); \
        INSTR = (0x7C000774 | (_src << 21) | (_dst << 16));}

#define EXTSH(REG_DST, REG_SRC) \
	{int _src = (REG_SRC); int _dst=(REG_DST); \
        INSTR = (0x7C000734 | (_src << 21) | (_dst << 16));}


/* floating point ops */
#define FDIVS(FPR_DST, FPR1, FPR2) \
	{INSTR = (0xEC000024 | (FPR_DST << 21) | (FPR1 << 16) | (FPR2 << 11));}

#define FDIV(FPR_DST, FPR1, FPR2) \
	{INSTR = (0xFC000024 | (FPR_DST << 21) | (FPR1 << 16) | (FPR2 << 11));}

#define FMULS(FPR_DST, FPR1, FPR2) \
	{INSTR = (0xEC000032 | (FPR_DST << 21) | (FPR1 << 16) | (FPR2 << 11));}

#define FMUL(FPR_DST, FPR1, FPR2) \
	{INSTR = (0xFC000032 | (FPR_DST << 21) | (FPR1 << 16) | (FPR2 << 11));}

#define FADDS(FPR_DST, FPR1, FPR2) \
	{INSTR = (0xEC00002A | (FPR_DST << 21) | (FPR1 << 16) | (FPR2 << 11));}

#define FADD(FPR_DST, FPR1, FPR2) \
	{INSTR = (0xFC00002A | (FPR_DST << 21) | (FPR1 << 16) | (FPR2 << 11));}

#define FRSP(FPR_DST, FPR_SRC) \
	{INSTR = (0xFC000018 | (FPR_DST << 21) | (FPR_SRC << 11));}

#define FCTIW(FPR_DST, FPR_SRC) \
	{INSTR = (0xFC00001C | (FPR_DST << 21) | (FPR_SRC << 11));}


#define LFS(FPR_DST, OFFSET, REG) \
	{INSTR = (0xC0000000 | (FPR_DST << 21) | (REG << 16) | ((OFFSET) & 0xffff));}

#define STFS(FPR_DST, OFFSET, REG) \
	{INSTR = (0xD0000000 | (FPR_DST << 21) | (REG << 16) | ((OFFSET) & 0xffff));}

#define LFD(FPR_DST, OFFSET, REG) \
	{INSTR = (0xC8000000 | (FPR_DST << 21) | (REG << 16) | ((OFFSET) & 0xffff));}

#define STFD(FPR_DST, OFFSET, REG) \
	{INSTR = (0xD8000000 | (FPR_DST << 21) | (REG << 16) | ((OFFSET) & 0xffff));}


/* extra combined opcodes */
#if 1
#define LIW(REG, IMM) /* Load Immidiate Word */ \
{ \
	int __reg = (REG); u32 __imm = (u32)(IMM); \
	if ((s32)__imm == (s32)((s16)__imm)) \
	{ \
		LI(__reg, (s32)((s16)__imm)); \
	} else if (__reg == 0) { \
		LIS(__reg, (((u32)__imm)>>16)); \
		if ((((u32)__imm) & 0xffff) != 0) \
		{ \
			ORI(__reg, __reg, __imm); \
		} \
	} else { \
		if ((((u32)__imm) & 0xffff) == 0) { \
			LIS(__reg, (((u32)__imm)>>16)); \
		} else { \
			LI(__reg, __imm); \
			if ((__imm & 0x8000) == 0) { \
				ADDIS(__reg, __reg, ((u32)__imm)>>16); \
			} else { \
				ADDIS(__reg, __reg, ((((u32)__imm)>>16) & 0xffff) + 1); \
			} \
		} \
		/*if ((((u32)__imm) & 0xffff) != 0) \
		{ \
			ORI(__reg, __reg, __imm); \
		}*/ \
	} \
}
#else
#define LIW(REG, IMM) /* Load Immidiate Word */ \
{ \
        int __reg = (REG); u32 __imm = (u32)(IMM); \
	if ((s32)__imm == (s32)((s16)__imm)) \
	{ \
		LI(__reg, (s32)((s16)__imm)); \
	} \
	else \
	{ \
		LIS(__reg, (((u32)__imm)>>16)); \
		if ((((u32)__imm) & 0xffff) != 0) \
		{ \
			ORI(__reg, __reg, __imm); \
		} \
	} \
}
#endif
Commit	Line	Data
ef79bbde P	1	// ppc_mnemonics.h
	2
	3	#define INSTR (*(ppcPtr)++)
	4
	5	/* Link register related */
	6	#define MFLR(REG) \
	7	{int _reg = (REG); \
	8	INSTR = (0x7C0802A6 \| (_reg << 21));}
	9
	10	#define MTLR(REG) \
	11	{int _reg = (REG); \
	12	INSTR = (0x7C0803A6 \| (_reg << 21));}
	13
	14	#define MTCTR(REG) \
	15	{int _reg = (REG); \
	16	INSTR = (0x7C0903A6 \| (_reg << 21));}
	17
	18	#define BLR() \
	19	{INSTR = (0x4E800020);}
	20
	21	#define BGTLR() \
	22	{INSTR = (0x4D810020);}
	23
	24
	25	/* Load ops */
	26	#define LI(REG, IMM) \
	27	{int _reg = (REG); \
	28	INSTR = (0x38000000 \| (_reg << 21) \| ((IMM) & 0xffff));}
	29
	30	#define LIS(REG_DST, IMM) \
	31	{int _dst = (REG_DST); \
	32	INSTR = (0x3C000000 \| (_dst << 21) \| ((IMM) & 0xffff));}
	33
	34	#define LWZ(REG_DST, OFFSET, REG) \
	35	{int _reg = (REG); int _dst=(REG_DST); \
	36	INSTR = (0x80000000 \| (_dst << 21) \| (_reg << 16) \| ((OFFSET) & 0xffff));}
	37
	38	#define LWZX(REG_DST, REG, REG_OFF) \
	39	{int _reg = (REG), _off = (REG_OFF); int _dst=(REG_DST); \
	40	INSTR = (0x7C00002E \| (_dst << 21) \| (_reg << 16) \| (_off << 11));}
	41
	42	#define LWBRX(REG_DST, REG, REG_OFF) \
	43	{int _reg = (REG), _off = (REG_OFF); int _dst=(REG_DST); \
	44	INSTR = (0x7C00042C \| (_dst << 21) \| (_reg << 16) \| (_off << 11));}
	45
	46	#define LHZ(REG_DST, OFFSET, REG) \
	47	{int _reg = (REG); int _dst=(REG_DST); \
	48	INSTR = (0xA0000000 \| (_dst << 21) \| (_reg << 16) \| ((OFFSET) & 0xffff));}
	49
	50	#define LHA(REG_DST, OFFSET, REG) \
	51	{int _reg = (REG); int _dst=(REG_DST); \
	52	INSTR = (0xA8000000 \| (_dst << 21) \| (_reg << 16) \| ((OFFSET) & 0xffff));}
	53
	54	#define LHBRX(REG_DST, REG, REG_OFF) \
	55	{int _reg = (REG), _off = (REG_OFF); int _dst=(REG_DST); \
	56	INSTR = (0x7C00062C \| (_dst << 21) \| (_reg << 16) \| (_off << 11));}
	57
	58	#define LBZ(REG_DST, OFFSET, REG) \
	59	{int _reg = (REG); int _dst=(REG_DST); \
	60	INSTR = (0x88000000 \| (_dst << 21) \| (_reg << 16) \| ((OFFSET) & 0xffff));}
	61
	62	#define LMW(REG_DST, OFFSET, REG) \
	63	{int _reg = (REG); int _dst=(REG_DST); \
	64	INSTR = (0xB8000000 \| (_dst << 21) \| (_reg << 16) \| ((OFFSET) & 0xffff));}
65
66
67
68	/* Store ops */
69	#define STMW(REG_SRC, OFFSET, REG) \
70	{int _reg = (REG), _src=(REG_SRC); \
71	INSTR = (0xBC000000 \| (_src << 21) \| (_reg << 16) \| ((OFFSET) & 0xffff));}
72
73	#define STW(REG_SRC, OFFSET, REG) \
74	{int _reg = (REG), _src=(REG_SRC); \
75	INSTR = (0x90000000 \| (_src << 21) \| (_reg << 16) \| ((OFFSET) & 0xffff));}
76
77	#define STWBRX(REG_SRC, REG, REG_OFF) \
78	{int _reg = (REG), _src=(REG_SRC), _off = (REG_OFF); \
79	INSTR = (0x7C00052C \| (_src << 21) \| (_reg << 16) \| (_off << 11));}
80
81	#define STH(REG_SRC, OFFSET, REG) \
82	{int _reg = (REG), _src=(REG_SRC); \
83	INSTR = (0xB0000000 \| (_src << 21) \| (_reg << 16) \| ((OFFSET) & 0xffff));}
84
85	#define STHBRX(REG_SRC, REG, REG_OFF) \
86	{int _reg = (REG), _src=(REG_SRC), _off = (REG_OFF); \
87	INSTR = (0x7C00072C \| (_src << 21) \| (_reg << 16) \| (_off << 11));}
88
89	#define STB(REG_SRC, OFFSET, REG) \
90	{int _reg = (REG), _src=(REG_SRC); \
91	INSTR = (0x98000000 \| (_src << 21) \| (_reg << 16) \| ((OFFSET) & 0xffff));}
92
93	#define STWU(REG_SRC, OFFSET, REG) \
94	{int _reg = (REG), _src=(REG_SRC); \
95	INSTR = (0x94000000 \| (_src << 21) \| (_reg << 16) \| ((OFFSET) & 0xffff));}
96
97
98	/* Arithmic ops */
99	#define ADDI(REG_DST, REG_SRC, IMM) \
100	{int _src = (REG_SRC); int _dst=(REG_DST); \
101	INSTR = (0x38000000 \| (_dst << 21) \| (_src << 16) \| ((IMM) & 0xffff));}
102
103	#define ADDIS(REG_DST, REG_SRC, IMM) \
104	{int _src = (REG_SRC); int _dst=(REG_DST); \
105	INSTR = (0x3C000000 \| (_dst << 21) \| (_src << 16) \| ((IMM) & 0xffff));}
106
107	#define MR(REG_DST, REG_SRC) \
108	{int __src = (REG_SRC); int __dst=(REG_DST); \
109	if (__src != __dst) {ADDI(__dst, __src, 0)}}
110
111	#define ADD(REG_DST, REG1, REG2) \
112	{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
113	INSTR = (0x7C000214 \| (_dst << 21) \| (_reg1 << 16) \| (_reg2 << 11));}
114
115	#define ADDO(REG_DST, REG1, REG2) \
116	{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
117	INSTR = (0x7C000614 \| (_dst << 21) \| (_reg1 << 16) \| (_reg2 << 11));}
118
119	#define ADDEO(REG_DST, REG1, REG2) \
120	{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
121	INSTR = (0x7C000514 \| (_dst << 21) \| (_reg1 << 16) \| (_reg2 << 11));}
122
123	#define ADDE(REG_DST, REG1, REG2) \
124	{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
125	INSTR = (0x7C000114 \| (_dst << 21) \| (_reg1 << 16) \| (_reg2 << 11));}
126
127	#define ADDCO(REG_DST, REG1, REG2) \
128	{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
129	INSTR = (0x7C000414 \| (_dst << 21) \| (_reg1 << 16) \| (_reg2 << 11));}
130
131	#define ADDIC(REG_DST, REG_SRC, IMM) \
132	{int _src = (REG_SRC); int _dst=(REG_DST); \
133	INSTR = (0x30000000 \| (_dst << 21) \| (_src << 16) \| ((IMM) & 0xffff));}
134
135	#define ADDIC_(REG_DST, REG_SRC, IMM) \
136	{int _src = (REG_SRC); int _dst=(REG_DST); \
137	INSTR = (0x34000000 \| (_dst << 21) \| (_src << 16) \| ((IMM) & 0xffff));}
138
139	#define ADDZE(REG_DST, REG_SRC) \
140	{int _src = (REG_SRC); int _dst=(REG_DST); \
141	INSTR = (0x7C000194 \| (_dst << 21) \| (_src << 16));}
142
143	#define SUBF(REG_DST, REG1, REG2) \
144	{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
145	INSTR = (0x7C000050 \| (_dst << 21) \| (_reg1 << 16) \| (_reg2 << 11));}
146
147	#define SUBFO(REG_DST, REG1, REG2) \
148	{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
149	INSTR = (0x7C000450 \| (_dst << 21) \| (_reg1 << 16) \| (_reg2 << 11));}
150
151	#define SUBFC(REG_DST, REG1, REG2) \
152	{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
153	INSTR = (0x7C000010 \| (_dst << 21) \| (_reg1 << 16) \| (_reg2 << 11));}
154
155	#define SUBFE(REG_DST, REG1, REG2) \
156	{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
157	INSTR = (0x7C000110 \| (_dst << 21) \| (_reg1 << 16) \| (_reg2 << 11));}
158
159	#define SUBFCO(REG_DST, REG1, REG2) \
160	{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
161	INSTR = (0x7C000410 \| (_dst << 21) \| (_reg1 << 16) \| (_reg2 << 11));}
162
163	#define SUBFCO_(REG_DST, REG1, REG2) \
164	{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
165	INSTR = (0x7C000411 \| (_dst << 21) \| (_reg1 << 16) \| (_reg2 << 11));}
166
167	#define SUB(REG_DST, REG1, REG2) \
168	{SUBF(REG_DST, REG2, REG1)}
169
170	#define SUBO(REG_DST, REG1, REG2) \
171	{SUBFO(REG_DST, REG2, REG1)}
172
173	#define SUBCO(REG_DST, REG1, REG2) \
174	{SUBFCO(REG_DST, REG2, REG1)}
175
176	#define SUBCO_(REG_DST, REG1, REG2) \
177	{SUBFCO_(REG_DST, REG2, REG1)}
178
179	#define SRAWI(REG_DST, REG_SRC, SHIFT) \
180	{int _src = (REG_SRC); int _dst=(REG_DST); \
181	INSTR = (0x7C000670 \| (_src << 21) \| (_dst << 16) \| (SHIFT << 11));}
182
183	#define MULHW(REG_DST, REG1, REG2) \
184	{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
185	INSTR = (0x7C000096 \| (_dst << 21) \| (_reg1 << 16) \| (_reg2 << 11));}
186
187	#define MULLW(REG_DST, REG1, REG2) \
188	{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
189	INSTR = (0x7C0001D6 \| (_dst << 21) \| (_reg1 << 16) \| (_reg2 << 11));}
190
191	#define MULHWU(REG_DST, REG1, REG2) \
192	{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
193	INSTR = (0x7C000016 \| (_dst << 21) \| (_reg1 << 16) \| (_reg2 << 11));}
194
195	#define MULLI(REG_DST, REG_SRC, IMM) \
196	{int _src = (REG_SRC); int _dst=(REG_DST); \
197	INSTR = (0x1C000000 \| (_dst << 21) \| (_src << 16) \| ((IMM) & 0xffff));}
198
199	#define DIVW(REG_DST, REG1, REG2) \
200	{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
201	INSTR = (0x7C0003D6 \| (_dst << 21) \| (_reg1 << 16) \| (_reg2 << 11));}
202
203	#define DIVWU(REG_DST, REG1, REG2) \
204	{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
205	INSTR = (0x7C000396 \| (_dst << 21) \| (_reg1 << 16) \| (_reg2 << 11));}
206
207
208	/* Branch ops */
209	#define B_FROM(VAR) VAR = ppcPtr
210	#define B_DST(VAR) VAR = VAR \| (((s16)((u32)ppcPtr - (u32)VAR)) & 0xfffc)
211
212	#define B(DST) \
213	{INSTR = (0x48000000 \| (((s32)(((DST)+1)<<2)) & 0x3fffffc));}
214
215	#define B_L(VAR) \
216	{B_FROM(VAR); INSTR = (0x48000000);}
217
218	#define BA(DST) \
219	{INSTR = (0x48000002 \| ((s32)((DST) & 0x3fffffc)));}
220
221	#define BLA(DST) \
222	{INSTR = (0x48000003 \| ((s32)((DST) & 0x3fffffc)));}
223
224	#define BNS(DST) \
225	{INSTR = (0x40830000 \| (((s16)(((DST)+1)<<2)) & 0xfffc));}
226
227	#define BNE(DST) \
228	{INSTR = (0x40820000 \| (((s16)(((DST)+1)<<2)) & 0xfffc));}
229
230	#define BNE_L(VAR) \
231	{B_FROM(VAR); INSTR = (0x40820000);}
232
233	#define BEQ(DST) \
234	{INSTR = (0x41820000 \| (((s16)(((DST)+1)<<2)) & 0xfffc));}
235
236	#define BEQ_L(VAR) \
237	{B_FROM(VAR); INSTR = (0x41820000);}
238
239	#define BLT(DST) \
240	{INSTR = (0x41800000 \| (((s16)(((DST)+1)<<2)) & 0xfffc));}
241
242	#define BLT_L(VAR) \
243	{B_FROM(VAR); INSTR = (0x41800000);}
244
245	#define BGT(DST) \
246	{INSTR = (0x41810000 \| (((s16)(((DST)+1)<<2)) & 0xfffc));}
247
248	#define BGT_L(VAR) \
249	{B_FROM(VAR); INSTR = (0x41810000);}
250
251	#define BGE(DST) \
252	{INSTR = (0x40800000 \| (((s16)(((DST)+1)<<2)) & 0xfffc));}
253
254	#define BGE_L(VAR) \
255	{B_FROM(VAR); INSTR = (0x40800000);}
256
257	#define BLE(DST) \
258	{INSTR = (0x40810000 \| (((s16)(((DST)+1)<<2)) & 0xfffc));}
259
260	#define BLE_L(VAR) \
261	{B_FROM(VAR); INSTR = (0x40810000);}
262
263	#define BCTRL() \
264	{INSTR = (0x4E800421);}
265
266	#define BCTR() \
267	{INSTR = (0x4E800420);}
268
269
270	/* compare ops */
271	#define CMPLWI(REG, IMM) \
272	{int _reg = (REG); \
273	INSTR = (0x28000000 \| (_reg << 16) \| ((IMM) & 0xffff));}
274
275	#define CMPLWI2(REG, IMM) \
276	{int _reg = (REG); \
277	INSTR = (0x29000000 \| (_reg << 16) \| ((IMM) & 0xffff));}
278
279	#define CMPLWI7(REG, IMM) \
280	{int _reg = (REG); \
281	INSTR = (0x2B800000 \| (_reg << 16) \| ((IMM) & 0xffff));}
282
283	#define CMPLW(REG1, REG2) \
284	{int _reg1 = (REG1), _reg2 = (REG2); \
285	INSTR = (0x7C000040 \| (_reg1 << 16) \| (_reg2 << 11));}
286
287	#define CMPLW1(REG1, REG2) \
288	{int _reg1 = (REG1), _reg2 = (REG2); \
289	INSTR = (0x7C800040 \| (_reg1 << 16) \| (_reg2 << 11));}
290
291	#define CMPLW2(REG1, REG2) \
292	{int _reg1 = (REG1), _reg2 = (REG2); \
293	INSTR = (0x7D000040 \| (_reg1 << 16) \| (_reg2 << 11));}
294
295	#define CMPW(REG1, REG2) \
296	{int _reg1 = (REG1), _reg2 = (REG2); \
297	INSTR = (0x7C000000 \| (_reg1 << 16) \| (_reg2 << 11));}
298
299	#define CMPW1(REG1, REG2) \
300	{int _reg1 = (REG1), _reg2 = (REG2); \
301	INSTR = (0x7C800000 \| (_reg1 << 16) \| (_reg2 << 11));}
302
303	#define CMPW2(REG1, REG2) \
304	{int _reg1 = (REG1), _reg2 = (REG2); \
305	INSTR = (0x7D000000 \| (_reg1 << 16) \| (_reg2 << 11));}
306
307	#define CMPWI(REG, IMM) \
308	{int _reg = (REG); \
309	INSTR = (0x2C000000 \| (_reg << 16) \| ((IMM) & 0xffff));}
310
311	#define CMPWI2(REG, IMM) \
312	{int _reg = (REG); \
313	INSTR = (0x2D000000 \| (_reg << 16) \| ((IMM) & 0xffff));}
314
315	#define MTCRF(MASK, REG) \
316	{int _reg = (REG); \
317	INSTR = (0x7C000120 \| (_reg << 21) \| (((MASK)&0xff)<<12));}
318
319	#define MFCR(REG) \
320	{int _reg = (REG); \
321	INSTR = (0x7C000026 \| (_reg << 21));}
322
323	#define CROR(CR_DST, CR1, CR2) \
324	{INSTR = (0x4C000382 \| ((CR_DST) << 21) \| ((CR1) << 16) \| ((CR2) << 11));}
325
326	#define CRXOR(CR_DST, CR1, CR2) \
327	{INSTR = (0x4C000182 \| ((CR_DST) << 21) \| ((CR1) << 16) \| ((CR2) << 11));}
328
329	#define CRNAND(CR_DST, CR1, CR2) \
330	{INSTR = (0x4C0001C2 \| ((CR_DST) << 21) \| ((CR1) << 16) \| ((CR2) << 11));}
331
332	#define CRANDC(CR_DST, CR1, CR2) \
333	{INSTR = (0x4C000102 \| ((CR_DST) << 21) \| ((CR1) << 16) \| ((CR2) << 11));}
334
335
336	/* shift ops */
337	#define RLWINM(REG_DST, REG_SRC, SHIFT, START, END) \
338	{int _src = (REG_SRC); int _dst = (REG_DST); \
339	INSTR = (0x54000000 \| (_src << 21) \| (_dst << 16) \| (SHIFT << 11) \| (START << 6) \| (END << 1));}
340
341	#define RLWINM_(REG_DST, REG_SRC, SHIFT, START, END) \
342	{int _src = (REG_SRC); int _dst = (REG_DST); \
343	INSTR = (0x54000001 \| (_src << 21) \| (_dst << 16) \| (SHIFT << 11) \| (START << 6) \| (END << 1));}
344
345	#define CLRRWI(REG_DST, REG_SRC, LEN) \
346	RLWINM(REG_DST, REG_SRC, 0, 0, 31-LEN)
347
348	#define SLWI(REG_DST, REG_SRC, SHIFT) \
349	{int _shift = (SHIFT); \
350	if (_shift==0) {MR(REG_DST, REG_SRC)} else \
351	{RLWINM(REG_DST, REG_SRC, _shift, 0, 31-_shift)}}
352
353	#define SRWI(REG_DST, REG_SRC, SHIFT) \
354	{int _shift = (SHIFT); \
355	if (_shift==0) {MR(REG_DST, REG_SRC)} else \
356	RLWINM(REG_DST, REG_SRC, 32-_shift, _shift, 31)}
357
358	#define SLW(REG_DST, REG_SRC, REG_SHIFT) \
359	{int _src = (REG_SRC), _shift = (REG_SHIFT); int _dst = (REG_DST); \
360	INSTR = (0x7C000030 \| (_src << 21) \| (_dst << 16) \| (_shift << 11));}
361
362	#define SRW(REG_DST, REG_SRC, REG_SHIFT) \
363	{int _src = (REG_SRC), _shift = (REG_SHIFT); int _dst = (REG_DST); \
364	INSTR = (0x7C000430 \| (_src << 21) \| (_dst << 16) \| (_shift << 11));}
365
366	#define SRAW(REG_DST, REG_SRC, REG_SHIFT) \
367	{int _src = (REG_SRC), _shift = (REG_SHIFT); int _dst = (REG_DST); \
368	INSTR = (0x7C000630 \| (_src << 21) \| (_dst << 16) \| (_shift << 11));}
369
370	#define SRAWI(REG_DST, REG_SRC, SHIFT) \
371	{int _src = (REG_SRC); int _dst = (REG_DST); int _shift = (SHIFT); \
372	if (_shift==0) {MR(REG_DST, REG_SRC)} else \
373	INSTR = (0x7C000670 \| (_src << 21) \| (_dst << 16) \| (_shift << 11));}
374
375	#define RLWNM(REG_DST, REG_SRC, REG_SHIFT, START, END) \
376	{int _src = (REG_SRC), _shift = (REG_SHIFT); int _dst = (REG_DST); \
377	INSTR = (0x5C000000 \| (_src << 21) \| (_dst << 16) \| (_shift << 11) \| (START << 6) \| (END << 1));}
378
379	/* other ops */
380	#define ORI(REG_DST, REG_SRC, IMM) \
381	{int _src = (REG_SRC), _imm = (IMM); int _dst = (REG_DST); \
382	if (!((_imm == 0) && ((_src^_dst) == 0))) \
383	INSTR = (0x60000000 \| (_src << 21) \| (_dst << 16) \| (_imm & 0xffff));}
384
385	#define ORIS(REG_DST, REG_SRC, IMM) \
386	{int _src = (REG_SRC), _imm = (IMM); int _dst = (REG_DST); \
387	if (!((_imm == 0) && ((_src^_dst) == 0))) \
388	INSTR = (0x64000000 \| (_src << 21) \| (_dst << 16) \| (_imm & 0xffff));}
389
390	#define OR(REG_DST, REG1, REG2) \
391	{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
392	INSTR = (0x7C000378 \| (_reg1 << 21) \| (_dst << 16) \| (_reg2 << 11));}
393
394	#define OR_(REG_DST, REG1, REG2) \
395	{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
396	INSTR = (0x7C000379 \| (_reg1 << 21) \| (_dst << 16) \| (_reg2 << 11));}
397
398	#define XORI(REG_DST, REG_SRC, IMM) \
399	{int _src = (REG_SRC); int _dst=(REG_DST); \
400	INSTR = (0x68000000 \| (_src << 21) \| (_dst << 16) \| ((IMM) & 0xffff));}
401
402	#define XOR(REG_DST, REG1, REG2) \
403	{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
404	INSTR = (0x7C000278 \| (_reg1 << 21) \| (_dst << 16) \| (_reg2 << 11));}
405
406	#define XOR_(REG_DST, REG1, REG2) \
407	{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
408	INSTR = (0x7C000279 \| (_reg1 << 21) \| (_dst << 16) \| (_reg2 << 11));}
409
410	#define ANDI_(REG_DST, REG_SRC, IMM) \
411	{int _src = (REG_SRC); int _dst=(REG_DST); \
412	INSTR = (0x70000000 \| (_src << 21) \| (_dst << 16) \| ((IMM) & 0xffff));}
413
414	#define AND(REG_DST, REG1, REG2) \
415	{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
416	INSTR = (0x7C000038 \| (_reg1 << 21) \| (_dst << 16) \| (_reg2 << 11));}
417
418	#define NOR(REG_DST, REG1, REG2) \
419	{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
420	INSTR = (0x7C0000f8 \| (_reg1 << 21) \| (_dst << 16) \| (_reg2 << 11));}
421
422	#define NEG(REG_DST, REG_SRC) \
423	{int _src = (REG_SRC); int _dst=(REG_DST); \
424	INSTR = (0x7C0000D0 \| (_dst << 21) \| (_src << 16));}
425
426	#define NOP() \
427	{INSTR = 0x60000000;}
428
429	#define MCRXR(CR_DST) \
430	{INSTR = (0x7C000400 \| (CR_DST << 23));}
431
432	#define EXTSB(REG_DST, REG_SRC) \
433	{int _src = (REG_SRC); int _dst=(REG_DST); \
434	INSTR = (0x7C000774 \| (_src << 21) \| (_dst << 16));}
435
436	#define EXTSH(REG_DST, REG_SRC) \
437	{int _src = (REG_SRC); int _dst=(REG_DST); \
438	INSTR = (0x7C000734 \| (_src << 21) \| (_dst << 16));}
439
440
441	/* floating point ops */
442	#define FDIVS(FPR_DST, FPR1, FPR2) \
443	{INSTR = (0xEC000024 \| (FPR_DST << 21) \| (FPR1 << 16) \| (FPR2 << 11));}
444
445	#define FDIV(FPR_DST, FPR1, FPR2) \
446	{INSTR = (0xFC000024 \| (FPR_DST << 21) \| (FPR1 << 16) \| (FPR2 << 11));}
447
448	#define FMULS(FPR_DST, FPR1, FPR2) \
449	{INSTR = (0xEC000032 \| (FPR_DST << 21) \| (FPR1 << 16) \| (FPR2 << 11));}
450
451	#define FMUL(FPR_DST, FPR1, FPR2) \
452	{INSTR = (0xFC000032 \| (FPR_DST << 21) \| (FPR1 << 16) \| (FPR2 << 11));}
453
454	#define FADDS(FPR_DST, FPR1, FPR2) \
455	{INSTR = (0xEC00002A \| (FPR_DST << 21) \| (FPR1 << 16) \| (FPR2 << 11));}
456
457	#define FADD(FPR_DST, FPR1, FPR2) \
458	{INSTR = (0xFC00002A \| (FPR_DST << 21) \| (FPR1 << 16) \| (FPR2 << 11));}
459
460	#define FRSP(FPR_DST, FPR_SRC) \
461	{INSTR = (0xFC000018 \| (FPR_DST << 21) \| (FPR_SRC << 11));}
462
463	#define FCTIW(FPR_DST, FPR_SRC) \
464	{INSTR = (0xFC00001C \| (FPR_DST << 21) \| (FPR_SRC << 11));}
465
466
467	#define LFS(FPR_DST, OFFSET, REG) \
468	{INSTR = (0xC0000000 \| (FPR_DST << 21) \| (REG << 16) \| ((OFFSET) & 0xffff));}
469
470	#define STFS(FPR_DST, OFFSET, REG) \
471	{INSTR = (0xD0000000 \| (FPR_DST << 21) \| (REG << 16) \| ((OFFSET) & 0xffff));}
472
473	#define LFD(FPR_DST, OFFSET, REG) \
474	{INSTR = (0xC8000000 \| (FPR_DST << 21) \| (REG << 16) \| ((OFFSET) & 0xffff));}
475
476	#define STFD(FPR_DST, OFFSET, REG) \
477	{INSTR = (0xD8000000 \| (FPR_DST << 21) \| (REG << 16) \| ((OFFSET) & 0xffff));}
478
479
480
481	/* extra combined opcodes */
482	#if 1
483	#define LIW(REG, IMM) /* Load Immidiate Word */ \
484	{ \
485	int __reg = (REG); u32 __imm = (u32)(IMM); \
486	if ((s32)__imm == (s32)((s16)__imm)) \
487	{ \
488	LI(__reg, (s32)((s16)__imm)); \
489	} else if (__reg == 0) { \
490	LIS(__reg, (((u32)__imm)>>16)); \
491	if ((((u32)__imm) & 0xffff) != 0) \
492	{ \
493	ORI(__reg, __reg, __imm); \
494	} \
495	} else { \
496	if ((((u32)__imm) & 0xffff) == 0) { \
497	LIS(__reg, (((u32)__imm)>>16)); \
498	} else { \
499	LI(__reg, __imm); \
500	if ((__imm & 0x8000) == 0) { \
501	ADDIS(__reg, __reg, ((u32)__imm)>>16); \
502	} else { \
503	ADDIS(__reg, __reg, ((((u32)__imm)>>16) & 0xffff) + 1); \
504	} \
505	} \
506	/*if ((((u32)__imm) & 0xffff) != 0) \
507	{ \
508	ORI(__reg, __reg, __imm); \
509	}*/ \
510	} \
511	}
512	#else
513	#define LIW(REG, IMM) /* Load Immidiate Word */ \
514	{ \
515	int __reg = (REG); u32 __imm = (u32)(IMM); \
516	if ((s32)__imm == (s32)((s16)__imm)) \
517	{ \
518	LI(__reg, (s32)((s16)__imm)); \
519	} \
520	else \
521	{ \
522	LIS(__reg, (((u32)__imm)>>16)); \
523	if ((((u32)__imm) & 0xffff) != 0) \
524	{ \
525	ORI(__reg, __reg, __imm); \
526	} \
527	} \
528	}
529	#endif