[pcsx_rearmed.git] / libpcsxcore / psxcounters.c

/***************************************************************************
 *   Copyright (C) 2010 by Blade_Arma                                      *
 *                                                                         *
 *   This program is free software; you can redistribute it and/or modify  *
 *   it under the terms of the GNU General Public License as published by  *
 *   the Free Software Foundation; either version 2 of the License, or     *
 *   (at your option) any later version.                                   *
 *                                                                         *
 *   This program is distributed in the hope that it will be useful,       *
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
 *   GNU General Public License for more details.                          *
 *                                                                         *
 *   You should have received a copy of the GNU General Public License     *
 *   along with this program; if not, write to the                         *
 *   Free Software Foundation, Inc.,                                       *
 *   51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA.           *
 ***************************************************************************/

/*
 * Internal PSX counters.
 */

#include "psxcounters.h"
#include "debug.h"

/******************************************************************************/

enum
{
    Rc0Gate           = 0x0001, // 0    not implemented
    Rc1Gate           = 0x0001, // 0    not implemented
    Rc2Disable        = 0x0001, // 0    partially implemented
    RcUnknown1        = 0x0002, // 1    ?
    RcUnknown2        = 0x0004, // 2    ?
    RcCountToTarget   = 0x0008, // 3
    RcIrqOnTarget     = 0x0010, // 4
    RcIrqOnOverflow   = 0x0020, // 5
    RcIrqRegenerate   = 0x0040, // 6
    RcUnknown7        = 0x0080, // 7    ?
    Rc0PixelClock     = 0x0100, // 8    fake implementation
    Rc1HSyncClock     = 0x0100, // 8
    Rc2Unknown8       = 0x0100, // 8    ?
    Rc0Unknown9       = 0x0200, // 9    ?
    Rc1Unknown9       = 0x0200, // 9    ?
    Rc2OneEighthClock = 0x0200, // 9
    RcUnknown10       = 0x0400, // 10   ?
    RcCountEqTarget   = 0x0800, // 11
    RcOverflow        = 0x1000, // 12
    RcUnknown13       = 0x2000, // 13   ? (always zero)
    RcUnknown14       = 0x4000, // 14   ? (always zero)
    RcUnknown15       = 0x8000, // 15   ? (always zero)
};

#define CounterQuantity           ( 4 )
//static const u32 CounterQuantity  = 4;

static const u32 CountToOverflow  = 0;
static const u32 CountToTarget    = 1;

static const u32 FrameRate[]      = { 60, 50 };
static const u32 VBlankStart[]    = { 240, 256 };
static const u32 HSyncTotal[]     = { 263, 313 };
static const u32 SpuUpdInterval[] = { 32, 32 };

#define VERBOSE_LEVEL 0
static const s32 VerboseLevel     = VERBOSE_LEVEL;

/******************************************************************************/

Rcnt rcnts[ CounterQuantity ];

static u32 hSyncCount = 0;
static u32 spuSyncCount = 0;
static u32 hsync_steps = 0;
static u32 gpu_wants_hcnt = 0;
static u32 base_cycle = 0;

u32 psxNextCounter = 0, psxNextsCounter = 0;

/******************************************************************************/

static inline
void setIrq( u32 irq )
{
    psxHu32ref(0x1070) |= SWAPu32(irq);
}

static
void verboseLog( u32 level, const char *str, ... )
{
#if VERBOSE_LEVEL > 0
    if( level <= VerboseLevel )
    {
        va_list va;
        char buf[ 4096 ];

        va_start( va, str );
        vsprintf( buf, str, va );
        va_end( va );

        printf( "%s", buf );
        fflush( stdout );
    }
#endif
}

/******************************************************************************/

static inline
void _psxRcntWcount( u32 index, u32 value )
{
    if( value > 0xffff )
    {
        verboseLog( 1, "[RCNT %i] wcount > 0xffff: %x\n", index, value );
        value &= 0xffff;
    }

    rcnts[index].cycleStart  = psxRegs.cycle;
    rcnts[index].cycleStart -= value * rcnts[index].rate;

    // TODO: <=.
    if( value < rcnts[index].target )
    {
        rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
        rcnts[index].counterState = CountToTarget;
    }
    else
    {
        rcnts[index].cycle = 0xffff * rcnts[index].rate;
        rcnts[index].counterState = CountToOverflow;
    }
}

static inline
u32 _psxRcntRcount( u32 index )
{
    u32 count;

    count  = psxRegs.cycle;
    count -= rcnts[index].cycleStart;
    if (rcnts[index].rate > 1)
        count /= rcnts[index].rate;

    if( count > 0xffff )
    {
        verboseLog( 1, "[RCNT %i] rcount > 0xffff: %x\n", index, count );
        count &= 0xffff;
    }

    return count;
}

/******************************************************************************/

static
void psxRcntSet()
{
    s32 countToUpdate;
    u32 i;

    psxNextsCounter = psxRegs.cycle;
    psxNextCounter  = 0x7fffffff;

    for( i = 0; i < CounterQuantity; ++i )
    {
        countToUpdate = rcnts[i].cycle - (psxNextsCounter - rcnts[i].cycleStart);

        if( countToUpdate < 0 )
        {
            psxNextCounter = 0;
            break;
        }

        if( countToUpdate < (s32)psxNextCounter )
        {
            psxNextCounter = countToUpdate;
        }
    }

    psxRegs.interrupt |= (1 << PSXINT_RCNT);
    new_dyna_set_event(PSXINT_RCNT, psxNextCounter);
}

/******************************************************************************/

static
void psxRcntReset( u32 index )
{
    u32 count;

    if( rcnts[index].counterState == CountToTarget )
    {
        if( rcnts[index].mode & RcCountToTarget )
        {
            count  = psxRegs.cycle;
            count -= rcnts[index].cycleStart;
            if (rcnts[index].rate > 1)
                count /= rcnts[index].rate;
            count -= rcnts[index].target;
        }
        else
        {
            count = _psxRcntRcount( index );
        }

        _psxRcntWcount( index, count );

        if( rcnts[index].mode & RcIrqOnTarget )
        {
            if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
            {
                verboseLog( 3, "[RCNT %i] irq: %x\n", index, count );
                setIrq( rcnts[index].irq );
                rcnts[index].irqState = 1;
            }
        }

        rcnts[index].mode |= RcCountEqTarget;
    }
    else if( rcnts[index].counterState == CountToOverflow )
    {
        count  = psxRegs.cycle;
        count -= rcnts[index].cycleStart;
        if (rcnts[index].rate > 1)
            count /= rcnts[index].rate;
        count -= 0xffff;

        _psxRcntWcount( index, count );

        if( rcnts[index].mode & RcIrqOnOverflow )
        {
            if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
            {
                verboseLog( 3, "[RCNT %i] irq: %x\n", index, count );
                setIrq( rcnts[index].irq );
                rcnts[index].irqState = 1;
            }
        }

        rcnts[index].mode |= RcOverflow;
    }

    rcnts[index].mode |= RcUnknown10;

    psxRcntSet();
}

void psxRcntUpdate()
{
    u32 cycle;

    cycle = psxRegs.cycle;

    // rcnt 0.
    if( cycle - rcnts[0].cycleStart >= rcnts[0].cycle )
    {
        psxRcntReset( 0 );
    }

    // rcnt 1.
    if( cycle - rcnts[1].cycleStart >= rcnts[1].cycle )
    {
        psxRcntReset( 1 );
    }

    // rcnt 2.
    if( cycle - rcnts[2].cycleStart >= rcnts[2].cycle )
    {
        psxRcntReset( 2 );
    }

    // rcnt base.
    if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle )
    {
        u32 leftover_cycles = cycle - rcnts[3].cycleStart - rcnts[3].cycle;
        u32 next_vsync, next_lace;

        spuSyncCount += hsync_steps;
        hSyncCount += hsync_steps;

        // Update spu.
        if( spuSyncCount >= SpuUpdInterval[Config.PsxType] )
        {
            spuSyncCount = 0;

            if( SPU_async )
            {
                SPU_async( SpuUpdInterval[Config.PsxType] * rcnts[3].target );
            }
        }
        
        // VSync irq.
        if( hSyncCount == VBlankStart[Config.PsxType] )
        {
            GPU_vBlank( 1, &hSyncCount, &gpu_wants_hcnt );
            
            // For the best times. :D
            //setIrq( 0x01 );
        }
        
        // Update lace. (with InuYasha fix)
        if( hSyncCount >= (Config.VSyncWA ? HSyncTotal[Config.PsxType] / BIAS : HSyncTotal[Config.PsxType]) )
        {
            hSyncCount = 0;

            GPU_vBlank( 0, &hSyncCount, &gpu_wants_hcnt );
            setIrq( 0x01 );

            EmuUpdate();
            GPU_updateLace();
        }

        // Schedule next call, in hsyncs
        hsync_steps = SpuUpdInterval[Config.PsxType] - spuSyncCount;
        next_vsync = VBlankStart[Config.PsxType] - hSyncCount; // ok to overflow
        next_lace = HSyncTotal[Config.PsxType] - hSyncCount;
        if( next_vsync && next_vsync < hsync_steps )
            hsync_steps = next_vsync;
        if( next_lace && next_lace < hsync_steps )
            hsync_steps = next_lace;
        if( gpu_wants_hcnt )
            hsync_steps = 1;

        rcnts[3].cycleStart = cycle - leftover_cycles;
        if (Config.PsxType)
                // 20.12 precision, clk / 50 / 313 ~= 2164.14
                base_cycle += hsync_steps * 8864320;
        else
                // clk / 60 / 263 ~= 2146.31
                base_cycle += hsync_steps * 8791293;
        rcnts[3].cycle = base_cycle >> 12;
        base_cycle &= 0xfff;
        psxRcntSet();
    }

#ifndef NDEBUG
    DebugVSync();
#endif
}

/******************************************************************************/

void psxRcntWcount( u32 index, u32 value )
{
    verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value );

    _psxRcntWcount( index, value );
    psxRcntSet();
}

void psxRcntWmode( u32 index, u32 value )
{
    verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value );

    rcnts[index].mode = value;
    rcnts[index].irqState = 0;

    switch( index )
    {
        case 0:
            if( value & Rc0PixelClock )
            {
                rcnts[index].rate = 5;
            }
            else
            {
                rcnts[index].rate = 1;
            }
        break;
        case 1:
            if( value & Rc1HSyncClock )
            {
                rcnts[index].rate = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
            }
            else
            {
                rcnts[index].rate = 1;
            }
        break;
        case 2:
            if( value & Rc2OneEighthClock )
            {
                rcnts[index].rate = 8;
            }
            else
            {
                rcnts[index].rate = 1;
            }

            // TODO: wcount must work.
            if( value & Rc2Disable )
            {
                rcnts[index].rate = 0xffffffff;
            }
        break;
    }

    _psxRcntWcount( index, 0 );
    psxRcntSet();
}

void psxRcntWtarget( u32 index, u32 value )
{
    verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value );

    rcnts[index].target = value;

    _psxRcntWcount( index, _psxRcntRcount( index ) );
    psxRcntSet();
}

/******************************************************************************/

u32 psxRcntRcount( u32 index )
{
    u32 count;

    count = _psxRcntRcount( index );

    // Parasite Eve 2 fix.
    if( Config.RCntFix )
    {
        if( index == 2 )
        {
            if( rcnts[index].counterState == CountToTarget )
            {
                count /= BIAS;
            }
        }
    }

    verboseLog( 2, "[RCNT %i] rcount: %x\n", index, count );

    return count;
}

u32 psxRcntRmode( u32 index )
{
    u16 mode;

    mode = rcnts[index].mode;
    rcnts[index].mode &= 0xe7ff;

    verboseLog( 2, "[RCNT %i] rmode: %x\n", index, mode );

    return mode;
}

u32 psxRcntRtarget( u32 index )
{
    verboseLog( 2, "[RCNT %i] rtarget: %x\n", index, rcnts[index].target );

    return rcnts[index].target;
}

/******************************************************************************/

void psxRcntInit()
{
    s32 i;

    // rcnt 0.
    rcnts[0].rate   = 1;
    rcnts[0].irq    = 0x10;

    // rcnt 1.
    rcnts[1].rate   = 1;
    rcnts[1].irq    = 0x20;

    // rcnt 2.
    rcnts[2].rate   = 1;
    rcnts[2].irq    = 0x40;

    // rcnt base.
    rcnts[3].rate   = 1;
    rcnts[3].mode   = RcCountToTarget;
    rcnts[3].target = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));

    for( i = 0; i < CounterQuantity; ++i )
    {
        _psxRcntWcount( i, 0 );
    }

    hSyncCount = 0;
    spuSyncCount = 0;
    hsync_steps = 1;

    psxRcntSet();
}

/******************************************************************************/

s32 psxRcntFreeze( gzFile f, s32 Mode )
{
    gzfreeze( &rcnts, sizeof(rcnts) );
    gzfreeze( &hSyncCount, sizeof(hSyncCount) );
    gzfreeze( &spuSyncCount, sizeof(spuSyncCount) );
    gzfreeze( &psxNextCounter, sizeof(psxNextCounter) );
    gzfreeze( &psxNextsCounter, sizeof(psxNextsCounter) );

    if (Mode == 0)
        hsync_steps = (psxRegs.cycle - rcnts[3].cycleStart) / rcnts[3].target;

    base_cycle = 0;

    return 0;
}

/******************************************************************************/
Commit	Line	Data
ef79bbde P	1	/***************************************************************************
	2	* Copyright (C) 2010 by Blade_Arma *
	3	* *
	4	* This program is free software; you can redistribute it and/or modify *
	5	* it under the terms of the GNU General Public License as published by *
	6	* the Free Software Foundation; either version 2 of the License, or *
	7	* (at your option) any later version. *
	8	* *
	9	* This program is distributed in the hope that it will be useful, *
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of *
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
	12	* GNU General Public License for more details. *
	13	* *
	14	* You should have received a copy of the GNU General Public License *
	15	* along with this program; if not, write to the *
	16	* Free Software Foundation, Inc., *
	17	* 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
	18	***************************************************************************/
	19
	20	/*
	21	* Internal PSX counters.
	22	*/
	23
	24	#include "psxcounters.h"
fc8145b7	25	#include "debug.h"
ef79bbde P	26
	27	/******************************************************************************/
	28
ef79bbde P	29	enum
	30	{
	31	Rc0Gate = 0x0001, // 0 not implemented
	32	Rc1Gate = 0x0001, // 0 not implemented
	33	Rc2Disable = 0x0001, // 0 partially implemented
	34	RcUnknown1 = 0x0002, // 1 ?
	35	RcUnknown2 = 0x0004, // 2 ?
	36	RcCountToTarget = 0x0008, // 3
	37	RcIrqOnTarget = 0x0010, // 4
	38	RcIrqOnOverflow = 0x0020, // 5
	39	RcIrqRegenerate = 0x0040, // 6
	40	RcUnknown7 = 0x0080, // 7 ?
	41	Rc0PixelClock = 0x0100, // 8 fake implementation
	42	Rc1HSyncClock = 0x0100, // 8
	43	Rc2Unknown8 = 0x0100, // 8 ?
	44	Rc0Unknown9 = 0x0200, // 9 ?
	45	Rc1Unknown9 = 0x0200, // 9 ?
	46	Rc2OneEighthClock = 0x0200, // 9
	47	RcUnknown10 = 0x0400, // 10 ?
	48	RcCountEqTarget = 0x0800, // 11
	49	RcOverflow = 0x1000, // 12
	50	RcUnknown13 = 0x2000, // 13 ? (always zero)
	51	RcUnknown14 = 0x4000, // 14 ? (always zero)
	52	RcUnknown15 = 0x8000, // 15 ? (always zero)
	53	};
	54
	55	#define CounterQuantity ( 4 )
	56	//static const u32 CounterQuantity = 4;
	57
	58	static const u32 CountToOverflow = 0;
	59	static const u32 CountToTarget = 1;
	60
	61	static const u32 FrameRate[] = { 60, 50 };
	62	static const u32 VBlankStart[] = { 240, 256 };
aecf98c5	63	static const u32 HSyncTotal[] = { 263, 313 };
554a2220	64	static const u32 SpuUpdInterval[] = { 32, 32 };
ef79bbde	65
9f7ee52e	66	#define VERBOSE_LEVEL 0
9f7ee52e	67	static const s32 VerboseLevel = VERBOSE_LEVEL;
ef79bbde P	68
	69	/******************************************************************************/
	70
b1be1eee	71	Rcnt rcnts[ CounterQuantity ];
ef79bbde P	72
	73	static u32 hSyncCount = 0;
	74	static u32 spuSyncCount = 0;
61ef5cf4	75	static u32 hsync_steps = 0;
61ef5cf4	76	static u32 gpu_wants_hcnt = 0;
4f55097d	77	static u32 base_cycle = 0;
ef79bbde P	78
	79	u32 psxNextCounter = 0, psxNextsCounter = 0;
	80
	81	/******************************************************************************/
	82
	83	static inline
	84	void setIrq( u32 irq )
	85	{
	86	psxHu32ref(0x1070) \|= SWAPu32(irq);
	87	}
	88
	89	static
9f7ee52e	90	void verboseLog( u32 level, const char *str, ... )
ef79bbde	91	{
9f7ee52e	92	#if VERBOSE_LEVEL > 0
ef79bbde P	93	if( level <= VerboseLevel )
	94	{
	95	va_list va;
	96	char buf[ 4096 ];
	97
	98	va_start( va, str );
	99	vsprintf( buf, str, va );
	100	va_end( va );
	101
ab948f7e	102	printf( "%s", buf );
ef79bbde P	103	fflush( stdout );
ef79bbde P	104	}
9f7ee52e	105	#endif
ef79bbde P	106	}
	107
	108	/******************************************************************************/
	109
	110	static inline
	111	void _psxRcntWcount( u32 index, u32 value )
	112	{
	113	if( value > 0xffff )
	114	{
	115	verboseLog( 1, "[RCNT %i] wcount > 0xffff: %x\n", index, value );
	116	value &= 0xffff;
	117	}
	118
	119	rcnts[index].cycleStart = psxRegs.cycle;
	120	rcnts[index].cycleStart -= value * rcnts[index].rate;
	121
	122	// TODO: <=.
	123	if( value < rcnts[index].target )
	124	{
	125	rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
	126	rcnts[index].counterState = CountToTarget;
	127	}
	128	else
	129	{
	130	rcnts[index].cycle = 0xffff * rcnts[index].rate;
	131	rcnts[index].counterState = CountToOverflow;
	132	}
	133	}
	134
	135	static inline
	136	u32 _psxRcntRcount( u32 index )
	137	{
	138	u32 count;
	139
	140	count = psxRegs.cycle;
	141	count -= rcnts[index].cycleStart;
61ef5cf4	142	if (rcnts[index].rate > 1)
61ef5cf4	143	count /= rcnts[index].rate;
ef79bbde P	144
	145	if( count > 0xffff )
	146	{
	147	verboseLog( 1, "[RCNT %i] rcount > 0xffff: %x\n", index, count );
	148	count &= 0xffff;
	149	}
	150
	151	return count;
	152	}
	153
	154	/******************************************************************************/
	155
	156	static
	157	void psxRcntSet()
	158	{
	159	s32 countToUpdate;
	160	u32 i;
	161
	162	psxNextsCounter = psxRegs.cycle;
	163	psxNextCounter = 0x7fffffff;
	164
	165	for( i = 0; i < CounterQuantity; ++i )
	166	{
	167	countToUpdate = rcnts[i].cycle - (psxNextsCounter - rcnts[i].cycleStart);
	168
	169	if( countToUpdate < 0 )
	170	{
	171	psxNextCounter = 0;
	172	break;
	173	}
	174
	175	if( countToUpdate < (s32)psxNextCounter )
	176	{
	177	psxNextCounter = countToUpdate;
	178	}
	179	}
5b8c000f	180
	181	psxRegs.interrupt \|= (1 << PSXINT_RCNT);
	182	new_dyna_set_event(PSXINT_RCNT, psxNextCounter);
ef79bbde P	183	}
	184
	185	/******************************************************************************/
	186
	187	static
	188	void psxRcntReset( u32 index )
	189	{
	190	u32 count;
	191
	192	if( rcnts[index].counterState == CountToTarget )
	193	{
	194	if( rcnts[index].mode & RcCountToTarget )
	195	{
	196	count = psxRegs.cycle;
	197	count -= rcnts[index].cycleStart;
61ef5cf4	198	if (rcnts[index].rate > 1)
61ef5cf4	199	count /= rcnts[index].rate;
ef79bbde P	200	count -= rcnts[index].target;
	201	}
	202	else
	203	{
	204	count = _psxRcntRcount( index );
	205	}
	206
	207	_psxRcntWcount( index, count );
	208
	209	if( rcnts[index].mode & RcIrqOnTarget )
	210	{
	211	if( (rcnts[index].mode & RcIrqRegenerate) \|\| (!rcnts[index].irqState) )
	212	{
	213	verboseLog( 3, "[RCNT %i] irq: %x\n", index, count );
	214	setIrq( rcnts[index].irq );
	215	rcnts[index].irqState = 1;
	216	}
	217	}
	218
	219	rcnts[index].mode \|= RcCountEqTarget;
	220	}
	221	else if( rcnts[index].counterState == CountToOverflow )
	222	{
	223	count = psxRegs.cycle;
	224	count -= rcnts[index].cycleStart;
61ef5cf4	225	if (rcnts[index].rate > 1)
61ef5cf4	226	count /= rcnts[index].rate;
ef79bbde P	227	count -= 0xffff;
	228
	229	_psxRcntWcount( index, count );
	230
	231	if( rcnts[index].mode & RcIrqOnOverflow )
	232	{
	233	if( (rcnts[index].mode & RcIrqRegenerate) \|\| (!rcnts[index].irqState) )
	234	{
	235	verboseLog( 3, "[RCNT %i] irq: %x\n", index, count );
	236	setIrq( rcnts[index].irq );
	237	rcnts[index].irqState = 1;
	238	}
	239	}
	240
	241	rcnts[index].mode \|= RcOverflow;
	242	}
	243
	244	rcnts[index].mode \|= RcUnknown10;
	245
	246	psxRcntSet();
	247	}
	248
	249	void psxRcntUpdate()
	250	{
	251	u32 cycle;
	252
	253	cycle = psxRegs.cycle;
	254
	255	// rcnt 0.
	256	if( cycle - rcnts[0].cycleStart >= rcnts[0].cycle )
	257	{
	258	psxRcntReset( 0 );
	259	}
	260
	261	// rcnt 1.
	262	if( cycle - rcnts[1].cycleStart >= rcnts[1].cycle )
	263	{
	264	psxRcntReset( 1 );
	265	}
	266
	267	// rcnt 2.
	268	if( cycle - rcnts[2].cycleStart >= rcnts[2].cycle )
	269	{
	270	psxRcntReset( 2 );
	271	}
	272
	273	// rcnt base.
	274	if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle )
	275	{
61ef5cf4	276	u32 leftover_cycles = cycle - rcnts[3].cycleStart - rcnts[3].cycle;
61ef5cf4	277	u32 next_vsync, next_lace;
ef79bbde	278
61ef5cf4	279	spuSyncCount += hsync_steps;
61ef5cf4	280	hSyncCount += hsync_steps;
ef79bbde P	281
	282	// Update spu.
	283	if( spuSyncCount >= SpuUpdInterval[Config.PsxType] )
	284	{
	285	spuSyncCount = 0;
	286
	287	if( SPU_async )
	288	{
	289	SPU_async( SpuUpdInterval[Config.PsxType] * rcnts[3].target );
	290	}
	291	}
	292
	293	// VSync irq.
	294	if( hSyncCount == VBlankStart[Config.PsxType] )
	295	{
61ef5cf4	296	GPU_vBlank( 1, &hSyncCount, &gpu_wants_hcnt );
ef79bbde P	297
	298	// For the best times. :D
	299	//setIrq( 0x01 );
	300	}
	301
	302	// Update lace. (with InuYasha fix)
	303	if( hSyncCount >= (Config.VSyncWA ? HSyncTotal[Config.PsxType] / BIAS : HSyncTotal[Config.PsxType]) )
	304	{
	305	hSyncCount = 0;
	306
61ef5cf4	307	GPU_vBlank( 0, &hSyncCount, &gpu_wants_hcnt );
ef79bbde P	308	setIrq( 0x01 );
ef79bbde P	309
ef79bbde	310	EmuUpdate();
cefe86b7	311	GPU_updateLace();
ef79bbde	312	}
61ef5cf4	313
	314	// Schedule next call, in hsyncs
	315	hsync_steps = SpuUpdInterval[Config.PsxType] - spuSyncCount;
	316	next_vsync = VBlankStart[Config.PsxType] - hSyncCount; // ok to overflow
	317	next_lace = HSyncTotal[Config.PsxType] - hSyncCount;
	318	if( next_vsync && next_vsync < hsync_steps )
	319	hsync_steps = next_vsync;
	320	if( next_lace && next_lace < hsync_steps )
	321	hsync_steps = next_lace;
	322	if( gpu_wants_hcnt )
	323	hsync_steps = 1;
	324
	325	rcnts[3].cycleStart = cycle - leftover_cycles;
4f55097d	326	if (Config.PsxType)
	327	// 20.12 precision, clk / 50 / 313 ~= 2164.14
	328	base_cycle += hsync_steps * 8864320;
	329	else
	330	// clk / 60 / 263 ~= 2146.31
	331	base_cycle += hsync_steps * 8791293;
	332	rcnts[3].cycle = base_cycle >> 12;
	333	base_cycle &= 0xfff;
61ef5cf4	334	psxRcntSet();
ef79bbde P	335	}
ef79bbde P	336
61ef5cf4	337	#ifndef NDEBUG
ef79bbde	338	DebugVSync();
61ef5cf4	339	#endif
ef79bbde P	340	}
	341
	342	/******************************************************************************/
	343
	344	void psxRcntWcount( u32 index, u32 value )
	345	{
	346	verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value );
	347
ef79bbde P	348	_psxRcntWcount( index, value );
	349	psxRcntSet();
	350	}
	351
	352	void psxRcntWmode( u32 index, u32 value )
	353	{
	354	verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value );
	355
ef79bbde P	356	rcnts[index].mode = value;
	357	rcnts[index].irqState = 0;
	358
	359	switch( index )
	360	{
	361	case 0:
	362	if( value & Rc0PixelClock )
	363	{
	364	rcnts[index].rate = 5;
	365	}
	366	else
	367	{
	368	rcnts[index].rate = 1;
	369	}
	370	break;
	371	case 1:
	372	if( value & Rc1HSyncClock )
	373	{
	374	rcnts[index].rate = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
	375	}
	376	else
	377	{
	378	rcnts[index].rate = 1;
	379	}
	380	break;
	381	case 2:
	382	if( value & Rc2OneEighthClock )
	383	{
	384	rcnts[index].rate = 8;
	385	}
	386	else
	387	{
	388	rcnts[index].rate = 1;
	389	}
	390
	391	// TODO: wcount must work.
	392	if( value & Rc2Disable )
	393	{
	394	rcnts[index].rate = 0xffffffff;
	395	}
	396	break;
	397	}
	398
	399	_psxRcntWcount( index, 0 );
	400	psxRcntSet();
	401	}
	402
	403	void psxRcntWtarget( u32 index, u32 value )
	404	{
	405	verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value );
	406
ef79bbde P	407	rcnts[index].target = value;
	408
	409	_psxRcntWcount( index, _psxRcntRcount( index ) );
	410	psxRcntSet();
	411	}
	412
	413	/******************************************************************************/
	414
	415	u32 psxRcntRcount( u32 index )
	416	{
	417	u32 count;
	418
ef79bbde P	419	count = _psxRcntRcount( index );
	420
	421	// Parasite Eve 2 fix.
	422	if( Config.RCntFix )
	423	{
	424	if( index == 2 )
	425	{
	426	if( rcnts[index].counterState == CountToTarget )
	427	{
	428	count /= BIAS;
	429	}
	430	}
	431	}
	432
	433	verboseLog( 2, "[RCNT %i] rcount: %x\n", index, count );
	434
	435	return count;
	436	}
	437
	438	u32 psxRcntRmode( u32 index )
	439	{
	440	u16 mode;
	441
ef79bbde P	442	mode = rcnts[index].mode;
	443	rcnts[index].mode &= 0xe7ff;
	444
	445	verboseLog( 2, "[RCNT %i] rmode: %x\n", index, mode );
	446
	447	return mode;
	448	}
	449
	450	u32 psxRcntRtarget( u32 index )
	451	{
	452	verboseLog( 2, "[RCNT %i] rtarget: %x\n", index, rcnts[index].target );
	453
	454	return rcnts[index].target;
	455	}
	456
	457	/******************************************************************************/
	458
	459	void psxRcntInit()
	460	{
	461	s32 i;
	462
	463	// rcnt 0.
	464	rcnts[0].rate = 1;
	465	rcnts[0].irq = 0x10;
	466
	467	// rcnt 1.
	468	rcnts[1].rate = 1;
	469	rcnts[1].irq = 0x20;
	470
	471	// rcnt 2.
	472	rcnts[2].rate = 1;
	473	rcnts[2].irq = 0x40;
	474
	475	// rcnt base.
	476	rcnts[3].rate = 1;
	477	rcnts[3].mode = RcCountToTarget;
	478	rcnts[3].target = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
	479
	480	for( i = 0; i < CounterQuantity; ++i )
	481	{
	482	_psxRcntWcount( i, 0 );
	483	}
	484
c62b43c9	485	hSyncCount = 0;
c62b43c9	486	spuSyncCount = 0;
61ef5cf4	487	hsync_steps = 1;
c62b43c9	488
ef79bbde P	489	psxRcntSet();
	490	}
	491
	492	/******************************************************************************/
	493
	494	s32 psxRcntFreeze( gzFile f, s32 Mode )
	495	{
	496	gzfreeze( &rcnts, sizeof(rcnts) );
	497	gzfreeze( &hSyncCount, sizeof(hSyncCount) );
	498	gzfreeze( &spuSyncCount, sizeof(spuSyncCount) );
	499	gzfreeze( &psxNextCounter, sizeof(psxNextCounter) );
	500	gzfreeze( &psxNextsCounter, sizeof(psxNextsCounter) );
	501
61ef5cf4	502	if (Mode == 0)
	503	hsync_steps = (psxRegs.cycle - rcnts[3].cycleStart) / rcnts[3].target;
	504
4f55097d	505	base_cycle = 0;
4f55097d	506
ef79bbde P	507	return 0;
	508	}
	509
	510	/******************************************************************************/