[pcsx_rearmed.git] / libpcsxcore / psxcounters.c

/***************************************************************************
 *   Copyright (C) 2010 by Blade_Arma                                      *
 *                                                                         *
 *   This program is free software; you can redistribute it and/or modify  *
 *   it under the terms of the GNU General Public License as published by  *
 *   the Free Software Foundation; either version 2 of the License, or     *
 *   (at your option) any later version.                                   *
 *                                                                         *
 *   This program is distributed in the hope that it will be useful,       *
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
 *   GNU General Public License for more details.                          *
 *                                                                         *
 *   You should have received a copy of the GNU General Public License     *
 *   along with this program; if not, write to the                         *
 *   Free Software Foundation, Inc.,                                       *
 *   51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA.           *
 ***************************************************************************/

/*
 * Internal PSX counters.
 */

#include "psxcounters.h"
#include "gpu.h"
#include "debug.h"

/******************************************************************************/

enum
{
    Rc0Gate           = 0x0001, // 0    not implemented
    Rc1Gate           = 0x0001, // 0    not implemented
    Rc2Disable        = 0x0001, // 0    partially implemented
    RcUnknown1        = 0x0002, // 1    ?
    RcUnknown2        = 0x0004, // 2    ?
    RcCountToTarget   = 0x0008, // 3
    RcIrqOnTarget     = 0x0010, // 4
    RcIrqOnOverflow   = 0x0020, // 5
    RcIrqRegenerate   = 0x0040, // 6
    RcUnknown7        = 0x0080, // 7    ?
    Rc0PixelClock     = 0x0100, // 8    fake implementation
    Rc1HSyncClock     = 0x0100, // 8
    Rc2Unknown8       = 0x0100, // 8    ?
    Rc0Unknown9       = 0x0200, // 9    ?
    Rc1Unknown9       = 0x0200, // 9    ?
    Rc2OneEighthClock = 0x0200, // 9
    RcUnknown10       = 0x0400, // 10   ?
    RcCountEqTarget   = 0x0800, // 11
    RcOverflow        = 0x1000, // 12
    RcUnknown13       = 0x2000, // 13   ? (always zero)
    RcUnknown14       = 0x4000, // 14   ? (always zero)
    RcUnknown15       = 0x8000, // 15   ? (always zero)
};

#define CounterQuantity           ( 4 )
//static const u32 CounterQuantity  = 4;

static const u32 CountToOverflow  = 0;
static const u32 CountToTarget    = 1;

static const u32 FrameRate[]      = { 60, 50 };
static const u32 HSyncTotal[]     = { 263, 313 };
static const u32 SpuUpdInterval[] = { 32, 32 };
#define VBlankStart 240

#define VERBOSE_LEVEL 0
static const s32 VerboseLevel     = VERBOSE_LEVEL;

/******************************************************************************/

Rcnt rcnts[ CounterQuantity ];

u32 hSyncCount = 0;
u32 frame_counter = 0;
static u32 spuSyncCount = 0;
static u32 hsync_steps = 0;
static u32 base_cycle = 0;

u32 psxNextCounter = 0, psxNextsCounter = 0;

/******************************************************************************/

static inline
void setIrq( u32 irq )
{
    psxHu32ref(0x1070) |= SWAPu32(irq);
}

static
void verboseLog( u32 level, const char *str, ... )
{
#if VERBOSE_LEVEL > 0
    if( level <= VerboseLevel )
    {
        va_list va;
        char buf[ 4096 ];

        va_start( va, str );
        vsprintf( buf, str, va );
        va_end( va );

        printf( "%s", buf );
        fflush( stdout );
    }
#endif
}

/******************************************************************************/

static inline
void _psxRcntWcount( u32 index, u32 value )
{
    if( value > 0xffff )
    {
        verboseLog( 1, "[RCNT %i] wcount > 0xffff: %x\n", index, value );
        value &= 0xffff;
    }

    rcnts[index].cycleStart  = psxRegs.cycle;
    rcnts[index].cycleStart -= value * rcnts[index].rate;

    // TODO: <=.
    if( value < rcnts[index].target )
    {
        rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
        rcnts[index].counterState = CountToTarget;
    }
    else
    {
        rcnts[index].cycle = 0x10000 * rcnts[index].rate;
        rcnts[index].counterState = CountToOverflow;
    }
}

static inline
u32 _psxRcntRcount( u32 index )
{
    u32 count;

    count  = psxRegs.cycle;
    count -= rcnts[index].cycleStart;
    if (rcnts[index].rate > 1)
        count /= rcnts[index].rate;

    if( count > 0x10000 )
    {
        verboseLog( 1, "[RCNT %i] rcount > 0x10000: %x\n", index, count );
    }
    count &= 0xffff;

    return count;
}

static
void _psxRcntWmode( u32 index, u32 value )
{
    rcnts[index].mode = value;

    switch( index )
    {
        case 0:
            if( value & Rc0PixelClock )
            {
                rcnts[index].rate = 5;
            }
            else
            {
                rcnts[index].rate = 1;
            }
        break;
        case 1:
            if( value & Rc1HSyncClock )
            {
                rcnts[index].rate = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
            }
            else
            {
                rcnts[index].rate = 1;
            }
        break;
        case 2:
            if( value & Rc2OneEighthClock )
            {
                rcnts[index].rate = 8;
            }
            else
            {
                rcnts[index].rate = 1;
            }

            // TODO: wcount must work.
            if( value & Rc2Disable )
            {
                rcnts[index].rate = 0xffffffff;
            }
        break;
    }
}

/******************************************************************************/

static
void psxRcntSet()
{
    s32 countToUpdate;
    u32 i;

    psxNextsCounter = psxRegs.cycle;
    psxNextCounter  = 0x7fffffff;

    for( i = 0; i < CounterQuantity; ++i )
    {
        countToUpdate = rcnts[i].cycle - (psxNextsCounter - rcnts[i].cycleStart);

        if( countToUpdate < 0 )
        {
            psxNextCounter = 0;
            break;
        }

        if( countToUpdate < (s32)psxNextCounter )
        {
            psxNextCounter = countToUpdate;
        }
    }

    psxRegs.interrupt |= (1 << PSXINT_RCNT);
    new_dyna_set_event(PSXINT_RCNT, psxNextCounter);
}

/******************************************************************************/

static
void psxRcntReset( u32 index )
{
    u32 rcycles;

    rcnts[index].mode |= RcUnknown10;

    if( rcnts[index].counterState == CountToTarget )
    {
        rcycles = psxRegs.cycle - rcnts[index].cycleStart;
        if( rcnts[index].mode & RcCountToTarget )
        {
            rcycles -= rcnts[index].target * rcnts[index].rate;
            rcnts[index].cycleStart = psxRegs.cycle - rcycles;
        }
        else
        {
            rcnts[index].cycle = 0x10000 * rcnts[index].rate;
            rcnts[index].counterState = CountToOverflow;
        }

        if( rcnts[index].mode & RcIrqOnTarget )
        {
            if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
            {
                verboseLog( 3, "[RCNT %i] irq\n", index );
                setIrq( rcnts[index].irq );
                rcnts[index].irqState = 1;
            }
        }

        rcnts[index].mode |= RcCountEqTarget;

        if( rcycles < 0x10000 * rcnts[index].rate )
            return;
    }

    if( rcnts[index].counterState == CountToOverflow )
    {
        rcycles = psxRegs.cycle - rcnts[index].cycleStart;
        rcycles -= 0x10000 * rcnts[index].rate;

        rcnts[index].cycleStart = psxRegs.cycle - rcycles;

        if( rcycles < rcnts[index].target * rcnts[index].rate )
        {
            rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
            rcnts[index].counterState = CountToTarget;
        }

        if( rcnts[index].mode & RcIrqOnOverflow )
        {
            if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
            {
                verboseLog( 3, "[RCNT %i] irq\n", index );
                setIrq( rcnts[index].irq );
                rcnts[index].irqState = 1;
            }
        }

        rcnts[index].mode |= RcOverflow;
    }
}

void psxRcntUpdate()
{
    u32 cycle;

    cycle = psxRegs.cycle;

    // rcnt 0.
    if( cycle - rcnts[0].cycleStart >= rcnts[0].cycle )
    {
        psxRcntReset( 0 );
    }

    // rcnt 1.
    if( cycle - rcnts[1].cycleStart >= rcnts[1].cycle )
    {
        psxRcntReset( 1 );
    }

    // rcnt 2.
    if( cycle - rcnts[2].cycleStart >= rcnts[2].cycle )
    {
        psxRcntReset( 2 );
    }

    // rcnt base.
    if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle )
    {
        u32 leftover_cycles = cycle - rcnts[3].cycleStart - rcnts[3].cycle;
        u32 next_vsync, next_lace;

        spuSyncCount += hsync_steps;
        hSyncCount += hsync_steps;

        // Update spu.
        if( spuSyncCount >= SpuUpdInterval[Config.PsxType] )
        {
            spuSyncCount = 0;

            if( SPU_async )
            {
                SPU_async( SpuUpdInterval[Config.PsxType] * rcnts[3].target );
            }
        }
        
        // VSync irq.
        if( hSyncCount == VBlankStart )
        {
            HW_GPU_STATUS &= ~PSXGPU_LCF;
            GPU_vBlank( 1, 0 );
            setIrq( 0x01 );

            EmuUpdate();
            GPU_updateLace();
        }
        
        // Update lace. (with InuYasha fix)
        if( hSyncCount >= (Config.VSyncWA ? HSyncTotal[Config.PsxType] / BIAS : HSyncTotal[Config.PsxType]) )
        {
            hSyncCount = 0;
            frame_counter++;

            gpuSyncPluginSR();
            if( (HW_GPU_STATUS & PSXGPU_ILACE_BITS) == PSXGPU_ILACE_BITS )
                HW_GPU_STATUS |= frame_counter << 31;
            GPU_vBlank( 0, HW_GPU_STATUS >> 31 );
        }

        // Schedule next call, in hsyncs
        hsync_steps = SpuUpdInterval[Config.PsxType] - spuSyncCount;
        next_vsync = VBlankStart - hSyncCount; // ok to overflow
        next_lace = HSyncTotal[Config.PsxType] - hSyncCount;
        if( next_vsync && next_vsync < hsync_steps )
            hsync_steps = next_vsync;
        if( next_lace && next_lace < hsync_steps )
            hsync_steps = next_lace;

        rcnts[3].cycleStart = cycle - leftover_cycles;
        if (Config.PsxType)
                // 20.12 precision, clk / 50 / 313 ~= 2164.14
                base_cycle += hsync_steps * 8864320;
        else
                // clk / 60 / 263 ~= 2146.31
                base_cycle += hsync_steps * 8791293;
        rcnts[3].cycle = base_cycle >> 12;
        base_cycle &= 0xfff;
    }

    psxRcntSet();

#ifndef NDEBUG
    DebugVSync();
#endif
}

/******************************************************************************/

void psxRcntWcount( u32 index, u32 value )
{
    verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value );

    _psxRcntWcount( index, value );
    psxRcntSet();
}

void psxRcntWmode( u32 index, u32 value )
{
    verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value );

    _psxRcntWmode( index, value );
    _psxRcntWcount( index, 0 );

    rcnts[index].irqState = 0;
    psxRcntSet();
}

void psxRcntWtarget( u32 index, u32 value )
{
    verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value );

    rcnts[index].target = value;

    _psxRcntWcount( index, _psxRcntRcount( index ) );
    psxRcntSet();
}

/******************************************************************************/

u32 psxRcntRcount( u32 index )
{
    u32 count;

    count = _psxRcntRcount( index );

    // Parasite Eve 2 fix.
    if( Config.RCntFix )
    {
        if( index == 2 )
        {
            if( rcnts[index].counterState == CountToTarget )
            {
                count /= BIAS;
            }
        }
    }

    verboseLog( 2, "[RCNT %i] rcount: %x\n", index, count );

    return count;
}

u32 psxRcntRmode( u32 index )
{
    u16 mode;

    mode = rcnts[index].mode;
    rcnts[index].mode &= 0xe7ff;

    verboseLog( 2, "[RCNT %i] rmode: %x\n", index, mode );

    return mode;
}

u32 psxRcntRtarget( u32 index )
{
    verboseLog( 2, "[RCNT %i] rtarget: %x\n", index, rcnts[index].target );

    return rcnts[index].target;
}

/******************************************************************************/

void psxRcntInit()
{
    s32 i;

    // rcnt 0.
    rcnts[0].rate   = 1;
    rcnts[0].irq    = 0x10;

    // rcnt 1.
    rcnts[1].rate   = 1;
    rcnts[1].irq    = 0x20;

    // rcnt 2.
    rcnts[2].rate   = 1;
    rcnts[2].irq    = 0x40;

    // rcnt base.
    rcnts[3].rate   = 1;
    rcnts[3].mode   = RcCountToTarget;
    rcnts[3].target = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));

    for( i = 0; i < CounterQuantity; ++i )
    {
        _psxRcntWcount( i, 0 );
    }

    hSyncCount = 0;
    spuSyncCount = 0;
    hsync_steps = 1;

    psxRcntSet();
}

/******************************************************************************/

s32 psxRcntFreeze( void *f, s32 Mode )
{
    u32 count;
    s32 i;

    gzfreeze( &rcnts, sizeof(rcnts) );
    gzfreeze( &hSyncCount, sizeof(hSyncCount) );
    gzfreeze( &spuSyncCount, sizeof(spuSyncCount) );
    gzfreeze( &psxNextCounter, sizeof(psxNextCounter) );
    gzfreeze( &psxNextsCounter, sizeof(psxNextsCounter) );

    if (Mode == 0)
    {
        // don't trust things from a savestate
        for( i = 0; i < CounterQuantity; ++i )
        {
            _psxRcntWmode( i, rcnts[i].mode );
            count = (psxRegs.cycle - rcnts[i].cycleStart) / rcnts[i].rate;
            _psxRcntWcount( i, count );
        }
        hsync_steps = (psxRegs.cycle - rcnts[3].cycleStart) / rcnts[3].target;
        psxRcntSet();

        base_cycle = 0;
    }

    return 0;
}

/******************************************************************************/
Commit	Line	Data
ef79bbde P	1	/***************************************************************************
	2	* Copyright (C) 2010 by Blade_Arma *
	3	* *
	4	* This program is free software; you can redistribute it and/or modify *
	5	* it under the terms of the GNU General Public License as published by *
	6	* the Free Software Foundation; either version 2 of the License, or *
	7	* (at your option) any later version. *
	8	* *
	9	* This program is distributed in the hope that it will be useful, *
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of *
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
	12	* GNU General Public License for more details. *
	13	* *
	14	* You should have received a copy of the GNU General Public License *
	15	* along with this program; if not, write to the *
	16	* Free Software Foundation, Inc., *
	17	* 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
	18	***************************************************************************/
	19
	20	/*
	21	* Internal PSX counters.
	22	*/
	23
	24	#include "psxcounters.h"
ddbaf678	25	#include "gpu.h"
fc8145b7	26	#include "debug.h"
ef79bbde P	27
	28	/******************************************************************************/
	29
ef79bbde P	30	enum
	31	{
	32	Rc0Gate = 0x0001, // 0 not implemented
	33	Rc1Gate = 0x0001, // 0 not implemented
	34	Rc2Disable = 0x0001, // 0 partially implemented
	35	RcUnknown1 = 0x0002, // 1 ?
	36	RcUnknown2 = 0x0004, // 2 ?
	37	RcCountToTarget = 0x0008, // 3
	38	RcIrqOnTarget = 0x0010, // 4
	39	RcIrqOnOverflow = 0x0020, // 5
	40	RcIrqRegenerate = 0x0040, // 6
	41	RcUnknown7 = 0x0080, // 7 ?
	42	Rc0PixelClock = 0x0100, // 8 fake implementation
	43	Rc1HSyncClock = 0x0100, // 8
	44	Rc2Unknown8 = 0x0100, // 8 ?
	45	Rc0Unknown9 = 0x0200, // 9 ?
	46	Rc1Unknown9 = 0x0200, // 9 ?
	47	Rc2OneEighthClock = 0x0200, // 9
	48	RcUnknown10 = 0x0400, // 10 ?
	49	RcCountEqTarget = 0x0800, // 11
	50	RcOverflow = 0x1000, // 12
	51	RcUnknown13 = 0x2000, // 13 ? (always zero)
	52	RcUnknown14 = 0x4000, // 14 ? (always zero)
	53	RcUnknown15 = 0x8000, // 15 ? (always zero)
	54	};
	55
	56	#define CounterQuantity ( 4 )
	57	//static const u32 CounterQuantity = 4;
	58
	59	static const u32 CountToOverflow = 0;
	60	static const u32 CountToTarget = 1;
	61
	62	static const u32 FrameRate[] = { 60, 50 };
aecf98c5	63	static const u32 HSyncTotal[] = { 263, 313 };
554a2220	64	static const u32 SpuUpdInterval[] = { 32, 32 };
0486fdc9	65	#define VBlankStart 240
ef79bbde	66
9f7ee52e	67	#define VERBOSE_LEVEL 0
9f7ee52e	68	static const s32 VerboseLevel = VERBOSE_LEVEL;
ef79bbde P	69
	70	/******************************************************************************/
	71
b1be1eee	72	Rcnt rcnts[ CounterQuantity ];
ef79bbde	73
24de2dd4	74	u32 hSyncCount = 0;
24de2dd4	75	u32 frame_counter = 0;
ef79bbde	76	static u32 spuSyncCount = 0;
61ef5cf4	77	static u32 hsync_steps = 0;
4f55097d	78	static u32 base_cycle = 0;
ef79bbde P	79
	80	u32 psxNextCounter = 0, psxNextsCounter = 0;
	81
	82	/******************************************************************************/
	83
	84	static inline
	85	void setIrq( u32 irq )
	86	{
	87	psxHu32ref(0x1070) \|= SWAPu32(irq);
	88	}
	89
	90	static
9f7ee52e	91	void verboseLog( u32 level, const char *str, ... )
ef79bbde	92	{
9f7ee52e	93	#if VERBOSE_LEVEL > 0
ef79bbde P	94	if( level <= VerboseLevel )
	95	{
	96	va_list va;
	97	char buf[ 4096 ];
	98
	99	va_start( va, str );
	100	vsprintf( buf, str, va );
	101	va_end( va );
	102
ab948f7e	103	printf( "%s", buf );
ef79bbde P	104	fflush( stdout );
ef79bbde P	105	}
9f7ee52e	106	#endif
ef79bbde P	107	}
	108
	109	/******************************************************************************/
	110
	111	static inline
	112	void _psxRcntWcount( u32 index, u32 value )
	113	{
	114	if( value > 0xffff )
	115	{
	116	verboseLog( 1, "[RCNT %i] wcount > 0xffff: %x\n", index, value );
	117	value &= 0xffff;
	118	}
	119
	120	rcnts[index].cycleStart = psxRegs.cycle;
	121	rcnts[index].cycleStart -= value * rcnts[index].rate;
	122
	123	// TODO: <=.
	124	if( value < rcnts[index].target )
	125	{
	126	rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
	127	rcnts[index].counterState = CountToTarget;
	128	}
	129	else
	130	{
8ca6b0a6	131	rcnts[index].cycle = 0x10000 * rcnts[index].rate;
ef79bbde P	132	rcnts[index].counterState = CountToOverflow;
	133	}
	134	}
	135
	136	static inline
	137	u32 _psxRcntRcount( u32 index )
	138	{
	139	u32 count;
	140
	141	count = psxRegs.cycle;
	142	count -= rcnts[index].cycleStart;
61ef5cf4	143	if (rcnts[index].rate > 1)
61ef5cf4	144	count /= rcnts[index].rate;
ef79bbde	145
8ca6b0a6	146	if( count > 0x10000 )
ef79bbde	147	{
8ca6b0a6	148	verboseLog( 1, "[RCNT %i] rcount > 0x10000: %x\n", index, count );
ef79bbde	149	}
8ca6b0a6	150	count &= 0xffff;
ef79bbde P	151
	152	return count;
	153	}
	154
a29f182f	155	static
	156	void _psxRcntWmode( u32 index, u32 value )
	157	{
	158	rcnts[index].mode = value;
	159
	160	switch( index )
	161	{
	162	case 0:
	163	if( value & Rc0PixelClock )
	164	{
	165	rcnts[index].rate = 5;
	166	}
	167	else
	168	{
	169	rcnts[index].rate = 1;
	170	}
	171	break;
	172	case 1:
	173	if( value & Rc1HSyncClock )
	174	{
	175	rcnts[index].rate = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
	176	}
	177	else
	178	{
	179	rcnts[index].rate = 1;
	180	}
	181	break;
	182	case 2:
	183	if( value & Rc2OneEighthClock )
	184	{
	185	rcnts[index].rate = 8;
	186	}
	187	else
	188	{
	189	rcnts[index].rate = 1;
	190	}
	191
	192	// TODO: wcount must work.
	193	if( value & Rc2Disable )
	194	{
	195	rcnts[index].rate = 0xffffffff;
	196	}
	197	break;
	198	}
	199	}
	200
ef79bbde P	201	/******************************************************************************/
	202
	203	static
	204	void psxRcntSet()
	205	{
	206	s32 countToUpdate;
	207	u32 i;
	208
	209	psxNextsCounter = psxRegs.cycle;
	210	psxNextCounter = 0x7fffffff;
	211
	212	for( i = 0; i < CounterQuantity; ++i )
	213	{
	214	countToUpdate = rcnts[i].cycle - (psxNextsCounter - rcnts[i].cycleStart);
	215
	216	if( countToUpdate < 0 )
	217	{
	218	psxNextCounter = 0;
	219	break;
	220	}
	221
	222	if( countToUpdate < (s32)psxNextCounter )
	223	{
	224	psxNextCounter = countToUpdate;
	225	}
	226	}
5b8c000f	227
	228	psxRegs.interrupt \|= (1 << PSXINT_RCNT);
	229	new_dyna_set_event(PSXINT_RCNT, psxNextCounter);
ef79bbde P	230	}
	231
	232	/******************************************************************************/
	233
	234	static
	235	void psxRcntReset( u32 index )
	236	{
8ca6b0a6	237	u32 rcycles;
ef79bbde	238
53c361f0	239	rcnts[index].mode \|= RcUnknown10;
53c361f0	240
ef79bbde P	241	if( rcnts[index].counterState == CountToTarget )
ef79bbde P	242	{
8ca6b0a6	243	rcycles = psxRegs.cycle - rcnts[index].cycleStart;
ef79bbde	244	if( rcnts[index].mode & RcCountToTarget )
8ca6b0a6	245	{
	246	rcycles -= rcnts[index].target * rcnts[index].rate;
	247	rcnts[index].cycleStart = psxRegs.cycle - rcycles;
	248	}
	249	else
	250	{
	251	rcnts[index].cycle = 0x10000 * rcnts[index].rate;
	252	rcnts[index].counterState = CountToOverflow;
	253	}
ef79bbde P	254
	255	if( rcnts[index].mode & RcIrqOnTarget )
	256	{
	257	if( (rcnts[index].mode & RcIrqRegenerate) \|\| (!rcnts[index].irqState) )
	258	{
8ca6b0a6	259	verboseLog( 3, "[RCNT %i] irq\n", index );
ef79bbde P	260	setIrq( rcnts[index].irq );
	261	rcnts[index].irqState = 1;
	262	}
	263	}
	264
	265	rcnts[index].mode \|= RcCountEqTarget;
53c361f0	266
8ca6b0a6	267	if( rcycles < 0x10000 * rcnts[index].rate )
53c361f0	268	return;
ef79bbde	269	}
53c361f0	270
53c361f0	271	if( rcnts[index].counterState == CountToOverflow )
ef79bbde	272	{
8ca6b0a6	273	rcycles = psxRegs.cycle - rcnts[index].cycleStart;
	274	rcycles -= 0x10000 * rcnts[index].rate;
	275
	276	rcnts[index].cycleStart = psxRegs.cycle - rcycles;
ef79bbde	277
8ca6b0a6	278	if( rcycles < rcnts[index].target * rcnts[index].rate )
	279	{
	280	rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
	281	rcnts[index].counterState = CountToTarget;
	282	}
ef79bbde P	283
	284	if( rcnts[index].mode & RcIrqOnOverflow )
	285	{
	286	if( (rcnts[index].mode & RcIrqRegenerate) \|\| (!rcnts[index].irqState) )
	287	{
8ca6b0a6	288	verboseLog( 3, "[RCNT %i] irq\n", index );
ef79bbde P	289	setIrq( rcnts[index].irq );
	290	rcnts[index].irqState = 1;
	291	}
	292	}
	293
	294	rcnts[index].mode \|= RcOverflow;
	295	}
ef79bbde P	296	}
	297
	298	void psxRcntUpdate()
	299	{
	300	u32 cycle;
	301
	302	cycle = psxRegs.cycle;
	303
	304	// rcnt 0.
	305	if( cycle - rcnts[0].cycleStart >= rcnts[0].cycle )
	306	{
	307	psxRcntReset( 0 );
	308	}
	309
	310	// rcnt 1.
	311	if( cycle - rcnts[1].cycleStart >= rcnts[1].cycle )
	312	{
	313	psxRcntReset( 1 );
	314	}
	315
	316	// rcnt 2.
	317	if( cycle - rcnts[2].cycleStart >= rcnts[2].cycle )
	318	{
	319	psxRcntReset( 2 );
	320	}
	321
	322	// rcnt base.
	323	if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle )
	324	{
61ef5cf4	325	u32 leftover_cycles = cycle - rcnts[3].cycleStart - rcnts[3].cycle;
61ef5cf4	326	u32 next_vsync, next_lace;
ef79bbde	327
61ef5cf4	328	spuSyncCount += hsync_steps;
61ef5cf4	329	hSyncCount += hsync_steps;
ef79bbde P	330
	331	// Update spu.
	332	if( spuSyncCount >= SpuUpdInterval[Config.PsxType] )
	333	{
	334	spuSyncCount = 0;
	335
	336	if( SPU_async )
	337	{
	338	SPU_async( SpuUpdInterval[Config.PsxType] * rcnts[3].target );
	339	}
	340	}
	341
	342	// VSync irq.
0486fdc9	343	if( hSyncCount == VBlankStart )
ef79bbde	344	{
0486fdc9	345	HW_GPU_STATUS &= ~PSXGPU_LCF;
72e5023f	346	GPU_vBlank( 1, 0 );
8bbbd091	347	setIrq( 0x01 );
	348
	349	EmuUpdate();
	350	GPU_updateLace();
ef79bbde P	351	}
	352
	353	// Update lace. (with InuYasha fix)
	354	if( hSyncCount >= (Config.VSyncWA ? HSyncTotal[Config.PsxType] / BIAS : HSyncTotal[Config.PsxType]) )
	355	{
	356	hSyncCount = 0;
ddbaf678	357	frame_counter++;
ef79bbde	358
0486fdc9	359	gpuSyncPluginSR();
0486fdc9	360	if( (HW_GPU_STATUS & PSXGPU_ILACE_BITS) == PSXGPU_ILACE_BITS )
ddbaf678	361	HW_GPU_STATUS \|= frame_counter << 31;
72e5023f	362	GPU_vBlank( 0, HW_GPU_STATUS >> 31 );
ef79bbde	363	}
61ef5cf4	364
	365	// Schedule next call, in hsyncs
	366	hsync_steps = SpuUpdInterval[Config.PsxType] - spuSyncCount;
0486fdc9	367	next_vsync = VBlankStart - hSyncCount; // ok to overflow
61ef5cf4	368	next_lace = HSyncTotal[Config.PsxType] - hSyncCount;
	369	if( next_vsync && next_vsync < hsync_steps )
	370	hsync_steps = next_vsync;
	371	if( next_lace && next_lace < hsync_steps )
	372	hsync_steps = next_lace;
61ef5cf4	373
61ef5cf4	374	rcnts[3].cycleStart = cycle - leftover_cycles;
4f55097d	375	if (Config.PsxType)
	376	// 20.12 precision, clk / 50 / 313 ~= 2164.14
	377	base_cycle += hsync_steps * 8864320;
	378	else
	379	// clk / 60 / 263 ~= 2146.31
	380	base_cycle += hsync_steps * 8791293;
	381	rcnts[3].cycle = base_cycle >> 12;
	382	base_cycle &= 0xfff;
ef79bbde P	383	}
ef79bbde P	384
95df1a04	385	psxRcntSet();
95df1a04	386
61ef5cf4	387	#ifndef NDEBUG
ef79bbde	388	DebugVSync();
61ef5cf4	389	#endif
ef79bbde P	390	}
	391
	392	/******************************************************************************/
	393
	394	void psxRcntWcount( u32 index, u32 value )
	395	{
	396	verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value );
	397
ef79bbde P	398	_psxRcntWcount( index, value );
	399	psxRcntSet();
	400	}
	401
	402	void psxRcntWmode( u32 index, u32 value )
	403	{
	404	verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value );
	405
a29f182f	406	_psxRcntWmode( index, value );
ef79bbde	407	_psxRcntWcount( index, 0 );
a29f182f	408
a29f182f	409	rcnts[index].irqState = 0;
ef79bbde P	410	psxRcntSet();
	411	}
	412
	413	void psxRcntWtarget( u32 index, u32 value )
	414	{
	415	verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value );
	416
ef79bbde P	417	rcnts[index].target = value;
	418
	419	_psxRcntWcount( index, _psxRcntRcount( index ) );
	420	psxRcntSet();
	421	}
	422
	423	/******************************************************************************/
	424
	425	u32 psxRcntRcount( u32 index )
	426	{
	427	u32 count;
	428
ef79bbde P	429	count = _psxRcntRcount( index );
	430
	431	// Parasite Eve 2 fix.
	432	if( Config.RCntFix )
	433	{
	434	if( index == 2 )
	435	{
	436	if( rcnts[index].counterState == CountToTarget )
	437	{
	438	count /= BIAS;
	439	}
	440	}
	441	}
	442
	443	verboseLog( 2, "[RCNT %i] rcount: %x\n", index, count );
	444
	445	return count;
	446	}
	447
	448	u32 psxRcntRmode( u32 index )
	449	{
	450	u16 mode;
	451
ef79bbde P	452	mode = rcnts[index].mode;
	453	rcnts[index].mode &= 0xe7ff;
	454
	455	verboseLog( 2, "[RCNT %i] rmode: %x\n", index, mode );
	456
	457	return mode;
	458	}
	459
	460	u32 psxRcntRtarget( u32 index )
	461	{
	462	verboseLog( 2, "[RCNT %i] rtarget: %x\n", index, rcnts[index].target );
	463
	464	return rcnts[index].target;
	465	}
	466
	467	/******************************************************************************/
	468
	469	void psxRcntInit()
	470	{
	471	s32 i;
	472
	473	// rcnt 0.
	474	rcnts[0].rate = 1;
	475	rcnts[0].irq = 0x10;
	476
	477	// rcnt 1.
	478	rcnts[1].rate = 1;
	479	rcnts[1].irq = 0x20;
	480
	481	// rcnt 2.
	482	rcnts[2].rate = 1;
	483	rcnts[2].irq = 0x40;
	484
	485	// rcnt base.
	486	rcnts[3].rate = 1;
	487	rcnts[3].mode = RcCountToTarget;
	488	rcnts[3].target = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
	489
	490	for( i = 0; i < CounterQuantity; ++i )
	491	{
	492	_psxRcntWcount( i, 0 );
	493	}
	494
c62b43c9	495	hSyncCount = 0;
c62b43c9	496	spuSyncCount = 0;
61ef5cf4	497	hsync_steps = 1;
c62b43c9	498
ef79bbde P	499	psxRcntSet();
	500	}
	501
	502	/******************************************************************************/
	503
496d88d4	504	s32 psxRcntFreeze( void *f, s32 Mode )
ef79bbde	505	{
a29f182f	506	u32 count;
	507	s32 i;
	508
ef79bbde P	509	gzfreeze( &rcnts, sizeof(rcnts) );
	510	gzfreeze( &hSyncCount, sizeof(hSyncCount) );
	511	gzfreeze( &spuSyncCount, sizeof(spuSyncCount) );
	512	gzfreeze( &psxNextCounter, sizeof(psxNextCounter) );
	513	gzfreeze( &psxNextsCounter, sizeof(psxNextsCounter) );
	514
61ef5cf4	515	if (Mode == 0)
a29f182f	516	{
	517	// don't trust things from a savestate
	518	for( i = 0; i < CounterQuantity; ++i )
	519	{
	520	_psxRcntWmode( i, rcnts[i].mode );
	521	count = (psxRegs.cycle - rcnts[i].cycleStart) / rcnts[i].rate;
	522	_psxRcntWcount( i, count );
	523	}
61ef5cf4	524	hsync_steps = (psxRegs.cycle - rcnts[3].cycleStart) / rcnts[3].target;
a29f182f	525	psxRcntSet();
61ef5cf4	526
a29f182f	527	base_cycle = 0;
a29f182f	528	}
4f55097d	529
ef79bbde P	530	return 0;
	531	}
	532
	533	/******************************************************************************/