[pcsx_rearmed.git] / libpcsxcore / psxcounters.c

/***************************************************************************
 *   Copyright (C) 2010 by Blade_Arma                                      *
 *                                                                         *
 *   This program is free software; you can redistribute it and/or modify  *
 *   it under the terms of the GNU General Public License as published by  *
 *   the Free Software Foundation; either version 2 of the License, or     *
 *   (at your option) any later version.                                   *
 *                                                                         *
 *   This program is distributed in the hope that it will be useful,       *
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
 *   GNU General Public License for more details.                          *
 *                                                                         *
 *   You should have received a copy of the GNU General Public License     *
 *   along with this program; if not, write to the                         *
 *   Free Software Foundation, Inc.,                                       *
 *   51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA.           *
 ***************************************************************************/

/*
 * Internal PSX counters.
 */

#include "psxcounters.h"

/******************************************************************************/

typedef struct Rcnt
{
    u16 mode, target;
    u32 rate, irq, counterState, irqState;
    u32 cycle, cycleStart;
} Rcnt;

enum
{
    Rc0Gate           = 0x0001, // 0    not implemented
    Rc1Gate           = 0x0001, // 0    not implemented
    Rc2Disable        = 0x0001, // 0    partially implemented
    RcUnknown1        = 0x0002, // 1    ?
    RcUnknown2        = 0x0004, // 2    ?
    RcCountToTarget   = 0x0008, // 3
    RcIrqOnTarget     = 0x0010, // 4
    RcIrqOnOverflow   = 0x0020, // 5
    RcIrqRegenerate   = 0x0040, // 6
    RcUnknown7        = 0x0080, // 7    ?
    Rc0PixelClock     = 0x0100, // 8    fake implementation
    Rc1HSyncClock     = 0x0100, // 8
    Rc2Unknown8       = 0x0100, // 8    ?
    Rc0Unknown9       = 0x0200, // 9    ?
    Rc1Unknown9       = 0x0200, // 9    ?
    Rc2OneEighthClock = 0x0200, // 9
    RcUnknown10       = 0x0400, // 10   ?
    RcCountEqTarget   = 0x0800, // 11
    RcOverflow        = 0x1000, // 12
    RcUnknown13       = 0x2000, // 13   ? (always zero)
    RcUnknown14       = 0x4000, // 14   ? (always zero)
    RcUnknown15       = 0x8000, // 15   ? (always zero)
};

#define CounterQuantity           ( 4 )
//static const u32 CounterQuantity  = 4;

static const u32 CountToOverflow  = 0;
static const u32 CountToTarget    = 1;

static const u32 FrameRate[]      = { 60, 50 };
static const u32 VBlankStart[]    = { 240, 256 };
static const u32 HSyncTotal[]     = { 262, 312 };
static const u32 SpuUpdInterval[] = { 23, 22 };

static const s32 VerboseLevel     = 0;

/******************************************************************************/

static Rcnt rcnts[ CounterQuantity ];

static u32 hSyncCount = 0;
static u32 spuSyncCount = 0;

u32 psxNextCounter = 0, psxNextsCounter = 0;

/******************************************************************************/

static inline
void setIrq( u32 irq )
{
    psxHu32ref(0x1070) |= SWAPu32(irq);
}

static
void verboseLog( s32 level, const char *str, ... )
{
    if( level <= VerboseLevel )
    {
        va_list va;
        char buf[ 4096 ];

        va_start( va, str );
        vsprintf( buf, str, va );
        va_end( va );

        printf( buf );
        fflush( stdout );
    }
}

/******************************************************************************/

static inline
void _psxRcntWcount( u32 index, u32 value )
{
    if( value > 0xffff )
    {
        verboseLog( 1, "[RCNT %i] wcount > 0xffff: %x\n", index, value );
        value &= 0xffff;
    }

    rcnts[index].cycleStart  = psxRegs.cycle;
    rcnts[index].cycleStart -= value * rcnts[index].rate;

    // TODO: <=.
    if( value < rcnts[index].target )
    {
        rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
        rcnts[index].counterState = CountToTarget;
    }
    else
    {
        rcnts[index].cycle = 0xffff * rcnts[index].rate;
        rcnts[index].counterState = CountToOverflow;
    }
}

static inline
u32 _psxRcntRcount( u32 index )
{
    u32 count;

    count  = psxRegs.cycle;
    count -= rcnts[index].cycleStart;
    count /= rcnts[index].rate;

    if( count > 0xffff )
    {
        verboseLog( 1, "[RCNT %i] rcount > 0xffff: %x\n", index, count );
        count &= 0xffff;
    }

    return count;
}

/******************************************************************************/

static
void psxRcntSet()
{
    s32 countToUpdate;
    u32 i;

    psxNextsCounter = psxRegs.cycle;
    psxNextCounter  = 0x7fffffff;

    for( i = 0; i < CounterQuantity; ++i )
    {
        countToUpdate = rcnts[i].cycle - (psxNextsCounter - rcnts[i].cycleStart);

        if( countToUpdate < 0 )
        {
            psxNextCounter = 0;
            break;
        }

        if( countToUpdate < (s32)psxNextCounter )
        {
            psxNextCounter = countToUpdate;
        }
    }
}

/******************************************************************************/

static
void psxRcntReset( u32 index )
{
    u32 count;

    if( rcnts[index].counterState == CountToTarget )
    {
        if( rcnts[index].mode & RcCountToTarget )
        {
            count  = psxRegs.cycle;
            count -= rcnts[index].cycleStart;
            count /= rcnts[index].rate;
            count -= rcnts[index].target;
        }
        else
        {
            count = _psxRcntRcount( index );
        }

        _psxRcntWcount( index, count );

        if( rcnts[index].mode & RcIrqOnTarget )
        {
            if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
            {
                verboseLog( 3, "[RCNT %i] irq: %x\n", index, count );
                setIrq( rcnts[index].irq );
                rcnts[index].irqState = 1;
            }
        }

        rcnts[index].mode |= RcCountEqTarget;
    }
    else if( rcnts[index].counterState == CountToOverflow )
    {
        count  = psxRegs.cycle;
        count -= rcnts[index].cycleStart;
        count /= rcnts[index].rate;
        count -= 0xffff;

        _psxRcntWcount( index, count );

        if( rcnts[index].mode & RcIrqOnOverflow )
        {
            if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
            {
                verboseLog( 3, "[RCNT %i] irq: %x\n", index, count );
                setIrq( rcnts[index].irq );
                rcnts[index].irqState = 1;
            }
        }

        rcnts[index].mode |= RcOverflow;
    }

    rcnts[index].mode |= RcUnknown10;

    psxRcntSet();
}

void psxRcntUpdate()
{
    u32 cycle;

    cycle = psxRegs.cycle;

    // rcnt 0.
    if( cycle - rcnts[0].cycleStart >= rcnts[0].cycle )
    {
        psxRcntReset( 0 );
    }

    // rcnt 1.
    if( cycle - rcnts[1].cycleStart >= rcnts[1].cycle )
    {
        psxRcntReset( 1 );
    }

    // rcnt 2.
    if( cycle - rcnts[2].cycleStart >= rcnts[2].cycle )
    {
        psxRcntReset( 2 );
    }

    // rcnt base.
    if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle )
    {
        psxRcntReset( 3 );

        spuSyncCount++;
        hSyncCount++;

        // Update spu.
        if( spuSyncCount >= SpuUpdInterval[Config.PsxType] )
        {
            spuSyncCount = 0;

            if( SPU_async )
            {
                SPU_async( SpuUpdInterval[Config.PsxType] * rcnts[3].target );
            }
        }
        
        // VSync irq.
        if( hSyncCount == VBlankStart[Config.PsxType] )
        {
            GPU_vBlank( 1 );
            
            // For the best times. :D
            //setIrq( 0x01 );
        }
        
        // Update lace. (with InuYasha fix)
        if( hSyncCount >= (Config.VSyncWA ? HSyncTotal[Config.PsxType] / BIAS : HSyncTotal[Config.PsxType]) )
        {
            hSyncCount = 0;

            GPU_vBlank( 0 );
            setIrq( 0x01 );

            GPU_updateLace();
            EmuUpdate();
        }
    }

    DebugVSync();
}

/******************************************************************************/

void psxRcntWcount( u32 index, u32 value )
{
    verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value );

    psxRcntUpdate();

    _psxRcntWcount( index, value );
    psxRcntSet();
}

void psxRcntWmode( u32 index, u32 value )
{
    verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value );

    psxRcntUpdate();

    rcnts[index].mode = value;
    rcnts[index].irqState = 0;

    switch( index )
    {
        case 0:
            if( value & Rc0PixelClock )
            {
                rcnts[index].rate = 5;
            }
            else
            {
                rcnts[index].rate = 1;
            }
        break;
        case 1:
            if( value & Rc1HSyncClock )
            {
                rcnts[index].rate = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
            }
            else
            {
                rcnts[index].rate = 1;
            }
        break;
        case 2:
            if( value & Rc2OneEighthClock )
            {
                rcnts[index].rate = 8;
            }
            else
            {
                rcnts[index].rate = 1;
            }

            // TODO: wcount must work.
            if( value & Rc2Disable )
            {
                rcnts[index].rate = 0xffffffff;
            }
        break;
    }

    _psxRcntWcount( index, 0 );
    psxRcntSet();
}

void psxRcntWtarget( u32 index, u32 value )
{
    verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value );

    psxRcntUpdate();

    rcnts[index].target = value;

    _psxRcntWcount( index, _psxRcntRcount( index ) );
    psxRcntSet();
}

/******************************************************************************/

u32 psxRcntRcount( u32 index )
{
    u32 count;

    psxRcntUpdate();

    count = _psxRcntRcount( index );

    // Parasite Eve 2 fix.
    if( Config.RCntFix )
    {
        if( index == 2 )
        {
            if( rcnts[index].counterState == CountToTarget )
            {
                count /= BIAS;
            }
        }
    }

    verboseLog( 2, "[RCNT %i] rcount: %x\n", index, count );

    return count;
}

u32 psxRcntRmode( u32 index )
{
    u16 mode;

    psxRcntUpdate();

    mode = rcnts[index].mode;
    rcnts[index].mode &= 0xe7ff;

    verboseLog( 2, "[RCNT %i] rmode: %x\n", index, mode );

    return mode;
}

u32 psxRcntRtarget( u32 index )
{
    verboseLog( 2, "[RCNT %i] rtarget: %x\n", index, rcnts[index].target );

    return rcnts[index].target;
}

/******************************************************************************/

void psxRcntInit()
{
    s32 i;

    // rcnt 0.
    rcnts[0].rate   = 1;
    rcnts[0].irq    = 0x10;

    // rcnt 1.
    rcnts[1].rate   = 1;
    rcnts[1].irq    = 0x20;

    // rcnt 2.
    rcnts[2].rate   = 1;
    rcnts[2].irq    = 0x40;

    // rcnt base.
    rcnts[3].rate   = 1;
    rcnts[3].mode   = RcCountToTarget;
    rcnts[3].target = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));

    for( i = 0; i < CounterQuantity; ++i )
    {
        _psxRcntWcount( i, 0 );
    }

    hSyncCount = 0;
    spuSyncCount = 0;

    psxRcntSet();
}

/******************************************************************************/

s32 psxRcntFreeze( gzFile f, s32 Mode )
{
    gzfreeze( &rcnts, sizeof(rcnts) );
    gzfreeze( &hSyncCount, sizeof(hSyncCount) );
    gzfreeze( &spuSyncCount, sizeof(spuSyncCount) );
    gzfreeze( &psxNextCounter, sizeof(psxNextCounter) );
    gzfreeze( &psxNextsCounter, sizeof(psxNextsCounter) );

    return 0;
}

/******************************************************************************/
Commit	Line	Data
ef79bbde P	1	/***************************************************************************
	2	* Copyright (C) 2010 by Blade_Arma *
	3	* *
	4	* This program is free software; you can redistribute it and/or modify *
	5	* it under the terms of the GNU General Public License as published by *
	6	* the Free Software Foundation; either version 2 of the License, or *
	7	* (at your option) any later version. *
	8	* *
	9	* This program is distributed in the hope that it will be useful, *
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of *
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
	12	* GNU General Public License for more details. *
	13	* *
	14	* You should have received a copy of the GNU General Public License *
	15	* along with this program; if not, write to the *
	16	* Free Software Foundation, Inc., *
	17	* 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
	18	***************************************************************************/
	19
	20	/*
	21	* Internal PSX counters.
	22	*/
	23
	24	#include "psxcounters.h"
	25
	26	/******************************************************************************/
	27
	28	typedef struct Rcnt
	29	{
	30	u16 mode, target;
	31	u32 rate, irq, counterState, irqState;
	32	u32 cycle, cycleStart;
	33	} Rcnt;
	34
	35	enum
	36	{
	37	Rc0Gate = 0x0001, // 0 not implemented
	38	Rc1Gate = 0x0001, // 0 not implemented
	39	Rc2Disable = 0x0001, // 0 partially implemented
	40	RcUnknown1 = 0x0002, // 1 ?
	41	RcUnknown2 = 0x0004, // 2 ?
	42	RcCountToTarget = 0x0008, // 3
	43	RcIrqOnTarget = 0x0010, // 4
	44	RcIrqOnOverflow = 0x0020, // 5
	45	RcIrqRegenerate = 0x0040, // 6
	46	RcUnknown7 = 0x0080, // 7 ?
	47	Rc0PixelClock = 0x0100, // 8 fake implementation
	48	Rc1HSyncClock = 0x0100, // 8
	49	Rc2Unknown8 = 0x0100, // 8 ?
	50	Rc0Unknown9 = 0x0200, // 9 ?
	51	Rc1Unknown9 = 0x0200, // 9 ?
	52	Rc2OneEighthClock = 0x0200, // 9
	53	RcUnknown10 = 0x0400, // 10 ?
	54	RcCountEqTarget = 0x0800, // 11
	55	RcOverflow = 0x1000, // 12
	56	RcUnknown13 = 0x2000, // 13 ? (always zero)
	57	RcUnknown14 = 0x4000, // 14 ? (always zero)
	58	RcUnknown15 = 0x8000, // 15 ? (always zero)
	59	};
	60
	61	#define CounterQuantity ( 4 )
	62	//static const u32 CounterQuantity = 4;
	63
	64	static const u32 CountToOverflow = 0;
65	static const u32 CountToTarget = 1;
66
67	static const u32 FrameRate[] = { 60, 50 };
68	static const u32 VBlankStart[] = { 240, 256 };
69	static const u32 HSyncTotal[] = { 262, 312 };
70	static const u32 SpuUpdInterval[] = { 23, 22 };
71
72	static const s32 VerboseLevel = 0;
73
74	/******************************************************************************/
75
76	static Rcnt rcnts[ CounterQuantity ];
77
78	static u32 hSyncCount = 0;
79	static u32 spuSyncCount = 0;
80
81	u32 psxNextCounter = 0, psxNextsCounter = 0;
82
83	/******************************************************************************/
84
85	static inline
86	void setIrq( u32 irq )
87	{
88	psxHu32ref(0x1070) \|= SWAPu32(irq);
89	}
90
91	static
92	void verboseLog( s32 level, const char *str, ... )
93	{
94	if( level <= VerboseLevel )
95	{
96	va_list va;
97	char buf[ 4096 ];
98
99	va_start( va, str );
100	vsprintf( buf, str, va );
101	va_end( va );
102
103	printf( buf );
104	fflush( stdout );
105	}
106	}
107
108	/******************************************************************************/
109
110	static inline
111	void _psxRcntWcount( u32 index, u32 value )
112	{
113	if( value > 0xffff )
114	{
115	verboseLog( 1, "[RCNT %i] wcount > 0xffff: %x\n", index, value );
116	value &= 0xffff;
117	}
118
119	rcnts[index].cycleStart = psxRegs.cycle;
120	rcnts[index].cycleStart -= value * rcnts[index].rate;
121
122	// TODO: <=.
123	if( value < rcnts[index].target )
124	{
125	rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
126	rcnts[index].counterState = CountToTarget;
127	}
128	else
129	{
130	rcnts[index].cycle = 0xffff * rcnts[index].rate;
131	rcnts[index].counterState = CountToOverflow;
132	}
133	}
134
135	static inline
136	u32 _psxRcntRcount( u32 index )
137	{
138	u32 count;
139
140	count = psxRegs.cycle;
141	count -= rcnts[index].cycleStart;
142	count /= rcnts[index].rate;
143
144	if( count > 0xffff )
145	{
146	verboseLog( 1, "[RCNT %i] rcount > 0xffff: %x\n", index, count );
147	count &= 0xffff;
148	}
149
150	return count;
151	}
152
153	/******************************************************************************/
154
155	static
156	void psxRcntSet()
157	{
158	s32 countToUpdate;
159	u32 i;
160
161	psxNextsCounter = psxRegs.cycle;
162	psxNextCounter = 0x7fffffff;
163
164	for( i = 0; i < CounterQuantity; ++i )
165	{
166	countToUpdate = rcnts[i].cycle - (psxNextsCounter - rcnts[i].cycleStart);
167
168	if( countToUpdate < 0 )
169	{
170	psxNextCounter = 0;
171	break;
172	}
173
174	if( countToUpdate < (s32)psxNextCounter )
175	{
176	psxNextCounter = countToUpdate;
177	}
178	}
179	}
180
181	/******************************************************************************/
182
183	static
184	void psxRcntReset( u32 index )
185	{
186	u32 count;
187
188	if( rcnts[index].counterState == CountToTarget )
189	{
190	if( rcnts[index].mode & RcCountToTarget )
191	{
192	count = psxRegs.cycle;
193	count -= rcnts[index].cycleStart;
194	count /= rcnts[index].rate;
195	count -= rcnts[index].target;
196	}
197	else
198	{
199	count = _psxRcntRcount( index );
200	}
201
202	_psxRcntWcount( index, count );
203
204	if( rcnts[index].mode & RcIrqOnTarget )
205	{
206	if( (rcnts[index].mode & RcIrqRegenerate) \|\| (!rcnts[index].irqState) )
207	{
208	verboseLog( 3, "[RCNT %i] irq: %x\n", index, count );
209	setIrq( rcnts[index].irq );
210	rcnts[index].irqState = 1;
211	}
212	}
213
214	rcnts[index].mode \|= RcCountEqTarget;
215	}
216	else if( rcnts[index].counterState == CountToOverflow )
217	{
218	count = psxRegs.cycle;
219	count -= rcnts[index].cycleStart;
220	count /= rcnts[index].rate;
221	count -= 0xffff;
222
223	_psxRcntWcount( index, count );
224
225	if( rcnts[index].mode & RcIrqOnOverflow )
226	{
227	if( (rcnts[index].mode & RcIrqRegenerate) \|\| (!rcnts[index].irqState) )
228	{
229	verboseLog( 3, "[RCNT %i] irq: %x\n", index, count );
230	setIrq( rcnts[index].irq );
231	rcnts[index].irqState = 1;
232	}
233	}
234
235	rcnts[index].mode \|= RcOverflow;
236	}
237
238	rcnts[index].mode \|= RcUnknown10;
239
240	psxRcntSet();
241	}
242
243	void psxRcntUpdate()
244	{
245	u32 cycle;
246
247	cycle = psxRegs.cycle;
248
249	// rcnt 0.
250	if( cycle - rcnts[0].cycleStart >= rcnts[0].cycle )
251	{
252	psxRcntReset( 0 );
253	}
254
255	// rcnt 1.
256	if( cycle - rcnts[1].cycleStart >= rcnts[1].cycle )
257	{
258	psxRcntReset( 1 );
259	}
260
261	// rcnt 2.
262	if( cycle - rcnts[2].cycleStart >= rcnts[2].cycle )
263	{
264	psxRcntReset( 2 );
265	}
266
267	// rcnt base.
268	if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle )
269	{
270	psxRcntReset( 3 );
271
272	spuSyncCount++;
273	hSyncCount++;
274
275	// Update spu.
276	if( spuSyncCount >= SpuUpdInterval[Config.PsxType] )
277	{
278	spuSyncCount = 0;
279
280	if( SPU_async )
281	{
282	SPU_async( SpuUpdInterval[Config.PsxType] * rcnts[3].target );
283	}
284	}
285
286	// VSync irq.
287	if( hSyncCount == VBlankStart[Config.PsxType] )
288	{
289	GPU_vBlank( 1 );
290
291	// For the best times. :D
292	//setIrq( 0x01 );
293	}
294
295	// Update lace. (with InuYasha fix)
296	if( hSyncCount >= (Config.VSyncWA ? HSyncTotal[Config.PsxType] / BIAS : HSyncTotal[Config.PsxType]) )
297	{
298	hSyncCount = 0;
299
300	GPU_vBlank( 0 );
301	setIrq( 0x01 );
302
303	GPU_updateLace();
304	EmuUpdate();
305	}
306	}
307
308	DebugVSync();
309	}
310
311	/******************************************************************************/
312
313	void psxRcntWcount( u32 index, u32 value )
314	{
315	verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value );
316
317	psxRcntUpdate();
318
319	_psxRcntWcount( index, value );
320	psxRcntSet();
321	}
322
323	void psxRcntWmode( u32 index, u32 value )
324	{
325	verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value );
326
327	psxRcntUpdate();
328
329	rcnts[index].mode = value;
330	rcnts[index].irqState = 0;
331
332	switch( index )
333	{
334	case 0:
335	if( value & Rc0PixelClock )
336	{
337	rcnts[index].rate = 5;
338	}
339	else
340	{
341	rcnts[index].rate = 1;
342	}
343	break;
344	case 1:
345	if( value & Rc1HSyncClock )
346	{
347	rcnts[index].rate = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
348	}
349	else
350	{
351	rcnts[index].rate = 1;
352	}
353	break;
354	case 2:
355	if( value & Rc2OneEighthClock )
356	{
357	rcnts[index].rate = 8;
358	}
359	else
360	{
361	rcnts[index].rate = 1;
362	}
363
364	// TODO: wcount must work.
365	if( value & Rc2Disable )
366	{
367	rcnts[index].rate = 0xffffffff;
368	}
369	break;
370	}
371
372	_psxRcntWcount( index, 0 );
373	psxRcntSet();
374	}
375
376	void psxRcntWtarget( u32 index, u32 value )
377	{
378	verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value );
379
380	psxRcntUpdate();
381
382	rcnts[index].target = value;
383
384	_psxRcntWcount( index, _psxRcntRcount( index ) );
385	psxRcntSet();
386	}
387
388	/******************************************************************************/
389
390	u32 psxRcntRcount( u32 index )
391	{
392	u32 count;
393
394	psxRcntUpdate();
395
396	count = _psxRcntRcount( index );
397
398	// Parasite Eve 2 fix.
399	if( Config.RCntFix )
400	{
401	if( index == 2 )
402	{
403	if( rcnts[index].counterState == CountToTarget )
404	{
405	count /= BIAS;
406	}
407	}
408	}
409
410	verboseLog( 2, "[RCNT %i] rcount: %x\n", index, count );
411
412	return count;
413	}
414
415	u32 psxRcntRmode( u32 index )
416	{
417	u16 mode;
418
419	psxRcntUpdate();
420
421	mode = rcnts[index].mode;
422	rcnts[index].mode &= 0xe7ff;
423
424	verboseLog( 2, "[RCNT %i] rmode: %x\n", index, mode );
425
426	return mode;
427	}
428
429	u32 psxRcntRtarget( u32 index )
430	{
431	verboseLog( 2, "[RCNT %i] rtarget: %x\n", index, rcnts[index].target );
432
433	return rcnts[index].target;
434	}
435
436	/******************************************************************************/
437
438	void psxRcntInit()
439	{
440	s32 i;
441
442	// rcnt 0.
443	rcnts[0].rate = 1;
444	rcnts[0].irq = 0x10;
445
446	// rcnt 1.
447	rcnts[1].rate = 1;
448	rcnts[1].irq = 0x20;
449
450	// rcnt 2.
451	rcnts[2].rate = 1;
452	rcnts[2].irq = 0x40;
453
454	// rcnt base.
455	rcnts[3].rate = 1;
456	rcnts[3].mode = RcCountToTarget;
457	rcnts[3].target = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
458
459	for( i = 0; i < CounterQuantity; ++i )
460	{
461	_psxRcntWcount( i, 0 );
462	}
463
c62b43c9	464	hSyncCount = 0;
	465	spuSyncCount = 0;
	466
ef79bbde P	467	psxRcntSet();
	468	}
	469
	470	/******************************************************************************/
	471
	472	s32 psxRcntFreeze( gzFile f, s32 Mode )
	473	{
	474	gzfreeze( &rcnts, sizeof(rcnts) );
	475	gzfreeze( &hSyncCount, sizeof(hSyncCount) );
	476	gzfreeze( &spuSyncCount, sizeof(spuSyncCount) );
	477	gzfreeze( &psxNextCounter, sizeof(psxNextCounter) );
	478	gzfreeze( &psxNextsCounter, sizeof(psxNextsCounter) );
	479
	480	return 0;
	481	}
	482
	483	/******************************************************************************/