[pcsx_rearmed.git] / libpcsxcore / psxcounters.c

/***************************************************************************
 *   Copyright (C) 2010 by Blade_Arma                                      *
 *                                                                         *
 *   This program is free software; you can redistribute it and/or modify  *
 *   it under the terms of the GNU General Public License as published by  *
 *   the Free Software Foundation; either version 2 of the License, or     *
 *   (at your option) any later version.                                   *
 *                                                                         *
 *   This program is distributed in the hope that it will be useful,       *
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
 *   GNU General Public License for more details.                          *
 *                                                                         *
 *   You should have received a copy of the GNU General Public License     *
 *   along with this program; if not, write to the                         *
 *   Free Software Foundation, Inc.,                                       *
 *   51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA.           *
 ***************************************************************************/

/*
 * Internal PSX counters.
 */

#include "psxcounters.h"
#include "gpu.h"
#include "debug.h"

/******************************************************************************/

enum
{
    Rc0Gate           = 0x0001, // 0    not implemented
    Rc1Gate           = 0x0001, // 0    not implemented
    Rc2Disable        = 0x0001, // 0    partially implemented
    RcUnknown1        = 0x0002, // 1    ?
    RcUnknown2        = 0x0004, // 2    ?
    RcCountToTarget   = 0x0008, // 3
    RcIrqOnTarget     = 0x0010, // 4
    RcIrqOnOverflow   = 0x0020, // 5
    RcIrqRegenerate   = 0x0040, // 6
    RcUnknown7        = 0x0080, // 7    ?
    Rc0PixelClock     = 0x0100, // 8    fake implementation
    Rc1HSyncClock     = 0x0100, // 8
    Rc2Unknown8       = 0x0100, // 8    ?
    Rc0Unknown9       = 0x0200, // 9    ?
    Rc1Unknown9       = 0x0200, // 9    ?
    Rc2OneEighthClock = 0x0200, // 9
    RcUnknown10       = 0x0400, // 10   ?
    RcCountEqTarget   = 0x0800, // 11
    RcOverflow        = 0x1000, // 12
    RcUnknown13       = 0x2000, // 13   ? (always zero)
    RcUnknown14       = 0x4000, // 14   ? (always zero)
    RcUnknown15       = 0x8000, // 15   ? (always zero)
};

#define CounterQuantity           ( 4 )
//static const u32 CounterQuantity  = 4;

static const u32 CountToOverflow  = 0;
static const u32 CountToTarget    = 1;

static const u32 FrameRate[]      = { 60, 50 };
static const u32 VBlankStart[]    = { 240, 256 };
static const u32 HSyncTotal[]     = { 263, 313 };
static const u32 SpuUpdInterval[] = { 32, 32 };

#define VERBOSE_LEVEL 0
static const s32 VerboseLevel     = VERBOSE_LEVEL;

/******************************************************************************/

Rcnt rcnts[ CounterQuantity ];

u32 hSyncCount = 0;
u32 frame_counter = 0;
static u32 spuSyncCount = 0;
static u32 hsync_steps = 0;
static u32 base_cycle = 0;

u32 psxNextCounter = 0, psxNextsCounter = 0;

/******************************************************************************/

static inline
void setIrq( u32 irq )
{
    psxHu32ref(0x1070) |= SWAPu32(irq);
}

static
void verboseLog( u32 level, const char *str, ... )
{
#if VERBOSE_LEVEL > 0
    if( level <= VerboseLevel )
    {
        va_list va;
        char buf[ 4096 ];

        va_start( va, str );
        vsprintf( buf, str, va );
        va_end( va );

        printf( "%s", buf );
        fflush( stdout );
    }
#endif
}

/******************************************************************************/

static inline
void _psxRcntWcount( u32 index, u32 value )
{
    if( value > 0xffff )
    {
        verboseLog( 1, "[RCNT %i] wcount > 0xffff: %x\n", index, value );
        value &= 0xffff;
    }

    rcnts[index].cycleStart  = psxRegs.cycle;
    rcnts[index].cycleStart -= value * rcnts[index].rate;

    // TODO: <=.
    if( value < rcnts[index].target )
    {
        rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
        rcnts[index].counterState = CountToTarget;
    }
    else
    {
        rcnts[index].cycle = 0xffff * rcnts[index].rate;
        rcnts[index].counterState = CountToOverflow;
    }
}

static inline
u32 _psxRcntRcount( u32 index )
{
    u32 count;

    count  = psxRegs.cycle;
    count -= rcnts[index].cycleStart;
    if (rcnts[index].rate > 1)
        count /= rcnts[index].rate;

    if( count > 0xffff )
    {
        verboseLog( 1, "[RCNT %i] rcount > 0xffff: %x\n", index, count );
        count &= 0xffff;
    }

    return count;
}

/******************************************************************************/

static
void psxRcntSet()
{
    s32 countToUpdate;
    u32 i;

    psxNextsCounter = psxRegs.cycle;
    psxNextCounter  = 0x7fffffff;

    for( i = 0; i < CounterQuantity; ++i )
    {
        countToUpdate = rcnts[i].cycle - (psxNextsCounter - rcnts[i].cycleStart);

        if( countToUpdate < 0 )
        {
            psxNextCounter = 0;
            break;
        }

        if( countToUpdate < (s32)psxNextCounter )
        {
            psxNextCounter = countToUpdate;
        }
    }

    psxRegs.interrupt |= (1 << PSXINT_RCNT);
    new_dyna_set_event(PSXINT_RCNT, psxNextCounter);
}

/******************************************************************************/

static
void psxRcntReset( u32 index )
{
    u32 count;

    rcnts[index].mode |= RcUnknown10;

    if( rcnts[index].counterState == CountToTarget )
    {
        count  = psxRegs.cycle;
        count -= rcnts[index].cycleStart;
        if( rcnts[index].rate > 1 )
            count /= rcnts[index].rate;
        if( rcnts[index].mode & RcCountToTarget )
            count -= rcnts[index].target;

        _psxRcntWcount( index, count );

        if( rcnts[index].mode & RcIrqOnTarget )
        {
            if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
            {
                verboseLog( 3, "[RCNT %i] irq: %x\n", index, count );
                setIrq( rcnts[index].irq );
                rcnts[index].irqState = 1;
            }
        }

        rcnts[index].mode |= RcCountEqTarget;

        if( count < 0xffff ) // special case, overflow too?
            return;
    }

    if( rcnts[index].counterState == CountToOverflow )
    {
        count  = psxRegs.cycle;
        count -= rcnts[index].cycleStart;
        if (rcnts[index].rate > 1)
            count /= rcnts[index].rate;
        count -= 0xffff;

        _psxRcntWcount( index, count );

        if( rcnts[index].mode & RcIrqOnOverflow )
        {
            if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
            {
                verboseLog( 3, "[RCNT %i] irq: %x\n", index, count );
                setIrq( rcnts[index].irq );
                rcnts[index].irqState = 1;
            }
        }

        rcnts[index].mode |= RcOverflow;
    }
}

void psxRcntUpdate()
{
    u32 cycle;

    cycle = psxRegs.cycle;

    // rcnt 0.
    if( cycle - rcnts[0].cycleStart >= rcnts[0].cycle )
    {
        psxRcntReset( 0 );
    }

    // rcnt 1.
    if( cycle - rcnts[1].cycleStart >= rcnts[1].cycle )
    {
        psxRcntReset( 1 );
    }

    // rcnt 2.
    if( cycle - rcnts[2].cycleStart >= rcnts[2].cycle )
    {
        psxRcntReset( 2 );
    }

    // rcnt base.
    if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle )
    {
        u32 leftover_cycles = cycle - rcnts[3].cycleStart - rcnts[3].cycle;
        u32 next_vsync, next_lace;

        spuSyncCount += hsync_steps;
        hSyncCount += hsync_steps;

        // Update spu.
        if( spuSyncCount >= SpuUpdInterval[Config.PsxType] )
        {
            spuSyncCount = 0;

            if( SPU_async )
            {
                SPU_async( SpuUpdInterval[Config.PsxType] * rcnts[3].target );
            }
        }
        
        // VSync irq.
        if( hSyncCount == VBlankStart[Config.PsxType] )
        {
            if( !(HW_GPU_STATUS & PSXGPU_ILACE) )
                HW_GPU_STATUS |= PSXGPU_LCF;

            setIrq( 0x01 );

            EmuUpdate();
            GPU_updateLace();
        }
        
        // Update lace. (with InuYasha fix)
        if( hSyncCount >= (Config.VSyncWA ? HSyncTotal[Config.PsxType] / BIAS : HSyncTotal[Config.PsxType]) )
        {
            hSyncCount = 0;
            frame_counter++;

            HW_GPU_STATUS &= ~PSXGPU_LCF;
            if( HW_GPU_STATUS & PSXGPU_ILACE )
                HW_GPU_STATUS |= frame_counter << 31;
        }

        // Schedule next call, in hsyncs
        hsync_steps = SpuUpdInterval[Config.PsxType] - spuSyncCount;
        next_vsync = VBlankStart[Config.PsxType] - hSyncCount; // ok to overflow
        next_lace = HSyncTotal[Config.PsxType] - hSyncCount;
        if( next_vsync && next_vsync < hsync_steps )
            hsync_steps = next_vsync;
        if( next_lace && next_lace < hsync_steps )
            hsync_steps = next_lace;

        rcnts[3].cycleStart = cycle - leftover_cycles;
        if (Config.PsxType)
                // 20.12 precision, clk / 50 / 313 ~= 2164.14
                base_cycle += hsync_steps * 8864320;
        else
                // clk / 60 / 263 ~= 2146.31
                base_cycle += hsync_steps * 8791293;
        rcnts[3].cycle = base_cycle >> 12;
        base_cycle &= 0xfff;
    }

    psxRcntSet();

#ifndef NDEBUG
    DebugVSync();
#endif
}

/******************************************************************************/

void psxRcntWcount( u32 index, u32 value )
{
    verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value );

    _psxRcntWcount( index, value );
    psxRcntSet();
}

void psxRcntWmode( u32 index, u32 value )
{
    verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value );

    rcnts[index].mode = value;
    rcnts[index].irqState = 0;

    switch( index )
    {
        case 0:
            if( value & Rc0PixelClock )
            {
                rcnts[index].rate = 5;
            }
            else
            {
                rcnts[index].rate = 1;
            }
        break;
        case 1:
            if( value & Rc1HSyncClock )
            {
                rcnts[index].rate = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
            }
            else
            {
                rcnts[index].rate = 1;
            }
        break;
        case 2:
            if( value & Rc2OneEighthClock )
            {
                rcnts[index].rate = 8;
            }
            else
            {
                rcnts[index].rate = 1;
            }

            // TODO: wcount must work.
            if( value & Rc2Disable )
            {
                rcnts[index].rate = 0xffffffff;
            }
        break;
    }

    _psxRcntWcount( index, 0 );
    psxRcntSet();
}

void psxRcntWtarget( u32 index, u32 value )
{
    verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value );

    rcnts[index].target = value;

    _psxRcntWcount( index, _psxRcntRcount( index ) );
    psxRcntSet();
}

/******************************************************************************/

u32 psxRcntRcount( u32 index )
{
    u32 count;

    count = _psxRcntRcount( index );

    // Parasite Eve 2 fix.
    if( Config.RCntFix )
    {
        if( index == 2 )
        {
            if( rcnts[index].counterState == CountToTarget )
            {
                count /= BIAS;
            }
        }
    }

    verboseLog( 2, "[RCNT %i] rcount: %x\n", index, count );

    return count;
}

u32 psxRcntRmode( u32 index )
{
    u16 mode;

    mode = rcnts[index].mode;
    rcnts[index].mode &= 0xe7ff;

    verboseLog( 2, "[RCNT %i] rmode: %x\n", index, mode );

    return mode;
}

u32 psxRcntRtarget( u32 index )
{
    verboseLog( 2, "[RCNT %i] rtarget: %x\n", index, rcnts[index].target );

    return rcnts[index].target;
}

/******************************************************************************/

void psxRcntInit()
{
    s32 i;

    // rcnt 0.
    rcnts[0].rate   = 1;
    rcnts[0].irq    = 0x10;

    // rcnt 1.
    rcnts[1].rate   = 1;
    rcnts[1].irq    = 0x20;

    // rcnt 2.
    rcnts[2].rate   = 1;
    rcnts[2].irq    = 0x40;

    // rcnt base.
    rcnts[3].rate   = 1;
    rcnts[3].mode   = RcCountToTarget;
    rcnts[3].target = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));

    for( i = 0; i < CounterQuantity; ++i )
    {
        _psxRcntWcount( i, 0 );
    }

    hSyncCount = 0;
    spuSyncCount = 0;
    hsync_steps = 1;

    psxRcntSet();
}

/******************************************************************************/

s32 psxRcntFreeze( gzFile f, s32 Mode )
{
    gzfreeze( &rcnts, sizeof(rcnts) );
    gzfreeze( &hSyncCount, sizeof(hSyncCount) );
    gzfreeze( &spuSyncCount, sizeof(spuSyncCount) );
    gzfreeze( &psxNextCounter, sizeof(psxNextCounter) );
    gzfreeze( &psxNextsCounter, sizeof(psxNextsCounter) );

    if (Mode == 0)
        hsync_steps = (psxRegs.cycle - rcnts[3].cycleStart) / rcnts[3].target;

    base_cycle = 0;

    return 0;
}

/******************************************************************************/
Commit	Line	Data
ef79bbde P	1	/***************************************************************************
	2	* Copyright (C) 2010 by Blade_Arma *
	3	* *
	4	* This program is free software; you can redistribute it and/or modify *
	5	* it under the terms of the GNU General Public License as published by *
	6	* the Free Software Foundation; either version 2 of the License, or *
	7	* (at your option) any later version. *
	8	* *
	9	* This program is distributed in the hope that it will be useful, *
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of *
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
	12	* GNU General Public License for more details. *
	13	* *
	14	* You should have received a copy of the GNU General Public License *
	15	* along with this program; if not, write to the *
	16	* Free Software Foundation, Inc., *
	17	* 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
	18	***************************************************************************/
	19
	20	/*
	21	* Internal PSX counters.
	22	*/
	23
	24	#include "psxcounters.h"
ddbaf678	25	#include "gpu.h"
fc8145b7	26	#include "debug.h"
ef79bbde P	27
	28	/******************************************************************************/
	29
ef79bbde P	30	enum
	31	{
	32	Rc0Gate = 0x0001, // 0 not implemented
	33	Rc1Gate = 0x0001, // 0 not implemented
	34	Rc2Disable = 0x0001, // 0 partially implemented
	35	RcUnknown1 = 0x0002, // 1 ?
	36	RcUnknown2 = 0x0004, // 2 ?
	37	RcCountToTarget = 0x0008, // 3
	38	RcIrqOnTarget = 0x0010, // 4
	39	RcIrqOnOverflow = 0x0020, // 5
	40	RcIrqRegenerate = 0x0040, // 6
	41	RcUnknown7 = 0x0080, // 7 ?
	42	Rc0PixelClock = 0x0100, // 8 fake implementation
	43	Rc1HSyncClock = 0x0100, // 8
	44	Rc2Unknown8 = 0x0100, // 8 ?
	45	Rc0Unknown9 = 0x0200, // 9 ?
	46	Rc1Unknown9 = 0x0200, // 9 ?
	47	Rc2OneEighthClock = 0x0200, // 9
	48	RcUnknown10 = 0x0400, // 10 ?
	49	RcCountEqTarget = 0x0800, // 11
	50	RcOverflow = 0x1000, // 12
	51	RcUnknown13 = 0x2000, // 13 ? (always zero)
	52	RcUnknown14 = 0x4000, // 14 ? (always zero)
	53	RcUnknown15 = 0x8000, // 15 ? (always zero)
	54	};
	55
	56	#define CounterQuantity ( 4 )
	57	//static const u32 CounterQuantity = 4;
	58
	59	static const u32 CountToOverflow = 0;
	60	static const u32 CountToTarget = 1;
	61
	62	static const u32 FrameRate[] = { 60, 50 };
	63	static const u32 VBlankStart[] = { 240, 256 };
aecf98c5	64	static const u32 HSyncTotal[] = { 263, 313 };
554a2220	65	static const u32 SpuUpdInterval[] = { 32, 32 };
ef79bbde	66
9f7ee52e	67	#define VERBOSE_LEVEL 0
9f7ee52e	68	static const s32 VerboseLevel = VERBOSE_LEVEL;
ef79bbde P	69
	70	/******************************************************************************/
	71
b1be1eee	72	Rcnt rcnts[ CounterQuantity ];
ef79bbde	73
24de2dd4	74	u32 hSyncCount = 0;
24de2dd4	75	u32 frame_counter = 0;
ef79bbde	76	static u32 spuSyncCount = 0;
61ef5cf4	77	static u32 hsync_steps = 0;
4f55097d	78	static u32 base_cycle = 0;
ef79bbde P	79
	80	u32 psxNextCounter = 0, psxNextsCounter = 0;
	81
	82	/******************************************************************************/
	83
	84	static inline
	85	void setIrq( u32 irq )
	86	{
	87	psxHu32ref(0x1070) \|= SWAPu32(irq);
	88	}
	89
	90	static
9f7ee52e	91	void verboseLog( u32 level, const char *str, ... )
ef79bbde	92	{
9f7ee52e	93	#if VERBOSE_LEVEL > 0
ef79bbde P	94	if( level <= VerboseLevel )
	95	{
	96	va_list va;
	97	char buf[ 4096 ];
	98
	99	va_start( va, str );
	100	vsprintf( buf, str, va );
	101	va_end( va );
	102
ab948f7e	103	printf( "%s", buf );
ef79bbde P	104	fflush( stdout );
ef79bbde P	105	}
9f7ee52e	106	#endif
ef79bbde P	107	}
	108
	109	/******************************************************************************/
	110
	111	static inline
	112	void _psxRcntWcount( u32 index, u32 value )
	113	{
	114	if( value > 0xffff )
	115	{
	116	verboseLog( 1, "[RCNT %i] wcount > 0xffff: %x\n", index, value );
	117	value &= 0xffff;
	118	}
	119
	120	rcnts[index].cycleStart = psxRegs.cycle;
	121	rcnts[index].cycleStart -= value * rcnts[index].rate;
	122
	123	// TODO: <=.
	124	if( value < rcnts[index].target )
	125	{
	126	rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
	127	rcnts[index].counterState = CountToTarget;
	128	}
	129	else
	130	{
	131	rcnts[index].cycle = 0xffff * rcnts[index].rate;
	132	rcnts[index].counterState = CountToOverflow;
	133	}
	134	}
	135
	136	static inline
	137	u32 _psxRcntRcount( u32 index )
	138	{
	139	u32 count;
	140
	141	count = psxRegs.cycle;
	142	count -= rcnts[index].cycleStart;
61ef5cf4	143	if (rcnts[index].rate > 1)
61ef5cf4	144	count /= rcnts[index].rate;
ef79bbde P	145
	146	if( count > 0xffff )
	147	{
	148	verboseLog( 1, "[RCNT %i] rcount > 0xffff: %x\n", index, count );
	149	count &= 0xffff;
	150	}
	151
	152	return count;
	153	}
	154
	155	/******************************************************************************/
	156
	157	static
	158	void psxRcntSet()
	159	{
	160	s32 countToUpdate;
	161	u32 i;
	162
	163	psxNextsCounter = psxRegs.cycle;
	164	psxNextCounter = 0x7fffffff;
	165
	166	for( i = 0; i < CounterQuantity; ++i )
	167	{
	168	countToUpdate = rcnts[i].cycle - (psxNextsCounter - rcnts[i].cycleStart);
	169
	170	if( countToUpdate < 0 )
	171	{
	172	psxNextCounter = 0;
	173	break;
	174	}
	175
	176	if( countToUpdate < (s32)psxNextCounter )
	177	{
	178	psxNextCounter = countToUpdate;
	179	}
	180	}
5b8c000f	181
	182	psxRegs.interrupt \|= (1 << PSXINT_RCNT);
	183	new_dyna_set_event(PSXINT_RCNT, psxNextCounter);
ef79bbde P	184	}
	185
	186	/******************************************************************************/
	187
	188	static
	189	void psxRcntReset( u32 index )
	190	{
	191	u32 count;
	192
53c361f0	193	rcnts[index].mode \|= RcUnknown10;
53c361f0	194
ef79bbde P	195	if( rcnts[index].counterState == CountToTarget )
ef79bbde P	196	{
95df1a04	197	count = psxRegs.cycle;
	198	count -= rcnts[index].cycleStart;
	199	if( rcnts[index].rate > 1 )
	200	count /= rcnts[index].rate;
ef79bbde	201	if( rcnts[index].mode & RcCountToTarget )
ef79bbde	202	count -= rcnts[index].target;
ef79bbde P	203
	204	_psxRcntWcount( index, count );
	205
	206	if( rcnts[index].mode & RcIrqOnTarget )
	207	{
	208	if( (rcnts[index].mode & RcIrqRegenerate) \|\| (!rcnts[index].irqState) )
	209	{
	210	verboseLog( 3, "[RCNT %i] irq: %x\n", index, count );
	211	setIrq( rcnts[index].irq );
	212	rcnts[index].irqState = 1;
	213	}
	214	}
	215
	216	rcnts[index].mode \|= RcCountEqTarget;
53c361f0	217
53c361f0	218	if( count < 0xffff ) // special case, overflow too?
53c361f0	219	return;
ef79bbde	220	}
53c361f0	221
53c361f0	222	if( rcnts[index].counterState == CountToOverflow )
ef79bbde P	223	{
	224	count = psxRegs.cycle;
	225	count -= rcnts[index].cycleStart;
61ef5cf4	226	if (rcnts[index].rate > 1)
61ef5cf4	227	count /= rcnts[index].rate;
ef79bbde P	228	count -= 0xffff;
	229
	230	_psxRcntWcount( index, count );
	231
	232	if( rcnts[index].mode & RcIrqOnOverflow )
	233	{
	234	if( (rcnts[index].mode & RcIrqRegenerate) \|\| (!rcnts[index].irqState) )
	235	{
	236	verboseLog( 3, "[RCNT %i] irq: %x\n", index, count );
	237	setIrq( rcnts[index].irq );
	238	rcnts[index].irqState = 1;
	239	}
	240	}
	241
	242	rcnts[index].mode \|= RcOverflow;
	243	}
ef79bbde P	244	}
	245
	246	void psxRcntUpdate()
	247	{
	248	u32 cycle;
	249
	250	cycle = psxRegs.cycle;
	251
	252	// rcnt 0.
	253	if( cycle - rcnts[0].cycleStart >= rcnts[0].cycle )
	254	{
	255	psxRcntReset( 0 );
	256	}
	257
	258	// rcnt 1.
	259	if( cycle - rcnts[1].cycleStart >= rcnts[1].cycle )
	260	{
	261	psxRcntReset( 1 );
	262	}
	263
	264	// rcnt 2.
	265	if( cycle - rcnts[2].cycleStart >= rcnts[2].cycle )
	266	{
	267	psxRcntReset( 2 );
	268	}
	269
	270	// rcnt base.
	271	if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle )
	272	{
61ef5cf4	273	u32 leftover_cycles = cycle - rcnts[3].cycleStart - rcnts[3].cycle;
61ef5cf4	274	u32 next_vsync, next_lace;
ef79bbde	275
61ef5cf4	276	spuSyncCount += hsync_steps;
61ef5cf4	277	hSyncCount += hsync_steps;
ef79bbde P	278
	279	// Update spu.
	280	if( spuSyncCount >= SpuUpdInterval[Config.PsxType] )
	281	{
	282	spuSyncCount = 0;
	283
	284	if( SPU_async )
	285	{
	286	SPU_async( SpuUpdInterval[Config.PsxType] * rcnts[3].target );
	287	}
	288	}
	289
	290	// VSync irq.
	291	if( hSyncCount == VBlankStart[Config.PsxType] )
	292	{
8bbbd091	293	if( !(HW_GPU_STATUS & PSXGPU_ILACE) )
ddbaf678	294	HW_GPU_STATUS \|= PSXGPU_LCF;
ddbaf678	295
8bbbd091	296	setIrq( 0x01 );
	297
	298	EmuUpdate();
	299	GPU_updateLace();
ef79bbde P	300	}
	301
	302	// Update lace. (with InuYasha fix)
	303	if( hSyncCount >= (Config.VSyncWA ? HSyncTotal[Config.PsxType] / BIAS : HSyncTotal[Config.PsxType]) )
	304	{
	305	hSyncCount = 0;
ddbaf678	306	frame_counter++;
ef79bbde	307
ddbaf678	308	HW_GPU_STATUS &= ~PSXGPU_LCF;
	309	if( HW_GPU_STATUS & PSXGPU_ILACE )
	310	HW_GPU_STATUS \|= frame_counter << 31;
ef79bbde	311	}
61ef5cf4	312
	313	// Schedule next call, in hsyncs
	314	hsync_steps = SpuUpdInterval[Config.PsxType] - spuSyncCount;
	315	next_vsync = VBlankStart[Config.PsxType] - hSyncCount; // ok to overflow
	316	next_lace = HSyncTotal[Config.PsxType] - hSyncCount;
	317	if( next_vsync && next_vsync < hsync_steps )
	318	hsync_steps = next_vsync;
	319	if( next_lace && next_lace < hsync_steps )
	320	hsync_steps = next_lace;
61ef5cf4	321
61ef5cf4	322	rcnts[3].cycleStart = cycle - leftover_cycles;
4f55097d	323	if (Config.PsxType)
	324	// 20.12 precision, clk / 50 / 313 ~= 2164.14
	325	base_cycle += hsync_steps * 8864320;
	326	else
	327	// clk / 60 / 263 ~= 2146.31
	328	base_cycle += hsync_steps * 8791293;
	329	rcnts[3].cycle = base_cycle >> 12;
	330	base_cycle &= 0xfff;
ef79bbde P	331	}
ef79bbde P	332
95df1a04	333	psxRcntSet();
95df1a04	334
61ef5cf4	335	#ifndef NDEBUG
ef79bbde	336	DebugVSync();
61ef5cf4	337	#endif
ef79bbde P	338	}
	339
	340	/******************************************************************************/
	341
	342	void psxRcntWcount( u32 index, u32 value )
	343	{
	344	verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value );
	345
ef79bbde P	346	_psxRcntWcount( index, value );
	347	psxRcntSet();
	348	}
	349
	350	void psxRcntWmode( u32 index, u32 value )
	351	{
	352	verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value );
	353
ef79bbde P	354	rcnts[index].mode = value;
	355	rcnts[index].irqState = 0;
	356
	357	switch( index )
	358	{
	359	case 0:
	360	if( value & Rc0PixelClock )
	361	{
	362	rcnts[index].rate = 5;
	363	}
	364	else
	365	{
	366	rcnts[index].rate = 1;
	367	}
	368	break;
	369	case 1:
	370	if( value & Rc1HSyncClock )
	371	{
	372	rcnts[index].rate = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
	373	}
	374	else
	375	{
	376	rcnts[index].rate = 1;
	377	}
	378	break;
	379	case 2:
	380	if( value & Rc2OneEighthClock )
	381	{
	382	rcnts[index].rate = 8;
	383	}
	384	else
	385	{
	386	rcnts[index].rate = 1;
	387	}
	388
	389	// TODO: wcount must work.
	390	if( value & Rc2Disable )
	391	{
	392	rcnts[index].rate = 0xffffffff;
	393	}
	394	break;
	395	}
	396
	397	_psxRcntWcount( index, 0 );
	398	psxRcntSet();
	399	}
	400
	401	void psxRcntWtarget( u32 index, u32 value )
	402	{
	403	verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value );
	404
ef79bbde P	405	rcnts[index].target = value;
	406
	407	_psxRcntWcount( index, _psxRcntRcount( index ) );
	408	psxRcntSet();
	409	}
	410
	411	/******************************************************************************/
	412
	413	u32 psxRcntRcount( u32 index )
	414	{
	415	u32 count;
	416
ef79bbde P	417	count = _psxRcntRcount( index );
	418
	419	// Parasite Eve 2 fix.
	420	if( Config.RCntFix )
	421	{
	422	if( index == 2 )
	423	{
	424	if( rcnts[index].counterState == CountToTarget )
	425	{
	426	count /= BIAS;
	427	}
	428	}
	429	}
	430
	431	verboseLog( 2, "[RCNT %i] rcount: %x\n", index, count );
	432
	433	return count;
	434	}
	435
	436	u32 psxRcntRmode( u32 index )
	437	{
	438	u16 mode;
	439
ef79bbde P	440	mode = rcnts[index].mode;
	441	rcnts[index].mode &= 0xe7ff;
	442
	443	verboseLog( 2, "[RCNT %i] rmode: %x\n", index, mode );
	444
	445	return mode;
	446	}
	447
	448	u32 psxRcntRtarget( u32 index )
	449	{
	450	verboseLog( 2, "[RCNT %i] rtarget: %x\n", index, rcnts[index].target );
	451
	452	return rcnts[index].target;
	453	}
	454
	455	/******************************************************************************/
	456
	457	void psxRcntInit()
	458	{
	459	s32 i;
	460
	461	// rcnt 0.
	462	rcnts[0].rate = 1;
	463	rcnts[0].irq = 0x10;
	464
	465	// rcnt 1.
	466	rcnts[1].rate = 1;
	467	rcnts[1].irq = 0x20;
	468
	469	// rcnt 2.
	470	rcnts[2].rate = 1;
	471	rcnts[2].irq = 0x40;
	472
	473	// rcnt base.
	474	rcnts[3].rate = 1;
	475	rcnts[3].mode = RcCountToTarget;
	476	rcnts[3].target = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
	477
	478	for( i = 0; i < CounterQuantity; ++i )
	479	{
	480	_psxRcntWcount( i, 0 );
	481	}
	482
c62b43c9	483	hSyncCount = 0;
c62b43c9	484	spuSyncCount = 0;
61ef5cf4	485	hsync_steps = 1;
c62b43c9	486
ef79bbde P	487	psxRcntSet();
	488	}
	489
	490	/******************************************************************************/
	491
	492	s32 psxRcntFreeze( gzFile f, s32 Mode )
	493	{
	494	gzfreeze( &rcnts, sizeof(rcnts) );
	495	gzfreeze( &hSyncCount, sizeof(hSyncCount) );
	496	gzfreeze( &spuSyncCount, sizeof(spuSyncCount) );
	497	gzfreeze( &psxNextCounter, sizeof(psxNextCounter) );
	498	gzfreeze( &psxNextsCounter, sizeof(psxNextsCounter) );
	499
61ef5cf4	500	if (Mode == 0)
	501	hsync_steps = (psxRegs.cycle - rcnts[3].cycleStart) / rcnts[3].target;
	502
4f55097d	503	base_cycle = 0;
4f55097d	504
ef79bbde P	505	return 0;
	506	}
	507
	508	/******************************************************************************/