[pcsx_rearmed.git] / libpcsxcore / psxcounters.c

/***************************************************************************
 *   Copyright (C) 2010 by Blade_Arma                                      *
 *                                                                         *
 *   This program is free software; you can redistribute it and/or modify  *
 *   it under the terms of the GNU General Public License as published by  *
 *   the Free Software Foundation; either version 2 of the License, or     *
 *   (at your option) any later version.                                   *
 *                                                                         *
 *   This program is distributed in the hope that it will be useful,       *
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
 *   GNU General Public License for more details.                          *
 *                                                                         *
 *   You should have received a copy of the GNU General Public License     *
 *   along with this program; if not, write to the                         *
 *   Free Software Foundation, Inc.,                                       *
 *   51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA.           *
 ***************************************************************************/

/*
 * Internal PSX counters.
 */

#include "psxcounters.h"
#include "debug.h"

/******************************************************************************/

typedef struct Rcnt
{
    u16 mode, target;
    u32 rate, irq, counterState, irqState;
    u32 cycle, cycleStart;
} Rcnt;

enum
{
    Rc0Gate           = 0x0001, // 0    not implemented
    Rc1Gate           = 0x0001, // 0    not implemented
    Rc2Disable        = 0x0001, // 0    partially implemented
    RcUnknown1        = 0x0002, // 1    ?
    RcUnknown2        = 0x0004, // 2    ?
    RcCountToTarget   = 0x0008, // 3
    RcIrqOnTarget     = 0x0010, // 4
    RcIrqOnOverflow   = 0x0020, // 5
    RcIrqRegenerate   = 0x0040, // 6
    RcUnknown7        = 0x0080, // 7    ?
    Rc0PixelClock     = 0x0100, // 8    fake implementation
    Rc1HSyncClock     = 0x0100, // 8
    Rc2Unknown8       = 0x0100, // 8    ?
    Rc0Unknown9       = 0x0200, // 9    ?
    Rc1Unknown9       = 0x0200, // 9    ?
    Rc2OneEighthClock = 0x0200, // 9
    RcUnknown10       = 0x0400, // 10   ?
    RcCountEqTarget   = 0x0800, // 11
    RcOverflow        = 0x1000, // 12
    RcUnknown13       = 0x2000, // 13   ? (always zero)
    RcUnknown14       = 0x4000, // 14   ? (always zero)
    RcUnknown15       = 0x8000, // 15   ? (always zero)
};

#define CounterQuantity           ( 4 )
//static const u32 CounterQuantity  = 4;

static const u32 CountToOverflow  = 0;
static const u32 CountToTarget    = 1;

static const u32 FrameRate[]      = { 60, 50 };
static const u32 VBlankStart[]    = { 240, 256 };
static const u32 HSyncTotal[]     = { 263, 313 };
static const u32 SpuUpdInterval[] = { 23, 22 };

static const s32 VerboseLevel     = 0;

/******************************************************************************/

static Rcnt rcnts[ CounterQuantity ];

static u32 hSyncCount = 0;
static u32 spuSyncCount = 0;

u32 psxNextCounter = 0, psxNextsCounter = 0;

/******************************************************************************/

static inline
void setIrq( u32 irq )
{
    psxHu32ref(0x1070) |= SWAPu32(irq);
}

static
void verboseLog( s32 level, const char *str, ... )
{
    if( level <= VerboseLevel )
    {
        va_list va;
        char buf[ 4096 ];

        va_start( va, str );
        vsprintf( buf, str, va );
        va_end( va );

        printf( "%s", buf );
        fflush( stdout );
    }
}

/******************************************************************************/

static inline
void _psxRcntWcount( u32 index, u32 value )
{
    if( value > 0xffff )
    {
        verboseLog( 1, "[RCNT %i] wcount > 0xffff: %x\n", index, value );
        value &= 0xffff;
    }

    rcnts[index].cycleStart  = psxRegs.cycle;
    rcnts[index].cycleStart -= value * rcnts[index].rate;

    // TODO: <=.
    if( value < rcnts[index].target )
    {
        rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
        rcnts[index].counterState = CountToTarget;
    }
    else
    {
        rcnts[index].cycle = 0xffff * rcnts[index].rate;
        rcnts[index].counterState = CountToOverflow;
    }
}

static inline
u32 _psxRcntRcount( u32 index )
{
    u32 count;

    count  = psxRegs.cycle;
    count -= rcnts[index].cycleStart;
    count /= rcnts[index].rate;

    if( count > 0xffff )
    {
        verboseLog( 1, "[RCNT %i] rcount > 0xffff: %x\n", index, count );
        count &= 0xffff;
    }

    return count;
}

/******************************************************************************/

static
void psxRcntSet()
{
    s32 countToUpdate;
    u32 i;

    psxNextsCounter = psxRegs.cycle;
    psxNextCounter  = 0x7fffffff;

    for( i = 0; i < CounterQuantity; ++i )
    {
        countToUpdate = rcnts[i].cycle - (psxNextsCounter - rcnts[i].cycleStart);

        if( countToUpdate < 0 )
        {
            psxNextCounter = 0;
            break;
        }

        if( countToUpdate < (s32)psxNextCounter )
        {
            psxNextCounter = countToUpdate;
        }
    }
}

/******************************************************************************/

static
void psxRcntReset( u32 index )
{
    u32 count;

    if( rcnts[index].counterState == CountToTarget )
    {
        if( rcnts[index].mode & RcCountToTarget )
        {
            count  = psxRegs.cycle;
            count -= rcnts[index].cycleStart;
            count /= rcnts[index].rate;
            count -= rcnts[index].target;
        }
        else
        {
            count = _psxRcntRcount( index );
        }

        _psxRcntWcount( index, count );

        if( rcnts[index].mode & RcIrqOnTarget )
        {
            if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
            {
                verboseLog( 3, "[RCNT %i] irq: %x\n", index, count );
                setIrq( rcnts[index].irq );
                rcnts[index].irqState = 1;
            }
        }

        rcnts[index].mode |= RcCountEqTarget;
    }
    else if( rcnts[index].counterState == CountToOverflow )
    {
        count  = psxRegs.cycle;
        count -= rcnts[index].cycleStart;
        count /= rcnts[index].rate;
        count -= 0xffff;

        _psxRcntWcount( index, count );

        if( rcnts[index].mode & RcIrqOnOverflow )
        {
            if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
            {
                verboseLog( 3, "[RCNT %i] irq: %x\n", index, count );
                setIrq( rcnts[index].irq );
                rcnts[index].irqState = 1;
            }
        }

        rcnts[index].mode |= RcOverflow;
    }

    rcnts[index].mode |= RcUnknown10;

    psxRcntSet();
}

void psxRcntUpdate()
{
    u32 cycle;

    cycle = psxRegs.cycle;

    // rcnt 0.
    if( cycle - rcnts[0].cycleStart >= rcnts[0].cycle )
    {
        psxRcntReset( 0 );
    }

    // rcnt 1.
    if( cycle - rcnts[1].cycleStart >= rcnts[1].cycle )
    {
        psxRcntReset( 1 );
    }

    // rcnt 2.
    if( cycle - rcnts[2].cycleStart >= rcnts[2].cycle )
    {
        psxRcntReset( 2 );
    }

    // rcnt base.
    if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle )
    {
        psxRcntReset( 3 );

        spuSyncCount++;
        hSyncCount++;

        // Update spu.
        if( spuSyncCount >= SpuUpdInterval[Config.PsxType] )
        {
            spuSyncCount = 0;

            if( SPU_async )
            {
                SPU_async( SpuUpdInterval[Config.PsxType] * rcnts[3].target );
            }
        }
        
        // VSync irq.
        if( hSyncCount == VBlankStart[Config.PsxType] )
        {
            GPU_vBlank( 1, &hSyncCount );
            
            // For the best times. :D
            //setIrq( 0x01 );
        }
        
        // Update lace. (with InuYasha fix)
        if( hSyncCount >= (Config.VSyncWA ? HSyncTotal[Config.PsxType] / BIAS : HSyncTotal[Config.PsxType]) )
        {
            hSyncCount = 0;

            GPU_vBlank( 0, &hSyncCount );
            setIrq( 0x01 );

            EmuUpdate();
            GPU_updateLace();
        }
    }

    DebugVSync();
}

/******************************************************************************/

void psxRcntWcount( u32 index, u32 value )
{
    verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value );

    psxRcntUpdate();

    _psxRcntWcount( index, value );
    psxRcntSet();
}

void psxRcntWmode( u32 index, u32 value )
{
    verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value );

    psxRcntUpdate();

    rcnts[index].mode = value;
    rcnts[index].irqState = 0;

    switch( index )
    {
        case 0:
            if( value & Rc0PixelClock )
            {
                rcnts[index].rate = 5;
            }
            else
            {
                rcnts[index].rate = 1;
            }
        break;
        case 1:
            if( value & Rc1HSyncClock )
            {
                rcnts[index].rate = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
            }
            else
            {
                rcnts[index].rate = 1;
            }
        break;
        case 2:
            if( value & Rc2OneEighthClock )
            {
                rcnts[index].rate = 8;
            }
            else
            {
                rcnts[index].rate = 1;
            }

            // TODO: wcount must work.
            if( value & Rc2Disable )
            {
                rcnts[index].rate = 0xffffffff;
            }
        break;
    }

    _psxRcntWcount( index, 0 );
    psxRcntSet();
}

void psxRcntWtarget( u32 index, u32 value )
{
    verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value );

    psxRcntUpdate();

    rcnts[index].target = value;

    _psxRcntWcount( index, _psxRcntRcount( index ) );
    psxRcntSet();
}

/******************************************************************************/

u32 psxRcntRcount( u32 index )
{
    u32 count;

    psxRcntUpdate();

    count = _psxRcntRcount( index );

    // Parasite Eve 2 fix.
    if( Config.RCntFix )
    {
        if( index == 2 )
        {
            if( rcnts[index].counterState == CountToTarget )
            {
                count /= BIAS;
            }
        }
    }

    verboseLog( 2, "[RCNT %i] rcount: %x\n", index, count );

    return count;
}

u32 psxRcntRmode( u32 index )
{
    u16 mode;

    psxRcntUpdate();

    mode = rcnts[index].mode;
    rcnts[index].mode &= 0xe7ff;

    verboseLog( 2, "[RCNT %i] rmode: %x\n", index, mode );

    return mode;
}

u32 psxRcntRtarget( u32 index )
{
    verboseLog( 2, "[RCNT %i] rtarget: %x\n", index, rcnts[index].target );

    return rcnts[index].target;
}

/******************************************************************************/

void psxRcntInit()
{
    s32 i;

    // rcnt 0.
    rcnts[0].rate   = 1;
    rcnts[0].irq    = 0x10;

    // rcnt 1.
    rcnts[1].rate   = 1;
    rcnts[1].irq    = 0x20;

    // rcnt 2.
    rcnts[2].rate   = 1;
    rcnts[2].irq    = 0x40;

    // rcnt base.
    rcnts[3].rate   = 1;
    rcnts[3].mode   = RcCountToTarget;
    rcnts[3].target = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));

    for( i = 0; i < CounterQuantity; ++i )
    {
        _psxRcntWcount( i, 0 );
    }

    hSyncCount = 0;
    spuSyncCount = 0;

    psxRcntSet();
}

/******************************************************************************/

s32 psxRcntFreeze( gzFile f, s32 Mode )
{
    gzfreeze( &rcnts, sizeof(rcnts) );
    gzfreeze( &hSyncCount, sizeof(hSyncCount) );
    gzfreeze( &spuSyncCount, sizeof(spuSyncCount) );
    gzfreeze( &psxNextCounter, sizeof(psxNextCounter) );
    gzfreeze( &psxNextsCounter, sizeof(psxNextsCounter) );

    return 0;
}

/******************************************************************************/
Commit	Line	Data
ef79bbde P	1	/***************************************************************************
	2	* Copyright (C) 2010 by Blade_Arma *
	3	* *
	4	* This program is free software; you can redistribute it and/or modify *
	5	* it under the terms of the GNU General Public License as published by *
	6	* the Free Software Foundation; either version 2 of the License, or *
	7	* (at your option) any later version. *
	8	* *
	9	* This program is distributed in the hope that it will be useful, *
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of *
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
	12	* GNU General Public License for more details. *
	13	* *
	14	* You should have received a copy of the GNU General Public License *
	15	* along with this program; if not, write to the *
	16	* Free Software Foundation, Inc., *
	17	* 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
	18	***************************************************************************/
	19
	20	/*
	21	* Internal PSX counters.
	22	*/
	23
	24	#include "psxcounters.h"
fc8145b7	25	#include "debug.h"
ef79bbde P	26
	27	/******************************************************************************/
	28
	29	typedef struct Rcnt
	30	{
	31	u16 mode, target;
	32	u32 rate, irq, counterState, irqState;
	33	u32 cycle, cycleStart;
	34	} Rcnt;
	35
	36	enum
	37	{
	38	Rc0Gate = 0x0001, // 0 not implemented
	39	Rc1Gate = 0x0001, // 0 not implemented
	40	Rc2Disable = 0x0001, // 0 partially implemented
	41	RcUnknown1 = 0x0002, // 1 ?
	42	RcUnknown2 = 0x0004, // 2 ?
	43	RcCountToTarget = 0x0008, // 3
	44	RcIrqOnTarget = 0x0010, // 4
	45	RcIrqOnOverflow = 0x0020, // 5
	46	RcIrqRegenerate = 0x0040, // 6
	47	RcUnknown7 = 0x0080, // 7 ?
	48	Rc0PixelClock = 0x0100, // 8 fake implementation
	49	Rc1HSyncClock = 0x0100, // 8
	50	Rc2Unknown8 = 0x0100, // 8 ?
	51	Rc0Unknown9 = 0x0200, // 9 ?
	52	Rc1Unknown9 = 0x0200, // 9 ?
	53	Rc2OneEighthClock = 0x0200, // 9
	54	RcUnknown10 = 0x0400, // 10 ?
	55	RcCountEqTarget = 0x0800, // 11
	56	RcOverflow = 0x1000, // 12
	57	RcUnknown13 = 0x2000, // 13 ? (always zero)
	58	RcUnknown14 = 0x4000, // 14 ? (always zero)
	59	RcUnknown15 = 0x8000, // 15 ? (always zero)
	60	};
	61
	62	#define CounterQuantity ( 4 )
	63	//static const u32 CounterQuantity = 4;
	64
	65	static const u32 CountToOverflow = 0;
	66	static const u32 CountToTarget = 1;
	67
	68	static const u32 FrameRate[] = { 60, 50 };
	69	static const u32 VBlankStart[] = { 240, 256 };
aecf98c5	70	static const u32 HSyncTotal[] = { 263, 313 };
ef79bbde P	71	static const u32 SpuUpdInterval[] = { 23, 22 };
	72
	73	static const s32 VerboseLevel = 0;
	74
	75	/******************************************************************************/
	76
	77	static Rcnt rcnts[ CounterQuantity ];
	78
	79	static u32 hSyncCount = 0;
	80	static u32 spuSyncCount = 0;
	81
	82	u32 psxNextCounter = 0, psxNextsCounter = 0;
	83
	84	/******************************************************************************/
	85
	86	static inline
	87	void setIrq( u32 irq )
	88	{
	89	psxHu32ref(0x1070) \|= SWAPu32(irq);
	90	}
	91
	92	static
	93	void verboseLog( s32 level, const char *str, ... )
	94	{
	95	if( level <= VerboseLevel )
	96	{
	97	va_list va;
	98	char buf[ 4096 ];
	99
	100	va_start( va, str );
	101	vsprintf( buf, str, va );
	102	va_end( va );
	103
ab948f7e	104	printf( "%s", buf );
ef79bbde P	105	fflush( stdout );
	106	}
	107	}
	108
	109	/******************************************************************************/
	110
	111	static inline
	112	void _psxRcntWcount( u32 index, u32 value )
	113	{
	114	if( value > 0xffff )
	115	{
	116	verboseLog( 1, "[RCNT %i] wcount > 0xffff: %x\n", index, value );
	117	value &= 0xffff;
	118	}
	119
	120	rcnts[index].cycleStart = psxRegs.cycle;
	121	rcnts[index].cycleStart -= value * rcnts[index].rate;
	122
	123	// TODO: <=.
	124	if( value < rcnts[index].target )
	125	{
	126	rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
	127	rcnts[index].counterState = CountToTarget;
	128	}
	129	else
	130	{
	131	rcnts[index].cycle = 0xffff * rcnts[index].rate;
	132	rcnts[index].counterState = CountToOverflow;
	133	}
	134	}
	135
	136	static inline
	137	u32 _psxRcntRcount( u32 index )
	138	{
	139	u32 count;
	140
	141	count = psxRegs.cycle;
	142	count -= rcnts[index].cycleStart;
	143	count /= rcnts[index].rate;
	144
	145	if( count > 0xffff )
	146	{
	147	verboseLog( 1, "[RCNT %i] rcount > 0xffff: %x\n", index, count );
	148	count &= 0xffff;
	149	}
	150
	151	return count;
	152	}
	153
	154	/******************************************************************************/
	155
	156	static
	157	void psxRcntSet()
	158	{
	159	s32 countToUpdate;
	160	u32 i;
	161
	162	psxNextsCounter = psxRegs.cycle;
	163	psxNextCounter = 0x7fffffff;
	164
	165	for( i = 0; i < CounterQuantity; ++i )
	166	{
	167	countToUpdate = rcnts[i].cycle - (psxNextsCounter - rcnts[i].cycleStart);
	168
169	if( countToUpdate < 0 )
170	{
171	psxNextCounter = 0;
172	break;
173	}
174
175	if( countToUpdate < (s32)psxNextCounter )
176	{
177	psxNextCounter = countToUpdate;
178	}
179	}
180	}
181
182	/******************************************************************************/
183
184	static
185	void psxRcntReset( u32 index )
186	{
187	u32 count;
188
189	if( rcnts[index].counterState == CountToTarget )
190	{
191	if( rcnts[index].mode & RcCountToTarget )
192	{
193	count = psxRegs.cycle;
194	count -= rcnts[index].cycleStart;
195	count /= rcnts[index].rate;
196	count -= rcnts[index].target;
197	}
198	else
199	{
200	count = _psxRcntRcount( index );
201	}
202
203	_psxRcntWcount( index, count );
204
205	if( rcnts[index].mode & RcIrqOnTarget )
206	{
207	if( (rcnts[index].mode & RcIrqRegenerate) \|\| (!rcnts[index].irqState) )
208	{
209	verboseLog( 3, "[RCNT %i] irq: %x\n", index, count );
210	setIrq( rcnts[index].irq );
211	rcnts[index].irqState = 1;
212	}
213	}
214
215	rcnts[index].mode \|= RcCountEqTarget;
216	}
217	else if( rcnts[index].counterState == CountToOverflow )
218	{
219	count = psxRegs.cycle;
220	count -= rcnts[index].cycleStart;
221	count /= rcnts[index].rate;
222	count -= 0xffff;
223
224	_psxRcntWcount( index, count );
225
226	if( rcnts[index].mode & RcIrqOnOverflow )
227	{
228	if( (rcnts[index].mode & RcIrqRegenerate) \|\| (!rcnts[index].irqState) )
229	{
230	verboseLog( 3, "[RCNT %i] irq: %x\n", index, count );
231	setIrq( rcnts[index].irq );
232	rcnts[index].irqState = 1;
233	}
234	}
235
236	rcnts[index].mode \|= RcOverflow;
237	}
238
239	rcnts[index].mode \|= RcUnknown10;
240
241	psxRcntSet();
242	}
243
244	void psxRcntUpdate()
245	{
246	u32 cycle;
247
248	cycle = psxRegs.cycle;
249
250	// rcnt 0.
251	if( cycle - rcnts[0].cycleStart >= rcnts[0].cycle )
252	{
253	psxRcntReset( 0 );
254	}
255
256	// rcnt 1.
257	if( cycle - rcnts[1].cycleStart >= rcnts[1].cycle )
258	{
259	psxRcntReset( 1 );
260	}
261
262	// rcnt 2.
263	if( cycle - rcnts[2].cycleStart >= rcnts[2].cycle )
264	{
265	psxRcntReset( 2 );
266	}
267
268	// rcnt base.
269	if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle )
270	{
271	psxRcntReset( 3 );
272
273	spuSyncCount++;
274	hSyncCount++;
275
276	// Update spu.
277	if( spuSyncCount >= SpuUpdInterval[Config.PsxType] )
278	{
279	spuSyncCount = 0;
280
281	if( SPU_async )
282	{
283	SPU_async( SpuUpdInterval[Config.PsxType] * rcnts[3].target );
284	}
285	}
286
287	// VSync irq.
288	if( hSyncCount == VBlankStart[Config.PsxType] )
289	{
6c9a982a	290	GPU_vBlank( 1, &hSyncCount );
ef79bbde P	291
	292	// For the best times. :D
	293	//setIrq( 0x01 );
	294	}
	295
	296	// Update lace. (with InuYasha fix)
	297	if( hSyncCount >= (Config.VSyncWA ? HSyncTotal[Config.PsxType] / BIAS : HSyncTotal[Config.PsxType]) )
	298	{
	299	hSyncCount = 0;
	300
6c9a982a	301	GPU_vBlank( 0, &hSyncCount );
ef79bbde P	302	setIrq( 0x01 );
ef79bbde P	303
ef79bbde	304	EmuUpdate();
cefe86b7	305	GPU_updateLace();
ef79bbde P	306	}
	307	}
	308
	309	DebugVSync();
	310	}
	311
	312	/******************************************************************************/
	313
	314	void psxRcntWcount( u32 index, u32 value )
	315	{
	316	verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value );
	317
	318	psxRcntUpdate();
	319
	320	_psxRcntWcount( index, value );
	321	psxRcntSet();
	322	}
	323
	324	void psxRcntWmode( u32 index, u32 value )
	325	{
	326	verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value );
	327
	328	psxRcntUpdate();
	329
	330	rcnts[index].mode = value;
	331	rcnts[index].irqState = 0;
	332
	333	switch( index )
	334	{
	335	case 0:
	336	if( value & Rc0PixelClock )
	337	{
	338	rcnts[index].rate = 5;
	339	}
	340	else
	341	{
	342	rcnts[index].rate = 1;
	343	}
	344	break;
	345	case 1:
	346	if( value & Rc1HSyncClock )
	347	{
	348	rcnts[index].rate = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
	349	}
	350	else
	351	{
	352	rcnts[index].rate = 1;
	353	}
	354	break;
	355	case 2:
	356	if( value & Rc2OneEighthClock )
	357	{
	358	rcnts[index].rate = 8;
	359	}
	360	else
	361	{
	362	rcnts[index].rate = 1;
	363	}
	364
	365	// TODO: wcount must work.
	366	if( value & Rc2Disable )
	367	{
	368	rcnts[index].rate = 0xffffffff;
	369	}
370	break;
371	}
372
373	_psxRcntWcount( index, 0 );
374	psxRcntSet();
375	}
376
377	void psxRcntWtarget( u32 index, u32 value )
378	{
379	verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value );
380
381	psxRcntUpdate();
382
383	rcnts[index].target = value;
384
385	_psxRcntWcount( index, _psxRcntRcount( index ) );
386	psxRcntSet();
387	}
388
389	/******************************************************************************/
390
391	u32 psxRcntRcount( u32 index )
392	{
393	u32 count;
394
395	psxRcntUpdate();
396
397	count = _psxRcntRcount( index );
398
399	// Parasite Eve 2 fix.
400	if( Config.RCntFix )
401	{
402	if( index == 2 )
403	{
404	if( rcnts[index].counterState == CountToTarget )
405	{
406	count /= BIAS;
407	}
408	}
409	}
410
411	verboseLog( 2, "[RCNT %i] rcount: %x\n", index, count );
412
413	return count;
414	}
415
416	u32 psxRcntRmode( u32 index )
417	{
418	u16 mode;
419
420	psxRcntUpdate();
421
422	mode = rcnts[index].mode;
423	rcnts[index].mode &= 0xe7ff;
424
425	verboseLog( 2, "[RCNT %i] rmode: %x\n", index, mode );
426
427	return mode;
428	}
429
430	u32 psxRcntRtarget( u32 index )
431	{
432	verboseLog( 2, "[RCNT %i] rtarget: %x\n", index, rcnts[index].target );
433
434	return rcnts[index].target;
435	}
436
437	/******************************************************************************/
438
439	void psxRcntInit()
440	{
441	s32 i;
442
443	// rcnt 0.
444	rcnts[0].rate = 1;
445	rcnts[0].irq = 0x10;
446
447	// rcnt 1.
448	rcnts[1].rate = 1;
449	rcnts[1].irq = 0x20;
450
451	// rcnt 2.
452	rcnts[2].rate = 1;
453	rcnts[2].irq = 0x40;
454
455	// rcnt base.
456	rcnts[3].rate = 1;
457	rcnts[3].mode = RcCountToTarget;
458	rcnts[3].target = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
459
460	for( i = 0; i < CounterQuantity; ++i )
461	{
462	_psxRcntWcount( i, 0 );
463	}
464
c62b43c9	465	hSyncCount = 0;
	466	spuSyncCount = 0;
	467
ef79bbde P	468	psxRcntSet();
	469	}
	470
	471	/******************************************************************************/
	472
	473	s32 psxRcntFreeze( gzFile f, s32 Mode )
	474	{
	475	gzfreeze( &rcnts, sizeof(rcnts) );
	476	gzfreeze( &hSyncCount, sizeof(hSyncCount) );
	477	gzfreeze( &spuSyncCount, sizeof(spuSyncCount) );
	478	gzfreeze( &psxNextCounter, sizeof(psxNextCounter) );
	479	gzfreeze( &psxNextsCounter, sizeof(psxNextsCounter) );
	480
	481	return 0;
	482	}
	483
	484	/******************************************************************************/