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drc: merge Ari64's patch: 05_dont_write_r0
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
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1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2010 Ari64 *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21#include <stdlib.h>
22#include <stdint.h> //include for uint64_t
23#include <assert.h>
24
25#include "emu_if.h" //emulator interface
26
27#include <sys/mman.h>
28
29#ifdef __i386__
30#include "assem_x86.h"
31#endif
32#ifdef __x86_64__
33#include "assem_x64.h"
34#endif
35#ifdef __arm__
36#include "assem_arm.h"
37#endif
38
39#define MAXBLOCK 4096
40#define MAX_OUTPUT_BLOCK_SIZE 262144
41#define CLOCK_DIVIDER 2
42
43struct regstat
44{
45 signed char regmap_entry[HOST_REGS];
46 signed char regmap[HOST_REGS];
47 uint64_t was32;
48 uint64_t is32;
49 uint64_t wasdirty;
50 uint64_t dirty;
51 uint64_t u;
52 uint64_t uu;
53 u_int wasconst;
54 u_int isconst;
55 uint64_t constmap[HOST_REGS];
56};
57
58struct ll_entry
59{
60 u_int vaddr;
61 u_int reg32;
62 void *addr;
63 struct ll_entry *next;
64};
65
66 u_int start;
67 u_int *source;
68 u_int pagelimit;
69 char insn[MAXBLOCK][10];
70 u_char itype[MAXBLOCK];
71 u_char opcode[MAXBLOCK];
72 u_char opcode2[MAXBLOCK];
73 u_char bt[MAXBLOCK];
74 u_char rs1[MAXBLOCK];
75 u_char rs2[MAXBLOCK];
76 u_char rt1[MAXBLOCK];
77 u_char rt2[MAXBLOCK];
78 u_char us1[MAXBLOCK];
79 u_char us2[MAXBLOCK];
80 u_char dep1[MAXBLOCK];
81 u_char dep2[MAXBLOCK];
82 u_char lt1[MAXBLOCK];
83 int imm[MAXBLOCK];
84 u_int ba[MAXBLOCK];
85 char likely[MAXBLOCK];
86 char is_ds[MAXBLOCK];
87 uint64_t unneeded_reg[MAXBLOCK];
88 uint64_t unneeded_reg_upper[MAXBLOCK];
89 uint64_t branch_unneeded_reg[MAXBLOCK];
90 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
91 uint64_t p32[MAXBLOCK];
92 uint64_t pr32[MAXBLOCK];
93 signed char regmap_pre[MAXBLOCK][HOST_REGS];
94 signed char regmap[MAXBLOCK][HOST_REGS];
95 signed char regmap_entry[MAXBLOCK][HOST_REGS];
96 uint64_t constmap[MAXBLOCK][HOST_REGS];
97 uint64_t known_value[HOST_REGS];
98 u_int known_reg;
99 struct regstat regs[MAXBLOCK];
100 struct regstat branch_regs[MAXBLOCK];
101 u_int needed_reg[MAXBLOCK];
102 uint64_t requires_32bit[MAXBLOCK];
103 u_int wont_dirty[MAXBLOCK];
104 u_int will_dirty[MAXBLOCK];
105 int ccadj[MAXBLOCK];
106 int slen;
107 u_int instr_addr[MAXBLOCK];
108 u_int link_addr[MAXBLOCK][3];
109 int linkcount;
110 u_int stubs[MAXBLOCK*3][8];
111 int stubcount;
112 u_int literals[1024][2];
113 int literalcount;
114 int is_delayslot;
115 int cop1_usable;
116 u_char *out;
117 struct ll_entry *jump_in[4096];
118 struct ll_entry *jump_out[4096];
119 struct ll_entry *jump_dirty[4096];
120 u_int hash_table[65536][4] __attribute__((aligned(16)));
121 char shadow[1048576] __attribute__((aligned(16)));
122 void *copy;
123 int expirep;
124 u_int using_tlb;
125 u_int stop_after_jal;
126 extern u_char restore_candidate[512];
127 extern int cycle_count;
128
129 /* registers that may be allocated */
130 /* 1-31 gpr */
131#define HIREG 32 // hi
132#define LOREG 33 // lo
133#define FSREG 34 // FPU status (FCSR)
134#define CSREG 35 // Coprocessor status
135#define CCREG 36 // Cycle count
136#define INVCP 37 // Pointer to invalid_code
137#define TEMPREG 38
138#define FTEMP 38 // FPU/LDL/LDR temporary register
139#define PTEMP 39 // Prefetch temporary register
140#define TLREG 40 // TLB mapping offset
141#define RHASH 41 // Return address hash
142#define RHTBL 42 // Return address hash table address
143#define RTEMP 43 // JR/JALR address register
144#define MAXREG 43
145#define AGEN1 44 // Address generation temporary register
146#define AGEN2 45 // Address generation temporary register
147#define MGEN1 46 // Maptable address generation temporary register
148#define MGEN2 47 // Maptable address generation temporary register
149#define BTREG 48 // Branch target temporary register
150
151 /* instruction types */
152#define NOP 0 // No operation
153#define LOAD 1 // Load
154#define STORE 2 // Store
155#define LOADLR 3 // Unaligned load
156#define STORELR 4 // Unaligned store
157#define MOV 5 // Move
158#define ALU 6 // Arithmetic/logic
159#define MULTDIV 7 // Multiply/divide
160#define SHIFT 8 // Shift by register
161#define SHIFTIMM 9// Shift by immediate
162#define IMM16 10 // 16-bit immediate
163#define RJUMP 11 // Unconditional jump to register
164#define UJUMP 12 // Unconditional jump
165#define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
166#define SJUMP 14 // Conditional branch (regimm format)
167#define COP0 15 // Coprocessor 0
168#define COP1 16 // Coprocessor 1
169#define C1LS 17 // Coprocessor 1 load/store
170#define FJUMP 18 // Conditional branch (floating point)
171#define FLOAT 19 // Floating point unit
172#define FCONV 20 // Convert integer to float
173#define FCOMP 21 // Floating point compare (sets FSREG)
174#define SYSCALL 22// SYSCALL
175#define OTHER 23 // Other
176#define SPAN 24 // Branch/delay slot spans 2 pages
177#define NI 25 // Not implemented
178#define HLECALL 26// PCSX fake opcodes for HLE
179#define COP2 27 // Coprocessor 2 move
180#define C2LS 28 // Coprocessor 2 load/store
181#define C2OP 29 // Coprocessor 2 operation
182#define INTCALL 30// Call interpreter to handle rare corner cases
183
184 /* stubs */
185#define CC_STUB 1
186#define FP_STUB 2
187#define LOADB_STUB 3
188#define LOADH_STUB 4
189#define LOADW_STUB 5
190#define LOADD_STUB 6
191#define LOADBU_STUB 7
192#define LOADHU_STUB 8
193#define STOREB_STUB 9
194#define STOREH_STUB 10
195#define STOREW_STUB 11
196#define STORED_STUB 12
197#define STORELR_STUB 13
198#define INVCODE_STUB 14
199
200 /* branch codes */
201#define TAKEN 1
202#define NOTTAKEN 2
203#define NULLDS 3
204
205// asm linkage
206int new_recompile_block(int addr);
207void *get_addr_ht(u_int vaddr);
208void invalidate_block(u_int block);
209void invalidate_addr(u_int addr);
210void remove_hash(int vaddr);
211void jump_vaddr();
212void dyna_linker();
213void dyna_linker_ds();
214void verify_code();
215void verify_code_vm();
216void verify_code_ds();
217void cc_interrupt();
218void fp_exception();
219void fp_exception_ds();
220void jump_syscall();
221void jump_syscall_hle();
222void jump_eret();
223void jump_hlecall();
224void jump_intcall();
225void new_dyna_leave();
226
227// TLB
228void TLBWI_new();
229void TLBWR_new();
230void read_nomem_new();
231void read_nomemb_new();
232void read_nomemh_new();
233void read_nomemd_new();
234void write_nomem_new();
235void write_nomemb_new();
236void write_nomemh_new();
237void write_nomemd_new();
238void write_rdram_new();
239void write_rdramb_new();
240void write_rdramh_new();
241void write_rdramd_new();
242extern u_int memory_map[1048576];
243
244// Needed by assembler
245void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
246void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
247void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
248void load_all_regs(signed char i_regmap[]);
249void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
250void load_regs_entry(int t);
251void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
252
253int tracedebug=0;
254
255//#define DEBUG_CYCLE_COUNT 1
256
257void nullf() {}
258//#define assem_debug printf
259//#define inv_debug printf
260#define assem_debug nullf
261#define inv_debug nullf
262
263static void tlb_hacks()
264{
265#ifndef DISABLE_TLB
266 // Goldeneye hack
267 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
268 {
269 u_int addr;
270 int n;
271 switch (ROM_HEADER->Country_code&0xFF)
272 {
273 case 0x45: // U
274 addr=0x34b30;
275 break;
276 case 0x4A: // J
277 addr=0x34b70;
278 break;
279 case 0x50: // E
280 addr=0x329f0;
281 break;
282 default:
283 // Unknown country code
284 addr=0;
285 break;
286 }
287 u_int rom_addr=(u_int)rom;
288 #ifdef ROM_COPY
289 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
290 // in the lower 4G of memory to use this hack. Copy it if necessary.
291 if((void *)rom>(void *)0xffffffff) {
292 munmap(ROM_COPY, 67108864);
293 if(mmap(ROM_COPY, 12582912,
294 PROT_READ | PROT_WRITE,
295 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
296 -1, 0) <= 0) {printf("mmap() failed\n");}
297 memcpy(ROM_COPY,rom,12582912);
298 rom_addr=(u_int)ROM_COPY;
299 }
300 #endif
301 if(addr) {
302 for(n=0x7F000;n<0x80000;n++) {
303 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
304 }
305 }
306 }
307#endif
308}
309
310static u_int get_page(u_int vaddr)
311{
312#ifndef PCSX
313 u_int page=(vaddr^0x80000000)>>12;
314#else
315 u_int page=vaddr&~0xe0000000;
316 if (page < 0x1000000)
317 page &= ~0x0e00000; // RAM mirrors
318 page>>=12;
319#endif
320#ifndef DISABLE_TLB
321 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
322#endif
323 if(page>2048) page=2048+(page&2047);
324 return page;
325}
326
327static u_int get_vpage(u_int vaddr)
328{
329 u_int vpage=(vaddr^0x80000000)>>12;
330#ifndef DISABLE_TLB
331 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
332#endif
333 if(vpage>2048) vpage=2048+(vpage&2047);
334 return vpage;
335}
336
337// Get address from virtual address
338// This is called from the recompiled JR/JALR instructions
339void *get_addr(u_int vaddr)
340{
341 u_int page=get_page(vaddr);
342 u_int vpage=get_vpage(vaddr);
343 struct ll_entry *head;
344 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
345 head=jump_in[page];
346 while(head!=NULL) {
347 if(head->vaddr==vaddr&&head->reg32==0) {
348 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
349 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
350 ht_bin[3]=ht_bin[1];
351 ht_bin[2]=ht_bin[0];
352 ht_bin[1]=(int)head->addr;
353 ht_bin[0]=vaddr;
354 return head->addr;
355 }
356 head=head->next;
357 }
358 head=jump_dirty[vpage];
359 while(head!=NULL) {
360 if(head->vaddr==vaddr&&head->reg32==0) {
361 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
362 // Don't restore blocks which are about to expire from the cache
363 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
364 if(verify_dirty(head->addr)) {
365 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
366 invalid_code[vaddr>>12]=0;
367 memory_map[vaddr>>12]|=0x40000000;
368 if(vpage<2048) {
369#ifndef DISABLE_TLB
370 if(tlb_LUT_r[vaddr>>12]) {
371 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
372 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
373 }
374#endif
375 restore_candidate[vpage>>3]|=1<<(vpage&7);
376 }
377 else restore_candidate[page>>3]|=1<<(page&7);
378 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
379 if(ht_bin[0]==vaddr) {
380 ht_bin[1]=(int)head->addr; // Replace existing entry
381 }
382 else
383 {
384 ht_bin[3]=ht_bin[1];
385 ht_bin[2]=ht_bin[0];
386 ht_bin[1]=(int)head->addr;
387 ht_bin[0]=vaddr;
388 }
389 return head->addr;
390 }
391 }
392 head=head->next;
393 }
394 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
395 int r=new_recompile_block(vaddr);
396 if(r==0) return get_addr(vaddr);
397 // Execute in unmapped page, generate pagefault execption
398 Status|=2;
399 Cause=(vaddr<<31)|0x8;
400 EPC=(vaddr&1)?vaddr-5:vaddr;
401 BadVAddr=(vaddr&~1);
402 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
403 EntryHi=BadVAddr&0xFFFFE000;
404 return get_addr_ht(0x80000000);
405}
406// Look up address in hash table first
407void *get_addr_ht(u_int vaddr)
408{
409 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
410 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
411 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
412 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
413 return get_addr(vaddr);
414}
415
416void *get_addr_32(u_int vaddr,u_int flags)
417{
418#ifdef FORCE32
419 return get_addr(vaddr);
420#else
421 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
422 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
423 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
424 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
425 u_int page=get_page(vaddr);
426 u_int vpage=get_vpage(vaddr);
427 struct ll_entry *head;
428 head=jump_in[page];
429 while(head!=NULL) {
430 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
431 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
432 if(head->reg32==0) {
433 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
434 if(ht_bin[0]==-1) {
435 ht_bin[1]=(int)head->addr;
436 ht_bin[0]=vaddr;
437 }else if(ht_bin[2]==-1) {
438 ht_bin[3]=(int)head->addr;
439 ht_bin[2]=vaddr;
440 }
441 //ht_bin[3]=ht_bin[1];
442 //ht_bin[2]=ht_bin[0];
443 //ht_bin[1]=(int)head->addr;
444 //ht_bin[0]=vaddr;
445 }
446 return head->addr;
447 }
448 head=head->next;
449 }
450 head=jump_dirty[vpage];
451 while(head!=NULL) {
452 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
453 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
454 // Don't restore blocks which are about to expire from the cache
455 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
456 if(verify_dirty(head->addr)) {
457 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
458 invalid_code[vaddr>>12]=0;
459 memory_map[vaddr>>12]|=0x40000000;
460 if(vpage<2048) {
461#ifndef DISABLE_TLB
462 if(tlb_LUT_r[vaddr>>12]) {
463 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
464 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
465 }
466#endif
467 restore_candidate[vpage>>3]|=1<<(vpage&7);
468 }
469 else restore_candidate[page>>3]|=1<<(page&7);
470 if(head->reg32==0) {
471 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
472 if(ht_bin[0]==-1) {
473 ht_bin[1]=(int)head->addr;
474 ht_bin[0]=vaddr;
475 }else if(ht_bin[2]==-1) {
476 ht_bin[3]=(int)head->addr;
477 ht_bin[2]=vaddr;
478 }
479 //ht_bin[3]=ht_bin[1];
480 //ht_bin[2]=ht_bin[0];
481 //ht_bin[1]=(int)head->addr;
482 //ht_bin[0]=vaddr;
483 }
484 return head->addr;
485 }
486 }
487 head=head->next;
488 }
489 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
490 int r=new_recompile_block(vaddr);
491 if(r==0) return get_addr(vaddr);
492 // Execute in unmapped page, generate pagefault execption
493 Status|=2;
494 Cause=(vaddr<<31)|0x8;
495 EPC=(vaddr&1)?vaddr-5:vaddr;
496 BadVAddr=(vaddr&~1);
497 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
498 EntryHi=BadVAddr&0xFFFFE000;
499 return get_addr_ht(0x80000000);
500#endif
501}
502
503void clear_all_regs(signed char regmap[])
504{
505 int hr;
506 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
507}
508
509signed char get_reg(signed char regmap[],int r)
510{
511 int hr;
512 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
513 return -1;
514}
515
516// Find a register that is available for two consecutive cycles
517signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
518{
519 int hr;
520 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
521 return -1;
522}
523
524int count_free_regs(signed char regmap[])
525{
526 int count=0;
527 int hr;
528 for(hr=0;hr<HOST_REGS;hr++)
529 {
530 if(hr!=EXCLUDE_REG) {
531 if(regmap[hr]<0) count++;
532 }
533 }
534 return count;
535}
536
537void dirty_reg(struct regstat *cur,signed char reg)
538{
539 int hr;
540 if(!reg) return;
541 for (hr=0;hr<HOST_REGS;hr++) {
542 if((cur->regmap[hr]&63)==reg) {
543 cur->dirty|=1<<hr;
544 }
545 }
546}
547
548// If we dirty the lower half of a 64 bit register which is now being
549// sign-extended, we need to dump the upper half.
550// Note: Do this only after completion of the instruction, because
551// some instructions may need to read the full 64-bit value even if
552// overwriting it (eg SLTI, DSRA32).
553static void flush_dirty_uppers(struct regstat *cur)
554{
555 int hr,reg;
556 for (hr=0;hr<HOST_REGS;hr++) {
557 if((cur->dirty>>hr)&1) {
558 reg=cur->regmap[hr];
559 if(reg>=64)
560 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
561 }
562 }
563}
564
565void set_const(struct regstat *cur,signed char reg,uint64_t value)
566{
567 int hr;
568 if(!reg) return;
569 for (hr=0;hr<HOST_REGS;hr++) {
570 if(cur->regmap[hr]==reg) {
571 cur->isconst|=1<<hr;
572 cur->constmap[hr]=value;
573 }
574 else if((cur->regmap[hr]^64)==reg) {
575 cur->isconst|=1<<hr;
576 cur->constmap[hr]=value>>32;
577 }
578 }
579}
580
581void clear_const(struct regstat *cur,signed char reg)
582{
583 int hr;
584 if(!reg) return;
585 for (hr=0;hr<HOST_REGS;hr++) {
586 if((cur->regmap[hr]&63)==reg) {
587 cur->isconst&=~(1<<hr);
588 }
589 }
590}
591
592int is_const(struct regstat *cur,signed char reg)
593{
594 int hr;
595 if(!reg) return 1;
596 for (hr=0;hr<HOST_REGS;hr++) {
597 if((cur->regmap[hr]&63)==reg) {
598 return (cur->isconst>>hr)&1;
599 }
600 }
601 return 0;
602}
603uint64_t get_const(struct regstat *cur,signed char reg)
604{
605 int hr;
606 if(!reg) return 0;
607 for (hr=0;hr<HOST_REGS;hr++) {
608 if(cur->regmap[hr]==reg) {
609 return cur->constmap[hr];
610 }
611 }
612 printf("Unknown constant in r%d\n",reg);
613 exit(1);
614}
615
616// Least soon needed registers
617// Look at the next ten instructions and see which registers
618// will be used. Try not to reallocate these.
619void lsn(u_char hsn[], int i, int *preferred_reg)
620{
621 int j;
622 int b=-1;
623 for(j=0;j<9;j++)
624 {
625 if(i+j>=slen) {
626 j=slen-i-1;
627 break;
628 }
629 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
630 {
631 // Don't go past an unconditonal jump
632 j++;
633 break;
634 }
635 }
636 for(;j>=0;j--)
637 {
638 if(rs1[i+j]) hsn[rs1[i+j]]=j;
639 if(rs2[i+j]) hsn[rs2[i+j]]=j;
640 if(rt1[i+j]) hsn[rt1[i+j]]=j;
641 if(rt2[i+j]) hsn[rt2[i+j]]=j;
642 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
643 // Stores can allocate zero
644 hsn[rs1[i+j]]=j;
645 hsn[rs2[i+j]]=j;
646 }
647 // On some architectures stores need invc_ptr
648 #if defined(HOST_IMM8)
649 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
650 hsn[INVCP]=j;
651 }
652 #endif
653 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
654 {
655 hsn[CCREG]=j;
656 b=j;
657 }
658 }
659 if(b>=0)
660 {
661 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
662 {
663 // Follow first branch
664 int t=(ba[i+b]-start)>>2;
665 j=7-b;if(t+j>=slen) j=slen-t-1;
666 for(;j>=0;j--)
667 {
668 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
669 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
670 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
671 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
672 }
673 }
674 // TODO: preferred register based on backward branch
675 }
676 // Delay slot should preferably not overwrite branch conditions or cycle count
677 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
678 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
679 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
680 hsn[CCREG]=1;
681 // ...or hash tables
682 hsn[RHASH]=1;
683 hsn[RHTBL]=1;
684 }
685 // Coprocessor load/store needs FTEMP, even if not declared
686 if(itype[i]==C1LS||itype[i]==C2LS) {
687 hsn[FTEMP]=0;
688 }
689 // Load L/R also uses FTEMP as a temporary register
690 if(itype[i]==LOADLR) {
691 hsn[FTEMP]=0;
692 }
693 // Also SWL/SWR/SDL/SDR
694 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
695 hsn[FTEMP]=0;
696 }
697 // Don't remove the TLB registers either
698 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
699 hsn[TLREG]=0;
700 }
701 // Don't remove the miniht registers
702 if(itype[i]==UJUMP||itype[i]==RJUMP)
703 {
704 hsn[RHASH]=0;
705 hsn[RHTBL]=0;
706 }
707}
708
709// We only want to allocate registers if we're going to use them again soon
710int needed_again(int r, int i)
711{
712 int j;
713 int b=-1;
714 int rn=10;
715 int hr;
716 u_char hsn[MAXREG+1];
717 int preferred_reg;
718
719 memset(hsn,10,sizeof(hsn));
720 lsn(hsn,i,&preferred_reg);
721
722 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
723 {
724 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
725 return 0; // Don't need any registers if exiting the block
726 }
727 for(j=0;j<9;j++)
728 {
729 if(i+j>=slen) {
730 j=slen-i-1;
731 break;
732 }
733 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
734 {
735 // Don't go past an unconditonal jump
736 j++;
737 break;
738 }
739 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
740 {
741 break;
742 }
743 }
744 for(;j>=1;j--)
745 {
746 if(rs1[i+j]==r) rn=j;
747 if(rs2[i+j]==r) rn=j;
748 if((unneeded_reg[i+j]>>r)&1) rn=10;
749 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
750 {
751 b=j;
752 }
753 }
754 /*
755 if(b>=0)
756 {
757 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
758 {
759 // Follow first branch
760 int o=rn;
761 int t=(ba[i+b]-start)>>2;
762 j=7-b;if(t+j>=slen) j=slen-t-1;
763 for(;j>=0;j--)
764 {
765 if(!((unneeded_reg[t+j]>>r)&1)) {
766 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
767 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
768 }
769 else rn=o;
770 }
771 }
772 }*/
773 for(hr=0;hr<HOST_REGS;hr++) {
774 if(hr!=EXCLUDE_REG) {
775 if(rn<hsn[hr]) return 1;
776 }
777 }
778 return 0;
779}
780
781// Try to match register allocations at the end of a loop with those
782// at the beginning
783int loop_reg(int i, int r, int hr)
784{
785 int j,k;
786 for(j=0;j<9;j++)
787 {
788 if(i+j>=slen) {
789 j=slen-i-1;
790 break;
791 }
792 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
793 {
794 // Don't go past an unconditonal jump
795 j++;
796 break;
797 }
798 }
799 k=0;
800 if(i>0){
801 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
802 k--;
803 }
804 for(;k<j;k++)
805 {
806 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
807 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
808 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
809 {
810 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
811 {
812 int t=(ba[i+k]-start)>>2;
813 int reg=get_reg(regs[t].regmap_entry,r);
814 if(reg>=0) return reg;
815 //reg=get_reg(regs[t+1].regmap_entry,r);
816 //if(reg>=0) return reg;
817 }
818 }
819 }
820 return hr;
821}
822
823
824// Allocate every register, preserving source/target regs
825void alloc_all(struct regstat *cur,int i)
826{
827 int hr;
828
829 for(hr=0;hr<HOST_REGS;hr++) {
830 if(hr!=EXCLUDE_REG) {
831 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
832 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
833 {
834 cur->regmap[hr]=-1;
835 cur->dirty&=~(1<<hr);
836 }
837 // Don't need zeros
838 if((cur->regmap[hr]&63)==0)
839 {
840 cur->regmap[hr]=-1;
841 cur->dirty&=~(1<<hr);
842 }
843 }
844 }
845}
846
847
848void div64(int64_t dividend,int64_t divisor)
849{
850 lo=dividend/divisor;
851 hi=dividend%divisor;
852 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
853 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
854}
855void divu64(uint64_t dividend,uint64_t divisor)
856{
857 lo=dividend/divisor;
858 hi=dividend%divisor;
859 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
860 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
861}
862
863void mult64(uint64_t m1,uint64_t m2)
864{
865 unsigned long long int op1, op2, op3, op4;
866 unsigned long long int result1, result2, result3, result4;
867 unsigned long long int temp1, temp2, temp3, temp4;
868 int sign = 0;
869
870 if (m1 < 0)
871 {
872 op2 = -m1;
873 sign = 1 - sign;
874 }
875 else op2 = m1;
876 if (m2 < 0)
877 {
878 op4 = -m2;
879 sign = 1 - sign;
880 }
881 else op4 = m2;
882
883 op1 = op2 & 0xFFFFFFFF;
884 op2 = (op2 >> 32) & 0xFFFFFFFF;
885 op3 = op4 & 0xFFFFFFFF;
886 op4 = (op4 >> 32) & 0xFFFFFFFF;
887
888 temp1 = op1 * op3;
889 temp2 = (temp1 >> 32) + op1 * op4;
890 temp3 = op2 * op3;
891 temp4 = (temp3 >> 32) + op2 * op4;
892
893 result1 = temp1 & 0xFFFFFFFF;
894 result2 = temp2 + (temp3 & 0xFFFFFFFF);
895 result3 = (result2 >> 32) + temp4;
896 result4 = (result3 >> 32);
897
898 lo = result1 | (result2 << 32);
899 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
900 if (sign)
901 {
902 hi = ~hi;
903 if (!lo) hi++;
904 else lo = ~lo + 1;
905 }
906}
907
908void multu64(uint64_t m1,uint64_t m2)
909{
910 unsigned long long int op1, op2, op3, op4;
911 unsigned long long int result1, result2, result3, result4;
912 unsigned long long int temp1, temp2, temp3, temp4;
913
914 op1 = m1 & 0xFFFFFFFF;
915 op2 = (m1 >> 32) & 0xFFFFFFFF;
916 op3 = m2 & 0xFFFFFFFF;
917 op4 = (m2 >> 32) & 0xFFFFFFFF;
918
919 temp1 = op1 * op3;
920 temp2 = (temp1 >> 32) + op1 * op4;
921 temp3 = op2 * op3;
922 temp4 = (temp3 >> 32) + op2 * op4;
923
924 result1 = temp1 & 0xFFFFFFFF;
925 result2 = temp2 + (temp3 & 0xFFFFFFFF);
926 result3 = (result2 >> 32) + temp4;
927 result4 = (result3 >> 32);
928
929 lo = result1 | (result2 << 32);
930 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
931
932 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
933 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
934}
935
936uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
937{
938 if(bits) {
939 original<<=64-bits;
940 original>>=64-bits;
941 loaded<<=bits;
942 original|=loaded;
943 }
944 else original=loaded;
945 return original;
946}
947uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
948{
949 if(bits^56) {
950 original>>=64-(bits^56);
951 original<<=64-(bits^56);
952 loaded>>=bits^56;
953 original|=loaded;
954 }
955 else original=loaded;
956 return original;
957}
958
959#ifdef __i386__
960#include "assem_x86.c"
961#endif
962#ifdef __x86_64__
963#include "assem_x64.c"
964#endif
965#ifdef __arm__
966#include "assem_arm.c"
967#endif
968
969// Add virtual address mapping to linked list
970void ll_add(struct ll_entry **head,int vaddr,void *addr)
971{
972 struct ll_entry *new_entry;
973 new_entry=malloc(sizeof(struct ll_entry));
974 assert(new_entry!=NULL);
975 new_entry->vaddr=vaddr;
976 new_entry->reg32=0;
977 new_entry->addr=addr;
978 new_entry->next=*head;
979 *head=new_entry;
980}
981
982// Add virtual address mapping for 32-bit compiled block
983void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
984{
985 ll_add(head,vaddr,addr);
986#ifndef FORCE32
987 (*head)->reg32=reg32;
988#endif
989}
990
991// Check if an address is already compiled
992// but don't return addresses which are about to expire from the cache
993void *check_addr(u_int vaddr)
994{
995 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
996 if(ht_bin[0]==vaddr) {
997 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
998 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
999 }
1000 if(ht_bin[2]==vaddr) {
1001 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1002 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1003 }
1004 u_int page=get_page(vaddr);
1005 struct ll_entry *head;
1006 head=jump_in[page];
1007 while(head!=NULL) {
1008 if(head->vaddr==vaddr&&head->reg32==0) {
1009 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1010 // Update existing entry with current address
1011 if(ht_bin[0]==vaddr) {
1012 ht_bin[1]=(int)head->addr;
1013 return head->addr;
1014 }
1015 if(ht_bin[2]==vaddr) {
1016 ht_bin[3]=(int)head->addr;
1017 return head->addr;
1018 }
1019 // Insert into hash table with low priority.
1020 // Don't evict existing entries, as they are probably
1021 // addresses that are being accessed frequently.
1022 if(ht_bin[0]==-1) {
1023 ht_bin[1]=(int)head->addr;
1024 ht_bin[0]=vaddr;
1025 }else if(ht_bin[2]==-1) {
1026 ht_bin[3]=(int)head->addr;
1027 ht_bin[2]=vaddr;
1028 }
1029 return head->addr;
1030 }
1031 }
1032 head=head->next;
1033 }
1034 return 0;
1035}
1036
1037void remove_hash(int vaddr)
1038{
1039 //printf("remove hash: %x\n",vaddr);
1040 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1041 if(ht_bin[2]==vaddr) {
1042 ht_bin[2]=ht_bin[3]=-1;
1043 }
1044 if(ht_bin[0]==vaddr) {
1045 ht_bin[0]=ht_bin[2];
1046 ht_bin[1]=ht_bin[3];
1047 ht_bin[2]=ht_bin[3]=-1;
1048 }
1049}
1050
1051void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1052{
1053 struct ll_entry *next;
1054 while(*head) {
1055 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1056 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1057 {
1058 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1059 remove_hash((*head)->vaddr);
1060 next=(*head)->next;
1061 free(*head);
1062 *head=next;
1063 }
1064 else
1065 {
1066 head=&((*head)->next);
1067 }
1068 }
1069}
1070
1071// Remove all entries from linked list
1072void ll_clear(struct ll_entry **head)
1073{
1074 struct ll_entry *cur;
1075 struct ll_entry *next;
1076 if(cur=*head) {
1077 *head=0;
1078 while(cur) {
1079 next=cur->next;
1080 free(cur);
1081 cur=next;
1082 }
1083 }
1084}
1085
1086// Dereference the pointers and remove if it matches
1087void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1088{
1089 u_int old_host_addr=0;
1090 while(head) {
1091 int ptr=get_pointer(head->addr);
1092 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1093 if(((ptr>>shift)==(addr>>shift)) ||
1094 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1095 {
1096 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1097 u_int host_addr=(u_int)kill_pointer(head->addr);
1098
1099 if((host_addr>>12)!=(old_host_addr>>12)) {
1100 #ifdef __arm__
1101 __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1102 #endif
1103 old_host_addr=host_addr;
1104 }
1105 }
1106 head=head->next;
1107 }
1108 #ifdef __arm__
1109 if (old_host_addr)
1110 __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1111 #endif
1112}
1113
1114// This is called when we write to a compiled block (see do_invstub)
1115void invalidate_page(u_int page)
1116{
1117 struct ll_entry *head;
1118 struct ll_entry *next;
1119 u_int old_host_addr=0;
1120 head=jump_in[page];
1121 jump_in[page]=0;
1122 while(head!=NULL) {
1123 inv_debug("INVALIDATE: %x\n",head->vaddr);
1124 remove_hash(head->vaddr);
1125 next=head->next;
1126 free(head);
1127 head=next;
1128 }
1129 head=jump_out[page];
1130 jump_out[page]=0;
1131 while(head!=NULL) {
1132 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1133 u_int host_addr=(u_int)kill_pointer(head->addr);
1134
1135 if((host_addr>>12)!=(old_host_addr>>12)) {
1136 #ifdef __arm__
1137 __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1138 #endif
1139 old_host_addr=host_addr;
1140 }
1141 next=head->next;
1142 free(head);
1143 head=next;
1144 }
1145 #ifdef __arm__
1146 if (old_host_addr)
1147 __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1148 #endif
1149}
1150void invalidate_block(u_int block)
1151{
1152 u_int page=get_page(block<<12);
1153 u_int vpage=get_vpage(block<<12);
1154 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1155 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1156 u_int first,last;
1157 first=last=page;
1158 struct ll_entry *head;
1159 head=jump_dirty[vpage];
1160 //printf("page=%d vpage=%d\n",page,vpage);
1161 while(head!=NULL) {
1162 u_int start,end;
1163 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1164 get_bounds((int)head->addr,&start,&end);
1165 //printf("start: %x end: %x\n",start,end);
1166 if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
1167 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1168 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1169 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1170 }
1171 }
1172#ifndef DISABLE_TLB
1173 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1174 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1175 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1176 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1177 }
1178 }
1179#endif
1180 }
1181 head=head->next;
1182 }
1183 //printf("first=%d last=%d\n",first,last);
1184 invalidate_page(page);
1185 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1186 assert(last<page+5);
1187 // Invalidate the adjacent pages if a block crosses a 4K boundary
1188 while(first<page) {
1189 invalidate_page(first);
1190 first++;
1191 }
1192 for(first=page+1;first<last;first++) {
1193 invalidate_page(first);
1194 }
1195
1196 // Don't trap writes
1197 invalid_code[block]=1;
1198#ifndef DISABLE_TLB
1199 // If there is a valid TLB entry for this page, remove write protect
1200 if(tlb_LUT_w[block]) {
1201 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1202 // CHECK: Is this right?
1203 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1204 u_int real_block=tlb_LUT_w[block]>>12;
1205 invalid_code[real_block]=1;
1206 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1207 }
1208 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1209#endif
1210
1211 #ifdef USE_MINI_HT
1212 memset(mini_ht,-1,sizeof(mini_ht));
1213 #endif
1214}
1215void invalidate_addr(u_int addr)
1216{
1217 invalidate_block(addr>>12);
1218}
1219void invalidate_all_pages()
1220{
1221 u_int page,n;
1222 for(page=0;page<4096;page++)
1223 invalidate_page(page);
1224 for(page=0;page<1048576;page++)
1225 if(!invalid_code[page]) {
1226 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1227 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1228 }
1229 #ifdef __arm__
1230 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1231 #endif
1232 #ifdef USE_MINI_HT
1233 memset(mini_ht,-1,sizeof(mini_ht));
1234 #endif
1235 #ifndef DISABLE_TLB
1236 // TLB
1237 for(page=0;page<0x100000;page++) {
1238 if(tlb_LUT_r[page]) {
1239 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1240 if(!tlb_LUT_w[page]||!invalid_code[page])
1241 memory_map[page]|=0x40000000; // Write protect
1242 }
1243 else memory_map[page]=-1;
1244 if(page==0x80000) page=0xC0000;
1245 }
1246 tlb_hacks();
1247 #endif
1248}
1249
1250// Add an entry to jump_out after making a link
1251void add_link(u_int vaddr,void *src)
1252{
1253 u_int page=get_page(vaddr);
1254 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1255 ll_add(jump_out+page,vaddr,src);
1256 //int ptr=get_pointer(src);
1257 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1258}
1259
1260// If a code block was found to be unmodified (bit was set in
1261// restore_candidate) and it remains unmodified (bit is clear
1262// in invalid_code) then move the entries for that 4K page from
1263// the dirty list to the clean list.
1264void clean_blocks(u_int page)
1265{
1266 struct ll_entry *head;
1267 inv_debug("INV: clean_blocks page=%d\n",page);
1268 head=jump_dirty[page];
1269 while(head!=NULL) {
1270 if(!invalid_code[head->vaddr>>12]) {
1271 // Don't restore blocks which are about to expire from the cache
1272 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1273 u_int start,end;
1274 if(verify_dirty((int)head->addr)) {
1275 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1276 u_int i;
1277 u_int inv=0;
1278 get_bounds((int)head->addr,&start,&end);
1279 if(start-(u_int)rdram<RAM_SIZE) {
1280 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1281 inv|=invalid_code[i];
1282 }
1283 }
1284 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1285 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1286 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1287 if(addr<start||addr>=end) inv=1;
1288 }
1289 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1290 inv=1;
1291 }
1292 if(!inv) {
1293 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1294 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1295 u_int ppage=page;
1296#ifndef DISABLE_TLB
1297 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1298#endif
1299 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1300 //printf("page=%x, addr=%x\n",page,head->vaddr);
1301 //assert(head->vaddr>>12==(page|0x80000));
1302 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1303 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1304 if(!head->reg32) {
1305 if(ht_bin[0]==head->vaddr) {
1306 ht_bin[1]=(int)clean_addr; // Replace existing entry
1307 }
1308 if(ht_bin[2]==head->vaddr) {
1309 ht_bin[3]=(int)clean_addr; // Replace existing entry
1310 }
1311 }
1312 }
1313 }
1314 }
1315 }
1316 }
1317 head=head->next;
1318 }
1319}
1320
1321
1322void mov_alloc(struct regstat *current,int i)
1323{
1324 // Note: Don't need to actually alloc the source registers
1325 if((~current->is32>>rs1[i])&1) {
1326 //alloc_reg64(current,i,rs1[i]);
1327 alloc_reg64(current,i,rt1[i]);
1328 current->is32&=~(1LL<<rt1[i]);
1329 } else {
1330 //alloc_reg(current,i,rs1[i]);
1331 alloc_reg(current,i,rt1[i]);
1332 current->is32|=(1LL<<rt1[i]);
1333 }
1334 clear_const(current,rs1[i]);
1335 clear_const(current,rt1[i]);
1336 dirty_reg(current,rt1[i]);
1337}
1338
1339void shiftimm_alloc(struct regstat *current,int i)
1340{
1341 clear_const(current,rs1[i]);
1342 clear_const(current,rt1[i]);
1343 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1344 {
1345 if(rt1[i]) {
1346 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1347 else lt1[i]=rs1[i];
1348 alloc_reg(current,i,rt1[i]);
1349 current->is32|=1LL<<rt1[i];
1350 dirty_reg(current,rt1[i]);
1351 }
1352 }
1353 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1354 {
1355 if(rt1[i]) {
1356 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1357 alloc_reg64(current,i,rt1[i]);
1358 current->is32&=~(1LL<<rt1[i]);
1359 dirty_reg(current,rt1[i]);
1360 }
1361 }
1362 if(opcode2[i]==0x3c) // DSLL32
1363 {
1364 if(rt1[i]) {
1365 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1366 alloc_reg64(current,i,rt1[i]);
1367 current->is32&=~(1LL<<rt1[i]);
1368 dirty_reg(current,rt1[i]);
1369 }
1370 }
1371 if(opcode2[i]==0x3e) // DSRL32
1372 {
1373 if(rt1[i]) {
1374 alloc_reg64(current,i,rs1[i]);
1375 if(imm[i]==32) {
1376 alloc_reg64(current,i,rt1[i]);
1377 current->is32&=~(1LL<<rt1[i]);
1378 } else {
1379 alloc_reg(current,i,rt1[i]);
1380 current->is32|=1LL<<rt1[i];
1381 }
1382 dirty_reg(current,rt1[i]);
1383 }
1384 }
1385 if(opcode2[i]==0x3f) // DSRA32
1386 {
1387 if(rt1[i]) {
1388 alloc_reg64(current,i,rs1[i]);
1389 alloc_reg(current,i,rt1[i]);
1390 current->is32|=1LL<<rt1[i];
1391 dirty_reg(current,rt1[i]);
1392 }
1393 }
1394}
1395
1396void shift_alloc(struct regstat *current,int i)
1397{
1398 if(rt1[i]) {
1399 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1400 {
1401 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1402 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1403 alloc_reg(current,i,rt1[i]);
1404 if(rt1[i]==rs2[i]) alloc_reg_temp(current,i,-1);
1405 current->is32|=1LL<<rt1[i];
1406 } else { // DSLLV/DSRLV/DSRAV
1407 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1408 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1409 alloc_reg64(current,i,rt1[i]);
1410 current->is32&=~(1LL<<rt1[i]);
1411 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1412 alloc_reg_temp(current,i,-1);
1413 }
1414 clear_const(current,rs1[i]);
1415 clear_const(current,rs2[i]);
1416 clear_const(current,rt1[i]);
1417 dirty_reg(current,rt1[i]);
1418 }
1419}
1420
1421void alu_alloc(struct regstat *current,int i)
1422{
1423 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1424 if(rt1[i]) {
1425 if(rs1[i]&&rs2[i]) {
1426 alloc_reg(current,i,rs1[i]);
1427 alloc_reg(current,i,rs2[i]);
1428 }
1429 else {
1430 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1431 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1432 }
1433 alloc_reg(current,i,rt1[i]);
1434 }
1435 current->is32|=1LL<<rt1[i];
1436 }
1437 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1438 if(rt1[i]) {
1439 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1440 {
1441 alloc_reg64(current,i,rs1[i]);
1442 alloc_reg64(current,i,rs2[i]);
1443 alloc_reg(current,i,rt1[i]);
1444 } else {
1445 alloc_reg(current,i,rs1[i]);
1446 alloc_reg(current,i,rs2[i]);
1447 alloc_reg(current,i,rt1[i]);
1448 }
1449 }
1450 current->is32|=1LL<<rt1[i];
1451 }
1452 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1453 if(rt1[i]) {
1454 if(rs1[i]&&rs2[i]) {
1455 alloc_reg(current,i,rs1[i]);
1456 alloc_reg(current,i,rs2[i]);
1457 }
1458 else
1459 {
1460 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1461 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1462 }
1463 alloc_reg(current,i,rt1[i]);
1464 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1465 {
1466 if(!((current->uu>>rt1[i])&1)) {
1467 alloc_reg64(current,i,rt1[i]);
1468 }
1469 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1470 if(rs1[i]&&rs2[i]) {
1471 alloc_reg64(current,i,rs1[i]);
1472 alloc_reg64(current,i,rs2[i]);
1473 }
1474 else
1475 {
1476 // Is is really worth it to keep 64-bit values in registers?
1477 #ifdef NATIVE_64BIT
1478 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1479 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1480 #endif
1481 }
1482 }
1483 current->is32&=~(1LL<<rt1[i]);
1484 } else {
1485 current->is32|=1LL<<rt1[i];
1486 }
1487 }
1488 }
1489 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1490 if(rt1[i]) {
1491 if(rs1[i]&&rs2[i]) {
1492 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1493 alloc_reg64(current,i,rs1[i]);
1494 alloc_reg64(current,i,rs2[i]);
1495 alloc_reg64(current,i,rt1[i]);
1496 } else {
1497 alloc_reg(current,i,rs1[i]);
1498 alloc_reg(current,i,rs2[i]);
1499 alloc_reg(current,i,rt1[i]);
1500 }
1501 }
1502 else {
1503 alloc_reg(current,i,rt1[i]);
1504 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1505 // DADD used as move, or zeroing
1506 // If we have a 64-bit source, then make the target 64 bits too
1507 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1508 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1509 alloc_reg64(current,i,rt1[i]);
1510 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1511 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1512 alloc_reg64(current,i,rt1[i]);
1513 }
1514 if(opcode2[i]>=0x2e&&rs2[i]) {
1515 // DSUB used as negation - 64-bit result
1516 // If we have a 32-bit register, extend it to 64 bits
1517 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1518 alloc_reg64(current,i,rt1[i]);
1519 }
1520 }
1521 }
1522 if(rs1[i]&&rs2[i]) {
1523 current->is32&=~(1LL<<rt1[i]);
1524 } else if(rs1[i]) {
1525 current->is32&=~(1LL<<rt1[i]);
1526 if((current->is32>>rs1[i])&1)
1527 current->is32|=1LL<<rt1[i];
1528 } else if(rs2[i]) {
1529 current->is32&=~(1LL<<rt1[i]);
1530 if((current->is32>>rs2[i])&1)
1531 current->is32|=1LL<<rt1[i];
1532 } else {
1533 current->is32|=1LL<<rt1[i];
1534 }
1535 }
1536 }
1537 clear_const(current,rs1[i]);
1538 clear_const(current,rs2[i]);
1539 clear_const(current,rt1[i]);
1540 dirty_reg(current,rt1[i]);
1541}
1542
1543void imm16_alloc(struct regstat *current,int i)
1544{
1545 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1546 else lt1[i]=rs1[i];
1547 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1548 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1549 current->is32&=~(1LL<<rt1[i]);
1550 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1551 // TODO: Could preserve the 32-bit flag if the immediate is zero
1552 alloc_reg64(current,i,rt1[i]);
1553 alloc_reg64(current,i,rs1[i]);
1554 }
1555 clear_const(current,rs1[i]);
1556 clear_const(current,rt1[i]);
1557 }
1558 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1559 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1560 current->is32|=1LL<<rt1[i];
1561 clear_const(current,rs1[i]);
1562 clear_const(current,rt1[i]);
1563 }
1564 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1565 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1566 if(rs1[i]!=rt1[i]) {
1567 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1568 alloc_reg64(current,i,rt1[i]);
1569 current->is32&=~(1LL<<rt1[i]);
1570 }
1571 }
1572 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1573 if(is_const(current,rs1[i])) {
1574 int v=get_const(current,rs1[i]);
1575 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1576 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1577 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1578 }
1579 else clear_const(current,rt1[i]);
1580 }
1581 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1582 if(is_const(current,rs1[i])) {
1583 int v=get_const(current,rs1[i]);
1584 set_const(current,rt1[i],v+imm[i]);
1585 }
1586 else clear_const(current,rt1[i]);
1587 current->is32|=1LL<<rt1[i];
1588 }
1589 else {
1590 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1591 current->is32|=1LL<<rt1[i];
1592 }
1593 dirty_reg(current,rt1[i]);
1594}
1595
1596void load_alloc(struct regstat *current,int i)
1597{
1598 clear_const(current,rt1[i]);
1599 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1600 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1601 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1602 if(rt1[i]) {
1603 alloc_reg(current,i,rt1[i]);
1604 if(get_reg(current->regmap,rt1[i])<0) {
1605 // dummy load, but we still need a register to calculate the address
1606 alloc_reg_temp(current,i,-1);
1607 }
1608 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1609 {
1610 current->is32&=~(1LL<<rt1[i]);
1611 alloc_reg64(current,i,rt1[i]);
1612 }
1613 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1614 {
1615 current->is32&=~(1LL<<rt1[i]);
1616 alloc_reg64(current,i,rt1[i]);
1617 alloc_all(current,i);
1618 alloc_reg64(current,i,FTEMP);
1619 }
1620 else current->is32|=1LL<<rt1[i];
1621 dirty_reg(current,rt1[i]);
1622 // If using TLB, need a register for pointer to the mapping table
1623 if(using_tlb) alloc_reg(current,i,TLREG);
1624 // LWL/LWR need a temporary register for the old value
1625 if(opcode[i]==0x22||opcode[i]==0x26)
1626 {
1627 alloc_reg(current,i,FTEMP);
1628 alloc_reg_temp(current,i,-1);
1629 }
1630 }
1631 else
1632 {
1633 // Load to r0 (dummy load)
1634 // but we still need a register to calculate the address
1635 if(opcode[i]==0x22||opcode[i]==0x26)
1636 {
1637 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1638 }
1639 alloc_reg_temp(current,i,-1);
1640 if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1641 {
1642 alloc_all(current,i);
1643 alloc_reg64(current,i,FTEMP);
1644 }
1645 }
1646}
1647
1648void store_alloc(struct regstat *current,int i)
1649{
1650 clear_const(current,rs2[i]);
1651 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1652 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1653 alloc_reg(current,i,rs2[i]);
1654 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1655 alloc_reg64(current,i,rs2[i]);
1656 if(rs2[i]) alloc_reg(current,i,FTEMP);
1657 }
1658 // If using TLB, need a register for pointer to the mapping table
1659 if(using_tlb) alloc_reg(current,i,TLREG);
1660 #if defined(HOST_IMM8)
1661 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1662 else alloc_reg(current,i,INVCP);
1663 #endif
1664 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1665 alloc_reg(current,i,FTEMP);
1666 }
1667 // We need a temporary register for address generation
1668 alloc_reg_temp(current,i,-1);
1669}
1670
1671void c1ls_alloc(struct regstat *current,int i)
1672{
1673 //clear_const(current,rs1[i]); // FIXME
1674 clear_const(current,rt1[i]);
1675 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1676 alloc_reg(current,i,CSREG); // Status
1677 alloc_reg(current,i,FTEMP);
1678 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1679 alloc_reg64(current,i,FTEMP);
1680 }
1681 // If using TLB, need a register for pointer to the mapping table
1682 if(using_tlb) alloc_reg(current,i,TLREG);
1683 #if defined(HOST_IMM8)
1684 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1685 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1686 alloc_reg(current,i,INVCP);
1687 #endif
1688 // We need a temporary register for address generation
1689 alloc_reg_temp(current,i,-1);
1690}
1691
1692void c2ls_alloc(struct regstat *current,int i)
1693{
1694 clear_const(current,rt1[i]);
1695 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1696 alloc_reg(current,i,FTEMP);
1697 // If using TLB, need a register for pointer to the mapping table
1698 if(using_tlb) alloc_reg(current,i,TLREG);
1699 #if defined(HOST_IMM8)
1700 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1701 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1702 alloc_reg(current,i,INVCP);
1703 #endif
1704 // We need a temporary register for address generation
1705 alloc_reg_temp(current,i,-1);
1706}
1707
1708#ifndef multdiv_alloc
1709void multdiv_alloc(struct regstat *current,int i)
1710{
1711 // case 0x18: MULT
1712 // case 0x19: MULTU
1713 // case 0x1A: DIV
1714 // case 0x1B: DIVU
1715 // case 0x1C: DMULT
1716 // case 0x1D: DMULTU
1717 // case 0x1E: DDIV
1718 // case 0x1F: DDIVU
1719 clear_const(current,rs1[i]);
1720 clear_const(current,rs2[i]);
1721 if(rs1[i]&&rs2[i])
1722 {
1723 if((opcode2[i]&4)==0) // 32-bit
1724 {
1725 current->u&=~(1LL<<HIREG);
1726 current->u&=~(1LL<<LOREG);
1727 alloc_reg(current,i,HIREG);
1728 alloc_reg(current,i,LOREG);
1729 alloc_reg(current,i,rs1[i]);
1730 alloc_reg(current,i,rs2[i]);
1731 current->is32|=1LL<<HIREG;
1732 current->is32|=1LL<<LOREG;
1733 dirty_reg(current,HIREG);
1734 dirty_reg(current,LOREG);
1735 }
1736 else // 64-bit
1737 {
1738 current->u&=~(1LL<<HIREG);
1739 current->u&=~(1LL<<LOREG);
1740 current->uu&=~(1LL<<HIREG);
1741 current->uu&=~(1LL<<LOREG);
1742 alloc_reg64(current,i,HIREG);
1743 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1744 alloc_reg64(current,i,rs1[i]);
1745 alloc_reg64(current,i,rs2[i]);
1746 alloc_all(current,i);
1747 current->is32&=~(1LL<<HIREG);
1748 current->is32&=~(1LL<<LOREG);
1749 dirty_reg(current,HIREG);
1750 dirty_reg(current,LOREG);
1751 }
1752 }
1753 else
1754 {
1755 // Multiply by zero is zero.
1756 // MIPS does not have a divide by zero exception.
1757 // The result is undefined, we return zero.
1758 alloc_reg(current,i,HIREG);
1759 alloc_reg(current,i,LOREG);
1760 current->is32|=1LL<<HIREG;
1761 current->is32|=1LL<<LOREG;
1762 dirty_reg(current,HIREG);
1763 dirty_reg(current,LOREG);
1764 }
1765}
1766#endif
1767
1768void cop0_alloc(struct regstat *current,int i)
1769{
1770 if(opcode2[i]==0) // MFC0
1771 {
1772 if(rt1[i]) {
1773 clear_const(current,rt1[i]);
1774 alloc_all(current,i);
1775 alloc_reg(current,i,rt1[i]);
1776 current->is32|=1LL<<rt1[i];
1777 dirty_reg(current,rt1[i]);
1778 }
1779 }
1780 else if(opcode2[i]==4) // MTC0
1781 {
1782 if(rs1[i]){
1783 clear_const(current,rs1[i]);
1784 alloc_reg(current,i,rs1[i]);
1785 alloc_all(current,i);
1786 }
1787 else {
1788 alloc_all(current,i); // FIXME: Keep r0
1789 current->u&=~1LL;
1790 alloc_reg(current,i,0);
1791 }
1792 }
1793 else
1794 {
1795 // TLBR/TLBWI/TLBWR/TLBP/ERET
1796 assert(opcode2[i]==0x10);
1797 alloc_all(current,i);
1798 }
1799}
1800
1801void cop1_alloc(struct regstat *current,int i)
1802{
1803 alloc_reg(current,i,CSREG); // Load status
1804 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1805 {
1806 if(rt1[i]){
1807 clear_const(current,rt1[i]);
1808 if(opcode2[i]==1) {
1809 alloc_reg64(current,i,rt1[i]); // DMFC1
1810 current->is32&=~(1LL<<rt1[i]);
1811 }else{
1812 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1813 current->is32|=1LL<<rt1[i];
1814 }
1815 dirty_reg(current,rt1[i]);
1816 }
1817 alloc_reg_temp(current,i,-1);
1818 }
1819 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1820 {
1821 if(rs1[i]){
1822 clear_const(current,rs1[i]);
1823 if(opcode2[i]==5)
1824 alloc_reg64(current,i,rs1[i]); // DMTC1
1825 else
1826 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1827 alloc_reg_temp(current,i,-1);
1828 }
1829 else {
1830 current->u&=~1LL;
1831 alloc_reg(current,i,0);
1832 alloc_reg_temp(current,i,-1);
1833 }
1834 }
1835}
1836void fconv_alloc(struct regstat *current,int i)
1837{
1838 alloc_reg(current,i,CSREG); // Load status
1839 alloc_reg_temp(current,i,-1);
1840}
1841void float_alloc(struct regstat *current,int i)
1842{
1843 alloc_reg(current,i,CSREG); // Load status
1844 alloc_reg_temp(current,i,-1);
1845}
1846void c2op_alloc(struct regstat *current,int i)
1847{
1848 alloc_reg_temp(current,i,-1);
1849}
1850void fcomp_alloc(struct regstat *current,int i)
1851{
1852 alloc_reg(current,i,CSREG); // Load status
1853 alloc_reg(current,i,FSREG); // Load flags
1854 dirty_reg(current,FSREG); // Flag will be modified
1855 alloc_reg_temp(current,i,-1);
1856}
1857
1858void syscall_alloc(struct regstat *current,int i)
1859{
1860 alloc_cc(current,i);
1861 dirty_reg(current,CCREG);
1862 alloc_all(current,i);
1863 current->isconst=0;
1864}
1865
1866void delayslot_alloc(struct regstat *current,int i)
1867{
1868 switch(itype[i]) {
1869 case UJUMP:
1870 case CJUMP:
1871 case SJUMP:
1872 case RJUMP:
1873 case FJUMP:
1874 case SYSCALL:
1875 case HLECALL:
1876 case SPAN:
1877 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1878 printf("Disabled speculative precompilation\n");
1879 stop_after_jal=1;
1880 break;
1881 case IMM16:
1882 imm16_alloc(current,i);
1883 break;
1884 case LOAD:
1885 case LOADLR:
1886 load_alloc(current,i);
1887 break;
1888 case STORE:
1889 case STORELR:
1890 store_alloc(current,i);
1891 break;
1892 case ALU:
1893 alu_alloc(current,i);
1894 break;
1895 case SHIFT:
1896 shift_alloc(current,i);
1897 break;
1898 case MULTDIV:
1899 multdiv_alloc(current,i);
1900 break;
1901 case SHIFTIMM:
1902 shiftimm_alloc(current,i);
1903 break;
1904 case MOV:
1905 mov_alloc(current,i);
1906 break;
1907 case COP0:
1908 cop0_alloc(current,i);
1909 break;
1910 case COP1:
1911 case COP2:
1912 cop1_alloc(current,i);
1913 break;
1914 case C1LS:
1915 c1ls_alloc(current,i);
1916 break;
1917 case C2LS:
1918 c2ls_alloc(current,i);
1919 break;
1920 case FCONV:
1921 fconv_alloc(current,i);
1922 break;
1923 case FLOAT:
1924 float_alloc(current,i);
1925 break;
1926 case FCOMP:
1927 fcomp_alloc(current,i);
1928 break;
1929 case C2OP:
1930 c2op_alloc(current,i);
1931 break;
1932 }
1933}
1934
1935// Special case where a branch and delay slot span two pages in virtual memory
1936static void pagespan_alloc(struct regstat *current,int i)
1937{
1938 current->isconst=0;
1939 current->wasconst=0;
1940 regs[i].wasconst=0;
1941 alloc_all(current,i);
1942 alloc_cc(current,i);
1943 dirty_reg(current,CCREG);
1944 if(opcode[i]==3) // JAL
1945 {
1946 alloc_reg(current,i,31);
1947 dirty_reg(current,31);
1948 }
1949 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1950 {
1951 alloc_reg(current,i,rs1[i]);
1952 if (rt1[i]!=0) {
1953 alloc_reg(current,i,rt1[i]);
1954 dirty_reg(current,rt1[i]);
1955 }
1956 }
1957 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1958 {
1959 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1960 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1961 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1962 {
1963 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1964 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1965 }
1966 }
1967 else
1968 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1969 {
1970 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1971 if(!((current->is32>>rs1[i])&1))
1972 {
1973 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1974 }
1975 }
1976 else
1977 if(opcode[i]==0x11) // BC1
1978 {
1979 alloc_reg(current,i,FSREG);
1980 alloc_reg(current,i,CSREG);
1981 }
1982 //else ...
1983}
1984
1985add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
1986{
1987 stubs[stubcount][0]=type;
1988 stubs[stubcount][1]=addr;
1989 stubs[stubcount][2]=retaddr;
1990 stubs[stubcount][3]=a;
1991 stubs[stubcount][4]=b;
1992 stubs[stubcount][5]=c;
1993 stubs[stubcount][6]=d;
1994 stubs[stubcount][7]=e;
1995 stubcount++;
1996}
1997
1998// Write out a single register
1999void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2000{
2001 int hr;
2002 for(hr=0;hr<HOST_REGS;hr++) {
2003 if(hr!=EXCLUDE_REG) {
2004 if((regmap[hr]&63)==r) {
2005 if((dirty>>hr)&1) {
2006 if(regmap[hr]<64) {
2007 emit_storereg(r,hr);
2008#ifndef FORCE32
2009 if((is32>>regmap[hr])&1) {
2010 emit_sarimm(hr,31,hr);
2011 emit_storereg(r|64,hr);
2012 }
2013#endif
2014 }else{
2015 emit_storereg(r|64,hr);
2016 }
2017 }
2018 }
2019 }
2020 }
2021}
2022
2023int mchecksum()
2024{
2025 //if(!tracedebug) return 0;
2026 int i;
2027 int sum=0;
2028 for(i=0;i<2097152;i++) {
2029 unsigned int temp=sum;
2030 sum<<=1;
2031 sum|=(~temp)>>31;
2032 sum^=((u_int *)rdram)[i];
2033 }
2034 return sum;
2035}
2036int rchecksum()
2037{
2038 int i;
2039 int sum=0;
2040 for(i=0;i<64;i++)
2041 sum^=((u_int *)reg)[i];
2042 return sum;
2043}
2044void rlist()
2045{
2046 int i;
2047 printf("TRACE: ");
2048 for(i=0;i<32;i++)
2049 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2050 printf("\n");
2051#ifndef DISABLE_COP1
2052 printf("TRACE: ");
2053 for(i=0;i<32;i++)
2054 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2055 printf("\n");
2056#endif
2057}
2058
2059void enabletrace()
2060{
2061 tracedebug=1;
2062}
2063
2064void memdebug(int i)
2065{
2066 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2067 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2068 //rlist();
2069 //if(tracedebug) {
2070 //if(Count>=-2084597794) {
2071 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2072 //if(0) {
2073 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2074 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2075 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2076 rlist();
2077 #ifdef __i386__
2078 printf("TRACE: %x\n",(&i)[-1]);
2079 #endif
2080 #ifdef __arm__
2081 int j;
2082 printf("TRACE: %x \n",(&j)[10]);
2083 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2084 #endif
2085 //fflush(stdout);
2086 }
2087 //printf("TRACE: %x\n",(&i)[-1]);
2088}
2089
2090void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2091{
2092 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2093}
2094
2095void alu_assemble(int i,struct regstat *i_regs)
2096{
2097 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2098 if(rt1[i]) {
2099 signed char s1,s2,t;
2100 t=get_reg(i_regs->regmap,rt1[i]);
2101 if(t>=0) {
2102 s1=get_reg(i_regs->regmap,rs1[i]);
2103 s2=get_reg(i_regs->regmap,rs2[i]);
2104 if(rs1[i]&&rs2[i]) {
2105 assert(s1>=0);
2106 assert(s2>=0);
2107 if(opcode2[i]&2) emit_sub(s1,s2,t);
2108 else emit_add(s1,s2,t);
2109 }
2110 else if(rs1[i]) {
2111 if(s1>=0) emit_mov(s1,t);
2112 else emit_loadreg(rs1[i],t);
2113 }
2114 else if(rs2[i]) {
2115 if(s2>=0) {
2116 if(opcode2[i]&2) emit_neg(s2,t);
2117 else emit_mov(s2,t);
2118 }
2119 else {
2120 emit_loadreg(rs2[i],t);
2121 if(opcode2[i]&2) emit_neg(t,t);
2122 }
2123 }
2124 else emit_zeroreg(t);
2125 }
2126 }
2127 }
2128 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2129 if(rt1[i]) {
2130 signed char s1l,s2l,s1h,s2h,tl,th;
2131 tl=get_reg(i_regs->regmap,rt1[i]);
2132 th=get_reg(i_regs->regmap,rt1[i]|64);
2133 if(tl>=0) {
2134 s1l=get_reg(i_regs->regmap,rs1[i]);
2135 s2l=get_reg(i_regs->regmap,rs2[i]);
2136 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2137 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2138 if(rs1[i]&&rs2[i]) {
2139 assert(s1l>=0);
2140 assert(s2l>=0);
2141 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2142 else emit_adds(s1l,s2l,tl);
2143 if(th>=0) {
2144 #ifdef INVERTED_CARRY
2145 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2146 #else
2147 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2148 #endif
2149 else emit_add(s1h,s2h,th);
2150 }
2151 }
2152 else if(rs1[i]) {
2153 if(s1l>=0) emit_mov(s1l,tl);
2154 else emit_loadreg(rs1[i],tl);
2155 if(th>=0) {
2156 if(s1h>=0) emit_mov(s1h,th);
2157 else emit_loadreg(rs1[i]|64,th);
2158 }
2159 }
2160 else if(rs2[i]) {
2161 if(s2l>=0) {
2162 if(opcode2[i]&2) emit_negs(s2l,tl);
2163 else emit_mov(s2l,tl);
2164 }
2165 else {
2166 emit_loadreg(rs2[i],tl);
2167 if(opcode2[i]&2) emit_negs(tl,tl);
2168 }
2169 if(th>=0) {
2170 #ifdef INVERTED_CARRY
2171 if(s2h>=0) emit_mov(s2h,th);
2172 else emit_loadreg(rs2[i]|64,th);
2173 if(opcode2[i]&2) {
2174 emit_adcimm(-1,th); // x86 has inverted carry flag
2175 emit_not(th,th);
2176 }
2177 #else
2178 if(opcode2[i]&2) {
2179 if(s2h>=0) emit_rscimm(s2h,0,th);
2180 else {
2181 emit_loadreg(rs2[i]|64,th);
2182 emit_rscimm(th,0,th);
2183 }
2184 }else{
2185 if(s2h>=0) emit_mov(s2h,th);
2186 else emit_loadreg(rs2[i]|64,th);
2187 }
2188 #endif
2189 }
2190 }
2191 else {
2192 emit_zeroreg(tl);
2193 if(th>=0) emit_zeroreg(th);
2194 }
2195 }
2196 }
2197 }
2198 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2199 if(rt1[i]) {
2200 signed char s1l,s1h,s2l,s2h,t;
2201 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2202 {
2203 t=get_reg(i_regs->regmap,rt1[i]);
2204 //assert(t>=0);
2205 if(t>=0) {
2206 s1l=get_reg(i_regs->regmap,rs1[i]);
2207 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2208 s2l=get_reg(i_regs->regmap,rs2[i]);
2209 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2210 if(rs2[i]==0) // rx<r0
2211 {
2212 assert(s1h>=0);
2213 if(opcode2[i]==0x2a) // SLT
2214 emit_shrimm(s1h,31,t);
2215 else // SLTU (unsigned can not be less than zero)
2216 emit_zeroreg(t);
2217 }
2218 else if(rs1[i]==0) // r0<rx
2219 {
2220 assert(s2h>=0);
2221 if(opcode2[i]==0x2a) // SLT
2222 emit_set_gz64_32(s2h,s2l,t);
2223 else // SLTU (set if not zero)
2224 emit_set_nz64_32(s2h,s2l,t);
2225 }
2226 else {
2227 assert(s1l>=0);assert(s1h>=0);
2228 assert(s2l>=0);assert(s2h>=0);
2229 if(opcode2[i]==0x2a) // SLT
2230 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2231 else // SLTU
2232 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2233 }
2234 }
2235 } else {
2236 t=get_reg(i_regs->regmap,rt1[i]);
2237 //assert(t>=0);
2238 if(t>=0) {
2239 s1l=get_reg(i_regs->regmap,rs1[i]);
2240 s2l=get_reg(i_regs->regmap,rs2[i]);
2241 if(rs2[i]==0) // rx<r0
2242 {
2243 assert(s1l>=0);
2244 if(opcode2[i]==0x2a) // SLT
2245 emit_shrimm(s1l,31,t);
2246 else // SLTU (unsigned can not be less than zero)
2247 emit_zeroreg(t);
2248 }
2249 else if(rs1[i]==0) // r0<rx
2250 {
2251 assert(s2l>=0);
2252 if(opcode2[i]==0x2a) // SLT
2253 emit_set_gz32(s2l,t);
2254 else // SLTU (set if not zero)
2255 emit_set_nz32(s2l,t);
2256 }
2257 else{
2258 assert(s1l>=0);assert(s2l>=0);
2259 if(opcode2[i]==0x2a) // SLT
2260 emit_set_if_less32(s1l,s2l,t);
2261 else // SLTU
2262 emit_set_if_carry32(s1l,s2l,t);
2263 }
2264 }
2265 }
2266 }
2267 }
2268 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2269 if(rt1[i]) {
2270 signed char s1l,s1h,s2l,s2h,th,tl;
2271 tl=get_reg(i_regs->regmap,rt1[i]);
2272 th=get_reg(i_regs->regmap,rt1[i]|64);
2273 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2274 {
2275 assert(tl>=0);
2276 if(tl>=0) {
2277 s1l=get_reg(i_regs->regmap,rs1[i]);
2278 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2279 s2l=get_reg(i_regs->regmap,rs2[i]);
2280 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2281 if(rs1[i]&&rs2[i]) {
2282 assert(s1l>=0);assert(s1h>=0);
2283 assert(s2l>=0);assert(s2h>=0);
2284 if(opcode2[i]==0x24) { // AND
2285 emit_and(s1l,s2l,tl);
2286 emit_and(s1h,s2h,th);
2287 } else
2288 if(opcode2[i]==0x25) { // OR
2289 emit_or(s1l,s2l,tl);
2290 emit_or(s1h,s2h,th);
2291 } else
2292 if(opcode2[i]==0x26) { // XOR
2293 emit_xor(s1l,s2l,tl);
2294 emit_xor(s1h,s2h,th);
2295 } else
2296 if(opcode2[i]==0x27) { // NOR
2297 emit_or(s1l,s2l,tl);
2298 emit_or(s1h,s2h,th);
2299 emit_not(tl,tl);
2300 emit_not(th,th);
2301 }
2302 }
2303 else
2304 {
2305 if(opcode2[i]==0x24) { // AND
2306 emit_zeroreg(tl);
2307 emit_zeroreg(th);
2308 } else
2309 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2310 if(rs1[i]){
2311 if(s1l>=0) emit_mov(s1l,tl);
2312 else emit_loadreg(rs1[i],tl);
2313 if(s1h>=0) emit_mov(s1h,th);
2314 else emit_loadreg(rs1[i]|64,th);
2315 }
2316 else
2317 if(rs2[i]){
2318 if(s2l>=0) emit_mov(s2l,tl);
2319 else emit_loadreg(rs2[i],tl);
2320 if(s2h>=0) emit_mov(s2h,th);
2321 else emit_loadreg(rs2[i]|64,th);
2322 }
2323 else{
2324 emit_zeroreg(tl);
2325 emit_zeroreg(th);
2326 }
2327 } else
2328 if(opcode2[i]==0x27) { // NOR
2329 if(rs1[i]){
2330 if(s1l>=0) emit_not(s1l,tl);
2331 else{
2332 emit_loadreg(rs1[i],tl);
2333 emit_not(tl,tl);
2334 }
2335 if(s1h>=0) emit_not(s1h,th);
2336 else{
2337 emit_loadreg(rs1[i]|64,th);
2338 emit_not(th,th);
2339 }
2340 }
2341 else
2342 if(rs2[i]){
2343 if(s2l>=0) emit_not(s2l,tl);
2344 else{
2345 emit_loadreg(rs2[i],tl);
2346 emit_not(tl,tl);
2347 }
2348 if(s2h>=0) emit_not(s2h,th);
2349 else{
2350 emit_loadreg(rs2[i]|64,th);
2351 emit_not(th,th);
2352 }
2353 }
2354 else {
2355 emit_movimm(-1,tl);
2356 emit_movimm(-1,th);
2357 }
2358 }
2359 }
2360 }
2361 }
2362 else
2363 {
2364 // 32 bit
2365 if(tl>=0) {
2366 s1l=get_reg(i_regs->regmap,rs1[i]);
2367 s2l=get_reg(i_regs->regmap,rs2[i]);
2368 if(rs1[i]&&rs2[i]) {
2369 assert(s1l>=0);
2370 assert(s2l>=0);
2371 if(opcode2[i]==0x24) { // AND
2372 emit_and(s1l,s2l,tl);
2373 } else
2374 if(opcode2[i]==0x25) { // OR
2375 emit_or(s1l,s2l,tl);
2376 } else
2377 if(opcode2[i]==0x26) { // XOR
2378 emit_xor(s1l,s2l,tl);
2379 } else
2380 if(opcode2[i]==0x27) { // NOR
2381 emit_or(s1l,s2l,tl);
2382 emit_not(tl,tl);
2383 }
2384 }
2385 else
2386 {
2387 if(opcode2[i]==0x24) { // AND
2388 emit_zeroreg(tl);
2389 } else
2390 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2391 if(rs1[i]){
2392 if(s1l>=0) emit_mov(s1l,tl);
2393 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2394 }
2395 else
2396 if(rs2[i]){
2397 if(s2l>=0) emit_mov(s2l,tl);
2398 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2399 }
2400 else emit_zeroreg(tl);
2401 } else
2402 if(opcode2[i]==0x27) { // NOR
2403 if(rs1[i]){
2404 if(s1l>=0) emit_not(s1l,tl);
2405 else {
2406 emit_loadreg(rs1[i],tl);
2407 emit_not(tl,tl);
2408 }
2409 }
2410 else
2411 if(rs2[i]){
2412 if(s2l>=0) emit_not(s2l,tl);
2413 else {
2414 emit_loadreg(rs2[i],tl);
2415 emit_not(tl,tl);
2416 }
2417 }
2418 else emit_movimm(-1,tl);
2419 }
2420 }
2421 }
2422 }
2423 }
2424 }
2425}
2426
2427void imm16_assemble(int i,struct regstat *i_regs)
2428{
2429 if (opcode[i]==0x0f) { // LUI
2430 if(rt1[i]) {
2431 signed char t;
2432 t=get_reg(i_regs->regmap,rt1[i]);
2433 //assert(t>=0);
2434 if(t>=0) {
2435 if(!((i_regs->isconst>>t)&1))
2436 emit_movimm(imm[i]<<16,t);
2437 }
2438 }
2439 }
2440 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2441 if(rt1[i]) {
2442 signed char s,t;
2443 t=get_reg(i_regs->regmap,rt1[i]);
2444 s=get_reg(i_regs->regmap,rs1[i]);
2445 if(rs1[i]) {
2446 //assert(t>=0);
2447 //assert(s>=0);
2448 if(t>=0) {
2449 if(!((i_regs->isconst>>t)&1)) {
2450 if(s<0) {
2451 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2452 emit_addimm(t,imm[i],t);
2453 }else{
2454 if(!((i_regs->wasconst>>s)&1))
2455 emit_addimm(s,imm[i],t);
2456 else
2457 emit_movimm(constmap[i][s]+imm[i],t);
2458 }
2459 }
2460 }
2461 } else {
2462 if(t>=0) {
2463 if(!((i_regs->isconst>>t)&1))
2464 emit_movimm(imm[i],t);
2465 }
2466 }
2467 }
2468 }
2469 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2470 if(rt1[i]) {
2471 signed char sh,sl,th,tl;
2472 th=get_reg(i_regs->regmap,rt1[i]|64);
2473 tl=get_reg(i_regs->regmap,rt1[i]);
2474 sh=get_reg(i_regs->regmap,rs1[i]|64);
2475 sl=get_reg(i_regs->regmap,rs1[i]);
2476 if(tl>=0) {
2477 if(rs1[i]) {
2478 assert(sh>=0);
2479 assert(sl>=0);
2480 if(th>=0) {
2481 emit_addimm64_32(sh,sl,imm[i],th,tl);
2482 }
2483 else {
2484 emit_addimm(sl,imm[i],tl);
2485 }
2486 } else {
2487 emit_movimm(imm[i],tl);
2488 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2489 }
2490 }
2491 }
2492 }
2493 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2494 if(rt1[i]) {
2495 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2496 signed char sh,sl,t;
2497 t=get_reg(i_regs->regmap,rt1[i]);
2498 sh=get_reg(i_regs->regmap,rs1[i]|64);
2499 sl=get_reg(i_regs->regmap,rs1[i]);
2500 //assert(t>=0);
2501 if(t>=0) {
2502 if(rs1[i]>0) {
2503 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2504 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2505 if(opcode[i]==0x0a) { // SLTI
2506 if(sl<0) {
2507 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2508 emit_slti32(t,imm[i],t);
2509 }else{
2510 emit_slti32(sl,imm[i],t);
2511 }
2512 }
2513 else { // SLTIU
2514 if(sl<0) {
2515 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2516 emit_sltiu32(t,imm[i],t);
2517 }else{
2518 emit_sltiu32(sl,imm[i],t);
2519 }
2520 }
2521 }else{ // 64-bit
2522 assert(sl>=0);
2523 if(opcode[i]==0x0a) // SLTI
2524 emit_slti64_32(sh,sl,imm[i],t);
2525 else // SLTIU
2526 emit_sltiu64_32(sh,sl,imm[i],t);
2527 }
2528 }else{
2529 // SLTI(U) with r0 is just stupid,
2530 // nonetheless examples can be found
2531 if(opcode[i]==0x0a) // SLTI
2532 if(0<imm[i]) emit_movimm(1,t);
2533 else emit_zeroreg(t);
2534 else // SLTIU
2535 {
2536 if(imm[i]) emit_movimm(1,t);
2537 else emit_zeroreg(t);
2538 }
2539 }
2540 }
2541 }
2542 }
2543 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2544 if(rt1[i]) {
2545 signed char sh,sl,th,tl;
2546 th=get_reg(i_regs->regmap,rt1[i]|64);
2547 tl=get_reg(i_regs->regmap,rt1[i]);
2548 sh=get_reg(i_regs->regmap,rs1[i]|64);
2549 sl=get_reg(i_regs->regmap,rs1[i]);
2550 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2551 if(opcode[i]==0x0c) //ANDI
2552 {
2553 if(rs1[i]) {
2554 if(sl<0) {
2555 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2556 emit_andimm(tl,imm[i],tl);
2557 }else{
2558 if(!((i_regs->wasconst>>sl)&1))
2559 emit_andimm(sl,imm[i],tl);
2560 else
2561 emit_movimm(constmap[i][sl]&imm[i],tl);
2562 }
2563 }
2564 else
2565 emit_zeroreg(tl);
2566 if(th>=0) emit_zeroreg(th);
2567 }
2568 else
2569 {
2570 if(rs1[i]) {
2571 if(sl<0) {
2572 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2573 }
2574 if(th>=0) {
2575 if(sh<0) {
2576 emit_loadreg(rs1[i]|64,th);
2577 }else{
2578 emit_mov(sh,th);
2579 }
2580 }
2581 if(opcode[i]==0x0d) //ORI
2582 if(sl<0) {
2583 emit_orimm(tl,imm[i],tl);
2584 }else{
2585 if(!((i_regs->wasconst>>sl)&1))
2586 emit_orimm(sl,imm[i],tl);
2587 else
2588 emit_movimm(constmap[i][sl]|imm[i],tl);
2589 }
2590 if(opcode[i]==0x0e) //XORI
2591 if(sl<0) {
2592 emit_xorimm(tl,imm[i],tl);
2593 }else{
2594 if(!((i_regs->wasconst>>sl)&1))
2595 emit_xorimm(sl,imm[i],tl);
2596 else
2597 emit_movimm(constmap[i][sl]^imm[i],tl);
2598 }
2599 }
2600 else {
2601 emit_movimm(imm[i],tl);
2602 if(th>=0) emit_zeroreg(th);
2603 }
2604 }
2605 }
2606 }
2607 }
2608}
2609
2610void shiftimm_assemble(int i,struct regstat *i_regs)
2611{
2612 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2613 {
2614 if(rt1[i]) {
2615 signed char s,t;
2616 t=get_reg(i_regs->regmap,rt1[i]);
2617 s=get_reg(i_regs->regmap,rs1[i]);
2618 //assert(t>=0);
2619 if(t>=0){
2620 if(rs1[i]==0)
2621 {
2622 emit_zeroreg(t);
2623 }
2624 else
2625 {
2626 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2627 if(imm[i]) {
2628 if(opcode2[i]==0) // SLL
2629 {
2630 emit_shlimm(s<0?t:s,imm[i],t);
2631 }
2632 if(opcode2[i]==2) // SRL
2633 {
2634 emit_shrimm(s<0?t:s,imm[i],t);
2635 }
2636 if(opcode2[i]==3) // SRA
2637 {
2638 emit_sarimm(s<0?t:s,imm[i],t);
2639 }
2640 }else{
2641 // Shift by zero
2642 if(s>=0 && s!=t) emit_mov(s,t);
2643 }
2644 }
2645 }
2646 //emit_storereg(rt1[i],t); //DEBUG
2647 }
2648 }
2649 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2650 {
2651 if(rt1[i]) {
2652 signed char sh,sl,th,tl;
2653 th=get_reg(i_regs->regmap,rt1[i]|64);
2654 tl=get_reg(i_regs->regmap,rt1[i]);
2655 sh=get_reg(i_regs->regmap,rs1[i]|64);
2656 sl=get_reg(i_regs->regmap,rs1[i]);
2657 if(tl>=0) {
2658 if(rs1[i]==0)
2659 {
2660 emit_zeroreg(tl);
2661 if(th>=0) emit_zeroreg(th);
2662 }
2663 else
2664 {
2665 assert(sl>=0);
2666 assert(sh>=0);
2667 if(imm[i]) {
2668 if(opcode2[i]==0x38) // DSLL
2669 {
2670 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2671 emit_shlimm(sl,imm[i],tl);
2672 }
2673 if(opcode2[i]==0x3a) // DSRL
2674 {
2675 emit_shrdimm(sl,sh,imm[i],tl);
2676 if(th>=0) emit_shrimm(sh,imm[i],th);
2677 }
2678 if(opcode2[i]==0x3b) // DSRA
2679 {
2680 emit_shrdimm(sl,sh,imm[i],tl);
2681 if(th>=0) emit_sarimm(sh,imm[i],th);
2682 }
2683 }else{
2684 // Shift by zero
2685 if(sl!=tl) emit_mov(sl,tl);
2686 if(th>=0&&sh!=th) emit_mov(sh,th);
2687 }
2688 }
2689 }
2690 }
2691 }
2692 if(opcode2[i]==0x3c) // DSLL32
2693 {
2694 if(rt1[i]) {
2695 signed char sl,tl,th;
2696 tl=get_reg(i_regs->regmap,rt1[i]);
2697 th=get_reg(i_regs->regmap,rt1[i]|64);
2698 sl=get_reg(i_regs->regmap,rs1[i]);
2699 if(th>=0||tl>=0){
2700 assert(tl>=0);
2701 assert(th>=0);
2702 assert(sl>=0);
2703 emit_mov(sl,th);
2704 emit_zeroreg(tl);
2705 if(imm[i]>32)
2706 {
2707 emit_shlimm(th,imm[i]&31,th);
2708 }
2709 }
2710 }
2711 }
2712 if(opcode2[i]==0x3e) // DSRL32
2713 {
2714 if(rt1[i]) {
2715 signed char sh,tl,th;
2716 tl=get_reg(i_regs->regmap,rt1[i]);
2717 th=get_reg(i_regs->regmap,rt1[i]|64);
2718 sh=get_reg(i_regs->regmap,rs1[i]|64);
2719 if(tl>=0){
2720 assert(sh>=0);
2721 emit_mov(sh,tl);
2722 if(th>=0) emit_zeroreg(th);
2723 if(imm[i]>32)
2724 {
2725 emit_shrimm(tl,imm[i]&31,tl);
2726 }
2727 }
2728 }
2729 }
2730 if(opcode2[i]==0x3f) // DSRA32
2731 {
2732 if(rt1[i]) {
2733 signed char sh,tl;
2734 tl=get_reg(i_regs->regmap,rt1[i]);
2735 sh=get_reg(i_regs->regmap,rs1[i]|64);
2736 if(tl>=0){
2737 assert(sh>=0);
2738 emit_mov(sh,tl);
2739 if(imm[i]>32)
2740 {
2741 emit_sarimm(tl,imm[i]&31,tl);
2742 }
2743 }
2744 }
2745 }
2746}
2747
2748#ifndef shift_assemble
2749void shift_assemble(int i,struct regstat *i_regs)
2750{
2751 printf("Need shift_assemble for this architecture.\n");
2752 exit(1);
2753}
2754#endif
2755
2756void load_assemble(int i,struct regstat *i_regs)
2757{
2758 int s,th,tl,addr,map=-1;
2759 int offset;
2760 int jaddr=0;
2761 int memtarget=0,c=0;
2762 u_int hr,reglist=0;
2763 th=get_reg(i_regs->regmap,rt1[i]|64);
2764 tl=get_reg(i_regs->regmap,rt1[i]);
2765 s=get_reg(i_regs->regmap,rs1[i]);
2766 offset=imm[i];
2767 for(hr=0;hr<HOST_REGS;hr++) {
2768 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2769 }
2770 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2771 if(s>=0) {
2772 c=(i_regs->wasconst>>s)&1;
2773 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2774 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2775 }
2776 //printf("load_assemble: c=%d\n",c);
2777 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2778 // FIXME: Even if the load is a NOP, we should check for pagefaults...
2779#ifdef PCSX
2780 if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2781 ||rt1[i]==0) {
2782 // could be FIFO, must perform the read
2783 // ||dummy read
2784 assem_debug("(forced read)\n");
2785 tl=get_reg(i_regs->regmap,-1);
2786 assert(tl>=0);
2787 }
2788#endif
2789 if(offset||s<0||c) addr=tl;
2790 else addr=s;
2791 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2792 if(tl>=0) {
2793 //printf("load_assemble: c=%d\n",c);
2794 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2795 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2796 reglist&=~(1<<tl);
2797 if(th>=0) reglist&=~(1<<th);
2798 if(!using_tlb) {
2799 if(!c) {
2800 #ifdef RAM_OFFSET
2801 map=get_reg(i_regs->regmap,ROREG);
2802 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2803 #endif
2804//#define R29_HACK 1
2805 #ifdef R29_HACK
2806 // Strmnnrmn's speed hack
2807 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2808 #endif
2809 {
2810 emit_cmpimm(addr,RAM_SIZE);
2811 jaddr=(int)out;
2812 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2813 // Hint to branch predictor that the branch is unlikely to be taken
2814 if(rs1[i]>=28)
2815 emit_jno_unlikely(0);
2816 else
2817 #endif
2818 emit_jno(0);
2819 }
2820 }
2821 }else{ // using tlb
2822 int x=0;
2823 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2824 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2825 map=get_reg(i_regs->regmap,TLREG);
2826 assert(map>=0);
2827 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2828 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2829 }
2830 int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2831 if (opcode[i]==0x20) { // LB
2832 if(!c||memtarget) {
2833 if(!dummy) {
2834 #ifdef HOST_IMM_ADDR32
2835 if(c)
2836 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2837 else
2838 #endif
2839 {
2840 //emit_xorimm(addr,3,tl);
2841 //gen_tlb_addr_r(tl,map);
2842 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2843 int x=0,a=tl;
2844#ifdef BIG_ENDIAN_MIPS
2845 if(!c) emit_xorimm(addr,3,tl);
2846 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2847#else
2848 if(!c) a=addr;
2849#endif
2850 emit_movsbl_indexed_tlb(x,a,map,tl);
2851 }
2852 }
2853 if(jaddr)
2854 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2855 }
2856 else
2857 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2858 }
2859 if (opcode[i]==0x21) { // LH
2860 if(!c||memtarget) {
2861 if(!dummy) {
2862 #ifdef HOST_IMM_ADDR32
2863 if(c)
2864 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2865 else
2866 #endif
2867 {
2868 int x=0,a=tl;
2869#ifdef BIG_ENDIAN_MIPS
2870 if(!c) emit_xorimm(addr,2,tl);
2871 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2872#else
2873 if(!c) a=addr;
2874#endif
2875 //#ifdef
2876 //emit_movswl_indexed_tlb(x,tl,map,tl);
2877 //else
2878 if(map>=0) {
2879 gen_tlb_addr_r(a,map);
2880 emit_movswl_indexed(x,a,tl);
2881 }else{
2882 #ifdef RAM_OFFSET
2883 emit_movswl_indexed(x,a,tl);
2884 #else
2885 emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2886 #endif
2887 }
2888 }
2889 }
2890 if(jaddr)
2891 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2892 }
2893 else
2894 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2895 }
2896 if (opcode[i]==0x23) { // LW
2897 if(!c||memtarget) {
2898 if(!dummy) {
2899 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2900 #ifdef HOST_IMM_ADDR32
2901 if(c)
2902 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2903 else
2904 #endif
2905 emit_readword_indexed_tlb(0,addr,map,tl);
2906 }
2907 if(jaddr)
2908 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2909 }
2910 else
2911 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2912 }
2913 if (opcode[i]==0x24) { // LBU
2914 if(!c||memtarget) {
2915 if(!dummy) {
2916 #ifdef HOST_IMM_ADDR32
2917 if(c)
2918 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2919 else
2920 #endif
2921 {
2922 //emit_xorimm(addr,3,tl);
2923 //gen_tlb_addr_r(tl,map);
2924 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
2925 int x=0,a=tl;
2926#ifdef BIG_ENDIAN_MIPS
2927 if(!c) emit_xorimm(addr,3,tl);
2928 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2929#else
2930 if(!c) a=addr;
2931#endif
2932 emit_movzbl_indexed_tlb(x,a,map,tl);
2933 }
2934 }
2935 if(jaddr)
2936 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2937 }
2938 else
2939 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2940 }
2941 if (opcode[i]==0x25) { // LHU
2942 if(!c||memtarget) {
2943 if(!dummy) {
2944 #ifdef HOST_IMM_ADDR32
2945 if(c)
2946 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2947 else
2948 #endif
2949 {
2950 int x=0,a=tl;
2951#ifdef BIG_ENDIAN_MIPS
2952 if(!c) emit_xorimm(addr,2,tl);
2953 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2954#else
2955 if(!c) a=addr;
2956#endif
2957 //#ifdef
2958 //emit_movzwl_indexed_tlb(x,tl,map,tl);
2959 //#else
2960 if(map>=0) {
2961 gen_tlb_addr_r(a,map);
2962 emit_movzwl_indexed(x,a,tl);
2963 }else{
2964 #ifdef RAM_OFFSET
2965 emit_movzwl_indexed(x,a,tl);
2966 #else
2967 emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
2968 #endif
2969 }
2970 }
2971 }
2972 if(jaddr)
2973 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2974 }
2975 else
2976 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2977 }
2978 if (opcode[i]==0x27) { // LWU
2979 assert(th>=0);
2980 if(!c||memtarget) {
2981 if(!dummy) {
2982 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2983 #ifdef HOST_IMM_ADDR32
2984 if(c)
2985 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2986 else
2987 #endif
2988 emit_readword_indexed_tlb(0,addr,map,tl);
2989 }
2990 if(jaddr)
2991 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2992 }
2993 else {
2994 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2995 }
2996 emit_zeroreg(th);
2997 }
2998 if (opcode[i]==0x37) { // LD
2999 if(!c||memtarget) {
3000 if(!dummy) {
3001 //gen_tlb_addr_r(tl,map);
3002 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3003 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3004 #ifdef HOST_IMM_ADDR32
3005 if(c)
3006 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3007 else
3008 #endif
3009 emit_readdword_indexed_tlb(0,addr,map,th,tl);
3010 }
3011 if(jaddr)
3012 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3013 }
3014 else
3015 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3016 }
3017 }
3018 //emit_storereg(rt1[i],tl); // DEBUG
3019 //if(opcode[i]==0x23)
3020 //if(opcode[i]==0x24)
3021 //if(opcode[i]==0x23||opcode[i]==0x24)
3022 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3023 {
3024 //emit_pusha();
3025 save_regs(0x100f);
3026 emit_readword((int)&last_count,ECX);
3027 #ifdef __i386__
3028 if(get_reg(i_regs->regmap,CCREG)<0)
3029 emit_loadreg(CCREG,HOST_CCREG);
3030 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3031 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3032 emit_writeword(HOST_CCREG,(int)&Count);
3033 #endif
3034 #ifdef __arm__
3035 if(get_reg(i_regs->regmap,CCREG)<0)
3036 emit_loadreg(CCREG,0);
3037 else
3038 emit_mov(HOST_CCREG,0);
3039 emit_add(0,ECX,0);
3040 emit_addimm(0,2*ccadj[i],0);
3041 emit_writeword(0,(int)&Count);
3042 #endif
3043 emit_call((int)memdebug);
3044 //emit_popa();
3045 restore_regs(0x100f);
3046 }/**/
3047}
3048
3049#ifndef loadlr_assemble
3050void loadlr_assemble(int i,struct regstat *i_regs)
3051{
3052 printf("Need loadlr_assemble for this architecture.\n");
3053 exit(1);
3054}
3055#endif
3056
3057void store_assemble(int i,struct regstat *i_regs)
3058{
3059 int s,th,tl,map=-1;
3060 int addr,temp;
3061 int offset;
3062 int jaddr=0,jaddr2,type;
3063 int memtarget=0,c=0;
3064 int agr=AGEN1+(i&1);
3065 u_int hr,reglist=0;
3066 th=get_reg(i_regs->regmap,rs2[i]|64);
3067 tl=get_reg(i_regs->regmap,rs2[i]);
3068 s=get_reg(i_regs->regmap,rs1[i]);
3069 temp=get_reg(i_regs->regmap,agr);
3070 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3071 offset=imm[i];
3072 if(s>=0) {
3073 c=(i_regs->wasconst>>s)&1;
3074 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3075 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3076 }
3077 assert(tl>=0);
3078 assert(temp>=0);
3079 for(hr=0;hr<HOST_REGS;hr++) {
3080 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3081 }
3082 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3083 if(offset||s<0||c) addr=temp;
3084 else addr=s;
3085 if(!using_tlb) {
3086 if(!c) {
3087 #ifdef R29_HACK
3088 // Strmnnrmn's speed hack
3089 memtarget=1;
3090 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3091 #endif
3092 emit_cmpimm(addr,RAM_SIZE);
3093 #ifdef DESTRUCTIVE_SHIFT
3094 if(s==addr) emit_mov(s,temp);
3095 #endif
3096 #ifdef R29_HACK
3097 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3098 #endif
3099 {
3100 jaddr=(int)out;
3101 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3102 // Hint to branch predictor that the branch is unlikely to be taken
3103 if(rs1[i]>=28)
3104 emit_jno_unlikely(0);
3105 else
3106 #endif
3107 emit_jno(0);
3108 }
3109 }
3110 }else{ // using tlb
3111 int x=0;
3112 if (opcode[i]==0x28) x=3; // SB
3113 if (opcode[i]==0x29) x=2; // SH
3114 map=get_reg(i_regs->regmap,TLREG);
3115 assert(map>=0);
3116 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3117 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3118 }
3119
3120 if (opcode[i]==0x28) { // SB
3121 if(!c||memtarget) {
3122 int x=0;
3123#ifdef BIG_ENDIAN_MIPS
3124 if(!c) emit_xorimm(addr,3,temp);
3125 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3126#else
3127 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3128 else if (addr!=temp) emit_mov(addr,temp);
3129#endif
3130 //gen_tlb_addr_w(temp,map);
3131 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3132 emit_writebyte_indexed_tlb(tl,x,temp,map,temp);
3133 }
3134 type=STOREB_STUB;
3135 }
3136 if (opcode[i]==0x29) { // SH
3137 if(!c||memtarget) {
3138 int x=0;
3139#ifdef BIG_ENDIAN_MIPS
3140 if(!c) emit_xorimm(addr,2,temp);
3141 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3142#else
3143 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3144 else if (addr!=temp) emit_mov(addr,temp);
3145#endif
3146 //#ifdef
3147 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3148 //#else
3149 if(map>=0) {
3150 gen_tlb_addr_w(temp,map);
3151 emit_writehword_indexed(tl,x,temp);
3152 }else
3153 emit_writehword_indexed(tl,(int)rdram-0x80000000+x,temp);
3154 }
3155 type=STOREH_STUB;
3156 }
3157 if (opcode[i]==0x2B) { // SW
3158 if(!c||memtarget)
3159 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3160 emit_writeword_indexed_tlb(tl,0,addr,map,temp);
3161 type=STOREW_STUB;
3162 }
3163 if (opcode[i]==0x3F) { // SD
3164 if(!c||memtarget) {
3165 if(rs2[i]) {
3166 assert(th>=0);
3167 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3168 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3169 emit_writedword_indexed_tlb(th,tl,0,addr,map,temp);
3170 }else{
3171 // Store zero
3172 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3173 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3174 emit_writedword_indexed_tlb(tl,tl,0,addr,map,temp);
3175 }
3176 }
3177 type=STORED_STUB;
3178 }
3179 if(!using_tlb&&(!c||memtarget))
3180 // addr could be a temp, make sure it survives STORE*_STUB
3181 reglist|=1<<addr;
3182 if(jaddr) {
3183 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3184 } else if(!memtarget) {
3185 inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3186 }
3187 if(!using_tlb) {
3188 if(!c||memtarget) {
3189 #ifdef DESTRUCTIVE_SHIFT
3190 // The x86 shift operation is 'destructive'; it overwrites the
3191 // source register, so we need to make a copy first and use that.
3192 addr=temp;
3193 #endif
3194 #if defined(HOST_IMM8)
3195 int ir=get_reg(i_regs->regmap,INVCP);
3196 assert(ir>=0);
3197 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3198 #else
3199 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3200 #endif
3201 jaddr2=(int)out;
3202 emit_jne(0);
3203 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3204 }
3205 }
3206 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3207 //if(opcode[i]==0x2B || opcode[i]==0x28)
3208 //if(opcode[i]==0x2B || opcode[i]==0x29)
3209 //if(opcode[i]==0x2B)
3210 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3211 {
3212 //emit_pusha();
3213 save_regs(0x100f);
3214 emit_readword((int)&last_count,ECX);
3215 #ifdef __i386__
3216 if(get_reg(i_regs->regmap,CCREG)<0)
3217 emit_loadreg(CCREG,HOST_CCREG);
3218 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3219 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3220 emit_writeword(HOST_CCREG,(int)&Count);
3221 #endif
3222 #ifdef __arm__
3223 if(get_reg(i_regs->regmap,CCREG)<0)
3224 emit_loadreg(CCREG,0);
3225 else
3226 emit_mov(HOST_CCREG,0);
3227 emit_add(0,ECX,0);
3228 emit_addimm(0,2*ccadj[i],0);
3229 emit_writeword(0,(int)&Count);
3230 #endif
3231 emit_call((int)memdebug);
3232 //emit_popa();
3233 restore_regs(0x100f);
3234 }/**/
3235}
3236
3237void storelr_assemble(int i,struct regstat *i_regs)
3238{
3239 int s,th,tl;
3240 int temp;
3241 int temp2;
3242 int offset;
3243 int jaddr=0,jaddr2;
3244 int case1,case2,case3;
3245 int done0,done1,done2;
3246 int memtarget,c=0;
3247 int agr=AGEN1+(i&1);
3248 u_int hr,reglist=0;
3249 th=get_reg(i_regs->regmap,rs2[i]|64);
3250 tl=get_reg(i_regs->regmap,rs2[i]);
3251 s=get_reg(i_regs->regmap,rs1[i]);
3252 temp=get_reg(i_regs->regmap,agr);
3253 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3254 offset=imm[i];
3255 if(s>=0) {
3256 c=(i_regs->isconst>>s)&1;
3257 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3258 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3259 }
3260 assert(tl>=0);
3261 for(hr=0;hr<HOST_REGS;hr++) {
3262 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3263 }
3264 assert(temp>=0);
3265 if(!using_tlb) {
3266 if(!c) {
3267 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3268 if(!offset&&s!=temp) emit_mov(s,temp);
3269 jaddr=(int)out;
3270 emit_jno(0);
3271 }
3272 else
3273 {
3274 if(!memtarget||!rs1[i]) {
3275 jaddr=(int)out;
3276 emit_jmp(0);
3277 }
3278 }
3279 #ifdef RAM_OFFSET
3280 int map=get_reg(i_regs->regmap,ROREG);
3281 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3282 gen_tlb_addr_w(temp,map);
3283 #else
3284 if((u_int)rdram!=0x80000000)
3285 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3286 #endif
3287 }else{ // using tlb
3288 int map=get_reg(i_regs->regmap,TLREG);
3289 assert(map>=0);
3290 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3291 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3292 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3293 if(!jaddr&&!memtarget) {
3294 jaddr=(int)out;
3295 emit_jmp(0);
3296 }
3297 gen_tlb_addr_w(temp,map);
3298 }
3299
3300 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3301 temp2=get_reg(i_regs->regmap,FTEMP);
3302 if(!rs2[i]) temp2=th=tl;
3303 }
3304
3305#ifndef BIG_ENDIAN_MIPS
3306 emit_xorimm(temp,3,temp);
3307#endif
3308 emit_testimm(temp,2);
3309 case2=(int)out;
3310 emit_jne(0);
3311 emit_testimm(temp,1);
3312 case1=(int)out;
3313 emit_jne(0);
3314 // 0
3315 if (opcode[i]==0x2A) { // SWL
3316 emit_writeword_indexed(tl,0,temp);
3317 }
3318 if (opcode[i]==0x2E) { // SWR
3319 emit_writebyte_indexed(tl,3,temp);
3320 }
3321 if (opcode[i]==0x2C) { // SDL
3322 emit_writeword_indexed(th,0,temp);
3323 if(rs2[i]) emit_mov(tl,temp2);
3324 }
3325 if (opcode[i]==0x2D) { // SDR
3326 emit_writebyte_indexed(tl,3,temp);
3327 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3328 }
3329 done0=(int)out;
3330 emit_jmp(0);
3331 // 1
3332 set_jump_target(case1,(int)out);
3333 if (opcode[i]==0x2A) { // SWL
3334 // Write 3 msb into three least significant bytes
3335 if(rs2[i]) emit_rorimm(tl,8,tl);
3336 emit_writehword_indexed(tl,-1,temp);
3337 if(rs2[i]) emit_rorimm(tl,16,tl);
3338 emit_writebyte_indexed(tl,1,temp);
3339 if(rs2[i]) emit_rorimm(tl,8,tl);
3340 }
3341 if (opcode[i]==0x2E) { // SWR
3342 // Write two lsb into two most significant bytes
3343 emit_writehword_indexed(tl,1,temp);
3344 }
3345 if (opcode[i]==0x2C) { // SDL
3346 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3347 // Write 3 msb into three least significant bytes
3348 if(rs2[i]) emit_rorimm(th,8,th);
3349 emit_writehword_indexed(th,-1,temp);
3350 if(rs2[i]) emit_rorimm(th,16,th);
3351 emit_writebyte_indexed(th,1,temp);
3352 if(rs2[i]) emit_rorimm(th,8,th);
3353 }
3354 if (opcode[i]==0x2D) { // SDR
3355 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3356 // Write two lsb into two most significant bytes
3357 emit_writehword_indexed(tl,1,temp);
3358 }
3359 done1=(int)out;
3360 emit_jmp(0);
3361 // 2
3362 set_jump_target(case2,(int)out);
3363 emit_testimm(temp,1);
3364 case3=(int)out;
3365 emit_jne(0);
3366 if (opcode[i]==0x2A) { // SWL
3367 // Write two msb into two least significant bytes
3368 if(rs2[i]) emit_rorimm(tl,16,tl);
3369 emit_writehword_indexed(tl,-2,temp);
3370 if(rs2[i]) emit_rorimm(tl,16,tl);
3371 }
3372 if (opcode[i]==0x2E) { // SWR
3373 // Write 3 lsb into three most significant bytes
3374 emit_writebyte_indexed(tl,-1,temp);
3375 if(rs2[i]) emit_rorimm(tl,8,tl);
3376 emit_writehword_indexed(tl,0,temp);
3377 if(rs2[i]) emit_rorimm(tl,24,tl);
3378 }
3379 if (opcode[i]==0x2C) { // SDL
3380 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3381 // Write two msb into two least significant bytes
3382 if(rs2[i]) emit_rorimm(th,16,th);
3383 emit_writehword_indexed(th,-2,temp);
3384 if(rs2[i]) emit_rorimm(th,16,th);
3385 }
3386 if (opcode[i]==0x2D) { // SDR
3387 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3388 // Write 3 lsb into three most significant bytes
3389 emit_writebyte_indexed(tl,-1,temp);
3390 if(rs2[i]) emit_rorimm(tl,8,tl);
3391 emit_writehword_indexed(tl,0,temp);
3392 if(rs2[i]) emit_rorimm(tl,24,tl);
3393 }
3394 done2=(int)out;
3395 emit_jmp(0);
3396 // 3
3397 set_jump_target(case3,(int)out);
3398 if (opcode[i]==0x2A) { // SWL
3399 // Write msb into least significant byte
3400 if(rs2[i]) emit_rorimm(tl,24,tl);
3401 emit_writebyte_indexed(tl,-3,temp);
3402 if(rs2[i]) emit_rorimm(tl,8,tl);
3403 }
3404 if (opcode[i]==0x2E) { // SWR
3405 // Write entire word
3406 emit_writeword_indexed(tl,-3,temp);
3407 }
3408 if (opcode[i]==0x2C) { // SDL
3409 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3410 // Write msb into least significant byte
3411 if(rs2[i]) emit_rorimm(th,24,th);
3412 emit_writebyte_indexed(th,-3,temp);
3413 if(rs2[i]) emit_rorimm(th,8,th);
3414 }
3415 if (opcode[i]==0x2D) { // SDR
3416 if(rs2[i]) emit_mov(th,temp2);
3417 // Write entire word
3418 emit_writeword_indexed(tl,-3,temp);
3419 }
3420 set_jump_target(done0,(int)out);
3421 set_jump_target(done1,(int)out);
3422 set_jump_target(done2,(int)out);
3423 if (opcode[i]==0x2C) { // SDL
3424 emit_testimm(temp,4);
3425 done0=(int)out;
3426 emit_jne(0);
3427 emit_andimm(temp,~3,temp);
3428 emit_writeword_indexed(temp2,4,temp);
3429 set_jump_target(done0,(int)out);
3430 }
3431 if (opcode[i]==0x2D) { // SDR
3432 emit_testimm(temp,4);
3433 done0=(int)out;
3434 emit_jeq(0);
3435 emit_andimm(temp,~3,temp);
3436 emit_writeword_indexed(temp2,-4,temp);
3437 set_jump_target(done0,(int)out);
3438 }
3439 if(!c||!memtarget)
3440 add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
3441 if(!using_tlb) {
3442 #ifdef RAM_OFFSET
3443 int map=get_reg(i_regs->regmap,ROREG);
3444 if(map<0) map=HOST_TEMPREG;
3445 gen_orig_addr_w(temp,map);
3446 #else
3447 emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3448 #endif
3449 #if defined(HOST_IMM8)
3450 int ir=get_reg(i_regs->regmap,INVCP);
3451 assert(ir>=0);
3452 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3453 #else
3454 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3455 #endif
3456 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3457 emit_callne(invalidate_addr_reg[temp]);
3458 #else
3459 jaddr2=(int)out;
3460 emit_jne(0);
3461 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3462 #endif
3463 }
3464 /*
3465 emit_pusha();
3466 //save_regs(0x100f);
3467 emit_readword((int)&last_count,ECX);
3468 if(get_reg(i_regs->regmap,CCREG)<0)
3469 emit_loadreg(CCREG,HOST_CCREG);
3470 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3471 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3472 emit_writeword(HOST_CCREG,(int)&Count);
3473 emit_call((int)memdebug);
3474 emit_popa();
3475 //restore_regs(0x100f);
3476 /**/
3477}
3478
3479void c1ls_assemble(int i,struct regstat *i_regs)
3480{
3481#ifndef DISABLE_COP1
3482 int s,th,tl;
3483 int temp,ar;
3484 int map=-1;
3485 int offset;
3486 int c=0;
3487 int jaddr,jaddr2=0,jaddr3,type;
3488 int agr=AGEN1+(i&1);
3489 u_int hr,reglist=0;
3490 th=get_reg(i_regs->regmap,FTEMP|64);
3491 tl=get_reg(i_regs->regmap,FTEMP);
3492 s=get_reg(i_regs->regmap,rs1[i]);
3493 temp=get_reg(i_regs->regmap,agr);
3494 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3495 offset=imm[i];
3496 assert(tl>=0);
3497 assert(rs1[i]>0);
3498 assert(temp>=0);
3499 for(hr=0;hr<HOST_REGS;hr++) {
3500 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3501 }
3502 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3503 if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3504 {
3505 // Loads use a temporary register which we need to save
3506 reglist|=1<<temp;
3507 }
3508 if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3509 ar=temp;
3510 else // LWC1/LDC1
3511 ar=tl;
3512 //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3513 //else c=(i_regs->wasconst>>s)&1;
3514 if(s>=0) c=(i_regs->wasconst>>s)&1;
3515 // Check cop1 unusable
3516 if(!cop1_usable) {
3517 signed char rs=get_reg(i_regs->regmap,CSREG);
3518 assert(rs>=0);
3519 emit_testimm(rs,0x20000000);
3520 jaddr=(int)out;
3521 emit_jeq(0);
3522 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3523 cop1_usable=1;
3524 }
3525 if (opcode[i]==0x39) { // SWC1 (get float address)
3526 emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],tl);
3527 }
3528 if (opcode[i]==0x3D) { // SDC1 (get double address)
3529 emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],tl);
3530 }
3531 // Generate address + offset
3532 if(!using_tlb) {
3533 if(!c)
3534 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3535 }
3536 else
3537 {
3538 map=get_reg(i_regs->regmap,TLREG);
3539 assert(map>=0);
3540 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3541 map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3542 }
3543 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3544 map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3545 }
3546 }
3547 if (opcode[i]==0x39) { // SWC1 (read float)
3548 emit_readword_indexed(0,tl,tl);
3549 }
3550 if (opcode[i]==0x3D) { // SDC1 (read double)
3551 emit_readword_indexed(4,tl,th);
3552 emit_readword_indexed(0,tl,tl);
3553 }
3554 if (opcode[i]==0x31) { // LWC1 (get target address)
3555 emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],temp);
3556 }
3557 if (opcode[i]==0x35) { // LDC1 (get target address)
3558 emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],temp);
3559 }
3560 if(!using_tlb) {
3561 if(!c) {
3562 jaddr2=(int)out;
3563 emit_jno(0);
3564 }
3565 else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
3566 jaddr2=(int)out;
3567 emit_jmp(0); // inline_readstub/inline_writestub? Very rare case
3568 }
3569 #ifdef DESTRUCTIVE_SHIFT
3570 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3571 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3572 }
3573 #endif
3574 }else{
3575 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3576 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3577 }
3578 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3579 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3580 }
3581 }
3582 if (opcode[i]==0x31) { // LWC1
3583 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3584 //gen_tlb_addr_r(ar,map);
3585 //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3586 #ifdef HOST_IMM_ADDR32
3587 if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3588 else
3589 #endif
3590 emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3591 type=LOADW_STUB;
3592 }
3593 if (opcode[i]==0x35) { // LDC1
3594 assert(th>=0);
3595 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3596 //gen_tlb_addr_r(ar,map);
3597 //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3598 //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3599 #ifdef HOST_IMM_ADDR32
3600 if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3601 else
3602 #endif
3603 emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3604 type=LOADD_STUB;
3605 }
3606 if (opcode[i]==0x39) { // SWC1
3607 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3608 emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3609 type=STOREW_STUB;
3610 }
3611 if (opcode[i]==0x3D) { // SDC1
3612 assert(th>=0);
3613 //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3614 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3615 emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3616 type=STORED_STUB;
3617 }
3618 if(!using_tlb) {
3619 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3620 #ifndef DESTRUCTIVE_SHIFT
3621 temp=offset||c||s<0?ar:s;
3622 #endif
3623 #if defined(HOST_IMM8)
3624 int ir=get_reg(i_regs->regmap,INVCP);
3625 assert(ir>=0);
3626 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3627 #else
3628 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3629 #endif
3630 jaddr3=(int)out;
3631 emit_jne(0);
3632 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3633 }
3634 }
3635 if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3636 if (opcode[i]==0x31) { // LWC1 (write float)
3637 emit_writeword_indexed(tl,0,temp);
3638 }
3639 if (opcode[i]==0x35) { // LDC1 (write double)
3640 emit_writeword_indexed(th,4,temp);
3641 emit_writeword_indexed(tl,0,temp);
3642 }
3643 //if(opcode[i]==0x39)
3644 /*if(opcode[i]==0x39||opcode[i]==0x31)
3645 {
3646 emit_pusha();
3647 emit_readword((int)&last_count,ECX);
3648 if(get_reg(i_regs->regmap,CCREG)<0)
3649 emit_loadreg(CCREG,HOST_CCREG);
3650 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3651 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3652 emit_writeword(HOST_CCREG,(int)&Count);
3653 emit_call((int)memdebug);
3654 emit_popa();
3655 }/**/
3656#else
3657 cop1_unusable(i, i_regs);
3658#endif
3659}
3660
3661void c2ls_assemble(int i,struct regstat *i_regs)
3662{
3663 int s,tl;
3664 int ar;
3665 int offset;
3666 int memtarget=0,c=0;
3667 int jaddr,jaddr2=0,jaddr3,type;
3668 int agr=AGEN1+(i&1);
3669 u_int hr,reglist=0;
3670 u_int copr=(source[i]>>16)&0x1f;
3671 s=get_reg(i_regs->regmap,rs1[i]);
3672 tl=get_reg(i_regs->regmap,FTEMP);
3673 offset=imm[i];
3674 assert(rs1[i]>0);
3675 assert(tl>=0);
3676 assert(!using_tlb);
3677
3678 for(hr=0;hr<HOST_REGS;hr++) {
3679 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3680 }
3681 if(i_regs->regmap[HOST_CCREG]==CCREG)
3682 reglist&=~(1<<HOST_CCREG);
3683
3684 // get the address
3685 if (opcode[i]==0x3a) { // SWC2
3686 ar=get_reg(i_regs->regmap,agr);
3687 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3688 reglist|=1<<ar;
3689 } else { // LWC2
3690 ar=tl;
3691 }
3692 if(s>=0) c=(i_regs->wasconst>>s)&1;
3693 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3694 if (!offset&&!c&&s>=0) ar=s;
3695 assert(ar>=0);
3696
3697 if (opcode[i]==0x3a) { // SWC2
3698 cop2_get_dreg(copr,tl,HOST_TEMPREG);
3699 type=STOREW_STUB;
3700 }
3701 else
3702 type=LOADW_STUB;
3703
3704 if(c&&!memtarget) {
3705 jaddr2=(int)out;
3706 emit_jmp(0); // inline_readstub/inline_writestub?
3707 }
3708 else {
3709 if(!c) {
3710 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3711 jaddr2=(int)out;
3712 emit_jno(0);
3713 }
3714 if (opcode[i]==0x32) { // LWC2
3715 #ifdef HOST_IMM_ADDR32
3716 if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3717 else
3718 #endif
3719 emit_readword_indexed(0,ar,tl);
3720 }
3721 if (opcode[i]==0x3a) { // SWC2
3722 #ifdef DESTRUCTIVE_SHIFT
3723 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3724 #endif
3725 emit_writeword_indexed(tl,0,ar);
3726 }
3727 }
3728 if(jaddr2)
3729 add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3730 if (opcode[i]==0x3a) { // SWC2
3731#if defined(HOST_IMM8)
3732 int ir=get_reg(i_regs->regmap,INVCP);
3733 assert(ir>=0);
3734 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3735#else
3736 emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3737#endif
3738 jaddr3=(int)out;
3739 emit_jne(0);
3740 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3741 }
3742 if (opcode[i]==0x32) { // LWC2
3743 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3744 }
3745}
3746
3747#ifndef multdiv_assemble
3748void multdiv_assemble(int i,struct regstat *i_regs)
3749{
3750 printf("Need multdiv_assemble for this architecture.\n");
3751 exit(1);
3752}
3753#endif
3754
3755void mov_assemble(int i,struct regstat *i_regs)
3756{
3757 //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3758 //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3759 if(rt1[i]) {
3760 signed char sh,sl,th,tl;
3761 th=get_reg(i_regs->regmap,rt1[i]|64);
3762 tl=get_reg(i_regs->regmap,rt1[i]);
3763 //assert(tl>=0);
3764 if(tl>=0) {
3765 sh=get_reg(i_regs->regmap,rs1[i]|64);
3766 sl=get_reg(i_regs->regmap,rs1[i]);
3767 if(sl>=0) emit_mov(sl,tl);
3768 else emit_loadreg(rs1[i],tl);
3769 if(th>=0) {
3770 if(sh>=0) emit_mov(sh,th);
3771 else emit_loadreg(rs1[i]|64,th);
3772 }
3773 }
3774 }
3775}
3776
3777#ifndef fconv_assemble
3778void fconv_assemble(int i,struct regstat *i_regs)
3779{
3780 printf("Need fconv_assemble for this architecture.\n");
3781 exit(1);
3782}
3783#endif
3784
3785#if 0
3786void float_assemble(int i,struct regstat *i_regs)
3787{
3788 printf("Need float_assemble for this architecture.\n");
3789 exit(1);
3790}
3791#endif
3792
3793void syscall_assemble(int i,struct regstat *i_regs)
3794{
3795 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3796 assert(ccreg==HOST_CCREG);
3797 assert(!is_delayslot);
3798 emit_movimm(start+i*4,EAX); // Get PC
3799 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
3800 emit_jmp((int)jump_syscall_hle); // XXX
3801}
3802
3803void hlecall_assemble(int i,struct regstat *i_regs)
3804{
3805 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3806 assert(ccreg==HOST_CCREG);
3807 assert(!is_delayslot);
3808 emit_movimm(start+i*4+4,0); // Get PC
3809 emit_movimm((int)psxHLEt[source[i]&7],1);
3810 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // XXX
3811 emit_jmp((int)jump_hlecall);
3812}
3813
3814void intcall_assemble(int i,struct regstat *i_regs)
3815{
3816 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3817 assert(ccreg==HOST_CCREG);
3818 assert(!is_delayslot);
3819 emit_movimm(start+i*4,0); // Get PC
3820 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3821 emit_jmp((int)jump_intcall);
3822}
3823
3824void ds_assemble(int i,struct regstat *i_regs)
3825{
3826 is_delayslot=1;
3827 switch(itype[i]) {
3828 case ALU:
3829 alu_assemble(i,i_regs);break;
3830 case IMM16:
3831 imm16_assemble(i,i_regs);break;
3832 case SHIFT:
3833 shift_assemble(i,i_regs);break;
3834 case SHIFTIMM:
3835 shiftimm_assemble(i,i_regs);break;
3836 case LOAD:
3837 load_assemble(i,i_regs);break;
3838 case LOADLR:
3839 loadlr_assemble(i,i_regs);break;
3840 case STORE:
3841 store_assemble(i,i_regs);break;
3842 case STORELR:
3843 storelr_assemble(i,i_regs);break;
3844 case COP0:
3845 cop0_assemble(i,i_regs);break;
3846 case COP1:
3847 cop1_assemble(i,i_regs);break;
3848 case C1LS:
3849 c1ls_assemble(i,i_regs);break;
3850 case COP2:
3851 cop2_assemble(i,i_regs);break;
3852 case C2LS:
3853 c2ls_assemble(i,i_regs);break;
3854 case C2OP:
3855 c2op_assemble(i,i_regs);break;
3856 case FCONV:
3857 fconv_assemble(i,i_regs);break;
3858 case FLOAT:
3859 float_assemble(i,i_regs);break;
3860 case FCOMP:
3861 fcomp_assemble(i,i_regs);break;
3862 case MULTDIV:
3863 multdiv_assemble(i,i_regs);break;
3864 case MOV:
3865 mov_assemble(i,i_regs);break;
3866 case SYSCALL:
3867 case HLECALL:
3868 case INTCALL:
3869 case SPAN:
3870 case UJUMP:
3871 case RJUMP:
3872 case CJUMP:
3873 case SJUMP:
3874 case FJUMP:
3875 printf("Jump in the delay slot. This is probably a bug.\n");
3876 }
3877 is_delayslot=0;
3878}
3879
3880// Is the branch target a valid internal jump?
3881int internal_branch(uint64_t i_is32,int addr)
3882{
3883 if(addr&1) return 0; // Indirect (register) jump
3884 if(addr>=start && addr<start+slen*4-4)
3885 {
3886 int t=(addr-start)>>2;
3887 // Delay slots are not valid branch targets
3888 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
3889 // 64 -> 32 bit transition requires a recompile
3890 /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
3891 {
3892 if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
3893 else printf("optimizable: yes\n");
3894 }*/
3895 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
3896#ifndef FORCE32
3897 if(requires_32bit[t]&~i_is32) return 0;
3898 else
3899#endif
3900 return 1;
3901 }
3902 return 0;
3903}
3904
3905#ifndef wb_invalidate
3906void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
3907 uint64_t u,uint64_t uu)
3908{
3909 int hr;
3910 for(hr=0;hr<HOST_REGS;hr++) {
3911 if(hr!=EXCLUDE_REG) {
3912 if(pre[hr]!=entry[hr]) {
3913 if(pre[hr]>=0) {
3914 if((dirty>>hr)&1) {
3915 if(get_reg(entry,pre[hr])<0) {
3916 if(pre[hr]<64) {
3917 if(!((u>>pre[hr])&1)) {
3918 emit_storereg(pre[hr],hr);
3919 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
3920 emit_sarimm(hr,31,hr);
3921 emit_storereg(pre[hr]|64,hr);
3922 }
3923 }
3924 }else{
3925 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
3926 emit_storereg(pre[hr],hr);
3927 }
3928 }
3929 }
3930 }
3931 }
3932 }
3933 }
3934 }
3935 // Move from one register to another (no writeback)
3936 for(hr=0;hr<HOST_REGS;hr++) {
3937 if(hr!=EXCLUDE_REG) {
3938 if(pre[hr]!=entry[hr]) {
3939 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
3940 int nr;
3941 if((nr=get_reg(entry,pre[hr]))>=0) {
3942 emit_mov(hr,nr);
3943 }
3944 }
3945 }
3946 }
3947 }
3948}
3949#endif
3950
3951// Load the specified registers
3952// This only loads the registers given as arguments because
3953// we don't want to load things that will be overwritten
3954void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
3955{
3956 int hr;
3957 // Load 32-bit regs
3958 for(hr=0;hr<HOST_REGS;hr++) {
3959 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
3960 if(entry[hr]!=regmap[hr]) {
3961 if(regmap[hr]==rs1||regmap[hr]==rs2)
3962 {
3963 if(regmap[hr]==0) {
3964 emit_zeroreg(hr);
3965 }
3966 else
3967 {
3968 emit_loadreg(regmap[hr],hr);
3969 }
3970 }
3971 }
3972 }
3973 }
3974 //Load 64-bit regs
3975 for(hr=0;hr<HOST_REGS;hr++) {
3976 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
3977 if(entry[hr]!=regmap[hr]) {
3978 if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
3979 {
3980 assert(regmap[hr]!=64);
3981 if((is32>>(regmap[hr]&63))&1) {
3982 int lr=get_reg(regmap,regmap[hr]-64);
3983 if(lr>=0)
3984 emit_sarimm(lr,31,hr);
3985 else
3986 emit_loadreg(regmap[hr],hr);
3987 }
3988 else
3989 {
3990 emit_loadreg(regmap[hr],hr);
3991 }
3992 }
3993 }
3994 }
3995 }
3996}
3997
3998// Load registers prior to the start of a loop
3999// so that they are not loaded within the loop
4000static void loop_preload(signed char pre[],signed char entry[])
4001{
4002 int hr;
4003 for(hr=0;hr<HOST_REGS;hr++) {
4004 if(hr!=EXCLUDE_REG) {
4005 if(pre[hr]!=entry[hr]) {
4006 if(entry[hr]>=0) {
4007 if(get_reg(pre,entry[hr])<0) {
4008 assem_debug("loop preload:\n");
4009 //printf("loop preload: %d\n",hr);
4010 if(entry[hr]==0) {
4011 emit_zeroreg(hr);
4012 }
4013 else if(entry[hr]<TEMPREG)
4014 {
4015 emit_loadreg(entry[hr],hr);
4016 }
4017 else if(entry[hr]-64<TEMPREG)
4018 {
4019 emit_loadreg(entry[hr],hr);
4020 }
4021 }
4022 }
4023 }
4024 }
4025 }
4026}
4027
4028// Generate address for load/store instruction
4029// goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
4030void address_generation(int i,struct regstat *i_regs,signed char entry[])
4031{
4032 if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
4033 int ra;
4034 int agr=AGEN1+(i&1);
4035 int mgr=MGEN1+(i&1);
4036 if(itype[i]==LOAD) {
4037 ra=get_reg(i_regs->regmap,rt1[i]);
4038 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4039 assert(ra>=0);
4040 }
4041 if(itype[i]==LOADLR) {
4042 ra=get_reg(i_regs->regmap,FTEMP);
4043 }
4044 if(itype[i]==STORE||itype[i]==STORELR) {
4045 ra=get_reg(i_regs->regmap,agr);
4046 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4047 }
4048 if(itype[i]==C1LS||itype[i]==C2LS) {
4049 if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
4050 ra=get_reg(i_regs->regmap,FTEMP);
4051 else { // SWC1/SDC1/SWC2/SDC2
4052 ra=get_reg(i_regs->regmap,agr);
4053 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4054 }
4055 }
4056 int rs=get_reg(i_regs->regmap,rs1[i]);
4057 int rm=get_reg(i_regs->regmap,TLREG);
4058 if(ra>=0) {
4059 int offset=imm[i];
4060 int c=(i_regs->wasconst>>rs)&1;
4061 if(rs1[i]==0) {
4062 // Using r0 as a base address
4063 /*if(rm>=0) {
4064 if(!entry||entry[rm]!=mgr) {
4065 generate_map_const(offset,rm);
4066 } // else did it in the previous cycle
4067 }*/
4068 if(!entry||entry[ra]!=agr) {
4069 if (opcode[i]==0x22||opcode[i]==0x26) {
4070 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4071 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4072 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4073 }else{
4074 emit_movimm(offset,ra);
4075 }
4076 } // else did it in the previous cycle
4077 }
4078 else if(rs<0) {
4079 if(!entry||entry[ra]!=rs1[i])
4080 emit_loadreg(rs1[i],ra);
4081 //if(!entry||entry[ra]!=rs1[i])
4082 // printf("poor load scheduling!\n");
4083 }
4084 else if(c) {
4085 if(rm>=0) {
4086 if(!entry||entry[rm]!=mgr) {
4087 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
4088 // Stores to memory go thru the mapper to detect self-modifying
4089 // code, loads don't.
4090 if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
4091 (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
4092 generate_map_const(constmap[i][rs]+offset,rm);
4093 }else{
4094 if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
4095 generate_map_const(constmap[i][rs]+offset,rm);
4096 }
4097 }
4098 }
4099 if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
4100 if(!entry||entry[ra]!=agr) {
4101 if (opcode[i]==0x22||opcode[i]==0x26) {
4102 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4103 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4104 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4105 }else{
4106 #ifdef HOST_IMM_ADDR32
4107 if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4108 (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4109 #endif
4110 emit_movimm(constmap[i][rs]+offset,ra);
4111 }
4112 } // else did it in the previous cycle
4113 } // else load_consts already did it
4114 }
4115 if(offset&&!c&&rs1[i]) {
4116 if(rs>=0) {
4117 emit_addimm(rs,offset,ra);
4118 }else{
4119 emit_addimm(ra,offset,ra);
4120 }
4121 }
4122 }
4123 }
4124 // Preload constants for next instruction
4125 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
4126 int agr,ra;
4127 #ifndef HOST_IMM_ADDR32
4128 // Mapper entry
4129 agr=MGEN1+((i+1)&1);
4130 ra=get_reg(i_regs->regmap,agr);
4131 if(ra>=0) {
4132 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4133 int offset=imm[i+1];
4134 int c=(regs[i+1].wasconst>>rs)&1;
4135 if(c) {
4136 if(itype[i+1]==STORE||itype[i+1]==STORELR
4137 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
4138 // Stores to memory go thru the mapper to detect self-modifying
4139 // code, loads don't.
4140 if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4141 (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
4142 generate_map_const(constmap[i+1][rs]+offset,ra);
4143 }else{
4144 if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4145 generate_map_const(constmap[i+1][rs]+offset,ra);
4146 }
4147 }
4148 /*else if(rs1[i]==0) {
4149 generate_map_const(offset,ra);
4150 }*/
4151 }
4152 #endif
4153 // Actual address
4154 agr=AGEN1+((i+1)&1);
4155 ra=get_reg(i_regs->regmap,agr);
4156 if(ra>=0) {
4157 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4158 int offset=imm[i+1];
4159 int c=(regs[i+1].wasconst>>rs)&1;
4160 if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4161 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4162 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4163 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4164 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4165 }else{
4166 #ifdef HOST_IMM_ADDR32
4167 if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4168 (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4169 #endif
4170 emit_movimm(constmap[i+1][rs]+offset,ra);
4171 }
4172 }
4173 else if(rs1[i+1]==0) {
4174 // Using r0 as a base address
4175 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4176 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4177 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4178 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4179 }else{
4180 emit_movimm(offset,ra);
4181 }
4182 }
4183 }
4184 }
4185}
4186
4187int get_final_value(int hr, int i, int *value)
4188{
4189 int reg=regs[i].regmap[hr];
4190 while(i<slen-1) {
4191 if(regs[i+1].regmap[hr]!=reg) break;
4192 if(!((regs[i+1].isconst>>hr)&1)) break;
4193 if(bt[i+1]) break;
4194 i++;
4195 }
4196 if(i<slen-1) {
4197 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4198 *value=constmap[i][hr];
4199 return 1;
4200 }
4201 if(!bt[i+1]) {
4202 if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4203 // Load in delay slot, out-of-order execution
4204 if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4205 {
4206 #ifdef HOST_IMM_ADDR32
4207 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4208 #endif
4209 // Precompute load address
4210 *value=constmap[i][hr]+imm[i+2];
4211 return 1;
4212 }
4213 }
4214 if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4215 {
4216 #ifdef HOST_IMM_ADDR32
4217 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4218 #endif
4219 // Precompute load address
4220 *value=constmap[i][hr]+imm[i+1];
4221 //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4222 return 1;
4223 }
4224 }
4225 }
4226 *value=constmap[i][hr];
4227 //printf("c=%x\n",(int)constmap[i][hr]);
4228 if(i==slen-1) return 1;
4229 if(reg<64) {
4230 return !((unneeded_reg[i+1]>>reg)&1);
4231 }else{
4232 return !((unneeded_reg_upper[i+1]>>reg)&1);
4233 }
4234}
4235
4236// Load registers with known constants
4237void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4238{
4239 int hr;
4240 // Load 32-bit regs
4241 for(hr=0;hr<HOST_REGS;hr++) {
4242 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4243 //if(entry[hr]!=regmap[hr]) {
4244 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4245 if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4246 int value;
4247 if(get_final_value(hr,i,&value)) {
4248 if(value==0) {
4249 emit_zeroreg(hr);
4250 }
4251 else {
4252 emit_movimm(value,hr);
4253 }
4254 }
4255 }
4256 }
4257 }
4258 }
4259 // Load 64-bit regs
4260 for(hr=0;hr<HOST_REGS;hr++) {
4261 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4262 //if(entry[hr]!=regmap[hr]) {
4263 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4264 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4265 if((is32>>(regmap[hr]&63))&1) {
4266 int lr=get_reg(regmap,regmap[hr]-64);
4267 assert(lr>=0);
4268 emit_sarimm(lr,31,hr);
4269 }
4270 else
4271 {
4272 int value;
4273 if(get_final_value(hr,i,&value)) {
4274 if(value==0) {
4275 emit_zeroreg(hr);
4276 }
4277 else {
4278 emit_movimm(value,hr);
4279 }
4280 }
4281 }
4282 }
4283 }
4284 }
4285 }
4286}
4287void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4288{
4289 int hr;
4290 // Load 32-bit regs
4291 for(hr=0;hr<HOST_REGS;hr++) {
4292 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4293 if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4294 int value=constmap[i][hr];
4295 if(value==0) {
4296 emit_zeroreg(hr);
4297 }
4298 else {
4299 emit_movimm(value,hr);
4300 }
4301 }
4302 }
4303 }
4304 // Load 64-bit regs
4305 for(hr=0;hr<HOST_REGS;hr++) {
4306 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4307 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4308 if((is32>>(regmap[hr]&63))&1) {
4309 int lr=get_reg(regmap,regmap[hr]-64);
4310 assert(lr>=0);
4311 emit_sarimm(lr,31,hr);
4312 }
4313 else
4314 {
4315 int value=constmap[i][hr];
4316 if(value==0) {
4317 emit_zeroreg(hr);
4318 }
4319 else {
4320 emit_movimm(value,hr);
4321 }
4322 }
4323 }
4324 }
4325 }
4326}
4327
4328// Write out all dirty registers (except cycle count)
4329void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4330{
4331 int hr;
4332 for(hr=0;hr<HOST_REGS;hr++) {
4333 if(hr!=EXCLUDE_REG) {
4334 if(i_regmap[hr]>0) {
4335 if(i_regmap[hr]!=CCREG) {
4336 if((i_dirty>>hr)&1) {
4337 if(i_regmap[hr]<64) {
4338 emit_storereg(i_regmap[hr],hr);
4339#ifndef FORCE32
4340 if( ((i_is32>>i_regmap[hr])&1) ) {
4341 #ifdef DESTRUCTIVE_WRITEBACK
4342 emit_sarimm(hr,31,hr);
4343 emit_storereg(i_regmap[hr]|64,hr);
4344 #else
4345 emit_sarimm(hr,31,HOST_TEMPREG);
4346 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4347 #endif
4348 }
4349#endif
4350 }else{
4351 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4352 emit_storereg(i_regmap[hr],hr);
4353 }
4354 }
4355 }
4356 }
4357 }
4358 }
4359 }
4360}
4361// Write out dirty registers that we need to reload (pair with load_needed_regs)
4362// This writes the registers not written by store_regs_bt
4363void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4364{
4365 int hr;
4366 int t=(addr-start)>>2;
4367 for(hr=0;hr<HOST_REGS;hr++) {
4368 if(hr!=EXCLUDE_REG) {
4369 if(i_regmap[hr]>0) {
4370 if(i_regmap[hr]!=CCREG) {
4371 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4372 if((i_dirty>>hr)&1) {
4373 if(i_regmap[hr]<64) {
4374 emit_storereg(i_regmap[hr],hr);
4375#ifndef FORCE32
4376 if( ((i_is32>>i_regmap[hr])&1) ) {
4377 #ifdef DESTRUCTIVE_WRITEBACK
4378 emit_sarimm(hr,31,hr);
4379 emit_storereg(i_regmap[hr]|64,hr);
4380 #else
4381 emit_sarimm(hr,31,HOST_TEMPREG);
4382 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4383 #endif
4384 }
4385#endif
4386 }else{
4387 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4388 emit_storereg(i_regmap[hr],hr);
4389 }
4390 }
4391 }
4392 }
4393 }
4394 }
4395 }
4396 }
4397}
4398
4399// Load all registers (except cycle count)
4400void load_all_regs(signed char i_regmap[])
4401{
4402 int hr;
4403 for(hr=0;hr<HOST_REGS;hr++) {
4404 if(hr!=EXCLUDE_REG) {
4405 if(i_regmap[hr]==0) {
4406 emit_zeroreg(hr);
4407 }
4408 else
4409 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG)
4410 {
4411 emit_loadreg(i_regmap[hr],hr);
4412 }
4413 }
4414 }
4415}
4416
4417// Load all current registers also needed by next instruction
4418void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4419{
4420 int hr;
4421 for(hr=0;hr<HOST_REGS;hr++) {
4422 if(hr!=EXCLUDE_REG) {
4423 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4424 if(i_regmap[hr]==0) {
4425 emit_zeroreg(hr);
4426 }
4427 else
4428 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG)
4429 {
4430 emit_loadreg(i_regmap[hr],hr);
4431 }
4432 }
4433 }
4434 }
4435}
4436
4437// Load all regs, storing cycle count if necessary
4438void load_regs_entry(int t)
4439{
4440 int hr;
4441 if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER,HOST_CCREG);
4442 else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t]*CLOCK_DIVIDER,HOST_CCREG);
4443 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4444 emit_storereg(CCREG,HOST_CCREG);
4445 }
4446 // Load 32-bit regs
4447 for(hr=0;hr<HOST_REGS;hr++) {
4448 if(regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<64) {
4449 if(regs[t].regmap_entry[hr]==0) {
4450 emit_zeroreg(hr);
4451 }
4452 else if(regs[t].regmap_entry[hr]!=CCREG)
4453 {
4454 emit_loadreg(regs[t].regmap_entry[hr],hr);
4455 }
4456 }
4457 }
4458 // Load 64-bit regs
4459 for(hr=0;hr<HOST_REGS;hr++) {
4460 if(regs[t].regmap_entry[hr]>=64) {
4461 assert(regs[t].regmap_entry[hr]!=64);
4462 if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4463 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4464 if(lr<0) {
4465 emit_loadreg(regs[t].regmap_entry[hr],hr);
4466 }
4467 else
4468 {
4469 emit_sarimm(lr,31,hr);
4470 }
4471 }
4472 else
4473 {
4474 emit_loadreg(regs[t].regmap_entry[hr],hr);
4475 }
4476 }
4477 }
4478}
4479
4480// Store dirty registers prior to branch
4481void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4482{
4483 if(internal_branch(i_is32,addr))
4484 {
4485 int t=(addr-start)>>2;
4486 int hr;
4487 for(hr=0;hr<HOST_REGS;hr++) {
4488 if(hr!=EXCLUDE_REG) {
4489 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4490 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4491 if((i_dirty>>hr)&1) {
4492 if(i_regmap[hr]<64) {
4493 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4494 emit_storereg(i_regmap[hr],hr);
4495 if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4496 #ifdef DESTRUCTIVE_WRITEBACK
4497 emit_sarimm(hr,31,hr);
4498 emit_storereg(i_regmap[hr]|64,hr);
4499 #else
4500 emit_sarimm(hr,31,HOST_TEMPREG);
4501 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4502 #endif
4503 }
4504 }
4505 }else{
4506 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4507 emit_storereg(i_regmap[hr],hr);
4508 }
4509 }
4510 }
4511 }
4512 }
4513 }
4514 }
4515 }
4516 else
4517 {
4518 // Branch out of this block, write out all dirty regs
4519 wb_dirtys(i_regmap,i_is32,i_dirty);
4520 }
4521}
4522
4523// Load all needed registers for branch target
4524void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4525{
4526 //if(addr>=start && addr<(start+slen*4))
4527 if(internal_branch(i_is32,addr))
4528 {
4529 int t=(addr-start)>>2;
4530 int hr;
4531 // Store the cycle count before loading something else
4532 if(i_regmap[HOST_CCREG]!=CCREG) {
4533 assert(i_regmap[HOST_CCREG]==-1);
4534 }
4535 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4536 emit_storereg(CCREG,HOST_CCREG);
4537 }
4538 // Load 32-bit regs
4539 for(hr=0;hr<HOST_REGS;hr++) {
4540 if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<64) {
4541 #ifdef DESTRUCTIVE_WRITEBACK
4542 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4543 #else
4544 if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4545 #endif
4546 if(regs[t].regmap_entry[hr]==0) {
4547 emit_zeroreg(hr);
4548 }
4549 else if(regs[t].regmap_entry[hr]!=CCREG)
4550 {
4551 emit_loadreg(regs[t].regmap_entry[hr],hr);
4552 }
4553 }
4554 }
4555 }
4556 //Load 64-bit regs
4557 for(hr=0;hr<HOST_REGS;hr++) {
4558 if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=64) {
4559 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4560 assert(regs[t].regmap_entry[hr]!=64);
4561 if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4562 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4563 if(lr<0) {
4564 emit_loadreg(regs[t].regmap_entry[hr],hr);
4565 }
4566 else
4567 {
4568 emit_sarimm(lr,31,hr);
4569 }
4570 }
4571 else
4572 {
4573 emit_loadreg(regs[t].regmap_entry[hr],hr);
4574 }
4575 }
4576 else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4577 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4578 assert(lr>=0);
4579 emit_sarimm(lr,31,hr);
4580 }
4581 }
4582 }
4583 }
4584}
4585
4586int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4587{
4588 if(addr>=start && addr<start+slen*4-4)
4589 {
4590 int t=(addr-start)>>2;
4591 int hr;
4592 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4593 for(hr=0;hr<HOST_REGS;hr++)
4594 {
4595 if(hr!=EXCLUDE_REG)
4596 {
4597 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4598 {
4599 if(regs[t].regmap_entry[hr]!=-1)
4600 {
4601 return 0;
4602 }
4603 else
4604 if((i_dirty>>hr)&1)
4605 {
4606 if(i_regmap[hr]<64)
4607 {
4608 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4609 return 0;
4610 }
4611 else
4612 {
4613 if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4614 return 0;
4615 }
4616 }
4617 }
4618 else // Same register but is it 32-bit or dirty?
4619 if(i_regmap[hr]>=0)
4620 {
4621 if(!((regs[t].dirty>>hr)&1))
4622 {
4623 if((i_dirty>>hr)&1)
4624 {
4625 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4626 {
4627 //printf("%x: dirty no match\n",addr);
4628 return 0;
4629 }
4630 }
4631 }
4632 if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4633 {
4634 //printf("%x: is32 no match\n",addr);
4635 return 0;
4636 }
4637 }
4638 }
4639 }
4640 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4641#ifndef FORCE32
4642 if(requires_32bit[t]&~i_is32) return 0;
4643#endif
4644 // Delay slots are not valid branch targets
4645 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4646 // Delay slots require additional processing, so do not match
4647 if(is_ds[t]) return 0;
4648 }
4649 else
4650 {
4651 int hr;
4652 for(hr=0;hr<HOST_REGS;hr++)
4653 {
4654 if(hr!=EXCLUDE_REG)
4655 {
4656 if(i_regmap[hr]>=0)
4657 {
4658 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4659 {
4660 if((i_dirty>>hr)&1)
4661 {
4662 return 0;
4663 }
4664 }
4665 }
4666 }
4667 }
4668 }
4669 return 1;
4670}
4671
4672// Used when a branch jumps into the delay slot of another branch
4673void ds_assemble_entry(int i)
4674{
4675 int t=(ba[i]-start)>>2;
4676 if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4677 assem_debug("Assemble delay slot at %x\n",ba[i]);
4678 assem_debug("<->\n");
4679 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
4680 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4681 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4682 address_generation(t,&regs[t],regs[t].regmap_entry);
4683 if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
4684 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4685 cop1_usable=0;
4686 is_delayslot=0;
4687 switch(itype[t]) {
4688 case ALU:
4689 alu_assemble(t,&regs[t]);break;
4690 case IMM16:
4691 imm16_assemble(t,&regs[t]);break;
4692 case SHIFT:
4693 shift_assemble(t,&regs[t]);break;
4694 case SHIFTIMM:
4695 shiftimm_assemble(t,&regs[t]);break;
4696 case LOAD:
4697 load_assemble(t,&regs[t]);break;
4698 case LOADLR:
4699 loadlr_assemble(t,&regs[t]);break;
4700 case STORE:
4701 store_assemble(t,&regs[t]);break;
4702 case STORELR:
4703 storelr_assemble(t,&regs[t]);break;
4704 case COP0:
4705 cop0_assemble(t,&regs[t]);break;
4706 case COP1:
4707 cop1_assemble(t,&regs[t]);break;
4708 case C1LS:
4709 c1ls_assemble(t,&regs[t]);break;
4710 case COP2:
4711 cop2_assemble(t,&regs[t]);break;
4712 case C2LS:
4713 c2ls_assemble(t,&regs[t]);break;
4714 case C2OP:
4715 c2op_assemble(t,&regs[t]);break;
4716 case FCONV:
4717 fconv_assemble(t,&regs[t]);break;
4718 case FLOAT:
4719 float_assemble(t,&regs[t]);break;
4720 case FCOMP:
4721 fcomp_assemble(t,&regs[t]);break;
4722 case MULTDIV:
4723 multdiv_assemble(t,&regs[t]);break;
4724 case MOV:
4725 mov_assemble(t,&regs[t]);break;
4726 case SYSCALL:
4727 case HLECALL:
4728 case INTCALL:
4729 case SPAN:
4730 case UJUMP:
4731 case RJUMP:
4732 case CJUMP:
4733 case SJUMP:
4734 case FJUMP:
4735 printf("Jump in the delay slot. This is probably a bug.\n");
4736 }
4737 store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4738 load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4739 if(internal_branch(regs[t].is32,ba[i]+4))
4740 assem_debug("branch: internal\n");
4741 else
4742 assem_debug("branch: external\n");
4743 assert(internal_branch(regs[t].is32,ba[i]+4));
4744 add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4745 emit_jmp(0);
4746}
4747
4748void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4749{
4750 int count;
4751 int jaddr;
4752 int idle=0;
4753 if(itype[i]==RJUMP)
4754 {
4755 *adj=0;
4756 }
4757 //if(ba[i]>=start && ba[i]<(start+slen*4))
4758 if(internal_branch(branch_regs[i].is32,ba[i]))
4759 {
4760 int t=(ba[i]-start)>>2;
4761 if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4762 else *adj=ccadj[t];
4763 }
4764 else
4765 {
4766 *adj=0;
4767 }
4768 count=ccadj[i];
4769 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4770 // Idle loop
4771 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4772 idle=(int)out;
4773 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4774 emit_andimm(HOST_CCREG,3,HOST_CCREG);
4775 jaddr=(int)out;
4776 emit_jmp(0);
4777 }
4778 else if(*adj==0||invert) {
4779 emit_addimm_and_set_flags(CLOCK_DIVIDER*(count+2),HOST_CCREG);
4780 jaddr=(int)out;
4781 emit_jns(0);
4782 }
4783 else
4784 {
4785 emit_cmpimm(HOST_CCREG,-2*(count+2));
4786 jaddr=(int)out;
4787 emit_jns(0);
4788 }
4789 add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4790}
4791
4792void do_ccstub(int n)
4793{
4794 literal_pool(256);
4795 assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
4796 set_jump_target(stubs[n][1],(int)out);
4797 int i=stubs[n][4];
4798 if(stubs[n][6]==NULLDS) {
4799 // Delay slot instruction is nullified ("likely" branch)
4800 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4801 }
4802 else if(stubs[n][6]!=TAKEN) {
4803 wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4804 }
4805 else {
4806 if(internal_branch(branch_regs[i].is32,ba[i]))
4807 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4808 }
4809 if(stubs[n][5]!=-1)
4810 {
4811 // Save PC as return address
4812 emit_movimm(stubs[n][5],EAX);
4813 emit_writeword(EAX,(int)&pcaddr);
4814 }
4815 else
4816 {
4817 // Return address depends on which way the branch goes
4818 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
4819 {
4820 int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4821 int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4822 int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4823 int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4824 if(rs1[i]==0)
4825 {
4826 s1l=s2l;s1h=s2h;
4827 s2l=s2h=-1;
4828 }
4829 else if(rs2[i]==0)
4830 {
4831 s2l=s2h=-1;
4832 }
4833 if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
4834 s1h=s2h=-1;
4835 }
4836 assert(s1l>=0);
4837 #ifdef DESTRUCTIVE_WRITEBACK
4838 if(rs1[i]) {
4839 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
4840 emit_loadreg(rs1[i],s1l);
4841 }
4842 else {
4843 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
4844 emit_loadreg(rs2[i],s1l);
4845 }
4846 if(s2l>=0)
4847 if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
4848 emit_loadreg(rs2[i],s2l);
4849 #endif
4850 int hr=0;
4851 int addr,alt,ntaddr;
4852 while(hr<HOST_REGS)
4853 {
4854 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4855 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4856 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4857 {
4858 addr=hr++;break;
4859 }
4860 hr++;
4861 }
4862 while(hr<HOST_REGS)
4863 {
4864 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4865 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4866 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4867 {
4868 alt=hr++;break;
4869 }
4870 hr++;
4871 }
4872 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
4873 {
4874 while(hr<HOST_REGS)
4875 {
4876 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4877 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4878 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4879 {
4880 ntaddr=hr;break;
4881 }
4882 hr++;
4883 }
4884 assert(hr<HOST_REGS);
4885 }
4886 if((opcode[i]&0x2f)==4) // BEQ
4887 {
4888 #ifdef HAVE_CMOV_IMM
4889 if(s1h<0) {
4890 if(s2l>=0) emit_cmp(s1l,s2l);
4891 else emit_test(s1l,s1l);
4892 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
4893 }
4894 else
4895 #endif
4896 {
4897 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4898 if(s1h>=0) {
4899 if(s2h>=0) emit_cmp(s1h,s2h);
4900 else emit_test(s1h,s1h);
4901 emit_cmovne_reg(alt,addr);
4902 }
4903 if(s2l>=0) emit_cmp(s1l,s2l);
4904 else emit_test(s1l,s1l);
4905 emit_cmovne_reg(alt,addr);
4906 }
4907 }
4908 if((opcode[i]&0x2f)==5) // BNE
4909 {
4910 #ifdef HAVE_CMOV_IMM
4911 if(s1h<0) {
4912 if(s2l>=0) emit_cmp(s1l,s2l);
4913 else emit_test(s1l,s1l);
4914 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
4915 }
4916 else
4917 #endif
4918 {
4919 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
4920 if(s1h>=0) {
4921 if(s2h>=0) emit_cmp(s1h,s2h);
4922 else emit_test(s1h,s1h);
4923 emit_cmovne_reg(alt,addr);
4924 }
4925 if(s2l>=0) emit_cmp(s1l,s2l);
4926 else emit_test(s1l,s1l);
4927 emit_cmovne_reg(alt,addr);
4928 }
4929 }
4930 if((opcode[i]&0x2f)==6) // BLEZ
4931 {
4932 //emit_movimm(ba[i],alt);
4933 //emit_movimm(start+i*4+8,addr);
4934 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4935 emit_cmpimm(s1l,1);
4936 if(s1h>=0) emit_mov(addr,ntaddr);
4937 emit_cmovl_reg(alt,addr);
4938 if(s1h>=0) {
4939 emit_test(s1h,s1h);
4940 emit_cmovne_reg(ntaddr,addr);
4941 emit_cmovs_reg(alt,addr);
4942 }
4943 }
4944 if((opcode[i]&0x2f)==7) // BGTZ
4945 {
4946 //emit_movimm(ba[i],addr);
4947 //emit_movimm(start+i*4+8,ntaddr);
4948 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
4949 emit_cmpimm(s1l,1);
4950 if(s1h>=0) emit_mov(addr,alt);
4951 emit_cmovl_reg(ntaddr,addr);
4952 if(s1h>=0) {
4953 emit_test(s1h,s1h);
4954 emit_cmovne_reg(alt,addr);
4955 emit_cmovs_reg(ntaddr,addr);
4956 }
4957 }
4958 if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
4959 {
4960 //emit_movimm(ba[i],alt);
4961 //emit_movimm(start+i*4+8,addr);
4962 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4963 if(s1h>=0) emit_test(s1h,s1h);
4964 else emit_test(s1l,s1l);
4965 emit_cmovs_reg(alt,addr);
4966 }
4967 if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
4968 {
4969 //emit_movimm(ba[i],addr);
4970 //emit_movimm(start+i*4+8,alt);
4971 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4972 if(s1h>=0) emit_test(s1h,s1h);
4973 else emit_test(s1l,s1l);
4974 emit_cmovs_reg(alt,addr);
4975 }
4976 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
4977 if(source[i]&0x10000) // BC1T
4978 {
4979 //emit_movimm(ba[i],alt);
4980 //emit_movimm(start+i*4+8,addr);
4981 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4982 emit_testimm(s1l,0x800000);
4983 emit_cmovne_reg(alt,addr);
4984 }
4985 else // BC1F
4986 {
4987 //emit_movimm(ba[i],addr);
4988 //emit_movimm(start+i*4+8,alt);
4989 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4990 emit_testimm(s1l,0x800000);
4991 emit_cmovne_reg(alt,addr);
4992 }
4993 }
4994 emit_writeword(addr,(int)&pcaddr);
4995 }
4996 else
4997 if(itype[i]==RJUMP)
4998 {
4999 int r=get_reg(branch_regs[i].regmap,rs1[i]);
5000 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5001 r=get_reg(branch_regs[i].regmap,RTEMP);
5002 }
5003 emit_writeword(r,(int)&pcaddr);
5004 }
5005 else {printf("Unknown branch type in do_ccstub\n");exit(1);}
5006 }
5007 // Update cycle count
5008 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5009 if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
5010 emit_call((int)cc_interrupt);
5011 if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
5012 if(stubs[n][6]==TAKEN) {
5013 if(internal_branch(branch_regs[i].is32,ba[i]))
5014 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
5015 else if(itype[i]==RJUMP) {
5016 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5017 emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5018 else
5019 emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
5020 }
5021 }else if(stubs[n][6]==NOTTAKEN) {
5022 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5023 else load_all_regs(branch_regs[i].regmap);
5024 }else if(stubs[n][6]==NULLDS) {
5025 // Delay slot instruction is nullified ("likely" branch)
5026 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5027 else load_all_regs(regs[i].regmap);
5028 }else{
5029 load_all_regs(branch_regs[i].regmap);
5030 }
5031 emit_jmp(stubs[n][2]); // return address
5032
5033 /* This works but uses a lot of memory...
5034 emit_readword((int)&last_count,ECX);
5035 emit_add(HOST_CCREG,ECX,EAX);
5036 emit_writeword(EAX,(int)&Count);
5037 emit_call((int)gen_interupt);
5038 emit_readword((int)&Count,HOST_CCREG);
5039 emit_readword((int)&next_interupt,EAX);
5040 emit_readword((int)&pending_exception,EBX);
5041 emit_writeword(EAX,(int)&last_count);
5042 emit_sub(HOST_CCREG,EAX,HOST_CCREG);
5043 emit_test(EBX,EBX);
5044 int jne_instr=(int)out;
5045 emit_jne(0);
5046 if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
5047 load_all_regs(branch_regs[i].regmap);
5048 emit_jmp(stubs[n][2]); // return address
5049 set_jump_target(jne_instr,(int)out);
5050 emit_readword((int)&pcaddr,EAX);
5051 // Call get_addr_ht instead of doing the hash table here.
5052 // This code is executed infrequently and takes up a lot of space
5053 // so smaller is better.
5054 emit_storereg(CCREG,HOST_CCREG);
5055 emit_pushreg(EAX);
5056 emit_call((int)get_addr_ht);
5057 emit_loadreg(CCREG,HOST_CCREG);
5058 emit_addimm(ESP,4,ESP);
5059 emit_jmpreg(EAX);*/
5060}
5061
5062add_to_linker(int addr,int target,int ext)
5063{
5064 link_addr[linkcount][0]=addr;
5065 link_addr[linkcount][1]=target;
5066 link_addr[linkcount][2]=ext;
5067 linkcount++;
5068}
5069
5070void ujump_assemble(int i,struct regstat *i_regs)
5071{
5072 signed char *i_regmap=i_regs->regmap;
5073 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5074 address_generation(i+1,i_regs,regs[i].regmap_entry);
5075 #ifdef REG_PREFETCH
5076 int temp=get_reg(branch_regs[i].regmap,PTEMP);
5077 if(rt1[i]==31&&temp>=0)
5078 {
5079 int return_address=start+i*4+8;
5080 if(get_reg(branch_regs[i].regmap,31)>0)
5081 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5082 }
5083 #endif
5084 ds_assemble(i+1,i_regs);
5085 uint64_t bc_unneeded=branch_regs[i].u;
5086 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5087 bc_unneeded|=1|(1LL<<rt1[i]);
5088 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5089 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5090 bc_unneeded,bc_unneeded_upper);
5091 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5092 if(rt1[i]==31) {
5093 int rt;
5094 unsigned int return_address;
5095 assert(rt1[i+1]!=31);
5096 assert(rt2[i+1]!=31);
5097 rt=get_reg(branch_regs[i].regmap,31);
5098 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5099 //assert(rt>=0);
5100 return_address=start+i*4+8;
5101 if(rt>=0) {
5102 #ifdef USE_MINI_HT
5103 if(internal_branch(branch_regs[i].is32,return_address)) {
5104 int temp=rt+1;
5105 if(temp==EXCLUDE_REG||temp>=HOST_REGS||
5106 branch_regs[i].regmap[temp]>=0)
5107 {
5108 temp=get_reg(branch_regs[i].regmap,-1);
5109 }
5110 #ifdef HOST_TEMPREG
5111 if(temp<0) temp=HOST_TEMPREG;
5112 #endif
5113 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5114 else emit_movimm(return_address,rt);
5115 }
5116 else
5117 #endif
5118 {
5119 #ifdef REG_PREFETCH
5120 if(temp>=0)
5121 {
5122 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5123 }
5124 #endif
5125 emit_movimm(return_address,rt); // PC into link register
5126 #ifdef IMM_PREFETCH
5127 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5128 #endif
5129 }
5130 }
5131 }
5132 int cc,adj;
5133 cc=get_reg(branch_regs[i].regmap,CCREG);
5134 assert(cc==HOST_CCREG);
5135 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5136 #ifdef REG_PREFETCH
5137 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5138 #endif
5139 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5140 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5141 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5142 if(internal_branch(branch_regs[i].is32,ba[i]))
5143 assem_debug("branch: internal\n");
5144 else
5145 assem_debug("branch: external\n");
5146 if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5147 ds_assemble_entry(i);
5148 }
5149 else {
5150 add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5151 emit_jmp(0);
5152 }
5153}
5154
5155void rjump_assemble(int i,struct regstat *i_regs)
5156{
5157 signed char *i_regmap=i_regs->regmap;
5158 int temp;
5159 int rs,cc,adj;
5160 rs=get_reg(branch_regs[i].regmap,rs1[i]);
5161 assert(rs>=0);
5162 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5163 // Delay slot abuse, make a copy of the branch address register
5164 temp=get_reg(branch_regs[i].regmap,RTEMP);
5165 assert(temp>=0);
5166 assert(regs[i].regmap[temp]==RTEMP);
5167 emit_mov(rs,temp);
5168 rs=temp;
5169 }
5170 address_generation(i+1,i_regs,regs[i].regmap_entry);
5171 #ifdef REG_PREFETCH
5172 if(rt1[i]==31)
5173 {
5174 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5175 int return_address=start+i*4+8;
5176 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5177 }
5178 }
5179 #endif
5180 #ifdef USE_MINI_HT
5181 if(rs1[i]==31) {
5182 int rh=get_reg(regs[i].regmap,RHASH);
5183 if(rh>=0) do_preload_rhash(rh);
5184 }
5185 #endif
5186 ds_assemble(i+1,i_regs);
5187 uint64_t bc_unneeded=branch_regs[i].u;
5188 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5189 bc_unneeded|=1|(1LL<<rt1[i]);
5190 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5191 bc_unneeded&=~(1LL<<rs1[i]);
5192 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5193 bc_unneeded,bc_unneeded_upper);
5194 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5195 if(rt1[i]!=0) {
5196 int rt,return_address;
5197 assert(rt1[i+1]!=rt1[i]);
5198 assert(rt2[i+1]!=rt1[i]);
5199 rt=get_reg(branch_regs[i].regmap,rt1[i]);
5200 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5201 assert(rt>=0);
5202 return_address=start+i*4+8;
5203 #ifdef REG_PREFETCH
5204 if(temp>=0)
5205 {
5206 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5207 }
5208 #endif
5209 emit_movimm(return_address,rt); // PC into link register
5210 #ifdef IMM_PREFETCH
5211 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5212 #endif
5213 }
5214 cc=get_reg(branch_regs[i].regmap,CCREG);
5215 assert(cc==HOST_CCREG);
5216 #ifdef USE_MINI_HT
5217 int rh=get_reg(branch_regs[i].regmap,RHASH);
5218 int ht=get_reg(branch_regs[i].regmap,RHTBL);
5219 if(rs1[i]==31) {
5220 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5221 do_preload_rhtbl(ht);
5222 do_rhash(rs,rh);
5223 }
5224 #endif
5225 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5226 #ifdef DESTRUCTIVE_WRITEBACK
5227 if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5228 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5229 emit_loadreg(rs1[i],rs);
5230 }
5231 }
5232 #endif
5233 #ifdef REG_PREFETCH
5234 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5235 #endif
5236 #ifdef USE_MINI_HT
5237 if(rs1[i]==31) {
5238 do_miniht_load(ht,rh);
5239 }
5240 #endif
5241 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5242 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5243 //assert(adj==0);
5244 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5245 add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5246 emit_jns(0);
5247 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5248 #ifdef USE_MINI_HT
5249 if(rs1[i]==31) {
5250 do_miniht_jump(rs,rh,ht);
5251 }
5252 else
5253 #endif
5254 {
5255 //if(rs!=EAX) emit_mov(rs,EAX);
5256 //emit_jmp((int)jump_vaddr_eax);
5257 emit_jmp(jump_vaddr_reg[rs]);
5258 }
5259 /* Check hash table
5260 temp=!rs;
5261 emit_mov(rs,temp);
5262 emit_shrimm(rs,16,rs);
5263 emit_xor(temp,rs,rs);
5264 emit_movzwl_reg(rs,rs);
5265 emit_shlimm(rs,4,rs);
5266 emit_cmpmem_indexed((int)hash_table,rs,temp);
5267 emit_jne((int)out+14);
5268 emit_readword_indexed((int)hash_table+4,rs,rs);
5269 emit_jmpreg(rs);
5270 emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5271 emit_addimm_no_flags(8,rs);
5272 emit_jeq((int)out-17);
5273 // No hit on hash table, call compiler
5274 emit_pushreg(temp);
5275//DEBUG >
5276#ifdef DEBUG_CYCLE_COUNT
5277 emit_readword((int)&last_count,ECX);
5278 emit_add(HOST_CCREG,ECX,HOST_CCREG);
5279 emit_readword((int)&next_interupt,ECX);
5280 emit_writeword(HOST_CCREG,(int)&Count);
5281 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5282 emit_writeword(ECX,(int)&last_count);
5283#endif
5284//DEBUG <
5285 emit_storereg(CCREG,HOST_CCREG);
5286 emit_call((int)get_addr);
5287 emit_loadreg(CCREG,HOST_CCREG);
5288 emit_addimm(ESP,4,ESP);
5289 emit_jmpreg(EAX);*/
5290 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5291 if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5292 #endif
5293}
5294
5295void cjump_assemble(int i,struct regstat *i_regs)
5296{
5297 signed char *i_regmap=i_regs->regmap;
5298 int cc;
5299 int match;
5300 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5301 assem_debug("match=%d\n",match);
5302 int s1h,s1l,s2h,s2l;
5303 int prev_cop1_usable=cop1_usable;
5304 int unconditional=0,nop=0;
5305 int only32=0;
5306 int ooo=1;
5307 int invert=0;
5308 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5309 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5310 if(likely[i]) ooo=0;
5311 if(!match) invert=1;
5312 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5313 if(i>(ba[i]-start)>>2) invert=1;
5314 #endif
5315
5316 if(ooo)
5317 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
5318 (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1])))
5319 {
5320 // Write-after-read dependency prevents out of order execution
5321 // First test branch condition, then execute delay slot, then branch
5322 ooo=0;
5323 }
5324
5325 if(ooo) {
5326 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5327 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5328 s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5329 s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5330 }
5331 else {
5332 s1l=get_reg(i_regmap,rs1[i]);
5333 s1h=get_reg(i_regmap,rs1[i]|64);
5334 s2l=get_reg(i_regmap,rs2[i]);
5335 s2h=get_reg(i_regmap,rs2[i]|64);
5336 }
5337 if(rs1[i]==0&&rs2[i]==0)
5338 {
5339 if(opcode[i]&1) nop=1;
5340 else unconditional=1;
5341 //assert(opcode[i]!=5);
5342 //assert(opcode[i]!=7);
5343 //assert(opcode[i]!=0x15);
5344 //assert(opcode[i]!=0x17);
5345 }
5346 else if(rs1[i]==0)
5347 {
5348 s1l=s2l;s1h=s2h;
5349 s2l=s2h=-1;
5350 only32=(regs[i].was32>>rs2[i])&1;
5351 }
5352 else if(rs2[i]==0)
5353 {
5354 s2l=s2h=-1;
5355 only32=(regs[i].was32>>rs1[i])&1;
5356 }
5357 else {
5358 only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5359 }
5360
5361 if(ooo) {
5362 // Out of order execution (delay slot first)
5363 //printf("OOOE\n");
5364 address_generation(i+1,i_regs,regs[i].regmap_entry);
5365 ds_assemble(i+1,i_regs);
5366 int adj;
5367 uint64_t bc_unneeded=branch_regs[i].u;
5368 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5369 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5370 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5371 bc_unneeded|=1;
5372 bc_unneeded_upper|=1;
5373 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5374 bc_unneeded,bc_unneeded_upper);
5375 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5376 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5377 cc=get_reg(branch_regs[i].regmap,CCREG);
5378 assert(cc==HOST_CCREG);
5379 if(unconditional)
5380 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5381 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5382 //assem_debug("cycle count (adj)\n");
5383 if(unconditional) {
5384 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5385 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5386 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5387 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5388 if(internal)
5389 assem_debug("branch: internal\n");
5390 else
5391 assem_debug("branch: external\n");
5392 if(internal&&is_ds[(ba[i]-start)>>2]) {
5393 ds_assemble_entry(i);
5394 }
5395 else {
5396 add_to_linker((int)out,ba[i],internal);
5397 emit_jmp(0);
5398 }
5399 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5400 if(((u_int)out)&7) emit_addnop(0);
5401 #endif
5402 }
5403 }
5404 else if(nop) {
5405 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5406 int jaddr=(int)out;
5407 emit_jns(0);
5408 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5409 }
5410 else {
5411 int taken=0,nottaken=0,nottaken1=0;
5412 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5413 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5414 if(!only32)
5415 {
5416 assert(s1h>=0);
5417 if(opcode[i]==4) // BEQ
5418 {
5419 if(s2h>=0) emit_cmp(s1h,s2h);
5420 else emit_test(s1h,s1h);
5421 nottaken1=(int)out;
5422 emit_jne(1);
5423 }
5424 if(opcode[i]==5) // BNE
5425 {
5426 if(s2h>=0) emit_cmp(s1h,s2h);
5427 else emit_test(s1h,s1h);
5428 if(invert) taken=(int)out;
5429 else add_to_linker((int)out,ba[i],internal);
5430 emit_jne(0);
5431 }
5432 if(opcode[i]==6) // BLEZ
5433 {
5434 emit_test(s1h,s1h);
5435 if(invert) taken=(int)out;
5436 else add_to_linker((int)out,ba[i],internal);
5437 emit_js(0);
5438 nottaken1=(int)out;
5439 emit_jne(1);
5440 }
5441 if(opcode[i]==7) // BGTZ
5442 {
5443 emit_test(s1h,s1h);
5444 nottaken1=(int)out;
5445 emit_js(1);
5446 if(invert) taken=(int)out;
5447 else add_to_linker((int)out,ba[i],internal);
5448 emit_jne(0);
5449 }
5450 } // if(!only32)
5451
5452 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5453 assert(s1l>=0);
5454 if(opcode[i]==4) // BEQ
5455 {
5456 if(s2l>=0) emit_cmp(s1l,s2l);
5457 else emit_test(s1l,s1l);
5458 if(invert){
5459 nottaken=(int)out;
5460 emit_jne(1);
5461 }else{
5462 add_to_linker((int)out,ba[i],internal);
5463 emit_jeq(0);
5464 }
5465 }
5466 if(opcode[i]==5) // BNE
5467 {
5468 if(s2l>=0) emit_cmp(s1l,s2l);
5469 else emit_test(s1l,s1l);
5470 if(invert){
5471 nottaken=(int)out;
5472 emit_jeq(1);
5473 }else{
5474 add_to_linker((int)out,ba[i],internal);
5475 emit_jne(0);
5476 }
5477 }
5478 if(opcode[i]==6) // BLEZ
5479 {
5480 emit_cmpimm(s1l,1);
5481 if(invert){
5482 nottaken=(int)out;
5483 emit_jge(1);
5484 }else{
5485 add_to_linker((int)out,ba[i],internal);
5486 emit_jl(0);
5487 }
5488 }
5489 if(opcode[i]==7) // BGTZ
5490 {
5491 emit_cmpimm(s1l,1);
5492 if(invert){
5493 nottaken=(int)out;
5494 emit_jl(1);
5495 }else{
5496 add_to_linker((int)out,ba[i],internal);
5497 emit_jge(0);
5498 }
5499 }
5500 if(invert) {
5501 if(taken) set_jump_target(taken,(int)out);
5502 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5503 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5504 if(adj) {
5505 emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5506 add_to_linker((int)out,ba[i],internal);
5507 }else{
5508 emit_addnop(13);
5509 add_to_linker((int)out,ba[i],internal*2);
5510 }
5511 emit_jmp(0);
5512 }else
5513 #endif
5514 {
5515 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5516 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5517 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5518 if(internal)
5519 assem_debug("branch: internal\n");
5520 else
5521 assem_debug("branch: external\n");
5522 if(internal&&is_ds[(ba[i]-start)>>2]) {
5523 ds_assemble_entry(i);
5524 }
5525 else {
5526 add_to_linker((int)out,ba[i],internal);
5527 emit_jmp(0);
5528 }
5529 }
5530 set_jump_target(nottaken,(int)out);
5531 }
5532
5533 if(nottaken1) set_jump_target(nottaken1,(int)out);
5534 if(adj) {
5535 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5536 }
5537 } // (!unconditional)
5538 } // if(ooo)
5539 else
5540 {
5541 // In-order execution (branch first)
5542 //if(likely[i]) printf("IOL\n");
5543 //else
5544 //printf("IOE\n");
5545 int taken=0,nottaken=0,nottaken1=0;
5546 if(!unconditional&&!nop) {
5547 if(!only32)
5548 {
5549 assert(s1h>=0);
5550 if((opcode[i]&0x2f)==4) // BEQ
5551 {
5552 if(s2h>=0) emit_cmp(s1h,s2h);
5553 else emit_test(s1h,s1h);
5554 nottaken1=(int)out;
5555 emit_jne(2);
5556 }
5557 if((opcode[i]&0x2f)==5) // BNE
5558 {
5559 if(s2h>=0) emit_cmp(s1h,s2h);
5560 else emit_test(s1h,s1h);
5561 taken=(int)out;
5562 emit_jne(1);
5563 }
5564 if((opcode[i]&0x2f)==6) // BLEZ
5565 {
5566 emit_test(s1h,s1h);
5567 taken=(int)out;
5568 emit_js(1);
5569 nottaken1=(int)out;
5570 emit_jne(2);
5571 }
5572 if((opcode[i]&0x2f)==7) // BGTZ
5573 {
5574 emit_test(s1h,s1h);
5575 nottaken1=(int)out;
5576 emit_js(2);
5577 taken=(int)out;
5578 emit_jne(1);
5579 }
5580 } // if(!only32)
5581
5582 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5583 assert(s1l>=0);
5584 if((opcode[i]&0x2f)==4) // BEQ
5585 {
5586 if(s2l>=0) emit_cmp(s1l,s2l);
5587 else emit_test(s1l,s1l);
5588 nottaken=(int)out;
5589 emit_jne(2);
5590 }
5591 if((opcode[i]&0x2f)==5) // BNE
5592 {
5593 if(s2l>=0) emit_cmp(s1l,s2l);
5594 else emit_test(s1l,s1l);
5595 nottaken=(int)out;
5596 emit_jeq(2);
5597 }
5598 if((opcode[i]&0x2f)==6) // BLEZ
5599 {
5600 emit_cmpimm(s1l,1);
5601 nottaken=(int)out;
5602 emit_jge(2);
5603 }
5604 if((opcode[i]&0x2f)==7) // BGTZ
5605 {
5606 emit_cmpimm(s1l,1);
5607 nottaken=(int)out;
5608 emit_jl(2);
5609 }
5610 } // if(!unconditional)
5611 int adj;
5612 uint64_t ds_unneeded=branch_regs[i].u;
5613 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5614 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5615 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5616 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5617 ds_unneeded|=1;
5618 ds_unneeded_upper|=1;
5619 // branch taken
5620 if(!nop) {
5621 if(taken) set_jump_target(taken,(int)out);
5622 assem_debug("1:\n");
5623 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5624 ds_unneeded,ds_unneeded_upper);
5625 // load regs
5626 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5627 address_generation(i+1,&branch_regs[i],0);
5628 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5629 ds_assemble(i+1,&branch_regs[i]);
5630 cc=get_reg(branch_regs[i].regmap,CCREG);
5631 if(cc==-1) {
5632 emit_loadreg(CCREG,cc=HOST_CCREG);
5633 // CHECK: Is the following instruction (fall thru) allocated ok?
5634 }
5635 assert(cc==HOST_CCREG);
5636 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5637 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5638 assem_debug("cycle count (adj)\n");
5639 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5640 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5641 if(internal)
5642 assem_debug("branch: internal\n");
5643 else
5644 assem_debug("branch: external\n");
5645 if(internal&&is_ds[(ba[i]-start)>>2]) {
5646 ds_assemble_entry(i);
5647 }
5648 else {
5649 add_to_linker((int)out,ba[i],internal);
5650 emit_jmp(0);
5651 }
5652 }
5653 // branch not taken
5654 cop1_usable=prev_cop1_usable;
5655 if(!unconditional) {
5656 if(nottaken1) set_jump_target(nottaken1,(int)out);
5657 set_jump_target(nottaken,(int)out);
5658 assem_debug("2:\n");
5659 if(!likely[i]) {
5660 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5661 ds_unneeded,ds_unneeded_upper);
5662 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5663 address_generation(i+1,&branch_regs[i],0);
5664 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5665 ds_assemble(i+1,&branch_regs[i]);
5666 }
5667 cc=get_reg(branch_regs[i].regmap,CCREG);
5668 if(cc==-1&&!likely[i]) {
5669 // Cycle count isn't in a register, temporarily load it then write it out
5670 emit_loadreg(CCREG,HOST_CCREG);
5671 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5672 int jaddr=(int)out;
5673 emit_jns(0);
5674 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5675 emit_storereg(CCREG,HOST_CCREG);
5676 }
5677 else{
5678 cc=get_reg(i_regmap,CCREG);
5679 assert(cc==HOST_CCREG);
5680 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5681 int jaddr=(int)out;
5682 emit_jns(0);
5683 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5684 }
5685 }
5686 }
5687}
5688
5689void sjump_assemble(int i,struct regstat *i_regs)
5690{
5691 signed char *i_regmap=i_regs->regmap;
5692 int cc;
5693 int match;
5694 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5695 assem_debug("smatch=%d\n",match);
5696 int s1h,s1l;
5697 int prev_cop1_usable=cop1_usable;
5698 int unconditional=0,nevertaken=0;
5699 int only32=0;
5700 int ooo=1;
5701 int invert=0;
5702 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5703 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5704 if(likely[i]) ooo=0;
5705 if(!match) invert=1;
5706 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5707 if(i>(ba[i]-start)>>2) invert=1;
5708 #endif
5709
5710 //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
5711 //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
5712
5713 if(ooo) {
5714 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))
5715 {
5716 // Write-after-read dependency prevents out of order execution
5717 // First test branch condition, then execute delay slot, then branch
5718 ooo=0;
5719 }
5720 if(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))
5721 // BxxZAL $ra is available to delay insn, so do it in order
5722 ooo=0;
5723 }
5724
5725 if(ooo) {
5726 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5727 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5728 }
5729 else {
5730 s1l=get_reg(i_regmap,rs1[i]);
5731 s1h=get_reg(i_regmap,rs1[i]|64);
5732 }
5733 if(rs1[i]==0)
5734 {
5735 if(opcode2[i]&1) unconditional=1;
5736 else nevertaken=1;
5737 // These are never taken (r0 is never less than zero)
5738 //assert(opcode2[i]!=0);
5739 //assert(opcode2[i]!=2);
5740 //assert(opcode2[i]!=0x10);
5741 //assert(opcode2[i]!=0x12);
5742 }
5743 else {
5744 only32=(regs[i].was32>>rs1[i])&1;
5745 }
5746
5747 if(ooo) {
5748 // Out of order execution (delay slot first)
5749 //printf("OOOE\n");
5750 address_generation(i+1,i_regs,regs[i].regmap_entry);
5751 ds_assemble(i+1,i_regs);
5752 int adj;
5753 uint64_t bc_unneeded=branch_regs[i].u;
5754 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5755 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5756 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5757 bc_unneeded|=1;
5758 bc_unneeded_upper|=1;
5759 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5760 bc_unneeded,bc_unneeded_upper);
5761 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5762 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5763 if(rt1[i]==31) {
5764 int rt,return_address;
5765 rt=get_reg(branch_regs[i].regmap,31);
5766 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5767 if(rt>=0) {
5768 // Save the PC even if the branch is not taken
5769 return_address=start+i*4+8;
5770 emit_movimm(return_address,rt); // PC into link register
5771 #ifdef IMM_PREFETCH
5772 if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5773 #endif
5774 }
5775 }
5776 cc=get_reg(branch_regs[i].regmap,CCREG);
5777 assert(cc==HOST_CCREG);
5778 if(unconditional)
5779 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5780 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5781 assem_debug("cycle count (adj)\n");
5782 if(unconditional) {
5783 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5784 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5785 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5786 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5787 if(internal)
5788 assem_debug("branch: internal\n");
5789 else
5790 assem_debug("branch: external\n");
5791 if(internal&&is_ds[(ba[i]-start)>>2]) {
5792 ds_assemble_entry(i);
5793 }
5794 else {
5795 add_to_linker((int)out,ba[i],internal);
5796 emit_jmp(0);
5797 }
5798 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5799 if(((u_int)out)&7) emit_addnop(0);
5800 #endif
5801 }
5802 }
5803 else if(nevertaken) {
5804 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5805 int jaddr=(int)out;
5806 emit_jns(0);
5807 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5808 }
5809 else {
5810 int nottaken=0;
5811 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5812 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5813 if(!only32)
5814 {
5815 assert(s1h>=0);
5816 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5817 {
5818 emit_test(s1h,s1h);
5819 if(invert){
5820 nottaken=(int)out;
5821 emit_jns(1);
5822 }else{
5823 add_to_linker((int)out,ba[i],internal);
5824 emit_js(0);
5825 }
5826 }
5827 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5828 {
5829 emit_test(s1h,s1h);
5830 if(invert){
5831 nottaken=(int)out;
5832 emit_js(1);
5833 }else{
5834 add_to_linker((int)out,ba[i],internal);
5835 emit_jns(0);
5836 }
5837 }
5838 } // if(!only32)
5839 else
5840 {
5841 assert(s1l>=0);
5842 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5843 {
5844 emit_test(s1l,s1l);
5845 if(invert){
5846 nottaken=(int)out;
5847 emit_jns(1);
5848 }else{
5849 add_to_linker((int)out,ba[i],internal);
5850 emit_js(0);
5851 }
5852 }
5853 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5854 {
5855 emit_test(s1l,s1l);
5856 if(invert){
5857 nottaken=(int)out;
5858 emit_js(1);
5859 }else{
5860 add_to_linker((int)out,ba[i],internal);
5861 emit_jns(0);
5862 }
5863 }
5864 } // if(!only32)
5865
5866 if(invert) {
5867 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5868 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5869 if(adj) {
5870 emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5871 add_to_linker((int)out,ba[i],internal);
5872 }else{
5873 emit_addnop(13);
5874 add_to_linker((int)out,ba[i],internal*2);
5875 }
5876 emit_jmp(0);
5877 }else
5878 #endif
5879 {
5880 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5881 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5882 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5883 if(internal)
5884 assem_debug("branch: internal\n");
5885 else
5886 assem_debug("branch: external\n");
5887 if(internal&&is_ds[(ba[i]-start)>>2]) {
5888 ds_assemble_entry(i);
5889 }
5890 else {
5891 add_to_linker((int)out,ba[i],internal);
5892 emit_jmp(0);
5893 }
5894 }
5895 set_jump_target(nottaken,(int)out);
5896 }
5897
5898 if(adj) {
5899 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5900 }
5901 } // (!unconditional)
5902 } // if(ooo)
5903 else
5904 {
5905 // In-order execution (branch first)
5906 //printf("IOE\n");
5907 int nottaken=0;
5908 if(rt1[i]==31) {
5909 int rt,return_address;
5910 rt=get_reg(branch_regs[i].regmap,31);
5911 if(rt>=0) {
5912 // Save the PC even if the branch is not taken
5913 return_address=start+i*4+8;
5914 emit_movimm(return_address,rt); // PC into link register
5915 #ifdef IMM_PREFETCH
5916 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5917 #endif
5918 }
5919 }
5920 if(!unconditional) {
5921 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5922 if(!only32)
5923 {
5924 assert(s1h>=0);
5925 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
5926 {
5927 emit_test(s1h,s1h);
5928 nottaken=(int)out;
5929 emit_jns(1);
5930 }
5931 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
5932 {
5933 emit_test(s1h,s1h);
5934 nottaken=(int)out;
5935 emit_js(1);
5936 }
5937 } // if(!only32)
5938 else
5939 {
5940 assert(s1l>=0);
5941 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
5942 {
5943 emit_test(s1l,s1l);
5944 nottaken=(int)out;
5945 emit_jns(1);
5946 }
5947 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
5948 {
5949 emit_test(s1l,s1l);
5950 nottaken=(int)out;
5951 emit_js(1);
5952 }
5953 }
5954 } // if(!unconditional)
5955 int adj;
5956 uint64_t ds_unneeded=branch_regs[i].u;
5957 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5958 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5959 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5960 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5961 ds_unneeded|=1;
5962 ds_unneeded_upper|=1;
5963 // branch taken
5964 if(!nevertaken) {
5965 //assem_debug("1:\n");
5966 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5967 ds_unneeded,ds_unneeded_upper);
5968 // load regs
5969 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5970 address_generation(i+1,&branch_regs[i],0);
5971 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5972 ds_assemble(i+1,&branch_regs[i]);
5973 cc=get_reg(branch_regs[i].regmap,CCREG);
5974 if(cc==-1) {
5975 emit_loadreg(CCREG,cc=HOST_CCREG);
5976 // CHECK: Is the following instruction (fall thru) allocated ok?
5977 }
5978 assert(cc==HOST_CCREG);
5979 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5980 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5981 assem_debug("cycle count (adj)\n");
5982 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5983 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5984 if(internal)
5985 assem_debug("branch: internal\n");
5986 else
5987 assem_debug("branch: external\n");
5988 if(internal&&is_ds[(ba[i]-start)>>2]) {
5989 ds_assemble_entry(i);
5990 }
5991 else {
5992 add_to_linker((int)out,ba[i],internal);
5993 emit_jmp(0);
5994 }
5995 }
5996 // branch not taken
5997 cop1_usable=prev_cop1_usable;
5998 if(!unconditional) {
5999 set_jump_target(nottaken,(int)out);
6000 assem_debug("1:\n");
6001 if(!likely[i]) {
6002 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6003 ds_unneeded,ds_unneeded_upper);
6004 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6005 address_generation(i+1,&branch_regs[i],0);
6006 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6007 ds_assemble(i+1,&branch_regs[i]);
6008 }
6009 cc=get_reg(branch_regs[i].regmap,CCREG);
6010 if(cc==-1&&!likely[i]) {
6011 // Cycle count isn't in a register, temporarily load it then write it out
6012 emit_loadreg(CCREG,HOST_CCREG);
6013 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6014 int jaddr=(int)out;
6015 emit_jns(0);
6016 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6017 emit_storereg(CCREG,HOST_CCREG);
6018 }
6019 else{
6020 cc=get_reg(i_regmap,CCREG);
6021 assert(cc==HOST_CCREG);
6022 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6023 int jaddr=(int)out;
6024 emit_jns(0);
6025 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6026 }
6027 }
6028 }
6029}
6030
6031void fjump_assemble(int i,struct regstat *i_regs)
6032{
6033 signed char *i_regmap=i_regs->regmap;
6034 int cc;
6035 int match;
6036 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6037 assem_debug("fmatch=%d\n",match);
6038 int fs,cs;
6039 int eaddr;
6040 int ooo=1;
6041 int invert=0;
6042 int internal=internal_branch(branch_regs[i].is32,ba[i]);
6043 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
6044 if(likely[i]) ooo=0;
6045 if(!match) invert=1;
6046 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6047 if(i>(ba[i]-start)>>2) invert=1;
6048 #endif
6049
6050 if(ooo)
6051 if(itype[i+1]==FCOMP)
6052 {
6053 // Write-after-read dependency prevents out of order execution
6054 // First test branch condition, then execute delay slot, then branch
6055 ooo=0;
6056 }
6057
6058 if(ooo) {
6059 fs=get_reg(branch_regs[i].regmap,FSREG);
6060 address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
6061 }
6062 else {
6063 fs=get_reg(i_regmap,FSREG);
6064 }
6065
6066 // Check cop1 unusable
6067 if(!cop1_usable) {
6068 cs=get_reg(i_regmap,CSREG);
6069 assert(cs>=0);
6070 emit_testimm(cs,0x20000000);
6071 eaddr=(int)out;
6072 emit_jeq(0);
6073 add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
6074 cop1_usable=1;
6075 }
6076
6077 if(ooo) {
6078 // Out of order execution (delay slot first)
6079 //printf("OOOE\n");
6080 ds_assemble(i+1,i_regs);
6081 int adj;
6082 uint64_t bc_unneeded=branch_regs[i].u;
6083 uint64_t bc_unneeded_upper=branch_regs[i].uu;
6084 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6085 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
6086 bc_unneeded|=1;
6087 bc_unneeded_upper|=1;
6088 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6089 bc_unneeded,bc_unneeded_upper);
6090 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
6091 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6092 cc=get_reg(branch_regs[i].regmap,CCREG);
6093 assert(cc==HOST_CCREG);
6094 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6095 assem_debug("cycle count (adj)\n");
6096 if(1) {
6097 int nottaken=0;
6098 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6099 if(1) {
6100 assert(fs>=0);
6101 emit_testimm(fs,0x800000);
6102 if(source[i]&0x10000) // BC1T
6103 {
6104 if(invert){
6105 nottaken=(int)out;
6106 emit_jeq(1);
6107 }else{
6108 add_to_linker((int)out,ba[i],internal);
6109 emit_jne(0);
6110 }
6111 }
6112 else // BC1F
6113 if(invert){
6114 nottaken=(int)out;
6115 emit_jne(1);
6116 }else{
6117 add_to_linker((int)out,ba[i],internal);
6118 emit_jeq(0);
6119 }
6120 {
6121 }
6122 } // if(!only32)
6123
6124 if(invert) {
6125 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
6126 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6127 else if(match) emit_addnop(13);
6128 #endif
6129 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6130 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6131 if(internal)
6132 assem_debug("branch: internal\n");
6133 else
6134 assem_debug("branch: external\n");
6135 if(internal&&is_ds[(ba[i]-start)>>2]) {
6136 ds_assemble_entry(i);
6137 }
6138 else {
6139 add_to_linker((int)out,ba[i],internal);
6140 emit_jmp(0);
6141 }
6142 set_jump_target(nottaken,(int)out);
6143 }
6144
6145 if(adj) {
6146 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
6147 }
6148 } // (!unconditional)
6149 } // if(ooo)
6150 else
6151 {
6152 // In-order execution (branch first)
6153 //printf("IOE\n");
6154 int nottaken=0;
6155 if(1) {
6156 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6157 if(1) {
6158 assert(fs>=0);
6159 emit_testimm(fs,0x800000);
6160 if(source[i]&0x10000) // BC1T
6161 {
6162 nottaken=(int)out;
6163 emit_jeq(1);
6164 }
6165 else // BC1F
6166 {
6167 nottaken=(int)out;
6168 emit_jne(1);
6169 }
6170 }
6171 } // if(!unconditional)
6172 int adj;
6173 uint64_t ds_unneeded=branch_regs[i].u;
6174 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6175 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6176 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6177 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6178 ds_unneeded|=1;
6179 ds_unneeded_upper|=1;
6180 // branch taken
6181 //assem_debug("1:\n");
6182 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6183 ds_unneeded,ds_unneeded_upper);
6184 // load regs
6185 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6186 address_generation(i+1,&branch_regs[i],0);
6187 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6188 ds_assemble(i+1,&branch_regs[i]);
6189 cc=get_reg(branch_regs[i].regmap,CCREG);
6190 if(cc==-1) {
6191 emit_loadreg(CCREG,cc=HOST_CCREG);
6192 // CHECK: Is the following instruction (fall thru) allocated ok?
6193 }
6194 assert(cc==HOST_CCREG);
6195 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6196 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6197 assem_debug("cycle count (adj)\n");
6198 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6199 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6200 if(internal)
6201 assem_debug("branch: internal\n");
6202 else
6203 assem_debug("branch: external\n");
6204 if(internal&&is_ds[(ba[i]-start)>>2]) {
6205 ds_assemble_entry(i);
6206 }
6207 else {
6208 add_to_linker((int)out,ba[i],internal);
6209 emit_jmp(0);
6210 }
6211
6212 // branch not taken
6213 if(1) { // <- FIXME (don't need this)
6214 set_jump_target(nottaken,(int)out);
6215 assem_debug("1:\n");
6216 if(!likely[i]) {
6217 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6218 ds_unneeded,ds_unneeded_upper);
6219 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6220 address_generation(i+1,&branch_regs[i],0);
6221 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6222 ds_assemble(i+1,&branch_regs[i]);
6223 }
6224 cc=get_reg(branch_regs[i].regmap,CCREG);
6225 if(cc==-1&&!likely[i]) {
6226 // Cycle count isn't in a register, temporarily load it then write it out
6227 emit_loadreg(CCREG,HOST_CCREG);
6228 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6229 int jaddr=(int)out;
6230 emit_jns(0);
6231 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6232 emit_storereg(CCREG,HOST_CCREG);
6233 }
6234 else{
6235 cc=get_reg(i_regmap,CCREG);
6236 assert(cc==HOST_CCREG);
6237 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6238 int jaddr=(int)out;
6239 emit_jns(0);
6240 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6241 }
6242 }
6243 }
6244}
6245
6246static void pagespan_assemble(int i,struct regstat *i_regs)
6247{
6248 int s1l=get_reg(i_regs->regmap,rs1[i]);
6249 int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6250 int s2l=get_reg(i_regs->regmap,rs2[i]);
6251 int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6252 void *nt_branch=NULL;
6253 int taken=0;
6254 int nottaken=0;
6255 int unconditional=0;
6256 if(rs1[i]==0)
6257 {
6258 s1l=s2l;s1h=s2h;
6259 s2l=s2h=-1;
6260 }
6261 else if(rs2[i]==0)
6262 {
6263 s2l=s2h=-1;
6264 }
6265 if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6266 s1h=s2h=-1;
6267 }
6268 int hr=0;
6269 int addr,alt,ntaddr;
6270 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6271 else {
6272 while(hr<HOST_REGS)
6273 {
6274 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6275 (i_regs->regmap[hr]&63)!=rs1[i] &&
6276 (i_regs->regmap[hr]&63)!=rs2[i] )
6277 {
6278 addr=hr++;break;
6279 }
6280 hr++;
6281 }
6282 }
6283 while(hr<HOST_REGS)
6284 {
6285 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6286 (i_regs->regmap[hr]&63)!=rs1[i] &&
6287 (i_regs->regmap[hr]&63)!=rs2[i] )
6288 {
6289 alt=hr++;break;
6290 }
6291 hr++;
6292 }
6293 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6294 {
6295 while(hr<HOST_REGS)
6296 {
6297 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6298 (i_regs->regmap[hr]&63)!=rs1[i] &&
6299 (i_regs->regmap[hr]&63)!=rs2[i] )
6300 {
6301 ntaddr=hr;break;
6302 }
6303 hr++;
6304 }
6305 }
6306 assert(hr<HOST_REGS);
6307 if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6308 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6309 }
6310 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6311 if(opcode[i]==2) // J
6312 {
6313 unconditional=1;
6314 }
6315 if(opcode[i]==3) // JAL
6316 {
6317 // TODO: mini_ht
6318 int rt=get_reg(i_regs->regmap,31);
6319 emit_movimm(start+i*4+8,rt);
6320 unconditional=1;
6321 }
6322 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6323 {
6324 emit_mov(s1l,addr);
6325 if(opcode2[i]==9) // JALR
6326 {
6327 int rt=get_reg(i_regs->regmap,rt1[i]);
6328 emit_movimm(start+i*4+8,rt);
6329 }
6330 }
6331 if((opcode[i]&0x3f)==4) // BEQ
6332 {
6333 if(rs1[i]==rs2[i])
6334 {
6335 unconditional=1;
6336 }
6337 else
6338 #ifdef HAVE_CMOV_IMM
6339 if(s1h<0) {
6340 if(s2l>=0) emit_cmp(s1l,s2l);
6341 else emit_test(s1l,s1l);
6342 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6343 }
6344 else
6345 #endif
6346 {
6347 assert(s1l>=0);
6348 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6349 if(s1h>=0) {
6350 if(s2h>=0) emit_cmp(s1h,s2h);
6351 else emit_test(s1h,s1h);
6352 emit_cmovne_reg(alt,addr);
6353 }
6354 if(s2l>=0) emit_cmp(s1l,s2l);
6355 else emit_test(s1l,s1l);
6356 emit_cmovne_reg(alt,addr);
6357 }
6358 }
6359 if((opcode[i]&0x3f)==5) // BNE
6360 {
6361 #ifdef HAVE_CMOV_IMM
6362 if(s1h<0) {
6363 if(s2l>=0) emit_cmp(s1l,s2l);
6364 else emit_test(s1l,s1l);
6365 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6366 }
6367 else
6368 #endif
6369 {
6370 assert(s1l>=0);
6371 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6372 if(s1h>=0) {
6373 if(s2h>=0) emit_cmp(s1h,s2h);
6374 else emit_test(s1h,s1h);
6375 emit_cmovne_reg(alt,addr);
6376 }
6377 if(s2l>=0) emit_cmp(s1l,s2l);
6378 else emit_test(s1l,s1l);
6379 emit_cmovne_reg(alt,addr);
6380 }
6381 }
6382 if((opcode[i]&0x3f)==0x14) // BEQL
6383 {
6384 if(s1h>=0) {
6385 if(s2h>=0) emit_cmp(s1h,s2h);
6386 else emit_test(s1h,s1h);
6387 nottaken=(int)out;
6388 emit_jne(0);
6389 }
6390 if(s2l>=0) emit_cmp(s1l,s2l);
6391 else emit_test(s1l,s1l);
6392 if(nottaken) set_jump_target(nottaken,(int)out);
6393 nottaken=(int)out;
6394 emit_jne(0);
6395 }
6396 if((opcode[i]&0x3f)==0x15) // BNEL
6397 {
6398 if(s1h>=0) {
6399 if(s2h>=0) emit_cmp(s1h,s2h);
6400 else emit_test(s1h,s1h);
6401 taken=(int)out;
6402 emit_jne(0);
6403 }
6404 if(s2l>=0) emit_cmp(s1l,s2l);
6405 else emit_test(s1l,s1l);
6406 nottaken=(int)out;
6407 emit_jeq(0);
6408 if(taken) set_jump_target(taken,(int)out);
6409 }
6410 if((opcode[i]&0x3f)==6) // BLEZ
6411 {
6412 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6413 emit_cmpimm(s1l,1);
6414 if(s1h>=0) emit_mov(addr,ntaddr);
6415 emit_cmovl_reg(alt,addr);
6416 if(s1h>=0) {
6417 emit_test(s1h,s1h);
6418 emit_cmovne_reg(ntaddr,addr);
6419 emit_cmovs_reg(alt,addr);
6420 }
6421 }
6422 if((opcode[i]&0x3f)==7) // BGTZ
6423 {
6424 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6425 emit_cmpimm(s1l,1);
6426 if(s1h>=0) emit_mov(addr,alt);
6427 emit_cmovl_reg(ntaddr,addr);
6428 if(s1h>=0) {
6429 emit_test(s1h,s1h);
6430 emit_cmovne_reg(alt,addr);
6431 emit_cmovs_reg(ntaddr,addr);
6432 }
6433 }
6434 if((opcode[i]&0x3f)==0x16) // BLEZL
6435 {
6436 assert((opcode[i]&0x3f)!=0x16);
6437 }
6438 if((opcode[i]&0x3f)==0x17) // BGTZL
6439 {
6440 assert((opcode[i]&0x3f)!=0x17);
6441 }
6442 assert(opcode[i]!=1); // BLTZ/BGEZ
6443
6444 //FIXME: Check CSREG
6445 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6446 if((source[i]&0x30000)==0) // BC1F
6447 {
6448 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6449 emit_testimm(s1l,0x800000);
6450 emit_cmovne_reg(alt,addr);
6451 }
6452 if((source[i]&0x30000)==0x10000) // BC1T
6453 {
6454 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6455 emit_testimm(s1l,0x800000);
6456 emit_cmovne_reg(alt,addr);
6457 }
6458 if((source[i]&0x30000)==0x20000) // BC1FL
6459 {
6460 emit_testimm(s1l,0x800000);
6461 nottaken=(int)out;
6462 emit_jne(0);
6463 }
6464 if((source[i]&0x30000)==0x30000) // BC1TL
6465 {
6466 emit_testimm(s1l,0x800000);
6467 nottaken=(int)out;
6468 emit_jeq(0);
6469 }
6470 }
6471
6472 assert(i_regs->regmap[HOST_CCREG]==CCREG);
6473 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6474 if(likely[i]||unconditional)
6475 {
6476 emit_movimm(ba[i],HOST_BTREG);
6477 }
6478 else if(addr!=HOST_BTREG)
6479 {
6480 emit_mov(addr,HOST_BTREG);
6481 }
6482 void *branch_addr=out;
6483 emit_jmp(0);
6484 int target_addr=start+i*4+5;
6485 void *stub=out;
6486 void *compiled_target_addr=check_addr(target_addr);
6487 emit_extjump_ds((int)branch_addr,target_addr);
6488 if(compiled_target_addr) {
6489 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6490 add_link(target_addr,stub);
6491 }
6492 else set_jump_target((int)branch_addr,(int)stub);
6493 if(likely[i]) {
6494 // Not-taken path
6495 set_jump_target((int)nottaken,(int)out);
6496 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6497 void *branch_addr=out;
6498 emit_jmp(0);
6499 int target_addr=start+i*4+8;
6500 void *stub=out;
6501 void *compiled_target_addr=check_addr(target_addr);
6502 emit_extjump_ds((int)branch_addr,target_addr);
6503 if(compiled_target_addr) {
6504 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6505 add_link(target_addr,stub);
6506 }
6507 else set_jump_target((int)branch_addr,(int)stub);
6508 }
6509}
6510
6511// Assemble the delay slot for the above
6512static void pagespan_ds()
6513{
6514 assem_debug("initial delay slot:\n");
6515 u_int vaddr=start+1;
6516 u_int page=get_page(vaddr);
6517 u_int vpage=get_vpage(vaddr);
6518 ll_add(jump_dirty+vpage,vaddr,(void *)out);
6519 do_dirty_stub_ds();
6520 ll_add(jump_in+page,vaddr,(void *)out);
6521 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6522 if(regs[0].regmap[HOST_CCREG]!=CCREG)
6523 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6524 if(regs[0].regmap[HOST_BTREG]!=BTREG)
6525 emit_writeword(HOST_BTREG,(int)&branch_target);
6526 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6527 address_generation(0,&regs[0],regs[0].regmap_entry);
6528 if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
6529 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6530 cop1_usable=0;
6531 is_delayslot=0;
6532 switch(itype[0]) {
6533 case ALU:
6534 alu_assemble(0,&regs[0]);break;
6535 case IMM16:
6536 imm16_assemble(0,&regs[0]);break;
6537 case SHIFT:
6538 shift_assemble(0,&regs[0]);break;
6539 case SHIFTIMM:
6540 shiftimm_assemble(0,&regs[0]);break;
6541 case LOAD:
6542 load_assemble(0,&regs[0]);break;
6543 case LOADLR:
6544 loadlr_assemble(0,&regs[0]);break;
6545 case STORE:
6546 store_assemble(0,&regs[0]);break;
6547 case STORELR:
6548 storelr_assemble(0,&regs[0]);break;
6549 case COP0:
6550 cop0_assemble(0,&regs[0]);break;
6551 case COP1:
6552 cop1_assemble(0,&regs[0]);break;
6553 case C1LS:
6554 c1ls_assemble(0,&regs[0]);break;
6555 case COP2:
6556 cop2_assemble(0,&regs[0]);break;
6557 case C2LS:
6558 c2ls_assemble(0,&regs[0]);break;
6559 case C2OP:
6560 c2op_assemble(0,&regs[0]);break;
6561 case FCONV:
6562 fconv_assemble(0,&regs[0]);break;
6563 case FLOAT:
6564 float_assemble(0,&regs[0]);break;
6565 case FCOMP:
6566 fcomp_assemble(0,&regs[0]);break;
6567 case MULTDIV:
6568 multdiv_assemble(0,&regs[0]);break;
6569 case MOV:
6570 mov_assemble(0,&regs[0]);break;
6571 case SYSCALL:
6572 case HLECALL:
6573 case INTCALL:
6574 case SPAN:
6575 case UJUMP:
6576 case RJUMP:
6577 case CJUMP:
6578 case SJUMP:
6579 case FJUMP:
6580 printf("Jump in the delay slot. This is probably a bug.\n");
6581 }
6582 int btaddr=get_reg(regs[0].regmap,BTREG);
6583 if(btaddr<0) {
6584 btaddr=get_reg(regs[0].regmap,-1);
6585 emit_readword((int)&branch_target,btaddr);
6586 }
6587 assert(btaddr!=HOST_CCREG);
6588 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6589#ifdef HOST_IMM8
6590 emit_movimm(start+4,HOST_TEMPREG);
6591 emit_cmp(btaddr,HOST_TEMPREG);
6592#else
6593 emit_cmpimm(btaddr,start+4);
6594#endif
6595 int branch=(int)out;
6596 emit_jeq(0);
6597 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6598 emit_jmp(jump_vaddr_reg[btaddr]);
6599 set_jump_target(branch,(int)out);
6600 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6601 load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6602}
6603
6604// Basic liveness analysis for MIPS registers
6605void unneeded_registers(int istart,int iend,int r)
6606{
6607 int i;
6608 uint64_t u,uu,b,bu;
6609 uint64_t temp_u,temp_uu;
6610 uint64_t tdep;
6611 if(iend==slen-1) {
6612 u=1;uu=1;
6613 }else{
6614 u=unneeded_reg[iend+1];
6615 uu=unneeded_reg_upper[iend+1];
6616 u=1;uu=1;
6617 }
6618 for (i=iend;i>=istart;i--)
6619 {
6620 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6621 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6622 {
6623 // If subroutine call, flag return address as a possible branch target
6624 if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6625
6626 if(ba[i]<start || ba[i]>=(start+slen*4))
6627 {
6628 // Branch out of this block, flush all regs
6629 u=1;
6630 uu=1;
6631 /* Hexagon hack
6632 if(itype[i]==UJUMP&&rt1[i]==31)
6633 {
6634 uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6635 }
6636 if(itype[i]==RJUMP&&rs1[i]==31)
6637 {
6638 uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6639 }
6640 if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
6641 if(itype[i]==UJUMP&&rt1[i]==31)
6642 {
6643 //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6644 uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6645 }
6646 if(itype[i]==RJUMP&&rs1[i]==31)
6647 {
6648 //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6649 uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6650 }
6651 }*/
6652 branch_unneeded_reg[i]=u;
6653 branch_unneeded_reg_upper[i]=uu;
6654 // Merge in delay slot
6655 tdep=(~uu>>rt1[i+1])&1;
6656 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6657 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6658 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6659 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6660 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6661 u|=1;uu|=1;
6662 // If branch is "likely" (and conditional)
6663 // then we skip the delay slot on the fall-thru path
6664 if(likely[i]) {
6665 if(i<slen-1) {
6666 u&=unneeded_reg[i+2];
6667 uu&=unneeded_reg_upper[i+2];
6668 }
6669 else
6670 {
6671 u=1;
6672 uu=1;
6673 }
6674 }
6675 }
6676 else
6677 {
6678 // Internal branch, flag target
6679 bt[(ba[i]-start)>>2]=1;
6680 if(ba[i]<=start+i*4) {
6681 // Backward branch
6682 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6683 {
6684 // Unconditional branch
6685 temp_u=1;temp_uu=1;
6686 } else {
6687 // Conditional branch (not taken case)
6688 temp_u=unneeded_reg[i+2];
6689 temp_uu=unneeded_reg_upper[i+2];
6690 }
6691 // Merge in delay slot
6692 tdep=(~temp_uu>>rt1[i+1])&1;
6693 temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6694 temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6695 temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6696 temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6697 temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6698 temp_u|=1;temp_uu|=1;
6699 // If branch is "likely" (and conditional)
6700 // then we skip the delay slot on the fall-thru path
6701 if(likely[i]) {
6702 if(i<slen-1) {
6703 temp_u&=unneeded_reg[i+2];
6704 temp_uu&=unneeded_reg_upper[i+2];
6705 }
6706 else
6707 {
6708 temp_u=1;
6709 temp_uu=1;
6710 }
6711 }
6712 tdep=(~temp_uu>>rt1[i])&1;
6713 temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6714 temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6715 temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6716 temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6717 temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6718 temp_u|=1;temp_uu|=1;
6719 unneeded_reg[i]=temp_u;
6720 unneeded_reg_upper[i]=temp_uu;
6721 // Only go three levels deep. This recursion can take an
6722 // excessive amount of time if there are a lot of nested loops.
6723 if(r<2) {
6724 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6725 }else{
6726 unneeded_reg[(ba[i]-start)>>2]=1;
6727 unneeded_reg_upper[(ba[i]-start)>>2]=1;
6728 }
6729 } /*else*/ if(1) {
6730 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6731 {
6732 // Unconditional branch
6733 u=unneeded_reg[(ba[i]-start)>>2];
6734 uu=unneeded_reg_upper[(ba[i]-start)>>2];
6735 branch_unneeded_reg[i]=u;
6736 branch_unneeded_reg_upper[i]=uu;
6737 //u=1;
6738 //uu=1;
6739 //branch_unneeded_reg[i]=u;
6740 //branch_unneeded_reg_upper[i]=uu;
6741 // Merge in delay slot
6742 tdep=(~uu>>rt1[i+1])&1;
6743 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6744 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6745 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6746 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6747 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6748 u|=1;uu|=1;
6749 } else {
6750 // Conditional branch
6751 b=unneeded_reg[(ba[i]-start)>>2];
6752 bu=unneeded_reg_upper[(ba[i]-start)>>2];
6753 branch_unneeded_reg[i]=b;
6754 branch_unneeded_reg_upper[i]=bu;
6755 //b=1;
6756 //bu=1;
6757 //branch_unneeded_reg[i]=b;
6758 //branch_unneeded_reg_upper[i]=bu;
6759 // Branch delay slot
6760 tdep=(~uu>>rt1[i+1])&1;
6761 b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6762 bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6763 b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6764 bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6765 bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6766 b|=1;bu|=1;
6767 // If branch is "likely" then we skip the
6768 // delay slot on the fall-thru path
6769 if(likely[i]) {
6770 u=b;
6771 uu=bu;
6772 if(i<slen-1) {
6773 u&=unneeded_reg[i+2];
6774 uu&=unneeded_reg_upper[i+2];
6775 //u=1;
6776 //uu=1;
6777 }
6778 } else {
6779 u&=b;
6780 uu&=bu;
6781 //u=1;
6782 //uu=1;
6783 }
6784 if(i<slen-1) {
6785 branch_unneeded_reg[i]&=unneeded_reg[i+2];
6786 branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6787 //branch_unneeded_reg[i]=1;
6788 //branch_unneeded_reg_upper[i]=1;
6789 } else {
6790 branch_unneeded_reg[i]=1;
6791 branch_unneeded_reg_upper[i]=1;
6792 }
6793 }
6794 }
6795 }
6796 }
6797 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
6798 {
6799 // SYSCALL instruction (software interrupt)
6800 u=1;
6801 uu=1;
6802 }
6803 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6804 {
6805 // ERET instruction (return from interrupt)
6806 u=1;
6807 uu=1;
6808 }
6809 //u=uu=1; // DEBUG
6810 tdep=(~uu>>rt1[i])&1;
6811 // Written registers are unneeded
6812 u|=1LL<<rt1[i];
6813 u|=1LL<<rt2[i];
6814 uu|=1LL<<rt1[i];
6815 uu|=1LL<<rt2[i];
6816 // Accessed registers are needed
6817 u&=~(1LL<<rs1[i]);
6818 u&=~(1LL<<rs2[i]);
6819 uu&=~(1LL<<us1[i]);
6820 uu&=~(1LL<<us2[i]);
6821 // Source-target dependencies
6822 uu&=~(tdep<<dep1[i]);
6823 uu&=~(tdep<<dep2[i]);
6824 // R0 is always unneeded
6825 u|=1;uu|=1;
6826 // Save it
6827 unneeded_reg[i]=u;
6828 unneeded_reg_upper[i]=uu;
6829 /*
6830 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6831 printf("U:");
6832 int r;
6833 for(r=1;r<=CCREG;r++) {
6834 if((unneeded_reg[i]>>r)&1) {
6835 if(r==HIREG) printf(" HI");
6836 else if(r==LOREG) printf(" LO");
6837 else printf(" r%d",r);
6838 }
6839 }
6840 printf(" UU:");
6841 for(r=1;r<=CCREG;r++) {
6842 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
6843 if(r==HIREG) printf(" HI");
6844 else if(r==LOREG) printf(" LO");
6845 else printf(" r%d",r);
6846 }
6847 }
6848 printf("\n");*/
6849 }
6850#ifdef FORCE32
6851 for (i=iend;i>=istart;i--)
6852 {
6853 unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
6854 }
6855#endif
6856}
6857
6858// Identify registers which are likely to contain 32-bit values
6859// This is used to predict whether any branches will jump to a
6860// location with 64-bit values in registers.
6861static void provisional_32bit()
6862{
6863 int i,j;
6864 uint64_t is32=1;
6865 uint64_t lastbranch=1;
6866
6867 for(i=0;i<slen;i++)
6868 {
6869 if(i>0) {
6870 if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
6871 if(i>1) is32=lastbranch;
6872 else is32=1;
6873 }
6874 }
6875 if(i>1)
6876 {
6877 if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
6878 if(likely[i-2]) {
6879 if(i>2) is32=lastbranch;
6880 else is32=1;
6881 }
6882 }
6883 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
6884 {
6885 if(rs1[i-2]==0||rs2[i-2]==0)
6886 {
6887 if(rs1[i-2]) {
6888 is32|=1LL<<rs1[i-2];
6889 }
6890 if(rs2[i-2]) {
6891 is32|=1LL<<rs2[i-2];
6892 }
6893 }
6894 }
6895 }
6896 // If something jumps here with 64-bit values
6897 // then promote those registers to 64 bits
6898 if(bt[i])
6899 {
6900 uint64_t temp_is32=is32;
6901 for(j=i-1;j>=0;j--)
6902 {
6903 if(ba[j]==start+i*4)
6904 //temp_is32&=branch_regs[j].is32;
6905 temp_is32&=p32[j];
6906 }
6907 for(j=i;j<slen;j++)
6908 {
6909 if(ba[j]==start+i*4)
6910 temp_is32=1;
6911 }
6912 is32=temp_is32;
6913 }
6914 int type=itype[i];
6915 int op=opcode[i];
6916 int op2=opcode2[i];
6917 int rt=rt1[i];
6918 int s1=rs1[i];
6919 int s2=rs2[i];
6920 if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
6921 // Branches don't write registers, consider the delay slot instead.
6922 type=itype[i+1];
6923 op=opcode[i+1];
6924 op2=opcode2[i+1];
6925 rt=rt1[i+1];
6926 s1=rs1[i+1];
6927 s2=rs2[i+1];
6928 lastbranch=is32;
6929 }
6930 switch(type) {
6931 case LOAD:
6932 if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
6933 opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
6934 is32&=~(1LL<<rt);
6935 else
6936 is32|=1LL<<rt;
6937 break;
6938 case STORE:
6939 case STORELR:
6940 break;
6941 case LOADLR:
6942 if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
6943 if(op==0x22) is32|=1LL<<rt; // LWL
6944 break;
6945 case IMM16:
6946 if (op==0x08||op==0x09|| // ADDI/ADDIU
6947 op==0x0a||op==0x0b|| // SLTI/SLTIU
6948 op==0x0c|| // ANDI
6949 op==0x0f) // LUI
6950 {
6951 is32|=1LL<<rt;
6952 }
6953 if(op==0x18||op==0x19) { // DADDI/DADDIU
6954 is32&=~(1LL<<rt);
6955 //if(imm[i]==0)
6956 // is32|=((is32>>s1)&1LL)<<rt;
6957 }
6958 if(op==0x0d||op==0x0e) { // ORI/XORI
6959 uint64_t sr=((is32>>s1)&1LL);
6960 is32&=~(1LL<<rt);
6961 is32|=sr<<rt;
6962 }
6963 break;
6964 case UJUMP:
6965 break;
6966 case RJUMP:
6967 break;
6968 case CJUMP:
6969 break;
6970 case SJUMP:
6971 break;
6972 case FJUMP:
6973 break;
6974 case ALU:
6975 if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
6976 is32|=1LL<<rt;
6977 }
6978 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
6979 is32|=1LL<<rt;
6980 }
6981 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
6982 uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
6983 is32&=~(1LL<<rt);
6984 is32|=sr<<rt;
6985 }
6986 else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
6987 if(s1==0&&s2==0) {
6988 is32|=1LL<<rt;
6989 }
6990 else if(s2==0) {
6991 uint64_t sr=((is32>>s1)&1LL);
6992 is32&=~(1LL<<rt);
6993 is32|=sr<<rt;
6994 }
6995 else if(s1==0) {
6996 uint64_t sr=((is32>>s2)&1LL);
6997 is32&=~(1LL<<rt);
6998 is32|=sr<<rt;
6999 }
7000 else {
7001 is32&=~(1LL<<rt);
7002 }
7003 }
7004 else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
7005 if(s1==0&&s2==0) {
7006 is32|=1LL<<rt;
7007 }
7008 else if(s2==0) {
7009 uint64_t sr=((is32>>s1)&1LL);
7010 is32&=~(1LL<<rt);
7011 is32|=sr<<rt;
7012 }
7013 else {
7014 is32&=~(1LL<<rt);
7015 }
7016 }
7017 break;
7018 case MULTDIV:
7019 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
7020 is32&=~((1LL<<HIREG)|(1LL<<LOREG));
7021 }
7022 else {
7023 is32|=(1LL<<HIREG)|(1LL<<LOREG);
7024 }
7025 break;
7026 case MOV:
7027 {
7028 uint64_t sr=((is32>>s1)&1LL);
7029 is32&=~(1LL<<rt);
7030 is32|=sr<<rt;
7031 }
7032 break;
7033 case SHIFT:
7034 if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
7035 else is32|=1LL<<rt; // SLLV/SRLV/SRAV
7036 break;
7037 case SHIFTIMM:
7038 is32|=1LL<<rt;
7039 // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
7040 if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
7041 break;
7042 case COP0:
7043 if(op2==0) is32|=1LL<<rt; // MFC0
7044 break;
7045 case COP1:
7046 case COP2:
7047 if(op2==0) is32|=1LL<<rt; // MFC1
7048 if(op2==1) is32&=~(1LL<<rt); // DMFC1
7049 if(op2==2) is32|=1LL<<rt; // CFC1
7050 break;
7051 case C1LS:
7052 case C2LS:
7053 break;
7054 case FLOAT:
7055 case FCONV:
7056 break;
7057 case FCOMP:
7058 break;
7059 case C2OP:
7060 case SYSCALL:
7061 case HLECALL:
7062 break;
7063 default:
7064 break;
7065 }
7066 is32|=1;
7067 p32[i]=is32;
7068
7069 if(i>0)
7070 {
7071 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
7072 {
7073 if(rt1[i-1]==31) // JAL/JALR
7074 {
7075 // Subroutine call will return here, don't alloc any registers
7076 is32=1;
7077 }
7078 else if(i+1<slen)
7079 {
7080 // Internal branch will jump here, match registers to caller
7081 is32=0x3FFFFFFFFLL;
7082 }
7083 }
7084 }
7085 }
7086}
7087
7088// Identify registers which may be assumed to contain 32-bit values
7089// and where optimizations will rely on this.
7090// This is used to determine whether backward branches can safely
7091// jump to a location with 64-bit values in registers.
7092static void provisional_r32()
7093{
7094 u_int r32=0;
7095 int i;
7096
7097 for (i=slen-1;i>=0;i--)
7098 {
7099 int hr;
7100 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7101 {
7102 if(ba[i]<start || ba[i]>=(start+slen*4))
7103 {
7104 // Branch out of this block, don't need anything
7105 r32=0;
7106 }
7107 else
7108 {
7109 // Internal branch
7110 // Need whatever matches the target
7111 // (and doesn't get overwritten by the delay slot instruction)
7112 r32=0;
7113 int t=(ba[i]-start)>>2;
7114 if(ba[i]>start+i*4) {
7115 // Forward branch
7116 //if(!(requires_32bit[t]&~regs[i].was32))
7117 // r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7118 if(!(pr32[t]&~regs[i].was32))
7119 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7120 }else{
7121 // Backward branch
7122 if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
7123 r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7124 }
7125 }
7126 // Conditional branch may need registers for following instructions
7127 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7128 {
7129 if(i<slen-2) {
7130 //r32|=requires_32bit[i+2];
7131 r32|=pr32[i+2];
7132 r32&=regs[i].was32;
7133 // Mark this address as a branch target since it may be called
7134 // upon return from interrupt
7135 //bt[i+2]=1;
7136 }
7137 }
7138 // Merge in delay slot
7139 if(!likely[i]) {
7140 // These are overwritten unless the branch is "likely"
7141 // and the delay slot is nullified if not taken
7142 r32&=~(1LL<<rt1[i+1]);
7143 r32&=~(1LL<<rt2[i+1]);
7144 }
7145 // Assume these are needed (delay slot)
7146 if(us1[i+1]>0)
7147 {
7148 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7149 }
7150 if(us2[i+1]>0)
7151 {
7152 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7153 }
7154 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7155 {
7156 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7157 }
7158 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7159 {
7160 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7161 }
7162 }
7163 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7164 {
7165 // SYSCALL instruction (software interrupt)
7166 r32=0;
7167 }
7168 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7169 {
7170 // ERET instruction (return from interrupt)
7171 r32=0;
7172 }
7173 // Check 32 bits
7174 r32&=~(1LL<<rt1[i]);
7175 r32&=~(1LL<<rt2[i]);
7176 if(us1[i]>0)
7177 {
7178 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7179 }
7180 if(us2[i]>0)
7181 {
7182 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7183 }
7184 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7185 {
7186 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7187 }
7188 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7189 {
7190 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7191 }
7192 //requires_32bit[i]=r32;
7193 pr32[i]=r32;
7194
7195 // Dirty registers which are 32-bit, require 32-bit input
7196 // as they will be written as 32-bit values
7197 for(hr=0;hr<HOST_REGS;hr++)
7198 {
7199 if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
7200 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7201 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7202 pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7203 //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7204 }
7205 }
7206 }
7207 }
7208}
7209
7210// Write back dirty registers as soon as we will no longer modify them,
7211// so that we don't end up with lots of writes at the branches.
7212void clean_registers(int istart,int iend,int wr)
7213{
7214 int i;
7215 int r;
7216 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7217 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7218 if(iend==slen-1) {
7219 will_dirty_i=will_dirty_next=0;
7220 wont_dirty_i=wont_dirty_next=0;
7221 }else{
7222 will_dirty_i=will_dirty_next=will_dirty[iend+1];
7223 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7224 }
7225 for (i=iend;i>=istart;i--)
7226 {
7227 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7228 {
7229 if(ba[i]<start || ba[i]>=(start+slen*4))
7230 {
7231 // Branch out of this block, flush all regs
7232 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7233 {
7234 // Unconditional branch
7235 will_dirty_i=0;
7236 wont_dirty_i=0;
7237 // Merge in delay slot (will dirty)
7238 for(r=0;r<HOST_REGS;r++) {
7239 if(r!=EXCLUDE_REG) {
7240 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7241 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7242 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7243 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7244 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7245 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7246 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7247 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7248 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7249 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7250 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7251 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7252 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7253 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7254 }
7255 }
7256 }
7257 else
7258 {
7259 // Conditional branch
7260 will_dirty_i=0;
7261 wont_dirty_i=wont_dirty_next;
7262 // Merge in delay slot (will dirty)
7263 for(r=0;r<HOST_REGS;r++) {
7264 if(r!=EXCLUDE_REG) {
7265 if(!likely[i]) {
7266 // Might not dirty if likely branch is not taken
7267 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7268 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7269 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7270 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7271 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7272 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7273 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7274 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7275 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7276 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7277 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7278 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7279 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7280 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7281 }
7282 }
7283 }
7284 }
7285 // Merge in delay slot (wont dirty)
7286 for(r=0;r<HOST_REGS;r++) {
7287 if(r!=EXCLUDE_REG) {
7288 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7289 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7290 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7291 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7292 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7293 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7294 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7295 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7296 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7297 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7298 }
7299 }
7300 if(wr) {
7301 #ifndef DESTRUCTIVE_WRITEBACK
7302 branch_regs[i].dirty&=wont_dirty_i;
7303 #endif
7304 branch_regs[i].dirty|=will_dirty_i;
7305 }
7306 }
7307 else
7308 {
7309 // Internal branch
7310 if(ba[i]<=start+i*4) {
7311 // Backward branch
7312 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7313 {
7314 // Unconditional branch
7315 temp_will_dirty=0;
7316 temp_wont_dirty=0;
7317 // Merge in delay slot (will dirty)
7318 for(r=0;r<HOST_REGS;r++) {
7319 if(r!=EXCLUDE_REG) {
7320 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7321 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7322 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7323 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7324 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7325 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7326 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7327 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7328 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7329 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7330 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7331 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7332 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7333 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7334 }
7335 }
7336 } else {
7337 // Conditional branch (not taken case)
7338 temp_will_dirty=will_dirty_next;
7339 temp_wont_dirty=wont_dirty_next;
7340 // Merge in delay slot (will dirty)
7341 for(r=0;r<HOST_REGS;r++) {
7342 if(r!=EXCLUDE_REG) {
7343 if(!likely[i]) {
7344 // Will not dirty if likely branch is not taken
7345 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7346 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7347 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7348 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7349 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7350 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7351 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7352 //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7353 //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7354 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7355 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7356 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7357 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7358 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7359 }
7360 }
7361 }
7362 }
7363 // Merge in delay slot (wont dirty)
7364 for(r=0;r<HOST_REGS;r++) {
7365 if(r!=EXCLUDE_REG) {
7366 if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7367 if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7368 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7369 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7370 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7371 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7372 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7373 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7374 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7375 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7376 }
7377 }
7378 // Deal with changed mappings
7379 if(i<iend) {
7380 for(r=0;r<HOST_REGS;r++) {
7381 if(r!=EXCLUDE_REG) {
7382 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7383 temp_will_dirty&=~(1<<r);
7384 temp_wont_dirty&=~(1<<r);
7385 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7386 temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7387 temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7388 } else {
7389 temp_will_dirty|=1<<r;
7390 temp_wont_dirty|=1<<r;
7391 }
7392 }
7393 }
7394 }
7395 }
7396 if(wr) {
7397 will_dirty[i]=temp_will_dirty;
7398 wont_dirty[i]=temp_wont_dirty;
7399 clean_registers((ba[i]-start)>>2,i-1,0);
7400 }else{
7401 // Limit recursion. It can take an excessive amount
7402 // of time if there are a lot of nested loops.
7403 will_dirty[(ba[i]-start)>>2]=0;
7404 wont_dirty[(ba[i]-start)>>2]=-1;
7405 }
7406 }
7407 /*else*/ if(1)
7408 {
7409 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7410 {
7411 // Unconditional branch
7412 will_dirty_i=0;
7413 wont_dirty_i=0;
7414 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7415 for(r=0;r<HOST_REGS;r++) {
7416 if(r!=EXCLUDE_REG) {
7417 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7418 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7419 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7420 }
7421 }
7422 }
7423 //}
7424 // Merge in delay slot
7425 for(r=0;r<HOST_REGS;r++) {
7426 if(r!=EXCLUDE_REG) {
7427 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7428 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7429 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7430 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7431 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7432 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7433 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7434 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7435 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7436 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7437 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7438 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7439 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7440 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7441 }
7442 }
7443 } else {
7444 // Conditional branch
7445 will_dirty_i=will_dirty_next;
7446 wont_dirty_i=wont_dirty_next;
7447 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7448 for(r=0;r<HOST_REGS;r++) {
7449 if(r!=EXCLUDE_REG) {
7450 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7451 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7452 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7453 }
7454 else
7455 {
7456 will_dirty_i&=~(1<<r);
7457 }
7458 // Treat delay slot as part of branch too
7459 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7460 will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7461 wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7462 }
7463 else
7464 {
7465 will_dirty[i+1]&=~(1<<r);
7466 }*/
7467 }
7468 }
7469 //}
7470 // Merge in delay slot
7471 for(r=0;r<HOST_REGS;r++) {
7472 if(r!=EXCLUDE_REG) {
7473 if(!likely[i]) {
7474 // Might not dirty if likely branch is not taken
7475 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7476 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7477 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7478 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7479 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7480 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7481 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7482 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7483 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7484 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7485 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7486 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7487 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7488 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7489 }
7490 }
7491 }
7492 }
7493 // Merge in delay slot
7494 for(r=0;r<HOST_REGS;r++) {
7495 if(r!=EXCLUDE_REG) {
7496 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7497 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7498 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7499 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7500 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7501 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7502 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7503 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7504 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7505 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7506 }
7507 }
7508 if(wr) {
7509 #ifndef DESTRUCTIVE_WRITEBACK
7510 branch_regs[i].dirty&=wont_dirty_i;
7511 #endif
7512 branch_regs[i].dirty|=will_dirty_i;
7513 }
7514 }
7515 }
7516 }
7517 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7518 {
7519 // SYSCALL instruction (software interrupt)
7520 will_dirty_i=0;
7521 wont_dirty_i=0;
7522 }
7523 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7524 {
7525 // ERET instruction (return from interrupt)
7526 will_dirty_i=0;
7527 wont_dirty_i=0;
7528 }
7529 will_dirty_next=will_dirty_i;
7530 wont_dirty_next=wont_dirty_i;
7531 for(r=0;r<HOST_REGS;r++) {
7532 if(r!=EXCLUDE_REG) {
7533 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7534 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7535 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7536 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7537 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7538 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7539 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7540 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7541 if(i>istart) {
7542 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7543 {
7544 // Don't store a register immediately after writing it,
7545 // may prevent dual-issue.
7546 if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7547 if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7548 }
7549 }
7550 }
7551 }
7552 // Save it
7553 will_dirty[i]=will_dirty_i;
7554 wont_dirty[i]=wont_dirty_i;
7555 // Mark registers that won't be dirtied as not dirty
7556 if(wr) {
7557 /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7558 for(r=0;r<HOST_REGS;r++) {
7559 if((will_dirty_i>>r)&1) {
7560 printf(" r%d",r);
7561 }
7562 }
7563 printf("\n");*/
7564
7565 //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7566 regs[i].dirty|=will_dirty_i;
7567 #ifndef DESTRUCTIVE_WRITEBACK
7568 regs[i].dirty&=wont_dirty_i;
7569 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7570 {
7571 if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7572 for(r=0;r<HOST_REGS;r++) {
7573 if(r!=EXCLUDE_REG) {
7574 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7575 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7576 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7577 }
7578 }
7579 }
7580 }
7581 else
7582 {
7583 if(i<iend) {
7584 for(r=0;r<HOST_REGS;r++) {
7585 if(r!=EXCLUDE_REG) {
7586 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7587 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7588 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7589 }
7590 }
7591 }
7592 }
7593 #endif
7594 //}
7595 }
7596 // Deal with changed mappings
7597 temp_will_dirty=will_dirty_i;
7598 temp_wont_dirty=wont_dirty_i;
7599 for(r=0;r<HOST_REGS;r++) {
7600 if(r!=EXCLUDE_REG) {
7601 int nr;
7602 if(regs[i].regmap[r]==regmap_pre[i][r]) {
7603 if(wr) {
7604 #ifndef DESTRUCTIVE_WRITEBACK
7605 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7606 #endif
7607 regs[i].wasdirty|=will_dirty_i&(1<<r);
7608 }
7609 }
7610 else if((nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7611 // Register moved to a different register
7612 will_dirty_i&=~(1<<r);
7613 wont_dirty_i&=~(1<<r);
7614 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7615 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7616 if(wr) {
7617 #ifndef DESTRUCTIVE_WRITEBACK
7618 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7619 #endif
7620 regs[i].wasdirty|=will_dirty_i&(1<<r);
7621 }
7622 }
7623 else {
7624 will_dirty_i&=~(1<<r);
7625 wont_dirty_i&=~(1<<r);
7626 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7627 will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7628 wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7629 } else {
7630 wont_dirty_i|=1<<r;
7631 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7632 }
7633 }
7634 }
7635 }
7636 }
7637}
7638
7639 /* disassembly */
7640void disassemble_inst(int i)
7641{
7642 if (bt[i]) printf("*"); else printf(" ");
7643 switch(itype[i]) {
7644 case UJUMP:
7645 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7646 case CJUMP:
7647 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7648 case SJUMP:
7649 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7650 case FJUMP:
7651 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7652 case RJUMP:
7653 if (opcode[i]==0x9&&rt1[i]!=31)
7654 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7655 else
7656 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7657 break;
7658 case SPAN:
7659 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7660 case IMM16:
7661 if(opcode[i]==0xf) //LUI
7662 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7663 else
7664 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7665 break;
7666 case LOAD:
7667 case LOADLR:
7668 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7669 break;
7670 case STORE:
7671 case STORELR:
7672 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7673 break;
7674 case ALU:
7675 case SHIFT:
7676 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7677 break;
7678 case MULTDIV:
7679 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7680 break;
7681 case SHIFTIMM:
7682 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7683 break;
7684 case MOV:
7685 if((opcode2[i]&0x1d)==0x10)
7686 printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7687 else if((opcode2[i]&0x1d)==0x11)
7688 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7689 else
7690 printf (" %x: %s\n",start+i*4,insn[i]);
7691 break;
7692 case COP0:
7693 if(opcode2[i]==0)
7694 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7695 else if(opcode2[i]==4)
7696 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7697 else printf (" %x: %s\n",start+i*4,insn[i]);
7698 break;
7699 case COP1:
7700 if(opcode2[i]<3)
7701 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7702 else if(opcode2[i]>3)
7703 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7704 else printf (" %x: %s\n",start+i*4,insn[i]);
7705 break;
7706 case COP2:
7707 if(opcode2[i]<3)
7708 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7709 else if(opcode2[i]>3)
7710 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7711 else printf (" %x: %s\n",start+i*4,insn[i]);
7712 break;
7713 case C1LS:
7714 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7715 break;
7716 case C2LS:
7717 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7718 break;
7719 case INTCALL:
7720 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
7721 break;
7722 default:
7723 //printf (" %s %8x\n",insn[i],source[i]);
7724 printf (" %x: %s\n",start+i*4,insn[i]);
7725 }
7726}
7727
7728void new_dynarec_init()
7729{
7730 printf("Init new dynarec\n");
7731 out=(u_char *)BASE_ADDR;
7732 if (mmap (out, 1<<TARGET_SIZE_2,
7733 PROT_READ | PROT_WRITE | PROT_EXEC,
7734 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
7735 -1, 0) <= 0) {printf("mmap() failed\n");}
7736#ifdef MUPEN64
7737 rdword=&readmem_dword;
7738 fake_pc.f.r.rs=&readmem_dword;
7739 fake_pc.f.r.rt=&readmem_dword;
7740 fake_pc.f.r.rd=&readmem_dword;
7741#endif
7742 int n;
7743 for(n=0x80000;n<0x80800;n++)
7744 invalid_code[n]=1;
7745 for(n=0;n<65536;n++)
7746 hash_table[n][0]=hash_table[n][2]=-1;
7747 memset(mini_ht,-1,sizeof(mini_ht));
7748 memset(restore_candidate,0,sizeof(restore_candidate));
7749 copy=shadow;
7750 expirep=16384; // Expiry pointer, +2 blocks
7751 pending_exception=0;
7752 literalcount=0;
7753#ifdef HOST_IMM8
7754 // Copy this into local area so we don't have to put it in every literal pool
7755 invc_ptr=invalid_code;
7756#endif
7757 stop_after_jal=0;
7758 // TLB
7759 using_tlb=0;
7760 for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7761 memory_map[n]=-1;
7762 for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7763 memory_map[n]=((u_int)rdram-0x80000000)>>2;
7764 for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7765 memory_map[n]=-1;
7766#ifdef MUPEN64
7767 for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
7768 writemem[n] = write_nomem_new;
7769 writememb[n] = write_nomemb_new;
7770 writememh[n] = write_nomemh_new;
7771#ifndef FORCE32
7772 writememd[n] = write_nomemd_new;
7773#endif
7774 readmem[n] = read_nomem_new;
7775 readmemb[n] = read_nomemb_new;
7776 readmemh[n] = read_nomemh_new;
7777#ifndef FORCE32
7778 readmemd[n] = read_nomemd_new;
7779#endif
7780 }
7781 for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
7782 writemem[n] = write_rdram_new;
7783 writememb[n] = write_rdramb_new;
7784 writememh[n] = write_rdramh_new;
7785#ifndef FORCE32
7786 writememd[n] = write_rdramd_new;
7787#endif
7788 }
7789 for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
7790 writemem[n] = write_nomem_new;
7791 writememb[n] = write_nomemb_new;
7792 writememh[n] = write_nomemh_new;
7793#ifndef FORCE32
7794 writememd[n] = write_nomemd_new;
7795#endif
7796 readmem[n] = read_nomem_new;
7797 readmemb[n] = read_nomemb_new;
7798 readmemh[n] = read_nomemh_new;
7799#ifndef FORCE32
7800 readmemd[n] = read_nomemd_new;
7801#endif
7802 }
7803#endif
7804 tlb_hacks();
7805 arch_init();
7806}
7807
7808void new_dynarec_cleanup()
7809{
7810 int n;
7811 if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
7812 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7813 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7814 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7815 #ifdef ROM_COPY
7816 if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
7817 #endif
7818}
7819
7820int new_recompile_block(int addr)
7821{
7822/*
7823 if(addr==0x800cd050) {
7824 int block;
7825 for(block=0x80000;block<0x80800;block++) invalidate_block(block);
7826 int n;
7827 for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
7828 }
7829*/
7830 //if(Count==365117028) tracedebug=1;
7831 assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7832 //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7833 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
7834 //if(debug)
7835 //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
7836 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
7837 /*if(Count>=312978186) {
7838 rlist();
7839 }*/
7840 //rlist();
7841 start = (u_int)addr&~3;
7842 //assert(((u_int)addr&1)==0);
7843#ifdef PCSX
7844 if (Config.HLE && start == 0x80001000) // hlecall
7845 {
7846 // XXX: is this enough? Maybe check hleSoftCall?
7847 u_int beginning=(u_int)out;
7848 u_int page=get_page(start);
7849 invalid_code[start>>12]=0;
7850 emit_movimm(start,0);
7851 emit_writeword(0,(int)&pcaddr);
7852 emit_jmp((int)new_dyna_leave);
7853#ifdef __arm__
7854 __clear_cache((void *)beginning,out);
7855#endif
7856 ll_add(jump_in+page,start,(void *)beginning);
7857 return 0;
7858 }
7859 else if ((u_int)addr < 0x00200000 ||
7860 (0xa0000000 <= addr && addr < 0xa0200000)) {
7861 // used for BIOS calls mostly?
7862 source = (u_int *)((u_int)rdram+(start&0x1fffff));
7863 pagelimit = (addr&0xa0000000)|0x00200000;
7864 }
7865 else if (!Config.HLE && (
7866/* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
7867 (0xbfc00000 <= addr && addr < 0xbfc80000))) {
7868 // BIOS
7869 source = (u_int *)((u_int)psxR+(start&0x7ffff));
7870 pagelimit = (addr&0xfff00000)|0x80000;
7871 }
7872 else
7873#endif
7874#ifdef MUPEN64
7875 if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
7876 source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
7877 pagelimit = 0xa4001000;
7878 }
7879 else
7880#endif
7881 if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
7882 source = (u_int *)((u_int)rdram+start-0x80000000);
7883 pagelimit = 0x80000000+RAM_SIZE;
7884 }
7885#ifndef DISABLE_TLB
7886 else if ((signed int)addr >= (signed int)0xC0000000) {
7887 //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
7888 //if(tlb_LUT_r[start>>12])
7889 //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
7890 if((signed int)memory_map[start>>12]>=0) {
7891 source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
7892 pagelimit=(start+4096)&0xFFFFF000;
7893 int map=memory_map[start>>12];
7894 int i;
7895 for(i=0;i<5;i++) {
7896 //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
7897 if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
7898 }
7899 assem_debug("pagelimit=%x\n",pagelimit);
7900 assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
7901 }
7902 else {
7903 assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
7904 //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
7905 return -1; // Caller will invoke exception handler
7906 }
7907 //printf("source= %x\n",(int)source);
7908 }
7909#endif
7910 else {
7911 printf("Compile at bogus memory address: %x \n", (int)addr);
7912 exit(1);
7913 }
7914
7915 /* Pass 1: disassemble */
7916 /* Pass 2: register dependencies, branch targets */
7917 /* Pass 3: register allocation */
7918 /* Pass 4: branch dependencies */
7919 /* Pass 5: pre-alloc */
7920 /* Pass 6: optimize clean/dirty state */
7921 /* Pass 7: flag 32-bit registers */
7922 /* Pass 8: assembly */
7923 /* Pass 9: linker */
7924 /* Pass 10: garbage collection / free memory */
7925
7926 int i,j;
7927 int done=0;
7928 unsigned int type,op,op2;
7929
7930 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
7931
7932 /* Pass 1 disassembly */
7933
7934 for(i=0;!done;i++) {
7935 bt[i]=0;likely[i]=0;op2=0;
7936 opcode[i]=op=source[i]>>26;
7937 switch(op)
7938 {
7939 case 0x00: strcpy(insn[i],"special"); type=NI;
7940 op2=source[i]&0x3f;
7941 switch(op2)
7942 {
7943 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
7944 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
7945 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
7946 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
7947 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
7948 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
7949 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
7950 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
7951 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
7952 case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
7953 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
7954 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
7955 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
7956 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
7957 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
7958 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
7959 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
7960 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
7961 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
7962 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
7963 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
7964 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
7965 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
7966 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
7967 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
7968 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
7969 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
7970 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
7971 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
7972 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
7973 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
7974 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
7975 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
7976 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
7977 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
7978 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
7979 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
7980 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
7981 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
7982 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
7983 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
7984 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
7985 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
7986 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
7987 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
7988 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
7989 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
7990 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
7991 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
7992 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
7993 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
7994 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
7995 }
7996 break;
7997 case 0x01: strcpy(insn[i],"regimm"); type=NI;
7998 op2=(source[i]>>16)&0x1f;
7999 switch(op2)
8000 {
8001 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
8002 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
8003 case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
8004 case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
8005 case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
8006 case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
8007 case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
8008 case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
8009 case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
8010 case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
8011 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
8012 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
8013 case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
8014 case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
8015 }
8016 break;
8017 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
8018 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
8019 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
8020 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
8021 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
8022 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
8023 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
8024 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
8025 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
8026 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
8027 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
8028 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
8029 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
8030 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
8031 case 0x10: strcpy(insn[i],"cop0"); type=NI;
8032 op2=(source[i]>>21)&0x1f;
8033 switch(op2)
8034 {
8035 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
8036 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
8037 case 0x10: strcpy(insn[i],"tlb"); type=NI;
8038 switch(source[i]&0x3f)
8039 {
8040 case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
8041 case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
8042 case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
8043 case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
8044#ifdef PCSX
8045 case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
8046#else
8047 case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
8048#endif
8049 }
8050 }
8051 break;
8052 case 0x11: strcpy(insn[i],"cop1"); type=NI;
8053 op2=(source[i]>>21)&0x1f;
8054 switch(op2)
8055 {
8056 case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
8057 case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
8058 case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
8059 case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
8060 case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
8061 case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
8062 case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
8063 switch((source[i]>>16)&0x3)
8064 {
8065 case 0x00: strcpy(insn[i],"BC1F"); break;
8066 case 0x01: strcpy(insn[i],"BC1T"); break;
8067 case 0x02: strcpy(insn[i],"BC1FL"); break;
8068 case 0x03: strcpy(insn[i],"BC1TL"); break;
8069 }
8070 break;
8071 case 0x10: strcpy(insn[i],"C1.S"); type=NI;
8072 switch(source[i]&0x3f)
8073 {
8074 case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
8075 case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
8076 case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
8077 case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
8078 case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
8079 case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
8080 case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
8081 case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
8082 case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
8083 case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
8084 case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
8085 case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
8086 case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
8087 case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
8088 case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
8089 case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
8090 case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
8091 case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
8092 case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
8093 case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
8094 case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
8095 case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
8096 case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
8097 case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
8098 case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
8099 case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
8100 case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
8101 case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
8102 case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
8103 case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
8104 case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
8105 case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
8106 case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
8107 case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
8108 case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
8109 }
8110 break;
8111 case 0x11: strcpy(insn[i],"C1.D"); type=NI;
8112 switch(source[i]&0x3f)
8113 {
8114 case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
8115 case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
8116 case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
8117 case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
8118 case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
8119 case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
8120 case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
8121 case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
8122 case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
8123 case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
8124 case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
8125 case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
8126 case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
8127 case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
8128 case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
8129 case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
8130 case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
8131 case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
8132 case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
8133 case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
8134 case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
8135 case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
8136 case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
8137 case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
8138 case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
8139 case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
8140 case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
8141 case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
8142 case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
8143 case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
8144 case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8145 case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8146 case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8147 case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8148 case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8149 }
8150 break;
8151 case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8152 switch(source[i]&0x3f)
8153 {
8154 case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8155 case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8156 }
8157 break;
8158 case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8159 switch(source[i]&0x3f)
8160 {
8161 case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8162 case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8163 }
8164 break;
8165 }
8166 break;
8167#ifndef FORCE32
8168 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8169 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8170 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8171 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8172 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8173 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8174 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8175 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
8176#endif
8177 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8178 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8179 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8180 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8181 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8182 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8183 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
8184 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
8185 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8186 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8187 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8188 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
8189#ifndef FORCE32
8190 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8191 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
8192#endif
8193 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8194 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8195 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8196 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
8197#ifndef FORCE32
8198 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8199 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8200 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
8201#endif
8202 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8203 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
8204#ifndef FORCE32
8205 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8206 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8207 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
8208#endif
8209#ifdef PCSX
8210 case 0x12: strcpy(insn[i],"COP2"); type=NI;
8211 // note: COP MIPS-1 encoding differs from MIPS32
8212 op2=(source[i]>>21)&0x1f;
8213 if (source[i]&0x3f) {
8214 if (gte_handlers[source[i]&0x3f]!=NULL) {
8215 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8216 type=C2OP;
8217 }
8218 }
8219 else switch(op2)
8220 {
8221 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8222 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8223 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8224 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
8225 }
8226 break;
8227 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8228 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8229 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8230#endif
8231 default: strcpy(insn[i],"???"); type=NI;
8232 printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
8233 break;
8234 }
8235#ifdef PCSX
8236 /* detect branch in delay slot early */
8237 if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
8238 opcode[i+1]=source[i+1]>>26;
8239 opcode2[i+1]=source[i+1]&0x3f;
8240 if((0<opcode[i+1]&&opcode[i+1]<8)||(opcode[i+1]==0&&(opcode2[i+1]==8||opcode2[i+1]==9))) {
8241 printf("branch in delay slot @%08x (%08x)\n", addr + i*4+4, addr);
8242 // don't handle first branch and call interpreter if it's hit
8243 type=INTCALL;
8244 }
8245 }
8246#endif
8247 itype[i]=type;
8248 opcode2[i]=op2;
8249 /* Get registers/immediates */
8250 lt1[i]=0;
8251 us1[i]=0;
8252 us2[i]=0;
8253 dep1[i]=0;
8254 dep2[i]=0;
8255 switch(type) {
8256 case LOAD:
8257 rs1[i]=(source[i]>>21)&0x1f;
8258 rs2[i]=0;
8259 rt1[i]=(source[i]>>16)&0x1f;
8260 rt2[i]=0;
8261 imm[i]=(short)source[i];
8262 break;
8263 case STORE:
8264 case STORELR:
8265 rs1[i]=(source[i]>>21)&0x1f;
8266 rs2[i]=(source[i]>>16)&0x1f;
8267 rt1[i]=0;
8268 rt2[i]=0;
8269 imm[i]=(short)source[i];
8270 if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8271 break;
8272 case LOADLR:
8273 // LWL/LWR only load part of the register,
8274 // therefore the target register must be treated as a source too
8275 rs1[i]=(source[i]>>21)&0x1f;
8276 rs2[i]=(source[i]>>16)&0x1f;
8277 rt1[i]=(source[i]>>16)&0x1f;
8278 rt2[i]=0;
8279 imm[i]=(short)source[i];
8280 if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8281 if(op==0x26) dep1[i]=rt1[i]; // LWR
8282 break;
8283 case IMM16:
8284 if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8285 else rs1[i]=(source[i]>>21)&0x1f;
8286 rs2[i]=0;
8287 rt1[i]=(source[i]>>16)&0x1f;
8288 rt2[i]=0;
8289 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8290 imm[i]=(unsigned short)source[i];
8291 }else{
8292 imm[i]=(short)source[i];
8293 }
8294 if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8295 if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8296 if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8297 break;
8298 case UJUMP:
8299 rs1[i]=0;
8300 rs2[i]=0;
8301 rt1[i]=0;
8302 rt2[i]=0;
8303 // The JAL instruction writes to r31.
8304 if (op&1) {
8305 rt1[i]=31;
8306 }
8307 rs2[i]=CCREG;
8308 break;
8309 case RJUMP:
8310 rs1[i]=(source[i]>>21)&0x1f;
8311 rs2[i]=0;
8312 rt1[i]=0;
8313 rt2[i]=0;
8314 // The JALR instruction writes to rd.
8315 if (op2&1) {
8316 rt1[i]=(source[i]>>11)&0x1f;
8317 }
8318 rs2[i]=CCREG;
8319 break;
8320 case CJUMP:
8321 rs1[i]=(source[i]>>21)&0x1f;
8322 rs2[i]=(source[i]>>16)&0x1f;
8323 rt1[i]=0;
8324 rt2[i]=0;
8325 if(op&2) { // BGTZ/BLEZ
8326 rs2[i]=0;
8327 }
8328 us1[i]=rs1[i];
8329 us2[i]=rs2[i];
8330 likely[i]=op>>4;
8331 break;
8332 case SJUMP:
8333 rs1[i]=(source[i]>>21)&0x1f;
8334 rs2[i]=CCREG;
8335 rt1[i]=0;
8336 rt2[i]=0;
8337 us1[i]=rs1[i];
8338 if(op2&0x10) { // BxxAL
8339 rt1[i]=31;
8340 // NOTE: If the branch is not taken, r31 is still overwritten
8341 }
8342 likely[i]=(op2&2)>>1;
8343 break;
8344 case FJUMP:
8345 rs1[i]=FSREG;
8346 rs2[i]=CSREG;
8347 rt1[i]=0;
8348 rt2[i]=0;
8349 likely[i]=((source[i])>>17)&1;
8350 break;
8351 case ALU:
8352 rs1[i]=(source[i]>>21)&0x1f; // source
8353 rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8354 rt1[i]=(source[i]>>11)&0x1f; // destination
8355 rt2[i]=0;
8356 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8357 us1[i]=rs1[i];us2[i]=rs2[i];
8358 }
8359 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8360 dep1[i]=rs1[i];dep2[i]=rs2[i];
8361 }
8362 else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8363 dep1[i]=rs1[i];dep2[i]=rs2[i];
8364 }
8365 break;
8366 case MULTDIV:
8367 rs1[i]=(source[i]>>21)&0x1f; // source
8368 rs2[i]=(source[i]>>16)&0x1f; // divisor
8369 rt1[i]=HIREG;
8370 rt2[i]=LOREG;
8371 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8372 us1[i]=rs1[i];us2[i]=rs2[i];
8373 }
8374 break;
8375 case MOV:
8376 rs1[i]=0;
8377 rs2[i]=0;
8378 rt1[i]=0;
8379 rt2[i]=0;
8380 if(op2==0x10) rs1[i]=HIREG; // MFHI
8381 if(op2==0x11) rt1[i]=HIREG; // MTHI
8382 if(op2==0x12) rs1[i]=LOREG; // MFLO
8383 if(op2==0x13) rt1[i]=LOREG; // MTLO
8384 if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8385 if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8386 dep1[i]=rs1[i];
8387 break;
8388 case SHIFT:
8389 rs1[i]=(source[i]>>16)&0x1f; // target of shift
8390 rs2[i]=(source[i]>>21)&0x1f; // shift amount
8391 rt1[i]=(source[i]>>11)&0x1f; // destination
8392 rt2[i]=0;
8393 // DSLLV/DSRLV/DSRAV are 64-bit
8394 if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8395 break;
8396 case SHIFTIMM:
8397 rs1[i]=(source[i]>>16)&0x1f;
8398 rs2[i]=0;
8399 rt1[i]=(source[i]>>11)&0x1f;
8400 rt2[i]=0;
8401 imm[i]=(source[i]>>6)&0x1f;
8402 // DSxx32 instructions
8403 if(op2>=0x3c) imm[i]|=0x20;
8404 // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8405 if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8406 break;
8407 case COP0:
8408 rs1[i]=0;
8409 rs2[i]=0;
8410 rt1[i]=0;
8411 rt2[i]=0;
8412 if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8413 if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8414 if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8415 if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8416 break;
8417 case COP1:
8418 case COP2:
8419 rs1[i]=0;
8420 rs2[i]=0;
8421 rt1[i]=0;
8422 rt2[i]=0;
8423 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8424 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8425 if(op2==5) us1[i]=rs1[i]; // DMTC1
8426 rs2[i]=CSREG;
8427 break;
8428 case C1LS:
8429 rs1[i]=(source[i]>>21)&0x1F;
8430 rs2[i]=CSREG;
8431 rt1[i]=0;
8432 rt2[i]=0;
8433 imm[i]=(short)source[i];
8434 break;
8435 case C2LS:
8436 rs1[i]=(source[i]>>21)&0x1F;
8437 rs2[i]=0;
8438 rt1[i]=0;
8439 rt2[i]=0;
8440 imm[i]=(short)source[i];
8441 break;
8442 case FLOAT:
8443 case FCONV:
8444 rs1[i]=0;
8445 rs2[i]=CSREG;
8446 rt1[i]=0;
8447 rt2[i]=0;
8448 break;
8449 case FCOMP:
8450 rs1[i]=FSREG;
8451 rs2[i]=CSREG;
8452 rt1[i]=FSREG;
8453 rt2[i]=0;
8454 break;
8455 case SYSCALL:
8456 case HLECALL:
8457 case INTCALL:
8458 rs1[i]=CCREG;
8459 rs2[i]=0;
8460 rt1[i]=0;
8461 rt2[i]=0;
8462 break;
8463 default:
8464 rs1[i]=0;
8465 rs2[i]=0;
8466 rt1[i]=0;
8467 rt2[i]=0;
8468 }
8469 /* Calculate branch target addresses */
8470 if(type==UJUMP)
8471 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8472 else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8473 ba[i]=start+i*4+8; // Ignore never taken branch
8474 else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8475 ba[i]=start+i*4+8; // Ignore never taken branch
8476 else if(type==CJUMP||type==SJUMP||type==FJUMP)
8477 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8478 else ba[i]=-1;
8479 /* Is this the end of the block? */
8480 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
8481#ifdef PCSX
8482 // check for link register access in delay slot
8483 int rt1_=rt1[i-1];
8484 if(rt1_!=0&&(rs1[i]==rt1_||rs2[i]==rt1_||rt1[i]==rt1_||rt2[i]==rt1_)) {
8485 printf("link access in delay slot @%08x (%08x)\n", addr + i*4, addr);
8486 ba[i-1]=-1;
8487 itype[i-1]=INTCALL;
8488 done=2;
8489 }
8490 else
8491#endif
8492 if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
8493 done=2;
8494 }
8495 else {
8496 if(stop_after_jal) done=1;
8497 // Stop on BREAK
8498 if((source[i+1]&0xfc00003f)==0x0d) done=1;
8499 }
8500 // Don't recompile stuff that's already compiled
8501 if(check_addr(start+i*4+4)) done=1;
8502 // Don't get too close to the limit
8503 if(i>MAXBLOCK/2) done=1;
8504 }
8505 if(itype[i]==SYSCALL&&stop_after_jal) done=1;
8506 if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
8507 if(done==2) {
8508 // Does the block continue due to a branch?
8509 for(j=i-1;j>=0;j--)
8510 {
8511 if(ba[j]==start+i*4+4) done=j=0;
8512 if(ba[j]==start+i*4+8) done=j=0;
8513 }
8514 }
8515 //assert(i<MAXBLOCK-1);
8516 if(start+i*4==pagelimit-4) done=1;
8517 assert(start+i*4<pagelimit);
8518 if (i==MAXBLOCK-1) done=1;
8519 // Stop if we're compiling junk
8520 if(itype[i]==NI&&opcode[i]==0x11) {
8521 done=stop_after_jal=1;
8522 printf("Disabled speculative precompilation\n");
8523 }
8524 }
8525 slen=i;
8526 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8527 if(start+i*4==pagelimit) {
8528 itype[i-1]=SPAN;
8529 }
8530 }
8531 assert(slen>0);
8532
8533 /* Pass 2 - Register dependencies and branch targets */
8534
8535 unneeded_registers(0,slen-1,0);
8536
8537 /* Pass 3 - Register allocation */
8538
8539 struct regstat current; // Current register allocations/status
8540 current.is32=1;
8541 current.dirty=0;
8542 current.u=unneeded_reg[0];
8543 current.uu=unneeded_reg_upper[0];
8544 clear_all_regs(current.regmap);
8545 alloc_reg(&current,0,CCREG);
8546 dirty_reg(&current,CCREG);
8547 current.isconst=0;
8548 current.wasconst=0;
8549 int ds=0;
8550 int cc=0;
8551 int hr;
8552
8553#ifndef FORCE32
8554 provisional_32bit();
8555#endif
8556 if((u_int)addr&1) {
8557 // First instruction is delay slot
8558 cc=-1;
8559 bt[1]=1;
8560 ds=1;
8561 unneeded_reg[0]=1;
8562 unneeded_reg_upper[0]=1;
8563 current.regmap[HOST_BTREG]=BTREG;
8564 }
8565
8566 for(i=0;i<slen;i++)
8567 {
8568 if(bt[i])
8569 {
8570 int hr;
8571 for(hr=0;hr<HOST_REGS;hr++)
8572 {
8573 // Is this really necessary?
8574 if(current.regmap[hr]==0) current.regmap[hr]=-1;
8575 }
8576 current.isconst=0;
8577 }
8578 if(i>1)
8579 {
8580 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8581 {
8582 if(rs1[i-2]==0||rs2[i-2]==0)
8583 {
8584 if(rs1[i-2]) {
8585 current.is32|=1LL<<rs1[i-2];
8586 int hr=get_reg(current.regmap,rs1[i-2]|64);
8587 if(hr>=0) current.regmap[hr]=-1;
8588 }
8589 if(rs2[i-2]) {
8590 current.is32|=1LL<<rs2[i-2];
8591 int hr=get_reg(current.regmap,rs2[i-2]|64);
8592 if(hr>=0) current.regmap[hr]=-1;
8593 }
8594 }
8595 }
8596 }
8597#ifndef FORCE32
8598 // If something jumps here with 64-bit values
8599 // then promote those registers to 64 bits
8600 if(bt[i])
8601 {
8602 uint64_t temp_is32=current.is32;
8603 for(j=i-1;j>=0;j--)
8604 {
8605 if(ba[j]==start+i*4)
8606 temp_is32&=branch_regs[j].is32;
8607 }
8608 for(j=i;j<slen;j++)
8609 {
8610 if(ba[j]==start+i*4)
8611 //temp_is32=1;
8612 temp_is32&=p32[j];
8613 }
8614 if(temp_is32!=current.is32) {
8615 //printf("dumping 32-bit regs (%x)\n",start+i*4);
8616 #ifdef DESTRUCTIVE_WRITEBACK
8617 for(hr=0;hr<HOST_REGS;hr++)
8618 {
8619 int r=current.regmap[hr];
8620 if(r>0&&r<64)
8621 {
8622 if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8623 temp_is32|=1LL<<r;
8624 //printf("restore %d\n",r);
8625 }
8626 }
8627 }
8628 #endif
8629 current.is32=temp_is32;
8630 }
8631 }
8632#else
8633 current.is32=-1LL;
8634#endif
8635
8636 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8637 regs[i].wasconst=current.isconst;
8638 regs[i].was32=current.is32;
8639 regs[i].wasdirty=current.dirty;
8640 #if defined(DESTRUCTIVE_WRITEBACK) && !defined(FORCE32)
8641 // To change a dirty register from 32 to 64 bits, we must write
8642 // it out during the previous cycle (for branches, 2 cycles)
8643 if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8644 {
8645 uint64_t temp_is32=current.is32;
8646 for(j=i-1;j>=0;j--)
8647 {
8648 if(ba[j]==start+i*4+4)
8649 temp_is32&=branch_regs[j].is32;
8650 }
8651 for(j=i;j<slen;j++)
8652 {
8653 if(ba[j]==start+i*4+4)
8654 //temp_is32=1;
8655 temp_is32&=p32[j];
8656 }
8657 if(temp_is32!=current.is32) {
8658 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8659 for(hr=0;hr<HOST_REGS;hr++)
8660 {
8661 int r=current.regmap[hr];
8662 if(r>0)
8663 {
8664 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8665 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
8666 {
8667 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
8668 {
8669 //printf("dump %d/r%d\n",hr,r);
8670 current.regmap[hr]=-1;
8671 if(get_reg(current.regmap,r|64)>=0)
8672 current.regmap[get_reg(current.regmap,r|64)]=-1;
8673 }
8674 }
8675 }
8676 }
8677 }
8678 }
8679 }
8680 else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
8681 {
8682 uint64_t temp_is32=current.is32;
8683 for(j=i-1;j>=0;j--)
8684 {
8685 if(ba[j]==start+i*4+8)
8686 temp_is32&=branch_regs[j].is32;
8687 }
8688 for(j=i;j<slen;j++)
8689 {
8690 if(ba[j]==start+i*4+8)
8691 //temp_is32=1;
8692 temp_is32&=p32[j];
8693 }
8694 if(temp_is32!=current.is32) {
8695 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8696 for(hr=0;hr<HOST_REGS;hr++)
8697 {
8698 int r=current.regmap[hr];
8699 if(r>0)
8700 {
8701 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8702 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
8703 {
8704 //printf("dump %d/r%d\n",hr,r);
8705 current.regmap[hr]=-1;
8706 if(get_reg(current.regmap,r|64)>=0)
8707 current.regmap[get_reg(current.regmap,r|64)]=-1;
8708 }
8709 }
8710 }
8711 }
8712 }
8713 }
8714 #endif
8715 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8716 if(i+1<slen) {
8717 current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8718 current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8719 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8720 current.u|=1;
8721 current.uu|=1;
8722 } else {
8723 current.u=1;
8724 current.uu=1;
8725 }
8726 } else {
8727 if(i+1<slen) {
8728 current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
8729 current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8730 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8731 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8732 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8733 current.u|=1;
8734 current.uu|=1;
8735 } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
8736 }
8737 is_ds[i]=ds;
8738 if(ds) {
8739 ds=0; // Skip delay slot, already allocated as part of branch
8740 // ...but we need to alloc it in case something jumps here
8741 if(i+1<slen) {
8742 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
8743 current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
8744 }else{
8745 current.u=branch_unneeded_reg[i-1];
8746 current.uu=branch_unneeded_reg_upper[i-1];
8747 }
8748 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8749 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8750 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8751 current.u|=1;
8752 current.uu|=1;
8753 struct regstat temp;
8754 memcpy(&temp,&current,sizeof(current));
8755 temp.wasdirty=temp.dirty;
8756 temp.was32=temp.is32;
8757 // TODO: Take into account unconditional branches, as below
8758 delayslot_alloc(&temp,i);
8759 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
8760 regs[i].wasdirty=temp.wasdirty;
8761 regs[i].was32=temp.was32;
8762 regs[i].dirty=temp.dirty;
8763 regs[i].is32=temp.is32;
8764 regs[i].isconst=0;
8765 regs[i].wasconst=0;
8766 current.isconst=0;
8767 // Create entry (branch target) regmap
8768 for(hr=0;hr<HOST_REGS;hr++)
8769 {
8770 int r=temp.regmap[hr];
8771 if(r>=0) {
8772 if(r!=regmap_pre[i][hr]) {
8773 regs[i].regmap_entry[hr]=-1;
8774 }
8775 else
8776 {
8777 if(r<64){
8778 if((current.u>>r)&1) {
8779 regs[i].regmap_entry[hr]=-1;
8780 regs[i].regmap[hr]=-1;
8781 //Don't clear regs in the delay slot as the branch might need them
8782 //current.regmap[hr]=-1;
8783 }else
8784 regs[i].regmap_entry[hr]=r;
8785 }
8786 else {
8787 if((current.uu>>(r&63))&1) {
8788 regs[i].regmap_entry[hr]=-1;
8789 regs[i].regmap[hr]=-1;
8790 //Don't clear regs in the delay slot as the branch might need them
8791 //current.regmap[hr]=-1;
8792 }else
8793 regs[i].regmap_entry[hr]=r;
8794 }
8795 }
8796 } else {
8797 // First instruction expects CCREG to be allocated
8798 if(i==0&&hr==HOST_CCREG)
8799 regs[i].regmap_entry[hr]=CCREG;
8800 else
8801 regs[i].regmap_entry[hr]=-1;
8802 }
8803 }
8804 }
8805 else { // Not delay slot
8806 switch(itype[i]) {
8807 case UJUMP:
8808 //current.isconst=0; // DEBUG
8809 //current.wasconst=0; // DEBUG
8810 //regs[i].wasconst=0; // DEBUG
8811 clear_const(&current,rt1[i]);
8812 alloc_cc(&current,i);
8813 dirty_reg(&current,CCREG);
8814 if (rt1[i]==31) {
8815 alloc_reg(&current,i,31);
8816 dirty_reg(&current,31);
8817 assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8818 assert(rt1[i+1]!=rt1[i]);
8819 #ifdef REG_PREFETCH
8820 alloc_reg(&current,i,PTEMP);
8821 #endif
8822 //current.is32|=1LL<<rt1[i];
8823 }
8824 delayslot_alloc(&current,i+1);
8825 //current.isconst=0; // DEBUG
8826 ds=1;
8827 //printf("i=%d, isconst=%x\n",i,current.isconst);
8828 break;
8829 case RJUMP:
8830 //current.isconst=0;
8831 //current.wasconst=0;
8832 //regs[i].wasconst=0;
8833 clear_const(&current,rs1[i]);
8834 clear_const(&current,rt1[i]);
8835 alloc_cc(&current,i);
8836 dirty_reg(&current,CCREG);
8837 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
8838 alloc_reg(&current,i,rs1[i]);
8839 if (rt1[i]!=0) {
8840 alloc_reg(&current,i,rt1[i]);
8841 dirty_reg(&current,rt1[i]);
8842 assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
8843 assert(rt1[i+1]!=rt1[i]);
8844 #ifdef REG_PREFETCH
8845 alloc_reg(&current,i,PTEMP);
8846 #endif
8847 }
8848 #ifdef USE_MINI_HT
8849 if(rs1[i]==31) { // JALR
8850 alloc_reg(&current,i,RHASH);
8851 #ifndef HOST_IMM_ADDR32
8852 alloc_reg(&current,i,RHTBL);
8853 #endif
8854 }
8855 #endif
8856 delayslot_alloc(&current,i+1);
8857 } else {
8858 // The delay slot overwrites our source register,
8859 // allocate a temporary register to hold the old value.
8860 current.isconst=0;
8861 current.wasconst=0;
8862 regs[i].wasconst=0;
8863 delayslot_alloc(&current,i+1);
8864 current.isconst=0;
8865 alloc_reg(&current,i,RTEMP);
8866 }
8867 //current.isconst=0; // DEBUG
8868 ds=1;
8869 break;
8870 case CJUMP:
8871 //current.isconst=0;
8872 //current.wasconst=0;
8873 //regs[i].wasconst=0;
8874 clear_const(&current,rs1[i]);
8875 clear_const(&current,rs2[i]);
8876 if((opcode[i]&0x3E)==4) // BEQ/BNE
8877 {
8878 alloc_cc(&current,i);
8879 dirty_reg(&current,CCREG);
8880 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8881 if(rs2[i]) alloc_reg(&current,i,rs2[i]);
8882 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8883 {
8884 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8885 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
8886 }
8887 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
8888 (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
8889 // The delay slot overwrites one of our conditions.
8890 // Allocate the branch condition registers instead.
8891 // Note that such a sequence of instructions could
8892 // be considered a bug since the branch can not be
8893 // re-executed if an exception occurs.
8894 current.isconst=0;
8895 current.wasconst=0;
8896 regs[i].wasconst=0;
8897 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8898 if(rs2[i]) alloc_reg(&current,i,rs2[i]);
8899 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8900 {
8901 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8902 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
8903 }
8904 }
8905 else delayslot_alloc(&current,i+1);
8906 }
8907 else
8908 if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
8909 {
8910 alloc_cc(&current,i);
8911 dirty_reg(&current,CCREG);
8912 alloc_reg(&current,i,rs1[i]);
8913 if(!(current.is32>>rs1[i]&1))
8914 {
8915 alloc_reg64(&current,i,rs1[i]);
8916 }
8917 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
8918 // The delay slot overwrites one of our conditions.
8919 // Allocate the branch condition registers instead.
8920 // Note that such a sequence of instructions could
8921 // be considered a bug since the branch can not be
8922 // re-executed if an exception occurs.
8923 current.isconst=0;
8924 current.wasconst=0;
8925 regs[i].wasconst=0;
8926 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8927 if(!((current.is32>>rs1[i])&1))
8928 {
8929 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8930 }
8931 }
8932 else delayslot_alloc(&current,i+1);
8933 }
8934 else
8935 // Don't alloc the delay slot yet because we might not execute it
8936 if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
8937 {
8938 current.isconst=0;
8939 current.wasconst=0;
8940 regs[i].wasconst=0;
8941 alloc_cc(&current,i);
8942 dirty_reg(&current,CCREG);
8943 alloc_reg(&current,i,rs1[i]);
8944 alloc_reg(&current,i,rs2[i]);
8945 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8946 {
8947 alloc_reg64(&current,i,rs1[i]);
8948 alloc_reg64(&current,i,rs2[i]);
8949 }
8950 }
8951 else
8952 if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
8953 {
8954 current.isconst=0;
8955 current.wasconst=0;
8956 regs[i].wasconst=0;
8957 alloc_cc(&current,i);
8958 dirty_reg(&current,CCREG);
8959 alloc_reg(&current,i,rs1[i]);
8960 if(!(current.is32>>rs1[i]&1))
8961 {
8962 alloc_reg64(&current,i,rs1[i]);
8963 }
8964 }
8965 ds=1;
8966 //current.isconst=0;
8967 break;
8968 case SJUMP:
8969 //current.isconst=0;
8970 //current.wasconst=0;
8971 //regs[i].wasconst=0;
8972 clear_const(&current,rs1[i]);
8973 clear_const(&current,rt1[i]);
8974 //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
8975 if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
8976 {
8977 alloc_cc(&current,i);
8978 dirty_reg(&current,CCREG);
8979 alloc_reg(&current,i,rs1[i]);
8980 if(!(current.is32>>rs1[i]&1))
8981 {
8982 alloc_reg64(&current,i,rs1[i]);
8983 }
8984 if (rt1[i]==31) { // BLTZAL/BGEZAL
8985 alloc_reg(&current,i,31);
8986 dirty_reg(&current,31);
8987 //#ifdef REG_PREFETCH
8988 //alloc_reg(&current,i,PTEMP);
8989 //#endif
8990 //current.is32|=1LL<<rt1[i];
8991 }
8992 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
8993 // The delay slot overwrites the branch condition.
8994 // Allocate the branch condition registers instead.
8995 // Note that such a sequence of instructions could
8996 // be considered a bug since the branch can not be
8997 // re-executed if an exception occurs.
8998 current.isconst=0;
8999 current.wasconst=0;
9000 regs[i].wasconst=0;
9001 if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9002 if(!((current.is32>>rs1[i])&1))
9003 {
9004 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9005 }
9006 }
9007 else delayslot_alloc(&current,i+1);
9008 }
9009 else
9010 // Don't alloc the delay slot yet because we might not execute it
9011 if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
9012 {
9013 current.isconst=0;
9014 current.wasconst=0;
9015 regs[i].wasconst=0;
9016 alloc_cc(&current,i);
9017 dirty_reg(&current,CCREG);
9018 alloc_reg(&current,i,rs1[i]);
9019 if(!(current.is32>>rs1[i]&1))
9020 {
9021 alloc_reg64(&current,i,rs1[i]);
9022 }
9023 }
9024 ds=1;
9025 //current.isconst=0;
9026 break;
9027 case FJUMP:
9028 current.isconst=0;
9029 current.wasconst=0;
9030 regs[i].wasconst=0;
9031 if(likely[i]==0) // BC1F/BC1T
9032 {
9033 // TODO: Theoretically we can run out of registers here on x86.
9034 // The delay slot can allocate up to six, and we need to check
9035 // CSREG before executing the delay slot. Possibly we can drop
9036 // the cycle count and then reload it after checking that the
9037 // FPU is in a usable state, or don't do out-of-order execution.
9038 alloc_cc(&current,i);
9039 dirty_reg(&current,CCREG);
9040 alloc_reg(&current,i,FSREG);
9041 alloc_reg(&current,i,CSREG);
9042 if(itype[i+1]==FCOMP) {
9043 // The delay slot overwrites the branch condition.
9044 // Allocate the branch condition registers instead.
9045 // Note that such a sequence of instructions could
9046 // be considered a bug since the branch can not be
9047 // re-executed if an exception occurs.
9048 alloc_cc(&current,i);
9049 dirty_reg(&current,CCREG);
9050 alloc_reg(&current,i,CSREG);
9051 alloc_reg(&current,i,FSREG);
9052 }
9053 else {
9054 delayslot_alloc(&current,i+1);
9055 alloc_reg(&current,i+1,CSREG);
9056 }
9057 }
9058 else
9059 // Don't alloc the delay slot yet because we might not execute it
9060 if(likely[i]) // BC1FL/BC1TL
9061 {
9062 alloc_cc(&current,i);
9063 dirty_reg(&current,CCREG);
9064 alloc_reg(&current,i,CSREG);
9065 alloc_reg(&current,i,FSREG);
9066 }
9067 ds=1;
9068 current.isconst=0;
9069 break;
9070 case IMM16:
9071 imm16_alloc(&current,i);
9072 break;
9073 case LOAD:
9074 case LOADLR:
9075 load_alloc(&current,i);
9076 break;
9077 case STORE:
9078 case STORELR:
9079 store_alloc(&current,i);
9080 break;
9081 case ALU:
9082 alu_alloc(&current,i);
9083 break;
9084 case SHIFT:
9085 shift_alloc(&current,i);
9086 break;
9087 case MULTDIV:
9088 multdiv_alloc(&current,i);
9089 break;
9090 case SHIFTIMM:
9091 shiftimm_alloc(&current,i);
9092 break;
9093 case MOV:
9094 mov_alloc(&current,i);
9095 break;
9096 case COP0:
9097 cop0_alloc(&current,i);
9098 break;
9099 case COP1:
9100 case COP2:
9101 cop1_alloc(&current,i);
9102 break;
9103 case C1LS:
9104 c1ls_alloc(&current,i);
9105 break;
9106 case C2LS:
9107 c2ls_alloc(&current,i);
9108 break;
9109 case C2OP:
9110 c2op_alloc(&current,i);
9111 break;
9112 case FCONV:
9113 fconv_alloc(&current,i);
9114 break;
9115 case FLOAT:
9116 float_alloc(&current,i);
9117 break;
9118 case FCOMP:
9119 fcomp_alloc(&current,i);
9120 break;
9121 case SYSCALL:
9122 case HLECALL:
9123 case INTCALL:
9124 syscall_alloc(&current,i);
9125 break;
9126 case SPAN:
9127 pagespan_alloc(&current,i);
9128 break;
9129 }
9130
9131 // Drop the upper half of registers that have become 32-bit
9132 current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
9133 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9134 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9135 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9136 current.uu|=1;
9137 } else {
9138 current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
9139 current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9140 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9141 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9142 current.uu|=1;
9143 }
9144
9145 // Create entry (branch target) regmap
9146 for(hr=0;hr<HOST_REGS;hr++)
9147 {
9148 int r,or,er;
9149 r=current.regmap[hr];
9150 if(r>=0) {
9151 if(r!=regmap_pre[i][hr]) {
9152 // TODO: delay slot (?)
9153 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9154 if(or<0||(r&63)>=TEMPREG){
9155 regs[i].regmap_entry[hr]=-1;
9156 }
9157 else
9158 {
9159 // Just move it to a different register
9160 regs[i].regmap_entry[hr]=r;
9161 // If it was dirty before, it's still dirty
9162 if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r&63);
9163 }
9164 }
9165 else
9166 {
9167 // Unneeded
9168 if(r==0){
9169 regs[i].regmap_entry[hr]=0;
9170 }
9171 else
9172 if(r<64){
9173 if((current.u>>r)&1) {
9174 regs[i].regmap_entry[hr]=-1;
9175 //regs[i].regmap[hr]=-1;
9176 current.regmap[hr]=-1;
9177 }else
9178 regs[i].regmap_entry[hr]=r;
9179 }
9180 else {
9181 if((current.uu>>(r&63))&1) {
9182 regs[i].regmap_entry[hr]=-1;
9183 //regs[i].regmap[hr]=-1;
9184 current.regmap[hr]=-1;
9185 }else
9186 regs[i].regmap_entry[hr]=r;
9187 }
9188 }
9189 } else {
9190 // Branches expect CCREG to be allocated at the target
9191 if(regmap_pre[i][hr]==CCREG)
9192 regs[i].regmap_entry[hr]=CCREG;
9193 else
9194 regs[i].regmap_entry[hr]=-1;
9195 }
9196 }
9197 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9198 }
9199 /* Branch post-alloc */
9200 if(i>0)
9201 {
9202 current.was32=current.is32;
9203 current.wasdirty=current.dirty;
9204 switch(itype[i-1]) {
9205 case UJUMP:
9206 memcpy(&branch_regs[i-1],&current,sizeof(current));
9207 branch_regs[i-1].isconst=0;
9208 branch_regs[i-1].wasconst=0;
9209 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9210 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9211 alloc_cc(&branch_regs[i-1],i-1);
9212 dirty_reg(&branch_regs[i-1],CCREG);
9213 if(rt1[i-1]==31) { // JAL
9214 alloc_reg(&branch_regs[i-1],i-1,31);
9215 dirty_reg(&branch_regs[i-1],31);
9216 branch_regs[i-1].is32|=1LL<<31;
9217 }
9218 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9219 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9220 break;
9221 case RJUMP:
9222 memcpy(&branch_regs[i-1],&current,sizeof(current));
9223 branch_regs[i-1].isconst=0;
9224 branch_regs[i-1].wasconst=0;
9225 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9226 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9227 alloc_cc(&branch_regs[i-1],i-1);
9228 dirty_reg(&branch_regs[i-1],CCREG);
9229 alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
9230 if(rt1[i-1]!=0) { // JALR
9231 alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9232 dirty_reg(&branch_regs[i-1],rt1[i-1]);
9233 branch_regs[i-1].is32|=1LL<<rt1[i-1];
9234 }
9235 #ifdef USE_MINI_HT
9236 if(rs1[i-1]==31) { // JALR
9237 alloc_reg(&branch_regs[i-1],i-1,RHASH);
9238 #ifndef HOST_IMM_ADDR32
9239 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9240 #endif
9241 }
9242 #endif
9243 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9244 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9245 break;
9246 case CJUMP:
9247 if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9248 {
9249 alloc_cc(&current,i-1);
9250 dirty_reg(&current,CCREG);
9251 if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9252 (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9253 // The delay slot overwrote one of our conditions
9254 // Delay slot goes after the test (in order)
9255 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9256 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9257 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9258 current.u|=1;
9259 current.uu|=1;
9260 delayslot_alloc(&current,i);
9261 current.isconst=0;
9262 }
9263 else
9264 {
9265 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9266 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9267 // Alloc the branch condition registers
9268 if(rs1[i-1]) alloc_reg(&current,i-1,rs1[i-1]);
9269 if(rs2[i-1]) alloc_reg(&current,i-1,rs2[i-1]);
9270 if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9271 {
9272 if(rs1[i-1]) alloc_reg64(&current,i-1,rs1[i-1]);
9273 if(rs2[i-1]) alloc_reg64(&current,i-1,rs2[i-1]);
9274 }
9275 }
9276 memcpy(&branch_regs[i-1],&current,sizeof(current));
9277 branch_regs[i-1].isconst=0;
9278 branch_regs[i-1].wasconst=0;
9279 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9280 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9281 }
9282 else
9283 if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9284 {
9285 alloc_cc(&current,i-1);
9286 dirty_reg(&current,CCREG);
9287 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9288 // The delay slot overwrote the branch condition
9289 // Delay slot goes after the test (in order)
9290 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9291 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9292 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9293 current.u|=1;
9294 current.uu|=1;
9295 delayslot_alloc(&current,i);
9296 current.isconst=0;
9297 }
9298 else
9299 {
9300 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9301 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9302 // Alloc the branch condition register
9303 alloc_reg(&current,i-1,rs1[i-1]);
9304 if(!(current.is32>>rs1[i-1]&1))
9305 {
9306 alloc_reg64(&current,i-1,rs1[i-1]);
9307 }
9308 }
9309 memcpy(&branch_regs[i-1],&current,sizeof(current));
9310 branch_regs[i-1].isconst=0;
9311 branch_regs[i-1].wasconst=0;
9312 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9313 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9314 }
9315 else
9316 // Alloc the delay slot in case the branch is taken
9317 if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9318 {
9319 memcpy(&branch_regs[i-1],&current,sizeof(current));
9320 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9321 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9322 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9323 alloc_cc(&branch_regs[i-1],i);
9324 dirty_reg(&branch_regs[i-1],CCREG);
9325 delayslot_alloc(&branch_regs[i-1],i);
9326 branch_regs[i-1].isconst=0;
9327 alloc_reg(&current,i,CCREG); // Not taken path
9328 dirty_reg(&current,CCREG);
9329 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9330 }
9331 else
9332 if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9333 {
9334 memcpy(&branch_regs[i-1],&current,sizeof(current));
9335 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9336 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9337 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9338 alloc_cc(&branch_regs[i-1],i);
9339 dirty_reg(&branch_regs[i-1],CCREG);
9340 delayslot_alloc(&branch_regs[i-1],i);
9341 branch_regs[i-1].isconst=0;
9342 alloc_reg(&current,i,CCREG); // Not taken path
9343 dirty_reg(&current,CCREG);
9344 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9345 }
9346 break;
9347 case SJUMP:
9348 //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9349 if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9350 {
9351 alloc_cc(&current,i-1);
9352 dirty_reg(&current,CCREG);
9353 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9354 // The delay slot overwrote the branch condition
9355 // Delay slot goes after the test (in order)
9356 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9357 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9358 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9359 current.u|=1;
9360 current.uu|=1;
9361 delayslot_alloc(&current,i);
9362 current.isconst=0;
9363 }
9364 else
9365 {
9366 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9367 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9368 // Alloc the branch condition register
9369 alloc_reg(&current,i-1,rs1[i-1]);
9370 if(!(current.is32>>rs1[i-1]&1))
9371 {
9372 alloc_reg64(&current,i-1,rs1[i-1]);
9373 }
9374 }
9375 memcpy(&branch_regs[i-1],&current,sizeof(current));
9376 branch_regs[i-1].isconst=0;
9377 branch_regs[i-1].wasconst=0;
9378 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9379 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9380 }
9381 else
9382 // Alloc the delay slot in case the branch is taken
9383 if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9384 {
9385 memcpy(&branch_regs[i-1],&current,sizeof(current));
9386 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9387 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9388 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9389 alloc_cc(&branch_regs[i-1],i);
9390 dirty_reg(&branch_regs[i-1],CCREG);
9391 delayslot_alloc(&branch_regs[i-1],i);
9392 branch_regs[i-1].isconst=0;
9393 alloc_reg(&current,i,CCREG); // Not taken path
9394 dirty_reg(&current,CCREG);
9395 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9396 }
9397 // FIXME: BLTZAL/BGEZAL
9398 if(opcode2[i-1]&0x10) { // BxxZAL
9399 alloc_reg(&branch_regs[i-1],i-1,31);
9400 dirty_reg(&branch_regs[i-1],31);
9401 branch_regs[i-1].is32|=1LL<<31;
9402 }
9403 break;
9404 case FJUMP:
9405 if(likely[i-1]==0) // BC1F/BC1T
9406 {
9407 alloc_cc(&current,i-1);
9408 dirty_reg(&current,CCREG);
9409 if(itype[i]==FCOMP) {
9410 // The delay slot overwrote the branch condition
9411 // Delay slot goes after the test (in order)
9412 delayslot_alloc(&current,i);
9413 current.isconst=0;
9414 }
9415 else
9416 {
9417 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9418 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9419 // Alloc the branch condition register
9420 alloc_reg(&current,i-1,FSREG);
9421 }
9422 memcpy(&branch_regs[i-1],&current,sizeof(current));
9423 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9424 }
9425 else // BC1FL/BC1TL
9426 {
9427 // Alloc the delay slot in case the branch is taken
9428 memcpy(&branch_regs[i-1],&current,sizeof(current));
9429 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9430 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9431 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9432 alloc_cc(&branch_regs[i-1],i);
9433 dirty_reg(&branch_regs[i-1],CCREG);
9434 delayslot_alloc(&branch_regs[i-1],i);
9435 branch_regs[i-1].isconst=0;
9436 alloc_reg(&current,i,CCREG); // Not taken path
9437 dirty_reg(&current,CCREG);
9438 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9439 }
9440 break;
9441 }
9442
9443 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9444 {
9445 if(rt1[i-1]==31) // JAL/JALR
9446 {
9447 // Subroutine call will return here, don't alloc any registers
9448 current.is32=1;
9449 current.dirty=0;
9450 clear_all_regs(current.regmap);
9451 alloc_reg(&current,i,CCREG);
9452 dirty_reg(&current,CCREG);
9453 }
9454 else if(i+1<slen)
9455 {
9456 // Internal branch will jump here, match registers to caller
9457 current.is32=0x3FFFFFFFFLL;
9458 current.dirty=0;
9459 clear_all_regs(current.regmap);
9460 alloc_reg(&current,i,CCREG);
9461 dirty_reg(&current,CCREG);
9462 for(j=i-1;j>=0;j--)
9463 {
9464 if(ba[j]==start+i*4+4) {
9465 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9466 current.is32=branch_regs[j].is32;
9467 current.dirty=branch_regs[j].dirty;
9468 break;
9469 }
9470 }
9471 while(j>=0) {
9472 if(ba[j]==start+i*4+4) {
9473 for(hr=0;hr<HOST_REGS;hr++) {
9474 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9475 current.regmap[hr]=-1;
9476 }
9477 current.is32&=branch_regs[j].is32;
9478 current.dirty&=branch_regs[j].dirty;
9479 }
9480 }
9481 j--;
9482 }
9483 }
9484 }
9485 }
9486
9487 // Count cycles in between branches
9488 ccadj[i]=cc;
9489 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
9490 {
9491 cc=0;
9492 }
9493 else
9494 {
9495 cc++;
9496 }
9497
9498 flush_dirty_uppers(&current);
9499 if(!is_ds[i]) {
9500 regs[i].is32=current.is32;
9501 regs[i].dirty=current.dirty;
9502 regs[i].isconst=current.isconst;
9503 memcpy(constmap[i],current.constmap,sizeof(current.constmap));
9504 }
9505 for(hr=0;hr<HOST_REGS;hr++) {
9506 if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
9507 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9508 regs[i].wasconst&=~(1<<hr);
9509 }
9510 }
9511 }
9512 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9513 }
9514
9515 /* Pass 4 - Cull unused host registers */
9516
9517 uint64_t nr=0;
9518
9519 for (i=slen-1;i>=0;i--)
9520 {
9521 int hr;
9522 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9523 {
9524 if(ba[i]<start || ba[i]>=(start+slen*4))
9525 {
9526 // Branch out of this block, don't need anything
9527 nr=0;
9528 }
9529 else
9530 {
9531 // Internal branch
9532 // Need whatever matches the target
9533 nr=0;
9534 int t=(ba[i]-start)>>2;
9535 for(hr=0;hr<HOST_REGS;hr++)
9536 {
9537 if(regs[i].regmap_entry[hr]>=0) {
9538 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9539 }
9540 }
9541 }
9542 // Conditional branch may need registers for following instructions
9543 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9544 {
9545 if(i<slen-2) {
9546 nr|=needed_reg[i+2];
9547 for(hr=0;hr<HOST_REGS;hr++)
9548 {
9549 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9550 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9551 }
9552 }
9553 }
9554 // Don't need stuff which is overwritten
9555 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9556 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9557 // Merge in delay slot
9558 for(hr=0;hr<HOST_REGS;hr++)
9559 {
9560 if(!likely[i]) {
9561 // These are overwritten unless the branch is "likely"
9562 // and the delay slot is nullified if not taken
9563 if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9564 if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9565 }
9566 if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9567 if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9568 if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9569 if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9570 if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9571 if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9572 if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9573 if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9574 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9575 if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9576 if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9577 }
9578 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9579 if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9580 if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9581 }
9582 if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
9583 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9584 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9585 }
9586 }
9587 }
9588 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
9589 {
9590 // SYSCALL instruction (software interrupt)
9591 nr=0;
9592 }
9593 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9594 {
9595 // ERET instruction (return from interrupt)
9596 nr=0;
9597 }
9598 else // Non-branch
9599 {
9600 if(i<slen-1) {
9601 for(hr=0;hr<HOST_REGS;hr++) {
9602 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9603 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9604 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9605 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9606 }
9607 }
9608 }
9609 for(hr=0;hr<HOST_REGS;hr++)
9610 {
9611 // Overwritten registers are not needed
9612 if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9613 if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9614 if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9615 // Source registers are needed
9616 if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9617 if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9618 if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9619 if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9620 if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9621 if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9622 if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9623 if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9624 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9625 if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9626 if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9627 }
9628 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
9629 if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9630 if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9631 }
9632 if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
9633 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9634 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9635 }
9636 // Don't store a register immediately after writing it,
9637 // may prevent dual-issue.
9638 // But do so if this is a branch target, otherwise we
9639 // might have to load the register before the branch.
9640 if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
9641 if((regmap_pre[i][hr]>0&&regmap_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
9642 (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
9643 if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9644 if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9645 }
9646 if((regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
9647 (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
9648 if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9649 if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9650 }
9651 }
9652 }
9653 // Cycle count is needed at branches. Assume it is needed at the target too.
9654 if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
9655 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9656 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9657 }
9658 // Save it
9659 needed_reg[i]=nr;
9660
9661 // Deallocate unneeded registers
9662 for(hr=0;hr<HOST_REGS;hr++)
9663 {
9664 if(!((nr>>hr)&1)) {
9665 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
9666 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9667 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9668 (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
9669 {
9670 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9671 {
9672 if(likely[i]) {
9673 regs[i].regmap[hr]=-1;
9674 regs[i].isconst&=~(1<<hr);
9675 if(i<slen-2) regmap_pre[i+2][hr]=-1;
9676 }
9677 }
9678 }
9679 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9680 {
9681 int d1=0,d2=0,map=0,temp=0;
9682 if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
9683 {
9684 d1=dep1[i+1];
9685 d2=dep2[i+1];
9686 }
9687 if(using_tlb) {
9688 if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
9689 itype[i+1]==STORE || itype[i+1]==STORELR ||
9690 itype[i+1]==C1LS || itype[i+1]==C2LS)
9691 map=TLREG;
9692 } else
9693 if(itype[i+1]==STORE || itype[i+1]==STORELR ||
9694 (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
9695 map=INVCP;
9696 }
9697 if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
9698 itype[i+1]==C1LS || itype[i+1]==C2LS)
9699 temp=FTEMP;
9700 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9701 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9702 (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
9703 (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
9704 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9705 regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
9706 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
9707 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
9708 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
9709 regs[i].regmap[hr]!=map )
9710 {
9711 regs[i].regmap[hr]=-1;
9712 regs[i].isconst&=~(1<<hr);
9713 if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
9714 (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
9715 (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
9716 (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
9717 (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
9718 branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
9719 (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
9720 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
9721 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
9722 branch_regs[i].regmap[hr]!=map)
9723 {
9724 branch_regs[i].regmap[hr]=-1;
9725 branch_regs[i].regmap_entry[hr]=-1;
9726 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9727 {
9728 if(!likely[i]&&i<slen-2) {
9729 regmap_pre[i+2][hr]=-1;
9730 }
9731 }
9732 }
9733 }
9734 }
9735 else
9736 {
9737 // Non-branch
9738 if(i>0)
9739 {
9740 int d1=0,d2=0,map=-1,temp=-1;
9741 if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
9742 {
9743 d1=dep1[i];
9744 d2=dep2[i];
9745 }
9746 if(using_tlb) {
9747 if(itype[i]==LOAD || itype[i]==LOADLR ||
9748 itype[i]==STORE || itype[i]==STORELR ||
9749 itype[i]==C1LS || itype[i]==C2LS)
9750 map=TLREG;
9751 } else if(itype[i]==STORE || itype[i]==STORELR ||
9752 (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
9753 map=INVCP;
9754 }
9755 if(itype[i]==LOADLR || itype[i]==STORELR ||
9756 itype[i]==C1LS || itype[i]==C2LS)
9757 temp=FTEMP;
9758 if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9759 (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
9760 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9761 regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
9762 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
9763 (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
9764 {
9765 if(i<slen-1&&!is_ds[i]) {
9766 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
9767 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
9768 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
9769 {
9770 printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
9771 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
9772 }
9773 regmap_pre[i+1][hr]=-1;
9774 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
9775 }
9776 regs[i].regmap[hr]=-1;
9777 regs[i].isconst&=~(1<<hr);
9778 }
9779 }
9780 }
9781 }
9782 }
9783 }
9784
9785 /* Pass 5 - Pre-allocate registers */
9786
9787 // If a register is allocated during a loop, try to allocate it for the
9788 // entire loop, if possible. This avoids loading/storing registers
9789 // inside of the loop.
9790
9791 signed char f_regmap[HOST_REGS];
9792 clear_all_regs(f_regmap);
9793 for(i=0;i<slen-1;i++)
9794 {
9795 if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9796 {
9797 if(ba[i]>=start && ba[i]<(start+i*4))
9798 if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
9799 ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
9800 ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
9801 ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
9802 ||itype[i+1]==FCOMP||itype[i+1]==FCONV
9803 ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
9804 {
9805 int t=(ba[i]-start)>>2;
9806 if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
9807 if(t<2||(itype[t-2]!=UJUMP)) // call/ret assumes no registers allocated
9808 for(hr=0;hr<HOST_REGS;hr++)
9809 {
9810 if(regs[i].regmap[hr]>64) {
9811 if(!((regs[i].dirty>>hr)&1))
9812 f_regmap[hr]=regs[i].regmap[hr];
9813 else f_regmap[hr]=-1;
9814 }
9815 else if(regs[i].regmap[hr]>=0) {
9816 if(f_regmap[hr]!=regs[i].regmap[hr]) {
9817 // dealloc old register
9818 int n;
9819 for(n=0;n<HOST_REGS;n++)
9820 {
9821 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
9822 }
9823 // and alloc new one
9824 f_regmap[hr]=regs[i].regmap[hr];
9825 }
9826 }
9827 if(branch_regs[i].regmap[hr]>64) {
9828 if(!((branch_regs[i].dirty>>hr)&1))
9829 f_regmap[hr]=branch_regs[i].regmap[hr];
9830 else f_regmap[hr]=-1;
9831 }
9832 else if(branch_regs[i].regmap[hr]>=0) {
9833 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
9834 // dealloc old register
9835 int n;
9836 for(n=0;n<HOST_REGS;n++)
9837 {
9838 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
9839 }
9840 // and alloc new one
9841 f_regmap[hr]=branch_regs[i].regmap[hr];
9842 }
9843 }
9844 if(itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
9845 ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
9846 ||itype[i+1]==FCOMP||itype[i+1]==FCONV
9847 ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
9848 {
9849 // Test both in case the delay slot is ooo,
9850 // could be done better...
9851 if(count_free_regs(branch_regs[i].regmap)<2
9852 ||count_free_regs(regs[i].regmap)<2)
9853 f_regmap[hr]=branch_regs[i].regmap[hr];
9854 }
9855 // Avoid dirty->clean transition
9856 // #ifdef DESTRUCTIVE_WRITEBACK here?
9857 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
9858 if(f_regmap[hr]>0) {
9859 if(regs[t].regmap_entry[hr]<0) {
9860 int r=f_regmap[hr];
9861 for(j=t;j<=i;j++)
9862 {
9863 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9864 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
9865 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
9866 if(r>63) {
9867 // NB This can exclude the case where the upper-half
9868 // register is lower numbered than the lower-half
9869 // register. Not sure if it's worth fixing...
9870 if(get_reg(regs[j].regmap,r&63)<0) break;
9871 if(regs[j].is32&(1LL<<(r&63))) break;
9872 }
9873 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
9874 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9875 int k;
9876 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
9877 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
9878 if(r>63) {
9879 if(get_reg(regs[i].regmap,r&63)<0) break;
9880 if(get_reg(branch_regs[i].regmap,r&63)<0) break;
9881 }
9882 k=i;
9883 while(k>1&&regs[k-1].regmap[hr]==-1) {
9884 if(itype[k-1]==STORE||itype[k-1]==STORELR
9885 ||itype[k-1]==C1LS||itype[k-1]==SHIFT||itype[k-1]==COP1
9886 ||itype[k-1]==FLOAT||itype[k-1]==FCONV||itype[k-1]==FCOMP
9887 ||itype[k-1]==COP2||itype[k-1]==C2LS||itype[k-1]==C2OP) {
9888 if(count_free_regs(regs[k-1].regmap)<2) {
9889 //printf("no free regs for store %x\n",start+(k-1)*4);
9890 break;
9891 }
9892 }
9893 else
9894 if(itype[k-1]!=NOP&&itype[k-1]!=MOV&&itype[k-1]!=ALU&&itype[k-1]!=SHIFTIMM&&itype[k-1]!=IMM16&&itype[k-1]!=LOAD) break;
9895 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
9896 //printf("no-match due to different register\n");
9897 break;
9898 }
9899 if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
9900 //printf("no-match due to branch\n");
9901 break;
9902 }
9903 // call/ret fast path assumes no registers allocated
9904 if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)) {
9905 break;
9906 }
9907 if(r>63) {
9908 // NB This can exclude the case where the upper-half
9909 // register is lower numbered than the lower-half
9910 // register. Not sure if it's worth fixing...
9911 if(get_reg(regs[k-1].regmap,r&63)<0) break;
9912 if(regs[k-1].is32&(1LL<<(r&63))) break;
9913 }
9914 k--;
9915 }
9916 if(i<slen-1) {
9917 if((regs[k].is32&(1LL<<f_regmap[hr]))!=
9918 (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
9919 //printf("bad match after branch\n");
9920 break;
9921 }
9922 }
9923 if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
9924 //printf("Extend r%d, %x ->\n",hr,start+k*4);
9925 while(k<i) {
9926 regs[k].regmap_entry[hr]=f_regmap[hr];
9927 regs[k].regmap[hr]=f_regmap[hr];
9928 regmap_pre[k+1][hr]=f_regmap[hr];
9929 regs[k].wasdirty&=~(1<<hr);
9930 regs[k].dirty&=~(1<<hr);
9931 regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
9932 regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
9933 regs[k].wasconst&=~(1<<hr);
9934 regs[k].isconst&=~(1<<hr);
9935 k++;
9936 }
9937 }
9938 else {
9939 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
9940 break;
9941 }
9942 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
9943 if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
9944 //printf("OK fill %x (r%d)\n",start+i*4,hr);
9945 regs[i].regmap_entry[hr]=f_regmap[hr];
9946 regs[i].regmap[hr]=f_regmap[hr];
9947 regs[i].wasdirty&=~(1<<hr);
9948 regs[i].dirty&=~(1<<hr);
9949 regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
9950 regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
9951 regs[i].wasconst&=~(1<<hr);
9952 regs[i].isconst&=~(1<<hr);
9953 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
9954 branch_regs[i].wasdirty&=~(1<<hr);
9955 branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
9956 branch_regs[i].regmap[hr]=f_regmap[hr];
9957 branch_regs[i].dirty&=~(1<<hr);
9958 branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
9959 branch_regs[i].wasconst&=~(1<<hr);
9960 branch_regs[i].isconst&=~(1<<hr);
9961 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
9962 regmap_pre[i+2][hr]=f_regmap[hr];
9963 regs[i+2].wasdirty&=~(1<<hr);
9964 regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
9965 assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
9966 (regs[i+2].was32&(1LL<<f_regmap[hr])));
9967 }
9968 }
9969 }
9970 for(k=t;k<j;k++) {
9971 regs[k].regmap_entry[hr]=f_regmap[hr];
9972 regs[k].regmap[hr]=f_regmap[hr];
9973 regmap_pre[k+1][hr]=f_regmap[hr];
9974 regs[k+1].wasdirty&=~(1<<hr);
9975 regs[k].dirty&=~(1<<hr);
9976 regs[k].wasconst&=~(1<<hr);
9977 regs[k].isconst&=~(1<<hr);
9978 }
9979 if(regs[j].regmap[hr]==f_regmap[hr])
9980 regs[j].regmap_entry[hr]=f_regmap[hr];
9981 break;
9982 }
9983 if(j==i) break;
9984 if(regs[j].regmap[hr]>=0)
9985 break;
9986 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
9987 //printf("no-match due to different register\n");
9988 break;
9989 }
9990 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
9991 //printf("32/64 mismatch %x %d\n",start+j*4,hr);
9992 break;
9993 }
9994 if(itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS
9995 ||itype[j]==SHIFT||itype[j]==COP1||itype[j]==FLOAT
9996 ||itype[j]==FCOMP||itype[j]==FCONV
9997 ||itype[j]==COP2||itype[j]==C2LS||itype[j]==C2OP) {
9998 if(count_free_regs(regs[j].regmap)<2) {
9999 //printf("No free regs for store %x\n",start+j*4);
10000 break;
10001 }
10002 }
10003 else if(itype[j]!=NOP&&itype[j]!=MOV&&itype[j]!=ALU&&itype[j]!=SHIFTIMM&&itype[j]!=IMM16&&itype[j]!=LOAD) break;
10004 if(f_regmap[hr]>=64) {
10005 if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
10006 break;
10007 }
10008 else
10009 {
10010 if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
10011 break;
10012 }
10013 }
10014 }
10015 }
10016 }
10017 }
10018 }
10019 }
10020 }else{
10021 int count=0;
10022 for(hr=0;hr<HOST_REGS;hr++)
10023 {
10024 if(hr!=EXCLUDE_REG) {
10025 if(regs[i].regmap[hr]>64) {
10026 if(!((regs[i].dirty>>hr)&1))
10027 f_regmap[hr]=regs[i].regmap[hr];
10028 }
10029 else if(regs[i].regmap[hr]>=0) {
10030 if(f_regmap[hr]!=regs[i].regmap[hr]) {
10031 // dealloc old register
10032 int n;
10033 for(n=0;n<HOST_REGS;n++)
10034 {
10035 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10036 }
10037 // and alloc new one
10038 f_regmap[hr]=regs[i].regmap[hr];
10039 }
10040 }
10041 else if(regs[i].regmap[hr]<0) count++;
10042 }
10043 }
10044 // Try to restore cycle count at branch targets
10045 if(bt[i]) {
10046 for(j=i;j<slen-1;j++) {
10047 if(regs[j].regmap[HOST_CCREG]!=-1) break;
10048 if(itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS
10049 ||itype[j]==SHIFT||itype[j]==COP1||itype[j]==FLOAT
10050 ||itype[j]==FCOMP||itype[j]==FCONV
10051 ||itype[j]==COP2||itype[j]==C2LS||itype[j]==C2OP) {
10052 if(count_free_regs(regs[j].regmap)<2) {
10053 //printf("no free regs for store %x\n",start+j*4);
10054 break;
10055 }
10056 }
10057 else
10058 if(itype[j]!=NOP&&itype[j]!=MOV&&itype[j]!=ALU&&itype[j]!=SHIFTIMM&&itype[j]!=IMM16&&itype[j]!=LOAD) break;
10059 }
10060 if(regs[j].regmap[HOST_CCREG]==CCREG) {
10061 int k=i;
10062 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
10063 while(k<j) {
10064 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10065 regs[k].regmap[HOST_CCREG]=CCREG;
10066 regmap_pre[k+1][HOST_CCREG]=CCREG;
10067 regs[k+1].wasdirty|=1<<HOST_CCREG;
10068 regs[k].dirty|=1<<HOST_CCREG;
10069 regs[k].wasconst&=~(1<<HOST_CCREG);
10070 regs[k].isconst&=~(1<<HOST_CCREG);
10071 k++;
10072 }
10073 regs[j].regmap_entry[HOST_CCREG]=CCREG;
10074 }
10075 // Work backwards from the branch target
10076 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
10077 {
10078 //printf("Extend backwards\n");
10079 int k;
10080 k=i;
10081 while(regs[k-1].regmap[HOST_CCREG]==-1) {
10082 if(itype[k-1]==STORE||itype[k-1]==STORELR||itype[k-1]==C1LS
10083 ||itype[k-1]==SHIFT||itype[k-1]==COP1||itype[k-1]==FLOAT
10084 ||itype[k-1]==FCONV||itype[k-1]==FCOMP
10085 ||itype[k-1]==COP2||itype[k-1]==C2LS||itype[k-1]==C2OP) {
10086 if(count_free_regs(regs[k-1].regmap)<2) {
10087 //printf("no free regs for store %x\n",start+(k-1)*4);
10088 break;
10089 }
10090 }
10091 else
10092 if(itype[k-1]!=NOP&&itype[k-1]!=MOV&&itype[k-1]!=ALU&&itype[k-1]!=SHIFTIMM&&itype[k-1]!=IMM16&&itype[k-1]!=LOAD) break;
10093 k--;
10094 }
10095 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
10096 //printf("Extend CC, %x ->\n",start+k*4);
10097 while(k<=i) {
10098 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10099 regs[k].regmap[HOST_CCREG]=CCREG;
10100 regmap_pre[k+1][HOST_CCREG]=CCREG;
10101 regs[k+1].wasdirty|=1<<HOST_CCREG;
10102 regs[k].dirty|=1<<HOST_CCREG;
10103 regs[k].wasconst&=~(1<<HOST_CCREG);
10104 regs[k].isconst&=~(1<<HOST_CCREG);
10105 k++;
10106 }
10107 }
10108 else {
10109 //printf("Fail Extend CC, %x ->\n",start+k*4);
10110 }
10111 }
10112 }
10113 if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
10114 itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
10115 itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
10116 itype[i]!=FCONV&&itype[i]!=FCOMP&&
10117 itype[i]!=COP2&&itype[i]!=C2LS&&itype[i]!=C2OP)
10118 {
10119 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
10120 }
10121 }
10122 }
10123
10124 // This allocates registers (if possible) one instruction prior
10125 // to use, which can avoid a load-use penalty on certain CPUs.
10126 for(i=0;i<slen-1;i++)
10127 {
10128 if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10129 {
10130 if(!bt[i+1])
10131 {
10132 if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
10133 ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
10134 {
10135 if(rs1[i+1]) {
10136 if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10137 {
10138 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10139 {
10140 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10141 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10142 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10143 regs[i].isconst&=~(1<<hr);
10144 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10145 constmap[i][hr]=constmap[i+1][hr];
10146 regs[i+1].wasdirty&=~(1<<hr);
10147 regs[i].dirty&=~(1<<hr);
10148 }
10149 }
10150 }
10151 if(rs2[i+1]) {
10152 if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10153 {
10154 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10155 {
10156 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10157 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10158 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10159 regs[i].isconst&=~(1<<hr);
10160 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10161 constmap[i][hr]=constmap[i+1][hr];
10162 regs[i+1].wasdirty&=~(1<<hr);
10163 regs[i].dirty&=~(1<<hr);
10164 }
10165 }
10166 }
10167 if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10168 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10169 {
10170 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10171 {
10172 regs[i].regmap[hr]=rs1[i+1];
10173 regmap_pre[i+1][hr]=rs1[i+1];
10174 regs[i+1].regmap_entry[hr]=rs1[i+1];
10175 regs[i].isconst&=~(1<<hr);
10176 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10177 constmap[i][hr]=constmap[i+1][hr];
10178 regs[i+1].wasdirty&=~(1<<hr);
10179 regs[i].dirty&=~(1<<hr);
10180 }
10181 }
10182 }
10183 if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10184 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10185 {
10186 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10187 {
10188 regs[i].regmap[hr]=rs1[i+1];
10189 regmap_pre[i+1][hr]=rs1[i+1];
10190 regs[i+1].regmap_entry[hr]=rs1[i+1];
10191 regs[i].isconst&=~(1<<hr);
10192 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10193 constmap[i][hr]=constmap[i+1][hr];
10194 regs[i+1].wasdirty&=~(1<<hr);
10195 regs[i].dirty&=~(1<<hr);
10196 }
10197 }
10198 }
10199 #ifndef HOST_IMM_ADDR32
10200 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
10201 hr=get_reg(regs[i+1].regmap,TLREG);
10202 if(hr>=0) {
10203 int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10204 if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10205 int nr;
10206 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10207 {
10208 regs[i].regmap[hr]=MGEN1+((i+1)&1);
10209 regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10210 regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10211 regs[i].isconst&=~(1<<hr);
10212 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10213 constmap[i][hr]=constmap[i+1][hr];
10214 regs[i+1].wasdirty&=~(1<<hr);
10215 regs[i].dirty&=~(1<<hr);
10216 }
10217 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10218 {
10219 // move it to another register
10220 regs[i+1].regmap[hr]=-1;
10221 regmap_pre[i+2][hr]=-1;
10222 regs[i+1].regmap[nr]=TLREG;
10223 regmap_pre[i+2][nr]=TLREG;
10224 regs[i].regmap[nr]=MGEN1+((i+1)&1);
10225 regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10226 regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10227 regs[i].isconst&=~(1<<nr);
10228 regs[i+1].isconst&=~(1<<nr);
10229 regs[i].dirty&=~(1<<nr);
10230 regs[i+1].wasdirty&=~(1<<nr);
10231 regs[i+1].dirty&=~(1<<nr);
10232 regs[i+2].wasdirty&=~(1<<nr);
10233 }
10234 }
10235 }
10236 }
10237 #endif
10238 if(itype[i+1]==STORE||itype[i+1]==STORELR
10239 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
10240 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10241 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10242 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10243 else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10244 assert(hr>=0);
10245 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10246 {
10247 regs[i].regmap[hr]=rs1[i+1];
10248 regmap_pre[i+1][hr]=rs1[i+1];
10249 regs[i+1].regmap_entry[hr]=rs1[i+1];
10250 regs[i].isconst&=~(1<<hr);
10251 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10252 constmap[i][hr]=constmap[i+1][hr];
10253 regs[i+1].wasdirty&=~(1<<hr);
10254 regs[i].dirty&=~(1<<hr);
10255 }
10256 }
10257 }
10258 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
10259 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10260 int nr;
10261 hr=get_reg(regs[i+1].regmap,FTEMP);
10262 assert(hr>=0);
10263 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10264 {
10265 regs[i].regmap[hr]=rs1[i+1];
10266 regmap_pre[i+1][hr]=rs1[i+1];
10267 regs[i+1].regmap_entry[hr]=rs1[i+1];
10268 regs[i].isconst&=~(1<<hr);
10269 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10270 constmap[i][hr]=constmap[i+1][hr];
10271 regs[i+1].wasdirty&=~(1<<hr);
10272 regs[i].dirty&=~(1<<hr);
10273 }
10274 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10275 {
10276 // move it to another register
10277 regs[i+1].regmap[hr]=-1;
10278 regmap_pre[i+2][hr]=-1;
10279 regs[i+1].regmap[nr]=FTEMP;
10280 regmap_pre[i+2][nr]=FTEMP;
10281 regs[i].regmap[nr]=rs1[i+1];
10282 regmap_pre[i+1][nr]=rs1[i+1];
10283 regs[i+1].regmap_entry[nr]=rs1[i+1];
10284 regs[i].isconst&=~(1<<nr);
10285 regs[i+1].isconst&=~(1<<nr);
10286 regs[i].dirty&=~(1<<nr);
10287 regs[i+1].wasdirty&=~(1<<nr);
10288 regs[i+1].dirty&=~(1<<nr);
10289 regs[i+2].wasdirty&=~(1<<nr);
10290 }
10291 }
10292 }
10293 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
10294 if(itype[i+1]==LOAD)
10295 hr=get_reg(regs[i+1].regmap,rt1[i+1]);
10296 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
10297 hr=get_reg(regs[i+1].regmap,FTEMP);
10298 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
10299 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10300 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10301 }
10302 if(hr>=0&&regs[i].regmap[hr]<0) {
10303 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10304 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10305 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10306 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10307 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10308 regs[i].isconst&=~(1<<hr);
10309 regs[i+1].wasdirty&=~(1<<hr);
10310 regs[i].dirty&=~(1<<hr);
10311 }
10312 }
10313 }
10314 }
10315 }
10316 }
10317 }
10318
10319 /* Pass 6 - Optimize clean/dirty state */
10320 clean_registers(0,slen-1,1);
10321
10322 /* Pass 7 - Identify 32-bit registers */
10323#ifndef FORCE32
10324 provisional_r32();
10325
10326 u_int r32=0;
10327
10328 for (i=slen-1;i>=0;i--)
10329 {
10330 int hr;
10331 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10332 {
10333 if(ba[i]<start || ba[i]>=(start+slen*4))
10334 {
10335 // Branch out of this block, don't need anything
10336 r32=0;
10337 }
10338 else
10339 {
10340 // Internal branch
10341 // Need whatever matches the target
10342 // (and doesn't get overwritten by the delay slot instruction)
10343 r32=0;
10344 int t=(ba[i]-start)>>2;
10345 if(ba[i]>start+i*4) {
10346 // Forward branch
10347 if(!(requires_32bit[t]&~regs[i].was32))
10348 r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10349 }else{
10350 // Backward branch
10351 //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10352 // r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10353 if(!(pr32[t]&~regs[i].was32))
10354 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10355 }
10356 }
10357 // Conditional branch may need registers for following instructions
10358 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10359 {
10360 if(i<slen-2) {
10361 r32|=requires_32bit[i+2];
10362 r32&=regs[i].was32;
10363 // Mark this address as a branch target since it may be called
10364 // upon return from interrupt
10365 bt[i+2]=1;
10366 }
10367 }
10368 // Merge in delay slot
10369 if(!likely[i]) {
10370 // These are overwritten unless the branch is "likely"
10371 // and the delay slot is nullified if not taken
10372 r32&=~(1LL<<rt1[i+1]);
10373 r32&=~(1LL<<rt2[i+1]);
10374 }
10375 // Assume these are needed (delay slot)
10376 if(us1[i+1]>0)
10377 {
10378 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10379 }
10380 if(us2[i+1]>0)
10381 {
10382 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10383 }
10384 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10385 {
10386 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10387 }
10388 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10389 {
10390 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10391 }
10392 }
10393 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
10394 {
10395 // SYSCALL instruction (software interrupt)
10396 r32=0;
10397 }
10398 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10399 {
10400 // ERET instruction (return from interrupt)
10401 r32=0;
10402 }
10403 // Check 32 bits
10404 r32&=~(1LL<<rt1[i]);
10405 r32&=~(1LL<<rt2[i]);
10406 if(us1[i]>0)
10407 {
10408 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10409 }
10410 if(us2[i]>0)
10411 {
10412 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10413 }
10414 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
10415 {
10416 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
10417 }
10418 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
10419 {
10420 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
10421 }
10422 requires_32bit[i]=r32;
10423
10424 // Dirty registers which are 32-bit, require 32-bit input
10425 // as they will be written as 32-bit values
10426 for(hr=0;hr<HOST_REGS;hr++)
10427 {
10428 if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
10429 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
10430 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
10431 requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
10432 }
10433 }
10434 }
10435 //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
10436 }
10437#endif
10438
10439 if(itype[slen-1]==SPAN) {
10440 bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
10441 }
10442
10443 /* Debug/disassembly */
10444 if((void*)assem_debug==(void*)printf)
10445 for(i=0;i<slen;i++)
10446 {
10447 printf("U:");
10448 int r;
10449 for(r=1;r<=CCREG;r++) {
10450 if((unneeded_reg[i]>>r)&1) {
10451 if(r==HIREG) printf(" HI");
10452 else if(r==LOREG) printf(" LO");
10453 else printf(" r%d",r);
10454 }
10455 }
10456#ifndef FORCE32
10457 printf(" UU:");
10458 for(r=1;r<=CCREG;r++) {
10459 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
10460 if(r==HIREG) printf(" HI");
10461 else if(r==LOREG) printf(" LO");
10462 else printf(" r%d",r);
10463 }
10464 }
10465 printf(" 32:");
10466 for(r=0;r<=CCREG;r++) {
10467 //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10468 if((regs[i].was32>>r)&1) {
10469 if(r==CCREG) printf(" CC");
10470 else if(r==HIREG) printf(" HI");
10471 else if(r==LOREG) printf(" LO");
10472 else printf(" r%d",r);
10473 }
10474 }
10475#endif
10476 printf("\n");
10477 #if defined(__i386__) || defined(__x86_64__)
10478 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
10479 #endif
10480 #ifdef __arm__
10481 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
10482 #endif
10483 printf("needs: ");
10484 if(needed_reg[i]&1) printf("eax ");
10485 if((needed_reg[i]>>1)&1) printf("ecx ");
10486 if((needed_reg[i]>>2)&1) printf("edx ");
10487 if((needed_reg[i]>>3)&1) printf("ebx ");
10488 if((needed_reg[i]>>5)&1) printf("ebp ");
10489 if((needed_reg[i]>>6)&1) printf("esi ");
10490 if((needed_reg[i]>>7)&1) printf("edi ");
10491 printf("r:");
10492 for(r=0;r<=CCREG;r++) {
10493 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10494 if((requires_32bit[i]>>r)&1) {
10495 if(r==CCREG) printf(" CC");
10496 else if(r==HIREG) printf(" HI");
10497 else if(r==LOREG) printf(" LO");
10498 else printf(" r%d",r);
10499 }
10500 }
10501 printf("\n");
10502 /*printf("pr:");
10503 for(r=0;r<=CCREG;r++) {
10504 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10505 if((pr32[i]>>r)&1) {
10506 if(r==CCREG) printf(" CC");
10507 else if(r==HIREG) printf(" HI");
10508 else if(r==LOREG) printf(" LO");
10509 else printf(" r%d",r);
10510 }
10511 }
10512 if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
10513 printf("\n");*/
10514 #if defined(__i386__) || defined(__x86_64__)
10515 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
10516 printf("dirty: ");
10517 if(regs[i].wasdirty&1) printf("eax ");
10518 if((regs[i].wasdirty>>1)&1) printf("ecx ");
10519 if((regs[i].wasdirty>>2)&1) printf("edx ");
10520 if((regs[i].wasdirty>>3)&1) printf("ebx ");
10521 if((regs[i].wasdirty>>5)&1) printf("ebp ");
10522 if((regs[i].wasdirty>>6)&1) printf("esi ");
10523 if((regs[i].wasdirty>>7)&1) printf("edi ");
10524 #endif
10525 #ifdef __arm__
10526 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
10527 printf("dirty: ");
10528 if(regs[i].wasdirty&1) printf("r0 ");
10529 if((regs[i].wasdirty>>1)&1) printf("r1 ");
10530 if((regs[i].wasdirty>>2)&1) printf("r2 ");
10531 if((regs[i].wasdirty>>3)&1) printf("r3 ");
10532 if((regs[i].wasdirty>>4)&1) printf("r4 ");
10533 if((regs[i].wasdirty>>5)&1) printf("r5 ");
10534 if((regs[i].wasdirty>>6)&1) printf("r6 ");
10535 if((regs[i].wasdirty>>7)&1) printf("r7 ");
10536 if((regs[i].wasdirty>>8)&1) printf("r8 ");
10537 if((regs[i].wasdirty>>9)&1) printf("r9 ");
10538 if((regs[i].wasdirty>>10)&1) printf("r10 ");
10539 if((regs[i].wasdirty>>12)&1) printf("r12 ");
10540 #endif
10541 printf("\n");
10542 disassemble_inst(i);
10543 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
10544 #if defined(__i386__) || defined(__x86_64__)
10545 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
10546 if(regs[i].dirty&1) printf("eax ");
10547 if((regs[i].dirty>>1)&1) printf("ecx ");
10548 if((regs[i].dirty>>2)&1) printf("edx ");
10549 if((regs[i].dirty>>3)&1) printf("ebx ");
10550 if((regs[i].dirty>>5)&1) printf("ebp ");
10551 if((regs[i].dirty>>6)&1) printf("esi ");
10552 if((regs[i].dirty>>7)&1) printf("edi ");
10553 #endif
10554 #ifdef __arm__
10555 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
10556 if(regs[i].dirty&1) printf("r0 ");
10557 if((regs[i].dirty>>1)&1) printf("r1 ");
10558 if((regs[i].dirty>>2)&1) printf("r2 ");
10559 if((regs[i].dirty>>3)&1) printf("r3 ");
10560 if((regs[i].dirty>>4)&1) printf("r4 ");
10561 if((regs[i].dirty>>5)&1) printf("r5 ");
10562 if((regs[i].dirty>>6)&1) printf("r6 ");
10563 if((regs[i].dirty>>7)&1) printf("r7 ");
10564 if((regs[i].dirty>>8)&1) printf("r8 ");
10565 if((regs[i].dirty>>9)&1) printf("r9 ");
10566 if((regs[i].dirty>>10)&1) printf("r10 ");
10567 if((regs[i].dirty>>12)&1) printf("r12 ");
10568 #endif
10569 printf("\n");
10570 if(regs[i].isconst) {
10571 printf("constants: ");
10572 #if defined(__i386__) || defined(__x86_64__)
10573 if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
10574 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
10575 if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
10576 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
10577 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
10578 if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
10579 if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
10580 #endif
10581 #ifdef __arm__
10582 if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
10583 if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
10584 if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
10585 if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
10586 if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
10587 if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
10588 if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
10589 if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
10590 if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
10591 if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
10592 if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
10593 if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
10594 #endif
10595 printf("\n");
10596 }
10597#ifndef FORCE32
10598 printf(" 32:");
10599 for(r=0;r<=CCREG;r++) {
10600 if((regs[i].is32>>r)&1) {
10601 if(r==CCREG) printf(" CC");
10602 else if(r==HIREG) printf(" HI");
10603 else if(r==LOREG) printf(" LO");
10604 else printf(" r%d",r);
10605 }
10606 }
10607 printf("\n");
10608#endif
10609 /*printf(" p32:");
10610 for(r=0;r<=CCREG;r++) {
10611 if((p32[i]>>r)&1) {
10612 if(r==CCREG) printf(" CC");
10613 else if(r==HIREG) printf(" HI");
10614 else if(r==LOREG) printf(" LO");
10615 else printf(" r%d",r);
10616 }
10617 }
10618 if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
10619 else printf("\n");*/
10620 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10621 #if defined(__i386__) || defined(__x86_64__)
10622 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
10623 if(branch_regs[i].dirty&1) printf("eax ");
10624 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
10625 if((branch_regs[i].dirty>>2)&1) printf("edx ");
10626 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
10627 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
10628 if((branch_regs[i].dirty>>6)&1) printf("esi ");
10629 if((branch_regs[i].dirty>>7)&1) printf("edi ");
10630 #endif
10631 #ifdef __arm__
10632 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
10633 if(branch_regs[i].dirty&1) printf("r0 ");
10634 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
10635 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
10636 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
10637 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
10638 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
10639 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
10640 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
10641 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
10642 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
10643 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
10644 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
10645 #endif
10646#ifndef FORCE32
10647 printf(" 32:");
10648 for(r=0;r<=CCREG;r++) {
10649 if((branch_regs[i].is32>>r)&1) {
10650 if(r==CCREG) printf(" CC");
10651 else if(r==HIREG) printf(" HI");
10652 else if(r==LOREG) printf(" LO");
10653 else printf(" r%d",r);
10654 }
10655 }
10656 printf("\n");
10657#endif
10658 }
10659 }
10660
10661 /* Pass 8 - Assembly */
10662 linkcount=0;stubcount=0;
10663 ds=0;is_delayslot=0;
10664 cop1_usable=0;
10665 uint64_t is32_pre=0;
10666 u_int dirty_pre=0;
10667 u_int beginning=(u_int)out;
10668 if((u_int)addr&1) {
10669 ds=1;
10670 pagespan_ds();
10671 }
10672 u_int instr_addr0_override=0;
10673
10674#ifdef PCSX
10675 if (start == 0x80030000) {
10676 // nasty hack for fastbios thing
10677 instr_addr0_override=(u_int)out;
10678 emit_movimm(start,0);
10679 emit_readword((int)&pcaddr,1);
10680 emit_writeword(0,(int)&pcaddr);
10681 emit_cmp(0,1);
10682 emit_jne((int)new_dyna_leave);
10683 }
10684#endif
10685 for(i=0;i<slen;i++)
10686 {
10687 //if(ds) printf("ds: ");
10688 if((void*)assem_debug==(void*)printf) disassemble_inst(i);
10689 if(ds) {
10690 ds=0; // Skip delay slot
10691 if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
10692 instr_addr[i]=0;
10693 } else {
10694 #ifndef DESTRUCTIVE_WRITEBACK
10695 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10696 {
10697 wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
10698 unneeded_reg[i],unneeded_reg_upper[i]);
10699 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
10700 unneeded_reg[i],unneeded_reg_upper[i]);
10701 }
10702 is32_pre=regs[i].is32;
10703 dirty_pre=regs[i].dirty;
10704 #endif
10705 // write back
10706 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10707 {
10708 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
10709 unneeded_reg[i],unneeded_reg_upper[i]);
10710 loop_preload(regmap_pre[i],regs[i].regmap_entry);
10711 }
10712 // branch target entry point
10713 instr_addr[i]=(u_int)out;
10714 assem_debug("<->\n");
10715 // load regs
10716 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
10717 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
10718 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
10719 address_generation(i,&regs[i],regs[i].regmap_entry);
10720 load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
10721 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10722 {
10723 // Load the delay slot registers if necessary
10724 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10725 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10726 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10727 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
10728 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
10729 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10730 }
10731 else if(i+1<slen)
10732 {
10733 // Preload registers for following instruction
10734 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10735 if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
10736 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10737 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10738 if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
10739 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
10740 }
10741 // TODO: if(is_ooo(i)) address_generation(i+1);
10742 if(itype[i]==CJUMP||itype[i]==FJUMP)
10743 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
10744 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
10745 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10746 if(bt[i]) cop1_usable=0;
10747 // assemble
10748 switch(itype[i]) {
10749 case ALU:
10750 alu_assemble(i,&regs[i]);break;
10751 case IMM16:
10752 imm16_assemble(i,&regs[i]);break;
10753 case SHIFT:
10754 shift_assemble(i,&regs[i]);break;
10755 case SHIFTIMM:
10756 shiftimm_assemble(i,&regs[i]);break;
10757 case LOAD:
10758 load_assemble(i,&regs[i]);break;
10759 case LOADLR:
10760 loadlr_assemble(i,&regs[i]);break;
10761 case STORE:
10762 store_assemble(i,&regs[i]);break;
10763 case STORELR:
10764 storelr_assemble(i,&regs[i]);break;
10765 case COP0:
10766 cop0_assemble(i,&regs[i]);break;
10767 case COP1:
10768 cop1_assemble(i,&regs[i]);break;
10769 case C1LS:
10770 c1ls_assemble(i,&regs[i]);break;
10771 case COP2:
10772 cop2_assemble(i,&regs[i]);break;
10773 case C2LS:
10774 c2ls_assemble(i,&regs[i]);break;
10775 case C2OP:
10776 c2op_assemble(i,&regs[i]);break;
10777 case FCONV:
10778 fconv_assemble(i,&regs[i]);break;
10779 case FLOAT:
10780 float_assemble(i,&regs[i]);break;
10781 case FCOMP:
10782 fcomp_assemble(i,&regs[i]);break;
10783 case MULTDIV:
10784 multdiv_assemble(i,&regs[i]);break;
10785 case MOV:
10786 mov_assemble(i,&regs[i]);break;
10787 case SYSCALL:
10788 syscall_assemble(i,&regs[i]);break;
10789 case HLECALL:
10790 hlecall_assemble(i,&regs[i]);break;
10791 case INTCALL:
10792 intcall_assemble(i,&regs[i]);break;
10793 case UJUMP:
10794 ujump_assemble(i,&regs[i]);ds=1;break;
10795 case RJUMP:
10796 rjump_assemble(i,&regs[i]);ds=1;break;
10797 case CJUMP:
10798 cjump_assemble(i,&regs[i]);ds=1;break;
10799 case SJUMP:
10800 sjump_assemble(i,&regs[i]);ds=1;break;
10801 case FJUMP:
10802 fjump_assemble(i,&regs[i]);ds=1;break;
10803 case SPAN:
10804 pagespan_assemble(i,&regs[i]);break;
10805 }
10806 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10807 literal_pool(1024);
10808 else
10809 literal_pool_jumpover(256);
10810 }
10811 }
10812 //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
10813 // If the block did not end with an unconditional branch,
10814 // add a jump to the next instruction.
10815 if(i>1) {
10816 if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
10817 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10818 assert(i==slen);
10819 if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
10820 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10821 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10822 emit_loadreg(CCREG,HOST_CCREG);
10823 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10824 }
10825 else if(!likely[i-2])
10826 {
10827 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
10828 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
10829 }
10830 else
10831 {
10832 store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
10833 assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
10834 }
10835 add_to_linker((int)out,start+i*4,0);
10836 emit_jmp(0);
10837 }
10838 }
10839 else
10840 {
10841 assert(i>0);
10842 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10843 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10844 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10845 emit_loadreg(CCREG,HOST_CCREG);
10846 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10847 add_to_linker((int)out,start+i*4,0);
10848 emit_jmp(0);
10849 }
10850
10851 // TODO: delay slot stubs?
10852 // Stubs
10853 for(i=0;i<stubcount;i++)
10854 {
10855 switch(stubs[i][0])
10856 {
10857 case LOADB_STUB:
10858 case LOADH_STUB:
10859 case LOADW_STUB:
10860 case LOADD_STUB:
10861 case LOADBU_STUB:
10862 case LOADHU_STUB:
10863 do_readstub(i);break;
10864 case STOREB_STUB:
10865 case STOREH_STUB:
10866 case STOREW_STUB:
10867 case STORED_STUB:
10868 do_writestub(i);break;
10869 case CC_STUB:
10870 do_ccstub(i);break;
10871 case INVCODE_STUB:
10872 do_invstub(i);break;
10873 case FP_STUB:
10874 do_cop1stub(i);break;
10875 case STORELR_STUB:
10876 do_unalignedwritestub(i);break;
10877 }
10878 }
10879
10880 if (instr_addr0_override)
10881 instr_addr[0] = instr_addr0_override;
10882
10883 /* Pass 9 - Linker */
10884 for(i=0;i<linkcount;i++)
10885 {
10886 assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
10887 literal_pool(64);
10888 if(!link_addr[i][2])
10889 {
10890 void *stub=out;
10891 void *addr=check_addr(link_addr[i][1]);
10892 emit_extjump(link_addr[i][0],link_addr[i][1]);
10893 if(addr) {
10894 set_jump_target(link_addr[i][0],(int)addr);
10895 add_link(link_addr[i][1],stub);
10896 }
10897 else set_jump_target(link_addr[i][0],(int)stub);
10898 }
10899 else
10900 {
10901 // Internal branch
10902 int target=(link_addr[i][1]-start)>>2;
10903 assert(target>=0&&target<slen);
10904 assert(instr_addr[target]);
10905 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10906 //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
10907 //#else
10908 set_jump_target(link_addr[i][0],instr_addr[target]);
10909 //#endif
10910 }
10911 }
10912 // External Branch Targets (jump_in)
10913 if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
10914 for(i=0;i<slen;i++)
10915 {
10916 if(bt[i]||i==0)
10917 {
10918 if(instr_addr[i]) // TODO - delay slots (=null)
10919 {
10920 u_int vaddr=start+i*4;
10921 u_int page=get_page(vaddr);
10922 u_int vpage=get_vpage(vaddr);
10923 literal_pool(256);
10924 //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
10925#ifndef FORCE32
10926 if(!requires_32bit[i])
10927#else
10928 if(1)
10929#endif
10930 {
10931 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
10932 assem_debug("jump_in: %x\n",start+i*4);
10933 ll_add(jump_dirty+vpage,vaddr,(void *)out);
10934 int entry_point=do_dirty_stub(i);
10935 ll_add(jump_in+page,vaddr,(void *)entry_point);
10936 // If there was an existing entry in the hash table,
10937 // replace it with the new address.
10938 // Don't add new entries. We'll insert the
10939 // ones that actually get used in check_addr().
10940 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
10941 if(ht_bin[0]==vaddr) {
10942 ht_bin[1]=entry_point;
10943 }
10944 if(ht_bin[2]==vaddr) {
10945 ht_bin[3]=entry_point;
10946 }
10947 }
10948 else
10949 {
10950 u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
10951 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
10952 assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
10953 //int entry_point=(int)out;
10954 ////assem_debug("entry_point: %x\n",entry_point);
10955 //load_regs_entry(i);
10956 //if(entry_point==(int)out)
10957 // entry_point=instr_addr[i];
10958 //else
10959 // emit_jmp(instr_addr[i]);
10960 //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
10961 ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
10962 int entry_point=do_dirty_stub(i);
10963 ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
10964 }
10965 }
10966 }
10967 }
10968 // Write out the literal pool if necessary
10969 literal_pool(0);
10970 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10971 // Align code
10972 if(((u_int)out)&7) emit_addnop(13);
10973 #endif
10974 assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
10975 //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
10976 memcpy(copy,source,slen*4);
10977 copy+=slen*4;
10978
10979 #ifdef __arm__
10980 __clear_cache((void *)beginning,out);
10981 #endif
10982
10983 // If we're within 256K of the end of the buffer,
10984 // start over from the beginning. (Is 256K enough?)
10985 if((int)out>BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
10986
10987 // Trap writes to any of the pages we compiled
10988 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
10989 invalid_code[i]=0;
10990#ifndef DISABLE_TLB
10991 memory_map[i]|=0x40000000;
10992 if((signed int)start>=(signed int)0xC0000000) {
10993 assert(using_tlb);
10994 j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
10995 invalid_code[j]=0;
10996 memory_map[j]|=0x40000000;
10997 //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
10998 }
10999#endif
11000 }
11001
11002 /* Pass 10 - Free memory by expiring oldest blocks */
11003
11004 int end=((((int)out-BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
11005 while(expirep!=end)
11006 {
11007 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
11008 int base=BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
11009 inv_debug("EXP: Phase %d\n",expirep);
11010 switch((expirep>>11)&3)
11011 {
11012 case 0:
11013 // Clear jump_in and jump_dirty
11014 ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
11015 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
11016 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
11017 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
11018 break;
11019 case 1:
11020 // Clear pointers
11021 ll_kill_pointers(jump_out[expirep&2047],base,shift);
11022 ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
11023 break;
11024 case 2:
11025 // Clear hash table
11026 for(i=0;i<32;i++) {
11027 int *ht_bin=hash_table[((expirep&2047)<<5)+i];
11028 if((ht_bin[3]>>shift)==(base>>shift) ||
11029 ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11030 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
11031 ht_bin[2]=ht_bin[3]=-1;
11032 }
11033 if((ht_bin[1]>>shift)==(base>>shift) ||
11034 ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11035 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
11036 ht_bin[0]=ht_bin[2];
11037 ht_bin[1]=ht_bin[3];
11038 ht_bin[2]=ht_bin[3]=-1;
11039 }
11040 }
11041 break;
11042 case 3:
11043 // Clear jump_out
11044 ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
11045 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
11046 break;
11047 }
11048 expirep=(expirep+1)&65535;
11049 }
11050 return 0;
11051}
11052
11053// vim:shiftwidth=2:expandtab
ARM optimized PCSX fork