[pcsx_rearmed.git] / libpcsxcore / psxcounters.c

/***************************************************************************
 *   Copyright (C) 2010 by Blade_Arma                                      *
 *                                                                         *
 *   This program is free software; you can redistribute it and/or modify  *
 *   it under the terms of the GNU General Public License as published by  *
 *   the Free Software Foundation; either version 2 of the License, or     *
 *   (at your option) any later version.                                   *
 *                                                                         *
 *   This program is distributed in the hope that it will be useful,       *
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
 *   GNU General Public License for more details.                          *
 *                                                                         *
 *   You should have received a copy of the GNU General Public License     *
 *   along with this program; if not, write to the                         *
 *   Free Software Foundation, Inc.,                                       *
 *   51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA.           *
 ***************************************************************************/

/*
 * Internal PSX counters.
 */

#include "psxcounters.h"
#include "gpu.h"
#include "debug.h"

/******************************************************************************/

enum
{
    Rc0Gate           = 0x0001, // 0    not implemented
    Rc1Gate           = 0x0001, // 0    not implemented
    Rc2Disable        = 0x0001, // 0    partially implemented
    RcUnknown1        = 0x0002, // 1    ?
    RcUnknown2        = 0x0004, // 2    ?
    RcCountToTarget   = 0x0008, // 3
    RcIrqOnTarget     = 0x0010, // 4
    RcIrqOnOverflow   = 0x0020, // 5
    RcIrqRegenerate   = 0x0040, // 6
    RcUnknown7        = 0x0080, // 7    ?
    Rc0PixelClock     = 0x0100, // 8    fake implementation
    Rc1HSyncClock     = 0x0100, // 8
    Rc2Unknown8       = 0x0100, // 8    ?
    Rc0Unknown9       = 0x0200, // 9    ?
    Rc1Unknown9       = 0x0200, // 9    ?
    Rc2OneEighthClock = 0x0200, // 9
    RcUnknown10       = 0x0400, // 10   ?
    RcCountEqTarget   = 0x0800, // 11
    RcOverflow        = 0x1000, // 12
    RcUnknown13       = 0x2000, // 13   ? (always zero)
    RcUnknown14       = 0x4000, // 14   ? (always zero)
    RcUnknown15       = 0x8000, // 15   ? (always zero)
};

#define CounterQuantity           ( 4 )
//static const u32 CounterQuantity  = 4;

static const u32 CountToOverflow  = 0;
static const u32 CountToTarget    = 1;

static const u32 FrameRate[]      = { 60, 50 };
static const u32 HSyncTotal[]     = { 263, 313 };
#define VBlankStart 240

#define VERBOSE_LEVEL 0
static const s32 VerboseLevel     = VERBOSE_LEVEL;

/******************************************************************************/

Rcnt rcnts[ CounterQuantity ];

u32 hSyncCount = 0;
u32 frame_counter = 0;
static u32 hsync_steps = 0;
static u32 base_cycle = 0;

u32 psxNextCounter = 0, psxNextsCounter = 0;

/******************************************************************************/

static inline
void setIrq( u32 irq )
{
    psxHu32ref(0x1070) |= SWAPu32(irq);
}

static
void verboseLog( u32 level, const char *str, ... )
{
#if VERBOSE_LEVEL > 0
    if( level <= VerboseLevel )
    {
        va_list va;
        char buf[ 4096 ];

        va_start( va, str );
        vsprintf( buf, str, va );
        va_end( va );

        printf( "%s", buf );
        fflush( stdout );
    }
#endif
}

/******************************************************************************/

static inline
void _psxRcntWcount( u32 index, u32 value )
{
    if( value > 0xffff )
    {
        verboseLog( 1, "[RCNT %i] wcount > 0xffff: %x\n", index, value );
        value &= 0xffff;
    }

    rcnts[index].cycleStart  = psxRegs.cycle;
    rcnts[index].cycleStart -= value * rcnts[index].rate;

    // TODO: <=.
    if( value < rcnts[index].target )
    {
        rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
        rcnts[index].counterState = CountToTarget;
    }
    else
    {
        rcnts[index].cycle = 0x10000 * rcnts[index].rate;
        rcnts[index].counterState = CountToOverflow;
    }
}

static inline
u32 _psxRcntRcount( u32 index )
{
    u32 count;

    count  = psxRegs.cycle;
    count -= rcnts[index].cycleStart;
    if (rcnts[index].rate > 1)
        count /= rcnts[index].rate;

    if( count > 0x10000 )
    {
        verboseLog( 1, "[RCNT %i] rcount > 0x10000: %x\n", index, count );
    }
    count &= 0xffff;

    return count;
}

static
void _psxRcntWmode( u32 index, u32 value )
{
    rcnts[index].mode = value;

    switch( index )
    {
        case 0:
            if( value & Rc0PixelClock )
            {
                rcnts[index].rate = 5;
            }
            else
            {
                rcnts[index].rate = 1;
            }
        break;
        case 1:
            if( value & Rc1HSyncClock )
            {
                rcnts[index].rate = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
            }
            else
            {
                rcnts[index].rate = 1;
            }
        break;
        case 2:
            if( value & Rc2OneEighthClock )
            {
                rcnts[index].rate = 8;
            }
            else
            {
                rcnts[index].rate = 1;
            }

            // TODO: wcount must work.
            if( value & Rc2Disable )
            {
                rcnts[index].rate = 0xffffffff;
            }
        break;
    }
}

/******************************************************************************/

static
void psxRcntSet()
{
    s32 countToUpdate;
    u32 i;

    psxNextsCounter = psxRegs.cycle;
    psxNextCounter  = 0x7fffffff;

    for( i = 0; i < CounterQuantity; ++i )
    {
        countToUpdate = rcnts[i].cycle - (psxNextsCounter - rcnts[i].cycleStart);

        if( countToUpdate < 0 )
        {
            psxNextCounter = 0;
            break;
        }

        if( countToUpdate < (s32)psxNextCounter )
        {
            psxNextCounter = countToUpdate;
        }
    }

    psxRegs.interrupt |= (1 << PSXINT_RCNT);
    new_dyna_set_event(PSXINT_RCNT, psxNextCounter);
}

/******************************************************************************/

static
void psxRcntReset( u32 index )
{
    u32 rcycles;

    rcnts[index].mode |= RcUnknown10;

    if( rcnts[index].counterState == CountToTarget )
    {
        rcycles = psxRegs.cycle - rcnts[index].cycleStart;
        if( rcnts[index].mode & RcCountToTarget )
        {
            rcycles -= rcnts[index].target * rcnts[index].rate;
            rcnts[index].cycleStart = psxRegs.cycle - rcycles;
        }
        else
        {
            rcnts[index].cycle = 0x10000 * rcnts[index].rate;
            rcnts[index].counterState = CountToOverflow;
        }

        if( rcnts[index].mode & RcIrqOnTarget )
        {
            if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
            {
                verboseLog( 3, "[RCNT %i] irq\n", index );
                setIrq( rcnts[index].irq );
                rcnts[index].irqState = 1;
            }
        }

        rcnts[index].mode |= RcCountEqTarget;

        if( rcycles < 0x10000 * rcnts[index].rate )
            return;
    }

    if( rcnts[index].counterState == CountToOverflow )
    {
        rcycles = psxRegs.cycle - rcnts[index].cycleStart;
        rcycles -= 0x10000 * rcnts[index].rate;

        rcnts[index].cycleStart = psxRegs.cycle - rcycles;

        if( rcycles < rcnts[index].target * rcnts[index].rate )
        {
            rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
            rcnts[index].counterState = CountToTarget;
        }

        if( rcnts[index].mode & RcIrqOnOverflow )
        {
            if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
            {
                verboseLog( 3, "[RCNT %i] irq\n", index );
                setIrq( rcnts[index].irq );
                rcnts[index].irqState = 1;
            }
        }

        rcnts[index].mode |= RcOverflow;
    }
}

void psxRcntUpdate()
{
    u32 cycle;

    cycle = psxRegs.cycle;

    // rcnt 0.
    if( cycle - rcnts[0].cycleStart >= rcnts[0].cycle )
    {
        psxRcntReset( 0 );
    }

    // rcnt 1.
    if( cycle - rcnts[1].cycleStart >= rcnts[1].cycle )
    {
        psxRcntReset( 1 );
    }

    // rcnt 2.
    if( cycle - rcnts[2].cycleStart >= rcnts[2].cycle )
    {
        psxRcntReset( 2 );
    }

    // rcnt base.
    if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle )
    {
        u32 leftover_cycles = cycle - rcnts[3].cycleStart - rcnts[3].cycle;
        u32 next_vsync;

        hSyncCount += hsync_steps;

        // VSync irq.
        if( hSyncCount == VBlankStart )
        {
            HW_GPU_STATUS &= ~PSXGPU_LCF;
            GPU_vBlank( 1, 0 );
            setIrq( 0x01 );

            EmuUpdate();
            GPU_updateLace();

            if( SPU_async )
            {
                SPU_async( cycle, 1 );
            }
        }
        
        // Update lace. (with InuYasha fix)
        if( hSyncCount >= (Config.VSyncWA ? HSyncTotal[Config.PsxType] / BIAS : HSyncTotal[Config.PsxType]) )
        {
            hSyncCount = 0;
            frame_counter++;

            gpuSyncPluginSR();
            if( (HW_GPU_STATUS & PSXGPU_ILACE_BITS) == PSXGPU_ILACE_BITS )
                HW_GPU_STATUS |= frame_counter << 31;
            GPU_vBlank( 0, HW_GPU_STATUS >> 31 );
        }

        // Schedule next call, in hsyncs
        hsync_steps = HSyncTotal[Config.PsxType] - hSyncCount;
        next_vsync = VBlankStart - hSyncCount; // ok to overflow
        if( next_vsync && next_vsync < hsync_steps )
            hsync_steps = next_vsync;

        rcnts[3].cycleStart = cycle - leftover_cycles;
        if (Config.PsxType)
                // 20.12 precision, clk / 50 / 313 ~= 2164.14
                base_cycle += hsync_steps * 8864320;
        else
                // clk / 60 / 263 ~= 2146.31
                base_cycle += hsync_steps * 8791293;
        rcnts[3].cycle = base_cycle >> 12;
        base_cycle &= 0xfff;
    }

    psxRcntSet();

#ifndef NDEBUG
    DebugVSync();
#endif
}

/******************************************************************************/

void psxRcntWcount( u32 index, u32 value )
{
    verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value );

    _psxRcntWcount( index, value );
    psxRcntSet();
}

void psxRcntWmode( u32 index, u32 value )
{
    verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value );

    _psxRcntWmode( index, value );
    _psxRcntWcount( index, 0 );

    rcnts[index].irqState = 0;
    psxRcntSet();
}

void psxRcntWtarget( u32 index, u32 value )
{
    verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value );

    rcnts[index].target = value;

    _psxRcntWcount( index, _psxRcntRcount( index ) );
    psxRcntSet();
}

/******************************************************************************/

u32 psxRcntRcount( u32 index )
{
    u32 count;

    count = _psxRcntRcount( index );

    // Parasite Eve 2 fix.
    if( Config.RCntFix )
    {
        if( index == 2 )
        {
            if( rcnts[index].counterState == CountToTarget )
            {
                count /= BIAS;
            }
        }
    }

    verboseLog( 2, "[RCNT %i] rcount: %x\n", index, count );

    return count;
}

u32 psxRcntRmode( u32 index )
{
    u16 mode;

    mode = rcnts[index].mode;
    rcnts[index].mode &= 0xe7ff;

    verboseLog( 2, "[RCNT %i] rmode: %x\n", index, mode );

    return mode;
}

u32 psxRcntRtarget( u32 index )
{
    verboseLog( 2, "[RCNT %i] rtarget: %x\n", index, rcnts[index].target );

    return rcnts[index].target;
}

/******************************************************************************/

void psxRcntInit()
{
    s32 i;

    // rcnt 0.
    rcnts[0].rate   = 1;
    rcnts[0].irq    = 0x10;

    // rcnt 1.
    rcnts[1].rate   = 1;
    rcnts[1].irq    = 0x20;

    // rcnt 2.
    rcnts[2].rate   = 1;
    rcnts[2].irq    = 0x40;

    // rcnt base.
    rcnts[3].rate   = 1;
    rcnts[3].mode   = RcCountToTarget;
    rcnts[3].target = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));

    for( i = 0; i < CounterQuantity; ++i )
    {
        _psxRcntWcount( i, 0 );
    }

    hSyncCount = 0;
    hsync_steps = 1;

    psxRcntSet();
}

/******************************************************************************/

s32 psxRcntFreeze( void *f, s32 Mode )
{
    u32 spuSyncCount = 0;
    u32 count;
    s32 i;

    gzfreeze( &rcnts, sizeof(rcnts) );
    gzfreeze( &hSyncCount, sizeof(hSyncCount) );
    gzfreeze( &spuSyncCount, sizeof(spuSyncCount) );
    gzfreeze( &psxNextCounter, sizeof(psxNextCounter) );
    gzfreeze( &psxNextsCounter, sizeof(psxNextsCounter) );

    if (Mode == 0)
    {
        // don't trust things from a savestate
        for( i = 0; i < CounterQuantity; ++i )
        {
            _psxRcntWmode( i, rcnts[i].mode );
            count = (psxRegs.cycle - rcnts[i].cycleStart) / rcnts[i].rate;
            _psxRcntWcount( i, count );
        }
        hsync_steps = (psxRegs.cycle - rcnts[3].cycleStart) / rcnts[3].target;
        psxRcntSet();

        base_cycle = 0;
    }

    return 0;
}

/******************************************************************************/
Commit	Line	Data
	1	/***************************************************************************
	2	* Copyright (C) 2010 by Blade_Arma *
	3	* *
	4	* This program is free software; you can redistribute it and/or modify *
	5	* it under the terms of the GNU General Public License as published by *
	6	* the Free Software Foundation; either version 2 of the License, or *
	7	* (at your option) any later version. *
	8	* *
	9	* This program is distributed in the hope that it will be useful, *
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of *
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
	12	* GNU General Public License for more details. *
	13	* *
	14	* You should have received a copy of the GNU General Public License *
	15	* along with this program; if not, write to the *
	16	* Free Software Foundation, Inc., *
	17	* 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
	18	***************************************************************************/
	19
	20	/*
	21	* Internal PSX counters.
	22	*/
	23
	24	#include "psxcounters.h"
	25	#include "gpu.h"
	26	#include "debug.h"
	27
	28	/******************************************************************************/
	29
	30	enum
	31	{
	32	Rc0Gate = 0x0001, // 0 not implemented
	33	Rc1Gate = 0x0001, // 0 not implemented
	34	Rc2Disable = 0x0001, // 0 partially implemented
	35	RcUnknown1 = 0x0002, // 1 ?
	36	RcUnknown2 = 0x0004, // 2 ?
	37	RcCountToTarget = 0x0008, // 3
	38	RcIrqOnTarget = 0x0010, // 4
	39	RcIrqOnOverflow = 0x0020, // 5
	40	RcIrqRegenerate = 0x0040, // 6
	41	RcUnknown7 = 0x0080, // 7 ?
	42	Rc0PixelClock = 0x0100, // 8 fake implementation
	43	Rc1HSyncClock = 0x0100, // 8
	44	Rc2Unknown8 = 0x0100, // 8 ?
	45	Rc0Unknown9 = 0x0200, // 9 ?
	46	Rc1Unknown9 = 0x0200, // 9 ?
	47	Rc2OneEighthClock = 0x0200, // 9
	48	RcUnknown10 = 0x0400, // 10 ?
	49	RcCountEqTarget = 0x0800, // 11
	50	RcOverflow = 0x1000, // 12
	51	RcUnknown13 = 0x2000, // 13 ? (always zero)
	52	RcUnknown14 = 0x4000, // 14 ? (always zero)
	53	RcUnknown15 = 0x8000, // 15 ? (always zero)
	54	};
	55
	56	#define CounterQuantity ( 4 )
	57	//static const u32 CounterQuantity = 4;
	58
	59	static const u32 CountToOverflow = 0;
	60	static const u32 CountToTarget = 1;
	61
	62	static const u32 FrameRate[] = { 60, 50 };
	63	static const u32 HSyncTotal[] = { 263, 313 };
	64	#define VBlankStart 240
	65
	66	#define VERBOSE_LEVEL 0
	67	static const s32 VerboseLevel = VERBOSE_LEVEL;
	68
	69	/******************************************************************************/
	70
	71	Rcnt rcnts[ CounterQuantity ];
	72
	73	u32 hSyncCount = 0;
	74	u32 frame_counter = 0;
	75	static u32 hsync_steps = 0;
	76	static u32 base_cycle = 0;
	77
	78	u32 psxNextCounter = 0, psxNextsCounter = 0;
	79
	80	/******************************************************************************/
	81
	82	static inline
	83	void setIrq( u32 irq )
	84	{
	85	psxHu32ref(0x1070) \|= SWAPu32(irq);
	86	}
	87
	88	static
	89	void verboseLog( u32 level, const char *str, ... )
	90	{
	91	#if VERBOSE_LEVEL > 0
	92	if( level <= VerboseLevel )
	93	{
	94	va_list va;
	95	char buf[ 4096 ];
	96
	97	va_start( va, str );
	98	vsprintf( buf, str, va );
	99	va_end( va );
	100
	101	printf( "%s", buf );
	102	fflush( stdout );
	103	}
	104	#endif
	105	}
	106
	107	/******************************************************************************/
	108
	109	static inline
	110	void _psxRcntWcount( u32 index, u32 value )
	111	{
	112	if( value > 0xffff )
	113	{
	114	verboseLog( 1, "[RCNT %i] wcount > 0xffff: %x\n", index, value );
	115	value &= 0xffff;
	116	}
	117
	118	rcnts[index].cycleStart = psxRegs.cycle;
	119	rcnts[index].cycleStart -= value * rcnts[index].rate;
	120
	121	// TODO: <=.
	122	if( value < rcnts[index].target )
	123	{
	124	rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
	125	rcnts[index].counterState = CountToTarget;
	126	}
	127	else
	128	{
	129	rcnts[index].cycle = 0x10000 * rcnts[index].rate;
	130	rcnts[index].counterState = CountToOverflow;
	131	}
	132	}
	133
	134	static inline
	135	u32 _psxRcntRcount( u32 index )
	136	{
	137	u32 count;
	138
	139	count = psxRegs.cycle;
	140	count -= rcnts[index].cycleStart;
	141	if (rcnts[index].rate > 1)
	142	count /= rcnts[index].rate;
	143
	144	if( count > 0x10000 )
	145	{
	146	verboseLog( 1, "[RCNT %i] rcount > 0x10000: %x\n", index, count );
	147	}
	148	count &= 0xffff;
	149
	150	return count;
	151	}
	152
	153	static
	154	void _psxRcntWmode( u32 index, u32 value )
	155	{
	156	rcnts[index].mode = value;
	157
	158	switch( index )
	159	{
	160	case 0:
	161	if( value & Rc0PixelClock )
	162	{
	163	rcnts[index].rate = 5;
	164	}
	165	else
	166	{
	167	rcnts[index].rate = 1;
	168	}
	169	break;
	170	case 1:
	171	if( value & Rc1HSyncClock )
	172	{
	173	rcnts[index].rate = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
	174	}
	175	else
	176	{
	177	rcnts[index].rate = 1;
	178	}
	179	break;
	180	case 2:
	181	if( value & Rc2OneEighthClock )
	182	{
	183	rcnts[index].rate = 8;
	184	}
	185	else
	186	{
	187	rcnts[index].rate = 1;
	188	}
	189
	190	// TODO: wcount must work.
	191	if( value & Rc2Disable )
	192	{
	193	rcnts[index].rate = 0xffffffff;
	194	}
	195	break;
	196	}
	197	}
	198
	199	/******************************************************************************/
	200
	201	static
	202	void psxRcntSet()
	203	{
	204	s32 countToUpdate;
	205	u32 i;
	206
	207	psxNextsCounter = psxRegs.cycle;
	208	psxNextCounter = 0x7fffffff;
	209
	210	for( i = 0; i < CounterQuantity; ++i )
	211	{
	212	countToUpdate = rcnts[i].cycle - (psxNextsCounter - rcnts[i].cycleStart);
	213
	214	if( countToUpdate < 0 )
	215	{
	216	psxNextCounter = 0;
	217	break;
	218	}
	219
	220	if( countToUpdate < (s32)psxNextCounter )
	221	{
	222	psxNextCounter = countToUpdate;
	223	}
	224	}
	225
	226	psxRegs.interrupt \|= (1 << PSXINT_RCNT);
	227	new_dyna_set_event(PSXINT_RCNT, psxNextCounter);
	228	}
	229
	230	/******************************************************************************/
	231
	232	static
	233	void psxRcntReset( u32 index )
	234	{
	235	u32 rcycles;
	236
	237	rcnts[index].mode \|= RcUnknown10;
	238
	239	if( rcnts[index].counterState == CountToTarget )
	240	{
	241	rcycles = psxRegs.cycle - rcnts[index].cycleStart;
	242	if( rcnts[index].mode & RcCountToTarget )
	243	{
	244	rcycles -= rcnts[index].target * rcnts[index].rate;
	245	rcnts[index].cycleStart = psxRegs.cycle - rcycles;
	246	}
	247	else
	248	{
	249	rcnts[index].cycle = 0x10000 * rcnts[index].rate;
	250	rcnts[index].counterState = CountToOverflow;
	251	}
	252
	253	if( rcnts[index].mode & RcIrqOnTarget )
	254	{
	255	if( (rcnts[index].mode & RcIrqRegenerate) \|\| (!rcnts[index].irqState) )
	256	{
	257	verboseLog( 3, "[RCNT %i] irq\n", index );
	258	setIrq( rcnts[index].irq );
	259	rcnts[index].irqState = 1;
	260	}
	261	}
	262
	263	rcnts[index].mode \|= RcCountEqTarget;
	264
	265	if( rcycles < 0x10000 * rcnts[index].rate )
	266	return;
	267	}
	268
	269	if( rcnts[index].counterState == CountToOverflow )
	270	{
	271	rcycles = psxRegs.cycle - rcnts[index].cycleStart;
	272	rcycles -= 0x10000 * rcnts[index].rate;
	273
	274	rcnts[index].cycleStart = psxRegs.cycle - rcycles;
	275
	276	if( rcycles < rcnts[index].target * rcnts[index].rate )
	277	{
	278	rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
	279	rcnts[index].counterState = CountToTarget;
	280	}
	281
	282	if( rcnts[index].mode & RcIrqOnOverflow )
	283	{
	284	if( (rcnts[index].mode & RcIrqRegenerate) \|\| (!rcnts[index].irqState) )
	285	{
	286	verboseLog( 3, "[RCNT %i] irq\n", index );
	287	setIrq( rcnts[index].irq );
	288	rcnts[index].irqState = 1;
	289	}
	290	}
	291
	292	rcnts[index].mode \|= RcOverflow;
	293	}
	294	}
	295
	296	void psxRcntUpdate()
	297	{
	298	u32 cycle;
	299
	300	cycle = psxRegs.cycle;
	301
	302	// rcnt 0.
	303	if( cycle - rcnts[0].cycleStart >= rcnts[0].cycle )
	304	{
	305	psxRcntReset( 0 );
	306	}
	307
	308	// rcnt 1.
	309	if( cycle - rcnts[1].cycleStart >= rcnts[1].cycle )
	310	{
	311	psxRcntReset( 1 );
	312	}
	313
	314	// rcnt 2.
	315	if( cycle - rcnts[2].cycleStart >= rcnts[2].cycle )
	316	{
	317	psxRcntReset( 2 );
	318	}
	319
	320	// rcnt base.
	321	if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle )
	322	{
	323	u32 leftover_cycles = cycle - rcnts[3].cycleStart - rcnts[3].cycle;
	324	u32 next_vsync;
	325
	326	hSyncCount += hsync_steps;
	327
	328	// VSync irq.
	329	if( hSyncCount == VBlankStart )
	330	{
	331	HW_GPU_STATUS &= ~PSXGPU_LCF;
	332	GPU_vBlank( 1, 0 );
	333	setIrq( 0x01 );
	334
	335	EmuUpdate();
	336	GPU_updateLace();
	337
	338	if( SPU_async )
	339	{
	340	SPU_async( cycle, 1 );
	341	}
	342	}
	343
	344	// Update lace. (with InuYasha fix)
	345	if( hSyncCount >= (Config.VSyncWA ? HSyncTotal[Config.PsxType] / BIAS : HSyncTotal[Config.PsxType]) )
	346	{
	347	hSyncCount = 0;
	348	frame_counter++;
	349
	350	gpuSyncPluginSR();
	351	if( (HW_GPU_STATUS & PSXGPU_ILACE_BITS) == PSXGPU_ILACE_BITS )
	352	HW_GPU_STATUS \|= frame_counter << 31;
	353	GPU_vBlank( 0, HW_GPU_STATUS >> 31 );
	354	}
	355
	356	// Schedule next call, in hsyncs
	357	hsync_steps = HSyncTotal[Config.PsxType] - hSyncCount;
	358	next_vsync = VBlankStart - hSyncCount; // ok to overflow
	359	if( next_vsync && next_vsync < hsync_steps )
	360	hsync_steps = next_vsync;
	361
	362	rcnts[3].cycleStart = cycle - leftover_cycles;
	363	if (Config.PsxType)
	364	// 20.12 precision, clk / 50 / 313 ~= 2164.14
	365	base_cycle += hsync_steps * 8864320;
	366	else
	367	// clk / 60 / 263 ~= 2146.31
	368	base_cycle += hsync_steps * 8791293;
	369	rcnts[3].cycle = base_cycle >> 12;
	370	base_cycle &= 0xfff;
	371	}
	372
	373	psxRcntSet();
	374
	375	#ifndef NDEBUG
	376	DebugVSync();
	377	#endif
	378	}
	379
	380	/******************************************************************************/
	381
	382	void psxRcntWcount( u32 index, u32 value )
	383	{
	384	verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value );
	385
	386	_psxRcntWcount( index, value );
	387	psxRcntSet();
	388	}
	389
	390	void psxRcntWmode( u32 index, u32 value )
	391	{
	392	verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value );
	393
	394	_psxRcntWmode( index, value );
	395	_psxRcntWcount( index, 0 );
	396
	397	rcnts[index].irqState = 0;
	398	psxRcntSet();
	399	}
	400
	401	void psxRcntWtarget( u32 index, u32 value )
	402	{
	403	verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value );
	404
	405	rcnts[index].target = value;
	406
	407	_psxRcntWcount( index, _psxRcntRcount( index ) );
	408	psxRcntSet();
	409	}
	410
	411	/******************************************************************************/
	412
	413	u32 psxRcntRcount( u32 index )
	414	{
	415	u32 count;
	416
	417	count = _psxRcntRcount( index );
	418
	419	// Parasite Eve 2 fix.
	420	if( Config.RCntFix )
	421	{
	422	if( index == 2 )
	423	{
	424	if( rcnts[index].counterState == CountToTarget )
	425	{
	426	count /= BIAS;
	427	}
	428	}
	429	}
	430
	431	verboseLog( 2, "[RCNT %i] rcount: %x\n", index, count );
	432
	433	return count;
	434	}
	435
	436	u32 psxRcntRmode( u32 index )
	437	{
	438	u16 mode;
	439
	440	mode = rcnts[index].mode;
	441	rcnts[index].mode &= 0xe7ff;
	442
	443	verboseLog( 2, "[RCNT %i] rmode: %x\n", index, mode );
	444
	445	return mode;
	446	}
	447
	448	u32 psxRcntRtarget( u32 index )
	449	{
	450	verboseLog( 2, "[RCNT %i] rtarget: %x\n", index, rcnts[index].target );
	451
	452	return rcnts[index].target;
	453	}
	454
	455	/******************************************************************************/
	456
	457	void psxRcntInit()
	458	{
	459	s32 i;
	460
	461	// rcnt 0.
	462	rcnts[0].rate = 1;
	463	rcnts[0].irq = 0x10;
	464
	465	// rcnt 1.
	466	rcnts[1].rate = 1;
	467	rcnts[1].irq = 0x20;
	468
	469	// rcnt 2.
	470	rcnts[2].rate = 1;
	471	rcnts[2].irq = 0x40;
	472
	473	// rcnt base.
	474	rcnts[3].rate = 1;
	475	rcnts[3].mode = RcCountToTarget;
	476	rcnts[3].target = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
	477
	478	for( i = 0; i < CounterQuantity; ++i )
	479	{
	480	_psxRcntWcount( i, 0 );
	481	}
	482
	483	hSyncCount = 0;
	484	hsync_steps = 1;
	485
	486	psxRcntSet();
	487	}
	488
	489	/******************************************************************************/
	490
	491	s32 psxRcntFreeze( void *f, s32 Mode )
	492	{
	493	u32 spuSyncCount = 0;
	494	u32 count;
	495	s32 i;
	496
	497	gzfreeze( &rcnts, sizeof(rcnts) );
	498	gzfreeze( &hSyncCount, sizeof(hSyncCount) );
	499	gzfreeze( &spuSyncCount, sizeof(spuSyncCount) );
	500	gzfreeze( &psxNextCounter, sizeof(psxNextCounter) );
	501	gzfreeze( &psxNextsCounter, sizeof(psxNextsCounter) );
	502
	503	if (Mode == 0)
	504	{
	505	// don't trust things from a savestate
	506	for( i = 0; i < CounterQuantity; ++i )
	507	{
	508	_psxRcntWmode( i, rcnts[i].mode );
	509	count = (psxRegs.cycle - rcnts[i].cycleStart) / rcnts[i].rate;
	510	_psxRcntWcount( i, count );
	511	}
	512	hsync_steps = (psxRegs.cycle - rcnts[3].cycleStart) / rcnts[3].target;
	513	psxRcntSet();
	514
	515	base_cycle = 0;
	516	}
	517
	518	return 0;
	519	}
	520
	521	/******************************************************************************/