1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - assem_arm.c *
3 * Copyright (C) 2009-2010 Ari64 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
21 extern int cycle_count;
22 extern int last_count;
24 extern int pending_exception;
25 extern int branch_target;
26 extern uint64_t readmem_dword;
28 extern precomp_instr fake_pc;
30 extern void *dynarec_local;
31 extern u_int memory_map[1048576];
32 extern u_int mini_ht[32][2];
33 extern u_int rounding_modes[4];
35 void indirect_jump_indexed();
48 void jump_vaddr_r10();
49 void jump_vaddr_r12();
51 const u_int jump_vaddr_reg[16] = {
71 unsigned int needs_clear_cache[1<<(TARGET_SIZE_2-17)];
75 void set_jump_target(int addr,u_int target)
77 u_char *ptr=(u_char *)addr;
78 u_int *ptr2=(u_int *)ptr;
80 assert((target-(u_int)ptr2-8)<1024);
82 assert((target&3)==0);
83 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>2)|0xF00;
84 //printf("target=%x addr=%x insn=%x\n",target,addr,*ptr2);
86 else if(ptr[3]==0x72) {
87 // generated by emit_jno_unlikely
88 if((target-(u_int)ptr2-8)<1024) {
90 assert((target&3)==0);
91 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>2)|0xF00;
93 else if((target-(u_int)ptr2-8)<4096&&!((target-(u_int)ptr2-8)&15)) {
95 assert((target&3)==0);
96 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>4)|0xE00;
98 else *ptr2=(0x7A000000)|(((target-(u_int)ptr2-8)<<6)>>8);
101 assert((ptr[3]&0x0e)==0xa);
102 *ptr2=(*ptr2&0xFF000000)|(((target-(u_int)ptr2-8)<<6)>>8);
106 // This optionally copies the instruction from the target of the branch into
107 // the space before the branch. Works, but the difference in speed is
108 // usually insignificant.
109 void set_jump_target_fillslot(int addr,u_int target,int copy)
111 u_char *ptr=(u_char *)addr;
112 u_int *ptr2=(u_int *)ptr;
113 assert(!copy||ptr2[-1]==0xe28dd000);
116 assert((target-(u_int)ptr2-8)<4096);
117 *ptr2=(*ptr2&0xFFFFF000)|(target-(u_int)ptr2-8);
120 assert((ptr[3]&0x0e)==0xa);
121 u_int target_insn=*(u_int *)target;
122 if((target_insn&0x0e100000)==0) { // ALU, no immediate, no flags
125 if((target_insn&0x0c100000)==0x04100000) { // Load
128 if(target_insn&0x08000000) {
132 ptr2[-1]=target_insn;
135 *ptr2=(*ptr2&0xFF000000)|(((target-(u_int)ptr2-8)<<6)>>8);
140 add_literal(int addr,int val)
142 literals[literalcount][0]=addr;
143 literals[literalcount][1]=val;
147 void *kill_pointer(void *stub)
149 int *ptr=(int *)(stub+4);
150 assert((*ptr&0x0ff00000)==0x05900000);
151 u_int offset=*ptr&0xfff;
152 int **l_ptr=(void *)ptr+offset+8;
154 set_jump_target((int)i_ptr,(int)stub);
158 int get_pointer(void *stub)
160 //printf("get_pointer(%x)\n",(int)stub);
161 int *ptr=(int *)(stub+4);
162 assert((*ptr&0x0ff00000)==0x05900000);
163 u_int offset=*ptr&0xfff;
164 int **l_ptr=(void *)ptr+offset+8;
166 assert((*i_ptr&0x0f000000)==0x0a000000);
167 return (int)i_ptr+((*i_ptr<<8)>>6)+8;
170 // Find the "clean" entry point from a "dirty" entry point
171 // by skipping past the call to verify_code
172 u_int get_clean_addr(int addr)
174 int *ptr=(int *)addr;
180 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
181 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
183 if((*ptr&0xFF000000)==0xea000000) {
184 return (int)ptr+((*ptr<<8)>>6)+8; // follow jump
189 int verify_dirty(int addr)
191 u_int *ptr=(u_int *)addr;
193 // get from literal pool
194 assert((*ptr&0xFFF00000)==0xe5900000);
195 u_int offset=*ptr&0xfff;
196 u_int *l_ptr=(void *)ptr+offset+8;
197 u_int source=l_ptr[0];
203 assert((*ptr&0xFFF00000)==0xe3000000);
204 u_int source=(ptr[0]&0xFFF)+((ptr[0]>>4)&0xF000)+((ptr[2]<<16)&0xFFF0000)+((ptr[2]<<12)&0xF0000000);
205 u_int copy=(ptr[1]&0xFFF)+((ptr[1]>>4)&0xF000)+((ptr[3]<<16)&0xFFF0000)+((ptr[3]<<12)&0xF0000000);
206 u_int len=(ptr[4]&0xFFF)+((ptr[4]>>4)&0xF000);
209 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
210 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
211 u_int verifier=(int)ptr+((signed int)(*ptr<<8)>>6)+8; // get target of bl
212 if(verifier==(u_int)verify_code_vm||verifier==(u_int)verify_code_ds) {
213 unsigned int page=source>>12;
214 unsigned int map_value=memory_map[page];
215 if(map_value>=0x80000000) return 0;
216 while(page<((source+len-1)>>12)) {
217 if((memory_map[++page]<<2)!=(map_value<<2)) return 0;
219 source = source+(map_value<<2);
221 //printf("verify_dirty: %x %x %x\n",source,copy,len);
222 return !memcmp((void *)source,(void *)copy,len);
225 // This doesn't necessarily find all clean entry points, just
226 // guarantees that it's not dirty
227 int isclean(int addr)
230 int *ptr=((u_int *)addr)+4;
232 int *ptr=((u_int *)addr)+6;
234 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
235 if((*ptr&0xFF000000)!=0xeb000000) return 1; // bl instruction
236 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code) return 0;
237 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code_vm) return 0;
238 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code_ds) return 0;
242 void get_bounds(int addr,u_int *start,u_int *end)
244 u_int *ptr=(u_int *)addr;
246 // get from literal pool
247 assert((*ptr&0xFFF00000)==0xe5900000);
248 u_int offset=*ptr&0xfff;
249 u_int *l_ptr=(void *)ptr+offset+8;
250 u_int source=l_ptr[0];
251 //u_int copy=l_ptr[1];
256 assert((*ptr&0xFFF00000)==0xe3000000);
257 u_int source=(ptr[0]&0xFFF)+((ptr[0]>>4)&0xF000)+((ptr[2]<<16)&0xFFF0000)+((ptr[2]<<12)&0xF0000000);
258 //u_int copy=(ptr[1]&0xFFF)+((ptr[1]>>4)&0xF000)+((ptr[3]<<16)&0xFFF0000)+((ptr[3]<<12)&0xF0000000);
259 u_int len=(ptr[4]&0xFFF)+((ptr[4]>>4)&0xF000);
262 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
263 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
264 u_int verifier=(int)ptr+((signed int)(*ptr<<8)>>6)+8; // get target of bl
265 if(verifier==(u_int)verify_code_vm||verifier==(u_int)verify_code_ds) {
266 if(memory_map[source>>12]>=0x80000000) source = 0;
267 else source = source+(memory_map[source>>12]<<2);
273 /* Register allocation */
275 // Note: registers are allocated clean (unmodified state)
276 // if you intend to modify the register, you must call dirty_reg().
277 void alloc_reg(struct regstat *cur,int i,signed char reg)
280 int preferred_reg = (reg&7);
281 if(reg==CCREG) preferred_reg=HOST_CCREG;
282 if(reg==PTEMP||reg==FTEMP) preferred_reg=12;
284 // Don't allocate unused registers
285 if((cur->u>>reg)&1) return;
287 // see if it's already allocated
288 for(hr=0;hr<HOST_REGS;hr++)
290 if(cur->regmap[hr]==reg) return;
293 // Keep the same mapping if the register was already allocated in a loop
294 preferred_reg = loop_reg(i,reg,preferred_reg);
296 // Try to allocate the preferred register
297 if(cur->regmap[preferred_reg]==-1) {
298 cur->regmap[preferred_reg]=reg;
299 cur->dirty&=~(1<<preferred_reg);
300 cur->isconst&=~(1<<preferred_reg);
303 r=cur->regmap[preferred_reg];
304 if(r<64&&((cur->u>>r)&1)) {
305 cur->regmap[preferred_reg]=reg;
306 cur->dirty&=~(1<<preferred_reg);
307 cur->isconst&=~(1<<preferred_reg);
310 if(r>=64&&((cur->uu>>(r&63))&1)) {
311 cur->regmap[preferred_reg]=reg;
312 cur->dirty&=~(1<<preferred_reg);
313 cur->isconst&=~(1<<preferred_reg);
317 // Clear any unneeded registers
318 // We try to keep the mapping consistent, if possible, because it
319 // makes branches easier (especially loops). So we try to allocate
320 // first (see above) before removing old mappings. If this is not
321 // possible then go ahead and clear out the registers that are no
323 for(hr=0;hr<HOST_REGS;hr++)
328 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
332 if((cur->uu>>(r&63))&1) {cur->regmap[hr]=-1;break;}
336 // Try to allocate any available register, but prefer
337 // registers that have not been used recently.
339 for(hr=0;hr<HOST_REGS;hr++) {
340 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
341 if(regs[i-1].regmap[hr]!=rs1[i-1]&®s[i-1].regmap[hr]!=rs2[i-1]&®s[i-1].regmap[hr]!=rt1[i-1]&®s[i-1].regmap[hr]!=rt2[i-1]) {
343 cur->dirty&=~(1<<hr);
344 cur->isconst&=~(1<<hr);
350 // Try to allocate any available register
351 for(hr=0;hr<HOST_REGS;hr++) {
352 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
354 cur->dirty&=~(1<<hr);
355 cur->isconst&=~(1<<hr);
360 // Ok, now we have to evict someone
361 // Pick a register we hopefully won't need soon
362 u_char hsn[MAXREG+1];
363 memset(hsn,10,sizeof(hsn));
365 lsn(hsn,i,&preferred_reg);
366 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
367 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
369 // Don't evict the cycle count at entry points, otherwise the entry
370 // stub will have to write it.
371 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
372 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
375 // Alloc preferred register if available
376 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
377 for(hr=0;hr<HOST_REGS;hr++) {
378 // Evict both parts of a 64-bit register
379 if((cur->regmap[hr]&63)==r) {
381 cur->dirty&=~(1<<hr);
382 cur->isconst&=~(1<<hr);
385 cur->regmap[preferred_reg]=reg;
388 for(r=1;r<=MAXREG;r++)
390 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
391 for(hr=0;hr<HOST_REGS;hr++) {
392 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
393 if(cur->regmap[hr]==r+64) {
395 cur->dirty&=~(1<<hr);
396 cur->isconst&=~(1<<hr);
401 for(hr=0;hr<HOST_REGS;hr++) {
402 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
403 if(cur->regmap[hr]==r) {
405 cur->dirty&=~(1<<hr);
406 cur->isconst&=~(1<<hr);
417 for(r=1;r<=MAXREG;r++)
420 for(hr=0;hr<HOST_REGS;hr++) {
421 if(cur->regmap[hr]==r+64) {
423 cur->dirty&=~(1<<hr);
424 cur->isconst&=~(1<<hr);
428 for(hr=0;hr<HOST_REGS;hr++) {
429 if(cur->regmap[hr]==r) {
431 cur->dirty&=~(1<<hr);
432 cur->isconst&=~(1<<hr);
439 printf("This shouldn't happen (alloc_reg)");exit(1);
442 void alloc_reg64(struct regstat *cur,int i,signed char reg)
444 int preferred_reg = 8+(reg&1);
447 // allocate the lower 32 bits
448 alloc_reg(cur,i,reg);
450 // Don't allocate unused registers
451 if((cur->uu>>reg)&1) return;
453 // see if the upper half is already allocated
454 for(hr=0;hr<HOST_REGS;hr++)
456 if(cur->regmap[hr]==reg+64) return;
459 // Keep the same mapping if the register was already allocated in a loop
460 preferred_reg = loop_reg(i,reg,preferred_reg);
462 // Try to allocate the preferred register
463 if(cur->regmap[preferred_reg]==-1) {
464 cur->regmap[preferred_reg]=reg|64;
465 cur->dirty&=~(1<<preferred_reg);
466 cur->isconst&=~(1<<preferred_reg);
469 r=cur->regmap[preferred_reg];
470 if(r<64&&((cur->u>>r)&1)) {
471 cur->regmap[preferred_reg]=reg|64;
472 cur->dirty&=~(1<<preferred_reg);
473 cur->isconst&=~(1<<preferred_reg);
476 if(r>=64&&((cur->uu>>(r&63))&1)) {
477 cur->regmap[preferred_reg]=reg|64;
478 cur->dirty&=~(1<<preferred_reg);
479 cur->isconst&=~(1<<preferred_reg);
483 // Clear any unneeded registers
484 // We try to keep the mapping consistent, if possible, because it
485 // makes branches easier (especially loops). So we try to allocate
486 // first (see above) before removing old mappings. If this is not
487 // possible then go ahead and clear out the registers that are no
489 for(hr=HOST_REGS-1;hr>=0;hr--)
494 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
498 if((cur->uu>>(r&63))&1) {cur->regmap[hr]=-1;break;}
502 // Try to allocate any available register, but prefer
503 // registers that have not been used recently.
505 for(hr=0;hr<HOST_REGS;hr++) {
506 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
507 if(regs[i-1].regmap[hr]!=rs1[i-1]&®s[i-1].regmap[hr]!=rs2[i-1]&®s[i-1].regmap[hr]!=rt1[i-1]&®s[i-1].regmap[hr]!=rt2[i-1]) {
508 cur->regmap[hr]=reg|64;
509 cur->dirty&=~(1<<hr);
510 cur->isconst&=~(1<<hr);
516 // Try to allocate any available register
517 for(hr=0;hr<HOST_REGS;hr++) {
518 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
519 cur->regmap[hr]=reg|64;
520 cur->dirty&=~(1<<hr);
521 cur->isconst&=~(1<<hr);
526 // Ok, now we have to evict someone
527 // Pick a register we hopefully won't need soon
528 u_char hsn[MAXREG+1];
529 memset(hsn,10,sizeof(hsn));
531 lsn(hsn,i,&preferred_reg);
532 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
533 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
535 // Don't evict the cycle count at entry points, otherwise the entry
536 // stub will have to write it.
537 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
538 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
541 // Alloc preferred register if available
542 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
543 for(hr=0;hr<HOST_REGS;hr++) {
544 // Evict both parts of a 64-bit register
545 if((cur->regmap[hr]&63)==r) {
547 cur->dirty&=~(1<<hr);
548 cur->isconst&=~(1<<hr);
551 cur->regmap[preferred_reg]=reg|64;
554 for(r=1;r<=MAXREG;r++)
556 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
557 for(hr=0;hr<HOST_REGS;hr++) {
558 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
559 if(cur->regmap[hr]==r+64) {
560 cur->regmap[hr]=reg|64;
561 cur->dirty&=~(1<<hr);
562 cur->isconst&=~(1<<hr);
567 for(hr=0;hr<HOST_REGS;hr++) {
568 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
569 if(cur->regmap[hr]==r) {
570 cur->regmap[hr]=reg|64;
571 cur->dirty&=~(1<<hr);
572 cur->isconst&=~(1<<hr);
583 for(r=1;r<=MAXREG;r++)
586 for(hr=0;hr<HOST_REGS;hr++) {
587 if(cur->regmap[hr]==r+64) {
588 cur->regmap[hr]=reg|64;
589 cur->dirty&=~(1<<hr);
590 cur->isconst&=~(1<<hr);
594 for(hr=0;hr<HOST_REGS;hr++) {
595 if(cur->regmap[hr]==r) {
596 cur->regmap[hr]=reg|64;
597 cur->dirty&=~(1<<hr);
598 cur->isconst&=~(1<<hr);
605 printf("This shouldn't happen");exit(1);
608 // Allocate a temporary register. This is done without regard to
609 // dirty status or whether the register we request is on the unneeded list
610 // Note: This will only allocate one register, even if called multiple times
611 void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
614 int preferred_reg = -1;
616 // see if it's already allocated
617 for(hr=0;hr<HOST_REGS;hr++)
619 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==reg) return;
622 // Try to allocate any available register
623 for(hr=HOST_REGS-1;hr>=0;hr--) {
624 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
626 cur->dirty&=~(1<<hr);
627 cur->isconst&=~(1<<hr);
632 // Find an unneeded register
633 for(hr=HOST_REGS-1;hr>=0;hr--)
639 if(i==0||((unneeded_reg[i-1]>>r)&1)) {
641 cur->dirty&=~(1<<hr);
642 cur->isconst&=~(1<<hr);
649 if((cur->uu>>(r&63))&1) {
650 if(i==0||((unneeded_reg_upper[i-1]>>(r&63))&1)) {
652 cur->dirty&=~(1<<hr);
653 cur->isconst&=~(1<<hr);
661 // Ok, now we have to evict someone
662 // Pick a register we hopefully won't need soon
663 // TODO: we might want to follow unconditional jumps here
664 // TODO: get rid of dupe code and make this into a function
665 u_char hsn[MAXREG+1];
666 memset(hsn,10,sizeof(hsn));
668 lsn(hsn,i,&preferred_reg);
669 //printf("hsn: %d %d %d %d %d %d %d\n",hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
671 // Don't evict the cycle count at entry points, otherwise the entry
672 // stub will have to write it.
673 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
674 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
677 for(r=1;r<=MAXREG;r++)
679 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
680 for(hr=0;hr<HOST_REGS;hr++) {
681 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
682 if(cur->regmap[hr]==r+64) {
684 cur->dirty&=~(1<<hr);
685 cur->isconst&=~(1<<hr);
690 for(hr=0;hr<HOST_REGS;hr++) {
691 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
692 if(cur->regmap[hr]==r) {
694 cur->dirty&=~(1<<hr);
695 cur->isconst&=~(1<<hr);
706 for(r=1;r<=MAXREG;r++)
709 for(hr=0;hr<HOST_REGS;hr++) {
710 if(cur->regmap[hr]==r+64) {
712 cur->dirty&=~(1<<hr);
713 cur->isconst&=~(1<<hr);
717 for(hr=0;hr<HOST_REGS;hr++) {
718 if(cur->regmap[hr]==r) {
720 cur->dirty&=~(1<<hr);
721 cur->isconst&=~(1<<hr);
728 printf("This shouldn't happen");exit(1);
730 // Allocate a specific ARM register.
731 void alloc_arm_reg(struct regstat *cur,int i,signed char reg,char hr)
735 // see if it's already allocated (and dealloc it)
736 for(n=0;n<HOST_REGS;n++)
738 if(n!=EXCLUDE_REG&&cur->regmap[n]==reg) {cur->regmap[n]=-1;}
742 cur->dirty&=~(1<<hr);
743 cur->isconst&=~(1<<hr);
746 // Alloc cycle count into dedicated register
747 alloc_cc(struct regstat *cur,int i)
749 alloc_arm_reg(cur,i,CCREG,HOST_CCREG);
757 char regname[16][4] = {
775 void output_byte(u_char byte)
779 void output_modrm(u_char mod,u_char rm,u_char ext)
784 u_char byte=(mod<<6)|(ext<<3)|rm;
787 void output_sib(u_char scale,u_char index,u_char base)
792 u_char byte=(scale<<6)|(index<<3)|base;
795 void output_w32(u_int word)
797 *((u_int *)out)=word;
800 u_int rd_rn_rm(u_int rd, u_int rn, u_int rm)
805 return((rn<<16)|(rd<<12)|rm);
807 u_int rd_rn_imm_shift(u_int rd, u_int rn, u_int imm, u_int shift)
812 assert((shift&1)==0);
813 return((rn<<16)|(rd<<12)|(((32-shift)&30)<<7)|imm);
815 u_int genimm(u_int imm,u_int *encoded)
817 if(imm==0) {*encoded=0;return 1;}
822 *encoded=((i&30)<<7)|imm;
825 imm=(imm>>2)|(imm<<30);i-=2;
829 void genimm_checked(u_int imm,u_int *encoded)
831 u_int ret=genimm(imm,encoded);
834 u_int genjmp(u_int addr)
836 int offset=addr-(int)out-8;
837 if(offset<-33554432||offset>=33554432) {
839 printf("genjmp: out of range: %08x\n", offset);
844 return ((u_int)offset>>2)&0xffffff;
847 void emit_mov(int rs,int rt)
849 assem_debug("mov %s,%s\n",regname[rt],regname[rs]);
850 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs));
853 void emit_movs(int rs,int rt)
855 assem_debug("movs %s,%s\n",regname[rt],regname[rs]);
856 output_w32(0xe1b00000|rd_rn_rm(rt,0,rs));
859 void emit_add(int rs1,int rs2,int rt)
861 assem_debug("add %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
862 output_w32(0xe0800000|rd_rn_rm(rt,rs1,rs2));
865 void emit_adds(int rs1,int rs2,int rt)
867 assem_debug("adds %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
868 output_w32(0xe0900000|rd_rn_rm(rt,rs1,rs2));
871 void emit_adcs(int rs1,int rs2,int rt)
873 assem_debug("adcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
874 output_w32(0xe0b00000|rd_rn_rm(rt,rs1,rs2));
877 void emit_sbc(int rs1,int rs2,int rt)
879 assem_debug("sbc %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
880 output_w32(0xe0c00000|rd_rn_rm(rt,rs1,rs2));
883 void emit_sbcs(int rs1,int rs2,int rt)
885 assem_debug("sbcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
886 output_w32(0xe0d00000|rd_rn_rm(rt,rs1,rs2));
889 void emit_neg(int rs, int rt)
891 assem_debug("rsb %s,%s,#0\n",regname[rt],regname[rs]);
892 output_w32(0xe2600000|rd_rn_rm(rt,rs,0));
895 void emit_negs(int rs, int rt)
897 assem_debug("rsbs %s,%s,#0\n",regname[rt],regname[rs]);
898 output_w32(0xe2700000|rd_rn_rm(rt,rs,0));
901 void emit_sub(int rs1,int rs2,int rt)
903 assem_debug("sub %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
904 output_w32(0xe0400000|rd_rn_rm(rt,rs1,rs2));
907 void emit_subs(int rs1,int rs2,int rt)
909 assem_debug("subs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
910 output_w32(0xe0500000|rd_rn_rm(rt,rs1,rs2));
913 void emit_zeroreg(int rt)
915 assem_debug("mov %s,#0\n",regname[rt]);
916 output_w32(0xe3a00000|rd_rn_rm(rt,0,0));
919 void emit_loadlp(u_int imm,u_int rt)
921 add_literal((int)out,imm);
922 assem_debug("ldr %s,pc+? [=%x]\n",regname[rt],imm);
923 output_w32(0xe5900000|rd_rn_rm(rt,15,0));
925 void emit_movw(u_int imm,u_int rt)
928 assem_debug("movw %s,#%d (0x%x)\n",regname[rt],imm,imm);
929 output_w32(0xe3000000|rd_rn_rm(rt,0,0)|(imm&0xfff)|((imm<<4)&0xf0000));
931 void emit_movt(u_int imm,u_int rt)
933 assem_debug("movt %s,#%d (0x%x)\n",regname[rt],imm&0xffff0000,imm&0xffff0000);
934 output_w32(0xe3400000|rd_rn_rm(rt,0,0)|((imm>>16)&0xfff)|((imm>>12)&0xf0000));
936 void emit_movimm(u_int imm,u_int rt)
939 if(genimm(imm,&armval)) {
940 assem_debug("mov %s,#%d\n",regname[rt],imm);
941 output_w32(0xe3a00000|rd_rn_rm(rt,0,0)|armval);
942 }else if(genimm(~imm,&armval)) {
943 assem_debug("mvn %s,#%d\n",regname[rt],imm);
944 output_w32(0xe3e00000|rd_rn_rm(rt,0,0)|armval);
945 }else if(imm<65536) {
947 assem_debug("mov %s,#%d\n",regname[rt],imm&0xFF00);
948 output_w32(0xe3a00000|rd_rn_imm_shift(rt,0,imm>>8,8));
949 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF);
950 output_w32(0xe2800000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
958 emit_movw(imm&0x0000FFFF,rt);
959 emit_movt(imm&0xFFFF0000,rt);
963 void emit_pcreladdr(u_int rt)
965 assem_debug("add %s,pc,#?\n",regname[rt]);
966 output_w32(0xe2800000|rd_rn_rm(rt,15,0));
969 void emit_loadreg(int r, int hr)
973 printf("64bit load in 32bit mode!\n");
980 int addr=((int)reg)+((r&63)<<REG_SHIFT)+((r&64)>>4);
981 if((r&63)==HIREG) addr=(int)&hi+((r&64)>>4);
982 if((r&63)==LOREG) addr=(int)&lo+((r&64)>>4);
983 if(r==CCREG) addr=(int)&cycle_count;
984 if(r==CSREG) addr=(int)&Status;
985 if(r==FSREG) addr=(int)&FCR31;
986 if(r==INVCP) addr=(int)&invc_ptr;
987 u_int offset = addr-(u_int)&dynarec_local;
989 assem_debug("ldr %s,fp+%d\n",regname[hr],offset);
990 output_w32(0xe5900000|rd_rn_rm(hr,FP,0)|offset);
993 void emit_storereg(int r, int hr)
997 printf("64bit store in 32bit mode!\n");
1001 int addr=((int)reg)+((r&63)<<REG_SHIFT)+((r&64)>>4);
1002 if((r&63)==HIREG) addr=(int)&hi+((r&64)>>4);
1003 if((r&63)==LOREG) addr=(int)&lo+((r&64)>>4);
1004 if(r==CCREG) addr=(int)&cycle_count;
1005 if(r==FSREG) addr=(int)&FCR31;
1006 u_int offset = addr-(u_int)&dynarec_local;
1007 assert(offset<4096);
1008 assem_debug("str %s,fp+%d\n",regname[hr],offset);
1009 output_w32(0xe5800000|rd_rn_rm(hr,FP,0)|offset);
1012 void emit_test(int rs, int rt)
1014 assem_debug("tst %s,%s\n",regname[rs],regname[rt]);
1015 output_w32(0xe1100000|rd_rn_rm(0,rs,rt));
1018 void emit_testimm(int rs,int imm)
1021 assem_debug("tst %s,$%d\n",regname[rs],imm);
1022 genimm_checked(imm,&armval);
1023 output_w32(0xe3100000|rd_rn_rm(0,rs,0)|armval);
1026 void emit_testeqimm(int rs,int imm)
1029 assem_debug("tsteq %s,$%d\n",regname[rs],imm);
1030 genimm_checked(imm,&armval);
1031 output_w32(0x03100000|rd_rn_rm(0,rs,0)|armval);
1034 void emit_not(int rs,int rt)
1036 assem_debug("mvn %s,%s\n",regname[rt],regname[rs]);
1037 output_w32(0xe1e00000|rd_rn_rm(rt,0,rs));
1040 void emit_mvnmi(int rs,int rt)
1042 assem_debug("mvnmi %s,%s\n",regname[rt],regname[rs]);
1043 output_w32(0x41e00000|rd_rn_rm(rt,0,rs));
1046 void emit_and(u_int rs1,u_int rs2,u_int rt)
1048 assem_debug("and %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1049 output_w32(0xe0000000|rd_rn_rm(rt,rs1,rs2));
1052 void emit_or(u_int rs1,u_int rs2,u_int rt)
1054 assem_debug("orr %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1055 output_w32(0xe1800000|rd_rn_rm(rt,rs1,rs2));
1057 void emit_or_and_set_flags(int rs1,int rs2,int rt)
1059 assem_debug("orrs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1060 output_w32(0xe1900000|rd_rn_rm(rt,rs1,rs2));
1063 void emit_orrshl_imm(u_int rs,u_int imm,u_int rt)
1068 assem_debug("orr %s,%s,%s,lsl #%d\n",regname[rt],regname[rt],regname[rs],imm);
1069 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|(imm<<7));
1072 void emit_orrshr_imm(u_int rs,u_int imm,u_int rt)
1077 assem_debug("orr %s,%s,%s,lsr #%d\n",regname[rt],regname[rt],regname[rs],imm);
1078 output_w32(0xe1800020|rd_rn_rm(rt,rt,rs)|(imm<<7));
1081 void emit_xor(u_int rs1,u_int rs2,u_int rt)
1083 assem_debug("eor %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1084 output_w32(0xe0200000|rd_rn_rm(rt,rs1,rs2));
1087 void emit_addimm(u_int rs,int imm,u_int rt)
1092 assert(imm>-65536&&imm<65536);
1094 if(genimm(imm,&armval)) {
1095 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rs],imm);
1096 output_w32(0xe2800000|rd_rn_rm(rt,rs,0)|armval);
1097 }else if(genimm(-imm,&armval)) {
1098 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rs],imm);
1099 output_w32(0xe2400000|rd_rn_rm(rt,rs,0)|armval);
1101 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rs],(-imm)&0xFF00);
1102 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF);
1103 output_w32(0xe2400000|rd_rn_imm_shift(rt,rs,(-imm)>>8,8));
1104 output_w32(0xe2400000|rd_rn_imm_shift(rt,rt,(-imm)&0xff,0));
1106 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF00);
1107 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF);
1108 output_w32(0xe2800000|rd_rn_imm_shift(rt,rs,imm>>8,8));
1109 output_w32(0xe2800000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1112 else if(rs!=rt) emit_mov(rs,rt);
1115 void emit_addimm_and_set_flags(int imm,int rt)
1117 assert(imm>-65536&&imm<65536);
1119 if(genimm(imm,&armval)) {
1120 assem_debug("adds %s,%s,#%d\n",regname[rt],regname[rt],imm);
1121 output_w32(0xe2900000|rd_rn_rm(rt,rt,0)|armval);
1122 }else if(genimm(-imm,&armval)) {
1123 assem_debug("subs %s,%s,#%d\n",regname[rt],regname[rt],imm);
1124 output_w32(0xe2500000|rd_rn_rm(rt,rt,0)|armval);
1126 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF00);
1127 assem_debug("subs %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF);
1128 output_w32(0xe2400000|rd_rn_imm_shift(rt,rt,(-imm)>>8,8));
1129 output_w32(0xe2500000|rd_rn_imm_shift(rt,rt,(-imm)&0xff,0));
1131 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF00);
1132 assem_debug("adds %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF);
1133 output_w32(0xe2800000|rd_rn_imm_shift(rt,rt,imm>>8,8));
1134 output_w32(0xe2900000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1137 void emit_addimm_no_flags(u_int imm,u_int rt)
1139 emit_addimm(rt,imm,rt);
1142 void emit_addnop(u_int r)
1145 assem_debug("add %s,%s,#0 (nop)\n",regname[r],regname[r]);
1146 output_w32(0xe2800000|rd_rn_rm(r,r,0));
1149 void emit_adcimm(u_int rs,int imm,u_int rt)
1152 genimm_checked(imm,&armval);
1153 assem_debug("adc %s,%s,#%d\n",regname[rt],regname[rs],imm);
1154 output_w32(0xe2a00000|rd_rn_rm(rt,rs,0)|armval);
1156 /*void emit_sbcimm(int imm,u_int rt)
1159 genimm_checked(imm,&armval);
1160 assem_debug("sbc %s,%s,#%d\n",regname[rt],regname[rt],imm);
1161 output_w32(0xe2c00000|rd_rn_rm(rt,rt,0)|armval);
1163 void emit_sbbimm(int imm,u_int rt)
1165 assem_debug("sbb $%d,%%%s\n",imm,regname[rt]);
1167 if(imm<128&&imm>=-128) {
1169 output_modrm(3,rt,3);
1175 output_modrm(3,rt,3);
1179 void emit_rscimm(int rs,int imm,u_int rt)
1183 genimm_checked(imm,&armval);
1184 assem_debug("rsc %s,%s,#%d\n",regname[rt],regname[rs],imm);
1185 output_w32(0xe2e00000|rd_rn_rm(rt,rs,0)|armval);
1188 void emit_addimm64_32(int rsh,int rsl,int imm,int rth,int rtl)
1190 // TODO: if(genimm(imm,&armval)) ...
1192 emit_movimm(imm,HOST_TEMPREG);
1193 emit_adds(HOST_TEMPREG,rsl,rtl);
1194 emit_adcimm(rsh,0,rth);
1197 void emit_sbb(int rs1,int rs2)
1199 assem_debug("sbb %%%s,%%%s\n",regname[rs2],regname[rs1]);
1201 output_modrm(3,rs1,rs2);
1204 void emit_andimm(int rs,int imm,int rt)
1209 }else if(genimm(imm,&armval)) {
1210 assem_debug("and %s,%s,#%d\n",regname[rt],regname[rs],imm);
1211 output_w32(0xe2000000|rd_rn_rm(rt,rs,0)|armval);
1212 }else if(genimm(~imm,&armval)) {
1213 assem_debug("bic %s,%s,#%d\n",regname[rt],regname[rs],imm);
1214 output_w32(0xe3c00000|rd_rn_rm(rt,rs,0)|armval);
1215 }else if(imm==65535) {
1217 assem_debug("bic %s,%s,#FF000000\n",regname[rt],regname[rs]);
1218 output_w32(0xe3c00000|rd_rn_rm(rt,rs,0)|0x4FF);
1219 assem_debug("bic %s,%s,#00FF0000\n",regname[rt],regname[rt]);
1220 output_w32(0xe3c00000|rd_rn_rm(rt,rt,0)|0x8FF);
1222 assem_debug("uxth %s,%s\n",regname[rt],regname[rs]);
1223 output_w32(0xe6ff0070|rd_rn_rm(rt,0,rs));
1226 assert(imm>0&&imm<65535);
1228 assem_debug("mov r14,#%d\n",imm&0xFF00);
1229 output_w32(0xe3a00000|rd_rn_imm_shift(HOST_TEMPREG,0,imm>>8,8));
1230 assem_debug("add r14,r14,#%d\n",imm&0xFF);
1231 output_w32(0xe2800000|rd_rn_imm_shift(HOST_TEMPREG,HOST_TEMPREG,imm&0xff,0));
1233 emit_movw(imm,HOST_TEMPREG);
1235 assem_debug("and %s,%s,r14\n",regname[rt],regname[rs]);
1236 output_w32(0xe0000000|rd_rn_rm(rt,rs,HOST_TEMPREG));
1240 void emit_orimm(int rs,int imm,int rt)
1244 if(rs!=rt) emit_mov(rs,rt);
1245 }else if(genimm(imm,&armval)) {
1246 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1247 output_w32(0xe3800000|rd_rn_rm(rt,rs,0)|armval);
1249 assert(imm>0&&imm<65536);
1250 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF00);
1251 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF);
1252 output_w32(0xe3800000|rd_rn_imm_shift(rt,rs,imm>>8,8));
1253 output_w32(0xe3800000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1257 void emit_xorimm(int rs,int imm,int rt)
1261 if(rs!=rt) emit_mov(rs,rt);
1262 }else if(genimm(imm,&armval)) {
1263 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm);
1264 output_w32(0xe2200000|rd_rn_rm(rt,rs,0)|armval);
1266 assert(imm>0&&imm<65536);
1267 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF00);
1268 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF);
1269 output_w32(0xe2200000|rd_rn_imm_shift(rt,rs,imm>>8,8));
1270 output_w32(0xe2200000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1274 void emit_shlimm(int rs,u_int imm,int rt)
1279 assem_debug("lsl %s,%s,#%d\n",regname[rt],regname[rs],imm);
1280 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1283 void emit_shrimm(int rs,u_int imm,int rt)
1287 assem_debug("lsr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1288 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x20|(imm<<7));
1291 void emit_sarimm(int rs,u_int imm,int rt)
1295 assem_debug("asr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1296 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x40|(imm<<7));
1299 void emit_rorimm(int rs,u_int imm,int rt)
1303 assem_debug("ror %s,%s,#%d\n",regname[rt],regname[rs],imm);
1304 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x60|(imm<<7));
1307 void emit_shldimm(int rs,int rs2,u_int imm,int rt)
1309 assem_debug("shld %%%s,%%%s,%d\n",regname[rt],regname[rs2],imm);
1313 assem_debug("lsl %s,%s,#%d\n",regname[rt],regname[rs],imm);
1314 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1315 assem_debug("orr %s,%s,%s,lsr #%d\n",regname[rt],regname[rt],regname[rs2],32-imm);
1316 output_w32(0xe1800020|rd_rn_rm(rt,rt,rs2)|((32-imm)<<7));
1319 void emit_shrdimm(int rs,int rs2,u_int imm,int rt)
1321 assem_debug("shrd %%%s,%%%s,%d\n",regname[rt],regname[rs2],imm);
1325 assem_debug("lsr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1326 output_w32(0xe1a00020|rd_rn_rm(rt,0,rs)|(imm<<7));
1327 assem_debug("orr %s,%s,%s,lsl #%d\n",regname[rt],regname[rt],regname[rs2],32-imm);
1328 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs2)|((32-imm)<<7));
1331 void emit_signextend16(int rs,int rt)
1334 emit_shlimm(rs,16,rt);
1335 emit_sarimm(rt,16,rt);
1337 assem_debug("sxth %s,%s\n",regname[rt],regname[rs]);
1338 output_w32(0xe6bf0070|rd_rn_rm(rt,0,rs));
1342 void emit_shl(u_int rs,u_int shift,u_int rt)
1348 assem_debug("lsl %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1349 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x10|(shift<<8));
1351 void emit_shr(u_int rs,u_int shift,u_int rt)
1356 assem_debug("lsr %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1357 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x30|(shift<<8));
1359 void emit_sar(u_int rs,u_int shift,u_int rt)
1364 assem_debug("asr %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1365 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x50|(shift<<8));
1367 void emit_shlcl(int r)
1369 assem_debug("shl %%%s,%%cl\n",regname[r]);
1372 void emit_shrcl(int r)
1374 assem_debug("shr %%%s,%%cl\n",regname[r]);
1377 void emit_sarcl(int r)
1379 assem_debug("sar %%%s,%%cl\n",regname[r]);
1383 void emit_shldcl(int r1,int r2)
1385 assem_debug("shld %%%s,%%%s,%%cl\n",regname[r1],regname[r2]);
1388 void emit_shrdcl(int r1,int r2)
1390 assem_debug("shrd %%%s,%%%s,%%cl\n",regname[r1],regname[r2]);
1393 void emit_orrshl(u_int rs,u_int shift,u_int rt)
1398 assem_debug("orr %s,%s,%s,lsl %s\n",regname[rt],regname[rt],regname[rs],regname[shift]);
1399 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|0x10|(shift<<8));
1401 void emit_orrshr(u_int rs,u_int shift,u_int rt)
1406 assem_debug("orr %s,%s,%s,lsr %s\n",regname[rt],regname[rt],regname[rs],regname[shift]);
1407 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|0x30|(shift<<8));
1410 void emit_cmpimm(int rs,int imm)
1413 if(genimm(imm,&armval)) {
1414 assem_debug("cmp %s,$%d\n",regname[rs],imm);
1415 output_w32(0xe3500000|rd_rn_rm(0,rs,0)|armval);
1416 }else if(genimm(-imm,&armval)) {
1417 assem_debug("cmn %s,$%d\n",regname[rs],imm);
1418 output_w32(0xe3700000|rd_rn_rm(0,rs,0)|armval);
1422 emit_movimm(imm,HOST_TEMPREG);
1424 emit_movw(imm,HOST_TEMPREG);
1426 assem_debug("cmp %s,r14\n",regname[rs]);
1427 output_w32(0xe1500000|rd_rn_rm(0,rs,HOST_TEMPREG));
1431 emit_movimm(-imm,HOST_TEMPREG);
1433 emit_movw(-imm,HOST_TEMPREG);
1435 assem_debug("cmn %s,r14\n",regname[rs]);
1436 output_w32(0xe1700000|rd_rn_rm(0,rs,HOST_TEMPREG));
1440 void emit_cmovne(u_int *addr,int rt)
1442 assem_debug("cmovne %x,%%%s",(int)addr,regname[rt]);
1445 void emit_cmovl(u_int *addr,int rt)
1447 assem_debug("cmovl %x,%%%s",(int)addr,regname[rt]);
1450 void emit_cmovs(u_int *addr,int rt)
1452 assem_debug("cmovs %x,%%%s",(int)addr,regname[rt]);
1455 void emit_cmovne_imm(int imm,int rt)
1457 assem_debug("movne %s,#%d\n",regname[rt],imm);
1459 genimm_checked(imm,&armval);
1460 output_w32(0x13a00000|rd_rn_rm(rt,0,0)|armval);
1462 void emit_cmovl_imm(int imm,int rt)
1464 assem_debug("movlt %s,#%d\n",regname[rt],imm);
1466 genimm_checked(imm,&armval);
1467 output_w32(0xb3a00000|rd_rn_rm(rt,0,0)|armval);
1469 void emit_cmovb_imm(int imm,int rt)
1471 assem_debug("movcc %s,#%d\n",regname[rt],imm);
1473 genimm_checked(imm,&armval);
1474 output_w32(0x33a00000|rd_rn_rm(rt,0,0)|armval);
1476 void emit_cmovs_imm(int imm,int rt)
1478 assem_debug("movmi %s,#%d\n",regname[rt],imm);
1480 genimm_checked(imm,&armval);
1481 output_w32(0x43a00000|rd_rn_rm(rt,0,0)|armval);
1483 void emit_cmove_reg(int rs,int rt)
1485 assem_debug("moveq %s,%s\n",regname[rt],regname[rs]);
1486 output_w32(0x01a00000|rd_rn_rm(rt,0,rs));
1488 void emit_cmovne_reg(int rs,int rt)
1490 assem_debug("movne %s,%s\n",regname[rt],regname[rs]);
1491 output_w32(0x11a00000|rd_rn_rm(rt,0,rs));
1493 void emit_cmovl_reg(int rs,int rt)
1495 assem_debug("movlt %s,%s\n",regname[rt],regname[rs]);
1496 output_w32(0xb1a00000|rd_rn_rm(rt,0,rs));
1498 void emit_cmovs_reg(int rs,int rt)
1500 assem_debug("movmi %s,%s\n",regname[rt],regname[rs]);
1501 output_w32(0x41a00000|rd_rn_rm(rt,0,rs));
1504 void emit_slti32(int rs,int imm,int rt)
1506 if(rs!=rt) emit_zeroreg(rt);
1507 emit_cmpimm(rs,imm);
1508 if(rs==rt) emit_movimm(0,rt);
1509 emit_cmovl_imm(1,rt);
1511 void emit_sltiu32(int rs,int imm,int rt)
1513 if(rs!=rt) emit_zeroreg(rt);
1514 emit_cmpimm(rs,imm);
1515 if(rs==rt) emit_movimm(0,rt);
1516 emit_cmovb_imm(1,rt);
1518 void emit_slti64_32(int rsh,int rsl,int imm,int rt)
1521 emit_slti32(rsl,imm,rt);
1525 emit_cmovne_imm(0,rt);
1526 emit_cmovs_imm(1,rt);
1530 emit_cmpimm(rsh,-1);
1531 emit_cmovne_imm(0,rt);
1532 emit_cmovl_imm(1,rt);
1535 void emit_sltiu64_32(int rsh,int rsl,int imm,int rt)
1538 emit_sltiu32(rsl,imm,rt);
1542 emit_cmovne_imm(0,rt);
1546 emit_cmpimm(rsh,-1);
1547 emit_cmovne_imm(1,rt);
1551 void emit_cmp(int rs,int rt)
1553 assem_debug("cmp %s,%s\n",regname[rs],regname[rt]);
1554 output_w32(0xe1500000|rd_rn_rm(0,rs,rt));
1556 void emit_set_gz32(int rs, int rt)
1558 //assem_debug("set_gz32\n");
1561 emit_cmovl_imm(0,rt);
1563 void emit_set_nz32(int rs, int rt)
1565 //assem_debug("set_nz32\n");
1566 if(rs!=rt) emit_movs(rs,rt);
1567 else emit_test(rs,rs);
1568 emit_cmovne_imm(1,rt);
1570 void emit_set_gz64_32(int rsh, int rsl, int rt)
1572 //assem_debug("set_gz64\n");
1573 emit_set_gz32(rsl,rt);
1575 emit_cmovne_imm(1,rt);
1576 emit_cmovs_imm(0,rt);
1578 void emit_set_nz64_32(int rsh, int rsl, int rt)
1580 //assem_debug("set_nz64\n");
1581 emit_or_and_set_flags(rsh,rsl,rt);
1582 emit_cmovne_imm(1,rt);
1584 void emit_set_if_less32(int rs1, int rs2, int rt)
1586 //assem_debug("set if less (%%%s,%%%s),%%%s\n",regname[rs1],regname[rs2],regname[rt]);
1587 if(rs1!=rt&&rs2!=rt) emit_zeroreg(rt);
1589 if(rs1==rt||rs2==rt) emit_movimm(0,rt);
1590 emit_cmovl_imm(1,rt);
1592 void emit_set_if_carry32(int rs1, int rs2, int rt)
1594 //assem_debug("set if carry (%%%s,%%%s),%%%s\n",regname[rs1],regname[rs2],regname[rt]);
1595 if(rs1!=rt&&rs2!=rt) emit_zeroreg(rt);
1597 if(rs1==rt||rs2==rt) emit_movimm(0,rt);
1598 emit_cmovb_imm(1,rt);
1600 void emit_set_if_less64_32(int u1, int l1, int u2, int l2, int rt)
1602 //assem_debug("set if less64 (%%%s,%%%s,%%%s,%%%s),%%%s\n",regname[u1],regname[l1],regname[u2],regname[l2],regname[rt]);
1607 emit_sbcs(u1,u2,HOST_TEMPREG);
1608 emit_cmovl_imm(1,rt);
1610 void emit_set_if_carry64_32(int u1, int l1, int u2, int l2, int rt)
1612 //assem_debug("set if carry64 (%%%s,%%%s,%%%s,%%%s),%%%s\n",regname[u1],regname[l1],regname[u2],regname[l2],regname[rt]);
1617 emit_sbcs(u1,u2,HOST_TEMPREG);
1618 emit_cmovb_imm(1,rt);
1621 void emit_call(int a)
1623 assem_debug("bl %x (%x+%x)\n",a,(int)out,a-(int)out-8);
1624 u_int offset=genjmp(a);
1625 output_w32(0xeb000000|offset);
1627 void emit_jmp(int a)
1629 assem_debug("b %x (%x+%x)\n",a,(int)out,a-(int)out-8);
1630 u_int offset=genjmp(a);
1631 output_w32(0xea000000|offset);
1633 void emit_jne(int a)
1635 assem_debug("bne %x\n",a);
1636 u_int offset=genjmp(a);
1637 output_w32(0x1a000000|offset);
1639 void emit_jeq(int a)
1641 assem_debug("beq %x\n",a);
1642 u_int offset=genjmp(a);
1643 output_w32(0x0a000000|offset);
1647 assem_debug("bmi %x\n",a);
1648 u_int offset=genjmp(a);
1649 output_w32(0x4a000000|offset);
1651 void emit_jns(int a)
1653 assem_debug("bpl %x\n",a);
1654 u_int offset=genjmp(a);
1655 output_w32(0x5a000000|offset);
1659 assem_debug("blt %x\n",a);
1660 u_int offset=genjmp(a);
1661 output_w32(0xba000000|offset);
1663 void emit_jge(int a)
1665 assem_debug("bge %x\n",a);
1666 u_int offset=genjmp(a);
1667 output_w32(0xaa000000|offset);
1669 void emit_jno(int a)
1671 assem_debug("bvc %x\n",a);
1672 u_int offset=genjmp(a);
1673 output_w32(0x7a000000|offset);
1677 assem_debug("bcs %x\n",a);
1678 u_int offset=genjmp(a);
1679 output_w32(0x2a000000|offset);
1681 void emit_jcc(int a)
1683 assem_debug("bcc %x\n",a);
1684 u_int offset=genjmp(a);
1685 output_w32(0x3a000000|offset);
1688 void emit_pushimm(int imm)
1690 assem_debug("push $%x\n",imm);
1695 assem_debug("pusha\n");
1700 assem_debug("popa\n");
1703 void emit_pushreg(u_int r)
1705 assem_debug("push %%%s\n",regname[r]);
1708 void emit_popreg(u_int r)
1710 assem_debug("pop %%%s\n",regname[r]);
1713 void emit_callreg(u_int r)
1715 assem_debug("call *%%%s\n",regname[r]);
1718 void emit_jmpreg(u_int r)
1720 assem_debug("mov pc,%s\n",regname[r]);
1721 output_w32(0xe1a00000|rd_rn_rm(15,0,r));
1724 void emit_readword_indexed(int offset, int rs, int rt)
1726 assert(offset>-4096&&offset<4096);
1727 assem_debug("ldr %s,%s+%d\n",regname[rt],regname[rs],offset);
1729 output_w32(0xe5900000|rd_rn_rm(rt,rs,0)|offset);
1731 output_w32(0xe5100000|rd_rn_rm(rt,rs,0)|(-offset));
1734 void emit_readword_dualindexedx4(int rs1, int rs2, int rt)
1736 assem_debug("ldr %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1737 output_w32(0xe7900000|rd_rn_rm(rt,rs1,rs2)|0x100);
1739 void emit_readword_indexed_tlb(int addr, int rs, int map, int rt)
1741 if(map<0) emit_readword_indexed(addr, rs, rt);
1744 emit_readword_dualindexedx4(rs, map, rt);
1747 void emit_readdword_indexed_tlb(int addr, int rs, int map, int rh, int rl)
1750 if(rh>=0) emit_readword_indexed(addr, rs, rh);
1751 emit_readword_indexed(addr+4, rs, rl);
1754 if(rh>=0) emit_readword_indexed_tlb(addr, rs, map, rh);
1755 emit_addimm(map,1,map);
1756 emit_readword_indexed_tlb(addr, rs, map, rl);
1759 void emit_movsbl_indexed(int offset, int rs, int rt)
1761 assert(offset>-256&&offset<256);
1762 assem_debug("ldrsb %s,%s+%d\n",regname[rt],regname[rs],offset);
1764 output_w32(0xe1d000d0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1766 output_w32(0xe15000d0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1769 void emit_movsbl_indexed_tlb(int addr, int rs, int map, int rt)
1771 if(map<0) emit_movsbl_indexed(addr, rs, rt);
1774 emit_shlimm(map,2,map);
1775 assem_debug("ldrsb %s,%s+%s\n",regname[rt],regname[rs],regname[map]);
1776 output_w32(0xe19000d0|rd_rn_rm(rt,rs,map));
1778 assert(addr>-256&&addr<256);
1779 assem_debug("add %s,%s,%s,lsl #2\n",regname[rt],regname[rs],regname[map]);
1780 output_w32(0xe0800000|rd_rn_rm(rt,rs,map)|(2<<7));
1781 emit_movsbl_indexed(addr, rt, rt);
1785 void emit_movswl_indexed(int offset, int rs, int rt)
1787 assert(offset>-256&&offset<256);
1788 assem_debug("ldrsh %s,%s+%d\n",regname[rt],regname[rs],offset);
1790 output_w32(0xe1d000f0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1792 output_w32(0xe15000f0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1795 void emit_movzbl_indexed(int offset, int rs, int rt)
1797 assert(offset>-4096&&offset<4096);
1798 assem_debug("ldrb %s,%s+%d\n",regname[rt],regname[rs],offset);
1800 output_w32(0xe5d00000|rd_rn_rm(rt,rs,0)|offset);
1802 output_w32(0xe5500000|rd_rn_rm(rt,rs,0)|(-offset));
1805 void emit_movzbl_dualindexedx4(int rs1, int rs2, int rt)
1807 assem_debug("ldrb %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1808 output_w32(0xe7d00000|rd_rn_rm(rt,rs1,rs2)|0x100);
1810 void emit_movzbl_indexed_tlb(int addr, int rs, int map, int rt)
1812 if(map<0) emit_movzbl_indexed(addr, rs, rt);
1815 emit_movzbl_dualindexedx4(rs, map, rt);
1817 emit_addimm(rs,addr,rt);
1818 emit_movzbl_dualindexedx4(rt, map, rt);
1822 void emit_movzwl_indexed(int offset, int rs, int rt)
1824 assert(offset>-256&&offset<256);
1825 assem_debug("ldrh %s,%s+%d\n",regname[rt],regname[rs],offset);
1827 output_w32(0xe1d000b0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1829 output_w32(0xe15000b0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1832 void emit_readword(int addr, int rt)
1834 u_int offset = addr-(u_int)&dynarec_local;
1835 assert(offset<4096);
1836 assem_debug("ldr %s,fp+%d\n",regname[rt],offset);
1837 output_w32(0xe5900000|rd_rn_rm(rt,FP,0)|offset);
1839 void emit_movsbl(int addr, int rt)
1841 u_int offset = addr-(u_int)&dynarec_local;
1843 assem_debug("ldrsb %s,fp+%d\n",regname[rt],offset);
1844 output_w32(0xe1d000d0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1846 void emit_movswl(int addr, int rt)
1848 u_int offset = addr-(u_int)&dynarec_local;
1850 assem_debug("ldrsh %s,fp+%d\n",regname[rt],offset);
1851 output_w32(0xe1d000f0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1853 void emit_movzbl(int addr, int rt)
1855 u_int offset = addr-(u_int)&dynarec_local;
1856 assert(offset<4096);
1857 assem_debug("ldrb %s,fp+%d\n",regname[rt],offset);
1858 output_w32(0xe5d00000|rd_rn_rm(rt,FP,0)|offset);
1860 void emit_movzwl(int addr, int rt)
1862 u_int offset = addr-(u_int)&dynarec_local;
1864 assem_debug("ldrh %s,fp+%d\n",regname[rt],offset);
1865 output_w32(0xe1d000b0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1867 void emit_movzwl_reg(int rs, int rt)
1869 assem_debug("movzwl %%%s,%%%s\n",regname[rs]+1,regname[rt]);
1873 void emit_xchg(int rs, int rt)
1875 assem_debug("xchg %%%s,%%%s\n",regname[rs],regname[rt]);
1878 void emit_writeword_indexed(int rt, int offset, int rs)
1880 assert(offset>-4096&&offset<4096);
1881 assem_debug("str %s,%s+%d\n",regname[rt],regname[rs],offset);
1883 output_w32(0xe5800000|rd_rn_rm(rt,rs,0)|offset);
1885 output_w32(0xe5000000|rd_rn_rm(rt,rs,0)|(-offset));
1888 void emit_writeword_dualindexedx4(int rt, int rs1, int rs2)
1890 assem_debug("str %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1891 output_w32(0xe7800000|rd_rn_rm(rt,rs1,rs2)|0x100);
1893 void emit_writeword_indexed_tlb(int rt, int addr, int rs, int map, int temp)
1895 if(map<0) emit_writeword_indexed(rt, addr, rs);
1898 emit_writeword_dualindexedx4(rt, rs, map);
1901 void emit_writedword_indexed_tlb(int rh, int rl, int addr, int rs, int map, int temp)
1904 if(rh>=0) emit_writeword_indexed(rh, addr, rs);
1905 emit_writeword_indexed(rl, addr+4, rs);
1908 if(temp!=rs) emit_addimm(map,1,temp);
1909 emit_writeword_indexed_tlb(rh, addr, rs, map, temp);
1910 if(temp!=rs) emit_writeword_indexed_tlb(rl, addr, rs, temp, temp);
1912 emit_addimm(rs,4,rs);
1913 emit_writeword_indexed_tlb(rl, addr, rs, map, temp);
1917 void emit_writehword_indexed(int rt, int offset, int rs)
1919 assert(offset>-256&&offset<256);
1920 assem_debug("strh %s,%s+%d\n",regname[rt],regname[rs],offset);
1922 output_w32(0xe1c000b0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1924 output_w32(0xe14000b0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1927 void emit_writebyte_indexed(int rt, int offset, int rs)
1929 assert(offset>-4096&&offset<4096);
1930 assem_debug("strb %s,%s+%d\n",regname[rt],regname[rs],offset);
1932 output_w32(0xe5c00000|rd_rn_rm(rt,rs,0)|offset);
1934 output_w32(0xe5400000|rd_rn_rm(rt,rs,0)|(-offset));
1937 void emit_writebyte_dualindexedx4(int rt, int rs1, int rs2)
1939 assem_debug("strb %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1940 output_w32(0xe7c00000|rd_rn_rm(rt,rs1,rs2)|0x100);
1942 void emit_writebyte_indexed_tlb(int rt, int addr, int rs, int map, int temp)
1944 if(map<0) emit_writebyte_indexed(rt, addr, rs);
1947 emit_writebyte_dualindexedx4(rt, rs, map);
1949 emit_addimm(rs,addr,temp);
1950 emit_writebyte_dualindexedx4(rt, temp, map);
1954 void emit_writeword(int rt, int addr)
1956 u_int offset = addr-(u_int)&dynarec_local;
1957 assert(offset<4096);
1958 assem_debug("str %s,fp+%d\n",regname[rt],offset);
1959 output_w32(0xe5800000|rd_rn_rm(rt,FP,0)|offset);
1961 void emit_writehword(int rt, int addr)
1963 u_int offset = addr-(u_int)&dynarec_local;
1965 assem_debug("strh %s,fp+%d\n",regname[rt],offset);
1966 output_w32(0xe1c000b0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1968 void emit_writebyte(int rt, int addr)
1970 u_int offset = addr-(u_int)&dynarec_local;
1971 assert(offset<4096);
1972 assem_debug("strb %s,fp+%d\n",regname[rt],offset);
1973 output_w32(0xe5c00000|rd_rn_rm(rt,FP,0)|offset);
1975 void emit_writeword_imm(int imm, int addr)
1977 assem_debug("movl $%x,%x\n",imm,addr);
1980 void emit_writebyte_imm(int imm, int addr)
1982 assem_debug("movb $%x,%x\n",imm,addr);
1986 void emit_mul(int rs)
1988 assem_debug("mul %%%s\n",regname[rs]);
1991 void emit_imul(int rs)
1993 assem_debug("imul %%%s\n",regname[rs]);
1996 void emit_umull(u_int rs1, u_int rs2, u_int hi, u_int lo)
1998 assem_debug("umull %s, %s, %s, %s\n",regname[lo],regname[hi],regname[rs1],regname[rs2]);
2003 output_w32(0xe0800090|(hi<<16)|(lo<<12)|(rs2<<8)|rs1);
2005 void emit_smull(u_int rs1, u_int rs2, u_int hi, u_int lo)
2007 assem_debug("smull %s, %s, %s, %s\n",regname[lo],regname[hi],regname[rs1],regname[rs2]);
2012 output_w32(0xe0c00090|(hi<<16)|(lo<<12)|(rs2<<8)|rs1);
2015 void emit_div(int rs)
2017 assem_debug("div %%%s\n",regname[rs]);
2020 void emit_idiv(int rs)
2022 assem_debug("idiv %%%s\n",regname[rs]);
2027 assem_debug("cdq\n");
2031 void emit_clz(int rs,int rt)
2033 assem_debug("clz %s,%s\n",regname[rt],regname[rs]);
2034 output_w32(0xe16f0f10|rd_rn_rm(rt,0,rs));
2037 void emit_subcs(int rs1,int rs2,int rt)
2039 assem_debug("subcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2040 output_w32(0x20400000|rd_rn_rm(rt,rs1,rs2));
2043 void emit_shrcc_imm(int rs,u_int imm,int rt)
2047 assem_debug("lsrcc %s,%s,#%d\n",regname[rt],regname[rs],imm);
2048 output_w32(0x31a00000|rd_rn_rm(rt,0,rs)|0x20|(imm<<7));
2051 void emit_negmi(int rs, int rt)
2053 assem_debug("rsbmi %s,%s,#0\n",regname[rt],regname[rs]);
2054 output_w32(0x42600000|rd_rn_rm(rt,rs,0));
2057 void emit_negsmi(int rs, int rt)
2059 assem_debug("rsbsmi %s,%s,#0\n",regname[rt],regname[rs]);
2060 output_w32(0x42700000|rd_rn_rm(rt,rs,0));
2063 void emit_orreq(u_int rs1,u_int rs2,u_int rt)
2065 assem_debug("orreq %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2066 output_w32(0x01800000|rd_rn_rm(rt,rs1,rs2));
2069 void emit_orrne(u_int rs1,u_int rs2,u_int rt)
2071 assem_debug("orrne %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2072 output_w32(0x11800000|rd_rn_rm(rt,rs1,rs2));
2075 void emit_bic_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2077 assem_debug("bic %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2078 output_w32(0xe1C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2081 void emit_biceq_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2083 assem_debug("biceq %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2084 output_w32(0x01C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2087 void emit_bicne_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2089 assem_debug("bicne %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2090 output_w32(0x11C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2093 void emit_bic_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2095 assem_debug("bic %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2096 output_w32(0xe1C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2099 void emit_biceq_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2101 assem_debug("biceq %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2102 output_w32(0x01C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2105 void emit_bicne_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2107 assem_debug("bicne %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2108 output_w32(0x11C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2111 void emit_teq(int rs, int rt)
2113 assem_debug("teq %s,%s\n",regname[rs],regname[rt]);
2114 output_w32(0xe1300000|rd_rn_rm(0,rs,rt));
2117 void emit_rsbimm(int rs, int imm, int rt)
2120 genimm_checked(imm,&armval);
2121 assem_debug("rsb %s,%s,#%d\n",regname[rt],regname[rs],imm);
2122 output_w32(0xe2600000|rd_rn_rm(rt,rs,0)|armval);
2125 // Load 2 immediates optimizing for small code size
2126 void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
2128 emit_movimm(imm1,rt1);
2130 if(genimm(imm2-imm1,&armval)) {
2131 assem_debug("add %s,%s,#%d\n",regname[rt2],regname[rt1],imm2-imm1);
2132 output_w32(0xe2800000|rd_rn_rm(rt2,rt1,0)|armval);
2133 }else if(genimm(imm1-imm2,&armval)) {
2134 assem_debug("sub %s,%s,#%d\n",regname[rt2],regname[rt1],imm1-imm2);
2135 output_w32(0xe2400000|rd_rn_rm(rt2,rt1,0)|armval);
2137 else emit_movimm(imm2,rt2);
2140 // Conditionally select one of two immediates, optimizing for small code size
2141 // This will only be called if HAVE_CMOV_IMM is defined
2142 void emit_cmov2imm_e_ne_compact(int imm1,int imm2,u_int rt)
2145 if(genimm(imm2-imm1,&armval)) {
2146 emit_movimm(imm1,rt);
2147 assem_debug("addne %s,%s,#%d\n",regname[rt],regname[rt],imm2-imm1);
2148 output_w32(0x12800000|rd_rn_rm(rt,rt,0)|armval);
2149 }else if(genimm(imm1-imm2,&armval)) {
2150 emit_movimm(imm1,rt);
2151 assem_debug("subne %s,%s,#%d\n",regname[rt],regname[rt],imm1-imm2);
2152 output_w32(0x12400000|rd_rn_rm(rt,rt,0)|armval);
2156 emit_movimm(imm1,rt);
2157 add_literal((int)out,imm2);
2158 assem_debug("ldrne %s,pc+? [=%x]\n",regname[rt],imm2);
2159 output_w32(0x15900000|rd_rn_rm(rt,15,0));
2161 emit_movw(imm1&0x0000FFFF,rt);
2162 if((imm1&0xFFFF)!=(imm2&0xFFFF)) {
2163 assem_debug("movwne %s,#%d (0x%x)\n",regname[rt],imm2&0xFFFF,imm2&0xFFFF);
2164 output_w32(0x13000000|rd_rn_rm(rt,0,0)|(imm2&0xfff)|((imm2<<4)&0xf0000));
2166 emit_movt(imm1&0xFFFF0000,rt);
2167 if((imm1&0xFFFF0000)!=(imm2&0xFFFF0000)) {
2168 assem_debug("movtne %s,#%d (0x%x)\n",regname[rt],imm2&0xffff0000,imm2&0xffff0000);
2169 output_w32(0x13400000|rd_rn_rm(rt,0,0)|((imm2>>16)&0xfff)|((imm2>>12)&0xf0000));
2175 // special case for checking invalid_code
2176 void emit_cmpmem_indexedsr12_imm(int addr,int r,int imm)
2181 // special case for checking invalid_code
2182 void emit_cmpmem_indexedsr12_reg(int base,int r,int imm)
2184 assert(imm<128&&imm>=0);
2186 assem_debug("ldrb lr,%s,%s lsr #12\n",regname[base],regname[r]);
2187 output_w32(0xe7d00000|rd_rn_rm(HOST_TEMPREG,base,r)|0x620);
2188 emit_cmpimm(HOST_TEMPREG,imm);
2191 // special case for tlb mapping
2192 void emit_addsr12(int rs1,int rs2,int rt)
2194 assem_debug("add %s,%s,%s lsr #12\n",regname[rt],regname[rs1],regname[rs2]);
2195 output_w32(0xe0800620|rd_rn_rm(rt,rs1,rs2));
2198 // Used to preload hash table entries
2199 void emit_prefetch(void *addr)
2201 assem_debug("prefetch %x\n",(int)addr);
2204 output_modrm(0,5,1);
2205 output_w32((int)addr);
2207 void emit_prefetchreg(int r)
2209 assem_debug("pld %s\n",regname[r]);
2210 output_w32(0xf5d0f000|rd_rn_rm(0,r,0));
2213 // Special case for mini_ht
2214 void emit_ldreq_indexed(int rs, u_int offset, int rt)
2216 assert(offset<4096);
2217 assem_debug("ldreq %s,[%s, #%d]\n",regname[rt],regname[rs],offset);
2218 output_w32(0x05900000|rd_rn_rm(rt,rs,0)|offset);
2221 void emit_flds(int r,int sr)
2223 assem_debug("flds s%d,[%s]\n",sr,regname[r]);
2224 output_w32(0xed900a00|((sr&14)<<11)|((sr&1)<<22)|(r<<16));
2227 void emit_vldr(int r,int vr)
2229 assem_debug("vldr d%d,[%s]\n",vr,regname[r]);
2230 output_w32(0xed900b00|(vr<<12)|(r<<16));
2233 void emit_fsts(int sr,int r)
2235 assem_debug("fsts s%d,[%s]\n",sr,regname[r]);
2236 output_w32(0xed800a00|((sr&14)<<11)|((sr&1)<<22)|(r<<16));
2239 void emit_vstr(int vr,int r)
2241 assem_debug("vstr d%d,[%s]\n",vr,regname[r]);
2242 output_w32(0xed800b00|(vr<<12)|(r<<16));
2245 void emit_ftosizs(int s,int d)
2247 assem_debug("ftosizs s%d,s%d\n",d,s);
2248 output_w32(0xeebd0ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2251 void emit_ftosizd(int s,int d)
2253 assem_debug("ftosizd s%d,d%d\n",d,s);
2254 output_w32(0xeebd0bc0|((d&14)<<11)|((d&1)<<22)|(s&7));
2257 void emit_fsitos(int s,int d)
2259 assem_debug("fsitos s%d,s%d\n",d,s);
2260 output_w32(0xeeb80ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2263 void emit_fsitod(int s,int d)
2265 assem_debug("fsitod d%d,s%d\n",d,s);
2266 output_w32(0xeeb80bc0|((d&7)<<12)|((s&14)>>1)|((s&1)<<5));
2269 void emit_fcvtds(int s,int d)
2271 assem_debug("fcvtds d%d,s%d\n",d,s);
2272 output_w32(0xeeb70ac0|((d&7)<<12)|((s&14)>>1)|((s&1)<<5));
2275 void emit_fcvtsd(int s,int d)
2277 assem_debug("fcvtsd s%d,d%d\n",d,s);
2278 output_w32(0xeeb70bc0|((d&14)<<11)|((d&1)<<22)|(s&7));
2281 void emit_fsqrts(int s,int d)
2283 assem_debug("fsqrts d%d,s%d\n",d,s);
2284 output_w32(0xeeb10ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2287 void emit_fsqrtd(int s,int d)
2289 assem_debug("fsqrtd s%d,d%d\n",d,s);
2290 output_w32(0xeeb10bc0|((d&7)<<12)|(s&7));
2293 void emit_fabss(int s,int d)
2295 assem_debug("fabss d%d,s%d\n",d,s);
2296 output_w32(0xeeb00ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2299 void emit_fabsd(int s,int d)
2301 assem_debug("fabsd s%d,d%d\n",d,s);
2302 output_w32(0xeeb00bc0|((d&7)<<12)|(s&7));
2305 void emit_fnegs(int s,int d)
2307 assem_debug("fnegs d%d,s%d\n",d,s);
2308 output_w32(0xeeb10a40|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2311 void emit_fnegd(int s,int d)
2313 assem_debug("fnegd s%d,d%d\n",d,s);
2314 output_w32(0xeeb10b40|((d&7)<<12)|(s&7));
2317 void emit_fadds(int s1,int s2,int d)
2319 assem_debug("fadds s%d,s%d,s%d\n",d,s1,s2);
2320 output_w32(0xee300a00|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2323 void emit_faddd(int s1,int s2,int d)
2325 assem_debug("faddd d%d,d%d,d%d\n",d,s1,s2);
2326 output_w32(0xee300b00|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2329 void emit_fsubs(int s1,int s2,int d)
2331 assem_debug("fsubs s%d,s%d,s%d\n",d,s1,s2);
2332 output_w32(0xee300a40|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2335 void emit_fsubd(int s1,int s2,int d)
2337 assem_debug("fsubd d%d,d%d,d%d\n",d,s1,s2);
2338 output_w32(0xee300b40|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2341 void emit_fmuls(int s1,int s2,int d)
2343 assem_debug("fmuls s%d,s%d,s%d\n",d,s1,s2);
2344 output_w32(0xee200a00|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2347 void emit_fmuld(int s1,int s2,int d)
2349 assem_debug("fmuld d%d,d%d,d%d\n",d,s1,s2);
2350 output_w32(0xee200b00|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2353 void emit_fdivs(int s1,int s2,int d)
2355 assem_debug("fdivs s%d,s%d,s%d\n",d,s1,s2);
2356 output_w32(0xee800a00|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2359 void emit_fdivd(int s1,int s2,int d)
2361 assem_debug("fdivd d%d,d%d,d%d\n",d,s1,s2);
2362 output_w32(0xee800b00|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2365 void emit_fcmps(int x,int y)
2367 assem_debug("fcmps s14, s15\n");
2368 output_w32(0xeeb47a67);
2371 void emit_fcmpd(int x,int y)
2373 assem_debug("fcmpd d6, d7\n");
2374 output_w32(0xeeb46b47);
2379 assem_debug("fmstat\n");
2380 output_w32(0xeef1fa10);
2383 void emit_bicne_imm(int rs,int imm,int rt)
2386 genimm_checked(imm,&armval);
2387 assem_debug("bicne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2388 output_w32(0x13c00000|rd_rn_rm(rt,rs,0)|armval);
2391 void emit_biccs_imm(int rs,int imm,int rt)
2394 genimm_checked(imm,&armval);
2395 assem_debug("biccs %s,%s,#%d\n",regname[rt],regname[rs],imm);
2396 output_w32(0x23c00000|rd_rn_rm(rt,rs,0)|armval);
2399 void emit_bicvc_imm(int rs,int imm,int rt)
2402 genimm_checked(imm,&armval);
2403 assem_debug("bicvc %s,%s,#%d\n",regname[rt],regname[rs],imm);
2404 output_w32(0x73c00000|rd_rn_rm(rt,rs,0)|armval);
2407 void emit_bichi_imm(int rs,int imm,int rt)
2410 genimm_checked(imm,&armval);
2411 assem_debug("bichi %s,%s,#%d\n",regname[rt],regname[rs],imm);
2412 output_w32(0x83c00000|rd_rn_rm(rt,rs,0)|armval);
2415 void emit_orrvs_imm(int rs,int imm,int rt)
2418 genimm_checked(imm,&armval);
2419 assem_debug("orrvs %s,%s,#%d\n",regname[rt],regname[rs],imm);
2420 output_w32(0x63800000|rd_rn_rm(rt,rs,0)|armval);
2423 void emit_orrne_imm(int rs,int imm,int rt)
2426 genimm_checked(imm,&armval);
2427 assem_debug("orrne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2428 output_w32(0x13800000|rd_rn_rm(rt,rs,0)|armval);
2431 void emit_andne_imm(int rs,int imm,int rt)
2434 genimm_checked(imm,&armval);
2435 assem_debug("andne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2436 output_w32(0x12000000|rd_rn_rm(rt,rs,0)|armval);
2439 void emit_jno_unlikely(int a)
2442 assem_debug("addvc pc,pc,#? (%x)\n",/*a-(int)out-8,*/a);
2443 output_w32(0x72800000|rd_rn_rm(15,15,0));
2446 // Save registers before function call
2447 void save_regs(u_int reglist)
2449 reglist&=0x100f; // only save the caller-save registers, r0-r3, r12
2450 if(!reglist) return;
2451 assem_debug("stmia fp,{");
2452 if(reglist&1) assem_debug("r0, ");
2453 if(reglist&2) assem_debug("r1, ");
2454 if(reglist&4) assem_debug("r2, ");
2455 if(reglist&8) assem_debug("r3, ");
2456 if(reglist&0x1000) assem_debug("r12");
2458 output_w32(0xe88b0000|reglist);
2460 // Restore registers after function call
2461 void restore_regs(u_int reglist)
2463 reglist&=0x100f; // only restore the caller-save registers, r0-r3, r12
2464 if(!reglist) return;
2465 assem_debug("ldmia fp,{");
2466 if(reglist&1) assem_debug("r0, ");
2467 if(reglist&2) assem_debug("r1, ");
2468 if(reglist&4) assem_debug("r2, ");
2469 if(reglist&8) assem_debug("r3, ");
2470 if(reglist&0x1000) assem_debug("r12");
2472 output_w32(0xe89b0000|reglist);
2475 // Write back consts using r14 so we don't disturb the other registers
2476 void wb_consts(signed char i_regmap[],uint64_t i_is32,u_int i_dirty,int i)
2479 for(hr=0;hr<HOST_REGS;hr++) {
2480 if(hr!=EXCLUDE_REG&&i_regmap[hr]>=0&&((i_dirty>>hr)&1)) {
2481 if(((regs[i].isconst>>hr)&1)&&i_regmap[hr]>0) {
2482 if(i_regmap[hr]<64 || !((i_is32>>(i_regmap[hr]&63))&1) ) {
2483 int value=constmap[i][hr];
2485 emit_zeroreg(HOST_TEMPREG);
2488 emit_movimm(value,HOST_TEMPREG);
2490 emit_storereg(i_regmap[hr],HOST_TEMPREG);
2492 if((i_is32>>i_regmap[hr])&1) {
2493 if(value!=-1&&value!=0) emit_sarimm(HOST_TEMPREG,31,HOST_TEMPREG);
2494 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
2503 /* Stubs/epilogue */
2505 void literal_pool(int n)
2507 if(!literalcount) return;
2509 if((int)out-literals[0][0]<4096-n) return;
2513 for(i=0;i<literalcount;i++)
2515 ptr=(u_int *)literals[i][0];
2516 u_int offset=(u_int)out-(u_int)ptr-8;
2517 assert(offset<4096);
2518 assert(!(offset&3));
2520 output_w32(literals[i][1]);
2525 void literal_pool_jumpover(int n)
2527 if(!literalcount) return;
2529 if((int)out-literals[0][0]<4096-n) return;
2534 set_jump_target(jaddr,(int)out);
2537 emit_extjump2(int addr, int target, int linker)
2539 u_char *ptr=(u_char *)addr;
2540 assert((ptr[3]&0x0e)==0xa);
2541 emit_loadlp(target,0);
2542 emit_loadlp(addr,1);
2543 assert(addr>=BASE_ADDR&&addr<(BASE_ADDR+(1<<TARGET_SIZE_2)));
2544 //assert((target>=0x80000000&&target<0x80800000)||(target>0xA4000000&&target<0xA4001000));
2546 #ifdef DEBUG_CYCLE_COUNT
2547 emit_readword((int)&last_count,ECX);
2548 emit_add(HOST_CCREG,ECX,HOST_CCREG);
2549 emit_readword((int)&next_interupt,ECX);
2550 emit_writeword(HOST_CCREG,(int)&Count);
2551 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
2552 emit_writeword(ECX,(int)&last_count);
2558 emit_extjump(int addr, int target)
2560 emit_extjump2(addr, target, (int)dyna_linker);
2562 emit_extjump_ds(int addr, int target)
2564 emit_extjump2(addr, target, (int)dyna_linker_ds);
2569 assem_debug("do_readstub %x\n",start+stubs[n][3]*4);
2571 set_jump_target(stubs[n][1],(int)out);
2572 int type=stubs[n][0];
2575 struct regstat *i_regs=(struct regstat *)stubs[n][5];
2576 u_int reglist=stubs[n][7];
2577 signed char *i_regmap=i_regs->regmap;
2578 int addr=get_reg(i_regmap,AGEN1+(i&1));
2581 if(itype[i]==C1LS||itype[i]==C2LS||itype[i]==LOADLR) {
2582 rth=get_reg(i_regmap,FTEMP|64);
2583 rt=get_reg(i_regmap,FTEMP);
2585 rth=get_reg(i_regmap,rt1[i]|64);
2586 rt=get_reg(i_regmap,rt1[i]);
2590 if(addr<0&&itype[i]!=C1LS&&itype[i]!=C2LS&&itype[i]!=LOADLR) addr=get_reg(i_regmap,-1);
2593 if(type==LOADB_STUB||type==LOADBU_STUB)
2594 ftable=(int)readmemb;
2595 if(type==LOADH_STUB||type==LOADHU_STUB)
2596 ftable=(int)readmemh;
2597 if(type==LOADW_STUB)
2598 ftable=(int)readmem;
2600 if(type==LOADD_STUB)
2601 ftable=(int)readmemd;
2604 emit_writeword(rs,(int)&address);
2607 ds=i_regs!=®s[i];
2608 int real_rs=(itype[i]==LOADLR)?-1:get_reg(i_regmap,rs1[i]);
2609 u_int cmask=ds?-1:(0x100f|~i_regs->wasconst);
2610 if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&0x100f,i);
2611 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty&cmask&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs)));
2612 if(!ds) wb_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&~0x100f,i);
2613 emit_shrimm(rs,16,1);
2614 int cc=get_reg(i_regmap,CCREG);
2616 emit_loadreg(CCREG,2);
2618 emit_movimm(ftable,0);
2619 emit_addimm(cc<0?2:cc,2*stubs[n][6]+2,2);
2620 emit_movimm(start+stubs[n][3]*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
2621 //emit_readword((int)&last_count,temp);
2622 //emit_add(cc,temp,cc);
2623 //emit_writeword(cc,(int)&Count);
2625 emit_call((int)&indirect_jump_indexed);
2627 //emit_readword_dualindexedx4(rs,HOST_TEMPREG,15);
2628 // We really shouldn't need to update the count here,
2629 // but not doing so causes random crashes...
2630 emit_readword((int)&Count,HOST_TEMPREG);
2631 emit_readword((int)&next_interupt,2);
2632 emit_addimm(HOST_TEMPREG,-2*stubs[n][6]-2,HOST_TEMPREG);
2633 emit_writeword(2,(int)&last_count);
2634 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
2636 emit_storereg(CCREG,HOST_TEMPREG);
2639 restore_regs(reglist);
2640 //if((cc=get_reg(regmap,CCREG))>=0) {
2641 // emit_loadreg(CCREG,cc);
2643 if(itype[i]==C1LS||itype[i]==C2LS||(rt>=0&&rt1[i]!=0)) {
2645 if(type==LOADB_STUB)
2646 emit_movsbl((int)&readmem_dword,rt);
2647 if(type==LOADBU_STUB)
2648 emit_movzbl((int)&readmem_dword,rt);
2649 if(type==LOADH_STUB)
2650 emit_movswl((int)&readmem_dword,rt);
2651 if(type==LOADHU_STUB)
2652 emit_movzwl((int)&readmem_dword,rt);
2653 if(type==LOADW_STUB)
2654 emit_readword((int)&readmem_dword,rt);
2655 if(type==LOADD_STUB) {
2656 emit_readword((int)&readmem_dword,rt);
2657 if(rth>=0) emit_readword(((int)&readmem_dword)+4,rth);
2660 emit_jmp(stubs[n][2]); // return address
2663 inline_readstub(int type, int i, u_int addr, signed char regmap[], int target, int adj, u_int reglist)
2665 int rs=get_reg(regmap,target);
2666 int rth=get_reg(regmap,target|64);
2667 int rt=get_reg(regmap,target);
2668 if(rs<0) rs=get_reg(regmap,-1);
2671 if(type==LOADB_STUB||type==LOADBU_STUB)
2672 ftable=(int)readmemb;
2673 if(type==LOADH_STUB||type==LOADHU_STUB)
2674 ftable=(int)readmemh;
2675 if(type==LOADW_STUB)
2676 ftable=(int)readmem;
2678 if(type==LOADD_STUB)
2679 ftable=(int)readmemd;
2683 emit_movimm(addr,rs);
2684 emit_writeword(rs,(int)&address);
2687 //emit_shrimm(rs,16,1);
2688 int cc=get_reg(regmap,CCREG);
2690 emit_loadreg(CCREG,2);
2692 //emit_movimm(ftable,0);
2693 emit_movimm(((u_int *)ftable)[addr>>16],0);
2694 //emit_readword((int)&last_count,12);
2695 emit_addimm(cc<0?2:cc,CLOCK_DIVIDER*(adj+1),2);
2696 if((signed int)addr>=(signed int)0xC0000000) {
2697 // Pagefault address
2698 int ds=regmap!=regs[i].regmap;
2699 emit_movimm(start+i*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
2702 //emit_writeword(2,(int)&Count);
2703 //emit_call(((u_int *)ftable)[addr>>16]);
2704 emit_call((int)&indirect_jump);
2705 // We really shouldn't need to update the count here,
2706 // but not doing so causes random crashes...
2707 emit_readword((int)&Count,HOST_TEMPREG);
2708 emit_readword((int)&next_interupt,2);
2709 emit_addimm(HOST_TEMPREG,-CLOCK_DIVIDER*(adj+1),HOST_TEMPREG);
2710 emit_writeword(2,(int)&last_count);
2711 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
2713 emit_storereg(CCREG,HOST_TEMPREG);
2716 restore_regs(reglist);
2718 if(type==LOADB_STUB)
2719 emit_movsbl((int)&readmem_dword,rt);
2720 if(type==LOADBU_STUB)
2721 emit_movzbl((int)&readmem_dword,rt);
2722 if(type==LOADH_STUB)
2723 emit_movswl((int)&readmem_dword,rt);
2724 if(type==LOADHU_STUB)
2725 emit_movzwl((int)&readmem_dword,rt);
2726 if(type==LOADW_STUB)
2727 emit_readword((int)&readmem_dword,rt);
2728 if(type==LOADD_STUB) {
2729 emit_readword((int)&readmem_dword,rt);
2730 if(rth>=0) emit_readword(((int)&readmem_dword)+4,rth);
2737 assem_debug("do_writestub %x\n",start+stubs[n][3]*4);
2739 set_jump_target(stubs[n][1],(int)out);
2740 int type=stubs[n][0];
2743 struct regstat *i_regs=(struct regstat *)stubs[n][5];
2744 u_int reglist=stubs[n][7];
2745 signed char *i_regmap=i_regs->regmap;
2746 int addr=get_reg(i_regmap,AGEN1+(i&1));
2749 if(itype[i]==C1LS||itype[i]==C2LS) {
2750 rth=get_reg(i_regmap,FTEMP|64);
2751 rt=get_reg(i_regmap,r=FTEMP);
2753 rth=get_reg(i_regmap,rs2[i]|64);
2754 rt=get_reg(i_regmap,r=rs2[i]);
2758 if(addr<0) addr=get_reg(i_regmap,-1);
2761 if(type==STOREB_STUB)
2762 ftable=(int)writememb;
2763 if(type==STOREH_STUB)
2764 ftable=(int)writememh;
2765 if(type==STOREW_STUB)
2766 ftable=(int)writemem;
2768 if(type==STORED_STUB)
2769 ftable=(int)writememd;
2772 emit_writeword(rs,(int)&address);
2773 //emit_shrimm(rs,16,rs);
2774 //emit_movmem_indexedx4(ftable,rs,rs);
2775 if(type==STOREB_STUB)
2776 emit_writebyte(rt,(int)&byte);
2777 if(type==STOREH_STUB)
2778 emit_writehword(rt,(int)&hword);
2779 if(type==STOREW_STUB)
2780 emit_writeword(rt,(int)&word);
2781 if(type==STORED_STUB) {
2783 emit_writeword(rt,(int)&dword);
2784 emit_writeword(r?rth:rt,(int)&dword+4);
2786 printf("STORED_STUB\n");
2791 ds=i_regs!=®s[i];
2792 int real_rs=get_reg(i_regmap,rs1[i]);
2793 u_int cmask=ds?-1:(0x100f|~i_regs->wasconst);
2794 if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&0x100f,i);
2795 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty&cmask&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs)));
2796 if(!ds) wb_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&~0x100f,i);
2797 emit_shrimm(rs,16,1);
2798 int cc=get_reg(i_regmap,CCREG);
2800 emit_loadreg(CCREG,2);
2802 emit_movimm(ftable,0);
2803 emit_addimm(cc<0?2:cc,2*stubs[n][6]+2,2);
2804 emit_movimm(start+stubs[n][3]*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
2805 //emit_readword((int)&last_count,temp);
2806 //emit_addimm(cc,2*stubs[n][5]+2,cc);
2807 //emit_add(cc,temp,cc);
2808 //emit_writeword(cc,(int)&Count);
2809 emit_call((int)&indirect_jump_indexed);
2811 emit_readword((int)&Count,HOST_TEMPREG);
2812 emit_readword((int)&next_interupt,2);
2813 emit_addimm(HOST_TEMPREG,-2*stubs[n][6]-2,HOST_TEMPREG);
2814 emit_writeword(2,(int)&last_count);
2815 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
2817 emit_storereg(CCREG,HOST_TEMPREG);
2820 restore_regs(reglist);
2821 //if((cc=get_reg(regmap,CCREG))>=0) {
2822 // emit_loadreg(CCREG,cc);
2824 emit_jmp(stubs[n][2]); // return address
2827 inline_writestub(int type, int i, u_int addr, signed char regmap[], int target, int adj, u_int reglist)
2829 int rs=get_reg(regmap,-1);
2830 int rth=get_reg(regmap,target|64);
2831 int rt=get_reg(regmap,target);
2835 if(type==STOREB_STUB)
2836 ftable=(int)writememb;
2837 if(type==STOREH_STUB)
2838 ftable=(int)writememh;
2839 if(type==STOREW_STUB)
2840 ftable=(int)writemem;
2842 if(type==STORED_STUB)
2843 ftable=(int)writememd;
2846 emit_writeword(rs,(int)&address);
2847 //emit_shrimm(rs,16,rs);
2848 //emit_movmem_indexedx4(ftable,rs,rs);
2849 if(type==STOREB_STUB)
2850 emit_writebyte(rt,(int)&byte);
2851 if(type==STOREH_STUB)
2852 emit_writehword(rt,(int)&hword);
2853 if(type==STOREW_STUB)
2854 emit_writeword(rt,(int)&word);
2855 if(type==STORED_STUB) {
2857 emit_writeword(rt,(int)&dword);
2858 emit_writeword(target?rth:rt,(int)&dword+4);
2860 printf("STORED_STUB\n");
2865 //emit_shrimm(rs,16,1);
2866 int cc=get_reg(regmap,CCREG);
2868 emit_loadreg(CCREG,2);
2870 //emit_movimm(ftable,0);
2871 emit_movimm(((u_int *)ftable)[addr>>16],0);
2872 //emit_readword((int)&last_count,12);
2873 emit_addimm(cc<0?2:cc,CLOCK_DIVIDER*(adj+1),2);
2874 if((signed int)addr>=(signed int)0xC0000000) {
2875 // Pagefault address
2876 int ds=regmap!=regs[i].regmap;
2877 emit_movimm(start+i*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
2880 //emit_writeword(2,(int)&Count);
2881 //emit_call(((u_int *)ftable)[addr>>16]);
2882 emit_call((int)&indirect_jump);
2883 emit_readword((int)&Count,HOST_TEMPREG);
2884 emit_readword((int)&next_interupt,2);
2885 emit_addimm(HOST_TEMPREG,-CLOCK_DIVIDER*(adj+1),HOST_TEMPREG);
2886 emit_writeword(2,(int)&last_count);
2887 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
2889 emit_storereg(CCREG,HOST_TEMPREG);
2892 restore_regs(reglist);
2895 do_unalignedwritestub(int n)
2897 assem_debug("do_unalignedwritestub %x\n",start+stubs[n][3]*4);
2899 set_jump_target(stubs[n][1],(int)out);
2902 struct regstat *i_regs=(struct regstat *)stubs[n][4];
2903 int addr=stubs[n][5];
2904 u_int reglist=stubs[n][7];
2905 signed char *i_regmap=i_regs->regmap;
2906 int temp2=get_reg(i_regmap,FTEMP);
2909 rt=get_reg(i_regmap,rs2[i]);
2912 assert(opcode[i]==0x2a||opcode[i]==0x2e); // SWL/SWR only implemented
2914 reglist&=~(1<<temp2);
2916 emit_andimm(addr,0xfffffffc,temp2);
2917 emit_writeword(temp2,(int)&address);
2920 ds=i_regs!=®s[i];
2921 real_rs=get_reg(i_regmap,rs1[i]);
2922 u_int cmask=ds?-1:(0x100f|~i_regs->wasconst);
2923 if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&0x100f,i);
2924 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty&cmask&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs)));
2925 if(!ds) wb_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&~0x100f,i);
2926 emit_shrimm(addr,16,1);
2927 int cc=get_reg(i_regmap,CCREG);
2929 emit_loadreg(CCREG,2);
2931 emit_movimm((u_int)readmem,0);
2932 emit_addimm(cc<0?2:cc,2*stubs[n][6]+2,2);
2933 emit_movimm(start+stubs[n][3]*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3); // XXX: can be rm'd?
2934 emit_call((int)&indirect_jump_indexed);
2935 restore_regs(reglist);
2937 emit_readword((int)&readmem_dword,temp2);
2938 int temp=addr; //hmh
2939 emit_shlimm(addr,3,temp);
2940 emit_andimm(temp,24,temp);
2941 #ifdef BIG_ENDIAN_MIPS
2942 if (opcode[i]==0x2e) // SWR
2944 if (opcode[i]==0x2a) // SWL
2946 emit_xorimm(temp,24,temp);
2947 emit_movimm(-1,HOST_TEMPREG);
2948 if (opcode[i]==0x2a) { // SWL
2949 emit_bic_lsr(temp2,HOST_TEMPREG,temp,temp2);
2950 emit_orrshr(rt,temp,temp2);
2952 emit_bic_lsl(temp2,HOST_TEMPREG,temp,temp2);
2953 emit_orrshl(rt,temp,temp2);
2955 emit_readword((int)&address,addr);
2956 emit_writeword(temp2,(int)&word);
2957 //save_regs(reglist); // don't need to, no state changes
2958 emit_shrimm(addr,16,1);
2959 emit_movimm((u_int)writemem,0);
2960 //emit_call((int)&indirect_jump_indexed);
2962 emit_readword_dualindexedx4(0,1,15);
2963 emit_readword((int)&Count,HOST_TEMPREG);
2964 emit_readword((int)&next_interupt,2);
2965 emit_addimm(HOST_TEMPREG,-2*stubs[n][6]-2,HOST_TEMPREG);
2966 emit_writeword(2,(int)&last_count);
2967 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
2969 emit_storereg(CCREG,HOST_TEMPREG);
2971 restore_regs(reglist);
2972 emit_jmp(stubs[n][2]); // return address
2975 void printregs(int edi,int esi,int ebp,int esp,int b,int d,int c,int a)
2977 printf("regs: %x %x %x %x %x %x %x (%x)\n",a,b,c,d,ebp,esi,edi,(&edi)[-1]);
2983 u_int reglist=stubs[n][3];
2984 set_jump_target(stubs[n][1],(int)out);
2986 if(stubs[n][4]!=0) emit_mov(stubs[n][4],0);
2987 emit_call((int)&invalidate_addr);
2988 restore_regs(reglist);
2989 emit_jmp(stubs[n][2]); // return address
2992 int do_dirty_stub(int i)
2994 assem_debug("do_dirty_stub %x\n",start+i*4);
2995 u_int addr=(int)start<(int)0xC0000000?(u_int)source:(u_int)start;
2999 // Careful about the code output here, verify_dirty needs to parse it.
3001 emit_loadlp(addr,1);
3002 emit_loadlp((int)copy,2);
3003 emit_loadlp(slen*4,3);
3005 emit_movw(addr&0x0000FFFF,1);
3006 emit_movw(((u_int)copy)&0x0000FFFF,2);
3007 emit_movt(addr&0xFFFF0000,1);
3008 emit_movt(((u_int)copy)&0xFFFF0000,2);
3009 emit_movw(slen*4,3);
3011 emit_movimm(start+i*4,0);
3012 emit_call((int)start<(int)0xC0000000?(int)&verify_code:(int)&verify_code_vm);
3015 if(entry==(int)out) entry=instr_addr[i];
3016 emit_jmp(instr_addr[i]);
3020 void do_dirty_stub_ds()
3022 // Careful about the code output here, verify_dirty needs to parse it.
3024 emit_loadlp((int)start<(int)0xC0000000?(int)source:(int)start,1);
3025 emit_loadlp((int)copy,2);
3026 emit_loadlp(slen*4,3);
3028 emit_movw(((int)start<(int)0xC0000000?(u_int)source:(u_int)start)&0x0000FFFF,1);
3029 emit_movw(((u_int)copy)&0x0000FFFF,2);
3030 emit_movt(((int)start<(int)0xC0000000?(u_int)source:(u_int)start)&0xFFFF0000,1);
3031 emit_movt(((u_int)copy)&0xFFFF0000,2);
3032 emit_movw(slen*4,3);
3034 emit_movimm(start+1,0);
3035 emit_call((int)&verify_code_ds);
3041 assem_debug("do_cop1stub %x\n",start+stubs[n][3]*4);
3042 set_jump_target(stubs[n][1],(int)out);
3044 // int rs=stubs[n][4];
3045 struct regstat *i_regs=(struct regstat *)stubs[n][5];
3048 load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
3049 //if(i_regs!=®s[i]) printf("oops: regs[i]=%x i_regs=%x",(int)®s[i],(int)i_regs);
3051 //else {printf("fp exception in delay slot\n");}
3052 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty);
3053 if(regs[i].regmap_entry[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
3054 emit_movimm(start+(i-ds)*4,EAX); // Get PC
3055 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
3056 emit_jmp(ds?(int)fp_exception_ds:(int)fp_exception);
3061 int do_tlb_r(int s,int ar,int map,int x,int a,int shift,int c,u_int addr)
3064 if((signed int)addr>=(signed int)0xC0000000) {
3065 // address_generation already loaded the const
3066 emit_readword_dualindexedx4(FP,map,map);
3069 return -1; // No mapping
3073 emit_movimm(((int)memory_map-(int)&dynarec_local)>>2,map);
3074 emit_addsr12(map,s,map);
3075 // Schedule this while we wait on the load
3076 //if(x) emit_xorimm(s,x,ar);
3077 if(shift>=0) emit_shlimm(s,3,shift);
3078 if(~a) emit_andimm(s,a,ar);
3079 emit_readword_dualindexedx4(FP,map,map);
3083 int do_tlb_r_branch(int map, int c, u_int addr, int *jaddr)
3085 if(!c||(signed int)addr>=(signed int)0xC0000000) {
3093 int gen_tlb_addr_r(int ar, int map) {
3095 assem_debug("add %s,%s,%s lsl #2\n",regname[ar],regname[ar],regname[map]);
3096 output_w32(0xe0800100|rd_rn_rm(ar,ar,map));
3100 int do_tlb_w(int s,int ar,int map,int x,int c,u_int addr)
3103 if(addr<0x80800000||addr>=0xC0000000) {
3104 // address_generation already loaded the const
3105 emit_readword_dualindexedx4(FP,map,map);
3108 return -1; // No mapping
3112 emit_movimm(((int)memory_map-(int)&dynarec_local)>>2,map);
3113 emit_addsr12(map,s,map);
3114 // Schedule this while we wait on the load
3115 //if(x) emit_xorimm(s,x,ar);
3116 emit_readword_dualindexedx4(FP,map,map);
3120 int do_tlb_w_branch(int map, int c, u_int addr, int *jaddr)
3122 if(!c||addr<0x80800000||addr>=0xC0000000) {
3123 emit_testimm(map,0x40000000);
3129 int gen_tlb_addr_w(int ar, int map) {
3131 assem_debug("add %s,%s,%s lsl #2\n",regname[ar],regname[ar],regname[map]);
3132 output_w32(0xe0800100|rd_rn_rm(ar,ar,map));
3136 // Generate the address of the memory_map entry, relative to dynarec_local
3137 generate_map_const(u_int addr,int reg) {
3138 //printf("generate_map_const(%x,%s)\n",addr,regname[reg]);
3139 emit_movimm((addr>>12)+(((u_int)memory_map-(u_int)&dynarec_local)>>2),reg);
3144 void shift_assemble_arm(int i,struct regstat *i_regs)
3147 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
3149 signed char s,t,shift;
3150 t=get_reg(i_regs->regmap,rt1[i]);
3151 s=get_reg(i_regs->regmap,rs1[i]);
3152 shift=get_reg(i_regs->regmap,rs2[i]);
3161 if(s!=t) emit_mov(s,t);
3165 emit_andimm(shift,31,HOST_TEMPREG);
3166 if(opcode2[i]==4) // SLLV
3168 emit_shl(s,HOST_TEMPREG,t);
3170 if(opcode2[i]==6) // SRLV
3172 emit_shr(s,HOST_TEMPREG,t);
3174 if(opcode2[i]==7) // SRAV
3176 emit_sar(s,HOST_TEMPREG,t);
3180 } else { // DSLLV/DSRLV/DSRAV
3181 signed char sh,sl,th,tl,shift;
3182 th=get_reg(i_regs->regmap,rt1[i]|64);
3183 tl=get_reg(i_regs->regmap,rt1[i]);
3184 sh=get_reg(i_regs->regmap,rs1[i]|64);
3185 sl=get_reg(i_regs->regmap,rs1[i]);
3186 shift=get_reg(i_regs->regmap,rs2[i]);
3191 if(th>=0) emit_zeroreg(th);
3196 if(sl!=tl) emit_mov(sl,tl);
3197 if(th>=0&&sh!=th) emit_mov(sh,th);
3201 // FIXME: What if shift==tl ?
3203 int temp=get_reg(i_regs->regmap,-1);
3205 if(th<0&&opcode2[i]!=0x14) {th=temp;} // DSLLV doesn't need a temporary register
3208 emit_andimm(shift,31,HOST_TEMPREG);
3209 if(opcode2[i]==0x14) // DSLLV
3211 if(th>=0) emit_shl(sh,HOST_TEMPREG,th);
3212 emit_rsbimm(HOST_TEMPREG,32,HOST_TEMPREG);
3213 emit_orrshr(sl,HOST_TEMPREG,th);
3214 emit_andimm(shift,31,HOST_TEMPREG);
3215 emit_testimm(shift,32);
3216 emit_shl(sl,HOST_TEMPREG,tl);
3217 if(th>=0) emit_cmovne_reg(tl,th);
3218 emit_cmovne_imm(0,tl);
3220 if(opcode2[i]==0x16) // DSRLV
3223 emit_shr(sl,HOST_TEMPREG,tl);
3224 emit_rsbimm(HOST_TEMPREG,32,HOST_TEMPREG);
3225 emit_orrshl(sh,HOST_TEMPREG,tl);
3226 emit_andimm(shift,31,HOST_TEMPREG);
3227 emit_testimm(shift,32);
3228 emit_shr(sh,HOST_TEMPREG,th);
3229 emit_cmovne_reg(th,tl);
3230 if(real_th>=0) emit_cmovne_imm(0,th);
3232 if(opcode2[i]==0x17) // DSRAV
3235 emit_shr(sl,HOST_TEMPREG,tl);
3236 emit_rsbimm(HOST_TEMPREG,32,HOST_TEMPREG);
3239 emit_sarimm(th,31,temp);
3241 emit_orrshl(sh,HOST_TEMPREG,tl);
3242 emit_andimm(shift,31,HOST_TEMPREG);
3243 emit_testimm(shift,32);
3244 emit_sar(sh,HOST_TEMPREG,th);
3245 emit_cmovne_reg(th,tl);
3246 if(real_th>=0) emit_cmovne_reg(temp,th);
3253 #define shift_assemble shift_assemble_arm
3255 void loadlr_assemble_arm(int i,struct regstat *i_regs)
3257 int s,th,tl,temp,temp2,addr,map=-1;
3262 th=get_reg(i_regs->regmap,rt1[i]|64);
3263 tl=get_reg(i_regs->regmap,rt1[i]);
3264 s=get_reg(i_regs->regmap,rs1[i]);
3265 temp=get_reg(i_regs->regmap,-1);
3266 temp2=get_reg(i_regs->regmap,FTEMP);
3267 addr=get_reg(i_regs->regmap,AGEN1+(i&1));
3270 for(hr=0;hr<HOST_REGS;hr++) {
3271 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3274 if(offset||s<0||c) addr=temp2;
3277 c=(i_regs->wasconst>>s)&1;
3278 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3279 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3284 map=get_reg(i_regs->regmap,ROREG);
3285 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3287 emit_shlimm(addr,3,temp);
3288 if (opcode[i]==0x22||opcode[i]==0x26) {
3289 emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR
3291 emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR
3293 emit_cmpimm(addr,RAM_SIZE);
3298 if (opcode[i]==0x22||opcode[i]==0x26) {
3299 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
3301 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
3308 }else if (opcode[i]==0x22||opcode[i]==0x26) {
3309 a=0xFFFFFFFC; // LWL/LWR
3311 a=0xFFFFFFF8; // LDL/LDR
3313 map=get_reg(i_regs->regmap,TLREG);
3315 map=do_tlb_r(addr,temp2,map,0,a,c?-1:temp,c,constmap[i][s]+offset);
3317 if (opcode[i]==0x22||opcode[i]==0x26) {
3318 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
3320 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
3323 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
3325 if (opcode[i]==0x22||opcode[i]==0x26) { // LWL/LWR
3327 //emit_readword_indexed((int)rdram-0x80000000,temp2,temp2);
3328 emit_readword_indexed_tlb(0,temp2,map,temp2);
3329 if(jaddr) add_stub(LOADW_STUB,jaddr,(int)out,i,temp2,(int)i_regs,ccadj[i],reglist);
3332 inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj[i],reglist);
3335 emit_andimm(temp,24,temp);
3336 #ifdef BIG_ENDIAN_MIPS
3337 if (opcode[i]==0x26) // LWR
3339 if (opcode[i]==0x22) // LWL
3341 emit_xorimm(temp,24,temp);
3342 emit_movimm(-1,HOST_TEMPREG);
3343 if (opcode[i]==0x26) {
3344 emit_shr(temp2,temp,temp2);
3345 emit_bic_lsr(tl,HOST_TEMPREG,temp,tl);
3347 emit_shl(temp2,temp,temp2);
3348 emit_bic_lsl(tl,HOST_TEMPREG,temp,tl);
3350 emit_or(temp2,tl,tl);
3352 //emit_storereg(rt1[i],tl); // DEBUG
3354 if (opcode[i]==0x1A||opcode[i]==0x1B) { // LDL/LDR
3355 // FIXME: little endian
3356 int temp2h=get_reg(i_regs->regmap,FTEMP|64);
3358 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,temp2,temp2h);
3359 //emit_readword_indexed((int)rdram-0x7FFFFFFC,temp2,temp2);
3360 emit_readdword_indexed_tlb(0,temp2,map,temp2h,temp2);
3361 if(jaddr) add_stub(LOADD_STUB,jaddr,(int)out,i,temp2,(int)i_regs,ccadj[i],reglist);
3364 inline_readstub(LOADD_STUB,i,(constmap[i][s]+offset)&0xFFFFFFF8,i_regs->regmap,FTEMP,ccadj[i],reglist);
3368 emit_testimm(temp,32);
3369 emit_andimm(temp,24,temp);
3370 if (opcode[i]==0x1A) { // LDL
3371 emit_rsbimm(temp,32,HOST_TEMPREG);
3372 emit_shl(temp2h,temp,temp2h);
3373 emit_orrshr(temp2,HOST_TEMPREG,temp2h);
3374 emit_movimm(-1,HOST_TEMPREG);
3375 emit_shl(temp2,temp,temp2);
3376 emit_cmove_reg(temp2h,th);
3377 emit_biceq_lsl(tl,HOST_TEMPREG,temp,tl);
3378 emit_bicne_lsl(th,HOST_TEMPREG,temp,th);
3379 emit_orreq(temp2,tl,tl);
3380 emit_orrne(temp2,th,th);
3382 if (opcode[i]==0x1B) { // LDR
3383 emit_xorimm(temp,24,temp);
3384 emit_rsbimm(temp,32,HOST_TEMPREG);
3385 emit_shr(temp2,temp,temp2);
3386 emit_orrshl(temp2h,HOST_TEMPREG,temp2);
3387 emit_movimm(-1,HOST_TEMPREG);
3388 emit_shr(temp2h,temp,temp2h);
3389 emit_cmovne_reg(temp2,tl);
3390 emit_bicne_lsr(th,HOST_TEMPREG,temp,th);
3391 emit_biceq_lsr(tl,HOST_TEMPREG,temp,tl);
3392 emit_orrne(temp2h,th,th);
3393 emit_orreq(temp2h,tl,tl);
3398 #define loadlr_assemble loadlr_assemble_arm
3400 void cop0_assemble(int i,struct regstat *i_regs)
3402 if(opcode2[i]==0) // MFC0
3404 signed char t=get_reg(i_regs->regmap,rt1[i]);
3405 char copr=(source[i]>>11)&0x1f;
3406 //assert(t>=0); // Why does this happen? OOT is weird
3407 if(t>=0&&rt1[i]!=0) {
3409 emit_addimm(FP,(int)&fake_pc-(int)&dynarec_local,0);
3410 emit_movimm((source[i]>>11)&0x1f,1);
3411 emit_writeword(0,(int)&PC);
3412 emit_writebyte(1,(int)&(fake_pc.f.r.nrd));
3414 emit_readword((int)&last_count,ECX);
3415 emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
3416 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3417 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3418 emit_writeword(HOST_CCREG,(int)&Count);
3420 emit_call((int)MFC0);
3421 emit_readword((int)&readmem_dword,t);
3423 emit_readword((int)®_cop0+copr*4,t);
3427 else if(opcode2[i]==4) // MTC0
3429 signed char s=get_reg(i_regs->regmap,rs1[i]);
3430 char copr=(source[i]>>11)&0x1f;
3432 emit_writeword(s,(int)&readmem_dword);
3433 wb_register(rs1[i],i_regs->regmap,i_regs->dirty,i_regs->is32);
3435 emit_addimm(FP,(int)&fake_pc-(int)&dynarec_local,0);
3436 emit_movimm((source[i]>>11)&0x1f,1);
3437 emit_writeword(0,(int)&PC);
3438 emit_writebyte(1,(int)&(fake_pc.f.r.nrd));
3440 if(copr==9||copr==11||copr==12||copr==13) {
3441 emit_readword((int)&last_count,ECX);
3442 emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
3443 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3444 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3445 emit_writeword(HOST_CCREG,(int)&Count);
3447 // What a mess. The status register (12) can enable interrupts,
3448 // so needs a special case to handle a pending interrupt.
3449 // The interrupt must be taken immediately, because a subsequent
3450 // instruction might disable interrupts again.
3451 if(copr==12||copr==13) {
3454 // burn cycles to cause cc_interrupt, which will
3455 // reschedule next_interupt. Relies on CCREG from above.
3456 assem_debug("MTC0 DS %d\n", copr);
3457 emit_writeword(HOST_CCREG,(int)&last_count);
3458 emit_movimm(0,HOST_CCREG);
3459 emit_storereg(CCREG,HOST_CCREG);
3460 emit_movimm(copr,0);
3461 emit_call((int)pcsx_mtc0_ds);
3465 emit_movimm(start+i*4+4,0);
3467 emit_writeword(0,(int)&pcaddr);
3468 emit_writeword(1,(int)&pending_exception);
3470 //else if(copr==12&&is_delayslot) emit_call((int)MTC0_R12);
3473 emit_movimm(copr,0);
3474 emit_call((int)pcsx_mtc0);
3476 emit_call((int)MTC0);
3478 if(copr==9||copr==11||copr==12||copr==13) {
3479 emit_readword((int)&Count,HOST_CCREG);
3480 emit_readword((int)&next_interupt,ECX);
3481 emit_addimm(HOST_CCREG,-CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3482 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
3483 emit_writeword(ECX,(int)&last_count);
3484 emit_storereg(CCREG,HOST_CCREG);
3486 if(copr==12||copr==13) {
3487 assert(!is_delayslot);
3488 emit_readword((int)&pending_exception,14);
3490 emit_loadreg(rs1[i],s);
3491 if(get_reg(i_regs->regmap,rs1[i]|64)>=0)
3492 emit_loadreg(rs1[i]|64,get_reg(i_regs->regmap,rs1[i]|64));
3493 if(copr==12||copr==13) {
3495 emit_jne((int)&do_interrupt);
3501 assert(opcode2[i]==0x10);
3503 if((source[i]&0x3f)==0x01) // TLBR
3504 emit_call((int)TLBR);
3505 if((source[i]&0x3f)==0x02) // TLBWI
3506 emit_call((int)TLBWI_new);
3507 if((source[i]&0x3f)==0x06) { // TLBWR
3508 // The TLB entry written by TLBWR is dependent on the count,
3509 // so update the cycle count
3510 emit_readword((int)&last_count,ECX);
3511 if(i_regs->regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
3512 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3513 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3514 emit_writeword(HOST_CCREG,(int)&Count);
3515 emit_call((int)TLBWR_new);
3517 if((source[i]&0x3f)==0x08) // TLBP
3518 emit_call((int)TLBP);
3521 if((source[i]&0x3f)==0x10) // RFE
3523 emit_readword((int)&Status,0);
3524 emit_andimm(0,0x3c,1);
3525 emit_andimm(0,~0xf,0);
3526 emit_orrshr_imm(1,2,0);
3527 emit_writeword(0,(int)&Status);
3530 if((source[i]&0x3f)==0x18) // ERET
3533 if(i_regs->regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
3534 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*count,HOST_CCREG); // TODO: Should there be an extra cycle here?
3535 emit_jmp((int)jump_eret);
3541 static void cop2_get_dreg(u_int copr,signed char tl,signed char temp)
3551 emit_readword((int)®_cop2d[copr],tl);
3552 emit_signextend16(tl,tl);
3553 emit_writeword(tl,(int)®_cop2d[copr]); // hmh
3560 emit_readword((int)®_cop2d[copr],tl);
3561 emit_andimm(tl,0xffff,tl);
3562 emit_writeword(tl,(int)®_cop2d[copr]);
3565 emit_readword((int)®_cop2d[14],tl); // SXY2
3566 emit_writeword(tl,(int)®_cop2d[copr]);
3570 emit_readword((int)®_cop2d[9],temp);
3571 emit_testimm(temp,0x8000); // do we need this?
3572 emit_andimm(temp,0xf80,temp);
3573 emit_andne_imm(temp,0,temp);
3574 emit_shrimm(temp,7,tl);
3575 emit_readword((int)®_cop2d[10],temp);
3576 emit_testimm(temp,0x8000);
3577 emit_andimm(temp,0xf80,temp);
3578 emit_andne_imm(temp,0,temp);
3579 emit_orrshr_imm(temp,2,tl);
3580 emit_readword((int)®_cop2d[11],temp);
3581 emit_testimm(temp,0x8000);
3582 emit_andimm(temp,0xf80,temp);
3583 emit_andne_imm(temp,0,temp);
3584 emit_orrshl_imm(temp,3,tl);
3585 emit_writeword(tl,(int)®_cop2d[copr]);
3588 emit_readword((int)®_cop2d[copr],tl);
3593 static void cop2_put_dreg(u_int copr,signed char sl,signed char temp)
3597 emit_readword((int)®_cop2d[13],temp); // SXY1
3598 emit_writeword(sl,(int)®_cop2d[copr]);
3599 emit_writeword(temp,(int)®_cop2d[12]); // SXY0
3600 emit_readword((int)®_cop2d[14],temp); // SXY2
3601 emit_writeword(sl,(int)®_cop2d[14]);
3602 emit_writeword(temp,(int)®_cop2d[13]); // SXY1
3605 emit_andimm(sl,0x001f,temp);
3606 emit_shlimm(temp,7,temp);
3607 emit_writeword(temp,(int)®_cop2d[9]);
3608 emit_andimm(sl,0x03e0,temp);
3609 emit_shlimm(temp,2,temp);
3610 emit_writeword(temp,(int)®_cop2d[10]);
3611 emit_andimm(sl,0x7c00,temp);
3612 emit_shrimm(temp,3,temp);
3613 emit_writeword(temp,(int)®_cop2d[11]);
3614 emit_writeword(sl,(int)®_cop2d[28]);
3618 emit_mvnmi(temp,temp);
3619 emit_clz(temp,temp);
3620 emit_writeword(sl,(int)®_cop2d[30]);
3621 emit_writeword(temp,(int)®_cop2d[31]);
3626 emit_writeword(sl,(int)®_cop2d[copr]);
3631 void cop2_assemble(int i,struct regstat *i_regs)
3633 u_int copr=(source[i]>>11)&0x1f;
3634 signed char temp=get_reg(i_regs->regmap,-1);
3635 if (opcode2[i]==0) { // MFC2
3636 signed char tl=get_reg(i_regs->regmap,rt1[i]);
3637 if(tl>=0&&rt1[i]!=0)
3638 cop2_get_dreg(copr,tl,temp);
3640 else if (opcode2[i]==4) { // MTC2
3641 signed char sl=get_reg(i_regs->regmap,rs1[i]);
3642 cop2_put_dreg(copr,sl,temp);
3644 else if (opcode2[i]==2) // CFC2
3646 signed char tl=get_reg(i_regs->regmap,rt1[i]);
3647 if(tl>=0&&rt1[i]!=0)
3648 emit_readword((int)®_cop2c[copr],tl);
3650 else if (opcode2[i]==6) // CTC2
3652 signed char sl=get_reg(i_regs->regmap,rs1[i]);
3661 emit_signextend16(sl,temp);
3664 //value = value & 0x7ffff000;
3665 //if (value & 0x7f87e000) value |= 0x80000000;
3666 emit_shrimm(sl,12,temp);
3667 emit_shlimm(temp,12,temp);
3668 emit_testimm(temp,0x7f000000);
3669 emit_testeqimm(temp,0x00870000);
3670 emit_testeqimm(temp,0x0000e000);
3671 emit_orrne_imm(temp,0x80000000,temp);
3677 emit_writeword(temp,(int)®_cop2c[copr]);
3682 void c2op_assemble(int i,struct regstat *i_regs)
3684 signed char temp=get_reg(i_regs->regmap,-1);
3685 u_int c2op=source[i]&0x3f;
3687 for(hr=0;hr<HOST_REGS;hr++) {
3688 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3690 if(i==0||itype[i-1]!=C2OP)
3693 if (gte_handlers[c2op]!=NULL) {
3694 int cc=get_reg(i_regs->regmap,CCREG);
3695 emit_movimm(source[i],temp); // opcode
3696 if (cc>=0&>e_cycletab[c2op])
3697 emit_addimm(cc,gte_cycletab[c2op]/2,cc); // XXX: cound just adjust ccadj?
3698 emit_writeword(temp,(int)&psxRegs.code);
3699 emit_call((int)gte_handlers[c2op]);
3702 if(i>=slen-1||itype[i+1]!=C2OP)
3703 restore_regs(reglist);
3706 void cop1_unusable(int i,struct regstat *i_regs)
3708 // XXX: should just just do the exception instead
3712 add_stub(FP_STUB,jaddr,(int)out,i,0,(int)i_regs,is_delayslot,0);
3717 void cop1_assemble(int i,struct regstat *i_regs)
3719 #ifndef DISABLE_COP1
3720 // Check cop1 unusable
3722 signed char rs=get_reg(i_regs->regmap,CSREG);
3724 emit_testimm(rs,0x20000000);
3727 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3730 if (opcode2[i]==0) { // MFC1
3731 signed char tl=get_reg(i_regs->regmap,rt1[i]);
3733 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],tl);
3734 emit_readword_indexed(0,tl,tl);
3737 else if (opcode2[i]==1) { // DMFC1
3738 signed char tl=get_reg(i_regs->regmap,rt1[i]);
3739 signed char th=get_reg(i_regs->regmap,rt1[i]|64);
3741 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],tl);
3742 if(th>=0) emit_readword_indexed(4,tl,th);
3743 emit_readword_indexed(0,tl,tl);
3746 else if (opcode2[i]==4) { // MTC1
3747 signed char sl=get_reg(i_regs->regmap,rs1[i]);
3748 signed char temp=get_reg(i_regs->regmap,-1);
3749 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
3750 emit_writeword_indexed(sl,0,temp);
3752 else if (opcode2[i]==5) { // DMTC1
3753 signed char sl=get_reg(i_regs->regmap,rs1[i]);
3754 signed char sh=rs1[i]>0?get_reg(i_regs->regmap,rs1[i]|64):sl;
3755 signed char temp=get_reg(i_regs->regmap,-1);
3756 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
3757 emit_writeword_indexed(sh,4,temp);
3758 emit_writeword_indexed(sl,0,temp);
3760 else if (opcode2[i]==2) // CFC1
3762 signed char tl=get_reg(i_regs->regmap,rt1[i]);
3764 u_int copr=(source[i]>>11)&0x1f;
3765 if(copr==0) emit_readword((int)&FCR0,tl);
3766 if(copr==31) emit_readword((int)&FCR31,tl);
3769 else if (opcode2[i]==6) // CTC1
3771 signed char sl=get_reg(i_regs->regmap,rs1[i]);
3772 u_int copr=(source[i]>>11)&0x1f;
3776 emit_writeword(sl,(int)&FCR31);
3777 // Set the rounding mode
3779 //char temp=get_reg(i_regs->regmap,-1);
3780 //emit_andimm(sl,3,temp);
3781 //emit_fldcw_indexed((int)&rounding_modes,temp);
3785 cop1_unusable(i, i_regs);
3789 void fconv_assemble_arm(int i,struct regstat *i_regs)
3791 #ifndef DISABLE_COP1
3792 signed char temp=get_reg(i_regs->regmap,-1);
3794 // Check cop1 unusable
3796 signed char rs=get_reg(i_regs->regmap,CSREG);
3798 emit_testimm(rs,0x20000000);
3801 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3805 #if(defined(__VFP_FP__) && !defined(__SOFTFP__))
3806 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0d) { // trunc_w_s
3807 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
3809 emit_ftosizs(15,15); // float->int, truncate
3810 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f))
3811 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
3815 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0d) { // trunc_w_d
3816 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
3818 emit_ftosizd(7,13); // double->int, truncate
3819 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
3824 if(opcode2[i]==0x14&&(source[i]&0x3f)==0x20) { // cvt_s_w
3825 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
3827 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f))
3828 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
3833 if(opcode2[i]==0x14&&(source[i]&0x3f)==0x21) { // cvt_d_w
3834 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
3836 emit_readword((int)®_cop1_double[(source[i]>>6)&0x1f],temp);
3842 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x21) { // cvt_d_s
3843 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
3845 emit_readword((int)®_cop1_double[(source[i]>>6)&0x1f],temp);
3850 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x20) { // cvt_s_d
3851 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
3853 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
3863 for(hr=0;hr<HOST_REGS;hr++) {
3864 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3868 if(opcode2[i]==0x14&&(source[i]&0x3f)==0x20) {
3869 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3870 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3871 emit_call((int)cvt_s_w);
3873 if(opcode2[i]==0x14&&(source[i]&0x3f)==0x21) {
3874 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3875 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3876 emit_call((int)cvt_d_w);
3878 if(opcode2[i]==0x15&&(source[i]&0x3f)==0x20) {
3879 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3880 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3881 emit_call((int)cvt_s_l);
3883 if(opcode2[i]==0x15&&(source[i]&0x3f)==0x21) {
3884 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3885 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3886 emit_call((int)cvt_d_l);
3889 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x21) {
3890 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3891 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3892 emit_call((int)cvt_d_s);
3894 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x24) {
3895 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3896 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3897 emit_call((int)cvt_w_s);
3899 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x25) {
3900 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3901 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3902 emit_call((int)cvt_l_s);
3905 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x20) {
3906 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3907 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3908 emit_call((int)cvt_s_d);
3910 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x24) {
3911 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3912 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3913 emit_call((int)cvt_w_d);
3915 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x25) {
3916 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3917 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3918 emit_call((int)cvt_l_d);
3921 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x08) {
3922 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3923 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3924 emit_call((int)round_l_s);
3926 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x09) {
3927 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3928 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3929 emit_call((int)trunc_l_s);
3931 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0a) {
3932 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3933 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3934 emit_call((int)ceil_l_s);
3936 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0b) {
3937 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3938 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3939 emit_call((int)floor_l_s);
3941 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0c) {
3942 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3943 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3944 emit_call((int)round_w_s);
3946 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0d) {
3947 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3948 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3949 emit_call((int)trunc_w_s);
3951 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0e) {
3952 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3953 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3954 emit_call((int)ceil_w_s);
3956 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0f) {
3957 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
3958 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3959 emit_call((int)floor_w_s);
3962 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x08) {
3963 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3964 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3965 emit_call((int)round_l_d);
3967 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x09) {
3968 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3969 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3970 emit_call((int)trunc_l_d);
3972 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0a) {
3973 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3974 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3975 emit_call((int)ceil_l_d);
3977 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0b) {
3978 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3979 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
3980 emit_call((int)floor_l_d);
3982 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0c) {
3983 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3984 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3985 emit_call((int)round_w_d);
3987 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0d) {
3988 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3989 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3990 emit_call((int)trunc_w_d);
3992 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0e) {
3993 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3994 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
3995 emit_call((int)ceil_w_d);
3997 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0f) {
3998 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
3999 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4000 emit_call((int)floor_w_d);
4003 restore_regs(reglist);
4005 cop1_unusable(i, i_regs);
4008 #define fconv_assemble fconv_assemble_arm
4010 void fcomp_assemble(int i,struct regstat *i_regs)
4012 #ifndef DISABLE_COP1
4013 signed char fs=get_reg(i_regs->regmap,FSREG);
4014 signed char temp=get_reg(i_regs->regmap,-1);
4016 // Check cop1 unusable
4018 signed char cs=get_reg(i_regs->regmap,CSREG);
4020 emit_testimm(cs,0x20000000);
4023 add_stub(FP_STUB,jaddr,(int)out,i,cs,(int)i_regs,is_delayslot,0);
4027 if((source[i]&0x3f)==0x30) {
4028 emit_andimm(fs,~0x800000,fs);
4032 if((source[i]&0x3e)==0x38) {
4033 // sf/ngle - these should throw exceptions for NaNs
4034 emit_andimm(fs,~0x800000,fs);
4038 #if(defined(__VFP_FP__) && !defined(__SOFTFP__))
4039 if(opcode2[i]==0x10) {
4040 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
4041 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],HOST_TEMPREG);
4042 emit_orimm(fs,0x800000,fs);
4044 emit_flds(HOST_TEMPREG,15);
4047 if((source[i]&0x3f)==0x31) emit_bicvc_imm(fs,0x800000,fs); // c_un_s
4048 if((source[i]&0x3f)==0x32) emit_bicne_imm(fs,0x800000,fs); // c_eq_s
4049 if((source[i]&0x3f)==0x33) {emit_bicne_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ueq_s
4050 if((source[i]&0x3f)==0x34) emit_biccs_imm(fs,0x800000,fs); // c_olt_s
4051 if((source[i]&0x3f)==0x35) {emit_biccs_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ult_s
4052 if((source[i]&0x3f)==0x36) emit_bichi_imm(fs,0x800000,fs); // c_ole_s
4053 if((source[i]&0x3f)==0x37) {emit_bichi_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ule_s
4054 if((source[i]&0x3f)==0x3a) emit_bicne_imm(fs,0x800000,fs); // c_seq_s
4055 if((source[i]&0x3f)==0x3b) emit_bicne_imm(fs,0x800000,fs); // c_ngl_s
4056 if((source[i]&0x3f)==0x3c) emit_biccs_imm(fs,0x800000,fs); // c_lt_s
4057 if((source[i]&0x3f)==0x3d) emit_biccs_imm(fs,0x800000,fs); // c_nge_s
4058 if((source[i]&0x3f)==0x3e) emit_bichi_imm(fs,0x800000,fs); // c_le_s
4059 if((source[i]&0x3f)==0x3f) emit_bichi_imm(fs,0x800000,fs); // c_ngt_s
4062 if(opcode2[i]==0x11) {
4063 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
4064 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],HOST_TEMPREG);
4065 emit_orimm(fs,0x800000,fs);
4067 emit_vldr(HOST_TEMPREG,7);
4070 if((source[i]&0x3f)==0x31) emit_bicvc_imm(fs,0x800000,fs); // c_un_d
4071 if((source[i]&0x3f)==0x32) emit_bicne_imm(fs,0x800000,fs); // c_eq_d
4072 if((source[i]&0x3f)==0x33) {emit_bicne_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ueq_d
4073 if((source[i]&0x3f)==0x34) emit_biccs_imm(fs,0x800000,fs); // c_olt_d
4074 if((source[i]&0x3f)==0x35) {emit_biccs_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ult_d
4075 if((source[i]&0x3f)==0x36) emit_bichi_imm(fs,0x800000,fs); // c_ole_d
4076 if((source[i]&0x3f)==0x37) {emit_bichi_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ule_d
4077 if((source[i]&0x3f)==0x3a) emit_bicne_imm(fs,0x800000,fs); // c_seq_d
4078 if((source[i]&0x3f)==0x3b) emit_bicne_imm(fs,0x800000,fs); // c_ngl_d
4079 if((source[i]&0x3f)==0x3c) emit_biccs_imm(fs,0x800000,fs); // c_lt_d
4080 if((source[i]&0x3f)==0x3d) emit_biccs_imm(fs,0x800000,fs); // c_nge_d
4081 if((source[i]&0x3f)==0x3e) emit_bichi_imm(fs,0x800000,fs); // c_le_d
4082 if((source[i]&0x3f)==0x3f) emit_bichi_imm(fs,0x800000,fs); // c_ngt_d
4090 for(hr=0;hr<HOST_REGS;hr++) {
4091 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
4095 if(opcode2[i]==0x10) {
4096 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4097 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],ARG2_REG);
4098 if((source[i]&0x3f)==0x30) emit_call((int)c_f_s);
4099 if((source[i]&0x3f)==0x31) emit_call((int)c_un_s);
4100 if((source[i]&0x3f)==0x32) emit_call((int)c_eq_s);
4101 if((source[i]&0x3f)==0x33) emit_call((int)c_ueq_s);
4102 if((source[i]&0x3f)==0x34) emit_call((int)c_olt_s);
4103 if((source[i]&0x3f)==0x35) emit_call((int)c_ult_s);
4104 if((source[i]&0x3f)==0x36) emit_call((int)c_ole_s);
4105 if((source[i]&0x3f)==0x37) emit_call((int)c_ule_s);
4106 if((source[i]&0x3f)==0x38) emit_call((int)c_sf_s);
4107 if((source[i]&0x3f)==0x39) emit_call((int)c_ngle_s);
4108 if((source[i]&0x3f)==0x3a) emit_call((int)c_seq_s);
4109 if((source[i]&0x3f)==0x3b) emit_call((int)c_ngl_s);
4110 if((source[i]&0x3f)==0x3c) emit_call((int)c_lt_s);
4111 if((source[i]&0x3f)==0x3d) emit_call((int)c_nge_s);
4112 if((source[i]&0x3f)==0x3e) emit_call((int)c_le_s);
4113 if((source[i]&0x3f)==0x3f) emit_call((int)c_ngt_s);
4115 if(opcode2[i]==0x11) {
4116 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4117 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],ARG2_REG);
4118 if((source[i]&0x3f)==0x30) emit_call((int)c_f_d);
4119 if((source[i]&0x3f)==0x31) emit_call((int)c_un_d);
4120 if((source[i]&0x3f)==0x32) emit_call((int)c_eq_d);
4121 if((source[i]&0x3f)==0x33) emit_call((int)c_ueq_d);
4122 if((source[i]&0x3f)==0x34) emit_call((int)c_olt_d);
4123 if((source[i]&0x3f)==0x35) emit_call((int)c_ult_d);
4124 if((source[i]&0x3f)==0x36) emit_call((int)c_ole_d);
4125 if((source[i]&0x3f)==0x37) emit_call((int)c_ule_d);
4126 if((source[i]&0x3f)==0x38) emit_call((int)c_sf_d);
4127 if((source[i]&0x3f)==0x39) emit_call((int)c_ngle_d);
4128 if((source[i]&0x3f)==0x3a) emit_call((int)c_seq_d);
4129 if((source[i]&0x3f)==0x3b) emit_call((int)c_ngl_d);
4130 if((source[i]&0x3f)==0x3c) emit_call((int)c_lt_d);
4131 if((source[i]&0x3f)==0x3d) emit_call((int)c_nge_d);
4132 if((source[i]&0x3f)==0x3e) emit_call((int)c_le_d);
4133 if((source[i]&0x3f)==0x3f) emit_call((int)c_ngt_d);
4135 restore_regs(reglist);
4136 emit_loadreg(FSREG,fs);
4138 cop1_unusable(i, i_regs);
4142 void float_assemble(int i,struct regstat *i_regs)
4144 #ifndef DISABLE_COP1
4145 signed char temp=get_reg(i_regs->regmap,-1);
4147 // Check cop1 unusable
4149 signed char cs=get_reg(i_regs->regmap,CSREG);
4151 emit_testimm(cs,0x20000000);
4154 add_stub(FP_STUB,jaddr,(int)out,i,cs,(int)i_regs,is_delayslot,0);
4158 #if(defined(__VFP_FP__) && !defined(__SOFTFP__))
4159 if((source[i]&0x3f)==6) // mov
4161 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
4162 if(opcode2[i]==0x10) {
4163 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
4164 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],HOST_TEMPREG);
4165 emit_readword_indexed(0,temp,temp);
4166 emit_writeword_indexed(temp,0,HOST_TEMPREG);
4168 if(opcode2[i]==0x11) {
4169 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
4170 emit_readword((int)®_cop1_double[(source[i]>>6)&0x1f],HOST_TEMPREG);
4172 emit_vstr(7,HOST_TEMPREG);
4178 if((source[i]&0x3f)>3)
4180 if(opcode2[i]==0x10) {
4181 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
4183 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
4184 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
4186 if((source[i]&0x3f)==4) // sqrt
4188 if((source[i]&0x3f)==5) // abs
4190 if((source[i]&0x3f)==7) // neg
4194 if(opcode2[i]==0x11) {
4195 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
4197 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
4198 emit_readword((int)®_cop1_double[(source[i]>>6)&0x1f],temp);
4200 if((source[i]&0x3f)==4) // sqrt
4202 if((source[i]&0x3f)==5) // abs
4204 if((source[i]&0x3f)==7) // neg
4210 if((source[i]&0x3f)<4)
4212 if(opcode2[i]==0x10) {
4213 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
4215 if(opcode2[i]==0x11) {
4216 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
4218 if(((source[i]>>11)&0x1f)!=((source[i]>>16)&0x1f)) {
4219 if(opcode2[i]==0x10) {
4220 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],HOST_TEMPREG);
4222 emit_flds(HOST_TEMPREG,13);
4223 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
4224 if(((source[i]>>16)&0x1f)!=((source[i]>>6)&0x1f)) {
4225 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
4228 if((source[i]&0x3f)==0) emit_fadds(15,13,15);
4229 if((source[i]&0x3f)==1) emit_fsubs(15,13,15);
4230 if((source[i]&0x3f)==2) emit_fmuls(15,13,15);
4231 if((source[i]&0x3f)==3) emit_fdivs(15,13,15);
4232 if(((source[i]>>16)&0x1f)==((source[i]>>6)&0x1f)) {
4233 emit_fsts(15,HOST_TEMPREG);
4238 else if(opcode2[i]==0x11) {
4239 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],HOST_TEMPREG);
4241 emit_vldr(HOST_TEMPREG,6);
4242 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
4243 if(((source[i]>>16)&0x1f)!=((source[i]>>6)&0x1f)) {
4244 emit_readword((int)®_cop1_double[(source[i]>>6)&0x1f],temp);
4247 if((source[i]&0x3f)==0) emit_faddd(7,6,7);
4248 if((source[i]&0x3f)==1) emit_fsubd(7,6,7);
4249 if((source[i]&0x3f)==2) emit_fmuld(7,6,7);
4250 if((source[i]&0x3f)==3) emit_fdivd(7,6,7);
4251 if(((source[i]>>16)&0x1f)==((source[i]>>6)&0x1f)) {
4252 emit_vstr(7,HOST_TEMPREG);
4259 if(opcode2[i]==0x10) {
4261 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
4262 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
4264 if((source[i]&0x3f)==0) emit_fadds(15,15,15);
4265 if((source[i]&0x3f)==1) emit_fsubs(15,15,15);
4266 if((source[i]&0x3f)==2) emit_fmuls(15,15,15);
4267 if((source[i]&0x3f)==3) emit_fdivs(15,15,15);
4270 else if(opcode2[i]==0x11) {
4272 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
4273 emit_readword((int)®_cop1_double[(source[i]>>6)&0x1f],temp);
4275 if((source[i]&0x3f)==0) emit_faddd(7,7,7);
4276 if((source[i]&0x3f)==1) emit_fsubd(7,7,7);
4277 if((source[i]&0x3f)==2) emit_fmuld(7,7,7);
4278 if((source[i]&0x3f)==3) emit_fdivd(7,7,7);
4287 for(hr=0;hr<HOST_REGS;hr++) {
4288 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
4290 if(opcode2[i]==0x10) { // Single precision
4292 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4293 if((source[i]&0x3f)<4) {
4294 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],ARG2_REG);
4295 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG3_REG);
4297 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4299 switch(source[i]&0x3f)
4301 case 0x00: emit_call((int)add_s);break;
4302 case 0x01: emit_call((int)sub_s);break;
4303 case 0x02: emit_call((int)mul_s);break;
4304 case 0x03: emit_call((int)div_s);break;
4305 case 0x04: emit_call((int)sqrt_s);break;
4306 case 0x05: emit_call((int)abs_s);break;
4307 case 0x06: emit_call((int)mov_s);break;
4308 case 0x07: emit_call((int)neg_s);break;
4310 restore_regs(reglist);
4312 if(opcode2[i]==0x11) { // Double precision
4314 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4315 if((source[i]&0x3f)<4) {
4316 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],ARG2_REG);
4317 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG3_REG);
4319 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
4321 switch(source[i]&0x3f)
4323 case 0x00: emit_call((int)add_d);break;
4324 case 0x01: emit_call((int)sub_d);break;
4325 case 0x02: emit_call((int)mul_d);break;
4326 case 0x03: emit_call((int)div_d);break;
4327 case 0x04: emit_call((int)sqrt_d);break;
4328 case 0x05: emit_call((int)abs_d);break;
4329 case 0x06: emit_call((int)mov_d);break;
4330 case 0x07: emit_call((int)neg_d);break;
4332 restore_regs(reglist);
4335 cop1_unusable(i, i_regs);
4339 void multdiv_assemble_arm(int i,struct regstat *i_regs)
4346 // case 0x1D: DMULTU
4351 if((opcode2[i]&4)==0) // 32-bit
4353 if(opcode2[i]==0x18) // MULT
4355 signed char m1=get_reg(i_regs->regmap,rs1[i]);
4356 signed char m2=get_reg(i_regs->regmap,rs2[i]);
4357 signed char hi=get_reg(i_regs->regmap,HIREG);
4358 signed char lo=get_reg(i_regs->regmap,LOREG);
4363 emit_smull(m1,m2,hi,lo);
4365 if(opcode2[i]==0x19) // MULTU
4367 signed char m1=get_reg(i_regs->regmap,rs1[i]);
4368 signed char m2=get_reg(i_regs->regmap,rs2[i]);
4369 signed char hi=get_reg(i_regs->regmap,HIREG);
4370 signed char lo=get_reg(i_regs->regmap,LOREG);
4375 emit_umull(m1,m2,hi,lo);
4377 if(opcode2[i]==0x1A) // DIV
4379 signed char d1=get_reg(i_regs->regmap,rs1[i]);
4380 signed char d2=get_reg(i_regs->regmap,rs2[i]);
4383 signed char quotient=get_reg(i_regs->regmap,LOREG);
4384 signed char remainder=get_reg(i_regs->regmap,HIREG);
4385 assert(quotient>=0);
4386 assert(remainder>=0);
4387 emit_movs(d1,remainder);
4388 emit_negmi(remainder,remainder);
4389 emit_movs(d2,HOST_TEMPREG);
4390 emit_jeq((int)out+52); // Division by zero
4391 emit_negmi(HOST_TEMPREG,HOST_TEMPREG);
4392 emit_clz(HOST_TEMPREG,quotient);
4393 emit_shl(HOST_TEMPREG,quotient,HOST_TEMPREG);
4394 emit_orimm(quotient,1<<31,quotient);
4395 emit_shr(quotient,quotient,quotient);
4396 emit_cmp(remainder,HOST_TEMPREG);
4397 emit_subcs(remainder,HOST_TEMPREG,remainder);
4398 emit_adcs(quotient,quotient,quotient);
4399 emit_shrimm(HOST_TEMPREG,1,HOST_TEMPREG);
4400 emit_jcc((int)out-16); // -4
4402 emit_negmi(quotient,quotient);
4404 emit_negmi(remainder,remainder);
4406 if(opcode2[i]==0x1B) // DIVU
4408 signed char d1=get_reg(i_regs->regmap,rs1[i]); // dividend
4409 signed char d2=get_reg(i_regs->regmap,rs2[i]); // divisor
4412 signed char quotient=get_reg(i_regs->regmap,LOREG);
4413 signed char remainder=get_reg(i_regs->regmap,HIREG);
4414 assert(quotient>=0);
4415 assert(remainder>=0);
4417 emit_jeq((int)out+44); // Division by zero
4418 emit_clz(d2,HOST_TEMPREG);
4419 emit_movimm(1<<31,quotient);
4420 emit_shl(d2,HOST_TEMPREG,d2);
4421 emit_mov(d1,remainder);
4422 emit_shr(quotient,HOST_TEMPREG,quotient);
4423 emit_cmp(remainder,d2);
4424 emit_subcs(remainder,d2,remainder);
4425 emit_adcs(quotient,quotient,quotient);
4426 emit_shrcc_imm(d2,1,d2);
4427 emit_jcc((int)out-16); // -4
4432 if(opcode2[i]==0x1C) // DMULT
4434 assert(opcode2[i]!=0x1C);
4435 signed char m1h=get_reg(i_regs->regmap,rs1[i]|64);
4436 signed char m1l=get_reg(i_regs->regmap,rs1[i]);
4437 signed char m2h=get_reg(i_regs->regmap,rs2[i]|64);
4438 signed char m2l=get_reg(i_regs->regmap,rs2[i]);
4447 emit_call((int)&mult64);
4452 signed char hih=get_reg(i_regs->regmap,HIREG|64);
4453 signed char hil=get_reg(i_regs->regmap,HIREG);
4454 if(hih>=0) emit_loadreg(HIREG|64,hih);
4455 if(hil>=0) emit_loadreg(HIREG,hil);
4456 signed char loh=get_reg(i_regs->regmap,LOREG|64);
4457 signed char lol=get_reg(i_regs->regmap,LOREG);
4458 if(loh>=0) emit_loadreg(LOREG|64,loh);
4459 if(lol>=0) emit_loadreg(LOREG,lol);
4461 if(opcode2[i]==0x1D) // DMULTU
4463 signed char m1h=get_reg(i_regs->regmap,rs1[i]|64);
4464 signed char m1l=get_reg(i_regs->regmap,rs1[i]);
4465 signed char m2h=get_reg(i_regs->regmap,rs2[i]|64);
4466 signed char m2l=get_reg(i_regs->regmap,rs2[i]);
4472 if(m1l!=0) emit_mov(m1l,0);
4473 if(m1h==0) emit_readword((int)&dynarec_local,1);
4474 else if(m1h>1) emit_mov(m1h,1);
4475 if(m2l<2) emit_readword((int)&dynarec_local+m2l*4,2);
4476 else if(m2l>2) emit_mov(m2l,2);
4477 if(m2h<3) emit_readword((int)&dynarec_local+m2h*4,3);
4478 else if(m2h>3) emit_mov(m2h,3);
4479 emit_call((int)&multu64);
4480 restore_regs(0x100f);
4481 signed char hih=get_reg(i_regs->regmap,HIREG|64);
4482 signed char hil=get_reg(i_regs->regmap,HIREG);
4483 signed char loh=get_reg(i_regs->regmap,LOREG|64);
4484 signed char lol=get_reg(i_regs->regmap,LOREG);
4485 /*signed char temp=get_reg(i_regs->regmap,-1);
4486 signed char rh=get_reg(i_regs->regmap,HIREG|64);
4487 signed char rl=get_reg(i_regs->regmap,HIREG);
4493 //emit_mov(m1l,EAX);
4495 emit_umull(rl,rh,m1l,m2l);
4496 emit_storereg(LOREG,rl);
4498 //emit_mov(m1h,EAX);
4500 emit_umull(rl,rh,m1h,m2l);
4501 emit_adds(rl,temp,temp);
4502 emit_adcimm(rh,0,rh);
4503 emit_storereg(HIREG,rh);
4504 //emit_mov(m2h,EAX);
4506 emit_umull(rl,rh,m1l,m2h);
4507 emit_adds(rl,temp,temp);
4508 emit_adcimm(rh,0,rh);
4509 emit_storereg(LOREG|64,temp);
4511 //emit_mov(m2h,EAX);
4513 emit_umull(rl,rh,m1h,m2h);
4514 emit_adds(rl,temp,rl);
4515 emit_loadreg(HIREG,temp);
4516 emit_adcimm(rh,0,rh);
4517 emit_adds(rl,temp,rl);
4518 emit_adcimm(rh,0,rh);
4525 emit_call((int)&multu64);
4530 signed char hih=get_reg(i_regs->regmap,HIREG|64);
4531 signed char hil=get_reg(i_regs->regmap,HIREG);
4532 if(hih>=0) emit_loadreg(HIREG|64,hih); // DEBUG
4533 if(hil>=0) emit_loadreg(HIREG,hil); // DEBUG
4535 // Shouldn't be necessary
4536 //char loh=get_reg(i_regs->regmap,LOREG|64);
4537 //char lol=get_reg(i_regs->regmap,LOREG);
4538 //if(loh>=0) emit_loadreg(LOREG|64,loh);
4539 //if(lol>=0) emit_loadreg(LOREG,lol);
4541 if(opcode2[i]==0x1E) // DDIV
4543 signed char d1h=get_reg(i_regs->regmap,rs1[i]|64);
4544 signed char d1l=get_reg(i_regs->regmap,rs1[i]);
4545 signed char d2h=get_reg(i_regs->regmap,rs2[i]|64);
4546 signed char d2l=get_reg(i_regs->regmap,rs2[i]);
4552 if(d1l!=0) emit_mov(d1l,0);
4553 if(d1h==0) emit_readword((int)&dynarec_local,1);
4554 else if(d1h>1) emit_mov(d1h,1);
4555 if(d2l<2) emit_readword((int)&dynarec_local+d2l*4,2);
4556 else if(d2l>2) emit_mov(d2l,2);
4557 if(d2h<3) emit_readword((int)&dynarec_local+d2h*4,3);
4558 else if(d2h>3) emit_mov(d2h,3);
4559 emit_call((int)&div64);
4560 restore_regs(0x100f);
4561 signed char hih=get_reg(i_regs->regmap,HIREG|64);
4562 signed char hil=get_reg(i_regs->regmap,HIREG);
4563 signed char loh=get_reg(i_regs->regmap,LOREG|64);
4564 signed char lol=get_reg(i_regs->regmap,LOREG);
4565 if(hih>=0) emit_loadreg(HIREG|64,hih);
4566 if(hil>=0) emit_loadreg(HIREG,hil);
4567 if(loh>=0) emit_loadreg(LOREG|64,loh);
4568 if(lol>=0) emit_loadreg(LOREG,lol);
4570 if(opcode2[i]==0x1F) // DDIVU
4572 //u_int hr,reglist=0;
4573 //for(hr=0;hr<HOST_REGS;hr++) {
4574 // if(i_regs->regmap[hr]>=0 && (i_regs->regmap[hr]&62)!=HIREG) reglist|=1<<hr;
4576 signed char d1h=get_reg(i_regs->regmap,rs1[i]|64);
4577 signed char d1l=get_reg(i_regs->regmap,rs1[i]);
4578 signed char d2h=get_reg(i_regs->regmap,rs2[i]|64);
4579 signed char d2l=get_reg(i_regs->regmap,rs2[i]);
4585 if(d1l!=0) emit_mov(d1l,0);
4586 if(d1h==0) emit_readword((int)&dynarec_local,1);
4587 else if(d1h>1) emit_mov(d1h,1);
4588 if(d2l<2) emit_readword((int)&dynarec_local+d2l*4,2);
4589 else if(d2l>2) emit_mov(d2l,2);
4590 if(d2h<3) emit_readword((int)&dynarec_local+d2h*4,3);
4591 else if(d2h>3) emit_mov(d2h,3);
4592 emit_call((int)&divu64);
4593 restore_regs(0x100f);
4594 signed char hih=get_reg(i_regs->regmap,HIREG|64);
4595 signed char hil=get_reg(i_regs->regmap,HIREG);
4596 signed char loh=get_reg(i_regs->regmap,LOREG|64);
4597 signed char lol=get_reg(i_regs->regmap,LOREG);
4598 if(hih>=0) emit_loadreg(HIREG|64,hih);
4599 if(hil>=0) emit_loadreg(HIREG,hil);
4600 if(loh>=0) emit_loadreg(LOREG|64,loh);
4601 if(lol>=0) emit_loadreg(LOREG,lol);
4607 // Multiply by zero is zero.
4608 // MIPS does not have a divide by zero exception.
4609 // The result is undefined, we return zero.
4610 signed char hr=get_reg(i_regs->regmap,HIREG);
4611 signed char lr=get_reg(i_regs->regmap,LOREG);
4612 if(hr>=0) emit_zeroreg(hr);
4613 if(lr>=0) emit_zeroreg(lr);
4616 #define multdiv_assemble multdiv_assemble_arm
4618 void do_preload_rhash(int r) {
4619 // Don't need this for ARM. On x86, this puts the value 0xf8 into the
4620 // register. On ARM the hash can be done with a single instruction (below)
4623 void do_preload_rhtbl(int ht) {
4624 emit_addimm(FP,(int)&mini_ht-(int)&dynarec_local,ht);
4627 void do_rhash(int rs,int rh) {
4628 emit_andimm(rs,0xf8,rh);
4631 void do_miniht_load(int ht,int rh) {
4632 assem_debug("ldr %s,[%s,%s]!\n",regname[rh],regname[ht],regname[rh]);
4633 output_w32(0xe7b00000|rd_rn_rm(rh,ht,rh));
4636 void do_miniht_jump(int rs,int rh,int ht) {
4638 emit_ldreq_indexed(ht,4,15);
4639 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
4641 emit_jmp(jump_vaddr_reg[7]);
4643 emit_jmp(jump_vaddr_reg[rs]);
4647 void do_miniht_insert(u_int return_address,int rt,int temp) {
4649 emit_movimm(return_address,rt); // PC into link register
4650 add_to_linker((int)out,return_address,1);
4651 emit_pcreladdr(temp);
4652 emit_writeword(rt,(int)&mini_ht[(return_address&0xFF)>>3][0]);
4653 emit_writeword(temp,(int)&mini_ht[(return_address&0xFF)>>3][1]);
4655 emit_movw(return_address&0x0000FFFF,rt);
4656 add_to_linker((int)out,return_address,1);
4657 emit_pcreladdr(temp);
4658 emit_writeword(temp,(int)&mini_ht[(return_address&0xFF)>>3][1]);
4659 emit_movt(return_address&0xFFFF0000,rt);
4660 emit_writeword(rt,(int)&mini_ht[(return_address&0xFF)>>3][0]);
4664 // Sign-extend to 64 bits and write out upper half of a register
4665 // This is useful where we have a 32-bit value in a register, and want to
4666 // keep it in a 32-bit register, but can't guarantee that it won't be read
4667 // as a 64-bit value later.
4668 void wb_sx(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32_pre,uint64_t is32,uint64_t u,uint64_t uu)
4671 if(is32_pre==is32) return;
4673 for(hr=0;hr<HOST_REGS;hr++) {
4674 if(hr!=EXCLUDE_REG) {
4675 //if(pre[hr]==entry[hr]) {
4676 if((reg=pre[hr])>=0) {
4678 if( ((is32_pre&~is32&~uu)>>reg)&1 ) {
4679 emit_sarimm(hr,31,HOST_TEMPREG);
4680 emit_storereg(reg|64,HOST_TEMPREG);
4690 void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t is32_pre,uint64_t u,uint64_t uu)
4692 //if(dirty_pre==dirty) return;
4694 for(hr=0;hr<HOST_REGS;hr++) {
4695 if(hr!=EXCLUDE_REG) {
4697 if(((~u)>>(reg&63))&1) {
4698 if(reg==entry[hr]||(reg>0&&entry[hr]<0)) {
4699 if(((dirty_pre&~dirty)>>hr)&1) {
4701 emit_storereg(reg,hr);
4702 if( ((is32_pre&~uu)>>reg)&1 ) {
4703 emit_sarimm(hr,31,HOST_TEMPREG);
4704 emit_storereg(reg|64,HOST_TEMPREG);
4708 emit_storereg(reg,hr);
4712 else // Check if register moved to a different register
4713 if((new_hr=get_reg(entry,reg))>=0) {
4714 if((dirty_pre>>hr)&(~dirty>>new_hr)&1) {
4716 emit_storereg(reg,hr);
4717 if( ((is32_pre&~uu)>>reg)&1 ) {
4718 emit_sarimm(hr,31,HOST_TEMPREG);
4719 emit_storereg(reg|64,HOST_TEMPREG);
4723 emit_storereg(reg,hr);
4733 /* using strd could possibly help but you'd have to allocate registers in pairs
4734 void wb_invalidate_arm(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,uint64_t u,uint64_t uu)
4738 for(hr=HOST_REGS-1;hr>=0;hr--) {
4739 if(hr!=EXCLUDE_REG) {
4740 if(pre[hr]!=entry[hr]) {
4743 if(get_reg(entry,pre[hr])<0) {
4745 if(!((u>>pre[hr])&1)) {
4746 if(hr<10&&(~hr&1)&&(pre[hr+1]<0||wrote==hr+1)) {
4747 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
4748 emit_sarimm(hr,31,hr+1);
4749 emit_strdreg(pre[hr],hr);
4752 emit_storereg(pre[hr],hr);
4754 emit_storereg(pre[hr],hr);
4755 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
4756 emit_sarimm(hr,31,hr);
4757 emit_storereg(pre[hr]|64,hr);
4762 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
4763 emit_storereg(pre[hr],hr);
4773 for(hr=0;hr<HOST_REGS;hr++) {
4774 if(hr!=EXCLUDE_REG) {
4775 if(pre[hr]!=entry[hr]) {
4778 if((nr=get_reg(entry,pre[hr]))>=0) {
4786 #define wb_invalidate wb_invalidate_arm
4789 // Clearing the cache is rather slow on ARM Linux, so mark the areas
4790 // that need to be cleared, and then only clear these areas once.
4791 void do_clear_cache()
4794 for (i=0;i<(1<<(TARGET_SIZE_2-17));i++)
4796 u_int bitmap=needs_clear_cache[i];
4802 start=BASE_ADDR+i*131072+j*4096;
4810 __clear_cache((void *)start,(void *)end);
4816 needs_clear_cache[i]=0;
4821 // CPU-architecture-specific initialization
4823 #ifndef DISABLE_COP1
4824 rounding_modes[0]=0x0<<22; // round
4825 rounding_modes[1]=0x3<<22; // trunc
4826 rounding_modes[2]=0x1<<22; // ceil
4827 rounding_modes[3]=0x2<<22; // floor
4831 // vim:shiftwidth=2:expandtab