libpcsxcore/new_dynarec/new_dynarec.c

   1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
   2  *   Mupen64plus - new_dynarec.c                                           *
   3  *   Copyright (C) 2009-2011 Ari64                                         *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.          *
  19  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
  20
  21 #include <stdlib.h>
  22 #include <stdint.h> //include for uint64_t
  23 #include <assert.h>
  24
  25 #include "emu_if.h" //emulator interface
  26
  27 #include <sys/mman.h>
  28
  29 #ifdef __i386__
  30 #include "assem_x86.h"
  31 #endif
  32 #ifdef __x86_64__
  33 #include "assem_x64.h"
  34 #endif
  35 #ifdef __arm__
  36 #include "assem_arm.h"
  37 #endif
  38
  39 #define MAXBLOCK 4096
  40 #define MAX_OUTPUT_BLOCK_SIZE 262144
  41 #define CLOCK_DIVIDER 2
  42
  43 struct regstat
  44 {
  45   signed char regmap_entry[HOST_REGS];
  46   signed char regmap[HOST_REGS];
  47   uint64_t was32;
  48   uint64_t is32;
  49   uint64_t wasdirty;
  50   uint64_t dirty;
  51   uint64_t u;
  52   uint64_t uu;
  53   u_int wasconst;
  54   u_int isconst;
  55   uint64_t constmap[HOST_REGS];
  56 };
  57
  58 struct ll_entry
  59 {
  60   u_int vaddr;
  61   u_int reg32;
  62   void *addr;
  63   struct ll_entry *next;
  64 };
  65
  66   u_int start;
  67   u_int *source;
  68   u_int pagelimit;
  69   char insn[MAXBLOCK][10];
  70   u_char itype[MAXBLOCK];
  71   u_char opcode[MAXBLOCK];
  72   u_char opcode2[MAXBLOCK];
  73   u_char bt[MAXBLOCK];
  74   u_char rs1[MAXBLOCK];
  75   u_char rs2[MAXBLOCK];
  76   u_char rt1[MAXBLOCK];
  77   u_char rt2[MAXBLOCK];
  78   u_char us1[MAXBLOCK];
  79   u_char us2[MAXBLOCK];
  80   u_char dep1[MAXBLOCK];
  81   u_char dep2[MAXBLOCK];
  82   u_char lt1[MAXBLOCK];
  83   int imm[MAXBLOCK];
  84   u_int ba[MAXBLOCK];
  85   char likely[MAXBLOCK];
  86   char is_ds[MAXBLOCK];
  87   char ooo[MAXBLOCK];
  88   uint64_t unneeded_reg[MAXBLOCK];
  89   uint64_t unneeded_reg_upper[MAXBLOCK];
  90   uint64_t branch_unneeded_reg[MAXBLOCK];
  91   uint64_t branch_unneeded_reg_upper[MAXBLOCK];
  92   uint64_t p32[MAXBLOCK];
  93   uint64_t pr32[MAXBLOCK];
  94   signed char regmap_pre[MAXBLOCK][HOST_REGS];
  95   signed char regmap[MAXBLOCK][HOST_REGS];
  96   signed char regmap_entry[MAXBLOCK][HOST_REGS];
  97   uint64_t constmap[MAXBLOCK][HOST_REGS];
  98   struct regstat regs[MAXBLOCK];
  99   struct regstat branch_regs[MAXBLOCK];
 100   signed char minimum_free_regs[MAXBLOCK];
 101   u_int needed_reg[MAXBLOCK];
 102   uint64_t requires_32bit[MAXBLOCK];
 103   u_int wont_dirty[MAXBLOCK];
 104   u_int will_dirty[MAXBLOCK];
 105   int ccadj[MAXBLOCK];
 106   int slen;
 107   u_int instr_addr[MAXBLOCK];
 108   u_int link_addr[MAXBLOCK][3];
 109   int linkcount;
 110   u_int stubs[MAXBLOCK*3][8];
 111   int stubcount;
 112   u_int literals[1024][2];
 113   int literalcount;
 114   int is_delayslot;
 115   int cop1_usable;
 116   u_char *out;
 117   struct ll_entry *jump_in[4096];
 118   struct ll_entry *jump_out[4096];
 119   struct ll_entry *jump_dirty[4096];
 120   u_int hash_table[65536][4]  __attribute__((aligned(16)));
 121   char shadow[1048576]  __attribute__((aligned(16)));
 122   void *copy;
 123   int expirep;
 124 #ifndef PCSX
 125   u_int using_tlb;
 126 #else
 127   static const u_int using_tlb=0;
 128 #endif
 129   static u_int sp_in_mirror;
 130   u_int stop_after_jal;
 131   extern u_char restore_candidate[512];
 132   extern int cycle_count;
 133
 134   /* registers that may be allocated */
 135   /* 1-31 gpr */
 136 #define HIREG 32 // hi
 137 #define LOREG 33 // lo
 138 #define FSREG 34 // FPU status (FCSR)
 139 #define CSREG 35 // Coprocessor status
 140 #define CCREG 36 // Cycle count
 141 #define INVCP 37 // Pointer to invalid_code
 142 #define MMREG 38 // Pointer to memory_map
 143 #define ROREG 39 // ram offset (if rdram!=0x80000000)
 144 #define TEMPREG 40
 145 #define FTEMP 40 // FPU temporary register
 146 #define PTEMP 41 // Prefetch temporary register
 147 #define TLREG 42 // TLB mapping offset
 148 #define RHASH 43 // Return address hash
 149 #define RHTBL 44 // Return address hash table address
 150 #define RTEMP 45 // JR/JALR address register
 151 #define MAXREG 45
 152 #define AGEN1 46 // Address generation temporary register
 153 #define AGEN2 47 // Address generation temporary register
 154 #define MGEN1 48 // Maptable address generation temporary register
 155 #define MGEN2 49 // Maptable address generation temporary register
 156 #define BTREG 50 // Branch target temporary register
 157
 158   /* instruction types */
 159 #define NOP 0     // No operation
 160 #define LOAD 1    // Load
 161 #define STORE 2   // Store
 162 #define LOADLR 3  // Unaligned load
 163 #define STORELR 4 // Unaligned store
 164 #define MOV 5     // Move
 165 #define ALU 6     // Arithmetic/logic
 166 #define MULTDIV 7 // Multiply/divide
 167 #define SHIFT 8   // Shift by register
 168 #define SHIFTIMM 9// Shift by immediate
 169 #define IMM16 10  // 16-bit immediate
 170 #define RJUMP 11  // Unconditional jump to register
 171 #define UJUMP 12  // Unconditional jump
 172 #define CJUMP 13  // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
 173 #define SJUMP 14  // Conditional branch (regimm format)
 174 #define COP0 15   // Coprocessor 0
 175 #define COP1 16   // Coprocessor 1
 176 #define C1LS 17   // Coprocessor 1 load/store
 177 #define FJUMP 18  // Conditional branch (floating point)
 178 #define FLOAT 19  // Floating point unit
 179 #define FCONV 20  // Convert integer to float
 180 #define FCOMP 21  // Floating point compare (sets FSREG)
 181 #define SYSCALL 22// SYSCALL
 182 #define OTHER 23  // Other
 183 #define SPAN 24   // Branch/delay slot spans 2 pages
 184 #define NI 25     // Not implemented
 185 #define HLECALL 26// PCSX fake opcodes for HLE
 186 #define COP2 27   // Coprocessor 2 move
 187 #define C2LS 28   // Coprocessor 2 load/store
 188 #define C2OP 29   // Coprocessor 2 operation
 189 #define INTCALL 30// Call interpreter to handle rare corner cases
 190
 191   /* stubs */
 192 #define CC_STUB 1
 193 #define FP_STUB 2
 194 #define LOADB_STUB 3
 195 #define LOADH_STUB 4
 196 #define LOADW_STUB 5
 197 #define LOADD_STUB 6
 198 #define LOADBU_STUB 7
 199 #define LOADHU_STUB 8
 200 #define STOREB_STUB 9
 201 #define STOREH_STUB 10
 202 #define STOREW_STUB 11
 203 #define STORED_STUB 12
 204 #define STORELR_STUB 13
 205 #define INVCODE_STUB 14
 206
 207   /* branch codes */
 208 #define TAKEN 1
 209 #define NOTTAKEN 2
 210 #define NULLDS 3
 211
 212 // asm linkage
 213 int new_recompile_block(int addr);
 214 void *get_addr_ht(u_int vaddr);
 215 void invalidate_block(u_int block);
 216 void invalidate_addr(u_int addr);
 217 void remove_hash(int vaddr);
 218 void jump_vaddr();
 219 void dyna_linker();
 220 void dyna_linker_ds();
 221 void verify_code();
 222 void verify_code_vm();
 223 void verify_code_ds();
 224 void cc_interrupt();
 225 void fp_exception();
 226 void fp_exception_ds();
 227 void jump_syscall();
 228 void jump_syscall_hle();
 229 void jump_eret();
 230 void jump_hlecall();
 231 void jump_intcall();
 232 void new_dyna_leave();
 233
 234 // TLB
 235 void TLBWI_new();
 236 void TLBWR_new();
 237 void read_nomem_new();
 238 void read_nomemb_new();
 239 void read_nomemh_new();
 240 void read_nomemd_new();
 241 void write_nomem_new();
 242 void write_nomemb_new();
 243 void write_nomemh_new();
 244 void write_nomemd_new();
 245 void write_rdram_new();
 246 void write_rdramb_new();
 247 void write_rdramh_new();
 248 void write_rdramd_new();
 249 extern u_int memory_map[1048576];
 250
 251 // Needed by assembler
 252 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
 253 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
 254 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
 255 void load_all_regs(signed char i_regmap[]);
 256 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
 257 void load_regs_entry(int t);
 258 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
 259
 260 int tracedebug=0;
 261
 262 //#define DEBUG_CYCLE_COUNT 1
 263
 264 void nullf() {}
 265 //#define assem_debug printf
 266 //#define inv_debug printf
 267 #define assem_debug nullf
 268 #define inv_debug nullf
 269
 270 static void tlb_hacks()
 271 {
 272 #ifndef DISABLE_TLB
 273   // Goldeneye hack
 274   if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
 275   {
 276     u_int addr;
 277     int n;
 278     switch (ROM_HEADER->Country_code&0xFF)
 279     {
 280       case 0x45: // U
 281         addr=0x34b30;
 282         break;
 283       case 0x4A: // J
 284         addr=0x34b70;
 285         break;
 286       case 0x50: // E
 287         addr=0x329f0;
 288         break;
 289       default:
 290         // Unknown country code
 291         addr=0;
 292         break;
 293     }
 294     u_int rom_addr=(u_int)rom;
 295     #ifdef ROM_COPY
 296     // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
 297     // in the lower 4G of memory to use this hack.  Copy it if necessary.
 298     if((void *)rom>(void *)0xffffffff) {
 299       munmap(ROM_COPY, 67108864);
 300       if(mmap(ROM_COPY, 12582912,
 301               PROT_READ | PROT_WRITE,
 302               MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
 303               -1, 0) <= 0) {printf("mmap() failed\n");}
 304       memcpy(ROM_COPY,rom,12582912);
 305       rom_addr=(u_int)ROM_COPY;
 306     }
 307     #endif
 308     if(addr) {
 309       for(n=0x7F000;n<0x80000;n++) {
 310         memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
 311       }
 312     }
 313   }
 314 #endif
 315 }
 316
 317 static u_int get_page(u_int vaddr)
 318 {
 319 #ifndef PCSX
 320   u_int page=(vaddr^0x80000000)>>12;
 321 #else
 322   u_int page=vaddr&~0xe0000000;
 323   if (page < 0x1000000)
 324     page &= ~0x0e00000; // RAM mirrors
 325   page>>=12;
 326 #endif
 327 #ifndef DISABLE_TLB
 328   if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
 329 #endif
 330   if(page>2048) page=2048+(page&2047);
 331   return page;
 332 }
 333
 334 static u_int get_vpage(u_int vaddr)
 335 {
 336   u_int vpage=(vaddr^0x80000000)>>12;
 337 #ifndef DISABLE_TLB
 338   if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
 339 #endif
 340   if(vpage>2048) vpage=2048+(vpage&2047);
 341   return vpage;
 342 }
 343
 344 // Get address from virtual address
 345 // This is called from the recompiled JR/JALR instructions
 346 void *get_addr(u_int vaddr)
 347 {
 348   u_int page=get_page(vaddr);
 349   u_int vpage=get_vpage(vaddr);
 350   struct ll_entry *head;
 351   //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
 352   head=jump_in[page];
 353   while(head!=NULL) {
 354     if(head->vaddr==vaddr&&head->reg32==0) {
 355   //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 356       int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 357       ht_bin[3]=ht_bin[1];
 358       ht_bin[2]=ht_bin[0];
 359       ht_bin[1]=(int)head->addr;
 360       ht_bin[0]=vaddr;
 361       return head->addr;
 362     }
 363     head=head->next;
 364   }
 365   head=jump_dirty[vpage];
 366   while(head!=NULL) {
 367     if(head->vaddr==vaddr&&head->reg32==0) {
 368       //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 369       // Don't restore blocks which are about to expire from the cache
 370       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 371       if(verify_dirty(head->addr)) {
 372         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
 373         invalid_code[vaddr>>12]=0;
 374         memory_map[vaddr>>12]|=0x40000000;
 375         if(vpage<2048) {
 376 #ifndef DISABLE_TLB
 377           if(tlb_LUT_r[vaddr>>12]) {
 378             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
 379             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
 380           }
 381 #endif
 382           restore_candidate[vpage>>3]|=1<<(vpage&7);
 383         }
 384         else restore_candidate[page>>3]|=1<<(page&7);
 385         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 386         if(ht_bin[0]==vaddr) {
 387           ht_bin[1]=(int)head->addr; // Replace existing entry
 388         }
 389         else
 390         {
 391           ht_bin[3]=ht_bin[1];
 392           ht_bin[2]=ht_bin[0];
 393           ht_bin[1]=(int)head->addr;
 394           ht_bin[0]=vaddr;
 395         }
 396         return head->addr;
 397       }
 398     }
 399     head=head->next;
 400   }
 401   //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
 402   int r=new_recompile_block(vaddr);
 403   if(r==0) return get_addr(vaddr);
 404   // Execute in unmapped page, generate pagefault execption
 405   Status|=2;
 406   Cause=(vaddr<<31)|0x8;
 407   EPC=(vaddr&1)?vaddr-5:vaddr;
 408   BadVAddr=(vaddr&~1);
 409   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
 410   EntryHi=BadVAddr&0xFFFFE000;
 411   return get_addr_ht(0x80000000);
 412 }
 413 // Look up address in hash table first
 414 void *get_addr_ht(u_int vaddr)
 415 {
 416   //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
 417   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 418   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
 419   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
 420   return get_addr(vaddr);
 421 }
 422
 423 void *get_addr_32(u_int vaddr,u_int flags)
 424 {
 425 #ifdef FORCE32
 426   return get_addr(vaddr);
 427 #else
 428   //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
 429   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 430   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
 431   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
 432   u_int page=get_page(vaddr);
 433   u_int vpage=get_vpage(vaddr);
 434   struct ll_entry *head;
 435   head=jump_in[page];
 436   while(head!=NULL) {
 437     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
 438       //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 439       if(head->reg32==0) {
 440         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 441         if(ht_bin[0]==-1) {
 442           ht_bin[1]=(int)head->addr;
 443           ht_bin[0]=vaddr;
 444         }else if(ht_bin[2]==-1) {
 445           ht_bin[3]=(int)head->addr;
 446           ht_bin[2]=vaddr;
 447         }
 448         //ht_bin[3]=ht_bin[1];
 449         //ht_bin[2]=ht_bin[0];
 450         //ht_bin[1]=(int)head->addr;
 451         //ht_bin[0]=vaddr;
 452       }
 453       return head->addr;
 454     }
 455     head=head->next;
 456   }
 457   head=jump_dirty[vpage];
 458   while(head!=NULL) {
 459     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
 460       //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 461       // Don't restore blocks which are about to expire from the cache
 462       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 463       if(verify_dirty(head->addr)) {
 464         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
 465         invalid_code[vaddr>>12]=0;
 466         memory_map[vaddr>>12]|=0x40000000;
 467         if(vpage<2048) {
 468 #ifndef DISABLE_TLB
 469           if(tlb_LUT_r[vaddr>>12]) {
 470             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
 471             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
 472           }
 473 #endif
 474           restore_candidate[vpage>>3]|=1<<(vpage&7);
 475         }
 476         else restore_candidate[page>>3]|=1<<(page&7);
 477         if(head->reg32==0) {
 478           int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 479           if(ht_bin[0]==-1) {
 480             ht_bin[1]=(int)head->addr;
 481             ht_bin[0]=vaddr;
 482           }else if(ht_bin[2]==-1) {
 483             ht_bin[3]=(int)head->addr;
 484             ht_bin[2]=vaddr;
 485           }
 486           //ht_bin[3]=ht_bin[1];
 487           //ht_bin[2]=ht_bin[0];
 488           //ht_bin[1]=(int)head->addr;
 489           //ht_bin[0]=vaddr;
 490         }
 491         return head->addr;
 492       }
 493     }
 494     head=head->next;
 495   }
 496   //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
 497   int r=new_recompile_block(vaddr);
 498   if(r==0) return get_addr(vaddr);
 499   // Execute in unmapped page, generate pagefault execption
 500   Status|=2;
 501   Cause=(vaddr<<31)|0x8;
 502   EPC=(vaddr&1)?vaddr-5:vaddr;
 503   BadVAddr=(vaddr&~1);
 504   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
 505   EntryHi=BadVAddr&0xFFFFE000;
 506   return get_addr_ht(0x80000000);
 507 #endif
 508 }
 509
 510 void clear_all_regs(signed char regmap[])
 511 {
 512   int hr;
 513   for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
 514 }
 515
 516 signed char get_reg(signed char regmap[],int r)
 517 {
 518   int hr;
 519   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
 520   return -1;
 521 }
 522
 523 // Find a register that is available for two consecutive cycles
 524 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
 525 {
 526   int hr;
 527   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
 528   return -1;
 529 }
 530
 531 int count_free_regs(signed char regmap[])
 532 {
 533   int count=0;
 534   int hr;
 535   for(hr=0;hr<HOST_REGS;hr++)
 536   {
 537     if(hr!=EXCLUDE_REG) {
 538       if(regmap[hr]<0) count++;
 539     }
 540   }
 541   return count;
 542 }
 543
 544 void dirty_reg(struct regstat *cur,signed char reg)
 545 {
 546   int hr;
 547   if(!reg) return;
 548   for (hr=0;hr<HOST_REGS;hr++) {
 549     if((cur->regmap[hr]&63)==reg) {
 550       cur->dirty|=1<<hr;
 551     }
 552   }
 553 }
 554
 555 // If we dirty the lower half of a 64 bit register which is now being
 556 // sign-extended, we need to dump the upper half.
 557 // Note: Do this only after completion of the instruction, because
 558 // some instructions may need to read the full 64-bit value even if
 559 // overwriting it (eg SLTI, DSRA32).
 560 static void flush_dirty_uppers(struct regstat *cur)
 561 {
 562   int hr,reg;
 563   for (hr=0;hr<HOST_REGS;hr++) {
 564     if((cur->dirty>>hr)&1) {
 565       reg=cur->regmap[hr];
 566       if(reg>=64)
 567         if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
 568     }
 569   }
 570 }
 571
 572 void set_const(struct regstat *cur,signed char reg,uint64_t value)
 573 {
 574   int hr;
 575   if(!reg) return;
 576   for (hr=0;hr<HOST_REGS;hr++) {
 577     if(cur->regmap[hr]==reg) {
 578       cur->isconst|=1<<hr;
 579       cur->constmap[hr]=value;
 580     }
 581     else if((cur->regmap[hr]^64)==reg) {
 582       cur->isconst|=1<<hr;
 583       cur->constmap[hr]=value>>32;
 584     }
 585   }
 586 }
 587
 588 void clear_const(struct regstat *cur,signed char reg)
 589 {
 590   int hr;
 591   if(!reg) return;
 592   for (hr=0;hr<HOST_REGS;hr++) {
 593     if((cur->regmap[hr]&63)==reg) {
 594       cur->isconst&=~(1<<hr);
 595     }
 596   }
 597 }
 598
 599 int is_const(struct regstat *cur,signed char reg)
 600 {
 601   int hr;
 602   if(reg<0) return 0;
 603   if(!reg) return 1;
 604   for (hr=0;hr<HOST_REGS;hr++) {
 605     if((cur->regmap[hr]&63)==reg) {
 606       return (cur->isconst>>hr)&1;
 607     }
 608   }
 609   return 0;
 610 }
 611 uint64_t get_const(struct regstat *cur,signed char reg)
 612 {
 613   int hr;
 614   if(!reg) return 0;
 615   for (hr=0;hr<HOST_REGS;hr++) {
 616     if(cur->regmap[hr]==reg) {
 617       return cur->constmap[hr];
 618     }
 619   }
 620   printf("Unknown constant in r%d\n",reg);
 621   exit(1);
 622 }
 623
 624 // Least soon needed registers
 625 // Look at the next ten instructions and see which registers
 626 // will be used.  Try not to reallocate these.
 627 void lsn(u_char hsn[], int i, int *preferred_reg)
 628 {
 629   int j;
 630   int b=-1;
 631   for(j=0;j<9;j++)
 632   {
 633     if(i+j>=slen) {
 634       j=slen-i-1;
 635       break;
 636     }
 637     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 638     {
 639       // Don't go past an unconditonal jump
 640       j++;
 641       break;
 642     }
 643   }
 644   for(;j>=0;j--)
 645   {
 646     if(rs1[i+j]) hsn[rs1[i+j]]=j;
 647     if(rs2[i+j]) hsn[rs2[i+j]]=j;
 648     if(rt1[i+j]) hsn[rt1[i+j]]=j;
 649     if(rt2[i+j]) hsn[rt2[i+j]]=j;
 650     if(itype[i+j]==STORE || itype[i+j]==STORELR) {
 651       // Stores can allocate zero
 652       hsn[rs1[i+j]]=j;
 653       hsn[rs2[i+j]]=j;
 654     }
 655     // On some architectures stores need invc_ptr
 656     #if defined(HOST_IMM8)
 657     if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
 658       hsn[INVCP]=j;
 659     }
 660     #endif
 661     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 662     {
 663       hsn[CCREG]=j;
 664       b=j;
 665     }
 666   }
 667   if(b>=0)
 668   {
 669     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 670     {
 671       // Follow first branch
 672       int t=(ba[i+b]-start)>>2;
 673       j=7-b;if(t+j>=slen) j=slen-t-1;
 674       for(;j>=0;j--)
 675       {
 676         if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
 677         if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
 678         //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
 679         //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
 680       }
 681     }
 682     // TODO: preferred register based on backward branch
 683   }
 684   // Delay slot should preferably not overwrite branch conditions or cycle count
 685   if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
 686     if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
 687     if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
 688     hsn[CCREG]=1;
 689     // ...or hash tables
 690     hsn[RHASH]=1;
 691     hsn[RHTBL]=1;
 692   }
 693   // due to the way JAL is currently done we need DS not to evict $ra
 694   if(i>0&&itype[i-1]==UJUMP&&rt1[i-1]==31) {
 695     hsn[31]=0;
 696   }
 697   // Coprocessor load/store needs FTEMP, even if not declared
 698   if(itype[i]==C1LS||itype[i]==C2LS) {
 699     hsn[FTEMP]=0;
 700   }
 701   // Load L/R also uses FTEMP as a temporary register
 702   if(itype[i]==LOADLR) {
 703     hsn[FTEMP]=0;
 704   }
 705   // Also SWL/SWR/SDL/SDR
 706   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
 707     hsn[FTEMP]=0;
 708   }
 709   // Don't remove the TLB registers either
 710   if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
 711     hsn[TLREG]=0;
 712   }
 713   // Don't remove the miniht registers
 714   if(itype[i]==UJUMP||itype[i]==RJUMP)
 715   {
 716     hsn[RHASH]=0;
 717     hsn[RHTBL]=0;
 718   }
 719 }
 720
 721 // We only want to allocate registers if we're going to use them again soon
 722 int needed_again(int r, int i)
 723 {
 724   int j;
 725   int b=-1;
 726   int rn=10;
 727
 728   if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
 729   {
 730     if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
 731       return 0; // Don't need any registers if exiting the block
 732   }
 733   for(j=0;j<9;j++)
 734   {
 735     if(i+j>=slen) {
 736       j=slen-i-1;
 737       break;
 738     }
 739     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 740     {
 741       // Don't go past an unconditonal jump
 742       j++;
 743       break;
 744     }
 745     if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
 746     {
 747       break;
 748     }
 749   }
 750   for(;j>=1;j--)
 751   {
 752     if(rs1[i+j]==r) rn=j;
 753     if(rs2[i+j]==r) rn=j;
 754     if((unneeded_reg[i+j]>>r)&1) rn=10;
 755     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 756     {
 757       b=j;
 758     }
 759   }
 760   /*
 761   if(b>=0)
 762   {
 763     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 764     {
 765       // Follow first branch
 766       int o=rn;
 767       int t=(ba[i+b]-start)>>2;
 768       j=7-b;if(t+j>=slen) j=slen-t-1;
 769       for(;j>=0;j--)
 770       {
 771         if(!((unneeded_reg[t+j]>>r)&1)) {
 772           if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 773           if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 774         }
 775         else rn=o;
 776       }
 777     }
 778   }*/
 779   if(rn<10) return 1;
 780   return 0;
 781 }
 782
 783 // Try to match register allocations at the end of a loop with those
 784 // at the beginning
 785 int loop_reg(int i, int r, int hr)
 786 {
 787   int j,k;
 788   for(j=0;j<9;j++)
 789   {
 790     if(i+j>=slen) {
 791       j=slen-i-1;
 792       break;
 793     }
 794     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 795     {
 796       // Don't go past an unconditonal jump
 797       j++;
 798       break;
 799     }
 800   }
 801   k=0;
 802   if(i>0){
 803     if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
 804       k--;
 805   }
 806   for(;k<j;k++)
 807   {
 808     if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
 809     if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
 810     if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
 811     {
 812       if(ba[i+k]>=start && ba[i+k]<(start+i*4))
 813       {
 814         int t=(ba[i+k]-start)>>2;
 815         int reg=get_reg(regs[t].regmap_entry,r);
 816         if(reg>=0) return reg;
 817         //reg=get_reg(regs[t+1].regmap_entry,r);
 818         //if(reg>=0) return reg;
 819       }
 820     }
 821   }
 822   return hr;
 823 }
 824
 825
 826 // Allocate every register, preserving source/target regs
 827 void alloc_all(struct regstat *cur,int i)
 828 {
 829   int hr;
 830
 831   for(hr=0;hr<HOST_REGS;hr++) {
 832     if(hr!=EXCLUDE_REG) {
 833       if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
 834          ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
 835       {
 836         cur->regmap[hr]=-1;
 837         cur->dirty&=~(1<<hr);
 838       }
 839       // Don't need zeros
 840       if((cur->regmap[hr]&63)==0)
 841       {
 842         cur->regmap[hr]=-1;
 843         cur->dirty&=~(1<<hr);
 844       }
 845     }
 846   }
 847 }
 848
 849
 850 void div64(int64_t dividend,int64_t divisor)
 851 {
 852   lo=dividend/divisor;
 853   hi=dividend%divisor;
 854   //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
 855   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 856 }
 857 void divu64(uint64_t dividend,uint64_t divisor)
 858 {
 859   lo=dividend/divisor;
 860   hi=dividend%divisor;
 861   //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 862   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 863 }
 864
 865 void mult64(uint64_t m1,uint64_t m2)
 866 {
 867    unsigned long long int op1, op2, op3, op4;
 868    unsigned long long int result1, result2, result3, result4;
 869    unsigned long long int temp1, temp2, temp3, temp4;
 870    int sign = 0;
 871
 872    if (m1 < 0)
 873      {
 874     op2 = -m1;
 875     sign = 1 - sign;
 876      }
 877    else op2 = m1;
 878    if (m2 < 0)
 879      {
 880     op4 = -m2;
 881     sign = 1 - sign;
 882      }
 883    else op4 = m2;
 884
 885    op1 = op2 & 0xFFFFFFFF;
 886    op2 = (op2 >> 32) & 0xFFFFFFFF;
 887    op3 = op4 & 0xFFFFFFFF;
 888    op4 = (op4 >> 32) & 0xFFFFFFFF;
 889
 890    temp1 = op1 * op3;
 891    temp2 = (temp1 >> 32) + op1 * op4;
 892    temp3 = op2 * op3;
 893    temp4 = (temp3 >> 32) + op2 * op4;
 894
 895    result1 = temp1 & 0xFFFFFFFF;
 896    result2 = temp2 + (temp3 & 0xFFFFFFFF);
 897    result3 = (result2 >> 32) + temp4;
 898    result4 = (result3 >> 32);
 899
 900    lo = result1 | (result2 << 32);
 901    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
 902    if (sign)
 903      {
 904     hi = ~hi;
 905     if (!lo) hi++;
 906     else lo = ~lo + 1;
 907      }
 908 }
 909
 910 void multu64(uint64_t m1,uint64_t m2)
 911 {
 912    unsigned long long int op1, op2, op3, op4;
 913    unsigned long long int result1, result2, result3, result4;
 914    unsigned long long int temp1, temp2, temp3, temp4;
 915
 916    op1 = m1 & 0xFFFFFFFF;
 917    op2 = (m1 >> 32) & 0xFFFFFFFF;
 918    op3 = m2 & 0xFFFFFFFF;
 919    op4 = (m2 >> 32) & 0xFFFFFFFF;
 920
 921    temp1 = op1 * op3;
 922    temp2 = (temp1 >> 32) + op1 * op4;
 923    temp3 = op2 * op3;
 924    temp4 = (temp3 >> 32) + op2 * op4;
 925
 926    result1 = temp1 & 0xFFFFFFFF;
 927    result2 = temp2 + (temp3 & 0xFFFFFFFF);
 928    result3 = (result2 >> 32) + temp4;
 929    result4 = (result3 >> 32);
 930
 931    lo = result1 | (result2 << 32);
 932    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
 933
 934   //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 935   //                                      ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 936 }
 937
 938 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
 939 {
 940   if(bits) {
 941     original<<=64-bits;
 942     original>>=64-bits;
 943     loaded<<=bits;
 944     original|=loaded;
 945   }
 946   else original=loaded;
 947   return original;
 948 }
 949 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
 950 {
 951   if(bits^56) {
 952     original>>=64-(bits^56);
 953     original<<=64-(bits^56);
 954     loaded>>=bits^56;
 955     original|=loaded;
 956   }
 957   else original=loaded;
 958   return original;
 959 }
 960
 961 #ifdef __i386__
 962 #include "assem_x86.c"
 963 #endif
 964 #ifdef __x86_64__
 965 #include "assem_x64.c"
 966 #endif
 967 #ifdef __arm__
 968 #include "assem_arm.c"
 969 #endif
 970
 971 // Add virtual address mapping to linked list
 972 void ll_add(struct ll_entry **head,int vaddr,void *addr)
 973 {
 974   struct ll_entry *new_entry;
 975   new_entry=malloc(sizeof(struct ll_entry));
 976   assert(new_entry!=NULL);
 977   new_entry->vaddr=vaddr;
 978   new_entry->reg32=0;
 979   new_entry->addr=addr;
 980   new_entry->next=*head;
 981   *head=new_entry;
 982 }
 983
 984 // Add virtual address mapping for 32-bit compiled block
 985 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
 986 {
 987   ll_add(head,vaddr,addr);
 988 #ifndef FORCE32
 989   (*head)->reg32=reg32;
 990 #endif
 991 }
 992
 993 // Check if an address is already compiled
 994 // but don't return addresses which are about to expire from the cache
 995 void *check_addr(u_int vaddr)
 996 {
 997   u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 998   if(ht_bin[0]==vaddr) {
 999     if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1000       if(isclean(ht_bin[1])) return (void *)ht_bin[1];
1001   }
1002   if(ht_bin[2]==vaddr) {
1003     if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1004       if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1005   }
1006   u_int page=get_page(vaddr);
1007   struct ll_entry *head;
1008   head=jump_in[page];
1009   while(head!=NULL) {
1010     if(head->vaddr==vaddr&&head->reg32==0) {
1011       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1012         // Update existing entry with current address
1013         if(ht_bin[0]==vaddr) {
1014           ht_bin[1]=(int)head->addr;
1015           return head->addr;
1016         }
1017         if(ht_bin[2]==vaddr) {
1018           ht_bin[3]=(int)head->addr;
1019           return head->addr;
1020         }
1021         // Insert into hash table with low priority.
1022         // Don't evict existing entries, as they are probably
1023         // addresses that are being accessed frequently.
1024         if(ht_bin[0]==-1) {
1025           ht_bin[1]=(int)head->addr;
1026           ht_bin[0]=vaddr;
1027         }else if(ht_bin[2]==-1) {
1028           ht_bin[3]=(int)head->addr;
1029           ht_bin[2]=vaddr;
1030         }
1031         return head->addr;
1032       }
1033     }
1034     head=head->next;
1035   }
1036   return 0;
1037 }
1038
1039 void remove_hash(int vaddr)
1040 {
1041   //printf("remove hash: %x\n",vaddr);
1042   int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1043   if(ht_bin[2]==vaddr) {
1044     ht_bin[2]=ht_bin[3]=-1;
1045   }
1046   if(ht_bin[0]==vaddr) {
1047     ht_bin[0]=ht_bin[2];
1048     ht_bin[1]=ht_bin[3];
1049     ht_bin[2]=ht_bin[3]=-1;
1050   }
1051 }
1052
1053 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1054 {
1055   struct ll_entry *next;
1056   while(*head) {
1057     if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1058        ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1059     {
1060       inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1061       remove_hash((*head)->vaddr);
1062       next=(*head)->next;
1063       free(*head);
1064       *head=next;
1065     }
1066     else
1067     {
1068       head=&((*head)->next);
1069     }
1070   }
1071 }
1072
1073 // Remove all entries from linked list
1074 void ll_clear(struct ll_entry **head)
1075 {
1076   struct ll_entry *cur;
1077   struct ll_entry *next;
1078   if(cur=*head) {
1079     *head=0;
1080     while(cur) {
1081       next=cur->next;
1082       free(cur);
1083       cur=next;
1084     }
1085   }
1086 }
1087
1088 // Dereference the pointers and remove if it matches
1089 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1090 {
1091   while(head) {
1092     int ptr=get_pointer(head->addr);
1093     inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1094     if(((ptr>>shift)==(addr>>shift)) ||
1095        (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1096     {
1097       inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1098       u_int host_addr=(u_int)kill_pointer(head->addr);
1099       #ifdef __arm__
1100         needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1101       #endif
1102     }
1103     head=head->next;
1104   }
1105 }
1106
1107 // This is called when we write to a compiled block (see do_invstub)
1108 void invalidate_page(u_int page)
1109 {
1110   struct ll_entry *head;
1111   struct ll_entry *next;
1112   head=jump_in[page];
1113   jump_in[page]=0;
1114   while(head!=NULL) {
1115     inv_debug("INVALIDATE: %x\n",head->vaddr);
1116     remove_hash(head->vaddr);
1117     next=head->next;
1118     free(head);
1119     head=next;
1120   }
1121   head=jump_out[page];
1122   jump_out[page]=0;
1123   while(head!=NULL) {
1124     inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1125     u_int host_addr=(u_int)kill_pointer(head->addr);
1126     #ifdef __arm__
1127       needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1128     #endif
1129     next=head->next;
1130     free(head);
1131     head=next;
1132   }
1133 }
1134 void invalidate_block(u_int block)
1135 {
1136   u_int page=get_page(block<<12);
1137   u_int vpage=get_vpage(block<<12);
1138   inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1139   //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1140   u_int first,last;
1141   first=last=page;
1142   struct ll_entry *head;
1143   head=jump_dirty[vpage];
1144   //printf("page=%d vpage=%d\n",page,vpage);
1145   while(head!=NULL) {
1146     u_int start,end;
1147     if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1148       get_bounds((int)head->addr,&start,&end);
1149       //printf("start: %x end: %x\n",start,end);
1150       if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
1151         if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1152           if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1153           if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1154         }
1155       }
1156 #ifndef DISABLE_TLB
1157       if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1158         if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1159           if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1160           if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1161         }
1162       }
1163 #endif
1164     }
1165     head=head->next;
1166   }
1167   //printf("first=%d last=%d\n",first,last);
1168   invalidate_page(page);
1169   assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1170   assert(last<page+5);
1171   // Invalidate the adjacent pages if a block crosses a 4K boundary
1172   while(first<page) {
1173     invalidate_page(first);
1174     first++;
1175   }
1176   for(first=page+1;first<last;first++) {
1177     invalidate_page(first);
1178   }
1179   #ifdef __arm__
1180     do_clear_cache();
1181   #endif
1182
1183   // Don't trap writes
1184   invalid_code[block]=1;
1185 #ifdef PCSX
1186   invalid_code[((u_int)0x80000000>>12)|page]=1;
1187 #endif
1188 #ifndef DISABLE_TLB
1189   // If there is a valid TLB entry for this page, remove write protect
1190   if(tlb_LUT_w[block]) {
1191     assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1192     // CHECK: Is this right?
1193     memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1194     u_int real_block=tlb_LUT_w[block]>>12;
1195     invalid_code[real_block]=1;
1196     if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1197   }
1198   else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1199 #endif
1200
1201   #ifdef USE_MINI_HT
1202   memset(mini_ht,-1,sizeof(mini_ht));
1203   #endif
1204 }
1205 void invalidate_addr(u_int addr)
1206 {
1207   invalidate_block(addr>>12);
1208 }
1209 // This is called when loading a save state.
1210 // Anything could have changed, so invalidate everything.
1211 void invalidate_all_pages()
1212 {
1213   u_int page,n;
1214   for(page=0;page<4096;page++)
1215     invalidate_page(page);
1216   for(page=0;page<1048576;page++)
1217     if(!invalid_code[page]) {
1218       restore_candidate[(page&2047)>>3]|=1<<(page&7);
1219       restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1220     }
1221   #ifdef __arm__
1222   __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1223   #endif
1224   #ifdef USE_MINI_HT
1225   memset(mini_ht,-1,sizeof(mini_ht));
1226   #endif
1227   #ifndef DISABLE_TLB
1228   // TLB
1229   for(page=0;page<0x100000;page++) {
1230     if(tlb_LUT_r[page]) {
1231       memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1232       if(!tlb_LUT_w[page]||!invalid_code[page])
1233         memory_map[page]|=0x40000000; // Write protect
1234     }
1235     else memory_map[page]=-1;
1236     if(page==0x80000) page=0xC0000;
1237   }
1238   tlb_hacks();
1239   #endif
1240 }
1241
1242 // Add an entry to jump_out after making a link
1243 void add_link(u_int vaddr,void *src)
1244 {
1245   u_int page=get_page(vaddr);
1246   inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1247   ll_add(jump_out+page,vaddr,src);
1248   //int ptr=get_pointer(src);
1249   //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1250 }
1251
1252 // If a code block was found to be unmodified (bit was set in
1253 // restore_candidate) and it remains unmodified (bit is clear
1254 // in invalid_code) then move the entries for that 4K page from
1255 // the dirty list to the clean list.
1256 void clean_blocks(u_int page)
1257 {
1258   struct ll_entry *head;
1259   inv_debug("INV: clean_blocks page=%d\n",page);
1260   head=jump_dirty[page];
1261   while(head!=NULL) {
1262     if(!invalid_code[head->vaddr>>12]) {
1263       // Don't restore blocks which are about to expire from the cache
1264       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1265         u_int start,end;
1266         if(verify_dirty((int)head->addr)) {
1267           //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1268           u_int i;
1269           u_int inv=0;
1270           get_bounds((int)head->addr,&start,&end);
1271           if(start-(u_int)rdram<RAM_SIZE) {
1272             for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1273               inv|=invalid_code[i];
1274             }
1275           }
1276           if((signed int)head->vaddr>=(signed int)0xC0000000) {
1277             u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1278             //printf("addr=%x start=%x end=%x\n",addr,start,end);
1279             if(addr<start||addr>=end) inv=1;
1280           }
1281           else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1282             inv=1;
1283           }
1284           if(!inv) {
1285             void * clean_addr=(void *)get_clean_addr((int)head->addr);
1286             if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1287               u_int ppage=page;
1288 #ifndef DISABLE_TLB
1289               if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1290 #endif
1291               inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1292               //printf("page=%x, addr=%x\n",page,head->vaddr);
1293               //assert(head->vaddr>>12==(page|0x80000));
1294               ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1295               int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1296               if(!head->reg32) {
1297                 if(ht_bin[0]==head->vaddr) {
1298                   ht_bin[1]=(int)clean_addr; // Replace existing entry
1299                 }
1300                 if(ht_bin[2]==head->vaddr) {
1301                   ht_bin[3]=(int)clean_addr; // Replace existing entry
1302                 }
1303               }
1304             }
1305           }
1306         }
1307       }
1308     }
1309     head=head->next;
1310   }
1311 }
1312
1313
1314 void mov_alloc(struct regstat *current,int i)
1315 {
1316   // Note: Don't need to actually alloc the source registers
1317   if((~current->is32>>rs1[i])&1) {
1318     //alloc_reg64(current,i,rs1[i]);
1319     alloc_reg64(current,i,rt1[i]);
1320     current->is32&=~(1LL<<rt1[i]);
1321   } else {
1322     //alloc_reg(current,i,rs1[i]);
1323     alloc_reg(current,i,rt1[i]);
1324     current->is32|=(1LL<<rt1[i]);
1325   }
1326   clear_const(current,rs1[i]);
1327   clear_const(current,rt1[i]);
1328   dirty_reg(current,rt1[i]);
1329 }
1330
1331 void shiftimm_alloc(struct regstat *current,int i)
1332 {
1333   clear_const(current,rs1[i]);
1334   clear_const(current,rt1[i]);
1335   if(opcode2[i]<=0x3) // SLL/SRL/SRA
1336   {
1337     if(rt1[i]) {
1338       if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1339       else lt1[i]=rs1[i];
1340       alloc_reg(current,i,rt1[i]);
1341       current->is32|=1LL<<rt1[i];
1342       dirty_reg(current,rt1[i]);
1343     }
1344   }
1345   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1346   {
1347     if(rt1[i]) {
1348       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1349       alloc_reg64(current,i,rt1[i]);
1350       current->is32&=~(1LL<<rt1[i]);
1351       dirty_reg(current,rt1[i]);
1352     }
1353   }
1354   if(opcode2[i]==0x3c) // DSLL32
1355   {
1356     if(rt1[i]) {
1357       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1358       alloc_reg64(current,i,rt1[i]);
1359       current->is32&=~(1LL<<rt1[i]);
1360       dirty_reg(current,rt1[i]);
1361     }
1362   }
1363   if(opcode2[i]==0x3e) // DSRL32
1364   {
1365     if(rt1[i]) {
1366       alloc_reg64(current,i,rs1[i]);
1367       if(imm[i]==32) {
1368         alloc_reg64(current,i,rt1[i]);
1369         current->is32&=~(1LL<<rt1[i]);
1370       } else {
1371         alloc_reg(current,i,rt1[i]);
1372         current->is32|=1LL<<rt1[i];
1373       }
1374       dirty_reg(current,rt1[i]);
1375     }
1376   }
1377   if(opcode2[i]==0x3f) // DSRA32
1378   {
1379     if(rt1[i]) {
1380       alloc_reg64(current,i,rs1[i]);
1381       alloc_reg(current,i,rt1[i]);
1382       current->is32|=1LL<<rt1[i];
1383       dirty_reg(current,rt1[i]);
1384     }
1385   }
1386 }
1387
1388 void shift_alloc(struct regstat *current,int i)
1389 {
1390   if(rt1[i]) {
1391     if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1392     {
1393       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1394       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1395       alloc_reg(current,i,rt1[i]);
1396       if(rt1[i]==rs2[i]) {
1397         alloc_reg_temp(current,i,-1);
1398         minimum_free_regs[i]=1;
1399       }
1400       current->is32|=1LL<<rt1[i];
1401     } else { // DSLLV/DSRLV/DSRAV
1402       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1403       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1404       alloc_reg64(current,i,rt1[i]);
1405       current->is32&=~(1LL<<rt1[i]);
1406       if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1407       {
1408         alloc_reg_temp(current,i,-1);
1409         minimum_free_regs[i]=1;
1410       }
1411     }
1412     clear_const(current,rs1[i]);
1413     clear_const(current,rs2[i]);
1414     clear_const(current,rt1[i]);
1415     dirty_reg(current,rt1[i]);
1416   }
1417 }
1418
1419 void alu_alloc(struct regstat *current,int i)
1420 {
1421   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1422     if(rt1[i]) {
1423       if(rs1[i]&&rs2[i]) {
1424         alloc_reg(current,i,rs1[i]);
1425         alloc_reg(current,i,rs2[i]);
1426       }
1427       else {
1428         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1429         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1430       }
1431       alloc_reg(current,i,rt1[i]);
1432     }
1433     current->is32|=1LL<<rt1[i];
1434   }
1435   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1436     if(rt1[i]) {
1437       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1438       {
1439         alloc_reg64(current,i,rs1[i]);
1440         alloc_reg64(current,i,rs2[i]);
1441         alloc_reg(current,i,rt1[i]);
1442       } else {
1443         alloc_reg(current,i,rs1[i]);
1444         alloc_reg(current,i,rs2[i]);
1445         alloc_reg(current,i,rt1[i]);
1446       }
1447     }
1448     current->is32|=1LL<<rt1[i];
1449   }
1450   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1451     if(rt1[i]) {
1452       if(rs1[i]&&rs2[i]) {
1453         alloc_reg(current,i,rs1[i]);
1454         alloc_reg(current,i,rs2[i]);
1455       }
1456       else
1457       {
1458         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1459         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1460       }
1461       alloc_reg(current,i,rt1[i]);
1462       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1463       {
1464         if(!((current->uu>>rt1[i])&1)) {
1465           alloc_reg64(current,i,rt1[i]);
1466         }
1467         if(get_reg(current->regmap,rt1[i]|64)>=0) {
1468           if(rs1[i]&&rs2[i]) {
1469             alloc_reg64(current,i,rs1[i]);
1470             alloc_reg64(current,i,rs2[i]);
1471           }
1472           else
1473           {
1474             // Is is really worth it to keep 64-bit values in registers?
1475             #ifdef NATIVE_64BIT
1476             if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1477             if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1478             #endif
1479           }
1480         }
1481         current->is32&=~(1LL<<rt1[i]);
1482       } else {
1483         current->is32|=1LL<<rt1[i];
1484       }
1485     }
1486   }
1487   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1488     if(rt1[i]) {
1489       if(rs1[i]&&rs2[i]) {
1490         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1491           alloc_reg64(current,i,rs1[i]);
1492           alloc_reg64(current,i,rs2[i]);
1493           alloc_reg64(current,i,rt1[i]);
1494         } else {
1495           alloc_reg(current,i,rs1[i]);
1496           alloc_reg(current,i,rs2[i]);
1497           alloc_reg(current,i,rt1[i]);
1498         }
1499       }
1500       else {
1501         alloc_reg(current,i,rt1[i]);
1502         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1503           // DADD used as move, or zeroing
1504           // If we have a 64-bit source, then make the target 64 bits too
1505           if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1506             if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1507             alloc_reg64(current,i,rt1[i]);
1508           } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1509             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1510             alloc_reg64(current,i,rt1[i]);
1511           }
1512           if(opcode2[i]>=0x2e&&rs2[i]) {
1513             // DSUB used as negation - 64-bit result
1514             // If we have a 32-bit register, extend it to 64 bits
1515             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1516             alloc_reg64(current,i,rt1[i]);
1517           }
1518         }
1519       }
1520       if(rs1[i]&&rs2[i]) {
1521         current->is32&=~(1LL<<rt1[i]);
1522       } else if(rs1[i]) {
1523         current->is32&=~(1LL<<rt1[i]);
1524         if((current->is32>>rs1[i])&1)
1525           current->is32|=1LL<<rt1[i];
1526       } else if(rs2[i]) {
1527         current->is32&=~(1LL<<rt1[i]);
1528         if((current->is32>>rs2[i])&1)
1529           current->is32|=1LL<<rt1[i];
1530       } else {
1531         current->is32|=1LL<<rt1[i];
1532       }
1533     }
1534   }
1535   clear_const(current,rs1[i]);
1536   clear_const(current,rs2[i]);
1537   clear_const(current,rt1[i]);
1538   dirty_reg(current,rt1[i]);
1539 }
1540
1541 void imm16_alloc(struct regstat *current,int i)
1542 {
1543   if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1544   else lt1[i]=rs1[i];
1545   if(rt1[i]) alloc_reg(current,i,rt1[i]);
1546   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1547     current->is32&=~(1LL<<rt1[i]);
1548     if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1549       // TODO: Could preserve the 32-bit flag if the immediate is zero
1550       alloc_reg64(current,i,rt1[i]);
1551       alloc_reg64(current,i,rs1[i]);
1552     }
1553     clear_const(current,rs1[i]);
1554     clear_const(current,rt1[i]);
1555   }
1556   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1557     if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1558     current->is32|=1LL<<rt1[i];
1559     clear_const(current,rs1[i]);
1560     clear_const(current,rt1[i]);
1561   }
1562   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1563     if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1564       if(rs1[i]!=rt1[i]) {
1565         if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1566         alloc_reg64(current,i,rt1[i]);
1567         current->is32&=~(1LL<<rt1[i]);
1568       }
1569     }
1570     else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1571     if(is_const(current,rs1[i])) {
1572       int v=get_const(current,rs1[i]);
1573       if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1574       if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1575       if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1576     }
1577     else clear_const(current,rt1[i]);
1578   }
1579   else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1580     if(is_const(current,rs1[i])) {
1581       int v=get_const(current,rs1[i]);
1582       set_const(current,rt1[i],v+imm[i]);
1583     }
1584     else clear_const(current,rt1[i]);
1585     current->is32|=1LL<<rt1[i];
1586   }
1587   else {
1588     set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1589     current->is32|=1LL<<rt1[i];
1590   }
1591   dirty_reg(current,rt1[i]);
1592 }
1593
1594 void load_alloc(struct regstat *current,int i)
1595 {
1596   clear_const(current,rt1[i]);
1597   //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1598   if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1599   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1600   if(rt1[i]&&!((current->u>>rt1[i])&1)) {
1601     alloc_reg(current,i,rt1[i]);
1602     assert(get_reg(current->regmap,rt1[i])>=0);
1603     if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1604     {
1605       current->is32&=~(1LL<<rt1[i]);
1606       alloc_reg64(current,i,rt1[i]);
1607     }
1608     else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1609     {
1610       current->is32&=~(1LL<<rt1[i]);
1611       alloc_reg64(current,i,rt1[i]);
1612       alloc_all(current,i);
1613       alloc_reg64(current,i,FTEMP);
1614       minimum_free_regs[i]=HOST_REGS;
1615     }
1616     else current->is32|=1LL<<rt1[i];
1617     dirty_reg(current,rt1[i]);
1618     // If using TLB, need a register for pointer to the mapping table
1619     if(using_tlb) alloc_reg(current,i,TLREG);
1620     // LWL/LWR need a temporary register for the old value
1621     if(opcode[i]==0x22||opcode[i]==0x26)
1622     {
1623       alloc_reg(current,i,FTEMP);
1624       alloc_reg_temp(current,i,-1);
1625       minimum_free_regs[i]=1;
1626     }
1627   }
1628   else
1629   {
1630     // Load to r0 or unneeded register (dummy load)
1631     // but we still need a register to calculate the address
1632     if(opcode[i]==0x22||opcode[i]==0x26)
1633     {
1634       alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1635     }
1636     // If using TLB, need a register for pointer to the mapping table
1637     if(using_tlb) alloc_reg(current,i,TLREG);
1638     alloc_reg_temp(current,i,-1);
1639     minimum_free_regs[i]=1;
1640     if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1641     {
1642       alloc_all(current,i);
1643       alloc_reg64(current,i,FTEMP);
1644       minimum_free_regs[i]=HOST_REGS;
1645     }
1646   }
1647 }
1648
1649 void store_alloc(struct regstat *current,int i)
1650 {
1651   clear_const(current,rs2[i]);
1652   if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1653   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1654   alloc_reg(current,i,rs2[i]);
1655   if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1656     alloc_reg64(current,i,rs2[i]);
1657     if(rs2[i]) alloc_reg(current,i,FTEMP);
1658   }
1659   // If using TLB, need a register for pointer to the mapping table
1660   if(using_tlb) alloc_reg(current,i,TLREG);
1661   #if defined(HOST_IMM8)
1662   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1663   else alloc_reg(current,i,INVCP);
1664   #endif
1665   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1666     alloc_reg(current,i,FTEMP);
1667   }
1668   // We need a temporary register for address generation
1669   alloc_reg_temp(current,i,-1);
1670   minimum_free_regs[i]=1;
1671 }
1672
1673 void c1ls_alloc(struct regstat *current,int i)
1674 {
1675   //clear_const(current,rs1[i]); // FIXME
1676   clear_const(current,rt1[i]);
1677   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1678   alloc_reg(current,i,CSREG); // Status
1679   alloc_reg(current,i,FTEMP);
1680   if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1681     alloc_reg64(current,i,FTEMP);
1682   }
1683   // If using TLB, need a register for pointer to the mapping table
1684   if(using_tlb) alloc_reg(current,i,TLREG);
1685   #if defined(HOST_IMM8)
1686   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1687   else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1688     alloc_reg(current,i,INVCP);
1689   #endif
1690   // We need a temporary register for address generation
1691   alloc_reg_temp(current,i,-1);
1692 }
1693
1694 void c2ls_alloc(struct regstat *current,int i)
1695 {
1696   clear_const(current,rt1[i]);
1697   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1698   alloc_reg(current,i,FTEMP);
1699   // If using TLB, need a register for pointer to the mapping table
1700   if(using_tlb) alloc_reg(current,i,TLREG);
1701   #if defined(HOST_IMM8)
1702   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1703   else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1704     alloc_reg(current,i,INVCP);
1705   #endif
1706   // We need a temporary register for address generation
1707   alloc_reg_temp(current,i,-1);
1708   minimum_free_regs[i]=1;
1709 }
1710
1711 #ifndef multdiv_alloc
1712 void multdiv_alloc(struct regstat *current,int i)
1713 {
1714   //  case 0x18: MULT
1715   //  case 0x19: MULTU
1716   //  case 0x1A: DIV
1717   //  case 0x1B: DIVU
1718   //  case 0x1C: DMULT
1719   //  case 0x1D: DMULTU
1720   //  case 0x1E: DDIV
1721   //  case 0x1F: DDIVU
1722   clear_const(current,rs1[i]);
1723   clear_const(current,rs2[i]);
1724   if(rs1[i]&&rs2[i])
1725   {
1726     if((opcode2[i]&4)==0) // 32-bit
1727     {
1728       current->u&=~(1LL<<HIREG);
1729       current->u&=~(1LL<<LOREG);
1730       alloc_reg(current,i,HIREG);
1731       alloc_reg(current,i,LOREG);
1732       alloc_reg(current,i,rs1[i]);
1733       alloc_reg(current,i,rs2[i]);
1734       current->is32|=1LL<<HIREG;
1735       current->is32|=1LL<<LOREG;
1736       dirty_reg(current,HIREG);
1737       dirty_reg(current,LOREG);
1738     }
1739     else // 64-bit
1740     {
1741       current->u&=~(1LL<<HIREG);
1742       current->u&=~(1LL<<LOREG);
1743       current->uu&=~(1LL<<HIREG);
1744       current->uu&=~(1LL<<LOREG);
1745       alloc_reg64(current,i,HIREG);
1746       //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1747       alloc_reg64(current,i,rs1[i]);
1748       alloc_reg64(current,i,rs2[i]);
1749       alloc_all(current,i);
1750       current->is32&=~(1LL<<HIREG);
1751       current->is32&=~(1LL<<LOREG);
1752       dirty_reg(current,HIREG);
1753       dirty_reg(current,LOREG);
1754       minimum_free_regs[i]=HOST_REGS;
1755     }
1756   }
1757   else
1758   {
1759     // Multiply by zero is zero.
1760     // MIPS does not have a divide by zero exception.
1761     // The result is undefined, we return zero.
1762     alloc_reg(current,i,HIREG);
1763     alloc_reg(current,i,LOREG);
1764     current->is32|=1LL<<HIREG;
1765     current->is32|=1LL<<LOREG;
1766     dirty_reg(current,HIREG);
1767     dirty_reg(current,LOREG);
1768   }
1769 }
1770 #endif
1771
1772 void cop0_alloc(struct regstat *current,int i)
1773 {
1774   if(opcode2[i]==0) // MFC0
1775   {
1776     if(rt1[i]) {
1777       clear_const(current,rt1[i]);
1778       alloc_all(current,i);
1779       alloc_reg(current,i,rt1[i]);
1780       current->is32|=1LL<<rt1[i];
1781       dirty_reg(current,rt1[i]);
1782     }
1783   }
1784   else if(opcode2[i]==4) // MTC0
1785   {
1786     if(rs1[i]){
1787       clear_const(current,rs1[i]);
1788       alloc_reg(current,i,rs1[i]);
1789       alloc_all(current,i);
1790     }
1791     else {
1792       alloc_all(current,i); // FIXME: Keep r0
1793       current->u&=~1LL;
1794       alloc_reg(current,i,0);
1795     }
1796   }
1797   else
1798   {
1799     // TLBR/TLBWI/TLBWR/TLBP/ERET
1800     assert(opcode2[i]==0x10);
1801     alloc_all(current,i);
1802   }
1803   minimum_free_regs[i]=HOST_REGS;
1804 }
1805
1806 void cop1_alloc(struct regstat *current,int i)
1807 {
1808   alloc_reg(current,i,CSREG); // Load status
1809   if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1810   {
1811     if(rt1[i]){
1812       clear_const(current,rt1[i]);
1813       if(opcode2[i]==1) {
1814         alloc_reg64(current,i,rt1[i]); // DMFC1
1815         current->is32&=~(1LL<<rt1[i]);
1816       }else{
1817         alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1818         current->is32|=1LL<<rt1[i];
1819       }
1820       dirty_reg(current,rt1[i]);
1821     }
1822     alloc_reg_temp(current,i,-1);
1823   }
1824   else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1825   {
1826     if(rs1[i]){
1827       clear_const(current,rs1[i]);
1828       if(opcode2[i]==5)
1829         alloc_reg64(current,i,rs1[i]); // DMTC1
1830       else
1831         alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1832       alloc_reg_temp(current,i,-1);
1833     }
1834     else {
1835       current->u&=~1LL;
1836       alloc_reg(current,i,0);
1837       alloc_reg_temp(current,i,-1);
1838     }
1839   }
1840   minimum_free_regs[i]=1;
1841 }
1842 void fconv_alloc(struct regstat *current,int i)
1843 {
1844   alloc_reg(current,i,CSREG); // Load status
1845   alloc_reg_temp(current,i,-1);
1846   minimum_free_regs[i]=1;
1847 }
1848 void float_alloc(struct regstat *current,int i)
1849 {
1850   alloc_reg(current,i,CSREG); // Load status
1851   alloc_reg_temp(current,i,-1);
1852   minimum_free_regs[i]=1;
1853 }
1854 void c2op_alloc(struct regstat *current,int i)
1855 {
1856   alloc_reg_temp(current,i,-1);
1857 }
1858 void fcomp_alloc(struct regstat *current,int i)
1859 {
1860   alloc_reg(current,i,CSREG); // Load status
1861   alloc_reg(current,i,FSREG); // Load flags
1862   dirty_reg(current,FSREG); // Flag will be modified
1863   alloc_reg_temp(current,i,-1);
1864   minimum_free_regs[i]=1;
1865 }
1866
1867 void syscall_alloc(struct regstat *current,int i)
1868 {
1869   alloc_cc(current,i);
1870   dirty_reg(current,CCREG);
1871   alloc_all(current,i);
1872   minimum_free_regs[i]=HOST_REGS;
1873   current->isconst=0;
1874 }
1875
1876 void delayslot_alloc(struct regstat *current,int i)
1877 {
1878   switch(itype[i]) {
1879     case UJUMP:
1880     case CJUMP:
1881     case SJUMP:
1882     case RJUMP:
1883     case FJUMP:
1884     case SYSCALL:
1885     case HLECALL:
1886     case SPAN:
1887       assem_debug("jump in the delay slot.  this shouldn't happen.\n");//exit(1);
1888       printf("Disabled speculative precompilation\n");
1889       stop_after_jal=1;
1890       break;
1891     case IMM16:
1892       imm16_alloc(current,i);
1893       break;
1894     case LOAD:
1895     case LOADLR:
1896       load_alloc(current,i);
1897       break;
1898     case STORE:
1899     case STORELR:
1900       store_alloc(current,i);
1901       break;
1902     case ALU:
1903       alu_alloc(current,i);
1904       break;
1905     case SHIFT:
1906       shift_alloc(current,i);
1907       break;
1908     case MULTDIV:
1909       multdiv_alloc(current,i);
1910       break;
1911     case SHIFTIMM:
1912       shiftimm_alloc(current,i);
1913       break;
1914     case MOV:
1915       mov_alloc(current,i);
1916       break;
1917     case COP0:
1918       cop0_alloc(current,i);
1919       break;
1920     case COP1:
1921     case COP2:
1922       cop1_alloc(current,i);
1923       break;
1924     case C1LS:
1925       c1ls_alloc(current,i);
1926       break;
1927     case C2LS:
1928       c2ls_alloc(current,i);
1929       break;
1930     case FCONV:
1931       fconv_alloc(current,i);
1932       break;
1933     case FLOAT:
1934       float_alloc(current,i);
1935       break;
1936     case FCOMP:
1937       fcomp_alloc(current,i);
1938       break;
1939     case C2OP:
1940       c2op_alloc(current,i);
1941       break;
1942   }
1943 }
1944
1945 // Special case where a branch and delay slot span two pages in virtual memory
1946 static void pagespan_alloc(struct regstat *current,int i)
1947 {
1948   current->isconst=0;
1949   current->wasconst=0;
1950   regs[i].wasconst=0;
1951   minimum_free_regs[i]=HOST_REGS;
1952   alloc_all(current,i);
1953   alloc_cc(current,i);
1954   dirty_reg(current,CCREG);
1955   if(opcode[i]==3) // JAL
1956   {
1957     alloc_reg(current,i,31);
1958     dirty_reg(current,31);
1959   }
1960   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1961   {
1962     alloc_reg(current,i,rs1[i]);
1963     if (rt1[i]!=0) {
1964       alloc_reg(current,i,rt1[i]);
1965       dirty_reg(current,rt1[i]);
1966     }
1967   }
1968   if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1969   {
1970     if(rs1[i]) alloc_reg(current,i,rs1[i]);
1971     if(rs2[i]) alloc_reg(current,i,rs2[i]);
1972     if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1973     {
1974       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1975       if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1976     }
1977   }
1978   else
1979   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1980   {
1981     if(rs1[i]) alloc_reg(current,i,rs1[i]);
1982     if(!((current->is32>>rs1[i])&1))
1983     {
1984       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1985     }
1986   }
1987   else
1988   if(opcode[i]==0x11) // BC1
1989   {
1990     alloc_reg(current,i,FSREG);
1991     alloc_reg(current,i,CSREG);
1992   }
1993   //else ...
1994 }
1995
1996 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
1997 {
1998   stubs[stubcount][0]=type;
1999   stubs[stubcount][1]=addr;
2000   stubs[stubcount][2]=retaddr;
2001   stubs[stubcount][3]=a;
2002   stubs[stubcount][4]=b;
2003   stubs[stubcount][5]=c;
2004   stubs[stubcount][6]=d;
2005   stubs[stubcount][7]=e;
2006   stubcount++;
2007 }
2008
2009 // Write out a single register
2010 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2011 {
2012   int hr;
2013   for(hr=0;hr<HOST_REGS;hr++) {
2014     if(hr!=EXCLUDE_REG) {
2015       if((regmap[hr]&63)==r) {
2016         if((dirty>>hr)&1) {
2017           if(regmap[hr]<64) {
2018             emit_storereg(r,hr);
2019 #ifndef FORCE32
2020             if((is32>>regmap[hr])&1) {
2021               emit_sarimm(hr,31,hr);
2022               emit_storereg(r|64,hr);
2023             }
2024 #endif
2025           }else{
2026             emit_storereg(r|64,hr);
2027           }
2028         }
2029       }
2030     }
2031   }
2032 }
2033
2034 int mchecksum()
2035 {
2036   //if(!tracedebug) return 0;
2037   int i;
2038   int sum=0;
2039   for(i=0;i<2097152;i++) {
2040     unsigned int temp=sum;
2041     sum<<=1;
2042     sum|=(~temp)>>31;
2043     sum^=((u_int *)rdram)[i];
2044   }
2045   return sum;
2046 }
2047 int rchecksum()
2048 {
2049   int i;
2050   int sum=0;
2051   for(i=0;i<64;i++)
2052     sum^=((u_int *)reg)[i];
2053   return sum;
2054 }
2055 void rlist()
2056 {
2057   int i;
2058   printf("TRACE: ");
2059   for(i=0;i<32;i++)
2060     printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2061   printf("\n");
2062 #ifndef DISABLE_COP1
2063   printf("TRACE: ");
2064   for(i=0;i<32;i++)
2065     printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2066   printf("\n");
2067 #endif
2068 }
2069
2070 void enabletrace()
2071 {
2072   tracedebug=1;
2073 }
2074
2075 void memdebug(int i)
2076 {
2077   //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2078   //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2079   //rlist();
2080   //if(tracedebug) {
2081   //if(Count>=-2084597794) {
2082   if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2083   //if(0) {
2084     printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2085     //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2086     //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2087     rlist();
2088     #ifdef __i386__
2089     printf("TRACE: %x\n",(&i)[-1]);
2090     #endif
2091     #ifdef __arm__
2092     int j;
2093     printf("TRACE: %x \n",(&j)[10]);
2094     printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2095     #endif
2096     //fflush(stdout);
2097   }
2098   //printf("TRACE: %x\n",(&i)[-1]);
2099 }
2100
2101 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2102 {
2103   printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2104 }
2105
2106 void alu_assemble(int i,struct regstat *i_regs)
2107 {
2108   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2109     if(rt1[i]) {
2110       signed char s1,s2,t;
2111       t=get_reg(i_regs->regmap,rt1[i]);
2112       if(t>=0) {
2113         s1=get_reg(i_regs->regmap,rs1[i]);
2114         s2=get_reg(i_regs->regmap,rs2[i]);
2115         if(rs1[i]&&rs2[i]) {
2116           assert(s1>=0);
2117           assert(s2>=0);
2118           if(opcode2[i]&2) emit_sub(s1,s2,t);
2119           else emit_add(s1,s2,t);
2120         }
2121         else if(rs1[i]) {
2122           if(s1>=0) emit_mov(s1,t);
2123           else emit_loadreg(rs1[i],t);
2124         }
2125         else if(rs2[i]) {
2126           if(s2>=0) {
2127             if(opcode2[i]&2) emit_neg(s2,t);
2128             else emit_mov(s2,t);
2129           }
2130           else {
2131             emit_loadreg(rs2[i],t);
2132             if(opcode2[i]&2) emit_neg(t,t);
2133           }
2134         }
2135         else emit_zeroreg(t);
2136       }
2137     }
2138   }
2139   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2140     if(rt1[i]) {
2141       signed char s1l,s2l,s1h,s2h,tl,th;
2142       tl=get_reg(i_regs->regmap,rt1[i]);
2143       th=get_reg(i_regs->regmap,rt1[i]|64);
2144       if(tl>=0) {
2145         s1l=get_reg(i_regs->regmap,rs1[i]);
2146         s2l=get_reg(i_regs->regmap,rs2[i]);
2147         s1h=get_reg(i_regs->regmap,rs1[i]|64);
2148         s2h=get_reg(i_regs->regmap,rs2[i]|64);
2149         if(rs1[i]&&rs2[i]) {
2150           assert(s1l>=0);
2151           assert(s2l>=0);
2152           if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2153           else emit_adds(s1l,s2l,tl);
2154           if(th>=0) {
2155             #ifdef INVERTED_CARRY
2156             if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2157             #else
2158             if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2159             #endif
2160             else emit_add(s1h,s2h,th);
2161           }
2162         }
2163         else if(rs1[i]) {
2164           if(s1l>=0) emit_mov(s1l,tl);
2165           else emit_loadreg(rs1[i],tl);
2166           if(th>=0) {
2167             if(s1h>=0) emit_mov(s1h,th);
2168             else emit_loadreg(rs1[i]|64,th);
2169           }
2170         }
2171         else if(rs2[i]) {
2172           if(s2l>=0) {
2173             if(opcode2[i]&2) emit_negs(s2l,tl);
2174             else emit_mov(s2l,tl);
2175           }
2176           else {
2177             emit_loadreg(rs2[i],tl);
2178             if(opcode2[i]&2) emit_negs(tl,tl);
2179           }
2180           if(th>=0) {
2181             #ifdef INVERTED_CARRY
2182             if(s2h>=0) emit_mov(s2h,th);
2183             else emit_loadreg(rs2[i]|64,th);
2184             if(opcode2[i]&2) {
2185               emit_adcimm(-1,th); // x86 has inverted carry flag
2186               emit_not(th,th);
2187             }
2188             #else
2189             if(opcode2[i]&2) {
2190               if(s2h>=0) emit_rscimm(s2h,0,th);
2191               else {
2192                 emit_loadreg(rs2[i]|64,th);
2193                 emit_rscimm(th,0,th);
2194               }
2195             }else{
2196               if(s2h>=0) emit_mov(s2h,th);
2197               else emit_loadreg(rs2[i]|64,th);
2198             }
2199             #endif
2200           }
2201         }
2202         else {
2203           emit_zeroreg(tl);
2204           if(th>=0) emit_zeroreg(th);
2205         }
2206       }
2207     }
2208   }
2209   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2210     if(rt1[i]) {
2211       signed char s1l,s1h,s2l,s2h,t;
2212       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2213       {
2214         t=get_reg(i_regs->regmap,rt1[i]);
2215         //assert(t>=0);
2216         if(t>=0) {
2217           s1l=get_reg(i_regs->regmap,rs1[i]);
2218           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2219           s2l=get_reg(i_regs->regmap,rs2[i]);
2220           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2221           if(rs2[i]==0) // rx<r0
2222           {
2223             assert(s1h>=0);
2224             if(opcode2[i]==0x2a) // SLT
2225               emit_shrimm(s1h,31,t);
2226             else // SLTU (unsigned can not be less than zero)
2227               emit_zeroreg(t);
2228           }
2229           else if(rs1[i]==0) // r0<rx
2230           {
2231             assert(s2h>=0);
2232             if(opcode2[i]==0x2a) // SLT
2233               emit_set_gz64_32(s2h,s2l,t);
2234             else // SLTU (set if not zero)
2235               emit_set_nz64_32(s2h,s2l,t);
2236           }
2237           else {
2238             assert(s1l>=0);assert(s1h>=0);
2239             assert(s2l>=0);assert(s2h>=0);
2240             if(opcode2[i]==0x2a) // SLT
2241               emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2242             else // SLTU
2243               emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2244           }
2245         }
2246       } else {
2247         t=get_reg(i_regs->regmap,rt1[i]);
2248         //assert(t>=0);
2249         if(t>=0) {
2250           s1l=get_reg(i_regs->regmap,rs1[i]);
2251           s2l=get_reg(i_regs->regmap,rs2[i]);
2252           if(rs2[i]==0) // rx<r0
2253           {
2254             assert(s1l>=0);
2255             if(opcode2[i]==0x2a) // SLT
2256               emit_shrimm(s1l,31,t);
2257             else // SLTU (unsigned can not be less than zero)
2258               emit_zeroreg(t);
2259           }
2260           else if(rs1[i]==0) // r0<rx
2261           {
2262             assert(s2l>=0);
2263             if(opcode2[i]==0x2a) // SLT
2264               emit_set_gz32(s2l,t);
2265             else // SLTU (set if not zero)
2266               emit_set_nz32(s2l,t);
2267           }
2268           else{
2269             assert(s1l>=0);assert(s2l>=0);
2270             if(opcode2[i]==0x2a) // SLT
2271               emit_set_if_less32(s1l,s2l,t);
2272             else // SLTU
2273               emit_set_if_carry32(s1l,s2l,t);
2274           }
2275         }
2276       }
2277     }
2278   }
2279   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2280     if(rt1[i]) {
2281       signed char s1l,s1h,s2l,s2h,th,tl;
2282       tl=get_reg(i_regs->regmap,rt1[i]);
2283       th=get_reg(i_regs->regmap,rt1[i]|64);
2284       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2285       {
2286         assert(tl>=0);
2287         if(tl>=0) {
2288           s1l=get_reg(i_regs->regmap,rs1[i]);
2289           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2290           s2l=get_reg(i_regs->regmap,rs2[i]);
2291           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2292           if(rs1[i]&&rs2[i]) {
2293             assert(s1l>=0);assert(s1h>=0);
2294             assert(s2l>=0);assert(s2h>=0);
2295             if(opcode2[i]==0x24) { // AND
2296               emit_and(s1l,s2l,tl);
2297               emit_and(s1h,s2h,th);
2298             } else
2299             if(opcode2[i]==0x25) { // OR
2300               emit_or(s1l,s2l,tl);
2301               emit_or(s1h,s2h,th);
2302             } else
2303             if(opcode2[i]==0x26) { // XOR
2304               emit_xor(s1l,s2l,tl);
2305               emit_xor(s1h,s2h,th);
2306             } else
2307             if(opcode2[i]==0x27) { // NOR
2308               emit_or(s1l,s2l,tl);
2309               emit_or(s1h,s2h,th);
2310               emit_not(tl,tl);
2311               emit_not(th,th);
2312             }
2313           }
2314           else
2315           {
2316             if(opcode2[i]==0x24) { // AND
2317               emit_zeroreg(tl);
2318               emit_zeroreg(th);
2319             } else
2320             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2321               if(rs1[i]){
2322                 if(s1l>=0) emit_mov(s1l,tl);
2323                 else emit_loadreg(rs1[i],tl);
2324                 if(s1h>=0) emit_mov(s1h,th);
2325                 else emit_loadreg(rs1[i]|64,th);
2326               }
2327               else
2328               if(rs2[i]){
2329                 if(s2l>=0) emit_mov(s2l,tl);
2330                 else emit_loadreg(rs2[i],tl);
2331                 if(s2h>=0) emit_mov(s2h,th);
2332                 else emit_loadreg(rs2[i]|64,th);
2333               }
2334               else{
2335                 emit_zeroreg(tl);
2336                 emit_zeroreg(th);
2337               }
2338             } else
2339             if(opcode2[i]==0x27) { // NOR
2340               if(rs1[i]){
2341                 if(s1l>=0) emit_not(s1l,tl);
2342                 else{
2343                   emit_loadreg(rs1[i],tl);
2344                   emit_not(tl,tl);
2345                 }
2346                 if(s1h>=0) emit_not(s1h,th);
2347                 else{
2348                   emit_loadreg(rs1[i]|64,th);
2349                   emit_not(th,th);
2350                 }
2351               }
2352               else
2353               if(rs2[i]){
2354                 if(s2l>=0) emit_not(s2l,tl);
2355                 else{
2356                   emit_loadreg(rs2[i],tl);
2357                   emit_not(tl,tl);
2358                 }
2359                 if(s2h>=0) emit_not(s2h,th);
2360                 else{
2361                   emit_loadreg(rs2[i]|64,th);
2362                   emit_not(th,th);
2363                 }
2364               }
2365               else {
2366                 emit_movimm(-1,tl);
2367                 emit_movimm(-1,th);
2368               }
2369             }
2370           }
2371         }
2372       }
2373       else
2374       {
2375         // 32 bit
2376         if(tl>=0) {
2377           s1l=get_reg(i_regs->regmap,rs1[i]);
2378           s2l=get_reg(i_regs->regmap,rs2[i]);
2379           if(rs1[i]&&rs2[i]) {
2380             assert(s1l>=0);
2381             assert(s2l>=0);
2382             if(opcode2[i]==0x24) { // AND
2383               emit_and(s1l,s2l,tl);
2384             } else
2385             if(opcode2[i]==0x25) { // OR
2386               emit_or(s1l,s2l,tl);
2387             } else
2388             if(opcode2[i]==0x26) { // XOR
2389               emit_xor(s1l,s2l,tl);
2390             } else
2391             if(opcode2[i]==0x27) { // NOR
2392               emit_or(s1l,s2l,tl);
2393               emit_not(tl,tl);
2394             }
2395           }
2396           else
2397           {
2398             if(opcode2[i]==0x24) { // AND
2399               emit_zeroreg(tl);
2400             } else
2401             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2402               if(rs1[i]){
2403                 if(s1l>=0) emit_mov(s1l,tl);
2404                 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2405               }
2406               else
2407               if(rs2[i]){
2408                 if(s2l>=0) emit_mov(s2l,tl);
2409                 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2410               }
2411               else emit_zeroreg(tl);
2412             } else
2413             if(opcode2[i]==0x27) { // NOR
2414               if(rs1[i]){
2415                 if(s1l>=0) emit_not(s1l,tl);
2416                 else {
2417                   emit_loadreg(rs1[i],tl);
2418                   emit_not(tl,tl);
2419                 }
2420               }
2421               else
2422               if(rs2[i]){
2423                 if(s2l>=0) emit_not(s2l,tl);
2424                 else {
2425                   emit_loadreg(rs2[i],tl);
2426                   emit_not(tl,tl);
2427                 }
2428               }
2429               else emit_movimm(-1,tl);
2430             }
2431           }
2432         }
2433       }
2434     }
2435   }
2436 }
2437
2438 void imm16_assemble(int i,struct regstat *i_regs)
2439 {
2440   if (opcode[i]==0x0f) { // LUI
2441     if(rt1[i]) {
2442       signed char t;
2443       t=get_reg(i_regs->regmap,rt1[i]);
2444       //assert(t>=0);
2445       if(t>=0) {
2446         if(!((i_regs->isconst>>t)&1))
2447           emit_movimm(imm[i]<<16,t);
2448       }
2449     }
2450   }
2451   if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2452     if(rt1[i]) {
2453       signed char s,t;
2454       t=get_reg(i_regs->regmap,rt1[i]);
2455       s=get_reg(i_regs->regmap,rs1[i]);
2456       if(rs1[i]) {
2457         //assert(t>=0);
2458         //assert(s>=0);
2459         if(t>=0) {
2460           if(!((i_regs->isconst>>t)&1)) {
2461             if(s<0) {
2462               if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2463               emit_addimm(t,imm[i],t);
2464             }else{
2465               if(!((i_regs->wasconst>>s)&1))
2466                 emit_addimm(s,imm[i],t);
2467               else
2468                 emit_movimm(constmap[i][s]+imm[i],t);
2469             }
2470           }
2471         }
2472       } else {
2473         if(t>=0) {
2474           if(!((i_regs->isconst>>t)&1))
2475             emit_movimm(imm[i],t);
2476         }
2477       }
2478     }
2479   }
2480   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2481     if(rt1[i]) {
2482       signed char sh,sl,th,tl;
2483       th=get_reg(i_regs->regmap,rt1[i]|64);
2484       tl=get_reg(i_regs->regmap,rt1[i]);
2485       sh=get_reg(i_regs->regmap,rs1[i]|64);
2486       sl=get_reg(i_regs->regmap,rs1[i]);
2487       if(tl>=0) {
2488         if(rs1[i]) {
2489           assert(sh>=0);
2490           assert(sl>=0);
2491           if(th>=0) {
2492             emit_addimm64_32(sh,sl,imm[i],th,tl);
2493           }
2494           else {
2495             emit_addimm(sl,imm[i],tl);
2496           }
2497         } else {
2498           emit_movimm(imm[i],tl);
2499           if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2500         }
2501       }
2502     }
2503   }
2504   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2505     if(rt1[i]) {
2506       //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2507       signed char sh,sl,t;
2508       t=get_reg(i_regs->regmap,rt1[i]);
2509       sh=get_reg(i_regs->regmap,rs1[i]|64);
2510       sl=get_reg(i_regs->regmap,rs1[i]);
2511       //assert(t>=0);
2512       if(t>=0) {
2513         if(rs1[i]>0) {
2514           if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2515           if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2516             if(opcode[i]==0x0a) { // SLTI
2517               if(sl<0) {
2518                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2519                 emit_slti32(t,imm[i],t);
2520               }else{
2521                 emit_slti32(sl,imm[i],t);
2522               }
2523             }
2524             else { // SLTIU
2525               if(sl<0) {
2526                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2527                 emit_sltiu32(t,imm[i],t);
2528               }else{
2529                 emit_sltiu32(sl,imm[i],t);
2530               }
2531             }
2532           }else{ // 64-bit
2533             assert(sl>=0);
2534             if(opcode[i]==0x0a) // SLTI
2535               emit_slti64_32(sh,sl,imm[i],t);
2536             else // SLTIU
2537               emit_sltiu64_32(sh,sl,imm[i],t);
2538           }
2539         }else{
2540           // SLTI(U) with r0 is just stupid,
2541           // nonetheless examples can be found
2542           if(opcode[i]==0x0a) // SLTI
2543             if(0<imm[i]) emit_movimm(1,t);
2544             else emit_zeroreg(t);
2545           else // SLTIU
2546           {
2547             if(imm[i]) emit_movimm(1,t);
2548             else emit_zeroreg(t);
2549           }
2550         }
2551       }
2552     }
2553   }
2554   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2555     if(rt1[i]) {
2556       signed char sh,sl,th,tl;
2557       th=get_reg(i_regs->regmap,rt1[i]|64);
2558       tl=get_reg(i_regs->regmap,rt1[i]);
2559       sh=get_reg(i_regs->regmap,rs1[i]|64);
2560       sl=get_reg(i_regs->regmap,rs1[i]);
2561       if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2562         if(opcode[i]==0x0c) //ANDI
2563         {
2564           if(rs1[i]) {
2565             if(sl<0) {
2566               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2567               emit_andimm(tl,imm[i],tl);
2568             }else{
2569               if(!((i_regs->wasconst>>sl)&1))
2570                 emit_andimm(sl,imm[i],tl);
2571               else
2572                 emit_movimm(constmap[i][sl]&imm[i],tl);
2573             }
2574           }
2575           else
2576             emit_zeroreg(tl);
2577           if(th>=0) emit_zeroreg(th);
2578         }
2579         else
2580         {
2581           if(rs1[i]) {
2582             if(sl<0) {
2583               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2584             }
2585             if(th>=0) {
2586               if(sh<0) {
2587                 emit_loadreg(rs1[i]|64,th);
2588               }else{
2589                 emit_mov(sh,th);
2590               }
2591             }
2592             if(opcode[i]==0x0d) //ORI
2593             if(sl<0) {
2594               emit_orimm(tl,imm[i],tl);
2595             }else{
2596               if(!((i_regs->wasconst>>sl)&1))
2597                 emit_orimm(sl,imm[i],tl);
2598               else
2599                 emit_movimm(constmap[i][sl]|imm[i],tl);
2600             }
2601             if(opcode[i]==0x0e) //XORI
2602             if(sl<0) {
2603               emit_xorimm(tl,imm[i],tl);
2604             }else{
2605               if(!((i_regs->wasconst>>sl)&1))
2606                 emit_xorimm(sl,imm[i],tl);
2607               else
2608                 emit_movimm(constmap[i][sl]^imm[i],tl);
2609             }
2610           }
2611           else {
2612             emit_movimm(imm[i],tl);
2613             if(th>=0) emit_zeroreg(th);
2614           }
2615         }
2616       }
2617     }
2618   }
2619 }
2620
2621 void shiftimm_assemble(int i,struct regstat *i_regs)
2622 {
2623   if(opcode2[i]<=0x3) // SLL/SRL/SRA
2624   {
2625     if(rt1[i]) {
2626       signed char s,t;
2627       t=get_reg(i_regs->regmap,rt1[i]);
2628       s=get_reg(i_regs->regmap,rs1[i]);
2629       //assert(t>=0);
2630       if(t>=0){
2631         if(rs1[i]==0)
2632         {
2633           emit_zeroreg(t);
2634         }
2635         else
2636         {
2637           if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2638           if(imm[i]) {
2639             if(opcode2[i]==0) // SLL
2640             {
2641               emit_shlimm(s<0?t:s,imm[i],t);
2642             }
2643             if(opcode2[i]==2) // SRL
2644             {
2645               emit_shrimm(s<0?t:s,imm[i],t);
2646             }
2647             if(opcode2[i]==3) // SRA
2648             {
2649               emit_sarimm(s<0?t:s,imm[i],t);
2650             }
2651           }else{
2652             // Shift by zero
2653             if(s>=0 && s!=t) emit_mov(s,t);
2654           }
2655         }
2656       }
2657       //emit_storereg(rt1[i],t); //DEBUG
2658     }
2659   }
2660   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2661   {
2662     if(rt1[i]) {
2663       signed char sh,sl,th,tl;
2664       th=get_reg(i_regs->regmap,rt1[i]|64);
2665       tl=get_reg(i_regs->regmap,rt1[i]);
2666       sh=get_reg(i_regs->regmap,rs1[i]|64);
2667       sl=get_reg(i_regs->regmap,rs1[i]);
2668       if(tl>=0) {
2669         if(rs1[i]==0)
2670         {
2671           emit_zeroreg(tl);
2672           if(th>=0) emit_zeroreg(th);
2673         }
2674         else
2675         {
2676           assert(sl>=0);
2677           assert(sh>=0);
2678           if(imm[i]) {
2679             if(opcode2[i]==0x38) // DSLL
2680             {
2681               if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2682               emit_shlimm(sl,imm[i],tl);
2683             }
2684             if(opcode2[i]==0x3a) // DSRL
2685             {
2686               emit_shrdimm(sl,sh,imm[i],tl);
2687               if(th>=0) emit_shrimm(sh,imm[i],th);
2688             }
2689             if(opcode2[i]==0x3b) // DSRA
2690             {
2691               emit_shrdimm(sl,sh,imm[i],tl);
2692               if(th>=0) emit_sarimm(sh,imm[i],th);
2693             }
2694           }else{
2695             // Shift by zero
2696             if(sl!=tl) emit_mov(sl,tl);
2697             if(th>=0&&sh!=th) emit_mov(sh,th);
2698           }
2699         }
2700       }
2701     }
2702   }
2703   if(opcode2[i]==0x3c) // DSLL32
2704   {
2705     if(rt1[i]) {
2706       signed char sl,tl,th;
2707       tl=get_reg(i_regs->regmap,rt1[i]);
2708       th=get_reg(i_regs->regmap,rt1[i]|64);
2709       sl=get_reg(i_regs->regmap,rs1[i]);
2710       if(th>=0||tl>=0){
2711         assert(tl>=0);
2712         assert(th>=0);
2713         assert(sl>=0);
2714         emit_mov(sl,th);
2715         emit_zeroreg(tl);
2716         if(imm[i]>32)
2717         {
2718           emit_shlimm(th,imm[i]&31,th);
2719         }
2720       }
2721     }
2722   }
2723   if(opcode2[i]==0x3e) // DSRL32
2724   {
2725     if(rt1[i]) {
2726       signed char sh,tl,th;
2727       tl=get_reg(i_regs->regmap,rt1[i]);
2728       th=get_reg(i_regs->regmap,rt1[i]|64);
2729       sh=get_reg(i_regs->regmap,rs1[i]|64);
2730       if(tl>=0){
2731         assert(sh>=0);
2732         emit_mov(sh,tl);
2733         if(th>=0) emit_zeroreg(th);
2734         if(imm[i]>32)
2735         {
2736           emit_shrimm(tl,imm[i]&31,tl);
2737         }
2738       }
2739     }
2740   }
2741   if(opcode2[i]==0x3f) // DSRA32
2742   {
2743     if(rt1[i]) {
2744       signed char sh,tl;
2745       tl=get_reg(i_regs->regmap,rt1[i]);
2746       sh=get_reg(i_regs->regmap,rs1[i]|64);
2747       if(tl>=0){
2748         assert(sh>=0);
2749         emit_mov(sh,tl);
2750         if(imm[i]>32)
2751         {
2752           emit_sarimm(tl,imm[i]&31,tl);
2753         }
2754       }
2755     }
2756   }
2757 }
2758
2759 #ifndef shift_assemble
2760 void shift_assemble(int i,struct regstat *i_regs)
2761 {
2762   printf("Need shift_assemble for this architecture.\n");
2763   exit(1);
2764 }
2765 #endif
2766
2767 void load_assemble(int i,struct regstat *i_regs)
2768 {
2769   int s,th,tl,addr,map=-1;
2770   int offset;
2771   int jaddr=0;
2772   int memtarget=0,c=0;
2773   int fastload_reg_override=0;
2774   u_int hr,reglist=0;
2775   th=get_reg(i_regs->regmap,rt1[i]|64);
2776   tl=get_reg(i_regs->regmap,rt1[i]);
2777   s=get_reg(i_regs->regmap,rs1[i]);
2778   offset=imm[i];
2779   for(hr=0;hr<HOST_REGS;hr++) {
2780     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2781   }
2782   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2783   if(s>=0) {
2784     c=(i_regs->wasconst>>s)&1;
2785     if (c) {
2786       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2787       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2788     }
2789   }
2790   //printf("load_assemble: c=%d\n",c);
2791   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2792   // FIXME: Even if the load is a NOP, we should check for pagefaults...
2793 #ifdef PCSX
2794   if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2795     ||rt1[i]==0) {
2796       // could be FIFO, must perform the read
2797       // ||dummy read
2798       assem_debug("(forced read)\n");
2799       tl=get_reg(i_regs->regmap,-1);
2800       assert(tl>=0);
2801   }
2802 #endif
2803   if(offset||s<0||c) addr=tl;
2804   else addr=s;
2805   //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2806  if(tl>=0) {
2807   //printf("load_assemble: c=%d\n",c);
2808   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2809   assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2810   reglist&=~(1<<tl);
2811   if(th>=0) reglist&=~(1<<th);
2812   if(!using_tlb) {
2813     if(!c) {
2814       #ifdef RAM_OFFSET
2815       map=get_reg(i_regs->regmap,ROREG);
2816       if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2817       #endif
2818 //#define R29_HACK 1
2819       #ifdef R29_HACK
2820       // Strmnnrmn's speed hack
2821       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2822       #endif
2823       {
2824         #ifdef PCSX
2825         if(sp_in_mirror&&rs1[i]==29) {
2826           emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
2827           emit_cmpimm(HOST_TEMPREG,RAM_SIZE);
2828           fastload_reg_override=HOST_TEMPREG;
2829         }
2830         else
2831         #endif
2832         emit_cmpimm(addr,RAM_SIZE);
2833         jaddr=(int)out;
2834         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2835         // Hint to branch predictor that the branch is unlikely to be taken
2836         if(rs1[i]>=28)
2837           emit_jno_unlikely(0);
2838         else
2839         #endif
2840         emit_jno(0);
2841       }
2842     }
2843   }else{ // using tlb
2844     int x=0;
2845     if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2846     if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2847     map=get_reg(i_regs->regmap,TLREG);
2848     assert(map>=0);
2849     reglist&=~(1<<map);
2850     map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2851     do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2852   }
2853   int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2854   if (opcode[i]==0x20) { // LB
2855     if(!c||memtarget) {
2856       if(!dummy) {
2857         #ifdef HOST_IMM_ADDR32
2858         if(c)
2859           emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2860         else
2861         #endif
2862         {
2863           //emit_xorimm(addr,3,tl);
2864           //gen_tlb_addr_r(tl,map);
2865           //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2866           int x=0,a=tl;
2867 #ifdef BIG_ENDIAN_MIPS
2868           if(!c) emit_xorimm(addr,3,tl);
2869           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2870 #else
2871           if(!c) a=addr;
2872 #endif
2873           if(fastload_reg_override) a=fastload_reg_override;
2874
2875           emit_movsbl_indexed_tlb(x,a,map,tl);
2876         }
2877       }
2878       if(jaddr)
2879         add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2880     }
2881     else
2882       inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2883   }
2884   if (opcode[i]==0x21) { // LH
2885     if(!c||memtarget) {
2886       if(!dummy) {
2887         #ifdef HOST_IMM_ADDR32
2888         if(c)
2889           emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2890         else
2891         #endif
2892         {
2893           int x=0,a=tl;
2894 #ifdef BIG_ENDIAN_MIPS
2895           if(!c) emit_xorimm(addr,2,tl);
2896           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2897 #else
2898           if(!c) a=addr;
2899 #endif
2900           if(fastload_reg_override) a=fastload_reg_override;
2901           //#ifdef
2902           //emit_movswl_indexed_tlb(x,tl,map,tl);
2903           //else
2904           if(map>=0) {
2905             gen_tlb_addr_r(a,map);
2906             emit_movswl_indexed(x,a,tl);
2907           }else{
2908             #ifdef RAM_OFFSET
2909             emit_movswl_indexed(x,a,tl);
2910             #else
2911             emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2912             #endif
2913           }
2914         }
2915       }
2916       if(jaddr)
2917         add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2918     }
2919     else
2920       inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2921   }
2922   if (opcode[i]==0x23) { // LW
2923     if(!c||memtarget) {
2924       if(!dummy) {
2925         int a=addr;
2926         if(fastload_reg_override) a=fastload_reg_override;
2927         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2928         #ifdef HOST_IMM_ADDR32
2929         if(c)
2930           emit_readword_tlb(constmap[i][s]+offset,map,tl);
2931         else
2932         #endif
2933         emit_readword_indexed_tlb(0,a,map,tl);
2934       }
2935       if(jaddr)
2936         add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2937     }
2938     else
2939       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2940   }
2941   if (opcode[i]==0x24) { // LBU
2942     if(!c||memtarget) {
2943       if(!dummy) {
2944         #ifdef HOST_IMM_ADDR32
2945         if(c)
2946           emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2947         else
2948         #endif
2949         {
2950           //emit_xorimm(addr,3,tl);
2951           //gen_tlb_addr_r(tl,map);
2952           //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
2953           int x=0,a=tl;
2954 #ifdef BIG_ENDIAN_MIPS
2955           if(!c) emit_xorimm(addr,3,tl);
2956           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2957 #else
2958           if(!c) a=addr;
2959 #endif
2960           if(fastload_reg_override) a=fastload_reg_override;
2961
2962           emit_movzbl_indexed_tlb(x,a,map,tl);
2963         }
2964       }
2965       if(jaddr)
2966         add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2967     }
2968     else
2969       inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2970   }
2971   if (opcode[i]==0x25) { // LHU
2972     if(!c||memtarget) {
2973       if(!dummy) {
2974         #ifdef HOST_IMM_ADDR32
2975         if(c)
2976           emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2977         else
2978         #endif
2979         {
2980           int x=0,a=tl;
2981 #ifdef BIG_ENDIAN_MIPS
2982           if(!c) emit_xorimm(addr,2,tl);
2983           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2984 #else
2985           if(!c) a=addr;
2986 #endif
2987           if(fastload_reg_override) a=fastload_reg_override;
2988           //#ifdef
2989           //emit_movzwl_indexed_tlb(x,tl,map,tl);
2990           //#else
2991           if(map>=0) {
2992             gen_tlb_addr_r(a,map);
2993             emit_movzwl_indexed(x,a,tl);
2994           }else{
2995             #ifdef RAM_OFFSET
2996             emit_movzwl_indexed(x,a,tl);
2997             #else
2998             emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
2999             #endif
3000           }
3001         }
3002       }
3003       if(jaddr)
3004         add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3005     }
3006     else
3007       inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3008   }
3009   if (opcode[i]==0x27) { // LWU
3010     assert(th>=0);
3011     if(!c||memtarget) {
3012       if(!dummy) {
3013         int a=addr;
3014         if(fastload_reg_override) a=fastload_reg_override;
3015         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3016         #ifdef HOST_IMM_ADDR32
3017         if(c)
3018           emit_readword_tlb(constmap[i][s]+offset,map,tl);
3019         else
3020         #endif
3021         emit_readword_indexed_tlb(0,a,map,tl);
3022       }
3023       if(jaddr)
3024         add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3025     }
3026     else {
3027       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3028     }
3029     emit_zeroreg(th);
3030   }
3031   if (opcode[i]==0x37) { // LD
3032     if(!c||memtarget) {
3033       if(!dummy) {
3034         int a=addr;
3035         if(fastload_reg_override) a=fastload_reg_override;
3036         //gen_tlb_addr_r(tl,map);
3037         //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3038         //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3039         #ifdef HOST_IMM_ADDR32
3040         if(c)
3041           emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3042         else
3043         #endif
3044         emit_readdword_indexed_tlb(0,a,map,th,tl);
3045       }
3046       if(jaddr)
3047         add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3048     }
3049     else
3050       inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3051   }
3052  }
3053   //emit_storereg(rt1[i],tl); // DEBUG
3054   //if(opcode[i]==0x23)
3055   //if(opcode[i]==0x24)
3056   //if(opcode[i]==0x23||opcode[i]==0x24)
3057   /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3058   {
3059     //emit_pusha();
3060     save_regs(0x100f);
3061         emit_readword((int)&last_count,ECX);
3062         #ifdef __i386__
3063         if(get_reg(i_regs->regmap,CCREG)<0)
3064           emit_loadreg(CCREG,HOST_CCREG);
3065         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3066         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3067         emit_writeword(HOST_CCREG,(int)&Count);
3068         #endif
3069         #ifdef __arm__
3070         if(get_reg(i_regs->regmap,CCREG)<0)
3071           emit_loadreg(CCREG,0);
3072         else
3073           emit_mov(HOST_CCREG,0);
3074         emit_add(0,ECX,0);
3075         emit_addimm(0,2*ccadj[i],0);
3076         emit_writeword(0,(int)&Count);
3077         #endif
3078     emit_call((int)memdebug);
3079     //emit_popa();
3080     restore_regs(0x100f);
3081   }/**/
3082 }
3083
3084 #ifndef loadlr_assemble
3085 void loadlr_assemble(int i,struct regstat *i_regs)
3086 {
3087   printf("Need loadlr_assemble for this architecture.\n");
3088   exit(1);
3089 }
3090 #endif
3091
3092 void store_assemble(int i,struct regstat *i_regs)
3093 {
3094   int s,th,tl,map=-1;
3095   int addr,temp;
3096   int offset;
3097   int jaddr=0,jaddr2,type;
3098   int memtarget=0,c=0;
3099   int agr=AGEN1+(i&1);
3100   int faststore_reg_override=0;
3101   u_int hr,reglist=0;
3102   th=get_reg(i_regs->regmap,rs2[i]|64);
3103   tl=get_reg(i_regs->regmap,rs2[i]);
3104   s=get_reg(i_regs->regmap,rs1[i]);
3105   temp=get_reg(i_regs->regmap,agr);
3106   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3107   offset=imm[i];
3108   if(s>=0) {
3109     c=(i_regs->wasconst>>s)&1;
3110     if(c) {
3111       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3112       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3113     }
3114   }
3115   assert(tl>=0);
3116   assert(temp>=0);
3117   for(hr=0;hr<HOST_REGS;hr++) {
3118     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3119   }
3120   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3121   if(offset||s<0||c) addr=temp;
3122   else addr=s;
3123   if(!using_tlb) {
3124     if(!c) {
3125       #ifdef PCSX
3126       if(sp_in_mirror&&rs1[i]==29) {
3127         emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
3128         emit_cmpimm(HOST_TEMPREG,RAM_SIZE);
3129         faststore_reg_override=HOST_TEMPREG;
3130       }
3131       else
3132       #endif
3133       #ifdef R29_HACK
3134       // Strmnnrmn's speed hack
3135       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3136       #endif
3137       emit_cmpimm(addr,RAM_SIZE);
3138       #ifdef DESTRUCTIVE_SHIFT
3139       if(s==addr) emit_mov(s,temp);
3140       #endif
3141       #ifdef R29_HACK
3142       memtarget=1;
3143       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3144       #endif
3145       {
3146         jaddr=(int)out;
3147         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3148         // Hint to branch predictor that the branch is unlikely to be taken
3149         if(rs1[i]>=28)
3150           emit_jno_unlikely(0);
3151         else
3152         #endif
3153         emit_jno(0);
3154       }
3155     }
3156   }else{ // using tlb
3157     int x=0;
3158     if (opcode[i]==0x28) x=3; // SB
3159     if (opcode[i]==0x29) x=2; // SH
3160     map=get_reg(i_regs->regmap,TLREG);
3161     assert(map>=0);
3162     reglist&=~(1<<map);
3163     map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3164     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3165   }
3166
3167   if (opcode[i]==0x28) { // SB
3168     if(!c||memtarget) {
3169       int x=0,a=temp;
3170 #ifdef BIG_ENDIAN_MIPS
3171       if(!c) emit_xorimm(addr,3,temp);
3172       else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3173 #else
3174       if(!c) a=addr;
3175 #endif
3176       if(faststore_reg_override) a=faststore_reg_override;
3177       //gen_tlb_addr_w(temp,map);
3178       //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3179       emit_writebyte_indexed_tlb(tl,x,a,map,a);
3180     }
3181     type=STOREB_STUB;
3182   }
3183   if (opcode[i]==0x29) { // SH
3184     if(!c||memtarget) {
3185       int x=0,a=temp;
3186 #ifdef BIG_ENDIAN_MIPS
3187       if(!c) emit_xorimm(addr,2,temp);
3188       else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3189 #else
3190       if(!c) a=addr;
3191 #endif
3192       if(faststore_reg_override) a=faststore_reg_override;
3193       //#ifdef
3194       //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3195       //#else
3196       if(map>=0) {
3197         gen_tlb_addr_w(a,map);
3198         emit_writehword_indexed(tl,x,a);
3199       }else
3200         emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
3201     }
3202     type=STOREH_STUB;
3203   }
3204   if (opcode[i]==0x2B) { // SW
3205     if(!c||memtarget) {
3206       int a=addr;
3207       if(faststore_reg_override) a=faststore_reg_override;
3208       //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3209       emit_writeword_indexed_tlb(tl,0,a,map,temp);
3210     }
3211     type=STOREW_STUB;
3212   }
3213   if (opcode[i]==0x3F) { // SD
3214     if(!c||memtarget) {
3215       int a=addr;
3216       if(faststore_reg_override) a=faststore_reg_override;
3217       if(rs2[i]) {
3218         assert(th>=0);
3219         //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3220         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3221         emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
3222       }else{
3223         // Store zero
3224         //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3225         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3226         emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
3227       }
3228     }
3229     type=STORED_STUB;
3230   }
3231   if(!using_tlb) {
3232     if(!c||memtarget) {
3233       #ifdef DESTRUCTIVE_SHIFT
3234       // The x86 shift operation is 'destructive'; it overwrites the
3235       // source register, so we need to make a copy first and use that.
3236       addr=temp;
3237       #endif
3238       #if defined(HOST_IMM8)
3239       int ir=get_reg(i_regs->regmap,INVCP);
3240       assert(ir>=0);
3241       emit_cmpmem_indexedsr12_reg(ir,addr,1);
3242       #else
3243       emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3244       #endif
3245       #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3246       emit_callne(invalidate_addr_reg[addr]);
3247       #else
3248       jaddr2=(int)out;
3249       emit_jne(0);
3250       add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3251       #endif
3252     }
3253   }
3254   if(jaddr) {
3255     add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3256   } else if(c&&!memtarget) {
3257     inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3258   }
3259   //if(opcode[i]==0x2B || opcode[i]==0x3F)
3260   //if(opcode[i]==0x2B || opcode[i]==0x28)
3261   //if(opcode[i]==0x2B || opcode[i]==0x29)
3262   //if(opcode[i]==0x2B)
3263   /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3264   {
3265     #ifdef __i386__
3266     emit_pusha();
3267     #endif
3268     #ifdef __arm__
3269     save_regs(0x100f);
3270     #endif
3271         emit_readword((int)&last_count,ECX);
3272         #ifdef __i386__
3273         if(get_reg(i_regs->regmap,CCREG)<0)
3274           emit_loadreg(CCREG,HOST_CCREG);
3275         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3276         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3277         emit_writeword(HOST_CCREG,(int)&Count);
3278         #endif
3279         #ifdef __arm__
3280         if(get_reg(i_regs->regmap,CCREG)<0)
3281           emit_loadreg(CCREG,0);
3282         else
3283           emit_mov(HOST_CCREG,0);
3284         emit_add(0,ECX,0);
3285         emit_addimm(0,2*ccadj[i],0);
3286         emit_writeword(0,(int)&Count);
3287         #endif
3288     emit_call((int)memdebug);
3289     #ifdef __i386__
3290     emit_popa();
3291     #endif
3292     #ifdef __arm__
3293     restore_regs(0x100f);
3294     #endif
3295   }/**/
3296 }
3297
3298 void storelr_assemble(int i,struct regstat *i_regs)
3299 {
3300   int s,th,tl;
3301   int temp;
3302   int temp2;
3303   int offset;
3304   int jaddr=0,jaddr2;
3305   int case1,case2,case3;
3306   int done0,done1,done2;
3307   int memtarget=0,c=0;
3308   int agr=AGEN1+(i&1);
3309   u_int hr,reglist=0;
3310   th=get_reg(i_regs->regmap,rs2[i]|64);
3311   tl=get_reg(i_regs->regmap,rs2[i]);
3312   s=get_reg(i_regs->regmap,rs1[i]);
3313   temp=get_reg(i_regs->regmap,agr);
3314   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3315   offset=imm[i];
3316   if(s>=0) {
3317     c=(i_regs->isconst>>s)&1;
3318     if(c) {
3319       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3320       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3321     }
3322   }
3323   assert(tl>=0);
3324   for(hr=0;hr<HOST_REGS;hr++) {
3325     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3326   }
3327   assert(temp>=0);
3328   if(!using_tlb) {
3329     if(!c) {
3330       emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3331       if(!offset&&s!=temp) emit_mov(s,temp);
3332       jaddr=(int)out;
3333       emit_jno(0);
3334     }
3335     else
3336     {
3337       if(!memtarget||!rs1[i]) {
3338         jaddr=(int)out;
3339         emit_jmp(0);
3340       }
3341     }
3342     #ifdef RAM_OFFSET
3343     int map=get_reg(i_regs->regmap,ROREG);
3344     if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3345     gen_tlb_addr_w(temp,map);
3346     #else
3347     if((u_int)rdram!=0x80000000)
3348       emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3349     #endif
3350   }else{ // using tlb
3351     int map=get_reg(i_regs->regmap,TLREG);
3352     assert(map>=0);
3353     reglist&=~(1<<map);
3354     map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3355     if(!c&&!offset&&s>=0) emit_mov(s,temp);
3356     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3357     if(!jaddr&&!memtarget) {
3358       jaddr=(int)out;
3359       emit_jmp(0);
3360     }
3361     gen_tlb_addr_w(temp,map);
3362   }
3363
3364   if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3365     temp2=get_reg(i_regs->regmap,FTEMP);
3366     if(!rs2[i]) temp2=th=tl;
3367   }
3368
3369 #ifndef BIG_ENDIAN_MIPS
3370     emit_xorimm(temp,3,temp);
3371 #endif
3372   emit_testimm(temp,2);
3373   case2=(int)out;
3374   emit_jne(0);
3375   emit_testimm(temp,1);
3376   case1=(int)out;
3377   emit_jne(0);
3378   // 0
3379   if (opcode[i]==0x2A) { // SWL
3380     emit_writeword_indexed(tl,0,temp);
3381   }
3382   if (opcode[i]==0x2E) { // SWR
3383     emit_writebyte_indexed(tl,3,temp);
3384   }
3385   if (opcode[i]==0x2C) { // SDL
3386     emit_writeword_indexed(th,0,temp);
3387     if(rs2[i]) emit_mov(tl,temp2);
3388   }
3389   if (opcode[i]==0x2D) { // SDR
3390     emit_writebyte_indexed(tl,3,temp);
3391     if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3392   }
3393   done0=(int)out;
3394   emit_jmp(0);
3395   // 1
3396   set_jump_target(case1,(int)out);
3397   if (opcode[i]==0x2A) { // SWL
3398     // Write 3 msb into three least significant bytes
3399     if(rs2[i]) emit_rorimm(tl,8,tl);
3400     emit_writehword_indexed(tl,-1,temp);
3401     if(rs2[i]) emit_rorimm(tl,16,tl);
3402     emit_writebyte_indexed(tl,1,temp);
3403     if(rs2[i]) emit_rorimm(tl,8,tl);
3404   }
3405   if (opcode[i]==0x2E) { // SWR
3406     // Write two lsb into two most significant bytes
3407     emit_writehword_indexed(tl,1,temp);
3408   }
3409   if (opcode[i]==0x2C) { // SDL
3410     if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3411     // Write 3 msb into three least significant bytes
3412     if(rs2[i]) emit_rorimm(th,8,th);
3413     emit_writehword_indexed(th,-1,temp);
3414     if(rs2[i]) emit_rorimm(th,16,th);
3415     emit_writebyte_indexed(th,1,temp);
3416     if(rs2[i]) emit_rorimm(th,8,th);
3417   }
3418   if (opcode[i]==0x2D) { // SDR
3419     if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3420     // Write two lsb into two most significant bytes
3421     emit_writehword_indexed(tl,1,temp);
3422   }
3423   done1=(int)out;
3424   emit_jmp(0);
3425   // 2
3426   set_jump_target(case2,(int)out);
3427   emit_testimm(temp,1);
3428   case3=(int)out;
3429   emit_jne(0);
3430   if (opcode[i]==0x2A) { // SWL
3431     // Write two msb into two least significant bytes
3432     if(rs2[i]) emit_rorimm(tl,16,tl);
3433     emit_writehword_indexed(tl,-2,temp);
3434     if(rs2[i]) emit_rorimm(tl,16,tl);
3435   }
3436   if (opcode[i]==0x2E) { // SWR
3437     // Write 3 lsb into three most significant bytes
3438     emit_writebyte_indexed(tl,-1,temp);
3439     if(rs2[i]) emit_rorimm(tl,8,tl);
3440     emit_writehword_indexed(tl,0,temp);
3441     if(rs2[i]) emit_rorimm(tl,24,tl);
3442   }
3443   if (opcode[i]==0x2C) { // SDL
3444     if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3445     // Write two msb into two least significant bytes
3446     if(rs2[i]) emit_rorimm(th,16,th);
3447     emit_writehword_indexed(th,-2,temp);
3448     if(rs2[i]) emit_rorimm(th,16,th);
3449   }
3450   if (opcode[i]==0x2D) { // SDR
3451     if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3452     // Write 3 lsb into three most significant bytes
3453     emit_writebyte_indexed(tl,-1,temp);
3454     if(rs2[i]) emit_rorimm(tl,8,tl);
3455     emit_writehword_indexed(tl,0,temp);
3456     if(rs2[i]) emit_rorimm(tl,24,tl);
3457   }
3458   done2=(int)out;
3459   emit_jmp(0);
3460   // 3
3461   set_jump_target(case3,(int)out);
3462   if (opcode[i]==0x2A) { // SWL
3463     // Write msb into least significant byte
3464     if(rs2[i]) emit_rorimm(tl,24,tl);
3465     emit_writebyte_indexed(tl,-3,temp);
3466     if(rs2[i]) emit_rorimm(tl,8,tl);
3467   }
3468   if (opcode[i]==0x2E) { // SWR
3469     // Write entire word
3470     emit_writeword_indexed(tl,-3,temp);
3471   }
3472   if (opcode[i]==0x2C) { // SDL
3473     if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3474     // Write msb into least significant byte
3475     if(rs2[i]) emit_rorimm(th,24,th);
3476     emit_writebyte_indexed(th,-3,temp);
3477     if(rs2[i]) emit_rorimm(th,8,th);
3478   }
3479   if (opcode[i]==0x2D) { // SDR
3480     if(rs2[i]) emit_mov(th,temp2);
3481     // Write entire word
3482     emit_writeword_indexed(tl,-3,temp);
3483   }
3484   set_jump_target(done0,(int)out);
3485   set_jump_target(done1,(int)out);
3486   set_jump_target(done2,(int)out);
3487   if (opcode[i]==0x2C) { // SDL
3488     emit_testimm(temp,4);
3489     done0=(int)out;
3490     emit_jne(0);
3491     emit_andimm(temp,~3,temp);
3492     emit_writeword_indexed(temp2,4,temp);
3493     set_jump_target(done0,(int)out);
3494   }
3495   if (opcode[i]==0x2D) { // SDR
3496     emit_testimm(temp,4);
3497     done0=(int)out;
3498     emit_jeq(0);
3499     emit_andimm(temp,~3,temp);
3500     emit_writeword_indexed(temp2,-4,temp);
3501     set_jump_target(done0,(int)out);
3502   }
3503   if(!c||!memtarget)
3504     add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
3505   if(!using_tlb) {
3506     #ifdef RAM_OFFSET
3507     int map=get_reg(i_regs->regmap,ROREG);
3508     if(map<0) map=HOST_TEMPREG;
3509     gen_orig_addr_w(temp,map);
3510     #else
3511     emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3512     #endif
3513     #if defined(HOST_IMM8)
3514     int ir=get_reg(i_regs->regmap,INVCP);
3515     assert(ir>=0);
3516     emit_cmpmem_indexedsr12_reg(ir,temp,1);
3517     #else
3518     emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3519     #endif
3520     #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3521     emit_callne(invalidate_addr_reg[temp]);
3522     #else
3523     jaddr2=(int)out;
3524     emit_jne(0);
3525     add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3526     #endif
3527   }
3528   /*
3529     emit_pusha();
3530     //save_regs(0x100f);
3531         emit_readword((int)&last_count,ECX);
3532         if(get_reg(i_regs->regmap,CCREG)<0)
3533           emit_loadreg(CCREG,HOST_CCREG);
3534         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3535         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3536         emit_writeword(HOST_CCREG,(int)&Count);
3537     emit_call((int)memdebug);
3538     emit_popa();
3539     //restore_regs(0x100f);
3540   /**/
3541 }
3542
3543 void c1ls_assemble(int i,struct regstat *i_regs)
3544 {
3545 #ifndef DISABLE_COP1
3546   int s,th,tl;
3547   int temp,ar;
3548   int map=-1;
3549   int offset;
3550   int c=0;
3551   int jaddr,jaddr2=0,jaddr3,type;
3552   int agr=AGEN1+(i&1);
3553   u_int hr,reglist=0;
3554   th=get_reg(i_regs->regmap,FTEMP|64);
3555   tl=get_reg(i_regs->regmap,FTEMP);
3556   s=get_reg(i_regs->regmap,rs1[i]);
3557   temp=get_reg(i_regs->regmap,agr);
3558   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3559   offset=imm[i];
3560   assert(tl>=0);
3561   assert(rs1[i]>0);
3562   assert(temp>=0);
3563   for(hr=0;hr<HOST_REGS;hr++) {
3564     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3565   }
3566   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3567   if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3568   {
3569     // Loads use a temporary register which we need to save
3570     reglist|=1<<temp;
3571   }
3572   if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3573     ar=temp;
3574   else // LWC1/LDC1
3575     ar=tl;
3576   //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3577   //else c=(i_regs->wasconst>>s)&1;
3578   if(s>=0) c=(i_regs->wasconst>>s)&1;
3579   // Check cop1 unusable
3580   if(!cop1_usable) {
3581     signed char rs=get_reg(i_regs->regmap,CSREG);
3582     assert(rs>=0);
3583     emit_testimm(rs,0x20000000);
3584     jaddr=(int)out;
3585     emit_jeq(0);
3586     add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3587     cop1_usable=1;
3588   }
3589   if (opcode[i]==0x39) { // SWC1 (get float address)
3590     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],tl);
3591   }
3592   if (opcode[i]==0x3D) { // SDC1 (get double address)
3593     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],tl);
3594   }
3595   // Generate address + offset
3596   if(!using_tlb) {
3597     if(!c)
3598       emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3599   }
3600   else
3601   {
3602     map=get_reg(i_regs->regmap,TLREG);
3603     assert(map>=0);
3604     reglist&=~(1<<map);
3605     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3606       map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3607     }
3608     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3609       map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3610     }
3611   }
3612   if (opcode[i]==0x39) { // SWC1 (read float)
3613     emit_readword_indexed(0,tl,tl);
3614   }
3615   if (opcode[i]==0x3D) { // SDC1 (read double)
3616     emit_readword_indexed(4,tl,th);
3617     emit_readword_indexed(0,tl,tl);
3618   }
3619   if (opcode[i]==0x31) { // LWC1 (get target address)
3620     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],temp);
3621   }
3622   if (opcode[i]==0x35) { // LDC1 (get target address)
3623     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],temp);
3624   }
3625   if(!using_tlb) {
3626     if(!c) {
3627       jaddr2=(int)out;
3628       emit_jno(0);
3629     }
3630     else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
3631       jaddr2=(int)out;
3632       emit_jmp(0); // inline_readstub/inline_writestub?  Very rare case
3633     }
3634     #ifdef DESTRUCTIVE_SHIFT
3635     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3636       if(!offset&&!c&&s>=0) emit_mov(s,ar);
3637     }
3638     #endif
3639   }else{
3640     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3641       do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3642     }
3643     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3644       do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3645     }
3646   }
3647   if (opcode[i]==0x31) { // LWC1
3648     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3649     //gen_tlb_addr_r(ar,map);
3650     //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3651     #ifdef HOST_IMM_ADDR32
3652     if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3653     else
3654     #endif
3655     emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3656     type=LOADW_STUB;
3657   }
3658   if (opcode[i]==0x35) { // LDC1
3659     assert(th>=0);
3660     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3661     //gen_tlb_addr_r(ar,map);
3662     //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3663     //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3664     #ifdef HOST_IMM_ADDR32
3665     if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3666     else
3667     #endif
3668     emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3669     type=LOADD_STUB;
3670   }
3671   if (opcode[i]==0x39) { // SWC1
3672     //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3673     emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3674     type=STOREW_STUB;
3675   }
3676   if (opcode[i]==0x3D) { // SDC1
3677     assert(th>=0);
3678     //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3679     //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3680     emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3681     type=STORED_STUB;
3682   }
3683   if(!using_tlb) {
3684     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3685       #ifndef DESTRUCTIVE_SHIFT
3686       temp=offset||c||s<0?ar:s;
3687       #endif
3688       #if defined(HOST_IMM8)
3689       int ir=get_reg(i_regs->regmap,INVCP);
3690       assert(ir>=0);
3691       emit_cmpmem_indexedsr12_reg(ir,temp,1);
3692       #else
3693       emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3694       #endif
3695       #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3696       emit_callne(invalidate_addr_reg[temp]);
3697       #else
3698       jaddr3=(int)out;
3699       emit_jne(0);
3700       add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3701       #endif
3702     }
3703   }
3704   if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3705   if (opcode[i]==0x31) { // LWC1 (write float)
3706     emit_writeword_indexed(tl,0,temp);
3707   }
3708   if (opcode[i]==0x35) { // LDC1 (write double)
3709     emit_writeword_indexed(th,4,temp);
3710     emit_writeword_indexed(tl,0,temp);
3711   }
3712   //if(opcode[i]==0x39)
3713   /*if(opcode[i]==0x39||opcode[i]==0x31)
3714   {
3715     emit_pusha();
3716         emit_readword((int)&last_count,ECX);
3717         if(get_reg(i_regs->regmap,CCREG)<0)
3718           emit_loadreg(CCREG,HOST_CCREG);
3719         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3720         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3721         emit_writeword(HOST_CCREG,(int)&Count);
3722     emit_call((int)memdebug);
3723     emit_popa();
3724   }/**/
3725 #else
3726   cop1_unusable(i, i_regs);
3727 #endif
3728 }
3729
3730 void c2ls_assemble(int i,struct regstat *i_regs)
3731 {
3732   int s,tl;
3733   int ar;
3734   int offset;
3735   int memtarget=0,c=0;
3736   int jaddr2=0,jaddr3,type;
3737   int agr=AGEN1+(i&1);
3738   u_int hr,reglist=0;
3739   u_int copr=(source[i]>>16)&0x1f;
3740   s=get_reg(i_regs->regmap,rs1[i]);
3741   tl=get_reg(i_regs->regmap,FTEMP);
3742   offset=imm[i];
3743   assert(rs1[i]>0);
3744   assert(tl>=0);
3745   assert(!using_tlb);
3746
3747   for(hr=0;hr<HOST_REGS;hr++) {
3748     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3749   }
3750   if(i_regs->regmap[HOST_CCREG]==CCREG)
3751     reglist&=~(1<<HOST_CCREG);
3752
3753   // get the address
3754   if (opcode[i]==0x3a) { // SWC2
3755     ar=get_reg(i_regs->regmap,agr);
3756     if(ar<0) ar=get_reg(i_regs->regmap,-1);
3757     reglist|=1<<ar;
3758   } else { // LWC2
3759     ar=tl;
3760   }
3761   if(s>=0) c=(i_regs->wasconst>>s)&1;
3762   memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3763   if (!offset&&!c&&s>=0) ar=s;
3764   assert(ar>=0);
3765
3766   if (opcode[i]==0x3a) { // SWC2
3767     cop2_get_dreg(copr,tl,HOST_TEMPREG);
3768     type=STOREW_STUB;
3769   }
3770   else
3771     type=LOADW_STUB;
3772
3773   if(c&&!memtarget) {
3774     jaddr2=(int)out;
3775     emit_jmp(0); // inline_readstub/inline_writestub?
3776   }
3777   else {
3778     if(!c) {
3779       emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3780       jaddr2=(int)out;
3781       emit_jno(0);
3782     }
3783     if (opcode[i]==0x32) { // LWC2
3784       #ifdef HOST_IMM_ADDR32
3785       if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3786       else
3787       #endif
3788       emit_readword_indexed(0,ar,tl);
3789     }
3790     if (opcode[i]==0x3a) { // SWC2
3791       #ifdef DESTRUCTIVE_SHIFT
3792       if(!offset&&!c&&s>=0) emit_mov(s,ar);
3793       #endif
3794       emit_writeword_indexed(tl,0,ar);
3795     }
3796   }
3797   if(jaddr2)
3798     add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3799   if (opcode[i]==0x3a) { // SWC2
3800 #if defined(HOST_IMM8)
3801     int ir=get_reg(i_regs->regmap,INVCP);
3802     assert(ir>=0);
3803     emit_cmpmem_indexedsr12_reg(ir,ar,1);
3804 #else
3805     emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3806 #endif
3807     #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3808     emit_callne(invalidate_addr_reg[ar]);
3809     #else
3810     jaddr3=(int)out;
3811     emit_jne(0);
3812     add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3813     #endif
3814   }
3815   if (opcode[i]==0x32) { // LWC2
3816     cop2_put_dreg(copr,tl,HOST_TEMPREG);
3817   }
3818 }
3819
3820 #ifndef multdiv_assemble
3821 void multdiv_assemble(int i,struct regstat *i_regs)
3822 {
3823   printf("Need multdiv_assemble for this architecture.\n");
3824   exit(1);
3825 }
3826 #endif
3827
3828 void mov_assemble(int i,struct regstat *i_regs)
3829 {
3830   //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3831   //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3832   if(rt1[i]) {
3833     signed char sh,sl,th,tl;
3834     th=get_reg(i_regs->regmap,rt1[i]|64);
3835     tl=get_reg(i_regs->regmap,rt1[i]);
3836     //assert(tl>=0);
3837     if(tl>=0) {
3838       sh=get_reg(i_regs->regmap,rs1[i]|64);
3839       sl=get_reg(i_regs->regmap,rs1[i]);
3840       if(sl>=0) emit_mov(sl,tl);
3841       else emit_loadreg(rs1[i],tl);
3842       if(th>=0) {
3843         if(sh>=0) emit_mov(sh,th);
3844         else emit_loadreg(rs1[i]|64,th);
3845       }
3846     }
3847   }
3848 }
3849
3850 #ifndef fconv_assemble
3851 void fconv_assemble(int i,struct regstat *i_regs)
3852 {
3853   printf("Need fconv_assemble for this architecture.\n");
3854   exit(1);
3855 }
3856 #endif
3857
3858 #if 0
3859 void float_assemble(int i,struct regstat *i_regs)
3860 {
3861   printf("Need float_assemble for this architecture.\n");
3862   exit(1);
3863 }
3864 #endif
3865
3866 void syscall_assemble(int i,struct regstat *i_regs)
3867 {
3868   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3869   assert(ccreg==HOST_CCREG);
3870   assert(!is_delayslot);
3871   emit_movimm(start+i*4,EAX); // Get PC
3872   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right?  There should probably be an extra cycle...
3873   emit_jmp((int)jump_syscall_hle); // XXX
3874 }
3875
3876 void hlecall_assemble(int i,struct regstat *i_regs)
3877 {
3878   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3879   assert(ccreg==HOST_CCREG);
3880   assert(!is_delayslot);
3881   emit_movimm(start+i*4+4,0); // Get PC
3882   emit_movimm((int)psxHLEt[source[i]&7],1);
3883   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // XXX
3884   emit_jmp((int)jump_hlecall);
3885 }
3886
3887 void intcall_assemble(int i,struct regstat *i_regs)
3888 {
3889   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3890   assert(ccreg==HOST_CCREG);
3891   assert(!is_delayslot);
3892   emit_movimm(start+i*4,0); // Get PC
3893   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3894   emit_jmp((int)jump_intcall);
3895 }
3896
3897 void ds_assemble(int i,struct regstat *i_regs)
3898 {
3899   is_delayslot=1;
3900   switch(itype[i]) {
3901     case ALU:
3902       alu_assemble(i,i_regs);break;
3903     case IMM16:
3904       imm16_assemble(i,i_regs);break;
3905     case SHIFT:
3906       shift_assemble(i,i_regs);break;
3907     case SHIFTIMM:
3908       shiftimm_assemble(i,i_regs);break;
3909     case LOAD:
3910       load_assemble(i,i_regs);break;
3911     case LOADLR:
3912       loadlr_assemble(i,i_regs);break;
3913     case STORE:
3914       store_assemble(i,i_regs);break;
3915     case STORELR:
3916       storelr_assemble(i,i_regs);break;
3917     case COP0:
3918       cop0_assemble(i,i_regs);break;
3919     case COP1:
3920       cop1_assemble(i,i_regs);break;
3921     case C1LS:
3922       c1ls_assemble(i,i_regs);break;
3923     case COP2:
3924       cop2_assemble(i,i_regs);break;
3925     case C2LS:
3926       c2ls_assemble(i,i_regs);break;
3927     case C2OP:
3928       c2op_assemble(i,i_regs);break;
3929     case FCONV:
3930       fconv_assemble(i,i_regs);break;
3931     case FLOAT:
3932       float_assemble(i,i_regs);break;
3933     case FCOMP:
3934       fcomp_assemble(i,i_regs);break;
3935     case MULTDIV:
3936       multdiv_assemble(i,i_regs);break;
3937     case MOV:
3938       mov_assemble(i,i_regs);break;
3939     case SYSCALL:
3940     case HLECALL:
3941     case INTCALL:
3942     case SPAN:
3943     case UJUMP:
3944     case RJUMP:
3945     case CJUMP:
3946     case SJUMP:
3947     case FJUMP:
3948       printf("Jump in the delay slot.  This is probably a bug.\n");
3949   }
3950   is_delayslot=0;
3951 }
3952
3953 // Is the branch target a valid internal jump?
3954 int internal_branch(uint64_t i_is32,int addr)
3955 {
3956   if(addr&1) return 0; // Indirect (register) jump
3957   if(addr>=start && addr<start+slen*4-4)
3958   {
3959     int t=(addr-start)>>2;
3960     // Delay slots are not valid branch targets
3961     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
3962     // 64 -> 32 bit transition requires a recompile
3963     /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
3964     {
3965       if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
3966       else printf("optimizable: yes\n");
3967     }*/
3968     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
3969 #ifndef FORCE32
3970     if(requires_32bit[t]&~i_is32) return 0;
3971     else
3972 #endif
3973       return 1;
3974   }
3975   return 0;
3976 }
3977
3978 #ifndef wb_invalidate
3979 void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
3980   uint64_t u,uint64_t uu)
3981 {
3982   int hr;
3983   for(hr=0;hr<HOST_REGS;hr++) {
3984     if(hr!=EXCLUDE_REG) {
3985       if(pre[hr]!=entry[hr]) {
3986         if(pre[hr]>=0) {
3987           if((dirty>>hr)&1) {
3988             if(get_reg(entry,pre[hr])<0) {
3989               if(pre[hr]<64) {
3990                 if(!((u>>pre[hr])&1)) {
3991                   emit_storereg(pre[hr],hr);
3992                   if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
3993                     emit_sarimm(hr,31,hr);
3994                     emit_storereg(pre[hr]|64,hr);
3995                   }
3996                 }
3997               }else{
3998                 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
3999                   emit_storereg(pre[hr],hr);
4000                 }
4001               }
4002             }
4003           }
4004         }
4005       }
4006     }
4007   }
4008   // Move from one register to another (no writeback)
4009   for(hr=0;hr<HOST_REGS;hr++) {
4010     if(hr!=EXCLUDE_REG) {
4011       if(pre[hr]!=entry[hr]) {
4012         if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
4013           int nr;
4014           if((nr=get_reg(entry,pre[hr]))>=0) {
4015             emit_mov(hr,nr);
4016           }
4017         }
4018       }
4019     }
4020   }
4021 }
4022 #endif
4023
4024 // Load the specified registers
4025 // This only loads the registers given as arguments because
4026 // we don't want to load things that will be overwritten
4027 void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
4028 {
4029   int hr;
4030   // Load 32-bit regs
4031   for(hr=0;hr<HOST_REGS;hr++) {
4032     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4033       if(entry[hr]!=regmap[hr]) {
4034         if(regmap[hr]==rs1||regmap[hr]==rs2)
4035         {
4036           if(regmap[hr]==0) {
4037             emit_zeroreg(hr);
4038           }
4039           else
4040           {
4041             emit_loadreg(regmap[hr],hr);
4042           }
4043         }
4044       }
4045     }
4046   }
4047   //Load 64-bit regs
4048   for(hr=0;hr<HOST_REGS;hr++) {
4049     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4050       if(entry[hr]!=regmap[hr]) {
4051         if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
4052         {
4053           assert(regmap[hr]!=64);
4054           if((is32>>(regmap[hr]&63))&1) {
4055             int lr=get_reg(regmap,regmap[hr]-64);
4056             if(lr>=0)
4057               emit_sarimm(lr,31,hr);
4058             else
4059               emit_loadreg(regmap[hr],hr);
4060           }
4061           else
4062           {
4063             emit_loadreg(regmap[hr],hr);
4064           }
4065         }
4066       }
4067     }
4068   }
4069 }
4070
4071 // Load registers prior to the start of a loop
4072 // so that they are not loaded within the loop
4073 static void loop_preload(signed char pre[],signed char entry[])
4074 {
4075   int hr;
4076   for(hr=0;hr<HOST_REGS;hr++) {
4077     if(hr!=EXCLUDE_REG) {
4078       if(pre[hr]!=entry[hr]) {
4079         if(entry[hr]>=0) {
4080           if(get_reg(pre,entry[hr])<0) {
4081             assem_debug("loop preload:\n");
4082             //printf("loop preload: %d\n",hr);
4083             if(entry[hr]==0) {
4084               emit_zeroreg(hr);
4085             }
4086             else if(entry[hr]<TEMPREG)
4087             {
4088               emit_loadreg(entry[hr],hr);
4089             }
4090             else if(entry[hr]-64<TEMPREG)
4091             {
4092               emit_loadreg(entry[hr],hr);
4093             }
4094           }
4095         }
4096       }
4097     }
4098   }
4099 }
4100
4101 // Generate address for load/store instruction
4102 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
4103 void address_generation(int i,struct regstat *i_regs,signed char entry[])
4104 {
4105   if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
4106     int ra=-1;
4107     int agr=AGEN1+(i&1);
4108     int mgr=MGEN1+(i&1);
4109     if(itype[i]==LOAD) {
4110       ra=get_reg(i_regs->regmap,rt1[i]);
4111       if(ra<0) ra=get_reg(i_regs->regmap,-1);
4112       assert(ra>=0);
4113     }
4114     if(itype[i]==LOADLR) {
4115       ra=get_reg(i_regs->regmap,FTEMP);
4116     }
4117     if(itype[i]==STORE||itype[i]==STORELR) {
4118       ra=get_reg(i_regs->regmap,agr);
4119       if(ra<0) ra=get_reg(i_regs->regmap,-1);
4120     }
4121     if(itype[i]==C1LS||itype[i]==C2LS) {
4122       if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
4123         ra=get_reg(i_regs->regmap,FTEMP);
4124       else { // SWC1/SDC1/SWC2/SDC2
4125         ra=get_reg(i_regs->regmap,agr);
4126         if(ra<0) ra=get_reg(i_regs->regmap,-1);
4127       }
4128     }
4129     int rs=get_reg(i_regs->regmap,rs1[i]);
4130     int rm=get_reg(i_regs->regmap,TLREG);
4131     if(ra>=0) {
4132       int offset=imm[i];
4133       int c=(i_regs->wasconst>>rs)&1;
4134       if(rs1[i]==0) {
4135         // Using r0 as a base address
4136         /*if(rm>=0) {
4137           if(!entry||entry[rm]!=mgr) {
4138             generate_map_const(offset,rm);
4139           } // else did it in the previous cycle
4140         }*/
4141         if(!entry||entry[ra]!=agr) {
4142           if (opcode[i]==0x22||opcode[i]==0x26) {
4143             emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4144           }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4145             emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4146           }else{
4147             emit_movimm(offset,ra);
4148           }
4149         } // else did it in the previous cycle
4150       }
4151       else if(rs<0) {
4152         if(!entry||entry[ra]!=rs1[i])
4153           emit_loadreg(rs1[i],ra);
4154         //if(!entry||entry[ra]!=rs1[i])
4155         //  printf("poor load scheduling!\n");
4156       }
4157       else if(c) {
4158         if(rm>=0) {
4159           if(!entry||entry[rm]!=mgr) {
4160             if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
4161               // Stores to memory go thru the mapper to detect self-modifying
4162               // code, loads don't.
4163               if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
4164                  (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
4165                 generate_map_const(constmap[i][rs]+offset,rm);
4166             }else{
4167               if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
4168                 generate_map_const(constmap[i][rs]+offset,rm);
4169             }
4170           }
4171         }
4172         if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
4173           if(!entry||entry[ra]!=agr) {
4174             if (opcode[i]==0x22||opcode[i]==0x26) {
4175               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4176             }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4177               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4178             }else{
4179               #ifdef HOST_IMM_ADDR32
4180               if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4181                  (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4182               #endif
4183               emit_movimm(constmap[i][rs]+offset,ra);
4184             }
4185           } // else did it in the previous cycle
4186         } // else load_consts already did it
4187       }
4188       if(offset&&!c&&rs1[i]) {
4189         if(rs>=0) {
4190           emit_addimm(rs,offset,ra);
4191         }else{
4192           emit_addimm(ra,offset,ra);
4193         }
4194       }
4195     }
4196   }
4197   // Preload constants for next instruction
4198   if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
4199     int agr,ra;
4200     #ifndef HOST_IMM_ADDR32
4201     // Mapper entry
4202     agr=MGEN1+((i+1)&1);
4203     ra=get_reg(i_regs->regmap,agr);
4204     if(ra>=0) {
4205       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4206       int offset=imm[i+1];
4207       int c=(regs[i+1].wasconst>>rs)&1;
4208       if(c) {
4209         if(itype[i+1]==STORE||itype[i+1]==STORELR
4210            ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
4211           // Stores to memory go thru the mapper to detect self-modifying
4212           // code, loads don't.
4213           if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4214              (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
4215             generate_map_const(constmap[i+1][rs]+offset,ra);
4216         }else{
4217           if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4218             generate_map_const(constmap[i+1][rs]+offset,ra);
4219         }
4220       }
4221       /*else if(rs1[i]==0) {
4222         generate_map_const(offset,ra);
4223       }*/
4224     }
4225     #endif
4226     // Actual address
4227     agr=AGEN1+((i+1)&1);
4228     ra=get_reg(i_regs->regmap,agr);
4229     if(ra>=0) {
4230       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4231       int offset=imm[i+1];
4232       int c=(regs[i+1].wasconst>>rs)&1;
4233       if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4234         if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4235           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4236         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4237           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4238         }else{
4239           #ifdef HOST_IMM_ADDR32
4240           if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4241              (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4242           #endif
4243           emit_movimm(constmap[i+1][rs]+offset,ra);
4244         }
4245       }
4246       else if(rs1[i+1]==0) {
4247         // Using r0 as a base address
4248         if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4249           emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4250         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4251           emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4252         }else{
4253           emit_movimm(offset,ra);
4254         }
4255       }
4256     }
4257   }
4258 }
4259
4260 int get_final_value(int hr, int i, int *value)
4261 {
4262   int reg=regs[i].regmap[hr];
4263   while(i<slen-1) {
4264     if(regs[i+1].regmap[hr]!=reg) break;
4265     if(!((regs[i+1].isconst>>hr)&1)) break;
4266     if(bt[i+1]) break;
4267     i++;
4268   }
4269   if(i<slen-1) {
4270     if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4271       *value=constmap[i][hr];
4272       return 1;
4273     }
4274     if(!bt[i+1]) {
4275       if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4276         // Load in delay slot, out-of-order execution
4277         if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4278         {
4279           #ifdef HOST_IMM_ADDR32
4280           if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4281           #endif
4282           // Precompute load address
4283           *value=constmap[i][hr]+imm[i+2];
4284           return 1;
4285         }
4286       }
4287       if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4288       {
4289         #ifdef HOST_IMM_ADDR32
4290         if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4291         #endif
4292         // Precompute load address
4293         *value=constmap[i][hr]+imm[i+1];
4294         //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4295         return 1;
4296       }
4297     }
4298   }
4299   *value=constmap[i][hr];
4300   //printf("c=%x\n",(int)constmap[i][hr]);
4301   if(i==slen-1) return 1;
4302   if(reg<64) {
4303     return !((unneeded_reg[i+1]>>reg)&1);
4304   }else{
4305     return !((unneeded_reg_upper[i+1]>>reg)&1);
4306   }
4307 }
4308
4309 // Load registers with known constants
4310 void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4311 {
4312   int hr;
4313   // Load 32-bit regs
4314   for(hr=0;hr<HOST_REGS;hr++) {
4315     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4316       //if(entry[hr]!=regmap[hr]) {
4317       if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4318         if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4319           int value;
4320           if(get_final_value(hr,i,&value)) {
4321             if(value==0) {
4322               emit_zeroreg(hr);
4323             }
4324             else {
4325               emit_movimm(value,hr);
4326             }
4327           }
4328         }
4329       }
4330     }
4331   }
4332   // Load 64-bit regs
4333   for(hr=0;hr<HOST_REGS;hr++) {
4334     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4335       //if(entry[hr]!=regmap[hr]) {
4336       if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4337         if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4338           if((is32>>(regmap[hr]&63))&1) {
4339             int lr=get_reg(regmap,regmap[hr]-64);
4340             assert(lr>=0);
4341             emit_sarimm(lr,31,hr);
4342           }
4343           else
4344           {
4345             int value;
4346             if(get_final_value(hr,i,&value)) {
4347               if(value==0) {
4348                 emit_zeroreg(hr);
4349               }
4350               else {
4351                 emit_movimm(value,hr);
4352               }
4353             }
4354           }
4355         }
4356       }
4357     }
4358   }
4359 }
4360 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4361 {
4362   int hr;
4363   // Load 32-bit regs
4364   for(hr=0;hr<HOST_REGS;hr++) {
4365     if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4366       if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4367         int value=constmap[i][hr];
4368         if(value==0) {
4369           emit_zeroreg(hr);
4370         }
4371         else {
4372           emit_movimm(value,hr);
4373         }
4374       }
4375     }
4376   }
4377   // Load 64-bit regs
4378   for(hr=0;hr<HOST_REGS;hr++) {
4379     if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4380       if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4381         if((is32>>(regmap[hr]&63))&1) {
4382           int lr=get_reg(regmap,regmap[hr]-64);
4383           assert(lr>=0);
4384           emit_sarimm(lr,31,hr);
4385         }
4386         else
4387         {
4388           int value=constmap[i][hr];
4389           if(value==0) {
4390             emit_zeroreg(hr);
4391           }
4392           else {
4393             emit_movimm(value,hr);
4394           }
4395         }
4396       }
4397     }
4398   }
4399 }
4400
4401 // Write out all dirty registers (except cycle count)
4402 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4403 {
4404   int hr;
4405   for(hr=0;hr<HOST_REGS;hr++) {
4406     if(hr!=EXCLUDE_REG) {
4407       if(i_regmap[hr]>0) {
4408         if(i_regmap[hr]!=CCREG) {
4409           if((i_dirty>>hr)&1) {
4410             if(i_regmap[hr]<64) {
4411               emit_storereg(i_regmap[hr],hr);
4412 #ifndef FORCE32
4413               if( ((i_is32>>i_regmap[hr])&1) ) {
4414                 #ifdef DESTRUCTIVE_WRITEBACK
4415                 emit_sarimm(hr,31,hr);
4416                 emit_storereg(i_regmap[hr]|64,hr);
4417                 #else
4418                 emit_sarimm(hr,31,HOST_TEMPREG);
4419                 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4420                 #endif
4421               }
4422 #endif
4423             }else{
4424               if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4425                 emit_storereg(i_regmap[hr],hr);
4426               }
4427             }
4428           }
4429         }
4430       }
4431     }
4432   }
4433 }
4434 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4435 // This writes the registers not written by store_regs_bt
4436 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4437 {
4438   int hr;
4439   int t=(addr-start)>>2;
4440   for(hr=0;hr<HOST_REGS;hr++) {
4441     if(hr!=EXCLUDE_REG) {
4442       if(i_regmap[hr]>0) {
4443         if(i_regmap[hr]!=CCREG) {
4444           if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4445             if((i_dirty>>hr)&1) {
4446               if(i_regmap[hr]<64) {
4447                 emit_storereg(i_regmap[hr],hr);
4448 #ifndef FORCE32
4449                 if( ((i_is32>>i_regmap[hr])&1) ) {
4450                   #ifdef DESTRUCTIVE_WRITEBACK
4451                   emit_sarimm(hr,31,hr);
4452                   emit_storereg(i_regmap[hr]|64,hr);
4453                   #else
4454                   emit_sarimm(hr,31,HOST_TEMPREG);
4455                   emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4456                   #endif
4457                 }
4458 #endif
4459               }else{
4460                 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4461                   emit_storereg(i_regmap[hr],hr);
4462                 }
4463               }
4464             }
4465           }
4466         }
4467       }
4468     }
4469   }
4470 }
4471
4472 // Load all registers (except cycle count)
4473 void load_all_regs(signed char i_regmap[])
4474 {
4475   int hr;
4476   for(hr=0;hr<HOST_REGS;hr++) {
4477     if(hr!=EXCLUDE_REG) {
4478       if(i_regmap[hr]==0) {
4479         emit_zeroreg(hr);
4480       }
4481       else
4482       if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4483       {
4484         emit_loadreg(i_regmap[hr],hr);
4485       }
4486     }
4487   }
4488 }
4489
4490 // Load all current registers also needed by next instruction
4491 void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4492 {
4493   int hr;
4494   for(hr=0;hr<HOST_REGS;hr++) {
4495     if(hr!=EXCLUDE_REG) {
4496       if(get_reg(next_regmap,i_regmap[hr])>=0) {
4497         if(i_regmap[hr]==0) {
4498           emit_zeroreg(hr);
4499         }
4500         else
4501         if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4502         {
4503           emit_loadreg(i_regmap[hr],hr);
4504         }
4505       }
4506     }
4507   }
4508 }
4509
4510 // Load all regs, storing cycle count if necessary
4511 void load_regs_entry(int t)
4512 {
4513   int hr;
4514   if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER,HOST_CCREG);
4515   else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t]*CLOCK_DIVIDER,HOST_CCREG);
4516   if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4517     emit_storereg(CCREG,HOST_CCREG);
4518   }
4519   // Load 32-bit regs
4520   for(hr=0;hr<HOST_REGS;hr++) {
4521     if(regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
4522       if(regs[t].regmap_entry[hr]==0) {
4523         emit_zeroreg(hr);
4524       }
4525       else if(regs[t].regmap_entry[hr]!=CCREG)
4526       {
4527         emit_loadreg(regs[t].regmap_entry[hr],hr);
4528       }
4529     }
4530   }
4531   // Load 64-bit regs
4532   for(hr=0;hr<HOST_REGS;hr++) {
4533     if(regs[t].regmap_entry[hr]>=64&&regs[t].regmap_entry[hr]<TEMPREG+64) {
4534       assert(regs[t].regmap_entry[hr]!=64);
4535       if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4536         int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4537         if(lr<0) {
4538           emit_loadreg(regs[t].regmap_entry[hr],hr);
4539         }
4540         else
4541         {
4542           emit_sarimm(lr,31,hr);
4543         }
4544       }
4545       else
4546       {
4547         emit_loadreg(regs[t].regmap_entry[hr],hr);
4548       }
4549     }
4550   }
4551 }
4552
4553 // Store dirty registers prior to branch
4554 void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4555 {
4556   if(internal_branch(i_is32,addr))
4557   {
4558     int t=(addr-start)>>2;
4559     int hr;
4560     for(hr=0;hr<HOST_REGS;hr++) {
4561       if(hr!=EXCLUDE_REG) {
4562         if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4563           if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4564             if((i_dirty>>hr)&1) {
4565               if(i_regmap[hr]<64) {
4566                 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4567                   emit_storereg(i_regmap[hr],hr);
4568                   if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4569                     #ifdef DESTRUCTIVE_WRITEBACK
4570                     emit_sarimm(hr,31,hr);
4571                     emit_storereg(i_regmap[hr]|64,hr);
4572                     #else
4573                     emit_sarimm(hr,31,HOST_TEMPREG);
4574                     emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4575                     #endif
4576                   }
4577                 }
4578               }else{
4579                 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4580                   emit_storereg(i_regmap[hr],hr);
4581                 }
4582               }
4583             }
4584           }
4585         }
4586       }
4587     }
4588   }
4589   else
4590   {
4591     // Branch out of this block, write out all dirty regs
4592     wb_dirtys(i_regmap,i_is32,i_dirty);
4593   }
4594 }
4595
4596 // Load all needed registers for branch target
4597 void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4598 {
4599   //if(addr>=start && addr<(start+slen*4))
4600   if(internal_branch(i_is32,addr))
4601   {
4602     int t=(addr-start)>>2;
4603     int hr;
4604     // Store the cycle count before loading something else
4605     if(i_regmap[HOST_CCREG]!=CCREG) {
4606       assert(i_regmap[HOST_CCREG]==-1);
4607     }
4608     if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4609       emit_storereg(CCREG,HOST_CCREG);
4610     }
4611     // Load 32-bit regs
4612     for(hr=0;hr<HOST_REGS;hr++) {
4613       if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
4614         #ifdef DESTRUCTIVE_WRITEBACK
4615         if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4616         #else
4617         if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4618         #endif
4619           if(regs[t].regmap_entry[hr]==0) {
4620             emit_zeroreg(hr);
4621           }
4622           else if(regs[t].regmap_entry[hr]!=CCREG)
4623           {
4624             emit_loadreg(regs[t].regmap_entry[hr],hr);
4625           }
4626         }
4627       }
4628     }
4629     //Load 64-bit regs
4630     for(hr=0;hr<HOST_REGS;hr++) {
4631       if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=64&&regs[t].regmap_entry[hr]<TEMPREG+64) {
4632         if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4633           assert(regs[t].regmap_entry[hr]!=64);
4634           if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4635             int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4636             if(lr<0) {
4637               emit_loadreg(regs[t].regmap_entry[hr],hr);
4638             }
4639             else
4640             {
4641               emit_sarimm(lr,31,hr);
4642             }
4643           }
4644           else
4645           {
4646             emit_loadreg(regs[t].regmap_entry[hr],hr);
4647           }
4648         }
4649         else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4650           int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4651           assert(lr>=0);
4652           emit_sarimm(lr,31,hr);
4653         }
4654       }
4655     }
4656   }
4657 }
4658
4659 int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4660 {
4661   if(addr>=start && addr<start+slen*4-4)
4662   {
4663     int t=(addr-start)>>2;
4664     int hr;
4665     if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4666     for(hr=0;hr<HOST_REGS;hr++)
4667     {
4668       if(hr!=EXCLUDE_REG)
4669       {
4670         if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4671         {
4672           if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
4673           {
4674             return 0;
4675           }
4676           else
4677           if((i_dirty>>hr)&1)
4678           {
4679             if(i_regmap[hr]<TEMPREG)
4680             {
4681               if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4682                 return 0;
4683             }
4684             else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
4685             {
4686               if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4687                 return 0;
4688             }
4689           }
4690         }
4691         else // Same register but is it 32-bit or dirty?
4692         if(i_regmap[hr]>=0)
4693         {
4694           if(!((regs[t].dirty>>hr)&1))
4695           {
4696             if((i_dirty>>hr)&1)
4697             {
4698               if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4699               {
4700                 //printf("%x: dirty no match\n",addr);
4701                 return 0;
4702               }
4703             }
4704           }
4705           if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4706           {
4707             //printf("%x: is32 no match\n",addr);
4708             return 0;
4709           }
4710         }
4711       }
4712     }
4713     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4714 #ifndef FORCE32
4715     if(requires_32bit[t]&~i_is32) return 0;
4716 #endif
4717     // Delay slots are not valid branch targets
4718     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4719     // Delay slots require additional processing, so do not match
4720     if(is_ds[t]) return 0;
4721   }
4722   else
4723   {
4724     int hr;
4725     for(hr=0;hr<HOST_REGS;hr++)
4726     {
4727       if(hr!=EXCLUDE_REG)
4728       {
4729         if(i_regmap[hr]>=0)
4730         {
4731           if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4732           {
4733             if((i_dirty>>hr)&1)
4734             {
4735               return 0;
4736             }
4737           }
4738         }
4739       }
4740     }
4741   }
4742   return 1;
4743 }
4744
4745 // Used when a branch jumps into the delay slot of another branch
4746 void ds_assemble_entry(int i)
4747 {
4748   int t=(ba[i]-start)>>2;
4749   if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4750   assem_debug("Assemble delay slot at %x\n",ba[i]);
4751   assem_debug("<->\n");
4752   if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
4753     wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4754   load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4755   address_generation(t,&regs[t],regs[t].regmap_entry);
4756   if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
4757     load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4758   cop1_usable=0;
4759   is_delayslot=0;
4760   switch(itype[t]) {
4761     case ALU:
4762       alu_assemble(t,&regs[t]);break;
4763     case IMM16:
4764       imm16_assemble(t,&regs[t]);break;
4765     case SHIFT:
4766       shift_assemble(t,&regs[t]);break;
4767     case SHIFTIMM:
4768       shiftimm_assemble(t,&regs[t]);break;
4769     case LOAD:
4770       load_assemble(t,&regs[t]);break;
4771     case LOADLR:
4772       loadlr_assemble(t,&regs[t]);break;
4773     case STORE:
4774       store_assemble(t,&regs[t]);break;
4775     case STORELR:
4776       storelr_assemble(t,&regs[t]);break;
4777     case COP0:
4778       cop0_assemble(t,&regs[t]);break;
4779     case COP1:
4780       cop1_assemble(t,&regs[t]);break;
4781     case C1LS:
4782       c1ls_assemble(t,&regs[t]);break;
4783     case COP2:
4784       cop2_assemble(t,&regs[t]);break;
4785     case C2LS:
4786       c2ls_assemble(t,&regs[t]);break;
4787     case C2OP:
4788       c2op_assemble(t,&regs[t]);break;
4789     case FCONV:
4790       fconv_assemble(t,&regs[t]);break;
4791     case FLOAT:
4792       float_assemble(t,&regs[t]);break;
4793     case FCOMP:
4794       fcomp_assemble(t,&regs[t]);break;
4795     case MULTDIV:
4796       multdiv_assemble(t,&regs[t]);break;
4797     case MOV:
4798       mov_assemble(t,&regs[t]);break;
4799     case SYSCALL:
4800     case HLECALL:
4801     case INTCALL:
4802     case SPAN:
4803     case UJUMP:
4804     case RJUMP:
4805     case CJUMP:
4806     case SJUMP:
4807     case FJUMP:
4808       printf("Jump in the delay slot.  This is probably a bug.\n");
4809   }
4810   store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4811   load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4812   if(internal_branch(regs[t].is32,ba[i]+4))
4813     assem_debug("branch: internal\n");
4814   else
4815     assem_debug("branch: external\n");
4816   assert(internal_branch(regs[t].is32,ba[i]+4));
4817   add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4818   emit_jmp(0);
4819 }
4820
4821 void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4822 {
4823   int count;
4824   int jaddr;
4825   int idle=0;
4826   if(itype[i]==RJUMP)
4827   {
4828     *adj=0;
4829   }
4830   //if(ba[i]>=start && ba[i]<(start+slen*4))
4831   if(internal_branch(branch_regs[i].is32,ba[i]))
4832   {
4833     int t=(ba[i]-start)>>2;
4834     if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4835     else *adj=ccadj[t];
4836   }
4837   else
4838   {
4839     *adj=0;
4840   }
4841   count=ccadj[i];
4842   if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4843     // Idle loop
4844     if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4845     idle=(int)out;
4846     //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4847     emit_andimm(HOST_CCREG,3,HOST_CCREG);
4848     jaddr=(int)out;
4849     emit_jmp(0);
4850   }
4851   else if(*adj==0||invert) {
4852     emit_addimm_and_set_flags(CLOCK_DIVIDER*(count+2),HOST_CCREG);
4853     jaddr=(int)out;
4854     emit_jns(0);
4855   }
4856   else
4857   {
4858     emit_cmpimm(HOST_CCREG,-CLOCK_DIVIDER*(count+2));
4859     jaddr=(int)out;
4860     emit_jns(0);
4861   }
4862   add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4863 }
4864
4865 void do_ccstub(int n)
4866 {
4867   literal_pool(256);
4868   assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
4869   set_jump_target(stubs[n][1],(int)out);
4870   int i=stubs[n][4];
4871   if(stubs[n][6]==NULLDS) {
4872     // Delay slot instruction is nullified ("likely" branch)
4873     wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4874   }
4875   else if(stubs[n][6]!=TAKEN) {
4876     wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4877   }
4878   else {
4879     if(internal_branch(branch_regs[i].is32,ba[i]))
4880       wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4881   }
4882   if(stubs[n][5]!=-1)
4883   {
4884     // Save PC as return address
4885     emit_movimm(stubs[n][5],EAX);
4886     emit_writeword(EAX,(int)&pcaddr);
4887   }
4888   else
4889   {
4890     // Return address depends on which way the branch goes
4891     if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
4892     {
4893       int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4894       int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4895       int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4896       int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4897       if(rs1[i]==0)
4898       {
4899         s1l=s2l;s1h=s2h;
4900         s2l=s2h=-1;
4901       }
4902       else if(rs2[i]==0)
4903       {
4904         s2l=s2h=-1;
4905       }
4906       if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
4907         s1h=s2h=-1;
4908       }
4909       assert(s1l>=0);
4910       #ifdef DESTRUCTIVE_WRITEBACK
4911       if(rs1[i]) {
4912         if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
4913           emit_loadreg(rs1[i],s1l);
4914       }
4915       else {
4916         if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
4917           emit_loadreg(rs2[i],s1l);
4918       }
4919       if(s2l>=0)
4920         if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
4921           emit_loadreg(rs2[i],s2l);
4922       #endif
4923       int hr=0;
4924       int addr=-1,alt=-1,ntaddr=-1;
4925       while(hr<HOST_REGS)
4926       {
4927         if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4928            (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4929            (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4930         {
4931           addr=hr++;break;
4932         }
4933         hr++;
4934       }
4935       while(hr<HOST_REGS)
4936       {
4937         if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4938            (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4939            (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4940         {
4941           alt=hr++;break;
4942         }
4943         hr++;
4944       }
4945       if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
4946       {
4947         while(hr<HOST_REGS)
4948         {
4949           if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4950              (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4951              (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4952           {
4953             ntaddr=hr;break;
4954           }
4955           hr++;
4956         }
4957         assert(hr<HOST_REGS);
4958       }
4959       if((opcode[i]&0x2f)==4) // BEQ
4960       {
4961         #ifdef HAVE_CMOV_IMM
4962         if(s1h<0) {
4963           if(s2l>=0) emit_cmp(s1l,s2l);
4964           else emit_test(s1l,s1l);
4965           emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
4966         }
4967         else
4968         #endif
4969         {
4970           emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4971           if(s1h>=0) {
4972             if(s2h>=0) emit_cmp(s1h,s2h);
4973             else emit_test(s1h,s1h);
4974             emit_cmovne_reg(alt,addr);
4975           }
4976           if(s2l>=0) emit_cmp(s1l,s2l);
4977           else emit_test(s1l,s1l);
4978           emit_cmovne_reg(alt,addr);
4979         }
4980       }
4981       if((opcode[i]&0x2f)==5) // BNE
4982       {
4983         #ifdef HAVE_CMOV_IMM
4984         if(s1h<0) {
4985           if(s2l>=0) emit_cmp(s1l,s2l);
4986           else emit_test(s1l,s1l);
4987           emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
4988         }
4989         else
4990         #endif
4991         {
4992           emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
4993           if(s1h>=0) {
4994             if(s2h>=0) emit_cmp(s1h,s2h);
4995             else emit_test(s1h,s1h);
4996             emit_cmovne_reg(alt,addr);
4997           }
4998           if(s2l>=0) emit_cmp(s1l,s2l);
4999           else emit_test(s1l,s1l);
5000           emit_cmovne_reg(alt,addr);
5001         }
5002       }
5003       if((opcode[i]&0x2f)==6) // BLEZ
5004       {
5005         //emit_movimm(ba[i],alt);
5006         //emit_movimm(start+i*4+8,addr);
5007         emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5008         emit_cmpimm(s1l,1);
5009         if(s1h>=0) emit_mov(addr,ntaddr);
5010         emit_cmovl_reg(alt,addr);
5011         if(s1h>=0) {
5012           emit_test(s1h,s1h);
5013           emit_cmovne_reg(ntaddr,addr);
5014           emit_cmovs_reg(alt,addr);
5015         }
5016       }
5017       if((opcode[i]&0x2f)==7) // BGTZ
5018       {
5019         //emit_movimm(ba[i],addr);
5020         //emit_movimm(start+i*4+8,ntaddr);
5021         emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5022         emit_cmpimm(s1l,1);
5023         if(s1h>=0) emit_mov(addr,alt);
5024         emit_cmovl_reg(ntaddr,addr);
5025         if(s1h>=0) {
5026           emit_test(s1h,s1h);
5027           emit_cmovne_reg(alt,addr);
5028           emit_cmovs_reg(ntaddr,addr);
5029         }
5030       }
5031       if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
5032       {
5033         //emit_movimm(ba[i],alt);
5034         //emit_movimm(start+i*4+8,addr);
5035         emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5036         if(s1h>=0) emit_test(s1h,s1h);
5037         else emit_test(s1l,s1l);
5038         emit_cmovs_reg(alt,addr);
5039       }
5040       if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
5041       {
5042         //emit_movimm(ba[i],addr);
5043         //emit_movimm(start+i*4+8,alt);
5044         emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5045         if(s1h>=0) emit_test(s1h,s1h);
5046         else emit_test(s1l,s1l);
5047         emit_cmovs_reg(alt,addr);
5048       }
5049       if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
5050         if(source[i]&0x10000) // BC1T
5051         {
5052           //emit_movimm(ba[i],alt);
5053           //emit_movimm(start+i*4+8,addr);
5054           emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5055           emit_testimm(s1l,0x800000);
5056           emit_cmovne_reg(alt,addr);
5057         }
5058         else // BC1F
5059         {
5060           //emit_movimm(ba[i],addr);
5061           //emit_movimm(start+i*4+8,alt);
5062           emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5063           emit_testimm(s1l,0x800000);
5064           emit_cmovne_reg(alt,addr);
5065         }
5066       }
5067       emit_writeword(addr,(int)&pcaddr);
5068     }
5069     else
5070     if(itype[i]==RJUMP)
5071     {
5072       int r=get_reg(branch_regs[i].regmap,rs1[i]);
5073       if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5074         r=get_reg(branch_regs[i].regmap,RTEMP);
5075       }
5076       emit_writeword(r,(int)&pcaddr);
5077     }
5078     else {printf("Unknown branch type in do_ccstub\n");exit(1);}
5079   }
5080   // Update cycle count
5081   assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5082   if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
5083   emit_call((int)cc_interrupt);
5084   if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
5085   if(stubs[n][6]==TAKEN) {
5086     if(internal_branch(branch_regs[i].is32,ba[i]))
5087       load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
5088     else if(itype[i]==RJUMP) {
5089       if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5090         emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5091       else
5092         emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
5093     }
5094   }else if(stubs[n][6]==NOTTAKEN) {
5095     if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5096     else load_all_regs(branch_regs[i].regmap);
5097   }else if(stubs[n][6]==NULLDS) {
5098     // Delay slot instruction is nullified ("likely" branch)
5099     if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5100     else load_all_regs(regs[i].regmap);
5101   }else{
5102     load_all_regs(branch_regs[i].regmap);
5103   }
5104   emit_jmp(stubs[n][2]); // return address
5105
5106   /* This works but uses a lot of memory...
5107   emit_readword((int)&last_count,ECX);
5108   emit_add(HOST_CCREG,ECX,EAX);
5109   emit_writeword(EAX,(int)&Count);
5110   emit_call((int)gen_interupt);
5111   emit_readword((int)&Count,HOST_CCREG);
5112   emit_readword((int)&next_interupt,EAX);
5113   emit_readword((int)&pending_exception,EBX);
5114   emit_writeword(EAX,(int)&last_count);
5115   emit_sub(HOST_CCREG,EAX,HOST_CCREG);
5116   emit_test(EBX,EBX);
5117   int jne_instr=(int)out;
5118   emit_jne(0);
5119   if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
5120   load_all_regs(branch_regs[i].regmap);
5121   emit_jmp(stubs[n][2]); // return address
5122   set_jump_target(jne_instr,(int)out);
5123   emit_readword((int)&pcaddr,EAX);
5124   // Call get_addr_ht instead of doing the hash table here.
5125   // This code is executed infrequently and takes up a lot of space
5126   // so smaller is better.
5127   emit_storereg(CCREG,HOST_CCREG);
5128   emit_pushreg(EAX);
5129   emit_call((int)get_addr_ht);
5130   emit_loadreg(CCREG,HOST_CCREG);
5131   emit_addimm(ESP,4,ESP);
5132   emit_jmpreg(EAX);*/
5133 }
5134
5135 add_to_linker(int addr,int target,int ext)
5136 {
5137   link_addr[linkcount][0]=addr;
5138   link_addr[linkcount][1]=target;
5139   link_addr[linkcount][2]=ext;
5140   linkcount++;
5141 }
5142
5143 void ujump_assemble(int i,struct regstat *i_regs)
5144 {
5145   signed char *i_regmap=i_regs->regmap;
5146   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5147   address_generation(i+1,i_regs,regs[i].regmap_entry);
5148   #ifdef REG_PREFETCH
5149   int temp=get_reg(branch_regs[i].regmap,PTEMP);
5150   if(rt1[i]==31&&temp>=0)
5151   {
5152     int return_address=start+i*4+8;
5153     if(get_reg(branch_regs[i].regmap,31)>0)
5154     if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5155   }
5156   #endif
5157   if(rt1[i]==31) {
5158     int rt;
5159     unsigned int return_address;
5160     rt=get_reg(branch_regs[i].regmap,31);
5161     assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5162     //assert(rt>=0);
5163     return_address=start+i*4+8;
5164     if(rt>=0) {
5165       #ifdef USE_MINI_HT
5166       if(internal_branch(branch_regs[i].is32,return_address)&&rt1[i+1]!=31) {
5167         int temp=-1; // note: must be ds-safe
5168         #ifdef HOST_TEMPREG
5169         temp=HOST_TEMPREG;
5170         #endif
5171         if(temp>=0) do_miniht_insert(return_address,rt,temp);
5172         else emit_movimm(return_address,rt);
5173       }
5174       else
5175       #endif
5176       {
5177         #ifdef REG_PREFETCH
5178         if(temp>=0)
5179         {
5180           if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5181         }
5182         #endif
5183         emit_movimm(return_address,rt); // PC into link register
5184         #ifdef IMM_PREFETCH
5185         emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5186         #endif
5187       }
5188     }
5189   }
5190   ds_assemble(i+1,i_regs);
5191   uint64_t bc_unneeded=branch_regs[i].u;
5192   uint64_t bc_unneeded_upper=branch_regs[i].uu;
5193   bc_unneeded|=1|(1LL<<rt1[i]);
5194   bc_unneeded_upper|=1|(1LL<<rt1[i]);
5195   wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5196                 bc_unneeded,bc_unneeded_upper);
5197   load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5198   int cc,adj;
5199   cc=get_reg(branch_regs[i].regmap,CCREG);
5200   assert(cc==HOST_CCREG);
5201   store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5202   #ifdef REG_PREFETCH
5203   if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5204   #endif
5205   do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5206   if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5207   load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5208   if(internal_branch(branch_regs[i].is32,ba[i]))
5209     assem_debug("branch: internal\n");
5210   else
5211     assem_debug("branch: external\n");
5212   if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5213     ds_assemble_entry(i);
5214   }
5215   else {
5216     add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5217     emit_jmp(0);
5218   }
5219 }
5220
5221 void rjump_assemble(int i,struct regstat *i_regs)
5222 {
5223   signed char *i_regmap=i_regs->regmap;
5224   int temp;
5225   int rs,cc,adj;
5226   rs=get_reg(branch_regs[i].regmap,rs1[i]);
5227   assert(rs>=0);
5228   if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5229     // Delay slot abuse, make a copy of the branch address register
5230     temp=get_reg(branch_regs[i].regmap,RTEMP);
5231     assert(temp>=0);
5232     assert(regs[i].regmap[temp]==RTEMP);
5233     emit_mov(rs,temp);
5234     rs=temp;
5235   }
5236   address_generation(i+1,i_regs,regs[i].regmap_entry);
5237   #ifdef REG_PREFETCH
5238   if(rt1[i]==31)
5239   {
5240     if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5241       int return_address=start+i*4+8;
5242       if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5243     }
5244   }
5245   #endif
5246   #ifdef USE_MINI_HT
5247   if(rs1[i]==31) {
5248     int rh=get_reg(regs[i].regmap,RHASH);
5249     if(rh>=0) do_preload_rhash(rh);
5250   }
5251   #endif
5252   ds_assemble(i+1,i_regs);
5253   uint64_t bc_unneeded=branch_regs[i].u;
5254   uint64_t bc_unneeded_upper=branch_regs[i].uu;
5255   bc_unneeded|=1|(1LL<<rt1[i]);
5256   bc_unneeded_upper|=1|(1LL<<rt1[i]);
5257   bc_unneeded&=~(1LL<<rs1[i]);
5258   wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5259                 bc_unneeded,bc_unneeded_upper);
5260   load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5261   if(rt1[i]!=0) {
5262     int rt,return_address;
5263     assert(rt1[i+1]!=rt1[i]);
5264     assert(rt2[i+1]!=rt1[i]);
5265     rt=get_reg(branch_regs[i].regmap,rt1[i]);
5266     assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5267     assert(rt>=0);
5268     return_address=start+i*4+8;
5269     #ifdef REG_PREFETCH
5270     if(temp>=0)
5271     {
5272       if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5273     }
5274     #endif
5275     emit_movimm(return_address,rt); // PC into link register
5276     #ifdef IMM_PREFETCH
5277     emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5278     #endif
5279   }
5280   cc=get_reg(branch_regs[i].regmap,CCREG);
5281   assert(cc==HOST_CCREG);
5282   #ifdef USE_MINI_HT
5283   int rh=get_reg(branch_regs[i].regmap,RHASH);
5284   int ht=get_reg(branch_regs[i].regmap,RHTBL);
5285   if(rs1[i]==31) {
5286     if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5287     do_preload_rhtbl(ht);
5288     do_rhash(rs,rh);
5289   }
5290   #endif
5291   store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5292   #ifdef DESTRUCTIVE_WRITEBACK
5293   if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5294     if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5295       emit_loadreg(rs1[i],rs);
5296     }
5297   }
5298   #endif
5299   #ifdef REG_PREFETCH
5300   if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5301   #endif
5302   #ifdef USE_MINI_HT
5303   if(rs1[i]==31) {
5304     do_miniht_load(ht,rh);
5305   }
5306   #endif
5307   //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5308   //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5309   //assert(adj==0);
5310   emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5311   add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5312   emit_jns(0);
5313   //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5314   #ifdef USE_MINI_HT
5315   if(rs1[i]==31) {
5316     do_miniht_jump(rs,rh,ht);
5317   }
5318   else
5319   #endif
5320   {
5321     //if(rs!=EAX) emit_mov(rs,EAX);
5322     //emit_jmp((int)jump_vaddr_eax);
5323     emit_jmp(jump_vaddr_reg[rs]);
5324   }
5325   /* Check hash table
5326   temp=!rs;
5327   emit_mov(rs,temp);
5328   emit_shrimm(rs,16,rs);
5329   emit_xor(temp,rs,rs);
5330   emit_movzwl_reg(rs,rs);
5331   emit_shlimm(rs,4,rs);
5332   emit_cmpmem_indexed((int)hash_table,rs,temp);
5333   emit_jne((int)out+14);
5334   emit_readword_indexed((int)hash_table+4,rs,rs);
5335   emit_jmpreg(rs);
5336   emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5337   emit_addimm_no_flags(8,rs);
5338   emit_jeq((int)out-17);
5339   // No hit on hash table, call compiler
5340   emit_pushreg(temp);
5341 //DEBUG >
5342 #ifdef DEBUG_CYCLE_COUNT
5343   emit_readword((int)&last_count,ECX);
5344   emit_add(HOST_CCREG,ECX,HOST_CCREG);
5345   emit_readword((int)&next_interupt,ECX);
5346   emit_writeword(HOST_CCREG,(int)&Count);
5347   emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5348   emit_writeword(ECX,(int)&last_count);
5349 #endif
5350 //DEBUG <
5351   emit_storereg(CCREG,HOST_CCREG);
5352   emit_call((int)get_addr);
5353   emit_loadreg(CCREG,HOST_CCREG);
5354   emit_addimm(ESP,4,ESP);
5355   emit_jmpreg(EAX);*/
5356   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5357   if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5358   #endif
5359 }
5360
5361 void cjump_assemble(int i,struct regstat *i_regs)
5362 {
5363   signed char *i_regmap=i_regs->regmap;
5364   int cc;
5365   int match;
5366   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5367   assem_debug("match=%d\n",match);
5368   int s1h,s1l,s2h,s2l;
5369   int prev_cop1_usable=cop1_usable;
5370   int unconditional=0,nop=0;
5371   int only32=0;
5372   int invert=0;
5373   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5374   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5375   if(!match) invert=1;
5376   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5377   if(i>(ba[i]-start)>>2) invert=1;
5378   #endif
5379
5380   if(ooo[i]) {
5381     s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5382     s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5383     s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5384     s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5385   }
5386   else {
5387     s1l=get_reg(i_regmap,rs1[i]);
5388     s1h=get_reg(i_regmap,rs1[i]|64);
5389     s2l=get_reg(i_regmap,rs2[i]);
5390     s2h=get_reg(i_regmap,rs2[i]|64);
5391   }
5392   if(rs1[i]==0&&rs2[i]==0)
5393   {
5394     if(opcode[i]&1) nop=1;
5395     else unconditional=1;
5396     //assert(opcode[i]!=5);
5397     //assert(opcode[i]!=7);
5398     //assert(opcode[i]!=0x15);
5399     //assert(opcode[i]!=0x17);
5400   }
5401   else if(rs1[i]==0)
5402   {
5403     s1l=s2l;s1h=s2h;
5404     s2l=s2h=-1;
5405     only32=(regs[i].was32>>rs2[i])&1;
5406   }
5407   else if(rs2[i]==0)
5408   {
5409     s2l=s2h=-1;
5410     only32=(regs[i].was32>>rs1[i])&1;
5411   }
5412   else {
5413     only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5414   }
5415
5416   if(ooo[i]) {
5417     // Out of order execution (delay slot first)
5418     //printf("OOOE\n");
5419     address_generation(i+1,i_regs,regs[i].regmap_entry);
5420     ds_assemble(i+1,i_regs);
5421     int adj;
5422     uint64_t bc_unneeded=branch_regs[i].u;
5423     uint64_t bc_unneeded_upper=branch_regs[i].uu;
5424     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5425     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5426     bc_unneeded|=1;
5427     bc_unneeded_upper|=1;
5428     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5429                   bc_unneeded,bc_unneeded_upper);
5430     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5431     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5432     cc=get_reg(branch_regs[i].regmap,CCREG);
5433     assert(cc==HOST_CCREG);
5434     if(unconditional)
5435       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5436     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5437     //assem_debug("cycle count (adj)\n");
5438     if(unconditional) {
5439       do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5440       if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5441         if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5442         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5443         if(internal)
5444           assem_debug("branch: internal\n");
5445         else
5446           assem_debug("branch: external\n");
5447         if(internal&&is_ds[(ba[i]-start)>>2]) {
5448           ds_assemble_entry(i);
5449         }
5450         else {
5451           add_to_linker((int)out,ba[i],internal);
5452           emit_jmp(0);
5453         }
5454         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5455         if(((u_int)out)&7) emit_addnop(0);
5456         #endif
5457       }
5458     }
5459     else if(nop) {
5460       emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5461       int jaddr=(int)out;
5462       emit_jns(0);
5463       add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5464     }
5465     else {
5466       int taken=0,nottaken=0,nottaken1=0;
5467       do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5468       if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5469       if(!only32)
5470       {
5471         assert(s1h>=0);
5472         if(opcode[i]==4) // BEQ
5473         {
5474           if(s2h>=0) emit_cmp(s1h,s2h);
5475           else emit_test(s1h,s1h);
5476           nottaken1=(int)out;
5477           emit_jne(1);
5478         }
5479         if(opcode[i]==5) // BNE
5480         {
5481           if(s2h>=0) emit_cmp(s1h,s2h);
5482           else emit_test(s1h,s1h);
5483           if(invert) taken=(int)out;
5484           else add_to_linker((int)out,ba[i],internal);
5485           emit_jne(0);
5486         }
5487         if(opcode[i]==6) // BLEZ
5488         {
5489           emit_test(s1h,s1h);
5490           if(invert) taken=(int)out;
5491           else add_to_linker((int)out,ba[i],internal);
5492           emit_js(0);
5493           nottaken1=(int)out;
5494           emit_jne(1);
5495         }
5496         if(opcode[i]==7) // BGTZ
5497         {
5498           emit_test(s1h,s1h);
5499           nottaken1=(int)out;
5500           emit_js(1);
5501           if(invert) taken=(int)out;
5502           else add_to_linker((int)out,ba[i],internal);
5503           emit_jne(0);
5504         }
5505       } // if(!only32)
5506
5507       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5508       assert(s1l>=0);
5509       if(opcode[i]==4) // BEQ
5510       {
5511         if(s2l>=0) emit_cmp(s1l,s2l);
5512         else emit_test(s1l,s1l);
5513         if(invert){
5514           nottaken=(int)out;
5515           emit_jne(1);
5516         }else{
5517           add_to_linker((int)out,ba[i],internal);
5518           emit_jeq(0);
5519         }
5520       }
5521       if(opcode[i]==5) // BNE
5522       {
5523         if(s2l>=0) emit_cmp(s1l,s2l);
5524         else emit_test(s1l,s1l);
5525         if(invert){
5526           nottaken=(int)out;
5527           emit_jeq(1);
5528         }else{
5529           add_to_linker((int)out,ba[i],internal);
5530           emit_jne(0);
5531         }
5532       }
5533       if(opcode[i]==6) // BLEZ
5534       {
5535         emit_cmpimm(s1l,1);
5536         if(invert){
5537           nottaken=(int)out;
5538           emit_jge(1);
5539         }else{
5540           add_to_linker((int)out,ba[i],internal);
5541           emit_jl(0);
5542         }
5543       }
5544       if(opcode[i]==7) // BGTZ
5545       {
5546         emit_cmpimm(s1l,1);
5547         if(invert){
5548           nottaken=(int)out;
5549           emit_jl(1);
5550         }else{
5551           add_to_linker((int)out,ba[i],internal);
5552           emit_jge(0);
5553         }
5554       }
5555       if(invert) {
5556         if(taken) set_jump_target(taken,(int)out);
5557         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5558         if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5559           if(adj) {
5560             emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5561             add_to_linker((int)out,ba[i],internal);
5562           }else{
5563             emit_addnop(13);
5564             add_to_linker((int)out,ba[i],internal*2);
5565           }
5566           emit_jmp(0);
5567         }else
5568         #endif
5569         {
5570           if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5571           store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5572           load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5573           if(internal)
5574             assem_debug("branch: internal\n");
5575           else
5576             assem_debug("branch: external\n");
5577           if(internal&&is_ds[(ba[i]-start)>>2]) {
5578             ds_assemble_entry(i);
5579           }
5580           else {
5581             add_to_linker((int)out,ba[i],internal);
5582             emit_jmp(0);
5583           }
5584         }
5585         set_jump_target(nottaken,(int)out);
5586       }
5587
5588       if(nottaken1) set_jump_target(nottaken1,(int)out);
5589       if(adj) {
5590         if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5591       }
5592     } // (!unconditional)
5593   } // if(ooo)
5594   else
5595   {
5596     // In-order execution (branch first)
5597     //if(likely[i]) printf("IOL\n");
5598     //else
5599     //printf("IOE\n");
5600     int taken=0,nottaken=0,nottaken1=0;
5601     if(!unconditional&&!nop) {
5602       if(!only32)
5603       {
5604         assert(s1h>=0);
5605         if((opcode[i]&0x2f)==4) // BEQ
5606         {
5607           if(s2h>=0) emit_cmp(s1h,s2h);
5608           else emit_test(s1h,s1h);
5609           nottaken1=(int)out;
5610           emit_jne(2);
5611         }
5612         if((opcode[i]&0x2f)==5) // BNE
5613         {
5614           if(s2h>=0) emit_cmp(s1h,s2h);
5615           else emit_test(s1h,s1h);
5616           taken=(int)out;
5617           emit_jne(1);
5618         }
5619         if((opcode[i]&0x2f)==6) // BLEZ
5620         {
5621           emit_test(s1h,s1h);
5622           taken=(int)out;
5623           emit_js(1);
5624           nottaken1=(int)out;
5625           emit_jne(2);
5626         }
5627         if((opcode[i]&0x2f)==7) // BGTZ
5628         {
5629           emit_test(s1h,s1h);
5630           nottaken1=(int)out;
5631           emit_js(2);
5632           taken=(int)out;
5633           emit_jne(1);
5634         }
5635       } // if(!only32)
5636
5637       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5638       assert(s1l>=0);
5639       if((opcode[i]&0x2f)==4) // BEQ
5640       {
5641         if(s2l>=0) emit_cmp(s1l,s2l);
5642         else emit_test(s1l,s1l);
5643         nottaken=(int)out;
5644         emit_jne(2);
5645       }
5646       if((opcode[i]&0x2f)==5) // BNE
5647       {
5648         if(s2l>=0) emit_cmp(s1l,s2l);
5649         else emit_test(s1l,s1l);
5650         nottaken=(int)out;
5651         emit_jeq(2);
5652       }
5653       if((opcode[i]&0x2f)==6) // BLEZ
5654       {
5655         emit_cmpimm(s1l,1);
5656         nottaken=(int)out;
5657         emit_jge(2);
5658       }
5659       if((opcode[i]&0x2f)==7) // BGTZ
5660       {
5661         emit_cmpimm(s1l,1);
5662         nottaken=(int)out;
5663         emit_jl(2);
5664       }
5665     } // if(!unconditional)
5666     int adj;
5667     uint64_t ds_unneeded=branch_regs[i].u;
5668     uint64_t ds_unneeded_upper=branch_regs[i].uu;
5669     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5670     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5671     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5672     ds_unneeded|=1;
5673     ds_unneeded_upper|=1;
5674     // branch taken
5675     if(!nop) {
5676       if(taken) set_jump_target(taken,(int)out);
5677       assem_debug("1:\n");
5678       wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5679                     ds_unneeded,ds_unneeded_upper);
5680       // load regs
5681       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5682       address_generation(i+1,&branch_regs[i],0);
5683       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5684       ds_assemble(i+1,&branch_regs[i]);
5685       cc=get_reg(branch_regs[i].regmap,CCREG);
5686       if(cc==-1) {
5687         emit_loadreg(CCREG,cc=HOST_CCREG);
5688         // CHECK: Is the following instruction (fall thru) allocated ok?
5689       }
5690       assert(cc==HOST_CCREG);
5691       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5692       do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5693       assem_debug("cycle count (adj)\n");
5694       if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5695       load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5696       if(internal)
5697         assem_debug("branch: internal\n");
5698       else
5699         assem_debug("branch: external\n");
5700       if(internal&&is_ds[(ba[i]-start)>>2]) {
5701         ds_assemble_entry(i);
5702       }
5703       else {
5704         add_to_linker((int)out,ba[i],internal);
5705         emit_jmp(0);
5706       }
5707     }
5708     // branch not taken
5709     cop1_usable=prev_cop1_usable;
5710     if(!unconditional) {
5711       if(nottaken1) set_jump_target(nottaken1,(int)out);
5712       set_jump_target(nottaken,(int)out);
5713       assem_debug("2:\n");
5714       if(!likely[i]) {
5715         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5716                       ds_unneeded,ds_unneeded_upper);
5717         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5718         address_generation(i+1,&branch_regs[i],0);
5719         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5720         ds_assemble(i+1,&branch_regs[i]);
5721       }
5722       cc=get_reg(branch_regs[i].regmap,CCREG);
5723       if(cc==-1&&!likely[i]) {
5724         // Cycle count isn't in a register, temporarily load it then write it out
5725         emit_loadreg(CCREG,HOST_CCREG);
5726         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5727         int jaddr=(int)out;
5728         emit_jns(0);
5729         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5730         emit_storereg(CCREG,HOST_CCREG);
5731       }
5732       else{
5733         cc=get_reg(i_regmap,CCREG);
5734         assert(cc==HOST_CCREG);
5735         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5736         int jaddr=(int)out;
5737         emit_jns(0);
5738         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5739       }
5740     }
5741   }
5742 }
5743
5744 void sjump_assemble(int i,struct regstat *i_regs)
5745 {
5746   signed char *i_regmap=i_regs->regmap;
5747   int cc;
5748   int match;
5749   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5750   assem_debug("smatch=%d\n",match);
5751   int s1h,s1l;
5752   int prev_cop1_usable=cop1_usable;
5753   int unconditional=0,nevertaken=0;
5754   int only32=0;
5755   int invert=0;
5756   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5757   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5758   if(!match) invert=1;
5759   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5760   if(i>(ba[i]-start)>>2) invert=1;
5761   #endif
5762
5763   //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
5764   //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
5765
5766   if(ooo[i]) {
5767     s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5768     s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5769   }
5770   else {
5771     s1l=get_reg(i_regmap,rs1[i]);
5772     s1h=get_reg(i_regmap,rs1[i]|64);
5773   }
5774   if(rs1[i]==0)
5775   {
5776     if(opcode2[i]&1) unconditional=1;
5777     else nevertaken=1;
5778     // These are never taken (r0 is never less than zero)
5779     //assert(opcode2[i]!=0);
5780     //assert(opcode2[i]!=2);
5781     //assert(opcode2[i]!=0x10);
5782     //assert(opcode2[i]!=0x12);
5783   }
5784   else {
5785     only32=(regs[i].was32>>rs1[i])&1;
5786   }
5787
5788   if(ooo[i]) {
5789     // Out of order execution (delay slot first)
5790     //printf("OOOE\n");
5791     address_generation(i+1,i_regs,regs[i].regmap_entry);
5792     ds_assemble(i+1,i_regs);
5793     int adj;
5794     uint64_t bc_unneeded=branch_regs[i].u;
5795     uint64_t bc_unneeded_upper=branch_regs[i].uu;
5796     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5797     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5798     bc_unneeded|=1;
5799     bc_unneeded_upper|=1;
5800     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5801                   bc_unneeded,bc_unneeded_upper);
5802     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5803     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5804     if(rt1[i]==31) {
5805       int rt,return_address;
5806       rt=get_reg(branch_regs[i].regmap,31);
5807       assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5808       if(rt>=0) {
5809         // Save the PC even if the branch is not taken
5810         return_address=start+i*4+8;
5811         emit_movimm(return_address,rt); // PC into link register
5812         #ifdef IMM_PREFETCH
5813         if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5814         #endif
5815       }
5816     }
5817     cc=get_reg(branch_regs[i].regmap,CCREG);
5818     assert(cc==HOST_CCREG);
5819     if(unconditional)
5820       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5821     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5822     assem_debug("cycle count (adj)\n");
5823     if(unconditional) {
5824       do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5825       if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5826         if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5827         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5828         if(internal)
5829           assem_debug("branch: internal\n");
5830         else
5831           assem_debug("branch: external\n");
5832         if(internal&&is_ds[(ba[i]-start)>>2]) {
5833           ds_assemble_entry(i);
5834         }
5835         else {
5836           add_to_linker((int)out,ba[i],internal);
5837           emit_jmp(0);
5838         }
5839         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5840         if(((u_int)out)&7) emit_addnop(0);
5841         #endif
5842       }
5843     }
5844     else if(nevertaken) {
5845       emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5846       int jaddr=(int)out;
5847       emit_jns(0);
5848       add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5849     }
5850     else {
5851       int nottaken=0;
5852       do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5853       if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5854       if(!only32)
5855       {
5856         assert(s1h>=0);
5857         if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5858         {
5859           emit_test(s1h,s1h);
5860           if(invert){
5861             nottaken=(int)out;
5862             emit_jns(1);
5863           }else{
5864             add_to_linker((int)out,ba[i],internal);
5865             emit_js(0);
5866           }
5867         }
5868         if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5869         {
5870           emit_test(s1h,s1h);
5871           if(invert){
5872             nottaken=(int)out;
5873             emit_js(1);
5874           }else{
5875             add_to_linker((int)out,ba[i],internal);
5876             emit_jns(0);
5877           }
5878         }
5879       } // if(!only32)
5880       else
5881       {
5882         assert(s1l>=0);
5883         if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5884         {
5885           emit_test(s1l,s1l);
5886           if(invert){
5887             nottaken=(int)out;
5888             emit_jns(1);
5889           }else{
5890             add_to_linker((int)out,ba[i],internal);
5891             emit_js(0);
5892           }
5893         }
5894         if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5895         {
5896           emit_test(s1l,s1l);
5897           if(invert){
5898             nottaken=(int)out;
5899             emit_js(1);
5900           }else{
5901             add_to_linker((int)out,ba[i],internal);
5902             emit_jns(0);
5903           }
5904         }
5905       } // if(!only32)
5906
5907       if(invert) {
5908         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5909         if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5910           if(adj) {
5911             emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5912             add_to_linker((int)out,ba[i],internal);
5913           }else{
5914             emit_addnop(13);
5915             add_to_linker((int)out,ba[i],internal*2);
5916           }
5917           emit_jmp(0);
5918         }else
5919         #endif
5920         {
5921           if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5922           store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5923           load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5924           if(internal)
5925             assem_debug("branch: internal\n");
5926           else
5927             assem_debug("branch: external\n");
5928           if(internal&&is_ds[(ba[i]-start)>>2]) {
5929             ds_assemble_entry(i);
5930           }
5931           else {
5932             add_to_linker((int)out,ba[i],internal);
5933             emit_jmp(0);
5934           }
5935         }
5936         set_jump_target(nottaken,(int)out);
5937       }
5938
5939       if(adj) {
5940         if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5941       }
5942     } // (!unconditional)
5943   } // if(ooo)
5944   else
5945   {
5946     // In-order execution (branch first)
5947     //printf("IOE\n");
5948     int nottaken=0;
5949     if(rt1[i]==31) {
5950       int rt,return_address;
5951       rt=get_reg(branch_regs[i].regmap,31);
5952       if(rt>=0) {
5953         // Save the PC even if the branch is not taken
5954         return_address=start+i*4+8;
5955         emit_movimm(return_address,rt); // PC into link register
5956         #ifdef IMM_PREFETCH
5957         emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5958         #endif
5959       }
5960     }
5961     if(!unconditional) {
5962       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5963       if(!only32)
5964       {
5965         assert(s1h>=0);
5966         if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
5967         {
5968           emit_test(s1h,s1h);
5969           nottaken=(int)out;
5970           emit_jns(1);
5971         }
5972         if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
5973         {
5974           emit_test(s1h,s1h);
5975           nottaken=(int)out;
5976           emit_js(1);
5977         }
5978       } // if(!only32)
5979       else
5980       {
5981         assert(s1l>=0);
5982         if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
5983         {
5984           emit_test(s1l,s1l);
5985           nottaken=(int)out;
5986           emit_jns(1);
5987         }
5988         if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
5989         {
5990           emit_test(s1l,s1l);
5991           nottaken=(int)out;
5992           emit_js(1);
5993         }
5994       }
5995     } // if(!unconditional)
5996     int adj;
5997     uint64_t ds_unneeded=branch_regs[i].u;
5998     uint64_t ds_unneeded_upper=branch_regs[i].uu;
5999     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6000     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6001     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6002     ds_unneeded|=1;
6003     ds_unneeded_upper|=1;
6004     // branch taken
6005     if(!nevertaken) {
6006       //assem_debug("1:\n");
6007       wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6008                     ds_unneeded,ds_unneeded_upper);
6009       // load regs
6010       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6011       address_generation(i+1,&branch_regs[i],0);
6012       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6013       ds_assemble(i+1,&branch_regs[i]);
6014       cc=get_reg(branch_regs[i].regmap,CCREG);
6015       if(cc==-1) {
6016         emit_loadreg(CCREG,cc=HOST_CCREG);
6017         // CHECK: Is the following instruction (fall thru) allocated ok?
6018       }
6019       assert(cc==HOST_CCREG);
6020       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6021       do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6022       assem_debug("cycle count (adj)\n");
6023       if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6024       load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6025       if(internal)
6026         assem_debug("branch: internal\n");
6027       else
6028         assem_debug("branch: external\n");
6029       if(internal&&is_ds[(ba[i]-start)>>2]) {
6030         ds_assemble_entry(i);
6031       }
6032       else {
6033         add_to_linker((int)out,ba[i],internal);
6034         emit_jmp(0);
6035       }
6036     }
6037     // branch not taken
6038     cop1_usable=prev_cop1_usable;
6039     if(!unconditional) {
6040       set_jump_target(nottaken,(int)out);
6041       assem_debug("1:\n");
6042       if(!likely[i]) {
6043         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6044                       ds_unneeded,ds_unneeded_upper);
6045         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6046         address_generation(i+1,&branch_regs[i],0);
6047         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6048         ds_assemble(i+1,&branch_regs[i]);
6049       }
6050       cc=get_reg(branch_regs[i].regmap,CCREG);
6051       if(cc==-1&&!likely[i]) {
6052         // Cycle count isn't in a register, temporarily load it then write it out
6053         emit_loadreg(CCREG,HOST_CCREG);
6054         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6055         int jaddr=(int)out;
6056         emit_jns(0);
6057         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6058         emit_storereg(CCREG,HOST_CCREG);
6059       }
6060       else{
6061         cc=get_reg(i_regmap,CCREG);
6062         assert(cc==HOST_CCREG);
6063         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6064         int jaddr=(int)out;
6065         emit_jns(0);
6066         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6067       }
6068     }
6069   }
6070 }
6071
6072 void fjump_assemble(int i,struct regstat *i_regs)
6073 {
6074   signed char *i_regmap=i_regs->regmap;
6075   int cc;
6076   int match;
6077   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6078   assem_debug("fmatch=%d\n",match);
6079   int fs,cs;
6080   int eaddr;
6081   int invert=0;
6082   int internal=internal_branch(branch_regs[i].is32,ba[i]);
6083   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
6084   if(!match) invert=1;
6085   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6086   if(i>(ba[i]-start)>>2) invert=1;
6087   #endif
6088
6089   if(ooo[i]) {
6090     fs=get_reg(branch_regs[i].regmap,FSREG);
6091     address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
6092   }
6093   else {
6094     fs=get_reg(i_regmap,FSREG);
6095   }
6096
6097   // Check cop1 unusable
6098   if(!cop1_usable) {
6099     cs=get_reg(i_regmap,CSREG);
6100     assert(cs>=0);
6101     emit_testimm(cs,0x20000000);
6102     eaddr=(int)out;
6103     emit_jeq(0);
6104     add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
6105     cop1_usable=1;
6106   }
6107
6108   if(ooo[i]) {
6109     // Out of order execution (delay slot first)
6110     //printf("OOOE\n");
6111     ds_assemble(i+1,i_regs);
6112     int adj;
6113     uint64_t bc_unneeded=branch_regs[i].u;
6114     uint64_t bc_unneeded_upper=branch_regs[i].uu;
6115     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6116     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
6117     bc_unneeded|=1;
6118     bc_unneeded_upper|=1;
6119     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6120                   bc_unneeded,bc_unneeded_upper);
6121     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
6122     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6123     cc=get_reg(branch_regs[i].regmap,CCREG);
6124     assert(cc==HOST_CCREG);
6125     do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6126     assem_debug("cycle count (adj)\n");
6127     if(1) {
6128       int nottaken=0;
6129       if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6130       if(1) {
6131         assert(fs>=0);
6132         emit_testimm(fs,0x800000);
6133         if(source[i]&0x10000) // BC1T
6134         {
6135           if(invert){
6136             nottaken=(int)out;
6137             emit_jeq(1);
6138           }else{
6139             add_to_linker((int)out,ba[i],internal);
6140             emit_jne(0);
6141           }
6142         }
6143         else // BC1F
6144           if(invert){
6145             nottaken=(int)out;
6146             emit_jne(1);
6147           }else{
6148             add_to_linker((int)out,ba[i],internal);
6149             emit_jeq(0);
6150           }
6151         {
6152         }
6153       } // if(!only32)
6154
6155       if(invert) {
6156         if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
6157         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6158         else if(match) emit_addnop(13);
6159         #endif
6160         store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6161         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6162         if(internal)
6163           assem_debug("branch: internal\n");
6164         else
6165           assem_debug("branch: external\n");
6166         if(internal&&is_ds[(ba[i]-start)>>2]) {
6167           ds_assemble_entry(i);
6168         }
6169         else {
6170           add_to_linker((int)out,ba[i],internal);
6171           emit_jmp(0);
6172         }
6173         set_jump_target(nottaken,(int)out);
6174       }
6175
6176       if(adj) {
6177         if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
6178       }
6179     } // (!unconditional)
6180   } // if(ooo)
6181   else
6182   {
6183     // In-order execution (branch first)
6184     //printf("IOE\n");
6185     int nottaken=0;
6186     if(1) {
6187       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6188       if(1) {
6189         assert(fs>=0);
6190         emit_testimm(fs,0x800000);
6191         if(source[i]&0x10000) // BC1T
6192         {
6193           nottaken=(int)out;
6194           emit_jeq(1);
6195         }
6196         else // BC1F
6197         {
6198           nottaken=(int)out;
6199           emit_jne(1);
6200         }
6201       }
6202     } // if(!unconditional)
6203     int adj;
6204     uint64_t ds_unneeded=branch_regs[i].u;
6205     uint64_t ds_unneeded_upper=branch_regs[i].uu;
6206     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6207     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6208     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6209     ds_unneeded|=1;
6210     ds_unneeded_upper|=1;
6211     // branch taken
6212     //assem_debug("1:\n");
6213     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6214                   ds_unneeded,ds_unneeded_upper);
6215     // load regs
6216     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6217     address_generation(i+1,&branch_regs[i],0);
6218     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6219     ds_assemble(i+1,&branch_regs[i]);
6220     cc=get_reg(branch_regs[i].regmap,CCREG);
6221     if(cc==-1) {
6222       emit_loadreg(CCREG,cc=HOST_CCREG);
6223       // CHECK: Is the following instruction (fall thru) allocated ok?
6224     }
6225     assert(cc==HOST_CCREG);
6226     store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6227     do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6228     assem_debug("cycle count (adj)\n");
6229     if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6230     load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6231     if(internal)
6232       assem_debug("branch: internal\n");
6233     else
6234       assem_debug("branch: external\n");
6235     if(internal&&is_ds[(ba[i]-start)>>2]) {
6236       ds_assemble_entry(i);
6237     }
6238     else {
6239       add_to_linker((int)out,ba[i],internal);
6240       emit_jmp(0);
6241     }
6242
6243     // branch not taken
6244     if(1) { // <- FIXME (don't need this)
6245       set_jump_target(nottaken,(int)out);
6246       assem_debug("1:\n");
6247       if(!likely[i]) {
6248         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6249                       ds_unneeded,ds_unneeded_upper);
6250         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6251         address_generation(i+1,&branch_regs[i],0);
6252         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6253         ds_assemble(i+1,&branch_regs[i]);
6254       }
6255       cc=get_reg(branch_regs[i].regmap,CCREG);
6256       if(cc==-1&&!likely[i]) {
6257         // Cycle count isn't in a register, temporarily load it then write it out
6258         emit_loadreg(CCREG,HOST_CCREG);
6259         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6260         int jaddr=(int)out;
6261         emit_jns(0);
6262         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6263         emit_storereg(CCREG,HOST_CCREG);
6264       }
6265       else{
6266         cc=get_reg(i_regmap,CCREG);
6267         assert(cc==HOST_CCREG);
6268         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6269         int jaddr=(int)out;
6270         emit_jns(0);
6271         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6272       }
6273     }
6274   }
6275 }
6276
6277 static void pagespan_assemble(int i,struct regstat *i_regs)
6278 {
6279   int s1l=get_reg(i_regs->regmap,rs1[i]);
6280   int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6281   int s2l=get_reg(i_regs->regmap,rs2[i]);
6282   int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6283   void *nt_branch=NULL;
6284   int taken=0;
6285   int nottaken=0;
6286   int unconditional=0;
6287   if(rs1[i]==0)
6288   {
6289     s1l=s2l;s1h=s2h;
6290     s2l=s2h=-1;
6291   }
6292   else if(rs2[i]==0)
6293   {
6294     s2l=s2h=-1;
6295   }
6296   if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6297     s1h=s2h=-1;
6298   }
6299   int hr=0;
6300   int addr,alt,ntaddr;
6301   if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6302   else {
6303     while(hr<HOST_REGS)
6304     {
6305       if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6306          (i_regs->regmap[hr]&63)!=rs1[i] &&
6307          (i_regs->regmap[hr]&63)!=rs2[i] )
6308       {
6309         addr=hr++;break;
6310       }
6311       hr++;
6312     }
6313   }
6314   while(hr<HOST_REGS)
6315   {
6316     if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6317        (i_regs->regmap[hr]&63)!=rs1[i] &&
6318        (i_regs->regmap[hr]&63)!=rs2[i] )
6319     {
6320       alt=hr++;break;
6321     }
6322     hr++;
6323   }
6324   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6325   {
6326     while(hr<HOST_REGS)
6327     {
6328       if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6329          (i_regs->regmap[hr]&63)!=rs1[i] &&
6330          (i_regs->regmap[hr]&63)!=rs2[i] )
6331       {
6332         ntaddr=hr;break;
6333       }
6334       hr++;
6335     }
6336   }
6337   assert(hr<HOST_REGS);
6338   if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6339     load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6340   }
6341   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6342   if(opcode[i]==2) // J
6343   {
6344     unconditional=1;
6345   }
6346   if(opcode[i]==3) // JAL
6347   {
6348     // TODO: mini_ht
6349     int rt=get_reg(i_regs->regmap,31);
6350     emit_movimm(start+i*4+8,rt);
6351     unconditional=1;
6352   }
6353   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6354   {
6355     emit_mov(s1l,addr);
6356     if(opcode2[i]==9) // JALR
6357     {
6358       int rt=get_reg(i_regs->regmap,rt1[i]);
6359       emit_movimm(start+i*4+8,rt);
6360     }
6361   }
6362   if((opcode[i]&0x3f)==4) // BEQ
6363   {
6364     if(rs1[i]==rs2[i])
6365     {
6366       unconditional=1;
6367     }
6368     else
6369     #ifdef HAVE_CMOV_IMM
6370     if(s1h<0) {
6371       if(s2l>=0) emit_cmp(s1l,s2l);
6372       else emit_test(s1l,s1l);
6373       emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6374     }
6375     else
6376     #endif
6377     {
6378       assert(s1l>=0);
6379       emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6380       if(s1h>=0) {
6381         if(s2h>=0) emit_cmp(s1h,s2h);
6382         else emit_test(s1h,s1h);
6383         emit_cmovne_reg(alt,addr);
6384       }
6385       if(s2l>=0) emit_cmp(s1l,s2l);
6386       else emit_test(s1l,s1l);
6387       emit_cmovne_reg(alt,addr);
6388     }
6389   }
6390   if((opcode[i]&0x3f)==5) // BNE
6391   {
6392     #ifdef HAVE_CMOV_IMM
6393     if(s1h<0) {
6394       if(s2l>=0) emit_cmp(s1l,s2l);
6395       else emit_test(s1l,s1l);
6396       emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6397     }
6398     else
6399     #endif
6400     {
6401       assert(s1l>=0);
6402       emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6403       if(s1h>=0) {
6404         if(s2h>=0) emit_cmp(s1h,s2h);
6405         else emit_test(s1h,s1h);
6406         emit_cmovne_reg(alt,addr);
6407       }
6408       if(s2l>=0) emit_cmp(s1l,s2l);
6409       else emit_test(s1l,s1l);
6410       emit_cmovne_reg(alt,addr);
6411     }
6412   }
6413   if((opcode[i]&0x3f)==0x14) // BEQL
6414   {
6415     if(s1h>=0) {
6416       if(s2h>=0) emit_cmp(s1h,s2h);
6417       else emit_test(s1h,s1h);
6418       nottaken=(int)out;
6419       emit_jne(0);
6420     }
6421     if(s2l>=0) emit_cmp(s1l,s2l);
6422     else emit_test(s1l,s1l);
6423     if(nottaken) set_jump_target(nottaken,(int)out);
6424     nottaken=(int)out;
6425     emit_jne(0);
6426   }
6427   if((opcode[i]&0x3f)==0x15) // BNEL
6428   {
6429     if(s1h>=0) {
6430       if(s2h>=0) emit_cmp(s1h,s2h);
6431       else emit_test(s1h,s1h);
6432       taken=(int)out;
6433       emit_jne(0);
6434     }
6435     if(s2l>=0) emit_cmp(s1l,s2l);
6436     else emit_test(s1l,s1l);
6437     nottaken=(int)out;
6438     emit_jeq(0);
6439     if(taken) set_jump_target(taken,(int)out);
6440   }
6441   if((opcode[i]&0x3f)==6) // BLEZ
6442   {
6443     emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6444     emit_cmpimm(s1l,1);
6445     if(s1h>=0) emit_mov(addr,ntaddr);
6446     emit_cmovl_reg(alt,addr);
6447     if(s1h>=0) {
6448       emit_test(s1h,s1h);
6449       emit_cmovne_reg(ntaddr,addr);
6450       emit_cmovs_reg(alt,addr);
6451     }
6452   }
6453   if((opcode[i]&0x3f)==7) // BGTZ
6454   {
6455     emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6456     emit_cmpimm(s1l,1);
6457     if(s1h>=0) emit_mov(addr,alt);
6458     emit_cmovl_reg(ntaddr,addr);
6459     if(s1h>=0) {
6460       emit_test(s1h,s1h);
6461       emit_cmovne_reg(alt,addr);
6462       emit_cmovs_reg(ntaddr,addr);
6463     }
6464   }
6465   if((opcode[i]&0x3f)==0x16) // BLEZL
6466   {
6467     assert((opcode[i]&0x3f)!=0x16);
6468   }
6469   if((opcode[i]&0x3f)==0x17) // BGTZL
6470   {
6471     assert((opcode[i]&0x3f)!=0x17);
6472   }
6473   assert(opcode[i]!=1); // BLTZ/BGEZ
6474
6475   //FIXME: Check CSREG
6476   if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6477     if((source[i]&0x30000)==0) // BC1F
6478     {
6479       emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6480       emit_testimm(s1l,0x800000);
6481       emit_cmovne_reg(alt,addr);
6482     }
6483     if((source[i]&0x30000)==0x10000) // BC1T
6484     {
6485       emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6486       emit_testimm(s1l,0x800000);
6487       emit_cmovne_reg(alt,addr);
6488     }
6489     if((source[i]&0x30000)==0x20000) // BC1FL
6490     {
6491       emit_testimm(s1l,0x800000);
6492       nottaken=(int)out;
6493       emit_jne(0);
6494     }
6495     if((source[i]&0x30000)==0x30000) // BC1TL
6496     {
6497       emit_testimm(s1l,0x800000);
6498       nottaken=(int)out;
6499       emit_jeq(0);
6500     }
6501   }
6502
6503   assert(i_regs->regmap[HOST_CCREG]==CCREG);
6504   wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6505   if(likely[i]||unconditional)
6506   {
6507     emit_movimm(ba[i],HOST_BTREG);
6508   }
6509   else if(addr!=HOST_BTREG)
6510   {
6511     emit_mov(addr,HOST_BTREG);
6512   }
6513   void *branch_addr=out;
6514   emit_jmp(0);
6515   int target_addr=start+i*4+5;
6516   void *stub=out;
6517   void *compiled_target_addr=check_addr(target_addr);
6518   emit_extjump_ds((int)branch_addr,target_addr);
6519   if(compiled_target_addr) {
6520     set_jump_target((int)branch_addr,(int)compiled_target_addr);
6521     add_link(target_addr,stub);
6522   }
6523   else set_jump_target((int)branch_addr,(int)stub);
6524   if(likely[i]) {
6525     // Not-taken path
6526     set_jump_target((int)nottaken,(int)out);
6527     wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6528     void *branch_addr=out;
6529     emit_jmp(0);
6530     int target_addr=start+i*4+8;
6531     void *stub=out;
6532     void *compiled_target_addr=check_addr(target_addr);
6533     emit_extjump_ds((int)branch_addr,target_addr);
6534     if(compiled_target_addr) {
6535       set_jump_target((int)branch_addr,(int)compiled_target_addr);
6536       add_link(target_addr,stub);
6537     }
6538     else set_jump_target((int)branch_addr,(int)stub);
6539   }
6540 }
6541
6542 // Assemble the delay slot for the above
6543 static void pagespan_ds()
6544 {
6545   assem_debug("initial delay slot:\n");
6546   u_int vaddr=start+1;
6547   u_int page=get_page(vaddr);
6548   u_int vpage=get_vpage(vaddr);
6549   ll_add(jump_dirty+vpage,vaddr,(void *)out);
6550   do_dirty_stub_ds();
6551   ll_add(jump_in+page,vaddr,(void *)out);
6552   assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6553   if(regs[0].regmap[HOST_CCREG]!=CCREG)
6554     wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6555   if(regs[0].regmap[HOST_BTREG]!=BTREG)
6556     emit_writeword(HOST_BTREG,(int)&branch_target);
6557   load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6558   address_generation(0,&regs[0],regs[0].regmap_entry);
6559   if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
6560     load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6561   cop1_usable=0;
6562   is_delayslot=0;
6563   switch(itype[0]) {
6564     case ALU:
6565       alu_assemble(0,&regs[0]);break;
6566     case IMM16:
6567       imm16_assemble(0,&regs[0]);break;
6568     case SHIFT:
6569       shift_assemble(0,&regs[0]);break;
6570     case SHIFTIMM:
6571       shiftimm_assemble(0,&regs[0]);break;
6572     case LOAD:
6573       load_assemble(0,&regs[0]);break;
6574     case LOADLR:
6575       loadlr_assemble(0,&regs[0]);break;
6576     case STORE:
6577       store_assemble(0,&regs[0]);break;
6578     case STORELR:
6579       storelr_assemble(0,&regs[0]);break;
6580     case COP0:
6581       cop0_assemble(0,&regs[0]);break;
6582     case COP1:
6583       cop1_assemble(0,&regs[0]);break;
6584     case C1LS:
6585       c1ls_assemble(0,&regs[0]);break;
6586     case COP2:
6587       cop2_assemble(0,&regs[0]);break;
6588     case C2LS:
6589       c2ls_assemble(0,&regs[0]);break;
6590     case C2OP:
6591       c2op_assemble(0,&regs[0]);break;
6592     case FCONV:
6593       fconv_assemble(0,&regs[0]);break;
6594     case FLOAT:
6595       float_assemble(0,&regs[0]);break;
6596     case FCOMP:
6597       fcomp_assemble(0,&regs[0]);break;
6598     case MULTDIV:
6599       multdiv_assemble(0,&regs[0]);break;
6600     case MOV:
6601       mov_assemble(0,&regs[0]);break;
6602     case SYSCALL:
6603     case HLECALL:
6604     case INTCALL:
6605     case SPAN:
6606     case UJUMP:
6607     case RJUMP:
6608     case CJUMP:
6609     case SJUMP:
6610     case FJUMP:
6611       printf("Jump in the delay slot.  This is probably a bug.\n");
6612   }
6613   int btaddr=get_reg(regs[0].regmap,BTREG);
6614   if(btaddr<0) {
6615     btaddr=get_reg(regs[0].regmap,-1);
6616     emit_readword((int)&branch_target,btaddr);
6617   }
6618   assert(btaddr!=HOST_CCREG);
6619   if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6620 #ifdef HOST_IMM8
6621   emit_movimm(start+4,HOST_TEMPREG);
6622   emit_cmp(btaddr,HOST_TEMPREG);
6623 #else
6624   emit_cmpimm(btaddr,start+4);
6625 #endif
6626   int branch=(int)out;
6627   emit_jeq(0);
6628   store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6629   emit_jmp(jump_vaddr_reg[btaddr]);
6630   set_jump_target(branch,(int)out);
6631   store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6632   load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6633 }
6634
6635 // Basic liveness analysis for MIPS registers
6636 void unneeded_registers(int istart,int iend,int r)
6637 {
6638   int i;
6639   uint64_t u,uu,b,bu;
6640   uint64_t temp_u,temp_uu;
6641   uint64_t tdep;
6642   if(iend==slen-1) {
6643     u=1;uu=1;
6644   }else{
6645     u=unneeded_reg[iend+1];
6646     uu=unneeded_reg_upper[iend+1];
6647     u=1;uu=1;
6648   }
6649   for (i=iend;i>=istart;i--)
6650   {
6651     //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6652     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6653     {
6654       // If subroutine call, flag return address as a possible branch target
6655       if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6656
6657       if(ba[i]<start || ba[i]>=(start+slen*4))
6658       {
6659         // Branch out of this block, flush all regs
6660         u=1;
6661         uu=1;
6662         /* Hexagon hack
6663         if(itype[i]==UJUMP&&rt1[i]==31)
6664         {
6665           uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6666         }
6667         if(itype[i]==RJUMP&&rs1[i]==31)
6668         {
6669           uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6670         }
6671         if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
6672           if(itype[i]==UJUMP&&rt1[i]==31)
6673           {
6674             //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6675             uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6676           }
6677           if(itype[i]==RJUMP&&rs1[i]==31)
6678           {
6679             //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6680             uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6681           }
6682         }*/
6683         branch_unneeded_reg[i]=u;
6684         branch_unneeded_reg_upper[i]=uu;
6685         // Merge in delay slot
6686         tdep=(~uu>>rt1[i+1])&1;
6687         u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6688         uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6689         u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6690         uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6691         uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6692         u|=1;uu|=1;
6693         // If branch is "likely" (and conditional)
6694         // then we skip the delay slot on the fall-thru path
6695         if(likely[i]) {
6696           if(i<slen-1) {
6697             u&=unneeded_reg[i+2];
6698             uu&=unneeded_reg_upper[i+2];
6699           }
6700           else
6701           {
6702             u=1;
6703             uu=1;
6704           }
6705         }
6706       }
6707       else
6708       {
6709         // Internal branch, flag target
6710         bt[(ba[i]-start)>>2]=1;
6711         if(ba[i]<=start+i*4) {
6712           // Backward branch
6713           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6714           {
6715             // Unconditional branch
6716             temp_u=1;temp_uu=1;
6717           } else {
6718             // Conditional branch (not taken case)
6719             temp_u=unneeded_reg[i+2];
6720             temp_uu=unneeded_reg_upper[i+2];
6721           }
6722           // Merge in delay slot
6723           tdep=(~temp_uu>>rt1[i+1])&1;
6724           temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6725           temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6726           temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6727           temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6728           temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6729           temp_u|=1;temp_uu|=1;
6730           // If branch is "likely" (and conditional)
6731           // then we skip the delay slot on the fall-thru path
6732           if(likely[i]) {
6733             if(i<slen-1) {
6734               temp_u&=unneeded_reg[i+2];
6735               temp_uu&=unneeded_reg_upper[i+2];
6736             }
6737             else
6738             {
6739               temp_u=1;
6740               temp_uu=1;
6741             }
6742           }
6743           tdep=(~temp_uu>>rt1[i])&1;
6744           temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6745           temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6746           temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6747           temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6748           temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6749           temp_u|=1;temp_uu|=1;
6750           unneeded_reg[i]=temp_u;
6751           unneeded_reg_upper[i]=temp_uu;
6752           // Only go three levels deep.  This recursion can take an
6753           // excessive amount of time if there are a lot of nested loops.
6754           if(r<2) {
6755             unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6756           }else{
6757             unneeded_reg[(ba[i]-start)>>2]=1;
6758             unneeded_reg_upper[(ba[i]-start)>>2]=1;
6759           }
6760         } /*else*/ if(1) {
6761           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6762           {
6763             // Unconditional branch
6764             u=unneeded_reg[(ba[i]-start)>>2];
6765             uu=unneeded_reg_upper[(ba[i]-start)>>2];
6766             branch_unneeded_reg[i]=u;
6767             branch_unneeded_reg_upper[i]=uu;
6768         //u=1;
6769         //uu=1;
6770         //branch_unneeded_reg[i]=u;
6771         //branch_unneeded_reg_upper[i]=uu;
6772             // Merge in delay slot
6773             tdep=(~uu>>rt1[i+1])&1;
6774             u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6775             uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6776             u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6777             uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6778             uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6779             u|=1;uu|=1;
6780           } else {
6781             // Conditional branch
6782             b=unneeded_reg[(ba[i]-start)>>2];
6783             bu=unneeded_reg_upper[(ba[i]-start)>>2];
6784             branch_unneeded_reg[i]=b;
6785             branch_unneeded_reg_upper[i]=bu;
6786         //b=1;
6787         //bu=1;
6788         //branch_unneeded_reg[i]=b;
6789         //branch_unneeded_reg_upper[i]=bu;
6790             // Branch delay slot
6791             tdep=(~uu>>rt1[i+1])&1;
6792             b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6793             bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6794             b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6795             bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6796             bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6797             b|=1;bu|=1;
6798             // If branch is "likely" then we skip the
6799             // delay slot on the fall-thru path
6800             if(likely[i]) {
6801               u=b;
6802               uu=bu;
6803               if(i<slen-1) {
6804                 u&=unneeded_reg[i+2];
6805                 uu&=unneeded_reg_upper[i+2];
6806         //u=1;
6807         //uu=1;
6808               }
6809             } else {
6810               u&=b;
6811               uu&=bu;
6812         //u=1;
6813         //uu=1;
6814             }
6815             if(i<slen-1) {
6816               branch_unneeded_reg[i]&=unneeded_reg[i+2];
6817               branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6818         //branch_unneeded_reg[i]=1;
6819         //branch_unneeded_reg_upper[i]=1;
6820             } else {
6821               branch_unneeded_reg[i]=1;
6822               branch_unneeded_reg_upper[i]=1;
6823             }
6824           }
6825         }
6826       }
6827     }
6828     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
6829     {
6830       // SYSCALL instruction (software interrupt)
6831       u=1;
6832       uu=1;
6833     }
6834     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6835     {
6836       // ERET instruction (return from interrupt)
6837       u=1;
6838       uu=1;
6839     }
6840     //u=uu=1; // DEBUG
6841     tdep=(~uu>>rt1[i])&1;
6842     // Written registers are unneeded
6843     u|=1LL<<rt1[i];
6844     u|=1LL<<rt2[i];
6845     uu|=1LL<<rt1[i];
6846     uu|=1LL<<rt2[i];
6847     // Accessed registers are needed
6848     u&=~(1LL<<rs1[i]);
6849     u&=~(1LL<<rs2[i]);
6850     uu&=~(1LL<<us1[i]);
6851     uu&=~(1LL<<us2[i]);
6852     // Source-target dependencies
6853     uu&=~(tdep<<dep1[i]);
6854     uu&=~(tdep<<dep2[i]);
6855     // R0 is always unneeded
6856     u|=1;uu|=1;
6857     // Save it
6858     unneeded_reg[i]=u;
6859     unneeded_reg_upper[i]=uu;
6860     /*
6861     printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6862     printf("U:");
6863     int r;
6864     for(r=1;r<=CCREG;r++) {
6865       if((unneeded_reg[i]>>r)&1) {
6866         if(r==HIREG) printf(" HI");
6867         else if(r==LOREG) printf(" LO");
6868         else printf(" r%d",r);
6869       }
6870     }
6871     printf(" UU:");
6872     for(r=1;r<=CCREG;r++) {
6873       if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
6874         if(r==HIREG) printf(" HI");
6875         else if(r==LOREG) printf(" LO");
6876         else printf(" r%d",r);
6877       }
6878     }
6879     printf("\n");*/
6880   }
6881 #ifdef FORCE32
6882   for (i=iend;i>=istart;i--)
6883   {
6884     unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
6885   }
6886 #endif
6887 }
6888
6889 // Identify registers which are likely to contain 32-bit values
6890 // This is used to predict whether any branches will jump to a
6891 // location with 64-bit values in registers.
6892 static void provisional_32bit()
6893 {
6894   int i,j;
6895   uint64_t is32=1;
6896   uint64_t lastbranch=1;
6897
6898   for(i=0;i<slen;i++)
6899   {
6900     if(i>0) {
6901       if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
6902         if(i>1) is32=lastbranch;
6903         else is32=1;
6904       }
6905     }
6906     if(i>1)
6907     {
6908       if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
6909         if(likely[i-2]) {
6910           if(i>2) is32=lastbranch;
6911           else is32=1;
6912         }
6913       }
6914       if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
6915       {
6916         if(rs1[i-2]==0||rs2[i-2]==0)
6917         {
6918           if(rs1[i-2]) {
6919             is32|=1LL<<rs1[i-2];
6920           }
6921           if(rs2[i-2]) {
6922             is32|=1LL<<rs2[i-2];
6923           }
6924         }
6925       }
6926     }
6927     // If something jumps here with 64-bit values
6928     // then promote those registers to 64 bits
6929     if(bt[i])
6930     {
6931       uint64_t temp_is32=is32;
6932       for(j=i-1;j>=0;j--)
6933       {
6934         if(ba[j]==start+i*4)
6935           //temp_is32&=branch_regs[j].is32;
6936           temp_is32&=p32[j];
6937       }
6938       for(j=i;j<slen;j++)
6939       {
6940         if(ba[j]==start+i*4)
6941           temp_is32=1;
6942       }
6943       is32=temp_is32;
6944     }
6945     int type=itype[i];
6946     int op=opcode[i];
6947     int op2=opcode2[i];
6948     int rt=rt1[i];
6949     int s1=rs1[i];
6950     int s2=rs2[i];
6951     if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
6952       // Branches don't write registers, consider the delay slot instead.
6953       type=itype[i+1];
6954       op=opcode[i+1];
6955       op2=opcode2[i+1];
6956       rt=rt1[i+1];
6957       s1=rs1[i+1];
6958       s2=rs2[i+1];
6959       lastbranch=is32;
6960     }
6961     switch(type) {
6962       case LOAD:
6963         if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
6964            opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
6965           is32&=~(1LL<<rt);
6966         else
6967           is32|=1LL<<rt;
6968         break;
6969       case STORE:
6970       case STORELR:
6971         break;
6972       case LOADLR:
6973         if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
6974         if(op==0x22) is32|=1LL<<rt; // LWL
6975         break;
6976       case IMM16:
6977         if (op==0x08||op==0x09|| // ADDI/ADDIU
6978             op==0x0a||op==0x0b|| // SLTI/SLTIU
6979             op==0x0c|| // ANDI
6980             op==0x0f)  // LUI
6981         {
6982           is32|=1LL<<rt;
6983         }
6984         if(op==0x18||op==0x19) { // DADDI/DADDIU
6985           is32&=~(1LL<<rt);
6986           //if(imm[i]==0)
6987           //  is32|=((is32>>s1)&1LL)<<rt;
6988         }
6989         if(op==0x0d||op==0x0e) { // ORI/XORI
6990           uint64_t sr=((is32>>s1)&1LL);
6991           is32&=~(1LL<<rt);
6992           is32|=sr<<rt;
6993         }
6994         break;
6995       case UJUMP:
6996         break;
6997       case RJUMP:
6998         break;
6999       case CJUMP:
7000         break;
7001       case SJUMP:
7002         break;
7003       case FJUMP:
7004         break;
7005       case ALU:
7006         if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
7007           is32|=1LL<<rt;
7008         }
7009         if(op2==0x2a||op2==0x2b) { // SLT/SLTU
7010           is32|=1LL<<rt;
7011         }
7012         else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
7013           uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
7014           is32&=~(1LL<<rt);
7015           is32|=sr<<rt;
7016         }
7017         else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
7018           if(s1==0&&s2==0) {
7019             is32|=1LL<<rt;
7020           }
7021           else if(s2==0) {
7022             uint64_t sr=((is32>>s1)&1LL);
7023             is32&=~(1LL<<rt);
7024             is32|=sr<<rt;
7025           }
7026           else if(s1==0) {
7027             uint64_t sr=((is32>>s2)&1LL);
7028             is32&=~(1LL<<rt);
7029             is32|=sr<<rt;
7030           }
7031           else {
7032             is32&=~(1LL<<rt);
7033           }
7034         }
7035         else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
7036           if(s1==0&&s2==0) {
7037             is32|=1LL<<rt;
7038           }
7039           else if(s2==0) {
7040             uint64_t sr=((is32>>s1)&1LL);
7041             is32&=~(1LL<<rt);
7042             is32|=sr<<rt;
7043           }
7044           else {
7045             is32&=~(1LL<<rt);
7046           }
7047         }
7048         break;
7049       case MULTDIV:
7050         if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
7051           is32&=~((1LL<<HIREG)|(1LL<<LOREG));
7052         }
7053         else {
7054           is32|=(1LL<<HIREG)|(1LL<<LOREG);
7055         }
7056         break;
7057       case MOV:
7058         {
7059           uint64_t sr=((is32>>s1)&1LL);
7060           is32&=~(1LL<<rt);
7061           is32|=sr<<rt;
7062         }
7063         break;
7064       case SHIFT:
7065         if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
7066         else is32|=1LL<<rt; // SLLV/SRLV/SRAV
7067         break;
7068       case SHIFTIMM:
7069         is32|=1LL<<rt;
7070         // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
7071         if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
7072         break;
7073       case COP0:
7074         if(op2==0) is32|=1LL<<rt; // MFC0
7075         break;
7076       case COP1:
7077       case COP2:
7078         if(op2==0) is32|=1LL<<rt; // MFC1
7079         if(op2==1) is32&=~(1LL<<rt); // DMFC1
7080         if(op2==2) is32|=1LL<<rt; // CFC1
7081         break;
7082       case C1LS:
7083       case C2LS:
7084         break;
7085       case FLOAT:
7086       case FCONV:
7087         break;
7088       case FCOMP:
7089         break;
7090       case C2OP:
7091       case SYSCALL:
7092       case HLECALL:
7093         break;
7094       default:
7095         break;
7096     }
7097     is32|=1;
7098     p32[i]=is32;
7099
7100     if(i>0)
7101     {
7102       if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
7103       {
7104         if(rt1[i-1]==31) // JAL/JALR
7105         {
7106           // Subroutine call will return here, don't alloc any registers
7107           is32=1;
7108         }
7109         else if(i+1<slen)
7110         {
7111           // Internal branch will jump here, match registers to caller
7112           is32=0x3FFFFFFFFLL;
7113         }
7114       }
7115     }
7116   }
7117 }
7118
7119 // Identify registers which may be assumed to contain 32-bit values
7120 // and where optimizations will rely on this.
7121 // This is used to determine whether backward branches can safely
7122 // jump to a location with 64-bit values in registers.
7123 static void provisional_r32()
7124 {
7125   u_int r32=0;
7126   int i;
7127
7128   for (i=slen-1;i>=0;i--)
7129   {
7130     int hr;
7131     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7132     {
7133       if(ba[i]<start || ba[i]>=(start+slen*4))
7134       {
7135         // Branch out of this block, don't need anything
7136         r32=0;
7137       }
7138       else
7139       {
7140         // Internal branch
7141         // Need whatever matches the target
7142         // (and doesn't get overwritten by the delay slot instruction)
7143         r32=0;
7144         int t=(ba[i]-start)>>2;
7145         if(ba[i]>start+i*4) {
7146           // Forward branch
7147           //if(!(requires_32bit[t]&~regs[i].was32))
7148           //  r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7149           if(!(pr32[t]&~regs[i].was32))
7150             r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7151         }else{
7152           // Backward branch
7153           if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
7154             r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7155         }
7156       }
7157       // Conditional branch may need registers for following instructions
7158       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7159       {
7160         if(i<slen-2) {
7161           //r32|=requires_32bit[i+2];
7162           r32|=pr32[i+2];
7163           r32&=regs[i].was32;
7164           // Mark this address as a branch target since it may be called
7165           // upon return from interrupt
7166           //bt[i+2]=1;
7167         }
7168       }
7169       // Merge in delay slot
7170       if(!likely[i]) {
7171         // These are overwritten unless the branch is "likely"
7172         // and the delay slot is nullified if not taken
7173         r32&=~(1LL<<rt1[i+1]);
7174         r32&=~(1LL<<rt2[i+1]);
7175       }
7176       // Assume these are needed (delay slot)
7177       if(us1[i+1]>0)
7178       {
7179         if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7180       }
7181       if(us2[i+1]>0)
7182       {
7183         if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7184       }
7185       if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7186       {
7187         if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7188       }
7189       if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7190       {
7191         if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7192       }
7193     }
7194     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7195     {
7196       // SYSCALL instruction (software interrupt)
7197       r32=0;
7198     }
7199     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7200     {
7201       // ERET instruction (return from interrupt)
7202       r32=0;
7203     }
7204     // Check 32 bits
7205     r32&=~(1LL<<rt1[i]);
7206     r32&=~(1LL<<rt2[i]);
7207     if(us1[i]>0)
7208     {
7209       if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7210     }
7211     if(us2[i]>0)
7212     {
7213       if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7214     }
7215     if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7216     {
7217       if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7218     }
7219     if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7220     {
7221       if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7222     }
7223     //requires_32bit[i]=r32;
7224     pr32[i]=r32;
7225
7226     // Dirty registers which are 32-bit, require 32-bit input
7227     // as they will be written as 32-bit values
7228     for(hr=0;hr<HOST_REGS;hr++)
7229     {
7230       if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
7231         if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7232           if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7233           pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7234           //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7235         }
7236       }
7237     }
7238   }
7239 }
7240
7241 // Write back dirty registers as soon as we will no longer modify them,
7242 // so that we don't end up with lots of writes at the branches.
7243 void clean_registers(int istart,int iend,int wr)
7244 {
7245   int i;
7246   int r;
7247   u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7248   u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7249   if(iend==slen-1) {
7250     will_dirty_i=will_dirty_next=0;
7251     wont_dirty_i=wont_dirty_next=0;
7252   }else{
7253     will_dirty_i=will_dirty_next=will_dirty[iend+1];
7254     wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7255   }
7256   for (i=iend;i>=istart;i--)
7257   {
7258     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7259     {
7260       if(ba[i]<start || ba[i]>=(start+slen*4))
7261       {
7262         // Branch out of this block, flush all regs
7263         if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7264         {
7265           // Unconditional branch
7266           will_dirty_i=0;
7267           wont_dirty_i=0;
7268           // Merge in delay slot (will dirty)
7269           for(r=0;r<HOST_REGS;r++) {
7270             if(r!=EXCLUDE_REG) {
7271               if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7272               if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7273               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7274               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7275               if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7276               if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7277               if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7278               if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7279               if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7280               if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7281               if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7282               if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7283               if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7284               if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7285             }
7286           }
7287         }
7288         else
7289         {
7290           // Conditional branch
7291           will_dirty_i=0;
7292           wont_dirty_i=wont_dirty_next;
7293           // Merge in delay slot (will dirty)
7294           for(r=0;r<HOST_REGS;r++) {
7295             if(r!=EXCLUDE_REG) {
7296               if(!likely[i]) {
7297                 // Might not dirty if likely branch is not taken
7298                 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7299                 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7300                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7301                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7302                 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7303                 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7304                 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7305                 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7306                 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7307                 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7308                 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7309                 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7310                 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7311                 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7312               }
7313             }
7314           }
7315         }
7316         // Merge in delay slot (wont dirty)
7317         for(r=0;r<HOST_REGS;r++) {
7318           if(r!=EXCLUDE_REG) {
7319             if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7320             if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7321             if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7322             if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7323             if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7324             if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7325             if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7326             if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7327             if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7328             if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7329           }
7330         }
7331         if(wr) {
7332           #ifndef DESTRUCTIVE_WRITEBACK
7333           branch_regs[i].dirty&=wont_dirty_i;
7334           #endif
7335           branch_regs[i].dirty|=will_dirty_i;
7336         }
7337       }
7338       else
7339       {
7340         // Internal branch
7341         if(ba[i]<=start+i*4) {
7342           // Backward branch
7343           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7344           {
7345             // Unconditional branch
7346             temp_will_dirty=0;
7347             temp_wont_dirty=0;
7348             // Merge in delay slot (will dirty)
7349             for(r=0;r<HOST_REGS;r++) {
7350               if(r!=EXCLUDE_REG) {
7351                 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7352                 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7353                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7354                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7355                 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7356                 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7357                 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7358                 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7359                 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7360                 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7361                 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7362                 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7363                 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7364                 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7365               }
7366             }
7367           } else {
7368             // Conditional branch (not taken case)
7369             temp_will_dirty=will_dirty_next;
7370             temp_wont_dirty=wont_dirty_next;
7371             // Merge in delay slot (will dirty)
7372             for(r=0;r<HOST_REGS;r++) {
7373               if(r!=EXCLUDE_REG) {
7374                 if(!likely[i]) {
7375                   // Will not dirty if likely branch is not taken
7376                   if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7377                   if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7378                   if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7379                   if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7380                   if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7381                   if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7382                   if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7383                   //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7384                   //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7385                   if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7386                   if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7387                   if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7388                   if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7389                   if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7390                 }
7391               }
7392             }
7393           }
7394           // Merge in delay slot (wont dirty)
7395           for(r=0;r<HOST_REGS;r++) {
7396             if(r!=EXCLUDE_REG) {
7397               if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7398               if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7399               if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7400               if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7401               if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7402               if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7403               if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7404               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7405               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7406               if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7407             }
7408           }
7409           // Deal with changed mappings
7410           if(i<iend) {
7411             for(r=0;r<HOST_REGS;r++) {
7412               if(r!=EXCLUDE_REG) {
7413                 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7414                   temp_will_dirty&=~(1<<r);
7415                   temp_wont_dirty&=~(1<<r);
7416                   if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7417                     temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7418                     temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7419                   } else {
7420                     temp_will_dirty|=1<<r;
7421                     temp_wont_dirty|=1<<r;
7422                   }
7423                 }
7424               }
7425             }
7426           }
7427           if(wr) {
7428             will_dirty[i]=temp_will_dirty;
7429             wont_dirty[i]=temp_wont_dirty;
7430             clean_registers((ba[i]-start)>>2,i-1,0);
7431           }else{
7432             // Limit recursion.  It can take an excessive amount
7433             // of time if there are a lot of nested loops.
7434             will_dirty[(ba[i]-start)>>2]=0;
7435             wont_dirty[(ba[i]-start)>>2]=-1;
7436           }
7437         }
7438         /*else*/ if(1)
7439         {
7440           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7441           {
7442             // Unconditional branch
7443             will_dirty_i=0;
7444             wont_dirty_i=0;
7445           //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7446             for(r=0;r<HOST_REGS;r++) {
7447               if(r!=EXCLUDE_REG) {
7448                 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7449                   will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7450                   wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7451                 }
7452                 if(branch_regs[i].regmap[r]>=0) {
7453                   will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7454                   wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7455                 }
7456               }
7457             }
7458           //}
7459             // Merge in delay slot
7460             for(r=0;r<HOST_REGS;r++) {
7461               if(r!=EXCLUDE_REG) {
7462                 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7463                 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7464                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7465                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7466                 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7467                 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7468                 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7469                 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7470                 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7471                 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7472                 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7473                 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7474                 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7475                 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7476               }
7477             }
7478           } else {
7479             // Conditional branch
7480             will_dirty_i=will_dirty_next;
7481             wont_dirty_i=wont_dirty_next;
7482           //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7483             for(r=0;r<HOST_REGS;r++) {
7484               if(r!=EXCLUDE_REG) {
7485                 signed char target_reg=branch_regs[i].regmap[r];
7486                 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7487                   will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7488                   wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7489                 }
7490                 else if(target_reg>=0) {
7491                   will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7492                   wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7493                 }
7494                 // Treat delay slot as part of branch too
7495                 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7496                   will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7497                   wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7498                 }
7499                 else
7500                 {
7501                   will_dirty[i+1]&=~(1<<r);
7502                 }*/
7503               }
7504             }
7505           //}
7506             // Merge in delay slot
7507             for(r=0;r<HOST_REGS;r++) {
7508               if(r!=EXCLUDE_REG) {
7509                 if(!likely[i]) {
7510                   // Might not dirty if likely branch is not taken
7511                   if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7512                   if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7513                   if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7514                   if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7515                   if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7516                   if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7517                   if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7518                   //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7519                   //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7520                   if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7521                   if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7522                   if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7523                   if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7524                   if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7525                 }
7526               }
7527             }
7528           }
7529           // Merge in delay slot (won't dirty)
7530           for(r=0;r<HOST_REGS;r++) {
7531             if(r!=EXCLUDE_REG) {
7532               if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7533               if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7534               if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7535               if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7536               if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7537               if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7538               if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7539               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7540               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7541               if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7542             }
7543           }
7544           if(wr) {
7545             #ifndef DESTRUCTIVE_WRITEBACK
7546             branch_regs[i].dirty&=wont_dirty_i;
7547             #endif
7548             branch_regs[i].dirty|=will_dirty_i;
7549           }
7550         }
7551       }
7552     }
7553     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7554     {
7555       // SYSCALL instruction (software interrupt)
7556       will_dirty_i=0;
7557       wont_dirty_i=0;
7558     }
7559     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7560     {
7561       // ERET instruction (return from interrupt)
7562       will_dirty_i=0;
7563       wont_dirty_i=0;
7564     }
7565     will_dirty_next=will_dirty_i;
7566     wont_dirty_next=wont_dirty_i;
7567     for(r=0;r<HOST_REGS;r++) {
7568       if(r!=EXCLUDE_REG) {
7569         if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7570         if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7571         if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7572         if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7573         if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7574         if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7575         if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7576         if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7577         if(i>istart) {
7578           if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7579           {
7580             // Don't store a register immediately after writing it,
7581             // may prevent dual-issue.
7582             if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7583             if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7584           }
7585         }
7586       }
7587     }
7588     // Save it
7589     will_dirty[i]=will_dirty_i;
7590     wont_dirty[i]=wont_dirty_i;
7591     // Mark registers that won't be dirtied as not dirty
7592     if(wr) {
7593       /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7594       for(r=0;r<HOST_REGS;r++) {
7595         if((will_dirty_i>>r)&1) {
7596           printf(" r%d",r);
7597         }
7598       }
7599       printf("\n");*/
7600
7601       //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7602         regs[i].dirty|=will_dirty_i;
7603         #ifndef DESTRUCTIVE_WRITEBACK
7604         regs[i].dirty&=wont_dirty_i;
7605         if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7606         {
7607           if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7608             for(r=0;r<HOST_REGS;r++) {
7609               if(r!=EXCLUDE_REG) {
7610                 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7611                   regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7612                 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7613               }
7614             }
7615           }
7616         }
7617         else
7618         {
7619           if(i<iend) {
7620             for(r=0;r<HOST_REGS;r++) {
7621               if(r!=EXCLUDE_REG) {
7622                 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7623                   regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7624                 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7625               }
7626             }
7627           }
7628         }
7629         #endif
7630       //}
7631     }
7632     // Deal with changed mappings
7633     temp_will_dirty=will_dirty_i;
7634     temp_wont_dirty=wont_dirty_i;
7635     for(r=0;r<HOST_REGS;r++) {
7636       if(r!=EXCLUDE_REG) {
7637         int nr;
7638         if(regs[i].regmap[r]==regmap_pre[i][r]) {
7639           if(wr) {
7640             #ifndef DESTRUCTIVE_WRITEBACK
7641             regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7642             #endif
7643             regs[i].wasdirty|=will_dirty_i&(1<<r);
7644           }
7645         }
7646         else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7647           // Register moved to a different register
7648           will_dirty_i&=~(1<<r);
7649           wont_dirty_i&=~(1<<r);
7650           will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7651           wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7652           if(wr) {
7653             #ifndef DESTRUCTIVE_WRITEBACK
7654             regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7655             #endif
7656             regs[i].wasdirty|=will_dirty_i&(1<<r);
7657           }
7658         }
7659         else {
7660           will_dirty_i&=~(1<<r);
7661           wont_dirty_i&=~(1<<r);
7662           if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7663             will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7664             wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7665           } else {
7666             wont_dirty_i|=1<<r;
7667             /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7668           }
7669         }
7670       }
7671     }
7672   }
7673 }
7674
7675   /* disassembly */
7676 void disassemble_inst(int i)
7677 {
7678     if (bt[i]) printf("*"); else printf(" ");
7679     switch(itype[i]) {
7680       case UJUMP:
7681         printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7682       case CJUMP:
7683         printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7684       case SJUMP:
7685         printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7686       case FJUMP:
7687         printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7688       case RJUMP:
7689         if (opcode[i]==0x9&&rt1[i]!=31)
7690           printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7691         else
7692           printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7693         break;
7694       case SPAN:
7695         printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7696       case IMM16:
7697         if(opcode[i]==0xf) //LUI
7698           printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7699         else
7700           printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7701         break;
7702       case LOAD:
7703       case LOADLR:
7704         printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7705         break;
7706       case STORE:
7707       case STORELR:
7708         printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7709         break;
7710       case ALU:
7711       case SHIFT:
7712         printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7713         break;
7714       case MULTDIV:
7715         printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7716         break;
7717       case SHIFTIMM:
7718         printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7719         break;
7720       case MOV:
7721         if((opcode2[i]&0x1d)==0x10)
7722           printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7723         else if((opcode2[i]&0x1d)==0x11)
7724           printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7725         else
7726           printf (" %x: %s\n",start+i*4,insn[i]);
7727         break;
7728       case COP0:
7729         if(opcode2[i]==0)
7730           printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7731         else if(opcode2[i]==4)
7732           printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7733         else printf (" %x: %s\n",start+i*4,insn[i]);
7734         break;
7735       case COP1:
7736         if(opcode2[i]<3)
7737           printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7738         else if(opcode2[i]>3)
7739           printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7740         else printf (" %x: %s\n",start+i*4,insn[i]);
7741         break;
7742       case COP2:
7743         if(opcode2[i]<3)
7744           printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7745         else if(opcode2[i]>3)
7746           printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7747         else printf (" %x: %s\n",start+i*4,insn[i]);
7748         break;
7749       case C1LS:
7750         printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7751         break;
7752       case C2LS:
7753         printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7754         break;
7755       case INTCALL:
7756         printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
7757         break;
7758       default:
7759         //printf (" %s %8x\n",insn[i],source[i]);
7760         printf (" %x: %s\n",start+i*4,insn[i]);
7761     }
7762 }
7763
7764 // clear the state completely, instead of just marking
7765 // things invalid like invalidate_all_pages() does
7766 void new_dynarec_clear_full()
7767 {
7768   int n;
7769   out=(u_char *)BASE_ADDR;
7770   memset(invalid_code,1,sizeof(invalid_code));
7771   memset(hash_table,0xff,sizeof(hash_table));
7772   memset(mini_ht,-1,sizeof(mini_ht));
7773   memset(restore_candidate,0,sizeof(restore_candidate));
7774   memset(shadow,0,sizeof(shadow));
7775   copy=shadow;
7776   expirep=16384; // Expiry pointer, +2 blocks
7777   pending_exception=0;
7778   literalcount=0;
7779   stop_after_jal=0;
7780   // TLB
7781 #ifndef DISABLE_TLB
7782   using_tlb=0;
7783 #endif
7784   sp_in_mirror=0;
7785   for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7786     memory_map[n]=-1;
7787   for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7788     memory_map[n]=((u_int)rdram-0x80000000)>>2;
7789   for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7790     memory_map[n]=-1;
7791   for(n=0;n<4096;n++) ll_clear(jump_in+n);
7792   for(n=0;n<4096;n++) ll_clear(jump_out+n);
7793   for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7794 }
7795
7796 void new_dynarec_init()
7797 {
7798   printf("Init new dynarec\n");
7799   out=(u_char *)BASE_ADDR;
7800   if (mmap (out, 1<<TARGET_SIZE_2,
7801             PROT_READ | PROT_WRITE | PROT_EXEC,
7802             MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
7803             -1, 0) <= 0) {printf("mmap() failed\n");}
7804 #ifdef MUPEN64
7805   rdword=&readmem_dword;
7806   fake_pc.f.r.rs=&readmem_dword;
7807   fake_pc.f.r.rt=&readmem_dword;
7808   fake_pc.f.r.rd=&readmem_dword;
7809 #endif
7810   int n;
7811   new_dynarec_clear_full();
7812 #ifdef HOST_IMM8
7813   // Copy this into local area so we don't have to put it in every literal pool
7814   invc_ptr=invalid_code;
7815 #endif
7816 #ifdef MUPEN64
7817   for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
7818     writemem[n] = write_nomem_new;
7819     writememb[n] = write_nomemb_new;
7820     writememh[n] = write_nomemh_new;
7821 #ifndef FORCE32
7822     writememd[n] = write_nomemd_new;
7823 #endif
7824     readmem[n] = read_nomem_new;
7825     readmemb[n] = read_nomemb_new;
7826     readmemh[n] = read_nomemh_new;
7827 #ifndef FORCE32
7828     readmemd[n] = read_nomemd_new;
7829 #endif
7830   }
7831   for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
7832     writemem[n] = write_rdram_new;
7833     writememb[n] = write_rdramb_new;
7834     writememh[n] = write_rdramh_new;
7835 #ifndef FORCE32
7836     writememd[n] = write_rdramd_new;
7837 #endif
7838   }
7839   for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
7840     writemem[n] = write_nomem_new;
7841     writememb[n] = write_nomemb_new;
7842     writememh[n] = write_nomemh_new;
7843 #ifndef FORCE32
7844     writememd[n] = write_nomemd_new;
7845 #endif
7846     readmem[n] = read_nomem_new;
7847     readmemb[n] = read_nomemb_new;
7848     readmemh[n] = read_nomemh_new;
7849 #ifndef FORCE32
7850     readmemd[n] = read_nomemd_new;
7851 #endif
7852   }
7853 #endif
7854   tlb_hacks();
7855   arch_init();
7856 }
7857
7858 void new_dynarec_cleanup()
7859 {
7860   int n;
7861   if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
7862   for(n=0;n<4096;n++) ll_clear(jump_in+n);
7863   for(n=0;n<4096;n++) ll_clear(jump_out+n);
7864   for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7865   #ifdef ROM_COPY
7866   if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
7867   #endif
7868 }
7869
7870 int new_recompile_block(int addr)
7871 {
7872 /*
7873   if(addr==0x800cd050) {
7874     int block;
7875     for(block=0x80000;block<0x80800;block++) invalidate_block(block);
7876     int n;
7877     for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
7878   }
7879 */
7880   //if(Count==365117028) tracedebug=1;
7881   assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7882   //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7883   //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
7884   //if(debug)
7885   //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
7886   //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
7887   /*if(Count>=312978186) {
7888     rlist();
7889   }*/
7890   //rlist();
7891   start = (u_int)addr&~3;
7892   //assert(((u_int)addr&1)==0);
7893 #ifdef PCSX
7894   if(!sp_in_mirror&&(signed int)(psxRegs.GPR.n.sp&0xffe00000)>0x80200000&&
7895      0x10000<=psxRegs.GPR.n.sp&&(psxRegs.GPR.n.sp&~0xe0e00000)<RAM_SIZE) {
7896     printf("SP hack enabled (%08x), @%08x\n", psxRegs.GPR.n.sp, psxRegs.pc);
7897     sp_in_mirror=1;
7898   }
7899   if (Config.HLE && start == 0x80001000) // hlecall
7900   {
7901     // XXX: is this enough? Maybe check hleSoftCall?
7902     u_int beginning=(u_int)out;
7903     u_int page=get_page(start);
7904     invalid_code[start>>12]=0;
7905     emit_movimm(start,0);
7906     emit_writeword(0,(int)&pcaddr);
7907     emit_jmp((int)new_dyna_leave);
7908 #ifdef __arm__
7909     __clear_cache((void *)beginning,out);
7910 #endif
7911     ll_add(jump_in+page,start,(void *)beginning);
7912     return 0;
7913   }
7914   else if ((u_int)addr < 0x00200000 ||
7915     (0xa0000000 <= addr && addr < 0xa0200000)) {
7916     // used for BIOS calls mostly?
7917     source = (u_int *)((u_int)rdram+(start&0x1fffff));
7918     pagelimit = (addr&0xa0000000)|0x00200000;
7919   }
7920   else if (!Config.HLE && (
7921 /*    (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
7922     (0xbfc00000 <= addr && addr < 0xbfc80000))) {
7923     // BIOS
7924     source = (u_int *)((u_int)psxR+(start&0x7ffff));
7925     pagelimit = (addr&0xfff00000)|0x80000;
7926   }
7927   else
7928 #endif
7929 #ifdef MUPEN64
7930   if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
7931     source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
7932     pagelimit = 0xa4001000;
7933   }
7934   else
7935 #endif
7936   if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
7937     source = (u_int *)((u_int)rdram+start-0x80000000);
7938     pagelimit = 0x80000000+RAM_SIZE;
7939   }
7940 #ifndef DISABLE_TLB
7941   else if ((signed int)addr >= (signed int)0xC0000000) {
7942     //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
7943     //if(tlb_LUT_r[start>>12])
7944       //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
7945     if((signed int)memory_map[start>>12]>=0) {
7946       source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
7947       pagelimit=(start+4096)&0xFFFFF000;
7948       int map=memory_map[start>>12];
7949       int i;
7950       for(i=0;i<5;i++) {
7951         //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
7952         if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
7953       }
7954       assem_debug("pagelimit=%x\n",pagelimit);
7955       assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
7956     }
7957     else {
7958       assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
7959       //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
7960       return -1; // Caller will invoke exception handler
7961     }
7962     //printf("source= %x\n",(int)source);
7963   }
7964 #endif
7965   else {
7966     printf("Compile at bogus memory address: %x \n", (int)addr);
7967     exit(1);
7968   }
7969
7970   /* Pass 1: disassemble */
7971   /* Pass 2: register dependencies, branch targets */
7972   /* Pass 3: register allocation */
7973   /* Pass 4: branch dependencies */
7974   /* Pass 5: pre-alloc */
7975   /* Pass 6: optimize clean/dirty state */
7976   /* Pass 7: flag 32-bit registers */
7977   /* Pass 8: assembly */
7978   /* Pass 9: linker */
7979   /* Pass 10: garbage collection / free memory */
7980
7981   int i,j;
7982   int done=0;
7983   unsigned int type,op,op2;
7984
7985   //printf("addr = %x source = %x %x\n", addr,source,source[0]);
7986
7987   /* Pass 1 disassembly */
7988
7989   for(i=0;!done;i++) {
7990     bt[i]=0;likely[i]=0;ooo[i]=0;op2=0;
7991     minimum_free_regs[i]=0;
7992     opcode[i]=op=source[i]>>26;
7993     switch(op)
7994     {
7995       case 0x00: strcpy(insn[i],"special"); type=NI;
7996         op2=source[i]&0x3f;
7997         switch(op2)
7998         {
7999           case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
8000           case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
8001           case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
8002           case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
8003           case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
8004           case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
8005           case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
8006           case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
8007           case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
8008           case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
8009           case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
8010           case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
8011           case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
8012           case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
8013           case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
8014           case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
8015           case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
8016           case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
8017           case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
8018           case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
8019           case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
8020           case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
8021           case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
8022           case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
8023           case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
8024           case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
8025           case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
8026           case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
8027           case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
8028           case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
8029           case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
8030           case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
8031           case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
8032           case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
8033           case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
8034 #ifndef FORCE32
8035           case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
8036           case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
8037           case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
8038           case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
8039           case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
8040           case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
8041           case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
8042           case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
8043           case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
8044           case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
8045           case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
8046           case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
8047           case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
8048           case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
8049           case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
8050           case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
8051           case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
8052 #endif
8053         }
8054         break;
8055       case 0x01: strcpy(insn[i],"regimm"); type=NI;
8056         op2=(source[i]>>16)&0x1f;
8057         switch(op2)
8058         {
8059           case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
8060           case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
8061           case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
8062           case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
8063           case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
8064           case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
8065           case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
8066           case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
8067           case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
8068           case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
8069           case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
8070           case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
8071           case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
8072           case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
8073         }
8074         break;
8075       case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
8076       case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
8077       case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
8078       case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
8079       case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
8080       case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
8081       case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
8082       case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
8083       case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
8084       case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
8085       case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
8086       case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
8087       case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
8088       case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
8089       case 0x10: strcpy(insn[i],"cop0"); type=NI;
8090         op2=(source[i]>>21)&0x1f;
8091         switch(op2)
8092         {
8093           case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
8094           case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
8095           case 0x10: strcpy(insn[i],"tlb"); type=NI;
8096           switch(source[i]&0x3f)
8097           {
8098             case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
8099             case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
8100             case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
8101             case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
8102 #ifdef PCSX
8103             case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
8104 #else
8105             case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
8106 #endif
8107           }
8108         }
8109         break;
8110       case 0x11: strcpy(insn[i],"cop1"); type=NI;
8111         op2=(source[i]>>21)&0x1f;
8112         switch(op2)
8113         {
8114           case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
8115           case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
8116           case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
8117           case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
8118           case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
8119           case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
8120           case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
8121           switch((source[i]>>16)&0x3)
8122           {
8123             case 0x00: strcpy(insn[i],"BC1F"); break;
8124             case 0x01: strcpy(insn[i],"BC1T"); break;
8125             case 0x02: strcpy(insn[i],"BC1FL"); break;
8126             case 0x03: strcpy(insn[i],"BC1TL"); break;
8127           }
8128           break;
8129           case 0x10: strcpy(insn[i],"C1.S"); type=NI;
8130           switch(source[i]&0x3f)
8131           {
8132             case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
8133             case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
8134             case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
8135             case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
8136             case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
8137             case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
8138             case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
8139             case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
8140             case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
8141             case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
8142             case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
8143             case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
8144             case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
8145             case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
8146             case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
8147             case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
8148             case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
8149             case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
8150             case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
8151             case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
8152             case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
8153             case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
8154             case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
8155             case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
8156             case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
8157             case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
8158             case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
8159             case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
8160             case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
8161             case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
8162             case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
8163             case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
8164             case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
8165             case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
8166             case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
8167           }
8168           break;
8169           case 0x11: strcpy(insn[i],"C1.D"); type=NI;
8170           switch(source[i]&0x3f)
8171           {
8172             case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
8173             case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
8174             case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
8175             case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
8176             case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
8177             case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
8178             case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
8179             case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
8180             case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
8181             case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
8182             case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
8183             case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
8184             case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
8185             case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
8186             case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
8187             case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
8188             case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
8189             case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
8190             case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
8191             case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
8192             case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
8193             case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
8194             case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
8195             case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
8196             case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
8197             case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
8198             case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
8199             case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
8200             case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
8201             case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
8202             case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8203             case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8204             case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8205             case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8206             case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8207           }
8208           break;
8209           case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8210           switch(source[i]&0x3f)
8211           {
8212             case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8213             case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8214           }
8215           break;
8216           case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8217           switch(source[i]&0x3f)
8218           {
8219             case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8220             case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8221           }
8222           break;
8223         }
8224         break;
8225 #ifndef FORCE32
8226       case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8227       case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8228       case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8229       case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8230       case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8231       case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8232       case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8233       case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
8234 #endif
8235       case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8236       case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8237       case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8238       case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8239       case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8240       case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8241       case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
8242 #ifndef FORCE32
8243       case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
8244 #endif
8245       case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8246       case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8247       case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8248       case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
8249 #ifndef FORCE32
8250       case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8251       case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
8252 #endif
8253       case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8254       case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8255       case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8256       case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
8257 #ifndef FORCE32
8258       case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8259       case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8260       case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
8261 #endif
8262       case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8263       case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
8264 #ifndef FORCE32
8265       case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8266       case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8267       case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
8268 #endif
8269 #ifdef PCSX
8270       case 0x12: strcpy(insn[i],"COP2"); type=NI;
8271         // note: COP MIPS-1 encoding differs from MIPS32
8272         op2=(source[i]>>21)&0x1f;
8273         if (source[i]&0x3f) {
8274           if (gte_handlers[source[i]&0x3f]!=NULL) {
8275             snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8276             type=C2OP;
8277           }
8278         }
8279         else switch(op2)
8280         {
8281           case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8282           case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8283           case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8284           case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
8285         }
8286         break;
8287       case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8288       case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8289       case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8290 #endif
8291       default: strcpy(insn[i],"???"); type=NI;
8292         printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
8293         break;
8294     }
8295     itype[i]=type;
8296     opcode2[i]=op2;
8297     /* Get registers/immediates */
8298     lt1[i]=0;
8299     us1[i]=0;
8300     us2[i]=0;
8301     dep1[i]=0;
8302     dep2[i]=0;
8303     switch(type) {
8304       case LOAD:
8305         rs1[i]=(source[i]>>21)&0x1f;
8306         rs2[i]=0;
8307         rt1[i]=(source[i]>>16)&0x1f;
8308         rt2[i]=0;
8309         imm[i]=(short)source[i];
8310         break;
8311       case STORE:
8312       case STORELR:
8313         rs1[i]=(source[i]>>21)&0x1f;
8314         rs2[i]=(source[i]>>16)&0x1f;
8315         rt1[i]=0;
8316         rt2[i]=0;
8317         imm[i]=(short)source[i];
8318         if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8319         break;
8320       case LOADLR:
8321         // LWL/LWR only load part of the register,
8322         // therefore the target register must be treated as a source too
8323         rs1[i]=(source[i]>>21)&0x1f;
8324         rs2[i]=(source[i]>>16)&0x1f;
8325         rt1[i]=(source[i]>>16)&0x1f;
8326         rt2[i]=0;
8327         imm[i]=(short)source[i];
8328         if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8329         if(op==0x26) dep1[i]=rt1[i]; // LWR
8330         break;
8331       case IMM16:
8332         if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8333         else rs1[i]=(source[i]>>21)&0x1f;
8334         rs2[i]=0;
8335         rt1[i]=(source[i]>>16)&0x1f;
8336         rt2[i]=0;
8337         if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8338           imm[i]=(unsigned short)source[i];
8339         }else{
8340           imm[i]=(short)source[i];
8341         }
8342         if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8343         if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8344         if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8345         break;
8346       case UJUMP:
8347         rs1[i]=0;
8348         rs2[i]=0;
8349         rt1[i]=0;
8350         rt2[i]=0;
8351         // The JAL instruction writes to r31.
8352         if (op&1) {
8353           rt1[i]=31;
8354         }
8355         rs2[i]=CCREG;
8356         break;
8357       case RJUMP:
8358         rs1[i]=(source[i]>>21)&0x1f;
8359         rs2[i]=0;
8360         rt1[i]=0;
8361         rt2[i]=0;
8362         // The JALR instruction writes to rd.
8363         if (op2&1) {
8364           rt1[i]=(source[i]>>11)&0x1f;
8365         }
8366         rs2[i]=CCREG;
8367         break;
8368       case CJUMP:
8369         rs1[i]=(source[i]>>21)&0x1f;
8370         rs2[i]=(source[i]>>16)&0x1f;
8371         rt1[i]=0;
8372         rt2[i]=0;
8373         if(op&2) { // BGTZ/BLEZ
8374           rs2[i]=0;
8375         }
8376         us1[i]=rs1[i];
8377         us2[i]=rs2[i];
8378         likely[i]=op>>4;
8379         break;
8380       case SJUMP:
8381         rs1[i]=(source[i]>>21)&0x1f;
8382         rs2[i]=CCREG;
8383         rt1[i]=0;
8384         rt2[i]=0;
8385         us1[i]=rs1[i];
8386         if(op2&0x10) { // BxxAL
8387           rt1[i]=31;
8388           // NOTE: If the branch is not taken, r31 is still overwritten
8389         }
8390         likely[i]=(op2&2)>>1;
8391         break;
8392       case FJUMP:
8393         rs1[i]=FSREG;
8394         rs2[i]=CSREG;
8395         rt1[i]=0;
8396         rt2[i]=0;
8397         likely[i]=((source[i])>>17)&1;
8398         break;
8399       case ALU:
8400         rs1[i]=(source[i]>>21)&0x1f; // source
8401         rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8402         rt1[i]=(source[i]>>11)&0x1f; // destination
8403         rt2[i]=0;
8404         if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8405           us1[i]=rs1[i];us2[i]=rs2[i];
8406         }
8407         else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8408           dep1[i]=rs1[i];dep2[i]=rs2[i];
8409         }
8410         else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8411           dep1[i]=rs1[i];dep2[i]=rs2[i];
8412         }
8413         break;
8414       case MULTDIV:
8415         rs1[i]=(source[i]>>21)&0x1f; // source
8416         rs2[i]=(source[i]>>16)&0x1f; // divisor
8417         rt1[i]=HIREG;
8418         rt2[i]=LOREG;
8419         if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8420           us1[i]=rs1[i];us2[i]=rs2[i];
8421         }
8422         break;
8423       case MOV:
8424         rs1[i]=0;
8425         rs2[i]=0;
8426         rt1[i]=0;
8427         rt2[i]=0;
8428         if(op2==0x10) rs1[i]=HIREG; // MFHI
8429         if(op2==0x11) rt1[i]=HIREG; // MTHI
8430         if(op2==0x12) rs1[i]=LOREG; // MFLO
8431         if(op2==0x13) rt1[i]=LOREG; // MTLO
8432         if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8433         if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8434         dep1[i]=rs1[i];
8435         break;
8436       case SHIFT:
8437         rs1[i]=(source[i]>>16)&0x1f; // target of shift
8438         rs2[i]=(source[i]>>21)&0x1f; // shift amount
8439         rt1[i]=(source[i]>>11)&0x1f; // destination
8440         rt2[i]=0;
8441         // DSLLV/DSRLV/DSRAV are 64-bit
8442         if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8443         break;
8444       case SHIFTIMM:
8445         rs1[i]=(source[i]>>16)&0x1f;
8446         rs2[i]=0;
8447         rt1[i]=(source[i]>>11)&0x1f;
8448         rt2[i]=0;
8449         imm[i]=(source[i]>>6)&0x1f;
8450         // DSxx32 instructions
8451         if(op2>=0x3c) imm[i]|=0x20;
8452         // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8453         if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8454         break;
8455       case COP0:
8456         rs1[i]=0;
8457         rs2[i]=0;
8458         rt1[i]=0;
8459         rt2[i]=0;
8460         if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8461         if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8462         if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8463         if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8464         break;
8465       case COP1:
8466       case COP2:
8467         rs1[i]=0;
8468         rs2[i]=0;
8469         rt1[i]=0;
8470         rt2[i]=0;
8471         if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8472         if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8473         if(op2==5) us1[i]=rs1[i]; // DMTC1
8474         rs2[i]=CSREG;
8475         break;
8476       case C1LS:
8477         rs1[i]=(source[i]>>21)&0x1F;
8478         rs2[i]=CSREG;
8479         rt1[i]=0;
8480         rt2[i]=0;
8481         imm[i]=(short)source[i];
8482         break;
8483       case C2LS:
8484         rs1[i]=(source[i]>>21)&0x1F;
8485         rs2[i]=0;
8486         rt1[i]=0;
8487         rt2[i]=0;
8488         imm[i]=(short)source[i];
8489         break;
8490       case FLOAT:
8491       case FCONV:
8492         rs1[i]=0;
8493         rs2[i]=CSREG;
8494         rt1[i]=0;
8495         rt2[i]=0;
8496         break;
8497       case FCOMP:
8498         rs1[i]=FSREG;
8499         rs2[i]=CSREG;
8500         rt1[i]=FSREG;
8501         rt2[i]=0;
8502         break;
8503       case SYSCALL:
8504       case HLECALL:
8505       case INTCALL:
8506         rs1[i]=CCREG;
8507         rs2[i]=0;
8508         rt1[i]=0;
8509         rt2[i]=0;
8510         break;
8511       default:
8512         rs1[i]=0;
8513         rs2[i]=0;
8514         rt1[i]=0;
8515         rt2[i]=0;
8516     }
8517     /* Calculate branch target addresses */
8518     if(type==UJUMP)
8519       ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8520     else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8521       ba[i]=start+i*4+8; // Ignore never taken branch
8522     else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8523       ba[i]=start+i*4+8; // Ignore never taken branch
8524     else if(type==CJUMP||type==SJUMP||type==FJUMP)
8525       ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8526     else ba[i]=-1;
8527 #ifdef PCSX
8528     if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
8529       int do_in_intrp=0;
8530       // branch in delay slot?
8531       if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
8532         // don't handle first branch and call interpreter if it's hit
8533         printf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
8534         do_in_intrp=1;
8535       }
8536       // basic load delay detection
8537       else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&rt1[i]!=0) {
8538         int t=(ba[i-1]-start)/4;
8539         if(0 <= t && t < i &&(rt1[i]==rs1[t]||rt1[i]==rs2[t])&&itype[t]!=CJUMP&&itype[t]!=SJUMP) {
8540           // jump target wants DS result - potential load delay effect
8541           printf("load delay @%08x (%08x)\n", addr + i*4, addr);
8542           do_in_intrp=1;
8543           bt[t+1]=1; // expected return from interpreter
8544         }
8545         else if(i>=2&&rt1[i-2]==2&&rt1[i]==2&&rs1[i]!=2&&rs2[i]!=2&&rs1[i-1]!=2&&rs2[i-1]!=2&&
8546               !(i>=3&&(itype[i-3]==RJUMP||itype[i-3]==UJUMP||itype[i-3]==CJUMP||itype[i-3]==SJUMP))) {
8547           // v0 overwrite like this is a sign of trouble, bail out
8548           printf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
8549           do_in_intrp=1;
8550         }
8551       }
8552       if(do_in_intrp) {
8553         rs1[i-1]=CCREG;
8554         rs2[i-1]=rt1[i-1]=rt2[i-1]=0;
8555         ba[i-1]=-1;
8556         itype[i-1]=INTCALL;
8557         done=2;
8558         i--; // don't compile the DS
8559       }
8560     }
8561 #endif
8562     /* Is this the end of the block? */
8563     if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
8564       if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
8565         done=2;
8566       }
8567       else {
8568         if(stop_after_jal) done=1;
8569         // Stop on BREAK
8570         if((source[i+1]&0xfc00003f)==0x0d) done=1;
8571       }
8572       // Don't recompile stuff that's already compiled
8573       if(check_addr(start+i*4+4)) done=1;
8574       // Don't get too close to the limit
8575       if(i>MAXBLOCK/2) done=1;
8576     }
8577     if(itype[i]==SYSCALL&&stop_after_jal) done=1;
8578     if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
8579     if(done==2) {
8580       // Does the block continue due to a branch?
8581       for(j=i-1;j>=0;j--)
8582       {
8583         if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
8584         if(ba[j]==start+i*4+4) done=j=0;
8585         if(ba[j]==start+i*4+8) done=j=0;
8586       }
8587     }
8588     //assert(i<MAXBLOCK-1);
8589     if(start+i*4==pagelimit-4) done=1;
8590     assert(start+i*4<pagelimit);
8591     if (i==MAXBLOCK-1) done=1;
8592     // Stop if we're compiling junk
8593     if(itype[i]==NI&&opcode[i]==0x11) {
8594       done=stop_after_jal=1;
8595       printf("Disabled speculative precompilation\n");
8596     }
8597   }
8598   slen=i;
8599   if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8600     if(start+i*4==pagelimit) {
8601       itype[i-1]=SPAN;
8602     }
8603   }
8604   assert(slen>0);
8605
8606   /* Pass 2 - Register dependencies and branch targets */
8607
8608   unneeded_registers(0,slen-1,0);
8609
8610   /* Pass 3 - Register allocation */
8611
8612   struct regstat current; // Current register allocations/status
8613   current.is32=1;
8614   current.dirty=0;
8615   current.u=unneeded_reg[0];
8616   current.uu=unneeded_reg_upper[0];
8617   clear_all_regs(current.regmap);
8618   alloc_reg(&current,0,CCREG);
8619   dirty_reg(&current,CCREG);
8620   current.isconst=0;
8621   current.wasconst=0;
8622   int ds=0;
8623   int cc=0;
8624   int hr=-1;
8625
8626 #ifndef FORCE32
8627   provisional_32bit();
8628 #endif
8629   if((u_int)addr&1) {
8630     // First instruction is delay slot
8631     cc=-1;
8632     bt[1]=1;
8633     ds=1;
8634     unneeded_reg[0]=1;
8635     unneeded_reg_upper[0]=1;
8636     current.regmap[HOST_BTREG]=BTREG;
8637   }
8638
8639   for(i=0;i<slen;i++)
8640   {
8641     if(bt[i])
8642     {
8643       int hr;
8644       for(hr=0;hr<HOST_REGS;hr++)
8645       {
8646         // Is this really necessary?
8647         if(current.regmap[hr]==0) current.regmap[hr]=-1;
8648       }
8649       current.isconst=0;
8650     }
8651     if(i>1)
8652     {
8653       if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8654       {
8655         if(rs1[i-2]==0||rs2[i-2]==0)
8656         {
8657           if(rs1[i-2]) {
8658             current.is32|=1LL<<rs1[i-2];
8659             int hr=get_reg(current.regmap,rs1[i-2]|64);
8660             if(hr>=0) current.regmap[hr]=-1;
8661           }
8662           if(rs2[i-2]) {
8663             current.is32|=1LL<<rs2[i-2];
8664             int hr=get_reg(current.regmap,rs2[i-2]|64);
8665             if(hr>=0) current.regmap[hr]=-1;
8666           }
8667         }
8668       }
8669     }
8670 #ifndef FORCE32
8671     // If something jumps here with 64-bit values
8672     // then promote those registers to 64 bits
8673     if(bt[i])
8674     {
8675       uint64_t temp_is32=current.is32;
8676       for(j=i-1;j>=0;j--)
8677       {
8678         if(ba[j]==start+i*4)
8679           temp_is32&=branch_regs[j].is32;
8680       }
8681       for(j=i;j<slen;j++)
8682       {
8683         if(ba[j]==start+i*4)
8684           //temp_is32=1;
8685           temp_is32&=p32[j];
8686       }
8687       if(temp_is32!=current.is32) {
8688         //printf("dumping 32-bit regs (%x)\n",start+i*4);
8689         #ifndef DESTRUCTIVE_WRITEBACK
8690         if(ds)
8691         #endif
8692         for(hr=0;hr<HOST_REGS;hr++)
8693         {
8694           int r=current.regmap[hr];
8695           if(r>0&&r<64)
8696           {
8697             if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8698               temp_is32|=1LL<<r;
8699               //printf("restore %d\n",r);
8700             }
8701           }
8702         }
8703         current.is32=temp_is32;
8704       }
8705     }
8706 #else
8707     current.is32=-1LL;
8708 #endif
8709
8710     memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8711     regs[i].wasconst=current.isconst;
8712     regs[i].was32=current.is32;
8713     regs[i].wasdirty=current.dirty;
8714     #if defined(DESTRUCTIVE_WRITEBACK) && !defined(FORCE32)
8715     // To change a dirty register from 32 to 64 bits, we must write
8716     // it out during the previous cycle (for branches, 2 cycles)
8717     if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8718     {
8719       uint64_t temp_is32=current.is32;
8720       for(j=i-1;j>=0;j--)
8721       {
8722         if(ba[j]==start+i*4+4)
8723           temp_is32&=branch_regs[j].is32;
8724       }
8725       for(j=i;j<slen;j++)
8726       {
8727         if(ba[j]==start+i*4+4)
8728           //temp_is32=1;
8729           temp_is32&=p32[j];
8730       }
8731       if(temp_is32!=current.is32) {
8732         //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8733         for(hr=0;hr<HOST_REGS;hr++)
8734         {
8735           int r=current.regmap[hr];
8736           if(r>0)
8737           {
8738             if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8739               if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
8740               {
8741                 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
8742                 {
8743                   //printf("dump %d/r%d\n",hr,r);
8744                   current.regmap[hr]=-1;
8745                   if(get_reg(current.regmap,r|64)>=0)
8746                     current.regmap[get_reg(current.regmap,r|64)]=-1;
8747                 }
8748               }
8749             }
8750           }
8751         }
8752       }
8753     }
8754     else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
8755     {
8756       uint64_t temp_is32=current.is32;
8757       for(j=i-1;j>=0;j--)
8758       {
8759         if(ba[j]==start+i*4+8)
8760           temp_is32&=branch_regs[j].is32;
8761       }
8762       for(j=i;j<slen;j++)
8763       {
8764         if(ba[j]==start+i*4+8)
8765           //temp_is32=1;
8766           temp_is32&=p32[j];
8767       }
8768       if(temp_is32!=current.is32) {
8769         //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8770         for(hr=0;hr<HOST_REGS;hr++)
8771         {
8772           int r=current.regmap[hr];
8773           if(r>0)
8774           {
8775             if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8776               if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
8777               {
8778                 //printf("dump %d/r%d\n",hr,r);
8779                 current.regmap[hr]=-1;
8780                 if(get_reg(current.regmap,r|64)>=0)
8781                   current.regmap[get_reg(current.regmap,r|64)]=-1;
8782               }
8783             }
8784           }
8785         }
8786       }
8787     }
8788     #endif
8789     if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8790       if(i+1<slen) {
8791         current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8792         current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8793         if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8794         current.u|=1;
8795         current.uu|=1;
8796       } else {
8797         current.u=1;
8798         current.uu=1;
8799       }
8800     } else {
8801       if(i+1<slen) {
8802         current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
8803         current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8804         if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8805         current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8806         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8807         current.u|=1;
8808         current.uu|=1;
8809       } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
8810     }
8811     is_ds[i]=ds;
8812     if(ds) {
8813       ds=0; // Skip delay slot, already allocated as part of branch
8814       // ...but we need to alloc it in case something jumps here
8815       if(i+1<slen) {
8816         current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
8817         current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
8818       }else{
8819         current.u=branch_unneeded_reg[i-1];
8820         current.uu=branch_unneeded_reg_upper[i-1];
8821       }
8822       current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8823       current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8824       if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8825       current.u|=1;
8826       current.uu|=1;
8827       struct regstat temp;
8828       memcpy(&temp,&current,sizeof(current));
8829       temp.wasdirty=temp.dirty;
8830       temp.was32=temp.is32;
8831       // TODO: Take into account unconditional branches, as below
8832       delayslot_alloc(&temp,i);
8833       memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
8834       regs[i].wasdirty=temp.wasdirty;
8835       regs[i].was32=temp.was32;
8836       regs[i].dirty=temp.dirty;
8837       regs[i].is32=temp.is32;
8838       regs[i].isconst=0;
8839       regs[i].wasconst=0;
8840       current.isconst=0;
8841       // Create entry (branch target) regmap
8842       for(hr=0;hr<HOST_REGS;hr++)
8843       {
8844         int r=temp.regmap[hr];
8845         if(r>=0) {
8846           if(r!=regmap_pre[i][hr]) {
8847             regs[i].regmap_entry[hr]=-1;
8848           }
8849           else
8850           {
8851             if(r<64){
8852               if((current.u>>r)&1) {
8853                 regs[i].regmap_entry[hr]=-1;
8854                 regs[i].regmap[hr]=-1;
8855                 //Don't clear regs in the delay slot as the branch might need them
8856                 //current.regmap[hr]=-1;
8857               }else
8858                 regs[i].regmap_entry[hr]=r;
8859             }
8860             else {
8861               if((current.uu>>(r&63))&1) {
8862                 regs[i].regmap_entry[hr]=-1;
8863                 regs[i].regmap[hr]=-1;
8864                 //Don't clear regs in the delay slot as the branch might need them
8865                 //current.regmap[hr]=-1;
8866               }else
8867                 regs[i].regmap_entry[hr]=r;
8868             }
8869           }
8870         } else {
8871           // First instruction expects CCREG to be allocated
8872           if(i==0&&hr==HOST_CCREG)
8873             regs[i].regmap_entry[hr]=CCREG;
8874           else
8875             regs[i].regmap_entry[hr]=-1;
8876         }
8877       }
8878     }
8879     else { // Not delay slot
8880       switch(itype[i]) {
8881         case UJUMP:
8882           //current.isconst=0; // DEBUG
8883           //current.wasconst=0; // DEBUG
8884           //regs[i].wasconst=0; // DEBUG
8885           clear_const(&current,rt1[i]);
8886           alloc_cc(&current,i);
8887           dirty_reg(&current,CCREG);
8888           if (rt1[i]==31) {
8889             alloc_reg(&current,i,31);
8890             dirty_reg(&current,31);
8891             //assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8892             //assert(rt1[i+1]!=rt1[i]);
8893             #ifdef REG_PREFETCH
8894             alloc_reg(&current,i,PTEMP);
8895             #endif
8896             //current.is32|=1LL<<rt1[i];
8897           }
8898           ooo[i]=1;
8899           delayslot_alloc(&current,i+1);
8900           //current.isconst=0; // DEBUG
8901           ds=1;
8902           //printf("i=%d, isconst=%x\n",i,current.isconst);
8903           break;
8904         case RJUMP:
8905           //current.isconst=0;
8906           //current.wasconst=0;
8907           //regs[i].wasconst=0;
8908           clear_const(&current,rs1[i]);
8909           clear_const(&current,rt1[i]);
8910           alloc_cc(&current,i);
8911           dirty_reg(&current,CCREG);
8912           if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
8913             alloc_reg(&current,i,rs1[i]);
8914             if (rt1[i]!=0) {
8915               alloc_reg(&current,i,rt1[i]);
8916               dirty_reg(&current,rt1[i]);
8917               assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
8918               assert(rt1[i+1]!=rt1[i]);
8919               #ifdef REG_PREFETCH
8920               alloc_reg(&current,i,PTEMP);
8921               #endif
8922             }
8923             #ifdef USE_MINI_HT
8924             if(rs1[i]==31) { // JALR
8925               alloc_reg(&current,i,RHASH);
8926               #ifndef HOST_IMM_ADDR32
8927               alloc_reg(&current,i,RHTBL);
8928               #endif
8929             }
8930             #endif
8931             delayslot_alloc(&current,i+1);
8932           } else {
8933             // The delay slot overwrites our source register,
8934             // allocate a temporary register to hold the old value.
8935             current.isconst=0;
8936             current.wasconst=0;
8937             regs[i].wasconst=0;
8938             delayslot_alloc(&current,i+1);
8939             current.isconst=0;
8940             alloc_reg(&current,i,RTEMP);
8941           }
8942           //current.isconst=0; // DEBUG
8943           ooo[i]=1;
8944           ds=1;
8945           break;
8946         case CJUMP:
8947           //current.isconst=0;
8948           //current.wasconst=0;
8949           //regs[i].wasconst=0;
8950           clear_const(&current,rs1[i]);
8951           clear_const(&current,rs2[i]);
8952           if((opcode[i]&0x3E)==4) // BEQ/BNE
8953           {
8954             alloc_cc(&current,i);
8955             dirty_reg(&current,CCREG);
8956             if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8957             if(rs2[i]) alloc_reg(&current,i,rs2[i]);
8958             if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8959             {
8960               if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8961               if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
8962             }
8963             if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
8964                (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
8965               // The delay slot overwrites one of our conditions.
8966               // Allocate the branch condition registers instead.
8967               current.isconst=0;
8968               current.wasconst=0;
8969               regs[i].wasconst=0;
8970               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8971               if(rs2[i]) alloc_reg(&current,i,rs2[i]);
8972               if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8973               {
8974                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8975                 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
8976               }
8977             }
8978             else
8979             {
8980               ooo[i]=1;
8981               delayslot_alloc(&current,i+1);
8982             }
8983           }
8984           else
8985           if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
8986           {
8987             alloc_cc(&current,i);
8988             dirty_reg(&current,CCREG);
8989             alloc_reg(&current,i,rs1[i]);
8990             if(!(current.is32>>rs1[i]&1))
8991             {
8992               alloc_reg64(&current,i,rs1[i]);
8993             }
8994             if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
8995               // The delay slot overwrites one of our conditions.
8996               // Allocate the branch condition registers instead.
8997               current.isconst=0;
8998               current.wasconst=0;
8999               regs[i].wasconst=0;
9000               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9001               if(!((current.is32>>rs1[i])&1))
9002               {
9003                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9004               }
9005             }
9006             else
9007             {
9008               ooo[i]=1;
9009               delayslot_alloc(&current,i+1);
9010             }
9011           }
9012           else
9013           // Don't alloc the delay slot yet because we might not execute it
9014           if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
9015           {
9016             current.isconst=0;
9017             current.wasconst=0;
9018             regs[i].wasconst=0;
9019             alloc_cc(&current,i);
9020             dirty_reg(&current,CCREG);
9021             alloc_reg(&current,i,rs1[i]);
9022             alloc_reg(&current,i,rs2[i]);
9023             if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9024             {
9025               alloc_reg64(&current,i,rs1[i]);
9026               alloc_reg64(&current,i,rs2[i]);
9027             }
9028           }
9029           else
9030           if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
9031           {
9032             current.isconst=0;
9033             current.wasconst=0;
9034             regs[i].wasconst=0;
9035             alloc_cc(&current,i);
9036             dirty_reg(&current,CCREG);
9037             alloc_reg(&current,i,rs1[i]);
9038             if(!(current.is32>>rs1[i]&1))
9039             {
9040               alloc_reg64(&current,i,rs1[i]);
9041             }
9042           }
9043           ds=1;
9044           //current.isconst=0;
9045           break;
9046         case SJUMP:
9047           //current.isconst=0;
9048           //current.wasconst=0;
9049           //regs[i].wasconst=0;
9050           clear_const(&current,rs1[i]);
9051           clear_const(&current,rt1[i]);
9052           //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
9053           if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
9054           {
9055             alloc_cc(&current,i);
9056             dirty_reg(&current,CCREG);
9057             alloc_reg(&current,i,rs1[i]);
9058             if(!(current.is32>>rs1[i]&1))
9059             {
9060               alloc_reg64(&current,i,rs1[i]);
9061             }
9062             if (rt1[i]==31) { // BLTZAL/BGEZAL
9063               alloc_reg(&current,i,31);
9064               dirty_reg(&current,31);
9065               //#ifdef REG_PREFETCH
9066               //alloc_reg(&current,i,PTEMP);
9067               //#endif
9068               //current.is32|=1LL<<rt1[i];
9069             }
9070             if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) // The delay slot overwrites the branch condition.
9071                ||(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))) { // DS touches $ra
9072               // Allocate the branch condition registers instead.
9073               current.isconst=0;
9074               current.wasconst=0;
9075               regs[i].wasconst=0;
9076               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9077               if(!((current.is32>>rs1[i])&1))
9078               {
9079                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9080               }
9081             }
9082             else
9083             {
9084               ooo[i]=1;
9085               delayslot_alloc(&current,i+1);
9086             }
9087           }
9088           else
9089           // Don't alloc the delay slot yet because we might not execute it
9090           if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
9091           {
9092             current.isconst=0;
9093             current.wasconst=0;
9094             regs[i].wasconst=0;
9095             alloc_cc(&current,i);
9096             dirty_reg(&current,CCREG);
9097             alloc_reg(&current,i,rs1[i]);
9098             if(!(current.is32>>rs1[i]&1))
9099             {
9100               alloc_reg64(&current,i,rs1[i]);
9101             }
9102           }
9103           ds=1;
9104           //current.isconst=0;
9105           break;
9106         case FJUMP:
9107           current.isconst=0;
9108           current.wasconst=0;
9109           regs[i].wasconst=0;
9110           if(likely[i]==0) // BC1F/BC1T
9111           {
9112             // TODO: Theoretically we can run out of registers here on x86.
9113             // The delay slot can allocate up to six, and we need to check
9114             // CSREG before executing the delay slot.  Possibly we can drop
9115             // the cycle count and then reload it after checking that the
9116             // FPU is in a usable state, or don't do out-of-order execution.
9117             alloc_cc(&current,i);
9118             dirty_reg(&current,CCREG);
9119             alloc_reg(&current,i,FSREG);
9120             alloc_reg(&current,i,CSREG);
9121             if(itype[i+1]==FCOMP) {
9122               // The delay slot overwrites the branch condition.
9123               // Allocate the branch condition registers instead.
9124               alloc_cc(&current,i);
9125               dirty_reg(&current,CCREG);
9126               alloc_reg(&current,i,CSREG);
9127               alloc_reg(&current,i,FSREG);
9128             }
9129             else {
9130               ooo[i]=1;
9131               delayslot_alloc(&current,i+1);
9132               alloc_reg(&current,i+1,CSREG);
9133             }
9134           }
9135           else
9136           // Don't alloc the delay slot yet because we might not execute it
9137           if(likely[i]) // BC1FL/BC1TL
9138           {
9139             alloc_cc(&current,i);
9140             dirty_reg(&current,CCREG);
9141             alloc_reg(&current,i,CSREG);
9142             alloc_reg(&current,i,FSREG);
9143           }
9144           ds=1;
9145           current.isconst=0;
9146           break;
9147         case IMM16:
9148           imm16_alloc(&current,i);
9149           break;
9150         case LOAD:
9151         case LOADLR:
9152           load_alloc(&current,i);
9153           break;
9154         case STORE:
9155         case STORELR:
9156           store_alloc(&current,i);
9157           break;
9158         case ALU:
9159           alu_alloc(&current,i);
9160           break;
9161         case SHIFT:
9162           shift_alloc(&current,i);
9163           break;
9164         case MULTDIV:
9165           multdiv_alloc(&current,i);
9166           break;
9167         case SHIFTIMM:
9168           shiftimm_alloc(&current,i);
9169           break;
9170         case MOV:
9171           mov_alloc(&current,i);
9172           break;
9173         case COP0:
9174           cop0_alloc(&current,i);
9175           break;
9176         case COP1:
9177         case COP2:
9178           cop1_alloc(&current,i);
9179           break;
9180         case C1LS:
9181           c1ls_alloc(&current,i);
9182           break;
9183         case C2LS:
9184           c2ls_alloc(&current,i);
9185           break;
9186         case C2OP:
9187           c2op_alloc(&current,i);
9188           break;
9189         case FCONV:
9190           fconv_alloc(&current,i);
9191           break;
9192         case FLOAT:
9193           float_alloc(&current,i);
9194           break;
9195         case FCOMP:
9196           fcomp_alloc(&current,i);
9197           break;
9198         case SYSCALL:
9199         case HLECALL:
9200         case INTCALL:
9201           syscall_alloc(&current,i);
9202           break;
9203         case SPAN:
9204           pagespan_alloc(&current,i);
9205           break;
9206       }
9207
9208       // Drop the upper half of registers that have become 32-bit
9209       current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
9210       if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9211         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9212         if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9213         current.uu|=1;
9214       } else {
9215         current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
9216         current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9217         if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9218         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9219         current.uu|=1;
9220       }
9221
9222       // Create entry (branch target) regmap
9223       for(hr=0;hr<HOST_REGS;hr++)
9224       {
9225         int r,or,er;
9226         r=current.regmap[hr];
9227         if(r>=0) {
9228           if(r!=regmap_pre[i][hr]) {
9229             // TODO: delay slot (?)
9230             or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9231             if(or<0||(r&63)>=TEMPREG){
9232               regs[i].regmap_entry[hr]=-1;
9233             }
9234             else
9235             {
9236               // Just move it to a different register
9237               regs[i].regmap_entry[hr]=r;
9238               // If it was dirty before, it's still dirty
9239               if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r&63);
9240             }
9241           }
9242           else
9243           {
9244             // Unneeded
9245             if(r==0){
9246               regs[i].regmap_entry[hr]=0;
9247             }
9248             else
9249             if(r<64){
9250               if((current.u>>r)&1) {
9251                 regs[i].regmap_entry[hr]=-1;
9252                 //regs[i].regmap[hr]=-1;
9253                 current.regmap[hr]=-1;
9254               }else
9255                 regs[i].regmap_entry[hr]=r;
9256             }
9257             else {
9258               if((current.uu>>(r&63))&1) {
9259                 regs[i].regmap_entry[hr]=-1;
9260                 //regs[i].regmap[hr]=-1;
9261                 current.regmap[hr]=-1;
9262               }else
9263                 regs[i].regmap_entry[hr]=r;
9264             }
9265           }
9266         } else {
9267           // Branches expect CCREG to be allocated at the target
9268           if(regmap_pre[i][hr]==CCREG)
9269             regs[i].regmap_entry[hr]=CCREG;
9270           else
9271             regs[i].regmap_entry[hr]=-1;
9272         }
9273       }
9274       memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9275     }
9276     /* Branch post-alloc */
9277     if(i>0)
9278     {
9279       current.was32=current.is32;
9280       current.wasdirty=current.dirty;
9281       switch(itype[i-1]) {
9282         case UJUMP:
9283           memcpy(&branch_regs[i-1],&current,sizeof(current));
9284           branch_regs[i-1].isconst=0;
9285           branch_regs[i-1].wasconst=0;
9286           branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9287           branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9288           alloc_cc(&branch_regs[i-1],i-1);
9289           dirty_reg(&branch_regs[i-1],CCREG);
9290           if(rt1[i-1]==31) { // JAL
9291             alloc_reg(&branch_regs[i-1],i-1,31);
9292             dirty_reg(&branch_regs[i-1],31);
9293             branch_regs[i-1].is32|=1LL<<31;
9294           }
9295           memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9296           memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9297           break;
9298         case RJUMP:
9299           memcpy(&branch_regs[i-1],&current,sizeof(current));
9300           branch_regs[i-1].isconst=0;
9301           branch_regs[i-1].wasconst=0;
9302           branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9303           branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9304           alloc_cc(&branch_regs[i-1],i-1);
9305           dirty_reg(&branch_regs[i-1],CCREG);
9306           alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
9307           if(rt1[i-1]!=0) { // JALR
9308             alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9309             dirty_reg(&branch_regs[i-1],rt1[i-1]);
9310             branch_regs[i-1].is32|=1LL<<rt1[i-1];
9311           }
9312           #ifdef USE_MINI_HT
9313           if(rs1[i-1]==31) { // JALR
9314             alloc_reg(&branch_regs[i-1],i-1,RHASH);
9315             #ifndef HOST_IMM_ADDR32
9316             alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9317             #endif
9318           }
9319           #endif
9320           memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9321           memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9322           break;
9323         case CJUMP:
9324           if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9325           {
9326             alloc_cc(&current,i-1);
9327             dirty_reg(&current,CCREG);
9328             if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9329                (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9330               // The delay slot overwrote one of our conditions
9331               // Delay slot goes after the test (in order)
9332               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9333               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9334               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9335               current.u|=1;
9336               current.uu|=1;
9337               delayslot_alloc(&current,i);
9338               current.isconst=0;
9339             }
9340             else
9341             {
9342               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9343               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9344               // Alloc the branch condition registers
9345               if(rs1[i-1]) alloc_reg(&current,i-1,rs1[i-1]);
9346               if(rs2[i-1]) alloc_reg(&current,i-1,rs2[i-1]);
9347               if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9348               {
9349                 if(rs1[i-1]) alloc_reg64(&current,i-1,rs1[i-1]);
9350                 if(rs2[i-1]) alloc_reg64(&current,i-1,rs2[i-1]);
9351               }
9352             }
9353             memcpy(&branch_regs[i-1],&current,sizeof(current));
9354             branch_regs[i-1].isconst=0;
9355             branch_regs[i-1].wasconst=0;
9356             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9357             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9358           }
9359           else
9360           if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9361           {
9362             alloc_cc(&current,i-1);
9363             dirty_reg(&current,CCREG);
9364             if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9365               // The delay slot overwrote the branch condition
9366               // Delay slot goes after the test (in order)
9367               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9368               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9369               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9370               current.u|=1;
9371               current.uu|=1;
9372               delayslot_alloc(&current,i);
9373               current.isconst=0;
9374             }
9375             else
9376             {
9377               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9378               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9379               // Alloc the branch condition register
9380               alloc_reg(&current,i-1,rs1[i-1]);
9381               if(!(current.is32>>rs1[i-1]&1))
9382               {
9383                 alloc_reg64(&current,i-1,rs1[i-1]);
9384               }
9385             }
9386             memcpy(&branch_regs[i-1],&current,sizeof(current));
9387             branch_regs[i-1].isconst=0;
9388             branch_regs[i-1].wasconst=0;
9389             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9390             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9391           }
9392           else
9393           // Alloc the delay slot in case the branch is taken
9394           if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9395           {
9396             memcpy(&branch_regs[i-1],&current,sizeof(current));
9397             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9398             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9399             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9400             alloc_cc(&branch_regs[i-1],i);
9401             dirty_reg(&branch_regs[i-1],CCREG);
9402             delayslot_alloc(&branch_regs[i-1],i);
9403             branch_regs[i-1].isconst=0;
9404             alloc_reg(&current,i,CCREG); // Not taken path
9405             dirty_reg(&current,CCREG);
9406             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9407           }
9408           else
9409           if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9410           {
9411             memcpy(&branch_regs[i-1],&current,sizeof(current));
9412             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9413             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9414             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9415             alloc_cc(&branch_regs[i-1],i);
9416             dirty_reg(&branch_regs[i-1],CCREG);
9417             delayslot_alloc(&branch_regs[i-1],i);
9418             branch_regs[i-1].isconst=0;
9419             alloc_reg(&current,i,CCREG); // Not taken path
9420             dirty_reg(&current,CCREG);
9421             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9422           }
9423           break;
9424         case SJUMP:
9425           //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9426           if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9427           {
9428             alloc_cc(&current,i-1);
9429             dirty_reg(&current,CCREG);
9430             if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9431               // The delay slot overwrote the branch condition
9432               // Delay slot goes after the test (in order)
9433               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9434               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9435               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9436               current.u|=1;
9437               current.uu|=1;
9438               delayslot_alloc(&current,i);
9439               current.isconst=0;
9440             }
9441             else
9442             {
9443               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9444               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9445               // Alloc the branch condition register
9446               alloc_reg(&current,i-1,rs1[i-1]);
9447               if(!(current.is32>>rs1[i-1]&1))
9448               {
9449                 alloc_reg64(&current,i-1,rs1[i-1]);
9450               }
9451             }
9452             memcpy(&branch_regs[i-1],&current,sizeof(current));
9453             branch_regs[i-1].isconst=0;
9454             branch_regs[i-1].wasconst=0;
9455             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9456             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9457           }
9458           else
9459           // Alloc the delay slot in case the branch is taken
9460           if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9461           {
9462             memcpy(&branch_regs[i-1],&current,sizeof(current));
9463             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9464             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9465             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9466             alloc_cc(&branch_regs[i-1],i);
9467             dirty_reg(&branch_regs[i-1],CCREG);
9468             delayslot_alloc(&branch_regs[i-1],i);
9469             branch_regs[i-1].isconst=0;
9470             alloc_reg(&current,i,CCREG); // Not taken path
9471             dirty_reg(&current,CCREG);
9472             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9473           }
9474           // FIXME: BLTZAL/BGEZAL
9475           if(opcode2[i-1]&0x10) { // BxxZAL
9476             alloc_reg(&branch_regs[i-1],i-1,31);
9477             dirty_reg(&branch_regs[i-1],31);
9478             branch_regs[i-1].is32|=1LL<<31;
9479           }
9480           break;
9481         case FJUMP:
9482           if(likely[i-1]==0) // BC1F/BC1T
9483           {
9484             alloc_cc(&current,i-1);
9485             dirty_reg(&current,CCREG);
9486             if(itype[i]==FCOMP) {
9487               // The delay slot overwrote the branch condition
9488               // Delay slot goes after the test (in order)
9489               delayslot_alloc(&current,i);
9490               current.isconst=0;
9491             }
9492             else
9493             {
9494               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9495               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9496               // Alloc the branch condition register
9497               alloc_reg(&current,i-1,FSREG);
9498             }
9499             memcpy(&branch_regs[i-1],&current,sizeof(current));
9500             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9501           }
9502           else // BC1FL/BC1TL
9503           {
9504             // Alloc the delay slot in case the branch is taken
9505             memcpy(&branch_regs[i-1],&current,sizeof(current));
9506             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9507             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9508             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9509             alloc_cc(&branch_regs[i-1],i);
9510             dirty_reg(&branch_regs[i-1],CCREG);
9511             delayslot_alloc(&branch_regs[i-1],i);
9512             branch_regs[i-1].isconst=0;
9513             alloc_reg(&current,i,CCREG); // Not taken path
9514             dirty_reg(&current,CCREG);
9515             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9516           }
9517           break;
9518       }
9519
9520       if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9521       {
9522         if(rt1[i-1]==31) // JAL/JALR
9523         {
9524           // Subroutine call will return here, don't alloc any registers
9525           current.is32=1;
9526           current.dirty=0;
9527           clear_all_regs(current.regmap);
9528           alloc_reg(&current,i,CCREG);
9529           dirty_reg(&current,CCREG);
9530         }
9531         else if(i+1<slen)
9532         {
9533           // Internal branch will jump here, match registers to caller
9534           current.is32=0x3FFFFFFFFLL;
9535           current.dirty=0;
9536           clear_all_regs(current.regmap);
9537           alloc_reg(&current,i,CCREG);
9538           dirty_reg(&current,CCREG);
9539           for(j=i-1;j>=0;j--)
9540           {
9541             if(ba[j]==start+i*4+4) {
9542               memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9543               current.is32=branch_regs[j].is32;
9544               current.dirty=branch_regs[j].dirty;
9545               break;
9546             }
9547           }
9548           while(j>=0) {
9549             if(ba[j]==start+i*4+4) {
9550               for(hr=0;hr<HOST_REGS;hr++) {
9551                 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9552                   current.regmap[hr]=-1;
9553                 }
9554                 current.is32&=branch_regs[j].is32;
9555                 current.dirty&=branch_regs[j].dirty;
9556               }
9557             }
9558             j--;
9559           }
9560         }
9561       }
9562     }
9563
9564     // Count cycles in between branches
9565     ccadj[i]=cc;
9566     if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
9567     {
9568       cc=0;
9569     }
9570 #ifdef PCSX
9571     else if(/*itype[i]==LOAD||*/itype[i]==STORE||itype[i]==C1LS) // load causes weird timing issues
9572     {
9573       cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
9574     }
9575     else if(itype[i]==C2LS)
9576     {
9577       cc+=4;
9578     }
9579 #endif
9580     else
9581     {
9582       cc++;
9583     }
9584
9585     flush_dirty_uppers(&current);
9586     if(!is_ds[i]) {
9587       regs[i].is32=current.is32;
9588       regs[i].dirty=current.dirty;
9589       regs[i].isconst=current.isconst;
9590       memcpy(constmap[i],current.constmap,sizeof(current.constmap));
9591     }
9592     for(hr=0;hr<HOST_REGS;hr++) {
9593       if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
9594         if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9595           regs[i].wasconst&=~(1<<hr);
9596         }
9597       }
9598     }
9599     if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9600   }
9601
9602   /* Pass 4 - Cull unused host registers */
9603
9604   uint64_t nr=0;
9605
9606   for (i=slen-1;i>=0;i--)
9607   {
9608     int hr;
9609     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9610     {
9611       if(ba[i]<start || ba[i]>=(start+slen*4))
9612       {
9613         // Branch out of this block, don't need anything
9614         nr=0;
9615       }
9616       else
9617       {
9618         // Internal branch
9619         // Need whatever matches the target
9620         nr=0;
9621         int t=(ba[i]-start)>>2;
9622         for(hr=0;hr<HOST_REGS;hr++)
9623         {
9624           if(regs[i].regmap_entry[hr]>=0) {
9625             if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9626           }
9627         }
9628       }
9629       // Conditional branch may need registers for following instructions
9630       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9631       {
9632         if(i<slen-2) {
9633           nr|=needed_reg[i+2];
9634           for(hr=0;hr<HOST_REGS;hr++)
9635           {
9636             if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9637             //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9638           }
9639         }
9640       }
9641       // Don't need stuff which is overwritten
9642       //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9643       //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9644       // Merge in delay slot
9645       for(hr=0;hr<HOST_REGS;hr++)
9646       {
9647         if(!likely[i]) {
9648           // These are overwritten unless the branch is "likely"
9649           // and the delay slot is nullified if not taken
9650           if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9651           if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9652         }
9653         if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9654         if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9655         if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9656         if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9657         if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9658         if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9659         if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9660         if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9661         if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9662           if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9663           if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9664         }
9665         if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9666           if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9667           if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9668         }
9669         if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
9670           if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9671           if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9672         }
9673       }
9674     }
9675     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
9676     {
9677       // SYSCALL instruction (software interrupt)
9678       nr=0;
9679     }
9680     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9681     {
9682       // ERET instruction (return from interrupt)
9683       nr=0;
9684     }
9685     else // Non-branch
9686     {
9687       if(i<slen-1) {
9688         for(hr=0;hr<HOST_REGS;hr++) {
9689           if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9690           if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9691           if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9692           if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9693         }
9694       }
9695     }
9696     for(hr=0;hr<HOST_REGS;hr++)
9697     {
9698       // Overwritten registers are not needed
9699       if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9700       if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9701       if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9702       // Source registers are needed
9703       if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9704       if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9705       if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9706       if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9707       if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9708       if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9709       if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9710       if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9711       if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9712         if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9713         if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9714       }
9715       if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
9716         if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9717         if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9718       }
9719       if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
9720         if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9721         if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9722       }
9723       // Don't store a register immediately after writing it,
9724       // may prevent dual-issue.
9725       // But do so if this is a branch target, otherwise we
9726       // might have to load the register before the branch.
9727       if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
9728         if((regmap_pre[i][hr]>0&&regmap_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
9729            (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
9730           if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9731           if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9732         }
9733         if((regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
9734            (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
9735           if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9736           if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9737         }
9738       }
9739     }
9740     // Cycle count is needed at branches.  Assume it is needed at the target too.
9741     if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
9742       if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9743       if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9744     }
9745     // Save it
9746     needed_reg[i]=nr;
9747
9748     // Deallocate unneeded registers
9749     for(hr=0;hr<HOST_REGS;hr++)
9750     {
9751       if(!((nr>>hr)&1)) {
9752         if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
9753         if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9754            (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9755            (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
9756         {
9757           if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9758           {
9759             if(likely[i]) {
9760               regs[i].regmap[hr]=-1;
9761               regs[i].isconst&=~(1<<hr);
9762               if(i<slen-2) {
9763                 regmap_pre[i+2][hr]=-1;
9764                 regs[i+2].wasconst&=~(1<<hr);
9765               }
9766             }
9767           }
9768         }
9769         if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9770         {
9771           int d1=0,d2=0,map=0,temp=0;
9772           if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
9773           {
9774             d1=dep1[i+1];
9775             d2=dep2[i+1];
9776           }
9777           if(using_tlb) {
9778             if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
9779                itype[i+1]==STORE || itype[i+1]==STORELR ||
9780                itype[i+1]==C1LS || itype[i+1]==C2LS)
9781             map=TLREG;
9782           } else
9783           if(itype[i+1]==STORE || itype[i+1]==STORELR ||
9784              (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
9785             map=INVCP;
9786           }
9787           if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
9788              itype[i+1]==C1LS || itype[i+1]==C2LS)
9789             temp=FTEMP;
9790           if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9791              (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9792              (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
9793              (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
9794              (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9795              regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
9796              (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
9797              regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
9798              regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
9799              regs[i].regmap[hr]!=map )
9800           {
9801             regs[i].regmap[hr]=-1;
9802             regs[i].isconst&=~(1<<hr);
9803             if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
9804                (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
9805                (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
9806                (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
9807                (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
9808                branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
9809                (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
9810                branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
9811                branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
9812                branch_regs[i].regmap[hr]!=map)
9813             {
9814               branch_regs[i].regmap[hr]=-1;
9815               branch_regs[i].regmap_entry[hr]=-1;
9816               if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9817               {
9818                 if(!likely[i]&&i<slen-2) {
9819                   regmap_pre[i+2][hr]=-1;
9820                   regs[i+2].wasconst&=~(1<<hr);
9821                 }
9822               }
9823             }
9824           }
9825         }
9826         else
9827         {
9828           // Non-branch
9829           if(i>0)
9830           {
9831             int d1=0,d2=0,map=-1,temp=-1;
9832             if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
9833             {
9834               d1=dep1[i];
9835               d2=dep2[i];
9836             }
9837             if(using_tlb) {
9838               if(itype[i]==LOAD || itype[i]==LOADLR ||
9839                  itype[i]==STORE || itype[i]==STORELR ||
9840                  itype[i]==C1LS || itype[i]==C2LS)
9841               map=TLREG;
9842             } else if(itype[i]==STORE || itype[i]==STORELR ||
9843                       (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
9844               map=INVCP;
9845             }
9846             if(itype[i]==LOADLR || itype[i]==STORELR ||
9847                itype[i]==C1LS || itype[i]==C2LS)
9848               temp=FTEMP;
9849             if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9850                (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
9851                (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9852                regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
9853                (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
9854                (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
9855             {
9856               if(i<slen-1&&!is_ds[i]) {
9857                 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
9858                 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
9859                 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
9860                 {
9861                   printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
9862                   assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
9863                 }
9864                 regmap_pre[i+1][hr]=-1;
9865                 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
9866                 regs[i+1].wasconst&=~(1<<hr);
9867               }
9868               regs[i].regmap[hr]=-1;
9869               regs[i].isconst&=~(1<<hr);
9870             }
9871           }
9872         }
9873       }
9874     }
9875   }
9876
9877   /* Pass 5 - Pre-allocate registers */
9878
9879   // If a register is allocated during a loop, try to allocate it for the
9880   // entire loop, if possible.  This avoids loading/storing registers
9881   // inside of the loop.
9882
9883   signed char f_regmap[HOST_REGS];
9884   clear_all_regs(f_regmap);
9885   for(i=0;i<slen-1;i++)
9886   {
9887     if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9888     {
9889       if(ba[i]>=start && ba[i]<(start+i*4))
9890       if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
9891       ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
9892       ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
9893       ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
9894       ||itype[i+1]==FCOMP||itype[i+1]==FCONV
9895       ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
9896       {
9897         int t=(ba[i]-start)>>2;
9898         if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
9899         if(t<2||(itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||rt1[t-2]!=31) // call/ret assumes no registers allocated
9900         for(hr=0;hr<HOST_REGS;hr++)
9901         {
9902           if(regs[i].regmap[hr]>64) {
9903             if(!((regs[i].dirty>>hr)&1))
9904               f_regmap[hr]=regs[i].regmap[hr];
9905             else f_regmap[hr]=-1;
9906           }
9907           else if(regs[i].regmap[hr]>=0) {
9908             if(f_regmap[hr]!=regs[i].regmap[hr]) {
9909               // dealloc old register
9910               int n;
9911               for(n=0;n<HOST_REGS;n++)
9912               {
9913                 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
9914               }
9915               // and alloc new one
9916               f_regmap[hr]=regs[i].regmap[hr];
9917             }
9918           }
9919           if(branch_regs[i].regmap[hr]>64) {
9920             if(!((branch_regs[i].dirty>>hr)&1))
9921               f_regmap[hr]=branch_regs[i].regmap[hr];
9922             else f_regmap[hr]=-1;
9923           }
9924           else if(branch_regs[i].regmap[hr]>=0) {
9925             if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
9926               // dealloc old register
9927               int n;
9928               for(n=0;n<HOST_REGS;n++)
9929               {
9930                 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
9931               }
9932               // and alloc new one
9933               f_regmap[hr]=branch_regs[i].regmap[hr];
9934             }
9935           }
9936           if(ooo[i]) {
9937             if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
9938               f_regmap[hr]=branch_regs[i].regmap[hr];
9939           }else{
9940             if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
9941               f_regmap[hr]=branch_regs[i].regmap[hr];
9942           }
9943           // Avoid dirty->clean transition
9944           #ifdef DESTRUCTIVE_WRITEBACK
9945           if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
9946           #endif
9947           // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
9948           // case above, however it's always a good idea.  We can't hoist the
9949           // load if the register was already allocated, so there's no point
9950           // wasting time analyzing most of these cases.  It only "succeeds"
9951           // when the mapping was different and the load can be replaced with
9952           // a mov, which is of negligible benefit.  So such cases are
9953           // skipped below.
9954           if(f_regmap[hr]>0) {
9955             if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
9956               int r=f_regmap[hr];
9957               for(j=t;j<=i;j++)
9958               {
9959                 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9960                 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
9961                 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
9962                 if(r>63) {
9963                   // NB This can exclude the case where the upper-half
9964                   // register is lower numbered than the lower-half
9965                   // register.  Not sure if it's worth fixing...
9966                   if(get_reg(regs[j].regmap,r&63)<0) break;
9967                   if(get_reg(regs[j].regmap_entry,r&63)<0) break;
9968                   if(regs[j].is32&(1LL<<(r&63))) break;
9969                 }
9970                 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
9971                   //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9972                   int k;
9973                   if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
9974                     if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
9975                     if(r>63) {
9976                       if(get_reg(regs[i].regmap,r&63)<0) break;
9977                       if(get_reg(branch_regs[i].regmap,r&63)<0) break;
9978                     }
9979                     k=i;
9980                     while(k>1&&regs[k-1].regmap[hr]==-1) {
9981                       if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
9982                         //printf("no free regs for store %x\n",start+(k-1)*4);
9983                         break;
9984                       }
9985                       if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
9986                         //printf("no-match due to different register\n");
9987                         break;
9988                       }
9989                       if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
9990                         //printf("no-match due to branch\n");
9991                         break;
9992                       }
9993                       // call/ret fast path assumes no registers allocated
9994                       if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)&&rt1[k-3]==31) {
9995                         break;
9996                       }
9997                       if(r>63) {
9998                         // NB This can exclude the case where the upper-half
9999                         // register is lower numbered than the lower-half
10000                         // register.  Not sure if it's worth fixing...
10001                         if(get_reg(regs[k-1].regmap,r&63)<0) break;
10002                         if(regs[k-1].is32&(1LL<<(r&63))) break;
10003                       }
10004                       k--;
10005                     }
10006                     if(i<slen-1) {
10007                       if((regs[k].is32&(1LL<<f_regmap[hr]))!=
10008                         (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
10009                         //printf("bad match after branch\n");
10010                         break;
10011                       }
10012                     }
10013                     if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
10014                       //printf("Extend r%d, %x ->\n",hr,start+k*4);
10015                       while(k<i) {
10016                         regs[k].regmap_entry[hr]=f_regmap[hr];
10017                         regs[k].regmap[hr]=f_regmap[hr];
10018                         regmap_pre[k+1][hr]=f_regmap[hr];
10019                         regs[k].wasdirty&=~(1<<hr);
10020                         regs[k].dirty&=~(1<<hr);
10021                         regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
10022                         regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
10023                         regs[k].wasconst&=~(1<<hr);
10024                         regs[k].isconst&=~(1<<hr);
10025                         k++;
10026                       }
10027                     }
10028                     else {
10029                       //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
10030                       break;
10031                     }
10032                     assert(regs[i-1].regmap[hr]==f_regmap[hr]);
10033                     if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
10034                       //printf("OK fill %x (r%d)\n",start+i*4,hr);
10035                       regs[i].regmap_entry[hr]=f_regmap[hr];
10036                       regs[i].regmap[hr]=f_regmap[hr];
10037                       regs[i].wasdirty&=~(1<<hr);
10038                       regs[i].dirty&=~(1<<hr);
10039                       regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
10040                       regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
10041                       regs[i].wasconst&=~(1<<hr);
10042                       regs[i].isconst&=~(1<<hr);
10043                       branch_regs[i].regmap_entry[hr]=f_regmap[hr];
10044                       branch_regs[i].wasdirty&=~(1<<hr);
10045                       branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
10046                       branch_regs[i].regmap[hr]=f_regmap[hr];
10047                       branch_regs[i].dirty&=~(1<<hr);
10048                       branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
10049                       branch_regs[i].wasconst&=~(1<<hr);
10050                       branch_regs[i].isconst&=~(1<<hr);
10051                       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
10052                         regmap_pre[i+2][hr]=f_regmap[hr];
10053                         regs[i+2].wasdirty&=~(1<<hr);
10054                         regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
10055                         assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
10056                           (regs[i+2].was32&(1LL<<f_regmap[hr])));
10057                       }
10058                     }
10059                   }
10060                   for(k=t;k<j;k++) {
10061                     // Alloc register clean at beginning of loop,
10062                     // but may dirty it in pass 6
10063                     regs[k].regmap_entry[hr]=f_regmap[hr];
10064                     regs[k].regmap[hr]=f_regmap[hr];
10065                     regs[k].dirty&=~(1<<hr);
10066                     regs[k].wasconst&=~(1<<hr);
10067                     regs[k].isconst&=~(1<<hr);
10068                     if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) {
10069                       branch_regs[k].regmap_entry[hr]=f_regmap[hr];
10070                       branch_regs[k].regmap[hr]=f_regmap[hr];
10071                       branch_regs[k].dirty&=~(1<<hr);
10072                       branch_regs[k].wasconst&=~(1<<hr);
10073                       branch_regs[k].isconst&=~(1<<hr);
10074                       if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
10075                         regmap_pre[k+2][hr]=f_regmap[hr];
10076                         regs[k+2].wasdirty&=~(1<<hr);
10077                         assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))==
10078                           (regs[k+2].was32&(1LL<<f_regmap[hr])));
10079                       }
10080                     }
10081                     else
10082                     {
10083                       regmap_pre[k+1][hr]=f_regmap[hr];
10084                       regs[k+1].wasdirty&=~(1<<hr);
10085                     }
10086                   }
10087                   if(regs[j].regmap[hr]==f_regmap[hr])
10088                     regs[j].regmap_entry[hr]=f_regmap[hr];
10089                   break;
10090                 }
10091                 if(j==i) break;
10092                 if(regs[j].regmap[hr]>=0)
10093                   break;
10094                 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
10095                   //printf("no-match due to different register\n");
10096                   break;
10097                 }
10098                 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
10099                   //printf("32/64 mismatch %x %d\n",start+j*4,hr);
10100                   break;
10101                 }
10102                 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10103                 {
10104                   // Stop on unconditional branch
10105                   break;
10106                 }
10107                 if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
10108                 {
10109                   if(ooo[j]) {
10110                     if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
10111                       break;
10112                   }else{
10113                     if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
10114                       break;
10115                   }
10116                   if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
10117                     //printf("no-match due to different register (branch)\n");
10118                     break;
10119                   }
10120                 }
10121                 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10122                   //printf("No free regs for store %x\n",start+j*4);
10123                   break;
10124                 }
10125                 if(f_regmap[hr]>=64) {
10126                   if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
10127                     break;
10128                   }
10129                   else
10130                   {
10131                     if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
10132                       break;
10133                     }
10134                   }
10135                 }
10136               }
10137             }
10138           }
10139         }
10140       }
10141     }else{
10142       // Non branch or undetermined branch target
10143       for(hr=0;hr<HOST_REGS;hr++)
10144       {
10145         if(hr!=EXCLUDE_REG) {
10146           if(regs[i].regmap[hr]>64) {
10147             if(!((regs[i].dirty>>hr)&1))
10148               f_regmap[hr]=regs[i].regmap[hr];
10149           }
10150           else if(regs[i].regmap[hr]>=0) {
10151             if(f_regmap[hr]!=regs[i].regmap[hr]) {
10152               // dealloc old register
10153               int n;
10154               for(n=0;n<HOST_REGS;n++)
10155               {
10156                 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10157               }
10158               // and alloc new one
10159               f_regmap[hr]=regs[i].regmap[hr];
10160             }
10161           }
10162         }
10163       }
10164       // Try to restore cycle count at branch targets
10165       if(bt[i]) {
10166         for(j=i;j<slen-1;j++) {
10167           if(regs[j].regmap[HOST_CCREG]!=-1) break;
10168           if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10169             //printf("no free regs for store %x\n",start+j*4);
10170             break;
10171           }
10172         }
10173         if(regs[j].regmap[HOST_CCREG]==CCREG) {
10174           int k=i;
10175           //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
10176           while(k<j) {
10177             regs[k].regmap_entry[HOST_CCREG]=CCREG;
10178             regs[k].regmap[HOST_CCREG]=CCREG;
10179             regmap_pre[k+1][HOST_CCREG]=CCREG;
10180             regs[k+1].wasdirty|=1<<HOST_CCREG;
10181             regs[k].dirty|=1<<HOST_CCREG;
10182             regs[k].wasconst&=~(1<<HOST_CCREG);
10183             regs[k].isconst&=~(1<<HOST_CCREG);
10184             k++;
10185           }
10186           regs[j].regmap_entry[HOST_CCREG]=CCREG;
10187         }
10188         // Work backwards from the branch target
10189         if(j>i&&f_regmap[HOST_CCREG]==CCREG)
10190         {
10191           //printf("Extend backwards\n");
10192           int k;
10193           k=i;
10194           while(regs[k-1].regmap[HOST_CCREG]==-1) {
10195             if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10196               //printf("no free regs for store %x\n",start+(k-1)*4);
10197               break;
10198             }
10199             k--;
10200           }
10201           if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
10202             //printf("Extend CC, %x ->\n",start+k*4);
10203             while(k<=i) {
10204               regs[k].regmap_entry[HOST_CCREG]=CCREG;
10205               regs[k].regmap[HOST_CCREG]=CCREG;
10206               regmap_pre[k+1][HOST_CCREG]=CCREG;
10207               regs[k+1].wasdirty|=1<<HOST_CCREG;
10208               regs[k].dirty|=1<<HOST_CCREG;
10209               regs[k].wasconst&=~(1<<HOST_CCREG);
10210               regs[k].isconst&=~(1<<HOST_CCREG);
10211               k++;
10212             }
10213           }
10214           else {
10215             //printf("Fail Extend CC, %x ->\n",start+k*4);
10216           }
10217         }
10218       }
10219       if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
10220          itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
10221          itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
10222          itype[i]!=FCONV&&itype[i]!=FCOMP)
10223       {
10224         memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
10225       }
10226     }
10227   }
10228
10229   // Cache memory offset or tlb map pointer if a register is available
10230   #ifndef HOST_IMM_ADDR32
10231   #ifndef RAM_OFFSET
10232   if(using_tlb)
10233   #endif
10234   {
10235     int earliest_available[HOST_REGS];
10236     int loop_start[HOST_REGS];
10237     int score[HOST_REGS];
10238     int end[HOST_REGS];
10239     int reg=using_tlb?MMREG:ROREG;
10240
10241     // Init
10242     for(hr=0;hr<HOST_REGS;hr++) {
10243       score[hr]=0;earliest_available[hr]=0;
10244       loop_start[hr]=MAXBLOCK;
10245     }
10246     for(i=0;i<slen-1;i++)
10247     {
10248       // Can't do anything if no registers are available
10249       if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i]) {
10250         for(hr=0;hr<HOST_REGS;hr++) {
10251           score[hr]=0;earliest_available[hr]=i+1;
10252           loop_start[hr]=MAXBLOCK;
10253         }
10254       }
10255       if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10256         if(!ooo[i]) {
10257           if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) {
10258             for(hr=0;hr<HOST_REGS;hr++) {
10259               score[hr]=0;earliest_available[hr]=i+1;
10260               loop_start[hr]=MAXBLOCK;
10261             }
10262           }
10263         }else{
10264           if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) {
10265             for(hr=0;hr<HOST_REGS;hr++) {
10266               score[hr]=0;earliest_available[hr]=i+1;
10267               loop_start[hr]=MAXBLOCK;
10268             }
10269           }
10270         }
10271       }
10272       // Mark unavailable registers
10273       for(hr=0;hr<HOST_REGS;hr++) {
10274         if(regs[i].regmap[hr]>=0) {
10275           score[hr]=0;earliest_available[hr]=i+1;
10276           loop_start[hr]=MAXBLOCK;
10277         }
10278         if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10279           if(branch_regs[i].regmap[hr]>=0) {
10280             score[hr]=0;earliest_available[hr]=i+2;
10281             loop_start[hr]=MAXBLOCK;
10282           }
10283         }
10284       }
10285       // No register allocations after unconditional jumps
10286       if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10287       {
10288         for(hr=0;hr<HOST_REGS;hr++) {
10289           score[hr]=0;earliest_available[hr]=i+2;
10290           loop_start[hr]=MAXBLOCK;
10291         }
10292         i++; // Skip delay slot too
10293         //printf("skip delay slot: %x\n",start+i*4);
10294       }
10295       else
10296       // Possible match
10297       if(itype[i]==LOAD||itype[i]==LOADLR||
10298          itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) {
10299         for(hr=0;hr<HOST_REGS;hr++) {
10300           if(hr!=EXCLUDE_REG) {
10301             end[hr]=i-1;
10302             for(j=i;j<slen-1;j++) {
10303               if(regs[j].regmap[hr]>=0) break;
10304               if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10305                 if(branch_regs[j].regmap[hr]>=0) break;
10306                 if(ooo[j]) {
10307                   if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) break;
10308                 }else{
10309                   if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) break;
10310                 }
10311               }
10312               else if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) break;
10313               if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10314                 int t=(ba[j]-start)>>2;
10315                 if(t<j&&t>=earliest_available[hr]) {
10316                   if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) { // call/ret assumes no registers allocated
10317                     // Score a point for hoisting loop invariant
10318                     if(t<loop_start[hr]) loop_start[hr]=t;
10319                     //printf("set loop_start: i=%x j=%x (%x)\n",start+i*4,start+j*4,start+t*4);
10320                     score[hr]++;
10321                     end[hr]=j;
10322                   }
10323                 }
10324                 else if(t<j) {
10325                   if(regs[t].regmap[hr]==reg) {
10326                     // Score a point if the branch target matches this register
10327                     score[hr]++;
10328                     end[hr]=j;
10329                   }
10330                 }
10331                 if(itype[j+1]==LOAD||itype[j+1]==LOADLR||
10332                    itype[j+1]==STORE||itype[j+1]==STORELR||itype[j+1]==C1LS) {
10333                   score[hr]++;
10334                   end[hr]=j;
10335                 }
10336               }
10337               if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10338               {
10339                 // Stop on unconditional branch
10340                 break;
10341               }
10342               else
10343               if(itype[j]==LOAD||itype[j]==LOADLR||
10344                  itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS) {
10345                 score[hr]++;
10346                 end[hr]=j;
10347               }
10348             }
10349           }
10350         }
10351         // Find highest score and allocate that register
10352         int maxscore=0;
10353         for(hr=0;hr<HOST_REGS;hr++) {
10354           if(hr!=EXCLUDE_REG) {
10355             if(score[hr]>score[maxscore]) {
10356               maxscore=hr;
10357               //printf("highest score: %d %d (%x->%x)\n",score[hr],hr,start+i*4,start+end[hr]*4);
10358             }
10359           }
10360         }
10361         if(score[maxscore]>1)
10362         {
10363           if(i<loop_start[maxscore]) loop_start[maxscore]=i;
10364           for(j=loop_start[maxscore];j<slen&&j<=end[maxscore];j++) {
10365             //if(regs[j].regmap[maxscore]>=0) {printf("oops: %x %x was %d=%d\n",loop_start[maxscore]*4+start,j*4+start,maxscore,regs[j].regmap[maxscore]);}
10366             assert(regs[j].regmap[maxscore]<0);
10367             if(j>loop_start[maxscore]) regs[j].regmap_entry[maxscore]=reg;
10368             regs[j].regmap[maxscore]=reg;
10369             regs[j].dirty&=~(1<<maxscore);
10370             regs[j].wasconst&=~(1<<maxscore);
10371             regs[j].isconst&=~(1<<maxscore);
10372             if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10373               branch_regs[j].regmap[maxscore]=reg;
10374               branch_regs[j].wasdirty&=~(1<<maxscore);
10375               branch_regs[j].dirty&=~(1<<maxscore);
10376               branch_regs[j].wasconst&=~(1<<maxscore);
10377               branch_regs[j].isconst&=~(1<<maxscore);
10378               if(itype[j]!=RJUMP&&itype[j]!=UJUMP&&(source[j]>>16)!=0x1000) {
10379                 regmap_pre[j+2][maxscore]=reg;
10380                 regs[j+2].wasdirty&=~(1<<maxscore);
10381               }
10382               // loop optimization (loop_preload)
10383               int t=(ba[j]-start)>>2;
10384               if(t==loop_start[maxscore]) {
10385                 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) // call/ret assumes no registers allocated
10386                   regs[t].regmap_entry[maxscore]=reg;
10387               }
10388             }
10389             else
10390             {
10391               if(j<1||(itype[j-1]!=RJUMP&&itype[j-1]!=UJUMP&&itype[j-1]!=CJUMP&&itype[j-1]!=SJUMP&&itype[j-1]!=FJUMP)) {
10392                 regmap_pre[j+1][maxscore]=reg;
10393                 regs[j+1].wasdirty&=~(1<<maxscore);
10394               }
10395             }
10396           }
10397           i=j-1;
10398           if(itype[j-1]==RJUMP||itype[j-1]==UJUMP||itype[j-1]==CJUMP||itype[j-1]==SJUMP||itype[j-1]==FJUMP) i++; // skip delay slot
10399           for(hr=0;hr<HOST_REGS;hr++) {
10400             score[hr]=0;earliest_available[hr]=i+i;
10401             loop_start[hr]=MAXBLOCK;
10402           }
10403         }
10404       }
10405     }
10406   }
10407   #endif
10408
10409   // This allocates registers (if possible) one instruction prior
10410   // to use, which can avoid a load-use penalty on certain CPUs.
10411   for(i=0;i<slen-1;i++)
10412   {
10413     if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10414     {
10415       if(!bt[i+1])
10416       {
10417         if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
10418            ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
10419         {
10420           if(rs1[i+1]) {
10421             if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10422             {
10423               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10424               {
10425                 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10426                 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10427                 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10428                 regs[i].isconst&=~(1<<hr);
10429                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10430                 constmap[i][hr]=constmap[i+1][hr];
10431                 regs[i+1].wasdirty&=~(1<<hr);
10432                 regs[i].dirty&=~(1<<hr);
10433               }
10434             }
10435           }
10436           if(rs2[i+1]) {
10437             if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10438             {
10439               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10440               {
10441                 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10442                 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10443                 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10444                 regs[i].isconst&=~(1<<hr);
10445                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10446                 constmap[i][hr]=constmap[i+1][hr];
10447                 regs[i+1].wasdirty&=~(1<<hr);
10448                 regs[i].dirty&=~(1<<hr);
10449               }
10450             }
10451           }
10452           // Preload target address for load instruction (non-constant)
10453           if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10454             if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10455             {
10456               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10457               {
10458                 regs[i].regmap[hr]=rs1[i+1];
10459                 regmap_pre[i+1][hr]=rs1[i+1];
10460                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10461                 regs[i].isconst&=~(1<<hr);
10462                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10463                 constmap[i][hr]=constmap[i+1][hr];
10464                 regs[i+1].wasdirty&=~(1<<hr);
10465                 regs[i].dirty&=~(1<<hr);
10466               }
10467             }
10468           }
10469           // Load source into target register
10470           if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10471             if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10472             {
10473               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10474               {
10475                 regs[i].regmap[hr]=rs1[i+1];
10476                 regmap_pre[i+1][hr]=rs1[i+1];
10477                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10478                 regs[i].isconst&=~(1<<hr);
10479                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10480                 constmap[i][hr]=constmap[i+1][hr];
10481                 regs[i+1].wasdirty&=~(1<<hr);
10482                 regs[i].dirty&=~(1<<hr);
10483               }
10484             }
10485           }
10486           // Preload map address
10487           #ifndef HOST_IMM_ADDR32
10488           if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
10489             hr=get_reg(regs[i+1].regmap,TLREG);
10490             if(hr>=0) {
10491               int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10492               if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10493                 int nr;
10494                 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10495                 {
10496                   regs[i].regmap[hr]=MGEN1+((i+1)&1);
10497                   regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10498                   regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10499                   regs[i].isconst&=~(1<<hr);
10500                   regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10501                   constmap[i][hr]=constmap[i+1][hr];
10502                   regs[i+1].wasdirty&=~(1<<hr);
10503                   regs[i].dirty&=~(1<<hr);
10504                 }
10505                 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10506                 {
10507                   // move it to another register
10508                   regs[i+1].regmap[hr]=-1;
10509                   regmap_pre[i+2][hr]=-1;
10510                   regs[i+1].regmap[nr]=TLREG;
10511                   regmap_pre[i+2][nr]=TLREG;
10512                   regs[i].regmap[nr]=MGEN1+((i+1)&1);
10513                   regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10514                   regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10515                   regs[i].isconst&=~(1<<nr);
10516                   regs[i+1].isconst&=~(1<<nr);
10517                   regs[i].dirty&=~(1<<nr);
10518                   regs[i+1].wasdirty&=~(1<<nr);
10519                   regs[i+1].dirty&=~(1<<nr);
10520                   regs[i+2].wasdirty&=~(1<<nr);
10521                 }
10522               }
10523             }
10524           }
10525           #endif
10526           // Address for store instruction (non-constant)
10527           if(itype[i+1]==STORE||itype[i+1]==STORELR
10528              ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
10529             if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10530               hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10531               if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10532               else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10533               assert(hr>=0);
10534               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10535               {
10536                 regs[i].regmap[hr]=rs1[i+1];
10537                 regmap_pre[i+1][hr]=rs1[i+1];
10538                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10539                 regs[i].isconst&=~(1<<hr);
10540                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10541                 constmap[i][hr]=constmap[i+1][hr];
10542                 regs[i+1].wasdirty&=~(1<<hr);
10543                 regs[i].dirty&=~(1<<hr);
10544               }
10545             }
10546           }
10547           if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
10548             if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10549               int nr;
10550               hr=get_reg(regs[i+1].regmap,FTEMP);
10551               assert(hr>=0);
10552               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10553               {
10554                 regs[i].regmap[hr]=rs1[i+1];
10555                 regmap_pre[i+1][hr]=rs1[i+1];
10556                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10557                 regs[i].isconst&=~(1<<hr);
10558                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10559                 constmap[i][hr]=constmap[i+1][hr];
10560                 regs[i+1].wasdirty&=~(1<<hr);
10561                 regs[i].dirty&=~(1<<hr);
10562               }
10563               else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10564               {
10565                 // move it to another register
10566                 regs[i+1].regmap[hr]=-1;
10567                 regmap_pre[i+2][hr]=-1;
10568                 regs[i+1].regmap[nr]=FTEMP;
10569                 regmap_pre[i+2][nr]=FTEMP;
10570                 regs[i].regmap[nr]=rs1[i+1];
10571                 regmap_pre[i+1][nr]=rs1[i+1];
10572                 regs[i+1].regmap_entry[nr]=rs1[i+1];
10573                 regs[i].isconst&=~(1<<nr);
10574                 regs[i+1].isconst&=~(1<<nr);
10575                 regs[i].dirty&=~(1<<nr);
10576                 regs[i+1].wasdirty&=~(1<<nr);
10577                 regs[i+1].dirty&=~(1<<nr);
10578                 regs[i+2].wasdirty&=~(1<<nr);
10579               }
10580             }
10581           }
10582           if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
10583             if(itype[i+1]==LOAD)
10584               hr=get_reg(regs[i+1].regmap,rt1[i+1]);
10585             if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
10586               hr=get_reg(regs[i+1].regmap,FTEMP);
10587             if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
10588               hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10589               if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10590             }
10591             if(hr>=0&&regs[i].regmap[hr]<0) {
10592               int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10593               if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10594                 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10595                 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10596                 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10597                 regs[i].isconst&=~(1<<hr);
10598                 regs[i+1].wasdirty&=~(1<<hr);
10599                 regs[i].dirty&=~(1<<hr);
10600               }
10601             }
10602           }
10603         }
10604       }
10605     }
10606   }
10607
10608   /* Pass 6 - Optimize clean/dirty state */
10609   clean_registers(0,slen-1,1);
10610
10611   /* Pass 7 - Identify 32-bit registers */
10612 #ifndef FORCE32
10613   provisional_r32();
10614
10615   u_int r32=0;
10616
10617   for (i=slen-1;i>=0;i--)
10618   {
10619     int hr;
10620     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10621     {
10622       if(ba[i]<start || ba[i]>=(start+slen*4))
10623       {
10624         // Branch out of this block, don't need anything
10625         r32=0;
10626       }
10627       else
10628       {
10629         // Internal branch
10630         // Need whatever matches the target
10631         // (and doesn't get overwritten by the delay slot instruction)
10632         r32=0;
10633         int t=(ba[i]-start)>>2;
10634         if(ba[i]>start+i*4) {
10635           // Forward branch
10636           if(!(requires_32bit[t]&~regs[i].was32))
10637             r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10638         }else{
10639           // Backward branch
10640           //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10641           //  r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10642           if(!(pr32[t]&~regs[i].was32))
10643             r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10644         }
10645       }
10646       // Conditional branch may need registers for following instructions
10647       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10648       {
10649         if(i<slen-2) {
10650           r32|=requires_32bit[i+2];
10651           r32&=regs[i].was32;
10652           // Mark this address as a branch target since it may be called
10653           // upon return from interrupt
10654           bt[i+2]=1;
10655         }
10656       }
10657       // Merge in delay slot
10658       if(!likely[i]) {
10659         // These are overwritten unless the branch is "likely"
10660         // and the delay slot is nullified if not taken
10661         r32&=~(1LL<<rt1[i+1]);
10662         r32&=~(1LL<<rt2[i+1]);
10663       }
10664       // Assume these are needed (delay slot)
10665       if(us1[i+1]>0)
10666       {
10667         if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10668       }
10669       if(us2[i+1]>0)
10670       {
10671         if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10672       }
10673       if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10674       {
10675         if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10676       }
10677       if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10678       {
10679         if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10680       }
10681     }
10682     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
10683     {
10684       // SYSCALL instruction (software interrupt)
10685       r32=0;
10686     }
10687     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10688     {
10689       // ERET instruction (return from interrupt)
10690       r32=0;
10691     }
10692     // Check 32 bits
10693     r32&=~(1LL<<rt1[i]);
10694     r32&=~(1LL<<rt2[i]);
10695     if(us1[i]>0)
10696     {
10697       if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10698     }
10699     if(us2[i]>0)
10700     {
10701       if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10702     }
10703     if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
10704     {
10705       if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
10706     }
10707     if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
10708     {
10709       if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
10710     }
10711     requires_32bit[i]=r32;
10712
10713     // Dirty registers which are 32-bit, require 32-bit input
10714     // as they will be written as 32-bit values
10715     for(hr=0;hr<HOST_REGS;hr++)
10716     {
10717       if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
10718         if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
10719           if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
10720           requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
10721         }
10722       }
10723     }
10724     //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
10725   }
10726 #else
10727   for (i=slen-1;i>=0;i--)
10728   {
10729     if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10730     {
10731       // Conditional branch
10732       if((source[i]>>16)!=0x1000&&i<slen-2) {
10733         // Mark this address as a branch target since it may be called
10734         // upon return from interrupt
10735         bt[i+2]=1;
10736       }
10737     }
10738   }
10739 #endif
10740
10741   if(itype[slen-1]==SPAN) {
10742     bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
10743   }
10744
10745   /* Debug/disassembly */
10746   if((void*)assem_debug==(void*)printf)
10747   for(i=0;i<slen;i++)
10748   {
10749     printf("U:");
10750     int r;
10751     for(r=1;r<=CCREG;r++) {
10752       if((unneeded_reg[i]>>r)&1) {
10753         if(r==HIREG) printf(" HI");
10754         else if(r==LOREG) printf(" LO");
10755         else printf(" r%d",r);
10756       }
10757     }
10758 #ifndef FORCE32
10759     printf(" UU:");
10760     for(r=1;r<=CCREG;r++) {
10761       if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
10762         if(r==HIREG) printf(" HI");
10763         else if(r==LOREG) printf(" LO");
10764         else printf(" r%d",r);
10765       }
10766     }
10767     printf(" 32:");
10768     for(r=0;r<=CCREG;r++) {
10769       //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10770       if((regs[i].was32>>r)&1) {
10771         if(r==CCREG) printf(" CC");
10772         else if(r==HIREG) printf(" HI");
10773         else if(r==LOREG) printf(" LO");
10774         else printf(" r%d",r);
10775       }
10776     }
10777 #endif
10778     printf("\n");
10779     #if defined(__i386__) || defined(__x86_64__)
10780     printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
10781     #endif
10782     #ifdef __arm__
10783     printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
10784     #endif
10785     printf("needs: ");
10786     if(needed_reg[i]&1) printf("eax ");
10787     if((needed_reg[i]>>1)&1) printf("ecx ");
10788     if((needed_reg[i]>>2)&1) printf("edx ");
10789     if((needed_reg[i]>>3)&1) printf("ebx ");
10790     if((needed_reg[i]>>5)&1) printf("ebp ");
10791     if((needed_reg[i]>>6)&1) printf("esi ");
10792     if((needed_reg[i]>>7)&1) printf("edi ");
10793     printf("r:");
10794     for(r=0;r<=CCREG;r++) {
10795       //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10796       if((requires_32bit[i]>>r)&1) {
10797         if(r==CCREG) printf(" CC");
10798         else if(r==HIREG) printf(" HI");
10799         else if(r==LOREG) printf(" LO");
10800         else printf(" r%d",r);
10801       }
10802     }
10803     printf("\n");
10804     /*printf("pr:");
10805     for(r=0;r<=CCREG;r++) {
10806       //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10807       if((pr32[i]>>r)&1) {
10808         if(r==CCREG) printf(" CC");
10809         else if(r==HIREG) printf(" HI");
10810         else if(r==LOREG) printf(" LO");
10811         else printf(" r%d",r);
10812       }
10813     }
10814     if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
10815     printf("\n");*/
10816     #if defined(__i386__) || defined(__x86_64__)
10817     printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
10818     printf("dirty: ");
10819     if(regs[i].wasdirty&1) printf("eax ");
10820     if((regs[i].wasdirty>>1)&1) printf("ecx ");
10821     if((regs[i].wasdirty>>2)&1) printf("edx ");
10822     if((regs[i].wasdirty>>3)&1) printf("ebx ");
10823     if((regs[i].wasdirty>>5)&1) printf("ebp ");
10824     if((regs[i].wasdirty>>6)&1) printf("esi ");
10825     if((regs[i].wasdirty>>7)&1) printf("edi ");
10826     #endif
10827     #ifdef __arm__
10828     printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
10829     printf("dirty: ");
10830     if(regs[i].wasdirty&1) printf("r0 ");
10831     if((regs[i].wasdirty>>1)&1) printf("r1 ");
10832     if((regs[i].wasdirty>>2)&1) printf("r2 ");
10833     if((regs[i].wasdirty>>3)&1) printf("r3 ");
10834     if((regs[i].wasdirty>>4)&1) printf("r4 ");
10835     if((regs[i].wasdirty>>5)&1) printf("r5 ");
10836     if((regs[i].wasdirty>>6)&1) printf("r6 ");
10837     if((regs[i].wasdirty>>7)&1) printf("r7 ");
10838     if((regs[i].wasdirty>>8)&1) printf("r8 ");
10839     if((regs[i].wasdirty>>9)&1) printf("r9 ");
10840     if((regs[i].wasdirty>>10)&1) printf("r10 ");
10841     if((regs[i].wasdirty>>12)&1) printf("r12 ");
10842     #endif
10843     printf("\n");
10844     disassemble_inst(i);
10845     //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
10846     #if defined(__i386__) || defined(__x86_64__)
10847     printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
10848     if(regs[i].dirty&1) printf("eax ");
10849     if((regs[i].dirty>>1)&1) printf("ecx ");
10850     if((regs[i].dirty>>2)&1) printf("edx ");
10851     if((regs[i].dirty>>3)&1) printf("ebx ");
10852     if((regs[i].dirty>>5)&1) printf("ebp ");
10853     if((regs[i].dirty>>6)&1) printf("esi ");
10854     if((regs[i].dirty>>7)&1) printf("edi ");
10855     #endif
10856     #ifdef __arm__
10857     printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
10858     if(regs[i].dirty&1) printf("r0 ");
10859     if((regs[i].dirty>>1)&1) printf("r1 ");
10860     if((regs[i].dirty>>2)&1) printf("r2 ");
10861     if((regs[i].dirty>>3)&1) printf("r3 ");
10862     if((regs[i].dirty>>4)&1) printf("r4 ");
10863     if((regs[i].dirty>>5)&1) printf("r5 ");
10864     if((regs[i].dirty>>6)&1) printf("r6 ");
10865     if((regs[i].dirty>>7)&1) printf("r7 ");
10866     if((regs[i].dirty>>8)&1) printf("r8 ");
10867     if((regs[i].dirty>>9)&1) printf("r9 ");
10868     if((regs[i].dirty>>10)&1) printf("r10 ");
10869     if((regs[i].dirty>>12)&1) printf("r12 ");
10870     #endif
10871     printf("\n");
10872     if(regs[i].isconst) {
10873       printf("constants: ");
10874       #if defined(__i386__) || defined(__x86_64__)
10875       if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
10876       if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
10877       if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
10878       if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
10879       if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
10880       if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
10881       if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
10882       #endif
10883       #ifdef __arm__
10884       if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
10885       if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
10886       if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
10887       if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
10888       if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
10889       if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
10890       if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
10891       if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
10892       if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
10893       if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
10894       if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
10895       if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
10896       #endif
10897       printf("\n");
10898     }
10899 #ifndef FORCE32
10900     printf(" 32:");
10901     for(r=0;r<=CCREG;r++) {
10902       if((regs[i].is32>>r)&1) {
10903         if(r==CCREG) printf(" CC");
10904         else if(r==HIREG) printf(" HI");
10905         else if(r==LOREG) printf(" LO");
10906         else printf(" r%d",r);
10907       }
10908     }
10909     printf("\n");
10910 #endif
10911     /*printf(" p32:");
10912     for(r=0;r<=CCREG;r++) {
10913       if((p32[i]>>r)&1) {
10914         if(r==CCREG) printf(" CC");
10915         else if(r==HIREG) printf(" HI");
10916         else if(r==LOREG) printf(" LO");
10917         else printf(" r%d",r);
10918       }
10919     }
10920     if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
10921     else printf("\n");*/
10922     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10923       #if defined(__i386__) || defined(__x86_64__)
10924       printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
10925       if(branch_regs[i].dirty&1) printf("eax ");
10926       if((branch_regs[i].dirty>>1)&1) printf("ecx ");
10927       if((branch_regs[i].dirty>>2)&1) printf("edx ");
10928       if((branch_regs[i].dirty>>3)&1) printf("ebx ");
10929       if((branch_regs[i].dirty>>5)&1) printf("ebp ");
10930       if((branch_regs[i].dirty>>6)&1) printf("esi ");
10931       if((branch_regs[i].dirty>>7)&1) printf("edi ");
10932       #endif
10933       #ifdef __arm__
10934       printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
10935       if(branch_regs[i].dirty&1) printf("r0 ");
10936       if((branch_regs[i].dirty>>1)&1) printf("r1 ");
10937       if((branch_regs[i].dirty>>2)&1) printf("r2 ");
10938       if((branch_regs[i].dirty>>3)&1) printf("r3 ");
10939       if((branch_regs[i].dirty>>4)&1) printf("r4 ");
10940       if((branch_regs[i].dirty>>5)&1) printf("r5 ");
10941       if((branch_regs[i].dirty>>6)&1) printf("r6 ");
10942       if((branch_regs[i].dirty>>7)&1) printf("r7 ");
10943       if((branch_regs[i].dirty>>8)&1) printf("r8 ");
10944       if((branch_regs[i].dirty>>9)&1) printf("r9 ");
10945       if((branch_regs[i].dirty>>10)&1) printf("r10 ");
10946       if((branch_regs[i].dirty>>12)&1) printf("r12 ");
10947       #endif
10948 #ifndef FORCE32
10949       printf(" 32:");
10950       for(r=0;r<=CCREG;r++) {
10951         if((branch_regs[i].is32>>r)&1) {
10952           if(r==CCREG) printf(" CC");
10953           else if(r==HIREG) printf(" HI");
10954           else if(r==LOREG) printf(" LO");
10955           else printf(" r%d",r);
10956         }
10957       }
10958       printf("\n");
10959 #endif
10960     }
10961   }
10962
10963   /* Pass 8 - Assembly */
10964   linkcount=0;stubcount=0;
10965   ds=0;is_delayslot=0;
10966   cop1_usable=0;
10967   uint64_t is32_pre=0;
10968   u_int dirty_pre=0;
10969   u_int beginning=(u_int)out;
10970   if((u_int)addr&1) {
10971     ds=1;
10972     pagespan_ds();
10973   }
10974   u_int instr_addr0_override=0;
10975
10976 #ifdef PCSX
10977   if (start == 0x80030000) {
10978     // nasty hack for fastbios thing
10979     // override block entry to this code
10980     instr_addr0_override=(u_int)out;
10981     emit_movimm(start,0);
10982     // abuse io address var as a flag that we
10983     // have already returned here once
10984     emit_readword((int)&address,1);
10985     emit_writeword(0,(int)&pcaddr);
10986     emit_writeword(0,(int)&address);
10987     emit_cmp(0,1);
10988     emit_jne((int)new_dyna_leave);
10989   }
10990 #endif
10991   for(i=0;i<slen;i++)
10992   {
10993     //if(ds) printf("ds: ");
10994     if((void*)assem_debug==(void*)printf) disassemble_inst(i);
10995     if(ds) {
10996       ds=0; // Skip delay slot
10997       if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
10998       instr_addr[i]=0;
10999     } else {
11000       #ifndef DESTRUCTIVE_WRITEBACK
11001       if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11002       {
11003         wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
11004               unneeded_reg[i],unneeded_reg_upper[i]);
11005         wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
11006               unneeded_reg[i],unneeded_reg_upper[i]);
11007       }
11008       if((itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)&&!likely[i]) {
11009         is32_pre=branch_regs[i].is32;
11010         dirty_pre=branch_regs[i].dirty;
11011       }else{
11012         is32_pre=regs[i].is32;
11013         dirty_pre=regs[i].dirty;
11014       }
11015       #endif
11016       // write back
11017       if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11018       {
11019         wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
11020                       unneeded_reg[i],unneeded_reg_upper[i]);
11021         loop_preload(regmap_pre[i],regs[i].regmap_entry);
11022       }
11023       // branch target entry point
11024       instr_addr[i]=(u_int)out;
11025       assem_debug("<->\n");
11026       // load regs
11027       if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
11028         wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
11029       load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
11030       address_generation(i,&regs[i],regs[i].regmap_entry);
11031       load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
11032       if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
11033       {
11034         // Load the delay slot registers if necessary
11035         if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i]&&(rs1[i+1]!=rt1[i]||rt1[i]==0))
11036           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11037         if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i]&&(rs2[i+1]!=rt1[i]||rt1[i]==0))
11038           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11039         if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
11040           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11041       }
11042       else if(i+1<slen)
11043       {
11044         // Preload registers for following instruction
11045         if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
11046           if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
11047             load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11048         if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
11049           if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
11050             load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11051       }
11052       // TODO: if(is_ooo(i)) address_generation(i+1);
11053       if(itype[i]==CJUMP||itype[i]==FJUMP)
11054         load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
11055       if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
11056         load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11057       if(bt[i]) cop1_usable=0;
11058       // assemble
11059       switch(itype[i]) {
11060         case ALU:
11061           alu_assemble(i,&regs[i]);break;
11062         case IMM16:
11063           imm16_assemble(i,&regs[i]);break;
11064         case SHIFT:
11065           shift_assemble(i,&regs[i]);break;
11066         case SHIFTIMM:
11067           shiftimm_assemble(i,&regs[i]);break;
11068         case LOAD:
11069           load_assemble(i,&regs[i]);break;
11070         case LOADLR:
11071           loadlr_assemble(i,&regs[i]);break;
11072         case STORE:
11073           store_assemble(i,&regs[i]);break;
11074         case STORELR:
11075           storelr_assemble(i,&regs[i]);break;
11076         case COP0:
11077           cop0_assemble(i,&regs[i]);break;
11078         case COP1:
11079           cop1_assemble(i,&regs[i]);break;
11080         case C1LS:
11081           c1ls_assemble(i,&regs[i]);break;
11082         case COP2:
11083           cop2_assemble(i,&regs[i]);break;
11084         case C2LS:
11085           c2ls_assemble(i,&regs[i]);break;
11086         case C2OP:
11087           c2op_assemble(i,&regs[i]);break;
11088         case FCONV:
11089           fconv_assemble(i,&regs[i]);break;
11090         case FLOAT:
11091           float_assemble(i,&regs[i]);break;
11092         case FCOMP:
11093           fcomp_assemble(i,&regs[i]);break;
11094         case MULTDIV:
11095           multdiv_assemble(i,&regs[i]);break;
11096         case MOV:
11097           mov_assemble(i,&regs[i]);break;
11098         case SYSCALL:
11099           syscall_assemble(i,&regs[i]);break;
11100         case HLECALL:
11101           hlecall_assemble(i,&regs[i]);break;
11102         case INTCALL:
11103           intcall_assemble(i,&regs[i]);break;
11104         case UJUMP:
11105           ujump_assemble(i,&regs[i]);ds=1;break;
11106         case RJUMP:
11107           rjump_assemble(i,&regs[i]);ds=1;break;
11108         case CJUMP:
11109           cjump_assemble(i,&regs[i]);ds=1;break;
11110         case SJUMP:
11111           sjump_assemble(i,&regs[i]);ds=1;break;
11112         case FJUMP:
11113           fjump_assemble(i,&regs[i]);ds=1;break;
11114         case SPAN:
11115           pagespan_assemble(i,&regs[i]);break;
11116       }
11117       if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
11118         literal_pool(1024);
11119       else
11120         literal_pool_jumpover(256);
11121     }
11122   }
11123   //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
11124   // If the block did not end with an unconditional branch,
11125   // add a jump to the next instruction.
11126   if(i>1) {
11127     if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
11128       assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11129       assert(i==slen);
11130       if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
11131         store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11132         if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11133           emit_loadreg(CCREG,HOST_CCREG);
11134         emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
11135       }
11136       else if(!likely[i-2])
11137       {
11138         store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
11139         assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
11140       }
11141       else
11142       {
11143         store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
11144         assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
11145       }
11146       add_to_linker((int)out,start+i*4,0);
11147       emit_jmp(0);
11148     }
11149   }
11150   else
11151   {
11152     assert(i>0);
11153     assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11154     store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11155     if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11156       emit_loadreg(CCREG,HOST_CCREG);
11157     emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
11158     add_to_linker((int)out,start+i*4,0);
11159     emit_jmp(0);
11160   }
11161
11162   // TODO: delay slot stubs?
11163   // Stubs
11164   for(i=0;i<stubcount;i++)
11165   {
11166     switch(stubs[i][0])
11167     {
11168       case LOADB_STUB:
11169       case LOADH_STUB:
11170       case LOADW_STUB:
11171       case LOADD_STUB:
11172       case LOADBU_STUB:
11173       case LOADHU_STUB:
11174         do_readstub(i);break;
11175       case STOREB_STUB:
11176       case STOREH_STUB:
11177       case STOREW_STUB:
11178       case STORED_STUB:
11179         do_writestub(i);break;
11180       case CC_STUB:
11181         do_ccstub(i);break;
11182       case INVCODE_STUB:
11183         do_invstub(i);break;
11184       case FP_STUB:
11185         do_cop1stub(i);break;
11186       case STORELR_STUB:
11187         do_unalignedwritestub(i);break;
11188     }
11189   }
11190
11191   if (instr_addr0_override)
11192     instr_addr[0] = instr_addr0_override;
11193
11194   /* Pass 9 - Linker */
11195   for(i=0;i<linkcount;i++)
11196   {
11197     assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
11198     literal_pool(64);
11199     if(!link_addr[i][2])
11200     {
11201       void *stub=out;
11202       void *addr=check_addr(link_addr[i][1]);
11203       emit_extjump(link_addr[i][0],link_addr[i][1]);
11204       if(addr) {
11205         set_jump_target(link_addr[i][0],(int)addr);
11206         add_link(link_addr[i][1],stub);
11207       }
11208       else set_jump_target(link_addr[i][0],(int)stub);
11209     }
11210     else
11211     {
11212       // Internal branch
11213       int target=(link_addr[i][1]-start)>>2;
11214       assert(target>=0&&target<slen);
11215       assert(instr_addr[target]);
11216       //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11217       //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
11218       //#else
11219       set_jump_target(link_addr[i][0],instr_addr[target]);
11220       //#endif
11221     }
11222   }
11223   // External Branch Targets (jump_in)
11224   if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
11225   for(i=0;i<slen;i++)
11226   {
11227     if(bt[i]||i==0)
11228     {
11229       if(instr_addr[i]) // TODO - delay slots (=null)
11230       {
11231         u_int vaddr=start+i*4;
11232         u_int page=get_page(vaddr);
11233         u_int vpage=get_vpage(vaddr);
11234         literal_pool(256);
11235         //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
11236 #ifndef FORCE32
11237         if(!requires_32bit[i])
11238 #else
11239         if(1)
11240 #endif
11241         {
11242           assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11243           assem_debug("jump_in: %x\n",start+i*4);
11244           ll_add(jump_dirty+vpage,vaddr,(void *)out);
11245           int entry_point=do_dirty_stub(i);
11246           ll_add(jump_in+page,vaddr,(void *)entry_point);
11247           // If there was an existing entry in the hash table,
11248           // replace it with the new address.
11249           // Don't add new entries.  We'll insert the
11250           // ones that actually get used in check_addr().
11251           int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
11252           if(ht_bin[0]==vaddr) {
11253             ht_bin[1]=entry_point;
11254           }
11255           if(ht_bin[2]==vaddr) {
11256             ht_bin[3]=entry_point;
11257           }
11258         }
11259         else
11260         {
11261           u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
11262           assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11263           assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
11264           //int entry_point=(int)out;
11265           ////assem_debug("entry_point: %x\n",entry_point);
11266           //load_regs_entry(i);
11267           //if(entry_point==(int)out)
11268           //  entry_point=instr_addr[i];
11269           //else
11270           //  emit_jmp(instr_addr[i]);
11271           //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11272           ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
11273           int entry_point=do_dirty_stub(i);
11274           ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11275         }
11276       }
11277     }
11278   }
11279   // Write out the literal pool if necessary
11280   literal_pool(0);
11281   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11282   // Align code
11283   if(((u_int)out)&7) emit_addnop(13);
11284   #endif
11285   assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
11286   //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
11287   memcpy(copy,source,slen*4);
11288   copy+=slen*4;
11289
11290   #ifdef __arm__
11291   __clear_cache((void *)beginning,out);
11292   #endif
11293
11294   // If we're within 256K of the end of the buffer,
11295   // start over from the beginning. (Is 256K enough?)
11296   if((int)out>BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
11297
11298   // Trap writes to any of the pages we compiled
11299   for(i=start>>12;i<=(start+slen*4)>>12;i++) {
11300     invalid_code[i]=0;
11301 #ifndef DISABLE_TLB
11302     memory_map[i]|=0x40000000;
11303     if((signed int)start>=(signed int)0xC0000000) {
11304       assert(using_tlb);
11305       j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
11306       invalid_code[j]=0;
11307       memory_map[j]|=0x40000000;
11308       //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
11309     }
11310 #endif
11311   }
11312 #ifdef PCSX
11313   // PCSX maps all RAM mirror invalid_code tests to 0x80000000..0x80000000+RAM_SIZE
11314   if(get_page(start)<(RAM_SIZE>>12))
11315     for(i=start>>12;i<=(start+slen*4)>>12;i++)
11316       invalid_code[((u_int)0x80000000>>12)|i]=0;
11317 #endif
11318
11319   /* Pass 10 - Free memory by expiring oldest blocks */
11320
11321   int end=((((int)out-BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
11322   while(expirep!=end)
11323   {
11324     int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
11325     int base=BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
11326     inv_debug("EXP: Phase %d\n",expirep);
11327     switch((expirep>>11)&3)
11328     {
11329       case 0:
11330         // Clear jump_in and jump_dirty
11331         ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
11332         ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
11333         ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
11334         ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
11335         break;
11336       case 1:
11337         // Clear pointers
11338         ll_kill_pointers(jump_out[expirep&2047],base,shift);
11339         ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
11340         break;
11341       case 2:
11342         // Clear hash table
11343         for(i=0;i<32;i++) {
11344           int *ht_bin=hash_table[((expirep&2047)<<5)+i];
11345           if((ht_bin[3]>>shift)==(base>>shift) ||
11346              ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11347             inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
11348             ht_bin[2]=ht_bin[3]=-1;
11349           }
11350           if((ht_bin[1]>>shift)==(base>>shift) ||
11351              ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11352             inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
11353             ht_bin[0]=ht_bin[2];
11354             ht_bin[1]=ht_bin[3];
11355             ht_bin[2]=ht_bin[3]=-1;
11356           }
11357         }
11358         break;
11359       case 3:
11360         // Clear jump_out
11361         #ifdef __arm__
11362         if((expirep&2047)==0)
11363           do_clear_cache();
11364         #endif
11365         ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
11366         ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
11367         break;
11368     }
11369     expirep=(expirep+1)&65535;
11370   }
11371   return 0;
11372 }
11373
11374 // vim:shiftwidth=2:expandtab