libpcsxcore/new_dynarec/new_dynarec.c

   1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
   2  *   Mupen64plus - new_dynarec.c                                           *
   3  *   Copyright (C) 2009-2010 Ari64                                         *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.          *
  19  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
  20
  21 #include <stdlib.h>
  22 #include <stdint.h> //include for uint64_t
  23 #include <assert.h>
  24
  25 #include "emu_if.h" //emulator interface
  26
  27 #include <sys/mman.h>
  28
  29 #ifdef __i386__
  30 #include "assem_x86.h"
  31 #endif
  32 #ifdef __x86_64__
  33 #include "assem_x64.h"
  34 #endif
  35 #ifdef __arm__
  36 #include "assem_arm.h"
  37 #endif
  38
  39 #define MAXBLOCK 4096
  40 #define MAX_OUTPUT_BLOCK_SIZE 262144
  41 #define CLOCK_DIVIDER 2
  42
  43 struct regstat
  44 {
  45   signed char regmap_entry[HOST_REGS];
  46   signed char regmap[HOST_REGS];
  47   uint64_t was32;
  48   uint64_t is32;
  49   uint64_t wasdirty;
  50   uint64_t dirty;
  51   uint64_t u;
  52   uint64_t uu;
  53   u_int wasconst;
  54   u_int isconst;
  55   uint64_t constmap[HOST_REGS];
  56 };
  57
  58 struct ll_entry
  59 {
  60   u_int vaddr;
  61   u_int reg32;
  62   void *addr;
  63   struct ll_entry *next;
  64 };
  65
  66   u_int start;
  67   u_int *source;
  68   u_int pagelimit;
  69   char insn[MAXBLOCK][10];
  70   u_char itype[MAXBLOCK];
  71   u_char opcode[MAXBLOCK];
  72   u_char opcode2[MAXBLOCK];
  73   u_char bt[MAXBLOCK];
  74   u_char rs1[MAXBLOCK];
  75   u_char rs2[MAXBLOCK];
  76   u_char rt1[MAXBLOCK];
  77   u_char rt2[MAXBLOCK];
  78   u_char us1[MAXBLOCK];
  79   u_char us2[MAXBLOCK];
  80   u_char dep1[MAXBLOCK];
  81   u_char dep2[MAXBLOCK];
  82   u_char lt1[MAXBLOCK];
  83   int imm[MAXBLOCK];
  84   u_int ba[MAXBLOCK];
  85   char likely[MAXBLOCK];
  86   char is_ds[MAXBLOCK];
  87   uint64_t unneeded_reg[MAXBLOCK];
  88   uint64_t unneeded_reg_upper[MAXBLOCK];
  89   uint64_t branch_unneeded_reg[MAXBLOCK];
  90   uint64_t branch_unneeded_reg_upper[MAXBLOCK];
  91   uint64_t p32[MAXBLOCK];
  92   uint64_t pr32[MAXBLOCK];
  93   signed char regmap_pre[MAXBLOCK][HOST_REGS];
  94   signed char regmap[MAXBLOCK][HOST_REGS];
  95   signed char regmap_entry[MAXBLOCK][HOST_REGS];
  96   uint64_t constmap[MAXBLOCK][HOST_REGS];
  97   uint64_t known_value[HOST_REGS];
  98   u_int known_reg;
  99   struct regstat regs[MAXBLOCK];
 100   struct regstat branch_regs[MAXBLOCK];
 101   u_int needed_reg[MAXBLOCK];
 102   uint64_t requires_32bit[MAXBLOCK];
 103   u_int wont_dirty[MAXBLOCK];
 104   u_int will_dirty[MAXBLOCK];
 105   int ccadj[MAXBLOCK];
 106   int slen;
 107   u_int instr_addr[MAXBLOCK];
 108   u_int link_addr[MAXBLOCK][3];
 109   int linkcount;
 110   u_int stubs[MAXBLOCK*3][8];
 111   int stubcount;
 112   u_int literals[1024][2];
 113   int literalcount;
 114   int is_delayslot;
 115   int cop1_usable;
 116   u_char *out;
 117   struct ll_entry *jump_in[4096];
 118   struct ll_entry *jump_out[4096];
 119   struct ll_entry *jump_dirty[4096];
 120   u_int hash_table[65536][4]  __attribute__((aligned(16)));
 121   char shadow[1048576]  __attribute__((aligned(16)));
 122   void *copy;
 123   int expirep;
 124   u_int using_tlb;
 125   u_int stop_after_jal;
 126   extern u_char restore_candidate[512];
 127   extern int cycle_count;
 128
 129   /* registers that may be allocated */
 130   /* 1-31 gpr */
 131 #define HIREG 32 // hi
 132 #define LOREG 33 // lo
 133 #define FSREG 34 // FPU status (FCSR)
 134 #define CSREG 35 // Coprocessor status
 135 #define CCREG 36 // Cycle count
 136 #define INVCP 37 // Pointer to invalid_code
 137 #define TEMPREG 38
 138 #define FTEMP 38 // FPU/LDL/LDR temporary register
 139 #define PTEMP 39 // Prefetch temporary register
 140 #define TLREG 40 // TLB mapping offset
 141 #define RHASH 41 // Return address hash
 142 #define RHTBL 42 // Return address hash table address
 143 #define RTEMP 43 // JR/JALR address register
 144 #define MAXREG 43
 145 #define AGEN1 44 // Address generation temporary register
 146 #define AGEN2 45 // Address generation temporary register
 147 #define MGEN1 46 // Maptable address generation temporary register
 148 #define MGEN2 47 // Maptable address generation temporary register
 149 #define BTREG 48 // Branch target temporary register
 150
 151   /* instruction types */
 152 #define NOP 0     // No operation
 153 #define LOAD 1    // Load
 154 #define STORE 2   // Store
 155 #define LOADLR 3  // Unaligned load
 156 #define STORELR 4 // Unaligned store
 157 #define MOV 5     // Move
 158 #define ALU 6     // Arithmetic/logic
 159 #define MULTDIV 7 // Multiply/divide
 160 #define SHIFT 8   // Shift by register
 161 #define SHIFTIMM 9// Shift by immediate
 162 #define IMM16 10  // 16-bit immediate
 163 #define RJUMP 11  // Unconditional jump to register
 164 #define UJUMP 12  // Unconditional jump
 165 #define CJUMP 13  // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
 166 #define SJUMP 14  // Conditional branch (regimm format)
 167 #define COP0 15   // Coprocessor 0
 168 #define COP1 16   // Coprocessor 1
 169 #define C1LS 17   // Coprocessor 1 load/store
 170 #define FJUMP 18  // Conditional branch (floating point)
 171 #define FLOAT 19  // Floating point unit
 172 #define FCONV 20  // Convert integer to float
 173 #define FCOMP 21  // Floating point compare (sets FSREG)
 174 #define SYSCALL 22// SYSCALL
 175 #define OTHER 23  // Other
 176 #define SPAN 24   // Branch/delay slot spans 2 pages
 177 #define NI 25     // Not implemented
 178 #define HLECALL 26// PCSX fake opcodes for HLE
 179 #define COP2 27   // Coprocessor 2 move
 180 #define C2LS 28   // Coprocessor 2 load/store
 181 #define C2OP 29   // Coprocessor 2 operation
 182
 183   /* stubs */
 184 #define CC_STUB 1
 185 #define FP_STUB 2
 186 #define LOADB_STUB 3
 187 #define LOADH_STUB 4
 188 #define LOADW_STUB 5
 189 #define LOADD_STUB 6
 190 #define LOADBU_STUB 7
 191 #define LOADHU_STUB 8
 192 #define STOREB_STUB 9
 193 #define STOREH_STUB 10
 194 #define STOREW_STUB 11
 195 #define STORED_STUB 12
 196 #define STORELR_STUB 13
 197 #define INVCODE_STUB 14
 198
 199   /* branch codes */
 200 #define TAKEN 1
 201 #define NOTTAKEN 2
 202 #define NULLDS 3
 203
 204 // asm linkage
 205 int new_recompile_block(int addr);
 206 void *get_addr_ht(u_int vaddr);
 207 void invalidate_block(u_int block);
 208 void invalidate_addr(u_int addr);
 209 void remove_hash(int vaddr);
 210 void jump_vaddr();
 211 void dyna_linker();
 212 void dyna_linker_ds();
 213 void verify_code();
 214 void verify_code_vm();
 215 void verify_code_ds();
 216 void cc_interrupt();
 217 void fp_exception();
 218 void fp_exception_ds();
 219 void jump_syscall();
 220 void jump_syscall_hle();
 221 void jump_eret();
 222 void jump_hlecall();
 223 void new_dyna_leave();
 224
 225 // TLB
 226 void TLBWI_new();
 227 void TLBWR_new();
 228 void read_nomem_new();
 229 void read_nomemb_new();
 230 void read_nomemh_new();
 231 void read_nomemd_new();
 232 void write_nomem_new();
 233 void write_nomemb_new();
 234 void write_nomemh_new();
 235 void write_nomemd_new();
 236 void write_rdram_new();
 237 void write_rdramb_new();
 238 void write_rdramh_new();
 239 void write_rdramd_new();
 240 extern u_int memory_map[1048576];
 241
 242 // Needed by assembler
 243 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
 244 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
 245 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
 246 void load_all_regs(signed char i_regmap[]);
 247 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
 248 void load_regs_entry(int t);
 249 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
 250
 251 int tracedebug=0;
 252
 253 //#define DEBUG_CYCLE_COUNT 1
 254
 255 void nullf() {}
 256 //#define assem_debug printf
 257 //#define inv_debug printf
 258 #define assem_debug nullf
 259 #define inv_debug nullf
 260
 261 static void tlb_hacks()
 262 {
 263 #ifndef DISABLE_TLB
 264   // Goldeneye hack
 265   if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
 266   {
 267     u_int addr;
 268     int n;
 269     switch (ROM_HEADER->Country_code&0xFF)
 270     {
 271       case 0x45: // U
 272         addr=0x34b30;
 273         break;
 274       case 0x4A: // J
 275         addr=0x34b70;
 276         break;
 277       case 0x50: // E
 278         addr=0x329f0;
 279         break;
 280       default:
 281         // Unknown country code
 282         addr=0;
 283         break;
 284     }
 285     u_int rom_addr=(u_int)rom;
 286     #ifdef ROM_COPY
 287     // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
 288     // in the lower 4G of memory to use this hack.  Copy it if necessary.
 289     if((void *)rom>(void *)0xffffffff) {
 290       munmap(ROM_COPY, 67108864);
 291       if(mmap(ROM_COPY, 12582912,
 292               PROT_READ | PROT_WRITE,
 293               MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
 294               -1, 0) <= 0) {printf("mmap() failed\n");}
 295       memcpy(ROM_COPY,rom,12582912);
 296       rom_addr=(u_int)ROM_COPY;
 297     }
 298     #endif
 299     if(addr) {
 300       for(n=0x7F000;n<0x80000;n++) {
 301         memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
 302       }
 303     }
 304   }
 305 #endif
 306 }
 307
 308 static u_int get_page(u_int vaddr)
 309 {
 310   u_int page=(vaddr^0x80000000)>>12;
 311 #ifndef DISABLE_TLB
 312   if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
 313 #endif
 314   if(page>2048) page=2048+(page&2047);
 315   return page;
 316 }
 317
 318 static u_int get_vpage(u_int vaddr)
 319 {
 320   u_int vpage=(vaddr^0x80000000)>>12;
 321 #ifndef DISABLE_TLB
 322   if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
 323 #endif
 324   if(vpage>2048) vpage=2048+(vpage&2047);
 325   return vpage;
 326 }
 327
 328 // Get address from virtual address
 329 // This is called from the recompiled JR/JALR instructions
 330 void *get_addr(u_int vaddr)
 331 {
 332   u_int page=get_page(vaddr);
 333   u_int vpage=get_vpage(vaddr);
 334   struct ll_entry *head;
 335   //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
 336   head=jump_in[page];
 337   while(head!=NULL) {
 338     if(head->vaddr==vaddr&&head->reg32==0) {
 339   //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 340       int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 341       ht_bin[3]=ht_bin[1];
 342       ht_bin[2]=ht_bin[0];
 343       ht_bin[1]=(int)head->addr;
 344       ht_bin[0]=vaddr;
 345       return head->addr;
 346     }
 347     head=head->next;
 348   }
 349   head=jump_dirty[vpage];
 350   while(head!=NULL) {
 351     if(head->vaddr==vaddr&&head->reg32==0) {
 352       //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 353       // Don't restore blocks which are about to expire from the cache
 354       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 355       if(verify_dirty(head->addr)) {
 356         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
 357         invalid_code[vaddr>>12]=0;
 358         memory_map[vaddr>>12]|=0x40000000;
 359         if(vpage<2048) {
 360 #ifndef DISABLE_TLB
 361           if(tlb_LUT_r[vaddr>>12]) {
 362             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
 363             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
 364           }
 365 #endif
 366           restore_candidate[vpage>>3]|=1<<(vpage&7);
 367         }
 368         else restore_candidate[page>>3]|=1<<(page&7);
 369         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 370         if(ht_bin[0]==vaddr) {
 371           ht_bin[1]=(int)head->addr; // Replace existing entry
 372         }
 373         else
 374         {
 375           ht_bin[3]=ht_bin[1];
 376           ht_bin[2]=ht_bin[0];
 377           ht_bin[1]=(int)head->addr;
 378           ht_bin[0]=vaddr;
 379         }
 380         return head->addr;
 381       }
 382     }
 383     head=head->next;
 384   }
 385   //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
 386   int r=new_recompile_block(vaddr);
 387   if(r==0) return get_addr(vaddr);
 388   // Execute in unmapped page, generate pagefault execption
 389   Status|=2;
 390   Cause=(vaddr<<31)|0x8;
 391   EPC=(vaddr&1)?vaddr-5:vaddr;
 392   BadVAddr=(vaddr&~1);
 393   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
 394   EntryHi=BadVAddr&0xFFFFE000;
 395   return get_addr_ht(0x80000000);
 396 }
 397 // Look up address in hash table first
 398 void *get_addr_ht(u_int vaddr)
 399 {
 400   //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
 401   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 402   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
 403   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
 404   return get_addr(vaddr);
 405 }
 406
 407 void *get_addr_32(u_int vaddr,u_int flags)
 408 {
 409 #ifdef FORCE32
 410   return get_addr(vaddr);
 411 #endif
 412   //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
 413   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 414   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
 415   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
 416   u_int page=get_page(vaddr);
 417   u_int vpage=get_vpage(vaddr);
 418   struct ll_entry *head;
 419   head=jump_in[page];
 420   while(head!=NULL) {
 421     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
 422       //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 423       if(head->reg32==0) {
 424         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 425         if(ht_bin[0]==-1) {
 426           ht_bin[1]=(int)head->addr;
 427           ht_bin[0]=vaddr;
 428         }else if(ht_bin[2]==-1) {
 429           ht_bin[3]=(int)head->addr;
 430           ht_bin[2]=vaddr;
 431         }
 432         //ht_bin[3]=ht_bin[1];
 433         //ht_bin[2]=ht_bin[0];
 434         //ht_bin[1]=(int)head->addr;
 435         //ht_bin[0]=vaddr;
 436       }
 437       return head->addr;
 438     }
 439     head=head->next;
 440   }
 441   head=jump_dirty[vpage];
 442   while(head!=NULL) {
 443     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
 444       //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 445       // Don't restore blocks which are about to expire from the cache
 446       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 447       if(verify_dirty(head->addr)) {
 448         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
 449         invalid_code[vaddr>>12]=0;
 450         memory_map[vaddr>>12]|=0x40000000;
 451         if(vpage<2048) {
 452 #ifndef DISABLE_TLB
 453           if(tlb_LUT_r[vaddr>>12]) {
 454             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
 455             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
 456           }
 457 #endif
 458           restore_candidate[vpage>>3]|=1<<(vpage&7);
 459         }
 460         else restore_candidate[page>>3]|=1<<(page&7);
 461         if(head->reg32==0) {
 462           int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 463           if(ht_bin[0]==-1) {
 464             ht_bin[1]=(int)head->addr;
 465             ht_bin[0]=vaddr;
 466           }else if(ht_bin[2]==-1) {
 467             ht_bin[3]=(int)head->addr;
 468             ht_bin[2]=vaddr;
 469           }
 470           //ht_bin[3]=ht_bin[1];
 471           //ht_bin[2]=ht_bin[0];
 472           //ht_bin[1]=(int)head->addr;
 473           //ht_bin[0]=vaddr;
 474         }
 475         return head->addr;
 476       }
 477     }
 478     head=head->next;
 479   }
 480   //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
 481   int r=new_recompile_block(vaddr);
 482   if(r==0) return get_addr(vaddr);
 483   // Execute in unmapped page, generate pagefault execption
 484   Status|=2;
 485   Cause=(vaddr<<31)|0x8;
 486   EPC=(vaddr&1)?vaddr-5:vaddr;
 487   BadVAddr=(vaddr&~1);
 488   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
 489   EntryHi=BadVAddr&0xFFFFE000;
 490   return get_addr_ht(0x80000000);
 491 }
 492
 493 void clear_all_regs(signed char regmap[])
 494 {
 495   int hr;
 496   for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
 497 }
 498
 499 signed char get_reg(signed char regmap[],int r)
 500 {
 501   int hr;
 502   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
 503   return -1;
 504 }
 505
 506 // Find a register that is available for two consecutive cycles
 507 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
 508 {
 509   int hr;
 510   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
 511   return -1;
 512 }
 513
 514 int count_free_regs(signed char regmap[])
 515 {
 516   int count=0;
 517   int hr;
 518   for(hr=0;hr<HOST_REGS;hr++)
 519   {
 520     if(hr!=EXCLUDE_REG) {
 521       if(regmap[hr]<0) count++;
 522     }
 523   }
 524   return count;
 525 }
 526
 527 void dirty_reg(struct regstat *cur,signed char reg)
 528 {
 529   int hr;
 530   if(!reg) return;
 531   for (hr=0;hr<HOST_REGS;hr++) {
 532     if((cur->regmap[hr]&63)==reg) {
 533       cur->dirty|=1<<hr;
 534     }
 535   }
 536 }
 537
 538 // If we dirty the lower half of a 64 bit register which is now being
 539 // sign-extended, we need to dump the upper half.
 540 // Note: Do this only after completion of the instruction, because
 541 // some instructions may need to read the full 64-bit value even if
 542 // overwriting it (eg SLTI, DSRA32).
 543 static void flush_dirty_uppers(struct regstat *cur)
 544 {
 545   int hr,reg;
 546   for (hr=0;hr<HOST_REGS;hr++) {
 547     if((cur->dirty>>hr)&1) {
 548       reg=cur->regmap[hr];
 549       if(reg>=64)
 550         if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
 551     }
 552   }
 553 }
 554
 555 void set_const(struct regstat *cur,signed char reg,uint64_t value)
 556 {
 557   int hr;
 558   if(!reg) return;
 559   for (hr=0;hr<HOST_REGS;hr++) {
 560     if(cur->regmap[hr]==reg) {
 561       cur->isconst|=1<<hr;
 562       cur->constmap[hr]=value;
 563     }
 564     else if((cur->regmap[hr]^64)==reg) {
 565       cur->isconst|=1<<hr;
 566       cur->constmap[hr]=value>>32;
 567     }
 568   }
 569 }
 570
 571 void clear_const(struct regstat *cur,signed char reg)
 572 {
 573   int hr;
 574   if(!reg) return;
 575   for (hr=0;hr<HOST_REGS;hr++) {
 576     if((cur->regmap[hr]&63)==reg) {
 577       cur->isconst&=~(1<<hr);
 578     }
 579   }
 580 }
 581
 582 int is_const(struct regstat *cur,signed char reg)
 583 {
 584   int hr;
 585   if(!reg) return 1;
 586   for (hr=0;hr<HOST_REGS;hr++) {
 587     if((cur->regmap[hr]&63)==reg) {
 588       return (cur->isconst>>hr)&1;
 589     }
 590   }
 591   return 0;
 592 }
 593 uint64_t get_const(struct regstat *cur,signed char reg)
 594 {
 595   int hr;
 596   if(!reg) return 0;
 597   for (hr=0;hr<HOST_REGS;hr++) {
 598     if(cur->regmap[hr]==reg) {
 599       return cur->constmap[hr];
 600     }
 601   }
 602   printf("Unknown constant in r%d\n",reg);
 603   exit(1);
 604 }
 605
 606 // Least soon needed registers
 607 // Look at the next ten instructions and see which registers
 608 // will be used.  Try not to reallocate these.
 609 void lsn(u_char hsn[], int i, int *preferred_reg)
 610 {
 611   int j;
 612   int b=-1;
 613   for(j=0;j<9;j++)
 614   {
 615     if(i+j>=slen) {
 616       j=slen-i-1;
 617       break;
 618     }
 619     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 620     {
 621       // Don't go past an unconditonal jump
 622       j++;
 623       break;
 624     }
 625   }
 626   for(;j>=0;j--)
 627   {
 628     if(rs1[i+j]) hsn[rs1[i+j]]=j;
 629     if(rs2[i+j]) hsn[rs2[i+j]]=j;
 630     if(rt1[i+j]) hsn[rt1[i+j]]=j;
 631     if(rt2[i+j]) hsn[rt2[i+j]]=j;
 632     if(itype[i+j]==STORE || itype[i+j]==STORELR) {
 633       // Stores can allocate zero
 634       hsn[rs1[i+j]]=j;
 635       hsn[rs2[i+j]]=j;
 636     }
 637     // On some architectures stores need invc_ptr
 638     #if defined(HOST_IMM8)
 639     if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
 640       hsn[INVCP]=j;
 641     }
 642     #endif
 643     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 644     {
 645       hsn[CCREG]=j;
 646       b=j;
 647     }
 648   }
 649   if(b>=0)
 650   {
 651     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 652     {
 653       // Follow first branch
 654       int t=(ba[i+b]-start)>>2;
 655       j=7-b;if(t+j>=slen) j=slen-t-1;
 656       for(;j>=0;j--)
 657       {
 658         if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
 659         if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
 660         //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
 661         //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
 662       }
 663     }
 664     // TODO: preferred register based on backward branch
 665   }
 666   // Delay slot should preferably not overwrite branch conditions or cycle count
 667   if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
 668     if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
 669     if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
 670     hsn[CCREG]=1;
 671     // ...or hash tables
 672     hsn[RHASH]=1;
 673     hsn[RHTBL]=1;
 674   }
 675   // Coprocessor load/store needs FTEMP, even if not declared
 676   if(itype[i]==C1LS||itype[i]==C2LS) {
 677     hsn[FTEMP]=0;
 678   }
 679   // Load L/R also uses FTEMP as a temporary register
 680   if(itype[i]==LOADLR) {
 681     hsn[FTEMP]=0;
 682   }
 683   // Also 64-bit SDL/SDR
 684   if(opcode[i]==0x2c||opcode[i]==0x2d) {
 685     hsn[FTEMP]=0;
 686   }
 687   // Don't remove the TLB registers either
 688   if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
 689     hsn[TLREG]=0;
 690   }
 691   // Don't remove the miniht registers
 692   if(itype[i]==UJUMP||itype[i]==RJUMP)
 693   {
 694     hsn[RHASH]=0;
 695     hsn[RHTBL]=0;
 696   }
 697 }
 698
 699 // We only want to allocate registers if we're going to use them again soon
 700 int needed_again(int r, int i)
 701 {
 702   int j;
 703   int b=-1;
 704   int rn=10;
 705   int hr;
 706   u_char hsn[MAXREG+1];
 707   int preferred_reg;
 708
 709   memset(hsn,10,sizeof(hsn));
 710   lsn(hsn,i,&preferred_reg);
 711
 712   if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
 713   {
 714     if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
 715       return 0; // Don't need any registers if exiting the block
 716   }
 717   for(j=0;j<9;j++)
 718   {
 719     if(i+j>=slen) {
 720       j=slen-i-1;
 721       break;
 722     }
 723     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 724     {
 725       // Don't go past an unconditonal jump
 726       j++;
 727       break;
 728     }
 729     if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||((source[i+j]&0xfc00003f)==0x0d))
 730     {
 731       break;
 732     }
 733   }
 734   for(;j>=1;j--)
 735   {
 736     if(rs1[i+j]==r) rn=j;
 737     if(rs2[i+j]==r) rn=j;
 738     if((unneeded_reg[i+j]>>r)&1) rn=10;
 739     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 740     {
 741       b=j;
 742     }
 743   }
 744   /*
 745   if(b>=0)
 746   {
 747     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 748     {
 749       // Follow first branch
 750       int o=rn;
 751       int t=(ba[i+b]-start)>>2;
 752       j=7-b;if(t+j>=slen) j=slen-t-1;
 753       for(;j>=0;j--)
 754       {
 755         if(!((unneeded_reg[t+j]>>r)&1)) {
 756           if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 757           if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 758         }
 759         else rn=o;
 760       }
 761     }
 762   }*/
 763   for(hr=0;hr<HOST_REGS;hr++) {
 764     if(hr!=EXCLUDE_REG) {
 765       if(rn<hsn[hr]) return 1;
 766     }
 767   }
 768   return 0;
 769 }
 770
 771 // Try to match register allocations at the end of a loop with those
 772 // at the beginning
 773 int loop_reg(int i, int r, int hr)
 774 {
 775   int j,k;
 776   for(j=0;j<9;j++)
 777   {
 778     if(i+j>=slen) {
 779       j=slen-i-1;
 780       break;
 781     }
 782     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 783     {
 784       // Don't go past an unconditonal jump
 785       j++;
 786       break;
 787     }
 788   }
 789   k=0;
 790   if(i>0){
 791     if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
 792       k--;
 793   }
 794   for(;k<j;k++)
 795   {
 796     if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
 797     if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
 798     if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
 799     {
 800       if(ba[i+k]>=start && ba[i+k]<(start+i*4))
 801       {
 802         int t=(ba[i+k]-start)>>2;
 803         int reg=get_reg(regs[t].regmap_entry,r);
 804         if(reg>=0) return reg;
 805         //reg=get_reg(regs[t+1].regmap_entry,r);
 806         //if(reg>=0) return reg;
 807       }
 808     }
 809   }
 810   return hr;
 811 }
 812
 813
 814 // Allocate every register, preserving source/target regs
 815 void alloc_all(struct regstat *cur,int i)
 816 {
 817   int hr;
 818
 819   for(hr=0;hr<HOST_REGS;hr++) {
 820     if(hr!=EXCLUDE_REG) {
 821       if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
 822          ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
 823       {
 824         cur->regmap[hr]=-1;
 825         cur->dirty&=~(1<<hr);
 826       }
 827       // Don't need zeros
 828       if((cur->regmap[hr]&63)==0)
 829       {
 830         cur->regmap[hr]=-1;
 831         cur->dirty&=~(1<<hr);
 832       }
 833     }
 834   }
 835 }
 836
 837
 838 void div64(int64_t dividend,int64_t divisor)
 839 {
 840   lo=dividend/divisor;
 841   hi=dividend%divisor;
 842   //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
 843   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 844 }
 845 void divu64(uint64_t dividend,uint64_t divisor)
 846 {
 847   lo=dividend/divisor;
 848   hi=dividend%divisor;
 849   //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 850   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 851 }
 852
 853 void mult64(uint64_t m1,uint64_t m2)
 854 {
 855    unsigned long long int op1, op2, op3, op4;
 856    unsigned long long int result1, result2, result3, result4;
 857    unsigned long long int temp1, temp2, temp3, temp4;
 858    int sign = 0;
 859
 860    if (m1 < 0)
 861      {
 862     op2 = -m1;
 863     sign = 1 - sign;
 864      }
 865    else op2 = m1;
 866    if (m2 < 0)
 867      {
 868     op4 = -m2;
 869     sign = 1 - sign;
 870      }
 871    else op4 = m2;
 872
 873    op1 = op2 & 0xFFFFFFFF;
 874    op2 = (op2 >> 32) & 0xFFFFFFFF;
 875    op3 = op4 & 0xFFFFFFFF;
 876    op4 = (op4 >> 32) & 0xFFFFFFFF;
 877
 878    temp1 = op1 * op3;
 879    temp2 = (temp1 >> 32) + op1 * op4;
 880    temp3 = op2 * op3;
 881    temp4 = (temp3 >> 32) + op2 * op4;
 882
 883    result1 = temp1 & 0xFFFFFFFF;
 884    result2 = temp2 + (temp3 & 0xFFFFFFFF);
 885    result3 = (result2 >> 32) + temp4;
 886    result4 = (result3 >> 32);
 887
 888    lo = result1 | (result2 << 32);
 889    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
 890    if (sign)
 891      {
 892     hi = ~hi;
 893     if (!lo) hi++;
 894     else lo = ~lo + 1;
 895      }
 896 }
 897
 898 void multu64(uint64_t m1,uint64_t m2)
 899 {
 900    unsigned long long int op1, op2, op3, op4;
 901    unsigned long long int result1, result2, result3, result4;
 902    unsigned long long int temp1, temp2, temp3, temp4;
 903
 904    op1 = m1 & 0xFFFFFFFF;
 905    op2 = (m1 >> 32) & 0xFFFFFFFF;
 906    op3 = m2 & 0xFFFFFFFF;
 907    op4 = (m2 >> 32) & 0xFFFFFFFF;
 908
 909    temp1 = op1 * op3;
 910    temp2 = (temp1 >> 32) + op1 * op4;
 911    temp3 = op2 * op3;
 912    temp4 = (temp3 >> 32) + op2 * op4;
 913
 914    result1 = temp1 & 0xFFFFFFFF;
 915    result2 = temp2 + (temp3 & 0xFFFFFFFF);
 916    result3 = (result2 >> 32) + temp4;
 917    result4 = (result3 >> 32);
 918
 919    lo = result1 | (result2 << 32);
 920    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
 921
 922   //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 923   //                                      ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 924 }
 925
 926 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
 927 {
 928   if(bits) {
 929     original<<=64-bits;
 930     original>>=64-bits;
 931     loaded<<=bits;
 932     original|=loaded;
 933   }
 934   else original=loaded;
 935   return original;
 936 }
 937 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
 938 {
 939   if(bits^56) {
 940     original>>=64-(bits^56);
 941     original<<=64-(bits^56);
 942     loaded>>=bits^56;
 943     original|=loaded;
 944   }
 945   else original=loaded;
 946   return original;
 947 }
 948
 949 #ifdef __i386__
 950 #include "assem_x86.c"
 951 #endif
 952 #ifdef __x86_64__
 953 #include "assem_x64.c"
 954 #endif
 955 #ifdef __arm__
 956 #include "assem_arm.c"
 957 #endif
 958
 959 // Add virtual address mapping to linked list
 960 void ll_add(struct ll_entry **head,int vaddr,void *addr)
 961 {
 962   struct ll_entry *new_entry;
 963   new_entry=malloc(sizeof(struct ll_entry));
 964   assert(new_entry!=NULL);
 965   new_entry->vaddr=vaddr;
 966   new_entry->reg32=0;
 967   new_entry->addr=addr;
 968   new_entry->next=*head;
 969   *head=new_entry;
 970 }
 971
 972 // Add virtual address mapping for 32-bit compiled block
 973 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
 974 {
 975   ll_add(head,vaddr,addr);
 976 #ifndef FORCE32
 977   (*head)->reg32=reg32;
 978 #endif
 979 }
 980
 981 // Check if an address is already compiled
 982 // but don't return addresses which are about to expire from the cache
 983 void *check_addr(u_int vaddr)
 984 {
 985   u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 986   if(ht_bin[0]==vaddr) {
 987     if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 988       if(isclean(ht_bin[1])) return (void *)ht_bin[1];
 989   }
 990   if(ht_bin[2]==vaddr) {
 991     if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 992       if(isclean(ht_bin[3])) return (void *)ht_bin[3];
 993   }
 994   u_int page=get_page(vaddr);
 995   struct ll_entry *head;
 996   head=jump_in[page];
 997   while(head!=NULL) {
 998     if(head->vaddr==vaddr&&head->reg32==0) {
 999       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1000         // Update existing entry with current address
1001         if(ht_bin[0]==vaddr) {
1002           ht_bin[1]=(int)head->addr;
1003           return head->addr;
1004         }
1005         if(ht_bin[2]==vaddr) {
1006           ht_bin[3]=(int)head->addr;
1007           return head->addr;
1008         }
1009         // Insert into hash table with low priority.
1010         // Don't evict existing entries, as they are probably
1011         // addresses that are being accessed frequently.
1012         if(ht_bin[0]==-1) {
1013           ht_bin[1]=(int)head->addr;
1014           ht_bin[0]=vaddr;
1015         }else if(ht_bin[2]==-1) {
1016           ht_bin[3]=(int)head->addr;
1017           ht_bin[2]=vaddr;
1018         }
1019         return head->addr;
1020       }
1021     }
1022     head=head->next;
1023   }
1024   return 0;
1025 }
1026
1027 void remove_hash(int vaddr)
1028 {
1029   //printf("remove hash: %x\n",vaddr);
1030   int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1031   if(ht_bin[2]==vaddr) {
1032     ht_bin[2]=ht_bin[3]=-1;
1033   }
1034   if(ht_bin[0]==vaddr) {
1035     ht_bin[0]=ht_bin[2];
1036     ht_bin[1]=ht_bin[3];
1037     ht_bin[2]=ht_bin[3]=-1;
1038   }
1039 }
1040
1041 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1042 {
1043   struct ll_entry *next;
1044   while(*head) {
1045     if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1046        ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1047     {
1048       inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1049       remove_hash((*head)->vaddr);
1050       next=(*head)->next;
1051       free(*head);
1052       *head=next;
1053     }
1054     else
1055     {
1056       head=&((*head)->next);
1057     }
1058   }
1059 }
1060
1061 // Remove all entries from linked list
1062 void ll_clear(struct ll_entry **head)
1063 {
1064   struct ll_entry *cur;
1065   struct ll_entry *next;
1066   if(cur=*head) {
1067     *head=0;
1068     while(cur) {
1069       next=cur->next;
1070       free(cur);
1071       cur=next;
1072     }
1073   }
1074 }
1075
1076 // Dereference the pointers and remove if it matches
1077 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1078 {
1079   while(head) {
1080     int ptr=get_pointer(head->addr);
1081     inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1082     if(((ptr>>shift)==(addr>>shift)) ||
1083        (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1084     {
1085       inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1086       kill_pointer(head->addr);
1087     }
1088     head=head->next;
1089   }
1090 }
1091
1092 // This is called when we write to a compiled block (see do_invstub)
1093 int invalidate_page(u_int page)
1094 {
1095   int modified=0;
1096   struct ll_entry *head;
1097   struct ll_entry *next;
1098   head=jump_in[page];
1099   jump_in[page]=0;
1100   while(head!=NULL) {
1101     inv_debug("INVALIDATE: %x\n",head->vaddr);
1102     remove_hash(head->vaddr);
1103     next=head->next;
1104     free(head);
1105     head=next;
1106   }
1107   head=jump_out[page];
1108   jump_out[page]=0;
1109   while(head!=NULL) {
1110     inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1111     kill_pointer(head->addr);
1112     modified=1;
1113     next=head->next;
1114     free(head);
1115     head=next;
1116   }
1117   return modified;
1118 }
1119 void invalidate_block(u_int block)
1120 {
1121   int modified;
1122   u_int page=get_page(block<<12);
1123   u_int vpage=get_vpage(block<<12);
1124   inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1125   //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1126   u_int first,last;
1127   first=last=page;
1128   struct ll_entry *head;
1129   head=jump_dirty[vpage];
1130   //printf("page=%d vpage=%d\n",page,vpage);
1131   while(head!=NULL) {
1132     u_int start,end;
1133     if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1134       get_bounds((int)head->addr,&start,&end);
1135       //printf("start: %x end: %x\n",start,end);
1136       if(page<2048&&start>=0x80000000&&end<0x80800000) {
1137         if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1138           if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1139           if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1140         }
1141       }
1142 #ifndef DISABLE_TLB
1143       if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1144         if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1145           if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1146           if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1147         }
1148       }
1149 #endif
1150     }
1151     head=head->next;
1152   }
1153   //printf("first=%d last=%d\n",first,last);
1154   modified=invalidate_page(page);
1155   assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1156   assert(last<page+5);
1157   // Invalidate the adjacent pages if a block crosses a 4K boundary
1158   while(first<page) {
1159     invalidate_page(first);
1160     first++;
1161   }
1162   for(first=page+1;first<last;first++) {
1163     invalidate_page(first);
1164   }
1165
1166   // Don't trap writes
1167   invalid_code[block]=1;
1168 #ifndef DISABLE_TLB
1169   // If there is a valid TLB entry for this page, remove write protect
1170   if(tlb_LUT_w[block]) {
1171     assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1172     // CHECK: Is this right?
1173     memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1174     u_int real_block=tlb_LUT_w[block]>>12;
1175     invalid_code[real_block]=1;
1176     if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1177   }
1178   else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1179 #endif
1180   #ifdef __arm__
1181   if(modified)
1182     __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1183   #endif
1184   #ifdef USE_MINI_HT
1185   memset(mini_ht,-1,sizeof(mini_ht));
1186   #endif
1187 }
1188 void invalidate_addr(u_int addr)
1189 {
1190   invalidate_block(addr>>12);
1191 }
1192 void invalidate_all_pages()
1193 {
1194   u_int page,n;
1195   for(page=0;page<4096;page++)
1196     invalidate_page(page);
1197   for(page=0;page<1048576;page++)
1198     if(!invalid_code[page]) {
1199       restore_candidate[(page&2047)>>3]|=1<<(page&7);
1200       restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1201     }
1202   #ifdef __arm__
1203   __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1204   #endif
1205   #ifdef USE_MINI_HT
1206   memset(mini_ht,-1,sizeof(mini_ht));
1207   #endif
1208   #ifndef DISABLE_TLB
1209   // TLB
1210   for(page=0;page<0x100000;page++) {
1211     if(tlb_LUT_r[page]) {
1212       memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1213       if(!tlb_LUT_w[page]||!invalid_code[page])
1214         memory_map[page]|=0x40000000; // Write protect
1215     }
1216     else memory_map[page]=-1;
1217     if(page==0x80000) page=0xC0000;
1218   }
1219   tlb_hacks();
1220   #endif
1221 }
1222
1223 // Add an entry to jump_out after making a link
1224 void add_link(u_int vaddr,void *src)
1225 {
1226   u_int page=get_page(vaddr);
1227   inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1228   ll_add(jump_out+page,vaddr,src);
1229   //int ptr=get_pointer(src);
1230   //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1231 }
1232
1233 // If a code block was found to be unmodified (bit was set in
1234 // restore_candidate) and it remains unmodified (bit is clear
1235 // in invalid_code) then move the entries for that 4K page from
1236 // the dirty list to the clean list.
1237 void clean_blocks(u_int page)
1238 {
1239   struct ll_entry *head;
1240   inv_debug("INV: clean_blocks page=%d\n",page);
1241   head=jump_dirty[page];
1242   while(head!=NULL) {
1243     if(!invalid_code[head->vaddr>>12]) {
1244       // Don't restore blocks which are about to expire from the cache
1245       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1246         u_int start,end;
1247         if(verify_dirty((int)head->addr)) {
1248           //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1249           u_int i;
1250           u_int inv=0;
1251           get_bounds((int)head->addr,&start,&end);
1252           if(start-(u_int)rdram<0x800000) {
1253             for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1254               inv|=invalid_code[i];
1255             }
1256           }
1257           if((signed int)head->vaddr>=(signed int)0xC0000000) {
1258             u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1259             //printf("addr=%x start=%x end=%x\n",addr,start,end);
1260             if(addr<start||addr>=end) inv=1;
1261           }
1262           else if((signed int)head->vaddr>=(signed int)0x80800000) {
1263             inv=1;
1264           }
1265           if(!inv) {
1266             void * clean_addr=(void *)get_clean_addr((int)head->addr);
1267             if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1268               u_int ppage=page;
1269 #ifndef DISABLE_TLB
1270               if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1271 #endif
1272               inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1273               //printf("page=%x, addr=%x\n",page,head->vaddr);
1274               //assert(head->vaddr>>12==(page|0x80000));
1275               ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1276               int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1277               if(!head->reg32) {
1278                 if(ht_bin[0]==head->vaddr) {
1279                   ht_bin[1]=(int)clean_addr; // Replace existing entry
1280                 }
1281                 if(ht_bin[2]==head->vaddr) {
1282                   ht_bin[3]=(int)clean_addr; // Replace existing entry
1283                 }
1284               }
1285             }
1286           }
1287         }
1288       }
1289     }
1290     head=head->next;
1291   }
1292 }
1293
1294
1295 void mov_alloc(struct regstat *current,int i)
1296 {
1297   // Note: Don't need to actually alloc the source registers
1298   if((~current->is32>>rs1[i])&1) {
1299     //alloc_reg64(current,i,rs1[i]);
1300     alloc_reg64(current,i,rt1[i]);
1301     current->is32&=~(1LL<<rt1[i]);
1302   } else {
1303     //alloc_reg(current,i,rs1[i]);
1304     alloc_reg(current,i,rt1[i]);
1305     current->is32|=(1LL<<rt1[i]);
1306   }
1307   clear_const(current,rs1[i]);
1308   clear_const(current,rt1[i]);
1309   dirty_reg(current,rt1[i]);
1310 }
1311
1312 void shiftimm_alloc(struct regstat *current,int i)
1313 {
1314   clear_const(current,rs1[i]);
1315   clear_const(current,rt1[i]);
1316   if(opcode2[i]<=0x3) // SLL/SRL/SRA
1317   {
1318     if(rt1[i]) {
1319       if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1320       else lt1[i]=rs1[i];
1321       alloc_reg(current,i,rt1[i]);
1322       current->is32|=1LL<<rt1[i];
1323       dirty_reg(current,rt1[i]);
1324     }
1325   }
1326   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1327   {
1328     if(rt1[i]) {
1329       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1330       alloc_reg64(current,i,rt1[i]);
1331       current->is32&=~(1LL<<rt1[i]);
1332       dirty_reg(current,rt1[i]);
1333     }
1334   }
1335   if(opcode2[i]==0x3c) // DSLL32
1336   {
1337     if(rt1[i]) {
1338       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1339       alloc_reg64(current,i,rt1[i]);
1340       current->is32&=~(1LL<<rt1[i]);
1341       dirty_reg(current,rt1[i]);
1342     }
1343   }
1344   if(opcode2[i]==0x3e) // DSRL32
1345   {
1346     if(rt1[i]) {
1347       alloc_reg64(current,i,rs1[i]);
1348       if(imm[i]==32) {
1349         alloc_reg64(current,i,rt1[i]);
1350         current->is32&=~(1LL<<rt1[i]);
1351       } else {
1352         alloc_reg(current,i,rt1[i]);
1353         current->is32|=1LL<<rt1[i];
1354       }
1355       dirty_reg(current,rt1[i]);
1356     }
1357   }
1358   if(opcode2[i]==0x3f) // DSRA32
1359   {
1360     if(rt1[i]) {
1361       alloc_reg64(current,i,rs1[i]);
1362       alloc_reg(current,i,rt1[i]);
1363       current->is32|=1LL<<rt1[i];
1364       dirty_reg(current,rt1[i]);
1365     }
1366   }
1367 }
1368
1369 void shift_alloc(struct regstat *current,int i)
1370 {
1371   if(rt1[i]) {
1372     if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1373     {
1374       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1375       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1376       alloc_reg(current,i,rt1[i]);
1377       if(rt1[i]==rs2[i]) alloc_reg_temp(current,i,-1);
1378       current->is32|=1LL<<rt1[i];
1379     } else { // DSLLV/DSRLV/DSRAV
1380       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1381       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1382       alloc_reg64(current,i,rt1[i]);
1383       current->is32&=~(1LL<<rt1[i]);
1384       if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1385         alloc_reg_temp(current,i,-1);
1386     }
1387     clear_const(current,rs1[i]);
1388     clear_const(current,rs2[i]);
1389     clear_const(current,rt1[i]);
1390     dirty_reg(current,rt1[i]);
1391   }
1392 }
1393
1394 void alu_alloc(struct regstat *current,int i)
1395 {
1396   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1397     if(rt1[i]) {
1398       if(rs1[i]&&rs2[i]) {
1399         alloc_reg(current,i,rs1[i]);
1400         alloc_reg(current,i,rs2[i]);
1401       }
1402       else {
1403         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1404         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1405       }
1406       alloc_reg(current,i,rt1[i]);
1407     }
1408     current->is32|=1LL<<rt1[i];
1409   }
1410   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1411     if(rt1[i]) {
1412       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1413       {
1414         alloc_reg64(current,i,rs1[i]);
1415         alloc_reg64(current,i,rs2[i]);
1416         alloc_reg(current,i,rt1[i]);
1417       } else {
1418         alloc_reg(current,i,rs1[i]);
1419         alloc_reg(current,i,rs2[i]);
1420         alloc_reg(current,i,rt1[i]);
1421       }
1422     }
1423     current->is32|=1LL<<rt1[i];
1424   }
1425   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1426     if(rt1[i]) {
1427       if(rs1[i]&&rs2[i]) {
1428         alloc_reg(current,i,rs1[i]);
1429         alloc_reg(current,i,rs2[i]);
1430       }
1431       else
1432       {
1433         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1434         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1435       }
1436       alloc_reg(current,i,rt1[i]);
1437       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1438       {
1439         if(!((current->uu>>rt1[i])&1)) {
1440           alloc_reg64(current,i,rt1[i]);
1441         }
1442         if(get_reg(current->regmap,rt1[i]|64)>=0) {
1443           if(rs1[i]&&rs2[i]) {
1444             alloc_reg64(current,i,rs1[i]);
1445             alloc_reg64(current,i,rs2[i]);
1446           }
1447           else
1448           {
1449             // Is is really worth it to keep 64-bit values in registers?
1450             #ifdef NATIVE_64BIT
1451             if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1452             if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1453             #endif
1454           }
1455         }
1456         current->is32&=~(1LL<<rt1[i]);
1457       } else {
1458         current->is32|=1LL<<rt1[i];
1459       }
1460     }
1461   }
1462   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1463     if(rt1[i]) {
1464       if(rs1[i]&&rs2[i]) {
1465         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1466           alloc_reg64(current,i,rs1[i]);
1467           alloc_reg64(current,i,rs2[i]);
1468           alloc_reg64(current,i,rt1[i]);
1469         } else {
1470           alloc_reg(current,i,rs1[i]);
1471           alloc_reg(current,i,rs2[i]);
1472           alloc_reg(current,i,rt1[i]);
1473         }
1474       }
1475       else {
1476         alloc_reg(current,i,rt1[i]);
1477         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1478           // DADD used as move, or zeroing
1479           // If we have a 64-bit source, then make the target 64 bits too
1480           if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1481             if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1482             alloc_reg64(current,i,rt1[i]);
1483           } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1484             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1485             alloc_reg64(current,i,rt1[i]);
1486           }
1487           if(opcode2[i]>=0x2e&&rs2[i]) {
1488             // DSUB used as negation - 64-bit result
1489             // If we have a 32-bit register, extend it to 64 bits
1490             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1491             alloc_reg64(current,i,rt1[i]);
1492           }
1493         }
1494       }
1495       if(rs1[i]&&rs2[i]) {
1496         current->is32&=~(1LL<<rt1[i]);
1497       } else if(rs1[i]) {
1498         current->is32&=~(1LL<<rt1[i]);
1499         if((current->is32>>rs1[i])&1)
1500           current->is32|=1LL<<rt1[i];
1501       } else if(rs2[i]) {
1502         current->is32&=~(1LL<<rt1[i]);
1503         if((current->is32>>rs2[i])&1)
1504           current->is32|=1LL<<rt1[i];
1505       } else {
1506         current->is32|=1LL<<rt1[i];
1507       }
1508     }
1509   }
1510   clear_const(current,rs1[i]);
1511   clear_const(current,rs2[i]);
1512   clear_const(current,rt1[i]);
1513   dirty_reg(current,rt1[i]);
1514 }
1515
1516 void imm16_alloc(struct regstat *current,int i)
1517 {
1518   if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1519   else lt1[i]=rs1[i];
1520   if(rt1[i]) alloc_reg(current,i,rt1[i]);
1521   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1522     current->is32&=~(1LL<<rt1[i]);
1523     if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1524       // TODO: Could preserve the 32-bit flag if the immediate is zero
1525       alloc_reg64(current,i,rt1[i]);
1526       alloc_reg64(current,i,rs1[i]);
1527     }
1528     clear_const(current,rs1[i]);
1529     clear_const(current,rt1[i]);
1530   }
1531   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1532     if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1533     current->is32|=1LL<<rt1[i];
1534     clear_const(current,rs1[i]);
1535     clear_const(current,rt1[i]);
1536   }
1537   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1538     if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1539       if(rs1[i]!=rt1[i]) {
1540         if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1541         alloc_reg64(current,i,rt1[i]);
1542         current->is32&=~(1LL<<rt1[i]);
1543       }
1544     }
1545     else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1546     if(is_const(current,rs1[i])) {
1547       int v=get_const(current,rs1[i]);
1548       if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1549       if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1550       if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1551     }
1552     else clear_const(current,rt1[i]);
1553   }
1554   else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1555     if(is_const(current,rs1[i])) {
1556       int v=get_const(current,rs1[i]);
1557       set_const(current,rt1[i],v+imm[i]);
1558     }
1559     else clear_const(current,rt1[i]);
1560     current->is32|=1LL<<rt1[i];
1561   }
1562   else {
1563     set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1564     current->is32|=1LL<<rt1[i];
1565   }
1566   dirty_reg(current,rt1[i]);
1567 }
1568
1569 void load_alloc(struct regstat *current,int i)
1570 {
1571   clear_const(current,rt1[i]);
1572   //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1573   if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1574   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1575   if(rt1[i]) {
1576     alloc_reg(current,i,rt1[i]);
1577     if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1578     {
1579       current->is32&=~(1LL<<rt1[i]);
1580       alloc_reg64(current,i,rt1[i]);
1581     }
1582     else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1583     {
1584       current->is32&=~(1LL<<rt1[i]);
1585       alloc_reg64(current,i,rt1[i]);
1586       alloc_all(current,i);
1587       alloc_reg64(current,i,FTEMP);
1588     }
1589     else current->is32|=1LL<<rt1[i];
1590     dirty_reg(current,rt1[i]);
1591     // If using TLB, need a register for pointer to the mapping table
1592     if(using_tlb) alloc_reg(current,i,TLREG);
1593     // LWL/LWR need a temporary register for the old value
1594     if(opcode[i]==0x22||opcode[i]==0x26)
1595     {
1596       alloc_reg(current,i,FTEMP);
1597       alloc_reg_temp(current,i,-1);
1598     }
1599   }
1600   else
1601   {
1602     // Load to r0 (dummy load)
1603     // but we still need a register to calculate the address
1604     alloc_reg_temp(current,i,-1);
1605   }
1606 }
1607
1608 void store_alloc(struct regstat *current,int i)
1609 {
1610   clear_const(current,rs2[i]);
1611   if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1612   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1613   alloc_reg(current,i,rs2[i]);
1614   if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1615     alloc_reg64(current,i,rs2[i]);
1616     if(rs2[i]) alloc_reg(current,i,FTEMP);
1617   }
1618   // If using TLB, need a register for pointer to the mapping table
1619   if(using_tlb) alloc_reg(current,i,TLREG);
1620   #if defined(HOST_IMM8)
1621   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1622   else alloc_reg(current,i,INVCP);
1623   #endif
1624   if(opcode[i]==0x2c||opcode[i]==0x2d) { // 64-bit SDL/SDR
1625     alloc_reg(current,i,FTEMP);
1626   }
1627   // We need a temporary register for address generation
1628   alloc_reg_temp(current,i,-1);
1629 }
1630
1631 void c1ls_alloc(struct regstat *current,int i)
1632 {
1633   //clear_const(current,rs1[i]); // FIXME
1634   clear_const(current,rt1[i]);
1635   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1636   alloc_reg(current,i,CSREG); // Status
1637   alloc_reg(current,i,FTEMP);
1638   if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1639     alloc_reg64(current,i,FTEMP);
1640   }
1641   // If using TLB, need a register for pointer to the mapping table
1642   if(using_tlb) alloc_reg(current,i,TLREG);
1643   #if defined(HOST_IMM8)
1644   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1645   else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1646     alloc_reg(current,i,INVCP);
1647   #endif
1648   // We need a temporary register for address generation
1649   alloc_reg_temp(current,i,-1);
1650 }
1651
1652 void c2ls_alloc(struct regstat *current,int i)
1653 {
1654   clear_const(current,rt1[i]);
1655   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1656   alloc_reg(current,i,FTEMP);
1657   // If using TLB, need a register for pointer to the mapping table
1658   if(using_tlb) alloc_reg(current,i,TLREG);
1659   #if defined(HOST_IMM8)
1660   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1661   else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1662     alloc_reg(current,i,INVCP);
1663   #endif
1664   // We need a temporary register for address generation
1665   alloc_reg_temp(current,i,-1);
1666 }
1667
1668 #ifndef multdiv_alloc
1669 void multdiv_alloc(struct regstat *current,int i)
1670 {
1671   //  case 0x18: MULT
1672   //  case 0x19: MULTU
1673   //  case 0x1A: DIV
1674   //  case 0x1B: DIVU
1675   //  case 0x1C: DMULT
1676   //  case 0x1D: DMULTU
1677   //  case 0x1E: DDIV
1678   //  case 0x1F: DDIVU
1679   clear_const(current,rs1[i]);
1680   clear_const(current,rs2[i]);
1681   if(rs1[i]&&rs2[i])
1682   {
1683     if((opcode2[i]&4)==0) // 32-bit
1684     {
1685       current->u&=~(1LL<<HIREG);
1686       current->u&=~(1LL<<LOREG);
1687       alloc_reg(current,i,HIREG);
1688       alloc_reg(current,i,LOREG);
1689       alloc_reg(current,i,rs1[i]);
1690       alloc_reg(current,i,rs2[i]);
1691       current->is32|=1LL<<HIREG;
1692       current->is32|=1LL<<LOREG;
1693       dirty_reg(current,HIREG);
1694       dirty_reg(current,LOREG);
1695     }
1696     else // 64-bit
1697     {
1698       current->u&=~(1LL<<HIREG);
1699       current->u&=~(1LL<<LOREG);
1700       current->uu&=~(1LL<<HIREG);
1701       current->uu&=~(1LL<<LOREG);
1702       alloc_reg64(current,i,HIREG);
1703       //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1704       alloc_reg64(current,i,rs1[i]);
1705       alloc_reg64(current,i,rs2[i]);
1706       alloc_all(current,i);
1707       current->is32&=~(1LL<<HIREG);
1708       current->is32&=~(1LL<<LOREG);
1709       dirty_reg(current,HIREG);
1710       dirty_reg(current,LOREG);
1711     }
1712   }
1713   else
1714   {
1715     // Multiply by zero is zero.
1716     // MIPS does not have a divide by zero exception.
1717     // The result is undefined, we return zero.
1718     alloc_reg(current,i,HIREG);
1719     alloc_reg(current,i,LOREG);
1720     current->is32|=1LL<<HIREG;
1721     current->is32|=1LL<<LOREG;
1722     dirty_reg(current,HIREG);
1723     dirty_reg(current,LOREG);
1724   }
1725 }
1726 #endif
1727
1728 void cop0_alloc(struct regstat *current,int i)
1729 {
1730   if(opcode2[i]==0) // MFC0
1731   {
1732     if(rt1[i]) {
1733       clear_const(current,rt1[i]);
1734       alloc_all(current,i);
1735       alloc_reg(current,i,rt1[i]);
1736       current->is32|=1LL<<rt1[i];
1737       dirty_reg(current,rt1[i]);
1738     }
1739   }
1740   else if(opcode2[i]==4) // MTC0
1741   {
1742     if(rs1[i]){
1743       clear_const(current,rs1[i]);
1744       alloc_reg(current,i,rs1[i]);
1745       alloc_all(current,i);
1746     }
1747     else {
1748       alloc_all(current,i); // FIXME: Keep r0
1749       current->u&=~1LL;
1750       alloc_reg(current,i,0);
1751     }
1752   }
1753   else
1754   {
1755     // TLBR/TLBWI/TLBWR/TLBP/ERET
1756     assert(opcode2[i]==0x10);
1757     alloc_all(current,i);
1758   }
1759 }
1760
1761 void cop1_alloc(struct regstat *current,int i)
1762 {
1763   alloc_reg(current,i,CSREG); // Load status
1764   if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1765   {
1766     assert(rt1[i]);
1767     clear_const(current,rt1[i]);
1768     if(opcode2[i]==1) {
1769       alloc_reg64(current,i,rt1[i]); // DMFC1
1770       current->is32&=~(1LL<<rt1[i]);
1771     }else{
1772       alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1773       current->is32|=1LL<<rt1[i];
1774     }
1775     dirty_reg(current,rt1[i]);
1776     alloc_reg_temp(current,i,-1);
1777   }
1778   else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1779   {
1780     if(rs1[i]){
1781       clear_const(current,rs1[i]);
1782       if(opcode2[i]==5)
1783         alloc_reg64(current,i,rs1[i]); // DMTC1
1784       else
1785         alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1786       alloc_reg_temp(current,i,-1);
1787     }
1788     else {
1789       current->u&=~1LL;
1790       alloc_reg(current,i,0);
1791       alloc_reg_temp(current,i,-1);
1792     }
1793   }
1794 }
1795 void fconv_alloc(struct regstat *current,int i)
1796 {
1797   alloc_reg(current,i,CSREG); // Load status
1798   alloc_reg_temp(current,i,-1);
1799 }
1800 void float_alloc(struct regstat *current,int i)
1801 {
1802   alloc_reg(current,i,CSREG); // Load status
1803   alloc_reg_temp(current,i,-1);
1804 }
1805 void c2op_alloc(struct regstat *current,int i)
1806 {
1807   alloc_reg_temp(current,i,-1);
1808 }
1809 void fcomp_alloc(struct regstat *current,int i)
1810 {
1811   alloc_reg(current,i,CSREG); // Load status
1812   alloc_reg(current,i,FSREG); // Load flags
1813   dirty_reg(current,FSREG); // Flag will be modified
1814   alloc_reg_temp(current,i,-1);
1815 }
1816
1817 void syscall_alloc(struct regstat *current,int i)
1818 {
1819   alloc_cc(current,i);
1820   dirty_reg(current,CCREG);
1821   alloc_all(current,i);
1822   current->isconst=0;
1823 }
1824
1825 void delayslot_alloc(struct regstat *current,int i)
1826 {
1827   switch(itype[i]) {
1828     case UJUMP:
1829     case CJUMP:
1830     case SJUMP:
1831     case RJUMP:
1832     case FJUMP:
1833     case SYSCALL:
1834     case HLECALL:
1835     case SPAN:
1836       assem_debug("jump in the delay slot.  this shouldn't happen.\n");//exit(1);
1837       printf("Disabled speculative precompilation\n");
1838       stop_after_jal=1;
1839       break;
1840     case IMM16:
1841       imm16_alloc(current,i);
1842       break;
1843     case LOAD:
1844     case LOADLR:
1845       load_alloc(current,i);
1846       break;
1847     case STORE:
1848     case STORELR:
1849       store_alloc(current,i);
1850       break;
1851     case ALU:
1852       alu_alloc(current,i);
1853       break;
1854     case SHIFT:
1855       shift_alloc(current,i);
1856       break;
1857     case MULTDIV:
1858       multdiv_alloc(current,i);
1859       break;
1860     case SHIFTIMM:
1861       shiftimm_alloc(current,i);
1862       break;
1863     case MOV:
1864       mov_alloc(current,i);
1865       break;
1866     case COP0:
1867       cop0_alloc(current,i);
1868       break;
1869     case COP1:
1870     case COP2:
1871       cop1_alloc(current,i);
1872       break;
1873     case C1LS:
1874       c1ls_alloc(current,i);
1875       break;
1876     case C2LS:
1877       c2ls_alloc(current,i);
1878       break;
1879     case FCONV:
1880       fconv_alloc(current,i);
1881       break;
1882     case FLOAT:
1883       float_alloc(current,i);
1884       break;
1885     case FCOMP:
1886       fcomp_alloc(current,i);
1887       break;
1888     case C2OP:
1889       c2op_alloc(current,i);
1890       break;
1891   }
1892 }
1893
1894 // Special case where a branch and delay slot span two pages in virtual memory
1895 static void pagespan_alloc(struct regstat *current,int i)
1896 {
1897   current->isconst=0;
1898   current->wasconst=0;
1899   regs[i].wasconst=0;
1900   alloc_all(current,i);
1901   alloc_cc(current,i);
1902   dirty_reg(current,CCREG);
1903   if(opcode[i]==3) // JAL
1904   {
1905     alloc_reg(current,i,31);
1906     dirty_reg(current,31);
1907   }
1908   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1909   {
1910     alloc_reg(current,i,rs1[i]);
1911     if (rt1[i]!=0) {
1912       alloc_reg(current,i,rt1[i]);
1913       dirty_reg(current,rt1[i]);
1914     }
1915   }
1916   if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1917   {
1918     if(rs1[i]) alloc_reg(current,i,rs1[i]);
1919     if(rs2[i]) alloc_reg(current,i,rs2[i]);
1920     if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1921     {
1922       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1923       if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1924     }
1925   }
1926   else
1927   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1928   {
1929     if(rs1[i]) alloc_reg(current,i,rs1[i]);
1930     if(!((current->is32>>rs1[i])&1))
1931     {
1932       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1933     }
1934   }
1935   else
1936   if(opcode[i]==0x11) // BC1
1937   {
1938     alloc_reg(current,i,FSREG);
1939     alloc_reg(current,i,CSREG);
1940   }
1941   //else ...
1942 }
1943
1944 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
1945 {
1946   stubs[stubcount][0]=type;
1947   stubs[stubcount][1]=addr;
1948   stubs[stubcount][2]=retaddr;
1949   stubs[stubcount][3]=a;
1950   stubs[stubcount][4]=b;
1951   stubs[stubcount][5]=c;
1952   stubs[stubcount][6]=d;
1953   stubs[stubcount][7]=e;
1954   stubcount++;
1955 }
1956
1957 // Write out a single register
1958 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
1959 {
1960   int hr;
1961   for(hr=0;hr<HOST_REGS;hr++) {
1962     if(hr!=EXCLUDE_REG) {
1963       if((regmap[hr]&63)==r) {
1964         if((dirty>>hr)&1) {
1965           if(regmap[hr]<64) {
1966             emit_storereg(r,hr);
1967 #ifndef FORCE32
1968             if((is32>>regmap[hr])&1) {
1969               emit_sarimm(hr,31,hr);
1970               emit_storereg(r|64,hr);
1971             }
1972 #endif
1973           }else{
1974             emit_storereg(r|64,hr);
1975           }
1976         }
1977       }
1978     }
1979   }
1980 }
1981
1982 int mchecksum()
1983 {
1984   //if(!tracedebug) return 0;
1985   int i;
1986   int sum=0;
1987   for(i=0;i<2097152;i++) {
1988     unsigned int temp=sum;
1989     sum<<=1;
1990     sum|=(~temp)>>31;
1991     sum^=((u_int *)rdram)[i];
1992   }
1993   return sum;
1994 }
1995 int rchecksum()
1996 {
1997   int i;
1998   int sum=0;
1999   for(i=0;i<64;i++)
2000     sum^=((u_int *)reg)[i];
2001   return sum;
2002 }
2003 void rlist()
2004 {
2005   int i;
2006   printf("TRACE: ");
2007   for(i=0;i<32;i++)
2008     printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2009   printf("\n");
2010 #ifndef DISABLE_COP1
2011   printf("TRACE: ");
2012   for(i=0;i<32;i++)
2013     printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2014   printf("\n");
2015 #endif
2016 }
2017
2018 void enabletrace()
2019 {
2020   tracedebug=1;
2021 }
2022
2023 void memdebug(int i)
2024 {
2025   //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2026   //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2027   //rlist();
2028   //if(tracedebug) {
2029   //if(Count>=-2084597794) {
2030   if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2031   //if(0) {
2032     printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2033     //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2034     //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2035     rlist();
2036     #ifdef __i386__
2037     printf("TRACE: %x\n",(&i)[-1]);
2038     #endif
2039     #ifdef __arm__
2040     int j;
2041     printf("TRACE: %x \n",(&j)[10]);
2042     printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2043     #endif
2044     //fflush(stdout);
2045   }
2046   //printf("TRACE: %x\n",(&i)[-1]);
2047 }
2048
2049 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2050 {
2051   printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2052 }
2053
2054 void alu_assemble(int i,struct regstat *i_regs)
2055 {
2056   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2057     if(rt1[i]) {
2058       signed char s1,s2,t;
2059       t=get_reg(i_regs->regmap,rt1[i]);
2060       if(t>=0) {
2061         s1=get_reg(i_regs->regmap,rs1[i]);
2062         s2=get_reg(i_regs->regmap,rs2[i]);
2063         if(rs1[i]&&rs2[i]) {
2064           assert(s1>=0);
2065           assert(s2>=0);
2066           if(opcode2[i]&2) emit_sub(s1,s2,t);
2067           else emit_add(s1,s2,t);
2068         }
2069         else if(rs1[i]) {
2070           if(s1>=0) emit_mov(s1,t);
2071           else emit_loadreg(rs1[i],t);
2072         }
2073         else if(rs2[i]) {
2074           if(s2>=0) {
2075             if(opcode2[i]&2) emit_neg(s2,t);
2076             else emit_mov(s2,t);
2077           }
2078           else {
2079             emit_loadreg(rs2[i],t);
2080             if(opcode2[i]&2) emit_neg(t,t);
2081           }
2082         }
2083         else emit_zeroreg(t);
2084       }
2085     }
2086   }
2087   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2088     if(rt1[i]) {
2089       signed char s1l,s2l,s1h,s2h,tl,th;
2090       tl=get_reg(i_regs->regmap,rt1[i]);
2091       th=get_reg(i_regs->regmap,rt1[i]|64);
2092       if(tl>=0) {
2093         s1l=get_reg(i_regs->regmap,rs1[i]);
2094         s2l=get_reg(i_regs->regmap,rs2[i]);
2095         s1h=get_reg(i_regs->regmap,rs1[i]|64);
2096         s2h=get_reg(i_regs->regmap,rs2[i]|64);
2097         if(rs1[i]&&rs2[i]) {
2098           assert(s1l>=0);
2099           assert(s2l>=0);
2100           if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2101           else emit_adds(s1l,s2l,tl);
2102           if(th>=0) {
2103             #ifdef INVERTED_CARRY
2104             if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2105             #else
2106             if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2107             #endif
2108             else emit_add(s1h,s2h,th);
2109           }
2110         }
2111         else if(rs1[i]) {
2112           if(s1l>=0) emit_mov(s1l,tl);
2113           else emit_loadreg(rs1[i],tl);
2114           if(th>=0) {
2115             if(s1h>=0) emit_mov(s1h,th);
2116             else emit_loadreg(rs1[i]|64,th);
2117           }
2118         }
2119         else if(rs2[i]) {
2120           if(s2l>=0) {
2121             if(opcode2[i]&2) emit_negs(s2l,tl);
2122             else emit_mov(s2l,tl);
2123           }
2124           else {
2125             emit_loadreg(rs2[i],tl);
2126             if(opcode2[i]&2) emit_negs(tl,tl);
2127           }
2128           if(th>=0) {
2129             #ifdef INVERTED_CARRY
2130             if(s2h>=0) emit_mov(s2h,th);
2131             else emit_loadreg(rs2[i]|64,th);
2132             if(opcode2[i]&2) {
2133               emit_adcimm(-1,th); // x86 has inverted carry flag
2134               emit_not(th,th);
2135             }
2136             #else
2137             if(opcode2[i]&2) {
2138               if(s2h>=0) emit_rscimm(s2h,0,th);
2139               else {
2140                 emit_loadreg(rs2[i]|64,th);
2141                 emit_rscimm(th,0,th);
2142               }
2143             }else{
2144               if(s2h>=0) emit_mov(s2h,th);
2145               else emit_loadreg(rs2[i]|64,th);
2146             }
2147             #endif
2148           }
2149         }
2150         else {
2151           emit_zeroreg(tl);
2152           if(th>=0) emit_zeroreg(th);
2153         }
2154       }
2155     }
2156   }
2157   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2158     if(rt1[i]) {
2159       signed char s1l,s1h,s2l,s2h,t;
2160       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2161       {
2162         t=get_reg(i_regs->regmap,rt1[i]);
2163         //assert(t>=0);
2164         if(t>=0) {
2165           s1l=get_reg(i_regs->regmap,rs1[i]);
2166           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2167           s2l=get_reg(i_regs->regmap,rs2[i]);
2168           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2169           if(rs2[i]==0) // rx<r0
2170           {
2171             assert(s1h>=0);
2172             if(opcode2[i]==0x2a) // SLT
2173               emit_shrimm(s1h,31,t);
2174             else // SLTU (unsigned can not be less than zero)
2175               emit_zeroreg(t);
2176           }
2177           else if(rs1[i]==0) // r0<rx
2178           {
2179             assert(s2h>=0);
2180             if(opcode2[i]==0x2a) // SLT
2181               emit_set_gz64_32(s2h,s2l,t);
2182             else // SLTU (set if not zero)
2183               emit_set_nz64_32(s2h,s2l,t);
2184           }
2185           else {
2186             assert(s1l>=0);assert(s1h>=0);
2187             assert(s2l>=0);assert(s2h>=0);
2188             if(opcode2[i]==0x2a) // SLT
2189               emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2190             else // SLTU
2191               emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2192           }
2193         }
2194       } else {
2195         t=get_reg(i_regs->regmap,rt1[i]);
2196         //assert(t>=0);
2197         if(t>=0) {
2198           s1l=get_reg(i_regs->regmap,rs1[i]);
2199           s2l=get_reg(i_regs->regmap,rs2[i]);
2200           if(rs2[i]==0) // rx<r0
2201           {
2202             assert(s1l>=0);
2203             if(opcode2[i]==0x2a) // SLT
2204               emit_shrimm(s1l,31,t);
2205             else // SLTU (unsigned can not be less than zero)
2206               emit_zeroreg(t);
2207           }
2208           else if(rs1[i]==0) // r0<rx
2209           {
2210             assert(s2l>=0);
2211             if(opcode2[i]==0x2a) // SLT
2212               emit_set_gz32(s2l,t);
2213             else // SLTU (set if not zero)
2214               emit_set_nz32(s2l,t);
2215           }
2216           else{
2217             assert(s1l>=0);assert(s2l>=0);
2218             if(opcode2[i]==0x2a) // SLT
2219               emit_set_if_less32(s1l,s2l,t);
2220             else // SLTU
2221               emit_set_if_carry32(s1l,s2l,t);
2222           }
2223         }
2224       }
2225     }
2226   }
2227   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2228     if(rt1[i]) {
2229       signed char s1l,s1h,s2l,s2h,th,tl;
2230       tl=get_reg(i_regs->regmap,rt1[i]);
2231       th=get_reg(i_regs->regmap,rt1[i]|64);
2232       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2233       {
2234         assert(tl>=0);
2235         if(tl>=0) {
2236           s1l=get_reg(i_regs->regmap,rs1[i]);
2237           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2238           s2l=get_reg(i_regs->regmap,rs2[i]);
2239           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2240           if(rs1[i]&&rs2[i]) {
2241             assert(s1l>=0);assert(s1h>=0);
2242             assert(s2l>=0);assert(s2h>=0);
2243             if(opcode2[i]==0x24) { // AND
2244               emit_and(s1l,s2l,tl);
2245               emit_and(s1h,s2h,th);
2246             } else
2247             if(opcode2[i]==0x25) { // OR
2248               emit_or(s1l,s2l,tl);
2249               emit_or(s1h,s2h,th);
2250             } else
2251             if(opcode2[i]==0x26) { // XOR
2252               emit_xor(s1l,s2l,tl);
2253               emit_xor(s1h,s2h,th);
2254             } else
2255             if(opcode2[i]==0x27) { // NOR
2256               emit_or(s1l,s2l,tl);
2257               emit_or(s1h,s2h,th);
2258               emit_not(tl,tl);
2259               emit_not(th,th);
2260             }
2261           }
2262           else
2263           {
2264             if(opcode2[i]==0x24) { // AND
2265               emit_zeroreg(tl);
2266               emit_zeroreg(th);
2267             } else
2268             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2269               if(rs1[i]){
2270                 if(s1l>=0) emit_mov(s1l,tl);
2271                 else emit_loadreg(rs1[i],tl);
2272                 if(s1h>=0) emit_mov(s1h,th);
2273                 else emit_loadreg(rs1[i]|64,th);
2274               }
2275               else
2276               if(rs2[i]){
2277                 if(s2l>=0) emit_mov(s2l,tl);
2278                 else emit_loadreg(rs2[i],tl);
2279                 if(s2h>=0) emit_mov(s2h,th);
2280                 else emit_loadreg(rs2[i]|64,th);
2281               }
2282               else{
2283                 emit_zeroreg(tl);
2284                 emit_zeroreg(th);
2285               }
2286             } else
2287             if(opcode2[i]==0x27) { // NOR
2288               if(rs1[i]){
2289                 if(s1l>=0) emit_not(s1l,tl);
2290                 else{
2291                   emit_loadreg(rs1[i],tl);
2292                   emit_not(tl,tl);
2293                 }
2294                 if(s1h>=0) emit_not(s1h,th);
2295                 else{
2296                   emit_loadreg(rs1[i]|64,th);
2297                   emit_not(th,th);
2298                 }
2299               }
2300               else
2301               if(rs2[i]){
2302                 if(s2l>=0) emit_not(s2l,tl);
2303                 else{
2304                   emit_loadreg(rs2[i],tl);
2305                   emit_not(tl,tl);
2306                 }
2307                 if(s2h>=0) emit_not(s2h,th);
2308                 else{
2309                   emit_loadreg(rs2[i]|64,th);
2310                   emit_not(th,th);
2311                 }
2312               }
2313               else {
2314                 emit_movimm(-1,tl);
2315                 emit_movimm(-1,th);
2316               }
2317             }
2318           }
2319         }
2320       }
2321       else
2322       {
2323         // 32 bit
2324         if(tl>=0) {
2325           s1l=get_reg(i_regs->regmap,rs1[i]);
2326           s2l=get_reg(i_regs->regmap,rs2[i]);
2327           if(rs1[i]&&rs2[i]) {
2328             assert(s1l>=0);
2329             assert(s2l>=0);
2330             if(opcode2[i]==0x24) { // AND
2331               emit_and(s1l,s2l,tl);
2332             } else
2333             if(opcode2[i]==0x25) { // OR
2334               emit_or(s1l,s2l,tl);
2335             } else
2336             if(opcode2[i]==0x26) { // XOR
2337               emit_xor(s1l,s2l,tl);
2338             } else
2339             if(opcode2[i]==0x27) { // NOR
2340               emit_or(s1l,s2l,tl);
2341               emit_not(tl,tl);
2342             }
2343           }
2344           else
2345           {
2346             if(opcode2[i]==0x24) { // AND
2347               emit_zeroreg(tl);
2348             } else
2349             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2350               if(rs1[i]){
2351                 if(s1l>=0) emit_mov(s1l,tl);
2352                 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2353               }
2354               else
2355               if(rs2[i]){
2356                 if(s2l>=0) emit_mov(s2l,tl);
2357                 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2358               }
2359               else emit_zeroreg(tl);
2360             } else
2361             if(opcode2[i]==0x27) { // NOR
2362               if(rs1[i]){
2363                 if(s1l>=0) emit_not(s1l,tl);
2364                 else {
2365                   emit_loadreg(rs1[i],tl);
2366                   emit_not(tl,tl);
2367                 }
2368               }
2369               else
2370               if(rs2[i]){
2371                 if(s2l>=0) emit_not(s2l,tl);
2372                 else {
2373                   emit_loadreg(rs2[i],tl);
2374                   emit_not(tl,tl);
2375                 }
2376               }
2377               else emit_movimm(-1,tl);
2378             }
2379           }
2380         }
2381       }
2382     }
2383   }
2384 }
2385
2386 void imm16_assemble(int i,struct regstat *i_regs)
2387 {
2388   if (opcode[i]==0x0f) { // LUI
2389     if(rt1[i]) {
2390       signed char t;
2391       t=get_reg(i_regs->regmap,rt1[i]);
2392       //assert(t>=0);
2393       if(t>=0) {
2394         if(!((i_regs->isconst>>t)&1))
2395           emit_movimm(imm[i]<<16,t);
2396       }
2397     }
2398   }
2399   if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2400     if(rt1[i]) {
2401       signed char s,t;
2402       t=get_reg(i_regs->regmap,rt1[i]);
2403       s=get_reg(i_regs->regmap,rs1[i]);
2404       if(rs1[i]) {
2405         //assert(t>=0);
2406         //assert(s>=0);
2407         if(t>=0) {
2408           if(!((i_regs->isconst>>t)&1)) {
2409             if(s<0) {
2410               if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2411               emit_addimm(t,imm[i],t);
2412             }else{
2413               if(!((i_regs->wasconst>>s)&1))
2414                 emit_addimm(s,imm[i],t);
2415               else
2416                 emit_movimm(constmap[i][s]+imm[i],t);
2417             }
2418           }
2419         }
2420       } else {
2421         if(t>=0) {
2422           if(!((i_regs->isconst>>t)&1))
2423             emit_movimm(imm[i],t);
2424         }
2425       }
2426     }
2427   }
2428   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2429     if(rt1[i]) {
2430       signed char sh,sl,th,tl;
2431       th=get_reg(i_regs->regmap,rt1[i]|64);
2432       tl=get_reg(i_regs->regmap,rt1[i]);
2433       sh=get_reg(i_regs->regmap,rs1[i]|64);
2434       sl=get_reg(i_regs->regmap,rs1[i]);
2435       if(tl>=0) {
2436         if(rs1[i]) {
2437           assert(sh>=0);
2438           assert(sl>=0);
2439           if(th>=0) {
2440             emit_addimm64_32(sh,sl,imm[i],th,tl);
2441           }
2442           else {
2443             emit_addimm(sl,imm[i],tl);
2444           }
2445         } else {
2446           emit_movimm(imm[i],tl);
2447           if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2448         }
2449       }
2450     }
2451   }
2452   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2453     if(rt1[i]) {
2454       //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2455       signed char sh,sl,t;
2456       t=get_reg(i_regs->regmap,rt1[i]);
2457       sh=get_reg(i_regs->regmap,rs1[i]|64);
2458       sl=get_reg(i_regs->regmap,rs1[i]);
2459       //assert(t>=0);
2460       if(t>=0) {
2461         if(rs1[i]>0) {
2462           if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2463           if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2464             if(opcode[i]==0x0a) { // SLTI
2465               if(sl<0) {
2466                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2467                 emit_slti32(t,imm[i],t);
2468               }else{
2469                 emit_slti32(sl,imm[i],t);
2470               }
2471             }
2472             else { // SLTIU
2473               if(sl<0) {
2474                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2475                 emit_sltiu32(t,imm[i],t);
2476               }else{
2477                 emit_sltiu32(sl,imm[i],t);
2478               }
2479             }
2480           }else{ // 64-bit
2481             assert(sl>=0);
2482             if(opcode[i]==0x0a) // SLTI
2483               emit_slti64_32(sh,sl,imm[i],t);
2484             else // SLTIU
2485               emit_sltiu64_32(sh,sl,imm[i],t);
2486           }
2487         }else{
2488           // SLTI(U) with r0 is just stupid,
2489           // nonetheless examples can be found
2490           if(opcode[i]==0x0a) // SLTI
2491             if(0<imm[i]) emit_movimm(1,t);
2492             else emit_zeroreg(t);
2493           else // SLTIU
2494           {
2495             if(imm[i]) emit_movimm(1,t);
2496             else emit_zeroreg(t);
2497           }
2498         }
2499       }
2500     }
2501   }
2502   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2503     if(rt1[i]) {
2504       signed char sh,sl,th,tl;
2505       th=get_reg(i_regs->regmap,rt1[i]|64);
2506       tl=get_reg(i_regs->regmap,rt1[i]);
2507       sh=get_reg(i_regs->regmap,rs1[i]|64);
2508       sl=get_reg(i_regs->regmap,rs1[i]);
2509       if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2510         if(opcode[i]==0x0c) //ANDI
2511         {
2512           if(rs1[i]) {
2513             if(sl<0) {
2514               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2515               emit_andimm(tl,imm[i],tl);
2516             }else{
2517               if(!((i_regs->wasconst>>sl)&1))
2518                 emit_andimm(sl,imm[i],tl);
2519               else
2520                 emit_movimm(constmap[i][sl]&imm[i],tl);
2521             }
2522           }
2523           else
2524             emit_zeroreg(tl);
2525           if(th>=0) emit_zeroreg(th);
2526         }
2527         else
2528         {
2529           if(rs1[i]) {
2530             if(sl<0) {
2531               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2532             }
2533             if(th>=0) {
2534               if(sh<0) {
2535                 emit_loadreg(rs1[i]|64,th);
2536               }else{
2537                 emit_mov(sh,th);
2538               }
2539             }
2540             if(opcode[i]==0x0d) //ORI
2541             if(sl<0) {
2542               emit_orimm(tl,imm[i],tl);
2543             }else{
2544               if(!((i_regs->wasconst>>sl)&1))
2545                 emit_orimm(sl,imm[i],tl);
2546               else
2547                 emit_movimm(constmap[i][sl]|imm[i],tl);
2548             }
2549             if(opcode[i]==0x0e) //XORI
2550             if(sl<0) {
2551               emit_xorimm(tl,imm[i],tl);
2552             }else{
2553               if(!((i_regs->wasconst>>sl)&1))
2554                 emit_xorimm(sl,imm[i],tl);
2555               else
2556                 emit_movimm(constmap[i][sl]^imm[i],tl);
2557             }
2558           }
2559           else {
2560             emit_movimm(imm[i],tl);
2561             if(th>=0) emit_zeroreg(th);
2562           }
2563         }
2564       }
2565     }
2566   }
2567 }
2568
2569 void shiftimm_assemble(int i,struct regstat *i_regs)
2570 {
2571   if(opcode2[i]<=0x3) // SLL/SRL/SRA
2572   {
2573     if(rt1[i]) {
2574       signed char s,t;
2575       t=get_reg(i_regs->regmap,rt1[i]);
2576       s=get_reg(i_regs->regmap,rs1[i]);
2577       //assert(t>=0);
2578       if(t>=0){
2579         if(rs1[i]==0)
2580         {
2581           emit_zeroreg(t);
2582         }
2583         else
2584         {
2585           if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2586           if(imm[i]) {
2587             if(opcode2[i]==0) // SLL
2588             {
2589               emit_shlimm(s<0?t:s,imm[i],t);
2590             }
2591             if(opcode2[i]==2) // SRL
2592             {
2593               emit_shrimm(s<0?t:s,imm[i],t);
2594             }
2595             if(opcode2[i]==3) // SRA
2596             {
2597               emit_sarimm(s<0?t:s,imm[i],t);
2598             }
2599           }else{
2600             // Shift by zero
2601             if(s>=0 && s!=t) emit_mov(s,t);
2602           }
2603         }
2604       }
2605       //emit_storereg(rt1[i],t); //DEBUG
2606     }
2607   }
2608   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2609   {
2610     if(rt1[i]) {
2611       signed char sh,sl,th,tl;
2612       th=get_reg(i_regs->regmap,rt1[i]|64);
2613       tl=get_reg(i_regs->regmap,rt1[i]);
2614       sh=get_reg(i_regs->regmap,rs1[i]|64);
2615       sl=get_reg(i_regs->regmap,rs1[i]);
2616       if(tl>=0) {
2617         if(rs1[i]==0)
2618         {
2619           emit_zeroreg(tl);
2620           if(th>=0) emit_zeroreg(th);
2621         }
2622         else
2623         {
2624           assert(sl>=0);
2625           assert(sh>=0);
2626           if(imm[i]) {
2627             if(opcode2[i]==0x38) // DSLL
2628             {
2629               if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2630               emit_shlimm(sl,imm[i],tl);
2631             }
2632             if(opcode2[i]==0x3a) // DSRL
2633             {
2634               emit_shrdimm(sl,sh,imm[i],tl);
2635               if(th>=0) emit_shrimm(sh,imm[i],th);
2636             }
2637             if(opcode2[i]==0x3b) // DSRA
2638             {
2639               emit_shrdimm(sl,sh,imm[i],tl);
2640               if(th>=0) emit_sarimm(sh,imm[i],th);
2641             }
2642           }else{
2643             // Shift by zero
2644             if(sl!=tl) emit_mov(sl,tl);
2645             if(th>=0&&sh!=th) emit_mov(sh,th);
2646           }
2647         }
2648       }
2649     }
2650   }
2651   if(opcode2[i]==0x3c) // DSLL32
2652   {
2653     if(rt1[i]) {
2654       signed char sl,tl,th;
2655       tl=get_reg(i_regs->regmap,rt1[i]);
2656       th=get_reg(i_regs->regmap,rt1[i]|64);
2657       sl=get_reg(i_regs->regmap,rs1[i]);
2658       if(th>=0||tl>=0){
2659         assert(tl>=0);
2660         assert(th>=0);
2661         assert(sl>=0);
2662         emit_mov(sl,th);
2663         emit_zeroreg(tl);
2664         if(imm[i]>32)
2665         {
2666           emit_shlimm(th,imm[i]&31,th);
2667         }
2668       }
2669     }
2670   }
2671   if(opcode2[i]==0x3e) // DSRL32
2672   {
2673     if(rt1[i]) {
2674       signed char sh,tl,th;
2675       tl=get_reg(i_regs->regmap,rt1[i]);
2676       th=get_reg(i_regs->regmap,rt1[i]|64);
2677       sh=get_reg(i_regs->regmap,rs1[i]|64);
2678       if(tl>=0){
2679         assert(sh>=0);
2680         emit_mov(sh,tl);
2681         if(th>=0) emit_zeroreg(th);
2682         if(imm[i]>32)
2683         {
2684           emit_shrimm(tl,imm[i]&31,tl);
2685         }
2686       }
2687     }
2688   }
2689   if(opcode2[i]==0x3f) // DSRA32
2690   {
2691     if(rt1[i]) {
2692       signed char sh,tl;
2693       tl=get_reg(i_regs->regmap,rt1[i]);
2694       sh=get_reg(i_regs->regmap,rs1[i]|64);
2695       if(tl>=0){
2696         assert(sh>=0);
2697         emit_mov(sh,tl);
2698         if(imm[i]>32)
2699         {
2700           emit_sarimm(tl,imm[i]&31,tl);
2701         }
2702       }
2703     }
2704   }
2705 }
2706
2707 #ifndef shift_assemble
2708 void shift_assemble(int i,struct regstat *i_regs)
2709 {
2710   printf("Need shift_assemble for this architecture.\n");
2711   exit(1);
2712 }
2713 #endif
2714
2715 void load_assemble(int i,struct regstat *i_regs)
2716 {
2717   int s,th,tl,addr,map=-1;
2718   int offset;
2719   int jaddr=0;
2720   int memtarget,c=0;
2721   u_int hr,reglist=0;
2722   th=get_reg(i_regs->regmap,rt1[i]|64);
2723   tl=get_reg(i_regs->regmap,rt1[i]);
2724   s=get_reg(i_regs->regmap,rs1[i]);
2725   offset=imm[i];
2726   for(hr=0;hr<HOST_REGS;hr++) {
2727     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2728   }
2729   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2730   if(s>=0) {
2731     c=(i_regs->wasconst>>s)&1;
2732     memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
2733     if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2734   }
2735   if(offset||s<0||c) addr=tl;
2736   else addr=s;
2737   //printf("load_assemble: c=%d\n",c);
2738   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2739   // FIXME: Even if the load is a NOP, we should check for pagefaults...
2740   if(tl>=0) {
2741     //assert(tl>=0);
2742     //assert(rt1[i]);
2743     reglist&=~(1<<tl);
2744     if(th>=0) reglist&=~(1<<th);
2745     if(!using_tlb) {
2746       if(!c) {
2747 //#define R29_HACK 1
2748         #ifdef R29_HACK
2749         // Strmnnrmn's speed hack
2750         if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
2751         #endif
2752         {
2753           emit_cmpimm(addr,0x800000);
2754           jaddr=(int)out;
2755           #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2756           // Hint to branch predictor that the branch is unlikely to be taken
2757           if(rs1[i]>=28)
2758             emit_jno_unlikely(0);
2759           else
2760           #endif
2761           emit_jno(0);
2762         }
2763       }
2764     }else{ // using tlb
2765       int x=0;
2766       if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2767       if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2768       map=get_reg(i_regs->regmap,TLREG);
2769       assert(map>=0);
2770       map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2771       do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2772     }
2773     if (opcode[i]==0x20) { // LB
2774       if(!c||memtarget) {
2775         #ifdef HOST_IMM_ADDR32
2776         if(c)
2777           emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2778         else
2779         #endif
2780         {
2781           //emit_xorimm(addr,3,tl);
2782           //gen_tlb_addr_r(tl,map);
2783           //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2784           int x=0;
2785 #ifdef BIG_ENDIAN_MIPS
2786           if(!c) emit_xorimm(addr,3,tl);
2787           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2788 #else
2789           if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2790           else if (tl!=addr) emit_mov(addr,tl);
2791 #endif
2792           emit_movsbl_indexed_tlb(x,tl,map,tl);
2793         }
2794         if(jaddr)
2795           add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2796       }
2797       else
2798         inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2799     }
2800     if (opcode[i]==0x21) { // LH
2801       if(!c||memtarget) {
2802         #ifdef HOST_IMM_ADDR32
2803         if(c)
2804           emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2805         else
2806         #endif
2807         {
2808           int x=0;
2809 #ifdef BIG_ENDIAN_MIPS
2810           if(!c) emit_xorimm(addr,2,tl);
2811           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2812 #else
2813           if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2814           else if (tl!=addr) emit_mov(addr,tl);
2815 #endif
2816           //#ifdef
2817           //emit_movswl_indexed_tlb(x,tl,map,tl);
2818           //else
2819           if(map>=0) {
2820             gen_tlb_addr_r(tl,map);
2821             emit_movswl_indexed(x,tl,tl);
2822           }else
2823             emit_movswl_indexed((int)rdram-0x80000000+x,tl,tl);
2824         }
2825         if(jaddr)
2826           add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2827       }
2828       else
2829         inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2830     }
2831     if (opcode[i]==0x23) { // LW
2832       if(!c||memtarget) {
2833         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2834         #ifdef HOST_IMM_ADDR32
2835         if(c)
2836           emit_readword_tlb(constmap[i][s]+offset,map,tl);
2837         else
2838         #endif
2839         emit_readword_indexed_tlb(0,addr,map,tl);
2840         if(jaddr)
2841           add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2842       }
2843       else
2844         inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2845     }
2846     if (opcode[i]==0x24) { // LBU
2847       if(!c||memtarget) {
2848         #ifdef HOST_IMM_ADDR32
2849         if(c)
2850           emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2851         else
2852         #endif
2853         {
2854           //emit_xorimm(addr,3,tl);
2855           //gen_tlb_addr_r(tl,map);
2856           //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
2857           int x=0;
2858 #ifdef BIG_ENDIAN_MIPS
2859           if(!c) emit_xorimm(addr,3,tl);
2860           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2861 #else
2862           if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2863           else if (tl!=addr) emit_mov(addr,tl);
2864 #endif
2865           emit_movzbl_indexed_tlb(x,tl,map,tl);
2866         }
2867         if(jaddr)
2868           add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2869       }
2870       else
2871         inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2872     }
2873     if (opcode[i]==0x25) { // LHU
2874       if(!c||memtarget) {
2875         #ifdef HOST_IMM_ADDR32
2876         if(c)
2877           emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2878         else
2879         #endif
2880         {
2881           int x=0;
2882 #ifdef BIG_ENDIAN_MIPS
2883           if(!c) emit_xorimm(addr,2,tl);
2884           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2885 #else
2886           if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2887           else if (tl!=addr) emit_mov(addr,tl);
2888 #endif
2889           //#ifdef
2890           //emit_movzwl_indexed_tlb(x,tl,map,tl);
2891           //#else
2892           if(map>=0) {
2893             gen_tlb_addr_r(tl,map);
2894             emit_movzwl_indexed(x,tl,tl);
2895           }else
2896             emit_movzwl_indexed((int)rdram-0x80000000+x,tl,tl);
2897           if(jaddr)
2898             add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2899         }
2900       }
2901       else
2902         inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2903     }
2904     if (opcode[i]==0x27) { // LWU
2905       assert(th>=0);
2906       if(!c||memtarget) {
2907         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2908         #ifdef HOST_IMM_ADDR32
2909         if(c)
2910           emit_readword_tlb(constmap[i][s]+offset,map,tl);
2911         else
2912         #endif
2913         emit_readword_indexed_tlb(0,addr,map,tl);
2914         if(jaddr)
2915           add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2916       }
2917       else {
2918         inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2919       }
2920       emit_zeroreg(th);
2921     }
2922     if (opcode[i]==0x37) { // LD
2923       if(!c||memtarget) {
2924         //gen_tlb_addr_r(tl,map);
2925         //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
2926         //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
2927         #ifdef HOST_IMM_ADDR32
2928         if(c)
2929           emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
2930         else
2931         #endif
2932         emit_readdword_indexed_tlb(0,addr,map,th,tl);
2933         if(jaddr)
2934           add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2935       }
2936       else
2937         inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2938     }
2939     //emit_storereg(rt1[i],tl); // DEBUG
2940   }
2941   //if(opcode[i]==0x23)
2942   //if(opcode[i]==0x24)
2943   //if(opcode[i]==0x23||opcode[i]==0x24)
2944   /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
2945   {
2946     //emit_pusha();
2947     save_regs(0x100f);
2948         emit_readword((int)&last_count,ECX);
2949         #ifdef __i386__
2950         if(get_reg(i_regs->regmap,CCREG)<0)
2951           emit_loadreg(CCREG,HOST_CCREG);
2952         emit_add(HOST_CCREG,ECX,HOST_CCREG);
2953         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
2954         emit_writeword(HOST_CCREG,(int)&Count);
2955         #endif
2956         #ifdef __arm__
2957         if(get_reg(i_regs->regmap,CCREG)<0)
2958           emit_loadreg(CCREG,0);
2959         else
2960           emit_mov(HOST_CCREG,0);
2961         emit_add(0,ECX,0);
2962         emit_addimm(0,2*ccadj[i],0);
2963         emit_writeword(0,(int)&Count);
2964         #endif
2965     emit_call((int)memdebug);
2966     //emit_popa();
2967     restore_regs(0x100f);
2968   }/**/
2969 }
2970
2971 #ifndef loadlr_assemble
2972 void loadlr_assemble(int i,struct regstat *i_regs)
2973 {
2974   printf("Need loadlr_assemble for this architecture.\n");
2975   exit(1);
2976 }
2977 #endif
2978
2979 void store_assemble(int i,struct regstat *i_regs)
2980 {
2981   int s,th,tl,map=-1;
2982   int addr,temp;
2983   int offset;
2984   int jaddr=0,jaddr2,type;
2985   int memtarget=0,c=0;
2986   int agr=AGEN1+(i&1);
2987   u_int hr,reglist=0;
2988   th=get_reg(i_regs->regmap,rs2[i]|64);
2989   tl=get_reg(i_regs->regmap,rs2[i]);
2990   s=get_reg(i_regs->regmap,rs1[i]);
2991   temp=get_reg(i_regs->regmap,agr);
2992   if(temp<0) temp=get_reg(i_regs->regmap,-1);
2993   offset=imm[i];
2994   if(s>=0) {
2995     c=(i_regs->wasconst>>s)&1;
2996     memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
2997     if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2998   }
2999   assert(tl>=0);
3000   assert(temp>=0);
3001   for(hr=0;hr<HOST_REGS;hr++) {
3002     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3003   }
3004   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3005   if(offset||s<0||c) addr=temp;
3006   else addr=s;
3007   if(!using_tlb) {
3008     if(!c) {
3009       #ifdef R29_HACK
3010       // Strmnnrmn's speed hack
3011       memtarget=1;
3012       if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
3013       #endif
3014       emit_cmpimm(addr,0x800000);
3015       #ifdef DESTRUCTIVE_SHIFT
3016       if(s==addr) emit_mov(s,temp);
3017       #endif
3018       #ifdef R29_HACK
3019       if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
3020       #endif
3021       {
3022         jaddr=(int)out;
3023         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3024         // Hint to branch predictor that the branch is unlikely to be taken
3025         if(rs1[i]>=28)
3026           emit_jno_unlikely(0);
3027         else
3028         #endif
3029         emit_jno(0);
3030       }
3031     }
3032   }else{ // using tlb
3033     int x=0;
3034     if (opcode[i]==0x28) x=3; // SB
3035     if (opcode[i]==0x29) x=2; // SH
3036     map=get_reg(i_regs->regmap,TLREG);
3037     assert(map>=0);
3038     map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3039     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3040   }
3041
3042   if (opcode[i]==0x28) { // SB
3043     if(!c||memtarget) {
3044       int x=0;
3045 #ifdef BIG_ENDIAN_MIPS
3046       if(!c) emit_xorimm(addr,3,temp);
3047       else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3048 #else
3049       if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3050       else if (addr!=temp) emit_mov(addr,temp);
3051 #endif
3052       //gen_tlb_addr_w(temp,map);
3053       //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3054       emit_writebyte_indexed_tlb(tl,x,temp,map,temp);
3055     }
3056     type=STOREB_STUB;
3057   }
3058   if (opcode[i]==0x29) { // SH
3059     if(!c||memtarget) {
3060       int x=0;
3061 #ifdef BIG_ENDIAN_MIPS
3062       if(!c) emit_xorimm(addr,2,temp);
3063       else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3064 #else
3065       if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3066       else if (addr!=temp) emit_mov(addr,temp);
3067 #endif
3068       //#ifdef
3069       //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3070       //#else
3071       if(map>=0) {
3072         gen_tlb_addr_w(temp,map);
3073         emit_writehword_indexed(tl,x,temp);
3074       }else
3075         emit_writehword_indexed(tl,(int)rdram-0x80000000+x,temp);
3076     }
3077     type=STOREH_STUB;
3078   }
3079   if (opcode[i]==0x2B) { // SW
3080     if(!c||memtarget)
3081       //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3082       emit_writeword_indexed_tlb(tl,0,addr,map,temp);
3083     type=STOREW_STUB;
3084   }
3085   if (opcode[i]==0x3F) { // SD
3086     if(!c||memtarget) {
3087       if(rs2[i]) {
3088         assert(th>=0);
3089         //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3090         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3091         emit_writedword_indexed_tlb(th,tl,0,addr,map,temp);
3092       }else{
3093         // Store zero
3094         //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3095         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3096         emit_writedword_indexed_tlb(tl,tl,0,addr,map,temp);
3097       }
3098     }
3099     type=STORED_STUB;
3100   }
3101   if(!using_tlb&&(!c||memtarget))
3102     // addr could be a temp, make sure it survives STORE*_STUB
3103     reglist|=1<<addr;
3104   if(jaddr) {
3105     add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3106   } else if(!memtarget) {
3107     inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3108   }
3109   if(!using_tlb) {
3110     if(!c||memtarget) {
3111       #ifdef DESTRUCTIVE_SHIFT
3112       // The x86 shift operation is 'destructive'; it overwrites the
3113       // source register, so we need to make a copy first and use that.
3114       addr=temp;
3115       #endif
3116       #if defined(HOST_IMM8)
3117       int ir=get_reg(i_regs->regmap,INVCP);
3118       assert(ir>=0);
3119       emit_cmpmem_indexedsr12_reg(ir,addr,1);
3120       #else
3121       emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3122       #endif
3123       jaddr2=(int)out;
3124       emit_jne(0);
3125       add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3126     }
3127   }
3128   //if(opcode[i]==0x2B || opcode[i]==0x3F)
3129   //if(opcode[i]==0x2B || opcode[i]==0x28)
3130   //if(opcode[i]==0x2B || opcode[i]==0x29)
3131   //if(opcode[i]==0x2B)
3132   /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3133   {
3134     //emit_pusha();
3135     save_regs(0x100f);
3136         emit_readword((int)&last_count,ECX);
3137         #ifdef __i386__
3138         if(get_reg(i_regs->regmap,CCREG)<0)
3139           emit_loadreg(CCREG,HOST_CCREG);
3140         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3141         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3142         emit_writeword(HOST_CCREG,(int)&Count);
3143         #endif
3144         #ifdef __arm__
3145         if(get_reg(i_regs->regmap,CCREG)<0)
3146           emit_loadreg(CCREG,0);
3147         else
3148           emit_mov(HOST_CCREG,0);
3149         emit_add(0,ECX,0);
3150         emit_addimm(0,2*ccadj[i],0);
3151         emit_writeword(0,(int)&Count);
3152         #endif
3153     emit_call((int)memdebug);
3154     //emit_popa();
3155     restore_regs(0x100f);
3156   }/**/
3157 }
3158
3159 void storelr_assemble(int i,struct regstat *i_regs)
3160 {
3161   int s,th,tl;
3162   int temp;
3163   int temp2;
3164   int offset;
3165   int jaddr=0,jaddr2;
3166   int case1,case2,case3;
3167   int done0,done1,done2;
3168   int memtarget,c=0;
3169   u_int hr,reglist=0;
3170   th=get_reg(i_regs->regmap,rs2[i]|64);
3171   tl=get_reg(i_regs->regmap,rs2[i]);
3172   s=get_reg(i_regs->regmap,rs1[i]);
3173   temp=get_reg(i_regs->regmap,-1);
3174   offset=imm[i];
3175   if(s>=0) {
3176     c=(i_regs->isconst>>s)&1;
3177     memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
3178     if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3179   }
3180   assert(tl>=0);
3181   for(hr=0;hr<HOST_REGS;hr++) {
3182     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3183   }
3184   if(tl>=0) {
3185     assert(temp>=0);
3186     if(!using_tlb) {
3187       if(!c) {
3188         emit_cmpimm(s<0||offset?temp:s,0x800000);
3189         if(!offset&&s!=temp) emit_mov(s,temp);
3190         jaddr=(int)out;
3191         emit_jno(0);
3192       }
3193       else
3194       {
3195         if(!memtarget||!rs1[i]) {
3196           jaddr=(int)out;
3197           emit_jmp(0);
3198         }
3199       }
3200       if((u_int)rdram!=0x80000000)
3201         emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3202     }else{ // using tlb
3203       int map=get_reg(i_regs->regmap,TLREG);
3204       assert(map>=0);
3205       map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3206       if(!c&&!offset&&s>=0) emit_mov(s,temp);
3207       do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3208       if(!jaddr&&!memtarget) {
3209         jaddr=(int)out;
3210         emit_jmp(0);
3211       }
3212       gen_tlb_addr_w(temp,map);
3213     }
3214
3215     if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3216       temp2=get_reg(i_regs->regmap,FTEMP);
3217       if(!rs2[i]) temp2=th=tl;
3218     }
3219
3220 #ifndef BIG_ENDIAN_MIPS
3221     emit_xorimm(temp,3,temp);
3222 #endif
3223     emit_testimm(temp,2);
3224     case2=(int)out;
3225     emit_jne(0);
3226     emit_testimm(temp,1);
3227     case1=(int)out;
3228     emit_jne(0);
3229     // 0
3230     if (opcode[i]==0x2A) { // SWL
3231       emit_writeword_indexed(tl,0,temp);
3232     }
3233     if (opcode[i]==0x2E) { // SWR
3234       emit_writebyte_indexed(tl,3,temp);
3235     }
3236     if (opcode[i]==0x2C) { // SDL
3237       emit_writeword_indexed(th,0,temp);
3238       if(rs2[i]) emit_mov(tl,temp2);
3239     }
3240     if (opcode[i]==0x2D) { // SDR
3241       emit_writebyte_indexed(tl,3,temp);
3242       if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3243     }
3244     done0=(int)out;
3245     emit_jmp(0);
3246     // 1
3247     set_jump_target(case1,(int)out);
3248     if (opcode[i]==0x2A) { // SWL
3249       // Write 3 msb into three least significant bytes
3250       if(rs2[i]) emit_rorimm(tl,8,tl);
3251       emit_writehword_indexed(tl,-1,temp);
3252       if(rs2[i]) emit_rorimm(tl,16,tl);
3253       emit_writebyte_indexed(tl,1,temp);
3254       if(rs2[i]) emit_rorimm(tl,8,tl);
3255     }
3256     if (opcode[i]==0x2E) { // SWR
3257       // Write two lsb into two most significant bytes
3258       emit_writehword_indexed(tl,1,temp);
3259     }
3260     if (opcode[i]==0x2C) { // SDL
3261       if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3262       // Write 3 msb into three least significant bytes
3263       if(rs2[i]) emit_rorimm(th,8,th);
3264       emit_writehword_indexed(th,-1,temp);
3265       if(rs2[i]) emit_rorimm(th,16,th);
3266       emit_writebyte_indexed(th,1,temp);
3267       if(rs2[i]) emit_rorimm(th,8,th);
3268     }
3269     if (opcode[i]==0x2D) { // SDR
3270       if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3271       // Write two lsb into two most significant bytes
3272       emit_writehword_indexed(tl,1,temp);
3273     }
3274     done1=(int)out;
3275     emit_jmp(0);
3276     // 2
3277     set_jump_target(case2,(int)out);
3278     emit_testimm(temp,1);
3279     case3=(int)out;
3280     emit_jne(0);
3281     if (opcode[i]==0x2A) { // SWL
3282       // Write two msb into two least significant bytes
3283       if(rs2[i]) emit_rorimm(tl,16,tl);
3284       emit_writehword_indexed(tl,-2,temp);
3285       if(rs2[i]) emit_rorimm(tl,16,tl);
3286     }
3287     if (opcode[i]==0x2E) { // SWR
3288       // Write 3 lsb into three most significant bytes
3289       emit_writebyte_indexed(tl,-1,temp);
3290       if(rs2[i]) emit_rorimm(tl,8,tl);
3291       emit_writehword_indexed(tl,0,temp);
3292       if(rs2[i]) emit_rorimm(tl,24,tl);
3293     }
3294     if (opcode[i]==0x2C) { // SDL
3295       if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3296       // Write two msb into two least significant bytes
3297       if(rs2[i]) emit_rorimm(th,16,th);
3298       emit_writehword_indexed(th,-2,temp);
3299       if(rs2[i]) emit_rorimm(th,16,th);
3300     }
3301     if (opcode[i]==0x2D) { // SDR
3302       if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3303       // Write 3 lsb into three most significant bytes
3304       emit_writebyte_indexed(tl,-1,temp);
3305       if(rs2[i]) emit_rorimm(tl,8,tl);
3306       emit_writehword_indexed(tl,0,temp);
3307       if(rs2[i]) emit_rorimm(tl,24,tl);
3308     }
3309     done2=(int)out;
3310     emit_jmp(0);
3311     // 3
3312     set_jump_target(case3,(int)out);
3313     if (opcode[i]==0x2A) { // SWL
3314       // Write msb into least significant byte
3315       if(rs2[i]) emit_rorimm(tl,24,tl);
3316       emit_writebyte_indexed(tl,-3,temp);
3317       if(rs2[i]) emit_rorimm(tl,8,tl);
3318     }
3319     if (opcode[i]==0x2E) { // SWR
3320       // Write entire word
3321       emit_writeword_indexed(tl,-3,temp);
3322     }
3323     if (opcode[i]==0x2C) { // SDL
3324       if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3325       // Write msb into least significant byte
3326       if(rs2[i]) emit_rorimm(th,24,th);
3327       emit_writebyte_indexed(th,-3,temp);
3328       if(rs2[i]) emit_rorimm(th,8,th);
3329     }
3330     if (opcode[i]==0x2D) { // SDR
3331       if(rs2[i]) emit_mov(th,temp2);
3332       // Write entire word
3333       emit_writeword_indexed(tl,-3,temp);
3334     }
3335     set_jump_target(done0,(int)out);
3336     set_jump_target(done1,(int)out);
3337     set_jump_target(done2,(int)out);
3338     if (opcode[i]==0x2C) { // SDL
3339       emit_testimm(temp,4);
3340       done0=(int)out;
3341       emit_jne(0);
3342       emit_andimm(temp,~3,temp);
3343       emit_writeword_indexed(temp2,4,temp);
3344       set_jump_target(done0,(int)out);
3345     }
3346     if (opcode[i]==0x2D) { // SDR
3347       emit_testimm(temp,4);
3348       done0=(int)out;
3349       emit_jeq(0);
3350       emit_andimm(temp,~3,temp);
3351       emit_writeword_indexed(temp2,-4,temp);
3352       set_jump_target(done0,(int)out);
3353     }
3354     if(!c||!memtarget)
3355       add_stub(STORELR_STUB,jaddr,(int)out,0,(int)i_regs,rs2[i],ccadj[i],reglist);
3356   }
3357   if(!using_tlb) {
3358     emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3359     #if defined(HOST_IMM8)
3360     int ir=get_reg(i_regs->regmap,INVCP);
3361     assert(ir>=0);
3362     emit_cmpmem_indexedsr12_reg(ir,temp,1);
3363     #else
3364     emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3365     #endif
3366     jaddr2=(int)out;
3367     emit_jne(0);
3368     add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3369   }
3370   /*
3371     emit_pusha();
3372     //save_regs(0x100f);
3373         emit_readword((int)&last_count,ECX);
3374         if(get_reg(i_regs->regmap,CCREG)<0)
3375           emit_loadreg(CCREG,HOST_CCREG);
3376         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3377         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3378         emit_writeword(HOST_CCREG,(int)&Count);
3379     emit_call((int)memdebug);
3380     emit_popa();
3381     //restore_regs(0x100f);
3382   /**/
3383 }
3384
3385 void c1ls_assemble(int i,struct regstat *i_regs)
3386 {
3387 #ifndef DISABLE_COP1
3388   int s,th,tl;
3389   int temp,ar;
3390   int map=-1;
3391   int offset;
3392   int c=0;
3393   int jaddr,jaddr2=0,jaddr3,type;
3394   int agr=AGEN1+(i&1);
3395   u_int hr,reglist=0;
3396   th=get_reg(i_regs->regmap,FTEMP|64);
3397   tl=get_reg(i_regs->regmap,FTEMP);
3398   s=get_reg(i_regs->regmap,rs1[i]);
3399   temp=get_reg(i_regs->regmap,agr);
3400   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3401   offset=imm[i];
3402   assert(tl>=0);
3403   assert(rs1[i]>0);
3404   assert(temp>=0);
3405   for(hr=0;hr<HOST_REGS;hr++) {
3406     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3407   }
3408   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3409   if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3410   {
3411     // Loads use a temporary register which we need to save
3412     reglist|=1<<temp;
3413   }
3414   if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3415     ar=temp;
3416   else // LWC1/LDC1
3417     ar=tl;
3418   //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3419   //else c=(i_regs->wasconst>>s)&1;
3420   if(s>=0) c=(i_regs->wasconst>>s)&1;
3421   // Check cop1 unusable
3422   if(!cop1_usable) {
3423     signed char rs=get_reg(i_regs->regmap,CSREG);
3424     assert(rs>=0);
3425     emit_testimm(rs,0x20000000);
3426     jaddr=(int)out;
3427     emit_jeq(0);
3428     add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3429     cop1_usable=1;
3430   }
3431   if (opcode[i]==0x39) { // SWC1 (get float address)
3432     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],tl);
3433   }
3434   if (opcode[i]==0x3D) { // SDC1 (get double address)
3435     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],tl);
3436   }
3437   // Generate address + offset
3438   if(!using_tlb) {
3439     if(!c)
3440       emit_cmpimm(offset||c||s<0?ar:s,0x800000);
3441   }
3442   else
3443   {
3444     map=get_reg(i_regs->regmap,TLREG);
3445     assert(map>=0);
3446     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3447       map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3448     }
3449     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3450       map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3451     }
3452   }
3453   if (opcode[i]==0x39) { // SWC1 (read float)
3454     emit_readword_indexed(0,tl,tl);
3455   }
3456   if (opcode[i]==0x3D) { // SDC1 (read double)
3457     emit_readword_indexed(4,tl,th);
3458     emit_readword_indexed(0,tl,tl);
3459   }
3460   if (opcode[i]==0x31) { // LWC1 (get target address)
3461     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],temp);
3462   }
3463   if (opcode[i]==0x35) { // LDC1 (get target address)
3464     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],temp);
3465   }
3466   if(!using_tlb) {
3467     if(!c) {
3468       jaddr2=(int)out;
3469       emit_jno(0);
3470     }
3471     else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80800000) {
3472       jaddr2=(int)out;
3473       emit_jmp(0); // inline_readstub/inline_writestub?  Very rare case
3474     }
3475     #ifdef DESTRUCTIVE_SHIFT
3476     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3477       if(!offset&&!c&&s>=0) emit_mov(s,ar);
3478     }
3479     #endif
3480   }else{
3481     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3482       do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3483     }
3484     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3485       do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3486     }
3487   }
3488   if (opcode[i]==0x31) { // LWC1
3489     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3490     //gen_tlb_addr_r(ar,map);
3491     //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3492     #ifdef HOST_IMM_ADDR32
3493     if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3494     else
3495     #endif
3496     emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3497     type=LOADW_STUB;
3498   }
3499   if (opcode[i]==0x35) { // LDC1
3500     assert(th>=0);
3501     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3502     //gen_tlb_addr_r(ar,map);
3503     //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3504     //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3505     #ifdef HOST_IMM_ADDR32
3506     if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3507     else
3508     #endif
3509     emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3510     type=LOADD_STUB;
3511   }
3512   if (opcode[i]==0x39) { // SWC1
3513     //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3514     emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3515     type=STOREW_STUB;
3516   }
3517   if (opcode[i]==0x3D) { // SDC1
3518     assert(th>=0);
3519     //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3520     //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3521     emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3522     type=STORED_STUB;
3523   }
3524   if(!using_tlb) {
3525     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3526       #ifndef DESTRUCTIVE_SHIFT
3527       temp=offset||c||s<0?ar:s;
3528       #endif
3529       #if defined(HOST_IMM8)
3530       int ir=get_reg(i_regs->regmap,INVCP);
3531       assert(ir>=0);
3532       emit_cmpmem_indexedsr12_reg(ir,temp,1);
3533       #else
3534       emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3535       #endif
3536       jaddr3=(int)out;
3537       emit_jne(0);
3538       add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3539     }
3540   }
3541   if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3542   if (opcode[i]==0x31) { // LWC1 (write float)
3543     emit_writeword_indexed(tl,0,temp);
3544   }
3545   if (opcode[i]==0x35) { // LDC1 (write double)
3546     emit_writeword_indexed(th,4,temp);
3547     emit_writeword_indexed(tl,0,temp);
3548   }
3549   //if(opcode[i]==0x39)
3550   /*if(opcode[i]==0x39||opcode[i]==0x31)
3551   {
3552     emit_pusha();
3553         emit_readword((int)&last_count,ECX);
3554         if(get_reg(i_regs->regmap,CCREG)<0)
3555           emit_loadreg(CCREG,HOST_CCREG);
3556         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3557         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3558         emit_writeword(HOST_CCREG,(int)&Count);
3559     emit_call((int)memdebug);
3560     emit_popa();
3561   }/**/
3562 #else
3563   cop1_unusable(i, i_regs);
3564 #endif
3565 }
3566
3567 void c2ls_assemble(int i,struct regstat *i_regs)
3568 {
3569   int s,tl;
3570   int ar;
3571   int offset;
3572   int c=0;
3573   int jaddr,jaddr2=0,jaddr3,type;
3574   int agr=AGEN1+(i&1);
3575   u_int hr,reglist=0;
3576   u_int copr=(source[i]>>16)&0x1f;
3577   s=get_reg(i_regs->regmap,rs1[i]);
3578   tl=get_reg(i_regs->regmap,FTEMP);
3579   offset=imm[i];
3580   assert(rs1[i]>0);
3581   assert(tl>=0);
3582   assert(!using_tlb);
3583
3584   for(hr=0;hr<HOST_REGS;hr++) {
3585     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3586   }
3587   if(i_regs->regmap[HOST_CCREG]==CCREG)
3588     reglist&=~(1<<HOST_CCREG);
3589
3590   // get the address
3591   if (opcode[i]==0x3a) { // SWC2
3592     ar=get_reg(i_regs->regmap,agr);
3593     if(ar<0) ar=get_reg(i_regs->regmap,-1);
3594     reglist|=1<<ar;
3595   } else { // LWC2
3596     ar=tl;
3597   }
3598   if (!offset&&!c&&s>=0) ar=s;
3599   assert(ar>=0);
3600
3601   if (opcode[i]==0x3a) { // SWC2
3602     cop2_get_dreg(copr,tl,HOST_TEMPREG);
3603   }
3604   if(s>=0) c=(i_regs->wasconst>>s)&1;
3605   if(!c) {
3606     emit_cmpimm(offset||c||s<0?ar:s,0x800000);
3607     jaddr2=(int)out;
3608     emit_jno(0);
3609   }
3610   else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80800000) {
3611     jaddr2=(int)out;
3612     emit_jmp(0); // inline_readstub/inline_writestub?  Very rare case
3613   }
3614   if (opcode[i]==0x32) { // LWC2
3615     #ifdef HOST_IMM_ADDR32
3616     if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3617     else
3618     #endif
3619     emit_readword_indexed(0,ar,tl);
3620     type=LOADW_STUB;
3621   }
3622   if (opcode[i]==0x3a) { // SWC2
3623 #ifdef DESTRUCTIVE_SHIFT
3624     if(!offset&&!c&&s>=0) emit_mov(s,ar);
3625 #endif
3626     emit_writeword_indexed(tl,0,ar);
3627     type=STOREW_STUB;
3628   }
3629   if(jaddr2)
3630     add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3631   if (opcode[i]==0x3a) { // SWC2
3632 #if defined(HOST_IMM8)
3633     int ir=get_reg(i_regs->regmap,INVCP);
3634     assert(ir>=0);
3635     emit_cmpmem_indexedsr12_reg(ir,ar,1);
3636 #else
3637     emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3638 #endif
3639     jaddr3=(int)out;
3640     emit_jne(0);
3641     add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3642   }
3643   if (opcode[i]==0x32) { // LWC2
3644     cop2_put_dreg(copr,tl,HOST_TEMPREG);
3645   }
3646 }
3647
3648 #ifndef multdiv_assemble
3649 void multdiv_assemble(int i,struct regstat *i_regs)
3650 {
3651   printf("Need multdiv_assemble for this architecture.\n");
3652   exit(1);
3653 }
3654 #endif
3655
3656 void mov_assemble(int i,struct regstat *i_regs)
3657 {
3658   //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3659   //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3660   assert(rt1[i]>0);
3661   if(rt1[i]) {
3662     signed char sh,sl,th,tl;
3663     th=get_reg(i_regs->regmap,rt1[i]|64);
3664     tl=get_reg(i_regs->regmap,rt1[i]);
3665     //assert(tl>=0);
3666     if(tl>=0) {
3667       sh=get_reg(i_regs->regmap,rs1[i]|64);
3668       sl=get_reg(i_regs->regmap,rs1[i]);
3669       if(sl>=0) emit_mov(sl,tl);
3670       else emit_loadreg(rs1[i],tl);
3671       if(th>=0) {
3672         if(sh>=0) emit_mov(sh,th);
3673         else emit_loadreg(rs1[i]|64,th);
3674       }
3675     }
3676   }
3677 }
3678
3679 #ifndef fconv_assemble
3680 void fconv_assemble(int i,struct regstat *i_regs)
3681 {
3682   printf("Need fconv_assemble for this architecture.\n");
3683   exit(1);
3684 }
3685 #endif
3686
3687 #if 0
3688 void float_assemble(int i,struct regstat *i_regs)
3689 {
3690   printf("Need float_assemble for this architecture.\n");
3691   exit(1);
3692 }
3693 #endif
3694
3695 void syscall_assemble(int i,struct regstat *i_regs)
3696 {
3697   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3698   assert(ccreg==HOST_CCREG);
3699   assert(!is_delayslot);
3700   emit_movimm(start+i*4,EAX); // Get PC
3701   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right?  There should probably be an extra cycle...
3702   emit_jmp((int)jump_syscall_hle); // XXX
3703 }
3704
3705 void hlecall_assemble(int i,struct regstat *i_regs)
3706 {
3707   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3708   assert(ccreg==HOST_CCREG);
3709   assert(!is_delayslot);
3710   emit_movimm(start+i*4+4,0); // Get PC
3711   emit_movimm((int)psxHLEt[source[i]&7],1);
3712   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // XXX
3713   emit_jmp((int)jump_hlecall);
3714 }
3715
3716 void ds_assemble(int i,struct regstat *i_regs)
3717 {
3718   is_delayslot=1;
3719   switch(itype[i]) {
3720     case ALU:
3721       alu_assemble(i,i_regs);break;
3722     case IMM16:
3723       imm16_assemble(i,i_regs);break;
3724     case SHIFT:
3725       shift_assemble(i,i_regs);break;
3726     case SHIFTIMM:
3727       shiftimm_assemble(i,i_regs);break;
3728     case LOAD:
3729       load_assemble(i,i_regs);break;
3730     case LOADLR:
3731       loadlr_assemble(i,i_regs);break;
3732     case STORE:
3733       store_assemble(i,i_regs);break;
3734     case STORELR:
3735       storelr_assemble(i,i_regs);break;
3736     case COP0:
3737       cop0_assemble(i,i_regs);break;
3738     case COP1:
3739       cop1_assemble(i,i_regs);break;
3740     case C1LS:
3741       c1ls_assemble(i,i_regs);break;
3742     case COP2:
3743       cop2_assemble(i,i_regs);break;
3744     case C2LS:
3745       c2ls_assemble(i,i_regs);break;
3746     case C2OP:
3747       c2op_assemble(i,i_regs);break;
3748     case FCONV:
3749       fconv_assemble(i,i_regs);break;
3750     case FLOAT:
3751       float_assemble(i,i_regs);break;
3752     case FCOMP:
3753       fcomp_assemble(i,i_regs);break;
3754     case MULTDIV:
3755       multdiv_assemble(i,i_regs);break;
3756     case MOV:
3757       mov_assemble(i,i_regs);break;
3758     case SYSCALL:
3759     case HLECALL:
3760     case SPAN:
3761     case UJUMP:
3762     case RJUMP:
3763     case CJUMP:
3764     case SJUMP:
3765     case FJUMP:
3766       printf("Jump in the delay slot.  This is probably a bug.\n");
3767   }
3768   is_delayslot=0;
3769 }
3770
3771 // Is the branch target a valid internal jump?
3772 int internal_branch(uint64_t i_is32,int addr)
3773 {
3774   if(addr&1) return 0; // Indirect (register) jump
3775   if(addr>=start && addr<start+slen*4-4)
3776   {
3777     int t=(addr-start)>>2;
3778     // Delay slots are not valid branch targets
3779     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
3780     // 64 -> 32 bit transition requires a recompile
3781     /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
3782     {
3783       if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
3784       else printf("optimizable: yes\n");
3785     }*/
3786     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
3787     if(requires_32bit[t]&~i_is32) return 0;
3788     else return 1;
3789   }
3790   return 0;
3791 }
3792
3793 #ifndef wb_invalidate
3794 void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
3795   uint64_t u,uint64_t uu)
3796 {
3797   int hr;
3798   for(hr=0;hr<HOST_REGS;hr++) {
3799     if(hr!=EXCLUDE_REG) {
3800       if(pre[hr]!=entry[hr]) {
3801         if(pre[hr]>=0) {
3802           if((dirty>>hr)&1) {
3803             if(get_reg(entry,pre[hr])<0) {
3804               if(pre[hr]<64) {
3805                 if(!((u>>pre[hr])&1)) {
3806                   emit_storereg(pre[hr],hr);
3807                   if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
3808                     emit_sarimm(hr,31,hr);
3809                     emit_storereg(pre[hr]|64,hr);
3810                   }
3811                 }
3812               }else{
3813                 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
3814                   emit_storereg(pre[hr],hr);
3815                 }
3816               }
3817             }
3818           }
3819         }
3820       }
3821     }
3822   }
3823   // Move from one register to another (no writeback)
3824   for(hr=0;hr<HOST_REGS;hr++) {
3825     if(hr!=EXCLUDE_REG) {
3826       if(pre[hr]!=entry[hr]) {
3827         if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
3828           int nr;
3829           if((nr=get_reg(entry,pre[hr]))>=0) {
3830             emit_mov(hr,nr);
3831           }
3832         }
3833       }
3834     }
3835   }
3836 }
3837 #endif
3838
3839 // Load the specified registers
3840 // This only loads the registers given as arguments because
3841 // we don't want to load things that will be overwritten
3842 void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
3843 {
3844   int hr;
3845   // Load 32-bit regs
3846   for(hr=0;hr<HOST_REGS;hr++) {
3847     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
3848       if(entry[hr]!=regmap[hr]) {
3849         if(regmap[hr]==rs1||regmap[hr]==rs2)
3850         {
3851           if(regmap[hr]==0) {
3852             emit_zeroreg(hr);
3853           }
3854           else
3855           {
3856             emit_loadreg(regmap[hr],hr);
3857           }
3858         }
3859       }
3860     }
3861   }
3862   //Load 64-bit regs
3863   for(hr=0;hr<HOST_REGS;hr++) {
3864     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
3865       if(entry[hr]!=regmap[hr]) {
3866         if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
3867         {
3868           assert(regmap[hr]!=64);
3869           if((is32>>(regmap[hr]&63))&1) {
3870             int lr=get_reg(regmap,regmap[hr]-64);
3871             if(lr>=0)
3872               emit_sarimm(lr,31,hr);
3873             else
3874               emit_loadreg(regmap[hr],hr);
3875           }
3876           else
3877           {
3878             emit_loadreg(regmap[hr],hr);
3879           }
3880         }
3881       }
3882     }
3883   }
3884 }
3885
3886 // Load registers prior to the start of a loop
3887 // so that they are not loaded within the loop
3888 static void loop_preload(signed char pre[],signed char entry[])
3889 {
3890   int hr;
3891   for(hr=0;hr<HOST_REGS;hr++) {
3892     if(hr!=EXCLUDE_REG) {
3893       if(pre[hr]!=entry[hr]) {
3894         if(entry[hr]>=0) {
3895           if(get_reg(pre,entry[hr])<0) {
3896             assem_debug("loop preload:\n");
3897             //printf("loop preload: %d\n",hr);
3898             if(entry[hr]==0) {
3899               emit_zeroreg(hr);
3900             }
3901             else if(entry[hr]<TEMPREG)
3902             {
3903               emit_loadreg(entry[hr],hr);
3904             }
3905             else if(entry[hr]-64<TEMPREG)
3906             {
3907               emit_loadreg(entry[hr],hr);
3908             }
3909           }
3910         }
3911       }
3912     }
3913   }
3914 }
3915
3916 // Generate address for load/store instruction
3917 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
3918 void address_generation(int i,struct regstat *i_regs,signed char entry[])
3919 {
3920   if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
3921     int ra;
3922     int agr=AGEN1+(i&1);
3923     int mgr=MGEN1+(i&1);
3924     if(itype[i]==LOAD) {
3925       ra=get_reg(i_regs->regmap,rt1[i]);
3926       //if(rt1[i]) assert(ra>=0);
3927     }
3928     if(itype[i]==LOADLR) {
3929       ra=get_reg(i_regs->regmap,FTEMP);
3930     }
3931     if(itype[i]==STORE||itype[i]==STORELR) {
3932       ra=get_reg(i_regs->regmap,agr);
3933       if(ra<0) ra=get_reg(i_regs->regmap,-1);
3934     }
3935     if(itype[i]==C1LS||itype[i]==C2LS) {
3936       if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
3937         ra=get_reg(i_regs->regmap,FTEMP);
3938       else { // SWC1/SDC1
3939         ra=get_reg(i_regs->regmap,agr);
3940         if(ra<0) ra=get_reg(i_regs->regmap,-1);
3941       }
3942     }
3943     int rs=get_reg(i_regs->regmap,rs1[i]);
3944     int rm=get_reg(i_regs->regmap,TLREG);
3945     if(ra>=0) {
3946       int offset=imm[i];
3947       int c=(i_regs->wasconst>>rs)&1;
3948       if(rs1[i]==0) {
3949         // Using r0 as a base address
3950         /*if(rm>=0) {
3951           if(!entry||entry[rm]!=mgr) {
3952             generate_map_const(offset,rm);
3953           } // else did it in the previous cycle
3954         }*/
3955         if(!entry||entry[ra]!=agr) {
3956           if (opcode[i]==0x22||opcode[i]==0x26) {
3957             emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
3958           }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
3959             emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
3960           }else{
3961             emit_movimm(offset,ra);
3962           }
3963         } // else did it in the previous cycle
3964       }
3965       else if(rs<0) {
3966         if(!entry||entry[ra]!=rs1[i])
3967           emit_loadreg(rs1[i],ra);
3968         //if(!entry||entry[ra]!=rs1[i])
3969         //  printf("poor load scheduling!\n");
3970       }
3971       else if(c) {
3972         if(rm>=0) {
3973           if(!entry||entry[rm]!=mgr) {
3974             if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
3975               // Stores to memory go thru the mapper to detect self-modifying
3976               // code, loads don't.
3977               if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
3978                  (unsigned int)(constmap[i][rs]+offset)<0x80800000 )
3979                 generate_map_const(constmap[i][rs]+offset,rm);
3980             }else{
3981               if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
3982                 generate_map_const(constmap[i][rs]+offset,rm);
3983             }
3984           }
3985         }
3986         if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
3987           if(!entry||entry[ra]!=agr) {
3988             if (opcode[i]==0x22||opcode[i]==0x26) {
3989               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
3990             }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
3991               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
3992             }else{
3993               #ifdef HOST_IMM_ADDR32
3994               if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
3995                  (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
3996               #endif
3997               emit_movimm(constmap[i][rs]+offset,ra);
3998             }
3999           } // else did it in the previous cycle
4000         } // else load_consts already did it
4001       }
4002       if(offset&&!c&&rs1[i]) {
4003         if(rs>=0) {
4004           emit_addimm(rs,offset,ra);
4005         }else{
4006           emit_addimm(ra,offset,ra);
4007         }
4008       }
4009     }
4010   }
4011   // Preload constants for next instruction
4012   if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
4013     int agr,ra;
4014     #ifndef HOST_IMM_ADDR32
4015     // Mapper entry
4016     agr=MGEN1+((i+1)&1);
4017     ra=get_reg(i_regs->regmap,agr);
4018     if(ra>=0) {
4019       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4020       int offset=imm[i+1];
4021       int c=(regs[i+1].wasconst>>rs)&1;
4022       if(c) {
4023         if(itype[i+1]==STORE||itype[i+1]==STORELR
4024            ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
4025           // Stores to memory go thru the mapper to detect self-modifying
4026           // code, loads don't.
4027           if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4028              (unsigned int)(constmap[i+1][rs]+offset)<0x80800000 )
4029             generate_map_const(constmap[i+1][rs]+offset,ra);
4030         }else{
4031           if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4032             generate_map_const(constmap[i+1][rs]+offset,ra);
4033         }
4034       }
4035       /*else if(rs1[i]==0) {
4036         generate_map_const(offset,ra);
4037       }*/
4038     }
4039     #endif
4040     // Actual address
4041     agr=AGEN1+((i+1)&1);
4042     ra=get_reg(i_regs->regmap,agr);
4043     if(ra>=0) {
4044       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4045       int offset=imm[i+1];
4046       int c=(regs[i+1].wasconst>>rs)&1;
4047       if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4048         if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4049           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4050         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4051           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4052         }else{
4053           #ifdef HOST_IMM_ADDR32
4054           if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4055              (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4056           #endif
4057           emit_movimm(constmap[i+1][rs]+offset,ra);
4058         }
4059       }
4060       else if(rs1[i+1]==0) {
4061         // Using r0 as a base address
4062         if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4063           emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4064         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4065           emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4066         }else{
4067           emit_movimm(offset,ra);
4068         }
4069       }
4070     }
4071   }
4072 }
4073
4074 int get_final_value(int hr, int i, int *value)
4075 {
4076   int reg=regs[i].regmap[hr];
4077   while(i<slen-1) {
4078     if(regs[i+1].regmap[hr]!=reg) break;
4079     if(!((regs[i+1].isconst>>hr)&1)) break;
4080     if(bt[i+1]) break;
4081     i++;
4082   }
4083   if(i<slen-1) {
4084     if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4085       *value=constmap[i][hr];
4086       return 1;
4087     }
4088     if(!bt[i+1]) {
4089       if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4090         // Load in delay slot, out-of-order execution
4091         if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4092         {
4093           #ifdef HOST_IMM_ADDR32
4094           if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4095           #endif
4096           // Precompute load address
4097           *value=constmap[i][hr]+imm[i+2];
4098           return 1;
4099         }
4100       }
4101       if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4102       {
4103         #ifdef HOST_IMM_ADDR32
4104         if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4105         #endif
4106         // Precompute load address
4107         *value=constmap[i][hr]+imm[i+1];
4108         //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4109         return 1;
4110       }
4111     }
4112   }
4113   *value=constmap[i][hr];
4114   //printf("c=%x\n",(int)constmap[i][hr]);
4115   if(i==slen-1) return 1;
4116   if(reg<64) {
4117     return !((unneeded_reg[i+1]>>reg)&1);
4118   }else{
4119     return !((unneeded_reg_upper[i+1]>>reg)&1);
4120   }
4121 }
4122
4123 // Load registers with known constants
4124 void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4125 {
4126   int hr;
4127   // Load 32-bit regs
4128   for(hr=0;hr<HOST_REGS;hr++) {
4129     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4130       //if(entry[hr]!=regmap[hr]) {
4131       if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4132         if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4133           int value;
4134           if(get_final_value(hr,i,&value)) {
4135             if(value==0) {
4136               emit_zeroreg(hr);
4137             }
4138             else {
4139               emit_movimm(value,hr);
4140             }
4141           }
4142         }
4143       }
4144     }
4145   }
4146   // Load 64-bit regs
4147   for(hr=0;hr<HOST_REGS;hr++) {
4148     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4149       //if(entry[hr]!=regmap[hr]) {
4150       if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4151         if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4152           if((is32>>(regmap[hr]&63))&1) {
4153             int lr=get_reg(regmap,regmap[hr]-64);
4154             assert(lr>=0);
4155             emit_sarimm(lr,31,hr);
4156           }
4157           else
4158           {
4159             int value;
4160             if(get_final_value(hr,i,&value)) {
4161               if(value==0) {
4162                 emit_zeroreg(hr);
4163               }
4164               else {
4165                 emit_movimm(value,hr);
4166               }
4167             }
4168           }
4169         }
4170       }
4171     }
4172   }
4173 }
4174 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4175 {
4176   int hr;
4177   // Load 32-bit regs
4178   for(hr=0;hr<HOST_REGS;hr++) {
4179     if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4180       if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4181         int value=constmap[i][hr];
4182         if(value==0) {
4183           emit_zeroreg(hr);
4184         }
4185         else {
4186           emit_movimm(value,hr);
4187         }
4188       }
4189     }
4190   }
4191   // Load 64-bit regs
4192   for(hr=0;hr<HOST_REGS;hr++) {
4193     if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4194       if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4195         if((is32>>(regmap[hr]&63))&1) {
4196           int lr=get_reg(regmap,regmap[hr]-64);
4197           assert(lr>=0);
4198           emit_sarimm(lr,31,hr);
4199         }
4200         else
4201         {
4202           int value=constmap[i][hr];
4203           if(value==0) {
4204             emit_zeroreg(hr);
4205           }
4206           else {
4207             emit_movimm(value,hr);
4208           }
4209         }
4210       }
4211     }
4212   }
4213 }
4214
4215 // Write out all dirty registers (except cycle count)
4216 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4217 {
4218   int hr;
4219   for(hr=0;hr<HOST_REGS;hr++) {
4220     if(hr!=EXCLUDE_REG) {
4221       if(i_regmap[hr]>0) {
4222         if(i_regmap[hr]!=CCREG) {
4223           if((i_dirty>>hr)&1) {
4224             if(i_regmap[hr]<64) {
4225               emit_storereg(i_regmap[hr],hr);
4226 #ifndef FORCE32
4227               if( ((i_is32>>i_regmap[hr])&1) ) {
4228                 #ifdef DESTRUCTIVE_WRITEBACK
4229                 emit_sarimm(hr,31,hr);
4230                 emit_storereg(i_regmap[hr]|64,hr);
4231                 #else
4232                 emit_sarimm(hr,31,HOST_TEMPREG);
4233                 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4234                 #endif
4235               }
4236 #endif
4237             }else{
4238               if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4239                 emit_storereg(i_regmap[hr],hr);
4240               }
4241             }
4242           }
4243         }
4244       }
4245     }
4246   }
4247 }
4248 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4249 // This writes the registers not written by store_regs_bt
4250 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4251 {
4252   int hr;
4253   int t=(addr-start)>>2;
4254   for(hr=0;hr<HOST_REGS;hr++) {
4255     if(hr!=EXCLUDE_REG) {
4256       if(i_regmap[hr]>0) {
4257         if(i_regmap[hr]!=CCREG) {
4258           if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4259             if((i_dirty>>hr)&1) {
4260               if(i_regmap[hr]<64) {
4261                 emit_storereg(i_regmap[hr],hr);
4262 #ifndef FORCE32
4263                 if( ((i_is32>>i_regmap[hr])&1) ) {
4264                   #ifdef DESTRUCTIVE_WRITEBACK
4265                   emit_sarimm(hr,31,hr);
4266                   emit_storereg(i_regmap[hr]|64,hr);
4267                   #else
4268                   emit_sarimm(hr,31,HOST_TEMPREG);
4269                   emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4270                   #endif
4271                 }
4272 #endif
4273               }else{
4274                 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4275                   emit_storereg(i_regmap[hr],hr);
4276                 }
4277               }
4278             }
4279           }
4280         }
4281       }
4282     }
4283   }
4284 }
4285
4286 // Load all registers (except cycle count)
4287 void load_all_regs(signed char i_regmap[])
4288 {
4289   int hr;
4290   for(hr=0;hr<HOST_REGS;hr++) {
4291     if(hr!=EXCLUDE_REG) {
4292       if(i_regmap[hr]==0) {
4293         emit_zeroreg(hr);
4294       }
4295       else
4296       if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG)
4297       {
4298         emit_loadreg(i_regmap[hr],hr);
4299       }
4300     }
4301   }
4302 }
4303
4304 // Load all current registers also needed by next instruction
4305 void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4306 {
4307   int hr;
4308   for(hr=0;hr<HOST_REGS;hr++) {
4309     if(hr!=EXCLUDE_REG) {
4310       if(get_reg(next_regmap,i_regmap[hr])>=0) {
4311         if(i_regmap[hr]==0) {
4312           emit_zeroreg(hr);
4313         }
4314         else
4315         if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG)
4316         {
4317           emit_loadreg(i_regmap[hr],hr);
4318         }
4319       }
4320     }
4321   }
4322 }
4323
4324 // Load all regs, storing cycle count if necessary
4325 void load_regs_entry(int t)
4326 {
4327   int hr;
4328   if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER,HOST_CCREG);
4329   else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t]*CLOCK_DIVIDER,HOST_CCREG);
4330   if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4331     emit_storereg(CCREG,HOST_CCREG);
4332   }
4333   // Load 32-bit regs
4334   for(hr=0;hr<HOST_REGS;hr++) {
4335     if(regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<64) {
4336       if(regs[t].regmap_entry[hr]==0) {
4337         emit_zeroreg(hr);
4338       }
4339       else if(regs[t].regmap_entry[hr]!=CCREG)
4340       {
4341         emit_loadreg(regs[t].regmap_entry[hr],hr);
4342       }
4343     }
4344   }
4345   // Load 64-bit regs
4346   for(hr=0;hr<HOST_REGS;hr++) {
4347     if(regs[t].regmap_entry[hr]>=64) {
4348       assert(regs[t].regmap_entry[hr]!=64);
4349       if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4350         int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4351         if(lr<0) {
4352           emit_loadreg(regs[t].regmap_entry[hr],hr);
4353         }
4354         else
4355         {
4356           emit_sarimm(lr,31,hr);
4357         }
4358       }
4359       else
4360       {
4361         emit_loadreg(regs[t].regmap_entry[hr],hr);
4362       }
4363     }
4364   }
4365 }
4366
4367 // Store dirty registers prior to branch
4368 void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4369 {
4370   if(internal_branch(i_is32,addr))
4371   {
4372     int t=(addr-start)>>2;
4373     int hr;
4374     for(hr=0;hr<HOST_REGS;hr++) {
4375       if(hr!=EXCLUDE_REG) {
4376         if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4377           if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4378             if((i_dirty>>hr)&1) {
4379               if(i_regmap[hr]<64) {
4380                 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4381                   emit_storereg(i_regmap[hr],hr);
4382                   if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4383                     #ifdef DESTRUCTIVE_WRITEBACK
4384                     emit_sarimm(hr,31,hr);
4385                     emit_storereg(i_regmap[hr]|64,hr);
4386                     #else
4387                     emit_sarimm(hr,31,HOST_TEMPREG);
4388                     emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4389                     #endif
4390                   }
4391                 }
4392               }else{
4393                 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4394                   emit_storereg(i_regmap[hr],hr);
4395                 }
4396               }
4397             }
4398           }
4399         }
4400       }
4401     }
4402   }
4403   else
4404   {
4405     // Branch out of this block, write out all dirty regs
4406     wb_dirtys(i_regmap,i_is32,i_dirty);
4407   }
4408 }
4409
4410 // Load all needed registers for branch target
4411 void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4412 {
4413   //if(addr>=start && addr<(start+slen*4))
4414   if(internal_branch(i_is32,addr))
4415   {
4416     int t=(addr-start)>>2;
4417     int hr;
4418     // Store the cycle count before loading something else
4419     if(i_regmap[HOST_CCREG]!=CCREG) {
4420       assert(i_regmap[HOST_CCREG]==-1);
4421     }
4422     if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4423       emit_storereg(CCREG,HOST_CCREG);
4424     }
4425     // Load 32-bit regs
4426     for(hr=0;hr<HOST_REGS;hr++) {
4427       if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<64) {
4428         #ifdef DESTRUCTIVE_WRITEBACK
4429         if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4430         #else
4431         if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4432         #endif
4433           if(regs[t].regmap_entry[hr]==0) {
4434             emit_zeroreg(hr);
4435           }
4436           else if(regs[t].regmap_entry[hr]!=CCREG)
4437           {
4438             emit_loadreg(regs[t].regmap_entry[hr],hr);
4439           }
4440         }
4441       }
4442     }
4443     //Load 64-bit regs
4444     for(hr=0;hr<HOST_REGS;hr++) {
4445       if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=64) {
4446         if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4447           assert(regs[t].regmap_entry[hr]!=64);
4448           if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4449             int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4450             if(lr<0) {
4451               emit_loadreg(regs[t].regmap_entry[hr],hr);
4452             }
4453             else
4454             {
4455               emit_sarimm(lr,31,hr);
4456             }
4457           }
4458           else
4459           {
4460             emit_loadreg(regs[t].regmap_entry[hr],hr);
4461           }
4462         }
4463         else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4464           int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4465           assert(lr>=0);
4466           emit_sarimm(lr,31,hr);
4467         }
4468       }
4469     }
4470   }
4471 }
4472
4473 int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4474 {
4475   if(addr>=start && addr<start+slen*4-4)
4476   {
4477     int t=(addr-start)>>2;
4478     int hr;
4479     if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4480     for(hr=0;hr<HOST_REGS;hr++)
4481     {
4482       if(hr!=EXCLUDE_REG)
4483       {
4484         if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4485         {
4486           if(regs[t].regmap_entry[hr]!=-1)
4487           {
4488             return 0;
4489           }
4490           else
4491           if((i_dirty>>hr)&1)
4492           {
4493             if(i_regmap[hr]<64)
4494             {
4495               if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4496                 return 0;
4497             }
4498             else
4499             {
4500               if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4501                 return 0;
4502             }
4503           }
4504         }
4505         else // Same register but is it 32-bit or dirty?
4506         if(i_regmap[hr]>=0)
4507         {
4508           if(!((regs[t].dirty>>hr)&1))
4509           {
4510             if((i_dirty>>hr)&1)
4511             {
4512               if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4513               {
4514                 //printf("%x: dirty no match\n",addr);
4515                 return 0;
4516               }
4517             }
4518           }
4519           if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4520           {
4521             //printf("%x: is32 no match\n",addr);
4522             return 0;
4523           }
4524         }
4525       }
4526     }
4527     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4528     if(requires_32bit[t]&~i_is32) return 0;
4529     // Delay slots are not valid branch targets
4530     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4531     // Delay slots require additional processing, so do not match
4532     if(is_ds[t]) return 0;
4533   }
4534   else
4535   {
4536     int hr;
4537     for(hr=0;hr<HOST_REGS;hr++)
4538     {
4539       if(hr!=EXCLUDE_REG)
4540       {
4541         if(i_regmap[hr]>=0)
4542         {
4543           if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4544           {
4545             if((i_dirty>>hr)&1)
4546             {
4547               return 0;
4548             }
4549           }
4550         }
4551       }
4552     }
4553   }
4554   return 1;
4555 }
4556
4557 // Used when a branch jumps into the delay slot of another branch
4558 void ds_assemble_entry(int i)
4559 {
4560   int t=(ba[i]-start)>>2;
4561   if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4562   assem_debug("Assemble delay slot at %x\n",ba[i]);
4563   assem_debug("<->\n");
4564   if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
4565     wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4566   load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4567   address_generation(t,&regs[t],regs[t].regmap_entry);
4568   if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
4569     load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4570   cop1_usable=0;
4571   is_delayslot=0;
4572   switch(itype[t]) {
4573     case ALU:
4574       alu_assemble(t,&regs[t]);break;
4575     case IMM16:
4576       imm16_assemble(t,&regs[t]);break;
4577     case SHIFT:
4578       shift_assemble(t,&regs[t]);break;
4579     case SHIFTIMM:
4580       shiftimm_assemble(t,&regs[t]);break;
4581     case LOAD:
4582       load_assemble(t,&regs[t]);break;
4583     case LOADLR:
4584       loadlr_assemble(t,&regs[t]);break;
4585     case STORE:
4586       store_assemble(t,&regs[t]);break;
4587     case STORELR:
4588       storelr_assemble(t,&regs[t]);break;
4589     case COP0:
4590       cop0_assemble(t,&regs[t]);break;
4591     case COP1:
4592       cop1_assemble(t,&regs[t]);break;
4593     case C1LS:
4594       c1ls_assemble(t,&regs[t]);break;
4595     case COP2:
4596       cop2_assemble(t,&regs[t]);break;
4597     case C2LS:
4598       c2ls_assemble(t,&regs[t]);break;
4599     case C2OP:
4600       c2op_assemble(t,&regs[t]);break;
4601     case FCONV:
4602       fconv_assemble(t,&regs[t]);break;
4603     case FLOAT:
4604       float_assemble(t,&regs[t]);break;
4605     case FCOMP:
4606       fcomp_assemble(t,&regs[t]);break;
4607     case MULTDIV:
4608       multdiv_assemble(t,&regs[t]);break;
4609     case MOV:
4610       mov_assemble(t,&regs[t]);break;
4611     case SYSCALL:
4612     case HLECALL:
4613     case SPAN:
4614     case UJUMP:
4615     case RJUMP:
4616     case CJUMP:
4617     case SJUMP:
4618     case FJUMP:
4619       printf("Jump in the delay slot.  This is probably a bug.\n");
4620   }
4621   store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4622   load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4623   if(internal_branch(regs[t].is32,ba[i]+4))
4624     assem_debug("branch: internal\n");
4625   else
4626     assem_debug("branch: external\n");
4627   assert(internal_branch(regs[t].is32,ba[i]+4));
4628   add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4629   emit_jmp(0);
4630 }
4631
4632 void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4633 {
4634   int count;
4635   int jaddr;
4636   int idle=0;
4637   if(itype[i]==RJUMP)
4638   {
4639     *adj=0;
4640   }
4641   //if(ba[i]>=start && ba[i]<(start+slen*4))
4642   if(internal_branch(branch_regs[i].is32,ba[i]))
4643   {
4644     int t=(ba[i]-start)>>2;
4645     if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4646     else *adj=ccadj[t];
4647   }
4648   else
4649   {
4650     *adj=0;
4651   }
4652   count=ccadj[i];
4653   if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4654     // Idle loop
4655     if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4656     idle=(int)out;
4657     //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4658     emit_andimm(HOST_CCREG,3,HOST_CCREG);
4659     jaddr=(int)out;
4660     emit_jmp(0);
4661   }
4662   else if(*adj==0||invert) {
4663     emit_addimm_and_set_flags(CLOCK_DIVIDER*(count+2),HOST_CCREG);
4664     jaddr=(int)out;
4665     emit_jns(0);
4666   }
4667   else
4668   {
4669     emit_cmpimm(HOST_CCREG,-2*(count+2));
4670     jaddr=(int)out;
4671     emit_jns(0);
4672   }
4673   add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4674 }
4675
4676 void do_ccstub(int n)
4677 {
4678   literal_pool(256);
4679   assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
4680   set_jump_target(stubs[n][1],(int)out);
4681   int i=stubs[n][4];
4682   if(stubs[n][6]==NULLDS) {
4683     // Delay slot instruction is nullified ("likely" branch)
4684     wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4685   }
4686   else if(stubs[n][6]!=TAKEN) {
4687     wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4688   }
4689   else {
4690     if(internal_branch(branch_regs[i].is32,ba[i]))
4691       wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4692   }
4693   if(stubs[n][5]!=-1)
4694   {
4695     // Save PC as return address
4696     emit_movimm(stubs[n][5],EAX);
4697     emit_writeword(EAX,(int)&pcaddr);
4698   }
4699   else
4700   {
4701     // Return address depends on which way the branch goes
4702     if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
4703     {
4704       int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4705       int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4706       int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4707       int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4708       if(rs1[i]==0)
4709       {
4710         s1l=s2l;s1h=s2h;
4711         s2l=s2h=-1;
4712       }
4713       else if(rs2[i]==0)
4714       {
4715         s2l=s2h=-1;
4716       }
4717       if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
4718         s1h=s2h=-1;
4719       }
4720       assert(s1l>=0);
4721       #ifdef DESTRUCTIVE_WRITEBACK
4722       if(rs1[i]) {
4723         if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
4724           emit_loadreg(rs1[i],s1l);
4725       }
4726       else {
4727         if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
4728           emit_loadreg(rs2[i],s1l);
4729       }
4730       if(s2l>=0)
4731         if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
4732           emit_loadreg(rs2[i],s2l);
4733       #endif
4734       int hr=0;
4735       int addr,alt,ntaddr;
4736       while(hr<HOST_REGS)
4737       {
4738         if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4739            (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4740            (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4741         {
4742           addr=hr++;break;
4743         }
4744         hr++;
4745       }
4746       while(hr<HOST_REGS)
4747       {
4748         if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4749            (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4750            (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4751         {
4752           alt=hr++;break;
4753         }
4754         hr++;
4755       }
4756       if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
4757       {
4758         while(hr<HOST_REGS)
4759         {
4760           if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4761              (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4762              (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4763           {
4764             ntaddr=hr;break;
4765           }
4766           hr++;
4767         }
4768         assert(hr<HOST_REGS);
4769       }
4770       if((opcode[i]&0x2f)==4) // BEQ
4771       {
4772         #ifdef HAVE_CMOV_IMM
4773         if(s1h<0) {
4774           if(s2l>=0) emit_cmp(s1l,s2l);
4775           else emit_test(s1l,s1l);
4776           emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
4777         }
4778         else
4779         #endif
4780         {
4781           emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4782           if(s1h>=0) {
4783             if(s2h>=0) emit_cmp(s1h,s2h);
4784             else emit_test(s1h,s1h);
4785             emit_cmovne_reg(alt,addr);
4786           }
4787           if(s2l>=0) emit_cmp(s1l,s2l);
4788           else emit_test(s1l,s1l);
4789           emit_cmovne_reg(alt,addr);
4790         }
4791       }
4792       if((opcode[i]&0x2f)==5) // BNE
4793       {
4794         #ifdef HAVE_CMOV_IMM
4795         if(s1h<0) {
4796           if(s2l>=0) emit_cmp(s1l,s2l);
4797           else emit_test(s1l,s1l);
4798           emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
4799         }
4800         else
4801         #endif
4802         {
4803           emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
4804           if(s1h>=0) {
4805             if(s2h>=0) emit_cmp(s1h,s2h);
4806             else emit_test(s1h,s1h);
4807             emit_cmovne_reg(alt,addr);
4808           }
4809           if(s2l>=0) emit_cmp(s1l,s2l);
4810           else emit_test(s1l,s1l);
4811           emit_cmovne_reg(alt,addr);
4812         }
4813       }
4814       if((opcode[i]&0x2f)==6) // BLEZ
4815       {
4816         //emit_movimm(ba[i],alt);
4817         //emit_movimm(start+i*4+8,addr);
4818         emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4819         emit_cmpimm(s1l,1);
4820         if(s1h>=0) emit_mov(addr,ntaddr);
4821         emit_cmovl_reg(alt,addr);
4822         if(s1h>=0) {
4823           emit_test(s1h,s1h);
4824           emit_cmovne_reg(ntaddr,addr);
4825           emit_cmovs_reg(alt,addr);
4826         }
4827       }
4828       if((opcode[i]&0x2f)==7) // BGTZ
4829       {
4830         //emit_movimm(ba[i],addr);
4831         //emit_movimm(start+i*4+8,ntaddr);
4832         emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
4833         emit_cmpimm(s1l,1);
4834         if(s1h>=0) emit_mov(addr,alt);
4835         emit_cmovl_reg(ntaddr,addr);
4836         if(s1h>=0) {
4837           emit_test(s1h,s1h);
4838           emit_cmovne_reg(alt,addr);
4839           emit_cmovs_reg(ntaddr,addr);
4840         }
4841       }
4842       if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
4843       {
4844         //emit_movimm(ba[i],alt);
4845         //emit_movimm(start+i*4+8,addr);
4846         emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4847         if(s1h>=0) emit_test(s1h,s1h);
4848         else emit_test(s1l,s1l);
4849         emit_cmovs_reg(alt,addr);
4850       }
4851       if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
4852       {
4853         //emit_movimm(ba[i],addr);
4854         //emit_movimm(start+i*4+8,alt);
4855         emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4856         if(s1h>=0) emit_test(s1h,s1h);
4857         else emit_test(s1l,s1l);
4858         emit_cmovs_reg(alt,addr);
4859       }
4860       if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
4861         if(source[i]&0x10000) // BC1T
4862         {
4863           //emit_movimm(ba[i],alt);
4864           //emit_movimm(start+i*4+8,addr);
4865           emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4866           emit_testimm(s1l,0x800000);
4867           emit_cmovne_reg(alt,addr);
4868         }
4869         else // BC1F
4870         {
4871           //emit_movimm(ba[i],addr);
4872           //emit_movimm(start+i*4+8,alt);
4873           emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4874           emit_testimm(s1l,0x800000);
4875           emit_cmovne_reg(alt,addr);
4876         }
4877       }
4878       emit_writeword(addr,(int)&pcaddr);
4879     }
4880     else
4881     if(itype[i]==RJUMP)
4882     {
4883       int r=get_reg(branch_regs[i].regmap,rs1[i]);
4884       if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
4885         r=get_reg(branch_regs[i].regmap,RTEMP);
4886       }
4887       emit_writeword(r,(int)&pcaddr);
4888     }
4889     else {printf("Unknown branch type in do_ccstub\n");exit(1);}
4890   }
4891   // Update cycle count
4892   assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
4893   if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
4894   emit_call((int)cc_interrupt);
4895   if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
4896   if(stubs[n][6]==TAKEN) {
4897     if(internal_branch(branch_regs[i].is32,ba[i]))
4898       load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
4899     else if(itype[i]==RJUMP) {
4900       if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
4901         emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
4902       else
4903         emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
4904     }
4905   }else if(stubs[n][6]==NOTTAKEN) {
4906     if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
4907     else load_all_regs(branch_regs[i].regmap);
4908   }else if(stubs[n][6]==NULLDS) {
4909     // Delay slot instruction is nullified ("likely" branch)
4910     if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
4911     else load_all_regs(regs[i].regmap);
4912   }else{
4913     load_all_regs(branch_regs[i].regmap);
4914   }
4915   emit_jmp(stubs[n][2]); // return address
4916
4917   /* This works but uses a lot of memory...
4918   emit_readword((int)&last_count,ECX);
4919   emit_add(HOST_CCREG,ECX,EAX);
4920   emit_writeword(EAX,(int)&Count);
4921   emit_call((int)gen_interupt);
4922   emit_readword((int)&Count,HOST_CCREG);
4923   emit_readword((int)&next_interupt,EAX);
4924   emit_readword((int)&pending_exception,EBX);
4925   emit_writeword(EAX,(int)&last_count);
4926   emit_sub(HOST_CCREG,EAX,HOST_CCREG);
4927   emit_test(EBX,EBX);
4928   int jne_instr=(int)out;
4929   emit_jne(0);
4930   if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
4931   load_all_regs(branch_regs[i].regmap);
4932   emit_jmp(stubs[n][2]); // return address
4933   set_jump_target(jne_instr,(int)out);
4934   emit_readword((int)&pcaddr,EAX);
4935   // Call get_addr_ht instead of doing the hash table here.
4936   // This code is executed infrequently and takes up a lot of space
4937   // so smaller is better.
4938   emit_storereg(CCREG,HOST_CCREG);
4939   emit_pushreg(EAX);
4940   emit_call((int)get_addr_ht);
4941   emit_loadreg(CCREG,HOST_CCREG);
4942   emit_addimm(ESP,4,ESP);
4943   emit_jmpreg(EAX);*/
4944 }
4945
4946 add_to_linker(int addr,int target,int ext)
4947 {
4948   link_addr[linkcount][0]=addr;
4949   link_addr[linkcount][1]=target;
4950   link_addr[linkcount][2]=ext;
4951   linkcount++;
4952 }
4953
4954 void ujump_assemble(int i,struct regstat *i_regs)
4955 {
4956   signed char *i_regmap=i_regs->regmap;
4957   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
4958   address_generation(i+1,i_regs,regs[i].regmap_entry);
4959   #ifdef REG_PREFETCH
4960   int temp=get_reg(branch_regs[i].regmap,PTEMP);
4961   if(rt1[i]==31&&temp>=0)
4962   {
4963     int return_address=start+i*4+8;
4964     if(get_reg(branch_regs[i].regmap,31)>0)
4965     if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
4966   }
4967   #endif
4968   ds_assemble(i+1,i_regs);
4969   uint64_t bc_unneeded=branch_regs[i].u;
4970   uint64_t bc_unneeded_upper=branch_regs[i].uu;
4971   bc_unneeded|=1|(1LL<<rt1[i]);
4972   bc_unneeded_upper|=1|(1LL<<rt1[i]);
4973   wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
4974                 bc_unneeded,bc_unneeded_upper);
4975   load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
4976   if(rt1[i]==31) {
4977     int rt;
4978     unsigned int return_address;
4979     assert(rt1[i+1]!=31);
4980     assert(rt2[i+1]!=31);
4981     rt=get_reg(branch_regs[i].regmap,31);
4982     assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
4983     //assert(rt>=0);
4984     return_address=start+i*4+8;
4985     if(rt>=0) {
4986       #ifdef USE_MINI_HT
4987       if(internal_branch(branch_regs[i].is32,return_address)) {
4988         int temp=rt+1;
4989         if(temp==EXCLUDE_REG||temp>=HOST_REGS||
4990            branch_regs[i].regmap[temp]>=0)
4991         {
4992           temp=get_reg(branch_regs[i].regmap,-1);
4993         }
4994         #ifdef HOST_TEMPREG
4995         if(temp<0) temp=HOST_TEMPREG;
4996         #endif
4997         if(temp>=0) do_miniht_insert(return_address,rt,temp);
4998         else emit_movimm(return_address,rt);
4999       }
5000       else
5001       #endif
5002       {
5003         #ifdef REG_PREFETCH
5004         if(temp>=0)
5005         {
5006           if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5007         }
5008         #endif
5009         emit_movimm(return_address,rt); // PC into link register
5010         #ifdef IMM_PREFETCH
5011         emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5012         #endif
5013       }
5014     }
5015   }
5016   int cc,adj;
5017   cc=get_reg(branch_regs[i].regmap,CCREG);
5018   assert(cc==HOST_CCREG);
5019   store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5020   #ifdef REG_PREFETCH
5021   if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5022   #endif
5023   do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5024   if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5025   load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5026   if(internal_branch(branch_regs[i].is32,ba[i]))
5027     assem_debug("branch: internal\n");
5028   else
5029     assem_debug("branch: external\n");
5030   if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5031     ds_assemble_entry(i);
5032   }
5033   else {
5034     add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5035     emit_jmp(0);
5036   }
5037 }
5038
5039 void rjump_assemble(int i,struct regstat *i_regs)
5040 {
5041   signed char *i_regmap=i_regs->regmap;
5042   int temp;
5043   int rs,cc,adj;
5044   rs=get_reg(branch_regs[i].regmap,rs1[i]);
5045   assert(rs>=0);
5046   if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5047     // Delay slot abuse, make a copy of the branch address register
5048     temp=get_reg(branch_regs[i].regmap,RTEMP);
5049     assert(temp>=0);
5050     assert(regs[i].regmap[temp]==RTEMP);
5051     emit_mov(rs,temp);
5052     rs=temp;
5053   }
5054   address_generation(i+1,i_regs,regs[i].regmap_entry);
5055   #ifdef REG_PREFETCH
5056   if(rt1[i]==31)
5057   {
5058     if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5059       int return_address=start+i*4+8;
5060       if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5061     }
5062   }
5063   #endif
5064   #ifdef USE_MINI_HT
5065   if(rs1[i]==31) {
5066     int rh=get_reg(regs[i].regmap,RHASH);
5067     if(rh>=0) do_preload_rhash(rh);
5068   }
5069   #endif
5070   ds_assemble(i+1,i_regs);
5071   uint64_t bc_unneeded=branch_regs[i].u;
5072   uint64_t bc_unneeded_upper=branch_regs[i].uu;
5073   bc_unneeded|=1|(1LL<<rt1[i]);
5074   bc_unneeded_upper|=1|(1LL<<rt1[i]);
5075   bc_unneeded&=~(1LL<<rs1[i]);
5076   wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5077                 bc_unneeded,bc_unneeded_upper);
5078   load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5079   if(rt1[i]!=0) {
5080     int rt,return_address;
5081     assert(rt1[i+1]!=rt1[i]);
5082     assert(rt2[i+1]!=rt1[i]);
5083     rt=get_reg(branch_regs[i].regmap,rt1[i]);
5084     assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5085     assert(rt>=0);
5086     return_address=start+i*4+8;
5087     #ifdef REG_PREFETCH
5088     if(temp>=0)
5089     {
5090       if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5091     }
5092     #endif
5093     emit_movimm(return_address,rt); // PC into link register
5094     #ifdef IMM_PREFETCH
5095     emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5096     #endif
5097   }
5098   cc=get_reg(branch_regs[i].regmap,CCREG);
5099   assert(cc==HOST_CCREG);
5100   #ifdef USE_MINI_HT
5101   int rh=get_reg(branch_regs[i].regmap,RHASH);
5102   int ht=get_reg(branch_regs[i].regmap,RHTBL);
5103   if(rs1[i]==31) {
5104     if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5105     do_preload_rhtbl(ht);
5106     do_rhash(rs,rh);
5107   }
5108   #endif
5109   store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5110   #ifdef DESTRUCTIVE_WRITEBACK
5111   if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5112     if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5113       emit_loadreg(rs1[i],rs);
5114     }
5115   }
5116   #endif
5117   #ifdef REG_PREFETCH
5118   if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5119   #endif
5120   #ifdef USE_MINI_HT
5121   if(rs1[i]==31) {
5122     do_miniht_load(ht,rh);
5123   }
5124   #endif
5125   //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5126   //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5127   //assert(adj==0);
5128   emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5129   add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5130   emit_jns(0);
5131   //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5132   #ifdef USE_MINI_HT
5133   if(rs1[i]==31) {
5134     do_miniht_jump(rs,rh,ht);
5135   }
5136   else
5137   #endif
5138   {
5139     //if(rs!=EAX) emit_mov(rs,EAX);
5140     //emit_jmp((int)jump_vaddr_eax);
5141     emit_jmp(jump_vaddr_reg[rs]);
5142   }
5143   /* Check hash table
5144   temp=!rs;
5145   emit_mov(rs,temp);
5146   emit_shrimm(rs,16,rs);
5147   emit_xor(temp,rs,rs);
5148   emit_movzwl_reg(rs,rs);
5149   emit_shlimm(rs,4,rs);
5150   emit_cmpmem_indexed((int)hash_table,rs,temp);
5151   emit_jne((int)out+14);
5152   emit_readword_indexed((int)hash_table+4,rs,rs);
5153   emit_jmpreg(rs);
5154   emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5155   emit_addimm_no_flags(8,rs);
5156   emit_jeq((int)out-17);
5157   // No hit on hash table, call compiler
5158   emit_pushreg(temp);
5159 //DEBUG >
5160 #ifdef DEBUG_CYCLE_COUNT
5161   emit_readword((int)&last_count,ECX);
5162   emit_add(HOST_CCREG,ECX,HOST_CCREG);
5163   emit_readword((int)&next_interupt,ECX);
5164   emit_writeword(HOST_CCREG,(int)&Count);
5165   emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5166   emit_writeword(ECX,(int)&last_count);
5167 #endif
5168 //DEBUG <
5169   emit_storereg(CCREG,HOST_CCREG);
5170   emit_call((int)get_addr);
5171   emit_loadreg(CCREG,HOST_CCREG);
5172   emit_addimm(ESP,4,ESP);
5173   emit_jmpreg(EAX);*/
5174   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5175   if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5176   #endif
5177 }
5178
5179 void cjump_assemble(int i,struct regstat *i_regs)
5180 {
5181   signed char *i_regmap=i_regs->regmap;
5182   int cc;
5183   int match;
5184   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5185   assem_debug("match=%d\n",match);
5186   int s1h,s1l,s2h,s2l;
5187   int prev_cop1_usable=cop1_usable;
5188   int unconditional=0,nop=0;
5189   int only32=0;
5190   int ooo=1;
5191   int invert=0;
5192   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5193   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5194   if(likely[i]) ooo=0;
5195   if(!match) invert=1;
5196   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5197   if(i>(ba[i]-start)>>2) invert=1;
5198   #endif
5199
5200   if(ooo)
5201     if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
5202        (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1])))
5203   {
5204     // Write-after-read dependency prevents out of order execution
5205     // First test branch condition, then execute delay slot, then branch
5206     ooo=0;
5207   }
5208
5209   if(ooo) {
5210     s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5211     s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5212     s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5213     s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5214   }
5215   else {
5216     s1l=get_reg(i_regmap,rs1[i]);
5217     s1h=get_reg(i_regmap,rs1[i]|64);
5218     s2l=get_reg(i_regmap,rs2[i]);
5219     s2h=get_reg(i_regmap,rs2[i]|64);
5220   }
5221   if(rs1[i]==0&&rs2[i]==0)
5222   {
5223     if(opcode[i]&1) nop=1;
5224     else unconditional=1;
5225     //assert(opcode[i]!=5);
5226     //assert(opcode[i]!=7);
5227     //assert(opcode[i]!=0x15);
5228     //assert(opcode[i]!=0x17);
5229   }
5230   else if(rs1[i]==0)
5231   {
5232     s1l=s2l;s1h=s2h;
5233     s2l=s2h=-1;
5234     only32=(regs[i].was32>>rs2[i])&1;
5235   }
5236   else if(rs2[i]==0)
5237   {
5238     s2l=s2h=-1;
5239     only32=(regs[i].was32>>rs1[i])&1;
5240   }
5241   else {
5242     only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5243   }
5244
5245   if(ooo) {
5246     // Out of order execution (delay slot first)
5247     //printf("OOOE\n");
5248     address_generation(i+1,i_regs,regs[i].regmap_entry);
5249     ds_assemble(i+1,i_regs);
5250     int adj;
5251     uint64_t bc_unneeded=branch_regs[i].u;
5252     uint64_t bc_unneeded_upper=branch_regs[i].uu;
5253     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5254     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5255     bc_unneeded|=1;
5256     bc_unneeded_upper|=1;
5257     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5258                   bc_unneeded,bc_unneeded_upper);
5259     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5260     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5261     cc=get_reg(branch_regs[i].regmap,CCREG);
5262     assert(cc==HOST_CCREG);
5263     if(unconditional)
5264       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5265     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5266     //assem_debug("cycle count (adj)\n");
5267     if(unconditional) {
5268       do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5269       if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5270         if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5271         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5272         if(internal)
5273           assem_debug("branch: internal\n");
5274         else
5275           assem_debug("branch: external\n");
5276         if(internal&&is_ds[(ba[i]-start)>>2]) {
5277           ds_assemble_entry(i);
5278         }
5279         else {
5280           add_to_linker((int)out,ba[i],internal);
5281           emit_jmp(0);
5282         }
5283         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5284         if(((u_int)out)&7) emit_addnop(0);
5285         #endif
5286       }
5287     }
5288     else if(nop) {
5289       emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5290       int jaddr=(int)out;
5291       emit_jns(0);
5292       add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5293     }
5294     else {
5295       int taken=0,nottaken=0,nottaken1=0;
5296       do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5297       if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5298       if(!only32)
5299       {
5300         assert(s1h>=0);
5301         if(opcode[i]==4) // BEQ
5302         {
5303           if(s2h>=0) emit_cmp(s1h,s2h);
5304           else emit_test(s1h,s1h);
5305           nottaken1=(int)out;
5306           emit_jne(1);
5307         }
5308         if(opcode[i]==5) // BNE
5309         {
5310           if(s2h>=0) emit_cmp(s1h,s2h);
5311           else emit_test(s1h,s1h);
5312           if(invert) taken=(int)out;
5313           else add_to_linker((int)out,ba[i],internal);
5314           emit_jne(0);
5315         }
5316         if(opcode[i]==6) // BLEZ
5317         {
5318           emit_test(s1h,s1h);
5319           if(invert) taken=(int)out;
5320           else add_to_linker((int)out,ba[i],internal);
5321           emit_js(0);
5322           nottaken1=(int)out;
5323           emit_jne(1);
5324         }
5325         if(opcode[i]==7) // BGTZ
5326         {
5327           emit_test(s1h,s1h);
5328           nottaken1=(int)out;
5329           emit_js(1);
5330           if(invert) taken=(int)out;
5331           else add_to_linker((int)out,ba[i],internal);
5332           emit_jne(0);
5333         }
5334       } // if(!only32)
5335
5336       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5337       assert(s1l>=0);
5338       if(opcode[i]==4) // BEQ
5339       {
5340         if(s2l>=0) emit_cmp(s1l,s2l);
5341         else emit_test(s1l,s1l);
5342         if(invert){
5343           nottaken=(int)out;
5344           emit_jne(1);
5345         }else{
5346           add_to_linker((int)out,ba[i],internal);
5347           emit_jeq(0);
5348         }
5349       }
5350       if(opcode[i]==5) // BNE
5351       {
5352         if(s2l>=0) emit_cmp(s1l,s2l);
5353         else emit_test(s1l,s1l);
5354         if(invert){
5355           nottaken=(int)out;
5356           emit_jeq(1);
5357         }else{
5358           add_to_linker((int)out,ba[i],internal);
5359           emit_jne(0);
5360         }
5361       }
5362       if(opcode[i]==6) // BLEZ
5363       {
5364         emit_cmpimm(s1l,1);
5365         if(invert){
5366           nottaken=(int)out;
5367           emit_jge(1);
5368         }else{
5369           add_to_linker((int)out,ba[i],internal);
5370           emit_jl(0);
5371         }
5372       }
5373       if(opcode[i]==7) // BGTZ
5374       {
5375         emit_cmpimm(s1l,1);
5376         if(invert){
5377           nottaken=(int)out;
5378           emit_jl(1);
5379         }else{
5380           add_to_linker((int)out,ba[i],internal);
5381           emit_jge(0);
5382         }
5383       }
5384       if(invert) {
5385         if(taken) set_jump_target(taken,(int)out);
5386         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5387         if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5388           if(adj) {
5389             emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5390             add_to_linker((int)out,ba[i],internal);
5391           }else{
5392             emit_addnop(13);
5393             add_to_linker((int)out,ba[i],internal*2);
5394           }
5395           emit_jmp(0);
5396         }else
5397         #endif
5398         {
5399           if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5400           store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5401           load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5402           if(internal)
5403             assem_debug("branch: internal\n");
5404           else
5405             assem_debug("branch: external\n");
5406           if(internal&&is_ds[(ba[i]-start)>>2]) {
5407             ds_assemble_entry(i);
5408           }
5409           else {
5410             add_to_linker((int)out,ba[i],internal);
5411             emit_jmp(0);
5412           }
5413         }
5414         set_jump_target(nottaken,(int)out);
5415       }
5416
5417       if(nottaken1) set_jump_target(nottaken1,(int)out);
5418       if(adj) {
5419         if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5420       }
5421     } // (!unconditional)
5422   } // if(ooo)
5423   else
5424   {
5425     // In-order execution (branch first)
5426     //if(likely[i]) printf("IOL\n");
5427     //else
5428     //printf("IOE\n");
5429     int taken=0,nottaken=0,nottaken1=0;
5430     if(!unconditional&&!nop) {
5431       if(!only32)
5432       {
5433         assert(s1h>=0);
5434         if((opcode[i]&0x2f)==4) // BEQ
5435         {
5436           if(s2h>=0) emit_cmp(s1h,s2h);
5437           else emit_test(s1h,s1h);
5438           nottaken1=(int)out;
5439           emit_jne(2);
5440         }
5441         if((opcode[i]&0x2f)==5) // BNE
5442         {
5443           if(s2h>=0) emit_cmp(s1h,s2h);
5444           else emit_test(s1h,s1h);
5445           taken=(int)out;
5446           emit_jne(1);
5447         }
5448         if((opcode[i]&0x2f)==6) // BLEZ
5449         {
5450           emit_test(s1h,s1h);
5451           taken=(int)out;
5452           emit_js(1);
5453           nottaken1=(int)out;
5454           emit_jne(2);
5455         }
5456         if((opcode[i]&0x2f)==7) // BGTZ
5457         {
5458           emit_test(s1h,s1h);
5459           nottaken1=(int)out;
5460           emit_js(2);
5461           taken=(int)out;
5462           emit_jne(1);
5463         }
5464       } // if(!only32)
5465
5466       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5467       assert(s1l>=0);
5468       if((opcode[i]&0x2f)==4) // BEQ
5469       {
5470         if(s2l>=0) emit_cmp(s1l,s2l);
5471         else emit_test(s1l,s1l);
5472         nottaken=(int)out;
5473         emit_jne(2);
5474       }
5475       if((opcode[i]&0x2f)==5) // BNE
5476       {
5477         if(s2l>=0) emit_cmp(s1l,s2l);
5478         else emit_test(s1l,s1l);
5479         nottaken=(int)out;
5480         emit_jeq(2);
5481       }
5482       if((opcode[i]&0x2f)==6) // BLEZ
5483       {
5484         emit_cmpimm(s1l,1);
5485         nottaken=(int)out;
5486         emit_jge(2);
5487       }
5488       if((opcode[i]&0x2f)==7) // BGTZ
5489       {
5490         emit_cmpimm(s1l,1);
5491         nottaken=(int)out;
5492         emit_jl(2);
5493       }
5494     } // if(!unconditional)
5495     int adj;
5496     uint64_t ds_unneeded=branch_regs[i].u;
5497     uint64_t ds_unneeded_upper=branch_regs[i].uu;
5498     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5499     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5500     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5501     ds_unneeded|=1;
5502     ds_unneeded_upper|=1;
5503     // branch taken
5504     if(!nop) {
5505       if(taken) set_jump_target(taken,(int)out);
5506       assem_debug("1:\n");
5507       wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5508                     ds_unneeded,ds_unneeded_upper);
5509       // load regs
5510       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5511       address_generation(i+1,&branch_regs[i],0);
5512       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5513       ds_assemble(i+1,&branch_regs[i]);
5514       cc=get_reg(branch_regs[i].regmap,CCREG);
5515       if(cc==-1) {
5516         emit_loadreg(CCREG,cc=HOST_CCREG);
5517         // CHECK: Is the following instruction (fall thru) allocated ok?
5518       }
5519       assert(cc==HOST_CCREG);
5520       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5521       do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5522       assem_debug("cycle count (adj)\n");
5523       if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5524       load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5525       if(internal)
5526         assem_debug("branch: internal\n");
5527       else
5528         assem_debug("branch: external\n");
5529       if(internal&&is_ds[(ba[i]-start)>>2]) {
5530         ds_assemble_entry(i);
5531       }
5532       else {
5533         add_to_linker((int)out,ba[i],internal);
5534         emit_jmp(0);
5535       }
5536     }
5537     // branch not taken
5538     cop1_usable=prev_cop1_usable;
5539     if(!unconditional) {
5540       if(nottaken1) set_jump_target(nottaken1,(int)out);
5541       set_jump_target(nottaken,(int)out);
5542       assem_debug("2:\n");
5543       if(!likely[i]) {
5544         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5545                       ds_unneeded,ds_unneeded_upper);
5546         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5547         address_generation(i+1,&branch_regs[i],0);
5548         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5549         ds_assemble(i+1,&branch_regs[i]);
5550       }
5551       cc=get_reg(branch_regs[i].regmap,CCREG);
5552       if(cc==-1&&!likely[i]) {
5553         // Cycle count isn't in a register, temporarily load it then write it out
5554         emit_loadreg(CCREG,HOST_CCREG);
5555         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5556         int jaddr=(int)out;
5557         emit_jns(0);
5558         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5559         emit_storereg(CCREG,HOST_CCREG);
5560       }
5561       else{
5562         cc=get_reg(i_regmap,CCREG);
5563         assert(cc==HOST_CCREG);
5564         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5565         int jaddr=(int)out;
5566         emit_jns(0);
5567         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5568       }
5569     }
5570   }
5571 }
5572
5573 void sjump_assemble(int i,struct regstat *i_regs)
5574 {
5575   signed char *i_regmap=i_regs->regmap;
5576   int cc;
5577   int match;
5578   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5579   assem_debug("smatch=%d\n",match);
5580   int s1h,s1l;
5581   int prev_cop1_usable=cop1_usable;
5582   int unconditional=0,nevertaken=0;
5583   int only32=0;
5584   int ooo=1;
5585   int invert=0;
5586   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5587   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5588   if(likely[i]) ooo=0;
5589   if(!match) invert=1;
5590   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5591   if(i>(ba[i]-start)>>2) invert=1;
5592   #endif
5593
5594   //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
5595   assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
5596
5597   if(ooo)
5598     if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))
5599   {
5600     // Write-after-read dependency prevents out of order execution
5601     // First test branch condition, then execute delay slot, then branch
5602     ooo=0;
5603   }
5604   // TODO: Conditional branches w/link must execute in-order so that
5605   // condition test and write to r31 occur before cycle count test
5606
5607   if(ooo) {
5608     s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5609     s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5610   }
5611   else {
5612     s1l=get_reg(i_regmap,rs1[i]);
5613     s1h=get_reg(i_regmap,rs1[i]|64);
5614   }
5615   if(rs1[i]==0)
5616   {
5617     if(opcode2[i]&1) unconditional=1;
5618     else nevertaken=1;
5619     // These are never taken (r0 is never less than zero)
5620     //assert(opcode2[i]!=0);
5621     //assert(opcode2[i]!=2);
5622     //assert(opcode2[i]!=0x10);
5623     //assert(opcode2[i]!=0x12);
5624   }
5625   else {
5626     only32=(regs[i].was32>>rs1[i])&1;
5627   }
5628
5629   if(ooo) {
5630     // Out of order execution (delay slot first)
5631     //printf("OOOE\n");
5632     address_generation(i+1,i_regs,regs[i].regmap_entry);
5633     ds_assemble(i+1,i_regs);
5634     int adj;
5635     uint64_t bc_unneeded=branch_regs[i].u;
5636     uint64_t bc_unneeded_upper=branch_regs[i].uu;
5637     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5638     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5639     bc_unneeded|=1;
5640     bc_unneeded_upper|=1;
5641     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5642                   bc_unneeded,bc_unneeded_upper);
5643     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5644     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5645     if(rt1[i]==31) {
5646       int rt,return_address;
5647       assert(rt1[i+1]!=31);
5648       assert(rt2[i+1]!=31);
5649       rt=get_reg(branch_regs[i].regmap,31);
5650       assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5651       if(rt>=0) {
5652         // Save the PC even if the branch is not taken
5653         return_address=start+i*4+8;
5654         emit_movimm(return_address,rt); // PC into link register
5655         #ifdef IMM_PREFETCH
5656         if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5657         #endif
5658       }
5659     }
5660     cc=get_reg(branch_regs[i].regmap,CCREG);
5661     assert(cc==HOST_CCREG);
5662     if(unconditional)
5663       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5664     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5665     assem_debug("cycle count (adj)\n");
5666     if(unconditional) {
5667       do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5668       if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5669         if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5670         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5671         if(internal)
5672           assem_debug("branch: internal\n");
5673         else
5674           assem_debug("branch: external\n");
5675         if(internal&&is_ds[(ba[i]-start)>>2]) {
5676           ds_assemble_entry(i);
5677         }
5678         else {
5679           add_to_linker((int)out,ba[i],internal);
5680           emit_jmp(0);
5681         }
5682         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5683         if(((u_int)out)&7) emit_addnop(0);
5684         #endif
5685       }
5686     }
5687     else if(nevertaken) {
5688       emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5689       int jaddr=(int)out;
5690       emit_jns(0);
5691       add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5692     }
5693     else {
5694       int nottaken=0;
5695       do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5696       if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5697       if(!only32)
5698       {
5699         assert(s1h>=0);
5700         if(opcode2[i]==0) // BLTZ
5701         {
5702           emit_test(s1h,s1h);
5703           if(invert){
5704             nottaken=(int)out;
5705             emit_jns(1);
5706           }else{
5707             add_to_linker((int)out,ba[i],internal);
5708             emit_js(0);
5709           }
5710         }
5711         if(opcode2[i]==1) // BGEZ
5712         {
5713           emit_test(s1h,s1h);
5714           if(invert){
5715             nottaken=(int)out;
5716             emit_js(1);
5717           }else{
5718             add_to_linker((int)out,ba[i],internal);
5719             emit_jns(0);
5720           }
5721         }
5722       } // if(!only32)
5723       else
5724       {
5725         assert(s1l>=0);
5726         if(opcode2[i]==0) // BLTZ
5727         {
5728           emit_test(s1l,s1l);
5729           if(invert){
5730             nottaken=(int)out;
5731             emit_jns(1);
5732           }else{
5733             add_to_linker((int)out,ba[i],internal);
5734             emit_js(0);
5735           }
5736         }
5737         if(opcode2[i]==1) // BGEZ
5738         {
5739           emit_test(s1l,s1l);
5740           if(invert){
5741             nottaken=(int)out;
5742             emit_js(1);
5743           }else{
5744             add_to_linker((int)out,ba[i],internal);
5745             emit_jns(0);
5746           }
5747         }
5748       } // if(!only32)
5749
5750       if(invert) {
5751         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5752         if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5753           if(adj) {
5754             emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5755             add_to_linker((int)out,ba[i],internal);
5756           }else{
5757             emit_addnop(13);
5758             add_to_linker((int)out,ba[i],internal*2);
5759           }
5760           emit_jmp(0);
5761         }else
5762         #endif
5763         {
5764           if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5765           store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5766           load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5767           if(internal)
5768             assem_debug("branch: internal\n");
5769           else
5770             assem_debug("branch: external\n");
5771           if(internal&&is_ds[(ba[i]-start)>>2]) {
5772             ds_assemble_entry(i);
5773           }
5774           else {
5775             add_to_linker((int)out,ba[i],internal);
5776             emit_jmp(0);
5777           }
5778         }
5779         set_jump_target(nottaken,(int)out);
5780       }
5781
5782       if(adj) {
5783         if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5784       }
5785     } // (!unconditional)
5786   } // if(ooo)
5787   else
5788   {
5789     // In-order execution (branch first)
5790     //printf("IOE\n");
5791     int nottaken=0;
5792     if(!unconditional) {
5793       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5794       if(!only32)
5795       {
5796         assert(s1h>=0);
5797         if((opcode2[i]&0x1d)==0) // BLTZ/BLTZL
5798         {
5799           emit_test(s1h,s1h);
5800           nottaken=(int)out;
5801           emit_jns(1);
5802         }
5803         if((opcode2[i]&0x1d)==1) // BGEZ/BGEZL
5804         {
5805           emit_test(s1h,s1h);
5806           nottaken=(int)out;
5807           emit_js(1);
5808         }
5809       } // if(!only32)
5810       else
5811       {
5812         assert(s1l>=0);
5813         if((opcode2[i]&0x1d)==0) // BLTZ/BLTZL
5814         {
5815           emit_test(s1l,s1l);
5816           nottaken=(int)out;
5817           emit_jns(1);
5818         }
5819         if((opcode2[i]&0x1d)==1) // BGEZ/BGEZL
5820         {
5821           emit_test(s1l,s1l);
5822           nottaken=(int)out;
5823           emit_js(1);
5824         }
5825       }
5826     } // if(!unconditional)
5827     int adj;
5828     uint64_t ds_unneeded=branch_regs[i].u;
5829     uint64_t ds_unneeded_upper=branch_regs[i].uu;
5830     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5831     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5832     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5833     ds_unneeded|=1;
5834     ds_unneeded_upper|=1;
5835     // branch taken
5836     if(!nevertaken) {
5837       //assem_debug("1:\n");
5838       wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5839                     ds_unneeded,ds_unneeded_upper);
5840       // load regs
5841       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5842       address_generation(i+1,&branch_regs[i],0);
5843       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5844       ds_assemble(i+1,&branch_regs[i]);
5845       cc=get_reg(branch_regs[i].regmap,CCREG);
5846       if(cc==-1) {
5847         emit_loadreg(CCREG,cc=HOST_CCREG);
5848         // CHECK: Is the following instruction (fall thru) allocated ok?
5849       }
5850       assert(cc==HOST_CCREG);
5851       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5852       do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5853       assem_debug("cycle count (adj)\n");
5854       if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5855       load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5856       if(internal)
5857         assem_debug("branch: internal\n");
5858       else
5859         assem_debug("branch: external\n");
5860       if(internal&&is_ds[(ba[i]-start)>>2]) {
5861         ds_assemble_entry(i);
5862       }
5863       else {
5864         add_to_linker((int)out,ba[i],internal);
5865         emit_jmp(0);
5866       }
5867     }
5868     // branch not taken
5869     cop1_usable=prev_cop1_usable;
5870     if(!unconditional) {
5871       set_jump_target(nottaken,(int)out);
5872       assem_debug("1:\n");
5873       if(!likely[i]) {
5874         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5875                       ds_unneeded,ds_unneeded_upper);
5876         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5877         address_generation(i+1,&branch_regs[i],0);
5878         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5879         ds_assemble(i+1,&branch_regs[i]);
5880       }
5881       cc=get_reg(branch_regs[i].regmap,CCREG);
5882       if(cc==-1&&!likely[i]) {
5883         // Cycle count isn't in a register, temporarily load it then write it out
5884         emit_loadreg(CCREG,HOST_CCREG);
5885         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5886         int jaddr=(int)out;
5887         emit_jns(0);
5888         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5889         emit_storereg(CCREG,HOST_CCREG);
5890       }
5891       else{
5892         cc=get_reg(i_regmap,CCREG);
5893         assert(cc==HOST_CCREG);
5894         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5895         int jaddr=(int)out;
5896         emit_jns(0);
5897         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5898       }
5899     }
5900   }
5901 }
5902
5903 void fjump_assemble(int i,struct regstat *i_regs)
5904 {
5905   signed char *i_regmap=i_regs->regmap;
5906   int cc;
5907   int match;
5908   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5909   assem_debug("fmatch=%d\n",match);
5910   int fs,cs;
5911   int eaddr;
5912   int ooo=1;
5913   int invert=0;
5914   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5915   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5916   if(likely[i]) ooo=0;
5917   if(!match) invert=1;
5918   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5919   if(i>(ba[i]-start)>>2) invert=1;
5920   #endif
5921
5922   if(ooo)
5923     if(itype[i+1]==FCOMP)
5924   {
5925     // Write-after-read dependency prevents out of order execution
5926     // First test branch condition, then execute delay slot, then branch
5927     ooo=0;
5928   }
5929
5930   if(ooo) {
5931     fs=get_reg(branch_regs[i].regmap,FSREG);
5932     address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
5933   }
5934   else {
5935     fs=get_reg(i_regmap,FSREG);
5936   }
5937
5938   // Check cop1 unusable
5939   if(!cop1_usable) {
5940     cs=get_reg(i_regmap,CSREG);
5941     assert(cs>=0);
5942     emit_testimm(cs,0x20000000);
5943     eaddr=(int)out;
5944     emit_jeq(0);
5945     add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
5946     cop1_usable=1;
5947   }
5948
5949   if(ooo) {
5950     // Out of order execution (delay slot first)
5951     //printf("OOOE\n");
5952     ds_assemble(i+1,i_regs);
5953     int adj;
5954     uint64_t bc_unneeded=branch_regs[i].u;
5955     uint64_t bc_unneeded_upper=branch_regs[i].uu;
5956     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5957     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5958     bc_unneeded|=1;
5959     bc_unneeded_upper|=1;
5960     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5961                   bc_unneeded,bc_unneeded_upper);
5962     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5963     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5964     cc=get_reg(branch_regs[i].regmap,CCREG);
5965     assert(cc==HOST_CCREG);
5966     do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5967     assem_debug("cycle count (adj)\n");
5968     if(1) {
5969       int nottaken=0;
5970       if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5971       if(1) {
5972         assert(fs>=0);
5973         emit_testimm(fs,0x800000);
5974         if(source[i]&0x10000) // BC1T
5975         {
5976           if(invert){
5977             nottaken=(int)out;
5978             emit_jeq(1);
5979           }else{
5980             add_to_linker((int)out,ba[i],internal);
5981             emit_jne(0);
5982           }
5983         }
5984         else // BC1F
5985           if(invert){
5986             nottaken=(int)out;
5987             emit_jne(1);
5988           }else{
5989             add_to_linker((int)out,ba[i],internal);
5990             emit_jeq(0);
5991           }
5992         {
5993         }
5994       } // if(!only32)
5995
5996       if(invert) {
5997         if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5998         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5999         else if(match) emit_addnop(13);
6000         #endif
6001         store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6002         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6003         if(internal)
6004           assem_debug("branch: internal\n");
6005         else
6006           assem_debug("branch: external\n");
6007         if(internal&&is_ds[(ba[i]-start)>>2]) {
6008           ds_assemble_entry(i);
6009         }
6010         else {
6011           add_to_linker((int)out,ba[i],internal);
6012           emit_jmp(0);
6013         }
6014         set_jump_target(nottaken,(int)out);
6015       }
6016
6017       if(adj) {
6018         if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
6019       }
6020     } // (!unconditional)
6021   } // if(ooo)
6022   else
6023   {
6024     // In-order execution (branch first)
6025     //printf("IOE\n");
6026     int nottaken=0;
6027     if(1) {
6028       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6029       if(1) {
6030         assert(fs>=0);
6031         emit_testimm(fs,0x800000);
6032         if(source[i]&0x10000) // BC1T
6033         {
6034           nottaken=(int)out;
6035           emit_jeq(1);
6036         }
6037         else // BC1F
6038         {
6039           nottaken=(int)out;
6040           emit_jne(1);
6041         }
6042       }
6043     } // if(!unconditional)
6044     int adj;
6045     uint64_t ds_unneeded=branch_regs[i].u;
6046     uint64_t ds_unneeded_upper=branch_regs[i].uu;
6047     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6048     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6049     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6050     ds_unneeded|=1;
6051     ds_unneeded_upper|=1;
6052     // branch taken
6053     //assem_debug("1:\n");
6054     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6055                   ds_unneeded,ds_unneeded_upper);
6056     // load regs
6057     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6058     address_generation(i+1,&branch_regs[i],0);
6059     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6060     ds_assemble(i+1,&branch_regs[i]);
6061     cc=get_reg(branch_regs[i].regmap,CCREG);
6062     if(cc==-1) {
6063       emit_loadreg(CCREG,cc=HOST_CCREG);
6064       // CHECK: Is the following instruction (fall thru) allocated ok?
6065     }
6066     assert(cc==HOST_CCREG);
6067     store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6068     do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6069     assem_debug("cycle count (adj)\n");
6070     if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6071     load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6072     if(internal)
6073       assem_debug("branch: internal\n");
6074     else
6075       assem_debug("branch: external\n");
6076     if(internal&&is_ds[(ba[i]-start)>>2]) {
6077       ds_assemble_entry(i);
6078     }
6079     else {
6080       add_to_linker((int)out,ba[i],internal);
6081       emit_jmp(0);
6082     }
6083
6084     // branch not taken
6085     if(1) { // <- FIXME (don't need this)
6086       set_jump_target(nottaken,(int)out);
6087       assem_debug("1:\n");
6088       if(!likely[i]) {
6089         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6090                       ds_unneeded,ds_unneeded_upper);
6091         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6092         address_generation(i+1,&branch_regs[i],0);
6093         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6094         ds_assemble(i+1,&branch_regs[i]);
6095       }
6096       cc=get_reg(branch_regs[i].regmap,CCREG);
6097       if(cc==-1&&!likely[i]) {
6098         // Cycle count isn't in a register, temporarily load it then write it out
6099         emit_loadreg(CCREG,HOST_CCREG);
6100         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6101         int jaddr=(int)out;
6102         emit_jns(0);
6103         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6104         emit_storereg(CCREG,HOST_CCREG);
6105       }
6106       else{
6107         cc=get_reg(i_regmap,CCREG);
6108         assert(cc==HOST_CCREG);
6109         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6110         int jaddr=(int)out;
6111         emit_jns(0);
6112         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6113       }
6114     }
6115   }
6116 }
6117
6118 static void pagespan_assemble(int i,struct regstat *i_regs)
6119 {
6120   int s1l=get_reg(i_regs->regmap,rs1[i]);
6121   int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6122   int s2l=get_reg(i_regs->regmap,rs2[i]);
6123   int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6124   void *nt_branch=NULL;
6125   int taken=0;
6126   int nottaken=0;
6127   int unconditional=0;
6128   if(rs1[i]==0)
6129   {
6130     s1l=s2l;s1h=s2h;
6131     s2l=s2h=-1;
6132   }
6133   else if(rs2[i]==0)
6134   {
6135     s2l=s2h=-1;
6136   }
6137   if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6138     s1h=s2h=-1;
6139   }
6140   int hr=0;
6141   int addr,alt,ntaddr;
6142   if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6143   else {
6144     while(hr<HOST_REGS)
6145     {
6146       if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6147          (i_regs->regmap[hr]&63)!=rs1[i] &&
6148          (i_regs->regmap[hr]&63)!=rs2[i] )
6149       {
6150         addr=hr++;break;
6151       }
6152       hr++;
6153     }
6154   }
6155   while(hr<HOST_REGS)
6156   {
6157     if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6158        (i_regs->regmap[hr]&63)!=rs1[i] &&
6159        (i_regs->regmap[hr]&63)!=rs2[i] )
6160     {
6161       alt=hr++;break;
6162     }
6163     hr++;
6164   }
6165   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6166   {
6167     while(hr<HOST_REGS)
6168     {
6169       if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6170          (i_regs->regmap[hr]&63)!=rs1[i] &&
6171          (i_regs->regmap[hr]&63)!=rs2[i] )
6172       {
6173         ntaddr=hr;break;
6174       }
6175       hr++;
6176     }
6177   }
6178   assert(hr<HOST_REGS);
6179   if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6180     load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6181   }
6182   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6183   if(opcode[i]==2) // J
6184   {
6185     unconditional=1;
6186   }
6187   if(opcode[i]==3) // JAL
6188   {
6189     // TODO: mini_ht
6190     int rt=get_reg(i_regs->regmap,31);
6191     emit_movimm(start+i*4+8,rt);
6192     unconditional=1;
6193   }
6194   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6195   {
6196     emit_mov(s1l,addr);
6197     if(opcode2[i]==9) // JALR
6198     {
6199       int rt=get_reg(i_regs->regmap,rt1[i]);
6200       emit_movimm(start+i*4+8,rt);
6201     }
6202   }
6203   if((opcode[i]&0x3f)==4) // BEQ
6204   {
6205     if(rs1[i]==rs2[i])
6206     {
6207       unconditional=1;
6208     }
6209     else
6210     #ifdef HAVE_CMOV_IMM
6211     if(s1h<0) {
6212       if(s2l>=0) emit_cmp(s1l,s2l);
6213       else emit_test(s1l,s1l);
6214       emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6215     }
6216     else
6217     #endif
6218     {
6219       assert(s1l>=0);
6220       emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6221       if(s1h>=0) {
6222         if(s2h>=0) emit_cmp(s1h,s2h);
6223         else emit_test(s1h,s1h);
6224         emit_cmovne_reg(alt,addr);
6225       }
6226       if(s2l>=0) emit_cmp(s1l,s2l);
6227       else emit_test(s1l,s1l);
6228       emit_cmovne_reg(alt,addr);
6229     }
6230   }
6231   if((opcode[i]&0x3f)==5) // BNE
6232   {
6233     #ifdef HAVE_CMOV_IMM
6234     if(s1h<0) {
6235       if(s2l>=0) emit_cmp(s1l,s2l);
6236       else emit_test(s1l,s1l);
6237       emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6238     }
6239     else
6240     #endif
6241     {
6242       assert(s1l>=0);
6243       emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6244       if(s1h>=0) {
6245         if(s2h>=0) emit_cmp(s1h,s2h);
6246         else emit_test(s1h,s1h);
6247         emit_cmovne_reg(alt,addr);
6248       }
6249       if(s2l>=0) emit_cmp(s1l,s2l);
6250       else emit_test(s1l,s1l);
6251       emit_cmovne_reg(alt,addr);
6252     }
6253   }
6254   if((opcode[i]&0x3f)==0x14) // BEQL
6255   {
6256     if(s1h>=0) {
6257       if(s2h>=0) emit_cmp(s1h,s2h);
6258       else emit_test(s1h,s1h);
6259       nottaken=(int)out;
6260       emit_jne(0);
6261     }
6262     if(s2l>=0) emit_cmp(s1l,s2l);
6263     else emit_test(s1l,s1l);
6264     if(nottaken) set_jump_target(nottaken,(int)out);
6265     nottaken=(int)out;
6266     emit_jne(0);
6267   }
6268   if((opcode[i]&0x3f)==0x15) // BNEL
6269   {
6270     if(s1h>=0) {
6271       if(s2h>=0) emit_cmp(s1h,s2h);
6272       else emit_test(s1h,s1h);
6273       taken=(int)out;
6274       emit_jne(0);
6275     }
6276     if(s2l>=0) emit_cmp(s1l,s2l);
6277     else emit_test(s1l,s1l);
6278     nottaken=(int)out;
6279     emit_jeq(0);
6280     if(taken) set_jump_target(taken,(int)out);
6281   }
6282   if((opcode[i]&0x3f)==6) // BLEZ
6283   {
6284     emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6285     emit_cmpimm(s1l,1);
6286     if(s1h>=0) emit_mov(addr,ntaddr);
6287     emit_cmovl_reg(alt,addr);
6288     if(s1h>=0) {
6289       emit_test(s1h,s1h);
6290       emit_cmovne_reg(ntaddr,addr);
6291       emit_cmovs_reg(alt,addr);
6292     }
6293   }
6294   if((opcode[i]&0x3f)==7) // BGTZ
6295   {
6296     emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6297     emit_cmpimm(s1l,1);
6298     if(s1h>=0) emit_mov(addr,alt);
6299     emit_cmovl_reg(ntaddr,addr);
6300     if(s1h>=0) {
6301       emit_test(s1h,s1h);
6302       emit_cmovne_reg(alt,addr);
6303       emit_cmovs_reg(ntaddr,addr);
6304     }
6305   }
6306   if((opcode[i]&0x3f)==0x16) // BLEZL
6307   {
6308     assert((opcode[i]&0x3f)!=0x16);
6309   }
6310   if((opcode[i]&0x3f)==0x17) // BGTZL
6311   {
6312     assert((opcode[i]&0x3f)!=0x17);
6313   }
6314   assert(opcode[i]!=1); // BLTZ/BGEZ
6315
6316   //FIXME: Check CSREG
6317   if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6318     if((source[i]&0x30000)==0) // BC1F
6319     {
6320       emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6321       emit_testimm(s1l,0x800000);
6322       emit_cmovne_reg(alt,addr);
6323     }
6324     if((source[i]&0x30000)==0x10000) // BC1T
6325     {
6326       emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6327       emit_testimm(s1l,0x800000);
6328       emit_cmovne_reg(alt,addr);
6329     }
6330     if((source[i]&0x30000)==0x20000) // BC1FL
6331     {
6332       emit_testimm(s1l,0x800000);
6333       nottaken=(int)out;
6334       emit_jne(0);
6335     }
6336     if((source[i]&0x30000)==0x30000) // BC1TL
6337     {
6338       emit_testimm(s1l,0x800000);
6339       nottaken=(int)out;
6340       emit_jeq(0);
6341     }
6342   }
6343
6344   assert(i_regs->regmap[HOST_CCREG]==CCREG);
6345   wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6346   if(likely[i]||unconditional)
6347   {
6348     emit_movimm(ba[i],HOST_BTREG);
6349   }
6350   else if(addr!=HOST_BTREG)
6351   {
6352     emit_mov(addr,HOST_BTREG);
6353   }
6354   void *branch_addr=out;
6355   emit_jmp(0);
6356   int target_addr=start+i*4+5;
6357   void *stub=out;
6358   void *compiled_target_addr=check_addr(target_addr);
6359   emit_extjump_ds((int)branch_addr,target_addr);
6360   if(compiled_target_addr) {
6361     set_jump_target((int)branch_addr,(int)compiled_target_addr);
6362     add_link(target_addr,stub);
6363   }
6364   else set_jump_target((int)branch_addr,(int)stub);
6365   if(likely[i]) {
6366     // Not-taken path
6367     set_jump_target((int)nottaken,(int)out);
6368     wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6369     void *branch_addr=out;
6370     emit_jmp(0);
6371     int target_addr=start+i*4+8;
6372     void *stub=out;
6373     void *compiled_target_addr=check_addr(target_addr);
6374     emit_extjump_ds((int)branch_addr,target_addr);
6375     if(compiled_target_addr) {
6376       set_jump_target((int)branch_addr,(int)compiled_target_addr);
6377       add_link(target_addr,stub);
6378     }
6379     else set_jump_target((int)branch_addr,(int)stub);
6380   }
6381 }
6382
6383 // Assemble the delay slot for the above
6384 static void pagespan_ds()
6385 {
6386   assem_debug("initial delay slot:\n");
6387   u_int vaddr=start+1;
6388   u_int page=get_page(vaddr);
6389   u_int vpage=get_vpage(vaddr);
6390   ll_add(jump_dirty+vpage,vaddr,(void *)out);
6391   do_dirty_stub_ds();
6392   ll_add(jump_in+page,vaddr,(void *)out);
6393   assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6394   if(regs[0].regmap[HOST_CCREG]!=CCREG)
6395     wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6396   if(regs[0].regmap[HOST_BTREG]!=BTREG)
6397     emit_writeword(HOST_BTREG,(int)&branch_target);
6398   load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6399   address_generation(0,&regs[0],regs[0].regmap_entry);
6400   if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
6401     load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6402   cop1_usable=0;
6403   is_delayslot=0;
6404   switch(itype[0]) {
6405     case ALU:
6406       alu_assemble(0,&regs[0]);break;
6407     case IMM16:
6408       imm16_assemble(0,&regs[0]);break;
6409     case SHIFT:
6410       shift_assemble(0,&regs[0]);break;
6411     case SHIFTIMM:
6412       shiftimm_assemble(0,&regs[0]);break;
6413     case LOAD:
6414       load_assemble(0,&regs[0]);break;
6415     case LOADLR:
6416       loadlr_assemble(0,&regs[0]);break;
6417     case STORE:
6418       store_assemble(0,&regs[0]);break;
6419     case STORELR:
6420       storelr_assemble(0,&regs[0]);break;
6421     case COP0:
6422       cop0_assemble(0,&regs[0]);break;
6423     case COP1:
6424       cop1_assemble(0,&regs[0]);break;
6425     case C1LS:
6426       c1ls_assemble(0,&regs[0]);break;
6427     case COP2:
6428       cop2_assemble(0,&regs[0]);break;
6429     case C2LS:
6430       c2ls_assemble(0,&regs[0]);break;
6431     case C2OP:
6432       c2op_assemble(0,&regs[0]);break;
6433     case FCONV:
6434       fconv_assemble(0,&regs[0]);break;
6435     case FLOAT:
6436       float_assemble(0,&regs[0]);break;
6437     case FCOMP:
6438       fcomp_assemble(0,&regs[0]);break;
6439     case MULTDIV:
6440       multdiv_assemble(0,&regs[0]);break;
6441     case MOV:
6442       mov_assemble(0,&regs[0]);break;
6443     case SYSCALL:
6444     case HLECALL:
6445     case SPAN:
6446     case UJUMP:
6447     case RJUMP:
6448     case CJUMP:
6449     case SJUMP:
6450     case FJUMP:
6451       printf("Jump in the delay slot.  This is probably a bug.\n");
6452   }
6453   int btaddr=get_reg(regs[0].regmap,BTREG);
6454   if(btaddr<0) {
6455     btaddr=get_reg(regs[0].regmap,-1);
6456     emit_readword((int)&branch_target,btaddr);
6457   }
6458   assert(btaddr!=HOST_CCREG);
6459   if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6460 #ifdef HOST_IMM8
6461   emit_movimm(start+4,HOST_TEMPREG);
6462   emit_cmp(btaddr,HOST_TEMPREG);
6463 #else
6464   emit_cmpimm(btaddr,start+4);
6465 #endif
6466   int branch=(int)out;
6467   emit_jeq(0);
6468   store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6469   emit_jmp(jump_vaddr_reg[btaddr]);
6470   set_jump_target(branch,(int)out);
6471   store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6472   load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6473 }
6474
6475 // Basic liveness analysis for MIPS registers
6476 void unneeded_registers(int istart,int iend,int r)
6477 {
6478   int i;
6479   uint64_t u,uu,b,bu;
6480   uint64_t temp_u,temp_uu;
6481   uint64_t tdep;
6482   if(iend==slen-1) {
6483     u=1;uu=1;
6484   }else{
6485     u=unneeded_reg[iend+1];
6486     uu=unneeded_reg_upper[iend+1];
6487     u=1;uu=1;
6488   }
6489   for (i=iend;i>=istart;i--)
6490   {
6491     //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6492     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6493     {
6494       // If subroutine call, flag return address as a possible branch target
6495       if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6496
6497       if(ba[i]<start || ba[i]>=(start+slen*4))
6498       {
6499         // Branch out of this block, flush all regs
6500         u=1;
6501         uu=1;
6502         /* Hexagon hack
6503         if(itype[i]==UJUMP&&rt1[i]==31)
6504         {
6505           uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6506         }
6507         if(itype[i]==RJUMP&&rs1[i]==31)
6508         {
6509           uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6510         }
6511         if(start>0x80000400&&start<0x80800000) {
6512           if(itype[i]==UJUMP&&rt1[i]==31)
6513           {
6514             //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6515             uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6516           }
6517           if(itype[i]==RJUMP&&rs1[i]==31)
6518           {
6519             //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6520             uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6521           }
6522         }*/
6523         branch_unneeded_reg[i]=u;
6524         branch_unneeded_reg_upper[i]=uu;
6525         // Merge in delay slot
6526         tdep=(~uu>>rt1[i+1])&1;
6527         u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6528         uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6529         u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6530         uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6531         uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6532         u|=1;uu|=1;
6533         // If branch is "likely" (and conditional)
6534         // then we skip the delay slot on the fall-thru path
6535         if(likely[i]) {
6536           if(i<slen-1) {
6537             u&=unneeded_reg[i+2];
6538             uu&=unneeded_reg_upper[i+2];
6539           }
6540           else
6541           {
6542             u=1;
6543             uu=1;
6544           }
6545         }
6546       }
6547       else
6548       {
6549         // Internal branch, flag target
6550         bt[(ba[i]-start)>>2]=1;
6551         if(ba[i]<=start+i*4) {
6552           // Backward branch
6553           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6554           {
6555             // Unconditional branch
6556             temp_u=1;temp_uu=1;
6557           } else {
6558             // Conditional branch (not taken case)
6559             temp_u=unneeded_reg[i+2];
6560             temp_uu=unneeded_reg_upper[i+2];
6561           }
6562           // Merge in delay slot
6563           tdep=(~temp_uu>>rt1[i+1])&1;
6564           temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6565           temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6566           temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6567           temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6568           temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6569           temp_u|=1;temp_uu|=1;
6570           // If branch is "likely" (and conditional)
6571           // then we skip the delay slot on the fall-thru path
6572           if(likely[i]) {
6573             if(i<slen-1) {
6574               temp_u&=unneeded_reg[i+2];
6575               temp_uu&=unneeded_reg_upper[i+2];
6576             }
6577             else
6578             {
6579               temp_u=1;
6580               temp_uu=1;
6581             }
6582           }
6583           tdep=(~temp_uu>>rt1[i])&1;
6584           temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6585           temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6586           temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6587           temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6588           temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6589           temp_u|=1;temp_uu|=1;
6590           unneeded_reg[i]=temp_u;
6591           unneeded_reg_upper[i]=temp_uu;
6592           // Only go three levels deep.  This recursion can take an
6593           // excessive amount of time if there are a lot of nested loops.
6594           if(r<2) {
6595             unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6596           }else{
6597             unneeded_reg[(ba[i]-start)>>2]=1;
6598             unneeded_reg_upper[(ba[i]-start)>>2]=1;
6599           }
6600         } /*else*/ if(1) {
6601           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6602           {
6603             // Unconditional branch
6604             u=unneeded_reg[(ba[i]-start)>>2];
6605             uu=unneeded_reg_upper[(ba[i]-start)>>2];
6606             branch_unneeded_reg[i]=u;
6607             branch_unneeded_reg_upper[i]=uu;
6608         //u=1;
6609         //uu=1;
6610         //branch_unneeded_reg[i]=u;
6611         //branch_unneeded_reg_upper[i]=uu;
6612             // Merge in delay slot
6613             tdep=(~uu>>rt1[i+1])&1;
6614             u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6615             uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6616             u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6617             uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6618             uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6619             u|=1;uu|=1;
6620           } else {
6621             // Conditional branch
6622             b=unneeded_reg[(ba[i]-start)>>2];
6623             bu=unneeded_reg_upper[(ba[i]-start)>>2];
6624             branch_unneeded_reg[i]=b;
6625             branch_unneeded_reg_upper[i]=bu;
6626         //b=1;
6627         //bu=1;
6628         //branch_unneeded_reg[i]=b;
6629         //branch_unneeded_reg_upper[i]=bu;
6630             // Branch delay slot
6631             tdep=(~uu>>rt1[i+1])&1;
6632             b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6633             bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6634             b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6635             bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6636             bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6637             b|=1;bu|=1;
6638             // If branch is "likely" then we skip the
6639             // delay slot on the fall-thru path
6640             if(likely[i]) {
6641               u=b;
6642               uu=bu;
6643               if(i<slen-1) {
6644                 u&=unneeded_reg[i+2];
6645                 uu&=unneeded_reg_upper[i+2];
6646         //u=1;
6647         //uu=1;
6648               }
6649             } else {
6650               u&=b;
6651               uu&=bu;
6652         //u=1;
6653         //uu=1;
6654             }
6655             if(i<slen-1) {
6656               branch_unneeded_reg[i]&=unneeded_reg[i+2];
6657               branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6658         //branch_unneeded_reg[i]=1;
6659         //branch_unneeded_reg_upper[i]=1;
6660             } else {
6661               branch_unneeded_reg[i]=1;
6662               branch_unneeded_reg_upper[i]=1;
6663             }
6664           }
6665         }
6666       }
6667     }
6668     else if(itype[i]==SYSCALL||itype[i]==HLECALL)
6669     {
6670       // SYSCALL instruction (software interrupt)
6671       u=1;
6672       uu=1;
6673     }
6674     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6675     {
6676       // ERET instruction (return from interrupt)
6677       u=1;
6678       uu=1;
6679     }
6680     //u=uu=1; // DEBUG
6681     tdep=(~uu>>rt1[i])&1;
6682     // Written registers are unneeded
6683     u|=1LL<<rt1[i];
6684     u|=1LL<<rt2[i];
6685     uu|=1LL<<rt1[i];
6686     uu|=1LL<<rt2[i];
6687     // Accessed registers are needed
6688     u&=~(1LL<<rs1[i]);
6689     u&=~(1LL<<rs2[i]);
6690     uu&=~(1LL<<us1[i]);
6691     uu&=~(1LL<<us2[i]);
6692     // Source-target dependencies
6693     uu&=~(tdep<<dep1[i]);
6694     uu&=~(tdep<<dep2[i]);
6695     // R0 is always unneeded
6696     u|=1;uu|=1;
6697     // Save it
6698     unneeded_reg[i]=u;
6699     unneeded_reg_upper[i]=uu;
6700 #ifdef FORCE32
6701     unneeded_reg_upper[i]=-1LL;
6702 #endif
6703     /*
6704     printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6705     printf("U:");
6706     int r;
6707     for(r=1;r<=CCREG;r++) {
6708       if((unneeded_reg[i]>>r)&1) {
6709         if(r==HIREG) printf(" HI");
6710         else if(r==LOREG) printf(" LO");
6711         else printf(" r%d",r);
6712       }
6713     }
6714     printf(" UU:");
6715     for(r=1;r<=CCREG;r++) {
6716       if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
6717         if(r==HIREG) printf(" HI");
6718         else if(r==LOREG) printf(" LO");
6719         else printf(" r%d",r);
6720       }
6721     }
6722     printf("\n");*/
6723   }
6724 }
6725
6726 // Identify registers which are likely to contain 32-bit values
6727 // This is used to predict whether any branches will jump to a
6728 // location with 64-bit values in registers.
6729 static void provisional_32bit()
6730 {
6731   int i,j;
6732   uint64_t is32=1;
6733   uint64_t lastbranch=1;
6734
6735   for(i=0;i<slen;i++)
6736   {
6737     if(i>0) {
6738       if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
6739         if(i>1) is32=lastbranch;
6740         else is32=1;
6741       }
6742     }
6743     if(i>1)
6744     {
6745       if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
6746         if(likely[i-2]) {
6747           if(i>2) is32=lastbranch;
6748           else is32=1;
6749         }
6750       }
6751       if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
6752       {
6753         if(rs1[i-2]==0||rs2[i-2]==0)
6754         {
6755           if(rs1[i-2]) {
6756             is32|=1LL<<rs1[i-2];
6757           }
6758           if(rs2[i-2]) {
6759             is32|=1LL<<rs2[i-2];
6760           }
6761         }
6762       }
6763     }
6764     // If something jumps here with 64-bit values
6765     // then promote those registers to 64 bits
6766     if(bt[i])
6767     {
6768       uint64_t temp_is32=is32;
6769       for(j=i-1;j>=0;j--)
6770       {
6771         if(ba[j]==start+i*4)
6772           //temp_is32&=branch_regs[j].is32;
6773           temp_is32&=p32[j];
6774       }
6775       for(j=i;j<slen;j++)
6776       {
6777         if(ba[j]==start+i*4)
6778           temp_is32=1;
6779       }
6780       is32=temp_is32;
6781     }
6782     int type=itype[i];
6783     int op=opcode[i];
6784     int op2=opcode2[i];
6785     int rt=rt1[i];
6786     int s1=rs1[i];
6787     int s2=rs2[i];
6788     if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
6789       // Branches don't write registers, consider the delay slot instead.
6790       type=itype[i+1];
6791       op=opcode[i+1];
6792       op2=opcode2[i+1];
6793       rt=rt1[i+1];
6794       s1=rs1[i+1];
6795       s2=rs2[i+1];
6796       lastbranch=is32;
6797     }
6798     switch(type) {
6799       case LOAD:
6800         if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
6801            opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
6802           is32&=~(1LL<<rt);
6803         else
6804           is32|=1LL<<rt;
6805         break;
6806       case STORE:
6807       case STORELR:
6808         break;
6809       case LOADLR:
6810         if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
6811         if(op==0x22) is32|=1LL<<rt; // LWL
6812         break;
6813       case IMM16:
6814         if (op==0x08||op==0x09|| // ADDI/ADDIU
6815             op==0x0a||op==0x0b|| // SLTI/SLTIU
6816             op==0x0c|| // ANDI
6817             op==0x0f)  // LUI
6818         {
6819           is32|=1LL<<rt;
6820         }
6821         if(op==0x18||op==0x19) { // DADDI/DADDIU
6822           is32&=~(1LL<<rt);
6823           //if(imm[i]==0)
6824           //  is32|=((is32>>s1)&1LL)<<rt;
6825         }
6826         if(op==0x0d||op==0x0e) { // ORI/XORI
6827           uint64_t sr=((is32>>s1)&1LL);
6828           is32&=~(1LL<<rt);
6829           is32|=sr<<rt;
6830         }
6831         break;
6832       case UJUMP:
6833         break;
6834       case RJUMP:
6835         break;
6836       case CJUMP:
6837         break;
6838       case SJUMP:
6839         break;
6840       case FJUMP:
6841         break;
6842       case ALU:
6843         if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
6844           is32|=1LL<<rt;
6845         }
6846         if(op2==0x2a||op2==0x2b) { // SLT/SLTU
6847           is32|=1LL<<rt;
6848         }
6849         else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
6850           uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
6851           is32&=~(1LL<<rt);
6852           is32|=sr<<rt;
6853         }
6854         else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
6855           if(s1==0&&s2==0) {
6856             is32|=1LL<<rt;
6857           }
6858           else if(s2==0) {
6859             uint64_t sr=((is32>>s1)&1LL);
6860             is32&=~(1LL<<rt);
6861             is32|=sr<<rt;
6862           }
6863           else if(s1==0) {
6864             uint64_t sr=((is32>>s2)&1LL);
6865             is32&=~(1LL<<rt);
6866             is32|=sr<<rt;
6867           }
6868           else {
6869             is32&=~(1LL<<rt);
6870           }
6871         }
6872         else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
6873           if(s1==0&&s2==0) {
6874             is32|=1LL<<rt;
6875           }
6876           else if(s2==0) {
6877             uint64_t sr=((is32>>s1)&1LL);
6878             is32&=~(1LL<<rt);
6879             is32|=sr<<rt;
6880           }
6881           else {
6882             is32&=~(1LL<<rt);
6883           }
6884         }
6885         break;
6886       case MULTDIV:
6887         if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
6888           is32&=~((1LL<<HIREG)|(1LL<<LOREG));
6889         }
6890         else {
6891           is32|=(1LL<<HIREG)|(1LL<<LOREG);
6892         }
6893         break;
6894       case MOV:
6895         {
6896           uint64_t sr=((is32>>s1)&1LL);
6897           is32&=~(1LL<<rt);
6898           is32|=sr<<rt;
6899         }
6900         break;
6901       case SHIFT:
6902         if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
6903         else is32|=1LL<<rt; // SLLV/SRLV/SRAV
6904         break;
6905       case SHIFTIMM:
6906         is32|=1LL<<rt;
6907         // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
6908         if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
6909         break;
6910       case COP0:
6911         if(op2==0) is32|=1LL<<rt; // MFC0
6912         break;
6913       case COP1:
6914       case COP2:
6915         if(op2==0) is32|=1LL<<rt; // MFC1
6916         if(op2==1) is32&=~(1LL<<rt); // DMFC1
6917         if(op2==2) is32|=1LL<<rt; // CFC1
6918         break;
6919       case C1LS:
6920       case C2LS:
6921         break;
6922       case FLOAT:
6923       case FCONV:
6924         break;
6925       case FCOMP:
6926         break;
6927       case C2OP:
6928       case SYSCALL:
6929       case HLECALL:
6930         break;
6931       default:
6932         break;
6933     }
6934     is32|=1;
6935     p32[i]=is32;
6936
6937     if(i>0)
6938     {
6939       if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
6940       {
6941         if(rt1[i-1]==31) // JAL/JALR
6942         {
6943           // Subroutine call will return here, don't alloc any registers
6944           is32=1;
6945         }
6946         else if(i+1<slen)
6947         {
6948           // Internal branch will jump here, match registers to caller
6949           is32=0x3FFFFFFFFLL;
6950         }
6951       }
6952     }
6953   }
6954 }
6955
6956 // Identify registers which may be assumed to contain 32-bit values
6957 // and where optimizations will rely on this.
6958 // This is used to determine whether backward branches can safely
6959 // jump to a location with 64-bit values in registers.
6960 static void provisional_r32()
6961 {
6962   u_int r32=0;
6963   int i;
6964
6965   for (i=slen-1;i>=0;i--)
6966   {
6967     int hr;
6968     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6969     {
6970       if(ba[i]<start || ba[i]>=(start+slen*4))
6971       {
6972         // Branch out of this block, don't need anything
6973         r32=0;
6974       }
6975       else
6976       {
6977         // Internal branch
6978         // Need whatever matches the target
6979         // (and doesn't get overwritten by the delay slot instruction)
6980         r32=0;
6981         int t=(ba[i]-start)>>2;
6982         if(ba[i]>start+i*4) {
6983           // Forward branch
6984           //if(!(requires_32bit[t]&~regs[i].was32))
6985           //  r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
6986           if(!(pr32[t]&~regs[i].was32))
6987             r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
6988         }else{
6989           // Backward branch
6990           if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
6991             r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
6992         }
6993       }
6994       // Conditional branch may need registers for following instructions
6995       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
6996       {
6997         if(i<slen-2) {
6998           //r32|=requires_32bit[i+2];
6999           r32|=pr32[i+2];
7000           r32&=regs[i].was32;
7001           // Mark this address as a branch target since it may be called
7002           // upon return from interrupt
7003           //bt[i+2]=1;
7004         }
7005       }
7006       // Merge in delay slot
7007       if(!likely[i]) {
7008         // These are overwritten unless the branch is "likely"
7009         // and the delay slot is nullified if not taken
7010         r32&=~(1LL<<rt1[i+1]);
7011         r32&=~(1LL<<rt2[i+1]);
7012       }
7013       // Assume these are needed (delay slot)
7014       if(us1[i+1]>0)
7015       {
7016         if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7017       }
7018       if(us2[i+1]>0)
7019       {
7020         if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7021       }
7022       if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7023       {
7024         if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7025       }
7026       if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7027       {
7028         if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7029       }
7030     }
7031     else if(itype[i]==SYSCALL||itype[i]==HLECALL)
7032     {
7033       // SYSCALL instruction (software interrupt)
7034       r32=0;
7035     }
7036     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7037     {
7038       // ERET instruction (return from interrupt)
7039       r32=0;
7040     }
7041     // Check 32 bits
7042     r32&=~(1LL<<rt1[i]);
7043     r32&=~(1LL<<rt2[i]);
7044     if(us1[i]>0)
7045     {
7046       if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7047     }
7048     if(us2[i]>0)
7049     {
7050       if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7051     }
7052     if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7053     {
7054       if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7055     }
7056     if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7057     {
7058       if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7059     }
7060     //requires_32bit[i]=r32;
7061     pr32[i]=r32;
7062
7063     // Dirty registers which are 32-bit, require 32-bit input
7064     // as they will be written as 32-bit values
7065     for(hr=0;hr<HOST_REGS;hr++)
7066     {
7067       if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
7068         if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7069           if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7070           pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7071           //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7072         }
7073       }
7074     }
7075   }
7076 }
7077
7078 // Write back dirty registers as soon as we will no longer modify them,
7079 // so that we don't end up with lots of writes at the branches.
7080 void clean_registers(int istart,int iend,int wr)
7081 {
7082   int i;
7083   int r;
7084   u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7085   u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7086   if(iend==slen-1) {
7087     will_dirty_i=will_dirty_next=0;
7088     wont_dirty_i=wont_dirty_next=0;
7089   }else{
7090     will_dirty_i=will_dirty_next=will_dirty[iend+1];
7091     wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7092   }
7093   for (i=iend;i>=istart;i--)
7094   {
7095     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7096     {
7097       if(ba[i]<start || ba[i]>=(start+slen*4))
7098       {
7099         // Branch out of this block, flush all regs
7100         if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7101         {
7102           // Unconditional branch
7103           will_dirty_i=0;
7104           wont_dirty_i=0;
7105           // Merge in delay slot (will dirty)
7106           for(r=0;r<HOST_REGS;r++) {
7107             if(r!=EXCLUDE_REG) {
7108               if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7109               if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7110               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7111               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7112               if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7113               if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7114               if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7115               if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7116               if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7117               if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7118               if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7119               if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7120               if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7121               if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7122             }
7123           }
7124         }
7125         else
7126         {
7127           // Conditional branch
7128           will_dirty_i=0;
7129           wont_dirty_i=wont_dirty_next;
7130           // Merge in delay slot (will dirty)
7131           for(r=0;r<HOST_REGS;r++) {
7132             if(r!=EXCLUDE_REG) {
7133               if(!likely[i]) {
7134                 // Might not dirty if likely branch is not taken
7135                 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7136                 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7137                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7138                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7139                 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7140                 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7141                 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7142                 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7143                 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7144                 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7145                 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7146                 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7147                 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7148                 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7149               }
7150             }
7151           }
7152         }
7153         // Merge in delay slot (wont dirty)
7154         for(r=0;r<HOST_REGS;r++) {
7155           if(r!=EXCLUDE_REG) {
7156             if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7157             if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7158             if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7159             if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7160             if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7161             if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7162             if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7163             if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7164             if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7165             if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7166           }
7167         }
7168         if(wr) {
7169           #ifndef DESTRUCTIVE_WRITEBACK
7170           branch_regs[i].dirty&=wont_dirty_i;
7171           #endif
7172           branch_regs[i].dirty|=will_dirty_i;
7173         }
7174       }
7175       else
7176       {
7177         // Internal branch
7178         if(ba[i]<=start+i*4) {
7179           // Backward branch
7180           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7181           {
7182             // Unconditional branch
7183             temp_will_dirty=0;
7184             temp_wont_dirty=0;
7185             // Merge in delay slot (will dirty)
7186             for(r=0;r<HOST_REGS;r++) {
7187               if(r!=EXCLUDE_REG) {
7188                 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7189                 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7190                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7191                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7192                 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7193                 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7194                 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7195                 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7196                 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7197                 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7198                 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7199                 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7200                 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7201                 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7202               }
7203             }
7204           } else {
7205             // Conditional branch (not taken case)
7206             temp_will_dirty=will_dirty_next;
7207             temp_wont_dirty=wont_dirty_next;
7208             // Merge in delay slot (will dirty)
7209             for(r=0;r<HOST_REGS;r++) {
7210               if(r!=EXCLUDE_REG) {
7211                 if(!likely[i]) {
7212                   // Will not dirty if likely branch is not taken
7213                   if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7214                   if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7215                   if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7216                   if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7217                   if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7218                   if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7219                   if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7220                   //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7221                   //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7222                   if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7223                   if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7224                   if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7225                   if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7226                   if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7227                 }
7228               }
7229             }
7230           }
7231           // Merge in delay slot (wont dirty)
7232           for(r=0;r<HOST_REGS;r++) {
7233             if(r!=EXCLUDE_REG) {
7234               if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7235               if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7236               if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7237               if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7238               if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7239               if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7240               if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7241               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7242               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7243               if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7244             }
7245           }
7246           // Deal with changed mappings
7247           if(i<iend) {
7248             for(r=0;r<HOST_REGS;r++) {
7249               if(r!=EXCLUDE_REG) {
7250                 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7251                   temp_will_dirty&=~(1<<r);
7252                   temp_wont_dirty&=~(1<<r);
7253                   if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7254                     temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7255                     temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7256                   } else {
7257                     temp_will_dirty|=1<<r;
7258                     temp_wont_dirty|=1<<r;
7259                   }
7260                 }
7261               }
7262             }
7263           }
7264           if(wr) {
7265             will_dirty[i]=temp_will_dirty;
7266             wont_dirty[i]=temp_wont_dirty;
7267             clean_registers((ba[i]-start)>>2,i-1,0);
7268           }else{
7269             // Limit recursion.  It can take an excessive amount
7270             // of time if there are a lot of nested loops.
7271             will_dirty[(ba[i]-start)>>2]=0;
7272             wont_dirty[(ba[i]-start)>>2]=-1;
7273           }
7274         }
7275         /*else*/ if(1)
7276         {
7277           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7278           {
7279             // Unconditional branch
7280             will_dirty_i=0;
7281             wont_dirty_i=0;
7282           //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7283             for(r=0;r<HOST_REGS;r++) {
7284               if(r!=EXCLUDE_REG) {
7285                 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7286                   will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7287                   wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7288                 }
7289               }
7290             }
7291           //}
7292             // Merge in delay slot
7293             for(r=0;r<HOST_REGS;r++) {
7294               if(r!=EXCLUDE_REG) {
7295                 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7296                 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7297                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7298                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7299                 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7300                 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7301                 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7302                 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7303                 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7304                 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7305                 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7306                 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7307                 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7308                 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7309               }
7310             }
7311           } else {
7312             // Conditional branch
7313             will_dirty_i=will_dirty_next;
7314             wont_dirty_i=wont_dirty_next;
7315           //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7316             for(r=0;r<HOST_REGS;r++) {
7317               if(r!=EXCLUDE_REG) {
7318                 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7319                   will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7320                   wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7321                 }
7322                 else
7323                 {
7324                   will_dirty_i&=~(1<<r);
7325                 }
7326                 // Treat delay slot as part of branch too
7327                 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7328                   will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7329                   wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7330                 }
7331                 else
7332                 {
7333                   will_dirty[i+1]&=~(1<<r);
7334                 }*/
7335               }
7336             }
7337           //}
7338             // Merge in delay slot
7339             for(r=0;r<HOST_REGS;r++) {
7340               if(r!=EXCLUDE_REG) {
7341                 if(!likely[i]) {
7342                   // Might not dirty if likely branch is not taken
7343                   if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7344                   if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7345                   if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7346                   if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7347                   if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7348                   if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7349                   if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7350                   //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7351                   //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7352                   if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7353                   if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7354                   if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7355                   if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7356                   if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7357                 }
7358               }
7359             }
7360           }
7361           // Merge in delay slot
7362           for(r=0;r<HOST_REGS;r++) {
7363             if(r!=EXCLUDE_REG) {
7364               if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7365               if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7366               if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7367               if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7368               if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7369               if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7370               if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7371               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7372               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7373               if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7374             }
7375           }
7376           if(wr) {
7377             #ifndef DESTRUCTIVE_WRITEBACK
7378             branch_regs[i].dirty&=wont_dirty_i;
7379             #endif
7380             branch_regs[i].dirty|=will_dirty_i;
7381           }
7382         }
7383       }
7384     }
7385     else if(itype[i]==SYSCALL||itype[i]==HLECALL)
7386     {
7387       // SYSCALL instruction (software interrupt)
7388       will_dirty_i=0;
7389       wont_dirty_i=0;
7390     }
7391     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7392     {
7393       // ERET instruction (return from interrupt)
7394       will_dirty_i=0;
7395       wont_dirty_i=0;
7396     }
7397     will_dirty_next=will_dirty_i;
7398     wont_dirty_next=wont_dirty_i;
7399     for(r=0;r<HOST_REGS;r++) {
7400       if(r!=EXCLUDE_REG) {
7401         if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7402         if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7403         if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7404         if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7405         if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7406         if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7407         if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7408         if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7409         if(i>istart) {
7410           if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7411           {
7412             // Don't store a register immediately after writing it,
7413             // may prevent dual-issue.
7414             if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7415             if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7416           }
7417         }
7418       }
7419     }
7420     // Save it
7421     will_dirty[i]=will_dirty_i;
7422     wont_dirty[i]=wont_dirty_i;
7423     // Mark registers that won't be dirtied as not dirty
7424     if(wr) {
7425       /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7426       for(r=0;r<HOST_REGS;r++) {
7427         if((will_dirty_i>>r)&1) {
7428           printf(" r%d",r);
7429         }
7430       }
7431       printf("\n");*/
7432
7433       //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7434         regs[i].dirty|=will_dirty_i;
7435         #ifndef DESTRUCTIVE_WRITEBACK
7436         regs[i].dirty&=wont_dirty_i;
7437         if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7438         {
7439           if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7440             for(r=0;r<HOST_REGS;r++) {
7441               if(r!=EXCLUDE_REG) {
7442                 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7443                   regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7444                 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7445               }
7446             }
7447           }
7448         }
7449         else
7450         {
7451           if(i<iend) {
7452             for(r=0;r<HOST_REGS;r++) {
7453               if(r!=EXCLUDE_REG) {
7454                 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7455                   regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7456                 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7457               }
7458             }
7459           }
7460         }
7461         #endif
7462       //}
7463     }
7464     // Deal with changed mappings
7465     temp_will_dirty=will_dirty_i;
7466     temp_wont_dirty=wont_dirty_i;
7467     for(r=0;r<HOST_REGS;r++) {
7468       if(r!=EXCLUDE_REG) {
7469         int nr;
7470         if(regs[i].regmap[r]==regmap_pre[i][r]) {
7471           if(wr) {
7472             #ifndef DESTRUCTIVE_WRITEBACK
7473             regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7474             #endif
7475             regs[i].wasdirty|=will_dirty_i&(1<<r);
7476           }
7477         }
7478         else if((nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7479           // Register moved to a different register
7480           will_dirty_i&=~(1<<r);
7481           wont_dirty_i&=~(1<<r);
7482           will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7483           wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7484           if(wr) {
7485             #ifndef DESTRUCTIVE_WRITEBACK
7486             regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7487             #endif
7488             regs[i].wasdirty|=will_dirty_i&(1<<r);
7489           }
7490         }
7491         else {
7492           will_dirty_i&=~(1<<r);
7493           wont_dirty_i&=~(1<<r);
7494           if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7495             will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7496             wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7497           } else {
7498             wont_dirty_i|=1<<r;
7499             /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7500           }
7501         }
7502       }
7503     }
7504   }
7505 }
7506
7507   /* disassembly */
7508 void disassemble_inst(int i)
7509 {
7510     if (bt[i]) printf("*"); else printf(" ");
7511     switch(itype[i]) {
7512       case UJUMP:
7513         printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7514       case CJUMP:
7515         printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7516       case SJUMP:
7517         printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7518       case FJUMP:
7519         printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7520       case RJUMP:
7521         if (rt1[i]!=31)
7522           printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7523         else
7524           printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7525         break;
7526       case SPAN:
7527         printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7528       case IMM16:
7529         if(opcode[i]==0xf) //LUI
7530           printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7531         else
7532           printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7533         break;
7534       case LOAD:
7535       case LOADLR:
7536         printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7537         break;
7538       case STORE:
7539       case STORELR:
7540         printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7541         break;
7542       case ALU:
7543       case SHIFT:
7544         printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7545         break;
7546       case MULTDIV:
7547         printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7548         break;
7549       case SHIFTIMM:
7550         printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7551         break;
7552       case MOV:
7553         if((opcode2[i]&0x1d)==0x10)
7554           printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7555         else if((opcode2[i]&0x1d)==0x11)
7556           printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7557         else
7558           printf (" %x: %s\n",start+i*4,insn[i]);
7559         break;
7560       case COP0:
7561         if(opcode2[i]==0)
7562           printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7563         else if(opcode2[i]==4)
7564           printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7565         else printf (" %x: %s\n",start+i*4,insn[i]);
7566         break;
7567       case COP1:
7568         if(opcode2[i]<3)
7569           printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7570         else if(opcode2[i]>3)
7571           printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7572         else printf (" %x: %s\n",start+i*4,insn[i]);
7573         break;
7574       case COP2:
7575         if(opcode2[i]<3)
7576           printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7577         else if(opcode2[i]>3)
7578           printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7579         else printf (" %x: %s\n",start+i*4,insn[i]);
7580         break;
7581       case C1LS:
7582         printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7583         break;
7584       case C2LS:
7585         printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7586         break;
7587       default:
7588         //printf (" %s %8x\n",insn[i],source[i]);
7589         printf (" %x: %s\n",start+i*4,insn[i]);
7590     }
7591 }
7592
7593 void new_dynarec_init()
7594 {
7595   printf("Init new dynarec\n");
7596   out=(u_char *)BASE_ADDR;
7597   if (mmap (out, 1<<TARGET_SIZE_2,
7598             PROT_READ | PROT_WRITE | PROT_EXEC,
7599             MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
7600             -1, 0) <= 0) {printf("mmap() failed\n");}
7601 #ifdef MUPEN64
7602   rdword=&readmem_dword;
7603   fake_pc.f.r.rs=&readmem_dword;
7604   fake_pc.f.r.rt=&readmem_dword;
7605   fake_pc.f.r.rd=&readmem_dword;
7606 #endif
7607   int n;
7608   for(n=0x80000;n<0x80800;n++)
7609     invalid_code[n]=1;
7610   for(n=0;n<65536;n++)
7611     hash_table[n][0]=hash_table[n][2]=-1;
7612   memset(mini_ht,-1,sizeof(mini_ht));
7613   memset(restore_candidate,0,sizeof(restore_candidate));
7614   copy=shadow;
7615   expirep=16384; // Expiry pointer, +2 blocks
7616   pending_exception=0;
7617   literalcount=0;
7618 #ifdef HOST_IMM8
7619   // Copy this into local area so we don't have to put it in every literal pool
7620   invc_ptr=invalid_code;
7621 #endif
7622   stop_after_jal=0;
7623   // TLB
7624   using_tlb=0;
7625   for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7626     memory_map[n]=-1;
7627   for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7628     memory_map[n]=((u_int)rdram-0x80000000)>>2;
7629   for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7630     memory_map[n]=-1;
7631 #ifdef MUPEN64
7632   for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
7633     writemem[n] = write_nomem_new;
7634     writememb[n] = write_nomemb_new;
7635     writememh[n] = write_nomemh_new;
7636 #ifndef FORCE32
7637     writememd[n] = write_nomemd_new;
7638 #endif
7639     readmem[n] = read_nomem_new;
7640     readmemb[n] = read_nomemb_new;
7641     readmemh[n] = read_nomemh_new;
7642 #ifndef FORCE32
7643     readmemd[n] = read_nomemd_new;
7644 #endif
7645   }
7646   for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
7647     writemem[n] = write_rdram_new;
7648     writememb[n] = write_rdramb_new;
7649     writememh[n] = write_rdramh_new;
7650 #ifndef FORCE32
7651     writememd[n] = write_rdramd_new;
7652 #endif
7653   }
7654   for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
7655     writemem[n] = write_nomem_new;
7656     writememb[n] = write_nomemb_new;
7657     writememh[n] = write_nomemh_new;
7658 #ifndef FORCE32
7659     writememd[n] = write_nomemd_new;
7660 #endif
7661     readmem[n] = read_nomem_new;
7662     readmemb[n] = read_nomemb_new;
7663     readmemh[n] = read_nomemh_new;
7664 #ifndef FORCE32
7665     readmemd[n] = read_nomemd_new;
7666 #endif
7667   }
7668 #endif
7669   tlb_hacks();
7670   arch_init();
7671 }
7672
7673 void new_dynarec_cleanup()
7674 {
7675   int n;
7676   if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
7677   for(n=0;n<4096;n++) ll_clear(jump_in+n);
7678   for(n=0;n<4096;n++) ll_clear(jump_out+n);
7679   for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7680   #ifdef ROM_COPY
7681   if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
7682   #endif
7683 }
7684
7685 int new_recompile_block(int addr)
7686 {
7687 /*
7688   if(addr==0x800cd050) {
7689     int block;
7690     for(block=0x80000;block<0x80800;block++) invalidate_block(block);
7691     int n;
7692     for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
7693   }
7694 */
7695   //if(Count==365117028) tracedebug=1;
7696   assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7697   //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7698   //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
7699   //if(debug)
7700   //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
7701   //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
7702   /*if(Count>=312978186) {
7703     rlist();
7704   }*/
7705   //rlist();
7706   start = (u_int)addr&~3;
7707   //assert(((u_int)addr&1)==0);
7708 #ifdef PCSX
7709   if (Config.HLE && start == 0x80001000) {
7710     // XXX: is this enough? Maybe check hleSoftCall?
7711     u_int page=get_page(start);
7712     ll_add(jump_in+page,start,out);
7713     invalid_code[start>>12]=0;
7714     emit_movimm(start,0);
7715     emit_writeword(0,(int)&pcaddr);
7716     emit_jmp((int)new_dyna_leave); // enough??
7717     return 0;
7718   }
7719   else if ((u_int)addr < 0x00200000) {
7720     // used for BIOS calls mostly?
7721     source = (u_int *)((u_int)rdram+start-0);
7722     pagelimit = 0x00200000;
7723   }
7724   else
7725 #endif
7726 #ifdef MUPEN64
7727   if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
7728     source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
7729     pagelimit = 0xa4001000;
7730   }
7731   else
7732 #endif
7733   if ((int)addr >= 0x80000000 && (int)addr < 0x80800000) {
7734     source = (u_int *)((u_int)rdram+start-0x80000000);
7735     pagelimit = 0x80800000;
7736   }
7737 #ifndef DISABLE_TLB
7738   else if ((signed int)addr >= (signed int)0xC0000000) {
7739     //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
7740     //if(tlb_LUT_r[start>>12])
7741       //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
7742     if((signed int)memory_map[start>>12]>=0) {
7743       source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
7744       pagelimit=(start+4096)&0xFFFFF000;
7745       int map=memory_map[start>>12];
7746       int i;
7747       for(i=0;i<5;i++) {
7748         //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
7749         if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
7750       }
7751       assem_debug("pagelimit=%x\n",pagelimit);
7752       assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
7753     }
7754     else {
7755       assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
7756       //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
7757       return 1; // Caller will invoke exception handler
7758     }
7759     //printf("source= %x\n",(int)source);
7760   }
7761 #endif
7762   else {
7763     printf("Compile at bogus memory address: %x \n", (int)addr);
7764     exit(1);
7765   }
7766
7767   /* Pass 1: disassemble */
7768   /* Pass 2: register dependencies, branch targets */
7769   /* Pass 3: register allocation */
7770   /* Pass 4: branch dependencies */
7771   /* Pass 5: pre-alloc */
7772   /* Pass 6: optimize clean/dirty state */
7773   /* Pass 7: flag 32-bit registers */
7774   /* Pass 8: assembly */
7775   /* Pass 9: linker */
7776   /* Pass 10: garbage collection / free memory */
7777
7778   int i,j;
7779   int done=0;
7780   unsigned int type,op,op2;
7781
7782   //printf("addr = %x source = %x %x\n", addr,source,source[0]);
7783
7784   /* Pass 1 disassembly */
7785
7786   for(i=0;!done;i++) {
7787     bt[i]=0;likely[i]=0;op2=0;
7788     opcode[i]=op=source[i]>>26;
7789     switch(op)
7790     {
7791       case 0x00: strcpy(insn[i],"special"); type=NI;
7792         op2=source[i]&0x3f;
7793         switch(op2)
7794         {
7795           case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
7796           case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
7797           case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
7798           case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
7799           case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
7800           case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
7801           case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
7802           case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
7803           case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
7804           case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
7805           case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
7806           case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
7807           case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
7808           case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
7809           case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
7810           case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
7811           case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
7812           case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
7813           case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
7814           case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
7815           case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
7816           case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
7817           case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
7818           case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
7819           case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
7820           case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
7821           case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
7822           case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
7823           case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
7824           case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
7825           case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
7826           case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
7827           case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
7828           case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
7829           case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
7830           case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
7831           case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
7832           case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
7833           case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
7834           case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
7835           case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
7836           case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
7837           case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
7838           case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
7839           case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
7840           case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
7841           case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
7842           case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
7843           case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
7844           case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
7845           case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
7846           case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
7847         }
7848         break;
7849       case 0x01: strcpy(insn[i],"regimm"); type=NI;
7850         op2=(source[i]>>16)&0x1f;
7851         switch(op2)
7852         {
7853           case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
7854           case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
7855           case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
7856           case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
7857           case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
7858           case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
7859           case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
7860           case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
7861           case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
7862           case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
7863           case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
7864           case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
7865           case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
7866           case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
7867         }
7868         break;
7869       case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
7870       case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
7871       case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
7872       case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
7873       case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
7874       case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
7875       case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
7876       case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
7877       case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
7878       case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
7879       case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
7880       case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
7881       case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
7882       case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
7883       case 0x10: strcpy(insn[i],"cop0"); type=NI;
7884         op2=(source[i]>>21)&0x1f;
7885         switch(op2)
7886         {
7887           case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
7888           case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
7889           case 0x10: strcpy(insn[i],"tlb"); type=NI;
7890           switch(source[i]&0x3f)
7891           {
7892             case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
7893             case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
7894             case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
7895             case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
7896             case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
7897           }
7898         }
7899         break;
7900       case 0x11: strcpy(insn[i],"cop1"); type=NI;
7901         op2=(source[i]>>21)&0x1f;
7902         switch(op2)
7903         {
7904           case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
7905           case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
7906           case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
7907           case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
7908           case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
7909           case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
7910           case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
7911           switch((source[i]>>16)&0x3)
7912           {
7913             case 0x00: strcpy(insn[i],"BC1F"); break;
7914             case 0x01: strcpy(insn[i],"BC1T"); break;
7915             case 0x02: strcpy(insn[i],"BC1FL"); break;
7916             case 0x03: strcpy(insn[i],"BC1TL"); break;
7917           }
7918           break;
7919           case 0x10: strcpy(insn[i],"C1.S"); type=NI;
7920           switch(source[i]&0x3f)
7921           {
7922             case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
7923             case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
7924             case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
7925             case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
7926             case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
7927             case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
7928             case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
7929             case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
7930             case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
7931             case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
7932             case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
7933             case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
7934             case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
7935             case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
7936             case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
7937             case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
7938             case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
7939             case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
7940             case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
7941             case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
7942             case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
7943             case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
7944             case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
7945             case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
7946             case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
7947             case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
7948             case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
7949             case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
7950             case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
7951             case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
7952             case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
7953             case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
7954             case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
7955             case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
7956             case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
7957           }
7958           break;
7959           case 0x11: strcpy(insn[i],"C1.D"); type=NI;
7960           switch(source[i]&0x3f)
7961           {
7962             case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
7963             case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
7964             case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
7965             case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
7966             case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
7967             case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
7968             case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
7969             case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
7970             case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
7971             case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
7972             case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
7973             case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
7974             case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
7975             case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
7976             case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
7977             case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
7978             case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
7979             case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
7980             case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
7981             case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
7982             case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
7983             case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
7984             case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
7985             case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
7986             case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
7987             case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
7988             case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
7989             case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
7990             case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
7991             case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
7992             case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
7993             case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
7994             case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
7995             case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
7996             case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
7997           }
7998           break;
7999           case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8000           switch(source[i]&0x3f)
8001           {
8002             case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8003             case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8004           }
8005           break;
8006           case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8007           switch(source[i]&0x3f)
8008           {
8009             case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8010             case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8011           }
8012           break;
8013         }
8014         break;
8015       case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8016       case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8017       case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8018       case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8019       case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8020       case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8021       case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8022       case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
8023       case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8024       case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8025       case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8026       case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8027       case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8028       case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8029       case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
8030       case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
8031       case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8032       case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8033       case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8034       case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
8035       case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8036       case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
8037       case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8038       case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8039       case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8040       case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
8041       case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8042       case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8043       case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
8044       case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8045       case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
8046       case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8047       case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8048       case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
8049 #ifdef PCSX
8050       case 0x12: strcpy(insn[i],"COP2"); type=NI;
8051         op2=(source[i]>>21)&0x1f;
8052         switch(op2)
8053         {
8054           case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8055           case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8056           case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8057           case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
8058           default:
8059             if (gte_handlers[source[i]&0x3f]!=NULL) {
8060               snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8061               type=C2OP;
8062             }
8063             break;
8064         }
8065         break;
8066       case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8067       case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8068       case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8069 #endif
8070       default: strcpy(insn[i],"???"); type=NI;
8071         printf("NI %08x @%08x\n", source[i], addr + i*4);
8072         break;
8073     }
8074     itype[i]=type;
8075     opcode2[i]=op2;
8076     /* Get registers/immediates */
8077     lt1[i]=0;
8078     us1[i]=0;
8079     us2[i]=0;
8080     dep1[i]=0;
8081     dep2[i]=0;
8082     switch(type) {
8083       case LOAD:
8084         rs1[i]=(source[i]>>21)&0x1f;
8085         rs2[i]=0;
8086         rt1[i]=(source[i]>>16)&0x1f;
8087         rt2[i]=0;
8088         imm[i]=(short)source[i];
8089         break;
8090       case STORE:
8091       case STORELR:
8092         rs1[i]=(source[i]>>21)&0x1f;
8093         rs2[i]=(source[i]>>16)&0x1f;
8094         rt1[i]=0;
8095         rt2[i]=0;
8096         imm[i]=(short)source[i];
8097         if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8098         break;
8099       case LOADLR:
8100         // LWL/LWR only load part of the register,
8101         // therefore the target register must be treated as a source too
8102         rs1[i]=(source[i]>>21)&0x1f;
8103         rs2[i]=(source[i]>>16)&0x1f;
8104         rt1[i]=(source[i]>>16)&0x1f;
8105         rt2[i]=0;
8106         imm[i]=(short)source[i];
8107         if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8108         if(op==0x26) dep1[i]=rt1[i]; // LWR
8109         break;
8110       case IMM16:
8111         if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8112         else rs1[i]=(source[i]>>21)&0x1f;
8113         rs2[i]=0;
8114         rt1[i]=(source[i]>>16)&0x1f;
8115         rt2[i]=0;
8116         if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8117           imm[i]=(unsigned short)source[i];
8118         }else{
8119           imm[i]=(short)source[i];
8120         }
8121         if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8122         if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8123         if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8124         break;
8125       case UJUMP:
8126         rs1[i]=0;
8127         rs2[i]=0;
8128         rt1[i]=0;
8129         rt2[i]=0;
8130         // The JAL instruction writes to r31.
8131         if (op&1) {
8132           rt1[i]=31;
8133         }
8134         rs2[i]=CCREG;
8135         break;
8136       case RJUMP:
8137         rs1[i]=(source[i]>>21)&0x1f;
8138         rs2[i]=0;
8139         rt1[i]=0;
8140         rt2[i]=0;
8141         // The JALR instruction writes to rd.
8142         if (op2&1) {
8143           rt1[i]=(source[i]>>11)&0x1f;
8144         }
8145         rs2[i]=CCREG;
8146         break;
8147       case CJUMP:
8148         rs1[i]=(source[i]>>21)&0x1f;
8149         rs2[i]=(source[i]>>16)&0x1f;
8150         rt1[i]=0;
8151         rt2[i]=0;
8152         if(op&2) { // BGTZ/BLEZ
8153           rs2[i]=0;
8154         }
8155         us1[i]=rs1[i];
8156         us2[i]=rs2[i];
8157         likely[i]=op>>4;
8158         break;
8159       case SJUMP:
8160         rs1[i]=(source[i]>>21)&0x1f;
8161         rs2[i]=CCREG;
8162         rt1[i]=0;
8163         rt2[i]=0;
8164         us1[i]=rs1[i];
8165         if(op2&0x10) { // BxxAL
8166           rt1[i]=31;
8167           // NOTE: If the branch is not taken, r31 is still overwritten
8168         }
8169         likely[i]=(op2&2)>>1;
8170         break;
8171       case FJUMP:
8172         rs1[i]=FSREG;
8173         rs2[i]=CSREG;
8174         rt1[i]=0;
8175         rt2[i]=0;
8176         likely[i]=((source[i])>>17)&1;
8177         break;
8178       case ALU:
8179         rs1[i]=(source[i]>>21)&0x1f; // source
8180         rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8181         rt1[i]=(source[i]>>11)&0x1f; // destination
8182         rt2[i]=0;
8183         if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8184           us1[i]=rs1[i];us2[i]=rs2[i];
8185         }
8186         else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8187           dep1[i]=rs1[i];dep2[i]=rs2[i];
8188         }
8189         else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8190           dep1[i]=rs1[i];dep2[i]=rs2[i];
8191         }
8192         break;
8193       case MULTDIV:
8194         rs1[i]=(source[i]>>21)&0x1f; // source
8195         rs2[i]=(source[i]>>16)&0x1f; // divisor
8196         rt1[i]=HIREG;
8197         rt2[i]=LOREG;
8198         if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8199           us1[i]=rs1[i];us2[i]=rs2[i];
8200         }
8201         break;
8202       case MOV:
8203         rs1[i]=0;
8204         rs2[i]=0;
8205         rt1[i]=0;
8206         rt2[i]=0;
8207         if(op2==0x10) rs1[i]=HIREG; // MFHI
8208         if(op2==0x11) rt1[i]=HIREG; // MTHI
8209         if(op2==0x12) rs1[i]=LOREG; // MFLO
8210         if(op2==0x13) rt1[i]=LOREG; // MTLO
8211         if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8212         if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8213         dep1[i]=rs1[i];
8214         break;
8215       case SHIFT:
8216         rs1[i]=(source[i]>>16)&0x1f; // target of shift
8217         rs2[i]=(source[i]>>21)&0x1f; // shift amount
8218         rt1[i]=(source[i]>>11)&0x1f; // destination
8219         rt2[i]=0;
8220         // DSLLV/DSRLV/DSRAV are 64-bit
8221         if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8222         break;
8223       case SHIFTIMM:
8224         rs1[i]=(source[i]>>16)&0x1f;
8225         rs2[i]=0;
8226         rt1[i]=(source[i]>>11)&0x1f;
8227         rt2[i]=0;
8228         imm[i]=(source[i]>>6)&0x1f;
8229         // DSxx32 instructions
8230         if(op2>=0x3c) imm[i]|=0x20;
8231         // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8232         if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8233         break;
8234       case COP0:
8235         rs1[i]=0;
8236         rs2[i]=0;
8237         rt1[i]=0;
8238         rt2[i]=0;
8239         if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8240         if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8241         if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8242         if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8243         break;
8244       case COP1:
8245       case COP2:
8246         rs1[i]=0;
8247         rs2[i]=0;
8248         rt1[i]=0;
8249         rt2[i]=0;
8250         if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8251         if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8252         if(op2==5) us1[i]=rs1[i]; // DMTC1
8253         rs2[i]=CSREG;
8254         break;
8255       case C1LS:
8256         rs1[i]=(source[i]>>21)&0x1F;
8257         rs2[i]=CSREG;
8258         rt1[i]=0;
8259         rt2[i]=0;
8260         imm[i]=(short)source[i];
8261         break;
8262       case C2LS:
8263         rs1[i]=(source[i]>>21)&0x1F;
8264         rs2[i]=0;
8265         rt1[i]=0;
8266         rt2[i]=0;
8267         imm[i]=(short)source[i];
8268         break;
8269       case FLOAT:
8270       case FCONV:
8271         rs1[i]=0;
8272         rs2[i]=CSREG;
8273         rt1[i]=0;
8274         rt2[i]=0;
8275         break;
8276       case FCOMP:
8277         rs1[i]=FSREG;
8278         rs2[i]=CSREG;
8279         rt1[i]=FSREG;
8280         rt2[i]=0;
8281         break;
8282       case SYSCALL:
8283       case HLECALL:
8284         rs1[i]=CCREG;
8285         rs2[i]=0;
8286         rt1[i]=0;
8287         rt2[i]=0;
8288         break;
8289       default:
8290         rs1[i]=0;
8291         rs2[i]=0;
8292         rt1[i]=0;
8293         rt2[i]=0;
8294     }
8295     /* Calculate branch target addresses */
8296     if(type==UJUMP)
8297       ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8298     else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8299       ba[i]=start+i*4+8; // Ignore never taken branch
8300     else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8301       ba[i]=start+i*4+8; // Ignore never taken branch
8302     else if(type==CJUMP||type==SJUMP||type==FJUMP)
8303       ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8304     else ba[i]=-1;
8305     /* Is this the end of the block? */
8306     if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
8307       if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
8308         done=1;
8309         // Does the block continue due to a branch?
8310         for(j=i-1;j>=0;j--)
8311         {
8312           if(ba[j]==start+i*4+4) done=j=0;
8313           if(ba[j]==start+i*4+8) done=j=0;
8314         }
8315       }
8316       else {
8317         if(stop_after_jal) done=1;
8318         // Stop on BREAK
8319         if((source[i+1]&0xfc00003f)==0x0d) done=1;
8320       }
8321       // Don't recompile stuff that's already compiled
8322       if(check_addr(start+i*4+4)) done=1;
8323       // Don't get too close to the limit
8324       if(i>MAXBLOCK/2) done=1;
8325     }
8326     if(i>0&&itype[i-1]==SYSCALL&&stop_after_jal) done=1;
8327     if(itype[i-1]==HLECALL) done=1;
8328     assert(i<MAXBLOCK-1);
8329     if(start+i*4==pagelimit-4) done=1;
8330     assert(start+i*4<pagelimit);
8331     if (i==MAXBLOCK-1) done=1;
8332     // Stop if we're compiling junk
8333     if(itype[i]==NI&&opcode[i]==0x11) {
8334       done=stop_after_jal=1;
8335       printf("Disabled speculative precompilation\n");
8336     }
8337   }
8338   slen=i;
8339   if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8340     if(start+i*4==pagelimit) {
8341       itype[i-1]=SPAN;
8342     }
8343   }
8344   assert(slen>0);
8345
8346   /* Pass 2 - Register dependencies and branch targets */
8347
8348   unneeded_registers(0,slen-1,0);
8349
8350   /* Pass 3 - Register allocation */
8351
8352   struct regstat current; // Current register allocations/status
8353   current.is32=1;
8354   current.dirty=0;
8355   current.u=unneeded_reg[0];
8356   current.uu=unneeded_reg_upper[0];
8357   clear_all_regs(current.regmap);
8358   alloc_reg(&current,0,CCREG);
8359   dirty_reg(&current,CCREG);
8360   current.isconst=0;
8361   current.wasconst=0;
8362   int ds=0;
8363   int cc=0;
8364   int hr;
8365
8366   provisional_32bit();
8367
8368   if((u_int)addr&1) {
8369     // First instruction is delay slot
8370     cc=-1;
8371     bt[1]=1;
8372     ds=1;
8373     unneeded_reg[0]=1;
8374     unneeded_reg_upper[0]=1;
8375     current.regmap[HOST_BTREG]=BTREG;
8376   }
8377
8378   for(i=0;i<slen;i++)
8379   {
8380     if(bt[i])
8381     {
8382       int hr;
8383       for(hr=0;hr<HOST_REGS;hr++)
8384       {
8385         // Is this really necessary?
8386         if(current.regmap[hr]==0) current.regmap[hr]=-1;
8387       }
8388       current.isconst=0;
8389     }
8390     if(i>1)
8391     {
8392       if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8393       {
8394         if(rs1[i-2]==0||rs2[i-2]==0)
8395         {
8396           if(rs1[i-2]) {
8397             current.is32|=1LL<<rs1[i-2];
8398             int hr=get_reg(current.regmap,rs1[i-2]|64);
8399             if(hr>=0) current.regmap[hr]=-1;
8400           }
8401           if(rs2[i-2]) {
8402             current.is32|=1LL<<rs2[i-2];
8403             int hr=get_reg(current.regmap,rs2[i-2]|64);
8404             if(hr>=0) current.regmap[hr]=-1;
8405           }
8406         }
8407       }
8408     }
8409     // If something jumps here with 64-bit values
8410     // then promote those registers to 64 bits
8411     if(bt[i])
8412     {
8413       uint64_t temp_is32=current.is32;
8414       for(j=i-1;j>=0;j--)
8415       {
8416         if(ba[j]==start+i*4)
8417           temp_is32&=branch_regs[j].is32;
8418       }
8419       for(j=i;j<slen;j++)
8420       {
8421         if(ba[j]==start+i*4)
8422           //temp_is32=1;
8423           temp_is32&=p32[j];
8424       }
8425       if(temp_is32!=current.is32) {
8426         //printf("dumping 32-bit regs (%x)\n",start+i*4);
8427         #ifdef DESTRUCTIVE_WRITEBACK
8428         for(hr=0;hr<HOST_REGS;hr++)
8429         {
8430           int r=current.regmap[hr];
8431           if(r>0&&r<64)
8432           {
8433             if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8434               temp_is32|=1LL<<r;
8435               //printf("restore %d\n",r);
8436             }
8437           }
8438         }
8439         #endif
8440         current.is32=temp_is32;
8441       }
8442     }
8443 #ifdef FORCE32
8444     memset(p32, 0xff, sizeof(p32));
8445     current.is32=-1LL;
8446 #endif
8447
8448     memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8449     regs[i].wasconst=current.isconst;
8450     regs[i].was32=current.is32;
8451     regs[i].wasdirty=current.dirty;
8452     #ifdef DESTRUCTIVE_WRITEBACK
8453     // To change a dirty register from 32 to 64 bits, we must write
8454     // it out during the previous cycle (for branches, 2 cycles)
8455     if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8456     {
8457       uint64_t temp_is32=current.is32;
8458       for(j=i-1;j>=0;j--)
8459       {
8460         if(ba[j]==start+i*4+4)
8461           temp_is32&=branch_regs[j].is32;
8462       }
8463       for(j=i;j<slen;j++)
8464       {
8465         if(ba[j]==start+i*4+4)
8466           //temp_is32=1;
8467           temp_is32&=p32[j];
8468       }
8469       if(temp_is32!=current.is32) {
8470         //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8471         for(hr=0;hr<HOST_REGS;hr++)
8472         {
8473           int r=current.regmap[hr];
8474           if(r>0)
8475           {
8476             if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8477               if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
8478               {
8479                 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
8480                 {
8481                   //printf("dump %d/r%d\n",hr,r);
8482                   current.regmap[hr]=-1;
8483                   if(get_reg(current.regmap,r|64)>=0)
8484                     current.regmap[get_reg(current.regmap,r|64)]=-1;
8485                 }
8486               }
8487             }
8488           }
8489         }
8490       }
8491     }
8492     else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
8493     {
8494       uint64_t temp_is32=current.is32;
8495       for(j=i-1;j>=0;j--)
8496       {
8497         if(ba[j]==start+i*4+8)
8498           temp_is32&=branch_regs[j].is32;
8499       }
8500       for(j=i;j<slen;j++)
8501       {
8502         if(ba[j]==start+i*4+8)
8503           //temp_is32=1;
8504           temp_is32&=p32[j];
8505       }
8506       if(temp_is32!=current.is32) {
8507         //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8508         for(hr=0;hr<HOST_REGS;hr++)
8509         {
8510           int r=current.regmap[hr];
8511           if(r>0)
8512           {
8513             if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8514               if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
8515               {
8516                 //printf("dump %d/r%d\n",hr,r);
8517                 current.regmap[hr]=-1;
8518                 if(get_reg(current.regmap,r|64)>=0)
8519                   current.regmap[get_reg(current.regmap,r|64)]=-1;
8520               }
8521             }
8522           }
8523         }
8524       }
8525     }
8526     #endif
8527     if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8528       if(i+1<slen) {
8529         current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8530         current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8531         if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8532         current.u|=1;
8533         current.uu|=1;
8534       } else {
8535         current.u=1;
8536         current.uu=1;
8537       }
8538     } else {
8539       if(i+1<slen) {
8540         current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
8541         current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8542         if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8543         current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8544         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8545         current.u|=1;
8546         current.uu|=1;
8547       } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
8548     }
8549     is_ds[i]=ds;
8550     if(ds) {
8551       ds=0; // Skip delay slot, already allocated as part of branch
8552       // ...but we need to alloc it in case something jumps here
8553       if(i+1<slen) {
8554         current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
8555         current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
8556       }else{
8557         current.u=branch_unneeded_reg[i-1];
8558         current.uu=branch_unneeded_reg_upper[i-1];
8559       }
8560       current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8561       current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8562       if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8563       current.u|=1;
8564       current.uu|=1;
8565       struct regstat temp;
8566       memcpy(&temp,&current,sizeof(current));
8567       temp.wasdirty=temp.dirty;
8568       temp.was32=temp.is32;
8569       // TODO: Take into account unconditional branches, as below
8570       delayslot_alloc(&temp,i);
8571       memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
8572       regs[i].wasdirty=temp.wasdirty;
8573       regs[i].was32=temp.was32;
8574       regs[i].dirty=temp.dirty;
8575       regs[i].is32=temp.is32;
8576       regs[i].isconst=0;
8577       regs[i].wasconst=0;
8578       current.isconst=0;
8579       // Create entry (branch target) regmap
8580       for(hr=0;hr<HOST_REGS;hr++)
8581       {
8582         int r=temp.regmap[hr];
8583         if(r>=0) {
8584           if(r!=regmap_pre[i][hr]) {
8585             regs[i].regmap_entry[hr]=-1;
8586           }
8587           else
8588           {
8589             if(r<64){
8590               if((current.u>>r)&1) {
8591                 regs[i].regmap_entry[hr]=-1;
8592                 regs[i].regmap[hr]=-1;
8593                 //Don't clear regs in the delay slot as the branch might need them
8594                 //current.regmap[hr]=-1;
8595               }else
8596                 regs[i].regmap_entry[hr]=r;
8597             }
8598             else {
8599               if((current.uu>>(r&63))&1) {
8600                 regs[i].regmap_entry[hr]=-1;
8601                 regs[i].regmap[hr]=-1;
8602                 //Don't clear regs in the delay slot as the branch might need them
8603                 //current.regmap[hr]=-1;
8604               }else
8605                 regs[i].regmap_entry[hr]=r;
8606             }
8607           }
8608         } else {
8609           // First instruction expects CCREG to be allocated
8610           if(i==0&&hr==HOST_CCREG)
8611             regs[i].regmap_entry[hr]=CCREG;
8612           else
8613             regs[i].regmap_entry[hr]=-1;
8614         }
8615       }
8616     }
8617     else { // Not delay slot
8618       switch(itype[i]) {
8619         case UJUMP:
8620           //current.isconst=0; // DEBUG
8621           //current.wasconst=0; // DEBUG
8622           //regs[i].wasconst=0; // DEBUG
8623           clear_const(&current,rt1[i]);
8624           alloc_cc(&current,i);
8625           dirty_reg(&current,CCREG);
8626           if (rt1[i]==31) {
8627             alloc_reg(&current,i,31);
8628             dirty_reg(&current,31);
8629             assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8630             #ifdef REG_PREFETCH
8631             alloc_reg(&current,i,PTEMP);
8632             #endif
8633             //current.is32|=1LL<<rt1[i];
8634           }
8635           delayslot_alloc(&current,i+1);
8636           //current.isconst=0; // DEBUG
8637           ds=1;
8638           //printf("i=%d, isconst=%x\n",i,current.isconst);
8639           break;
8640         case RJUMP:
8641           //current.isconst=0;
8642           //current.wasconst=0;
8643           //regs[i].wasconst=0;
8644           clear_const(&current,rs1[i]);
8645           clear_const(&current,rt1[i]);
8646           alloc_cc(&current,i);
8647           dirty_reg(&current,CCREG);
8648           if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
8649             alloc_reg(&current,i,rs1[i]);
8650             if (rt1[i]!=0) {
8651               alloc_reg(&current,i,rt1[i]);
8652               dirty_reg(&current,rt1[i]);
8653               assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8654               #ifdef REG_PREFETCH
8655               alloc_reg(&current,i,PTEMP);
8656               #endif
8657             }
8658             #ifdef USE_MINI_HT
8659             if(rs1[i]==31) { // JALR
8660               alloc_reg(&current,i,RHASH);
8661               #ifndef HOST_IMM_ADDR32
8662               alloc_reg(&current,i,RHTBL);
8663               #endif
8664             }
8665             #endif
8666             delayslot_alloc(&current,i+1);
8667           } else {
8668             // The delay slot overwrites our source register,
8669             // allocate a temporary register to hold the old value.
8670             current.isconst=0;
8671             current.wasconst=0;
8672             regs[i].wasconst=0;
8673             delayslot_alloc(&current,i+1);
8674             current.isconst=0;
8675             alloc_reg(&current,i,RTEMP);
8676           }
8677           //current.isconst=0; // DEBUG
8678           ds=1;
8679           break;
8680         case CJUMP:
8681           //current.isconst=0;
8682           //current.wasconst=0;
8683           //regs[i].wasconst=0;
8684           clear_const(&current,rs1[i]);
8685           clear_const(&current,rs2[i]);
8686           if((opcode[i]&0x3E)==4) // BEQ/BNE
8687           {
8688             alloc_cc(&current,i);
8689             dirty_reg(&current,CCREG);
8690             if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8691             if(rs2[i]) alloc_reg(&current,i,rs2[i]);
8692             if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8693             {
8694               if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8695               if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
8696             }
8697             if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
8698                (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
8699               // The delay slot overwrites one of our conditions.
8700               // Allocate the branch condition registers instead.
8701               // Note that such a sequence of instructions could
8702               // be considered a bug since the branch can not be
8703               // re-executed if an exception occurs.
8704               current.isconst=0;
8705               current.wasconst=0;
8706               regs[i].wasconst=0;
8707               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8708               if(rs2[i]) alloc_reg(&current,i,rs2[i]);
8709               if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8710               {
8711                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8712                 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
8713               }
8714             }
8715             else delayslot_alloc(&current,i+1);
8716           }
8717           else
8718           if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
8719           {
8720             alloc_cc(&current,i);
8721             dirty_reg(&current,CCREG);
8722             alloc_reg(&current,i,rs1[i]);
8723             if(!(current.is32>>rs1[i]&1))
8724             {
8725               alloc_reg64(&current,i,rs1[i]);
8726             }
8727             if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
8728               // The delay slot overwrites one of our conditions.
8729               // Allocate the branch condition registers instead.
8730               // Note that such a sequence of instructions could
8731               // be considered a bug since the branch can not be
8732               // re-executed if an exception occurs.
8733               current.isconst=0;
8734               current.wasconst=0;
8735               regs[i].wasconst=0;
8736               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8737               if(!((current.is32>>rs1[i])&1))
8738               {
8739                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8740               }
8741             }
8742             else delayslot_alloc(&current,i+1);
8743           }
8744           else
8745           // Don't alloc the delay slot yet because we might not execute it
8746           if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
8747           {
8748             current.isconst=0;
8749             current.wasconst=0;
8750             regs[i].wasconst=0;
8751             alloc_cc(&current,i);
8752             dirty_reg(&current,CCREG);
8753             alloc_reg(&current,i,rs1[i]);
8754             alloc_reg(&current,i,rs2[i]);
8755             if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8756             {
8757               alloc_reg64(&current,i,rs1[i]);
8758               alloc_reg64(&current,i,rs2[i]);
8759             }
8760           }
8761           else
8762           if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
8763           {
8764             current.isconst=0;
8765             current.wasconst=0;
8766             regs[i].wasconst=0;
8767             alloc_cc(&current,i);
8768             dirty_reg(&current,CCREG);
8769             alloc_reg(&current,i,rs1[i]);
8770             if(!(current.is32>>rs1[i]&1))
8771             {
8772               alloc_reg64(&current,i,rs1[i]);
8773             }
8774           }
8775           ds=1;
8776           //current.isconst=0;
8777           break;
8778         case SJUMP:
8779           //current.isconst=0;
8780           //current.wasconst=0;
8781           //regs[i].wasconst=0;
8782           clear_const(&current,rs1[i]);
8783           clear_const(&current,rt1[i]);
8784           //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
8785           if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
8786           {
8787             alloc_cc(&current,i);
8788             dirty_reg(&current,CCREG);
8789             alloc_reg(&current,i,rs1[i]);
8790             if(!(current.is32>>rs1[i]&1))
8791             {
8792               alloc_reg64(&current,i,rs1[i]);
8793             }
8794             if (rt1[i]==31) { // BLTZAL/BGEZAL
8795               alloc_reg(&current,i,31);
8796               dirty_reg(&current,31);
8797               assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8798               //#ifdef REG_PREFETCH
8799               //alloc_reg(&current,i,PTEMP);
8800               //#endif
8801               //current.is32|=1LL<<rt1[i];
8802             }
8803             if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
8804               // The delay slot overwrites the branch condition.
8805               // Allocate the branch condition registers instead.
8806               // Note that such a sequence of instructions could
8807               // be considered a bug since the branch can not be
8808               // re-executed if an exception occurs.
8809               current.isconst=0;
8810               current.wasconst=0;
8811               regs[i].wasconst=0;
8812               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8813               if(!((current.is32>>rs1[i])&1))
8814               {
8815                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8816               }
8817             }
8818             else delayslot_alloc(&current,i+1);
8819           }
8820           else
8821           // Don't alloc the delay slot yet because we might not execute it
8822           if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
8823           {
8824             current.isconst=0;
8825             current.wasconst=0;
8826             regs[i].wasconst=0;
8827             alloc_cc(&current,i);
8828             dirty_reg(&current,CCREG);
8829             alloc_reg(&current,i,rs1[i]);
8830             if(!(current.is32>>rs1[i]&1))
8831             {
8832               alloc_reg64(&current,i,rs1[i]);
8833             }
8834           }
8835           ds=1;
8836           //current.isconst=0;
8837           break;
8838         case FJUMP:
8839           current.isconst=0;
8840           current.wasconst=0;
8841           regs[i].wasconst=0;
8842           if(likely[i]==0) // BC1F/BC1T
8843           {
8844             // TODO: Theoretically we can run out of registers here on x86.
8845             // The delay slot can allocate up to six, and we need to check
8846             // CSREG before executing the delay slot.  Possibly we can drop
8847             // the cycle count and then reload it after checking that the
8848             // FPU is in a usable state, or don't do out-of-order execution.
8849             alloc_cc(&current,i);
8850             dirty_reg(&current,CCREG);
8851             alloc_reg(&current,i,FSREG);
8852             alloc_reg(&current,i,CSREG);
8853             if(itype[i+1]==FCOMP) {
8854               // The delay slot overwrites the branch condition.
8855               // Allocate the branch condition registers instead.
8856               // Note that such a sequence of instructions could
8857               // be considered a bug since the branch can not be
8858               // re-executed if an exception occurs.
8859               alloc_cc(&current,i);
8860               dirty_reg(&current,CCREG);
8861               alloc_reg(&current,i,CSREG);
8862               alloc_reg(&current,i,FSREG);
8863             }
8864             else {
8865               delayslot_alloc(&current,i+1);
8866               alloc_reg(&current,i+1,CSREG);
8867             }
8868           }
8869           else
8870           // Don't alloc the delay slot yet because we might not execute it
8871           if(likely[i]) // BC1FL/BC1TL
8872           {
8873             alloc_cc(&current,i);
8874             dirty_reg(&current,CCREG);
8875             alloc_reg(&current,i,CSREG);
8876             alloc_reg(&current,i,FSREG);
8877           }
8878           ds=1;
8879           current.isconst=0;
8880           break;
8881         case IMM16:
8882           imm16_alloc(&current,i);
8883           break;
8884         case LOAD:
8885         case LOADLR:
8886           load_alloc(&current,i);
8887           break;
8888         case STORE:
8889         case STORELR:
8890           store_alloc(&current,i);
8891           break;
8892         case ALU:
8893           alu_alloc(&current,i);
8894           break;
8895         case SHIFT:
8896           shift_alloc(&current,i);
8897           break;
8898         case MULTDIV:
8899           multdiv_alloc(&current,i);
8900           break;
8901         case SHIFTIMM:
8902           shiftimm_alloc(&current,i);
8903           break;
8904         case MOV:
8905           mov_alloc(&current,i);
8906           break;
8907         case COP0:
8908           cop0_alloc(&current,i);
8909           break;
8910         case COP1:
8911         case COP2:
8912           cop1_alloc(&current,i);
8913           break;
8914         case C1LS:
8915           c1ls_alloc(&current,i);
8916           break;
8917         case C2LS:
8918           c2ls_alloc(&current,i);
8919           break;
8920         case C2OP:
8921           c2op_alloc(&current,i);
8922           break;
8923         case FCONV:
8924           fconv_alloc(&current,i);
8925           break;
8926         case FLOAT:
8927           float_alloc(&current,i);
8928           break;
8929         case FCOMP:
8930           fcomp_alloc(&current,i);
8931           break;
8932         case SYSCALL:
8933         case HLECALL:
8934           syscall_alloc(&current,i);
8935           break;
8936         case SPAN:
8937           pagespan_alloc(&current,i);
8938           break;
8939       }
8940
8941       // Drop the upper half of registers that have become 32-bit
8942       current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
8943       if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8944         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8945         if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8946         current.uu|=1;
8947       } else {
8948         current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
8949         current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8950         if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8951         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8952         current.uu|=1;
8953       }
8954
8955       // Create entry (branch target) regmap
8956       for(hr=0;hr<HOST_REGS;hr++)
8957       {
8958         int r,or,er;
8959         r=current.regmap[hr];
8960         if(r>=0) {
8961           if(r!=regmap_pre[i][hr]) {
8962             // TODO: delay slot (?)
8963             or=get_reg(regmap_pre[i],r); // Get old mapping for this register
8964             if(or<0||(r&63)>=TEMPREG){
8965               regs[i].regmap_entry[hr]=-1;
8966             }
8967             else
8968             {
8969               // Just move it to a different register
8970               regs[i].regmap_entry[hr]=r;
8971               // If it was dirty before, it's still dirty
8972               if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r&63);
8973             }
8974           }
8975           else
8976           {
8977             // Unneeded
8978             if(r==0){
8979               regs[i].regmap_entry[hr]=0;
8980             }
8981             else
8982             if(r<64){
8983               if((current.u>>r)&1) {
8984                 regs[i].regmap_entry[hr]=-1;
8985                 //regs[i].regmap[hr]=-1;
8986                 current.regmap[hr]=-1;
8987               }else
8988                 regs[i].regmap_entry[hr]=r;
8989             }
8990             else {
8991               if((current.uu>>(r&63))&1) {
8992                 regs[i].regmap_entry[hr]=-1;
8993                 //regs[i].regmap[hr]=-1;
8994                 current.regmap[hr]=-1;
8995               }else
8996                 regs[i].regmap_entry[hr]=r;
8997             }
8998           }
8999         } else {
9000           // Branches expect CCREG to be allocated at the target
9001           if(regmap_pre[i][hr]==CCREG)
9002             regs[i].regmap_entry[hr]=CCREG;
9003           else
9004             regs[i].regmap_entry[hr]=-1;
9005         }
9006       }
9007       memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9008     }
9009     /* Branch post-alloc */
9010     if(i>0)
9011     {
9012       current.was32=current.is32;
9013       current.wasdirty=current.dirty;
9014       switch(itype[i-1]) {
9015         case UJUMP:
9016           memcpy(&branch_regs[i-1],&current,sizeof(current));
9017           branch_regs[i-1].isconst=0;
9018           branch_regs[i-1].wasconst=0;
9019           branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9020           branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9021           alloc_cc(&branch_regs[i-1],i-1);
9022           dirty_reg(&branch_regs[i-1],CCREG);
9023           if(rt1[i-1]==31) { // JAL
9024             alloc_reg(&branch_regs[i-1],i-1,31);
9025             dirty_reg(&branch_regs[i-1],31);
9026             branch_regs[i-1].is32|=1LL<<31;
9027           }
9028           memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9029           memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9030           break;
9031         case RJUMP:
9032           memcpy(&branch_regs[i-1],&current,sizeof(current));
9033           branch_regs[i-1].isconst=0;
9034           branch_regs[i-1].wasconst=0;
9035           branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9036           branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9037           alloc_cc(&branch_regs[i-1],i-1);
9038           dirty_reg(&branch_regs[i-1],CCREG);
9039           alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
9040           if(rt1[i-1]!=0) { // JALR
9041             alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9042             dirty_reg(&branch_regs[i-1],rt1[i-1]);
9043             branch_regs[i-1].is32|=1LL<<rt1[i-1];
9044           }
9045           #ifdef USE_MINI_HT
9046           if(rs1[i-1]==31) { // JALR
9047             alloc_reg(&branch_regs[i-1],i-1,RHASH);
9048             #ifndef HOST_IMM_ADDR32
9049             alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9050             #endif
9051           }
9052           #endif
9053           memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9054           memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9055           break;
9056         case CJUMP:
9057           if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9058           {
9059             alloc_cc(&current,i-1);
9060             dirty_reg(&current,CCREG);
9061             if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9062                (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9063               // The delay slot overwrote one of our conditions
9064               // Delay slot goes after the test (in order)
9065               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9066               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9067               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9068               current.u|=1;
9069               current.uu|=1;
9070               delayslot_alloc(&current,i);
9071               current.isconst=0;
9072             }
9073             else
9074             {
9075               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9076               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9077               // Alloc the branch condition registers
9078               if(rs1[i-1]) alloc_reg(&current,i-1,rs1[i-1]);
9079               if(rs2[i-1]) alloc_reg(&current,i-1,rs2[i-1]);
9080               if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9081               {
9082                 if(rs1[i-1]) alloc_reg64(&current,i-1,rs1[i-1]);
9083                 if(rs2[i-1]) alloc_reg64(&current,i-1,rs2[i-1]);
9084               }
9085             }
9086             memcpy(&branch_regs[i-1],&current,sizeof(current));
9087             branch_regs[i-1].isconst=0;
9088             branch_regs[i-1].wasconst=0;
9089             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9090             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9091           }
9092           else
9093           if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9094           {
9095             alloc_cc(&current,i-1);
9096             dirty_reg(&current,CCREG);
9097             if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9098               // The delay slot overwrote the branch condition
9099               // Delay slot goes after the test (in order)
9100               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9101               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9102               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9103               current.u|=1;
9104               current.uu|=1;
9105               delayslot_alloc(&current,i);
9106               current.isconst=0;
9107             }
9108             else
9109             {
9110               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9111               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9112               // Alloc the branch condition register
9113               alloc_reg(&current,i-1,rs1[i-1]);
9114               if(!(current.is32>>rs1[i-1]&1))
9115               {
9116                 alloc_reg64(&current,i-1,rs1[i-1]);
9117               }
9118             }
9119             memcpy(&branch_regs[i-1],&current,sizeof(current));
9120             branch_regs[i-1].isconst=0;
9121             branch_regs[i-1].wasconst=0;
9122             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9123             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9124           }
9125           else
9126           // Alloc the delay slot in case the branch is taken
9127           if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9128           {
9129             memcpy(&branch_regs[i-1],&current,sizeof(current));
9130             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9131             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9132             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9133             alloc_cc(&branch_regs[i-1],i);
9134             dirty_reg(&branch_regs[i-1],CCREG);
9135             delayslot_alloc(&branch_regs[i-1],i);
9136             branch_regs[i-1].isconst=0;
9137             alloc_reg(&current,i,CCREG); // Not taken path
9138             dirty_reg(&current,CCREG);
9139             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9140           }
9141           else
9142           if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9143           {
9144             memcpy(&branch_regs[i-1],&current,sizeof(current));
9145             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9146             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9147             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9148             alloc_cc(&branch_regs[i-1],i);
9149             dirty_reg(&branch_regs[i-1],CCREG);
9150             delayslot_alloc(&branch_regs[i-1],i);
9151             branch_regs[i-1].isconst=0;
9152             alloc_reg(&current,i,CCREG); // Not taken path
9153             dirty_reg(&current,CCREG);
9154             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9155           }
9156           break;
9157         case SJUMP:
9158           //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9159           if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9160           {
9161             alloc_cc(&current,i-1);
9162             dirty_reg(&current,CCREG);
9163             if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9164               // The delay slot overwrote the branch condition
9165               // Delay slot goes after the test (in order)
9166               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9167               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9168               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9169               current.u|=1;
9170               current.uu|=1;
9171               delayslot_alloc(&current,i);
9172               current.isconst=0;
9173             }
9174             else
9175             {
9176               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9177               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9178               // Alloc the branch condition register
9179               alloc_reg(&current,i-1,rs1[i-1]);
9180               if(!(current.is32>>rs1[i-1]&1))
9181               {
9182                 alloc_reg64(&current,i-1,rs1[i-1]);
9183               }
9184             }
9185             memcpy(&branch_regs[i-1],&current,sizeof(current));
9186             branch_regs[i-1].isconst=0;
9187             branch_regs[i-1].wasconst=0;
9188             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9189             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9190           }
9191           else
9192           // Alloc the delay slot in case the branch is taken
9193           if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9194           {
9195             memcpy(&branch_regs[i-1],&current,sizeof(current));
9196             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9197             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9198             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9199             alloc_cc(&branch_regs[i-1],i);
9200             dirty_reg(&branch_regs[i-1],CCREG);
9201             delayslot_alloc(&branch_regs[i-1],i);
9202             branch_regs[i-1].isconst=0;
9203             alloc_reg(&current,i,CCREG); // Not taken path
9204             dirty_reg(&current,CCREG);
9205             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9206           }
9207           // FIXME: BLTZAL/BGEZAL
9208           if(opcode2[i-1]&0x10) { // BxxZAL
9209             alloc_reg(&branch_regs[i-1],i-1,31);
9210             dirty_reg(&branch_regs[i-1],31);
9211             branch_regs[i-1].is32|=1LL<<31;
9212           }
9213           break;
9214         case FJUMP:
9215           if(likely[i-1]==0) // BC1F/BC1T
9216           {
9217             alloc_cc(&current,i-1);
9218             dirty_reg(&current,CCREG);
9219             if(itype[i]==FCOMP) {
9220               // The delay slot overwrote the branch condition
9221               // Delay slot goes after the test (in order)
9222               delayslot_alloc(&current,i);
9223               current.isconst=0;
9224             }
9225             else
9226             {
9227               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9228               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9229               // Alloc the branch condition register
9230               alloc_reg(&current,i-1,FSREG);
9231             }
9232             memcpy(&branch_regs[i-1],&current,sizeof(current));
9233             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9234           }
9235           else // BC1FL/BC1TL
9236           {
9237             // Alloc the delay slot in case the branch is taken
9238             memcpy(&branch_regs[i-1],&current,sizeof(current));
9239             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9240             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9241             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9242             alloc_cc(&branch_regs[i-1],i);
9243             dirty_reg(&branch_regs[i-1],CCREG);
9244             delayslot_alloc(&branch_regs[i-1],i);
9245             branch_regs[i-1].isconst=0;
9246             alloc_reg(&current,i,CCREG); // Not taken path
9247             dirty_reg(&current,CCREG);
9248             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9249           }
9250           break;
9251       }
9252
9253       if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9254       {
9255         if(rt1[i-1]==31) // JAL/JALR
9256         {
9257           // Subroutine call will return here, don't alloc any registers
9258           current.is32=1;
9259           current.dirty=0;
9260           clear_all_regs(current.regmap);
9261           alloc_reg(&current,i,CCREG);
9262           dirty_reg(&current,CCREG);
9263         }
9264         else if(i+1<slen)
9265         {
9266           // Internal branch will jump here, match registers to caller
9267           current.is32=0x3FFFFFFFFLL;
9268           current.dirty=0;
9269           clear_all_regs(current.regmap);
9270           alloc_reg(&current,i,CCREG);
9271           dirty_reg(&current,CCREG);
9272           for(j=i-1;j>=0;j--)
9273           {
9274             if(ba[j]==start+i*4+4) {
9275               memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9276               current.is32=branch_regs[j].is32;
9277               current.dirty=branch_regs[j].dirty;
9278               break;
9279             }
9280           }
9281           while(j>=0) {
9282             if(ba[j]==start+i*4+4) {
9283               for(hr=0;hr<HOST_REGS;hr++) {
9284                 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9285                   current.regmap[hr]=-1;
9286                 }
9287                 current.is32&=branch_regs[j].is32;
9288                 current.dirty&=branch_regs[j].dirty;
9289               }
9290             }
9291             j--;
9292           }
9293         }
9294       }
9295     }
9296
9297     // Count cycles in between branches
9298     ccadj[i]=cc;
9299     if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
9300     {
9301       cc=0;
9302     }
9303     else
9304     {
9305       cc++;
9306     }
9307
9308     flush_dirty_uppers(&current);
9309     if(!is_ds[i]) {
9310       regs[i].is32=current.is32;
9311       regs[i].dirty=current.dirty;
9312       regs[i].isconst=current.isconst;
9313       memcpy(constmap[i],current.constmap,sizeof(current.constmap));
9314     }
9315     for(hr=0;hr<HOST_REGS;hr++) {
9316       if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
9317         if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9318           regs[i].wasconst&=~(1<<hr);
9319         }
9320       }
9321     }
9322     if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9323   }
9324
9325   /* Pass 4 - Cull unused host registers */
9326
9327   uint64_t nr=0;
9328
9329   for (i=slen-1;i>=0;i--)
9330   {
9331     int hr;
9332     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9333     {
9334       if(ba[i]<start || ba[i]>=(start+slen*4))
9335       {
9336         // Branch out of this block, don't need anything
9337         nr=0;
9338       }
9339       else
9340       {
9341         // Internal branch
9342         // Need whatever matches the target
9343         nr=0;
9344         int t=(ba[i]-start)>>2;
9345         for(hr=0;hr<HOST_REGS;hr++)
9346         {
9347           if(regs[i].regmap_entry[hr]>=0) {
9348             if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9349           }
9350         }
9351       }
9352       // Conditional branch may need registers for following instructions
9353       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9354       {
9355         if(i<slen-2) {
9356           nr|=needed_reg[i+2];
9357           for(hr=0;hr<HOST_REGS;hr++)
9358           {
9359             if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9360             //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9361           }
9362         }
9363       }
9364       // Don't need stuff which is overwritten
9365       if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9366       if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9367       // Merge in delay slot
9368       for(hr=0;hr<HOST_REGS;hr++)
9369       {
9370         if(!likely[i]) {
9371           // These are overwritten unless the branch is "likely"
9372           // and the delay slot is nullified if not taken
9373           if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9374           if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9375         }
9376         if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9377         if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9378         if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9379         if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9380         if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9381         if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9382         if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9383         if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9384         if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9385           if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9386           if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9387         }
9388         if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9389           if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9390           if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9391         }
9392         if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
9393           if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9394           if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9395         }
9396       }
9397     }
9398     else if(itype[i]==SYSCALL||itype[i]==HLECALL)
9399     {
9400       // SYSCALL instruction (software interrupt)
9401       nr=0;
9402     }
9403     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9404     {
9405       // ERET instruction (return from interrupt)
9406       nr=0;
9407     }
9408     else // Non-branch
9409     {
9410       if(i<slen-1) {
9411         for(hr=0;hr<HOST_REGS;hr++) {
9412           if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9413           if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9414           if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9415           if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9416         }
9417       }
9418     }
9419     for(hr=0;hr<HOST_REGS;hr++)
9420     {
9421       // Overwritten registers are not needed
9422       if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9423       if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9424       if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9425       // Source registers are needed
9426       if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9427       if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9428       if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9429       if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9430       if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9431       if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9432       if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9433       if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9434       if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9435         if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9436         if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9437       }
9438       if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
9439         if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9440         if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9441       }
9442       if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
9443         if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9444         if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9445       }
9446       // Don't store a register immediately after writing it,
9447       // may prevent dual-issue.
9448       // But do so if this is a branch target, otherwise we
9449       // might have to load the register before the branch.
9450       if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
9451         if((regmap_pre[i][hr]>0&&regmap_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
9452            (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
9453           if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9454           if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9455         }
9456         if((regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
9457            (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
9458           if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9459           if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9460         }
9461       }
9462     }
9463     // Cycle count is needed at branches.  Assume it is needed at the target too.
9464     if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
9465       if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9466       if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9467     }
9468     // Save it
9469     needed_reg[i]=nr;
9470
9471     // Deallocate unneeded registers
9472     for(hr=0;hr<HOST_REGS;hr++)
9473     {
9474       if(!((nr>>hr)&1)) {
9475         if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
9476         if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9477            (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9478            (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
9479         {
9480           if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9481           {
9482             if(likely[i]) {
9483               regs[i].regmap[hr]=-1;
9484               regs[i].isconst&=~(1<<hr);
9485               if(i<slen-2) regmap_pre[i+2][hr]=-1;
9486             }
9487           }
9488         }
9489         if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9490         {
9491           int d1=0,d2=0,map=0,temp=0;
9492           if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
9493           {
9494             d1=dep1[i+1];
9495             d2=dep2[i+1];
9496           }
9497           if(using_tlb) {
9498             if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
9499                itype[i+1]==STORE || itype[i+1]==STORELR ||
9500                itype[i+1]==C1LS || itype[i+1]==C2LS)
9501             map=TLREG;
9502           } else
9503           if(itype[i+1]==STORE || itype[i+1]==STORELR ||
9504              (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
9505             map=INVCP;
9506           }
9507           if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
9508              itype[i+1]==C1LS || itype[i+1]==C2LS)
9509             temp=FTEMP;
9510           if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9511              (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9512              (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
9513              (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
9514              (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9515              regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
9516              (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
9517              regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
9518              regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
9519              regs[i].regmap[hr]!=map )
9520           {
9521             regs[i].regmap[hr]=-1;
9522             regs[i].isconst&=~(1<<hr);
9523             if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
9524                (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
9525                (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
9526                (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
9527                (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
9528                branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
9529                (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
9530                branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
9531                branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
9532                branch_regs[i].regmap[hr]!=map)
9533             {
9534               branch_regs[i].regmap[hr]=-1;
9535               branch_regs[i].regmap_entry[hr]=-1;
9536               if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9537               {
9538                 if(!likely[i]&&i<slen-2) {
9539                   regmap_pre[i+2][hr]=-1;
9540                 }
9541               }
9542             }
9543           }
9544         }
9545         else
9546         {
9547           // Non-branch
9548           if(i>0)
9549           {
9550             int d1=0,d2=0,map=-1,temp=-1;
9551             if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
9552             {
9553               d1=dep1[i];
9554               d2=dep2[i];
9555             }
9556             if(using_tlb) {
9557               if(itype[i]==LOAD || itype[i]==LOADLR ||
9558                  itype[i]==STORE || itype[i]==STORELR ||
9559                  itype[i]==C1LS || itype[i]==C2LS)
9560               map=TLREG;
9561             } else if(itype[i]==STORE || itype[i]==STORELR ||
9562                       (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
9563               map=INVCP;
9564             }
9565             if(itype[i]==LOADLR || itype[i]==STORELR ||
9566                itype[i]==C1LS || itype[i]==C2LS)
9567               temp=FTEMP;
9568             if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9569                (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
9570                (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9571                regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
9572                (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
9573                (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
9574             {
9575               if(i<slen-1&&!is_ds[i]) {
9576                 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
9577                 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
9578                 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
9579                 {
9580                   printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
9581                   assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
9582                 }
9583                 regmap_pre[i+1][hr]=-1;
9584                 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
9585               }
9586               regs[i].regmap[hr]=-1;
9587               regs[i].isconst&=~(1<<hr);
9588             }
9589           }
9590         }
9591       }
9592     }
9593   }
9594
9595   /* Pass 5 - Pre-allocate registers */
9596
9597   // If a register is allocated during a loop, try to allocate it for the
9598   // entire loop, if possible.  This avoids loading/storing registers
9599   // inside of the loop.
9600
9601   signed char f_regmap[HOST_REGS];
9602   clear_all_regs(f_regmap);
9603   for(i=0;i<slen-1;i++)
9604   {
9605     if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9606     {
9607       if(ba[i]>=start && ba[i]<(start+i*4))
9608       if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
9609       ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
9610       ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
9611       ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
9612       ||itype[i+1]==FCOMP||itype[i+1]==FCONV
9613       ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
9614       {
9615         int t=(ba[i]-start)>>2;
9616         if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
9617         if(t<2||(itype[t-2]!=UJUMP)) // call/ret assumes no registers allocated
9618         for(hr=0;hr<HOST_REGS;hr++)
9619         {
9620           if(regs[i].regmap[hr]>64) {
9621             if(!((regs[i].dirty>>hr)&1))
9622               f_regmap[hr]=regs[i].regmap[hr];
9623             else f_regmap[hr]=-1;
9624           }
9625           else if(regs[i].regmap[hr]>=0) f_regmap[hr]=regs[i].regmap[hr];
9626           if(branch_regs[i].regmap[hr]>64) {
9627             if(!((branch_regs[i].dirty>>hr)&1))
9628               f_regmap[hr]=branch_regs[i].regmap[hr];
9629             else f_regmap[hr]=-1;
9630           }
9631           else if(branch_regs[i].regmap[hr]>=0) f_regmap[hr]=branch_regs[i].regmap[hr];
9632           if(itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
9633           ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
9634           ||itype[i+1]==FCOMP||itype[i+1]==FCONV
9635           ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
9636           {
9637             // Test both in case the delay slot is ooo,
9638             // could be done better...
9639             if(count_free_regs(branch_regs[i].regmap)<2
9640              ||count_free_regs(regs[i].regmap)<2)
9641               f_regmap[hr]=branch_regs[i].regmap[hr];
9642           }
9643           // Avoid dirty->clean transition
9644           // #ifdef DESTRUCTIVE_WRITEBACK here?
9645           if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
9646           if(f_regmap[hr]>0) {
9647             if(regs[t].regmap_entry[hr]<0) {
9648               int r=f_regmap[hr];
9649               for(j=t;j<=i;j++)
9650               {
9651                 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9652                 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
9653                 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
9654                 if(r>63) {
9655                   // NB This can exclude the case where the upper-half
9656                   // register is lower numbered than the lower-half
9657                   // register.  Not sure if it's worth fixing...
9658                   if(get_reg(regs[j].regmap,r&63)<0) break;
9659                   if(regs[j].is32&(1LL<<(r&63))) break;
9660                 }
9661                 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
9662                   //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9663                   int k;
9664                   if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
9665                     if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
9666                     if(r>63) {
9667                       if(get_reg(regs[i].regmap,r&63)<0) break;
9668                       if(get_reg(branch_regs[i].regmap,r&63)<0) break;
9669                     }
9670                     k=i;
9671                     while(k>1&&regs[k-1].regmap[hr]==-1) {
9672                       if(itype[k-1]==STORE||itype[k-1]==STORELR
9673                       ||itype[k-1]==C1LS||itype[k-1]==SHIFT||itype[k-1]==COP1
9674                       ||itype[k-1]==FLOAT||itype[k-1]==FCONV||itype[k-1]==FCOMP
9675                       ||itype[k-1]==COP2||itype[k-1]==C2LS||itype[k-1]==C2OP) {
9676                         if(count_free_regs(regs[k-1].regmap)<2) {
9677                           //printf("no free regs for store %x\n",start+(k-1)*4);
9678                           break;
9679                         }
9680                       }
9681                       else
9682                       if(itype[k-1]!=NOP&&itype[k-1]!=MOV&&itype[k-1]!=ALU&&itype[k-1]!=SHIFTIMM&&itype[k-1]!=IMM16&&itype[k-1]!=LOAD) break;
9683                       if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
9684                         //printf("no-match due to different register\n");
9685                         break;
9686                       }
9687                       if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
9688                         //printf("no-match due to branch\n");
9689                         break;
9690                       }
9691                       // call/ret fast path assumes no registers allocated
9692                       if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)) {
9693                         break;
9694                       }
9695                       if(r>63) {
9696                         // NB This can exclude the case where the upper-half
9697                         // register is lower numbered than the lower-half
9698                         // register.  Not sure if it's worth fixing...
9699                         if(get_reg(regs[k-1].regmap,r&63)<0) break;
9700                         if(regs[k-1].is32&(1LL<<(r&63))) break;
9701                       }
9702                       k--;
9703                     }
9704                     if(i<slen-1) {
9705                       if((regs[k].is32&(1LL<<f_regmap[hr]))!=
9706                         (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
9707                         //printf("bad match after branch\n");
9708                         break;
9709                       }
9710                     }
9711                     if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
9712                       //printf("Extend r%d, %x ->\n",hr,start+k*4);
9713                       while(k<i) {
9714                         regs[k].regmap_entry[hr]=f_regmap[hr];
9715                         regs[k].regmap[hr]=f_regmap[hr];
9716                         regmap_pre[k+1][hr]=f_regmap[hr];
9717                         regs[k].wasdirty&=~(1<<hr);
9718                         regs[k].dirty&=~(1<<hr);
9719                         regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
9720                         regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
9721                         regs[k].wasconst&=~(1<<hr);
9722                         regs[k].isconst&=~(1<<hr);
9723                         k++;
9724                       }
9725                     }
9726                     else {
9727                       //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
9728                       break;
9729                     }
9730                     assert(regs[i-1].regmap[hr]==f_regmap[hr]);
9731                     if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
9732                       //printf("OK fill %x (r%d)\n",start+i*4,hr);
9733                       regs[i].regmap_entry[hr]=f_regmap[hr];
9734                       regs[i].regmap[hr]=f_regmap[hr];
9735                       regs[i].wasdirty&=~(1<<hr);
9736                       regs[i].dirty&=~(1<<hr);
9737                       regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
9738                       regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
9739                       regs[i].wasconst&=~(1<<hr);
9740                       regs[i].isconst&=~(1<<hr);
9741                       branch_regs[i].regmap_entry[hr]=f_regmap[hr];
9742                       branch_regs[i].wasdirty&=~(1<<hr);
9743                       branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
9744                       branch_regs[i].regmap[hr]=f_regmap[hr];
9745                       branch_regs[i].dirty&=~(1<<hr);
9746                       branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
9747                       branch_regs[i].wasconst&=~(1<<hr);
9748                       branch_regs[i].isconst&=~(1<<hr);
9749                       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
9750                         regmap_pre[i+2][hr]=f_regmap[hr];
9751                         regs[i+2].wasdirty&=~(1<<hr);
9752                         regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
9753                         assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
9754                           (regs[i+2].was32&(1LL<<f_regmap[hr])));
9755                       }
9756                     }
9757                   }
9758                   for(k=t;k<j;k++) {
9759                     regs[k].regmap_entry[hr]=f_regmap[hr];
9760                     regs[k].regmap[hr]=f_regmap[hr];
9761                     regmap_pre[k+1][hr]=f_regmap[hr];
9762                     regs[k+1].wasdirty&=~(1<<hr);
9763                     regs[k].dirty&=~(1<<hr);
9764                     regs[k].wasconst&=~(1<<hr);
9765                     regs[k].isconst&=~(1<<hr);
9766                   }
9767                   if(regs[j].regmap[hr]==f_regmap[hr])
9768                     regs[j].regmap_entry[hr]=f_regmap[hr];
9769                   break;
9770                 }
9771                 if(j==i) break;
9772                 if(regs[j].regmap[hr]>=0)
9773                   break;
9774                 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
9775                   //printf("no-match due to different register\n");
9776                   break;
9777                 }
9778                 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
9779                   //printf("32/64 mismatch %x %d\n",start+j*4,hr);
9780                   break;
9781                 }
9782                 if(itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS
9783                 ||itype[j]==SHIFT||itype[j]==COP1||itype[j]==FLOAT
9784                 ||itype[j]==FCOMP||itype[j]==FCONV
9785                 ||itype[j]==COP2||itype[j]==C2LS||itype[j]==C2OP) {
9786                   if(count_free_regs(regs[j].regmap)<2) {
9787                     //printf("No free regs for store %x\n",start+j*4);
9788                     break;
9789                   }
9790                 }
9791                 else if(itype[j]!=NOP&&itype[j]!=MOV&&itype[j]!=ALU&&itype[j]!=SHIFTIMM&&itype[j]!=IMM16&&itype[j]!=LOAD) break;
9792                 if(f_regmap[hr]>=64) {
9793                   if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
9794                     break;
9795                   }
9796                   else
9797                   {
9798                     if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
9799                       break;
9800                     }
9801                   }
9802                 }
9803               }
9804             }
9805           }
9806         }
9807       }
9808     }else{
9809       int count=0;
9810       for(hr=0;hr<HOST_REGS;hr++)
9811       {
9812         if(hr!=EXCLUDE_REG) {
9813           if(regs[i].regmap[hr]>64) {
9814             if(!((regs[i].dirty>>hr)&1))
9815               f_regmap[hr]=regs[i].regmap[hr];
9816           }
9817           else if(regs[i].regmap[hr]>=0) f_regmap[hr]=regs[i].regmap[hr];
9818           else if(regs[i].regmap[hr]<0) count++;
9819         }
9820       }
9821       // Try to restore cycle count at branch targets
9822       if(bt[i]) {
9823         for(j=i;j<slen-1;j++) {
9824           if(regs[j].regmap[HOST_CCREG]!=-1) break;
9825           if(itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS
9826           ||itype[j]==SHIFT||itype[j]==COP1||itype[j]==FLOAT
9827           ||itype[j]==FCOMP||itype[j]==FCONV
9828           ||itype[j]==COP2||itype[j]==C2LS||itype[j]==C2OP) {
9829             if(count_free_regs(regs[j].regmap)<2) {
9830               //printf("no free regs for store %x\n",start+j*4);
9831               break;
9832             }
9833           }
9834           else
9835           if(itype[j]!=NOP&&itype[j]!=MOV&&itype[j]!=ALU&&itype[j]!=SHIFTIMM&&itype[j]!=IMM16&&itype[j]!=LOAD) break;
9836         }
9837         if(regs[j].regmap[HOST_CCREG]==CCREG) {
9838           int k=i;
9839           //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
9840           while(k<j) {
9841             regs[k].regmap_entry[HOST_CCREG]=CCREG;
9842             regs[k].regmap[HOST_CCREG]=CCREG;
9843             regmap_pre[k+1][HOST_CCREG]=CCREG;
9844             regs[k+1].wasdirty|=1<<HOST_CCREG;
9845             regs[k].dirty|=1<<HOST_CCREG;
9846             regs[k].wasconst&=~(1<<HOST_CCREG);
9847             regs[k].isconst&=~(1<<HOST_CCREG);
9848             k++;
9849           }
9850           regs[j].regmap_entry[HOST_CCREG]=CCREG;
9851         }
9852         // Work backwards from the branch target
9853         if(j>i&&f_regmap[HOST_CCREG]==CCREG)
9854         {
9855           //printf("Extend backwards\n");
9856           int k;
9857           k=i;
9858           while(regs[k-1].regmap[HOST_CCREG]==-1) {
9859             if(itype[k-1]==STORE||itype[k-1]==STORELR||itype[k-1]==C1LS
9860             ||itype[k-1]==SHIFT||itype[k-1]==COP1||itype[k-1]==FLOAT
9861             ||itype[k-1]==FCONV||itype[k-1]==FCOMP
9862             ||itype[k-1]==COP2||itype[k-1]==C2LS||itype[k-1]==C2OP) {
9863               if(count_free_regs(regs[k-1].regmap)<2) {
9864                 //printf("no free regs for store %x\n",start+(k-1)*4);
9865                 break;
9866               }
9867             }
9868             else
9869             if(itype[k-1]!=NOP&&itype[k-1]!=MOV&&itype[k-1]!=ALU&&itype[k-1]!=SHIFTIMM&&itype[k-1]!=IMM16&&itype[k-1]!=LOAD) break;
9870             k--;
9871           }
9872           if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
9873             //printf("Extend CC, %x ->\n",start+k*4);
9874             while(k<=i) {
9875               regs[k].regmap_entry[HOST_CCREG]=CCREG;
9876               regs[k].regmap[HOST_CCREG]=CCREG;
9877               regmap_pre[k+1][HOST_CCREG]=CCREG;
9878               regs[k+1].wasdirty|=1<<HOST_CCREG;
9879               regs[k].dirty|=1<<HOST_CCREG;
9880               regs[k].wasconst&=~(1<<HOST_CCREG);
9881               regs[k].isconst&=~(1<<HOST_CCREG);
9882               k++;
9883             }
9884           }
9885           else {
9886             //printf("Fail Extend CC, %x ->\n",start+k*4);
9887           }
9888         }
9889       }
9890       if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
9891          itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
9892          itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
9893          itype[i]!=FCONV&&itype[i]!=FCOMP&&
9894          itype[i]!=COP2&&itype[i]!=C2LS&&itype[i]!=C2OP)
9895       {
9896         memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
9897       }
9898     }
9899   }
9900
9901   // This allocates registers (if possible) one instruction prior
9902   // to use, which can avoid a load-use penalty on certain CPUs.
9903   for(i=0;i<slen-1;i++)
9904   {
9905     if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
9906     {
9907       if(!bt[i+1])
9908       {
9909         if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
9910            ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
9911         {
9912           if(rs1[i+1]) {
9913             if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
9914             {
9915               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
9916               {
9917                 regs[i].regmap[hr]=regs[i+1].regmap[hr];
9918                 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
9919                 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
9920                 regs[i].isconst&=~(1<<hr);
9921                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9922                 constmap[i][hr]=constmap[i+1][hr];
9923                 regs[i+1].wasdirty&=~(1<<hr);
9924                 regs[i].dirty&=~(1<<hr);
9925               }
9926             }
9927           }
9928           if(rs2[i+1]) {
9929             if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
9930             {
9931               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
9932               {
9933                 regs[i].regmap[hr]=regs[i+1].regmap[hr];
9934                 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
9935                 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
9936                 regs[i].isconst&=~(1<<hr);
9937                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9938                 constmap[i][hr]=constmap[i+1][hr];
9939                 regs[i+1].wasdirty&=~(1<<hr);
9940                 regs[i].dirty&=~(1<<hr);
9941               }
9942             }
9943           }
9944           if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
9945             if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
9946             {
9947               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
9948               {
9949                 regs[i].regmap[hr]=rs1[i+1];
9950                 regmap_pre[i+1][hr]=rs1[i+1];
9951                 regs[i+1].regmap_entry[hr]=rs1[i+1];
9952                 regs[i].isconst&=~(1<<hr);
9953                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9954                 constmap[i][hr]=constmap[i+1][hr];
9955                 regs[i+1].wasdirty&=~(1<<hr);
9956                 regs[i].dirty&=~(1<<hr);
9957               }
9958             }
9959           }
9960           if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
9961             if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
9962             {
9963               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
9964               {
9965                 regs[i].regmap[hr]=rs1[i+1];
9966                 regmap_pre[i+1][hr]=rs1[i+1];
9967                 regs[i+1].regmap_entry[hr]=rs1[i+1];
9968                 regs[i].isconst&=~(1<<hr);
9969                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9970                 constmap[i][hr]=constmap[i+1][hr];
9971                 regs[i+1].wasdirty&=~(1<<hr);
9972                 regs[i].dirty&=~(1<<hr);
9973               }
9974             }
9975           }
9976           #ifndef HOST_IMM_ADDR32
9977           if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
9978             hr=get_reg(regs[i+1].regmap,TLREG);
9979             if(hr>=0) {
9980               int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
9981               if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
9982                 int nr;
9983                 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
9984                 {
9985                   regs[i].regmap[hr]=MGEN1+((i+1)&1);
9986                   regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
9987                   regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
9988                   regs[i].isconst&=~(1<<hr);
9989                   regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9990                   constmap[i][hr]=constmap[i+1][hr];
9991                   regs[i+1].wasdirty&=~(1<<hr);
9992                   regs[i].dirty&=~(1<<hr);
9993                 }
9994                 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
9995                 {
9996                   // move it to another register
9997                   regs[i+1].regmap[hr]=-1;
9998                   regmap_pre[i+2][hr]=-1;
9999                   regs[i+1].regmap[nr]=TLREG;
10000                   regmap_pre[i+2][nr]=TLREG;
10001                   regs[i].regmap[nr]=MGEN1+((i+1)&1);
10002                   regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10003                   regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10004                   regs[i].isconst&=~(1<<nr);
10005                   regs[i+1].isconst&=~(1<<nr);
10006                   regs[i].dirty&=~(1<<nr);
10007                   regs[i+1].wasdirty&=~(1<<nr);
10008                   regs[i+1].dirty&=~(1<<nr);
10009                   regs[i+2].wasdirty&=~(1<<nr);
10010                 }
10011               }
10012             }
10013           }
10014           #endif
10015           if(itype[i+1]==STORE||itype[i+1]==STORELR
10016              ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
10017             if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10018               hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10019               if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10020               else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10021               assert(hr>=0);
10022               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10023               {
10024                 regs[i].regmap[hr]=rs1[i+1];
10025                 regmap_pre[i+1][hr]=rs1[i+1];
10026                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10027                 regs[i].isconst&=~(1<<hr);
10028                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10029                 constmap[i][hr]=constmap[i+1][hr];
10030                 regs[i+1].wasdirty&=~(1<<hr);
10031                 regs[i].dirty&=~(1<<hr);
10032               }
10033             }
10034           }
10035           if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
10036             if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10037               int nr;
10038               hr=get_reg(regs[i+1].regmap,FTEMP);
10039               assert(hr>=0);
10040               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10041               {
10042                 regs[i].regmap[hr]=rs1[i+1];
10043                 regmap_pre[i+1][hr]=rs1[i+1];
10044                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10045                 regs[i].isconst&=~(1<<hr);
10046                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10047                 constmap[i][hr]=constmap[i+1][hr];
10048                 regs[i+1].wasdirty&=~(1<<hr);
10049                 regs[i].dirty&=~(1<<hr);
10050               }
10051               else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10052               {
10053                 // move it to another register
10054                 regs[i+1].regmap[hr]=-1;
10055                 regmap_pre[i+2][hr]=-1;
10056                 regs[i+1].regmap[nr]=FTEMP;
10057                 regmap_pre[i+2][nr]=FTEMP;
10058                 regs[i].regmap[nr]=rs1[i+1];
10059                 regmap_pre[i+1][nr]=rs1[i+1];
10060                 regs[i+1].regmap_entry[nr]=rs1[i+1];
10061                 regs[i].isconst&=~(1<<nr);
10062                 regs[i+1].isconst&=~(1<<nr);
10063                 regs[i].dirty&=~(1<<nr);
10064                 regs[i+1].wasdirty&=~(1<<nr);
10065                 regs[i+1].dirty&=~(1<<nr);
10066                 regs[i+2].wasdirty&=~(1<<nr);
10067               }
10068             }
10069           }
10070           if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
10071             if(itype[i+1]==LOAD)
10072               hr=get_reg(regs[i+1].regmap,rt1[i+1]);
10073             if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
10074               hr=get_reg(regs[i+1].regmap,FTEMP);
10075             if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
10076               hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10077               if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10078             }
10079             if(hr>=0&&regs[i].regmap[hr]<0) {
10080               int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10081               if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10082                 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10083                 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10084                 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10085                 regs[i].isconst&=~(1<<hr);
10086                 regs[i+1].wasdirty&=~(1<<hr);
10087                 regs[i].dirty&=~(1<<hr);
10088               }
10089             }
10090           }
10091         }
10092       }
10093     }
10094   }
10095
10096   /* Pass 6 - Optimize clean/dirty state */
10097   clean_registers(0,slen-1,1);
10098
10099   /* Pass 7 - Identify 32-bit registers */
10100
10101   provisional_r32();
10102
10103   u_int r32=0;
10104
10105   for (i=slen-1;i>=0;i--)
10106   {
10107     int hr;
10108     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10109     {
10110       if(ba[i]<start || ba[i]>=(start+slen*4))
10111       {
10112         // Branch out of this block, don't need anything
10113         r32=0;
10114       }
10115       else
10116       {
10117         // Internal branch
10118         // Need whatever matches the target
10119         // (and doesn't get overwritten by the delay slot instruction)
10120         r32=0;
10121         int t=(ba[i]-start)>>2;
10122         if(ba[i]>start+i*4) {
10123           // Forward branch
10124           if(!(requires_32bit[t]&~regs[i].was32))
10125             r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10126         }else{
10127           // Backward branch
10128           //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10129           //  r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10130           if(!(pr32[t]&~regs[i].was32))
10131             r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10132         }
10133       }
10134       // Conditional branch may need registers for following instructions
10135       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10136       {
10137         if(i<slen-2) {
10138           r32|=requires_32bit[i+2];
10139           r32&=regs[i].was32;
10140           // Mark this address as a branch target since it may be called
10141           // upon return from interrupt
10142           bt[i+2]=1;
10143         }
10144       }
10145       // Merge in delay slot
10146       if(!likely[i]) {
10147         // These are overwritten unless the branch is "likely"
10148         // and the delay slot is nullified if not taken
10149         r32&=~(1LL<<rt1[i+1]);
10150         r32&=~(1LL<<rt2[i+1]);
10151       }
10152       // Assume these are needed (delay slot)
10153       if(us1[i+1]>0)
10154       {
10155         if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10156       }
10157       if(us2[i+1]>0)
10158       {
10159         if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10160       }
10161       if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10162       {
10163         if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10164       }
10165       if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10166       {
10167         if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10168       }
10169     }
10170     else if(itype[i]==SYSCALL||itype[i]==HLECALL)
10171     {
10172       // SYSCALL instruction (software interrupt)
10173       r32=0;
10174     }
10175     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10176     {
10177       // ERET instruction (return from interrupt)
10178       r32=0;
10179     }
10180     // Check 32 bits
10181     r32&=~(1LL<<rt1[i]);
10182     r32&=~(1LL<<rt2[i]);
10183     if(us1[i]>0)
10184     {
10185       if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10186     }
10187     if(us2[i]>0)
10188     {
10189       if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10190     }
10191     if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
10192     {
10193       if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
10194     }
10195     if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
10196     {
10197       if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
10198     }
10199     requires_32bit[i]=r32;
10200
10201     // Dirty registers which are 32-bit, require 32-bit input
10202     // as they will be written as 32-bit values
10203     for(hr=0;hr<HOST_REGS;hr++)
10204     {
10205       if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
10206         if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
10207           if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
10208           requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
10209         }
10210       }
10211     }
10212     //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
10213   }
10214
10215   if(itype[slen-1]==SPAN) {
10216     bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
10217   }
10218
10219   /* Debug/disassembly */
10220   if((void*)assem_debug==(void*)printf)
10221   for(i=0;i<slen;i++)
10222   {
10223     printf("U:");
10224     int r;
10225     for(r=1;r<=CCREG;r++) {
10226       if((unneeded_reg[i]>>r)&1) {
10227         if(r==HIREG) printf(" HI");
10228         else if(r==LOREG) printf(" LO");
10229         else printf(" r%d",r);
10230       }
10231     }
10232 #ifndef FORCE32
10233     printf(" UU:");
10234     for(r=1;r<=CCREG;r++) {
10235       if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
10236         if(r==HIREG) printf(" HI");
10237         else if(r==LOREG) printf(" LO");
10238         else printf(" r%d",r);
10239       }
10240     }
10241     printf(" 32:");
10242     for(r=0;r<=CCREG;r++) {
10243       //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10244       if((regs[i].was32>>r)&1) {
10245         if(r==CCREG) printf(" CC");
10246         else if(r==HIREG) printf(" HI");
10247         else if(r==LOREG) printf(" LO");
10248         else printf(" r%d",r);
10249       }
10250     }
10251 #endif
10252     printf("\n");
10253     #if defined(__i386__) || defined(__x86_64__)
10254     printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
10255     #endif
10256     #ifdef __arm__
10257     printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
10258     #endif
10259     printf("needs: ");
10260     if(needed_reg[i]&1) printf("eax ");
10261     if((needed_reg[i]>>1)&1) printf("ecx ");
10262     if((needed_reg[i]>>2)&1) printf("edx ");
10263     if((needed_reg[i]>>3)&1) printf("ebx ");
10264     if((needed_reg[i]>>5)&1) printf("ebp ");
10265     if((needed_reg[i]>>6)&1) printf("esi ");
10266     if((needed_reg[i]>>7)&1) printf("edi ");
10267     printf("r:");
10268     for(r=0;r<=CCREG;r++) {
10269       //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10270       if((requires_32bit[i]>>r)&1) {
10271         if(r==CCREG) printf(" CC");
10272         else if(r==HIREG) printf(" HI");
10273         else if(r==LOREG) printf(" LO");
10274         else printf(" r%d",r);
10275       }
10276     }
10277     printf("\n");
10278     /*printf("pr:");
10279     for(r=0;r<=CCREG;r++) {
10280       //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10281       if((pr32[i]>>r)&1) {
10282         if(r==CCREG) printf(" CC");
10283         else if(r==HIREG) printf(" HI");
10284         else if(r==LOREG) printf(" LO");
10285         else printf(" r%d",r);
10286       }
10287     }
10288     if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
10289     printf("\n");*/
10290     #if defined(__i386__) || defined(__x86_64__)
10291     printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
10292     printf("dirty: ");
10293     if(regs[i].wasdirty&1) printf("eax ");
10294     if((regs[i].wasdirty>>1)&1) printf("ecx ");
10295     if((regs[i].wasdirty>>2)&1) printf("edx ");
10296     if((regs[i].wasdirty>>3)&1) printf("ebx ");
10297     if((regs[i].wasdirty>>5)&1) printf("ebp ");
10298     if((regs[i].wasdirty>>6)&1) printf("esi ");
10299     if((regs[i].wasdirty>>7)&1) printf("edi ");
10300     #endif
10301     #ifdef __arm__
10302     printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
10303     printf("dirty: ");
10304     if(regs[i].wasdirty&1) printf("r0 ");
10305     if((regs[i].wasdirty>>1)&1) printf("r1 ");
10306     if((regs[i].wasdirty>>2)&1) printf("r2 ");
10307     if((regs[i].wasdirty>>3)&1) printf("r3 ");
10308     if((regs[i].wasdirty>>4)&1) printf("r4 ");
10309     if((regs[i].wasdirty>>5)&1) printf("r5 ");
10310     if((regs[i].wasdirty>>6)&1) printf("r6 ");
10311     if((regs[i].wasdirty>>7)&1) printf("r7 ");
10312     if((regs[i].wasdirty>>8)&1) printf("r8 ");
10313     if((regs[i].wasdirty>>9)&1) printf("r9 ");
10314     if((regs[i].wasdirty>>10)&1) printf("r10 ");
10315     if((regs[i].wasdirty>>12)&1) printf("r12 ");
10316     #endif
10317     printf("\n");
10318     disassemble_inst(i);
10319     //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
10320     #if defined(__i386__) || defined(__x86_64__)
10321     printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
10322     if(regs[i].dirty&1) printf("eax ");
10323     if((regs[i].dirty>>1)&1) printf("ecx ");
10324     if((regs[i].dirty>>2)&1) printf("edx ");
10325     if((regs[i].dirty>>3)&1) printf("ebx ");
10326     if((regs[i].dirty>>5)&1) printf("ebp ");
10327     if((regs[i].dirty>>6)&1) printf("esi ");
10328     if((regs[i].dirty>>7)&1) printf("edi ");
10329     #endif
10330     #ifdef __arm__
10331     printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
10332     if(regs[i].dirty&1) printf("r0 ");
10333     if((regs[i].dirty>>1)&1) printf("r1 ");
10334     if((regs[i].dirty>>2)&1) printf("r2 ");
10335     if((regs[i].dirty>>3)&1) printf("r3 ");
10336     if((regs[i].dirty>>4)&1) printf("r4 ");
10337     if((regs[i].dirty>>5)&1) printf("r5 ");
10338     if((regs[i].dirty>>6)&1) printf("r6 ");
10339     if((regs[i].dirty>>7)&1) printf("r7 ");
10340     if((regs[i].dirty>>8)&1) printf("r8 ");
10341     if((regs[i].dirty>>9)&1) printf("r9 ");
10342     if((regs[i].dirty>>10)&1) printf("r10 ");
10343     if((regs[i].dirty>>12)&1) printf("r12 ");
10344     #endif
10345     printf("\n");
10346     if(regs[i].isconst) {
10347       printf("constants: ");
10348       #if defined(__i386__) || defined(__x86_64__)
10349       if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
10350       if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
10351       if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
10352       if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
10353       if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
10354       if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
10355       if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
10356       #endif
10357       #ifdef __arm__
10358       if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
10359       if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
10360       if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
10361       if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
10362       if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
10363       if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
10364       if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
10365       if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
10366       if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
10367       if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
10368       if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
10369       if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
10370       #endif
10371       printf("\n");
10372     }
10373 #ifndef FORCE32
10374     printf(" 32:");
10375     for(r=0;r<=CCREG;r++) {
10376       if((regs[i].is32>>r)&1) {
10377         if(r==CCREG) printf(" CC");
10378         else if(r==HIREG) printf(" HI");
10379         else if(r==LOREG) printf(" LO");
10380         else printf(" r%d",r);
10381       }
10382     }
10383     printf("\n");
10384 #endif
10385     /*printf(" p32:");
10386     for(r=0;r<=CCREG;r++) {
10387       if((p32[i]>>r)&1) {
10388         if(r==CCREG) printf(" CC");
10389         else if(r==HIREG) printf(" HI");
10390         else if(r==LOREG) printf(" LO");
10391         else printf(" r%d",r);
10392       }
10393     }
10394     if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
10395     else printf("\n");*/
10396     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10397       #if defined(__i386__) || defined(__x86_64__)
10398       printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
10399       if(branch_regs[i].dirty&1) printf("eax ");
10400       if((branch_regs[i].dirty>>1)&1) printf("ecx ");
10401       if((branch_regs[i].dirty>>2)&1) printf("edx ");
10402       if((branch_regs[i].dirty>>3)&1) printf("ebx ");
10403       if((branch_regs[i].dirty>>5)&1) printf("ebp ");
10404       if((branch_regs[i].dirty>>6)&1) printf("esi ");
10405       if((branch_regs[i].dirty>>7)&1) printf("edi ");
10406       #endif
10407       #ifdef __arm__
10408       printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
10409       if(branch_regs[i].dirty&1) printf("r0 ");
10410       if((branch_regs[i].dirty>>1)&1) printf("r1 ");
10411       if((branch_regs[i].dirty>>2)&1) printf("r2 ");
10412       if((branch_regs[i].dirty>>3)&1) printf("r3 ");
10413       if((branch_regs[i].dirty>>4)&1) printf("r4 ");
10414       if((branch_regs[i].dirty>>5)&1) printf("r5 ");
10415       if((branch_regs[i].dirty>>6)&1) printf("r6 ");
10416       if((branch_regs[i].dirty>>7)&1) printf("r7 ");
10417       if((branch_regs[i].dirty>>8)&1) printf("r8 ");
10418       if((branch_regs[i].dirty>>9)&1) printf("r9 ");
10419       if((branch_regs[i].dirty>>10)&1) printf("r10 ");
10420       if((branch_regs[i].dirty>>12)&1) printf("r12 ");
10421       #endif
10422 #ifndef FORCE32
10423       printf(" 32:");
10424       for(r=0;r<=CCREG;r++) {
10425         if((branch_regs[i].is32>>r)&1) {
10426           if(r==CCREG) printf(" CC");
10427           else if(r==HIREG) printf(" HI");
10428           else if(r==LOREG) printf(" LO");
10429           else printf(" r%d",r);
10430         }
10431       }
10432       printf("\n");
10433 #endif
10434     }
10435   }
10436
10437   /* Pass 8 - Assembly */
10438   linkcount=0;stubcount=0;
10439   ds=0;is_delayslot=0;
10440   cop1_usable=0;
10441   uint64_t is32_pre=0;
10442   u_int dirty_pre=0;
10443   u_int beginning=(u_int)out;
10444   if((u_int)addr&1) {
10445     ds=1;
10446     pagespan_ds();
10447   }
10448   for(i=0;i<slen;i++)
10449   {
10450     //if(ds) printf("ds: ");
10451     if((void*)assem_debug==(void*)printf) disassemble_inst(i);
10452     if(ds) {
10453       ds=0; // Skip delay slot
10454       if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
10455       instr_addr[i]=0;
10456     } else {
10457       #ifndef DESTRUCTIVE_WRITEBACK
10458       if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10459       {
10460         wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
10461               unneeded_reg[i],unneeded_reg_upper[i]);
10462         wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
10463               unneeded_reg[i],unneeded_reg_upper[i]);
10464       }
10465       is32_pre=regs[i].is32;
10466       dirty_pre=regs[i].dirty;
10467       #endif
10468       // write back
10469       if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10470       {
10471         wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
10472                       unneeded_reg[i],unneeded_reg_upper[i]);
10473         loop_preload(regmap_pre[i],regs[i].regmap_entry);
10474       }
10475       // branch target entry point
10476       instr_addr[i]=(u_int)out;
10477       assem_debug("<->\n");
10478       // load regs
10479       if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
10480         wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
10481       load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
10482       address_generation(i,&regs[i],regs[i].regmap_entry);
10483       load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
10484       if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10485       {
10486         // Load the delay slot registers if necessary
10487         if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10488           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10489         if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10490           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
10491         if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
10492           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10493       }
10494       else if(i+1<slen)
10495       {
10496         // Preload registers for following instruction
10497         if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10498           if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
10499             load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10500         if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10501           if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
10502             load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
10503       }
10504       // TODO: if(is_ooo(i)) address_generation(i+1);
10505       if(itype[i]==CJUMP||itype[i]==FJUMP)
10506         load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
10507       if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
10508         load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10509       if(bt[i]) cop1_usable=0;
10510       // assemble
10511       switch(itype[i]) {
10512         case ALU:
10513           alu_assemble(i,&regs[i]);break;
10514         case IMM16:
10515           imm16_assemble(i,&regs[i]);break;
10516         case SHIFT:
10517           shift_assemble(i,&regs[i]);break;
10518         case SHIFTIMM:
10519           shiftimm_assemble(i,&regs[i]);break;
10520         case LOAD:
10521           load_assemble(i,&regs[i]);break;
10522         case LOADLR:
10523           loadlr_assemble(i,&regs[i]);break;
10524         case STORE:
10525           store_assemble(i,&regs[i]);break;
10526         case STORELR:
10527           storelr_assemble(i,&regs[i]);break;
10528         case COP0:
10529           cop0_assemble(i,&regs[i]);break;
10530         case COP1:
10531           cop1_assemble(i,&regs[i]);break;
10532         case C1LS:
10533           c1ls_assemble(i,&regs[i]);break;
10534         case COP2:
10535           cop2_assemble(i,&regs[i]);break;
10536         case C2LS:
10537           c2ls_assemble(i,&regs[i]);break;
10538         case C2OP:
10539           c2op_assemble(i,&regs[i]);break;
10540         case FCONV:
10541           fconv_assemble(i,&regs[i]);break;
10542         case FLOAT:
10543           float_assemble(i,&regs[i]);break;
10544         case FCOMP:
10545           fcomp_assemble(i,&regs[i]);break;
10546         case MULTDIV:
10547           multdiv_assemble(i,&regs[i]);break;
10548         case MOV:
10549           mov_assemble(i,&regs[i]);break;
10550         case SYSCALL:
10551           syscall_assemble(i,&regs[i]);break;
10552         case HLECALL:
10553           hlecall_assemble(i,&regs[i]);break;
10554         case UJUMP:
10555           ujump_assemble(i,&regs[i]);ds=1;break;
10556         case RJUMP:
10557           rjump_assemble(i,&regs[i]);ds=1;break;
10558         case CJUMP:
10559           cjump_assemble(i,&regs[i]);ds=1;break;
10560         case SJUMP:
10561           sjump_assemble(i,&regs[i]);ds=1;break;
10562         case FJUMP:
10563           fjump_assemble(i,&regs[i]);ds=1;break;
10564         case SPAN:
10565           pagespan_assemble(i,&regs[i]);break;
10566       }
10567       if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10568         literal_pool(1024);
10569       else
10570         literal_pool_jumpover(256);
10571     }
10572   }
10573   //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
10574   // If the block did not end with an unconditional branch,
10575   // add a jump to the next instruction.
10576   if(i>1) {
10577     if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
10578       assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10579       assert(i==slen);
10580       if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
10581         store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10582         if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10583           emit_loadreg(CCREG,HOST_CCREG);
10584         emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10585       }
10586       else if(!likely[i-2])
10587       {
10588         store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
10589         assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
10590       }
10591       else
10592       {
10593         store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
10594         assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
10595       }
10596       add_to_linker((int)out,start+i*4,0);
10597       emit_jmp(0);
10598     }
10599   }
10600   else
10601   {
10602     assert(i>0);
10603     assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10604     store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10605     if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10606       emit_loadreg(CCREG,HOST_CCREG);
10607     emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10608     add_to_linker((int)out,start+i*4,0);
10609     emit_jmp(0);
10610   }
10611
10612   // TODO: delay slot stubs?
10613   // Stubs
10614   for(i=0;i<stubcount;i++)
10615   {
10616     switch(stubs[i][0])
10617     {
10618       case LOADB_STUB:
10619       case LOADH_STUB:
10620       case LOADW_STUB:
10621       case LOADD_STUB:
10622       case LOADBU_STUB:
10623       case LOADHU_STUB:
10624         do_readstub(i);break;
10625       case STOREB_STUB:
10626       case STOREH_STUB:
10627       case STOREW_STUB:
10628       case STORED_STUB:
10629         do_writestub(i);break;
10630       case CC_STUB:
10631         do_ccstub(i);break;
10632       case INVCODE_STUB:
10633         do_invstub(i);break;
10634       case FP_STUB:
10635         do_cop1stub(i);break;
10636       case STORELR_STUB:
10637         do_unalignedwritestub(i);break;
10638     }
10639   }
10640
10641   /* Pass 9 - Linker */
10642   for(i=0;i<linkcount;i++)
10643   {
10644     assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
10645     literal_pool(64);
10646     if(!link_addr[i][2])
10647     {
10648       void *stub=out;
10649       void *addr=check_addr(link_addr[i][1]);
10650       emit_extjump(link_addr[i][0],link_addr[i][1]);
10651       if(addr) {
10652         set_jump_target(link_addr[i][0],(int)addr);
10653         add_link(link_addr[i][1],stub);
10654       }
10655       else set_jump_target(link_addr[i][0],(int)stub);
10656     }
10657     else
10658     {
10659       // Internal branch
10660       int target=(link_addr[i][1]-start)>>2;
10661       assert(target>=0&&target<slen);
10662       assert(instr_addr[target]);
10663       //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10664       //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
10665       //#else
10666       set_jump_target(link_addr[i][0],instr_addr[target]);
10667       //#endif
10668     }
10669   }
10670   // External Branch Targets (jump_in)
10671   if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
10672   for(i=0;i<slen;i++)
10673   {
10674     if(bt[i]||i==0)
10675     {
10676       if(instr_addr[i]) // TODO - delay slots (=null)
10677       {
10678         u_int vaddr=start+i*4;
10679         u_int page=get_page(vaddr);
10680         u_int vpage=get_vpage(vaddr);
10681         literal_pool(256);
10682         //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
10683         if(!requires_32bit[i])
10684         {
10685           assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
10686           assem_debug("jump_in: %x\n",start+i*4);
10687           ll_add(jump_dirty+vpage,vaddr,(void *)out);
10688           int entry_point=do_dirty_stub(i);
10689           ll_add(jump_in+page,vaddr,(void *)entry_point);
10690           // If there was an existing entry in the hash table,
10691           // replace it with the new address.
10692           // Don't add new entries.  We'll insert the
10693           // ones that actually get used in check_addr().
10694           int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
10695           if(ht_bin[0]==vaddr) {
10696             ht_bin[1]=entry_point;
10697           }
10698           if(ht_bin[2]==vaddr) {
10699             ht_bin[3]=entry_point;
10700           }
10701         }
10702         else
10703         {
10704           u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
10705           assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
10706           assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
10707           //int entry_point=(int)out;
10708           ////assem_debug("entry_point: %x\n",entry_point);
10709           //load_regs_entry(i);
10710           //if(entry_point==(int)out)
10711           //  entry_point=instr_addr[i];
10712           //else
10713           //  emit_jmp(instr_addr[i]);
10714           //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
10715           ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
10716           int entry_point=do_dirty_stub(i);
10717           ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
10718         }
10719       }
10720     }
10721   }
10722   // Write out the literal pool if necessary
10723   literal_pool(0);
10724   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10725   // Align code
10726   if(((u_int)out)&7) emit_addnop(13);
10727   #endif
10728   assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
10729   //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
10730   memcpy(copy,source,slen*4);
10731   copy+=slen*4;
10732
10733   #ifdef __arm__
10734   __clear_cache((void *)beginning,out);
10735   #endif
10736
10737   // If we're within 256K of the end of the buffer,
10738   // start over from the beginning. (Is 256K enough?)
10739   if((int)out>BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
10740
10741   // Trap writes to any of the pages we compiled
10742   for(i=start>>12;i<=(start+slen*4)>>12;i++) {
10743     invalid_code[i]=0;
10744 #ifndef DISABLE_TLB
10745     memory_map[i]|=0x40000000;
10746     if((signed int)start>=(signed int)0xC0000000) {
10747       assert(using_tlb);
10748       j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
10749       invalid_code[j]=0;
10750       memory_map[j]|=0x40000000;
10751       //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
10752     }
10753 #endif
10754   }
10755
10756   /* Pass 10 - Free memory by expiring oldest blocks */
10757
10758   int end=((((int)out-BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
10759   while(expirep!=end)
10760   {
10761     int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
10762     int base=BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
10763     inv_debug("EXP: Phase %d\n",expirep);
10764     switch((expirep>>11)&3)
10765     {
10766       case 0:
10767         // Clear jump_in and jump_dirty
10768         ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
10769         ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
10770         ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
10771         ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
10772         break;
10773       case 1:
10774         // Clear pointers
10775         ll_kill_pointers(jump_out[expirep&2047],base,shift);
10776         ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
10777         break;
10778       case 2:
10779         // Clear hash table
10780         for(i=0;i<32;i++) {
10781           int *ht_bin=hash_table[((expirep&2047)<<5)+i];
10782           if((ht_bin[3]>>shift)==(base>>shift) ||
10783              ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
10784             inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
10785             ht_bin[2]=ht_bin[3]=-1;
10786           }
10787           if((ht_bin[1]>>shift)==(base>>shift) ||
10788              ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
10789             inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
10790             ht_bin[0]=ht_bin[2];
10791             ht_bin[1]=ht_bin[3];
10792             ht_bin[2]=ht_bin[3]=-1;
10793           }
10794         }
10795         break;
10796       case 3:
10797         // Clear jump_out
10798         #ifdef __arm__
10799         if((expirep&2047)==0)
10800           __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
10801         #endif
10802         ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
10803         ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
10804         break;
10805     }
10806     expirep=(expirep+1)&65535;
10807   }
10808   return 0;
10809 }
10810
10811 // vim:shiftwidth=2:expandtab