libpcsxcore/new_dynarec/new_dynarec.c

   1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
   2  *   Mupen64plus - new_dynarec.c                                           *
   3  *   Copyright (C) 2009-2011 Ari64                                         *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.          *
  19  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
  20
  21 #include <stdlib.h>
  22 #include <stdint.h> //include for uint64_t
  23 #include <assert.h>
  24 #include <errno.h>
  25 #include <sys/mman.h>
  26
  27 #include "emu_if.h" //emulator interface
  28
  29 //#define DISASM
  30 //#define assem_debug printf
  31 //#define inv_debug printf
  32 #define assem_debug(...)
  33 #define inv_debug(...)
  34
  35 #ifdef __i386__
  36 #include "assem_x86.h"
  37 #endif
  38 #ifdef __x86_64__
  39 #include "assem_x64.h"
  40 #endif
  41 #ifdef __arm__
  42 #include "assem_arm.h"
  43 #endif
  44
  45 #ifdef __BLACKBERRY_QNX__
  46 #undef __clear_cache
  47 #define __clear_cache(start,end) msync(start, (size_t)((void*)end - (void*)start), MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE);
  48 #elif defined(__MACH__)
  49 #include <libkern/OSCacheControl.h>
  50 #define __clear_cache mach_clear_cache
  51 static void __clear_cache(void *start, void *end) {
  52   size_t len = (char *)end - (char *)start;
  53   sys_dcache_flush(start, len);
  54   sys_icache_invalidate(start, len);
  55 }
  56 #endif
  57
  58 #define MAXBLOCK 4096
  59 #define MAX_OUTPUT_BLOCK_SIZE 262144
  60
  61 struct regstat
  62 {
  63   signed char regmap_entry[HOST_REGS];
  64   signed char regmap[HOST_REGS];
  65   uint64_t was32;
  66   uint64_t is32;
  67   uint64_t wasdirty;
  68   uint64_t dirty;
  69   uint64_t u;
  70   uint64_t uu;
  71   u_int wasconst;
  72   u_int isconst;
  73   u_int loadedconst;             // host regs that have constants loaded
  74   u_int waswritten;              // MIPS regs that were used as store base before
  75 };
  76
  77 // note: asm depends on this layout
  78 struct ll_entry
  79 {
  80   u_int vaddr;
  81   u_int reg_sv_flags;
  82   void *addr;
  83   struct ll_entry *next;
  84 };
  85
  86   u_int start;
  87   u_int *source;
  88   u_int pagelimit;
  89   char insn[MAXBLOCK][10];
  90   u_char itype[MAXBLOCK];
  91   u_char opcode[MAXBLOCK];
  92   u_char opcode2[MAXBLOCK];
  93   u_char bt[MAXBLOCK];
  94   u_char rs1[MAXBLOCK];
  95   u_char rs2[MAXBLOCK];
  96   u_char rt1[MAXBLOCK];
  97   u_char rt2[MAXBLOCK];
  98   u_char us1[MAXBLOCK];
  99   u_char us2[MAXBLOCK];
 100   u_char dep1[MAXBLOCK];
 101   u_char dep2[MAXBLOCK];
 102   u_char lt1[MAXBLOCK];
 103   static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
 104   static uint64_t gte_rt[MAXBLOCK];
 105   static uint64_t gte_unneeded[MAXBLOCK];
 106   static u_int smrv[32]; // speculated MIPS register values
 107   static u_int smrv_strong; // mask or regs that are likely to have correct values
 108   static u_int smrv_weak; // same, but somewhat less likely
 109   static u_int smrv_strong_next; // same, but after current insn executes
 110   static u_int smrv_weak_next;
 111   int imm[MAXBLOCK];
 112   u_int ba[MAXBLOCK];
 113   char likely[MAXBLOCK];
 114   char is_ds[MAXBLOCK];
 115   char ooo[MAXBLOCK];
 116   uint64_t unneeded_reg[MAXBLOCK];
 117   uint64_t unneeded_reg_upper[MAXBLOCK];
 118   uint64_t branch_unneeded_reg[MAXBLOCK];
 119   uint64_t branch_unneeded_reg_upper[MAXBLOCK];
 120   uint64_t p32[MAXBLOCK];
 121   uint64_t pr32[MAXBLOCK];
 122   signed char regmap_pre[MAXBLOCK][HOST_REGS];
 123   static uint64_t current_constmap[HOST_REGS];
 124   static uint64_t constmap[MAXBLOCK][HOST_REGS];
 125   static struct regstat regs[MAXBLOCK];
 126   static struct regstat branch_regs[MAXBLOCK];
 127   signed char minimum_free_regs[MAXBLOCK];
 128   u_int needed_reg[MAXBLOCK];
 129   uint64_t requires_32bit[MAXBLOCK];
 130   u_int wont_dirty[MAXBLOCK];
 131   u_int will_dirty[MAXBLOCK];
 132   int ccadj[MAXBLOCK];
 133   int slen;
 134   u_int instr_addr[MAXBLOCK];
 135   u_int link_addr[MAXBLOCK][3];
 136   int linkcount;
 137   u_int stubs[MAXBLOCK*3][8];
 138   int stubcount;
 139   u_int literals[1024][2];
 140   int literalcount;
 141   int is_delayslot;
 142   int cop1_usable;
 143   u_char *out;
 144   struct ll_entry *jump_in[4096] __attribute__((aligned(16)));
 145   struct ll_entry *jump_out[4096];
 146   struct ll_entry *jump_dirty[4096];
 147   u_int hash_table[65536][4]  __attribute__((aligned(16)));
 148   char shadow[1048576]  __attribute__((aligned(16)));
 149   void *copy;
 150   int expirep;
 151 #ifndef PCSX
 152   u_int using_tlb;
 153 #else
 154   static const u_int using_tlb=0;
 155 #endif
 156   int new_dynarec_did_compile;
 157   int new_dynarec_hacks;
 158   u_int stop_after_jal;
 159 #ifndef RAM_FIXED
 160   static u_int ram_offset;
 161 #else
 162   static const u_int ram_offset=0;
 163 #endif
 164   extern u_char restore_candidate[512];
 165   extern int cycle_count;
 166
 167   /* registers that may be allocated */
 168   /* 1-31 gpr */
 169 #define HIREG 32 // hi
 170 #define LOREG 33 // lo
 171 #define FSREG 34 // FPU status (FCSR)
 172 #define CSREG 35 // Coprocessor status
 173 #define CCREG 36 // Cycle count
 174 #define INVCP 37 // Pointer to invalid_code
 175 #define MMREG 38 // Pointer to memory_map
 176 #define ROREG 39 // ram offset (if rdram!=0x80000000)
 177 #define TEMPREG 40
 178 #define FTEMP 40 // FPU temporary register
 179 #define PTEMP 41 // Prefetch temporary register
 180 #define TLREG 42 // TLB mapping offset
 181 #define RHASH 43 // Return address hash
 182 #define RHTBL 44 // Return address hash table address
 183 #define RTEMP 45 // JR/JALR address register
 184 #define MAXREG 45
 185 #define AGEN1 46 // Address generation temporary register
 186 #define AGEN2 47 // Address generation temporary register
 187 #define MGEN1 48 // Maptable address generation temporary register
 188 #define MGEN2 49 // Maptable address generation temporary register
 189 #define BTREG 50 // Branch target temporary register
 190
 191   /* instruction types */
 192 #define NOP 0     // No operation
 193 #define LOAD 1    // Load
 194 #define STORE 2   // Store
 195 #define LOADLR 3  // Unaligned load
 196 #define STORELR 4 // Unaligned store
 197 #define MOV 5     // Move
 198 #define ALU 6     // Arithmetic/logic
 199 #define MULTDIV 7 // Multiply/divide
 200 #define SHIFT 8   // Shift by register
 201 #define SHIFTIMM 9// Shift by immediate
 202 #define IMM16 10  // 16-bit immediate
 203 #define RJUMP 11  // Unconditional jump to register
 204 #define UJUMP 12  // Unconditional jump
 205 #define CJUMP 13  // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
 206 #define SJUMP 14  // Conditional branch (regimm format)
 207 #define COP0 15   // Coprocessor 0
 208 #define COP1 16   // Coprocessor 1
 209 #define C1LS 17   // Coprocessor 1 load/store
 210 #define FJUMP 18  // Conditional branch (floating point)
 211 #define FLOAT 19  // Floating point unit
 212 #define FCONV 20  // Convert integer to float
 213 #define FCOMP 21  // Floating point compare (sets FSREG)
 214 #define SYSCALL 22// SYSCALL
 215 #define OTHER 23  // Other
 216 #define SPAN 24   // Branch/delay slot spans 2 pages
 217 #define NI 25     // Not implemented
 218 #define HLECALL 26// PCSX fake opcodes for HLE
 219 #define COP2 27   // Coprocessor 2 move
 220 #define C2LS 28   // Coprocessor 2 load/store
 221 #define C2OP 29   // Coprocessor 2 operation
 222 #define INTCALL 30// Call interpreter to handle rare corner cases
 223
 224   /* stubs */
 225 #define CC_STUB 1
 226 #define FP_STUB 2
 227 #define LOADB_STUB 3
 228 #define LOADH_STUB 4
 229 #define LOADW_STUB 5
 230 #define LOADD_STUB 6
 231 #define LOADBU_STUB 7
 232 #define LOADHU_STUB 8
 233 #define STOREB_STUB 9
 234 #define STOREH_STUB 10
 235 #define STOREW_STUB 11
 236 #define STORED_STUB 12
 237 #define STORELR_STUB 13
 238 #define INVCODE_STUB 14
 239
 240   /* branch codes */
 241 #define TAKEN 1
 242 #define NOTTAKEN 2
 243 #define NULLDS 3
 244
 245 // asm linkage
 246 int new_recompile_block(int addr);
 247 void *get_addr_ht(u_int vaddr);
 248 void invalidate_block(u_int block);
 249 void invalidate_addr(u_int addr);
 250 void remove_hash(int vaddr);
 251 void jump_vaddr();
 252 void dyna_linker();
 253 void dyna_linker_ds();
 254 void verify_code();
 255 void verify_code_vm();
 256 void verify_code_ds();
 257 void cc_interrupt();
 258 void fp_exception();
 259 void fp_exception_ds();
 260 void jump_syscall();
 261 void jump_syscall_hle();
 262 void jump_eret();
 263 void jump_hlecall();
 264 void jump_intcall();
 265 void new_dyna_leave();
 266
 267 // TLB
 268 void TLBWI_new();
 269 void TLBWR_new();
 270 void read_nomem_new();
 271 void read_nomemb_new();
 272 void read_nomemh_new();
 273 void read_nomemd_new();
 274 void write_nomem_new();
 275 void write_nomemb_new();
 276 void write_nomemh_new();
 277 void write_nomemd_new();
 278 void write_rdram_new();
 279 void write_rdramb_new();
 280 void write_rdramh_new();
 281 void write_rdramd_new();
 282 extern u_int memory_map[1048576];
 283
 284 // Needed by assembler
 285 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
 286 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
 287 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
 288 void load_all_regs(signed char i_regmap[]);
 289 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
 290 void load_regs_entry(int t);
 291 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
 292
 293 int tracedebug=0;
 294
 295 //#define DEBUG_CYCLE_COUNT 1
 296
 297 #define NO_CYCLE_PENALTY_THR 12
 298
 299 int cycle_multiplier; // 100 for 1.0
 300
 301 static int CLOCK_ADJUST(int x)
 302 {
 303   int s=(x>>31)|1;
 304   return (x * cycle_multiplier + s * 50) / 100;
 305 }
 306
 307 static void tlb_hacks()
 308 {
 309 #ifndef DISABLE_TLB
 310   // Goldeneye hack
 311   if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
 312   {
 313     u_int addr;
 314     int n;
 315     switch (ROM_HEADER->Country_code&0xFF)
 316     {
 317       case 0x45: // U
 318         addr=0x34b30;
 319         break;
 320       case 0x4A: // J
 321         addr=0x34b70;
 322         break;
 323       case 0x50: // E
 324         addr=0x329f0;
 325         break;
 326       default:
 327         // Unknown country code
 328         addr=0;
 329         break;
 330     }
 331     u_int rom_addr=(u_int)rom;
 332     #ifdef ROM_COPY
 333     // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
 334     // in the lower 4G of memory to use this hack.  Copy it if necessary.
 335     if((void *)rom>(void *)0xffffffff) {
 336       munmap(ROM_COPY, 67108864);
 337       if(mmap(ROM_COPY, 12582912,
 338               PROT_READ | PROT_WRITE,
 339               MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
 340               -1, 0) <= 0) {printf("mmap() failed\n");}
 341       memcpy(ROM_COPY,rom,12582912);
 342       rom_addr=(u_int)ROM_COPY;
 343     }
 344     #endif
 345     if(addr) {
 346       for(n=0x7F000;n<0x80000;n++) {
 347         memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
 348       }
 349     }
 350   }
 351 #endif
 352 }
 353
 354 static u_int get_page(u_int vaddr)
 355 {
 356 #ifndef PCSX
 357   u_int page=(vaddr^0x80000000)>>12;
 358 #else
 359   u_int page=vaddr&~0xe0000000;
 360   if (page < 0x1000000)
 361     page &= ~0x0e00000; // RAM mirrors
 362   page>>=12;
 363 #endif
 364 #ifndef DISABLE_TLB
 365   if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
 366 #endif
 367   if(page>2048) page=2048+(page&2047);
 368   return page;
 369 }
 370
 371 #ifndef PCSX
 372 static u_int get_vpage(u_int vaddr)
 373 {
 374   u_int vpage=(vaddr^0x80000000)>>12;
 375 #ifndef DISABLE_TLB
 376   if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
 377 #endif
 378   if(vpage>2048) vpage=2048+(vpage&2047);
 379   return vpage;
 380 }
 381 #else
 382 // no virtual mem in PCSX
 383 static u_int get_vpage(u_int vaddr)
 384 {
 385   return get_page(vaddr);
 386 }
 387 #endif
 388
 389 // Get address from virtual address
 390 // This is called from the recompiled JR/JALR instructions
 391 void *get_addr(u_int vaddr)
 392 {
 393   u_int page=get_page(vaddr);
 394   u_int vpage=get_vpage(vaddr);
 395   struct ll_entry *head;
 396   //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
 397   head=jump_in[page];
 398   while(head!=NULL) {
 399     if(head->vaddr==vaddr) {
 400   //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 401       int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 402       ht_bin[3]=ht_bin[1];
 403       ht_bin[2]=ht_bin[0];
 404       ht_bin[1]=(int)head->addr;
 405       ht_bin[0]=vaddr;
 406       return head->addr;
 407     }
 408     head=head->next;
 409   }
 410   head=jump_dirty[vpage];
 411   while(head!=NULL) {
 412     if(head->vaddr==vaddr) {
 413       //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 414       // Don't restore blocks which are about to expire from the cache
 415       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 416       if(verify_dirty(head->addr)) {
 417         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
 418         invalid_code[vaddr>>12]=0;
 419         inv_code_start=inv_code_end=~0;
 420 #ifndef DISABLE_TLB
 421         memory_map[vaddr>>12]|=0x40000000;
 422 #endif
 423         if(vpage<2048) {
 424 #ifndef DISABLE_TLB
 425           if(tlb_LUT_r[vaddr>>12]) {
 426             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
 427             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
 428           }
 429 #endif
 430           restore_candidate[vpage>>3]|=1<<(vpage&7);
 431         }
 432         else restore_candidate[page>>3]|=1<<(page&7);
 433         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 434         if(ht_bin[0]==vaddr) {
 435           ht_bin[1]=(int)head->addr; // Replace existing entry
 436         }
 437         else
 438         {
 439           ht_bin[3]=ht_bin[1];
 440           ht_bin[2]=ht_bin[0];
 441           ht_bin[1]=(int)head->addr;
 442           ht_bin[0]=vaddr;
 443         }
 444         return head->addr;
 445       }
 446     }
 447     head=head->next;
 448   }
 449   //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
 450   int r=new_recompile_block(vaddr);
 451   if(r==0) return get_addr(vaddr);
 452   // Execute in unmapped page, generate pagefault execption
 453   Status|=2;
 454   Cause=(vaddr<<31)|0x8;
 455   EPC=(vaddr&1)?vaddr-5:vaddr;
 456   BadVAddr=(vaddr&~1);
 457   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
 458   EntryHi=BadVAddr&0xFFFFE000;
 459   return get_addr_ht(0x80000000);
 460 }
 461 // Look up address in hash table first
 462 void *get_addr_ht(u_int vaddr)
 463 {
 464   //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
 465   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 466   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
 467   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
 468   return get_addr(vaddr);
 469 }
 470
 471 void clear_all_regs(signed char regmap[])
 472 {
 473   int hr;
 474   for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
 475 }
 476
 477 signed char get_reg(signed char regmap[],int r)
 478 {
 479   int hr;
 480   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
 481   return -1;
 482 }
 483
 484 // Find a register that is available for two consecutive cycles
 485 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
 486 {
 487   int hr;
 488   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
 489   return -1;
 490 }
 491
 492 int count_free_regs(signed char regmap[])
 493 {
 494   int count=0;
 495   int hr;
 496   for(hr=0;hr<HOST_REGS;hr++)
 497   {
 498     if(hr!=EXCLUDE_REG) {
 499       if(regmap[hr]<0) count++;
 500     }
 501   }
 502   return count;
 503 }
 504
 505 void dirty_reg(struct regstat *cur,signed char reg)
 506 {
 507   int hr;
 508   if(!reg) return;
 509   for (hr=0;hr<HOST_REGS;hr++) {
 510     if((cur->regmap[hr]&63)==reg) {
 511       cur->dirty|=1<<hr;
 512     }
 513   }
 514 }
 515
 516 // If we dirty the lower half of a 64 bit register which is now being
 517 // sign-extended, we need to dump the upper half.
 518 // Note: Do this only after completion of the instruction, because
 519 // some instructions may need to read the full 64-bit value even if
 520 // overwriting it (eg SLTI, DSRA32).
 521 static void flush_dirty_uppers(struct regstat *cur)
 522 {
 523   int hr,reg;
 524   for (hr=0;hr<HOST_REGS;hr++) {
 525     if((cur->dirty>>hr)&1) {
 526       reg=cur->regmap[hr];
 527       if(reg>=64)
 528         if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
 529     }
 530   }
 531 }
 532
 533 void set_const(struct regstat *cur,signed char reg,uint64_t value)
 534 {
 535   int hr;
 536   if(!reg) return;
 537   for (hr=0;hr<HOST_REGS;hr++) {
 538     if(cur->regmap[hr]==reg) {
 539       cur->isconst|=1<<hr;
 540       current_constmap[hr]=value;
 541     }
 542     else if((cur->regmap[hr]^64)==reg) {
 543       cur->isconst|=1<<hr;
 544       current_constmap[hr]=value>>32;
 545     }
 546   }
 547 }
 548
 549 void clear_const(struct regstat *cur,signed char reg)
 550 {
 551   int hr;
 552   if(!reg) return;
 553   for (hr=0;hr<HOST_REGS;hr++) {
 554     if((cur->regmap[hr]&63)==reg) {
 555       cur->isconst&=~(1<<hr);
 556     }
 557   }
 558 }
 559
 560 int is_const(struct regstat *cur,signed char reg)
 561 {
 562   int hr;
 563   if(reg<0) return 0;
 564   if(!reg) return 1;
 565   for (hr=0;hr<HOST_REGS;hr++) {
 566     if((cur->regmap[hr]&63)==reg) {
 567       return (cur->isconst>>hr)&1;
 568     }
 569   }
 570   return 0;
 571 }
 572 uint64_t get_const(struct regstat *cur,signed char reg)
 573 {
 574   int hr;
 575   if(!reg) return 0;
 576   for (hr=0;hr<HOST_REGS;hr++) {
 577     if(cur->regmap[hr]==reg) {
 578       return current_constmap[hr];
 579     }
 580   }
 581   SysPrintf("Unknown constant in r%d\n",reg);
 582   exit(1);
 583 }
 584
 585 // Least soon needed registers
 586 // Look at the next ten instructions and see which registers
 587 // will be used.  Try not to reallocate these.
 588 void lsn(u_char hsn[], int i, int *preferred_reg)
 589 {
 590   int j;
 591   int b=-1;
 592   for(j=0;j<9;j++)
 593   {
 594     if(i+j>=slen) {
 595       j=slen-i-1;
 596       break;
 597     }
 598     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 599     {
 600       // Don't go past an unconditonal jump
 601       j++;
 602       break;
 603     }
 604   }
 605   for(;j>=0;j--)
 606   {
 607     if(rs1[i+j]) hsn[rs1[i+j]]=j;
 608     if(rs2[i+j]) hsn[rs2[i+j]]=j;
 609     if(rt1[i+j]) hsn[rt1[i+j]]=j;
 610     if(rt2[i+j]) hsn[rt2[i+j]]=j;
 611     if(itype[i+j]==STORE || itype[i+j]==STORELR) {
 612       // Stores can allocate zero
 613       hsn[rs1[i+j]]=j;
 614       hsn[rs2[i+j]]=j;
 615     }
 616     // On some architectures stores need invc_ptr
 617     #if defined(HOST_IMM8)
 618     if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
 619       hsn[INVCP]=j;
 620     }
 621     #endif
 622     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 623     {
 624       hsn[CCREG]=j;
 625       b=j;
 626     }
 627   }
 628   if(b>=0)
 629   {
 630     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 631     {
 632       // Follow first branch
 633       int t=(ba[i+b]-start)>>2;
 634       j=7-b;if(t+j>=slen) j=slen-t-1;
 635       for(;j>=0;j--)
 636       {
 637         if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
 638         if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
 639         //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
 640         //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
 641       }
 642     }
 643     // TODO: preferred register based on backward branch
 644   }
 645   // Delay slot should preferably not overwrite branch conditions or cycle count
 646   if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
 647     if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
 648     if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
 649     hsn[CCREG]=1;
 650     // ...or hash tables
 651     hsn[RHASH]=1;
 652     hsn[RHTBL]=1;
 653   }
 654   // Coprocessor load/store needs FTEMP, even if not declared
 655   if(itype[i]==C1LS||itype[i]==C2LS) {
 656     hsn[FTEMP]=0;
 657   }
 658   // Load L/R also uses FTEMP as a temporary register
 659   if(itype[i]==LOADLR) {
 660     hsn[FTEMP]=0;
 661   }
 662   // Also SWL/SWR/SDL/SDR
 663   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
 664     hsn[FTEMP]=0;
 665   }
 666   // Don't remove the TLB registers either
 667   if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
 668     hsn[TLREG]=0;
 669   }
 670   // Don't remove the miniht registers
 671   if(itype[i]==UJUMP||itype[i]==RJUMP)
 672   {
 673     hsn[RHASH]=0;
 674     hsn[RHTBL]=0;
 675   }
 676 }
 677
 678 // We only want to allocate registers if we're going to use them again soon
 679 int needed_again(int r, int i)
 680 {
 681   int j;
 682   int b=-1;
 683   int rn=10;
 684
 685   if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
 686   {
 687     if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
 688       return 0; // Don't need any registers if exiting the block
 689   }
 690   for(j=0;j<9;j++)
 691   {
 692     if(i+j>=slen) {
 693       j=slen-i-1;
 694       break;
 695     }
 696     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 697     {
 698       // Don't go past an unconditonal jump
 699       j++;
 700       break;
 701     }
 702     if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
 703     {
 704       break;
 705     }
 706   }
 707   for(;j>=1;j--)
 708   {
 709     if(rs1[i+j]==r) rn=j;
 710     if(rs2[i+j]==r) rn=j;
 711     if((unneeded_reg[i+j]>>r)&1) rn=10;
 712     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 713     {
 714       b=j;
 715     }
 716   }
 717   /*
 718   if(b>=0)
 719   {
 720     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 721     {
 722       // Follow first branch
 723       int o=rn;
 724       int t=(ba[i+b]-start)>>2;
 725       j=7-b;if(t+j>=slen) j=slen-t-1;
 726       for(;j>=0;j--)
 727       {
 728         if(!((unneeded_reg[t+j]>>r)&1)) {
 729           if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 730           if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 731         }
 732         else rn=o;
 733       }
 734     }
 735   }*/
 736   if(rn<10) return 1;
 737   return 0;
 738 }
 739
 740 // Try to match register allocations at the end of a loop with those
 741 // at the beginning
 742 int loop_reg(int i, int r, int hr)
 743 {
 744   int j,k;
 745   for(j=0;j<9;j++)
 746   {
 747     if(i+j>=slen) {
 748       j=slen-i-1;
 749       break;
 750     }
 751     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 752     {
 753       // Don't go past an unconditonal jump
 754       j++;
 755       break;
 756     }
 757   }
 758   k=0;
 759   if(i>0){
 760     if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
 761       k--;
 762   }
 763   for(;k<j;k++)
 764   {
 765     if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
 766     if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
 767     if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
 768     {
 769       if(ba[i+k]>=start && ba[i+k]<(start+i*4))
 770       {
 771         int t=(ba[i+k]-start)>>2;
 772         int reg=get_reg(regs[t].regmap_entry,r);
 773         if(reg>=0) return reg;
 774         //reg=get_reg(regs[t+1].regmap_entry,r);
 775         //if(reg>=0) return reg;
 776       }
 777     }
 778   }
 779   return hr;
 780 }
 781
 782
 783 // Allocate every register, preserving source/target regs
 784 void alloc_all(struct regstat *cur,int i)
 785 {
 786   int hr;
 787
 788   for(hr=0;hr<HOST_REGS;hr++) {
 789     if(hr!=EXCLUDE_REG) {
 790       if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
 791          ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
 792       {
 793         cur->regmap[hr]=-1;
 794         cur->dirty&=~(1<<hr);
 795       }
 796       // Don't need zeros
 797       if((cur->regmap[hr]&63)==0)
 798       {
 799         cur->regmap[hr]=-1;
 800         cur->dirty&=~(1<<hr);
 801       }
 802     }
 803   }
 804 }
 805
 806 #ifndef FORCE32
 807 void div64(int64_t dividend,int64_t divisor)
 808 {
 809   lo=dividend/divisor;
 810   hi=dividend%divisor;
 811   //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
 812   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 813 }
 814 void divu64(uint64_t dividend,uint64_t divisor)
 815 {
 816   lo=dividend/divisor;
 817   hi=dividend%divisor;
 818   //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 819   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 820 }
 821
 822 void mult64(uint64_t m1,uint64_t m2)
 823 {
 824    unsigned long long int op1, op2, op3, op4;
 825    unsigned long long int result1, result2, result3, result4;
 826    unsigned long long int temp1, temp2, temp3, temp4;
 827    int sign = 0;
 828
 829    if (m1 < 0)
 830      {
 831     op2 = -m1;
 832     sign = 1 - sign;
 833      }
 834    else op2 = m1;
 835    if (m2 < 0)
 836      {
 837     op4 = -m2;
 838     sign = 1 - sign;
 839      }
 840    else op4 = m2;
 841
 842    op1 = op2 & 0xFFFFFFFF;
 843    op2 = (op2 >> 32) & 0xFFFFFFFF;
 844    op3 = op4 & 0xFFFFFFFF;
 845    op4 = (op4 >> 32) & 0xFFFFFFFF;
 846
 847    temp1 = op1 * op3;
 848    temp2 = (temp1 >> 32) + op1 * op4;
 849    temp3 = op2 * op3;
 850    temp4 = (temp3 >> 32) + op2 * op4;
 851
 852    result1 = temp1 & 0xFFFFFFFF;
 853    result2 = temp2 + (temp3 & 0xFFFFFFFF);
 854    result3 = (result2 >> 32) + temp4;
 855    result4 = (result3 >> 32);
 856
 857    lo = result1 | (result2 << 32);
 858    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
 859    if (sign)
 860      {
 861     hi = ~hi;
 862     if (!lo) hi++;
 863     else lo = ~lo + 1;
 864      }
 865 }
 866
 867 void multu64(uint64_t m1,uint64_t m2)
 868 {
 869    unsigned long long int op1, op2, op3, op4;
 870    unsigned long long int result1, result2, result3, result4;
 871    unsigned long long int temp1, temp2, temp3, temp4;
 872
 873    op1 = m1 & 0xFFFFFFFF;
 874    op2 = (m1 >> 32) & 0xFFFFFFFF;
 875    op3 = m2 & 0xFFFFFFFF;
 876    op4 = (m2 >> 32) & 0xFFFFFFFF;
 877
 878    temp1 = op1 * op3;
 879    temp2 = (temp1 >> 32) + op1 * op4;
 880    temp3 = op2 * op3;
 881    temp4 = (temp3 >> 32) + op2 * op4;
 882
 883    result1 = temp1 & 0xFFFFFFFF;
 884    result2 = temp2 + (temp3 & 0xFFFFFFFF);
 885    result3 = (result2 >> 32) + temp4;
 886    result4 = (result3 >> 32);
 887
 888    lo = result1 | (result2 << 32);
 889    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
 890
 891   //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 892   //                                      ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 893 }
 894
 895 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
 896 {
 897   if(bits) {
 898     original<<=64-bits;
 899     original>>=64-bits;
 900     loaded<<=bits;
 901     original|=loaded;
 902   }
 903   else original=loaded;
 904   return original;
 905 }
 906 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
 907 {
 908   if(bits^56) {
 909     original>>=64-(bits^56);
 910     original<<=64-(bits^56);
 911     loaded>>=bits^56;
 912     original|=loaded;
 913   }
 914   else original=loaded;
 915   return original;
 916 }
 917 #endif
 918
 919 #ifdef __i386__
 920 #include "assem_x86.c"
 921 #endif
 922 #ifdef __x86_64__
 923 #include "assem_x64.c"
 924 #endif
 925 #ifdef __arm__
 926 #include "assem_arm.c"
 927 #endif
 928
 929 // Add virtual address mapping to linked list
 930 void ll_add(struct ll_entry **head,int vaddr,void *addr)
 931 {
 932   struct ll_entry *new_entry;
 933   new_entry=malloc(sizeof(struct ll_entry));
 934   assert(new_entry!=NULL);
 935   new_entry->vaddr=vaddr;
 936   new_entry->reg_sv_flags=0;
 937   new_entry->addr=addr;
 938   new_entry->next=*head;
 939   *head=new_entry;
 940 }
 941
 942 void ll_add_flags(struct ll_entry **head,int vaddr,u_int reg_sv_flags,void *addr)
 943 {
 944   ll_add(head,vaddr,addr);
 945   (*head)->reg_sv_flags=reg_sv_flags;
 946 }
 947
 948 // Check if an address is already compiled
 949 // but don't return addresses which are about to expire from the cache
 950 void *check_addr(u_int vaddr)
 951 {
 952   u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 953   if(ht_bin[0]==vaddr) {
 954     if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 955       if(isclean(ht_bin[1])) return (void *)ht_bin[1];
 956   }
 957   if(ht_bin[2]==vaddr) {
 958     if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 959       if(isclean(ht_bin[3])) return (void *)ht_bin[3];
 960   }
 961   u_int page=get_page(vaddr);
 962   struct ll_entry *head;
 963   head=jump_in[page];
 964   while(head!=NULL) {
 965     if(head->vaddr==vaddr) {
 966       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
 967         // Update existing entry with current address
 968         if(ht_bin[0]==vaddr) {
 969           ht_bin[1]=(int)head->addr;
 970           return head->addr;
 971         }
 972         if(ht_bin[2]==vaddr) {
 973           ht_bin[3]=(int)head->addr;
 974           return head->addr;
 975         }
 976         // Insert into hash table with low priority.
 977         // Don't evict existing entries, as they are probably
 978         // addresses that are being accessed frequently.
 979         if(ht_bin[0]==-1) {
 980           ht_bin[1]=(int)head->addr;
 981           ht_bin[0]=vaddr;
 982         }else if(ht_bin[2]==-1) {
 983           ht_bin[3]=(int)head->addr;
 984           ht_bin[2]=vaddr;
 985         }
 986         return head->addr;
 987       }
 988     }
 989     head=head->next;
 990   }
 991   return 0;
 992 }
 993
 994 void remove_hash(int vaddr)
 995 {
 996   //printf("remove hash: %x\n",vaddr);
 997   int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
 998   if(ht_bin[2]==vaddr) {
 999     ht_bin[2]=ht_bin[3]=-1;
1000   }
1001   if(ht_bin[0]==vaddr) {
1002     ht_bin[0]=ht_bin[2];
1003     ht_bin[1]=ht_bin[3];
1004     ht_bin[2]=ht_bin[3]=-1;
1005   }
1006 }
1007
1008 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1009 {
1010   struct ll_entry *next;
1011   while(*head) {
1012     if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1013        ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1014     {
1015       inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1016       remove_hash((*head)->vaddr);
1017       next=(*head)->next;
1018       free(*head);
1019       *head=next;
1020     }
1021     else
1022     {
1023       head=&((*head)->next);
1024     }
1025   }
1026 }
1027
1028 // Remove all entries from linked list
1029 void ll_clear(struct ll_entry **head)
1030 {
1031   struct ll_entry *cur;
1032   struct ll_entry *next;
1033   if(cur=*head) {
1034     *head=0;
1035     while(cur) {
1036       next=cur->next;
1037       free(cur);
1038       cur=next;
1039     }
1040   }
1041 }
1042
1043 // Dereference the pointers and remove if it matches
1044 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1045 {
1046   while(head) {
1047     int ptr=get_pointer(head->addr);
1048     inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1049     if(((ptr>>shift)==(addr>>shift)) ||
1050        (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1051     {
1052       inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1053       u_int host_addr=(u_int)kill_pointer(head->addr);
1054       #ifdef __arm__
1055         needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1056       #endif
1057     }
1058     head=head->next;
1059   }
1060 }
1061
1062 // This is called when we write to a compiled block (see do_invstub)
1063 void invalidate_page(u_int page)
1064 {
1065   struct ll_entry *head;
1066   struct ll_entry *next;
1067   head=jump_in[page];
1068   jump_in[page]=0;
1069   while(head!=NULL) {
1070     inv_debug("INVALIDATE: %x\n",head->vaddr);
1071     remove_hash(head->vaddr);
1072     next=head->next;
1073     free(head);
1074     head=next;
1075   }
1076   head=jump_out[page];
1077   jump_out[page]=0;
1078   while(head!=NULL) {
1079     inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1080     u_int host_addr=(u_int)kill_pointer(head->addr);
1081     #ifdef __arm__
1082       needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1083     #endif
1084     next=head->next;
1085     free(head);
1086     head=next;
1087   }
1088 }
1089
1090 static void invalidate_block_range(u_int block, u_int first, u_int last)
1091 {
1092   u_int page=get_page(block<<12);
1093   //printf("first=%d last=%d\n",first,last);
1094   invalidate_page(page);
1095   assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1096   assert(last<page+5);
1097   // Invalidate the adjacent pages if a block crosses a 4K boundary
1098   while(first<page) {
1099     invalidate_page(first);
1100     first++;
1101   }
1102   for(first=page+1;first<last;first++) {
1103     invalidate_page(first);
1104   }
1105   #ifdef __arm__
1106     do_clear_cache();
1107   #endif
1108
1109   // Don't trap writes
1110   invalid_code[block]=1;
1111 #ifndef DISABLE_TLB
1112   // If there is a valid TLB entry for this page, remove write protect
1113   if(tlb_LUT_w[block]) {
1114     assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1115     // CHECK: Is this right?
1116     memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1117     u_int real_block=tlb_LUT_w[block]>>12;
1118     invalid_code[real_block]=1;
1119     if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1120   }
1121   else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1122 #endif
1123
1124   #ifdef USE_MINI_HT
1125   memset(mini_ht,-1,sizeof(mini_ht));
1126   #endif
1127 }
1128
1129 void invalidate_block(u_int block)
1130 {
1131   u_int page=get_page(block<<12);
1132   u_int vpage=get_vpage(block<<12);
1133   inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1134   //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1135   u_int first,last;
1136   first=last=page;
1137   struct ll_entry *head;
1138   head=jump_dirty[vpage];
1139   //printf("page=%d vpage=%d\n",page,vpage);
1140   while(head!=NULL) {
1141     u_int start,end;
1142     if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1143       get_bounds((int)head->addr,&start,&end);
1144       //printf("start: %x end: %x\n",start,end);
1145       if(page<2048&&start>=(u_int)rdram&&end<(u_int)rdram+RAM_SIZE) {
1146         if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1147           if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1148           if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1149         }
1150       }
1151 #ifndef DISABLE_TLB
1152       if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1153         if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1154           if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1155           if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1156         }
1157       }
1158 #endif
1159     }
1160     head=head->next;
1161   }
1162   invalidate_block_range(block,first,last);
1163 }
1164
1165 void invalidate_addr(u_int addr)
1166 {
1167 #ifdef PCSX
1168   //static int rhits;
1169   // this check is done by the caller
1170   //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
1171   u_int page=get_vpage(addr);
1172   if(page<2048) { // RAM
1173     struct ll_entry *head;
1174     u_int addr_min=~0, addr_max=0;
1175     u_int mask=RAM_SIZE-1;
1176     u_int addr_main=0x80000000|(addr&mask);
1177     int pg1;
1178     inv_code_start=addr_main&~0xfff;
1179     inv_code_end=addr_main|0xfff;
1180     pg1=page;
1181     if (pg1>0) {
1182       // must check previous page too because of spans..
1183       pg1--;
1184       inv_code_start-=0x1000;
1185     }
1186     for(;pg1<=page;pg1++) {
1187       for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
1188         u_int start,end;
1189         get_bounds((int)head->addr,&start,&end);
1190         if(ram_offset) {
1191           start-=ram_offset;
1192           end-=ram_offset;
1193         }
1194         if(start<=addr_main&&addr_main<end) {
1195           if(start<addr_min) addr_min=start;
1196           if(end>addr_max) addr_max=end;
1197         }
1198         else if(addr_main<start) {
1199           if(start<inv_code_end)
1200             inv_code_end=start-1;
1201         }
1202         else {
1203           if(end>inv_code_start)
1204             inv_code_start=end;
1205         }
1206       }
1207     }
1208     if (addr_min!=~0) {
1209       inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1210       inv_code_start=inv_code_end=~0;
1211       invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1212       return;
1213     }
1214     else {
1215       inv_code_start=(addr&~mask)|(inv_code_start&mask);
1216       inv_code_end=(addr&~mask)|(inv_code_end&mask);
1217       inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);
1218       return;
1219     }
1220   }
1221 #endif
1222   invalidate_block(addr>>12);
1223 }
1224
1225 // This is called when loading a save state.
1226 // Anything could have changed, so invalidate everything.
1227 void invalidate_all_pages()
1228 {
1229   u_int page,n;
1230   for(page=0;page<4096;page++)
1231     invalidate_page(page);
1232   for(page=0;page<1048576;page++)
1233     if(!invalid_code[page]) {
1234       restore_candidate[(page&2047)>>3]|=1<<(page&7);
1235       restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1236     }
1237   #ifdef __arm__
1238   __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1239   #endif
1240   #ifdef USE_MINI_HT
1241   memset(mini_ht,-1,sizeof(mini_ht));
1242   #endif
1243   #ifndef DISABLE_TLB
1244   // TLB
1245   for(page=0;page<0x100000;page++) {
1246     if(tlb_LUT_r[page]) {
1247       memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1248       if(!tlb_LUT_w[page]||!invalid_code[page])
1249         memory_map[page]|=0x40000000; // Write protect
1250     }
1251     else memory_map[page]=-1;
1252     if(page==0x80000) page=0xC0000;
1253   }
1254   tlb_hacks();
1255   #endif
1256 }
1257
1258 // Add an entry to jump_out after making a link
1259 void add_link(u_int vaddr,void *src)
1260 {
1261   u_int page=get_page(vaddr);
1262   inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1263   int *ptr=(int *)(src+4);
1264   assert((*ptr&0x0fff0000)==0x059f0000);
1265   ll_add(jump_out+page,vaddr,src);
1266   //int ptr=get_pointer(src);
1267   //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1268 }
1269
1270 // If a code block was found to be unmodified (bit was set in
1271 // restore_candidate) and it remains unmodified (bit is clear
1272 // in invalid_code) then move the entries for that 4K page from
1273 // the dirty list to the clean list.
1274 void clean_blocks(u_int page)
1275 {
1276   struct ll_entry *head;
1277   inv_debug("INV: clean_blocks page=%d\n",page);
1278   head=jump_dirty[page];
1279   while(head!=NULL) {
1280     if(!invalid_code[head->vaddr>>12]) {
1281       // Don't restore blocks which are about to expire from the cache
1282       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1283         u_int start,end;
1284         if(verify_dirty((int)head->addr)) {
1285           //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1286           u_int i;
1287           u_int inv=0;
1288           get_bounds((int)head->addr,&start,&end);
1289           if(start-(u_int)rdram<RAM_SIZE) {
1290             for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1291               inv|=invalid_code[i];
1292             }
1293           }
1294 #ifndef DISABLE_TLB
1295           if((signed int)head->vaddr>=(signed int)0xC0000000) {
1296             u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1297             //printf("addr=%x start=%x end=%x\n",addr,start,end);
1298             if(addr<start||addr>=end) inv=1;
1299           }
1300 #endif
1301           else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1302             inv=1;
1303           }
1304           if(!inv) {
1305             void * clean_addr=(void *)get_clean_addr((int)head->addr);
1306             if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1307               u_int ppage=page;
1308 #ifndef DISABLE_TLB
1309               if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1310 #endif
1311               inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1312               //printf("page=%x, addr=%x\n",page,head->vaddr);
1313               //assert(head->vaddr>>12==(page|0x80000));
1314               ll_add_flags(jump_in+ppage,head->vaddr,head->reg_sv_flags,clean_addr);
1315               int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1316               if(ht_bin[0]==head->vaddr) {
1317                 ht_bin[1]=(int)clean_addr; // Replace existing entry
1318               }
1319               if(ht_bin[2]==head->vaddr) {
1320                 ht_bin[3]=(int)clean_addr; // Replace existing entry
1321               }
1322             }
1323           }
1324         }
1325       }
1326     }
1327     head=head->next;
1328   }
1329 }
1330
1331
1332 void mov_alloc(struct regstat *current,int i)
1333 {
1334   // Note: Don't need to actually alloc the source registers
1335   if((~current->is32>>rs1[i])&1) {
1336     //alloc_reg64(current,i,rs1[i]);
1337     alloc_reg64(current,i,rt1[i]);
1338     current->is32&=~(1LL<<rt1[i]);
1339   } else {
1340     //alloc_reg(current,i,rs1[i]);
1341     alloc_reg(current,i,rt1[i]);
1342     current->is32|=(1LL<<rt1[i]);
1343   }
1344   clear_const(current,rs1[i]);
1345   clear_const(current,rt1[i]);
1346   dirty_reg(current,rt1[i]);
1347 }
1348
1349 void shiftimm_alloc(struct regstat *current,int i)
1350 {
1351   if(opcode2[i]<=0x3) // SLL/SRL/SRA
1352   {
1353     if(rt1[i]) {
1354       if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1355       else lt1[i]=rs1[i];
1356       alloc_reg(current,i,rt1[i]);
1357       current->is32|=1LL<<rt1[i];
1358       dirty_reg(current,rt1[i]);
1359       if(is_const(current,rs1[i])) {
1360         int v=get_const(current,rs1[i]);
1361         if(opcode2[i]==0x00) set_const(current,rt1[i],v<<imm[i]);
1362         if(opcode2[i]==0x02) set_const(current,rt1[i],(u_int)v>>imm[i]);
1363         if(opcode2[i]==0x03) set_const(current,rt1[i],v>>imm[i]);
1364       }
1365       else clear_const(current,rt1[i]);
1366     }
1367   }
1368   else
1369   {
1370     clear_const(current,rs1[i]);
1371     clear_const(current,rt1[i]);
1372   }
1373
1374   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1375   {
1376     if(rt1[i]) {
1377       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1378       alloc_reg64(current,i,rt1[i]);
1379       current->is32&=~(1LL<<rt1[i]);
1380       dirty_reg(current,rt1[i]);
1381     }
1382   }
1383   if(opcode2[i]==0x3c) // DSLL32
1384   {
1385     if(rt1[i]) {
1386       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1387       alloc_reg64(current,i,rt1[i]);
1388       current->is32&=~(1LL<<rt1[i]);
1389       dirty_reg(current,rt1[i]);
1390     }
1391   }
1392   if(opcode2[i]==0x3e) // DSRL32
1393   {
1394     if(rt1[i]) {
1395       alloc_reg64(current,i,rs1[i]);
1396       if(imm[i]==32) {
1397         alloc_reg64(current,i,rt1[i]);
1398         current->is32&=~(1LL<<rt1[i]);
1399       } else {
1400         alloc_reg(current,i,rt1[i]);
1401         current->is32|=1LL<<rt1[i];
1402       }
1403       dirty_reg(current,rt1[i]);
1404     }
1405   }
1406   if(opcode2[i]==0x3f) // DSRA32
1407   {
1408     if(rt1[i]) {
1409       alloc_reg64(current,i,rs1[i]);
1410       alloc_reg(current,i,rt1[i]);
1411       current->is32|=1LL<<rt1[i];
1412       dirty_reg(current,rt1[i]);
1413     }
1414   }
1415 }
1416
1417 void shift_alloc(struct regstat *current,int i)
1418 {
1419   if(rt1[i]) {
1420     if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1421     {
1422       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1423       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1424       alloc_reg(current,i,rt1[i]);
1425       if(rt1[i]==rs2[i]) {
1426         alloc_reg_temp(current,i,-1);
1427         minimum_free_regs[i]=1;
1428       }
1429       current->is32|=1LL<<rt1[i];
1430     } else { // DSLLV/DSRLV/DSRAV
1431       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1432       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1433       alloc_reg64(current,i,rt1[i]);
1434       current->is32&=~(1LL<<rt1[i]);
1435       if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1436       {
1437         alloc_reg_temp(current,i,-1);
1438         minimum_free_regs[i]=1;
1439       }
1440     }
1441     clear_const(current,rs1[i]);
1442     clear_const(current,rs2[i]);
1443     clear_const(current,rt1[i]);
1444     dirty_reg(current,rt1[i]);
1445   }
1446 }
1447
1448 void alu_alloc(struct regstat *current,int i)
1449 {
1450   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1451     if(rt1[i]) {
1452       if(rs1[i]&&rs2[i]) {
1453         alloc_reg(current,i,rs1[i]);
1454         alloc_reg(current,i,rs2[i]);
1455       }
1456       else {
1457         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1458         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1459       }
1460       alloc_reg(current,i,rt1[i]);
1461     }
1462     current->is32|=1LL<<rt1[i];
1463   }
1464   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1465     if(rt1[i]) {
1466       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1467       {
1468         alloc_reg64(current,i,rs1[i]);
1469         alloc_reg64(current,i,rs2[i]);
1470         alloc_reg(current,i,rt1[i]);
1471       } else {
1472         alloc_reg(current,i,rs1[i]);
1473         alloc_reg(current,i,rs2[i]);
1474         alloc_reg(current,i,rt1[i]);
1475       }
1476     }
1477     current->is32|=1LL<<rt1[i];
1478   }
1479   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1480     if(rt1[i]) {
1481       if(rs1[i]&&rs2[i]) {
1482         alloc_reg(current,i,rs1[i]);
1483         alloc_reg(current,i,rs2[i]);
1484       }
1485       else
1486       {
1487         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1488         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1489       }
1490       alloc_reg(current,i,rt1[i]);
1491       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1492       {
1493         if(!((current->uu>>rt1[i])&1)) {
1494           alloc_reg64(current,i,rt1[i]);
1495         }
1496         if(get_reg(current->regmap,rt1[i]|64)>=0) {
1497           if(rs1[i]&&rs2[i]) {
1498             alloc_reg64(current,i,rs1[i]);
1499             alloc_reg64(current,i,rs2[i]);
1500           }
1501           else
1502           {
1503             // Is is really worth it to keep 64-bit values in registers?
1504             #ifdef NATIVE_64BIT
1505             if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1506             if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1507             #endif
1508           }
1509         }
1510         current->is32&=~(1LL<<rt1[i]);
1511       } else {
1512         current->is32|=1LL<<rt1[i];
1513       }
1514     }
1515   }
1516   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1517     if(rt1[i]) {
1518       if(rs1[i]&&rs2[i]) {
1519         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1520           alloc_reg64(current,i,rs1[i]);
1521           alloc_reg64(current,i,rs2[i]);
1522           alloc_reg64(current,i,rt1[i]);
1523         } else {
1524           alloc_reg(current,i,rs1[i]);
1525           alloc_reg(current,i,rs2[i]);
1526           alloc_reg(current,i,rt1[i]);
1527         }
1528       }
1529       else {
1530         alloc_reg(current,i,rt1[i]);
1531         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1532           // DADD used as move, or zeroing
1533           // If we have a 64-bit source, then make the target 64 bits too
1534           if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1535             if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1536             alloc_reg64(current,i,rt1[i]);
1537           } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1538             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1539             alloc_reg64(current,i,rt1[i]);
1540           }
1541           if(opcode2[i]>=0x2e&&rs2[i]) {
1542             // DSUB used as negation - 64-bit result
1543             // If we have a 32-bit register, extend it to 64 bits
1544             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1545             alloc_reg64(current,i,rt1[i]);
1546           }
1547         }
1548       }
1549       if(rs1[i]&&rs2[i]) {
1550         current->is32&=~(1LL<<rt1[i]);
1551       } else if(rs1[i]) {
1552         current->is32&=~(1LL<<rt1[i]);
1553         if((current->is32>>rs1[i])&1)
1554           current->is32|=1LL<<rt1[i];
1555       } else if(rs2[i]) {
1556         current->is32&=~(1LL<<rt1[i]);
1557         if((current->is32>>rs2[i])&1)
1558           current->is32|=1LL<<rt1[i];
1559       } else {
1560         current->is32|=1LL<<rt1[i];
1561       }
1562     }
1563   }
1564   clear_const(current,rs1[i]);
1565   clear_const(current,rs2[i]);
1566   clear_const(current,rt1[i]);
1567   dirty_reg(current,rt1[i]);
1568 }
1569
1570 void imm16_alloc(struct regstat *current,int i)
1571 {
1572   if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1573   else lt1[i]=rs1[i];
1574   if(rt1[i]) alloc_reg(current,i,rt1[i]);
1575   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1576     current->is32&=~(1LL<<rt1[i]);
1577     if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1578       // TODO: Could preserve the 32-bit flag if the immediate is zero
1579       alloc_reg64(current,i,rt1[i]);
1580       alloc_reg64(current,i,rs1[i]);
1581     }
1582     clear_const(current,rs1[i]);
1583     clear_const(current,rt1[i]);
1584   }
1585   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1586     if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1587     current->is32|=1LL<<rt1[i];
1588     clear_const(current,rs1[i]);
1589     clear_const(current,rt1[i]);
1590   }
1591   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1592     if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1593       if(rs1[i]!=rt1[i]) {
1594         if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1595         alloc_reg64(current,i,rt1[i]);
1596         current->is32&=~(1LL<<rt1[i]);
1597       }
1598     }
1599     else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1600     if(is_const(current,rs1[i])) {
1601       int v=get_const(current,rs1[i]);
1602       if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1603       if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1604       if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1605     }
1606     else clear_const(current,rt1[i]);
1607   }
1608   else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1609     if(is_const(current,rs1[i])) {
1610       int v=get_const(current,rs1[i]);
1611       set_const(current,rt1[i],v+imm[i]);
1612     }
1613     else clear_const(current,rt1[i]);
1614     current->is32|=1LL<<rt1[i];
1615   }
1616   else {
1617     set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1618     current->is32|=1LL<<rt1[i];
1619   }
1620   dirty_reg(current,rt1[i]);
1621 }
1622
1623 void load_alloc(struct regstat *current,int i)
1624 {
1625   clear_const(current,rt1[i]);
1626   //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1627   if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1628   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1629   if(rt1[i]&&!((current->u>>rt1[i])&1)) {
1630     alloc_reg(current,i,rt1[i]);
1631     assert(get_reg(current->regmap,rt1[i])>=0);
1632     if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1633     {
1634       current->is32&=~(1LL<<rt1[i]);
1635       alloc_reg64(current,i,rt1[i]);
1636     }
1637     else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1638     {
1639       current->is32&=~(1LL<<rt1[i]);
1640       alloc_reg64(current,i,rt1[i]);
1641       alloc_all(current,i);
1642       alloc_reg64(current,i,FTEMP);
1643       minimum_free_regs[i]=HOST_REGS;
1644     }
1645     else current->is32|=1LL<<rt1[i];
1646     dirty_reg(current,rt1[i]);
1647     // If using TLB, need a register for pointer to the mapping table
1648     if(using_tlb) alloc_reg(current,i,TLREG);
1649     // LWL/LWR need a temporary register for the old value
1650     if(opcode[i]==0x22||opcode[i]==0x26)
1651     {
1652       alloc_reg(current,i,FTEMP);
1653       alloc_reg_temp(current,i,-1);
1654       minimum_free_regs[i]=1;
1655     }
1656   }
1657   else
1658   {
1659     // Load to r0 or unneeded register (dummy load)
1660     // but we still need a register to calculate the address
1661     if(opcode[i]==0x22||opcode[i]==0x26)
1662     {
1663       alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1664     }
1665     // If using TLB, need a register for pointer to the mapping table
1666     if(using_tlb) alloc_reg(current,i,TLREG);
1667     alloc_reg_temp(current,i,-1);
1668     minimum_free_regs[i]=1;
1669     if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1670     {
1671       alloc_all(current,i);
1672       alloc_reg64(current,i,FTEMP);
1673       minimum_free_regs[i]=HOST_REGS;
1674     }
1675   }
1676 }
1677
1678 void store_alloc(struct regstat *current,int i)
1679 {
1680   clear_const(current,rs2[i]);
1681   if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1682   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1683   alloc_reg(current,i,rs2[i]);
1684   if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1685     alloc_reg64(current,i,rs2[i]);
1686     if(rs2[i]) alloc_reg(current,i,FTEMP);
1687   }
1688   // If using TLB, need a register for pointer to the mapping table
1689   if(using_tlb) alloc_reg(current,i,TLREG);
1690   #if defined(HOST_IMM8)
1691   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1692   else alloc_reg(current,i,INVCP);
1693   #endif
1694   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1695     alloc_reg(current,i,FTEMP);
1696   }
1697   // We need a temporary register for address generation
1698   alloc_reg_temp(current,i,-1);
1699   minimum_free_regs[i]=1;
1700 }
1701
1702 void c1ls_alloc(struct regstat *current,int i)
1703 {
1704   //clear_const(current,rs1[i]); // FIXME
1705   clear_const(current,rt1[i]);
1706   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1707   alloc_reg(current,i,CSREG); // Status
1708   alloc_reg(current,i,FTEMP);
1709   if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1710     alloc_reg64(current,i,FTEMP);
1711   }
1712   // If using TLB, need a register for pointer to the mapping table
1713   if(using_tlb) alloc_reg(current,i,TLREG);
1714   #if defined(HOST_IMM8)
1715   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1716   else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1717     alloc_reg(current,i,INVCP);
1718   #endif
1719   // We need a temporary register for address generation
1720   alloc_reg_temp(current,i,-1);
1721 }
1722
1723 void c2ls_alloc(struct regstat *current,int i)
1724 {
1725   clear_const(current,rt1[i]);
1726   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1727   alloc_reg(current,i,FTEMP);
1728   // If using TLB, need a register for pointer to the mapping table
1729   if(using_tlb) alloc_reg(current,i,TLREG);
1730   #if defined(HOST_IMM8)
1731   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1732   else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1733     alloc_reg(current,i,INVCP);
1734   #endif
1735   // We need a temporary register for address generation
1736   alloc_reg_temp(current,i,-1);
1737   minimum_free_regs[i]=1;
1738 }
1739
1740 #ifndef multdiv_alloc
1741 void multdiv_alloc(struct regstat *current,int i)
1742 {
1743   //  case 0x18: MULT
1744   //  case 0x19: MULTU
1745   //  case 0x1A: DIV
1746   //  case 0x1B: DIVU
1747   //  case 0x1C: DMULT
1748   //  case 0x1D: DMULTU
1749   //  case 0x1E: DDIV
1750   //  case 0x1F: DDIVU
1751   clear_const(current,rs1[i]);
1752   clear_const(current,rs2[i]);
1753   if(rs1[i]&&rs2[i])
1754   {
1755     if((opcode2[i]&4)==0) // 32-bit
1756     {
1757       current->u&=~(1LL<<HIREG);
1758       current->u&=~(1LL<<LOREG);
1759       alloc_reg(current,i,HIREG);
1760       alloc_reg(current,i,LOREG);
1761       alloc_reg(current,i,rs1[i]);
1762       alloc_reg(current,i,rs2[i]);
1763       current->is32|=1LL<<HIREG;
1764       current->is32|=1LL<<LOREG;
1765       dirty_reg(current,HIREG);
1766       dirty_reg(current,LOREG);
1767     }
1768     else // 64-bit
1769     {
1770       current->u&=~(1LL<<HIREG);
1771       current->u&=~(1LL<<LOREG);
1772       current->uu&=~(1LL<<HIREG);
1773       current->uu&=~(1LL<<LOREG);
1774       alloc_reg64(current,i,HIREG);
1775       //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1776       alloc_reg64(current,i,rs1[i]);
1777       alloc_reg64(current,i,rs2[i]);
1778       alloc_all(current,i);
1779       current->is32&=~(1LL<<HIREG);
1780       current->is32&=~(1LL<<LOREG);
1781       dirty_reg(current,HIREG);
1782       dirty_reg(current,LOREG);
1783       minimum_free_regs[i]=HOST_REGS;
1784     }
1785   }
1786   else
1787   {
1788     // Multiply by zero is zero.
1789     // MIPS does not have a divide by zero exception.
1790     // The result is undefined, we return zero.
1791     alloc_reg(current,i,HIREG);
1792     alloc_reg(current,i,LOREG);
1793     current->is32|=1LL<<HIREG;
1794     current->is32|=1LL<<LOREG;
1795     dirty_reg(current,HIREG);
1796     dirty_reg(current,LOREG);
1797   }
1798 }
1799 #endif
1800
1801 void cop0_alloc(struct regstat *current,int i)
1802 {
1803   if(opcode2[i]==0) // MFC0
1804   {
1805     if(rt1[i]) {
1806       clear_const(current,rt1[i]);
1807       alloc_all(current,i);
1808       alloc_reg(current,i,rt1[i]);
1809       current->is32|=1LL<<rt1[i];
1810       dirty_reg(current,rt1[i]);
1811     }
1812   }
1813   else if(opcode2[i]==4) // MTC0
1814   {
1815     if(rs1[i]){
1816       clear_const(current,rs1[i]);
1817       alloc_reg(current,i,rs1[i]);
1818       alloc_all(current,i);
1819     }
1820     else {
1821       alloc_all(current,i); // FIXME: Keep r0
1822       current->u&=~1LL;
1823       alloc_reg(current,i,0);
1824     }
1825   }
1826   else
1827   {
1828     // TLBR/TLBWI/TLBWR/TLBP/ERET
1829     assert(opcode2[i]==0x10);
1830     alloc_all(current,i);
1831   }
1832   minimum_free_regs[i]=HOST_REGS;
1833 }
1834
1835 void cop1_alloc(struct regstat *current,int i)
1836 {
1837   alloc_reg(current,i,CSREG); // Load status
1838   if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1839   {
1840     if(rt1[i]){
1841       clear_const(current,rt1[i]);
1842       if(opcode2[i]==1) {
1843         alloc_reg64(current,i,rt1[i]); // DMFC1
1844         current->is32&=~(1LL<<rt1[i]);
1845       }else{
1846         alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1847         current->is32|=1LL<<rt1[i];
1848       }
1849       dirty_reg(current,rt1[i]);
1850     }
1851     alloc_reg_temp(current,i,-1);
1852   }
1853   else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1854   {
1855     if(rs1[i]){
1856       clear_const(current,rs1[i]);
1857       if(opcode2[i]==5)
1858         alloc_reg64(current,i,rs1[i]); // DMTC1
1859       else
1860         alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1861       alloc_reg_temp(current,i,-1);
1862     }
1863     else {
1864       current->u&=~1LL;
1865       alloc_reg(current,i,0);
1866       alloc_reg_temp(current,i,-1);
1867     }
1868   }
1869   minimum_free_regs[i]=1;
1870 }
1871 void fconv_alloc(struct regstat *current,int i)
1872 {
1873   alloc_reg(current,i,CSREG); // Load status
1874   alloc_reg_temp(current,i,-1);
1875   minimum_free_regs[i]=1;
1876 }
1877 void float_alloc(struct regstat *current,int i)
1878 {
1879   alloc_reg(current,i,CSREG); // Load status
1880   alloc_reg_temp(current,i,-1);
1881   minimum_free_regs[i]=1;
1882 }
1883 void c2op_alloc(struct regstat *current,int i)
1884 {
1885   alloc_reg_temp(current,i,-1);
1886 }
1887 void fcomp_alloc(struct regstat *current,int i)
1888 {
1889   alloc_reg(current,i,CSREG); // Load status
1890   alloc_reg(current,i,FSREG); // Load flags
1891   dirty_reg(current,FSREG); // Flag will be modified
1892   alloc_reg_temp(current,i,-1);
1893   minimum_free_regs[i]=1;
1894 }
1895
1896 void syscall_alloc(struct regstat *current,int i)
1897 {
1898   alloc_cc(current,i);
1899   dirty_reg(current,CCREG);
1900   alloc_all(current,i);
1901   minimum_free_regs[i]=HOST_REGS;
1902   current->isconst=0;
1903 }
1904
1905 void delayslot_alloc(struct regstat *current,int i)
1906 {
1907   switch(itype[i]) {
1908     case UJUMP:
1909     case CJUMP:
1910     case SJUMP:
1911     case RJUMP:
1912     case FJUMP:
1913     case SYSCALL:
1914     case HLECALL:
1915     case SPAN:
1916       assem_debug("jump in the delay slot.  this shouldn't happen.\n");//exit(1);
1917       SysPrintf("Disabled speculative precompilation\n");
1918       stop_after_jal=1;
1919       break;
1920     case IMM16:
1921       imm16_alloc(current,i);
1922       break;
1923     case LOAD:
1924     case LOADLR:
1925       load_alloc(current,i);
1926       break;
1927     case STORE:
1928     case STORELR:
1929       store_alloc(current,i);
1930       break;
1931     case ALU:
1932       alu_alloc(current,i);
1933       break;
1934     case SHIFT:
1935       shift_alloc(current,i);
1936       break;
1937     case MULTDIV:
1938       multdiv_alloc(current,i);
1939       break;
1940     case SHIFTIMM:
1941       shiftimm_alloc(current,i);
1942       break;
1943     case MOV:
1944       mov_alloc(current,i);
1945       break;
1946     case COP0:
1947       cop0_alloc(current,i);
1948       break;
1949     case COP1:
1950     case COP2:
1951       cop1_alloc(current,i);
1952       break;
1953     case C1LS:
1954       c1ls_alloc(current,i);
1955       break;
1956     case C2LS:
1957       c2ls_alloc(current,i);
1958       break;
1959     case FCONV:
1960       fconv_alloc(current,i);
1961       break;
1962     case FLOAT:
1963       float_alloc(current,i);
1964       break;
1965     case FCOMP:
1966       fcomp_alloc(current,i);
1967       break;
1968     case C2OP:
1969       c2op_alloc(current,i);
1970       break;
1971   }
1972 }
1973
1974 // Special case where a branch and delay slot span two pages in virtual memory
1975 static void pagespan_alloc(struct regstat *current,int i)
1976 {
1977   current->isconst=0;
1978   current->wasconst=0;
1979   regs[i].wasconst=0;
1980   minimum_free_regs[i]=HOST_REGS;
1981   alloc_all(current,i);
1982   alloc_cc(current,i);
1983   dirty_reg(current,CCREG);
1984   if(opcode[i]==3) // JAL
1985   {
1986     alloc_reg(current,i,31);
1987     dirty_reg(current,31);
1988   }
1989   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1990   {
1991     alloc_reg(current,i,rs1[i]);
1992     if (rt1[i]!=0) {
1993       alloc_reg(current,i,rt1[i]);
1994       dirty_reg(current,rt1[i]);
1995     }
1996   }
1997   if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1998   {
1999     if(rs1[i]) alloc_reg(current,i,rs1[i]);
2000     if(rs2[i]) alloc_reg(current,i,rs2[i]);
2001     if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
2002     {
2003       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2004       if(rs2[i]) alloc_reg64(current,i,rs2[i]);
2005     }
2006   }
2007   else
2008   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
2009   {
2010     if(rs1[i]) alloc_reg(current,i,rs1[i]);
2011     if(!((current->is32>>rs1[i])&1))
2012     {
2013       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2014     }
2015   }
2016   else
2017   if(opcode[i]==0x11) // BC1
2018   {
2019     alloc_reg(current,i,FSREG);
2020     alloc_reg(current,i,CSREG);
2021   }
2022   //else ...
2023 }
2024
2025 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
2026 {
2027   stubs[stubcount][0]=type;
2028   stubs[stubcount][1]=addr;
2029   stubs[stubcount][2]=retaddr;
2030   stubs[stubcount][3]=a;
2031   stubs[stubcount][4]=b;
2032   stubs[stubcount][5]=c;
2033   stubs[stubcount][6]=d;
2034   stubs[stubcount][7]=e;
2035   stubcount++;
2036 }
2037
2038 // Write out a single register
2039 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2040 {
2041   int hr;
2042   for(hr=0;hr<HOST_REGS;hr++) {
2043     if(hr!=EXCLUDE_REG) {
2044       if((regmap[hr]&63)==r) {
2045         if((dirty>>hr)&1) {
2046           if(regmap[hr]<64) {
2047             emit_storereg(r,hr);
2048 #ifndef FORCE32
2049             if((is32>>regmap[hr])&1) {
2050               emit_sarimm(hr,31,hr);
2051               emit_storereg(r|64,hr);
2052             }
2053 #endif
2054           }else{
2055             emit_storereg(r|64,hr);
2056           }
2057         }
2058       }
2059     }
2060   }
2061 }
2062
2063 int mchecksum()
2064 {
2065   //if(!tracedebug) return 0;
2066   int i;
2067   int sum=0;
2068   for(i=0;i<2097152;i++) {
2069     unsigned int temp=sum;
2070     sum<<=1;
2071     sum|=(~temp)>>31;
2072     sum^=((u_int *)rdram)[i];
2073   }
2074   return sum;
2075 }
2076 int rchecksum()
2077 {
2078   int i;
2079   int sum=0;
2080   for(i=0;i<64;i++)
2081     sum^=((u_int *)reg)[i];
2082   return sum;
2083 }
2084 void rlist()
2085 {
2086   int i;
2087   printf("TRACE: ");
2088   for(i=0;i<32;i++)
2089     printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2090   printf("\n");
2091 #ifndef DISABLE_COP1
2092   printf("TRACE: ");
2093   for(i=0;i<32;i++)
2094     printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2095   printf("\n");
2096 #endif
2097 }
2098
2099 void enabletrace()
2100 {
2101   tracedebug=1;
2102 }
2103
2104 void memdebug(int i)
2105 {
2106   //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2107   //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2108   //rlist();
2109   //if(tracedebug) {
2110   //if(Count>=-2084597794) {
2111   if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2112   //if(0) {
2113     printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2114     //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2115     //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2116     rlist();
2117     #ifdef __i386__
2118     printf("TRACE: %x\n",(&i)[-1]);
2119     #endif
2120     #ifdef __arm__
2121     int j;
2122     printf("TRACE: %x \n",(&j)[10]);
2123     printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2124     #endif
2125     //fflush(stdout);
2126   }
2127   //printf("TRACE: %x\n",(&i)[-1]);
2128 }
2129
2130 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2131 {
2132   printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2133 }
2134
2135 void alu_assemble(int i,struct regstat *i_regs)
2136 {
2137   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2138     if(rt1[i]) {
2139       signed char s1,s2,t;
2140       t=get_reg(i_regs->regmap,rt1[i]);
2141       if(t>=0) {
2142         s1=get_reg(i_regs->regmap,rs1[i]);
2143         s2=get_reg(i_regs->regmap,rs2[i]);
2144         if(rs1[i]&&rs2[i]) {
2145           assert(s1>=0);
2146           assert(s2>=0);
2147           if(opcode2[i]&2) emit_sub(s1,s2,t);
2148           else emit_add(s1,s2,t);
2149         }
2150         else if(rs1[i]) {
2151           if(s1>=0) emit_mov(s1,t);
2152           else emit_loadreg(rs1[i],t);
2153         }
2154         else if(rs2[i]) {
2155           if(s2>=0) {
2156             if(opcode2[i]&2) emit_neg(s2,t);
2157             else emit_mov(s2,t);
2158           }
2159           else {
2160             emit_loadreg(rs2[i],t);
2161             if(opcode2[i]&2) emit_neg(t,t);
2162           }
2163         }
2164         else emit_zeroreg(t);
2165       }
2166     }
2167   }
2168   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2169     if(rt1[i]) {
2170       signed char s1l,s2l,s1h,s2h,tl,th;
2171       tl=get_reg(i_regs->regmap,rt1[i]);
2172       th=get_reg(i_regs->regmap,rt1[i]|64);
2173       if(tl>=0) {
2174         s1l=get_reg(i_regs->regmap,rs1[i]);
2175         s2l=get_reg(i_regs->regmap,rs2[i]);
2176         s1h=get_reg(i_regs->regmap,rs1[i]|64);
2177         s2h=get_reg(i_regs->regmap,rs2[i]|64);
2178         if(rs1[i]&&rs2[i]) {
2179           assert(s1l>=0);
2180           assert(s2l>=0);
2181           if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2182           else emit_adds(s1l,s2l,tl);
2183           if(th>=0) {
2184             #ifdef INVERTED_CARRY
2185             if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2186             #else
2187             if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2188             #endif
2189             else emit_add(s1h,s2h,th);
2190           }
2191         }
2192         else if(rs1[i]) {
2193           if(s1l>=0) emit_mov(s1l,tl);
2194           else emit_loadreg(rs1[i],tl);
2195           if(th>=0) {
2196             if(s1h>=0) emit_mov(s1h,th);
2197             else emit_loadreg(rs1[i]|64,th);
2198           }
2199         }
2200         else if(rs2[i]) {
2201           if(s2l>=0) {
2202             if(opcode2[i]&2) emit_negs(s2l,tl);
2203             else emit_mov(s2l,tl);
2204           }
2205           else {
2206             emit_loadreg(rs2[i],tl);
2207             if(opcode2[i]&2) emit_negs(tl,tl);
2208           }
2209           if(th>=0) {
2210             #ifdef INVERTED_CARRY
2211             if(s2h>=0) emit_mov(s2h,th);
2212             else emit_loadreg(rs2[i]|64,th);
2213             if(opcode2[i]&2) {
2214               emit_adcimm(-1,th); // x86 has inverted carry flag
2215               emit_not(th,th);
2216             }
2217             #else
2218             if(opcode2[i]&2) {
2219               if(s2h>=0) emit_rscimm(s2h,0,th);
2220               else {
2221                 emit_loadreg(rs2[i]|64,th);
2222                 emit_rscimm(th,0,th);
2223               }
2224             }else{
2225               if(s2h>=0) emit_mov(s2h,th);
2226               else emit_loadreg(rs2[i]|64,th);
2227             }
2228             #endif
2229           }
2230         }
2231         else {
2232           emit_zeroreg(tl);
2233           if(th>=0) emit_zeroreg(th);
2234         }
2235       }
2236     }
2237   }
2238   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2239     if(rt1[i]) {
2240       signed char s1l,s1h,s2l,s2h,t;
2241       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2242       {
2243         t=get_reg(i_regs->regmap,rt1[i]);
2244         //assert(t>=0);
2245         if(t>=0) {
2246           s1l=get_reg(i_regs->regmap,rs1[i]);
2247           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2248           s2l=get_reg(i_regs->regmap,rs2[i]);
2249           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2250           if(rs2[i]==0) // rx<r0
2251           {
2252             assert(s1h>=0);
2253             if(opcode2[i]==0x2a) // SLT
2254               emit_shrimm(s1h,31,t);
2255             else // SLTU (unsigned can not be less than zero)
2256               emit_zeroreg(t);
2257           }
2258           else if(rs1[i]==0) // r0<rx
2259           {
2260             assert(s2h>=0);
2261             if(opcode2[i]==0x2a) // SLT
2262               emit_set_gz64_32(s2h,s2l,t);
2263             else // SLTU (set if not zero)
2264               emit_set_nz64_32(s2h,s2l,t);
2265           }
2266           else {
2267             assert(s1l>=0);assert(s1h>=0);
2268             assert(s2l>=0);assert(s2h>=0);
2269             if(opcode2[i]==0x2a) // SLT
2270               emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2271             else // SLTU
2272               emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2273           }
2274         }
2275       } else {
2276         t=get_reg(i_regs->regmap,rt1[i]);
2277         //assert(t>=0);
2278         if(t>=0) {
2279           s1l=get_reg(i_regs->regmap,rs1[i]);
2280           s2l=get_reg(i_regs->regmap,rs2[i]);
2281           if(rs2[i]==0) // rx<r0
2282           {
2283             assert(s1l>=0);
2284             if(opcode2[i]==0x2a) // SLT
2285               emit_shrimm(s1l,31,t);
2286             else // SLTU (unsigned can not be less than zero)
2287               emit_zeroreg(t);
2288           }
2289           else if(rs1[i]==0) // r0<rx
2290           {
2291             assert(s2l>=0);
2292             if(opcode2[i]==0x2a) // SLT
2293               emit_set_gz32(s2l,t);
2294             else // SLTU (set if not zero)
2295               emit_set_nz32(s2l,t);
2296           }
2297           else{
2298             assert(s1l>=0);assert(s2l>=0);
2299             if(opcode2[i]==0x2a) // SLT
2300               emit_set_if_less32(s1l,s2l,t);
2301             else // SLTU
2302               emit_set_if_carry32(s1l,s2l,t);
2303           }
2304         }
2305       }
2306     }
2307   }
2308   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2309     if(rt1[i]) {
2310       signed char s1l,s1h,s2l,s2h,th,tl;
2311       tl=get_reg(i_regs->regmap,rt1[i]);
2312       th=get_reg(i_regs->regmap,rt1[i]|64);
2313       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2314       {
2315         assert(tl>=0);
2316         if(tl>=0) {
2317           s1l=get_reg(i_regs->regmap,rs1[i]);
2318           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2319           s2l=get_reg(i_regs->regmap,rs2[i]);
2320           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2321           if(rs1[i]&&rs2[i]) {
2322             assert(s1l>=0);assert(s1h>=0);
2323             assert(s2l>=0);assert(s2h>=0);
2324             if(opcode2[i]==0x24) { // AND
2325               emit_and(s1l,s2l,tl);
2326               emit_and(s1h,s2h,th);
2327             } else
2328             if(opcode2[i]==0x25) { // OR
2329               emit_or(s1l,s2l,tl);
2330               emit_or(s1h,s2h,th);
2331             } else
2332             if(opcode2[i]==0x26) { // XOR
2333               emit_xor(s1l,s2l,tl);
2334               emit_xor(s1h,s2h,th);
2335             } else
2336             if(opcode2[i]==0x27) { // NOR
2337               emit_or(s1l,s2l,tl);
2338               emit_or(s1h,s2h,th);
2339               emit_not(tl,tl);
2340               emit_not(th,th);
2341             }
2342           }
2343           else
2344           {
2345             if(opcode2[i]==0x24) { // AND
2346               emit_zeroreg(tl);
2347               emit_zeroreg(th);
2348             } else
2349             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2350               if(rs1[i]){
2351                 if(s1l>=0) emit_mov(s1l,tl);
2352                 else emit_loadreg(rs1[i],tl);
2353                 if(s1h>=0) emit_mov(s1h,th);
2354                 else emit_loadreg(rs1[i]|64,th);
2355               }
2356               else
2357               if(rs2[i]){
2358                 if(s2l>=0) emit_mov(s2l,tl);
2359                 else emit_loadreg(rs2[i],tl);
2360                 if(s2h>=0) emit_mov(s2h,th);
2361                 else emit_loadreg(rs2[i]|64,th);
2362               }
2363               else{
2364                 emit_zeroreg(tl);
2365                 emit_zeroreg(th);
2366               }
2367             } else
2368             if(opcode2[i]==0x27) { // NOR
2369               if(rs1[i]){
2370                 if(s1l>=0) emit_not(s1l,tl);
2371                 else{
2372                   emit_loadreg(rs1[i],tl);
2373                   emit_not(tl,tl);
2374                 }
2375                 if(s1h>=0) emit_not(s1h,th);
2376                 else{
2377                   emit_loadreg(rs1[i]|64,th);
2378                   emit_not(th,th);
2379                 }
2380               }
2381               else
2382               if(rs2[i]){
2383                 if(s2l>=0) emit_not(s2l,tl);
2384                 else{
2385                   emit_loadreg(rs2[i],tl);
2386                   emit_not(tl,tl);
2387                 }
2388                 if(s2h>=0) emit_not(s2h,th);
2389                 else{
2390                   emit_loadreg(rs2[i]|64,th);
2391                   emit_not(th,th);
2392                 }
2393               }
2394               else {
2395                 emit_movimm(-1,tl);
2396                 emit_movimm(-1,th);
2397               }
2398             }
2399           }
2400         }
2401       }
2402       else
2403       {
2404         // 32 bit
2405         if(tl>=0) {
2406           s1l=get_reg(i_regs->regmap,rs1[i]);
2407           s2l=get_reg(i_regs->regmap,rs2[i]);
2408           if(rs1[i]&&rs2[i]) {
2409             assert(s1l>=0);
2410             assert(s2l>=0);
2411             if(opcode2[i]==0x24) { // AND
2412               emit_and(s1l,s2l,tl);
2413             } else
2414             if(opcode2[i]==0x25) { // OR
2415               emit_or(s1l,s2l,tl);
2416             } else
2417             if(opcode2[i]==0x26) { // XOR
2418               emit_xor(s1l,s2l,tl);
2419             } else
2420             if(opcode2[i]==0x27) { // NOR
2421               emit_or(s1l,s2l,tl);
2422               emit_not(tl,tl);
2423             }
2424           }
2425           else
2426           {
2427             if(opcode2[i]==0x24) { // AND
2428               emit_zeroreg(tl);
2429             } else
2430             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2431               if(rs1[i]){
2432                 if(s1l>=0) emit_mov(s1l,tl);
2433                 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2434               }
2435               else
2436               if(rs2[i]){
2437                 if(s2l>=0) emit_mov(s2l,tl);
2438                 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2439               }
2440               else emit_zeroreg(tl);
2441             } else
2442             if(opcode2[i]==0x27) { // NOR
2443               if(rs1[i]){
2444                 if(s1l>=0) emit_not(s1l,tl);
2445                 else {
2446                   emit_loadreg(rs1[i],tl);
2447                   emit_not(tl,tl);
2448                 }
2449               }
2450               else
2451               if(rs2[i]){
2452                 if(s2l>=0) emit_not(s2l,tl);
2453                 else {
2454                   emit_loadreg(rs2[i],tl);
2455                   emit_not(tl,tl);
2456                 }
2457               }
2458               else emit_movimm(-1,tl);
2459             }
2460           }
2461         }
2462       }
2463     }
2464   }
2465 }
2466
2467 void imm16_assemble(int i,struct regstat *i_regs)
2468 {
2469   if (opcode[i]==0x0f) { // LUI
2470     if(rt1[i]) {
2471       signed char t;
2472       t=get_reg(i_regs->regmap,rt1[i]);
2473       //assert(t>=0);
2474       if(t>=0) {
2475         if(!((i_regs->isconst>>t)&1))
2476           emit_movimm(imm[i]<<16,t);
2477       }
2478     }
2479   }
2480   if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2481     if(rt1[i]) {
2482       signed char s,t;
2483       t=get_reg(i_regs->regmap,rt1[i]);
2484       s=get_reg(i_regs->regmap,rs1[i]);
2485       if(rs1[i]) {
2486         //assert(t>=0);
2487         //assert(s>=0);
2488         if(t>=0) {
2489           if(!((i_regs->isconst>>t)&1)) {
2490             if(s<0) {
2491               if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2492               emit_addimm(t,imm[i],t);
2493             }else{
2494               if(!((i_regs->wasconst>>s)&1))
2495                 emit_addimm(s,imm[i],t);
2496               else
2497                 emit_movimm(constmap[i][s]+imm[i],t);
2498             }
2499           }
2500         }
2501       } else {
2502         if(t>=0) {
2503           if(!((i_regs->isconst>>t)&1))
2504             emit_movimm(imm[i],t);
2505         }
2506       }
2507     }
2508   }
2509   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2510     if(rt1[i]) {
2511       signed char sh,sl,th,tl;
2512       th=get_reg(i_regs->regmap,rt1[i]|64);
2513       tl=get_reg(i_regs->regmap,rt1[i]);
2514       sh=get_reg(i_regs->regmap,rs1[i]|64);
2515       sl=get_reg(i_regs->regmap,rs1[i]);
2516       if(tl>=0) {
2517         if(rs1[i]) {
2518           assert(sh>=0);
2519           assert(sl>=0);
2520           if(th>=0) {
2521             emit_addimm64_32(sh,sl,imm[i],th,tl);
2522           }
2523           else {
2524             emit_addimm(sl,imm[i],tl);
2525           }
2526         } else {
2527           emit_movimm(imm[i],tl);
2528           if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2529         }
2530       }
2531     }
2532   }
2533   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2534     if(rt1[i]) {
2535       //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2536       signed char sh,sl,t;
2537       t=get_reg(i_regs->regmap,rt1[i]);
2538       sh=get_reg(i_regs->regmap,rs1[i]|64);
2539       sl=get_reg(i_regs->regmap,rs1[i]);
2540       //assert(t>=0);
2541       if(t>=0) {
2542         if(rs1[i]>0) {
2543           if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2544           if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2545             if(opcode[i]==0x0a) { // SLTI
2546               if(sl<0) {
2547                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2548                 emit_slti32(t,imm[i],t);
2549               }else{
2550                 emit_slti32(sl,imm[i],t);
2551               }
2552             }
2553             else { // SLTIU
2554               if(sl<0) {
2555                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2556                 emit_sltiu32(t,imm[i],t);
2557               }else{
2558                 emit_sltiu32(sl,imm[i],t);
2559               }
2560             }
2561           }else{ // 64-bit
2562             assert(sl>=0);
2563             if(opcode[i]==0x0a) // SLTI
2564               emit_slti64_32(sh,sl,imm[i],t);
2565             else // SLTIU
2566               emit_sltiu64_32(sh,sl,imm[i],t);
2567           }
2568         }else{
2569           // SLTI(U) with r0 is just stupid,
2570           // nonetheless examples can be found
2571           if(opcode[i]==0x0a) // SLTI
2572             if(0<imm[i]) emit_movimm(1,t);
2573             else emit_zeroreg(t);
2574           else // SLTIU
2575           {
2576             if(imm[i]) emit_movimm(1,t);
2577             else emit_zeroreg(t);
2578           }
2579         }
2580       }
2581     }
2582   }
2583   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2584     if(rt1[i]) {
2585       signed char sh,sl,th,tl;
2586       th=get_reg(i_regs->regmap,rt1[i]|64);
2587       tl=get_reg(i_regs->regmap,rt1[i]);
2588       sh=get_reg(i_regs->regmap,rs1[i]|64);
2589       sl=get_reg(i_regs->regmap,rs1[i]);
2590       if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2591         if(opcode[i]==0x0c) //ANDI
2592         {
2593           if(rs1[i]) {
2594             if(sl<0) {
2595               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2596               emit_andimm(tl,imm[i],tl);
2597             }else{
2598               if(!((i_regs->wasconst>>sl)&1))
2599                 emit_andimm(sl,imm[i],tl);
2600               else
2601                 emit_movimm(constmap[i][sl]&imm[i],tl);
2602             }
2603           }
2604           else
2605             emit_zeroreg(tl);
2606           if(th>=0) emit_zeroreg(th);
2607         }
2608         else
2609         {
2610           if(rs1[i]) {
2611             if(sl<0) {
2612               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2613             }
2614             if(th>=0) {
2615               if(sh<0) {
2616                 emit_loadreg(rs1[i]|64,th);
2617               }else{
2618                 emit_mov(sh,th);
2619               }
2620             }
2621             if(opcode[i]==0x0d) //ORI
2622             if(sl<0) {
2623               emit_orimm(tl,imm[i],tl);
2624             }else{
2625               if(!((i_regs->wasconst>>sl)&1))
2626                 emit_orimm(sl,imm[i],tl);
2627               else
2628                 emit_movimm(constmap[i][sl]|imm[i],tl);
2629             }
2630             if(opcode[i]==0x0e) //XORI
2631             if(sl<0) {
2632               emit_xorimm(tl,imm[i],tl);
2633             }else{
2634               if(!((i_regs->wasconst>>sl)&1))
2635                 emit_xorimm(sl,imm[i],tl);
2636               else
2637                 emit_movimm(constmap[i][sl]^imm[i],tl);
2638             }
2639           }
2640           else {
2641             emit_movimm(imm[i],tl);
2642             if(th>=0) emit_zeroreg(th);
2643           }
2644         }
2645       }
2646     }
2647   }
2648 }
2649
2650 void shiftimm_assemble(int i,struct regstat *i_regs)
2651 {
2652   if(opcode2[i]<=0x3) // SLL/SRL/SRA
2653   {
2654     if(rt1[i]) {
2655       signed char s,t;
2656       t=get_reg(i_regs->regmap,rt1[i]);
2657       s=get_reg(i_regs->regmap,rs1[i]);
2658       //assert(t>=0);
2659       if(t>=0&&!((i_regs->isconst>>t)&1)){
2660         if(rs1[i]==0)
2661         {
2662           emit_zeroreg(t);
2663         }
2664         else
2665         {
2666           if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2667           if(imm[i]) {
2668             if(opcode2[i]==0) // SLL
2669             {
2670               emit_shlimm(s<0?t:s,imm[i],t);
2671             }
2672             if(opcode2[i]==2) // SRL
2673             {
2674               emit_shrimm(s<0?t:s,imm[i],t);
2675             }
2676             if(opcode2[i]==3) // SRA
2677             {
2678               emit_sarimm(s<0?t:s,imm[i],t);
2679             }
2680           }else{
2681             // Shift by zero
2682             if(s>=0 && s!=t) emit_mov(s,t);
2683           }
2684         }
2685       }
2686       //emit_storereg(rt1[i],t); //DEBUG
2687     }
2688   }
2689   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2690   {
2691     if(rt1[i]) {
2692       signed char sh,sl,th,tl;
2693       th=get_reg(i_regs->regmap,rt1[i]|64);
2694       tl=get_reg(i_regs->regmap,rt1[i]);
2695       sh=get_reg(i_regs->regmap,rs1[i]|64);
2696       sl=get_reg(i_regs->regmap,rs1[i]);
2697       if(tl>=0) {
2698         if(rs1[i]==0)
2699         {
2700           emit_zeroreg(tl);
2701           if(th>=0) emit_zeroreg(th);
2702         }
2703         else
2704         {
2705           assert(sl>=0);
2706           assert(sh>=0);
2707           if(imm[i]) {
2708             if(opcode2[i]==0x38) // DSLL
2709             {
2710               if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2711               emit_shlimm(sl,imm[i],tl);
2712             }
2713             if(opcode2[i]==0x3a) // DSRL
2714             {
2715               emit_shrdimm(sl,sh,imm[i],tl);
2716               if(th>=0) emit_shrimm(sh,imm[i],th);
2717             }
2718             if(opcode2[i]==0x3b) // DSRA
2719             {
2720               emit_shrdimm(sl,sh,imm[i],tl);
2721               if(th>=0) emit_sarimm(sh,imm[i],th);
2722             }
2723           }else{
2724             // Shift by zero
2725             if(sl!=tl) emit_mov(sl,tl);
2726             if(th>=0&&sh!=th) emit_mov(sh,th);
2727           }
2728         }
2729       }
2730     }
2731   }
2732   if(opcode2[i]==0x3c) // DSLL32
2733   {
2734     if(rt1[i]) {
2735       signed char sl,tl,th;
2736       tl=get_reg(i_regs->regmap,rt1[i]);
2737       th=get_reg(i_regs->regmap,rt1[i]|64);
2738       sl=get_reg(i_regs->regmap,rs1[i]);
2739       if(th>=0||tl>=0){
2740         assert(tl>=0);
2741         assert(th>=0);
2742         assert(sl>=0);
2743         emit_mov(sl,th);
2744         emit_zeroreg(tl);
2745         if(imm[i]>32)
2746         {
2747           emit_shlimm(th,imm[i]&31,th);
2748         }
2749       }
2750     }
2751   }
2752   if(opcode2[i]==0x3e) // DSRL32
2753   {
2754     if(rt1[i]) {
2755       signed char sh,tl,th;
2756       tl=get_reg(i_regs->regmap,rt1[i]);
2757       th=get_reg(i_regs->regmap,rt1[i]|64);
2758       sh=get_reg(i_regs->regmap,rs1[i]|64);
2759       if(tl>=0){
2760         assert(sh>=0);
2761         emit_mov(sh,tl);
2762         if(th>=0) emit_zeroreg(th);
2763         if(imm[i]>32)
2764         {
2765           emit_shrimm(tl,imm[i]&31,tl);
2766         }
2767       }
2768     }
2769   }
2770   if(opcode2[i]==0x3f) // DSRA32
2771   {
2772     if(rt1[i]) {
2773       signed char sh,tl;
2774       tl=get_reg(i_regs->regmap,rt1[i]);
2775       sh=get_reg(i_regs->regmap,rs1[i]|64);
2776       if(tl>=0){
2777         assert(sh>=0);
2778         emit_mov(sh,tl);
2779         if(imm[i]>32)
2780         {
2781           emit_sarimm(tl,imm[i]&31,tl);
2782         }
2783       }
2784     }
2785   }
2786 }
2787
2788 #ifndef shift_assemble
2789 void shift_assemble(int i,struct regstat *i_regs)
2790 {
2791   printf("Need shift_assemble for this architecture.\n");
2792   exit(1);
2793 }
2794 #endif
2795
2796 void load_assemble(int i,struct regstat *i_regs)
2797 {
2798   int s,th,tl,addr,map=-1;
2799   int offset;
2800   int jaddr=0;
2801   int memtarget=0,c=0;
2802   int fastload_reg_override=0;
2803   u_int hr,reglist=0;
2804   th=get_reg(i_regs->regmap,rt1[i]|64);
2805   tl=get_reg(i_regs->regmap,rt1[i]);
2806   s=get_reg(i_regs->regmap,rs1[i]);
2807   offset=imm[i];
2808   for(hr=0;hr<HOST_REGS;hr++) {
2809     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2810   }
2811   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2812   if(s>=0) {
2813     c=(i_regs->wasconst>>s)&1;
2814     if (c) {
2815       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2816       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2817     }
2818   }
2819   //printf("load_assemble: c=%d\n",c);
2820   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2821   // FIXME: Even if the load is a NOP, we should check for pagefaults...
2822 #ifdef PCSX
2823   if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2824     ||rt1[i]==0) {
2825       // could be FIFO, must perform the read
2826       // ||dummy read
2827       assem_debug("(forced read)\n");
2828       tl=get_reg(i_regs->regmap,-1);
2829       assert(tl>=0);
2830   }
2831 #endif
2832   if(offset||s<0||c) addr=tl;
2833   else addr=s;
2834   //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2835  if(tl>=0) {
2836   //printf("load_assemble: c=%d\n",c);
2837   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2838   assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2839   reglist&=~(1<<tl);
2840   if(th>=0) reglist&=~(1<<th);
2841   if(!using_tlb) {
2842     if(!c) {
2843       #ifdef RAM_OFFSET
2844       map=get_reg(i_regs->regmap,ROREG);
2845       if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2846       #endif
2847 //#define R29_HACK 1
2848       #ifdef R29_HACK
2849       // Strmnnrmn's speed hack
2850       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2851       #endif
2852       {
2853         jaddr=emit_fastpath_cmp_jump(i,addr,&fastload_reg_override);
2854       }
2855     }
2856     else if(ram_offset&&memtarget) {
2857       emit_addimm(addr,ram_offset,HOST_TEMPREG);
2858       fastload_reg_override=HOST_TEMPREG;
2859     }
2860   }else{ // using tlb
2861     int x=0;
2862     if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2863     if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2864     map=get_reg(i_regs->regmap,TLREG);
2865     assert(map>=0);
2866     reglist&=~(1<<map);
2867     map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2868     do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2869   }
2870   int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2871   if (opcode[i]==0x20) { // LB
2872     if(!c||memtarget) {
2873       if(!dummy) {
2874         #ifdef HOST_IMM_ADDR32
2875         if(c)
2876           emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2877         else
2878         #endif
2879         {
2880           //emit_xorimm(addr,3,tl);
2881           //gen_tlb_addr_r(tl,map);
2882           //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2883           int x=0,a=tl;
2884 #ifdef BIG_ENDIAN_MIPS
2885           if(!c) emit_xorimm(addr,3,tl);
2886           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2887 #else
2888           if(!c) a=addr;
2889 #endif
2890           if(fastload_reg_override) a=fastload_reg_override;
2891
2892           emit_movsbl_indexed_tlb(x,a,map,tl);
2893         }
2894       }
2895       if(jaddr)
2896         add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2897     }
2898     else
2899       inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2900   }
2901   if (opcode[i]==0x21) { // LH
2902     if(!c||memtarget) {
2903       if(!dummy) {
2904         #ifdef HOST_IMM_ADDR32
2905         if(c)
2906           emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2907         else
2908         #endif
2909         {
2910           int x=0,a=tl;
2911 #ifdef BIG_ENDIAN_MIPS
2912           if(!c) emit_xorimm(addr,2,tl);
2913           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2914 #else
2915           if(!c) a=addr;
2916 #endif
2917           if(fastload_reg_override) a=fastload_reg_override;
2918           //#ifdef
2919           //emit_movswl_indexed_tlb(x,tl,map,tl);
2920           //else
2921           if(map>=0) {
2922             gen_tlb_addr_r(a,map);
2923             emit_movswl_indexed(x,a,tl);
2924           }else{
2925             #if 1 //def RAM_OFFSET
2926             emit_movswl_indexed(x,a,tl);
2927             #else
2928             emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2929             #endif
2930           }
2931         }
2932       }
2933       if(jaddr)
2934         add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2935     }
2936     else
2937       inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2938   }
2939   if (opcode[i]==0x23) { // LW
2940     if(!c||memtarget) {
2941       if(!dummy) {
2942         int a=addr;
2943         if(fastload_reg_override) a=fastload_reg_override;
2944         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2945         #ifdef HOST_IMM_ADDR32
2946         if(c)
2947           emit_readword_tlb(constmap[i][s]+offset,map,tl);
2948         else
2949         #endif
2950         emit_readword_indexed_tlb(0,a,map,tl);
2951       }
2952       if(jaddr)
2953         add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2954     }
2955     else
2956       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2957   }
2958   if (opcode[i]==0x24) { // LBU
2959     if(!c||memtarget) {
2960       if(!dummy) {
2961         #ifdef HOST_IMM_ADDR32
2962         if(c)
2963           emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2964         else
2965         #endif
2966         {
2967           //emit_xorimm(addr,3,tl);
2968           //gen_tlb_addr_r(tl,map);
2969           //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
2970           int x=0,a=tl;
2971 #ifdef BIG_ENDIAN_MIPS
2972           if(!c) emit_xorimm(addr,3,tl);
2973           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2974 #else
2975           if(!c) a=addr;
2976 #endif
2977           if(fastload_reg_override) a=fastload_reg_override;
2978
2979           emit_movzbl_indexed_tlb(x,a,map,tl);
2980         }
2981       }
2982       if(jaddr)
2983         add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2984     }
2985     else
2986       inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2987   }
2988   if (opcode[i]==0x25) { // LHU
2989     if(!c||memtarget) {
2990       if(!dummy) {
2991         #ifdef HOST_IMM_ADDR32
2992         if(c)
2993           emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2994         else
2995         #endif
2996         {
2997           int x=0,a=tl;
2998 #ifdef BIG_ENDIAN_MIPS
2999           if(!c) emit_xorimm(addr,2,tl);
3000           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3001 #else
3002           if(!c) a=addr;
3003 #endif
3004           if(fastload_reg_override) a=fastload_reg_override;
3005           //#ifdef
3006           //emit_movzwl_indexed_tlb(x,tl,map,tl);
3007           //#else
3008           if(map>=0) {
3009             gen_tlb_addr_r(a,map);
3010             emit_movzwl_indexed(x,a,tl);
3011           }else{
3012             #if 1 //def RAM_OFFSET
3013             emit_movzwl_indexed(x,a,tl);
3014             #else
3015             emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
3016             #endif
3017           }
3018         }
3019       }
3020       if(jaddr)
3021         add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3022     }
3023     else
3024       inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3025   }
3026   if (opcode[i]==0x27) { // LWU
3027     assert(th>=0);
3028     if(!c||memtarget) {
3029       if(!dummy) {
3030         int a=addr;
3031         if(fastload_reg_override) a=fastload_reg_override;
3032         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3033         #ifdef HOST_IMM_ADDR32
3034         if(c)
3035           emit_readword_tlb(constmap[i][s]+offset,map,tl);
3036         else
3037         #endif
3038         emit_readword_indexed_tlb(0,a,map,tl);
3039       }
3040       if(jaddr)
3041         add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3042     }
3043     else {
3044       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3045     }
3046     emit_zeroreg(th);
3047   }
3048   if (opcode[i]==0x37) { // LD
3049     if(!c||memtarget) {
3050       if(!dummy) {
3051         int a=addr;
3052         if(fastload_reg_override) a=fastload_reg_override;
3053         //gen_tlb_addr_r(tl,map);
3054         //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3055         //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3056         #ifdef HOST_IMM_ADDR32
3057         if(c)
3058           emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3059         else
3060         #endif
3061         emit_readdword_indexed_tlb(0,a,map,th,tl);
3062       }
3063       if(jaddr)
3064         add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3065     }
3066     else
3067       inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3068   }
3069  }
3070   //emit_storereg(rt1[i],tl); // DEBUG
3071   //if(opcode[i]==0x23)
3072   //if(opcode[i]==0x24)
3073   //if(opcode[i]==0x23||opcode[i]==0x24)
3074   /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3075   {
3076     //emit_pusha();
3077     save_regs(0x100f);
3078         emit_readword((int)&last_count,ECX);
3079         #ifdef __i386__
3080         if(get_reg(i_regs->regmap,CCREG)<0)
3081           emit_loadreg(CCREG,HOST_CCREG);
3082         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3083         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3084         emit_writeword(HOST_CCREG,(int)&Count);
3085         #endif
3086         #ifdef __arm__
3087         if(get_reg(i_regs->regmap,CCREG)<0)
3088           emit_loadreg(CCREG,0);
3089         else
3090           emit_mov(HOST_CCREG,0);
3091         emit_add(0,ECX,0);
3092         emit_addimm(0,2*ccadj[i],0);
3093         emit_writeword(0,(int)&Count);
3094         #endif
3095     emit_call((int)memdebug);
3096     //emit_popa();
3097     restore_regs(0x100f);
3098   }/**/
3099 }
3100
3101 #ifndef loadlr_assemble
3102 void loadlr_assemble(int i,struct regstat *i_regs)
3103 {
3104   printf("Need loadlr_assemble for this architecture.\n");
3105   exit(1);
3106 }
3107 #endif
3108
3109 void store_assemble(int i,struct regstat *i_regs)
3110 {
3111   int s,th,tl,map=-1;
3112   int addr,temp;
3113   int offset;
3114   int jaddr=0,jaddr2,type;
3115   int memtarget=0,c=0;
3116   int agr=AGEN1+(i&1);
3117   int faststore_reg_override=0;
3118   u_int hr,reglist=0;
3119   th=get_reg(i_regs->regmap,rs2[i]|64);
3120   tl=get_reg(i_regs->regmap,rs2[i]);
3121   s=get_reg(i_regs->regmap,rs1[i]);
3122   temp=get_reg(i_regs->regmap,agr);
3123   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3124   offset=imm[i];
3125   if(s>=0) {
3126     c=(i_regs->wasconst>>s)&1;
3127     if(c) {
3128       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3129       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3130     }
3131   }
3132   assert(tl>=0);
3133   assert(temp>=0);
3134   for(hr=0;hr<HOST_REGS;hr++) {
3135     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3136   }
3137   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3138   if(offset||s<0||c) addr=temp;
3139   else addr=s;
3140   if(!using_tlb) {
3141     if(!c) {
3142       #ifndef PCSX
3143       #ifdef R29_HACK
3144       // Strmnnrmn's speed hack
3145       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3146       #endif
3147       emit_cmpimm(addr,RAM_SIZE);
3148       #ifdef DESTRUCTIVE_SHIFT
3149       if(s==addr) emit_mov(s,temp);
3150       #endif
3151       #ifdef R29_HACK
3152       memtarget=1;
3153       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3154       #endif
3155       {
3156         jaddr=(int)out;
3157         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3158         // Hint to branch predictor that the branch is unlikely to be taken
3159         if(rs1[i]>=28)
3160           emit_jno_unlikely(0);
3161         else
3162         #endif
3163         emit_jno(0);
3164       }
3165       #else
3166         jaddr=emit_fastpath_cmp_jump(i,addr,&faststore_reg_override);
3167       #endif
3168     }
3169     else if(ram_offset&&memtarget) {
3170       emit_addimm(addr,ram_offset,HOST_TEMPREG);
3171       faststore_reg_override=HOST_TEMPREG;
3172     }
3173   }else{ // using tlb
3174     int x=0;
3175     if (opcode[i]==0x28) x=3; // SB
3176     if (opcode[i]==0x29) x=2; // SH
3177     map=get_reg(i_regs->regmap,TLREG);
3178     assert(map>=0);
3179     reglist&=~(1<<map);
3180     map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3181     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3182   }
3183
3184   if (opcode[i]==0x28) { // SB
3185     if(!c||memtarget) {
3186       int x=0,a=temp;
3187 #ifdef BIG_ENDIAN_MIPS
3188       if(!c) emit_xorimm(addr,3,temp);
3189       else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3190 #else
3191       if(!c) a=addr;
3192 #endif
3193       if(faststore_reg_override) a=faststore_reg_override;
3194       //gen_tlb_addr_w(temp,map);
3195       //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3196       emit_writebyte_indexed_tlb(tl,x,a,map,a);
3197     }
3198     type=STOREB_STUB;
3199   }
3200   if (opcode[i]==0x29) { // SH
3201     if(!c||memtarget) {
3202       int x=0,a=temp;
3203 #ifdef BIG_ENDIAN_MIPS
3204       if(!c) emit_xorimm(addr,2,temp);
3205       else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3206 #else
3207       if(!c) a=addr;
3208 #endif
3209       if(faststore_reg_override) a=faststore_reg_override;
3210       //#ifdef
3211       //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3212       //#else
3213       if(map>=0) {
3214         gen_tlb_addr_w(a,map);
3215         emit_writehword_indexed(tl,x,a);
3216       }else
3217         //emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
3218         emit_writehword_indexed(tl,x,a);
3219     }
3220     type=STOREH_STUB;
3221   }
3222   if (opcode[i]==0x2B) { // SW
3223     if(!c||memtarget) {
3224       int a=addr;
3225       if(faststore_reg_override) a=faststore_reg_override;
3226       //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3227       emit_writeword_indexed_tlb(tl,0,a,map,temp);
3228     }
3229     type=STOREW_STUB;
3230   }
3231   if (opcode[i]==0x3F) { // SD
3232     if(!c||memtarget) {
3233       int a=addr;
3234       if(faststore_reg_override) a=faststore_reg_override;
3235       if(rs2[i]) {
3236         assert(th>=0);
3237         //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3238         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3239         emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
3240       }else{
3241         // Store zero
3242         //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3243         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3244         emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
3245       }
3246     }
3247     type=STORED_STUB;
3248   }
3249 #ifdef PCSX
3250   if(jaddr) {
3251     // PCSX store handlers don't check invcode again
3252     reglist|=1<<addr;
3253     add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3254     jaddr=0;
3255   }
3256 #endif
3257   if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3258     if(!c||memtarget) {
3259       #ifdef DESTRUCTIVE_SHIFT
3260       // The x86 shift operation is 'destructive'; it overwrites the
3261       // source register, so we need to make a copy first and use that.
3262       addr=temp;
3263       #endif
3264       #if defined(HOST_IMM8)
3265       int ir=get_reg(i_regs->regmap,INVCP);
3266       assert(ir>=0);
3267       emit_cmpmem_indexedsr12_reg(ir,addr,1);
3268       #else
3269       emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3270       #endif
3271       #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3272       emit_callne(invalidate_addr_reg[addr]);
3273       #else
3274       jaddr2=(int)out;
3275       emit_jne(0);
3276       add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3277       #endif
3278     }
3279   }
3280   u_int addr_val=constmap[i][s]+offset;
3281   if(jaddr) {
3282     add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3283   } else if(c&&!memtarget) {
3284     inline_writestub(type,i,addr_val,i_regs->regmap,rs2[i],ccadj[i],reglist);
3285   }
3286   // basic current block modification detection..
3287   // not looking back as that should be in mips cache already
3288   if(c&&start+i*4<addr_val&&addr_val<start+slen*4) {
3289     SysPrintf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4);
3290     assert(i_regs->regmap==regs[i].regmap); // not delay slot
3291     if(i_regs->regmap==regs[i].regmap) {
3292       load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
3293       wb_dirtys(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty);
3294       emit_movimm(start+i*4+4,0);
3295       emit_writeword(0,(int)&pcaddr);
3296       emit_jmp((int)do_interrupt);
3297     }
3298   }
3299   //if(opcode[i]==0x2B || opcode[i]==0x3F)
3300   //if(opcode[i]==0x2B || opcode[i]==0x28)
3301   //if(opcode[i]==0x2B || opcode[i]==0x29)
3302   //if(opcode[i]==0x2B)
3303   /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3304   {
3305     #ifdef __i386__
3306     emit_pusha();
3307     #endif
3308     #ifdef __arm__
3309     save_regs(0x100f);
3310     #endif
3311         emit_readword((int)&last_count,ECX);
3312         #ifdef __i386__
3313         if(get_reg(i_regs->regmap,CCREG)<0)
3314           emit_loadreg(CCREG,HOST_CCREG);
3315         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3316         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3317         emit_writeword(HOST_CCREG,(int)&Count);
3318         #endif
3319         #ifdef __arm__
3320         if(get_reg(i_regs->regmap,CCREG)<0)
3321           emit_loadreg(CCREG,0);
3322         else
3323           emit_mov(HOST_CCREG,0);
3324         emit_add(0,ECX,0);
3325         emit_addimm(0,2*ccadj[i],0);
3326         emit_writeword(0,(int)&Count);
3327         #endif
3328     emit_call((int)memdebug);
3329     #ifdef __i386__
3330     emit_popa();
3331     #endif
3332     #ifdef __arm__
3333     restore_regs(0x100f);
3334     #endif
3335   }/**/
3336 }
3337
3338 void storelr_assemble(int i,struct regstat *i_regs)
3339 {
3340   int s,th,tl;
3341   int temp;
3342   int temp2;
3343   int offset;
3344   int jaddr=0,jaddr2;
3345   int case1,case2,case3;
3346   int done0,done1,done2;
3347   int memtarget=0,c=0;
3348   int agr=AGEN1+(i&1);
3349   u_int hr,reglist=0;
3350   th=get_reg(i_regs->regmap,rs2[i]|64);
3351   tl=get_reg(i_regs->regmap,rs2[i]);
3352   s=get_reg(i_regs->regmap,rs1[i]);
3353   temp=get_reg(i_regs->regmap,agr);
3354   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3355   offset=imm[i];
3356   if(s>=0) {
3357     c=(i_regs->isconst>>s)&1;
3358     if(c) {
3359       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3360       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3361     }
3362   }
3363   assert(tl>=0);
3364   for(hr=0;hr<HOST_REGS;hr++) {
3365     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3366   }
3367   assert(temp>=0);
3368   if(!using_tlb) {
3369     if(!c) {
3370       emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3371       if(!offset&&s!=temp) emit_mov(s,temp);
3372       jaddr=(int)out;
3373       emit_jno(0);
3374     }
3375     else
3376     {
3377       if(!memtarget||!rs1[i]) {
3378         jaddr=(int)out;
3379         emit_jmp(0);
3380       }
3381     }
3382     #ifdef RAM_OFFSET
3383     int map=get_reg(i_regs->regmap,ROREG);
3384     if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3385     gen_tlb_addr_w(temp,map);
3386     #else
3387     if((u_int)rdram!=0x80000000)
3388       emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3389     #endif
3390   }else{ // using tlb
3391     int map=get_reg(i_regs->regmap,TLREG);
3392     assert(map>=0);
3393     reglist&=~(1<<map);
3394     map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3395     if(!c&&!offset&&s>=0) emit_mov(s,temp);
3396     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3397     if(!jaddr&&!memtarget) {
3398       jaddr=(int)out;
3399       emit_jmp(0);
3400     }
3401     gen_tlb_addr_w(temp,map);
3402   }
3403
3404   if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3405     temp2=get_reg(i_regs->regmap,FTEMP);
3406     if(!rs2[i]) temp2=th=tl;
3407   }
3408
3409 #ifndef BIG_ENDIAN_MIPS
3410     emit_xorimm(temp,3,temp);
3411 #endif
3412   emit_testimm(temp,2);
3413   case2=(int)out;
3414   emit_jne(0);
3415   emit_testimm(temp,1);
3416   case1=(int)out;
3417   emit_jne(0);
3418   // 0
3419   if (opcode[i]==0x2A) { // SWL
3420     emit_writeword_indexed(tl,0,temp);
3421   }
3422   if (opcode[i]==0x2E) { // SWR
3423     emit_writebyte_indexed(tl,3,temp);
3424   }
3425   if (opcode[i]==0x2C) { // SDL
3426     emit_writeword_indexed(th,0,temp);
3427     if(rs2[i]) emit_mov(tl,temp2);
3428   }
3429   if (opcode[i]==0x2D) { // SDR
3430     emit_writebyte_indexed(tl,3,temp);
3431     if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3432   }
3433   done0=(int)out;
3434   emit_jmp(0);
3435   // 1
3436   set_jump_target(case1,(int)out);
3437   if (opcode[i]==0x2A) { // SWL
3438     // Write 3 msb into three least significant bytes
3439     if(rs2[i]) emit_rorimm(tl,8,tl);
3440     emit_writehword_indexed(tl,-1,temp);
3441     if(rs2[i]) emit_rorimm(tl,16,tl);
3442     emit_writebyte_indexed(tl,1,temp);
3443     if(rs2[i]) emit_rorimm(tl,8,tl);
3444   }
3445   if (opcode[i]==0x2E) { // SWR
3446     // Write two lsb into two most significant bytes
3447     emit_writehword_indexed(tl,1,temp);
3448   }
3449   if (opcode[i]==0x2C) { // SDL
3450     if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3451     // Write 3 msb into three least significant bytes
3452     if(rs2[i]) emit_rorimm(th,8,th);
3453     emit_writehword_indexed(th,-1,temp);
3454     if(rs2[i]) emit_rorimm(th,16,th);
3455     emit_writebyte_indexed(th,1,temp);
3456     if(rs2[i]) emit_rorimm(th,8,th);
3457   }
3458   if (opcode[i]==0x2D) { // SDR
3459     if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3460     // Write two lsb into two most significant bytes
3461     emit_writehword_indexed(tl,1,temp);
3462   }
3463   done1=(int)out;
3464   emit_jmp(0);
3465   // 2
3466   set_jump_target(case2,(int)out);
3467   emit_testimm(temp,1);
3468   case3=(int)out;
3469   emit_jne(0);
3470   if (opcode[i]==0x2A) { // SWL
3471     // Write two msb into two least significant bytes
3472     if(rs2[i]) emit_rorimm(tl,16,tl);
3473     emit_writehword_indexed(tl,-2,temp);
3474     if(rs2[i]) emit_rorimm(tl,16,tl);
3475   }
3476   if (opcode[i]==0x2E) { // SWR
3477     // Write 3 lsb into three most significant bytes
3478     emit_writebyte_indexed(tl,-1,temp);
3479     if(rs2[i]) emit_rorimm(tl,8,tl);
3480     emit_writehword_indexed(tl,0,temp);
3481     if(rs2[i]) emit_rorimm(tl,24,tl);
3482   }
3483   if (opcode[i]==0x2C) { // SDL
3484     if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3485     // Write two msb into two least significant bytes
3486     if(rs2[i]) emit_rorimm(th,16,th);
3487     emit_writehword_indexed(th,-2,temp);
3488     if(rs2[i]) emit_rorimm(th,16,th);
3489   }
3490   if (opcode[i]==0x2D) { // SDR
3491     if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3492     // Write 3 lsb into three most significant bytes
3493     emit_writebyte_indexed(tl,-1,temp);
3494     if(rs2[i]) emit_rorimm(tl,8,tl);
3495     emit_writehword_indexed(tl,0,temp);
3496     if(rs2[i]) emit_rorimm(tl,24,tl);
3497   }
3498   done2=(int)out;
3499   emit_jmp(0);
3500   // 3
3501   set_jump_target(case3,(int)out);
3502   if (opcode[i]==0x2A) { // SWL
3503     // Write msb into least significant byte
3504     if(rs2[i]) emit_rorimm(tl,24,tl);
3505     emit_writebyte_indexed(tl,-3,temp);
3506     if(rs2[i]) emit_rorimm(tl,8,tl);
3507   }
3508   if (opcode[i]==0x2E) { // SWR
3509     // Write entire word
3510     emit_writeword_indexed(tl,-3,temp);
3511   }
3512   if (opcode[i]==0x2C) { // SDL
3513     if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3514     // Write msb into least significant byte
3515     if(rs2[i]) emit_rorimm(th,24,th);
3516     emit_writebyte_indexed(th,-3,temp);
3517     if(rs2[i]) emit_rorimm(th,8,th);
3518   }
3519   if (opcode[i]==0x2D) { // SDR
3520     if(rs2[i]) emit_mov(th,temp2);
3521     // Write entire word
3522     emit_writeword_indexed(tl,-3,temp);
3523   }
3524   set_jump_target(done0,(int)out);
3525   set_jump_target(done1,(int)out);
3526   set_jump_target(done2,(int)out);
3527   if (opcode[i]==0x2C) { // SDL
3528     emit_testimm(temp,4);
3529     done0=(int)out;
3530     emit_jne(0);
3531     emit_andimm(temp,~3,temp);
3532     emit_writeword_indexed(temp2,4,temp);
3533     set_jump_target(done0,(int)out);
3534   }
3535   if (opcode[i]==0x2D) { // SDR
3536     emit_testimm(temp,4);
3537     done0=(int)out;
3538     emit_jeq(0);
3539     emit_andimm(temp,~3,temp);
3540     emit_writeword_indexed(temp2,-4,temp);
3541     set_jump_target(done0,(int)out);
3542   }
3543   if(!c||!memtarget)
3544     add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
3545   if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3546     #ifdef RAM_OFFSET
3547     int map=get_reg(i_regs->regmap,ROREG);
3548     if(map<0) map=HOST_TEMPREG;
3549     gen_orig_addr_w(temp,map);
3550     #else
3551     emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3552     #endif
3553     #if defined(HOST_IMM8)
3554     int ir=get_reg(i_regs->regmap,INVCP);
3555     assert(ir>=0);
3556     emit_cmpmem_indexedsr12_reg(ir,temp,1);
3557     #else
3558     emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3559     #endif
3560     #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3561     emit_callne(invalidate_addr_reg[temp]);
3562     #else
3563     jaddr2=(int)out;
3564     emit_jne(0);
3565     add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3566     #endif
3567   }
3568   /*
3569     emit_pusha();
3570     //save_regs(0x100f);
3571         emit_readword((int)&last_count,ECX);
3572         if(get_reg(i_regs->regmap,CCREG)<0)
3573           emit_loadreg(CCREG,HOST_CCREG);
3574         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3575         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3576         emit_writeword(HOST_CCREG,(int)&Count);
3577     emit_call((int)memdebug);
3578     emit_popa();
3579     //restore_regs(0x100f);
3580   /**/
3581 }
3582
3583 void c1ls_assemble(int i,struct regstat *i_regs)
3584 {
3585 #ifndef DISABLE_COP1
3586   int s,th,tl;
3587   int temp,ar;
3588   int map=-1;
3589   int offset;
3590   int c=0;
3591   int jaddr,jaddr2=0,jaddr3,type;
3592   int agr=AGEN1+(i&1);
3593   u_int hr,reglist=0;
3594   th=get_reg(i_regs->regmap,FTEMP|64);
3595   tl=get_reg(i_regs->regmap,FTEMP);
3596   s=get_reg(i_regs->regmap,rs1[i]);
3597   temp=get_reg(i_regs->regmap,agr);
3598   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3599   offset=imm[i];
3600   assert(tl>=0);
3601   assert(rs1[i]>0);
3602   assert(temp>=0);
3603   for(hr=0;hr<HOST_REGS;hr++) {
3604     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3605   }
3606   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3607   if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3608   {
3609     // Loads use a temporary register which we need to save
3610     reglist|=1<<temp;
3611   }
3612   if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3613     ar=temp;
3614   else // LWC1/LDC1
3615     ar=tl;
3616   //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3617   //else c=(i_regs->wasconst>>s)&1;
3618   if(s>=0) c=(i_regs->wasconst>>s)&1;
3619   // Check cop1 unusable
3620   if(!cop1_usable) {
3621     signed char rs=get_reg(i_regs->regmap,CSREG);
3622     assert(rs>=0);
3623     emit_testimm(rs,0x20000000);
3624     jaddr=(int)out;
3625     emit_jeq(0);
3626     add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3627     cop1_usable=1;
3628   }
3629   if (opcode[i]==0x39) { // SWC1 (get float address)
3630     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],tl);
3631   }
3632   if (opcode[i]==0x3D) { // SDC1 (get double address)
3633     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],tl);
3634   }
3635   // Generate address + offset
3636   if(!using_tlb) {
3637     if(!c)
3638       emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3639   }
3640   else
3641   {
3642     map=get_reg(i_regs->regmap,TLREG);
3643     assert(map>=0);
3644     reglist&=~(1<<map);
3645     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3646       map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3647     }
3648     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3649       map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3650     }
3651   }
3652   if (opcode[i]==0x39) { // SWC1 (read float)
3653     emit_readword_indexed(0,tl,tl);
3654   }
3655   if (opcode[i]==0x3D) { // SDC1 (read double)
3656     emit_readword_indexed(4,tl,th);
3657     emit_readword_indexed(0,tl,tl);
3658   }
3659   if (opcode[i]==0x31) { // LWC1 (get target address)
3660     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],temp);
3661   }
3662   if (opcode[i]==0x35) { // LDC1 (get target address)
3663     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],temp);
3664   }
3665   if(!using_tlb) {
3666     if(!c) {
3667       jaddr2=(int)out;
3668       emit_jno(0);
3669     }
3670     else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
3671       jaddr2=(int)out;
3672       emit_jmp(0); // inline_readstub/inline_writestub?  Very rare case
3673     }
3674     #ifdef DESTRUCTIVE_SHIFT
3675     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3676       if(!offset&&!c&&s>=0) emit_mov(s,ar);
3677     }
3678     #endif
3679   }else{
3680     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3681       do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3682     }
3683     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3684       do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3685     }
3686   }
3687   if (opcode[i]==0x31) { // LWC1
3688     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3689     //gen_tlb_addr_r(ar,map);
3690     //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3691     #ifdef HOST_IMM_ADDR32
3692     if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3693     else
3694     #endif
3695     emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3696     type=LOADW_STUB;
3697   }
3698   if (opcode[i]==0x35) { // LDC1
3699     assert(th>=0);
3700     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3701     //gen_tlb_addr_r(ar,map);
3702     //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3703     //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3704     #ifdef HOST_IMM_ADDR32
3705     if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3706     else
3707     #endif
3708     emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3709     type=LOADD_STUB;
3710   }
3711   if (opcode[i]==0x39) { // SWC1
3712     //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3713     emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3714     type=STOREW_STUB;
3715   }
3716   if (opcode[i]==0x3D) { // SDC1
3717     assert(th>=0);
3718     //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3719     //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3720     emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3721     type=STORED_STUB;
3722   }
3723   if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3724     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3725       #ifndef DESTRUCTIVE_SHIFT
3726       temp=offset||c||s<0?ar:s;
3727       #endif
3728       #if defined(HOST_IMM8)
3729       int ir=get_reg(i_regs->regmap,INVCP);
3730       assert(ir>=0);
3731       emit_cmpmem_indexedsr12_reg(ir,temp,1);
3732       #else
3733       emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3734       #endif
3735       #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3736       emit_callne(invalidate_addr_reg[temp]);
3737       #else
3738       jaddr3=(int)out;
3739       emit_jne(0);
3740       add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3741       #endif
3742     }
3743   }
3744   if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3745   if (opcode[i]==0x31) { // LWC1 (write float)
3746     emit_writeword_indexed(tl,0,temp);
3747   }
3748   if (opcode[i]==0x35) { // LDC1 (write double)
3749     emit_writeword_indexed(th,4,temp);
3750     emit_writeword_indexed(tl,0,temp);
3751   }
3752   //if(opcode[i]==0x39)
3753   /*if(opcode[i]==0x39||opcode[i]==0x31)
3754   {
3755     emit_pusha();
3756         emit_readword((int)&last_count,ECX);
3757         if(get_reg(i_regs->regmap,CCREG)<0)
3758           emit_loadreg(CCREG,HOST_CCREG);
3759         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3760         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3761         emit_writeword(HOST_CCREG,(int)&Count);
3762     emit_call((int)memdebug);
3763     emit_popa();
3764   }/**/
3765 #else
3766   cop1_unusable(i, i_regs);
3767 #endif
3768 }
3769
3770 void c2ls_assemble(int i,struct regstat *i_regs)
3771 {
3772   int s,tl;
3773   int ar;
3774   int offset;
3775   int memtarget=0,c=0;
3776   int jaddr2=0,jaddr3,type;
3777   int agr=AGEN1+(i&1);
3778   int fastio_reg_override=0;
3779   u_int hr,reglist=0;
3780   u_int copr=(source[i]>>16)&0x1f;
3781   s=get_reg(i_regs->regmap,rs1[i]);
3782   tl=get_reg(i_regs->regmap,FTEMP);
3783   offset=imm[i];
3784   assert(rs1[i]>0);
3785   assert(tl>=0);
3786   assert(!using_tlb);
3787
3788   for(hr=0;hr<HOST_REGS;hr++) {
3789     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3790   }
3791   if(i_regs->regmap[HOST_CCREG]==CCREG)
3792     reglist&=~(1<<HOST_CCREG);
3793
3794   // get the address
3795   if (opcode[i]==0x3a) { // SWC2
3796     ar=get_reg(i_regs->regmap,agr);
3797     if(ar<0) ar=get_reg(i_regs->regmap,-1);
3798     reglist|=1<<ar;
3799   } else { // LWC2
3800     ar=tl;
3801   }
3802   if(s>=0) c=(i_regs->wasconst>>s)&1;
3803   memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3804   if (!offset&&!c&&s>=0) ar=s;
3805   assert(ar>=0);
3806
3807   if (opcode[i]==0x3a) { // SWC2
3808     cop2_get_dreg(copr,tl,HOST_TEMPREG);
3809     type=STOREW_STUB;
3810   }
3811   else
3812     type=LOADW_STUB;
3813
3814   if(c&&!memtarget) {
3815     jaddr2=(int)out;
3816     emit_jmp(0); // inline_readstub/inline_writestub?
3817   }
3818   else {
3819     if(!c) {
3820       jaddr2=emit_fastpath_cmp_jump(i,ar,&fastio_reg_override);
3821     }
3822     else if(ram_offset&&memtarget) {
3823       emit_addimm(ar,ram_offset,HOST_TEMPREG);
3824       fastio_reg_override=HOST_TEMPREG;
3825     }
3826     if (opcode[i]==0x32) { // LWC2
3827       #ifdef HOST_IMM_ADDR32
3828       if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3829       else
3830       #endif
3831       int a=ar;
3832       if(fastio_reg_override) a=fastio_reg_override;
3833       emit_readword_indexed(0,a,tl);
3834     }
3835     if (opcode[i]==0x3a) { // SWC2
3836       #ifdef DESTRUCTIVE_SHIFT
3837       if(!offset&&!c&&s>=0) emit_mov(s,ar);
3838       #endif
3839       int a=ar;
3840       if(fastio_reg_override) a=fastio_reg_override;
3841       emit_writeword_indexed(tl,0,a);
3842     }
3843   }
3844   if(jaddr2)
3845     add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3846   if(opcode[i]==0x3a) // SWC2
3847   if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3848 #if defined(HOST_IMM8)
3849     int ir=get_reg(i_regs->regmap,INVCP);
3850     assert(ir>=0);
3851     emit_cmpmem_indexedsr12_reg(ir,ar,1);
3852 #else
3853     emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3854 #endif
3855     #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3856     emit_callne(invalidate_addr_reg[ar]);
3857     #else
3858     jaddr3=(int)out;
3859     emit_jne(0);
3860     add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3861     #endif
3862   }
3863   if (opcode[i]==0x32) { // LWC2
3864     cop2_put_dreg(copr,tl,HOST_TEMPREG);
3865   }
3866 }
3867
3868 #ifndef multdiv_assemble
3869 void multdiv_assemble(int i,struct regstat *i_regs)
3870 {
3871   printf("Need multdiv_assemble for this architecture.\n");
3872   exit(1);
3873 }
3874 #endif
3875
3876 void mov_assemble(int i,struct regstat *i_regs)
3877 {
3878   //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3879   //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3880   if(rt1[i]) {
3881     signed char sh,sl,th,tl;
3882     th=get_reg(i_regs->regmap,rt1[i]|64);
3883     tl=get_reg(i_regs->regmap,rt1[i]);
3884     //assert(tl>=0);
3885     if(tl>=0) {
3886       sh=get_reg(i_regs->regmap,rs1[i]|64);
3887       sl=get_reg(i_regs->regmap,rs1[i]);
3888       if(sl>=0) emit_mov(sl,tl);
3889       else emit_loadreg(rs1[i],tl);
3890       if(th>=0) {
3891         if(sh>=0) emit_mov(sh,th);
3892         else emit_loadreg(rs1[i]|64,th);
3893       }
3894     }
3895   }
3896 }
3897
3898 #ifndef fconv_assemble
3899 void fconv_assemble(int i,struct regstat *i_regs)
3900 {
3901   printf("Need fconv_assemble for this architecture.\n");
3902   exit(1);
3903 }
3904 #endif
3905
3906 #if 0
3907 void float_assemble(int i,struct regstat *i_regs)
3908 {
3909   printf("Need float_assemble for this architecture.\n");
3910   exit(1);
3911 }
3912 #endif
3913
3914 void syscall_assemble(int i,struct regstat *i_regs)
3915 {
3916   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3917   assert(ccreg==HOST_CCREG);
3918   assert(!is_delayslot);
3919   emit_movimm(start+i*4,EAX); // Get PC
3920   emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // CHECK: is this right?  There should probably be an extra cycle...
3921   emit_jmp((int)jump_syscall_hle); // XXX
3922 }
3923
3924 void hlecall_assemble(int i,struct regstat *i_regs)
3925 {
3926   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3927   assert(ccreg==HOST_CCREG);
3928   assert(!is_delayslot);
3929   emit_movimm(start+i*4+4,0); // Get PC
3930   emit_movimm((int)psxHLEt[source[i]&7],1);
3931   emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // XXX
3932   emit_jmp((int)jump_hlecall);
3933 }
3934
3935 void intcall_assemble(int i,struct regstat *i_regs)
3936 {
3937   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3938   assert(ccreg==HOST_CCREG);
3939   assert(!is_delayslot);
3940   emit_movimm(start+i*4,0); // Get PC
3941   emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
3942   emit_jmp((int)jump_intcall);
3943 }
3944
3945 void ds_assemble(int i,struct regstat *i_regs)
3946 {
3947   speculate_register_values(i);
3948   is_delayslot=1;
3949   switch(itype[i]) {
3950     case ALU:
3951       alu_assemble(i,i_regs);break;
3952     case IMM16:
3953       imm16_assemble(i,i_regs);break;
3954     case SHIFT:
3955       shift_assemble(i,i_regs);break;
3956     case SHIFTIMM:
3957       shiftimm_assemble(i,i_regs);break;
3958     case LOAD:
3959       load_assemble(i,i_regs);break;
3960     case LOADLR:
3961       loadlr_assemble(i,i_regs);break;
3962     case STORE:
3963       store_assemble(i,i_regs);break;
3964     case STORELR:
3965       storelr_assemble(i,i_regs);break;
3966     case COP0:
3967       cop0_assemble(i,i_regs);break;
3968     case COP1:
3969       cop1_assemble(i,i_regs);break;
3970     case C1LS:
3971       c1ls_assemble(i,i_regs);break;
3972     case COP2:
3973       cop2_assemble(i,i_regs);break;
3974     case C2LS:
3975       c2ls_assemble(i,i_regs);break;
3976     case C2OP:
3977       c2op_assemble(i,i_regs);break;
3978     case FCONV:
3979       fconv_assemble(i,i_regs);break;
3980     case FLOAT:
3981       float_assemble(i,i_regs);break;
3982     case FCOMP:
3983       fcomp_assemble(i,i_regs);break;
3984     case MULTDIV:
3985       multdiv_assemble(i,i_regs);break;
3986     case MOV:
3987       mov_assemble(i,i_regs);break;
3988     case SYSCALL:
3989     case HLECALL:
3990     case INTCALL:
3991     case SPAN:
3992     case UJUMP:
3993     case RJUMP:
3994     case CJUMP:
3995     case SJUMP:
3996     case FJUMP:
3997       SysPrintf("Jump in the delay slot.  This is probably a bug.\n");
3998   }
3999   is_delayslot=0;
4000 }
4001
4002 // Is the branch target a valid internal jump?
4003 int internal_branch(uint64_t i_is32,int addr)
4004 {
4005   if(addr&1) return 0; // Indirect (register) jump
4006   if(addr>=start && addr<start+slen*4-4)
4007   {
4008     int t=(addr-start)>>2;
4009     // Delay slots are not valid branch targets
4010     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4011     // 64 -> 32 bit transition requires a recompile
4012     /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
4013     {
4014       if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
4015       else printf("optimizable: yes\n");
4016     }*/
4017     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4018 #ifndef FORCE32
4019     if(requires_32bit[t]&~i_is32) return 0;
4020     else
4021 #endif
4022       return 1;
4023   }
4024   return 0;
4025 }
4026
4027 #ifndef wb_invalidate
4028 void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
4029   uint64_t u,uint64_t uu)
4030 {
4031   int hr;
4032   for(hr=0;hr<HOST_REGS;hr++) {
4033     if(hr!=EXCLUDE_REG) {
4034       if(pre[hr]!=entry[hr]) {
4035         if(pre[hr]>=0) {
4036           if((dirty>>hr)&1) {
4037             if(get_reg(entry,pre[hr])<0) {
4038               if(pre[hr]<64) {
4039                 if(!((u>>pre[hr])&1)) {
4040                   emit_storereg(pre[hr],hr);
4041                   if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
4042                     emit_sarimm(hr,31,hr);
4043                     emit_storereg(pre[hr]|64,hr);
4044                   }
4045                 }
4046               }else{
4047                 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
4048                   emit_storereg(pre[hr],hr);
4049                 }
4050               }
4051             }
4052           }
4053         }
4054       }
4055     }
4056   }
4057   // Move from one register to another (no writeback)
4058   for(hr=0;hr<HOST_REGS;hr++) {
4059     if(hr!=EXCLUDE_REG) {
4060       if(pre[hr]!=entry[hr]) {
4061         if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
4062           int nr;
4063           if((nr=get_reg(entry,pre[hr]))>=0) {
4064             emit_mov(hr,nr);
4065           }
4066         }
4067       }
4068     }
4069   }
4070 }
4071 #endif
4072
4073 // Load the specified registers
4074 // This only loads the registers given as arguments because
4075 // we don't want to load things that will be overwritten
4076 void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
4077 {
4078   int hr;
4079   // Load 32-bit regs
4080   for(hr=0;hr<HOST_REGS;hr++) {
4081     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4082       if(entry[hr]!=regmap[hr]) {
4083         if(regmap[hr]==rs1||regmap[hr]==rs2)
4084         {
4085           if(regmap[hr]==0) {
4086             emit_zeroreg(hr);
4087           }
4088           else
4089           {
4090             emit_loadreg(regmap[hr],hr);
4091           }
4092         }
4093       }
4094     }
4095   }
4096   //Load 64-bit regs
4097   for(hr=0;hr<HOST_REGS;hr++) {
4098     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4099       if(entry[hr]!=regmap[hr]) {
4100         if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
4101         {
4102           assert(regmap[hr]!=64);
4103           if((is32>>(regmap[hr]&63))&1) {
4104             int lr=get_reg(regmap,regmap[hr]-64);
4105             if(lr>=0)
4106               emit_sarimm(lr,31,hr);
4107             else
4108               emit_loadreg(regmap[hr],hr);
4109           }
4110           else
4111           {
4112             emit_loadreg(regmap[hr],hr);
4113           }
4114         }
4115       }
4116     }
4117   }
4118 }
4119
4120 // Load registers prior to the start of a loop
4121 // so that they are not loaded within the loop
4122 static void loop_preload(signed char pre[],signed char entry[])
4123 {
4124   int hr;
4125   for(hr=0;hr<HOST_REGS;hr++) {
4126     if(hr!=EXCLUDE_REG) {
4127       if(pre[hr]!=entry[hr]) {
4128         if(entry[hr]>=0) {
4129           if(get_reg(pre,entry[hr])<0) {
4130             assem_debug("loop preload:\n");
4131             //printf("loop preload: %d\n",hr);
4132             if(entry[hr]==0) {
4133               emit_zeroreg(hr);
4134             }
4135             else if(entry[hr]<TEMPREG)
4136             {
4137               emit_loadreg(entry[hr],hr);
4138             }
4139             else if(entry[hr]-64<TEMPREG)
4140             {
4141               emit_loadreg(entry[hr],hr);
4142             }
4143           }
4144         }
4145       }
4146     }
4147   }
4148 }
4149
4150 // Generate address for load/store instruction
4151 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
4152 void address_generation(int i,struct regstat *i_regs,signed char entry[])
4153 {
4154   if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
4155     int ra=-1;
4156     int agr=AGEN1+(i&1);
4157     int mgr=MGEN1+(i&1);
4158     if(itype[i]==LOAD) {
4159       ra=get_reg(i_regs->regmap,rt1[i]);
4160       if(ra<0) ra=get_reg(i_regs->regmap,-1);
4161       assert(ra>=0);
4162     }
4163     if(itype[i]==LOADLR) {
4164       ra=get_reg(i_regs->regmap,FTEMP);
4165     }
4166     if(itype[i]==STORE||itype[i]==STORELR) {
4167       ra=get_reg(i_regs->regmap,agr);
4168       if(ra<0) ra=get_reg(i_regs->regmap,-1);
4169     }
4170     if(itype[i]==C1LS||itype[i]==C2LS) {
4171       if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
4172         ra=get_reg(i_regs->regmap,FTEMP);
4173       else { // SWC1/SDC1/SWC2/SDC2
4174         ra=get_reg(i_regs->regmap,agr);
4175         if(ra<0) ra=get_reg(i_regs->regmap,-1);
4176       }
4177     }
4178     int rs=get_reg(i_regs->regmap,rs1[i]);
4179     int rm=get_reg(i_regs->regmap,TLREG);
4180     if(ra>=0) {
4181       int offset=imm[i];
4182       int c=(i_regs->wasconst>>rs)&1;
4183       if(rs1[i]==0) {
4184         // Using r0 as a base address
4185         /*if(rm>=0) {
4186           if(!entry||entry[rm]!=mgr) {
4187             generate_map_const(offset,rm);
4188           } // else did it in the previous cycle
4189         }*/
4190         if(!entry||entry[ra]!=agr) {
4191           if (opcode[i]==0x22||opcode[i]==0x26) {
4192             emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4193           }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4194             emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4195           }else{
4196             emit_movimm(offset,ra);
4197           }
4198         } // else did it in the previous cycle
4199       }
4200       else if(rs<0) {
4201         if(!entry||entry[ra]!=rs1[i])
4202           emit_loadreg(rs1[i],ra);
4203         //if(!entry||entry[ra]!=rs1[i])
4204         //  printf("poor load scheduling!\n");
4205       }
4206       else if(c) {
4207 #ifndef DISABLE_TLB
4208         if(rm>=0) {
4209           if(!entry||entry[rm]!=mgr) {
4210             if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
4211               // Stores to memory go thru the mapper to detect self-modifying
4212               // code, loads don't.
4213               if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
4214                  (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
4215                 generate_map_const(constmap[i][rs]+offset,rm);
4216             }else{
4217               if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
4218                 generate_map_const(constmap[i][rs]+offset,rm);
4219             }
4220           }
4221         }
4222 #endif
4223         if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
4224           if(!entry||entry[ra]!=agr) {
4225             if (opcode[i]==0x22||opcode[i]==0x26) {
4226               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4227             }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4228               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4229             }else{
4230               #ifdef HOST_IMM_ADDR32
4231               if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4232                  (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4233               #endif
4234               emit_movimm(constmap[i][rs]+offset,ra);
4235               regs[i].loadedconst|=1<<ra;
4236             }
4237           } // else did it in the previous cycle
4238         } // else load_consts already did it
4239       }
4240       if(offset&&!c&&rs1[i]) {
4241         if(rs>=0) {
4242           emit_addimm(rs,offset,ra);
4243         }else{
4244           emit_addimm(ra,offset,ra);
4245         }
4246       }
4247     }
4248   }
4249   // Preload constants for next instruction
4250   if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
4251     int agr,ra;
4252     #if !defined(HOST_IMM_ADDR32) && !defined(DISABLE_TLB)
4253     // Mapper entry
4254     agr=MGEN1+((i+1)&1);
4255     ra=get_reg(i_regs->regmap,agr);
4256     if(ra>=0) {
4257       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4258       int offset=imm[i+1];
4259       int c=(regs[i+1].wasconst>>rs)&1;
4260       if(c) {
4261         if(itype[i+1]==STORE||itype[i+1]==STORELR
4262            ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
4263           // Stores to memory go thru the mapper to detect self-modifying
4264           // code, loads don't.
4265           if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4266              (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
4267             generate_map_const(constmap[i+1][rs]+offset,ra);
4268         }else{
4269           if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4270             generate_map_const(constmap[i+1][rs]+offset,ra);
4271         }
4272       }
4273       /*else if(rs1[i]==0) {
4274         generate_map_const(offset,ra);
4275       }*/
4276     }
4277     #endif
4278     // Actual address
4279     agr=AGEN1+((i+1)&1);
4280     ra=get_reg(i_regs->regmap,agr);
4281     if(ra>=0) {
4282       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4283       int offset=imm[i+1];
4284       int c=(regs[i+1].wasconst>>rs)&1;
4285       if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4286         if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4287           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4288         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4289           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4290         }else{
4291           #ifdef HOST_IMM_ADDR32
4292           if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4293              (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4294           #endif
4295           emit_movimm(constmap[i+1][rs]+offset,ra);
4296           regs[i+1].loadedconst|=1<<ra;
4297         }
4298       }
4299       else if(rs1[i+1]==0) {
4300         // Using r0 as a base address
4301         if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4302           emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4303         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4304           emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4305         }else{
4306           emit_movimm(offset,ra);
4307         }
4308       }
4309     }
4310   }
4311 }
4312
4313 int get_final_value(int hr, int i, int *value)
4314 {
4315   int reg=regs[i].regmap[hr];
4316   while(i<slen-1) {
4317     if(regs[i+1].regmap[hr]!=reg) break;
4318     if(!((regs[i+1].isconst>>hr)&1)) break;
4319     if(bt[i+1]) break;
4320     i++;
4321   }
4322   if(i<slen-1) {
4323     if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4324       *value=constmap[i][hr];
4325       return 1;
4326     }
4327     if(!bt[i+1]) {
4328       if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4329         // Load in delay slot, out-of-order execution
4330         if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4331         {
4332           #ifdef HOST_IMM_ADDR32
4333           if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4334           #endif
4335           // Precompute load address
4336           *value=constmap[i][hr]+imm[i+2];
4337           return 1;
4338         }
4339       }
4340       if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4341       {
4342         #ifdef HOST_IMM_ADDR32
4343         if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4344         #endif
4345         // Precompute load address
4346         *value=constmap[i][hr]+imm[i+1];
4347         //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4348         return 1;
4349       }
4350     }
4351   }
4352   *value=constmap[i][hr];
4353   //printf("c=%x\n",(int)constmap[i][hr]);
4354   if(i==slen-1) return 1;
4355   if(reg<64) {
4356     return !((unneeded_reg[i+1]>>reg)&1);
4357   }else{
4358     return !((unneeded_reg_upper[i+1]>>reg)&1);
4359   }
4360 }
4361
4362 // Load registers with known constants
4363 void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4364 {
4365   int hr,hr2;
4366   // propagate loaded constant flags
4367   if(i==0||bt[i])
4368     regs[i].loadedconst=0;
4369   else {
4370     for(hr=0;hr<HOST_REGS;hr++) {
4371       if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((regs[i-1].isconst>>hr)&1)&&pre[hr]==regmap[hr]
4372          &&regmap[hr]==regs[i-1].regmap[hr]&&((regs[i-1].loadedconst>>hr)&1))
4373       {
4374         regs[i].loadedconst|=1<<hr;
4375       }
4376     }
4377   }
4378   // Load 32-bit regs
4379   for(hr=0;hr<HOST_REGS;hr++) {
4380     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4381       //if(entry[hr]!=regmap[hr]) {
4382       if(!((regs[i].loadedconst>>hr)&1)) {
4383         if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4384           int value,similar=0;
4385           if(get_final_value(hr,i,&value)) {
4386             // see if some other register has similar value
4387             for(hr2=0;hr2<HOST_REGS;hr2++) {
4388               if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
4389                 if(is_similar_value(value,constmap[i][hr2])) {
4390                   similar=1;
4391                   break;
4392                 }
4393               }
4394             }
4395             if(similar) {
4396               int value2;
4397               if(get_final_value(hr2,i,&value2)) // is this needed?
4398                 emit_movimm_from(value2,hr2,value,hr);
4399               else
4400                 emit_movimm(value,hr);
4401             }
4402             else if(value==0) {
4403               emit_zeroreg(hr);
4404             }
4405             else {
4406               emit_movimm(value,hr);
4407             }
4408           }
4409           regs[i].loadedconst|=1<<hr;
4410         }
4411       }
4412     }
4413   }
4414   // Load 64-bit regs
4415   for(hr=0;hr<HOST_REGS;hr++) {
4416     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4417       //if(entry[hr]!=regmap[hr]) {
4418       if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4419         if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4420           if((is32>>(regmap[hr]&63))&1) {
4421             int lr=get_reg(regmap,regmap[hr]-64);
4422             assert(lr>=0);
4423             emit_sarimm(lr,31,hr);
4424           }
4425           else
4426           {
4427             int value;
4428             if(get_final_value(hr,i,&value)) {
4429               if(value==0) {
4430                 emit_zeroreg(hr);
4431               }
4432               else {
4433                 emit_movimm(value,hr);
4434               }
4435             }
4436           }
4437         }
4438       }
4439     }
4440   }
4441 }
4442 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4443 {
4444   int hr;
4445   // Load 32-bit regs
4446   for(hr=0;hr<HOST_REGS;hr++) {
4447     if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4448       if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4449         int value=constmap[i][hr];
4450         if(value==0) {
4451           emit_zeroreg(hr);
4452         }
4453         else {
4454           emit_movimm(value,hr);
4455         }
4456       }
4457     }
4458   }
4459   // Load 64-bit regs
4460   for(hr=0;hr<HOST_REGS;hr++) {
4461     if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4462       if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4463         if((is32>>(regmap[hr]&63))&1) {
4464           int lr=get_reg(regmap,regmap[hr]-64);
4465           assert(lr>=0);
4466           emit_sarimm(lr,31,hr);
4467         }
4468         else
4469         {
4470           int value=constmap[i][hr];
4471           if(value==0) {
4472             emit_zeroreg(hr);
4473           }
4474           else {
4475             emit_movimm(value,hr);
4476           }
4477         }
4478       }
4479     }
4480   }
4481 }
4482
4483 // Write out all dirty registers (except cycle count)
4484 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4485 {
4486   int hr;
4487   for(hr=0;hr<HOST_REGS;hr++) {
4488     if(hr!=EXCLUDE_REG) {
4489       if(i_regmap[hr]>0) {
4490         if(i_regmap[hr]!=CCREG) {
4491           if((i_dirty>>hr)&1) {
4492             if(i_regmap[hr]<64) {
4493               emit_storereg(i_regmap[hr],hr);
4494 #ifndef FORCE32
4495               if( ((i_is32>>i_regmap[hr])&1) ) {
4496                 #ifdef DESTRUCTIVE_WRITEBACK
4497                 emit_sarimm(hr,31,hr);
4498                 emit_storereg(i_regmap[hr]|64,hr);
4499                 #else
4500                 emit_sarimm(hr,31,HOST_TEMPREG);
4501                 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4502                 #endif
4503               }
4504 #endif
4505             }else{
4506               if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4507                 emit_storereg(i_regmap[hr],hr);
4508               }
4509             }
4510           }
4511         }
4512       }
4513     }
4514   }
4515 }
4516 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4517 // This writes the registers not written by store_regs_bt
4518 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4519 {
4520   int hr;
4521   int t=(addr-start)>>2;
4522   for(hr=0;hr<HOST_REGS;hr++) {
4523     if(hr!=EXCLUDE_REG) {
4524       if(i_regmap[hr]>0) {
4525         if(i_regmap[hr]!=CCREG) {
4526           if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4527             if((i_dirty>>hr)&1) {
4528               if(i_regmap[hr]<64) {
4529                 emit_storereg(i_regmap[hr],hr);
4530 #ifndef FORCE32
4531                 if( ((i_is32>>i_regmap[hr])&1) ) {
4532                   #ifdef DESTRUCTIVE_WRITEBACK
4533                   emit_sarimm(hr,31,hr);
4534                   emit_storereg(i_regmap[hr]|64,hr);
4535                   #else
4536                   emit_sarimm(hr,31,HOST_TEMPREG);
4537                   emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4538                   #endif
4539                 }
4540 #endif
4541               }else{
4542                 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4543                   emit_storereg(i_regmap[hr],hr);
4544                 }
4545               }
4546             }
4547           }
4548         }
4549       }
4550     }
4551   }
4552 }
4553
4554 // Load all registers (except cycle count)
4555 void load_all_regs(signed char i_regmap[])
4556 {
4557   int hr;
4558   for(hr=0;hr<HOST_REGS;hr++) {
4559     if(hr!=EXCLUDE_REG) {
4560       if(i_regmap[hr]==0) {
4561         emit_zeroreg(hr);
4562       }
4563       else
4564       if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4565       {
4566         emit_loadreg(i_regmap[hr],hr);
4567       }
4568     }
4569   }
4570 }
4571
4572 // Load all current registers also needed by next instruction
4573 void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4574 {
4575   int hr;
4576   for(hr=0;hr<HOST_REGS;hr++) {
4577     if(hr!=EXCLUDE_REG) {
4578       if(get_reg(next_regmap,i_regmap[hr])>=0) {
4579         if(i_regmap[hr]==0) {
4580           emit_zeroreg(hr);
4581         }
4582         else
4583         if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4584         {
4585           emit_loadreg(i_regmap[hr],hr);
4586         }
4587       }
4588     }
4589   }
4590 }
4591
4592 // Load all regs, storing cycle count if necessary
4593 void load_regs_entry(int t)
4594 {
4595   int hr;
4596   if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
4597   else if(ccadj[t]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST(ccadj[t]),HOST_CCREG);
4598   if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4599     emit_storereg(CCREG,HOST_CCREG);
4600   }
4601   // Load 32-bit regs
4602   for(hr=0;hr<HOST_REGS;hr++) {
4603     if(regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
4604       if(regs[t].regmap_entry[hr]==0) {
4605         emit_zeroreg(hr);
4606       }
4607       else if(regs[t].regmap_entry[hr]!=CCREG)
4608       {
4609         emit_loadreg(regs[t].regmap_entry[hr],hr);
4610       }
4611     }
4612   }
4613   // Load 64-bit regs
4614   for(hr=0;hr<HOST_REGS;hr++) {
4615     if(regs[t].regmap_entry[hr]>=64&&regs[t].regmap_entry[hr]<TEMPREG+64) {
4616       assert(regs[t].regmap_entry[hr]!=64);
4617       if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4618         int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4619         if(lr<0) {
4620           emit_loadreg(regs[t].regmap_entry[hr],hr);
4621         }
4622         else
4623         {
4624           emit_sarimm(lr,31,hr);
4625         }
4626       }
4627       else
4628       {
4629         emit_loadreg(regs[t].regmap_entry[hr],hr);
4630       }
4631     }
4632   }
4633 }
4634
4635 // Store dirty registers prior to branch
4636 void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4637 {
4638   if(internal_branch(i_is32,addr))
4639   {
4640     int t=(addr-start)>>2;
4641     int hr;
4642     for(hr=0;hr<HOST_REGS;hr++) {
4643       if(hr!=EXCLUDE_REG) {
4644         if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4645           if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4646             if((i_dirty>>hr)&1) {
4647               if(i_regmap[hr]<64) {
4648                 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4649                   emit_storereg(i_regmap[hr],hr);
4650                   if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4651                     #ifdef DESTRUCTIVE_WRITEBACK
4652                     emit_sarimm(hr,31,hr);
4653                     emit_storereg(i_regmap[hr]|64,hr);
4654                     #else
4655                     emit_sarimm(hr,31,HOST_TEMPREG);
4656                     emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4657                     #endif
4658                   }
4659                 }
4660               }else{
4661                 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4662                   emit_storereg(i_regmap[hr],hr);
4663                 }
4664               }
4665             }
4666           }
4667         }
4668       }
4669     }
4670   }
4671   else
4672   {
4673     // Branch out of this block, write out all dirty regs
4674     wb_dirtys(i_regmap,i_is32,i_dirty);
4675   }
4676 }
4677
4678 // Load all needed registers for branch target
4679 void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4680 {
4681   //if(addr>=start && addr<(start+slen*4))
4682   if(internal_branch(i_is32,addr))
4683   {
4684     int t=(addr-start)>>2;
4685     int hr;
4686     // Store the cycle count before loading something else
4687     if(i_regmap[HOST_CCREG]!=CCREG) {
4688       assert(i_regmap[HOST_CCREG]==-1);
4689     }
4690     if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4691       emit_storereg(CCREG,HOST_CCREG);
4692     }
4693     // Load 32-bit regs
4694     for(hr=0;hr<HOST_REGS;hr++) {
4695       if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
4696         #ifdef DESTRUCTIVE_WRITEBACK
4697         if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4698         #else
4699         if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4700         #endif
4701           if(regs[t].regmap_entry[hr]==0) {
4702             emit_zeroreg(hr);
4703           }
4704           else if(regs[t].regmap_entry[hr]!=CCREG)
4705           {
4706             emit_loadreg(regs[t].regmap_entry[hr],hr);
4707           }
4708         }
4709       }
4710     }
4711     //Load 64-bit regs
4712     for(hr=0;hr<HOST_REGS;hr++) {
4713       if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=64&&regs[t].regmap_entry[hr]<TEMPREG+64) {
4714         if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4715           assert(regs[t].regmap_entry[hr]!=64);
4716           if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4717             int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4718             if(lr<0) {
4719               emit_loadreg(regs[t].regmap_entry[hr],hr);
4720             }
4721             else
4722             {
4723               emit_sarimm(lr,31,hr);
4724             }
4725           }
4726           else
4727           {
4728             emit_loadreg(regs[t].regmap_entry[hr],hr);
4729           }
4730         }
4731         else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4732           int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4733           assert(lr>=0);
4734           emit_sarimm(lr,31,hr);
4735         }
4736       }
4737     }
4738   }
4739 }
4740
4741 int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4742 {
4743   if(addr>=start && addr<start+slen*4-4)
4744   {
4745     int t=(addr-start)>>2;
4746     int hr;
4747     if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4748     for(hr=0;hr<HOST_REGS;hr++)
4749     {
4750       if(hr!=EXCLUDE_REG)
4751       {
4752         if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4753         {
4754           if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
4755           {
4756             return 0;
4757           }
4758           else
4759           if((i_dirty>>hr)&1)
4760           {
4761             if(i_regmap[hr]<TEMPREG)
4762             {
4763               if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4764                 return 0;
4765             }
4766             else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
4767             {
4768               if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4769                 return 0;
4770             }
4771           }
4772         }
4773         else // Same register but is it 32-bit or dirty?
4774         if(i_regmap[hr]>=0)
4775         {
4776           if(!((regs[t].dirty>>hr)&1))
4777           {
4778             if((i_dirty>>hr)&1)
4779             {
4780               if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4781               {
4782                 //printf("%x: dirty no match\n",addr);
4783                 return 0;
4784               }
4785             }
4786           }
4787           if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4788           {
4789             //printf("%x: is32 no match\n",addr);
4790             return 0;
4791           }
4792         }
4793       }
4794     }
4795     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4796 #ifndef FORCE32
4797     if(requires_32bit[t]&~i_is32) return 0;
4798 #endif
4799     // Delay slots are not valid branch targets
4800     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4801     // Delay slots require additional processing, so do not match
4802     if(is_ds[t]) return 0;
4803   }
4804   else
4805   {
4806     int hr;
4807     for(hr=0;hr<HOST_REGS;hr++)
4808     {
4809       if(hr!=EXCLUDE_REG)
4810       {
4811         if(i_regmap[hr]>=0)
4812         {
4813           if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4814           {
4815             if((i_dirty>>hr)&1)
4816             {
4817               return 0;
4818             }
4819           }
4820         }
4821       }
4822     }
4823   }
4824   return 1;
4825 }
4826
4827 // Used when a branch jumps into the delay slot of another branch
4828 void ds_assemble_entry(int i)
4829 {
4830   int t=(ba[i]-start)>>2;
4831   if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4832   assem_debug("Assemble delay slot at %x\n",ba[i]);
4833   assem_debug("<->\n");
4834   if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
4835     wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4836   load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4837   address_generation(t,&regs[t],regs[t].regmap_entry);
4838   if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
4839     load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4840   cop1_usable=0;
4841   is_delayslot=0;
4842   switch(itype[t]) {
4843     case ALU:
4844       alu_assemble(t,&regs[t]);break;
4845     case IMM16:
4846       imm16_assemble(t,&regs[t]);break;
4847     case SHIFT:
4848       shift_assemble(t,&regs[t]);break;
4849     case SHIFTIMM:
4850       shiftimm_assemble(t,&regs[t]);break;
4851     case LOAD:
4852       load_assemble(t,&regs[t]);break;
4853     case LOADLR:
4854       loadlr_assemble(t,&regs[t]);break;
4855     case STORE:
4856       store_assemble(t,&regs[t]);break;
4857     case STORELR:
4858       storelr_assemble(t,&regs[t]);break;
4859     case COP0:
4860       cop0_assemble(t,&regs[t]);break;
4861     case COP1:
4862       cop1_assemble(t,&regs[t]);break;
4863     case C1LS:
4864       c1ls_assemble(t,&regs[t]);break;
4865     case COP2:
4866       cop2_assemble(t,&regs[t]);break;
4867     case C2LS:
4868       c2ls_assemble(t,&regs[t]);break;
4869     case C2OP:
4870       c2op_assemble(t,&regs[t]);break;
4871     case FCONV:
4872       fconv_assemble(t,&regs[t]);break;
4873     case FLOAT:
4874       float_assemble(t,&regs[t]);break;
4875     case FCOMP:
4876       fcomp_assemble(t,&regs[t]);break;
4877     case MULTDIV:
4878       multdiv_assemble(t,&regs[t]);break;
4879     case MOV:
4880       mov_assemble(t,&regs[t]);break;
4881     case SYSCALL:
4882     case HLECALL:
4883     case INTCALL:
4884     case SPAN:
4885     case UJUMP:
4886     case RJUMP:
4887     case CJUMP:
4888     case SJUMP:
4889     case FJUMP:
4890       SysPrintf("Jump in the delay slot.  This is probably a bug.\n");
4891   }
4892   store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4893   load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4894   if(internal_branch(regs[t].is32,ba[i]+4))
4895     assem_debug("branch: internal\n");
4896   else
4897     assem_debug("branch: external\n");
4898   assert(internal_branch(regs[t].is32,ba[i]+4));
4899   add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4900   emit_jmp(0);
4901 }
4902
4903 void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4904 {
4905   int count;
4906   int jaddr;
4907   int idle=0;
4908   int t=0;
4909   if(itype[i]==RJUMP)
4910   {
4911     *adj=0;
4912   }
4913   //if(ba[i]>=start && ba[i]<(start+slen*4))
4914   if(internal_branch(branch_regs[i].is32,ba[i]))
4915   {
4916     t=(ba[i]-start)>>2;
4917     if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4918     else *adj=ccadj[t];
4919   }
4920   else
4921   {
4922     *adj=0;
4923   }
4924   count=ccadj[i];
4925   if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4926     // Idle loop
4927     if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4928     idle=(int)out;
4929     //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4930     emit_andimm(HOST_CCREG,3,HOST_CCREG);
4931     jaddr=(int)out;
4932     emit_jmp(0);
4933   }
4934   else if(*adj==0||invert) {
4935     int cycles=CLOCK_ADJUST(count+2);
4936     // faster loop HACK
4937     if (t&&*adj) {
4938       int rel=t-i;
4939       if(-NO_CYCLE_PENALTY_THR<rel&&rel<0)
4940         cycles=CLOCK_ADJUST(*adj)+count+2-*adj;
4941     }
4942     emit_addimm_and_set_flags(cycles,HOST_CCREG);
4943     jaddr=(int)out;
4944     emit_jns(0);
4945   }
4946   else
4947   {
4948     emit_cmpimm(HOST_CCREG,-CLOCK_ADJUST(count+2));
4949     jaddr=(int)out;
4950     emit_jns(0);
4951   }
4952   add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4953 }
4954
4955 void do_ccstub(int n)
4956 {
4957   literal_pool(256);
4958   assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
4959   set_jump_target(stubs[n][1],(int)out);
4960   int i=stubs[n][4];
4961   if(stubs[n][6]==NULLDS) {
4962     // Delay slot instruction is nullified ("likely" branch)
4963     wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4964   }
4965   else if(stubs[n][6]!=TAKEN) {
4966     wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4967   }
4968   else {
4969     if(internal_branch(branch_regs[i].is32,ba[i]))
4970       wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4971   }
4972   if(stubs[n][5]!=-1)
4973   {
4974     // Save PC as return address
4975     emit_movimm(stubs[n][5],EAX);
4976     emit_writeword(EAX,(int)&pcaddr);
4977   }
4978   else
4979   {
4980     // Return address depends on which way the branch goes
4981     if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
4982     {
4983       int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4984       int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4985       int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4986       int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4987       if(rs1[i]==0)
4988       {
4989         s1l=s2l;s1h=s2h;
4990         s2l=s2h=-1;
4991       }
4992       else if(rs2[i]==0)
4993       {
4994         s2l=s2h=-1;
4995       }
4996       if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
4997         s1h=s2h=-1;
4998       }
4999       assert(s1l>=0);
5000       #ifdef DESTRUCTIVE_WRITEBACK
5001       if(rs1[i]) {
5002         if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
5003           emit_loadreg(rs1[i],s1l);
5004       }
5005       else {
5006         if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
5007           emit_loadreg(rs2[i],s1l);
5008       }
5009       if(s2l>=0)
5010         if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
5011           emit_loadreg(rs2[i],s2l);
5012       #endif
5013       int hr=0;
5014       int addr=-1,alt=-1,ntaddr=-1;
5015       while(hr<HOST_REGS)
5016       {
5017         if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5018            (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5019            (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5020         {
5021           addr=hr++;break;
5022         }
5023         hr++;
5024       }
5025       while(hr<HOST_REGS)
5026       {
5027         if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5028            (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5029            (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5030         {
5031           alt=hr++;break;
5032         }
5033         hr++;
5034       }
5035       if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
5036       {
5037         while(hr<HOST_REGS)
5038         {
5039           if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5040              (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5041              (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5042           {
5043             ntaddr=hr;break;
5044           }
5045           hr++;
5046         }
5047         assert(hr<HOST_REGS);
5048       }
5049       if((opcode[i]&0x2f)==4) // BEQ
5050       {
5051         #ifdef HAVE_CMOV_IMM
5052         if(s1h<0) {
5053           if(s2l>=0) emit_cmp(s1l,s2l);
5054           else emit_test(s1l,s1l);
5055           emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5056         }
5057         else
5058         #endif
5059         {
5060           emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5061           if(s1h>=0) {
5062             if(s2h>=0) emit_cmp(s1h,s2h);
5063             else emit_test(s1h,s1h);
5064             emit_cmovne_reg(alt,addr);
5065           }
5066           if(s2l>=0) emit_cmp(s1l,s2l);
5067           else emit_test(s1l,s1l);
5068           emit_cmovne_reg(alt,addr);
5069         }
5070       }
5071       if((opcode[i]&0x2f)==5) // BNE
5072       {
5073         #ifdef HAVE_CMOV_IMM
5074         if(s1h<0) {
5075           if(s2l>=0) emit_cmp(s1l,s2l);
5076           else emit_test(s1l,s1l);
5077           emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5078         }
5079         else
5080         #endif
5081         {
5082           emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5083           if(s1h>=0) {
5084             if(s2h>=0) emit_cmp(s1h,s2h);
5085             else emit_test(s1h,s1h);
5086             emit_cmovne_reg(alt,addr);
5087           }
5088           if(s2l>=0) emit_cmp(s1l,s2l);
5089           else emit_test(s1l,s1l);
5090           emit_cmovne_reg(alt,addr);
5091         }
5092       }
5093       if((opcode[i]&0x2f)==6) // BLEZ
5094       {
5095         //emit_movimm(ba[i],alt);
5096         //emit_movimm(start+i*4+8,addr);
5097         emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5098         emit_cmpimm(s1l,1);
5099         if(s1h>=0) emit_mov(addr,ntaddr);
5100         emit_cmovl_reg(alt,addr);
5101         if(s1h>=0) {
5102           emit_test(s1h,s1h);
5103           emit_cmovne_reg(ntaddr,addr);
5104           emit_cmovs_reg(alt,addr);
5105         }
5106       }
5107       if((opcode[i]&0x2f)==7) // BGTZ
5108       {
5109         //emit_movimm(ba[i],addr);
5110         //emit_movimm(start+i*4+8,ntaddr);
5111         emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5112         emit_cmpimm(s1l,1);
5113         if(s1h>=0) emit_mov(addr,alt);
5114         emit_cmovl_reg(ntaddr,addr);
5115         if(s1h>=0) {
5116           emit_test(s1h,s1h);
5117           emit_cmovne_reg(alt,addr);
5118           emit_cmovs_reg(ntaddr,addr);
5119         }
5120       }
5121       if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
5122       {
5123         //emit_movimm(ba[i],alt);
5124         //emit_movimm(start+i*4+8,addr);
5125         emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5126         if(s1h>=0) emit_test(s1h,s1h);
5127         else emit_test(s1l,s1l);
5128         emit_cmovs_reg(alt,addr);
5129       }
5130       if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
5131       {
5132         //emit_movimm(ba[i],addr);
5133         //emit_movimm(start+i*4+8,alt);
5134         emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5135         if(s1h>=0) emit_test(s1h,s1h);
5136         else emit_test(s1l,s1l);
5137         emit_cmovs_reg(alt,addr);
5138       }
5139       if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
5140         if(source[i]&0x10000) // BC1T
5141         {
5142           //emit_movimm(ba[i],alt);
5143           //emit_movimm(start+i*4+8,addr);
5144           emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5145           emit_testimm(s1l,0x800000);
5146           emit_cmovne_reg(alt,addr);
5147         }
5148         else // BC1F
5149         {
5150           //emit_movimm(ba[i],addr);
5151           //emit_movimm(start+i*4+8,alt);
5152           emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5153           emit_testimm(s1l,0x800000);
5154           emit_cmovne_reg(alt,addr);
5155         }
5156       }
5157       emit_writeword(addr,(int)&pcaddr);
5158     }
5159     else
5160     if(itype[i]==RJUMP)
5161     {
5162       int r=get_reg(branch_regs[i].regmap,rs1[i]);
5163       if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5164         r=get_reg(branch_regs[i].regmap,RTEMP);
5165       }
5166       emit_writeword(r,(int)&pcaddr);
5167     }
5168     else {SysPrintf("Unknown branch type in do_ccstub\n");exit(1);}
5169   }
5170   // Update cycle count
5171   assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5172   if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG);
5173   emit_call((int)cc_interrupt);
5174   if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG);
5175   if(stubs[n][6]==TAKEN) {
5176     if(internal_branch(branch_regs[i].is32,ba[i]))
5177       load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
5178     else if(itype[i]==RJUMP) {
5179       if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5180         emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5181       else
5182         emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
5183     }
5184   }else if(stubs[n][6]==NOTTAKEN) {
5185     if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5186     else load_all_regs(branch_regs[i].regmap);
5187   }else if(stubs[n][6]==NULLDS) {
5188     // Delay slot instruction is nullified ("likely" branch)
5189     if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5190     else load_all_regs(regs[i].regmap);
5191   }else{
5192     load_all_regs(branch_regs[i].regmap);
5193   }
5194   emit_jmp(stubs[n][2]); // return address
5195
5196   /* This works but uses a lot of memory...
5197   emit_readword((int)&last_count,ECX);
5198   emit_add(HOST_CCREG,ECX,EAX);
5199   emit_writeword(EAX,(int)&Count);
5200   emit_call((int)gen_interupt);
5201   emit_readword((int)&Count,HOST_CCREG);
5202   emit_readword((int)&next_interupt,EAX);
5203   emit_readword((int)&pending_exception,EBX);
5204   emit_writeword(EAX,(int)&last_count);
5205   emit_sub(HOST_CCREG,EAX,HOST_CCREG);
5206   emit_test(EBX,EBX);
5207   int jne_instr=(int)out;
5208   emit_jne(0);
5209   if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
5210   load_all_regs(branch_regs[i].regmap);
5211   emit_jmp(stubs[n][2]); // return address
5212   set_jump_target(jne_instr,(int)out);
5213   emit_readword((int)&pcaddr,EAX);
5214   // Call get_addr_ht instead of doing the hash table here.
5215   // This code is executed infrequently and takes up a lot of space
5216   // so smaller is better.
5217   emit_storereg(CCREG,HOST_CCREG);
5218   emit_pushreg(EAX);
5219   emit_call((int)get_addr_ht);
5220   emit_loadreg(CCREG,HOST_CCREG);
5221   emit_addimm(ESP,4,ESP);
5222   emit_jmpreg(EAX);*/
5223 }
5224
5225 add_to_linker(int addr,int target,int ext)
5226 {
5227   link_addr[linkcount][0]=addr;
5228   link_addr[linkcount][1]=target;
5229   link_addr[linkcount][2]=ext;
5230   linkcount++;
5231 }
5232
5233 static void ujump_assemble_write_ra(int i)
5234 {
5235   int rt;
5236   unsigned int return_address;
5237   rt=get_reg(branch_regs[i].regmap,31);
5238   assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5239   //assert(rt>=0);
5240   return_address=start+i*4+8;
5241   if(rt>=0) {
5242     #ifdef USE_MINI_HT
5243     if(internal_branch(branch_regs[i].is32,return_address)&&rt1[i+1]!=31) {
5244       int temp=-1; // note: must be ds-safe
5245       #ifdef HOST_TEMPREG
5246       temp=HOST_TEMPREG;
5247       #endif
5248       if(temp>=0) do_miniht_insert(return_address,rt,temp);
5249       else emit_movimm(return_address,rt);
5250     }
5251     else
5252     #endif
5253     {
5254       #ifdef REG_PREFETCH
5255       if(temp>=0)
5256       {
5257         if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5258       }
5259       #endif
5260       emit_movimm(return_address,rt); // PC into link register
5261       #ifdef IMM_PREFETCH
5262       emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5263       #endif
5264     }
5265   }
5266 }
5267
5268 void ujump_assemble(int i,struct regstat *i_regs)
5269 {
5270   signed char *i_regmap=i_regs->regmap;
5271   int ra_done=0;
5272   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5273   address_generation(i+1,i_regs,regs[i].regmap_entry);
5274   #ifdef REG_PREFETCH
5275   int temp=get_reg(branch_regs[i].regmap,PTEMP);
5276   if(rt1[i]==31&&temp>=0)
5277   {
5278     int return_address=start+i*4+8;
5279     if(get_reg(branch_regs[i].regmap,31)>0)
5280     if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5281   }
5282   #endif
5283   if(rt1[i]==31&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5284     ujump_assemble_write_ra(i); // writeback ra for DS
5285     ra_done=1;
5286   }
5287   ds_assemble(i+1,i_regs);
5288   uint64_t bc_unneeded=branch_regs[i].u;
5289   uint64_t bc_unneeded_upper=branch_regs[i].uu;
5290   bc_unneeded|=1|(1LL<<rt1[i]);
5291   bc_unneeded_upper|=1|(1LL<<rt1[i]);
5292   wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5293                 bc_unneeded,bc_unneeded_upper);
5294   load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5295   if(!ra_done&&rt1[i]==31)
5296     ujump_assemble_write_ra(i);
5297   int cc,adj;
5298   cc=get_reg(branch_regs[i].regmap,CCREG);
5299   assert(cc==HOST_CCREG);
5300   store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5301   #ifdef REG_PREFETCH
5302   if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5303   #endif
5304   do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5305   if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5306   load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5307   if(internal_branch(branch_regs[i].is32,ba[i]))
5308     assem_debug("branch: internal\n");
5309   else
5310     assem_debug("branch: external\n");
5311   if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5312     ds_assemble_entry(i);
5313   }
5314   else {
5315     add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5316     emit_jmp(0);
5317   }
5318 }
5319
5320 static void rjump_assemble_write_ra(int i)
5321 {
5322   int rt,return_address;
5323   assert(rt1[i+1]!=rt1[i]);
5324   assert(rt2[i+1]!=rt1[i]);
5325   rt=get_reg(branch_regs[i].regmap,rt1[i]);
5326   assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5327   assert(rt>=0);
5328   return_address=start+i*4+8;
5329   #ifdef REG_PREFETCH
5330   if(temp>=0)
5331   {
5332     if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5333   }
5334   #endif
5335   emit_movimm(return_address,rt); // PC into link register
5336   #ifdef IMM_PREFETCH
5337   emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5338   #endif
5339 }
5340
5341 void rjump_assemble(int i,struct regstat *i_regs)
5342 {
5343   signed char *i_regmap=i_regs->regmap;
5344   int temp;
5345   int rs,cc,adj;
5346   int ra_done=0;
5347   rs=get_reg(branch_regs[i].regmap,rs1[i]);
5348   assert(rs>=0);
5349   if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5350     // Delay slot abuse, make a copy of the branch address register
5351     temp=get_reg(branch_regs[i].regmap,RTEMP);
5352     assert(temp>=0);
5353     assert(regs[i].regmap[temp]==RTEMP);
5354     emit_mov(rs,temp);
5355     rs=temp;
5356   }
5357   address_generation(i+1,i_regs,regs[i].regmap_entry);
5358   #ifdef REG_PREFETCH
5359   if(rt1[i]==31)
5360   {
5361     if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5362       int return_address=start+i*4+8;
5363       if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5364     }
5365   }
5366   #endif
5367   #ifdef USE_MINI_HT
5368   if(rs1[i]==31) {
5369     int rh=get_reg(regs[i].regmap,RHASH);
5370     if(rh>=0) do_preload_rhash(rh);
5371   }
5372   #endif
5373   if(rt1[i]!=0&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5374     rjump_assemble_write_ra(i);
5375     ra_done=1;
5376   }
5377   ds_assemble(i+1,i_regs);
5378   uint64_t bc_unneeded=branch_regs[i].u;
5379   uint64_t bc_unneeded_upper=branch_regs[i].uu;
5380   bc_unneeded|=1|(1LL<<rt1[i]);
5381   bc_unneeded_upper|=1|(1LL<<rt1[i]);
5382   bc_unneeded&=~(1LL<<rs1[i]);
5383   wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5384                 bc_unneeded,bc_unneeded_upper);
5385   load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5386   if(!ra_done&&rt1[i]!=0)
5387     rjump_assemble_write_ra(i);
5388   cc=get_reg(branch_regs[i].regmap,CCREG);
5389   assert(cc==HOST_CCREG);
5390   #ifdef USE_MINI_HT
5391   int rh=get_reg(branch_regs[i].regmap,RHASH);
5392   int ht=get_reg(branch_regs[i].regmap,RHTBL);
5393   if(rs1[i]==31) {
5394     if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5395     do_preload_rhtbl(ht);
5396     do_rhash(rs,rh);
5397   }
5398   #endif
5399   store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5400   #ifdef DESTRUCTIVE_WRITEBACK
5401   if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5402     if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5403       emit_loadreg(rs1[i],rs);
5404     }
5405   }
5406   #endif
5407   #ifdef REG_PREFETCH
5408   if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5409   #endif
5410   #ifdef USE_MINI_HT
5411   if(rs1[i]==31) {
5412     do_miniht_load(ht,rh);
5413   }
5414   #endif
5415   //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5416   //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5417   //assert(adj==0);
5418   emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5419   add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5420 #ifdef PCSX
5421   if(itype[i+1]==COP0&&(source[i+1]&0x3f)==0x10)
5422     // special case for RFE
5423     emit_jmp(0);
5424   else
5425 #endif
5426   emit_jns(0);
5427   //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5428   #ifdef USE_MINI_HT
5429   if(rs1[i]==31) {
5430     do_miniht_jump(rs,rh,ht);
5431   }
5432   else
5433   #endif
5434   {
5435     //if(rs!=EAX) emit_mov(rs,EAX);
5436     //emit_jmp((int)jump_vaddr_eax);
5437     emit_jmp(jump_vaddr_reg[rs]);
5438   }
5439   /* Check hash table
5440   temp=!rs;
5441   emit_mov(rs,temp);
5442   emit_shrimm(rs,16,rs);
5443   emit_xor(temp,rs,rs);
5444   emit_movzwl_reg(rs,rs);
5445   emit_shlimm(rs,4,rs);
5446   emit_cmpmem_indexed((int)hash_table,rs,temp);
5447   emit_jne((int)out+14);
5448   emit_readword_indexed((int)hash_table+4,rs,rs);
5449   emit_jmpreg(rs);
5450   emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5451   emit_addimm_no_flags(8,rs);
5452   emit_jeq((int)out-17);
5453   // No hit on hash table, call compiler
5454   emit_pushreg(temp);
5455 //DEBUG >
5456 #ifdef DEBUG_CYCLE_COUNT
5457   emit_readword((int)&last_count,ECX);
5458   emit_add(HOST_CCREG,ECX,HOST_CCREG);
5459   emit_readword((int)&next_interupt,ECX);
5460   emit_writeword(HOST_CCREG,(int)&Count);
5461   emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5462   emit_writeword(ECX,(int)&last_count);
5463 #endif
5464 //DEBUG <
5465   emit_storereg(CCREG,HOST_CCREG);
5466   emit_call((int)get_addr);
5467   emit_loadreg(CCREG,HOST_CCREG);
5468   emit_addimm(ESP,4,ESP);
5469   emit_jmpreg(EAX);*/
5470   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5471   if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5472   #endif
5473 }
5474
5475 void cjump_assemble(int i,struct regstat *i_regs)
5476 {
5477   signed char *i_regmap=i_regs->regmap;
5478   int cc;
5479   int match;
5480   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5481   assem_debug("match=%d\n",match);
5482   int s1h,s1l,s2h,s2l;
5483   int prev_cop1_usable=cop1_usable;
5484   int unconditional=0,nop=0;
5485   int only32=0;
5486   int invert=0;
5487   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5488   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5489   if(!match) invert=1;
5490   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5491   if(i>(ba[i]-start)>>2) invert=1;
5492   #endif
5493
5494   if(ooo[i]) {
5495     s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5496     s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5497     s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5498     s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5499   }
5500   else {
5501     s1l=get_reg(i_regmap,rs1[i]);
5502     s1h=get_reg(i_regmap,rs1[i]|64);
5503     s2l=get_reg(i_regmap,rs2[i]);
5504     s2h=get_reg(i_regmap,rs2[i]|64);
5505   }
5506   if(rs1[i]==0&&rs2[i]==0)
5507   {
5508     if(opcode[i]&1) nop=1;
5509     else unconditional=1;
5510     //assert(opcode[i]!=5);
5511     //assert(opcode[i]!=7);
5512     //assert(opcode[i]!=0x15);
5513     //assert(opcode[i]!=0x17);
5514   }
5515   else if(rs1[i]==0)
5516   {
5517     s1l=s2l;s1h=s2h;
5518     s2l=s2h=-1;
5519     only32=(regs[i].was32>>rs2[i])&1;
5520   }
5521   else if(rs2[i]==0)
5522   {
5523     s2l=s2h=-1;
5524     only32=(regs[i].was32>>rs1[i])&1;
5525   }
5526   else {
5527     only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5528   }
5529
5530   if(ooo[i]) {
5531     // Out of order execution (delay slot first)
5532     //printf("OOOE\n");
5533     address_generation(i+1,i_regs,regs[i].regmap_entry);
5534     ds_assemble(i+1,i_regs);
5535     int adj;
5536     uint64_t bc_unneeded=branch_regs[i].u;
5537     uint64_t bc_unneeded_upper=branch_regs[i].uu;
5538     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5539     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5540     bc_unneeded|=1;
5541     bc_unneeded_upper|=1;
5542     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5543                   bc_unneeded,bc_unneeded_upper);
5544     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5545     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5546     cc=get_reg(branch_regs[i].regmap,CCREG);
5547     assert(cc==HOST_CCREG);
5548     if(unconditional)
5549       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5550     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5551     //assem_debug("cycle count (adj)\n");
5552     if(unconditional) {
5553       do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5554       if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5555         if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5556         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5557         if(internal)
5558           assem_debug("branch: internal\n");
5559         else
5560           assem_debug("branch: external\n");
5561         if(internal&&is_ds[(ba[i]-start)>>2]) {
5562           ds_assemble_entry(i);
5563         }
5564         else {
5565           add_to_linker((int)out,ba[i],internal);
5566           emit_jmp(0);
5567         }
5568         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5569         if(((u_int)out)&7) emit_addnop(0);
5570         #endif
5571       }
5572     }
5573     else if(nop) {
5574       emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5575       int jaddr=(int)out;
5576       emit_jns(0);
5577       add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5578     }
5579     else {
5580       int taken=0,nottaken=0,nottaken1=0;
5581       do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5582       if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5583       if(!only32)
5584       {
5585         assert(s1h>=0);
5586         if(opcode[i]==4) // BEQ
5587         {
5588           if(s2h>=0) emit_cmp(s1h,s2h);
5589           else emit_test(s1h,s1h);
5590           nottaken1=(int)out;
5591           emit_jne(1);
5592         }
5593         if(opcode[i]==5) // BNE
5594         {
5595           if(s2h>=0) emit_cmp(s1h,s2h);
5596           else emit_test(s1h,s1h);
5597           if(invert) taken=(int)out;
5598           else add_to_linker((int)out,ba[i],internal);
5599           emit_jne(0);
5600         }
5601         if(opcode[i]==6) // BLEZ
5602         {
5603           emit_test(s1h,s1h);
5604           if(invert) taken=(int)out;
5605           else add_to_linker((int)out,ba[i],internal);
5606           emit_js(0);
5607           nottaken1=(int)out;
5608           emit_jne(1);
5609         }
5610         if(opcode[i]==7) // BGTZ
5611         {
5612           emit_test(s1h,s1h);
5613           nottaken1=(int)out;
5614           emit_js(1);
5615           if(invert) taken=(int)out;
5616           else add_to_linker((int)out,ba[i],internal);
5617           emit_jne(0);
5618         }
5619       } // if(!only32)
5620
5621       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5622       assert(s1l>=0);
5623       if(opcode[i]==4) // BEQ
5624       {
5625         if(s2l>=0) emit_cmp(s1l,s2l);
5626         else emit_test(s1l,s1l);
5627         if(invert){
5628           nottaken=(int)out;
5629           emit_jne(1);
5630         }else{
5631           add_to_linker((int)out,ba[i],internal);
5632           emit_jeq(0);
5633         }
5634       }
5635       if(opcode[i]==5) // BNE
5636       {
5637         if(s2l>=0) emit_cmp(s1l,s2l);
5638         else emit_test(s1l,s1l);
5639         if(invert){
5640           nottaken=(int)out;
5641           emit_jeq(1);
5642         }else{
5643           add_to_linker((int)out,ba[i],internal);
5644           emit_jne(0);
5645         }
5646       }
5647       if(opcode[i]==6) // BLEZ
5648       {
5649         emit_cmpimm(s1l,1);
5650         if(invert){
5651           nottaken=(int)out;
5652           emit_jge(1);
5653         }else{
5654           add_to_linker((int)out,ba[i],internal);
5655           emit_jl(0);
5656         }
5657       }
5658       if(opcode[i]==7) // BGTZ
5659       {
5660         emit_cmpimm(s1l,1);
5661         if(invert){
5662           nottaken=(int)out;
5663           emit_jl(1);
5664         }else{
5665           add_to_linker((int)out,ba[i],internal);
5666           emit_jge(0);
5667         }
5668       }
5669       if(invert) {
5670         if(taken) set_jump_target(taken,(int)out);
5671         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5672         if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5673           if(adj) {
5674             emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5675             add_to_linker((int)out,ba[i],internal);
5676           }else{
5677             emit_addnop(13);
5678             add_to_linker((int)out,ba[i],internal*2);
5679           }
5680           emit_jmp(0);
5681         }else
5682         #endif
5683         {
5684           if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5685           store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5686           load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5687           if(internal)
5688             assem_debug("branch: internal\n");
5689           else
5690             assem_debug("branch: external\n");
5691           if(internal&&is_ds[(ba[i]-start)>>2]) {
5692             ds_assemble_entry(i);
5693           }
5694           else {
5695             add_to_linker((int)out,ba[i],internal);
5696             emit_jmp(0);
5697           }
5698         }
5699         set_jump_target(nottaken,(int)out);
5700       }
5701
5702       if(nottaken1) set_jump_target(nottaken1,(int)out);
5703       if(adj) {
5704         if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
5705       }
5706     } // (!unconditional)
5707   } // if(ooo)
5708   else
5709   {
5710     // In-order execution (branch first)
5711     //if(likely[i]) printf("IOL\n");
5712     //else
5713     //printf("IOE\n");
5714     int taken=0,nottaken=0,nottaken1=0;
5715     if(!unconditional&&!nop) {
5716       if(!only32)
5717       {
5718         assert(s1h>=0);
5719         if((opcode[i]&0x2f)==4) // BEQ
5720         {
5721           if(s2h>=0) emit_cmp(s1h,s2h);
5722           else emit_test(s1h,s1h);
5723           nottaken1=(int)out;
5724           emit_jne(2);
5725         }
5726         if((opcode[i]&0x2f)==5) // BNE
5727         {
5728           if(s2h>=0) emit_cmp(s1h,s2h);
5729           else emit_test(s1h,s1h);
5730           taken=(int)out;
5731           emit_jne(1);
5732         }
5733         if((opcode[i]&0x2f)==6) // BLEZ
5734         {
5735           emit_test(s1h,s1h);
5736           taken=(int)out;
5737           emit_js(1);
5738           nottaken1=(int)out;
5739           emit_jne(2);
5740         }
5741         if((opcode[i]&0x2f)==7) // BGTZ
5742         {
5743           emit_test(s1h,s1h);
5744           nottaken1=(int)out;
5745           emit_js(2);
5746           taken=(int)out;
5747           emit_jne(1);
5748         }
5749       } // if(!only32)
5750
5751       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5752       assert(s1l>=0);
5753       if((opcode[i]&0x2f)==4) // BEQ
5754       {
5755         if(s2l>=0) emit_cmp(s1l,s2l);
5756         else emit_test(s1l,s1l);
5757         nottaken=(int)out;
5758         emit_jne(2);
5759       }
5760       if((opcode[i]&0x2f)==5) // BNE
5761       {
5762         if(s2l>=0) emit_cmp(s1l,s2l);
5763         else emit_test(s1l,s1l);
5764         nottaken=(int)out;
5765         emit_jeq(2);
5766       }
5767       if((opcode[i]&0x2f)==6) // BLEZ
5768       {
5769         emit_cmpimm(s1l,1);
5770         nottaken=(int)out;
5771         emit_jge(2);
5772       }
5773       if((opcode[i]&0x2f)==7) // BGTZ
5774       {
5775         emit_cmpimm(s1l,1);
5776         nottaken=(int)out;
5777         emit_jl(2);
5778       }
5779     } // if(!unconditional)
5780     int adj;
5781     uint64_t ds_unneeded=branch_regs[i].u;
5782     uint64_t ds_unneeded_upper=branch_regs[i].uu;
5783     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5784     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5785     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5786     ds_unneeded|=1;
5787     ds_unneeded_upper|=1;
5788     // branch taken
5789     if(!nop) {
5790       if(taken) set_jump_target(taken,(int)out);
5791       assem_debug("1:\n");
5792       wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5793                     ds_unneeded,ds_unneeded_upper);
5794       // load regs
5795       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5796       address_generation(i+1,&branch_regs[i],0);
5797       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5798       ds_assemble(i+1,&branch_regs[i]);
5799       cc=get_reg(branch_regs[i].regmap,CCREG);
5800       if(cc==-1) {
5801         emit_loadreg(CCREG,cc=HOST_CCREG);
5802         // CHECK: Is the following instruction (fall thru) allocated ok?
5803       }
5804       assert(cc==HOST_CCREG);
5805       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5806       do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5807       assem_debug("cycle count (adj)\n");
5808       if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5809       load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5810       if(internal)
5811         assem_debug("branch: internal\n");
5812       else
5813         assem_debug("branch: external\n");
5814       if(internal&&is_ds[(ba[i]-start)>>2]) {
5815         ds_assemble_entry(i);
5816       }
5817       else {
5818         add_to_linker((int)out,ba[i],internal);
5819         emit_jmp(0);
5820       }
5821     }
5822     // branch not taken
5823     cop1_usable=prev_cop1_usable;
5824     if(!unconditional) {
5825       if(nottaken1) set_jump_target(nottaken1,(int)out);
5826       set_jump_target(nottaken,(int)out);
5827       assem_debug("2:\n");
5828       if(!likely[i]) {
5829         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5830                       ds_unneeded,ds_unneeded_upper);
5831         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5832         address_generation(i+1,&branch_regs[i],0);
5833         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5834         ds_assemble(i+1,&branch_regs[i]);
5835       }
5836       cc=get_reg(branch_regs[i].regmap,CCREG);
5837       if(cc==-1&&!likely[i]) {
5838         // Cycle count isn't in a register, temporarily load it then write it out
5839         emit_loadreg(CCREG,HOST_CCREG);
5840         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5841         int jaddr=(int)out;
5842         emit_jns(0);
5843         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5844         emit_storereg(CCREG,HOST_CCREG);
5845       }
5846       else{
5847         cc=get_reg(i_regmap,CCREG);
5848         assert(cc==HOST_CCREG);
5849         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5850         int jaddr=(int)out;
5851         emit_jns(0);
5852         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5853       }
5854     }
5855   }
5856 }
5857
5858 void sjump_assemble(int i,struct regstat *i_regs)
5859 {
5860   signed char *i_regmap=i_regs->regmap;
5861   int cc;
5862   int match;
5863   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5864   assem_debug("smatch=%d\n",match);
5865   int s1h,s1l;
5866   int prev_cop1_usable=cop1_usable;
5867   int unconditional=0,nevertaken=0;
5868   int only32=0;
5869   int invert=0;
5870   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5871   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5872   if(!match) invert=1;
5873   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5874   if(i>(ba[i]-start)>>2) invert=1;
5875   #endif
5876
5877   //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
5878   //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
5879
5880   if(ooo[i]) {
5881     s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5882     s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5883   }
5884   else {
5885     s1l=get_reg(i_regmap,rs1[i]);
5886     s1h=get_reg(i_regmap,rs1[i]|64);
5887   }
5888   if(rs1[i]==0)
5889   {
5890     if(opcode2[i]&1) unconditional=1;
5891     else nevertaken=1;
5892     // These are never taken (r0 is never less than zero)
5893     //assert(opcode2[i]!=0);
5894     //assert(opcode2[i]!=2);
5895     //assert(opcode2[i]!=0x10);
5896     //assert(opcode2[i]!=0x12);
5897   }
5898   else {
5899     only32=(regs[i].was32>>rs1[i])&1;
5900   }
5901
5902   if(ooo[i]) {
5903     // Out of order execution (delay slot first)
5904     //printf("OOOE\n");
5905     address_generation(i+1,i_regs,regs[i].regmap_entry);
5906     ds_assemble(i+1,i_regs);
5907     int adj;
5908     uint64_t bc_unneeded=branch_regs[i].u;
5909     uint64_t bc_unneeded_upper=branch_regs[i].uu;
5910     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5911     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5912     bc_unneeded|=1;
5913     bc_unneeded_upper|=1;
5914     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5915                   bc_unneeded,bc_unneeded_upper);
5916     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5917     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5918     if(rt1[i]==31) {
5919       int rt,return_address;
5920       rt=get_reg(branch_regs[i].regmap,31);
5921       assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5922       if(rt>=0) {
5923         // Save the PC even if the branch is not taken
5924         return_address=start+i*4+8;
5925         emit_movimm(return_address,rt); // PC into link register
5926         #ifdef IMM_PREFETCH
5927         if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5928         #endif
5929       }
5930     }
5931     cc=get_reg(branch_regs[i].regmap,CCREG);
5932     assert(cc==HOST_CCREG);
5933     if(unconditional)
5934       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5935     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5936     assem_debug("cycle count (adj)\n");
5937     if(unconditional) {
5938       do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5939       if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5940         if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5941         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5942         if(internal)
5943           assem_debug("branch: internal\n");
5944         else
5945           assem_debug("branch: external\n");
5946         if(internal&&is_ds[(ba[i]-start)>>2]) {
5947           ds_assemble_entry(i);
5948         }
5949         else {
5950           add_to_linker((int)out,ba[i],internal);
5951           emit_jmp(0);
5952         }
5953         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5954         if(((u_int)out)&7) emit_addnop(0);
5955         #endif
5956       }
5957     }
5958     else if(nevertaken) {
5959       emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5960       int jaddr=(int)out;
5961       emit_jns(0);
5962       add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5963     }
5964     else {
5965       int nottaken=0;
5966       do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5967       if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5968       if(!only32)
5969       {
5970         assert(s1h>=0);
5971         if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5972         {
5973           emit_test(s1h,s1h);
5974           if(invert){
5975             nottaken=(int)out;
5976             emit_jns(1);
5977           }else{
5978             add_to_linker((int)out,ba[i],internal);
5979             emit_js(0);
5980           }
5981         }
5982         if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5983         {
5984           emit_test(s1h,s1h);
5985           if(invert){
5986             nottaken=(int)out;
5987             emit_js(1);
5988           }else{
5989             add_to_linker((int)out,ba[i],internal);
5990             emit_jns(0);
5991           }
5992         }
5993       } // if(!only32)
5994       else
5995       {
5996         assert(s1l>=0);
5997         if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5998         {
5999           emit_test(s1l,s1l);
6000           if(invert){
6001             nottaken=(int)out;
6002             emit_jns(1);
6003           }else{
6004             add_to_linker((int)out,ba[i],internal);
6005             emit_js(0);
6006           }
6007         }
6008         if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
6009         {
6010           emit_test(s1l,s1l);
6011           if(invert){
6012             nottaken=(int)out;
6013             emit_js(1);
6014           }else{
6015             add_to_linker((int)out,ba[i],internal);
6016             emit_jns(0);
6017           }
6018         }
6019       } // if(!only32)
6020
6021       if(invert) {
6022         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6023         if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
6024           if(adj) {
6025             emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6026             add_to_linker((int)out,ba[i],internal);
6027           }else{
6028             emit_addnop(13);
6029             add_to_linker((int)out,ba[i],internal*2);
6030           }
6031           emit_jmp(0);
6032         }else
6033         #endif
6034         {
6035           if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6036           store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6037           load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6038           if(internal)
6039             assem_debug("branch: internal\n");
6040           else
6041             assem_debug("branch: external\n");
6042           if(internal&&is_ds[(ba[i]-start)>>2]) {
6043             ds_assemble_entry(i);
6044           }
6045           else {
6046             add_to_linker((int)out,ba[i],internal);
6047             emit_jmp(0);
6048           }
6049         }
6050         set_jump_target(nottaken,(int)out);
6051       }
6052
6053       if(adj) {
6054         if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
6055       }
6056     } // (!unconditional)
6057   } // if(ooo)
6058   else
6059   {
6060     // In-order execution (branch first)
6061     //printf("IOE\n");
6062     int nottaken=0;
6063     if(rt1[i]==31) {
6064       int rt,return_address;
6065       rt=get_reg(branch_regs[i].regmap,31);
6066       if(rt>=0) {
6067         // Save the PC even if the branch is not taken
6068         return_address=start+i*4+8;
6069         emit_movimm(return_address,rt); // PC into link register
6070         #ifdef IMM_PREFETCH
6071         emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
6072         #endif
6073       }
6074     }
6075     if(!unconditional) {
6076       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6077       if(!only32)
6078       {
6079         assert(s1h>=0);
6080         if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
6081         {
6082           emit_test(s1h,s1h);
6083           nottaken=(int)out;
6084           emit_jns(1);
6085         }
6086         if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
6087         {
6088           emit_test(s1h,s1h);
6089           nottaken=(int)out;
6090           emit_js(1);
6091         }
6092       } // if(!only32)
6093       else
6094       {
6095         assert(s1l>=0);
6096         if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
6097         {
6098           emit_test(s1l,s1l);
6099           nottaken=(int)out;
6100           emit_jns(1);
6101         }
6102         if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
6103         {
6104           emit_test(s1l,s1l);
6105           nottaken=(int)out;
6106           emit_js(1);
6107         }
6108       }
6109     } // if(!unconditional)
6110     int adj;
6111     uint64_t ds_unneeded=branch_regs[i].u;
6112     uint64_t ds_unneeded_upper=branch_regs[i].uu;
6113     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6114     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6115     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6116     ds_unneeded|=1;
6117     ds_unneeded_upper|=1;
6118     // branch taken
6119     if(!nevertaken) {
6120       //assem_debug("1:\n");
6121       wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6122                     ds_unneeded,ds_unneeded_upper);
6123       // load regs
6124       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6125       address_generation(i+1,&branch_regs[i],0);
6126       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6127       ds_assemble(i+1,&branch_regs[i]);
6128       cc=get_reg(branch_regs[i].regmap,CCREG);
6129       if(cc==-1) {
6130         emit_loadreg(CCREG,cc=HOST_CCREG);
6131         // CHECK: Is the following instruction (fall thru) allocated ok?
6132       }
6133       assert(cc==HOST_CCREG);
6134       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6135       do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6136       assem_debug("cycle count (adj)\n");
6137       if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6138       load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6139       if(internal)
6140         assem_debug("branch: internal\n");
6141       else
6142         assem_debug("branch: external\n");
6143       if(internal&&is_ds[(ba[i]-start)>>2]) {
6144         ds_assemble_entry(i);
6145       }
6146       else {
6147         add_to_linker((int)out,ba[i],internal);
6148         emit_jmp(0);
6149       }
6150     }
6151     // branch not taken
6152     cop1_usable=prev_cop1_usable;
6153     if(!unconditional) {
6154       set_jump_target(nottaken,(int)out);
6155       assem_debug("1:\n");
6156       if(!likely[i]) {
6157         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6158                       ds_unneeded,ds_unneeded_upper);
6159         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6160         address_generation(i+1,&branch_regs[i],0);
6161         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6162         ds_assemble(i+1,&branch_regs[i]);
6163       }
6164       cc=get_reg(branch_regs[i].regmap,CCREG);
6165       if(cc==-1&&!likely[i]) {
6166         // Cycle count isn't in a register, temporarily load it then write it out
6167         emit_loadreg(CCREG,HOST_CCREG);
6168         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6169         int jaddr=(int)out;
6170         emit_jns(0);
6171         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6172         emit_storereg(CCREG,HOST_CCREG);
6173       }
6174       else{
6175         cc=get_reg(i_regmap,CCREG);
6176         assert(cc==HOST_CCREG);
6177         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
6178         int jaddr=(int)out;
6179         emit_jns(0);
6180         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6181       }
6182     }
6183   }
6184 }
6185
6186 void fjump_assemble(int i,struct regstat *i_regs)
6187 {
6188   signed char *i_regmap=i_regs->regmap;
6189   int cc;
6190   int match;
6191   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6192   assem_debug("fmatch=%d\n",match);
6193   int fs,cs;
6194   int eaddr;
6195   int invert=0;
6196   int internal=internal_branch(branch_regs[i].is32,ba[i]);
6197   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
6198   if(!match) invert=1;
6199   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6200   if(i>(ba[i]-start)>>2) invert=1;
6201   #endif
6202
6203   if(ooo[i]) {
6204     fs=get_reg(branch_regs[i].regmap,FSREG);
6205     address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
6206   }
6207   else {
6208     fs=get_reg(i_regmap,FSREG);
6209   }
6210
6211   // Check cop1 unusable
6212   if(!cop1_usable) {
6213     cs=get_reg(i_regmap,CSREG);
6214     assert(cs>=0);
6215     emit_testimm(cs,0x20000000);
6216     eaddr=(int)out;
6217     emit_jeq(0);
6218     add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
6219     cop1_usable=1;
6220   }
6221
6222   if(ooo[i]) {
6223     // Out of order execution (delay slot first)
6224     //printf("OOOE\n");
6225     ds_assemble(i+1,i_regs);
6226     int adj;
6227     uint64_t bc_unneeded=branch_regs[i].u;
6228     uint64_t bc_unneeded_upper=branch_regs[i].uu;
6229     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6230     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
6231     bc_unneeded|=1;
6232     bc_unneeded_upper|=1;
6233     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6234                   bc_unneeded,bc_unneeded_upper);
6235     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
6236     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6237     cc=get_reg(branch_regs[i].regmap,CCREG);
6238     assert(cc==HOST_CCREG);
6239     do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6240     assem_debug("cycle count (adj)\n");
6241     if(1) {
6242       int nottaken=0;
6243       if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6244       if(1) {
6245         assert(fs>=0);
6246         emit_testimm(fs,0x800000);
6247         if(source[i]&0x10000) // BC1T
6248         {
6249           if(invert){
6250             nottaken=(int)out;
6251             emit_jeq(1);
6252           }else{
6253             add_to_linker((int)out,ba[i],internal);
6254             emit_jne(0);
6255           }
6256         }
6257         else // BC1F
6258           if(invert){
6259             nottaken=(int)out;
6260             emit_jne(1);
6261           }else{
6262             add_to_linker((int)out,ba[i],internal);
6263             emit_jeq(0);
6264           }
6265         {
6266         }
6267       } // if(!only32)
6268
6269       if(invert) {
6270         if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6271         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6272         else if(match) emit_addnop(13);
6273         #endif
6274         store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6275         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6276         if(internal)
6277           assem_debug("branch: internal\n");
6278         else
6279           assem_debug("branch: external\n");
6280         if(internal&&is_ds[(ba[i]-start)>>2]) {
6281           ds_assemble_entry(i);
6282         }
6283         else {
6284           add_to_linker((int)out,ba[i],internal);
6285           emit_jmp(0);
6286         }
6287         set_jump_target(nottaken,(int)out);
6288       }
6289
6290       if(adj) {
6291         if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
6292       }
6293     } // (!unconditional)
6294   } // if(ooo)
6295   else
6296   {
6297     // In-order execution (branch first)
6298     //printf("IOE\n");
6299     int nottaken=0;
6300     if(1) {
6301       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6302       if(1) {
6303         assert(fs>=0);
6304         emit_testimm(fs,0x800000);
6305         if(source[i]&0x10000) // BC1T
6306         {
6307           nottaken=(int)out;
6308           emit_jeq(1);
6309         }
6310         else // BC1F
6311         {
6312           nottaken=(int)out;
6313           emit_jne(1);
6314         }
6315       }
6316     } // if(!unconditional)
6317     int adj;
6318     uint64_t ds_unneeded=branch_regs[i].u;
6319     uint64_t ds_unneeded_upper=branch_regs[i].uu;
6320     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6321     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6322     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6323     ds_unneeded|=1;
6324     ds_unneeded_upper|=1;
6325     // branch taken
6326     //assem_debug("1:\n");
6327     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6328                   ds_unneeded,ds_unneeded_upper);
6329     // load regs
6330     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6331     address_generation(i+1,&branch_regs[i],0);
6332     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6333     ds_assemble(i+1,&branch_regs[i]);
6334     cc=get_reg(branch_regs[i].regmap,CCREG);
6335     if(cc==-1) {
6336       emit_loadreg(CCREG,cc=HOST_CCREG);
6337       // CHECK: Is the following instruction (fall thru) allocated ok?
6338     }
6339     assert(cc==HOST_CCREG);
6340     store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6341     do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6342     assem_debug("cycle count (adj)\n");
6343     if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6344     load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6345     if(internal)
6346       assem_debug("branch: internal\n");
6347     else
6348       assem_debug("branch: external\n");
6349     if(internal&&is_ds[(ba[i]-start)>>2]) {
6350       ds_assemble_entry(i);
6351     }
6352     else {
6353       add_to_linker((int)out,ba[i],internal);
6354       emit_jmp(0);
6355     }
6356
6357     // branch not taken
6358     if(1) { // <- FIXME (don't need this)
6359       set_jump_target(nottaken,(int)out);
6360       assem_debug("1:\n");
6361       if(!likely[i]) {
6362         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6363                       ds_unneeded,ds_unneeded_upper);
6364         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6365         address_generation(i+1,&branch_regs[i],0);
6366         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6367         ds_assemble(i+1,&branch_regs[i]);
6368       }
6369       cc=get_reg(branch_regs[i].regmap,CCREG);
6370       if(cc==-1&&!likely[i]) {
6371         // Cycle count isn't in a register, temporarily load it then write it out
6372         emit_loadreg(CCREG,HOST_CCREG);
6373         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6374         int jaddr=(int)out;
6375         emit_jns(0);
6376         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6377         emit_storereg(CCREG,HOST_CCREG);
6378       }
6379       else{
6380         cc=get_reg(i_regmap,CCREG);
6381         assert(cc==HOST_CCREG);
6382         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
6383         int jaddr=(int)out;
6384         emit_jns(0);
6385         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6386       }
6387     }
6388   }
6389 }
6390
6391 static void pagespan_assemble(int i,struct regstat *i_regs)
6392 {
6393   int s1l=get_reg(i_regs->regmap,rs1[i]);
6394   int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6395   int s2l=get_reg(i_regs->regmap,rs2[i]);
6396   int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6397   void *nt_branch=NULL;
6398   int taken=0;
6399   int nottaken=0;
6400   int unconditional=0;
6401   if(rs1[i]==0)
6402   {
6403     s1l=s2l;s1h=s2h;
6404     s2l=s2h=-1;
6405   }
6406   else if(rs2[i]==0)
6407   {
6408     s2l=s2h=-1;
6409   }
6410   if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6411     s1h=s2h=-1;
6412   }
6413   int hr=0;
6414   int addr,alt,ntaddr;
6415   if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6416   else {
6417     while(hr<HOST_REGS)
6418     {
6419       if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6420          (i_regs->regmap[hr]&63)!=rs1[i] &&
6421          (i_regs->regmap[hr]&63)!=rs2[i] )
6422       {
6423         addr=hr++;break;
6424       }
6425       hr++;
6426     }
6427   }
6428   while(hr<HOST_REGS)
6429   {
6430     if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6431        (i_regs->regmap[hr]&63)!=rs1[i] &&
6432        (i_regs->regmap[hr]&63)!=rs2[i] )
6433     {
6434       alt=hr++;break;
6435     }
6436     hr++;
6437   }
6438   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6439   {
6440     while(hr<HOST_REGS)
6441     {
6442       if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6443          (i_regs->regmap[hr]&63)!=rs1[i] &&
6444          (i_regs->regmap[hr]&63)!=rs2[i] )
6445       {
6446         ntaddr=hr;break;
6447       }
6448       hr++;
6449     }
6450   }
6451   assert(hr<HOST_REGS);
6452   if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6453     load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6454   }
6455   emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6456   if(opcode[i]==2) // J
6457   {
6458     unconditional=1;
6459   }
6460   if(opcode[i]==3) // JAL
6461   {
6462     // TODO: mini_ht
6463     int rt=get_reg(i_regs->regmap,31);
6464     emit_movimm(start+i*4+8,rt);
6465     unconditional=1;
6466   }
6467   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6468   {
6469     emit_mov(s1l,addr);
6470     if(opcode2[i]==9) // JALR
6471     {
6472       int rt=get_reg(i_regs->regmap,rt1[i]);
6473       emit_movimm(start+i*4+8,rt);
6474     }
6475   }
6476   if((opcode[i]&0x3f)==4) // BEQ
6477   {
6478     if(rs1[i]==rs2[i])
6479     {
6480       unconditional=1;
6481     }
6482     else
6483     #ifdef HAVE_CMOV_IMM
6484     if(s1h<0) {
6485       if(s2l>=0) emit_cmp(s1l,s2l);
6486       else emit_test(s1l,s1l);
6487       emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6488     }
6489     else
6490     #endif
6491     {
6492       assert(s1l>=0);
6493       emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6494       if(s1h>=0) {
6495         if(s2h>=0) emit_cmp(s1h,s2h);
6496         else emit_test(s1h,s1h);
6497         emit_cmovne_reg(alt,addr);
6498       }
6499       if(s2l>=0) emit_cmp(s1l,s2l);
6500       else emit_test(s1l,s1l);
6501       emit_cmovne_reg(alt,addr);
6502     }
6503   }
6504   if((opcode[i]&0x3f)==5) // BNE
6505   {
6506     #ifdef HAVE_CMOV_IMM
6507     if(s1h<0) {
6508       if(s2l>=0) emit_cmp(s1l,s2l);
6509       else emit_test(s1l,s1l);
6510       emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6511     }
6512     else
6513     #endif
6514     {
6515       assert(s1l>=0);
6516       emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6517       if(s1h>=0) {
6518         if(s2h>=0) emit_cmp(s1h,s2h);
6519         else emit_test(s1h,s1h);
6520         emit_cmovne_reg(alt,addr);
6521       }
6522       if(s2l>=0) emit_cmp(s1l,s2l);
6523       else emit_test(s1l,s1l);
6524       emit_cmovne_reg(alt,addr);
6525     }
6526   }
6527   if((opcode[i]&0x3f)==0x14) // BEQL
6528   {
6529     if(s1h>=0) {
6530       if(s2h>=0) emit_cmp(s1h,s2h);
6531       else emit_test(s1h,s1h);
6532       nottaken=(int)out;
6533       emit_jne(0);
6534     }
6535     if(s2l>=0) emit_cmp(s1l,s2l);
6536     else emit_test(s1l,s1l);
6537     if(nottaken) set_jump_target(nottaken,(int)out);
6538     nottaken=(int)out;
6539     emit_jne(0);
6540   }
6541   if((opcode[i]&0x3f)==0x15) // BNEL
6542   {
6543     if(s1h>=0) {
6544       if(s2h>=0) emit_cmp(s1h,s2h);
6545       else emit_test(s1h,s1h);
6546       taken=(int)out;
6547       emit_jne(0);
6548     }
6549     if(s2l>=0) emit_cmp(s1l,s2l);
6550     else emit_test(s1l,s1l);
6551     nottaken=(int)out;
6552     emit_jeq(0);
6553     if(taken) set_jump_target(taken,(int)out);
6554   }
6555   if((opcode[i]&0x3f)==6) // BLEZ
6556   {
6557     emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6558     emit_cmpimm(s1l,1);
6559     if(s1h>=0) emit_mov(addr,ntaddr);
6560     emit_cmovl_reg(alt,addr);
6561     if(s1h>=0) {
6562       emit_test(s1h,s1h);
6563       emit_cmovne_reg(ntaddr,addr);
6564       emit_cmovs_reg(alt,addr);
6565     }
6566   }
6567   if((opcode[i]&0x3f)==7) // BGTZ
6568   {
6569     emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6570     emit_cmpimm(s1l,1);
6571     if(s1h>=0) emit_mov(addr,alt);
6572     emit_cmovl_reg(ntaddr,addr);
6573     if(s1h>=0) {
6574       emit_test(s1h,s1h);
6575       emit_cmovne_reg(alt,addr);
6576       emit_cmovs_reg(ntaddr,addr);
6577     }
6578   }
6579   if((opcode[i]&0x3f)==0x16) // BLEZL
6580   {
6581     assert((opcode[i]&0x3f)!=0x16);
6582   }
6583   if((opcode[i]&0x3f)==0x17) // BGTZL
6584   {
6585     assert((opcode[i]&0x3f)!=0x17);
6586   }
6587   assert(opcode[i]!=1); // BLTZ/BGEZ
6588
6589   //FIXME: Check CSREG
6590   if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6591     if((source[i]&0x30000)==0) // BC1F
6592     {
6593       emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6594       emit_testimm(s1l,0x800000);
6595       emit_cmovne_reg(alt,addr);
6596     }
6597     if((source[i]&0x30000)==0x10000) // BC1T
6598     {
6599       emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6600       emit_testimm(s1l,0x800000);
6601       emit_cmovne_reg(alt,addr);
6602     }
6603     if((source[i]&0x30000)==0x20000) // BC1FL
6604     {
6605       emit_testimm(s1l,0x800000);
6606       nottaken=(int)out;
6607       emit_jne(0);
6608     }
6609     if((source[i]&0x30000)==0x30000) // BC1TL
6610     {
6611       emit_testimm(s1l,0x800000);
6612       nottaken=(int)out;
6613       emit_jeq(0);
6614     }
6615   }
6616
6617   assert(i_regs->regmap[HOST_CCREG]==CCREG);
6618   wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6619   if(likely[i]||unconditional)
6620   {
6621     emit_movimm(ba[i],HOST_BTREG);
6622   }
6623   else if(addr!=HOST_BTREG)
6624   {
6625     emit_mov(addr,HOST_BTREG);
6626   }
6627   void *branch_addr=out;
6628   emit_jmp(0);
6629   int target_addr=start+i*4+5;
6630   void *stub=out;
6631   void *compiled_target_addr=check_addr(target_addr);
6632   emit_extjump_ds((int)branch_addr,target_addr);
6633   if(compiled_target_addr) {
6634     set_jump_target((int)branch_addr,(int)compiled_target_addr);
6635     add_link(target_addr,stub);
6636   }
6637   else set_jump_target((int)branch_addr,(int)stub);
6638   if(likely[i]) {
6639     // Not-taken path
6640     set_jump_target((int)nottaken,(int)out);
6641     wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6642     void *branch_addr=out;
6643     emit_jmp(0);
6644     int target_addr=start+i*4+8;
6645     void *stub=out;
6646     void *compiled_target_addr=check_addr(target_addr);
6647     emit_extjump_ds((int)branch_addr,target_addr);
6648     if(compiled_target_addr) {
6649       set_jump_target((int)branch_addr,(int)compiled_target_addr);
6650       add_link(target_addr,stub);
6651     }
6652     else set_jump_target((int)branch_addr,(int)stub);
6653   }
6654 }
6655
6656 // Assemble the delay slot for the above
6657 static void pagespan_ds()
6658 {
6659   assem_debug("initial delay slot:\n");
6660   u_int vaddr=start+1;
6661   u_int page=get_page(vaddr);
6662   u_int vpage=get_vpage(vaddr);
6663   ll_add(jump_dirty+vpage,vaddr,(void *)out);
6664   do_dirty_stub_ds();
6665   ll_add(jump_in+page,vaddr,(void *)out);
6666   assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6667   if(regs[0].regmap[HOST_CCREG]!=CCREG)
6668     wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6669   if(regs[0].regmap[HOST_BTREG]!=BTREG)
6670     emit_writeword(HOST_BTREG,(int)&branch_target);
6671   load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6672   address_generation(0,&regs[0],regs[0].regmap_entry);
6673   if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
6674     load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6675   cop1_usable=0;
6676   is_delayslot=0;
6677   switch(itype[0]) {
6678     case ALU:
6679       alu_assemble(0,&regs[0]);break;
6680     case IMM16:
6681       imm16_assemble(0,&regs[0]);break;
6682     case SHIFT:
6683       shift_assemble(0,&regs[0]);break;
6684     case SHIFTIMM:
6685       shiftimm_assemble(0,&regs[0]);break;
6686     case LOAD:
6687       load_assemble(0,&regs[0]);break;
6688     case LOADLR:
6689       loadlr_assemble(0,&regs[0]);break;
6690     case STORE:
6691       store_assemble(0,&regs[0]);break;
6692     case STORELR:
6693       storelr_assemble(0,&regs[0]);break;
6694     case COP0:
6695       cop0_assemble(0,&regs[0]);break;
6696     case COP1:
6697       cop1_assemble(0,&regs[0]);break;
6698     case C1LS:
6699       c1ls_assemble(0,&regs[0]);break;
6700     case COP2:
6701       cop2_assemble(0,&regs[0]);break;
6702     case C2LS:
6703       c2ls_assemble(0,&regs[0]);break;
6704     case C2OP:
6705       c2op_assemble(0,&regs[0]);break;
6706     case FCONV:
6707       fconv_assemble(0,&regs[0]);break;
6708     case FLOAT:
6709       float_assemble(0,&regs[0]);break;
6710     case FCOMP:
6711       fcomp_assemble(0,&regs[0]);break;
6712     case MULTDIV:
6713       multdiv_assemble(0,&regs[0]);break;
6714     case MOV:
6715       mov_assemble(0,&regs[0]);break;
6716     case SYSCALL:
6717     case HLECALL:
6718     case INTCALL:
6719     case SPAN:
6720     case UJUMP:
6721     case RJUMP:
6722     case CJUMP:
6723     case SJUMP:
6724     case FJUMP:
6725       SysPrintf("Jump in the delay slot.  This is probably a bug.\n");
6726   }
6727   int btaddr=get_reg(regs[0].regmap,BTREG);
6728   if(btaddr<0) {
6729     btaddr=get_reg(regs[0].regmap,-1);
6730     emit_readword((int)&branch_target,btaddr);
6731   }
6732   assert(btaddr!=HOST_CCREG);
6733   if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6734 #ifdef HOST_IMM8
6735   emit_movimm(start+4,HOST_TEMPREG);
6736   emit_cmp(btaddr,HOST_TEMPREG);
6737 #else
6738   emit_cmpimm(btaddr,start+4);
6739 #endif
6740   int branch=(int)out;
6741   emit_jeq(0);
6742   store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6743   emit_jmp(jump_vaddr_reg[btaddr]);
6744   set_jump_target(branch,(int)out);
6745   store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6746   load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6747 }
6748
6749 // Basic liveness analysis for MIPS registers
6750 void unneeded_registers(int istart,int iend,int r)
6751 {
6752   int i;
6753   uint64_t u,uu,gte_u,b,bu,gte_bu;
6754   uint64_t temp_u,temp_uu,temp_gte_u=0;
6755   uint64_t tdep;
6756   uint64_t gte_u_unknown=0;
6757   if(new_dynarec_hacks&NDHACK_GTE_UNNEEDED)
6758     gte_u_unknown=~0ll;
6759   if(iend==slen-1) {
6760     u=1;uu=1;
6761     gte_u=gte_u_unknown;
6762   }else{
6763     u=unneeded_reg[iend+1];
6764     uu=unneeded_reg_upper[iend+1];
6765     u=1;uu=1;
6766     gte_u=gte_unneeded[iend+1];
6767   }
6768
6769   for (i=iend;i>=istart;i--)
6770   {
6771     //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6772     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6773     {
6774       // If subroutine call, flag return address as a possible branch target
6775       if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6776
6777       if(ba[i]<start || ba[i]>=(start+slen*4))
6778       {
6779         // Branch out of this block, flush all regs
6780         u=1;
6781         uu=1;
6782         gte_u=gte_u_unknown;
6783         /* Hexagon hack
6784         if(itype[i]==UJUMP&&rt1[i]==31)
6785         {
6786           uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6787         }
6788         if(itype[i]==RJUMP&&rs1[i]==31)
6789         {
6790           uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6791         }
6792         if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
6793           if(itype[i]==UJUMP&&rt1[i]==31)
6794           {
6795             //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6796             uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6797           }
6798           if(itype[i]==RJUMP&&rs1[i]==31)
6799           {
6800             //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6801             uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6802           }
6803         }*/
6804         branch_unneeded_reg[i]=u;
6805         branch_unneeded_reg_upper[i]=uu;
6806         // Merge in delay slot
6807         tdep=(~uu>>rt1[i+1])&1;
6808         u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6809         uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6810         u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6811         uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6812         uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6813         u|=1;uu|=1;
6814         gte_u|=gte_rt[i+1];
6815         gte_u&=~gte_rs[i+1];
6816         // If branch is "likely" (and conditional)
6817         // then we skip the delay slot on the fall-thru path
6818         if(likely[i]) {
6819           if(i<slen-1) {
6820             u&=unneeded_reg[i+2];
6821             uu&=unneeded_reg_upper[i+2];
6822             gte_u&=gte_unneeded[i+2];
6823           }
6824           else
6825           {
6826             u=1;
6827             uu=1;
6828             gte_u=gte_u_unknown;
6829           }
6830         }
6831       }
6832       else
6833       {
6834         // Internal branch, flag target
6835         bt[(ba[i]-start)>>2]=1;
6836         if(ba[i]<=start+i*4) {
6837           // Backward branch
6838           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6839           {
6840             // Unconditional branch
6841             temp_u=1;temp_uu=1;
6842             temp_gte_u=0;
6843           } else {
6844             // Conditional branch (not taken case)
6845             temp_u=unneeded_reg[i+2];
6846             temp_uu=unneeded_reg_upper[i+2];
6847             temp_gte_u&=gte_unneeded[i+2];
6848           }
6849           // Merge in delay slot
6850           tdep=(~temp_uu>>rt1[i+1])&1;
6851           temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6852           temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6853           temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6854           temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6855           temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6856           temp_u|=1;temp_uu|=1;
6857           temp_gte_u|=gte_rt[i+1];
6858           temp_gte_u&=~gte_rs[i+1];
6859           // If branch is "likely" (and conditional)
6860           // then we skip the delay slot on the fall-thru path
6861           if(likely[i]) {
6862             if(i<slen-1) {
6863               temp_u&=unneeded_reg[i+2];
6864               temp_uu&=unneeded_reg_upper[i+2];
6865               temp_gte_u&=gte_unneeded[i+2];
6866             }
6867             else
6868             {
6869               temp_u=1;
6870               temp_uu=1;
6871               temp_gte_u=gte_u_unknown;
6872             }
6873           }
6874           tdep=(~temp_uu>>rt1[i])&1;
6875           temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6876           temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6877           temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6878           temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6879           temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6880           temp_u|=1;temp_uu|=1;
6881           temp_gte_u|=gte_rt[i];
6882           temp_gte_u&=~gte_rs[i];
6883           unneeded_reg[i]=temp_u;
6884           unneeded_reg_upper[i]=temp_uu;
6885           gte_unneeded[i]=temp_gte_u;
6886           // Only go three levels deep.  This recursion can take an
6887           // excessive amount of time if there are a lot of nested loops.
6888           if(r<2) {
6889             unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6890           }else{
6891             unneeded_reg[(ba[i]-start)>>2]=1;
6892             unneeded_reg_upper[(ba[i]-start)>>2]=1;
6893             gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown;
6894           }
6895         } /*else*/ if(1) {
6896           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6897           {
6898             // Unconditional branch
6899             u=unneeded_reg[(ba[i]-start)>>2];
6900             uu=unneeded_reg_upper[(ba[i]-start)>>2];
6901             gte_u=gte_unneeded[(ba[i]-start)>>2];
6902             branch_unneeded_reg[i]=u;
6903             branch_unneeded_reg_upper[i]=uu;
6904         //u=1;
6905         //uu=1;
6906         //branch_unneeded_reg[i]=u;
6907         //branch_unneeded_reg_upper[i]=uu;
6908             // Merge in delay slot
6909             tdep=(~uu>>rt1[i+1])&1;
6910             u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6911             uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6912             u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6913             uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6914             uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6915             u|=1;uu|=1;
6916             gte_u|=gte_rt[i+1];
6917             gte_u&=~gte_rs[i+1];
6918           } else {
6919             // Conditional branch
6920             b=unneeded_reg[(ba[i]-start)>>2];
6921             bu=unneeded_reg_upper[(ba[i]-start)>>2];
6922             gte_bu=gte_unneeded[(ba[i]-start)>>2];
6923             branch_unneeded_reg[i]=b;
6924             branch_unneeded_reg_upper[i]=bu;
6925         //b=1;
6926         //bu=1;
6927         //branch_unneeded_reg[i]=b;
6928         //branch_unneeded_reg_upper[i]=bu;
6929             // Branch delay slot
6930             tdep=(~uu>>rt1[i+1])&1;
6931             b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6932             bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6933             b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6934             bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6935             bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6936             b|=1;bu|=1;
6937             gte_bu|=gte_rt[i+1];
6938             gte_bu&=~gte_rs[i+1];
6939             // If branch is "likely" then we skip the
6940             // delay slot on the fall-thru path
6941             if(likely[i]) {
6942               u=b;
6943               uu=bu;
6944               gte_u=gte_bu;
6945               if(i<slen-1) {
6946                 u&=unneeded_reg[i+2];
6947                 uu&=unneeded_reg_upper[i+2];
6948                 gte_u&=gte_unneeded[i+2];
6949         //u=1;
6950         //uu=1;
6951               }
6952             } else {
6953               u&=b;
6954               uu&=bu;
6955               gte_u&=gte_bu;
6956         //u=1;
6957         //uu=1;
6958             }
6959             if(i<slen-1) {
6960               branch_unneeded_reg[i]&=unneeded_reg[i+2];
6961               branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6962         //branch_unneeded_reg[i]=1;
6963         //branch_unneeded_reg_upper[i]=1;
6964             } else {
6965               branch_unneeded_reg[i]=1;
6966               branch_unneeded_reg_upper[i]=1;
6967             }
6968           }
6969         }
6970       }
6971     }
6972     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
6973     {
6974       // SYSCALL instruction (software interrupt)
6975       u=1;
6976       uu=1;
6977     }
6978     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6979     {
6980       // ERET instruction (return from interrupt)
6981       u=1;
6982       uu=1;
6983     }
6984     //u=uu=1; // DEBUG
6985     tdep=(~uu>>rt1[i])&1;
6986     // Written registers are unneeded
6987     u|=1LL<<rt1[i];
6988     u|=1LL<<rt2[i];
6989     uu|=1LL<<rt1[i];
6990     uu|=1LL<<rt2[i];
6991     gte_u|=gte_rt[i];
6992     // Accessed registers are needed
6993     u&=~(1LL<<rs1[i]);
6994     u&=~(1LL<<rs2[i]);
6995     uu&=~(1LL<<us1[i]);
6996     uu&=~(1LL<<us2[i]);
6997     gte_u&=~gte_rs[i];
6998     if(gte_rs[i]&&rt1[i]&&(unneeded_reg[i+1]&(1ll<<rt1[i])))
6999       gte_u|=gte_rs[i]&gte_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded
7000     // Source-target dependencies
7001     uu&=~(tdep<<dep1[i]);
7002     uu&=~(tdep<<dep2[i]);
7003     // R0 is always unneeded
7004     u|=1;uu|=1;
7005     // Save it
7006     unneeded_reg[i]=u;
7007     unneeded_reg_upper[i]=uu;
7008     gte_unneeded[i]=gte_u;
7009     /*
7010     printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
7011     printf("U:");
7012     int r;
7013     for(r=1;r<=CCREG;r++) {
7014       if((unneeded_reg[i]>>r)&1) {
7015         if(r==HIREG) printf(" HI");
7016         else if(r==LOREG) printf(" LO");
7017         else printf(" r%d",r);
7018       }
7019     }
7020     printf(" UU:");
7021     for(r=1;r<=CCREG;r++) {
7022       if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
7023         if(r==HIREG) printf(" HI");
7024         else if(r==LOREG) printf(" LO");
7025         else printf(" r%d",r);
7026       }
7027     }
7028     printf("\n");*/
7029   }
7030 #ifdef FORCE32
7031   for (i=iend;i>=istart;i--)
7032   {
7033     unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
7034   }
7035 #endif
7036 }
7037
7038 // Identify registers which are likely to contain 32-bit values
7039 // This is used to predict whether any branches will jump to a
7040 // location with 64-bit values in registers.
7041 static void provisional_32bit()
7042 {
7043   int i,j;
7044   uint64_t is32=1;
7045   uint64_t lastbranch=1;
7046
7047   for(i=0;i<slen;i++)
7048   {
7049     if(i>0) {
7050       if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
7051         if(i>1) is32=lastbranch;
7052         else is32=1;
7053       }
7054     }
7055     if(i>1)
7056     {
7057       if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
7058         if(likely[i-2]) {
7059           if(i>2) is32=lastbranch;
7060           else is32=1;
7061         }
7062       }
7063       if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
7064       {
7065         if(rs1[i-2]==0||rs2[i-2]==0)
7066         {
7067           if(rs1[i-2]) {
7068             is32|=1LL<<rs1[i-2];
7069           }
7070           if(rs2[i-2]) {
7071             is32|=1LL<<rs2[i-2];
7072           }
7073         }
7074       }
7075     }
7076     // If something jumps here with 64-bit values
7077     // then promote those registers to 64 bits
7078     if(bt[i])
7079     {
7080       uint64_t temp_is32=is32;
7081       for(j=i-1;j>=0;j--)
7082       {
7083         if(ba[j]==start+i*4)
7084           //temp_is32&=branch_regs[j].is32;
7085           temp_is32&=p32[j];
7086       }
7087       for(j=i;j<slen;j++)
7088       {
7089         if(ba[j]==start+i*4)
7090           temp_is32=1;
7091       }
7092       is32=temp_is32;
7093     }
7094     int type=itype[i];
7095     int op=opcode[i];
7096     int op2=opcode2[i];
7097     int rt=rt1[i];
7098     int s1=rs1[i];
7099     int s2=rs2[i];
7100     if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
7101       // Branches don't write registers, consider the delay slot instead.
7102       type=itype[i+1];
7103       op=opcode[i+1];
7104       op2=opcode2[i+1];
7105       rt=rt1[i+1];
7106       s1=rs1[i+1];
7107       s2=rs2[i+1];
7108       lastbranch=is32;
7109     }
7110     switch(type) {
7111       case LOAD:
7112         if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
7113            opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
7114           is32&=~(1LL<<rt);
7115         else
7116           is32|=1LL<<rt;
7117         break;
7118       case STORE:
7119       case STORELR:
7120         break;
7121       case LOADLR:
7122         if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
7123         if(op==0x22) is32|=1LL<<rt; // LWL
7124         break;
7125       case IMM16:
7126         if (op==0x08||op==0x09|| // ADDI/ADDIU
7127             op==0x0a||op==0x0b|| // SLTI/SLTIU
7128             op==0x0c|| // ANDI
7129             op==0x0f)  // LUI
7130         {
7131           is32|=1LL<<rt;
7132         }
7133         if(op==0x18||op==0x19) { // DADDI/DADDIU
7134           is32&=~(1LL<<rt);
7135           //if(imm[i]==0)
7136           //  is32|=((is32>>s1)&1LL)<<rt;
7137         }
7138         if(op==0x0d||op==0x0e) { // ORI/XORI
7139           uint64_t sr=((is32>>s1)&1LL);
7140           is32&=~(1LL<<rt);
7141           is32|=sr<<rt;
7142         }
7143         break;
7144       case UJUMP:
7145         break;
7146       case RJUMP:
7147         break;
7148       case CJUMP:
7149         break;
7150       case SJUMP:
7151         break;
7152       case FJUMP:
7153         break;
7154       case ALU:
7155         if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
7156           is32|=1LL<<rt;
7157         }
7158         if(op2==0x2a||op2==0x2b) { // SLT/SLTU
7159           is32|=1LL<<rt;
7160         }
7161         else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
7162           uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
7163           is32&=~(1LL<<rt);
7164           is32|=sr<<rt;
7165         }
7166         else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
7167           if(s1==0&&s2==0) {
7168             is32|=1LL<<rt;
7169           }
7170           else if(s2==0) {
7171             uint64_t sr=((is32>>s1)&1LL);
7172             is32&=~(1LL<<rt);
7173             is32|=sr<<rt;
7174           }
7175           else if(s1==0) {
7176             uint64_t sr=((is32>>s2)&1LL);
7177             is32&=~(1LL<<rt);
7178             is32|=sr<<rt;
7179           }
7180           else {
7181             is32&=~(1LL<<rt);
7182           }
7183         }
7184         else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
7185           if(s1==0&&s2==0) {
7186             is32|=1LL<<rt;
7187           }
7188           else if(s2==0) {
7189             uint64_t sr=((is32>>s1)&1LL);
7190             is32&=~(1LL<<rt);
7191             is32|=sr<<rt;
7192           }
7193           else {
7194             is32&=~(1LL<<rt);
7195           }
7196         }
7197         break;
7198       case MULTDIV:
7199         if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
7200           is32&=~((1LL<<HIREG)|(1LL<<LOREG));
7201         }
7202         else {
7203           is32|=(1LL<<HIREG)|(1LL<<LOREG);
7204         }
7205         break;
7206       case MOV:
7207         {
7208           uint64_t sr=((is32>>s1)&1LL);
7209           is32&=~(1LL<<rt);
7210           is32|=sr<<rt;
7211         }
7212         break;
7213       case SHIFT:
7214         if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
7215         else is32|=1LL<<rt; // SLLV/SRLV/SRAV
7216         break;
7217       case SHIFTIMM:
7218         is32|=1LL<<rt;
7219         // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
7220         if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
7221         break;
7222       case COP0:
7223         if(op2==0) is32|=1LL<<rt; // MFC0
7224         break;
7225       case COP1:
7226       case COP2:
7227         if(op2==0) is32|=1LL<<rt; // MFC1
7228         if(op2==1) is32&=~(1LL<<rt); // DMFC1
7229         if(op2==2) is32|=1LL<<rt; // CFC1
7230         break;
7231       case C1LS:
7232       case C2LS:
7233         break;
7234       case FLOAT:
7235       case FCONV:
7236         break;
7237       case FCOMP:
7238         break;
7239       case C2OP:
7240       case SYSCALL:
7241       case HLECALL:
7242         break;
7243       default:
7244         break;
7245     }
7246     is32|=1;
7247     p32[i]=is32;
7248
7249     if(i>0)
7250     {
7251       if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
7252       {
7253         if(rt1[i-1]==31) // JAL/JALR
7254         {
7255           // Subroutine call will return here, don't alloc any registers
7256           is32=1;
7257         }
7258         else if(i+1<slen)
7259         {
7260           // Internal branch will jump here, match registers to caller
7261           is32=0x3FFFFFFFFLL;
7262         }
7263       }
7264     }
7265   }
7266 }
7267
7268 // Identify registers which may be assumed to contain 32-bit values
7269 // and where optimizations will rely on this.
7270 // This is used to determine whether backward branches can safely
7271 // jump to a location with 64-bit values in registers.
7272 static void provisional_r32()
7273 {
7274   u_int r32=0;
7275   int i;
7276
7277   for (i=slen-1;i>=0;i--)
7278   {
7279     int hr;
7280     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7281     {
7282       if(ba[i]<start || ba[i]>=(start+slen*4))
7283       {
7284         // Branch out of this block, don't need anything
7285         r32=0;
7286       }
7287       else
7288       {
7289         // Internal branch
7290         // Need whatever matches the target
7291         // (and doesn't get overwritten by the delay slot instruction)
7292         r32=0;
7293         int t=(ba[i]-start)>>2;
7294         if(ba[i]>start+i*4) {
7295           // Forward branch
7296           //if(!(requires_32bit[t]&~regs[i].was32))
7297           //  r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7298           if(!(pr32[t]&~regs[i].was32))
7299             r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7300         }else{
7301           // Backward branch
7302           if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
7303             r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7304         }
7305       }
7306       // Conditional branch may need registers for following instructions
7307       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7308       {
7309         if(i<slen-2) {
7310           //r32|=requires_32bit[i+2];
7311           r32|=pr32[i+2];
7312           r32&=regs[i].was32;
7313           // Mark this address as a branch target since it may be called
7314           // upon return from interrupt
7315           //bt[i+2]=1;
7316         }
7317       }
7318       // Merge in delay slot
7319       if(!likely[i]) {
7320         // These are overwritten unless the branch is "likely"
7321         // and the delay slot is nullified if not taken
7322         r32&=~(1LL<<rt1[i+1]);
7323         r32&=~(1LL<<rt2[i+1]);
7324       }
7325       // Assume these are needed (delay slot)
7326       if(us1[i+1]>0)
7327       {
7328         if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7329       }
7330       if(us2[i+1]>0)
7331       {
7332         if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7333       }
7334       if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7335       {
7336         if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7337       }
7338       if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7339       {
7340         if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7341       }
7342     }
7343     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7344     {
7345       // SYSCALL instruction (software interrupt)
7346       r32=0;
7347     }
7348     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7349     {
7350       // ERET instruction (return from interrupt)
7351       r32=0;
7352     }
7353     // Check 32 bits
7354     r32&=~(1LL<<rt1[i]);
7355     r32&=~(1LL<<rt2[i]);
7356     if(us1[i]>0)
7357     {
7358       if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7359     }
7360     if(us2[i]>0)
7361     {
7362       if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7363     }
7364     if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7365     {
7366       if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7367     }
7368     if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7369     {
7370       if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7371     }
7372     //requires_32bit[i]=r32;
7373     pr32[i]=r32;
7374
7375     // Dirty registers which are 32-bit, require 32-bit input
7376     // as they will be written as 32-bit values
7377     for(hr=0;hr<HOST_REGS;hr++)
7378     {
7379       if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
7380         if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7381           if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7382           pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7383           //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7384         }
7385       }
7386     }
7387   }
7388 }
7389
7390 // Write back dirty registers as soon as we will no longer modify them,
7391 // so that we don't end up with lots of writes at the branches.
7392 void clean_registers(int istart,int iend,int wr)
7393 {
7394   int i;
7395   int r;
7396   u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7397   u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7398   if(iend==slen-1) {
7399     will_dirty_i=will_dirty_next=0;
7400     wont_dirty_i=wont_dirty_next=0;
7401   }else{
7402     will_dirty_i=will_dirty_next=will_dirty[iend+1];
7403     wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7404   }
7405   for (i=iend;i>=istart;i--)
7406   {
7407     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7408     {
7409       if(ba[i]<start || ba[i]>=(start+slen*4))
7410       {
7411         // Branch out of this block, flush all regs
7412         if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7413         {
7414           // Unconditional branch
7415           will_dirty_i=0;
7416           wont_dirty_i=0;
7417           // Merge in delay slot (will dirty)
7418           for(r=0;r<HOST_REGS;r++) {
7419             if(r!=EXCLUDE_REG) {
7420               if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7421               if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7422               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7423               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7424               if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7425               if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7426               if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7427               if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7428               if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7429               if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7430               if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7431               if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7432               if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7433               if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7434             }
7435           }
7436         }
7437         else
7438         {
7439           // Conditional branch
7440           will_dirty_i=0;
7441           wont_dirty_i=wont_dirty_next;
7442           // Merge in delay slot (will dirty)
7443           for(r=0;r<HOST_REGS;r++) {
7444             if(r!=EXCLUDE_REG) {
7445               if(!likely[i]) {
7446                 // Might not dirty if likely branch is not taken
7447                 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7448                 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7449                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7450                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7451                 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7452                 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7453                 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7454                 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7455                 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7456                 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7457                 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7458                 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7459                 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7460                 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7461               }
7462             }
7463           }
7464         }
7465         // Merge in delay slot (wont dirty)
7466         for(r=0;r<HOST_REGS;r++) {
7467           if(r!=EXCLUDE_REG) {
7468             if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7469             if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7470             if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7471             if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7472             if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7473             if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7474             if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7475             if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7476             if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7477             if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7478           }
7479         }
7480         if(wr) {
7481           #ifndef DESTRUCTIVE_WRITEBACK
7482           branch_regs[i].dirty&=wont_dirty_i;
7483           #endif
7484           branch_regs[i].dirty|=will_dirty_i;
7485         }
7486       }
7487       else
7488       {
7489         // Internal branch
7490         if(ba[i]<=start+i*4) {
7491           // Backward branch
7492           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7493           {
7494             // Unconditional branch
7495             temp_will_dirty=0;
7496             temp_wont_dirty=0;
7497             // Merge in delay slot (will dirty)
7498             for(r=0;r<HOST_REGS;r++) {
7499               if(r!=EXCLUDE_REG) {
7500                 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7501                 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7502                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7503                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7504                 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7505                 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7506                 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7507                 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7508                 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7509                 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7510                 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7511                 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7512                 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7513                 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7514               }
7515             }
7516           } else {
7517             // Conditional branch (not taken case)
7518             temp_will_dirty=will_dirty_next;
7519             temp_wont_dirty=wont_dirty_next;
7520             // Merge in delay slot (will dirty)
7521             for(r=0;r<HOST_REGS;r++) {
7522               if(r!=EXCLUDE_REG) {
7523                 if(!likely[i]) {
7524                   // Will not dirty if likely branch is not taken
7525                   if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7526                   if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7527                   if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7528                   if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7529                   if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7530                   if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7531                   if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7532                   //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7533                   //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7534                   if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7535                   if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7536                   if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7537                   if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7538                   if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7539                 }
7540               }
7541             }
7542           }
7543           // Merge in delay slot (wont dirty)
7544           for(r=0;r<HOST_REGS;r++) {
7545             if(r!=EXCLUDE_REG) {
7546               if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7547               if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7548               if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7549               if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7550               if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7551               if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7552               if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7553               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7554               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7555               if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7556             }
7557           }
7558           // Deal with changed mappings
7559           if(i<iend) {
7560             for(r=0;r<HOST_REGS;r++) {
7561               if(r!=EXCLUDE_REG) {
7562                 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7563                   temp_will_dirty&=~(1<<r);
7564                   temp_wont_dirty&=~(1<<r);
7565                   if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7566                     temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7567                     temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7568                   } else {
7569                     temp_will_dirty|=1<<r;
7570                     temp_wont_dirty|=1<<r;
7571                   }
7572                 }
7573               }
7574             }
7575           }
7576           if(wr) {
7577             will_dirty[i]=temp_will_dirty;
7578             wont_dirty[i]=temp_wont_dirty;
7579             clean_registers((ba[i]-start)>>2,i-1,0);
7580           }else{
7581             // Limit recursion.  It can take an excessive amount
7582             // of time if there are a lot of nested loops.
7583             will_dirty[(ba[i]-start)>>2]=0;
7584             wont_dirty[(ba[i]-start)>>2]=-1;
7585           }
7586         }
7587         /*else*/ if(1)
7588         {
7589           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7590           {
7591             // Unconditional branch
7592             will_dirty_i=0;
7593             wont_dirty_i=0;
7594           //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7595             for(r=0;r<HOST_REGS;r++) {
7596               if(r!=EXCLUDE_REG) {
7597                 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7598                   will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7599                   wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7600                 }
7601                 if(branch_regs[i].regmap[r]>=0) {
7602                   will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7603                   wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7604                 }
7605               }
7606             }
7607           //}
7608             // Merge in delay slot
7609             for(r=0;r<HOST_REGS;r++) {
7610               if(r!=EXCLUDE_REG) {
7611                 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7612                 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7613                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7614                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7615                 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7616                 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7617                 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7618                 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7619                 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7620                 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7621                 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7622                 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7623                 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7624                 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7625               }
7626             }
7627           } else {
7628             // Conditional branch
7629             will_dirty_i=will_dirty_next;
7630             wont_dirty_i=wont_dirty_next;
7631           //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7632             for(r=0;r<HOST_REGS;r++) {
7633               if(r!=EXCLUDE_REG) {
7634                 signed char target_reg=branch_regs[i].regmap[r];
7635                 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7636                   will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7637                   wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7638                 }
7639                 else if(target_reg>=0) {
7640                   will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7641                   wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7642                 }
7643                 // Treat delay slot as part of branch too
7644                 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7645                   will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7646                   wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7647                 }
7648                 else
7649                 {
7650                   will_dirty[i+1]&=~(1<<r);
7651                 }*/
7652               }
7653             }
7654           //}
7655             // Merge in delay slot
7656             for(r=0;r<HOST_REGS;r++) {
7657               if(r!=EXCLUDE_REG) {
7658                 if(!likely[i]) {
7659                   // Might not dirty if likely branch is not taken
7660                   if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7661                   if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7662                   if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7663                   if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7664                   if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7665                   if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7666                   if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7667                   //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7668                   //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7669                   if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7670                   if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7671                   if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7672                   if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7673                   if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7674                 }
7675               }
7676             }
7677           }
7678           // Merge in delay slot (won't dirty)
7679           for(r=0;r<HOST_REGS;r++) {
7680             if(r!=EXCLUDE_REG) {
7681               if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7682               if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7683               if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7684               if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7685               if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7686               if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7687               if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7688               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7689               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7690               if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7691             }
7692           }
7693           if(wr) {
7694             #ifndef DESTRUCTIVE_WRITEBACK
7695             branch_regs[i].dirty&=wont_dirty_i;
7696             #endif
7697             branch_regs[i].dirty|=will_dirty_i;
7698           }
7699         }
7700       }
7701     }
7702     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7703     {
7704       // SYSCALL instruction (software interrupt)
7705       will_dirty_i=0;
7706       wont_dirty_i=0;
7707     }
7708     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7709     {
7710       // ERET instruction (return from interrupt)
7711       will_dirty_i=0;
7712       wont_dirty_i=0;
7713     }
7714     will_dirty_next=will_dirty_i;
7715     wont_dirty_next=wont_dirty_i;
7716     for(r=0;r<HOST_REGS;r++) {
7717       if(r!=EXCLUDE_REG) {
7718         if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7719         if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7720         if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7721         if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7722         if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7723         if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7724         if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7725         if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7726         if(i>istart) {
7727           if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7728           {
7729             // Don't store a register immediately after writing it,
7730             // may prevent dual-issue.
7731             if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7732             if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7733           }
7734         }
7735       }
7736     }
7737     // Save it
7738     will_dirty[i]=will_dirty_i;
7739     wont_dirty[i]=wont_dirty_i;
7740     // Mark registers that won't be dirtied as not dirty
7741     if(wr) {
7742       /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7743       for(r=0;r<HOST_REGS;r++) {
7744         if((will_dirty_i>>r)&1) {
7745           printf(" r%d",r);
7746         }
7747       }
7748       printf("\n");*/
7749
7750       //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7751         regs[i].dirty|=will_dirty_i;
7752         #ifndef DESTRUCTIVE_WRITEBACK
7753         regs[i].dirty&=wont_dirty_i;
7754         if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7755         {
7756           if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7757             for(r=0;r<HOST_REGS;r++) {
7758               if(r!=EXCLUDE_REG) {
7759                 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7760                   regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7761                 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7762               }
7763             }
7764           }
7765         }
7766         else
7767         {
7768           if(i<iend) {
7769             for(r=0;r<HOST_REGS;r++) {
7770               if(r!=EXCLUDE_REG) {
7771                 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7772                   regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7773                 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7774               }
7775             }
7776           }
7777         }
7778         #endif
7779       //}
7780     }
7781     // Deal with changed mappings
7782     temp_will_dirty=will_dirty_i;
7783     temp_wont_dirty=wont_dirty_i;
7784     for(r=0;r<HOST_REGS;r++) {
7785       if(r!=EXCLUDE_REG) {
7786         int nr;
7787         if(regs[i].regmap[r]==regmap_pre[i][r]) {
7788           if(wr) {
7789             #ifndef DESTRUCTIVE_WRITEBACK
7790             regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7791             #endif
7792             regs[i].wasdirty|=will_dirty_i&(1<<r);
7793           }
7794         }
7795         else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7796           // Register moved to a different register
7797           will_dirty_i&=~(1<<r);
7798           wont_dirty_i&=~(1<<r);
7799           will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7800           wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7801           if(wr) {
7802             #ifndef DESTRUCTIVE_WRITEBACK
7803             regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7804             #endif
7805             regs[i].wasdirty|=will_dirty_i&(1<<r);
7806           }
7807         }
7808         else {
7809           will_dirty_i&=~(1<<r);
7810           wont_dirty_i&=~(1<<r);
7811           if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7812             will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7813             wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7814           } else {
7815             wont_dirty_i|=1<<r;
7816             /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7817           }
7818         }
7819       }
7820     }
7821   }
7822 }
7823
7824 #ifdef DISASM
7825   /* disassembly */
7826 void disassemble_inst(int i)
7827 {
7828     if (bt[i]) printf("*"); else printf(" ");
7829     switch(itype[i]) {
7830       case UJUMP:
7831         printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7832       case CJUMP:
7833         printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7834       case SJUMP:
7835         printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7836       case FJUMP:
7837         printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7838       case RJUMP:
7839         if (opcode[i]==0x9&&rt1[i]!=31)
7840           printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7841         else
7842           printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7843         break;
7844       case SPAN:
7845         printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7846       case IMM16:
7847         if(opcode[i]==0xf) //LUI
7848           printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7849         else
7850           printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7851         break;
7852       case LOAD:
7853       case LOADLR:
7854         printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7855         break;
7856       case STORE:
7857       case STORELR:
7858         printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7859         break;
7860       case ALU:
7861       case SHIFT:
7862         printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7863         break;
7864       case MULTDIV:
7865         printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7866         break;
7867       case SHIFTIMM:
7868         printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7869         break;
7870       case MOV:
7871         if((opcode2[i]&0x1d)==0x10)
7872           printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7873         else if((opcode2[i]&0x1d)==0x11)
7874           printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7875         else
7876           printf (" %x: %s\n",start+i*4,insn[i]);
7877         break;
7878       case COP0:
7879         if(opcode2[i]==0)
7880           printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7881         else if(opcode2[i]==4)
7882           printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7883         else printf (" %x: %s\n",start+i*4,insn[i]);
7884         break;
7885       case COP1:
7886         if(opcode2[i]<3)
7887           printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7888         else if(opcode2[i]>3)
7889           printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7890         else printf (" %x: %s\n",start+i*4,insn[i]);
7891         break;
7892       case COP2:
7893         if(opcode2[i]<3)
7894           printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7895         else if(opcode2[i]>3)
7896           printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7897         else printf (" %x: %s\n",start+i*4,insn[i]);
7898         break;
7899       case C1LS:
7900         printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7901         break;
7902       case C2LS:
7903         printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7904         break;
7905       case INTCALL:
7906         printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
7907         break;
7908       default:
7909         //printf (" %s %8x\n",insn[i],source[i]);
7910         printf (" %x: %s\n",start+i*4,insn[i]);
7911     }
7912 }
7913 #else
7914 static void disassemble_inst(int i) {}
7915 #endif // DISASM
7916
7917 #define DRC_TEST_VAL 0x74657374
7918
7919 static int new_dynarec_test(void)
7920 {
7921   int (*testfunc)(void) = (void *)out;
7922   int ret;
7923   emit_movimm(DRC_TEST_VAL,0); // test
7924   emit_jmpreg(14);
7925   literal_pool(0);
7926 #ifdef __arm__
7927   __clear_cache((void *)testfunc, out);
7928 #endif
7929   SysPrintf("testing if we can run recompiled code..\n");
7930   ret = testfunc();
7931   if (ret == DRC_TEST_VAL)
7932     SysPrintf("test passed.\n");
7933   else
7934     SysPrintf("test failed: %08x\n", ret);
7935   out=(u_char *)BASE_ADDR;
7936   return ret == DRC_TEST_VAL;
7937 }
7938
7939 // clear the state completely, instead of just marking
7940 // things invalid like invalidate_all_pages() does
7941 void new_dynarec_clear_full()
7942 {
7943   int n;
7944   out=(u_char *)BASE_ADDR;
7945   memset(invalid_code,1,sizeof(invalid_code));
7946   memset(hash_table,0xff,sizeof(hash_table));
7947   memset(mini_ht,-1,sizeof(mini_ht));
7948   memset(restore_candidate,0,sizeof(restore_candidate));
7949   memset(shadow,0,sizeof(shadow));
7950   copy=shadow;
7951   expirep=16384; // Expiry pointer, +2 blocks
7952   pending_exception=0;
7953   literalcount=0;
7954   stop_after_jal=0;
7955   inv_code_start=inv_code_end=~0;
7956   // TLB
7957 #ifndef DISABLE_TLB
7958   using_tlb=0;
7959   for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7960     memory_map[n]=-1;
7961   for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7962     memory_map[n]=((u_int)rdram-0x80000000)>>2;
7963   for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7964     memory_map[n]=-1;
7965 #endif
7966   for(n=0;n<4096;n++) ll_clear(jump_in+n);
7967   for(n=0;n<4096;n++) ll_clear(jump_out+n);
7968   for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7969 }
7970
7971 void new_dynarec_init()
7972 {
7973   SysPrintf("Init new dynarec\n");
7974   out=(u_char *)BASE_ADDR;
7975 #if BASE_ADDR_FIXED
7976   if (mmap (out, 1<<TARGET_SIZE_2,
7977             PROT_READ | PROT_WRITE | PROT_EXEC,
7978             MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
7979             -1, 0) <= 0) {
7980     SysPrintf("mmap() failed: %s\n", strerror(errno));
7981   }
7982 #else
7983   // not all systems allow execute in data segment by default
7984   if (mprotect(out, 1<<TARGET_SIZE_2, PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
7985     SysPrintf("mprotect() failed: %s\n", strerror(errno));
7986 #endif
7987 #ifdef MUPEN64
7988   rdword=&readmem_dword;
7989   fake_pc.f.r.rs=&readmem_dword;
7990   fake_pc.f.r.rt=&readmem_dword;
7991   fake_pc.f.r.rd=&readmem_dword;
7992 #endif
7993   int n;
7994   cycle_multiplier=200;
7995   new_dynarec_clear_full();
7996 #ifdef HOST_IMM8
7997   // Copy this into local area so we don't have to put it in every literal pool
7998   invc_ptr=invalid_code;
7999 #endif
8000 #ifdef MUPEN64
8001   for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
8002     writemem[n] = write_nomem_new;
8003     writememb[n] = write_nomemb_new;
8004     writememh[n] = write_nomemh_new;
8005 #ifndef FORCE32
8006     writememd[n] = write_nomemd_new;
8007 #endif
8008     readmem[n] = read_nomem_new;
8009     readmemb[n] = read_nomemb_new;
8010     readmemh[n] = read_nomemh_new;
8011 #ifndef FORCE32
8012     readmemd[n] = read_nomemd_new;
8013 #endif
8014   }
8015   for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
8016     writemem[n] = write_rdram_new;
8017     writememb[n] = write_rdramb_new;
8018     writememh[n] = write_rdramh_new;
8019 #ifndef FORCE32
8020     writememd[n] = write_rdramd_new;
8021 #endif
8022   }
8023   for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
8024     writemem[n] = write_nomem_new;
8025     writememb[n] = write_nomemb_new;
8026     writememh[n] = write_nomemh_new;
8027 #ifndef FORCE32
8028     writememd[n] = write_nomemd_new;
8029 #endif
8030     readmem[n] = read_nomem_new;
8031     readmemb[n] = read_nomemb_new;
8032     readmemh[n] = read_nomemh_new;
8033 #ifndef FORCE32
8034     readmemd[n] = read_nomemd_new;
8035 #endif
8036   }
8037 #endif
8038   tlb_hacks();
8039   arch_init();
8040   new_dynarec_test();
8041 #ifndef RAM_FIXED
8042   ram_offset=(u_int)rdram-0x80000000;
8043 #endif
8044   if (ram_offset!=0)
8045     SysPrintf("warning: RAM is not directly mapped, performance will suffer\n");
8046 }
8047
8048 void new_dynarec_cleanup()
8049 {
8050   int n;
8051   #if BASE_ADDR_FIXED
8052   if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {SysPrintf("munmap() failed\n");}
8053   #endif
8054   for(n=0;n<4096;n++) ll_clear(jump_in+n);
8055   for(n=0;n<4096;n++) ll_clear(jump_out+n);
8056   for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
8057   #ifdef ROM_COPY
8058   if (munmap (ROM_COPY, 67108864) < 0) {SysPrintf("munmap() failed\n");}
8059   #endif
8060 }
8061
8062 int new_recompile_block(int addr)
8063 {
8064 /*
8065   if(addr==0x800cd050) {
8066     int block;
8067     for(block=0x80000;block<0x80800;block++) invalidate_block(block);
8068     int n;
8069     for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
8070   }
8071 */
8072   //if(Count==365117028) tracedebug=1;
8073   assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
8074   //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
8075   //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
8076   //if(debug)
8077   //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
8078   //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
8079   /*if(Count>=312978186) {
8080     rlist();
8081   }*/
8082   //rlist();
8083   start = (u_int)addr&~3;
8084   //assert(((u_int)addr&1)==0);
8085   new_dynarec_did_compile=1;
8086 #ifdef PCSX
8087   if (Config.HLE && start == 0x80001000) // hlecall
8088   {
8089     // XXX: is this enough? Maybe check hleSoftCall?
8090     u_int beginning=(u_int)out;
8091     u_int page=get_page(start);
8092     invalid_code[start>>12]=0;
8093     emit_movimm(start,0);
8094     emit_writeword(0,(int)&pcaddr);
8095     emit_jmp((int)new_dyna_leave);
8096     literal_pool(0);
8097 #ifdef __arm__
8098     __clear_cache((void *)beginning,out);
8099 #endif
8100     ll_add(jump_in+page,start,(void *)beginning);
8101     return 0;
8102   }
8103   else if ((u_int)addr < 0x00200000 ||
8104     (0xa0000000 <= addr && addr < 0xa0200000)) {
8105     // used for BIOS calls mostly?
8106     source = (u_int *)((u_int)rdram+(start&0x1fffff));
8107     pagelimit = (addr&0xa0000000)|0x00200000;
8108   }
8109   else if (!Config.HLE && (
8110 /*    (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
8111     (0xbfc00000 <= addr && addr < 0xbfc80000))) {
8112     // BIOS
8113     source = (u_int *)((u_int)psxR+(start&0x7ffff));
8114     pagelimit = (addr&0xfff00000)|0x80000;
8115   }
8116   else
8117 #endif
8118 #ifdef MUPEN64
8119   if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
8120     source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
8121     pagelimit = 0xa4001000;
8122   }
8123   else
8124 #endif
8125   if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
8126     source = (u_int *)((u_int)rdram+start-0x80000000);
8127     pagelimit = 0x80000000+RAM_SIZE;
8128   }
8129 #ifndef DISABLE_TLB
8130   else if ((signed int)addr >= (signed int)0xC0000000) {
8131     //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
8132     //if(tlb_LUT_r[start>>12])
8133       //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
8134     if((signed int)memory_map[start>>12]>=0) {
8135       source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
8136       pagelimit=(start+4096)&0xFFFFF000;
8137       int map=memory_map[start>>12];
8138       int i;
8139       for(i=0;i<5;i++) {
8140         //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
8141         if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
8142       }
8143       assem_debug("pagelimit=%x\n",pagelimit);
8144       assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
8145     }
8146     else {
8147       assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
8148       //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
8149       return -1; // Caller will invoke exception handler
8150     }
8151     //printf("source= %x\n",(int)source);
8152   }
8153 #endif
8154   else {
8155     SysPrintf("Compile at bogus memory address: %x \n", (int)addr);
8156     exit(1);
8157   }
8158
8159   /* Pass 1: disassemble */
8160   /* Pass 2: register dependencies, branch targets */
8161   /* Pass 3: register allocation */
8162   /* Pass 4: branch dependencies */
8163   /* Pass 5: pre-alloc */
8164   /* Pass 6: optimize clean/dirty state */
8165   /* Pass 7: flag 32-bit registers */
8166   /* Pass 8: assembly */
8167   /* Pass 9: linker */
8168   /* Pass 10: garbage collection / free memory */
8169
8170   int i,j;
8171   int done=0;
8172   unsigned int type,op,op2;
8173
8174   //printf("addr = %x source = %x %x\n", addr,source,source[0]);
8175
8176   /* Pass 1 disassembly */
8177
8178   for(i=0;!done;i++) {
8179     bt[i]=0;likely[i]=0;ooo[i]=0;op2=0;
8180     minimum_free_regs[i]=0;
8181     opcode[i]=op=source[i]>>26;
8182     switch(op)
8183     {
8184       case 0x00: strcpy(insn[i],"special"); type=NI;
8185         op2=source[i]&0x3f;
8186         switch(op2)
8187         {
8188           case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
8189           case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
8190           case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
8191           case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
8192           case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
8193           case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
8194           case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
8195           case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
8196           case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
8197           case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
8198           case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
8199           case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
8200           case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
8201           case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
8202           case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
8203           case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
8204           case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
8205           case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
8206           case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
8207           case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
8208           case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
8209           case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
8210           case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
8211           case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
8212           case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
8213           case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
8214           case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
8215           case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
8216           case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
8217           case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
8218           case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
8219           case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
8220           case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
8221           case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
8222           case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
8223 #ifndef FORCE32
8224           case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
8225           case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
8226           case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
8227           case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
8228           case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
8229           case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
8230           case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
8231           case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
8232           case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
8233           case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
8234           case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
8235           case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
8236           case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
8237           case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
8238           case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
8239           case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
8240           case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
8241 #endif
8242         }
8243         break;
8244       case 0x01: strcpy(insn[i],"regimm"); type=NI;
8245         op2=(source[i]>>16)&0x1f;
8246         switch(op2)
8247         {
8248           case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
8249           case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
8250           case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
8251           case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
8252           case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
8253           case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
8254           case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
8255           case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
8256           case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
8257           case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
8258           case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
8259           case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
8260           case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
8261           case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
8262         }
8263         break;
8264       case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
8265       case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
8266       case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
8267       case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
8268       case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
8269       case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
8270       case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
8271       case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
8272       case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
8273       case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
8274       case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
8275       case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
8276       case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
8277       case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
8278       case 0x10: strcpy(insn[i],"cop0"); type=NI;
8279         op2=(source[i]>>21)&0x1f;
8280         switch(op2)
8281         {
8282           case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
8283           case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
8284           case 0x10: strcpy(insn[i],"tlb"); type=NI;
8285           switch(source[i]&0x3f)
8286           {
8287             case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
8288             case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
8289             case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
8290             case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
8291 #ifdef PCSX
8292             case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
8293 #else
8294             case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
8295 #endif
8296           }
8297         }
8298         break;
8299       case 0x11: strcpy(insn[i],"cop1"); type=NI;
8300         op2=(source[i]>>21)&0x1f;
8301         switch(op2)
8302         {
8303           case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
8304           case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
8305           case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
8306           case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
8307           case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
8308           case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
8309           case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
8310           switch((source[i]>>16)&0x3)
8311           {
8312             case 0x00: strcpy(insn[i],"BC1F"); break;
8313             case 0x01: strcpy(insn[i],"BC1T"); break;
8314             case 0x02: strcpy(insn[i],"BC1FL"); break;
8315             case 0x03: strcpy(insn[i],"BC1TL"); break;
8316           }
8317           break;
8318           case 0x10: strcpy(insn[i],"C1.S"); type=NI;
8319           switch(source[i]&0x3f)
8320           {
8321             case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
8322             case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
8323             case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
8324             case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
8325             case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
8326             case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
8327             case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
8328             case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
8329             case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
8330             case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
8331             case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
8332             case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
8333             case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
8334             case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
8335             case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
8336             case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
8337             case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
8338             case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
8339             case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
8340             case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
8341             case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
8342             case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
8343             case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
8344             case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
8345             case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
8346             case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
8347             case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
8348             case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
8349             case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
8350             case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
8351             case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
8352             case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
8353             case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
8354             case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
8355             case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
8356           }
8357           break;
8358           case 0x11: strcpy(insn[i],"C1.D"); type=NI;
8359           switch(source[i]&0x3f)
8360           {
8361             case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
8362             case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
8363             case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
8364             case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
8365             case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
8366             case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
8367             case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
8368             case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
8369             case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
8370             case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
8371             case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
8372             case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
8373             case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
8374             case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
8375             case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
8376             case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
8377             case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
8378             case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
8379             case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
8380             case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
8381             case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
8382             case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
8383             case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
8384             case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
8385             case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
8386             case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
8387             case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
8388             case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
8389             case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
8390             case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
8391             case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8392             case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8393             case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8394             case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8395             case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8396           }
8397           break;
8398           case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8399           switch(source[i]&0x3f)
8400           {
8401             case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8402             case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8403           }
8404           break;
8405           case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8406           switch(source[i]&0x3f)
8407           {
8408             case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8409             case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8410           }
8411           break;
8412         }
8413         break;
8414 #ifndef FORCE32
8415       case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8416       case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8417       case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8418       case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8419       case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8420       case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8421       case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8422       case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
8423 #endif
8424       case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8425       case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8426       case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8427       case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8428       case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8429       case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8430       case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
8431 #ifndef FORCE32
8432       case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
8433 #endif
8434       case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8435       case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8436       case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8437       case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
8438 #ifndef FORCE32
8439       case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8440       case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
8441 #endif
8442       case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8443       case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8444       case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8445       case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
8446 #ifndef FORCE32
8447       case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8448       case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8449       case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
8450 #endif
8451       case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8452       case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
8453 #ifndef FORCE32
8454       case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8455       case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8456       case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
8457 #endif
8458 #ifdef PCSX
8459       case 0x12: strcpy(insn[i],"COP2"); type=NI;
8460         op2=(source[i]>>21)&0x1f;
8461         //if (op2 & 0x10) {
8462         if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
8463           if (gte_handlers[source[i]&0x3f]!=NULL) {
8464             if (gte_regnames[source[i]&0x3f]!=NULL)
8465               strcpy(insn[i],gte_regnames[source[i]&0x3f]);
8466             else
8467               snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8468             type=C2OP;
8469           }
8470         }
8471         else switch(op2)
8472         {
8473           case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8474           case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8475           case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8476           case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
8477         }
8478         break;
8479       case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8480       case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8481       case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8482 #endif
8483       default: strcpy(insn[i],"???"); type=NI;
8484         SysPrintf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
8485         break;
8486     }
8487     itype[i]=type;
8488     opcode2[i]=op2;
8489     /* Get registers/immediates */
8490     lt1[i]=0;
8491     us1[i]=0;
8492     us2[i]=0;
8493     dep1[i]=0;
8494     dep2[i]=0;
8495     gte_rs[i]=gte_rt[i]=0;
8496     switch(type) {
8497       case LOAD:
8498         rs1[i]=(source[i]>>21)&0x1f;
8499         rs2[i]=0;
8500         rt1[i]=(source[i]>>16)&0x1f;
8501         rt2[i]=0;
8502         imm[i]=(short)source[i];
8503         break;
8504       case STORE:
8505       case STORELR:
8506         rs1[i]=(source[i]>>21)&0x1f;
8507         rs2[i]=(source[i]>>16)&0x1f;
8508         rt1[i]=0;
8509         rt2[i]=0;
8510         imm[i]=(short)source[i];
8511         if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8512         break;
8513       case LOADLR:
8514         // LWL/LWR only load part of the register,
8515         // therefore the target register must be treated as a source too
8516         rs1[i]=(source[i]>>21)&0x1f;
8517         rs2[i]=(source[i]>>16)&0x1f;
8518         rt1[i]=(source[i]>>16)&0x1f;
8519         rt2[i]=0;
8520         imm[i]=(short)source[i];
8521         if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8522         if(op==0x26) dep1[i]=rt1[i]; // LWR
8523         break;
8524       case IMM16:
8525         if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8526         else rs1[i]=(source[i]>>21)&0x1f;
8527         rs2[i]=0;
8528         rt1[i]=(source[i]>>16)&0x1f;
8529         rt2[i]=0;
8530         if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8531           imm[i]=(unsigned short)source[i];
8532         }else{
8533           imm[i]=(short)source[i];
8534         }
8535         if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8536         if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8537         if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8538         break;
8539       case UJUMP:
8540         rs1[i]=0;
8541         rs2[i]=0;
8542         rt1[i]=0;
8543         rt2[i]=0;
8544         // The JAL instruction writes to r31.
8545         if (op&1) {
8546           rt1[i]=31;
8547         }
8548         rs2[i]=CCREG;
8549         break;
8550       case RJUMP:
8551         rs1[i]=(source[i]>>21)&0x1f;
8552         rs2[i]=0;
8553         rt1[i]=0;
8554         rt2[i]=0;
8555         // The JALR instruction writes to rd.
8556         if (op2&1) {
8557           rt1[i]=(source[i]>>11)&0x1f;
8558         }
8559         rs2[i]=CCREG;
8560         break;
8561       case CJUMP:
8562         rs1[i]=(source[i]>>21)&0x1f;
8563         rs2[i]=(source[i]>>16)&0x1f;
8564         rt1[i]=0;
8565         rt2[i]=0;
8566         if(op&2) { // BGTZ/BLEZ
8567           rs2[i]=0;
8568         }
8569         us1[i]=rs1[i];
8570         us2[i]=rs2[i];
8571         likely[i]=op>>4;
8572         break;
8573       case SJUMP:
8574         rs1[i]=(source[i]>>21)&0x1f;
8575         rs2[i]=CCREG;
8576         rt1[i]=0;
8577         rt2[i]=0;
8578         us1[i]=rs1[i];
8579         if(op2&0x10) { // BxxAL
8580           rt1[i]=31;
8581           // NOTE: If the branch is not taken, r31 is still overwritten
8582         }
8583         likely[i]=(op2&2)>>1;
8584         break;
8585       case FJUMP:
8586         rs1[i]=FSREG;
8587         rs2[i]=CSREG;
8588         rt1[i]=0;
8589         rt2[i]=0;
8590         likely[i]=((source[i])>>17)&1;
8591         break;
8592       case ALU:
8593         rs1[i]=(source[i]>>21)&0x1f; // source
8594         rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8595         rt1[i]=(source[i]>>11)&0x1f; // destination
8596         rt2[i]=0;
8597         if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8598           us1[i]=rs1[i];us2[i]=rs2[i];
8599         }
8600         else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8601           dep1[i]=rs1[i];dep2[i]=rs2[i];
8602         }
8603         else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8604           dep1[i]=rs1[i];dep2[i]=rs2[i];
8605         }
8606         break;
8607       case MULTDIV:
8608         rs1[i]=(source[i]>>21)&0x1f; // source
8609         rs2[i]=(source[i]>>16)&0x1f; // divisor
8610         rt1[i]=HIREG;
8611         rt2[i]=LOREG;
8612         if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8613           us1[i]=rs1[i];us2[i]=rs2[i];
8614         }
8615         break;
8616       case MOV:
8617         rs1[i]=0;
8618         rs2[i]=0;
8619         rt1[i]=0;
8620         rt2[i]=0;
8621         if(op2==0x10) rs1[i]=HIREG; // MFHI
8622         if(op2==0x11) rt1[i]=HIREG; // MTHI
8623         if(op2==0x12) rs1[i]=LOREG; // MFLO
8624         if(op2==0x13) rt1[i]=LOREG; // MTLO
8625         if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8626         if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8627         dep1[i]=rs1[i];
8628         break;
8629       case SHIFT:
8630         rs1[i]=(source[i]>>16)&0x1f; // target of shift
8631         rs2[i]=(source[i]>>21)&0x1f; // shift amount
8632         rt1[i]=(source[i]>>11)&0x1f; // destination
8633         rt2[i]=0;
8634         // DSLLV/DSRLV/DSRAV are 64-bit
8635         if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8636         break;
8637       case SHIFTIMM:
8638         rs1[i]=(source[i]>>16)&0x1f;
8639         rs2[i]=0;
8640         rt1[i]=(source[i]>>11)&0x1f;
8641         rt2[i]=0;
8642         imm[i]=(source[i]>>6)&0x1f;
8643         // DSxx32 instructions
8644         if(op2>=0x3c) imm[i]|=0x20;
8645         // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8646         if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8647         break;
8648       case COP0:
8649         rs1[i]=0;
8650         rs2[i]=0;
8651         rt1[i]=0;
8652         rt2[i]=0;
8653         if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8654         if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8655         if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8656         if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8657         break;
8658       case COP1:
8659         rs1[i]=0;
8660         rs2[i]=0;
8661         rt1[i]=0;
8662         rt2[i]=0;
8663         if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8664         if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8665         if(op2==5) us1[i]=rs1[i]; // DMTC1
8666         rs2[i]=CSREG;
8667         break;
8668       case COP2:
8669         rs1[i]=0;
8670         rs2[i]=0;
8671         rt1[i]=0;
8672         rt2[i]=0;
8673         if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC2/CFC2
8674         if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC2/CTC2
8675         rs2[i]=CSREG;
8676         int gr=(source[i]>>11)&0x1F;
8677         switch(op2)
8678         {
8679           case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
8680           case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
8681           case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2
8682           case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
8683         }
8684         break;
8685       case C1LS:
8686         rs1[i]=(source[i]>>21)&0x1F;
8687         rs2[i]=CSREG;
8688         rt1[i]=0;
8689         rt2[i]=0;
8690         imm[i]=(short)source[i];
8691         break;
8692       case C2LS:
8693         rs1[i]=(source[i]>>21)&0x1F;
8694         rs2[i]=0;
8695         rt1[i]=0;
8696         rt2[i]=0;
8697         imm[i]=(short)source[i];
8698         if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
8699         else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
8700         break;
8701       case C2OP:
8702         rs1[i]=0;
8703         rs2[i]=0;
8704         rt1[i]=0;
8705         rt2[i]=0;
8706         gte_rs[i]=gte_reg_reads[source[i]&0x3f];
8707         gte_rt[i]=gte_reg_writes[source[i]&0x3f];
8708         gte_rt[i]|=1ll<<63; // every op changes flags
8709         if((source[i]&0x3f)==GTE_MVMVA) {
8710           int v = (source[i] >> 15) & 3;
8711           gte_rs[i]&=~0xe3fll;
8712           if(v==3) gte_rs[i]|=0xe00ll;
8713           else gte_rs[i]|=3ll<<(v*2);
8714         }
8715         break;
8716       case FLOAT:
8717       case FCONV:
8718         rs1[i]=0;
8719         rs2[i]=CSREG;
8720         rt1[i]=0;
8721         rt2[i]=0;
8722         break;
8723       case FCOMP:
8724         rs1[i]=FSREG;
8725         rs2[i]=CSREG;
8726         rt1[i]=FSREG;
8727         rt2[i]=0;
8728         break;
8729       case SYSCALL:
8730       case HLECALL:
8731       case INTCALL:
8732         rs1[i]=CCREG;
8733         rs2[i]=0;
8734         rt1[i]=0;
8735         rt2[i]=0;
8736         break;
8737       default:
8738         rs1[i]=0;
8739         rs2[i]=0;
8740         rt1[i]=0;
8741         rt2[i]=0;
8742     }
8743     /* Calculate branch target addresses */
8744     if(type==UJUMP)
8745       ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8746     else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8747       ba[i]=start+i*4+8; // Ignore never taken branch
8748     else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8749       ba[i]=start+i*4+8; // Ignore never taken branch
8750     else if(type==CJUMP||type==SJUMP||type==FJUMP)
8751       ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8752     else ba[i]=-1;
8753 #ifdef PCSX
8754     if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
8755       int do_in_intrp=0;
8756       // branch in delay slot?
8757       if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
8758         // don't handle first branch and call interpreter if it's hit
8759         SysPrintf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
8760         do_in_intrp=1;
8761       }
8762       // basic load delay detection
8763       else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&rt1[i]!=0) {
8764         int t=(ba[i-1]-start)/4;
8765         if(0 <= t && t < i &&(rt1[i]==rs1[t]||rt1[i]==rs2[t])&&itype[t]!=CJUMP&&itype[t]!=SJUMP) {
8766           // jump target wants DS result - potential load delay effect
8767           SysPrintf("load delay @%08x (%08x)\n", addr + i*4, addr);
8768           do_in_intrp=1;
8769           bt[t+1]=1; // expected return from interpreter
8770         }
8771         else if(i>=2&&rt1[i-2]==2&&rt1[i]==2&&rs1[i]!=2&&rs2[i]!=2&&rs1[i-1]!=2&&rs2[i-1]!=2&&
8772               !(i>=3&&(itype[i-3]==RJUMP||itype[i-3]==UJUMP||itype[i-3]==CJUMP||itype[i-3]==SJUMP))) {
8773           // v0 overwrite like this is a sign of trouble, bail out
8774           SysPrintf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
8775           do_in_intrp=1;
8776         }
8777       }
8778       if(do_in_intrp) {
8779         rs1[i-1]=CCREG;
8780         rs2[i-1]=rt1[i-1]=rt2[i-1]=0;
8781         ba[i-1]=-1;
8782         itype[i-1]=INTCALL;
8783         done=2;
8784         i--; // don't compile the DS
8785       }
8786     }
8787 #endif
8788     /* Is this the end of the block? */
8789     if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
8790       if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
8791         done=2;
8792       }
8793       else {
8794         if(stop_after_jal) done=1;
8795         // Stop on BREAK
8796         if((source[i+1]&0xfc00003f)==0x0d) done=1;
8797       }
8798       // Don't recompile stuff that's already compiled
8799       if(check_addr(start+i*4+4)) done=1;
8800       // Don't get too close to the limit
8801       if(i>MAXBLOCK/2) done=1;
8802     }
8803     if(itype[i]==SYSCALL&&stop_after_jal) done=1;
8804     if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
8805     if(done==2) {
8806       // Does the block continue due to a branch?
8807       for(j=i-1;j>=0;j--)
8808       {
8809         if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
8810         if(ba[j]==start+i*4+4) done=j=0;
8811         if(ba[j]==start+i*4+8) done=j=0;
8812       }
8813     }
8814     //assert(i<MAXBLOCK-1);
8815     if(start+i*4==pagelimit-4) done=1;
8816     assert(start+i*4<pagelimit);
8817     if (i==MAXBLOCK-1) done=1;
8818     // Stop if we're compiling junk
8819     if(itype[i]==NI&&opcode[i]==0x11) {
8820       done=stop_after_jal=1;
8821       SysPrintf("Disabled speculative precompilation\n");
8822     }
8823   }
8824   slen=i;
8825   if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8826     if(start+i*4==pagelimit) {
8827       itype[i-1]=SPAN;
8828     }
8829   }
8830   assert(slen>0);
8831
8832   /* Pass 2 - Register dependencies and branch targets */
8833
8834   unneeded_registers(0,slen-1,0);
8835
8836   /* Pass 3 - Register allocation */
8837
8838   struct regstat current; // Current register allocations/status
8839   current.is32=1;
8840   current.dirty=0;
8841   current.u=unneeded_reg[0];
8842   current.uu=unneeded_reg_upper[0];
8843   clear_all_regs(current.regmap);
8844   alloc_reg(&current,0,CCREG);
8845   dirty_reg(&current,CCREG);
8846   current.isconst=0;
8847   current.wasconst=0;
8848   current.waswritten=0;
8849   int ds=0;
8850   int cc=0;
8851   int hr=-1;
8852
8853 #ifndef FORCE32
8854   provisional_32bit();
8855 #endif
8856   if((u_int)addr&1) {
8857     // First instruction is delay slot
8858     cc=-1;
8859     bt[1]=1;
8860     ds=1;
8861     unneeded_reg[0]=1;
8862     unneeded_reg_upper[0]=1;
8863     current.regmap[HOST_BTREG]=BTREG;
8864   }
8865
8866   for(i=0;i<slen;i++)
8867   {
8868     if(bt[i])
8869     {
8870       int hr;
8871       for(hr=0;hr<HOST_REGS;hr++)
8872       {
8873         // Is this really necessary?
8874         if(current.regmap[hr]==0) current.regmap[hr]=-1;
8875       }
8876       current.isconst=0;
8877       current.waswritten=0;
8878     }
8879     if(i>1)
8880     {
8881       if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8882       {
8883         if(rs1[i-2]==0||rs2[i-2]==0)
8884         {
8885           if(rs1[i-2]) {
8886             current.is32|=1LL<<rs1[i-2];
8887             int hr=get_reg(current.regmap,rs1[i-2]|64);
8888             if(hr>=0) current.regmap[hr]=-1;
8889           }
8890           if(rs2[i-2]) {
8891             current.is32|=1LL<<rs2[i-2];
8892             int hr=get_reg(current.regmap,rs2[i-2]|64);
8893             if(hr>=0) current.regmap[hr]=-1;
8894           }
8895         }
8896       }
8897     }
8898 #ifndef FORCE32
8899     // If something jumps here with 64-bit values
8900     // then promote those registers to 64 bits
8901     if(bt[i])
8902     {
8903       uint64_t temp_is32=current.is32;
8904       for(j=i-1;j>=0;j--)
8905       {
8906         if(ba[j]==start+i*4)
8907           temp_is32&=branch_regs[j].is32;
8908       }
8909       for(j=i;j<slen;j++)
8910       {
8911         if(ba[j]==start+i*4)
8912           //temp_is32=1;
8913           temp_is32&=p32[j];
8914       }
8915       if(temp_is32!=current.is32) {
8916         //printf("dumping 32-bit regs (%x)\n",start+i*4);
8917         #ifndef DESTRUCTIVE_WRITEBACK
8918         if(ds)
8919         #endif
8920         for(hr=0;hr<HOST_REGS;hr++)
8921         {
8922           int r=current.regmap[hr];
8923           if(r>0&&r<64)
8924           {
8925             if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8926               temp_is32|=1LL<<r;
8927               //printf("restore %d\n",r);
8928             }
8929           }
8930         }
8931         current.is32=temp_is32;
8932       }
8933     }
8934 #else
8935     current.is32=-1LL;
8936 #endif
8937
8938     memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8939     regs[i].wasconst=current.isconst;
8940     regs[i].was32=current.is32;
8941     regs[i].wasdirty=current.dirty;
8942     regs[i].loadedconst=0;
8943     #if defined(DESTRUCTIVE_WRITEBACK) && !defined(FORCE32)
8944     // To change a dirty register from 32 to 64 bits, we must write
8945     // it out during the previous cycle (for branches, 2 cycles)
8946     if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8947     {
8948       uint64_t temp_is32=current.is32;
8949       for(j=i-1;j>=0;j--)
8950       {
8951         if(ba[j]==start+i*4+4)
8952           temp_is32&=branch_regs[j].is32;
8953       }
8954       for(j=i;j<slen;j++)
8955       {
8956         if(ba[j]==start+i*4+4)
8957           //temp_is32=1;
8958           temp_is32&=p32[j];
8959       }
8960       if(temp_is32!=current.is32) {
8961         //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8962         for(hr=0;hr<HOST_REGS;hr++)
8963         {
8964           int r=current.regmap[hr];
8965           if(r>0)
8966           {
8967             if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8968               if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
8969               {
8970                 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
8971                 {
8972                   //printf("dump %d/r%d\n",hr,r);
8973                   current.regmap[hr]=-1;
8974                   if(get_reg(current.regmap,r|64)>=0)
8975                     current.regmap[get_reg(current.regmap,r|64)]=-1;
8976                 }
8977               }
8978             }
8979           }
8980         }
8981       }
8982     }
8983     else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
8984     {
8985       uint64_t temp_is32=current.is32;
8986       for(j=i-1;j>=0;j--)
8987       {
8988         if(ba[j]==start+i*4+8)
8989           temp_is32&=branch_regs[j].is32;
8990       }
8991       for(j=i;j<slen;j++)
8992       {
8993         if(ba[j]==start+i*4+8)
8994           //temp_is32=1;
8995           temp_is32&=p32[j];
8996       }
8997       if(temp_is32!=current.is32) {
8998         //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8999         for(hr=0;hr<HOST_REGS;hr++)
9000         {
9001           int r=current.regmap[hr];
9002           if(r>0)
9003           {
9004             if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
9005               if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
9006               {
9007                 //printf("dump %d/r%d\n",hr,r);
9008                 current.regmap[hr]=-1;
9009                 if(get_reg(current.regmap,r|64)>=0)
9010                   current.regmap[get_reg(current.regmap,r|64)]=-1;
9011               }
9012             }
9013           }
9014         }
9015       }
9016     }
9017     #endif
9018     if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9019       if(i+1<slen) {
9020         current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9021         current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9022         if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9023         current.u|=1;
9024         current.uu|=1;
9025       } else {
9026         current.u=1;
9027         current.uu=1;
9028       }
9029     } else {
9030       if(i+1<slen) {
9031         current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
9032         current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9033         if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9034         current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
9035         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9036         current.u|=1;
9037         current.uu|=1;
9038       } else { SysPrintf("oops, branch at end of block with no delay slot\n");exit(1); }
9039     }
9040     is_ds[i]=ds;
9041     if(ds) {
9042       ds=0; // Skip delay slot, already allocated as part of branch
9043       // ...but we need to alloc it in case something jumps here
9044       if(i+1<slen) {
9045         current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
9046         current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
9047       }else{
9048         current.u=branch_unneeded_reg[i-1];
9049         current.uu=branch_unneeded_reg_upper[i-1];
9050       }
9051       current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
9052       current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9053       if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9054       current.u|=1;
9055       current.uu|=1;
9056       struct regstat temp;
9057       memcpy(&temp,&current,sizeof(current));
9058       temp.wasdirty=temp.dirty;
9059       temp.was32=temp.is32;
9060       // TODO: Take into account unconditional branches, as below
9061       delayslot_alloc(&temp,i);
9062       memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
9063       regs[i].wasdirty=temp.wasdirty;
9064       regs[i].was32=temp.was32;
9065       regs[i].dirty=temp.dirty;
9066       regs[i].is32=temp.is32;
9067       regs[i].isconst=0;
9068       regs[i].wasconst=0;
9069       current.isconst=0;
9070       // Create entry (branch target) regmap
9071       for(hr=0;hr<HOST_REGS;hr++)
9072       {
9073         int r=temp.regmap[hr];
9074         if(r>=0) {
9075           if(r!=regmap_pre[i][hr]) {
9076             regs[i].regmap_entry[hr]=-1;
9077           }
9078           else
9079           {
9080             if(r<64){
9081               if((current.u>>r)&1) {
9082                 regs[i].regmap_entry[hr]=-1;
9083                 regs[i].regmap[hr]=-1;
9084                 //Don't clear regs in the delay slot as the branch might need them
9085                 //current.regmap[hr]=-1;
9086               }else
9087                 regs[i].regmap_entry[hr]=r;
9088             }
9089             else {
9090               if((current.uu>>(r&63))&1) {
9091                 regs[i].regmap_entry[hr]=-1;
9092                 regs[i].regmap[hr]=-1;
9093                 //Don't clear regs in the delay slot as the branch might need them
9094                 //current.regmap[hr]=-1;
9095               }else
9096                 regs[i].regmap_entry[hr]=r;
9097             }
9098           }
9099         } else {
9100           // First instruction expects CCREG to be allocated
9101           if(i==0&&hr==HOST_CCREG)
9102             regs[i].regmap_entry[hr]=CCREG;
9103           else
9104             regs[i].regmap_entry[hr]=-1;
9105         }
9106       }
9107     }
9108     else { // Not delay slot
9109       switch(itype[i]) {
9110         case UJUMP:
9111           //current.isconst=0; // DEBUG
9112           //current.wasconst=0; // DEBUG
9113           //regs[i].wasconst=0; // DEBUG
9114           clear_const(&current,rt1[i]);
9115           alloc_cc(&current,i);
9116           dirty_reg(&current,CCREG);
9117           if (rt1[i]==31) {
9118             alloc_reg(&current,i,31);
9119             dirty_reg(&current,31);
9120             //assert(rs1[i+1]!=31&&rs2[i+1]!=31);
9121             //assert(rt1[i+1]!=rt1[i]);
9122             #ifdef REG_PREFETCH
9123             alloc_reg(&current,i,PTEMP);
9124             #endif
9125             //current.is32|=1LL<<rt1[i];
9126           }
9127           ooo[i]=1;
9128           delayslot_alloc(&current,i+1);
9129           //current.isconst=0; // DEBUG
9130           ds=1;
9131           //printf("i=%d, isconst=%x\n",i,current.isconst);
9132           break;
9133         case RJUMP:
9134           //current.isconst=0;
9135           //current.wasconst=0;
9136           //regs[i].wasconst=0;
9137           clear_const(&current,rs1[i]);
9138           clear_const(&current,rt1[i]);
9139           alloc_cc(&current,i);
9140           dirty_reg(&current,CCREG);
9141           if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
9142             alloc_reg(&current,i,rs1[i]);
9143             if (rt1[i]!=0) {
9144               alloc_reg(&current,i,rt1[i]);
9145               dirty_reg(&current,rt1[i]);
9146               assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
9147               assert(rt1[i+1]!=rt1[i]);
9148               #ifdef REG_PREFETCH
9149               alloc_reg(&current,i,PTEMP);
9150               #endif
9151             }
9152             #ifdef USE_MINI_HT
9153             if(rs1[i]==31) { // JALR
9154               alloc_reg(&current,i,RHASH);
9155               #ifndef HOST_IMM_ADDR32
9156               alloc_reg(&current,i,RHTBL);
9157               #endif
9158             }
9159             #endif
9160             delayslot_alloc(&current,i+1);
9161           } else {
9162             // The delay slot overwrites our source register,
9163             // allocate a temporary register to hold the old value.
9164             current.isconst=0;
9165             current.wasconst=0;
9166             regs[i].wasconst=0;
9167             delayslot_alloc(&current,i+1);
9168             current.isconst=0;
9169             alloc_reg(&current,i,RTEMP);
9170           }
9171           //current.isconst=0; // DEBUG
9172           ooo[i]=1;
9173           ds=1;
9174           break;
9175         case CJUMP:
9176           //current.isconst=0;
9177           //current.wasconst=0;
9178           //regs[i].wasconst=0;
9179           clear_const(&current,rs1[i]);
9180           clear_const(&current,rs2[i]);
9181           if((opcode[i]&0x3E)==4) // BEQ/BNE
9182           {
9183             alloc_cc(&current,i);
9184             dirty_reg(&current,CCREG);
9185             if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9186             if(rs2[i]) alloc_reg(&current,i,rs2[i]);
9187             if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9188             {
9189               if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9190               if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
9191             }
9192             if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
9193                (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
9194               // The delay slot overwrites one of our conditions.
9195               // Allocate the branch condition registers instead.
9196               current.isconst=0;
9197               current.wasconst=0;
9198               regs[i].wasconst=0;
9199               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9200               if(rs2[i]) alloc_reg(&current,i,rs2[i]);
9201               if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9202               {
9203                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9204                 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
9205               }
9206             }
9207             else
9208             {
9209               ooo[i]=1;
9210               delayslot_alloc(&current,i+1);
9211             }
9212           }
9213           else
9214           if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
9215           {
9216             alloc_cc(&current,i);
9217             dirty_reg(&current,CCREG);
9218             alloc_reg(&current,i,rs1[i]);
9219             if(!(current.is32>>rs1[i]&1))
9220             {
9221               alloc_reg64(&current,i,rs1[i]);
9222             }
9223             if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
9224               // The delay slot overwrites one of our conditions.
9225               // Allocate the branch condition registers instead.
9226               current.isconst=0;
9227               current.wasconst=0;
9228               regs[i].wasconst=0;
9229               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9230               if(!((current.is32>>rs1[i])&1))
9231               {
9232                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9233               }
9234             }
9235             else
9236             {
9237               ooo[i]=1;
9238               delayslot_alloc(&current,i+1);
9239             }
9240           }
9241           else
9242           // Don't alloc the delay slot yet because we might not execute it
9243           if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
9244           {
9245             current.isconst=0;
9246             current.wasconst=0;
9247             regs[i].wasconst=0;
9248             alloc_cc(&current,i);
9249             dirty_reg(&current,CCREG);
9250             alloc_reg(&current,i,rs1[i]);
9251             alloc_reg(&current,i,rs2[i]);
9252             if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9253             {
9254               alloc_reg64(&current,i,rs1[i]);
9255               alloc_reg64(&current,i,rs2[i]);
9256             }
9257           }
9258           else
9259           if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
9260           {
9261             current.isconst=0;
9262             current.wasconst=0;
9263             regs[i].wasconst=0;
9264             alloc_cc(&current,i);
9265             dirty_reg(&current,CCREG);
9266             alloc_reg(&current,i,rs1[i]);
9267             if(!(current.is32>>rs1[i]&1))
9268             {
9269               alloc_reg64(&current,i,rs1[i]);
9270             }
9271           }
9272           ds=1;
9273           //current.isconst=0;
9274           break;
9275         case SJUMP:
9276           //current.isconst=0;
9277           //current.wasconst=0;
9278           //regs[i].wasconst=0;
9279           clear_const(&current,rs1[i]);
9280           clear_const(&current,rt1[i]);
9281           //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
9282           if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
9283           {
9284             alloc_cc(&current,i);
9285             dirty_reg(&current,CCREG);
9286             alloc_reg(&current,i,rs1[i]);
9287             if(!(current.is32>>rs1[i]&1))
9288             {
9289               alloc_reg64(&current,i,rs1[i]);
9290             }
9291             if (rt1[i]==31) { // BLTZAL/BGEZAL
9292               alloc_reg(&current,i,31);
9293               dirty_reg(&current,31);
9294               //#ifdef REG_PREFETCH
9295               //alloc_reg(&current,i,PTEMP);
9296               //#endif
9297               //current.is32|=1LL<<rt1[i];
9298             }
9299             if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) // The delay slot overwrites the branch condition.
9300                ||(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))) { // DS touches $ra
9301               // Allocate the branch condition registers instead.
9302               current.isconst=0;
9303               current.wasconst=0;
9304               regs[i].wasconst=0;
9305               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9306               if(!((current.is32>>rs1[i])&1))
9307               {
9308                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9309               }
9310             }
9311             else
9312             {
9313               ooo[i]=1;
9314               delayslot_alloc(&current,i+1);
9315             }
9316           }
9317           else
9318           // Don't alloc the delay slot yet because we might not execute it
9319           if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
9320           {
9321             current.isconst=0;
9322             current.wasconst=0;
9323             regs[i].wasconst=0;
9324             alloc_cc(&current,i);
9325             dirty_reg(&current,CCREG);
9326             alloc_reg(&current,i,rs1[i]);
9327             if(!(current.is32>>rs1[i]&1))
9328             {
9329               alloc_reg64(&current,i,rs1[i]);
9330             }
9331           }
9332           ds=1;
9333           //current.isconst=0;
9334           break;
9335         case FJUMP:
9336           current.isconst=0;
9337           current.wasconst=0;
9338           regs[i].wasconst=0;
9339           if(likely[i]==0) // BC1F/BC1T
9340           {
9341             // TODO: Theoretically we can run out of registers here on x86.
9342             // The delay slot can allocate up to six, and we need to check
9343             // CSREG before executing the delay slot.  Possibly we can drop
9344             // the cycle count and then reload it after checking that the
9345             // FPU is in a usable state, or don't do out-of-order execution.
9346             alloc_cc(&current,i);
9347             dirty_reg(&current,CCREG);
9348             alloc_reg(&current,i,FSREG);
9349             alloc_reg(&current,i,CSREG);
9350             if(itype[i+1]==FCOMP) {
9351               // The delay slot overwrites the branch condition.
9352               // Allocate the branch condition registers instead.
9353               alloc_cc(&current,i);
9354               dirty_reg(&current,CCREG);
9355               alloc_reg(&current,i,CSREG);
9356               alloc_reg(&current,i,FSREG);
9357             }
9358             else {
9359               ooo[i]=1;
9360               delayslot_alloc(&current,i+1);
9361               alloc_reg(&current,i+1,CSREG);
9362             }
9363           }
9364           else
9365           // Don't alloc the delay slot yet because we might not execute it
9366           if(likely[i]) // BC1FL/BC1TL
9367           {
9368             alloc_cc(&current,i);
9369             dirty_reg(&current,CCREG);
9370             alloc_reg(&current,i,CSREG);
9371             alloc_reg(&current,i,FSREG);
9372           }
9373           ds=1;
9374           current.isconst=0;
9375           break;
9376         case IMM16:
9377           imm16_alloc(&current,i);
9378           break;
9379         case LOAD:
9380         case LOADLR:
9381           load_alloc(&current,i);
9382           break;
9383         case STORE:
9384         case STORELR:
9385           store_alloc(&current,i);
9386           break;
9387         case ALU:
9388           alu_alloc(&current,i);
9389           break;
9390         case SHIFT:
9391           shift_alloc(&current,i);
9392           break;
9393         case MULTDIV:
9394           multdiv_alloc(&current,i);
9395           break;
9396         case SHIFTIMM:
9397           shiftimm_alloc(&current,i);
9398           break;
9399         case MOV:
9400           mov_alloc(&current,i);
9401           break;
9402         case COP0:
9403           cop0_alloc(&current,i);
9404           break;
9405         case COP1:
9406         case COP2:
9407           cop1_alloc(&current,i);
9408           break;
9409         case C1LS:
9410           c1ls_alloc(&current,i);
9411           break;
9412         case C2LS:
9413           c2ls_alloc(&current,i);
9414           break;
9415         case C2OP:
9416           c2op_alloc(&current,i);
9417           break;
9418         case FCONV:
9419           fconv_alloc(&current,i);
9420           break;
9421         case FLOAT:
9422           float_alloc(&current,i);
9423           break;
9424         case FCOMP:
9425           fcomp_alloc(&current,i);
9426           break;
9427         case SYSCALL:
9428         case HLECALL:
9429         case INTCALL:
9430           syscall_alloc(&current,i);
9431           break;
9432         case SPAN:
9433           pagespan_alloc(&current,i);
9434           break;
9435       }
9436
9437       // Drop the upper half of registers that have become 32-bit
9438       current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
9439       if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9440         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9441         if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9442         current.uu|=1;
9443       } else {
9444         current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
9445         current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9446         if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9447         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9448         current.uu|=1;
9449       }
9450
9451       // Create entry (branch target) regmap
9452       for(hr=0;hr<HOST_REGS;hr++)
9453       {
9454         int r,or,er;
9455         r=current.regmap[hr];
9456         if(r>=0) {
9457           if(r!=regmap_pre[i][hr]) {
9458             // TODO: delay slot (?)
9459             or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9460             if(or<0||(r&63)>=TEMPREG){
9461               regs[i].regmap_entry[hr]=-1;
9462             }
9463             else
9464             {
9465               // Just move it to a different register
9466               regs[i].regmap_entry[hr]=r;
9467               // If it was dirty before, it's still dirty
9468               if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r&63);
9469             }
9470           }
9471           else
9472           {
9473             // Unneeded
9474             if(r==0){
9475               regs[i].regmap_entry[hr]=0;
9476             }
9477             else
9478             if(r<64){
9479               if((current.u>>r)&1) {
9480                 regs[i].regmap_entry[hr]=-1;
9481                 //regs[i].regmap[hr]=-1;
9482                 current.regmap[hr]=-1;
9483               }else
9484                 regs[i].regmap_entry[hr]=r;
9485             }
9486             else {
9487               if((current.uu>>(r&63))&1) {
9488                 regs[i].regmap_entry[hr]=-1;
9489                 //regs[i].regmap[hr]=-1;
9490                 current.regmap[hr]=-1;
9491               }else
9492                 regs[i].regmap_entry[hr]=r;
9493             }
9494           }
9495         } else {
9496           // Branches expect CCREG to be allocated at the target
9497           if(regmap_pre[i][hr]==CCREG)
9498             regs[i].regmap_entry[hr]=CCREG;
9499           else
9500             regs[i].regmap_entry[hr]=-1;
9501         }
9502       }
9503       memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9504     }
9505
9506     if(i>0&&(itype[i-1]==STORE||itype[i-1]==STORELR||(itype[i-1]==C2LS&&opcode[i-1]==0x3a))&&(u_int)imm[i-1]<0x800)
9507       current.waswritten|=1<<rs1[i-1];
9508     current.waswritten&=~(1<<rt1[i]);
9509     current.waswritten&=~(1<<rt2[i]);
9510     if((itype[i]==STORE||itype[i]==STORELR||(itype[i]==C2LS&&opcode[i]==0x3a))&&(u_int)imm[i]>=0x800)
9511       current.waswritten&=~(1<<rs1[i]);
9512
9513     /* Branch post-alloc */
9514     if(i>0)
9515     {
9516       current.was32=current.is32;
9517       current.wasdirty=current.dirty;
9518       switch(itype[i-1]) {
9519         case UJUMP:
9520           memcpy(&branch_regs[i-1],&current,sizeof(current));
9521           branch_regs[i-1].isconst=0;
9522           branch_regs[i-1].wasconst=0;
9523           branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9524           branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9525           alloc_cc(&branch_regs[i-1],i-1);
9526           dirty_reg(&branch_regs[i-1],CCREG);
9527           if(rt1[i-1]==31) { // JAL
9528             alloc_reg(&branch_regs[i-1],i-1,31);
9529             dirty_reg(&branch_regs[i-1],31);
9530             branch_regs[i-1].is32|=1LL<<31;
9531           }
9532           memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9533           memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
9534           break;
9535         case RJUMP:
9536           memcpy(&branch_regs[i-1],&current,sizeof(current));
9537           branch_regs[i-1].isconst=0;
9538           branch_regs[i-1].wasconst=0;
9539           branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9540           branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9541           alloc_cc(&branch_regs[i-1],i-1);
9542           dirty_reg(&branch_regs[i-1],CCREG);
9543           alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
9544           if(rt1[i-1]!=0) { // JALR
9545             alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9546             dirty_reg(&branch_regs[i-1],rt1[i-1]);
9547             branch_regs[i-1].is32|=1LL<<rt1[i-1];
9548           }
9549           #ifdef USE_MINI_HT
9550           if(rs1[i-1]==31) { // JALR
9551             alloc_reg(&branch_regs[i-1],i-1,RHASH);
9552             #ifndef HOST_IMM_ADDR32
9553             alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9554             #endif
9555           }
9556           #endif
9557           memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9558           memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
9559           break;
9560         case CJUMP:
9561           if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9562           {
9563             alloc_cc(&current,i-1);
9564             dirty_reg(&current,CCREG);
9565             if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9566                (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9567               // The delay slot overwrote one of our conditions
9568               // Delay slot goes after the test (in order)
9569               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9570               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9571               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9572               current.u|=1;
9573               current.uu|=1;
9574               delayslot_alloc(&current,i);
9575               current.isconst=0;
9576             }
9577             else
9578             {
9579               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9580               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9581               // Alloc the branch condition registers
9582               if(rs1[i-1]) alloc_reg(&current,i-1,rs1[i-1]);
9583               if(rs2[i-1]) alloc_reg(&current,i-1,rs2[i-1]);
9584               if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9585               {
9586                 if(rs1[i-1]) alloc_reg64(&current,i-1,rs1[i-1]);
9587                 if(rs2[i-1]) alloc_reg64(&current,i-1,rs2[i-1]);
9588               }
9589             }
9590             memcpy(&branch_regs[i-1],&current,sizeof(current));
9591             branch_regs[i-1].isconst=0;
9592             branch_regs[i-1].wasconst=0;
9593             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9594             memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
9595           }
9596           else
9597           if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9598           {
9599             alloc_cc(&current,i-1);
9600             dirty_reg(&current,CCREG);
9601             if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9602               // The delay slot overwrote the branch condition
9603               // Delay slot goes after the test (in order)
9604               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9605               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9606               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9607               current.u|=1;
9608               current.uu|=1;
9609               delayslot_alloc(&current,i);
9610               current.isconst=0;
9611             }
9612             else
9613             {
9614               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9615               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9616               // Alloc the branch condition register
9617               alloc_reg(&current,i-1,rs1[i-1]);
9618               if(!(current.is32>>rs1[i-1]&1))
9619               {
9620                 alloc_reg64(&current,i-1,rs1[i-1]);
9621               }
9622             }
9623             memcpy(&branch_regs[i-1],&current,sizeof(current));
9624             branch_regs[i-1].isconst=0;
9625             branch_regs[i-1].wasconst=0;
9626             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9627             memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
9628           }
9629           else
9630           // Alloc the delay slot in case the branch is taken
9631           if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9632           {
9633             memcpy(&branch_regs[i-1],&current,sizeof(current));
9634             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9635             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9636             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9637             alloc_cc(&branch_regs[i-1],i);
9638             dirty_reg(&branch_regs[i-1],CCREG);
9639             delayslot_alloc(&branch_regs[i-1],i);
9640             branch_regs[i-1].isconst=0;
9641             alloc_reg(&current,i,CCREG); // Not taken path
9642             dirty_reg(&current,CCREG);
9643             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9644           }
9645           else
9646           if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9647           {
9648             memcpy(&branch_regs[i-1],&current,sizeof(current));
9649             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9650             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9651             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9652             alloc_cc(&branch_regs[i-1],i);
9653             dirty_reg(&branch_regs[i-1],CCREG);
9654             delayslot_alloc(&branch_regs[i-1],i);
9655             branch_regs[i-1].isconst=0;
9656             alloc_reg(&current,i,CCREG); // Not taken path
9657             dirty_reg(&current,CCREG);
9658             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9659           }
9660           break;
9661         case SJUMP:
9662           //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9663           if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9664           {
9665             alloc_cc(&current,i-1);
9666             dirty_reg(&current,CCREG);
9667             if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9668               // The delay slot overwrote the branch condition
9669               // Delay slot goes after the test (in order)
9670               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9671               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9672               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9673               current.u|=1;
9674               current.uu|=1;
9675               delayslot_alloc(&current,i);
9676               current.isconst=0;
9677             }
9678             else
9679             {
9680               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9681               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9682               // Alloc the branch condition register
9683               alloc_reg(&current,i-1,rs1[i-1]);
9684               if(!(current.is32>>rs1[i-1]&1))
9685               {
9686                 alloc_reg64(&current,i-1,rs1[i-1]);
9687               }
9688             }
9689             memcpy(&branch_regs[i-1],&current,sizeof(current));
9690             branch_regs[i-1].isconst=0;
9691             branch_regs[i-1].wasconst=0;
9692             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9693             memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
9694           }
9695           else
9696           // Alloc the delay slot in case the branch is taken
9697           if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9698           {
9699             memcpy(&branch_regs[i-1],&current,sizeof(current));
9700             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9701             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9702             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9703             alloc_cc(&branch_regs[i-1],i);
9704             dirty_reg(&branch_regs[i-1],CCREG);
9705             delayslot_alloc(&branch_regs[i-1],i);
9706             branch_regs[i-1].isconst=0;
9707             alloc_reg(&current,i,CCREG); // Not taken path
9708             dirty_reg(&current,CCREG);
9709             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9710           }
9711           // FIXME: BLTZAL/BGEZAL
9712           if(opcode2[i-1]&0x10) { // BxxZAL
9713             alloc_reg(&branch_regs[i-1],i-1,31);
9714             dirty_reg(&branch_regs[i-1],31);
9715             branch_regs[i-1].is32|=1LL<<31;
9716           }
9717           break;
9718         case FJUMP:
9719           if(likely[i-1]==0) // BC1F/BC1T
9720           {
9721             alloc_cc(&current,i-1);
9722             dirty_reg(&current,CCREG);
9723             if(itype[i]==FCOMP) {
9724               // The delay slot overwrote the branch condition
9725               // Delay slot goes after the test (in order)
9726               delayslot_alloc(&current,i);
9727               current.isconst=0;
9728             }
9729             else
9730             {
9731               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9732               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9733               // Alloc the branch condition register
9734               alloc_reg(&current,i-1,FSREG);
9735             }
9736             memcpy(&branch_regs[i-1],&current,sizeof(current));
9737             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9738           }
9739           else // BC1FL/BC1TL
9740           {
9741             // Alloc the delay slot in case the branch is taken
9742             memcpy(&branch_regs[i-1],&current,sizeof(current));
9743             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9744             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9745             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9746             alloc_cc(&branch_regs[i-1],i);
9747             dirty_reg(&branch_regs[i-1],CCREG);
9748             delayslot_alloc(&branch_regs[i-1],i);
9749             branch_regs[i-1].isconst=0;
9750             alloc_reg(&current,i,CCREG); // Not taken path
9751             dirty_reg(&current,CCREG);
9752             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9753           }
9754           break;
9755       }
9756
9757       if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9758       {
9759         if(rt1[i-1]==31) // JAL/JALR
9760         {
9761           // Subroutine call will return here, don't alloc any registers
9762           current.is32=1;
9763           current.dirty=0;
9764           clear_all_regs(current.regmap);
9765           alloc_reg(&current,i,CCREG);
9766           dirty_reg(&current,CCREG);
9767         }
9768         else if(i+1<slen)
9769         {
9770           // Internal branch will jump here, match registers to caller
9771           current.is32=0x3FFFFFFFFLL;
9772           current.dirty=0;
9773           clear_all_regs(current.regmap);
9774           alloc_reg(&current,i,CCREG);
9775           dirty_reg(&current,CCREG);
9776           for(j=i-1;j>=0;j--)
9777           {
9778             if(ba[j]==start+i*4+4) {
9779               memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9780               current.is32=branch_regs[j].is32;
9781               current.dirty=branch_regs[j].dirty;
9782               break;
9783             }
9784           }
9785           while(j>=0) {
9786             if(ba[j]==start+i*4+4) {
9787               for(hr=0;hr<HOST_REGS;hr++) {
9788                 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9789                   current.regmap[hr]=-1;
9790                 }
9791                 current.is32&=branch_regs[j].is32;
9792                 current.dirty&=branch_regs[j].dirty;
9793               }
9794             }
9795             j--;
9796           }
9797         }
9798       }
9799     }
9800
9801     // Count cycles in between branches
9802     ccadj[i]=cc;
9803     if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
9804     {
9805       cc=0;
9806     }
9807 #if defined(PCSX) && !defined(DRC_DBG)
9808     else if(itype[i]==C2OP&&gte_cycletab[source[i]&0x3f]>2)
9809     {
9810       // GTE runs in parallel until accessed, divide by 2 for a rough guess
9811       cc+=gte_cycletab[source[i]&0x3f]/2;
9812     }
9813     else if(/*itype[i]==LOAD||itype[i]==STORE||*/itype[i]==C1LS) // load,store causes weird timing issues
9814     {
9815       cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
9816     }
9817     else if(itype[i]==C2LS)
9818     {
9819       cc+=4;
9820     }
9821 #endif
9822     else
9823     {
9824       cc++;
9825     }
9826
9827     flush_dirty_uppers(&current);
9828     if(!is_ds[i]) {
9829       regs[i].is32=current.is32;
9830       regs[i].dirty=current.dirty;
9831       regs[i].isconst=current.isconst;
9832       memcpy(constmap[i],current_constmap,sizeof(current_constmap));
9833     }
9834     for(hr=0;hr<HOST_REGS;hr++) {
9835       if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
9836         if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9837           regs[i].wasconst&=~(1<<hr);
9838         }
9839       }
9840     }
9841     if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9842     regs[i].waswritten=current.waswritten;
9843   }
9844
9845   /* Pass 4 - Cull unused host registers */
9846
9847   uint64_t nr=0;
9848
9849   for (i=slen-1;i>=0;i--)
9850   {
9851     int hr;
9852     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9853     {
9854       if(ba[i]<start || ba[i]>=(start+slen*4))
9855       {
9856         // Branch out of this block, don't need anything
9857         nr=0;
9858       }
9859       else
9860       {
9861         // Internal branch
9862         // Need whatever matches the target
9863         nr=0;
9864         int t=(ba[i]-start)>>2;
9865         for(hr=0;hr<HOST_REGS;hr++)
9866         {
9867           if(regs[i].regmap_entry[hr]>=0) {
9868             if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9869           }
9870         }
9871       }
9872       // Conditional branch may need registers for following instructions
9873       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9874       {
9875         if(i<slen-2) {
9876           nr|=needed_reg[i+2];
9877           for(hr=0;hr<HOST_REGS;hr++)
9878           {
9879             if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9880             //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9881           }
9882         }
9883       }
9884       // Don't need stuff which is overwritten
9885       //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9886       //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9887       // Merge in delay slot
9888       for(hr=0;hr<HOST_REGS;hr++)
9889       {
9890         if(!likely[i]) {
9891           // These are overwritten unless the branch is "likely"
9892           // and the delay slot is nullified if not taken
9893           if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9894           if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9895         }
9896         if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9897         if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9898         if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9899         if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9900         if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9901         if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9902         if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9903         if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9904         if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9905           if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9906           if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9907         }
9908         if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9909           if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9910           if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9911         }
9912         if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
9913           if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9914           if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9915         }
9916       }
9917     }
9918     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
9919     {
9920       // SYSCALL instruction (software interrupt)
9921       nr=0;
9922     }
9923     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9924     {
9925       // ERET instruction (return from interrupt)
9926       nr=0;
9927     }
9928     else // Non-branch
9929     {
9930       if(i<slen-1) {
9931         for(hr=0;hr<HOST_REGS;hr++) {
9932           if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9933           if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9934           if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9935           if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9936         }
9937       }
9938     }
9939     for(hr=0;hr<HOST_REGS;hr++)
9940     {
9941       // Overwritten registers are not needed
9942       if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9943       if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9944       if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9945       // Source registers are needed
9946       if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9947       if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9948       if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9949       if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9950       if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9951       if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9952       if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9953       if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9954       if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9955         if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9956         if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9957       }
9958       if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
9959         if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9960         if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9961       }
9962       if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
9963         if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9964         if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9965       }
9966       // Don't store a register immediately after writing it,
9967       // may prevent dual-issue.
9968       // But do so if this is a branch target, otherwise we
9969       // might have to load the register before the branch.
9970       if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
9971         if((regmap_pre[i][hr]>0&&regmap_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
9972            (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
9973           if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9974           if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9975         }
9976         if((regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
9977            (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
9978           if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9979           if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9980         }
9981       }
9982     }
9983     // Cycle count is needed at branches.  Assume it is needed at the target too.
9984     if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
9985       if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9986       if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9987     }
9988     // Save it
9989     needed_reg[i]=nr;
9990
9991     // Deallocate unneeded registers
9992     for(hr=0;hr<HOST_REGS;hr++)
9993     {
9994       if(!((nr>>hr)&1)) {
9995         if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
9996         if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9997            (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9998            (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
9999         {
10000           if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10001           {
10002             if(likely[i]) {
10003               regs[i].regmap[hr]=-1;
10004               regs[i].isconst&=~(1<<hr);
10005               if(i<slen-2) {
10006                 regmap_pre[i+2][hr]=-1;
10007                 regs[i+2].wasconst&=~(1<<hr);
10008               }
10009             }
10010           }
10011         }
10012         if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10013         {
10014           int d1=0,d2=0,map=0,temp=0;
10015           if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
10016           {
10017             d1=dep1[i+1];
10018             d2=dep2[i+1];
10019           }
10020           if(using_tlb) {
10021             if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
10022                itype[i+1]==STORE || itype[i+1]==STORELR ||
10023                itype[i+1]==C1LS || itype[i+1]==C2LS)
10024             map=TLREG;
10025           } else
10026           if(itype[i+1]==STORE || itype[i+1]==STORELR ||
10027              (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
10028             map=INVCP;
10029           }
10030           if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
10031              itype[i+1]==C1LS || itype[i+1]==C2LS)
10032             temp=FTEMP;
10033           if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
10034              (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
10035              (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
10036              (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
10037              (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
10038              regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
10039              (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
10040              regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
10041              regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
10042              regs[i].regmap[hr]!=map )
10043           {
10044             regs[i].regmap[hr]=-1;
10045             regs[i].isconst&=~(1<<hr);
10046             if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
10047                (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
10048                (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
10049                (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
10050                (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
10051                branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
10052                (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
10053                branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
10054                branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
10055                branch_regs[i].regmap[hr]!=map)
10056             {
10057               branch_regs[i].regmap[hr]=-1;
10058               branch_regs[i].regmap_entry[hr]=-1;
10059               if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10060               {
10061                 if(!likely[i]&&i<slen-2) {
10062                   regmap_pre[i+2][hr]=-1;
10063                   regs[i+2].wasconst&=~(1<<hr);
10064                 }
10065               }
10066             }
10067           }
10068         }
10069         else
10070         {
10071           // Non-branch
10072           if(i>0)
10073           {
10074             int d1=0,d2=0,map=-1,temp=-1;
10075             if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
10076             {
10077               d1=dep1[i];
10078               d2=dep2[i];
10079             }
10080             if(using_tlb) {
10081               if(itype[i]==LOAD || itype[i]==LOADLR ||
10082                  itype[i]==STORE || itype[i]==STORELR ||
10083                  itype[i]==C1LS || itype[i]==C2LS)
10084               map=TLREG;
10085             } else if(itype[i]==STORE || itype[i]==STORELR ||
10086                       (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
10087               map=INVCP;
10088             }
10089             if(itype[i]==LOADLR || itype[i]==STORELR ||
10090                itype[i]==C1LS || itype[i]==C2LS)
10091               temp=FTEMP;
10092             if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
10093                (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
10094                (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
10095                regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
10096                (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
10097                (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
10098             {
10099               if(i<slen-1&&!is_ds[i]) {
10100                 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
10101                 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
10102                 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
10103                 {
10104                   SysPrintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
10105                   assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
10106                 }
10107                 regmap_pre[i+1][hr]=-1;
10108                 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
10109                 regs[i+1].wasconst&=~(1<<hr);
10110               }
10111               regs[i].regmap[hr]=-1;
10112               regs[i].isconst&=~(1<<hr);
10113             }
10114           }
10115         }
10116       }
10117     }
10118   }
10119
10120   /* Pass 5 - Pre-allocate registers */
10121
10122   // If a register is allocated during a loop, try to allocate it for the
10123   // entire loop, if possible.  This avoids loading/storing registers
10124   // inside of the loop.
10125
10126   signed char f_regmap[HOST_REGS];
10127   clear_all_regs(f_regmap);
10128   for(i=0;i<slen-1;i++)
10129   {
10130     if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10131     {
10132       if(ba[i]>=start && ba[i]<(start+i*4))
10133       if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
10134       ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
10135       ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
10136       ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
10137       ||itype[i+1]==FCOMP||itype[i+1]==FCONV
10138       ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
10139       {
10140         int t=(ba[i]-start)>>2;
10141         if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
10142         if(t<2||(itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||rt1[t-2]!=31) // call/ret assumes no registers allocated
10143         for(hr=0;hr<HOST_REGS;hr++)
10144         {
10145           if(regs[i].regmap[hr]>64) {
10146             if(!((regs[i].dirty>>hr)&1))
10147               f_regmap[hr]=regs[i].regmap[hr];
10148             else f_regmap[hr]=-1;
10149           }
10150           else if(regs[i].regmap[hr]>=0) {
10151             if(f_regmap[hr]!=regs[i].regmap[hr]) {
10152               // dealloc old register
10153               int n;
10154               for(n=0;n<HOST_REGS;n++)
10155               {
10156                 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10157               }
10158               // and alloc new one
10159               f_regmap[hr]=regs[i].regmap[hr];
10160             }
10161           }
10162           if(branch_regs[i].regmap[hr]>64) {
10163             if(!((branch_regs[i].dirty>>hr)&1))
10164               f_regmap[hr]=branch_regs[i].regmap[hr];
10165             else f_regmap[hr]=-1;
10166           }
10167           else if(branch_regs[i].regmap[hr]>=0) {
10168             if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
10169               // dealloc old register
10170               int n;
10171               for(n=0;n<HOST_REGS;n++)
10172               {
10173                 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
10174               }
10175               // and alloc new one
10176               f_regmap[hr]=branch_regs[i].regmap[hr];
10177             }
10178           }
10179           if(ooo[i]) {
10180             if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
10181               f_regmap[hr]=branch_regs[i].regmap[hr];
10182           }else{
10183             if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
10184               f_regmap[hr]=branch_regs[i].regmap[hr];
10185           }
10186           // Avoid dirty->clean transition
10187           #ifdef DESTRUCTIVE_WRITEBACK
10188           if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
10189           #endif
10190           // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
10191           // case above, however it's always a good idea.  We can't hoist the
10192           // load if the register was already allocated, so there's no point
10193           // wasting time analyzing most of these cases.  It only "succeeds"
10194           // when the mapping was different and the load can be replaced with
10195           // a mov, which is of negligible benefit.  So such cases are
10196           // skipped below.
10197           if(f_regmap[hr]>0) {
10198             if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
10199               int r=f_regmap[hr];
10200               for(j=t;j<=i;j++)
10201               {
10202                 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10203                 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
10204                 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
10205                 if(r>63) {
10206                   // NB This can exclude the case where the upper-half
10207                   // register is lower numbered than the lower-half
10208                   // register.  Not sure if it's worth fixing...
10209                   if(get_reg(regs[j].regmap,r&63)<0) break;
10210                   if(get_reg(regs[j].regmap_entry,r&63)<0) break;
10211                   if(regs[j].is32&(1LL<<(r&63))) break;
10212                 }
10213                 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
10214                   //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10215                   int k;
10216                   if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
10217                     if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
10218                     if(r>63) {
10219                       if(get_reg(regs[i].regmap,r&63)<0) break;
10220                       if(get_reg(branch_regs[i].regmap,r&63)<0) break;
10221                     }
10222                     k=i;
10223                     while(k>1&&regs[k-1].regmap[hr]==-1) {
10224                       if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10225                         //printf("no free regs for store %x\n",start+(k-1)*4);
10226                         break;
10227                       }
10228                       if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
10229                         //printf("no-match due to different register\n");
10230                         break;
10231                       }
10232                       if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
10233                         //printf("no-match due to branch\n");
10234                         break;
10235                       }
10236                       // call/ret fast path assumes no registers allocated
10237                       if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)&&rt1[k-3]==31) {
10238                         break;
10239                       }
10240                       if(r>63) {
10241                         // NB This can exclude the case where the upper-half
10242                         // register is lower numbered than the lower-half
10243                         // register.  Not sure if it's worth fixing...
10244                         if(get_reg(regs[k-1].regmap,r&63)<0) break;
10245                         if(regs[k-1].is32&(1LL<<(r&63))) break;
10246                       }
10247                       k--;
10248                     }
10249                     if(i<slen-1) {
10250                       if((regs[k].is32&(1LL<<f_regmap[hr]))!=
10251                         (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
10252                         //printf("bad match after branch\n");
10253                         break;
10254                       }
10255                     }
10256                     if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
10257                       //printf("Extend r%d, %x ->\n",hr,start+k*4);
10258                       while(k<i) {
10259                         regs[k].regmap_entry[hr]=f_regmap[hr];
10260                         regs[k].regmap[hr]=f_regmap[hr];
10261                         regmap_pre[k+1][hr]=f_regmap[hr];
10262                         regs[k].wasdirty&=~(1<<hr);
10263                         regs[k].dirty&=~(1<<hr);
10264                         regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
10265                         regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
10266                         regs[k].wasconst&=~(1<<hr);
10267                         regs[k].isconst&=~(1<<hr);
10268                         k++;
10269                       }
10270                     }
10271                     else {
10272                       //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
10273                       break;
10274                     }
10275                     assert(regs[i-1].regmap[hr]==f_regmap[hr]);
10276                     if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
10277                       //printf("OK fill %x (r%d)\n",start+i*4,hr);
10278                       regs[i].regmap_entry[hr]=f_regmap[hr];
10279                       regs[i].regmap[hr]=f_regmap[hr];
10280                       regs[i].wasdirty&=~(1<<hr);
10281                       regs[i].dirty&=~(1<<hr);
10282                       regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
10283                       regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
10284                       regs[i].wasconst&=~(1<<hr);
10285                       regs[i].isconst&=~(1<<hr);
10286                       branch_regs[i].regmap_entry[hr]=f_regmap[hr];
10287                       branch_regs[i].wasdirty&=~(1<<hr);
10288                       branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
10289                       branch_regs[i].regmap[hr]=f_regmap[hr];
10290                       branch_regs[i].dirty&=~(1<<hr);
10291                       branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
10292                       branch_regs[i].wasconst&=~(1<<hr);
10293                       branch_regs[i].isconst&=~(1<<hr);
10294                       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
10295                         regmap_pre[i+2][hr]=f_regmap[hr];
10296                         regs[i+2].wasdirty&=~(1<<hr);
10297                         regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
10298                         assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
10299                           (regs[i+2].was32&(1LL<<f_regmap[hr])));
10300                       }
10301                     }
10302                   }
10303                   for(k=t;k<j;k++) {
10304                     // Alloc register clean at beginning of loop,
10305                     // but may dirty it in pass 6
10306                     regs[k].regmap_entry[hr]=f_regmap[hr];
10307                     regs[k].regmap[hr]=f_regmap[hr];
10308                     regs[k].dirty&=~(1<<hr);
10309                     regs[k].wasconst&=~(1<<hr);
10310                     regs[k].isconst&=~(1<<hr);
10311                     if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) {
10312                       branch_regs[k].regmap_entry[hr]=f_regmap[hr];
10313                       branch_regs[k].regmap[hr]=f_regmap[hr];
10314                       branch_regs[k].dirty&=~(1<<hr);
10315                       branch_regs[k].wasconst&=~(1<<hr);
10316                       branch_regs[k].isconst&=~(1<<hr);
10317                       if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
10318                         regmap_pre[k+2][hr]=f_regmap[hr];
10319                         regs[k+2].wasdirty&=~(1<<hr);
10320                         assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))==
10321                           (regs[k+2].was32&(1LL<<f_regmap[hr])));
10322                       }
10323                     }
10324                     else
10325                     {
10326                       regmap_pre[k+1][hr]=f_regmap[hr];
10327                       regs[k+1].wasdirty&=~(1<<hr);
10328                     }
10329                   }
10330                   if(regs[j].regmap[hr]==f_regmap[hr])
10331                     regs[j].regmap_entry[hr]=f_regmap[hr];
10332                   break;
10333                 }
10334                 if(j==i) break;
10335                 if(regs[j].regmap[hr]>=0)
10336                   break;
10337                 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
10338                   //printf("no-match due to different register\n");
10339                   break;
10340                 }
10341                 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
10342                   //printf("32/64 mismatch %x %d\n",start+j*4,hr);
10343                   break;
10344                 }
10345                 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10346                 {
10347                   // Stop on unconditional branch
10348                   break;
10349                 }
10350                 if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
10351                 {
10352                   if(ooo[j]) {
10353                     if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
10354                       break;
10355                   }else{
10356                     if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
10357                       break;
10358                   }
10359                   if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
10360                     //printf("no-match due to different register (branch)\n");
10361                     break;
10362                   }
10363                 }
10364                 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10365                   //printf("No free regs for store %x\n",start+j*4);
10366                   break;
10367                 }
10368                 if(f_regmap[hr]>=64) {
10369                   if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
10370                     break;
10371                   }
10372                   else
10373                   {
10374                     if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
10375                       break;
10376                     }
10377                   }
10378                 }
10379               }
10380             }
10381           }
10382         }
10383       }
10384     }else{
10385       // Non branch or undetermined branch target
10386       for(hr=0;hr<HOST_REGS;hr++)
10387       {
10388         if(hr!=EXCLUDE_REG) {
10389           if(regs[i].regmap[hr]>64) {
10390             if(!((regs[i].dirty>>hr)&1))
10391               f_regmap[hr]=regs[i].regmap[hr];
10392           }
10393           else if(regs[i].regmap[hr]>=0) {
10394             if(f_regmap[hr]!=regs[i].regmap[hr]) {
10395               // dealloc old register
10396               int n;
10397               for(n=0;n<HOST_REGS;n++)
10398               {
10399                 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10400               }
10401               // and alloc new one
10402               f_regmap[hr]=regs[i].regmap[hr];
10403             }
10404           }
10405         }
10406       }
10407       // Try to restore cycle count at branch targets
10408       if(bt[i]) {
10409         for(j=i;j<slen-1;j++) {
10410           if(regs[j].regmap[HOST_CCREG]!=-1) break;
10411           if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10412             //printf("no free regs for store %x\n",start+j*4);
10413             break;
10414           }
10415         }
10416         if(regs[j].regmap[HOST_CCREG]==CCREG) {
10417           int k=i;
10418           //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
10419           while(k<j) {
10420             regs[k].regmap_entry[HOST_CCREG]=CCREG;
10421             regs[k].regmap[HOST_CCREG]=CCREG;
10422             regmap_pre[k+1][HOST_CCREG]=CCREG;
10423             regs[k+1].wasdirty|=1<<HOST_CCREG;
10424             regs[k].dirty|=1<<HOST_CCREG;
10425             regs[k].wasconst&=~(1<<HOST_CCREG);
10426             regs[k].isconst&=~(1<<HOST_CCREG);
10427             k++;
10428           }
10429           regs[j].regmap_entry[HOST_CCREG]=CCREG;
10430         }
10431         // Work backwards from the branch target
10432         if(j>i&&f_regmap[HOST_CCREG]==CCREG)
10433         {
10434           //printf("Extend backwards\n");
10435           int k;
10436           k=i;
10437           while(regs[k-1].regmap[HOST_CCREG]==-1) {
10438             if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10439               //printf("no free regs for store %x\n",start+(k-1)*4);
10440               break;
10441             }
10442             k--;
10443           }
10444           if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
10445             //printf("Extend CC, %x ->\n",start+k*4);
10446             while(k<=i) {
10447               regs[k].regmap_entry[HOST_CCREG]=CCREG;
10448               regs[k].regmap[HOST_CCREG]=CCREG;
10449               regmap_pre[k+1][HOST_CCREG]=CCREG;
10450               regs[k+1].wasdirty|=1<<HOST_CCREG;
10451               regs[k].dirty|=1<<HOST_CCREG;
10452               regs[k].wasconst&=~(1<<HOST_CCREG);
10453               regs[k].isconst&=~(1<<HOST_CCREG);
10454               k++;
10455             }
10456           }
10457           else {
10458             //printf("Fail Extend CC, %x ->\n",start+k*4);
10459           }
10460         }
10461       }
10462       if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
10463          itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
10464          itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
10465          itype[i]!=FCONV&&itype[i]!=FCOMP)
10466       {
10467         memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
10468       }
10469     }
10470   }
10471
10472   // Cache memory offset or tlb map pointer if a register is available
10473   #ifndef HOST_IMM_ADDR32
10474   #ifndef RAM_OFFSET
10475   if(using_tlb)
10476   #endif
10477   {
10478     int earliest_available[HOST_REGS];
10479     int loop_start[HOST_REGS];
10480     int score[HOST_REGS];
10481     int end[HOST_REGS];
10482     int reg=using_tlb?MMREG:ROREG;
10483
10484     // Init
10485     for(hr=0;hr<HOST_REGS;hr++) {
10486       score[hr]=0;earliest_available[hr]=0;
10487       loop_start[hr]=MAXBLOCK;
10488     }
10489     for(i=0;i<slen-1;i++)
10490     {
10491       // Can't do anything if no registers are available
10492       if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i]) {
10493         for(hr=0;hr<HOST_REGS;hr++) {
10494           score[hr]=0;earliest_available[hr]=i+1;
10495           loop_start[hr]=MAXBLOCK;
10496         }
10497       }
10498       if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10499         if(!ooo[i]) {
10500           if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) {
10501             for(hr=0;hr<HOST_REGS;hr++) {
10502               score[hr]=0;earliest_available[hr]=i+1;
10503               loop_start[hr]=MAXBLOCK;
10504             }
10505           }
10506         }else{
10507           if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) {
10508             for(hr=0;hr<HOST_REGS;hr++) {
10509               score[hr]=0;earliest_available[hr]=i+1;
10510               loop_start[hr]=MAXBLOCK;
10511             }
10512           }
10513         }
10514       }
10515       // Mark unavailable registers
10516       for(hr=0;hr<HOST_REGS;hr++) {
10517         if(regs[i].regmap[hr]>=0) {
10518           score[hr]=0;earliest_available[hr]=i+1;
10519           loop_start[hr]=MAXBLOCK;
10520         }
10521         if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10522           if(branch_regs[i].regmap[hr]>=0) {
10523             score[hr]=0;earliest_available[hr]=i+2;
10524             loop_start[hr]=MAXBLOCK;
10525           }
10526         }
10527       }
10528       // No register allocations after unconditional jumps
10529       if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10530       {
10531         for(hr=0;hr<HOST_REGS;hr++) {
10532           score[hr]=0;earliest_available[hr]=i+2;
10533           loop_start[hr]=MAXBLOCK;
10534         }
10535         i++; // Skip delay slot too
10536         //printf("skip delay slot: %x\n",start+i*4);
10537       }
10538       else
10539       // Possible match
10540       if(itype[i]==LOAD||itype[i]==LOADLR||
10541          itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) {
10542         for(hr=0;hr<HOST_REGS;hr++) {
10543           if(hr!=EXCLUDE_REG) {
10544             end[hr]=i-1;
10545             for(j=i;j<slen-1;j++) {
10546               if(regs[j].regmap[hr]>=0) break;
10547               if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10548                 if(branch_regs[j].regmap[hr]>=0) break;
10549                 if(ooo[j]) {
10550                   if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) break;
10551                 }else{
10552                   if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) break;
10553                 }
10554               }
10555               else if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) break;
10556               if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10557                 int t=(ba[j]-start)>>2;
10558                 if(t<j&&t>=earliest_available[hr]) {
10559                   if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) { // call/ret assumes no registers allocated
10560                     // Score a point for hoisting loop invariant
10561                     if(t<loop_start[hr]) loop_start[hr]=t;
10562                     //printf("set loop_start: i=%x j=%x (%x)\n",start+i*4,start+j*4,start+t*4);
10563                     score[hr]++;
10564                     end[hr]=j;
10565                   }
10566                 }
10567                 else if(t<j) {
10568                   if(regs[t].regmap[hr]==reg) {
10569                     // Score a point if the branch target matches this register
10570                     score[hr]++;
10571                     end[hr]=j;
10572                   }
10573                 }
10574                 if(itype[j+1]==LOAD||itype[j+1]==LOADLR||
10575                    itype[j+1]==STORE||itype[j+1]==STORELR||itype[j+1]==C1LS) {
10576                   score[hr]++;
10577                   end[hr]=j;
10578                 }
10579               }
10580               if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10581               {
10582                 // Stop on unconditional branch
10583                 break;
10584               }
10585               else
10586               if(itype[j]==LOAD||itype[j]==LOADLR||
10587                  itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS) {
10588                 score[hr]++;
10589                 end[hr]=j;
10590               }
10591             }
10592           }
10593         }
10594         // Find highest score and allocate that register
10595         int maxscore=0;
10596         for(hr=0;hr<HOST_REGS;hr++) {
10597           if(hr!=EXCLUDE_REG) {
10598             if(score[hr]>score[maxscore]) {
10599               maxscore=hr;
10600               //printf("highest score: %d %d (%x->%x)\n",score[hr],hr,start+i*4,start+end[hr]*4);
10601             }
10602           }
10603         }
10604         if(score[maxscore]>1)
10605         {
10606           if(i<loop_start[maxscore]) loop_start[maxscore]=i;
10607           for(j=loop_start[maxscore];j<slen&&j<=end[maxscore];j++) {
10608             //if(regs[j].regmap[maxscore]>=0) {printf("oops: %x %x was %d=%d\n",loop_start[maxscore]*4+start,j*4+start,maxscore,regs[j].regmap[maxscore]);}
10609             assert(regs[j].regmap[maxscore]<0);
10610             if(j>loop_start[maxscore]) regs[j].regmap_entry[maxscore]=reg;
10611             regs[j].regmap[maxscore]=reg;
10612             regs[j].dirty&=~(1<<maxscore);
10613             regs[j].wasconst&=~(1<<maxscore);
10614             regs[j].isconst&=~(1<<maxscore);
10615             if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10616               branch_regs[j].regmap[maxscore]=reg;
10617               branch_regs[j].wasdirty&=~(1<<maxscore);
10618               branch_regs[j].dirty&=~(1<<maxscore);
10619               branch_regs[j].wasconst&=~(1<<maxscore);
10620               branch_regs[j].isconst&=~(1<<maxscore);
10621               if(itype[j]!=RJUMP&&itype[j]!=UJUMP&&(source[j]>>16)!=0x1000) {
10622                 regmap_pre[j+2][maxscore]=reg;
10623                 regs[j+2].wasdirty&=~(1<<maxscore);
10624               }
10625               // loop optimization (loop_preload)
10626               int t=(ba[j]-start)>>2;
10627               if(t==loop_start[maxscore]) {
10628                 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) // call/ret assumes no registers allocated
10629                   regs[t].regmap_entry[maxscore]=reg;
10630               }
10631             }
10632             else
10633             {
10634               if(j<1||(itype[j-1]!=RJUMP&&itype[j-1]!=UJUMP&&itype[j-1]!=CJUMP&&itype[j-1]!=SJUMP&&itype[j-1]!=FJUMP)) {
10635                 regmap_pre[j+1][maxscore]=reg;
10636                 regs[j+1].wasdirty&=~(1<<maxscore);
10637               }
10638             }
10639           }
10640           i=j-1;
10641           if(itype[j-1]==RJUMP||itype[j-1]==UJUMP||itype[j-1]==CJUMP||itype[j-1]==SJUMP||itype[j-1]==FJUMP) i++; // skip delay slot
10642           for(hr=0;hr<HOST_REGS;hr++) {
10643             score[hr]=0;earliest_available[hr]=i+i;
10644             loop_start[hr]=MAXBLOCK;
10645           }
10646         }
10647       }
10648     }
10649   }
10650   #endif
10651
10652   // This allocates registers (if possible) one instruction prior
10653   // to use, which can avoid a load-use penalty on certain CPUs.
10654   for(i=0;i<slen-1;i++)
10655   {
10656     if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10657     {
10658       if(!bt[i+1])
10659       {
10660         if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
10661            ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
10662         {
10663           if(rs1[i+1]) {
10664             if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10665             {
10666               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10667               {
10668                 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10669                 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10670                 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10671                 regs[i].isconst&=~(1<<hr);
10672                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10673                 constmap[i][hr]=constmap[i+1][hr];
10674                 regs[i+1].wasdirty&=~(1<<hr);
10675                 regs[i].dirty&=~(1<<hr);
10676               }
10677             }
10678           }
10679           if(rs2[i+1]) {
10680             if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10681             {
10682               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10683               {
10684                 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10685                 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10686                 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10687                 regs[i].isconst&=~(1<<hr);
10688                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10689                 constmap[i][hr]=constmap[i+1][hr];
10690                 regs[i+1].wasdirty&=~(1<<hr);
10691                 regs[i].dirty&=~(1<<hr);
10692               }
10693             }
10694           }
10695           // Preload target address for load instruction (non-constant)
10696           if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10697             if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10698             {
10699               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10700               {
10701                 regs[i].regmap[hr]=rs1[i+1];
10702                 regmap_pre[i+1][hr]=rs1[i+1];
10703                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10704                 regs[i].isconst&=~(1<<hr);
10705                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10706                 constmap[i][hr]=constmap[i+1][hr];
10707                 regs[i+1].wasdirty&=~(1<<hr);
10708                 regs[i].dirty&=~(1<<hr);
10709               }
10710             }
10711           }
10712           // Load source into target register
10713           if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10714             if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10715             {
10716               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10717               {
10718                 regs[i].regmap[hr]=rs1[i+1];
10719                 regmap_pre[i+1][hr]=rs1[i+1];
10720                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10721                 regs[i].isconst&=~(1<<hr);
10722                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10723                 constmap[i][hr]=constmap[i+1][hr];
10724                 regs[i+1].wasdirty&=~(1<<hr);
10725                 regs[i].dirty&=~(1<<hr);
10726               }
10727             }
10728           }
10729           // Preload map address
10730           #ifndef HOST_IMM_ADDR32
10731           if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
10732             hr=get_reg(regs[i+1].regmap,TLREG);
10733             if(hr>=0) {
10734               int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10735               if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10736                 int nr;
10737                 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10738                 {
10739                   regs[i].regmap[hr]=MGEN1+((i+1)&1);
10740                   regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10741                   regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10742                   regs[i].isconst&=~(1<<hr);
10743                   regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10744                   constmap[i][hr]=constmap[i+1][hr];
10745                   regs[i+1].wasdirty&=~(1<<hr);
10746                   regs[i].dirty&=~(1<<hr);
10747                 }
10748                 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10749                 {
10750                   // move it to another register
10751                   regs[i+1].regmap[hr]=-1;
10752                   regmap_pre[i+2][hr]=-1;
10753                   regs[i+1].regmap[nr]=TLREG;
10754                   regmap_pre[i+2][nr]=TLREG;
10755                   regs[i].regmap[nr]=MGEN1+((i+1)&1);
10756                   regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10757                   regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10758                   regs[i].isconst&=~(1<<nr);
10759                   regs[i+1].isconst&=~(1<<nr);
10760                   regs[i].dirty&=~(1<<nr);
10761                   regs[i+1].wasdirty&=~(1<<nr);
10762                   regs[i+1].dirty&=~(1<<nr);
10763                   regs[i+2].wasdirty&=~(1<<nr);
10764                 }
10765               }
10766             }
10767           }
10768           #endif
10769           // Address for store instruction (non-constant)
10770           if(itype[i+1]==STORE||itype[i+1]==STORELR
10771              ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
10772             if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10773               hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10774               if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10775               else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10776               assert(hr>=0);
10777               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10778               {
10779                 regs[i].regmap[hr]=rs1[i+1];
10780                 regmap_pre[i+1][hr]=rs1[i+1];
10781                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10782                 regs[i].isconst&=~(1<<hr);
10783                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10784                 constmap[i][hr]=constmap[i+1][hr];
10785                 regs[i+1].wasdirty&=~(1<<hr);
10786                 regs[i].dirty&=~(1<<hr);
10787               }
10788             }
10789           }
10790           if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
10791             if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10792               int nr;
10793               hr=get_reg(regs[i+1].regmap,FTEMP);
10794               assert(hr>=0);
10795               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10796               {
10797                 regs[i].regmap[hr]=rs1[i+1];
10798                 regmap_pre[i+1][hr]=rs1[i+1];
10799                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10800                 regs[i].isconst&=~(1<<hr);
10801                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10802                 constmap[i][hr]=constmap[i+1][hr];
10803                 regs[i+1].wasdirty&=~(1<<hr);
10804                 regs[i].dirty&=~(1<<hr);
10805               }
10806               else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10807               {
10808                 // move it to another register
10809                 regs[i+1].regmap[hr]=-1;
10810                 regmap_pre[i+2][hr]=-1;
10811                 regs[i+1].regmap[nr]=FTEMP;
10812                 regmap_pre[i+2][nr]=FTEMP;
10813                 regs[i].regmap[nr]=rs1[i+1];
10814                 regmap_pre[i+1][nr]=rs1[i+1];
10815                 regs[i+1].regmap_entry[nr]=rs1[i+1];
10816                 regs[i].isconst&=~(1<<nr);
10817                 regs[i+1].isconst&=~(1<<nr);
10818                 regs[i].dirty&=~(1<<nr);
10819                 regs[i+1].wasdirty&=~(1<<nr);
10820                 regs[i+1].dirty&=~(1<<nr);
10821                 regs[i+2].wasdirty&=~(1<<nr);
10822               }
10823             }
10824           }
10825           if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
10826             if(itype[i+1]==LOAD)
10827               hr=get_reg(regs[i+1].regmap,rt1[i+1]);
10828             if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
10829               hr=get_reg(regs[i+1].regmap,FTEMP);
10830             if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
10831               hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10832               if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10833             }
10834             if(hr>=0&&regs[i].regmap[hr]<0) {
10835               int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10836               if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10837                 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10838                 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10839                 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10840                 regs[i].isconst&=~(1<<hr);
10841                 regs[i+1].wasdirty&=~(1<<hr);
10842                 regs[i].dirty&=~(1<<hr);
10843               }
10844             }
10845           }
10846         }
10847       }
10848     }
10849   }
10850
10851   /* Pass 6 - Optimize clean/dirty state */
10852   clean_registers(0,slen-1,1);
10853
10854   /* Pass 7 - Identify 32-bit registers */
10855 #ifndef FORCE32
10856   provisional_r32();
10857
10858   u_int r32=0;
10859
10860   for (i=slen-1;i>=0;i--)
10861   {
10862     int hr;
10863     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10864     {
10865       if(ba[i]<start || ba[i]>=(start+slen*4))
10866       {
10867         // Branch out of this block, don't need anything
10868         r32=0;
10869       }
10870       else
10871       {
10872         // Internal branch
10873         // Need whatever matches the target
10874         // (and doesn't get overwritten by the delay slot instruction)
10875         r32=0;
10876         int t=(ba[i]-start)>>2;
10877         if(ba[i]>start+i*4) {
10878           // Forward branch
10879           if(!(requires_32bit[t]&~regs[i].was32))
10880             r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10881         }else{
10882           // Backward branch
10883           //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10884           //  r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10885           if(!(pr32[t]&~regs[i].was32))
10886             r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10887         }
10888       }
10889       // Conditional branch may need registers for following instructions
10890       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10891       {
10892         if(i<slen-2) {
10893           r32|=requires_32bit[i+2];
10894           r32&=regs[i].was32;
10895           // Mark this address as a branch target since it may be called
10896           // upon return from interrupt
10897           bt[i+2]=1;
10898         }
10899       }
10900       // Merge in delay slot
10901       if(!likely[i]) {
10902         // These are overwritten unless the branch is "likely"
10903         // and the delay slot is nullified if not taken
10904         r32&=~(1LL<<rt1[i+1]);
10905         r32&=~(1LL<<rt2[i+1]);
10906       }
10907       // Assume these are needed (delay slot)
10908       if(us1[i+1]>0)
10909       {
10910         if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10911       }
10912       if(us2[i+1]>0)
10913       {
10914         if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10915       }
10916       if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10917       {
10918         if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10919       }
10920       if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10921       {
10922         if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10923       }
10924     }
10925     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
10926     {
10927       // SYSCALL instruction (software interrupt)
10928       r32=0;
10929     }
10930     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10931     {
10932       // ERET instruction (return from interrupt)
10933       r32=0;
10934     }
10935     // Check 32 bits
10936     r32&=~(1LL<<rt1[i]);
10937     r32&=~(1LL<<rt2[i]);
10938     if(us1[i]>0)
10939     {
10940       if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10941     }
10942     if(us2[i]>0)
10943     {
10944       if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10945     }
10946     if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
10947     {
10948       if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
10949     }
10950     if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
10951     {
10952       if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
10953     }
10954     requires_32bit[i]=r32;
10955
10956     // Dirty registers which are 32-bit, require 32-bit input
10957     // as they will be written as 32-bit values
10958     for(hr=0;hr<HOST_REGS;hr++)
10959     {
10960       if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
10961         if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
10962           if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
10963           requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
10964         }
10965       }
10966     }
10967     //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
10968   }
10969 #else
10970   for (i=slen-1;i>=0;i--)
10971   {
10972     if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10973     {
10974       // Conditional branch
10975       if((source[i]>>16)!=0x1000&&i<slen-2) {
10976         // Mark this address as a branch target since it may be called
10977         // upon return from interrupt
10978         bt[i+2]=1;
10979       }
10980     }
10981   }
10982 #endif
10983
10984   if(itype[slen-1]==SPAN) {
10985     bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
10986   }
10987
10988 #ifdef DISASM
10989   /* Debug/disassembly */
10990   for(i=0;i<slen;i++)
10991   {
10992     printf("U:");
10993     int r;
10994     for(r=1;r<=CCREG;r++) {
10995       if((unneeded_reg[i]>>r)&1) {
10996         if(r==HIREG) printf(" HI");
10997         else if(r==LOREG) printf(" LO");
10998         else printf(" r%d",r);
10999       }
11000     }
11001 #ifndef FORCE32
11002     printf(" UU:");
11003     for(r=1;r<=CCREG;r++) {
11004       if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
11005         if(r==HIREG) printf(" HI");
11006         else if(r==LOREG) printf(" LO");
11007         else printf(" r%d",r);
11008       }
11009     }
11010     printf(" 32:");
11011     for(r=0;r<=CCREG;r++) {
11012       //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
11013       if((regs[i].was32>>r)&1) {
11014         if(r==CCREG) printf(" CC");
11015         else if(r==HIREG) printf(" HI");
11016         else if(r==LOREG) printf(" LO");
11017         else printf(" r%d",r);
11018       }
11019     }
11020 #endif
11021     printf("\n");
11022     #if defined(__i386__) || defined(__x86_64__)
11023     printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
11024     #endif
11025     #ifdef __arm__
11026     printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
11027     #endif
11028     printf("needs: ");
11029     if(needed_reg[i]&1) printf("eax ");
11030     if((needed_reg[i]>>1)&1) printf("ecx ");
11031     if((needed_reg[i]>>2)&1) printf("edx ");
11032     if((needed_reg[i]>>3)&1) printf("ebx ");
11033     if((needed_reg[i]>>5)&1) printf("ebp ");
11034     if((needed_reg[i]>>6)&1) printf("esi ");
11035     if((needed_reg[i]>>7)&1) printf("edi ");
11036     printf("r:");
11037     for(r=0;r<=CCREG;r++) {
11038       //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
11039       if((requires_32bit[i]>>r)&1) {
11040         if(r==CCREG) printf(" CC");
11041         else if(r==HIREG) printf(" HI");
11042         else if(r==LOREG) printf(" LO");
11043         else printf(" r%d",r);
11044       }
11045     }
11046     printf("\n");
11047     /*printf("pr:");
11048     for(r=0;r<=CCREG;r++) {
11049       //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
11050       if((pr32[i]>>r)&1) {
11051         if(r==CCREG) printf(" CC");
11052         else if(r==HIREG) printf(" HI");
11053         else if(r==LOREG) printf(" LO");
11054         else printf(" r%d",r);
11055       }
11056     }
11057     if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
11058     printf("\n");*/
11059     #if defined(__i386__) || defined(__x86_64__)
11060     printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
11061     printf("dirty: ");
11062     if(regs[i].wasdirty&1) printf("eax ");
11063     if((regs[i].wasdirty>>1)&1) printf("ecx ");
11064     if((regs[i].wasdirty>>2)&1) printf("edx ");
11065     if((regs[i].wasdirty>>3)&1) printf("ebx ");
11066     if((regs[i].wasdirty>>5)&1) printf("ebp ");
11067     if((regs[i].wasdirty>>6)&1) printf("esi ");
11068     if((regs[i].wasdirty>>7)&1) printf("edi ");
11069     #endif
11070     #ifdef __arm__
11071     printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
11072     printf("dirty: ");
11073     if(regs[i].wasdirty&1) printf("r0 ");
11074     if((regs[i].wasdirty>>1)&1) printf("r1 ");
11075     if((regs[i].wasdirty>>2)&1) printf("r2 ");
11076     if((regs[i].wasdirty>>3)&1) printf("r3 ");
11077     if((regs[i].wasdirty>>4)&1) printf("r4 ");
11078     if((regs[i].wasdirty>>5)&1) printf("r5 ");
11079     if((regs[i].wasdirty>>6)&1) printf("r6 ");
11080     if((regs[i].wasdirty>>7)&1) printf("r7 ");
11081     if((regs[i].wasdirty>>8)&1) printf("r8 ");
11082     if((regs[i].wasdirty>>9)&1) printf("r9 ");
11083     if((regs[i].wasdirty>>10)&1) printf("r10 ");
11084     if((regs[i].wasdirty>>12)&1) printf("r12 ");
11085     #endif
11086     printf("\n");
11087     disassemble_inst(i);
11088     //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
11089     #if defined(__i386__) || defined(__x86_64__)
11090     printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
11091     if(regs[i].dirty&1) printf("eax ");
11092     if((regs[i].dirty>>1)&1) printf("ecx ");
11093     if((regs[i].dirty>>2)&1) printf("edx ");
11094     if((regs[i].dirty>>3)&1) printf("ebx ");
11095     if((regs[i].dirty>>5)&1) printf("ebp ");
11096     if((regs[i].dirty>>6)&1) printf("esi ");
11097     if((regs[i].dirty>>7)&1) printf("edi ");
11098     #endif
11099     #ifdef __arm__
11100     printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
11101     if(regs[i].dirty&1) printf("r0 ");
11102     if((regs[i].dirty>>1)&1) printf("r1 ");
11103     if((regs[i].dirty>>2)&1) printf("r2 ");
11104     if((regs[i].dirty>>3)&1) printf("r3 ");
11105     if((regs[i].dirty>>4)&1) printf("r4 ");
11106     if((regs[i].dirty>>5)&1) printf("r5 ");
11107     if((regs[i].dirty>>6)&1) printf("r6 ");
11108     if((regs[i].dirty>>7)&1) printf("r7 ");
11109     if((regs[i].dirty>>8)&1) printf("r8 ");
11110     if((regs[i].dirty>>9)&1) printf("r9 ");
11111     if((regs[i].dirty>>10)&1) printf("r10 ");
11112     if((regs[i].dirty>>12)&1) printf("r12 ");
11113     #endif
11114     printf("\n");
11115     if(regs[i].isconst) {
11116       printf("constants: ");
11117       #if defined(__i386__) || defined(__x86_64__)
11118       if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
11119       if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
11120       if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
11121       if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
11122       if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
11123       if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
11124       if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
11125       #endif
11126       #ifdef __arm__
11127       if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
11128       if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
11129       if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
11130       if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
11131       if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
11132       if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
11133       if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
11134       if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
11135       if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
11136       if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
11137       if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
11138       if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
11139       #endif
11140       printf("\n");
11141     }
11142 #ifndef FORCE32
11143     printf(" 32:");
11144     for(r=0;r<=CCREG;r++) {
11145       if((regs[i].is32>>r)&1) {
11146         if(r==CCREG) printf(" CC");
11147         else if(r==HIREG) printf(" HI");
11148         else if(r==LOREG) printf(" LO");
11149         else printf(" r%d",r);
11150       }
11151     }
11152     printf("\n");
11153 #endif
11154     /*printf(" p32:");
11155     for(r=0;r<=CCREG;r++) {
11156       if((p32[i]>>r)&1) {
11157         if(r==CCREG) printf(" CC");
11158         else if(r==HIREG) printf(" HI");
11159         else if(r==LOREG) printf(" LO");
11160         else printf(" r%d",r);
11161       }
11162     }
11163     if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
11164     else printf("\n");*/
11165     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
11166       #if defined(__i386__) || defined(__x86_64__)
11167       printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
11168       if(branch_regs[i].dirty&1) printf("eax ");
11169       if((branch_regs[i].dirty>>1)&1) printf("ecx ");
11170       if((branch_regs[i].dirty>>2)&1) printf("edx ");
11171       if((branch_regs[i].dirty>>3)&1) printf("ebx ");
11172       if((branch_regs[i].dirty>>5)&1) printf("ebp ");
11173       if((branch_regs[i].dirty>>6)&1) printf("esi ");
11174       if((branch_regs[i].dirty>>7)&1) printf("edi ");
11175       #endif
11176       #ifdef __arm__
11177       printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
11178       if(branch_regs[i].dirty&1) printf("r0 ");
11179       if((branch_regs[i].dirty>>1)&1) printf("r1 ");
11180       if((branch_regs[i].dirty>>2)&1) printf("r2 ");
11181       if((branch_regs[i].dirty>>3)&1) printf("r3 ");
11182       if((branch_regs[i].dirty>>4)&1) printf("r4 ");
11183       if((branch_regs[i].dirty>>5)&1) printf("r5 ");
11184       if((branch_regs[i].dirty>>6)&1) printf("r6 ");
11185       if((branch_regs[i].dirty>>7)&1) printf("r7 ");
11186       if((branch_regs[i].dirty>>8)&1) printf("r8 ");
11187       if((branch_regs[i].dirty>>9)&1) printf("r9 ");
11188       if((branch_regs[i].dirty>>10)&1) printf("r10 ");
11189       if((branch_regs[i].dirty>>12)&1) printf("r12 ");
11190       #endif
11191 #ifndef FORCE32
11192       printf(" 32:");
11193       for(r=0;r<=CCREG;r++) {
11194         if((branch_regs[i].is32>>r)&1) {
11195           if(r==CCREG) printf(" CC");
11196           else if(r==HIREG) printf(" HI");
11197           else if(r==LOREG) printf(" LO");
11198           else printf(" r%d",r);
11199         }
11200       }
11201       printf("\n");
11202 #endif
11203     }
11204   }
11205 #endif // DISASM
11206
11207   /* Pass 8 - Assembly */
11208   linkcount=0;stubcount=0;
11209   ds=0;is_delayslot=0;
11210   cop1_usable=0;
11211   uint64_t is32_pre=0;
11212   u_int dirty_pre=0;
11213   u_int beginning=(u_int)out;
11214   if((u_int)addr&1) {
11215     ds=1;
11216     pagespan_ds();
11217   }
11218   u_int instr_addr0_override=0;
11219
11220 #ifdef PCSX
11221   if (start == 0x80030000) {
11222     // nasty hack for fastbios thing
11223     // override block entry to this code
11224     instr_addr0_override=(u_int)out;
11225     emit_movimm(start,0);
11226     // abuse io address var as a flag that we
11227     // have already returned here once
11228     emit_readword((int)&address,1);
11229     emit_writeword(0,(int)&pcaddr);
11230     emit_writeword(0,(int)&address);
11231     emit_cmp(0,1);
11232     emit_jne((int)new_dyna_leave);
11233   }
11234 #endif
11235   for(i=0;i<slen;i++)
11236   {
11237     //if(ds) printf("ds: ");
11238     disassemble_inst(i);
11239     if(ds) {
11240       ds=0; // Skip delay slot
11241       if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
11242       instr_addr[i]=0;
11243     } else {
11244       speculate_register_values(i);
11245       #ifndef DESTRUCTIVE_WRITEBACK
11246       if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11247       {
11248         wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
11249               unneeded_reg[i],unneeded_reg_upper[i]);
11250         wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
11251               unneeded_reg[i],unneeded_reg_upper[i]);
11252       }
11253       if((itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)&&!likely[i]) {
11254         is32_pre=branch_regs[i].is32;
11255         dirty_pre=branch_regs[i].dirty;
11256       }else{
11257         is32_pre=regs[i].is32;
11258         dirty_pre=regs[i].dirty;
11259       }
11260       #endif
11261       // write back
11262       if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11263       {
11264         wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
11265                       unneeded_reg[i],unneeded_reg_upper[i]);
11266         loop_preload(regmap_pre[i],regs[i].regmap_entry);
11267       }
11268       // branch target entry point
11269       instr_addr[i]=(u_int)out;
11270       assem_debug("<->\n");
11271       // load regs
11272       if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
11273         wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
11274       load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
11275       address_generation(i,&regs[i],regs[i].regmap_entry);
11276       load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
11277       if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
11278       {
11279         // Load the delay slot registers if necessary
11280         if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i]&&(rs1[i+1]!=rt1[i]||rt1[i]==0))
11281           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11282         if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i]&&(rs2[i+1]!=rt1[i]||rt1[i]==0))
11283           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11284         if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
11285           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11286       }
11287       else if(i+1<slen)
11288       {
11289         // Preload registers for following instruction
11290         if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
11291           if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
11292             load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11293         if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
11294           if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
11295             load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11296       }
11297       // TODO: if(is_ooo(i)) address_generation(i+1);
11298       if(itype[i]==CJUMP||itype[i]==FJUMP)
11299         load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
11300       if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
11301         load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11302       if(bt[i]) cop1_usable=0;
11303       // assemble
11304       switch(itype[i]) {
11305         case ALU:
11306           alu_assemble(i,&regs[i]);break;
11307         case IMM16:
11308           imm16_assemble(i,&regs[i]);break;
11309         case SHIFT:
11310           shift_assemble(i,&regs[i]);break;
11311         case SHIFTIMM:
11312           shiftimm_assemble(i,&regs[i]);break;
11313         case LOAD:
11314           load_assemble(i,&regs[i]);break;
11315         case LOADLR:
11316           loadlr_assemble(i,&regs[i]);break;
11317         case STORE:
11318           store_assemble(i,&regs[i]);break;
11319         case STORELR:
11320           storelr_assemble(i,&regs[i]);break;
11321         case COP0:
11322           cop0_assemble(i,&regs[i]);break;
11323         case COP1:
11324           cop1_assemble(i,&regs[i]);break;
11325         case C1LS:
11326           c1ls_assemble(i,&regs[i]);break;
11327         case COP2:
11328           cop2_assemble(i,&regs[i]);break;
11329         case C2LS:
11330           c2ls_assemble(i,&regs[i]);break;
11331         case C2OP:
11332           c2op_assemble(i,&regs[i]);break;
11333         case FCONV:
11334           fconv_assemble(i,&regs[i]);break;
11335         case FLOAT:
11336           float_assemble(i,&regs[i]);break;
11337         case FCOMP:
11338           fcomp_assemble(i,&regs[i]);break;
11339         case MULTDIV:
11340           multdiv_assemble(i,&regs[i]);break;
11341         case MOV:
11342           mov_assemble(i,&regs[i]);break;
11343         case SYSCALL:
11344           syscall_assemble(i,&regs[i]);break;
11345         case HLECALL:
11346           hlecall_assemble(i,&regs[i]);break;
11347         case INTCALL:
11348           intcall_assemble(i,&regs[i]);break;
11349         case UJUMP:
11350           ujump_assemble(i,&regs[i]);ds=1;break;
11351         case RJUMP:
11352           rjump_assemble(i,&regs[i]);ds=1;break;
11353         case CJUMP:
11354           cjump_assemble(i,&regs[i]);ds=1;break;
11355         case SJUMP:
11356           sjump_assemble(i,&regs[i]);ds=1;break;
11357         case FJUMP:
11358           fjump_assemble(i,&regs[i]);ds=1;break;
11359         case SPAN:
11360           pagespan_assemble(i,&regs[i]);break;
11361       }
11362       if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
11363         literal_pool(1024);
11364       else
11365         literal_pool_jumpover(256);
11366     }
11367   }
11368   //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
11369   // If the block did not end with an unconditional branch,
11370   // add a jump to the next instruction.
11371   if(i>1) {
11372     if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
11373       assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11374       assert(i==slen);
11375       if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
11376         store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11377         if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11378           emit_loadreg(CCREG,HOST_CCREG);
11379         emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
11380       }
11381       else if(!likely[i-2])
11382       {
11383         store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
11384         assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
11385       }
11386       else
11387       {
11388         store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
11389         assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
11390       }
11391       add_to_linker((int)out,start+i*4,0);
11392       emit_jmp(0);
11393     }
11394   }
11395   else
11396   {
11397     assert(i>0);
11398     assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11399     store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11400     if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11401       emit_loadreg(CCREG,HOST_CCREG);
11402     emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
11403     add_to_linker((int)out,start+i*4,0);
11404     emit_jmp(0);
11405   }
11406
11407   // TODO: delay slot stubs?
11408   // Stubs
11409   for(i=0;i<stubcount;i++)
11410   {
11411     switch(stubs[i][0])
11412     {
11413       case LOADB_STUB:
11414       case LOADH_STUB:
11415       case LOADW_STUB:
11416       case LOADD_STUB:
11417       case LOADBU_STUB:
11418       case LOADHU_STUB:
11419         do_readstub(i);break;
11420       case STOREB_STUB:
11421       case STOREH_STUB:
11422       case STOREW_STUB:
11423       case STORED_STUB:
11424         do_writestub(i);break;
11425       case CC_STUB:
11426         do_ccstub(i);break;
11427       case INVCODE_STUB:
11428         do_invstub(i);break;
11429       case FP_STUB:
11430         do_cop1stub(i);break;
11431       case STORELR_STUB:
11432         do_unalignedwritestub(i);break;
11433     }
11434   }
11435
11436   if (instr_addr0_override)
11437     instr_addr[0] = instr_addr0_override;
11438
11439   /* Pass 9 - Linker */
11440   for(i=0;i<linkcount;i++)
11441   {
11442     assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
11443     literal_pool(64);
11444     if(!link_addr[i][2])
11445     {
11446       void *stub=out;
11447       void *addr=check_addr(link_addr[i][1]);
11448       emit_extjump(link_addr[i][0],link_addr[i][1]);
11449       if(addr) {
11450         set_jump_target(link_addr[i][0],(int)addr);
11451         add_link(link_addr[i][1],stub);
11452       }
11453       else set_jump_target(link_addr[i][0],(int)stub);
11454     }
11455     else
11456     {
11457       // Internal branch
11458       int target=(link_addr[i][1]-start)>>2;
11459       assert(target>=0&&target<slen);
11460       assert(instr_addr[target]);
11461       //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11462       //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
11463       //#else
11464       set_jump_target(link_addr[i][0],instr_addr[target]);
11465       //#endif
11466     }
11467   }
11468   // External Branch Targets (jump_in)
11469   if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
11470   for(i=0;i<slen;i++)
11471   {
11472     if(bt[i]||i==0)
11473     {
11474       if(instr_addr[i]) // TODO - delay slots (=null)
11475       {
11476         u_int vaddr=start+i*4;
11477         u_int page=get_page(vaddr);
11478         u_int vpage=get_vpage(vaddr);
11479         literal_pool(256);
11480         {
11481           assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11482           assem_debug("jump_in: %x\n",start+i*4);
11483           ll_add(jump_dirty+vpage,vaddr,(void *)out);
11484           int entry_point=do_dirty_stub(i);
11485           ll_add(jump_in+page,vaddr,(void *)entry_point);
11486           // If there was an existing entry in the hash table,
11487           // replace it with the new address.
11488           // Don't add new entries.  We'll insert the
11489           // ones that actually get used in check_addr().
11490           int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
11491           if(ht_bin[0]==vaddr) {
11492             ht_bin[1]=entry_point;
11493           }
11494           if(ht_bin[2]==vaddr) {
11495             ht_bin[3]=entry_point;
11496           }
11497         }
11498       }
11499     }
11500   }
11501   // Write out the literal pool if necessary
11502   literal_pool(0);
11503   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11504   // Align code
11505   if(((u_int)out)&7) emit_addnop(13);
11506   #endif
11507   assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
11508   //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
11509   memcpy(copy,source,slen*4);
11510   copy+=slen*4;
11511
11512   #ifdef __arm__
11513   __clear_cache((void *)beginning,out);
11514   #endif
11515
11516   // If we're within 256K of the end of the buffer,
11517   // start over from the beginning. (Is 256K enough?)
11518   if((u_int)out>(u_int)BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
11519
11520   // Trap writes to any of the pages we compiled
11521   for(i=start>>12;i<=(start+slen*4)>>12;i++) {
11522     invalid_code[i]=0;
11523 #ifndef DISABLE_TLB
11524     memory_map[i]|=0x40000000;
11525     if((signed int)start>=(signed int)0xC0000000) {
11526       assert(using_tlb);
11527       j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
11528       invalid_code[j]=0;
11529       memory_map[j]|=0x40000000;
11530       //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
11531     }
11532 #endif
11533   }
11534   inv_code_start=inv_code_end=~0;
11535 #ifdef PCSX
11536   // for PCSX we need to mark all mirrors too
11537   if(get_page(start)<(RAM_SIZE>>12))
11538     for(i=start>>12;i<=(start+slen*4)>>12;i++)
11539       invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]=
11540       invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]=
11541       invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0;
11542 #endif
11543
11544   /* Pass 10 - Free memory by expiring oldest blocks */
11545
11546   int end=((((int)out-(int)BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
11547   while(expirep!=end)
11548   {
11549     int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
11550     int base=(int)BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
11551     inv_debug("EXP: Phase %d\n",expirep);
11552     switch((expirep>>11)&3)
11553     {
11554       case 0:
11555         // Clear jump_in and jump_dirty
11556         ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
11557         ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
11558         ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
11559         ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
11560         break;
11561       case 1:
11562         // Clear pointers
11563         ll_kill_pointers(jump_out[expirep&2047],base,shift);
11564         ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
11565         break;
11566       case 2:
11567         // Clear hash table
11568         for(i=0;i<32;i++) {
11569           int *ht_bin=hash_table[((expirep&2047)<<5)+i];
11570           if((ht_bin[3]>>shift)==(base>>shift) ||
11571              ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11572             inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
11573             ht_bin[2]=ht_bin[3]=-1;
11574           }
11575           if((ht_bin[1]>>shift)==(base>>shift) ||
11576              ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11577             inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
11578             ht_bin[0]=ht_bin[2];
11579             ht_bin[1]=ht_bin[3];
11580             ht_bin[2]=ht_bin[3]=-1;
11581           }
11582         }
11583         break;
11584       case 3:
11585         // Clear jump_out
11586         #ifdef __arm__
11587         if((expirep&2047)==0)
11588           do_clear_cache();
11589         #endif
11590         ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
11591         ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
11592         break;
11593     }
11594     expirep=(expirep+1)&65535;
11595   }
11596   return 0;
11597 }
11598
11599 // vim:shiftwidth=2:expandtab