1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2010 Ari64 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include <stdint.h> //include for uint64_t
25 #include "emu_if.h" //emulator interface
30 #include "assem_x86.h"
33 #include "assem_x64.h"
36 #include "assem_arm.h"
40 #define MAX_OUTPUT_BLOCK_SIZE 262144
41 #define CLOCK_DIVIDER 2
45 signed char regmap_entry[HOST_REGS];
46 signed char regmap[HOST_REGS];
55 uint64_t constmap[HOST_REGS];
63 struct ll_entry *next;
69 char insn[MAXBLOCK][10];
70 u_char itype[MAXBLOCK];
71 u_char opcode[MAXBLOCK];
72 u_char opcode2[MAXBLOCK];
80 u_char dep1[MAXBLOCK];
81 u_char dep2[MAXBLOCK];
85 char likely[MAXBLOCK];
88 uint64_t unneeded_reg[MAXBLOCK];
89 uint64_t unneeded_reg_upper[MAXBLOCK];
90 uint64_t branch_unneeded_reg[MAXBLOCK];
91 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
92 uint64_t p32[MAXBLOCK];
93 uint64_t pr32[MAXBLOCK];
94 signed char regmap_pre[MAXBLOCK][HOST_REGS];
95 signed char regmap[MAXBLOCK][HOST_REGS];
96 signed char regmap_entry[MAXBLOCK][HOST_REGS];
97 uint64_t constmap[MAXBLOCK][HOST_REGS];
98 struct regstat regs[MAXBLOCK];
99 struct regstat branch_regs[MAXBLOCK];
100 signed char minimum_free_regs[MAXBLOCK];
101 u_int needed_reg[MAXBLOCK];
102 uint64_t requires_32bit[MAXBLOCK];
103 u_int wont_dirty[MAXBLOCK];
104 u_int will_dirty[MAXBLOCK];
107 u_int instr_addr[MAXBLOCK];
108 u_int link_addr[MAXBLOCK][3];
110 u_int stubs[MAXBLOCK*3][8];
112 u_int literals[1024][2];
117 struct ll_entry *jump_in[4096];
118 struct ll_entry *jump_out[4096];
119 struct ll_entry *jump_dirty[4096];
120 u_int hash_table[65536][4] __attribute__((aligned(16)));
121 char shadow[1048576] __attribute__((aligned(16)));
125 u_int stop_after_jal;
126 extern u_char restore_candidate[512];
127 extern int cycle_count;
129 /* registers that may be allocated */
131 #define HIREG 32 // hi
132 #define LOREG 33 // lo
133 #define FSREG 34 // FPU status (FCSR)
134 #define CSREG 35 // Coprocessor status
135 #define CCREG 36 // Cycle count
136 #define INVCP 37 // Pointer to invalid_code
138 #define FTEMP 38 // FPU/LDL/LDR temporary register
139 #define PTEMP 39 // Prefetch temporary register
140 #define TLREG 40 // TLB mapping offset
141 #define RHASH 41 // Return address hash
142 #define RHTBL 42 // Return address hash table address
143 #define RTEMP 43 // JR/JALR address register
145 #define AGEN1 44 // Address generation temporary register
146 #define AGEN2 45 // Address generation temporary register
147 #define MGEN1 46 // Maptable address generation temporary register
148 #define MGEN2 47 // Maptable address generation temporary register
149 #define BTREG 48 // Branch target temporary register
151 /* instruction types */
152 #define NOP 0 // No operation
153 #define LOAD 1 // Load
154 #define STORE 2 // Store
155 #define LOADLR 3 // Unaligned load
156 #define STORELR 4 // Unaligned store
157 #define MOV 5 // Move
158 #define ALU 6 // Arithmetic/logic
159 #define MULTDIV 7 // Multiply/divide
160 #define SHIFT 8 // Shift by register
161 #define SHIFTIMM 9// Shift by immediate
162 #define IMM16 10 // 16-bit immediate
163 #define RJUMP 11 // Unconditional jump to register
164 #define UJUMP 12 // Unconditional jump
165 #define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
166 #define SJUMP 14 // Conditional branch (regimm format)
167 #define COP0 15 // Coprocessor 0
168 #define COP1 16 // Coprocessor 1
169 #define C1LS 17 // Coprocessor 1 load/store
170 #define FJUMP 18 // Conditional branch (floating point)
171 #define FLOAT 19 // Floating point unit
172 #define FCONV 20 // Convert integer to float
173 #define FCOMP 21 // Floating point compare (sets FSREG)
174 #define SYSCALL 22// SYSCALL
175 #define OTHER 23 // Other
176 #define SPAN 24 // Branch/delay slot spans 2 pages
177 #define NI 25 // Not implemented
178 #define HLECALL 26// PCSX fake opcodes for HLE
179 #define COP2 27 // Coprocessor 2 move
180 #define C2LS 28 // Coprocessor 2 load/store
181 #define C2OP 29 // Coprocessor 2 operation
182 #define INTCALL 30// Call interpreter to handle rare corner cases
191 #define LOADBU_STUB 7
192 #define LOADHU_STUB 8
193 #define STOREB_STUB 9
194 #define STOREH_STUB 10
195 #define STOREW_STUB 11
196 #define STORED_STUB 12
197 #define STORELR_STUB 13
198 #define INVCODE_STUB 14
206 int new_recompile_block(int addr);
207 void *get_addr_ht(u_int vaddr);
208 void invalidate_block(u_int block);
209 void invalidate_addr(u_int addr);
210 void remove_hash(int vaddr);
213 void dyna_linker_ds();
215 void verify_code_vm();
216 void verify_code_ds();
219 void fp_exception_ds();
221 void jump_syscall_hle();
225 void new_dyna_leave();
230 void read_nomem_new();
231 void read_nomemb_new();
232 void read_nomemh_new();
233 void read_nomemd_new();
234 void write_nomem_new();
235 void write_nomemb_new();
236 void write_nomemh_new();
237 void write_nomemd_new();
238 void write_rdram_new();
239 void write_rdramb_new();
240 void write_rdramh_new();
241 void write_rdramd_new();
242 extern u_int memory_map[1048576];
244 // Needed by assembler
245 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
246 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
247 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
248 void load_all_regs(signed char i_regmap[]);
249 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
250 void load_regs_entry(int t);
251 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
255 //#define DEBUG_CYCLE_COUNT 1
258 //#define assem_debug printf
259 //#define inv_debug printf
260 #define assem_debug nullf
261 #define inv_debug nullf
263 static void tlb_hacks()
267 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
271 switch (ROM_HEADER->Country_code&0xFF)
283 // Unknown country code
287 u_int rom_addr=(u_int)rom;
289 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
290 // in the lower 4G of memory to use this hack. Copy it if necessary.
291 if((void *)rom>(void *)0xffffffff) {
292 munmap(ROM_COPY, 67108864);
293 if(mmap(ROM_COPY, 12582912,
294 PROT_READ | PROT_WRITE,
295 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
296 -1, 0) <= 0) {printf("mmap() failed\n");}
297 memcpy(ROM_COPY,rom,12582912);
298 rom_addr=(u_int)ROM_COPY;
302 for(n=0x7F000;n<0x80000;n++) {
303 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
310 static u_int get_page(u_int vaddr)
313 u_int page=(vaddr^0x80000000)>>12;
315 u_int page=vaddr&~0xe0000000;
316 if (page < 0x1000000)
317 page &= ~0x0e00000; // RAM mirrors
321 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
323 if(page>2048) page=2048+(page&2047);
327 static u_int get_vpage(u_int vaddr)
329 u_int vpage=(vaddr^0x80000000)>>12;
331 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
333 if(vpage>2048) vpage=2048+(vpage&2047);
337 // Get address from virtual address
338 // This is called from the recompiled JR/JALR instructions
339 void *get_addr(u_int vaddr)
341 u_int page=get_page(vaddr);
342 u_int vpage=get_vpage(vaddr);
343 struct ll_entry *head;
344 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
347 if(head->vaddr==vaddr&&head->reg32==0) {
348 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
349 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
352 ht_bin[1]=(int)head->addr;
358 head=jump_dirty[vpage];
360 if(head->vaddr==vaddr&&head->reg32==0) {
361 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
362 // Don't restore blocks which are about to expire from the cache
363 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
364 if(verify_dirty(head->addr)) {
365 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
366 invalid_code[vaddr>>12]=0;
367 memory_map[vaddr>>12]|=0x40000000;
370 if(tlb_LUT_r[vaddr>>12]) {
371 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
372 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
375 restore_candidate[vpage>>3]|=1<<(vpage&7);
377 else restore_candidate[page>>3]|=1<<(page&7);
378 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
379 if(ht_bin[0]==vaddr) {
380 ht_bin[1]=(int)head->addr; // Replace existing entry
386 ht_bin[1]=(int)head->addr;
394 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
395 int r=new_recompile_block(vaddr);
396 if(r==0) return get_addr(vaddr);
397 // Execute in unmapped page, generate pagefault execption
399 Cause=(vaddr<<31)|0x8;
400 EPC=(vaddr&1)?vaddr-5:vaddr;
402 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
403 EntryHi=BadVAddr&0xFFFFE000;
404 return get_addr_ht(0x80000000);
406 // Look up address in hash table first
407 void *get_addr_ht(u_int vaddr)
409 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
410 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
411 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
412 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
413 return get_addr(vaddr);
416 void *get_addr_32(u_int vaddr,u_int flags)
419 return get_addr(vaddr);
421 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
422 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
423 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
424 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
425 u_int page=get_page(vaddr);
426 u_int vpage=get_vpage(vaddr);
427 struct ll_entry *head;
430 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
431 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
433 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
435 ht_bin[1]=(int)head->addr;
437 }else if(ht_bin[2]==-1) {
438 ht_bin[3]=(int)head->addr;
441 //ht_bin[3]=ht_bin[1];
442 //ht_bin[2]=ht_bin[0];
443 //ht_bin[1]=(int)head->addr;
450 head=jump_dirty[vpage];
452 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
453 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
454 // Don't restore blocks which are about to expire from the cache
455 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
456 if(verify_dirty(head->addr)) {
457 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
458 invalid_code[vaddr>>12]=0;
459 memory_map[vaddr>>12]|=0x40000000;
462 if(tlb_LUT_r[vaddr>>12]) {
463 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
464 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
467 restore_candidate[vpage>>3]|=1<<(vpage&7);
469 else restore_candidate[page>>3]|=1<<(page&7);
471 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
473 ht_bin[1]=(int)head->addr;
475 }else if(ht_bin[2]==-1) {
476 ht_bin[3]=(int)head->addr;
479 //ht_bin[3]=ht_bin[1];
480 //ht_bin[2]=ht_bin[0];
481 //ht_bin[1]=(int)head->addr;
489 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
490 int r=new_recompile_block(vaddr);
491 if(r==0) return get_addr(vaddr);
492 // Execute in unmapped page, generate pagefault execption
494 Cause=(vaddr<<31)|0x8;
495 EPC=(vaddr&1)?vaddr-5:vaddr;
497 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
498 EntryHi=BadVAddr&0xFFFFE000;
499 return get_addr_ht(0x80000000);
503 void clear_all_regs(signed char regmap[])
506 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
509 signed char get_reg(signed char regmap[],int r)
512 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map[hr]==r) return hr;
516 // Find a register that is available for two consecutive cycles
517 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
520 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr;
524 int count_free_regs(signed char regmap[])
528 for(hr=0;hr<HOST_REGS;hr++)
530 if(hr!=EXCLUDE_REG) {
531 if(regmap[hr]<0) count++;
537 void dirty_reg(struct regstat *cur,signed char reg)
541 for (hr=0;hr<HOST_REGS;hr++) {
542 if((cur->regmap[hr]&63)==reg) {
548 // If we dirty the lower half of a 64 bit register which is now being
549 // sign-extended, we need to dump the upper half.
550 // Note: Do this only after completion of the instruction, because
551 // some instructions may need to read the full 64-bit value even if
552 // overwriting it (eg SLTI, DSRA32).
553 static void flush_dirty_uppers(struct regstat *cur)
556 for (hr=0;hr<HOST_REGS;hr++) {
557 if((cur->dirty>>hr)&1) {
560 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
565 void set_const(struct regstat *cur,signed char reg,uint64_t value)
569 for (hr=0;hr<HOST_REGS;hr++) {
570 if(cur->regmap[hr]==reg) {
572 cur->constmap[hr]=value;
574 else if((cur->regmap[hr]^64)==reg) {
576 cur->constmap[hr]=value>>32;
581 void clear_const(struct regstat *cur,signed char reg)
585 for (hr=0;hr<HOST_REGS;hr++) {
586 if((cur->regmap[hr]&63)==reg) {
587 cur->isconst&=~(1<<hr);
592 int is_const(struct regstat *cur,signed char reg)
596 for (hr=0;hr<HOST_REGS;hr++) {
597 if((cur->regmap[hr]&63)==reg) {
598 return (cur->isconst>>hr)&1;
603 uint64_t get_const(struct regstat *cur,signed char reg)
607 for (hr=0;hr<HOST_REGS;hr++) {
608 if(cur->regmap[hr]==reg) {
609 return cur->constmap[hr];
612 printf("Unknown constant in r%d\n",reg);
616 // Least soon needed registers
617 // Look at the next ten instructions and see which registers
618 // will be used. Try not to reallocate these.
619 void lsn(u_char hsn[], int i, int *preferred_reg)
629 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
631 // Don't go past an unconditonal jump
638 if(rs1[i+j]) hsn[rs1[i+j]]=j;
639 if(rs2[i+j]) hsn[rs2[i+j]]=j;
640 if(rt1[i+j]) hsn[rt1[i+j]]=j;
641 if(rt2[i+j]) hsn[rt2[i+j]]=j;
642 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
643 // Stores can allocate zero
647 // On some architectures stores need invc_ptr
648 #if defined(HOST_IMM8)
649 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
653 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
661 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
663 // Follow first branch
664 int t=(ba[i+b]-start)>>2;
665 j=7-b;if(t+j>=slen) j=slen-t-1;
668 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
669 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
670 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
671 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
674 // TODO: preferred register based on backward branch
676 // Delay slot should preferably not overwrite branch conditions or cycle count
677 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
678 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
679 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
685 // Coprocessor load/store needs FTEMP, even if not declared
686 if(itype[i]==C1LS||itype[i]==C2LS) {
689 // Load L/R also uses FTEMP as a temporary register
690 if(itype[i]==LOADLR) {
693 // Also SWL/SWR/SDL/SDR
694 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
697 // Don't remove the TLB registers either
698 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
701 // Don't remove the miniht registers
702 if(itype[i]==UJUMP||itype[i]==RJUMP)
709 // We only want to allocate registers if we're going to use them again soon
710 int needed_again(int r, int i)
716 u_char hsn[MAXREG+1];
719 memset(hsn,10,sizeof(hsn));
720 lsn(hsn,i,&preferred_reg);
722 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
724 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
725 return 0; // Don't need any registers if exiting the block
733 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
735 // Don't go past an unconditonal jump
739 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
746 if(rs1[i+j]==r) rn=j;
747 if(rs2[i+j]==r) rn=j;
748 if((unneeded_reg[i+j]>>r)&1) rn=10;
749 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
757 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
759 // Follow first branch
761 int t=(ba[i+b]-start)>>2;
762 j=7-b;if(t+j>=slen) j=slen-t-1;
765 if(!((unneeded_reg[t+j]>>r)&1)) {
766 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
767 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
773 for(hr=0;hr<HOST_REGS;hr++) {
774 if(hr!=EXCLUDE_REG) {
775 if(rn<hsn[hr]) return 1;
781 // Try to match register allocations at the end of a loop with those
783 int loop_reg(int i, int r, int hr)
792 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
794 // Don't go past an unconditonal jump
801 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
806 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
807 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
808 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
810 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
812 int t=(ba[i+k]-start)>>2;
813 int reg=get_reg(regs[t].regmap_entry,r);
814 if(reg>=0) return reg;
815 //reg=get_reg(regs[t+1].regmap_entry,r);
816 //if(reg>=0) return reg;
824 // Allocate every register, preserving source/target regs
825 void alloc_all(struct regstat *cur,int i)
829 for(hr=0;hr<HOST_REGS;hr++) {
830 if(hr!=EXCLUDE_REG) {
831 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
832 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
835 cur->dirty&=~(1<<hr);
838 if((cur->regmap[hr]&63)==0)
841 cur->dirty&=~(1<<hr);
848 void div64(int64_t dividend,int64_t divisor)
852 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
853 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
855 void divu64(uint64_t dividend,uint64_t divisor)
859 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
860 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
863 void mult64(uint64_t m1,uint64_t m2)
865 unsigned long long int op1, op2, op3, op4;
866 unsigned long long int result1, result2, result3, result4;
867 unsigned long long int temp1, temp2, temp3, temp4;
883 op1 = op2 & 0xFFFFFFFF;
884 op2 = (op2 >> 32) & 0xFFFFFFFF;
885 op3 = op4 & 0xFFFFFFFF;
886 op4 = (op4 >> 32) & 0xFFFFFFFF;
889 temp2 = (temp1 >> 32) + op1 * op4;
891 temp4 = (temp3 >> 32) + op2 * op4;
893 result1 = temp1 & 0xFFFFFFFF;
894 result2 = temp2 + (temp3 & 0xFFFFFFFF);
895 result3 = (result2 >> 32) + temp4;
896 result4 = (result3 >> 32);
898 lo = result1 | (result2 << 32);
899 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
908 void multu64(uint64_t m1,uint64_t m2)
910 unsigned long long int op1, op2, op3, op4;
911 unsigned long long int result1, result2, result3, result4;
912 unsigned long long int temp1, temp2, temp3, temp4;
914 op1 = m1 & 0xFFFFFFFF;
915 op2 = (m1 >> 32) & 0xFFFFFFFF;
916 op3 = m2 & 0xFFFFFFFF;
917 op4 = (m2 >> 32) & 0xFFFFFFFF;
920 temp2 = (temp1 >> 32) + op1 * op4;
922 temp4 = (temp3 >> 32) + op2 * op4;
924 result1 = temp1 & 0xFFFFFFFF;
925 result2 = temp2 + (temp3 & 0xFFFFFFFF);
926 result3 = (result2 >> 32) + temp4;
927 result4 = (result3 >> 32);
929 lo = result1 | (result2 << 32);
930 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
932 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
933 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
936 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
944 else original=loaded;
947 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
950 original>>=64-(bits^56);
951 original<<=64-(bits^56);
955 else original=loaded;
960 #include "assem_x86.c"
963 #include "assem_x64.c"
966 #include "assem_arm.c"
969 // Add virtual address mapping to linked list
970 void ll_add(struct ll_entry **head,int vaddr,void *addr)
972 struct ll_entry *new_entry;
973 new_entry=malloc(sizeof(struct ll_entry));
974 assert(new_entry!=NULL);
975 new_entry->vaddr=vaddr;
977 new_entry->addr=addr;
978 new_entry->next=*head;
982 // Add virtual address mapping for 32-bit compiled block
983 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
985 ll_add(head,vaddr,addr);
987 (*head)->reg32=reg32;
991 // Check if an address is already compiled
992 // but don't return addresses which are about to expire from the cache
993 void *check_addr(u_int vaddr)
995 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
996 if(ht_bin[0]==vaddr) {
997 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
998 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
1000 if(ht_bin[2]==vaddr) {
1001 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1002 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1004 u_int page=get_page(vaddr);
1005 struct ll_entry *head;
1008 if(head->vaddr==vaddr&&head->reg32==0) {
1009 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1010 // Update existing entry with current address
1011 if(ht_bin[0]==vaddr) {
1012 ht_bin[1]=(int)head->addr;
1015 if(ht_bin[2]==vaddr) {
1016 ht_bin[3]=(int)head->addr;
1019 // Insert into hash table with low priority.
1020 // Don't evict existing entries, as they are probably
1021 // addresses that are being accessed frequently.
1023 ht_bin[1]=(int)head->addr;
1025 }else if(ht_bin[2]==-1) {
1026 ht_bin[3]=(int)head->addr;
1037 void remove_hash(int vaddr)
1039 //printf("remove hash: %x\n",vaddr);
1040 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1041 if(ht_bin[2]==vaddr) {
1042 ht_bin[2]=ht_bin[3]=-1;
1044 if(ht_bin[0]==vaddr) {
1045 ht_bin[0]=ht_bin[2];
1046 ht_bin[1]=ht_bin[3];
1047 ht_bin[2]=ht_bin[3]=-1;
1051 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1053 struct ll_entry *next;
1055 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1056 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1058 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1059 remove_hash((*head)->vaddr);
1066 head=&((*head)->next);
1071 // Remove all entries from linked list
1072 void ll_clear(struct ll_entry **head)
1074 struct ll_entry *cur;
1075 struct ll_entry *next;
1086 // Dereference the pointers and remove if it matches
1087 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1090 int ptr=get_pointer(head->addr);
1091 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1092 if(((ptr>>shift)==(addr>>shift)) ||
1093 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1095 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1096 u_int host_addr=(u_int)kill_pointer(head->addr);
1098 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1105 // This is called when we write to a compiled block (see do_invstub)
1106 void invalidate_page(u_int page)
1108 struct ll_entry *head;
1109 struct ll_entry *next;
1113 inv_debug("INVALIDATE: %x\n",head->vaddr);
1114 remove_hash(head->vaddr);
1119 head=jump_out[page];
1122 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1123 u_int host_addr=(u_int)kill_pointer(head->addr);
1125 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1132 void invalidate_block(u_int block)
1134 u_int page=get_page(block<<12);
1135 u_int vpage=get_vpage(block<<12);
1136 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1137 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1140 struct ll_entry *head;
1141 head=jump_dirty[vpage];
1142 //printf("page=%d vpage=%d\n",page,vpage);
1145 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1146 get_bounds((int)head->addr,&start,&end);
1147 //printf("start: %x end: %x\n",start,end);
1148 if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
1149 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1150 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1151 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1155 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1156 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1157 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1158 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1165 //printf("first=%d last=%d\n",first,last);
1166 invalidate_page(page);
1167 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1168 assert(last<page+5);
1169 // Invalidate the adjacent pages if a block crosses a 4K boundary
1171 invalidate_page(first);
1174 for(first=page+1;first<last;first++) {
1175 invalidate_page(first);
1181 // Don't trap writes
1182 invalid_code[block]=1;
1184 // If there is a valid TLB entry for this page, remove write protect
1185 if(tlb_LUT_w[block]) {
1186 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1187 // CHECK: Is this right?
1188 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1189 u_int real_block=tlb_LUT_w[block]>>12;
1190 invalid_code[real_block]=1;
1191 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1193 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1197 memset(mini_ht,-1,sizeof(mini_ht));
1200 void invalidate_addr(u_int addr)
1202 invalidate_block(addr>>12);
1204 // This is called when loading a save state.
1205 // Anything could have changed, so invalidate everything.
1206 void invalidate_all_pages()
1209 for(page=0;page<4096;page++)
1210 invalidate_page(page);
1211 for(page=0;page<1048576;page++)
1212 if(!invalid_code[page]) {
1213 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1214 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1217 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1220 memset(mini_ht,-1,sizeof(mini_ht));
1224 for(page=0;page<0x100000;page++) {
1225 if(tlb_LUT_r[page]) {
1226 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1227 if(!tlb_LUT_w[page]||!invalid_code[page])
1228 memory_map[page]|=0x40000000; // Write protect
1230 else memory_map[page]=-1;
1231 if(page==0x80000) page=0xC0000;
1237 // Add an entry to jump_out after making a link
1238 void add_link(u_int vaddr,void *src)
1240 u_int page=get_page(vaddr);
1241 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1242 ll_add(jump_out+page,vaddr,src);
1243 //int ptr=get_pointer(src);
1244 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1247 // If a code block was found to be unmodified (bit was set in
1248 // restore_candidate) and it remains unmodified (bit is clear
1249 // in invalid_code) then move the entries for that 4K page from
1250 // the dirty list to the clean list.
1251 void clean_blocks(u_int page)
1253 struct ll_entry *head;
1254 inv_debug("INV: clean_blocks page=%d\n",page);
1255 head=jump_dirty[page];
1257 if(!invalid_code[head->vaddr>>12]) {
1258 // Don't restore blocks which are about to expire from the cache
1259 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1261 if(verify_dirty((int)head->addr)) {
1262 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1265 get_bounds((int)head->addr,&start,&end);
1266 if(start-(u_int)rdram<RAM_SIZE) {
1267 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1268 inv|=invalid_code[i];
1271 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1272 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1273 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1274 if(addr<start||addr>=end) inv=1;
1276 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1280 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1281 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1284 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1286 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1287 //printf("page=%x, addr=%x\n",page,head->vaddr);
1288 //assert(head->vaddr>>12==(page|0x80000));
1289 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1290 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1292 if(ht_bin[0]==head->vaddr) {
1293 ht_bin[1]=(int)clean_addr; // Replace existing entry
1295 if(ht_bin[2]==head->vaddr) {
1296 ht_bin[3]=(int)clean_addr; // Replace existing entry
1309 void mov_alloc(struct regstat *current,int i)
1311 // Note: Don't need to actually alloc the source registers
1312 if((~current->is32>>rs1[i])&1) {
1313 //alloc_reg64(current,i,rs1[i]);
1314 alloc_reg64(current,i,rt1[i]);
1315 current->is32&=~(1LL<<rt1[i]);
1317 //alloc_reg(current,i,rs1[i]);
1318 alloc_reg(current,i,rt1[i]);
1319 current->is32|=(1LL<<rt1[i]);
1321 clear_const(current,rs1[i]);
1322 clear_const(current,rt1[i]);
1323 dirty_reg(current,rt1[i]);
1326 void shiftimm_alloc(struct regstat *current,int i)
1328 clear_const(current,rs1[i]);
1329 clear_const(current,rt1[i]);
1330 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1333 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1335 alloc_reg(current,i,rt1[i]);
1336 current->is32|=1LL<<rt1[i];
1337 dirty_reg(current,rt1[i]);
1340 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1343 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1344 alloc_reg64(current,i,rt1[i]);
1345 current->is32&=~(1LL<<rt1[i]);
1346 dirty_reg(current,rt1[i]);
1349 if(opcode2[i]==0x3c) // DSLL32
1352 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1353 alloc_reg64(current,i,rt1[i]);
1354 current->is32&=~(1LL<<rt1[i]);
1355 dirty_reg(current,rt1[i]);
1358 if(opcode2[i]==0x3e) // DSRL32
1361 alloc_reg64(current,i,rs1[i]);
1363 alloc_reg64(current,i,rt1[i]);
1364 current->is32&=~(1LL<<rt1[i]);
1366 alloc_reg(current,i,rt1[i]);
1367 current->is32|=1LL<<rt1[i];
1369 dirty_reg(current,rt1[i]);
1372 if(opcode2[i]==0x3f) // DSRA32
1375 alloc_reg64(current,i,rs1[i]);
1376 alloc_reg(current,i,rt1[i]);
1377 current->is32|=1LL<<rt1[i];
1378 dirty_reg(current,rt1[i]);
1383 void shift_alloc(struct regstat *current,int i)
1386 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1388 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1389 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1390 alloc_reg(current,i,rt1[i]);
1391 if(rt1[i]==rs2[i]) {
1392 alloc_reg_temp(current,i,-1);
1393 minimum_free_regs[i]=1;
1395 current->is32|=1LL<<rt1[i];
1396 } else { // DSLLV/DSRLV/DSRAV
1397 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1398 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1399 alloc_reg64(current,i,rt1[i]);
1400 current->is32&=~(1LL<<rt1[i]);
1401 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1403 alloc_reg_temp(current,i,-1);
1404 minimum_free_regs[i]=1;
1407 clear_const(current,rs1[i]);
1408 clear_const(current,rs2[i]);
1409 clear_const(current,rt1[i]);
1410 dirty_reg(current,rt1[i]);
1414 void alu_alloc(struct regstat *current,int i)
1416 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1418 if(rs1[i]&&rs2[i]) {
1419 alloc_reg(current,i,rs1[i]);
1420 alloc_reg(current,i,rs2[i]);
1423 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1424 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1426 alloc_reg(current,i,rt1[i]);
1428 current->is32|=1LL<<rt1[i];
1430 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1432 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1434 alloc_reg64(current,i,rs1[i]);
1435 alloc_reg64(current,i,rs2[i]);
1436 alloc_reg(current,i,rt1[i]);
1438 alloc_reg(current,i,rs1[i]);
1439 alloc_reg(current,i,rs2[i]);
1440 alloc_reg(current,i,rt1[i]);
1443 current->is32|=1LL<<rt1[i];
1445 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1447 if(rs1[i]&&rs2[i]) {
1448 alloc_reg(current,i,rs1[i]);
1449 alloc_reg(current,i,rs2[i]);
1453 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1454 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1456 alloc_reg(current,i,rt1[i]);
1457 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1459 if(!((current->uu>>rt1[i])&1)) {
1460 alloc_reg64(current,i,rt1[i]);
1462 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1463 if(rs1[i]&&rs2[i]) {
1464 alloc_reg64(current,i,rs1[i]);
1465 alloc_reg64(current,i,rs2[i]);
1469 // Is is really worth it to keep 64-bit values in registers?
1471 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1472 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1476 current->is32&=~(1LL<<rt1[i]);
1478 current->is32|=1LL<<rt1[i];
1482 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1484 if(rs1[i]&&rs2[i]) {
1485 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1486 alloc_reg64(current,i,rs1[i]);
1487 alloc_reg64(current,i,rs2[i]);
1488 alloc_reg64(current,i,rt1[i]);
1490 alloc_reg(current,i,rs1[i]);
1491 alloc_reg(current,i,rs2[i]);
1492 alloc_reg(current,i,rt1[i]);
1496 alloc_reg(current,i,rt1[i]);
1497 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1498 // DADD used as move, or zeroing
1499 // If we have a 64-bit source, then make the target 64 bits too
1500 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1501 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1502 alloc_reg64(current,i,rt1[i]);
1503 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1504 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1505 alloc_reg64(current,i,rt1[i]);
1507 if(opcode2[i]>=0x2e&&rs2[i]) {
1508 // DSUB used as negation - 64-bit result
1509 // If we have a 32-bit register, extend it to 64 bits
1510 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1511 alloc_reg64(current,i,rt1[i]);
1515 if(rs1[i]&&rs2[i]) {
1516 current->is32&=~(1LL<<rt1[i]);
1518 current->is32&=~(1LL<<rt1[i]);
1519 if((current->is32>>rs1[i])&1)
1520 current->is32|=1LL<<rt1[i];
1522 current->is32&=~(1LL<<rt1[i]);
1523 if((current->is32>>rs2[i])&1)
1524 current->is32|=1LL<<rt1[i];
1526 current->is32|=1LL<<rt1[i];
1530 clear_const(current,rs1[i]);
1531 clear_const(current,rs2[i]);
1532 clear_const(current,rt1[i]);
1533 dirty_reg(current,rt1[i]);
1536 void imm16_alloc(struct regstat *current,int i)
1538 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1540 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1541 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1542 current->is32&=~(1LL<<rt1[i]);
1543 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1544 // TODO: Could preserve the 32-bit flag if the immediate is zero
1545 alloc_reg64(current,i,rt1[i]);
1546 alloc_reg64(current,i,rs1[i]);
1548 clear_const(current,rs1[i]);
1549 clear_const(current,rt1[i]);
1551 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1552 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1553 current->is32|=1LL<<rt1[i];
1554 clear_const(current,rs1[i]);
1555 clear_const(current,rt1[i]);
1557 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1558 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1559 if(rs1[i]!=rt1[i]) {
1560 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1561 alloc_reg64(current,i,rt1[i]);
1562 current->is32&=~(1LL<<rt1[i]);
1565 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1566 if(is_const(current,rs1[i])) {
1567 int v=get_const(current,rs1[i]);
1568 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1569 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1570 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1572 else clear_const(current,rt1[i]);
1574 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1575 if(is_const(current,rs1[i])) {
1576 int v=get_const(current,rs1[i]);
1577 set_const(current,rt1[i],v+imm[i]);
1579 else clear_const(current,rt1[i]);
1580 current->is32|=1LL<<rt1[i];
1583 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1584 current->is32|=1LL<<rt1[i];
1586 dirty_reg(current,rt1[i]);
1589 void load_alloc(struct regstat *current,int i)
1591 clear_const(current,rt1[i]);
1592 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1593 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1594 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1596 alloc_reg(current,i,rt1[i]);
1597 if(get_reg(current->regmap,rt1[i])<0) {
1598 // dummy load, but we still need a register to calculate the address
1599 alloc_reg_temp(current,i,-1);
1600 minimum_free_regs[i]=1;
1602 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1604 current->is32&=~(1LL<<rt1[i]);
1605 alloc_reg64(current,i,rt1[i]);
1607 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1609 current->is32&=~(1LL<<rt1[i]);
1610 alloc_reg64(current,i,rt1[i]);
1611 alloc_all(current,i);
1612 alloc_reg64(current,i,FTEMP);
1613 minimum_free_regs[i]=HOST_REGS;
1615 else current->is32|=1LL<<rt1[i];
1616 dirty_reg(current,rt1[i]);
1617 // If using TLB, need a register for pointer to the mapping table
1618 if(using_tlb) alloc_reg(current,i,TLREG);
1619 // LWL/LWR need a temporary register for the old value
1620 if(opcode[i]==0x22||opcode[i]==0x26)
1622 alloc_reg(current,i,FTEMP);
1623 alloc_reg_temp(current,i,-1);
1624 minimum_free_regs[i]=1;
1629 // Load to r0 (dummy load)
1630 // but we still need a register to calculate the address
1631 if(opcode[i]==0x22||opcode[i]==0x26)
1633 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1635 alloc_reg_temp(current,i,-1);
1636 minimum_free_regs[i]=1;
1637 if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1639 alloc_all(current,i);
1640 alloc_reg64(current,i,FTEMP);
1641 minimum_free_regs[i]=HOST_REGS;
1646 void store_alloc(struct regstat *current,int i)
1648 clear_const(current,rs2[i]);
1649 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1650 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1651 alloc_reg(current,i,rs2[i]);
1652 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1653 alloc_reg64(current,i,rs2[i]);
1654 if(rs2[i]) alloc_reg(current,i,FTEMP);
1656 // If using TLB, need a register for pointer to the mapping table
1657 if(using_tlb) alloc_reg(current,i,TLREG);
1658 #if defined(HOST_IMM8)
1659 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1660 else alloc_reg(current,i,INVCP);
1662 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1663 alloc_reg(current,i,FTEMP);
1665 // We need a temporary register for address generation
1666 alloc_reg_temp(current,i,-1);
1667 minimum_free_regs[i]=1;
1670 void c1ls_alloc(struct regstat *current,int i)
1672 //clear_const(current,rs1[i]); // FIXME
1673 clear_const(current,rt1[i]);
1674 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1675 alloc_reg(current,i,CSREG); // Status
1676 alloc_reg(current,i,FTEMP);
1677 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1678 alloc_reg64(current,i,FTEMP);
1680 // If using TLB, need a register for pointer to the mapping table
1681 if(using_tlb) alloc_reg(current,i,TLREG);
1682 #if defined(HOST_IMM8)
1683 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1684 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1685 alloc_reg(current,i,INVCP);
1687 // We need a temporary register for address generation
1688 alloc_reg_temp(current,i,-1);
1691 void c2ls_alloc(struct regstat *current,int i)
1693 clear_const(current,rt1[i]);
1694 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1695 alloc_reg(current,i,FTEMP);
1696 // If using TLB, need a register for pointer to the mapping table
1697 if(using_tlb) alloc_reg(current,i,TLREG);
1698 #if defined(HOST_IMM8)
1699 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1700 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1701 alloc_reg(current,i,INVCP);
1703 // We need a temporary register for address generation
1704 alloc_reg_temp(current,i,-1);
1705 minimum_free_regs[i]=1;
1708 #ifndef multdiv_alloc
1709 void multdiv_alloc(struct regstat *current,int i)
1716 // case 0x1D: DMULTU
1719 clear_const(current,rs1[i]);
1720 clear_const(current,rs2[i]);
1723 if((opcode2[i]&4)==0) // 32-bit
1725 current->u&=~(1LL<<HIREG);
1726 current->u&=~(1LL<<LOREG);
1727 alloc_reg(current,i,HIREG);
1728 alloc_reg(current,i,LOREG);
1729 alloc_reg(current,i,rs1[i]);
1730 alloc_reg(current,i,rs2[i]);
1731 current->is32|=1LL<<HIREG;
1732 current->is32|=1LL<<LOREG;
1733 dirty_reg(current,HIREG);
1734 dirty_reg(current,LOREG);
1738 current->u&=~(1LL<<HIREG);
1739 current->u&=~(1LL<<LOREG);
1740 current->uu&=~(1LL<<HIREG);
1741 current->uu&=~(1LL<<LOREG);
1742 alloc_reg64(current,i,HIREG);
1743 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1744 alloc_reg64(current,i,rs1[i]);
1745 alloc_reg64(current,i,rs2[i]);
1746 alloc_all(current,i);
1747 current->is32&=~(1LL<<HIREG);
1748 current->is32&=~(1LL<<LOREG);
1749 dirty_reg(current,HIREG);
1750 dirty_reg(current,LOREG);
1751 minimum_free_regs[i]=HOST_REGS;
1756 // Multiply by zero is zero.
1757 // MIPS does not have a divide by zero exception.
1758 // The result is undefined, we return zero.
1759 alloc_reg(current,i,HIREG);
1760 alloc_reg(current,i,LOREG);
1761 current->is32|=1LL<<HIREG;
1762 current->is32|=1LL<<LOREG;
1763 dirty_reg(current,HIREG);
1764 dirty_reg(current,LOREG);
1769 void cop0_alloc(struct regstat *current,int i)
1771 if(opcode2[i]==0) // MFC0
1774 clear_const(current,rt1[i]);
1775 alloc_all(current,i);
1776 alloc_reg(current,i,rt1[i]);
1777 current->is32|=1LL<<rt1[i];
1778 dirty_reg(current,rt1[i]);
1781 else if(opcode2[i]==4) // MTC0
1784 clear_const(current,rs1[i]);
1785 alloc_reg(current,i,rs1[i]);
1786 alloc_all(current,i);
1789 alloc_all(current,i); // FIXME: Keep r0
1791 alloc_reg(current,i,0);
1796 // TLBR/TLBWI/TLBWR/TLBP/ERET
1797 assert(opcode2[i]==0x10);
1798 alloc_all(current,i);
1800 minimum_free_regs[i]=HOST_REGS;
1803 void cop1_alloc(struct regstat *current,int i)
1805 alloc_reg(current,i,CSREG); // Load status
1806 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1809 clear_const(current,rt1[i]);
1811 alloc_reg64(current,i,rt1[i]); // DMFC1
1812 current->is32&=~(1LL<<rt1[i]);
1814 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1815 current->is32|=1LL<<rt1[i];
1817 dirty_reg(current,rt1[i]);
1819 alloc_reg_temp(current,i,-1);
1821 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1824 clear_const(current,rs1[i]);
1826 alloc_reg64(current,i,rs1[i]); // DMTC1
1828 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1829 alloc_reg_temp(current,i,-1);
1833 alloc_reg(current,i,0);
1834 alloc_reg_temp(current,i,-1);
1837 minimum_free_regs[i]=1;
1839 void fconv_alloc(struct regstat *current,int i)
1841 alloc_reg(current,i,CSREG); // Load status
1842 alloc_reg_temp(current,i,-1);
1843 minimum_free_regs[i]=1;
1845 void float_alloc(struct regstat *current,int i)
1847 alloc_reg(current,i,CSREG); // Load status
1848 alloc_reg_temp(current,i,-1);
1849 minimum_free_regs[i]=1;
1851 void c2op_alloc(struct regstat *current,int i)
1853 alloc_reg_temp(current,i,-1);
1855 void fcomp_alloc(struct regstat *current,int i)
1857 alloc_reg(current,i,CSREG); // Load status
1858 alloc_reg(current,i,FSREG); // Load flags
1859 dirty_reg(current,FSREG); // Flag will be modified
1860 alloc_reg_temp(current,i,-1);
1861 minimum_free_regs[i]=1;
1864 void syscall_alloc(struct regstat *current,int i)
1866 alloc_cc(current,i);
1867 dirty_reg(current,CCREG);
1868 alloc_all(current,i);
1869 minimum_free_regs[i]=HOST_REGS;
1873 void delayslot_alloc(struct regstat *current,int i)
1884 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1885 printf("Disabled speculative precompilation\n");
1889 imm16_alloc(current,i);
1893 load_alloc(current,i);
1897 store_alloc(current,i);
1900 alu_alloc(current,i);
1903 shift_alloc(current,i);
1906 multdiv_alloc(current,i);
1909 shiftimm_alloc(current,i);
1912 mov_alloc(current,i);
1915 cop0_alloc(current,i);
1919 cop1_alloc(current,i);
1922 c1ls_alloc(current,i);
1925 c2ls_alloc(current,i);
1928 fconv_alloc(current,i);
1931 float_alloc(current,i);
1934 fcomp_alloc(current,i);
1937 c2op_alloc(current,i);
1942 // Special case where a branch and delay slot span two pages in virtual memory
1943 static void pagespan_alloc(struct regstat *current,int i)
1946 current->wasconst=0;
1948 minimum_free_regs[i]=HOST_REGS;
1949 alloc_all(current,i);
1950 alloc_cc(current,i);
1951 dirty_reg(current,CCREG);
1952 if(opcode[i]==3) // JAL
1954 alloc_reg(current,i,31);
1955 dirty_reg(current,31);
1957 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1959 alloc_reg(current,i,rs1[i]);
1961 alloc_reg(current,i,rt1[i]);
1962 dirty_reg(current,rt1[i]);
1965 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1967 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1968 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1969 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1971 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1972 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1976 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1978 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1979 if(!((current->is32>>rs1[i])&1))
1981 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1985 if(opcode[i]==0x11) // BC1
1987 alloc_reg(current,i,FSREG);
1988 alloc_reg(current,i,CSREG);
1993 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
1995 stubs[stubcount][0]=type;
1996 stubs[stubcount][1]=addr;
1997 stubs[stubcount][2]=retaddr;
1998 stubs[stubcount][3]=a;
1999 stubs[stubcount][4]=b;
2000 stubs[stubcount][5]=c;
2001 stubs[stubcount][6]=d;
2002 stubs[stubcount][7]=e;
2006 // Write out a single register
2007 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2010 for(hr=0;hr<HOST_REGS;hr++) {
2011 if(hr!=EXCLUDE_REG) {
2012 if((regmap[hr]&63)==r) {
2015 emit_storereg(r,hr);
2017 if((is32>>regmap[hr])&1) {
2018 emit_sarimm(hr,31,hr);
2019 emit_storereg(r|64,hr);
2023 emit_storereg(r|64,hr);
2033 //if(!tracedebug) return 0;
2036 for(i=0;i<2097152;i++) {
2037 unsigned int temp=sum;
2040 sum^=((u_int *)rdram)[i];
2049 sum^=((u_int *)reg)[i];
2057 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2059 #ifndef DISABLE_COP1
2062 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2072 void memdebug(int i)
2074 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2075 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2078 //if(Count>=-2084597794) {
2079 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2081 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2082 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2083 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2086 printf("TRACE: %x\n",(&i)[-1]);
2090 printf("TRACE: %x \n",(&j)[10]);
2091 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2095 //printf("TRACE: %x\n",(&i)[-1]);
2098 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2100 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2103 void alu_assemble(int i,struct regstat *i_regs)
2105 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2107 signed char s1,s2,t;
2108 t=get_reg(i_regs->regmap,rt1[i]);
2110 s1=get_reg(i_regs->regmap,rs1[i]);
2111 s2=get_reg(i_regs->regmap,rs2[i]);
2112 if(rs1[i]&&rs2[i]) {
2115 if(opcode2[i]&2) emit_sub(s1,s2,t);
2116 else emit_add(s1,s2,t);
2119 if(s1>=0) emit_mov(s1,t);
2120 else emit_loadreg(rs1[i],t);
2124 if(opcode2[i]&2) emit_neg(s2,t);
2125 else emit_mov(s2,t);
2128 emit_loadreg(rs2[i],t);
2129 if(opcode2[i]&2) emit_neg(t,t);
2132 else emit_zeroreg(t);
2136 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2138 signed char s1l,s2l,s1h,s2h,tl,th;
2139 tl=get_reg(i_regs->regmap,rt1[i]);
2140 th=get_reg(i_regs->regmap,rt1[i]|64);
2142 s1l=get_reg(i_regs->regmap,rs1[i]);
2143 s2l=get_reg(i_regs->regmap,rs2[i]);
2144 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2145 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2146 if(rs1[i]&&rs2[i]) {
2149 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2150 else emit_adds(s1l,s2l,tl);
2152 #ifdef INVERTED_CARRY
2153 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2155 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2157 else emit_add(s1h,s2h,th);
2161 if(s1l>=0) emit_mov(s1l,tl);
2162 else emit_loadreg(rs1[i],tl);
2164 if(s1h>=0) emit_mov(s1h,th);
2165 else emit_loadreg(rs1[i]|64,th);
2170 if(opcode2[i]&2) emit_negs(s2l,tl);
2171 else emit_mov(s2l,tl);
2174 emit_loadreg(rs2[i],tl);
2175 if(opcode2[i]&2) emit_negs(tl,tl);
2178 #ifdef INVERTED_CARRY
2179 if(s2h>=0) emit_mov(s2h,th);
2180 else emit_loadreg(rs2[i]|64,th);
2182 emit_adcimm(-1,th); // x86 has inverted carry flag
2187 if(s2h>=0) emit_rscimm(s2h,0,th);
2189 emit_loadreg(rs2[i]|64,th);
2190 emit_rscimm(th,0,th);
2193 if(s2h>=0) emit_mov(s2h,th);
2194 else emit_loadreg(rs2[i]|64,th);
2201 if(th>=0) emit_zeroreg(th);
2206 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2208 signed char s1l,s1h,s2l,s2h,t;
2209 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2211 t=get_reg(i_regs->regmap,rt1[i]);
2214 s1l=get_reg(i_regs->regmap,rs1[i]);
2215 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2216 s2l=get_reg(i_regs->regmap,rs2[i]);
2217 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2218 if(rs2[i]==0) // rx<r0
2221 if(opcode2[i]==0x2a) // SLT
2222 emit_shrimm(s1h,31,t);
2223 else // SLTU (unsigned can not be less than zero)
2226 else if(rs1[i]==0) // r0<rx
2229 if(opcode2[i]==0x2a) // SLT
2230 emit_set_gz64_32(s2h,s2l,t);
2231 else // SLTU (set if not zero)
2232 emit_set_nz64_32(s2h,s2l,t);
2235 assert(s1l>=0);assert(s1h>=0);
2236 assert(s2l>=0);assert(s2h>=0);
2237 if(opcode2[i]==0x2a) // SLT
2238 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2240 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2244 t=get_reg(i_regs->regmap,rt1[i]);
2247 s1l=get_reg(i_regs->regmap,rs1[i]);
2248 s2l=get_reg(i_regs->regmap,rs2[i]);
2249 if(rs2[i]==0) // rx<r0
2252 if(opcode2[i]==0x2a) // SLT
2253 emit_shrimm(s1l,31,t);
2254 else // SLTU (unsigned can not be less than zero)
2257 else if(rs1[i]==0) // r0<rx
2260 if(opcode2[i]==0x2a) // SLT
2261 emit_set_gz32(s2l,t);
2262 else // SLTU (set if not zero)
2263 emit_set_nz32(s2l,t);
2266 assert(s1l>=0);assert(s2l>=0);
2267 if(opcode2[i]==0x2a) // SLT
2268 emit_set_if_less32(s1l,s2l,t);
2270 emit_set_if_carry32(s1l,s2l,t);
2276 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2278 signed char s1l,s1h,s2l,s2h,th,tl;
2279 tl=get_reg(i_regs->regmap,rt1[i]);
2280 th=get_reg(i_regs->regmap,rt1[i]|64);
2281 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2285 s1l=get_reg(i_regs->regmap,rs1[i]);
2286 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2287 s2l=get_reg(i_regs->regmap,rs2[i]);
2288 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2289 if(rs1[i]&&rs2[i]) {
2290 assert(s1l>=0);assert(s1h>=0);
2291 assert(s2l>=0);assert(s2h>=0);
2292 if(opcode2[i]==0x24) { // AND
2293 emit_and(s1l,s2l,tl);
2294 emit_and(s1h,s2h,th);
2296 if(opcode2[i]==0x25) { // OR
2297 emit_or(s1l,s2l,tl);
2298 emit_or(s1h,s2h,th);
2300 if(opcode2[i]==0x26) { // XOR
2301 emit_xor(s1l,s2l,tl);
2302 emit_xor(s1h,s2h,th);
2304 if(opcode2[i]==0x27) { // NOR
2305 emit_or(s1l,s2l,tl);
2306 emit_or(s1h,s2h,th);
2313 if(opcode2[i]==0x24) { // AND
2317 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2319 if(s1l>=0) emit_mov(s1l,tl);
2320 else emit_loadreg(rs1[i],tl);
2321 if(s1h>=0) emit_mov(s1h,th);
2322 else emit_loadreg(rs1[i]|64,th);
2326 if(s2l>=0) emit_mov(s2l,tl);
2327 else emit_loadreg(rs2[i],tl);
2328 if(s2h>=0) emit_mov(s2h,th);
2329 else emit_loadreg(rs2[i]|64,th);
2336 if(opcode2[i]==0x27) { // NOR
2338 if(s1l>=0) emit_not(s1l,tl);
2340 emit_loadreg(rs1[i],tl);
2343 if(s1h>=0) emit_not(s1h,th);
2345 emit_loadreg(rs1[i]|64,th);
2351 if(s2l>=0) emit_not(s2l,tl);
2353 emit_loadreg(rs2[i],tl);
2356 if(s2h>=0) emit_not(s2h,th);
2358 emit_loadreg(rs2[i]|64,th);
2374 s1l=get_reg(i_regs->regmap,rs1[i]);
2375 s2l=get_reg(i_regs->regmap,rs2[i]);
2376 if(rs1[i]&&rs2[i]) {
2379 if(opcode2[i]==0x24) { // AND
2380 emit_and(s1l,s2l,tl);
2382 if(opcode2[i]==0x25) { // OR
2383 emit_or(s1l,s2l,tl);
2385 if(opcode2[i]==0x26) { // XOR
2386 emit_xor(s1l,s2l,tl);
2388 if(opcode2[i]==0x27) { // NOR
2389 emit_or(s1l,s2l,tl);
2395 if(opcode2[i]==0x24) { // AND
2398 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2400 if(s1l>=0) emit_mov(s1l,tl);
2401 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2405 if(s2l>=0) emit_mov(s2l,tl);
2406 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2408 else emit_zeroreg(tl);
2410 if(opcode2[i]==0x27) { // NOR
2412 if(s1l>=0) emit_not(s1l,tl);
2414 emit_loadreg(rs1[i],tl);
2420 if(s2l>=0) emit_not(s2l,tl);
2422 emit_loadreg(rs2[i],tl);
2426 else emit_movimm(-1,tl);
2435 void imm16_assemble(int i,struct regstat *i_regs)
2437 if (opcode[i]==0x0f) { // LUI
2440 t=get_reg(i_regs->regmap,rt1[i]);
2443 if(!((i_regs->isconst>>t)&1))
2444 emit_movimm(imm[i]<<16,t);
2448 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2451 t=get_reg(i_regs->regmap,rt1[i]);
2452 s=get_reg(i_regs->regmap,rs1[i]);
2457 if(!((i_regs->isconst>>t)&1)) {
2459 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2460 emit_addimm(t,imm[i],t);
2462 if(!((i_regs->wasconst>>s)&1))
2463 emit_addimm(s,imm[i],t);
2465 emit_movimm(constmap[i][s]+imm[i],t);
2471 if(!((i_regs->isconst>>t)&1))
2472 emit_movimm(imm[i],t);
2477 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2479 signed char sh,sl,th,tl;
2480 th=get_reg(i_regs->regmap,rt1[i]|64);
2481 tl=get_reg(i_regs->regmap,rt1[i]);
2482 sh=get_reg(i_regs->regmap,rs1[i]|64);
2483 sl=get_reg(i_regs->regmap,rs1[i]);
2489 emit_addimm64_32(sh,sl,imm[i],th,tl);
2492 emit_addimm(sl,imm[i],tl);
2495 emit_movimm(imm[i],tl);
2496 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2501 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2503 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2504 signed char sh,sl,t;
2505 t=get_reg(i_regs->regmap,rt1[i]);
2506 sh=get_reg(i_regs->regmap,rs1[i]|64);
2507 sl=get_reg(i_regs->regmap,rs1[i]);
2511 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2512 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2513 if(opcode[i]==0x0a) { // SLTI
2515 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2516 emit_slti32(t,imm[i],t);
2518 emit_slti32(sl,imm[i],t);
2523 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2524 emit_sltiu32(t,imm[i],t);
2526 emit_sltiu32(sl,imm[i],t);
2531 if(opcode[i]==0x0a) // SLTI
2532 emit_slti64_32(sh,sl,imm[i],t);
2534 emit_sltiu64_32(sh,sl,imm[i],t);
2537 // SLTI(U) with r0 is just stupid,
2538 // nonetheless examples can be found
2539 if(opcode[i]==0x0a) // SLTI
2540 if(0<imm[i]) emit_movimm(1,t);
2541 else emit_zeroreg(t);
2544 if(imm[i]) emit_movimm(1,t);
2545 else emit_zeroreg(t);
2551 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2553 signed char sh,sl,th,tl;
2554 th=get_reg(i_regs->regmap,rt1[i]|64);
2555 tl=get_reg(i_regs->regmap,rt1[i]);
2556 sh=get_reg(i_regs->regmap,rs1[i]|64);
2557 sl=get_reg(i_regs->regmap,rs1[i]);
2558 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2559 if(opcode[i]==0x0c) //ANDI
2563 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2564 emit_andimm(tl,imm[i],tl);
2566 if(!((i_regs->wasconst>>sl)&1))
2567 emit_andimm(sl,imm[i],tl);
2569 emit_movimm(constmap[i][sl]&imm[i],tl);
2574 if(th>=0) emit_zeroreg(th);
2580 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2584 emit_loadreg(rs1[i]|64,th);
2589 if(opcode[i]==0x0d) //ORI
2591 emit_orimm(tl,imm[i],tl);
2593 if(!((i_regs->wasconst>>sl)&1))
2594 emit_orimm(sl,imm[i],tl);
2596 emit_movimm(constmap[i][sl]|imm[i],tl);
2598 if(opcode[i]==0x0e) //XORI
2600 emit_xorimm(tl,imm[i],tl);
2602 if(!((i_regs->wasconst>>sl)&1))
2603 emit_xorimm(sl,imm[i],tl);
2605 emit_movimm(constmap[i][sl]^imm[i],tl);
2609 emit_movimm(imm[i],tl);
2610 if(th>=0) emit_zeroreg(th);
2618 void shiftimm_assemble(int i,struct regstat *i_regs)
2620 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2624 t=get_reg(i_regs->regmap,rt1[i]);
2625 s=get_reg(i_regs->regmap,rs1[i]);
2634 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2636 if(opcode2[i]==0) // SLL
2638 emit_shlimm(s<0?t:s,imm[i],t);
2640 if(opcode2[i]==2) // SRL
2642 emit_shrimm(s<0?t:s,imm[i],t);
2644 if(opcode2[i]==3) // SRA
2646 emit_sarimm(s<0?t:s,imm[i],t);
2650 if(s>=0 && s!=t) emit_mov(s,t);
2654 //emit_storereg(rt1[i],t); //DEBUG
2657 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2660 signed char sh,sl,th,tl;
2661 th=get_reg(i_regs->regmap,rt1[i]|64);
2662 tl=get_reg(i_regs->regmap,rt1[i]);
2663 sh=get_reg(i_regs->regmap,rs1[i]|64);
2664 sl=get_reg(i_regs->regmap,rs1[i]);
2669 if(th>=0) emit_zeroreg(th);
2676 if(opcode2[i]==0x38) // DSLL
2678 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2679 emit_shlimm(sl,imm[i],tl);
2681 if(opcode2[i]==0x3a) // DSRL
2683 emit_shrdimm(sl,sh,imm[i],tl);
2684 if(th>=0) emit_shrimm(sh,imm[i],th);
2686 if(opcode2[i]==0x3b) // DSRA
2688 emit_shrdimm(sl,sh,imm[i],tl);
2689 if(th>=0) emit_sarimm(sh,imm[i],th);
2693 if(sl!=tl) emit_mov(sl,tl);
2694 if(th>=0&&sh!=th) emit_mov(sh,th);
2700 if(opcode2[i]==0x3c) // DSLL32
2703 signed char sl,tl,th;
2704 tl=get_reg(i_regs->regmap,rt1[i]);
2705 th=get_reg(i_regs->regmap,rt1[i]|64);
2706 sl=get_reg(i_regs->regmap,rs1[i]);
2715 emit_shlimm(th,imm[i]&31,th);
2720 if(opcode2[i]==0x3e) // DSRL32
2723 signed char sh,tl,th;
2724 tl=get_reg(i_regs->regmap,rt1[i]);
2725 th=get_reg(i_regs->regmap,rt1[i]|64);
2726 sh=get_reg(i_regs->regmap,rs1[i]|64);
2730 if(th>=0) emit_zeroreg(th);
2733 emit_shrimm(tl,imm[i]&31,tl);
2738 if(opcode2[i]==0x3f) // DSRA32
2742 tl=get_reg(i_regs->regmap,rt1[i]);
2743 sh=get_reg(i_regs->regmap,rs1[i]|64);
2749 emit_sarimm(tl,imm[i]&31,tl);
2756 #ifndef shift_assemble
2757 void shift_assemble(int i,struct regstat *i_regs)
2759 printf("Need shift_assemble for this architecture.\n");
2764 void load_assemble(int i,struct regstat *i_regs)
2766 int s,th,tl,addr,map=-1;
2769 int memtarget=0,c=0;
2771 th=get_reg(i_regs->regmap,rt1[i]|64);
2772 tl=get_reg(i_regs->regmap,rt1[i]);
2773 s=get_reg(i_regs->regmap,rs1[i]);
2775 for(hr=0;hr<HOST_REGS;hr++) {
2776 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2778 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2780 c=(i_regs->wasconst>>s)&1;
2781 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2782 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2784 //printf("load_assemble: c=%d\n",c);
2785 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2786 // FIXME: Even if the load is a NOP, we should check for pagefaults...
2788 if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2790 // could be FIFO, must perform the read
2792 assem_debug("(forced read)\n");
2793 tl=get_reg(i_regs->regmap,-1);
2797 if(offset||s<0||c) addr=tl;
2799 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2801 //printf("load_assemble: c=%d\n",c);
2802 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2803 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2805 if(th>=0) reglist&=~(1<<th);
2809 map=get_reg(i_regs->regmap,ROREG);
2810 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2812 //#define R29_HACK 1
2814 // Strmnnrmn's speed hack
2815 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2818 emit_cmpimm(addr,RAM_SIZE);
2820 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2821 // Hint to branch predictor that the branch is unlikely to be taken
2823 emit_jno_unlikely(0);
2831 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2832 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2833 map=get_reg(i_regs->regmap,TLREG);
2835 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2836 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2838 int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2839 if (opcode[i]==0x20) { // LB
2842 #ifdef HOST_IMM_ADDR32
2844 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2848 //emit_xorimm(addr,3,tl);
2849 //gen_tlb_addr_r(tl,map);
2850 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2852 #ifdef BIG_ENDIAN_MIPS
2853 if(!c) emit_xorimm(addr,3,tl);
2854 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2858 emit_movsbl_indexed_tlb(x,a,map,tl);
2862 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2865 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2867 if (opcode[i]==0x21) { // LH
2870 #ifdef HOST_IMM_ADDR32
2872 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2877 #ifdef BIG_ENDIAN_MIPS
2878 if(!c) emit_xorimm(addr,2,tl);
2879 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2884 //emit_movswl_indexed_tlb(x,tl,map,tl);
2887 gen_tlb_addr_r(a,map);
2888 emit_movswl_indexed(x,a,tl);
2891 emit_movswl_indexed(x,a,tl);
2893 emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2899 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2902 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2904 if (opcode[i]==0x23) { // LW
2907 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2908 #ifdef HOST_IMM_ADDR32
2910 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2913 emit_readword_indexed_tlb(0,addr,map,tl);
2916 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2919 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2921 if (opcode[i]==0x24) { // LBU
2924 #ifdef HOST_IMM_ADDR32
2926 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2930 //emit_xorimm(addr,3,tl);
2931 //gen_tlb_addr_r(tl,map);
2932 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
2934 #ifdef BIG_ENDIAN_MIPS
2935 if(!c) emit_xorimm(addr,3,tl);
2936 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2940 emit_movzbl_indexed_tlb(x,a,map,tl);
2944 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2947 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2949 if (opcode[i]==0x25) { // LHU
2952 #ifdef HOST_IMM_ADDR32
2954 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2959 #ifdef BIG_ENDIAN_MIPS
2960 if(!c) emit_xorimm(addr,2,tl);
2961 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2966 //emit_movzwl_indexed_tlb(x,tl,map,tl);
2969 gen_tlb_addr_r(a,map);
2970 emit_movzwl_indexed(x,a,tl);
2973 emit_movzwl_indexed(x,a,tl);
2975 emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
2981 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2984 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2986 if (opcode[i]==0x27) { // LWU
2990 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2991 #ifdef HOST_IMM_ADDR32
2993 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2996 emit_readword_indexed_tlb(0,addr,map,tl);
2999 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3002 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3006 if (opcode[i]==0x37) { // LD
3009 //gen_tlb_addr_r(tl,map);
3010 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3011 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3012 #ifdef HOST_IMM_ADDR32
3014 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3017 emit_readdword_indexed_tlb(0,addr,map,th,tl);
3020 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3023 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3026 //emit_storereg(rt1[i],tl); // DEBUG
3027 //if(opcode[i]==0x23)
3028 //if(opcode[i]==0x24)
3029 //if(opcode[i]==0x23||opcode[i]==0x24)
3030 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3034 emit_readword((int)&last_count,ECX);
3036 if(get_reg(i_regs->regmap,CCREG)<0)
3037 emit_loadreg(CCREG,HOST_CCREG);
3038 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3039 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3040 emit_writeword(HOST_CCREG,(int)&Count);
3043 if(get_reg(i_regs->regmap,CCREG)<0)
3044 emit_loadreg(CCREG,0);
3046 emit_mov(HOST_CCREG,0);
3048 emit_addimm(0,2*ccadj[i],0);
3049 emit_writeword(0,(int)&Count);
3051 emit_call((int)memdebug);
3053 restore_regs(0x100f);
3057 #ifndef loadlr_assemble
3058 void loadlr_assemble(int i,struct regstat *i_regs)
3060 printf("Need loadlr_assemble for this architecture.\n");
3065 void store_assemble(int i,struct regstat *i_regs)
3070 int jaddr=0,jaddr2,type;
3071 int memtarget=0,c=0;
3072 int agr=AGEN1+(i&1);
3074 th=get_reg(i_regs->regmap,rs2[i]|64);
3075 tl=get_reg(i_regs->regmap,rs2[i]);
3076 s=get_reg(i_regs->regmap,rs1[i]);
3077 temp=get_reg(i_regs->regmap,agr);
3078 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3081 c=(i_regs->wasconst>>s)&1;
3082 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3083 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3087 for(hr=0;hr<HOST_REGS;hr++) {
3088 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3090 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3091 if(offset||s<0||c) addr=temp;
3096 // Strmnnrmn's speed hack
3098 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3100 emit_cmpimm(addr,RAM_SIZE);
3101 #ifdef DESTRUCTIVE_SHIFT
3102 if(s==addr) emit_mov(s,temp);
3105 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3109 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3110 // Hint to branch predictor that the branch is unlikely to be taken
3112 emit_jno_unlikely(0);
3120 if (opcode[i]==0x28) x=3; // SB
3121 if (opcode[i]==0x29) x=2; // SH
3122 map=get_reg(i_regs->regmap,TLREG);
3124 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3125 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3128 if (opcode[i]==0x28) { // SB
3131 #ifdef BIG_ENDIAN_MIPS
3132 if(!c) emit_xorimm(addr,3,temp);
3133 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3135 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3136 else if (addr!=temp) emit_mov(addr,temp);
3138 //gen_tlb_addr_w(temp,map);
3139 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3140 emit_writebyte_indexed_tlb(tl,x,temp,map,temp);
3144 if (opcode[i]==0x29) { // SH
3147 #ifdef BIG_ENDIAN_MIPS
3148 if(!c) emit_xorimm(addr,2,temp);
3149 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3151 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3152 else if (addr!=temp) emit_mov(addr,temp);
3155 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3158 gen_tlb_addr_w(temp,map);
3159 emit_writehword_indexed(tl,x,temp);
3161 emit_writehword_indexed(tl,(int)rdram-0x80000000+x,temp);
3165 if (opcode[i]==0x2B) { // SW
3167 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3168 emit_writeword_indexed_tlb(tl,0,addr,map,temp);
3171 if (opcode[i]==0x3F) { // SD
3175 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3176 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3177 emit_writedword_indexed_tlb(th,tl,0,addr,map,temp);
3180 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3181 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3182 emit_writedword_indexed_tlb(tl,tl,0,addr,map,temp);
3189 #ifdef DESTRUCTIVE_SHIFT
3190 // The x86 shift operation is 'destructive'; it overwrites the
3191 // source register, so we need to make a copy first and use that.
3194 #if defined(HOST_IMM8)
3195 int ir=get_reg(i_regs->regmap,INVCP);
3197 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3199 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3203 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3207 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3208 } else if(c&&!memtarget) {
3209 inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3211 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3212 //if(opcode[i]==0x2B || opcode[i]==0x28)
3213 //if(opcode[i]==0x2B || opcode[i]==0x29)
3214 //if(opcode[i]==0x2B)
3215 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3219 emit_readword((int)&last_count,ECX);
3221 if(get_reg(i_regs->regmap,CCREG)<0)
3222 emit_loadreg(CCREG,HOST_CCREG);
3223 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3224 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3225 emit_writeword(HOST_CCREG,(int)&Count);
3228 if(get_reg(i_regs->regmap,CCREG)<0)
3229 emit_loadreg(CCREG,0);
3231 emit_mov(HOST_CCREG,0);
3233 emit_addimm(0,2*ccadj[i],0);
3234 emit_writeword(0,(int)&Count);
3236 emit_call((int)memdebug);
3238 restore_regs(0x100f);
3242 void storelr_assemble(int i,struct regstat *i_regs)
3249 int case1,case2,case3;
3250 int done0,done1,done2;
3252 int agr=AGEN1+(i&1);
3254 th=get_reg(i_regs->regmap,rs2[i]|64);
3255 tl=get_reg(i_regs->regmap,rs2[i]);
3256 s=get_reg(i_regs->regmap,rs1[i]);
3257 temp=get_reg(i_regs->regmap,agr);
3258 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3261 c=(i_regs->isconst>>s)&1;
3262 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3263 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3266 for(hr=0;hr<HOST_REGS;hr++) {
3267 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3272 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3273 if(!offset&&s!=temp) emit_mov(s,temp);
3279 if(!memtarget||!rs1[i]) {
3285 int map=get_reg(i_regs->regmap,ROREG);
3286 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3287 gen_tlb_addr_w(temp,map);
3289 if((u_int)rdram!=0x80000000)
3290 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3293 int map=get_reg(i_regs->regmap,TLREG);
3295 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3296 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3297 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3298 if(!jaddr&&!memtarget) {
3302 gen_tlb_addr_w(temp,map);
3305 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3306 temp2=get_reg(i_regs->regmap,FTEMP);
3307 if(!rs2[i]) temp2=th=tl;
3310 #ifndef BIG_ENDIAN_MIPS
3311 emit_xorimm(temp,3,temp);
3313 emit_testimm(temp,2);
3316 emit_testimm(temp,1);
3320 if (opcode[i]==0x2A) { // SWL
3321 emit_writeword_indexed(tl,0,temp);
3323 if (opcode[i]==0x2E) { // SWR
3324 emit_writebyte_indexed(tl,3,temp);
3326 if (opcode[i]==0x2C) { // SDL
3327 emit_writeword_indexed(th,0,temp);
3328 if(rs2[i]) emit_mov(tl,temp2);
3330 if (opcode[i]==0x2D) { // SDR
3331 emit_writebyte_indexed(tl,3,temp);
3332 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3337 set_jump_target(case1,(int)out);
3338 if (opcode[i]==0x2A) { // SWL
3339 // Write 3 msb into three least significant bytes
3340 if(rs2[i]) emit_rorimm(tl,8,tl);
3341 emit_writehword_indexed(tl,-1,temp);
3342 if(rs2[i]) emit_rorimm(tl,16,tl);
3343 emit_writebyte_indexed(tl,1,temp);
3344 if(rs2[i]) emit_rorimm(tl,8,tl);
3346 if (opcode[i]==0x2E) { // SWR
3347 // Write two lsb into two most significant bytes
3348 emit_writehword_indexed(tl,1,temp);
3350 if (opcode[i]==0x2C) { // SDL
3351 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3352 // Write 3 msb into three least significant bytes
3353 if(rs2[i]) emit_rorimm(th,8,th);
3354 emit_writehword_indexed(th,-1,temp);
3355 if(rs2[i]) emit_rorimm(th,16,th);
3356 emit_writebyte_indexed(th,1,temp);
3357 if(rs2[i]) emit_rorimm(th,8,th);
3359 if (opcode[i]==0x2D) { // SDR
3360 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3361 // Write two lsb into two most significant bytes
3362 emit_writehword_indexed(tl,1,temp);
3367 set_jump_target(case2,(int)out);
3368 emit_testimm(temp,1);
3371 if (opcode[i]==0x2A) { // SWL
3372 // Write two msb into two least significant bytes
3373 if(rs2[i]) emit_rorimm(tl,16,tl);
3374 emit_writehword_indexed(tl,-2,temp);
3375 if(rs2[i]) emit_rorimm(tl,16,tl);
3377 if (opcode[i]==0x2E) { // SWR
3378 // Write 3 lsb into three most significant bytes
3379 emit_writebyte_indexed(tl,-1,temp);
3380 if(rs2[i]) emit_rorimm(tl,8,tl);
3381 emit_writehword_indexed(tl,0,temp);
3382 if(rs2[i]) emit_rorimm(tl,24,tl);
3384 if (opcode[i]==0x2C) { // SDL
3385 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3386 // Write two msb into two least significant bytes
3387 if(rs2[i]) emit_rorimm(th,16,th);
3388 emit_writehword_indexed(th,-2,temp);
3389 if(rs2[i]) emit_rorimm(th,16,th);
3391 if (opcode[i]==0x2D) { // SDR
3392 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3393 // Write 3 lsb into three most significant bytes
3394 emit_writebyte_indexed(tl,-1,temp);
3395 if(rs2[i]) emit_rorimm(tl,8,tl);
3396 emit_writehword_indexed(tl,0,temp);
3397 if(rs2[i]) emit_rorimm(tl,24,tl);
3402 set_jump_target(case3,(int)out);
3403 if (opcode[i]==0x2A) { // SWL
3404 // Write msb into least significant byte
3405 if(rs2[i]) emit_rorimm(tl,24,tl);
3406 emit_writebyte_indexed(tl,-3,temp);
3407 if(rs2[i]) emit_rorimm(tl,8,tl);
3409 if (opcode[i]==0x2E) { // SWR
3410 // Write entire word
3411 emit_writeword_indexed(tl,-3,temp);
3413 if (opcode[i]==0x2C) { // SDL
3414 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3415 // Write msb into least significant byte
3416 if(rs2[i]) emit_rorimm(th,24,th);
3417 emit_writebyte_indexed(th,-3,temp);
3418 if(rs2[i]) emit_rorimm(th,8,th);
3420 if (opcode[i]==0x2D) { // SDR
3421 if(rs2[i]) emit_mov(th,temp2);
3422 // Write entire word
3423 emit_writeword_indexed(tl,-3,temp);
3425 set_jump_target(done0,(int)out);
3426 set_jump_target(done1,(int)out);
3427 set_jump_target(done2,(int)out);
3428 if (opcode[i]==0x2C) { // SDL
3429 emit_testimm(temp,4);
3432 emit_andimm(temp,~3,temp);
3433 emit_writeword_indexed(temp2,4,temp);
3434 set_jump_target(done0,(int)out);
3436 if (opcode[i]==0x2D) { // SDR
3437 emit_testimm(temp,4);
3440 emit_andimm(temp,~3,temp);
3441 emit_writeword_indexed(temp2,-4,temp);
3442 set_jump_target(done0,(int)out);
3445 add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
3448 int map=get_reg(i_regs->regmap,ROREG);
3449 if(map<0) map=HOST_TEMPREG;
3450 gen_orig_addr_w(temp,map);
3452 emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3454 #if defined(HOST_IMM8)
3455 int ir=get_reg(i_regs->regmap,INVCP);
3457 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3459 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3461 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3462 emit_callne(invalidate_addr_reg[temp]);
3466 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3471 //save_regs(0x100f);
3472 emit_readword((int)&last_count,ECX);
3473 if(get_reg(i_regs->regmap,CCREG)<0)
3474 emit_loadreg(CCREG,HOST_CCREG);
3475 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3476 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3477 emit_writeword(HOST_CCREG,(int)&Count);
3478 emit_call((int)memdebug);
3480 //restore_regs(0x100f);
3484 void c1ls_assemble(int i,struct regstat *i_regs)
3486 #ifndef DISABLE_COP1
3492 int jaddr,jaddr2=0,jaddr3,type;
3493 int agr=AGEN1+(i&1);
3495 th=get_reg(i_regs->regmap,FTEMP|64);
3496 tl=get_reg(i_regs->regmap,FTEMP);
3497 s=get_reg(i_regs->regmap,rs1[i]);
3498 temp=get_reg(i_regs->regmap,agr);
3499 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3504 for(hr=0;hr<HOST_REGS;hr++) {
3505 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3507 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3508 if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3510 // Loads use a temporary register which we need to save
3513 if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3517 //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3518 //else c=(i_regs->wasconst>>s)&1;
3519 if(s>=0) c=(i_regs->wasconst>>s)&1;
3520 // Check cop1 unusable
3522 signed char rs=get_reg(i_regs->regmap,CSREG);
3524 emit_testimm(rs,0x20000000);
3527 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3530 if (opcode[i]==0x39) { // SWC1 (get float address)
3531 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],tl);
3533 if (opcode[i]==0x3D) { // SDC1 (get double address)
3534 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],tl);
3536 // Generate address + offset
3539 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3543 map=get_reg(i_regs->regmap,TLREG);
3545 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3546 map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3548 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3549 map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3552 if (opcode[i]==0x39) { // SWC1 (read float)
3553 emit_readword_indexed(0,tl,tl);
3555 if (opcode[i]==0x3D) { // SDC1 (read double)
3556 emit_readword_indexed(4,tl,th);
3557 emit_readword_indexed(0,tl,tl);
3559 if (opcode[i]==0x31) { // LWC1 (get target address)
3560 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],temp);
3562 if (opcode[i]==0x35) { // LDC1 (get target address)
3563 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],temp);
3570 else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
3572 emit_jmp(0); // inline_readstub/inline_writestub? Very rare case
3574 #ifdef DESTRUCTIVE_SHIFT
3575 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3576 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3580 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3581 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3583 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3584 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3587 if (opcode[i]==0x31) { // LWC1
3588 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3589 //gen_tlb_addr_r(ar,map);
3590 //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3591 #ifdef HOST_IMM_ADDR32
3592 if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3595 emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3598 if (opcode[i]==0x35) { // LDC1
3600 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3601 //gen_tlb_addr_r(ar,map);
3602 //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3603 //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3604 #ifdef HOST_IMM_ADDR32
3605 if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3608 emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3611 if (opcode[i]==0x39) { // SWC1
3612 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3613 emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3616 if (opcode[i]==0x3D) { // SDC1
3618 //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3619 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3620 emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3624 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3625 #ifndef DESTRUCTIVE_SHIFT
3626 temp=offset||c||s<0?ar:s;
3628 #if defined(HOST_IMM8)
3629 int ir=get_reg(i_regs->regmap,INVCP);
3631 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3633 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3637 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3640 if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3641 if (opcode[i]==0x31) { // LWC1 (write float)
3642 emit_writeword_indexed(tl,0,temp);
3644 if (opcode[i]==0x35) { // LDC1 (write double)
3645 emit_writeword_indexed(th,4,temp);
3646 emit_writeword_indexed(tl,0,temp);
3648 //if(opcode[i]==0x39)
3649 /*if(opcode[i]==0x39||opcode[i]==0x31)
3652 emit_readword((int)&last_count,ECX);
3653 if(get_reg(i_regs->regmap,CCREG)<0)
3654 emit_loadreg(CCREG,HOST_CCREG);
3655 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3656 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3657 emit_writeword(HOST_CCREG,(int)&Count);
3658 emit_call((int)memdebug);
3662 cop1_unusable(i, i_regs);
3666 void c2ls_assemble(int i,struct regstat *i_regs)
3671 int memtarget=0,c=0;
3672 int jaddr,jaddr2=0,jaddr3,type;
3673 int agr=AGEN1+(i&1);
3675 u_int copr=(source[i]>>16)&0x1f;
3676 s=get_reg(i_regs->regmap,rs1[i]);
3677 tl=get_reg(i_regs->regmap,FTEMP);
3683 for(hr=0;hr<HOST_REGS;hr++) {
3684 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3686 if(i_regs->regmap[HOST_CCREG]==CCREG)
3687 reglist&=~(1<<HOST_CCREG);
3690 if (opcode[i]==0x3a) { // SWC2
3691 ar=get_reg(i_regs->regmap,agr);
3692 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3697 if(s>=0) c=(i_regs->wasconst>>s)&1;
3698 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3699 if (!offset&&!c&&s>=0) ar=s;
3702 if (opcode[i]==0x3a) { // SWC2
3703 cop2_get_dreg(copr,tl,HOST_TEMPREG);
3711 emit_jmp(0); // inline_readstub/inline_writestub?
3715 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3719 if (opcode[i]==0x32) { // LWC2
3720 #ifdef HOST_IMM_ADDR32
3721 if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3724 emit_readword_indexed(0,ar,tl);
3726 if (opcode[i]==0x3a) { // SWC2
3727 #ifdef DESTRUCTIVE_SHIFT
3728 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3730 emit_writeword_indexed(tl,0,ar);
3734 add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3735 if (opcode[i]==0x3a) { // SWC2
3736 #if defined(HOST_IMM8)
3737 int ir=get_reg(i_regs->regmap,INVCP);
3739 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3741 emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3745 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3747 if (opcode[i]==0x32) { // LWC2
3748 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3752 #ifndef multdiv_assemble
3753 void multdiv_assemble(int i,struct regstat *i_regs)
3755 printf("Need multdiv_assemble for this architecture.\n");
3760 void mov_assemble(int i,struct regstat *i_regs)
3762 //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3763 //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3765 signed char sh,sl,th,tl;
3766 th=get_reg(i_regs->regmap,rt1[i]|64);
3767 tl=get_reg(i_regs->regmap,rt1[i]);
3770 sh=get_reg(i_regs->regmap,rs1[i]|64);
3771 sl=get_reg(i_regs->regmap,rs1[i]);
3772 if(sl>=0) emit_mov(sl,tl);
3773 else emit_loadreg(rs1[i],tl);
3775 if(sh>=0) emit_mov(sh,th);
3776 else emit_loadreg(rs1[i]|64,th);
3782 #ifndef fconv_assemble
3783 void fconv_assemble(int i,struct regstat *i_regs)
3785 printf("Need fconv_assemble for this architecture.\n");
3791 void float_assemble(int i,struct regstat *i_regs)
3793 printf("Need float_assemble for this architecture.\n");
3798 void syscall_assemble(int i,struct regstat *i_regs)
3800 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3801 assert(ccreg==HOST_CCREG);
3802 assert(!is_delayslot);
3803 emit_movimm(start+i*4,EAX); // Get PC
3804 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
3805 emit_jmp((int)jump_syscall_hle); // XXX
3808 void hlecall_assemble(int i,struct regstat *i_regs)
3810 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3811 assert(ccreg==HOST_CCREG);
3812 assert(!is_delayslot);
3813 emit_movimm(start+i*4+4,0); // Get PC
3814 emit_movimm((int)psxHLEt[source[i]&7],1);
3815 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // XXX
3816 emit_jmp((int)jump_hlecall);
3819 void intcall_assemble(int i,struct regstat *i_regs)
3821 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3822 assert(ccreg==HOST_CCREG);
3823 assert(!is_delayslot);
3824 emit_movimm(start+i*4,0); // Get PC
3825 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3826 emit_jmp((int)jump_intcall);
3829 void ds_assemble(int i,struct regstat *i_regs)
3834 alu_assemble(i,i_regs);break;
3836 imm16_assemble(i,i_regs);break;
3838 shift_assemble(i,i_regs);break;
3840 shiftimm_assemble(i,i_regs);break;
3842 load_assemble(i,i_regs);break;
3844 loadlr_assemble(i,i_regs);break;
3846 store_assemble(i,i_regs);break;
3848 storelr_assemble(i,i_regs);break;
3850 cop0_assemble(i,i_regs);break;
3852 cop1_assemble(i,i_regs);break;
3854 c1ls_assemble(i,i_regs);break;
3856 cop2_assemble(i,i_regs);break;
3858 c2ls_assemble(i,i_regs);break;
3860 c2op_assemble(i,i_regs);break;
3862 fconv_assemble(i,i_regs);break;
3864 float_assemble(i,i_regs);break;
3866 fcomp_assemble(i,i_regs);break;
3868 multdiv_assemble(i,i_regs);break;
3870 mov_assemble(i,i_regs);break;
3880 printf("Jump in the delay slot. This is probably a bug.\n");
3885 // Is the branch target a valid internal jump?
3886 int internal_branch(uint64_t i_is32,int addr)
3888 if(addr&1) return 0; // Indirect (register) jump
3889 if(addr>=start && addr<start+slen*4-4)
3891 int t=(addr-start)>>2;
3892 // Delay slots are not valid branch targets
3893 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
3894 // 64 -> 32 bit transition requires a recompile
3895 /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
3897 if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
3898 else printf("optimizable: yes\n");
3900 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
3902 if(requires_32bit[t]&~i_is32) return 0;
3910 #ifndef wb_invalidate
3911 void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
3912 uint64_t u,uint64_t uu)
3915 for(hr=0;hr<HOST_REGS;hr++) {
3916 if(hr!=EXCLUDE_REG) {
3917 if(pre[hr]!=entry[hr]) {
3920 if(get_reg(entry,pre[hr])<0) {
3922 if(!((u>>pre[hr])&1)) {
3923 emit_storereg(pre[hr],hr);
3924 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
3925 emit_sarimm(hr,31,hr);
3926 emit_storereg(pre[hr]|64,hr);
3930 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
3931 emit_storereg(pre[hr],hr);
3940 // Move from one register to another (no writeback)
3941 for(hr=0;hr<HOST_REGS;hr++) {
3942 if(hr!=EXCLUDE_REG) {
3943 if(pre[hr]!=entry[hr]) {
3944 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
3946 if((nr=get_reg(entry,pre[hr]))>=0) {
3956 // Load the specified registers
3957 // This only loads the registers given as arguments because
3958 // we don't want to load things that will be overwritten
3959 void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
3963 for(hr=0;hr<HOST_REGS;hr++) {
3964 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
3965 if(entry[hr]!=regmap[hr]) {
3966 if(regmap[hr]==rs1||regmap[hr]==rs2)
3973 emit_loadreg(regmap[hr],hr);
3980 for(hr=0;hr<HOST_REGS;hr++) {
3981 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
3982 if(entry[hr]!=regmap[hr]) {
3983 if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
3985 assert(regmap[hr]!=64);
3986 if((is32>>(regmap[hr]&63))&1) {
3987 int lr=get_reg(regmap,regmap[hr]-64);
3989 emit_sarimm(lr,31,hr);
3991 emit_loadreg(regmap[hr],hr);
3995 emit_loadreg(regmap[hr],hr);
4003 // Load registers prior to the start of a loop
4004 // so that they are not loaded within the loop
4005 static void loop_preload(signed char pre[],signed char entry[])
4008 for(hr=0;hr<HOST_REGS;hr++) {
4009 if(hr!=EXCLUDE_REG) {
4010 if(pre[hr]!=entry[hr]) {
4012 if(get_reg(pre,entry[hr])<0) {
4013 assem_debug("loop preload:\n");
4014 //printf("loop preload: %d\n",hr);
4018 else if(entry[hr]<TEMPREG)
4020 emit_loadreg(entry[hr],hr);
4022 else if(entry[hr]-64<TEMPREG)
4024 emit_loadreg(entry[hr],hr);
4033 // Generate address for load/store instruction
4034 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
4035 void address_generation(int i,struct regstat *i_regs,signed char entry[])
4037 if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
4039 int agr=AGEN1+(i&1);
4040 int mgr=MGEN1+(i&1);
4041 if(itype[i]==LOAD) {
4042 ra=get_reg(i_regs->regmap,rt1[i]);
4043 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4046 if(itype[i]==LOADLR) {
4047 ra=get_reg(i_regs->regmap,FTEMP);
4049 if(itype[i]==STORE||itype[i]==STORELR) {
4050 ra=get_reg(i_regs->regmap,agr);
4051 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4053 if(itype[i]==C1LS||itype[i]==C2LS) {
4054 if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
4055 ra=get_reg(i_regs->regmap,FTEMP);
4056 else { // SWC1/SDC1/SWC2/SDC2
4057 ra=get_reg(i_regs->regmap,agr);
4058 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4061 int rs=get_reg(i_regs->regmap,rs1[i]);
4062 int rm=get_reg(i_regs->regmap,TLREG);
4065 int c=(i_regs->wasconst>>rs)&1;
4067 // Using r0 as a base address
4069 if(!entry||entry[rm]!=mgr) {
4070 generate_map_const(offset,rm);
4071 } // else did it in the previous cycle
4073 if(!entry||entry[ra]!=agr) {
4074 if (opcode[i]==0x22||opcode[i]==0x26) {
4075 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4076 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4077 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4079 emit_movimm(offset,ra);
4081 } // else did it in the previous cycle
4084 if(!entry||entry[ra]!=rs1[i])
4085 emit_loadreg(rs1[i],ra);
4086 //if(!entry||entry[ra]!=rs1[i])
4087 // printf("poor load scheduling!\n");
4091 if(!entry||entry[rm]!=mgr) {
4092 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
4093 // Stores to memory go thru the mapper to detect self-modifying
4094 // code, loads don't.
4095 if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
4096 (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
4097 generate_map_const(constmap[i][rs]+offset,rm);
4099 if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
4100 generate_map_const(constmap[i][rs]+offset,rm);
4104 if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
4105 if(!entry||entry[ra]!=agr) {
4106 if (opcode[i]==0x22||opcode[i]==0x26) {
4107 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4108 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4109 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4111 #ifdef HOST_IMM_ADDR32
4112 if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4113 (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4115 emit_movimm(constmap[i][rs]+offset,ra);
4117 } // else did it in the previous cycle
4118 } // else load_consts already did it
4120 if(offset&&!c&&rs1[i]) {
4122 emit_addimm(rs,offset,ra);
4124 emit_addimm(ra,offset,ra);
4129 // Preload constants for next instruction
4130 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
4132 #ifndef HOST_IMM_ADDR32
4134 agr=MGEN1+((i+1)&1);
4135 ra=get_reg(i_regs->regmap,agr);
4137 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4138 int offset=imm[i+1];
4139 int c=(regs[i+1].wasconst>>rs)&1;
4141 if(itype[i+1]==STORE||itype[i+1]==STORELR
4142 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
4143 // Stores to memory go thru the mapper to detect self-modifying
4144 // code, loads don't.
4145 if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4146 (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
4147 generate_map_const(constmap[i+1][rs]+offset,ra);
4149 if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4150 generate_map_const(constmap[i+1][rs]+offset,ra);
4153 /*else if(rs1[i]==0) {
4154 generate_map_const(offset,ra);
4159 agr=AGEN1+((i+1)&1);
4160 ra=get_reg(i_regs->regmap,agr);
4162 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4163 int offset=imm[i+1];
4164 int c=(regs[i+1].wasconst>>rs)&1;
4165 if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4166 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4167 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4168 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4169 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4171 #ifdef HOST_IMM_ADDR32
4172 if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4173 (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4175 emit_movimm(constmap[i+1][rs]+offset,ra);
4178 else if(rs1[i+1]==0) {
4179 // Using r0 as a base address
4180 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4181 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4182 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4183 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4185 emit_movimm(offset,ra);
4192 int get_final_value(int hr, int i, int *value)
4194 int reg=regs[i].regmap[hr];
4196 if(regs[i+1].regmap[hr]!=reg) break;
4197 if(!((regs[i+1].isconst>>hr)&1)) break;
4202 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4203 *value=constmap[i][hr];
4207 if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4208 // Load in delay slot, out-of-order execution
4209 if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4211 #ifdef HOST_IMM_ADDR32
4212 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4214 // Precompute load address
4215 *value=constmap[i][hr]+imm[i+2];
4219 if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4221 #ifdef HOST_IMM_ADDR32
4222 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4224 // Precompute load address
4225 *value=constmap[i][hr]+imm[i+1];
4226 //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4231 *value=constmap[i][hr];
4232 //printf("c=%x\n",(int)constmap[i][hr]);
4233 if(i==slen-1) return 1;
4235 return !((unneeded_reg[i+1]>>reg)&1);
4237 return !((unneeded_reg_upper[i+1]>>reg)&1);
4241 // Load registers with known constants
4242 void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4246 for(hr=0;hr<HOST_REGS;hr++) {
4247 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4248 //if(entry[hr]!=regmap[hr]) {
4249 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4250 if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) {
4252 if(get_final_value(hr,i,&value)) {
4257 emit_movimm(value,hr);
4265 for(hr=0;hr<HOST_REGS;hr++) {
4266 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4267 //if(entry[hr]!=regmap[hr]) {
4268 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4269 if(((regs[i].isconst>>hr)&1)&®map[hr]>64) {
4270 if((is32>>(regmap[hr]&63))&1) {
4271 int lr=get_reg(regmap,regmap[hr]-64);
4273 emit_sarimm(lr,31,hr);
4278 if(get_final_value(hr,i,&value)) {
4283 emit_movimm(value,hr);
4292 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4296 for(hr=0;hr<HOST_REGS;hr++) {
4297 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4298 if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) {
4299 int value=constmap[i][hr];
4304 emit_movimm(value,hr);
4310 for(hr=0;hr<HOST_REGS;hr++) {
4311 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4312 if(((regs[i].isconst>>hr)&1)&®map[hr]>64) {
4313 if((is32>>(regmap[hr]&63))&1) {
4314 int lr=get_reg(regmap,regmap[hr]-64);
4316 emit_sarimm(lr,31,hr);
4320 int value=constmap[i][hr];
4325 emit_movimm(value,hr);
4333 // Write out all dirty registers (except cycle count)
4334 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4337 for(hr=0;hr<HOST_REGS;hr++) {
4338 if(hr!=EXCLUDE_REG) {
4339 if(i_regmap[hr]>0) {
4340 if(i_regmap[hr]!=CCREG) {
4341 if((i_dirty>>hr)&1) {
4342 if(i_regmap[hr]<64) {
4343 emit_storereg(i_regmap[hr],hr);
4345 if( ((i_is32>>i_regmap[hr])&1) ) {
4346 #ifdef DESTRUCTIVE_WRITEBACK
4347 emit_sarimm(hr,31,hr);
4348 emit_storereg(i_regmap[hr]|64,hr);
4350 emit_sarimm(hr,31,HOST_TEMPREG);
4351 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4356 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4357 emit_storereg(i_regmap[hr],hr);
4366 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4367 // This writes the registers not written by store_regs_bt
4368 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4371 int t=(addr-start)>>2;
4372 for(hr=0;hr<HOST_REGS;hr++) {
4373 if(hr!=EXCLUDE_REG) {
4374 if(i_regmap[hr]>0) {
4375 if(i_regmap[hr]!=CCREG) {
4376 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4377 if((i_dirty>>hr)&1) {
4378 if(i_regmap[hr]<64) {
4379 emit_storereg(i_regmap[hr],hr);
4381 if( ((i_is32>>i_regmap[hr])&1) ) {
4382 #ifdef DESTRUCTIVE_WRITEBACK
4383 emit_sarimm(hr,31,hr);
4384 emit_storereg(i_regmap[hr]|64,hr);
4386 emit_sarimm(hr,31,HOST_TEMPREG);
4387 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4392 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4393 emit_storereg(i_regmap[hr],hr);
4404 // Load all registers (except cycle count)
4405 void load_all_regs(signed char i_regmap[])
4408 for(hr=0;hr<HOST_REGS;hr++) {
4409 if(hr!=EXCLUDE_REG) {
4410 if(i_regmap[hr]==0) {
4414 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG)
4416 emit_loadreg(i_regmap[hr],hr);
4422 // Load all current registers also needed by next instruction
4423 void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4426 for(hr=0;hr<HOST_REGS;hr++) {
4427 if(hr!=EXCLUDE_REG) {
4428 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4429 if(i_regmap[hr]==0) {
4433 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG)
4435 emit_loadreg(i_regmap[hr],hr);
4442 // Load all regs, storing cycle count if necessary
4443 void load_regs_entry(int t)
4446 if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER,HOST_CCREG);
4447 else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t]*CLOCK_DIVIDER,HOST_CCREG);
4448 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4449 emit_storereg(CCREG,HOST_CCREG);
4452 for(hr=0;hr<HOST_REGS;hr++) {
4453 if(regs[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<64) {
4454 if(regs[t].regmap_entry[hr]==0) {
4457 else if(regs[t].regmap_entry[hr]!=CCREG)
4459 emit_loadreg(regs[t].regmap_entry[hr],hr);
4464 for(hr=0;hr<HOST_REGS;hr++) {
4465 if(regs[t].regmap_entry[hr]>=64) {
4466 assert(regs[t].regmap_entry[hr]!=64);
4467 if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4468 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4470 emit_loadreg(regs[t].regmap_entry[hr],hr);
4474 emit_sarimm(lr,31,hr);
4479 emit_loadreg(regs[t].regmap_entry[hr],hr);
4485 // Store dirty registers prior to branch
4486 void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4488 if(internal_branch(i_is32,addr))
4490 int t=(addr-start)>>2;
4492 for(hr=0;hr<HOST_REGS;hr++) {
4493 if(hr!=EXCLUDE_REG) {
4494 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4495 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4496 if((i_dirty>>hr)&1) {
4497 if(i_regmap[hr]<64) {
4498 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4499 emit_storereg(i_regmap[hr],hr);
4500 if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4501 #ifdef DESTRUCTIVE_WRITEBACK
4502 emit_sarimm(hr,31,hr);
4503 emit_storereg(i_regmap[hr]|64,hr);
4505 emit_sarimm(hr,31,HOST_TEMPREG);
4506 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4511 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4512 emit_storereg(i_regmap[hr],hr);
4523 // Branch out of this block, write out all dirty regs
4524 wb_dirtys(i_regmap,i_is32,i_dirty);
4528 // Load all needed registers for branch target
4529 void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4531 //if(addr>=start && addr<(start+slen*4))
4532 if(internal_branch(i_is32,addr))
4534 int t=(addr-start)>>2;
4536 // Store the cycle count before loading something else
4537 if(i_regmap[HOST_CCREG]!=CCREG) {
4538 assert(i_regmap[HOST_CCREG]==-1);
4540 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4541 emit_storereg(CCREG,HOST_CCREG);
4544 for(hr=0;hr<HOST_REGS;hr++) {
4545 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<64) {
4546 #ifdef DESTRUCTIVE_WRITEBACK
4547 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4549 if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4551 if(regs[t].regmap_entry[hr]==0) {
4554 else if(regs[t].regmap_entry[hr]!=CCREG)
4556 emit_loadreg(regs[t].regmap_entry[hr],hr);
4562 for(hr=0;hr<HOST_REGS;hr++) {
4563 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=64) {
4564 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4565 assert(regs[t].regmap_entry[hr]!=64);
4566 if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4567 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4569 emit_loadreg(regs[t].regmap_entry[hr],hr);
4573 emit_sarimm(lr,31,hr);
4578 emit_loadreg(regs[t].regmap_entry[hr],hr);
4581 else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4582 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4584 emit_sarimm(lr,31,hr);
4591 int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4593 if(addr>=start && addr<start+slen*4-4)
4595 int t=(addr-start)>>2;
4597 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4598 for(hr=0;hr<HOST_REGS;hr++)
4602 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4604 if(regs[t].regmap_entry[hr]!=-1)
4613 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4618 if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4623 else // Same register but is it 32-bit or dirty?
4626 if(!((regs[t].dirty>>hr)&1))
4630 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4632 //printf("%x: dirty no match\n",addr);
4637 if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4639 //printf("%x: is32 no match\n",addr);
4645 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4647 if(requires_32bit[t]&~i_is32) return 0;
4649 // Delay slots are not valid branch targets
4650 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4651 // Delay slots require additional processing, so do not match
4652 if(is_ds[t]) return 0;
4657 for(hr=0;hr<HOST_REGS;hr++)
4663 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4677 // Used when a branch jumps into the delay slot of another branch
4678 void ds_assemble_entry(int i)
4680 int t=(ba[i]-start)>>2;
4681 if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4682 assem_debug("Assemble delay slot at %x\n",ba[i]);
4683 assem_debug("<->\n");
4684 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&®s[t].regmap[HOST_CCREG]!=CCREG)
4685 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4686 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4687 address_generation(t,®s[t],regs[t].regmap_entry);
4688 if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
4689 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4694 alu_assemble(t,®s[t]);break;
4696 imm16_assemble(t,®s[t]);break;
4698 shift_assemble(t,®s[t]);break;
4700 shiftimm_assemble(t,®s[t]);break;
4702 load_assemble(t,®s[t]);break;
4704 loadlr_assemble(t,®s[t]);break;
4706 store_assemble(t,®s[t]);break;
4708 storelr_assemble(t,®s[t]);break;
4710 cop0_assemble(t,®s[t]);break;
4712 cop1_assemble(t,®s[t]);break;
4714 c1ls_assemble(t,®s[t]);break;
4716 cop2_assemble(t,®s[t]);break;
4718 c2ls_assemble(t,®s[t]);break;
4720 c2op_assemble(t,®s[t]);break;
4722 fconv_assemble(t,®s[t]);break;
4724 float_assemble(t,®s[t]);break;
4726 fcomp_assemble(t,®s[t]);break;
4728 multdiv_assemble(t,®s[t]);break;
4730 mov_assemble(t,®s[t]);break;
4740 printf("Jump in the delay slot. This is probably a bug.\n");
4742 store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4743 load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4744 if(internal_branch(regs[t].is32,ba[i]+4))
4745 assem_debug("branch: internal\n");
4747 assem_debug("branch: external\n");
4748 assert(internal_branch(regs[t].is32,ba[i]+4));
4749 add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4753 void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4762 //if(ba[i]>=start && ba[i]<(start+slen*4))
4763 if(internal_branch(branch_regs[i].is32,ba[i]))
4765 int t=(ba[i]-start)>>2;
4766 if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4774 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4776 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4778 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4779 emit_andimm(HOST_CCREG,3,HOST_CCREG);
4783 else if(*adj==0||invert) {
4784 emit_addimm_and_set_flags(CLOCK_DIVIDER*(count+2),HOST_CCREG);
4790 emit_cmpimm(HOST_CCREG,-2*(count+2));
4794 add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4797 void do_ccstub(int n)
4800 assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
4801 set_jump_target(stubs[n][1],(int)out);
4803 if(stubs[n][6]==NULLDS) {
4804 // Delay slot instruction is nullified ("likely" branch)
4805 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4807 else if(stubs[n][6]!=TAKEN) {
4808 wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4811 if(internal_branch(branch_regs[i].is32,ba[i]))
4812 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4816 // Save PC as return address
4817 emit_movimm(stubs[n][5],EAX);
4818 emit_writeword(EAX,(int)&pcaddr);
4822 // Return address depends on which way the branch goes
4823 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
4825 int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4826 int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4827 int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4828 int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4838 if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
4842 #ifdef DESTRUCTIVE_WRITEBACK
4844 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
4845 emit_loadreg(rs1[i],s1l);
4848 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
4849 emit_loadreg(rs2[i],s1l);
4852 if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
4853 emit_loadreg(rs2[i],s2l);
4856 int addr,alt,ntaddr;
4859 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4860 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4861 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4869 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4870 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4871 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4877 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
4881 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4882 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4883 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4889 assert(hr<HOST_REGS);
4891 if((opcode[i]&0x2f)==4) // BEQ
4893 #ifdef HAVE_CMOV_IMM
4895 if(s2l>=0) emit_cmp(s1l,s2l);
4896 else emit_test(s1l,s1l);
4897 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
4902 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4904 if(s2h>=0) emit_cmp(s1h,s2h);
4905 else emit_test(s1h,s1h);
4906 emit_cmovne_reg(alt,addr);
4908 if(s2l>=0) emit_cmp(s1l,s2l);
4909 else emit_test(s1l,s1l);
4910 emit_cmovne_reg(alt,addr);
4913 if((opcode[i]&0x2f)==5) // BNE
4915 #ifdef HAVE_CMOV_IMM
4917 if(s2l>=0) emit_cmp(s1l,s2l);
4918 else emit_test(s1l,s1l);
4919 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
4924 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
4926 if(s2h>=0) emit_cmp(s1h,s2h);
4927 else emit_test(s1h,s1h);
4928 emit_cmovne_reg(alt,addr);
4930 if(s2l>=0) emit_cmp(s1l,s2l);
4931 else emit_test(s1l,s1l);
4932 emit_cmovne_reg(alt,addr);
4935 if((opcode[i]&0x2f)==6) // BLEZ
4937 //emit_movimm(ba[i],alt);
4938 //emit_movimm(start+i*4+8,addr);
4939 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4941 if(s1h>=0) emit_mov(addr,ntaddr);
4942 emit_cmovl_reg(alt,addr);
4945 emit_cmovne_reg(ntaddr,addr);
4946 emit_cmovs_reg(alt,addr);
4949 if((opcode[i]&0x2f)==7) // BGTZ
4951 //emit_movimm(ba[i],addr);
4952 //emit_movimm(start+i*4+8,ntaddr);
4953 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
4955 if(s1h>=0) emit_mov(addr,alt);
4956 emit_cmovl_reg(ntaddr,addr);
4959 emit_cmovne_reg(alt,addr);
4960 emit_cmovs_reg(ntaddr,addr);
4963 if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
4965 //emit_movimm(ba[i],alt);
4966 //emit_movimm(start+i*4+8,addr);
4967 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4968 if(s1h>=0) emit_test(s1h,s1h);
4969 else emit_test(s1l,s1l);
4970 emit_cmovs_reg(alt,addr);
4972 if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
4974 //emit_movimm(ba[i],addr);
4975 //emit_movimm(start+i*4+8,alt);
4976 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4977 if(s1h>=0) emit_test(s1h,s1h);
4978 else emit_test(s1l,s1l);
4979 emit_cmovs_reg(alt,addr);
4981 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
4982 if(source[i]&0x10000) // BC1T
4984 //emit_movimm(ba[i],alt);
4985 //emit_movimm(start+i*4+8,addr);
4986 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4987 emit_testimm(s1l,0x800000);
4988 emit_cmovne_reg(alt,addr);
4992 //emit_movimm(ba[i],addr);
4993 //emit_movimm(start+i*4+8,alt);
4994 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4995 emit_testimm(s1l,0x800000);
4996 emit_cmovne_reg(alt,addr);
4999 emit_writeword(addr,(int)&pcaddr);
5004 int r=get_reg(branch_regs[i].regmap,rs1[i]);
5005 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5006 r=get_reg(branch_regs[i].regmap,RTEMP);
5008 emit_writeword(r,(int)&pcaddr);
5010 else {printf("Unknown branch type in do_ccstub\n");exit(1);}
5012 // Update cycle count
5013 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5014 if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
5015 emit_call((int)cc_interrupt);
5016 if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
5017 if(stubs[n][6]==TAKEN) {
5018 if(internal_branch(branch_regs[i].is32,ba[i]))
5019 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
5020 else if(itype[i]==RJUMP) {
5021 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5022 emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5024 emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
5026 }else if(stubs[n][6]==NOTTAKEN) {
5027 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5028 else load_all_regs(branch_regs[i].regmap);
5029 }else if(stubs[n][6]==NULLDS) {
5030 // Delay slot instruction is nullified ("likely" branch)
5031 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5032 else load_all_regs(regs[i].regmap);
5034 load_all_regs(branch_regs[i].regmap);
5036 emit_jmp(stubs[n][2]); // return address
5038 /* This works but uses a lot of memory...
5039 emit_readword((int)&last_count,ECX);
5040 emit_add(HOST_CCREG,ECX,EAX);
5041 emit_writeword(EAX,(int)&Count);
5042 emit_call((int)gen_interupt);
5043 emit_readword((int)&Count,HOST_CCREG);
5044 emit_readword((int)&next_interupt,EAX);
5045 emit_readword((int)&pending_exception,EBX);
5046 emit_writeword(EAX,(int)&last_count);
5047 emit_sub(HOST_CCREG,EAX,HOST_CCREG);
5049 int jne_instr=(int)out;
5051 if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
5052 load_all_regs(branch_regs[i].regmap);
5053 emit_jmp(stubs[n][2]); // return address
5054 set_jump_target(jne_instr,(int)out);
5055 emit_readword((int)&pcaddr,EAX);
5056 // Call get_addr_ht instead of doing the hash table here.
5057 // This code is executed infrequently and takes up a lot of space
5058 // so smaller is better.
5059 emit_storereg(CCREG,HOST_CCREG);
5061 emit_call((int)get_addr_ht);
5062 emit_loadreg(CCREG,HOST_CCREG);
5063 emit_addimm(ESP,4,ESP);
5067 add_to_linker(int addr,int target,int ext)
5069 link_addr[linkcount][0]=addr;
5070 link_addr[linkcount][1]=target;
5071 link_addr[linkcount][2]=ext;
5075 void ujump_assemble(int i,struct regstat *i_regs)
5077 signed char *i_regmap=i_regs->regmap;
5078 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5079 address_generation(i+1,i_regs,regs[i].regmap_entry);
5081 int temp=get_reg(branch_regs[i].regmap,PTEMP);
5082 if(rt1[i]==31&&temp>=0)
5084 int return_address=start+i*4+8;
5085 if(get_reg(branch_regs[i].regmap,31)>0)
5086 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5089 ds_assemble(i+1,i_regs);
5090 uint64_t bc_unneeded=branch_regs[i].u;
5091 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5092 bc_unneeded|=1|(1LL<<rt1[i]);
5093 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5094 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5095 bc_unneeded,bc_unneeded_upper);
5096 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5099 unsigned int return_address;
5100 assert(rt1[i+1]!=31);
5101 assert(rt2[i+1]!=31);
5102 rt=get_reg(branch_regs[i].regmap,31);
5103 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5105 return_address=start+i*4+8;
5108 if(internal_branch(branch_regs[i].is32,return_address)) {
5110 if(temp==EXCLUDE_REG||temp>=HOST_REGS||
5111 branch_regs[i].regmap[temp]>=0)
5113 temp=get_reg(branch_regs[i].regmap,-1);
5116 if(temp<0) temp=HOST_TEMPREG;
5118 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5119 else emit_movimm(return_address,rt);
5127 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5130 emit_movimm(return_address,rt); // PC into link register
5132 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5138 cc=get_reg(branch_regs[i].regmap,CCREG);
5139 assert(cc==HOST_CCREG);
5140 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5142 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5144 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5145 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5146 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5147 if(internal_branch(branch_regs[i].is32,ba[i]))
5148 assem_debug("branch: internal\n");
5150 assem_debug("branch: external\n");
5151 if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5152 ds_assemble_entry(i);
5155 add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5160 void rjump_assemble(int i,struct regstat *i_regs)
5162 signed char *i_regmap=i_regs->regmap;
5165 rs=get_reg(branch_regs[i].regmap,rs1[i]);
5167 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5168 // Delay slot abuse, make a copy of the branch address register
5169 temp=get_reg(branch_regs[i].regmap,RTEMP);
5171 assert(regs[i].regmap[temp]==RTEMP);
5175 address_generation(i+1,i_regs,regs[i].regmap_entry);
5179 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5180 int return_address=start+i*4+8;
5181 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5187 int rh=get_reg(regs[i].regmap,RHASH);
5188 if(rh>=0) do_preload_rhash(rh);
5191 ds_assemble(i+1,i_regs);
5192 uint64_t bc_unneeded=branch_regs[i].u;
5193 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5194 bc_unneeded|=1|(1LL<<rt1[i]);
5195 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5196 bc_unneeded&=~(1LL<<rs1[i]);
5197 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5198 bc_unneeded,bc_unneeded_upper);
5199 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5201 int rt,return_address;
5202 assert(rt1[i+1]!=rt1[i]);
5203 assert(rt2[i+1]!=rt1[i]);
5204 rt=get_reg(branch_regs[i].regmap,rt1[i]);
5205 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5207 return_address=start+i*4+8;
5211 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5214 emit_movimm(return_address,rt); // PC into link register
5216 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5219 cc=get_reg(branch_regs[i].regmap,CCREG);
5220 assert(cc==HOST_CCREG);
5222 int rh=get_reg(branch_regs[i].regmap,RHASH);
5223 int ht=get_reg(branch_regs[i].regmap,RHTBL);
5225 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5226 do_preload_rhtbl(ht);
5230 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5231 #ifdef DESTRUCTIVE_WRITEBACK
5232 if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5233 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5234 emit_loadreg(rs1[i],rs);
5239 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5243 do_miniht_load(ht,rh);
5246 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5247 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5249 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5250 add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5252 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5255 do_miniht_jump(rs,rh,ht);
5260 //if(rs!=EAX) emit_mov(rs,EAX);
5261 //emit_jmp((int)jump_vaddr_eax);
5262 emit_jmp(jump_vaddr_reg[rs]);
5267 emit_shrimm(rs,16,rs);
5268 emit_xor(temp,rs,rs);
5269 emit_movzwl_reg(rs,rs);
5270 emit_shlimm(rs,4,rs);
5271 emit_cmpmem_indexed((int)hash_table,rs,temp);
5272 emit_jne((int)out+14);
5273 emit_readword_indexed((int)hash_table+4,rs,rs);
5275 emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5276 emit_addimm_no_flags(8,rs);
5277 emit_jeq((int)out-17);
5278 // No hit on hash table, call compiler
5281 #ifdef DEBUG_CYCLE_COUNT
5282 emit_readword((int)&last_count,ECX);
5283 emit_add(HOST_CCREG,ECX,HOST_CCREG);
5284 emit_readword((int)&next_interupt,ECX);
5285 emit_writeword(HOST_CCREG,(int)&Count);
5286 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5287 emit_writeword(ECX,(int)&last_count);
5290 emit_storereg(CCREG,HOST_CCREG);
5291 emit_call((int)get_addr);
5292 emit_loadreg(CCREG,HOST_CCREG);
5293 emit_addimm(ESP,4,ESP);
5295 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5296 if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5300 void cjump_assemble(int i,struct regstat *i_regs)
5302 signed char *i_regmap=i_regs->regmap;
5305 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5306 assem_debug("match=%d\n",match);
5307 int s1h,s1l,s2h,s2l;
5308 int prev_cop1_usable=cop1_usable;
5309 int unconditional=0,nop=0;
5312 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5313 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5314 if(!match) invert=1;
5315 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5316 if(i>(ba[i]-start)>>2) invert=1;
5320 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5321 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5322 s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5323 s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5326 s1l=get_reg(i_regmap,rs1[i]);
5327 s1h=get_reg(i_regmap,rs1[i]|64);
5328 s2l=get_reg(i_regmap,rs2[i]);
5329 s2h=get_reg(i_regmap,rs2[i]|64);
5331 if(rs1[i]==0&&rs2[i]==0)
5333 if(opcode[i]&1) nop=1;
5334 else unconditional=1;
5335 //assert(opcode[i]!=5);
5336 //assert(opcode[i]!=7);
5337 //assert(opcode[i]!=0x15);
5338 //assert(opcode[i]!=0x17);
5344 only32=(regs[i].was32>>rs2[i])&1;
5349 only32=(regs[i].was32>>rs1[i])&1;
5352 only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5356 // Out of order execution (delay slot first)
5358 address_generation(i+1,i_regs,regs[i].regmap_entry);
5359 ds_assemble(i+1,i_regs);
5361 uint64_t bc_unneeded=branch_regs[i].u;
5362 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5363 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5364 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5366 bc_unneeded_upper|=1;
5367 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5368 bc_unneeded,bc_unneeded_upper);
5369 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5370 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5371 cc=get_reg(branch_regs[i].regmap,CCREG);
5372 assert(cc==HOST_CCREG);
5374 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5375 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5376 //assem_debug("cycle count (adj)\n");
5378 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5379 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5380 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5381 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5383 assem_debug("branch: internal\n");
5385 assem_debug("branch: external\n");
5386 if(internal&&is_ds[(ba[i]-start)>>2]) {
5387 ds_assemble_entry(i);
5390 add_to_linker((int)out,ba[i],internal);
5393 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5394 if(((u_int)out)&7) emit_addnop(0);
5399 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5402 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5405 int taken=0,nottaken=0,nottaken1=0;
5406 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5407 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5411 if(opcode[i]==4) // BEQ
5413 if(s2h>=0) emit_cmp(s1h,s2h);
5414 else emit_test(s1h,s1h);
5418 if(opcode[i]==5) // BNE
5420 if(s2h>=0) emit_cmp(s1h,s2h);
5421 else emit_test(s1h,s1h);
5422 if(invert) taken=(int)out;
5423 else add_to_linker((int)out,ba[i],internal);
5426 if(opcode[i]==6) // BLEZ
5429 if(invert) taken=(int)out;
5430 else add_to_linker((int)out,ba[i],internal);
5435 if(opcode[i]==7) // BGTZ
5440 if(invert) taken=(int)out;
5441 else add_to_linker((int)out,ba[i],internal);
5446 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5448 if(opcode[i]==4) // BEQ
5450 if(s2l>=0) emit_cmp(s1l,s2l);
5451 else emit_test(s1l,s1l);
5456 add_to_linker((int)out,ba[i],internal);
5460 if(opcode[i]==5) // BNE
5462 if(s2l>=0) emit_cmp(s1l,s2l);
5463 else emit_test(s1l,s1l);
5468 add_to_linker((int)out,ba[i],internal);
5472 if(opcode[i]==6) // BLEZ
5479 add_to_linker((int)out,ba[i],internal);
5483 if(opcode[i]==7) // BGTZ
5490 add_to_linker((int)out,ba[i],internal);
5495 if(taken) set_jump_target(taken,(int)out);
5496 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5497 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5499 emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5500 add_to_linker((int)out,ba[i],internal);
5503 add_to_linker((int)out,ba[i],internal*2);
5509 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5510 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5511 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5513 assem_debug("branch: internal\n");
5515 assem_debug("branch: external\n");
5516 if(internal&&is_ds[(ba[i]-start)>>2]) {
5517 ds_assemble_entry(i);
5520 add_to_linker((int)out,ba[i],internal);
5524 set_jump_target(nottaken,(int)out);
5527 if(nottaken1) set_jump_target(nottaken1,(int)out);
5529 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5531 } // (!unconditional)
5535 // In-order execution (branch first)
5536 //if(likely[i]) printf("IOL\n");
5539 int taken=0,nottaken=0,nottaken1=0;
5540 if(!unconditional&&!nop) {
5544 if((opcode[i]&0x2f)==4) // BEQ
5546 if(s2h>=0) emit_cmp(s1h,s2h);
5547 else emit_test(s1h,s1h);
5551 if((opcode[i]&0x2f)==5) // BNE
5553 if(s2h>=0) emit_cmp(s1h,s2h);
5554 else emit_test(s1h,s1h);
5558 if((opcode[i]&0x2f)==6) // BLEZ
5566 if((opcode[i]&0x2f)==7) // BGTZ
5576 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5578 if((opcode[i]&0x2f)==4) // BEQ
5580 if(s2l>=0) emit_cmp(s1l,s2l);
5581 else emit_test(s1l,s1l);
5585 if((opcode[i]&0x2f)==5) // BNE
5587 if(s2l>=0) emit_cmp(s1l,s2l);
5588 else emit_test(s1l,s1l);
5592 if((opcode[i]&0x2f)==6) // BLEZ
5598 if((opcode[i]&0x2f)==7) // BGTZ
5604 } // if(!unconditional)
5606 uint64_t ds_unneeded=branch_regs[i].u;
5607 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5608 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5609 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5610 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5612 ds_unneeded_upper|=1;
5615 if(taken) set_jump_target(taken,(int)out);
5616 assem_debug("1:\n");
5617 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5618 ds_unneeded,ds_unneeded_upper);
5620 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5621 address_generation(i+1,&branch_regs[i],0);
5622 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5623 ds_assemble(i+1,&branch_regs[i]);
5624 cc=get_reg(branch_regs[i].regmap,CCREG);
5626 emit_loadreg(CCREG,cc=HOST_CCREG);
5627 // CHECK: Is the following instruction (fall thru) allocated ok?
5629 assert(cc==HOST_CCREG);
5630 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5631 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5632 assem_debug("cycle count (adj)\n");
5633 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5634 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5636 assem_debug("branch: internal\n");
5638 assem_debug("branch: external\n");
5639 if(internal&&is_ds[(ba[i]-start)>>2]) {
5640 ds_assemble_entry(i);
5643 add_to_linker((int)out,ba[i],internal);
5648 cop1_usable=prev_cop1_usable;
5649 if(!unconditional) {
5650 if(nottaken1) set_jump_target(nottaken1,(int)out);
5651 set_jump_target(nottaken,(int)out);
5652 assem_debug("2:\n");
5654 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5655 ds_unneeded,ds_unneeded_upper);
5656 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5657 address_generation(i+1,&branch_regs[i],0);
5658 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5659 ds_assemble(i+1,&branch_regs[i]);
5661 cc=get_reg(branch_regs[i].regmap,CCREG);
5662 if(cc==-1&&!likely[i]) {
5663 // Cycle count isn't in a register, temporarily load it then write it out
5664 emit_loadreg(CCREG,HOST_CCREG);
5665 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5668 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5669 emit_storereg(CCREG,HOST_CCREG);
5672 cc=get_reg(i_regmap,CCREG);
5673 assert(cc==HOST_CCREG);
5674 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5677 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5683 void sjump_assemble(int i,struct regstat *i_regs)
5685 signed char *i_regmap=i_regs->regmap;
5688 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5689 assem_debug("smatch=%d\n",match);
5691 int prev_cop1_usable=cop1_usable;
5692 int unconditional=0,nevertaken=0;
5695 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5696 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5697 if(!match) invert=1;
5698 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5699 if(i>(ba[i]-start)>>2) invert=1;
5702 //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
5703 //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
5706 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5707 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5710 s1l=get_reg(i_regmap,rs1[i]);
5711 s1h=get_reg(i_regmap,rs1[i]|64);
5715 if(opcode2[i]&1) unconditional=1;
5717 // These are never taken (r0 is never less than zero)
5718 //assert(opcode2[i]!=0);
5719 //assert(opcode2[i]!=2);
5720 //assert(opcode2[i]!=0x10);
5721 //assert(opcode2[i]!=0x12);
5724 only32=(regs[i].was32>>rs1[i])&1;
5728 // Out of order execution (delay slot first)
5730 address_generation(i+1,i_regs,regs[i].regmap_entry);
5731 ds_assemble(i+1,i_regs);
5733 uint64_t bc_unneeded=branch_regs[i].u;
5734 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5735 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5736 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5738 bc_unneeded_upper|=1;
5739 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5740 bc_unneeded,bc_unneeded_upper);
5741 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5742 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5744 int rt,return_address;
5745 rt=get_reg(branch_regs[i].regmap,31);
5746 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5748 // Save the PC even if the branch is not taken
5749 return_address=start+i*4+8;
5750 emit_movimm(return_address,rt); // PC into link register
5752 if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5756 cc=get_reg(branch_regs[i].regmap,CCREG);
5757 assert(cc==HOST_CCREG);
5759 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5760 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5761 assem_debug("cycle count (adj)\n");
5763 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5764 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5765 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5766 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5768 assem_debug("branch: internal\n");
5770 assem_debug("branch: external\n");
5771 if(internal&&is_ds[(ba[i]-start)>>2]) {
5772 ds_assemble_entry(i);
5775 add_to_linker((int)out,ba[i],internal);
5778 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5779 if(((u_int)out)&7) emit_addnop(0);
5783 else if(nevertaken) {
5784 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5787 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5791 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5792 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5796 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5803 add_to_linker((int)out,ba[i],internal);
5807 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5814 add_to_linker((int)out,ba[i],internal);
5822 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5829 add_to_linker((int)out,ba[i],internal);
5833 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5840 add_to_linker((int)out,ba[i],internal);
5847 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5848 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5850 emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5851 add_to_linker((int)out,ba[i],internal);
5854 add_to_linker((int)out,ba[i],internal*2);
5860 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5861 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5862 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5864 assem_debug("branch: internal\n");
5866 assem_debug("branch: external\n");
5867 if(internal&&is_ds[(ba[i]-start)>>2]) {
5868 ds_assemble_entry(i);
5871 add_to_linker((int)out,ba[i],internal);
5875 set_jump_target(nottaken,(int)out);
5879 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5881 } // (!unconditional)
5885 // In-order execution (branch first)
5889 int rt,return_address;
5890 rt=get_reg(branch_regs[i].regmap,31);
5892 // Save the PC even if the branch is not taken
5893 return_address=start+i*4+8;
5894 emit_movimm(return_address,rt); // PC into link register
5896 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5900 if(!unconditional) {
5901 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5905 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
5911 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
5921 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
5927 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
5934 } // if(!unconditional)
5936 uint64_t ds_unneeded=branch_regs[i].u;
5937 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5938 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5939 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5940 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5942 ds_unneeded_upper|=1;
5945 //assem_debug("1:\n");
5946 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5947 ds_unneeded,ds_unneeded_upper);
5949 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5950 address_generation(i+1,&branch_regs[i],0);
5951 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5952 ds_assemble(i+1,&branch_regs[i]);
5953 cc=get_reg(branch_regs[i].regmap,CCREG);
5955 emit_loadreg(CCREG,cc=HOST_CCREG);
5956 // CHECK: Is the following instruction (fall thru) allocated ok?
5958 assert(cc==HOST_CCREG);
5959 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5960 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5961 assem_debug("cycle count (adj)\n");
5962 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5963 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5965 assem_debug("branch: internal\n");
5967 assem_debug("branch: external\n");
5968 if(internal&&is_ds[(ba[i]-start)>>2]) {
5969 ds_assemble_entry(i);
5972 add_to_linker((int)out,ba[i],internal);
5977 cop1_usable=prev_cop1_usable;
5978 if(!unconditional) {
5979 set_jump_target(nottaken,(int)out);
5980 assem_debug("1:\n");
5982 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5983 ds_unneeded,ds_unneeded_upper);
5984 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5985 address_generation(i+1,&branch_regs[i],0);
5986 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5987 ds_assemble(i+1,&branch_regs[i]);
5989 cc=get_reg(branch_regs[i].regmap,CCREG);
5990 if(cc==-1&&!likely[i]) {
5991 // Cycle count isn't in a register, temporarily load it then write it out
5992 emit_loadreg(CCREG,HOST_CCREG);
5993 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5996 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5997 emit_storereg(CCREG,HOST_CCREG);
6000 cc=get_reg(i_regmap,CCREG);
6001 assert(cc==HOST_CCREG);
6002 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6005 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6011 void fjump_assemble(int i,struct regstat *i_regs)
6013 signed char *i_regmap=i_regs->regmap;
6016 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6017 assem_debug("fmatch=%d\n",match);
6021 int internal=internal_branch(branch_regs[i].is32,ba[i]);
6022 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
6023 if(!match) invert=1;
6024 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6025 if(i>(ba[i]-start)>>2) invert=1;
6029 fs=get_reg(branch_regs[i].regmap,FSREG);
6030 address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
6033 fs=get_reg(i_regmap,FSREG);
6036 // Check cop1 unusable
6038 cs=get_reg(i_regmap,CSREG);
6040 emit_testimm(cs,0x20000000);
6043 add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
6048 // Out of order execution (delay slot first)
6050 ds_assemble(i+1,i_regs);
6052 uint64_t bc_unneeded=branch_regs[i].u;
6053 uint64_t bc_unneeded_upper=branch_regs[i].uu;
6054 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6055 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
6057 bc_unneeded_upper|=1;
6058 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6059 bc_unneeded,bc_unneeded_upper);
6060 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
6061 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6062 cc=get_reg(branch_regs[i].regmap,CCREG);
6063 assert(cc==HOST_CCREG);
6064 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6065 assem_debug("cycle count (adj)\n");
6068 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6071 emit_testimm(fs,0x800000);
6072 if(source[i]&0x10000) // BC1T
6078 add_to_linker((int)out,ba[i],internal);
6087 add_to_linker((int)out,ba[i],internal);
6095 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
6096 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6097 else if(match) emit_addnop(13);
6099 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6100 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6102 assem_debug("branch: internal\n");
6104 assem_debug("branch: external\n");
6105 if(internal&&is_ds[(ba[i]-start)>>2]) {
6106 ds_assemble_entry(i);
6109 add_to_linker((int)out,ba[i],internal);
6112 set_jump_target(nottaken,(int)out);
6116 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
6118 } // (!unconditional)
6122 // In-order execution (branch first)
6126 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6129 emit_testimm(fs,0x800000);
6130 if(source[i]&0x10000) // BC1T
6141 } // if(!unconditional)
6143 uint64_t ds_unneeded=branch_regs[i].u;
6144 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6145 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6146 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6147 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6149 ds_unneeded_upper|=1;
6151 //assem_debug("1:\n");
6152 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6153 ds_unneeded,ds_unneeded_upper);
6155 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6156 address_generation(i+1,&branch_regs[i],0);
6157 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6158 ds_assemble(i+1,&branch_regs[i]);
6159 cc=get_reg(branch_regs[i].regmap,CCREG);
6161 emit_loadreg(CCREG,cc=HOST_CCREG);
6162 // CHECK: Is the following instruction (fall thru) allocated ok?
6164 assert(cc==HOST_CCREG);
6165 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6166 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6167 assem_debug("cycle count (adj)\n");
6168 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6169 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6171 assem_debug("branch: internal\n");
6173 assem_debug("branch: external\n");
6174 if(internal&&is_ds[(ba[i]-start)>>2]) {
6175 ds_assemble_entry(i);
6178 add_to_linker((int)out,ba[i],internal);
6183 if(1) { // <- FIXME (don't need this)
6184 set_jump_target(nottaken,(int)out);
6185 assem_debug("1:\n");
6187 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6188 ds_unneeded,ds_unneeded_upper);
6189 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6190 address_generation(i+1,&branch_regs[i],0);
6191 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6192 ds_assemble(i+1,&branch_regs[i]);
6194 cc=get_reg(branch_regs[i].regmap,CCREG);
6195 if(cc==-1&&!likely[i]) {
6196 // Cycle count isn't in a register, temporarily load it then write it out
6197 emit_loadreg(CCREG,HOST_CCREG);
6198 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6201 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6202 emit_storereg(CCREG,HOST_CCREG);
6205 cc=get_reg(i_regmap,CCREG);
6206 assert(cc==HOST_CCREG);
6207 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6210 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6216 static void pagespan_assemble(int i,struct regstat *i_regs)
6218 int s1l=get_reg(i_regs->regmap,rs1[i]);
6219 int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6220 int s2l=get_reg(i_regs->regmap,rs2[i]);
6221 int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6222 void *nt_branch=NULL;
6225 int unconditional=0;
6235 if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6239 int addr,alt,ntaddr;
6240 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6244 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6245 (i_regs->regmap[hr]&63)!=rs1[i] &&
6246 (i_regs->regmap[hr]&63)!=rs2[i] )
6255 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6256 (i_regs->regmap[hr]&63)!=rs1[i] &&
6257 (i_regs->regmap[hr]&63)!=rs2[i] )
6263 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6267 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6268 (i_regs->regmap[hr]&63)!=rs1[i] &&
6269 (i_regs->regmap[hr]&63)!=rs2[i] )
6276 assert(hr<HOST_REGS);
6277 if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6278 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6280 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6281 if(opcode[i]==2) // J
6285 if(opcode[i]==3) // JAL
6288 int rt=get_reg(i_regs->regmap,31);
6289 emit_movimm(start+i*4+8,rt);
6292 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6295 if(opcode2[i]==9) // JALR
6297 int rt=get_reg(i_regs->regmap,rt1[i]);
6298 emit_movimm(start+i*4+8,rt);
6301 if((opcode[i]&0x3f)==4) // BEQ
6308 #ifdef HAVE_CMOV_IMM
6310 if(s2l>=0) emit_cmp(s1l,s2l);
6311 else emit_test(s1l,s1l);
6312 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6318 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6320 if(s2h>=0) emit_cmp(s1h,s2h);
6321 else emit_test(s1h,s1h);
6322 emit_cmovne_reg(alt,addr);
6324 if(s2l>=0) emit_cmp(s1l,s2l);
6325 else emit_test(s1l,s1l);
6326 emit_cmovne_reg(alt,addr);
6329 if((opcode[i]&0x3f)==5) // BNE
6331 #ifdef HAVE_CMOV_IMM
6333 if(s2l>=0) emit_cmp(s1l,s2l);
6334 else emit_test(s1l,s1l);
6335 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6341 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6343 if(s2h>=0) emit_cmp(s1h,s2h);
6344 else emit_test(s1h,s1h);
6345 emit_cmovne_reg(alt,addr);
6347 if(s2l>=0) emit_cmp(s1l,s2l);
6348 else emit_test(s1l,s1l);
6349 emit_cmovne_reg(alt,addr);
6352 if((opcode[i]&0x3f)==0x14) // BEQL
6355 if(s2h>=0) emit_cmp(s1h,s2h);
6356 else emit_test(s1h,s1h);
6360 if(s2l>=0) emit_cmp(s1l,s2l);
6361 else emit_test(s1l,s1l);
6362 if(nottaken) set_jump_target(nottaken,(int)out);
6366 if((opcode[i]&0x3f)==0x15) // BNEL
6369 if(s2h>=0) emit_cmp(s1h,s2h);
6370 else emit_test(s1h,s1h);
6374 if(s2l>=0) emit_cmp(s1l,s2l);
6375 else emit_test(s1l,s1l);
6378 if(taken) set_jump_target(taken,(int)out);
6380 if((opcode[i]&0x3f)==6) // BLEZ
6382 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6384 if(s1h>=0) emit_mov(addr,ntaddr);
6385 emit_cmovl_reg(alt,addr);
6388 emit_cmovne_reg(ntaddr,addr);
6389 emit_cmovs_reg(alt,addr);
6392 if((opcode[i]&0x3f)==7) // BGTZ
6394 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6396 if(s1h>=0) emit_mov(addr,alt);
6397 emit_cmovl_reg(ntaddr,addr);
6400 emit_cmovne_reg(alt,addr);
6401 emit_cmovs_reg(ntaddr,addr);
6404 if((opcode[i]&0x3f)==0x16) // BLEZL
6406 assert((opcode[i]&0x3f)!=0x16);
6408 if((opcode[i]&0x3f)==0x17) // BGTZL
6410 assert((opcode[i]&0x3f)!=0x17);
6412 assert(opcode[i]!=1); // BLTZ/BGEZ
6414 //FIXME: Check CSREG
6415 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6416 if((source[i]&0x30000)==0) // BC1F
6418 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6419 emit_testimm(s1l,0x800000);
6420 emit_cmovne_reg(alt,addr);
6422 if((source[i]&0x30000)==0x10000) // BC1T
6424 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6425 emit_testimm(s1l,0x800000);
6426 emit_cmovne_reg(alt,addr);
6428 if((source[i]&0x30000)==0x20000) // BC1FL
6430 emit_testimm(s1l,0x800000);
6434 if((source[i]&0x30000)==0x30000) // BC1TL
6436 emit_testimm(s1l,0x800000);
6442 assert(i_regs->regmap[HOST_CCREG]==CCREG);
6443 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6444 if(likely[i]||unconditional)
6446 emit_movimm(ba[i],HOST_BTREG);
6448 else if(addr!=HOST_BTREG)
6450 emit_mov(addr,HOST_BTREG);
6452 void *branch_addr=out;
6454 int target_addr=start+i*4+5;
6456 void *compiled_target_addr=check_addr(target_addr);
6457 emit_extjump_ds((int)branch_addr,target_addr);
6458 if(compiled_target_addr) {
6459 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6460 add_link(target_addr,stub);
6462 else set_jump_target((int)branch_addr,(int)stub);
6465 set_jump_target((int)nottaken,(int)out);
6466 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6467 void *branch_addr=out;
6469 int target_addr=start+i*4+8;
6471 void *compiled_target_addr=check_addr(target_addr);
6472 emit_extjump_ds((int)branch_addr,target_addr);
6473 if(compiled_target_addr) {
6474 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6475 add_link(target_addr,stub);
6477 else set_jump_target((int)branch_addr,(int)stub);
6481 // Assemble the delay slot for the above
6482 static void pagespan_ds()
6484 assem_debug("initial delay slot:\n");
6485 u_int vaddr=start+1;
6486 u_int page=get_page(vaddr);
6487 u_int vpage=get_vpage(vaddr);
6488 ll_add(jump_dirty+vpage,vaddr,(void *)out);
6490 ll_add(jump_in+page,vaddr,(void *)out);
6491 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6492 if(regs[0].regmap[HOST_CCREG]!=CCREG)
6493 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6494 if(regs[0].regmap[HOST_BTREG]!=BTREG)
6495 emit_writeword(HOST_BTREG,(int)&branch_target);
6496 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6497 address_generation(0,®s[0],regs[0].regmap_entry);
6498 if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
6499 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6504 alu_assemble(0,®s[0]);break;
6506 imm16_assemble(0,®s[0]);break;
6508 shift_assemble(0,®s[0]);break;
6510 shiftimm_assemble(0,®s[0]);break;
6512 load_assemble(0,®s[0]);break;
6514 loadlr_assemble(0,®s[0]);break;
6516 store_assemble(0,®s[0]);break;
6518 storelr_assemble(0,®s[0]);break;
6520 cop0_assemble(0,®s[0]);break;
6522 cop1_assemble(0,®s[0]);break;
6524 c1ls_assemble(0,®s[0]);break;
6526 cop2_assemble(0,®s[0]);break;
6528 c2ls_assemble(0,®s[0]);break;
6530 c2op_assemble(0,®s[0]);break;
6532 fconv_assemble(0,®s[0]);break;
6534 float_assemble(0,®s[0]);break;
6536 fcomp_assemble(0,®s[0]);break;
6538 multdiv_assemble(0,®s[0]);break;
6540 mov_assemble(0,®s[0]);break;
6550 printf("Jump in the delay slot. This is probably a bug.\n");
6552 int btaddr=get_reg(regs[0].regmap,BTREG);
6554 btaddr=get_reg(regs[0].regmap,-1);
6555 emit_readword((int)&branch_target,btaddr);
6557 assert(btaddr!=HOST_CCREG);
6558 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6560 emit_movimm(start+4,HOST_TEMPREG);
6561 emit_cmp(btaddr,HOST_TEMPREG);
6563 emit_cmpimm(btaddr,start+4);
6565 int branch=(int)out;
6567 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6568 emit_jmp(jump_vaddr_reg[btaddr]);
6569 set_jump_target(branch,(int)out);
6570 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6571 load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6574 // Basic liveness analysis for MIPS registers
6575 void unneeded_registers(int istart,int iend,int r)
6579 uint64_t temp_u,temp_uu;
6584 u=unneeded_reg[iend+1];
6585 uu=unneeded_reg_upper[iend+1];
6588 for (i=iend;i>=istart;i--)
6590 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6591 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6593 // If subroutine call, flag return address as a possible branch target
6594 if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6596 if(ba[i]<start || ba[i]>=(start+slen*4))
6598 // Branch out of this block, flush all regs
6602 if(itype[i]==UJUMP&&rt1[i]==31)
6604 uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6606 if(itype[i]==RJUMP&&rs1[i]==31)
6608 uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6610 if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
6611 if(itype[i]==UJUMP&&rt1[i]==31)
6613 //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6614 uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6616 if(itype[i]==RJUMP&&rs1[i]==31)
6618 //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6619 uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6622 branch_unneeded_reg[i]=u;
6623 branch_unneeded_reg_upper[i]=uu;
6624 // Merge in delay slot
6625 tdep=(~uu>>rt1[i+1])&1;
6626 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6627 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6628 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6629 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6630 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6632 // If branch is "likely" (and conditional)
6633 // then we skip the delay slot on the fall-thru path
6636 u&=unneeded_reg[i+2];
6637 uu&=unneeded_reg_upper[i+2];
6648 // Internal branch, flag target
6649 bt[(ba[i]-start)>>2]=1;
6650 if(ba[i]<=start+i*4) {
6652 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6654 // Unconditional branch
6657 // Conditional branch (not taken case)
6658 temp_u=unneeded_reg[i+2];
6659 temp_uu=unneeded_reg_upper[i+2];
6661 // Merge in delay slot
6662 tdep=(~temp_uu>>rt1[i+1])&1;
6663 temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6664 temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6665 temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6666 temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6667 temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6668 temp_u|=1;temp_uu|=1;
6669 // If branch is "likely" (and conditional)
6670 // then we skip the delay slot on the fall-thru path
6673 temp_u&=unneeded_reg[i+2];
6674 temp_uu&=unneeded_reg_upper[i+2];
6682 tdep=(~temp_uu>>rt1[i])&1;
6683 temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6684 temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6685 temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6686 temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6687 temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6688 temp_u|=1;temp_uu|=1;
6689 unneeded_reg[i]=temp_u;
6690 unneeded_reg_upper[i]=temp_uu;
6691 // Only go three levels deep. This recursion can take an
6692 // excessive amount of time if there are a lot of nested loops.
6694 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6696 unneeded_reg[(ba[i]-start)>>2]=1;
6697 unneeded_reg_upper[(ba[i]-start)>>2]=1;
6700 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6702 // Unconditional branch
6703 u=unneeded_reg[(ba[i]-start)>>2];
6704 uu=unneeded_reg_upper[(ba[i]-start)>>2];
6705 branch_unneeded_reg[i]=u;
6706 branch_unneeded_reg_upper[i]=uu;
6709 //branch_unneeded_reg[i]=u;
6710 //branch_unneeded_reg_upper[i]=uu;
6711 // Merge in delay slot
6712 tdep=(~uu>>rt1[i+1])&1;
6713 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6714 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6715 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6716 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6717 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6720 // Conditional branch
6721 b=unneeded_reg[(ba[i]-start)>>2];
6722 bu=unneeded_reg_upper[(ba[i]-start)>>2];
6723 branch_unneeded_reg[i]=b;
6724 branch_unneeded_reg_upper[i]=bu;
6727 //branch_unneeded_reg[i]=b;
6728 //branch_unneeded_reg_upper[i]=bu;
6729 // Branch delay slot
6730 tdep=(~uu>>rt1[i+1])&1;
6731 b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6732 bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6733 b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6734 bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6735 bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6737 // If branch is "likely" then we skip the
6738 // delay slot on the fall-thru path
6743 u&=unneeded_reg[i+2];
6744 uu&=unneeded_reg_upper[i+2];
6755 branch_unneeded_reg[i]&=unneeded_reg[i+2];
6756 branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6757 //branch_unneeded_reg[i]=1;
6758 //branch_unneeded_reg_upper[i]=1;
6760 branch_unneeded_reg[i]=1;
6761 branch_unneeded_reg_upper[i]=1;
6767 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
6769 // SYSCALL instruction (software interrupt)
6773 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6775 // ERET instruction (return from interrupt)
6780 tdep=(~uu>>rt1[i])&1;
6781 // Written registers are unneeded
6786 // Accessed registers are needed
6791 // Source-target dependencies
6792 uu&=~(tdep<<dep1[i]);
6793 uu&=~(tdep<<dep2[i]);
6794 // R0 is always unneeded
6798 unneeded_reg_upper[i]=uu;
6800 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6803 for(r=1;r<=CCREG;r++) {
6804 if((unneeded_reg[i]>>r)&1) {
6805 if(r==HIREG) printf(" HI");
6806 else if(r==LOREG) printf(" LO");
6807 else printf(" r%d",r);
6811 for(r=1;r<=CCREG;r++) {
6812 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
6813 if(r==HIREG) printf(" HI");
6814 else if(r==LOREG) printf(" LO");
6815 else printf(" r%d",r);
6821 for (i=iend;i>=istart;i--)
6823 unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
6828 // Identify registers which are likely to contain 32-bit values
6829 // This is used to predict whether any branches will jump to a
6830 // location with 64-bit values in registers.
6831 static void provisional_32bit()
6835 uint64_t lastbranch=1;
6840 if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
6841 if(i>1) is32=lastbranch;
6847 if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
6849 if(i>2) is32=lastbranch;
6853 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
6855 if(rs1[i-2]==0||rs2[i-2]==0)
6858 is32|=1LL<<rs1[i-2];
6861 is32|=1LL<<rs2[i-2];
6866 // If something jumps here with 64-bit values
6867 // then promote those registers to 64 bits
6870 uint64_t temp_is32=is32;
6873 if(ba[j]==start+i*4)
6874 //temp_is32&=branch_regs[j].is32;
6879 if(ba[j]==start+i*4)
6890 if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
6891 // Branches don't write registers, consider the delay slot instead.
6902 if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
6903 opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
6912 if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
6913 if(op==0x22) is32|=1LL<<rt; // LWL
6916 if (op==0x08||op==0x09|| // ADDI/ADDIU
6917 op==0x0a||op==0x0b|| // SLTI/SLTIU
6923 if(op==0x18||op==0x19) { // DADDI/DADDIU
6926 // is32|=((is32>>s1)&1LL)<<rt;
6928 if(op==0x0d||op==0x0e) { // ORI/XORI
6929 uint64_t sr=((is32>>s1)&1LL);
6945 if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
6948 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
6951 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
6952 uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
6956 else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
6961 uint64_t sr=((is32>>s1)&1LL);
6966 uint64_t sr=((is32>>s2)&1LL);
6974 else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
6979 uint64_t sr=((is32>>s1)&1LL);
6989 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
6990 is32&=~((1LL<<HIREG)|(1LL<<LOREG));
6993 is32|=(1LL<<HIREG)|(1LL<<LOREG);
6998 uint64_t sr=((is32>>s1)&1LL);
7004 if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
7005 else is32|=1LL<<rt; // SLLV/SRLV/SRAV
7009 // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
7010 if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
7013 if(op2==0) is32|=1LL<<rt; // MFC0
7017 if(op2==0) is32|=1LL<<rt; // MFC1
7018 if(op2==1) is32&=~(1LL<<rt); // DMFC1
7019 if(op2==2) is32|=1LL<<rt; // CFC1
7041 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
7043 if(rt1[i-1]==31) // JAL/JALR
7045 // Subroutine call will return here, don't alloc any registers
7050 // Internal branch will jump here, match registers to caller
7058 // Identify registers which may be assumed to contain 32-bit values
7059 // and where optimizations will rely on this.
7060 // This is used to determine whether backward branches can safely
7061 // jump to a location with 64-bit values in registers.
7062 static void provisional_r32()
7067 for (i=slen-1;i>=0;i--)
7070 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7072 if(ba[i]<start || ba[i]>=(start+slen*4))
7074 // Branch out of this block, don't need anything
7080 // Need whatever matches the target
7081 // (and doesn't get overwritten by the delay slot instruction)
7083 int t=(ba[i]-start)>>2;
7084 if(ba[i]>start+i*4) {
7086 //if(!(requires_32bit[t]&~regs[i].was32))
7087 // r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7088 if(!(pr32[t]&~regs[i].was32))
7089 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7092 if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
7093 r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7096 // Conditional branch may need registers for following instructions
7097 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7100 //r32|=requires_32bit[i+2];
7103 // Mark this address as a branch target since it may be called
7104 // upon return from interrupt
7108 // Merge in delay slot
7110 // These are overwritten unless the branch is "likely"
7111 // and the delay slot is nullified if not taken
7112 r32&=~(1LL<<rt1[i+1]);
7113 r32&=~(1LL<<rt2[i+1]);
7115 // Assume these are needed (delay slot)
7118 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7122 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7124 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7126 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7128 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7130 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7133 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7135 // SYSCALL instruction (software interrupt)
7138 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7140 // ERET instruction (return from interrupt)
7144 r32&=~(1LL<<rt1[i]);
7145 r32&=~(1LL<<rt2[i]);
7148 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7152 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7154 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7156 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7158 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7160 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7162 //requires_32bit[i]=r32;
7165 // Dirty registers which are 32-bit, require 32-bit input
7166 // as they will be written as 32-bit values
7167 for(hr=0;hr<HOST_REGS;hr++)
7169 if(regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64) {
7170 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7171 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7172 pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7173 //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7180 // Write back dirty registers as soon as we will no longer modify them,
7181 // so that we don't end up with lots of writes at the branches.
7182 void clean_registers(int istart,int iend,int wr)
7186 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7187 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7189 will_dirty_i=will_dirty_next=0;
7190 wont_dirty_i=wont_dirty_next=0;
7192 will_dirty_i=will_dirty_next=will_dirty[iend+1];
7193 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7195 for (i=iend;i>=istart;i--)
7197 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7199 if(ba[i]<start || ba[i]>=(start+slen*4))
7201 // Branch out of this block, flush all regs
7202 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7204 // Unconditional branch
7207 // Merge in delay slot (will dirty)
7208 for(r=0;r<HOST_REGS;r++) {
7209 if(r!=EXCLUDE_REG) {
7210 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7211 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7212 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7213 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7214 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7215 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7216 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7217 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7218 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7219 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7220 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7221 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7222 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7223 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7229 // Conditional branch
7231 wont_dirty_i=wont_dirty_next;
7232 // Merge in delay slot (will dirty)
7233 for(r=0;r<HOST_REGS;r++) {
7234 if(r!=EXCLUDE_REG) {
7236 // Might not dirty if likely branch is not taken
7237 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7238 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7239 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7240 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7241 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7242 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7243 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7244 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7245 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7246 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7247 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7248 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7249 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7250 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7255 // Merge in delay slot (wont dirty)
7256 for(r=0;r<HOST_REGS;r++) {
7257 if(r!=EXCLUDE_REG) {
7258 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7259 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7260 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7261 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7262 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7263 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7264 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7265 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7266 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7267 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7271 #ifndef DESTRUCTIVE_WRITEBACK
7272 branch_regs[i].dirty&=wont_dirty_i;
7274 branch_regs[i].dirty|=will_dirty_i;
7280 if(ba[i]<=start+i*4) {
7282 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7284 // Unconditional branch
7287 // Merge in delay slot (will dirty)
7288 for(r=0;r<HOST_REGS;r++) {
7289 if(r!=EXCLUDE_REG) {
7290 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7291 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7292 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7293 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7294 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7295 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7296 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7297 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7298 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7299 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7300 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7301 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7302 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7303 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7307 // Conditional branch (not taken case)
7308 temp_will_dirty=will_dirty_next;
7309 temp_wont_dirty=wont_dirty_next;
7310 // Merge in delay slot (will dirty)
7311 for(r=0;r<HOST_REGS;r++) {
7312 if(r!=EXCLUDE_REG) {
7314 // Will not dirty if likely branch is not taken
7315 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7316 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7317 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7318 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7319 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7320 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7321 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7322 //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7323 //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7324 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7325 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7326 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7327 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7328 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7333 // Merge in delay slot (wont dirty)
7334 for(r=0;r<HOST_REGS;r++) {
7335 if(r!=EXCLUDE_REG) {
7336 if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7337 if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7338 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7339 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7340 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7341 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7342 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7343 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7344 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7345 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7348 // Deal with changed mappings
7350 for(r=0;r<HOST_REGS;r++) {
7351 if(r!=EXCLUDE_REG) {
7352 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7353 temp_will_dirty&=~(1<<r);
7354 temp_wont_dirty&=~(1<<r);
7355 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7356 temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7357 temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7359 temp_will_dirty|=1<<r;
7360 temp_wont_dirty|=1<<r;
7367 will_dirty[i]=temp_will_dirty;
7368 wont_dirty[i]=temp_wont_dirty;
7369 clean_registers((ba[i]-start)>>2,i-1,0);
7371 // Limit recursion. It can take an excessive amount
7372 // of time if there are a lot of nested loops.
7373 will_dirty[(ba[i]-start)>>2]=0;
7374 wont_dirty[(ba[i]-start)>>2]=-1;
7379 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7381 // Unconditional branch
7384 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7385 for(r=0;r<HOST_REGS;r++) {
7386 if(r!=EXCLUDE_REG) {
7387 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7388 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7389 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7394 // Merge in delay slot
7395 for(r=0;r<HOST_REGS;r++) {
7396 if(r!=EXCLUDE_REG) {
7397 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7398 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7399 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7400 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7401 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7402 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7403 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7404 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7405 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7406 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7407 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7408 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7409 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7410 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7414 // Conditional branch
7415 will_dirty_i=will_dirty_next;
7416 wont_dirty_i=wont_dirty_next;
7417 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7418 for(r=0;r<HOST_REGS;r++) {
7419 if(r!=EXCLUDE_REG) {
7420 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7421 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7422 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7426 will_dirty_i&=~(1<<r);
7428 // Treat delay slot as part of branch too
7429 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7430 will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7431 wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7435 will_dirty[i+1]&=~(1<<r);
7440 // Merge in delay slot
7441 for(r=0;r<HOST_REGS;r++) {
7442 if(r!=EXCLUDE_REG) {
7444 // Might not dirty if likely branch is not taken
7445 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7446 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7447 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7448 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7449 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7450 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7451 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7452 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7453 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7454 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7455 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7456 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7457 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7458 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7463 // Merge in delay slot
7464 for(r=0;r<HOST_REGS;r++) {
7465 if(r!=EXCLUDE_REG) {
7466 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7467 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7468 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7469 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7470 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7471 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7472 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7473 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7474 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7475 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7479 #ifndef DESTRUCTIVE_WRITEBACK
7480 branch_regs[i].dirty&=wont_dirty_i;
7482 branch_regs[i].dirty|=will_dirty_i;
7487 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7489 // SYSCALL instruction (software interrupt)
7493 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7495 // ERET instruction (return from interrupt)
7499 will_dirty_next=will_dirty_i;
7500 wont_dirty_next=wont_dirty_i;
7501 for(r=0;r<HOST_REGS;r++) {
7502 if(r!=EXCLUDE_REG) {
7503 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7504 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7505 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7506 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7507 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7508 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7509 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7510 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7512 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7514 // Don't store a register immediately after writing it,
7515 // may prevent dual-issue.
7516 if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7517 if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7523 will_dirty[i]=will_dirty_i;
7524 wont_dirty[i]=wont_dirty_i;
7525 // Mark registers that won't be dirtied as not dirty
7527 /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7528 for(r=0;r<HOST_REGS;r++) {
7529 if((will_dirty_i>>r)&1) {
7535 //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7536 regs[i].dirty|=will_dirty_i;
7537 #ifndef DESTRUCTIVE_WRITEBACK
7538 regs[i].dirty&=wont_dirty_i;
7539 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7541 if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7542 for(r=0;r<HOST_REGS;r++) {
7543 if(r!=EXCLUDE_REG) {
7544 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7545 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7546 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7554 for(r=0;r<HOST_REGS;r++) {
7555 if(r!=EXCLUDE_REG) {
7556 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7557 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7558 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7566 // Deal with changed mappings
7567 temp_will_dirty=will_dirty_i;
7568 temp_wont_dirty=wont_dirty_i;
7569 for(r=0;r<HOST_REGS;r++) {
7570 if(r!=EXCLUDE_REG) {
7572 if(regs[i].regmap[r]==regmap_pre[i][r]) {
7574 #ifndef DESTRUCTIVE_WRITEBACK
7575 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7577 regs[i].wasdirty|=will_dirty_i&(1<<r);
7580 else if((nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7581 // Register moved to a different register
7582 will_dirty_i&=~(1<<r);
7583 wont_dirty_i&=~(1<<r);
7584 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7585 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7587 #ifndef DESTRUCTIVE_WRITEBACK
7588 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7590 regs[i].wasdirty|=will_dirty_i&(1<<r);
7594 will_dirty_i&=~(1<<r);
7595 wont_dirty_i&=~(1<<r);
7596 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7597 will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7598 wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7601 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7610 void disassemble_inst(int i)
7612 if (bt[i]) printf("*"); else printf(" ");
7615 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7617 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7619 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7621 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7623 if (opcode[i]==0x9&&rt1[i]!=31)
7624 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7626 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7629 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7631 if(opcode[i]==0xf) //LUI
7632 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7634 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7638 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7642 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7646 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7649 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7652 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7655 if((opcode2[i]&0x1d)==0x10)
7656 printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7657 else if((opcode2[i]&0x1d)==0x11)
7658 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7660 printf (" %x: %s\n",start+i*4,insn[i]);
7664 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7665 else if(opcode2[i]==4)
7666 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7667 else printf (" %x: %s\n",start+i*4,insn[i]);
7671 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7672 else if(opcode2[i]>3)
7673 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7674 else printf (" %x: %s\n",start+i*4,insn[i]);
7678 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7679 else if(opcode2[i]>3)
7680 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7681 else printf (" %x: %s\n",start+i*4,insn[i]);
7684 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7687 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7690 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
7693 //printf (" %s %8x\n",insn[i],source[i]);
7694 printf (" %x: %s\n",start+i*4,insn[i]);
7698 void new_dynarec_init()
7700 printf("Init new dynarec\n");
7701 out=(u_char *)BASE_ADDR;
7702 if (mmap (out, 1<<TARGET_SIZE_2,
7703 PROT_READ | PROT_WRITE | PROT_EXEC,
7704 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
7705 -1, 0) <= 0) {printf("mmap() failed\n");}
7707 rdword=&readmem_dword;
7708 fake_pc.f.r.rs=&readmem_dword;
7709 fake_pc.f.r.rt=&readmem_dword;
7710 fake_pc.f.r.rd=&readmem_dword;
7713 for(n=0x80000;n<0x80800;n++)
7715 for(n=0;n<65536;n++)
7716 hash_table[n][0]=hash_table[n][2]=-1;
7717 memset(mini_ht,-1,sizeof(mini_ht));
7718 memset(restore_candidate,0,sizeof(restore_candidate));
7720 expirep=16384; // Expiry pointer, +2 blocks
7721 pending_exception=0;
7724 // Copy this into local area so we don't have to put it in every literal pool
7725 invc_ptr=invalid_code;
7730 for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7732 for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7733 memory_map[n]=((u_int)rdram-0x80000000)>>2;
7734 for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7737 for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
7738 writemem[n] = write_nomem_new;
7739 writememb[n] = write_nomemb_new;
7740 writememh[n] = write_nomemh_new;
7742 writememd[n] = write_nomemd_new;
7744 readmem[n] = read_nomem_new;
7745 readmemb[n] = read_nomemb_new;
7746 readmemh[n] = read_nomemh_new;
7748 readmemd[n] = read_nomemd_new;
7751 for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
7752 writemem[n] = write_rdram_new;
7753 writememb[n] = write_rdramb_new;
7754 writememh[n] = write_rdramh_new;
7756 writememd[n] = write_rdramd_new;
7759 for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
7760 writemem[n] = write_nomem_new;
7761 writememb[n] = write_nomemb_new;
7762 writememh[n] = write_nomemh_new;
7764 writememd[n] = write_nomemd_new;
7766 readmem[n] = read_nomem_new;
7767 readmemb[n] = read_nomemb_new;
7768 readmemh[n] = read_nomemh_new;
7770 readmemd[n] = read_nomemd_new;
7778 void new_dynarec_cleanup()
7781 if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
7782 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7783 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7784 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7786 if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
7790 int new_recompile_block(int addr)
7793 if(addr==0x800cd050) {
7795 for(block=0x80000;block<0x80800;block++) invalidate_block(block);
7797 for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
7800 //if(Count==365117028) tracedebug=1;
7801 assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7802 //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7803 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
7805 //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
7806 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
7807 /*if(Count>=312978186) {
7811 start = (u_int)addr&~3;
7812 //assert(((u_int)addr&1)==0);
7814 if (Config.HLE && start == 0x80001000) // hlecall
7816 // XXX: is this enough? Maybe check hleSoftCall?
7817 u_int beginning=(u_int)out;
7818 u_int page=get_page(start);
7819 invalid_code[start>>12]=0;
7820 emit_movimm(start,0);
7821 emit_writeword(0,(int)&pcaddr);
7822 emit_jmp((int)new_dyna_leave);
7824 __clear_cache((void *)beginning,out);
7826 ll_add(jump_in+page,start,(void *)beginning);
7829 else if ((u_int)addr < 0x00200000 ||
7830 (0xa0000000 <= addr && addr < 0xa0200000)) {
7831 // used for BIOS calls mostly?
7832 source = (u_int *)((u_int)rdram+(start&0x1fffff));
7833 pagelimit = (addr&0xa0000000)|0x00200000;
7835 else if (!Config.HLE && (
7836 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
7837 (0xbfc00000 <= addr && addr < 0xbfc80000))) {
7839 source = (u_int *)((u_int)psxR+(start&0x7ffff));
7840 pagelimit = (addr&0xfff00000)|0x80000;
7845 if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
7846 source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
7847 pagelimit = 0xa4001000;
7851 if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
7852 source = (u_int *)((u_int)rdram+start-0x80000000);
7853 pagelimit = 0x80000000+RAM_SIZE;
7856 else if ((signed int)addr >= (signed int)0xC0000000) {
7857 //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
7858 //if(tlb_LUT_r[start>>12])
7859 //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
7860 if((signed int)memory_map[start>>12]>=0) {
7861 source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
7862 pagelimit=(start+4096)&0xFFFFF000;
7863 int map=memory_map[start>>12];
7866 //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
7867 if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
7869 assem_debug("pagelimit=%x\n",pagelimit);
7870 assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
7873 assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
7874 //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
7875 return -1; // Caller will invoke exception handler
7877 //printf("source= %x\n",(int)source);
7881 printf("Compile at bogus memory address: %x \n", (int)addr);
7885 /* Pass 1: disassemble */
7886 /* Pass 2: register dependencies, branch targets */
7887 /* Pass 3: register allocation */
7888 /* Pass 4: branch dependencies */
7889 /* Pass 5: pre-alloc */
7890 /* Pass 6: optimize clean/dirty state */
7891 /* Pass 7: flag 32-bit registers */
7892 /* Pass 8: assembly */
7893 /* Pass 9: linker */
7894 /* Pass 10: garbage collection / free memory */
7898 unsigned int type,op,op2;
7900 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
7902 /* Pass 1 disassembly */
7904 for(i=0;!done;i++) {
7905 bt[i]=0;likely[i]=0;ooo[i]=0;op2=0;
7906 minimum_free_regs[i]=0;
7907 opcode[i]=op=source[i]>>26;
7910 case 0x00: strcpy(insn[i],"special"); type=NI;
7914 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
7915 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
7916 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
7917 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
7918 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
7919 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
7920 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
7921 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
7922 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
7923 case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
7924 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
7925 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
7926 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
7927 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
7928 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
7929 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
7930 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
7931 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
7932 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
7933 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
7934 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
7935 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
7936 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
7937 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
7938 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
7939 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
7940 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
7941 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
7942 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
7943 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
7944 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
7945 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
7946 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
7947 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
7948 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
7949 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
7950 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
7951 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
7952 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
7953 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
7954 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
7955 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
7956 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
7957 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
7958 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
7959 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
7960 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
7961 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
7962 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
7963 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
7964 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
7965 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
7968 case 0x01: strcpy(insn[i],"regimm"); type=NI;
7969 op2=(source[i]>>16)&0x1f;
7972 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
7973 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
7974 case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
7975 case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
7976 case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
7977 case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
7978 case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
7979 case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
7980 case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
7981 case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
7982 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
7983 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
7984 case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
7985 case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
7988 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
7989 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
7990 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
7991 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
7992 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
7993 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
7994 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
7995 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
7996 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
7997 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
7998 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
7999 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
8000 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
8001 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
8002 case 0x10: strcpy(insn[i],"cop0"); type=NI;
8003 op2=(source[i]>>21)&0x1f;
8006 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
8007 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
8008 case 0x10: strcpy(insn[i],"tlb"); type=NI;
8009 switch(source[i]&0x3f)
8011 case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
8012 case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
8013 case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
8014 case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
8016 case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
8018 case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
8023 case 0x11: strcpy(insn[i],"cop1"); type=NI;
8024 op2=(source[i]>>21)&0x1f;
8027 case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
8028 case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
8029 case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
8030 case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
8031 case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
8032 case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
8033 case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
8034 switch((source[i]>>16)&0x3)
8036 case 0x00: strcpy(insn[i],"BC1F"); break;
8037 case 0x01: strcpy(insn[i],"BC1T"); break;
8038 case 0x02: strcpy(insn[i],"BC1FL"); break;
8039 case 0x03: strcpy(insn[i],"BC1TL"); break;
8042 case 0x10: strcpy(insn[i],"C1.S"); type=NI;
8043 switch(source[i]&0x3f)
8045 case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
8046 case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
8047 case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
8048 case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
8049 case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
8050 case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
8051 case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
8052 case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
8053 case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
8054 case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
8055 case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
8056 case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
8057 case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
8058 case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
8059 case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
8060 case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
8061 case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
8062 case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
8063 case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
8064 case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
8065 case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
8066 case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
8067 case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
8068 case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
8069 case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
8070 case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
8071 case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
8072 case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
8073 case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
8074 case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
8075 case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
8076 case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
8077 case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
8078 case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
8079 case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
8082 case 0x11: strcpy(insn[i],"C1.D"); type=NI;
8083 switch(source[i]&0x3f)
8085 case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
8086 case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
8087 case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
8088 case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
8089 case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
8090 case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
8091 case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
8092 case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
8093 case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
8094 case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
8095 case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
8096 case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
8097 case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
8098 case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
8099 case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
8100 case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
8101 case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
8102 case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
8103 case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
8104 case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
8105 case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
8106 case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
8107 case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
8108 case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
8109 case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
8110 case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
8111 case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
8112 case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
8113 case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
8114 case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
8115 case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8116 case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8117 case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8118 case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8119 case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8122 case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8123 switch(source[i]&0x3f)
8125 case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8126 case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8129 case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8130 switch(source[i]&0x3f)
8132 case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8133 case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8139 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8140 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8141 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8142 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8143 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8144 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8145 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8146 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
8148 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8149 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8150 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8151 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8152 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8153 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8154 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
8155 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
8156 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8157 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8158 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8159 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
8161 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8162 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
8164 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8165 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8166 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8167 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
8169 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8170 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8171 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
8173 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8174 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
8176 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8177 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8178 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
8181 case 0x12: strcpy(insn[i],"COP2"); type=NI;
8182 // note: COP MIPS-1 encoding differs from MIPS32
8183 op2=(source[i]>>21)&0x1f;
8184 if (source[i]&0x3f) {
8185 if (gte_handlers[source[i]&0x3f]!=NULL) {
8186 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8192 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8193 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8194 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8195 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
8198 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8199 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8200 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8202 default: strcpy(insn[i],"???"); type=NI;
8203 printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
8207 /* detect branch in delay slot early */
8208 if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
8209 opcode[i+1]=source[i+1]>>26;
8210 opcode2[i+1]=source[i+1]&0x3f;
8211 if((0<opcode[i+1]&&opcode[i+1]<8)||(opcode[i+1]==0&&(opcode2[i+1]==8||opcode2[i+1]==9))) {
8212 printf("branch in delay slot @%08x (%08x)\n", addr + i*4+4, addr);
8213 // don't handle first branch and call interpreter if it's hit
8220 /* Get registers/immediates */
8228 rs1[i]=(source[i]>>21)&0x1f;
8230 rt1[i]=(source[i]>>16)&0x1f;
8232 imm[i]=(short)source[i];
8236 rs1[i]=(source[i]>>21)&0x1f;
8237 rs2[i]=(source[i]>>16)&0x1f;
8240 imm[i]=(short)source[i];
8241 if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8244 // LWL/LWR only load part of the register,
8245 // therefore the target register must be treated as a source too
8246 rs1[i]=(source[i]>>21)&0x1f;
8247 rs2[i]=(source[i]>>16)&0x1f;
8248 rt1[i]=(source[i]>>16)&0x1f;
8250 imm[i]=(short)source[i];
8251 if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8252 if(op==0x26) dep1[i]=rt1[i]; // LWR
8255 if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8256 else rs1[i]=(source[i]>>21)&0x1f;
8258 rt1[i]=(source[i]>>16)&0x1f;
8260 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8261 imm[i]=(unsigned short)source[i];
8263 imm[i]=(short)source[i];
8265 if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8266 if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8267 if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8274 // The JAL instruction writes to r31.
8281 rs1[i]=(source[i]>>21)&0x1f;
8285 // The JALR instruction writes to rd.
8287 rt1[i]=(source[i]>>11)&0x1f;
8292 rs1[i]=(source[i]>>21)&0x1f;
8293 rs2[i]=(source[i]>>16)&0x1f;
8296 if(op&2) { // BGTZ/BLEZ
8304 rs1[i]=(source[i]>>21)&0x1f;
8309 if(op2&0x10) { // BxxAL
8311 // NOTE: If the branch is not taken, r31 is still overwritten
8313 likely[i]=(op2&2)>>1;
8320 likely[i]=((source[i])>>17)&1;
8323 rs1[i]=(source[i]>>21)&0x1f; // source
8324 rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8325 rt1[i]=(source[i]>>11)&0x1f; // destination
8327 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8328 us1[i]=rs1[i];us2[i]=rs2[i];
8330 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8331 dep1[i]=rs1[i];dep2[i]=rs2[i];
8333 else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8334 dep1[i]=rs1[i];dep2[i]=rs2[i];
8338 rs1[i]=(source[i]>>21)&0x1f; // source
8339 rs2[i]=(source[i]>>16)&0x1f; // divisor
8342 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8343 us1[i]=rs1[i];us2[i]=rs2[i];
8351 if(op2==0x10) rs1[i]=HIREG; // MFHI
8352 if(op2==0x11) rt1[i]=HIREG; // MTHI
8353 if(op2==0x12) rs1[i]=LOREG; // MFLO
8354 if(op2==0x13) rt1[i]=LOREG; // MTLO
8355 if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8356 if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8360 rs1[i]=(source[i]>>16)&0x1f; // target of shift
8361 rs2[i]=(source[i]>>21)&0x1f; // shift amount
8362 rt1[i]=(source[i]>>11)&0x1f; // destination
8364 // DSLLV/DSRLV/DSRAV are 64-bit
8365 if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8368 rs1[i]=(source[i]>>16)&0x1f;
8370 rt1[i]=(source[i]>>11)&0x1f;
8372 imm[i]=(source[i]>>6)&0x1f;
8373 // DSxx32 instructions
8374 if(op2>=0x3c) imm[i]|=0x20;
8375 // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8376 if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8383 if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8384 if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8385 if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8386 if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8394 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8395 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8396 if(op2==5) us1[i]=rs1[i]; // DMTC1
8400 rs1[i]=(source[i]>>21)&0x1F;
8404 imm[i]=(short)source[i];
8407 rs1[i]=(source[i]>>21)&0x1F;
8411 imm[i]=(short)source[i];
8440 /* Calculate branch target addresses */
8442 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8443 else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8444 ba[i]=start+i*4+8; // Ignore never taken branch
8445 else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8446 ba[i]=start+i*4+8; // Ignore never taken branch
8447 else if(type==CJUMP||type==SJUMP||type==FJUMP)
8448 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8450 /* Is this the end of the block? */
8451 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
8453 // check for link register access in delay slot
8455 if(rt1_!=0&&(rs1[i]==rt1_||rs2[i]==rt1_||rt1[i]==rt1_||rt2[i]==rt1_)) {
8456 printf("link access in delay slot @%08x (%08x)\n", addr + i*4, addr);
8463 if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
8467 if(stop_after_jal) done=1;
8469 if((source[i+1]&0xfc00003f)==0x0d) done=1;
8471 // Don't recompile stuff that's already compiled
8472 if(check_addr(start+i*4+4)) done=1;
8473 // Don't get too close to the limit
8474 if(i>MAXBLOCK/2) done=1;
8476 if(itype[i]==SYSCALL&&stop_after_jal) done=1;
8477 if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
8479 // Does the block continue due to a branch?
8482 if(ba[j]==start+i*4+4) done=j=0;
8483 if(ba[j]==start+i*4+8) done=j=0;
8486 //assert(i<MAXBLOCK-1);
8487 if(start+i*4==pagelimit-4) done=1;
8488 assert(start+i*4<pagelimit);
8489 if (i==MAXBLOCK-1) done=1;
8490 // Stop if we're compiling junk
8491 if(itype[i]==NI&&opcode[i]==0x11) {
8492 done=stop_after_jal=1;
8493 printf("Disabled speculative precompilation\n");
8497 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8498 if(start+i*4==pagelimit) {
8504 /* Pass 2 - Register dependencies and branch targets */
8506 unneeded_registers(0,slen-1,0);
8508 /* Pass 3 - Register allocation */
8510 struct regstat current; // Current register allocations/status
8513 current.u=unneeded_reg[0];
8514 current.uu=unneeded_reg_upper[0];
8515 clear_all_regs(current.regmap);
8516 alloc_reg(¤t,0,CCREG);
8517 dirty_reg(¤t,CCREG);
8525 provisional_32bit();
8528 // First instruction is delay slot
8533 unneeded_reg_upper[0]=1;
8534 current.regmap[HOST_BTREG]=BTREG;
8542 for(hr=0;hr<HOST_REGS;hr++)
8544 // Is this really necessary?
8545 if(current.regmap[hr]==0) current.regmap[hr]=-1;
8551 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8553 if(rs1[i-2]==0||rs2[i-2]==0)
8556 current.is32|=1LL<<rs1[i-2];
8557 int hr=get_reg(current.regmap,rs1[i-2]|64);
8558 if(hr>=0) current.regmap[hr]=-1;
8561 current.is32|=1LL<<rs2[i-2];
8562 int hr=get_reg(current.regmap,rs2[i-2]|64);
8563 if(hr>=0) current.regmap[hr]=-1;
8569 // If something jumps here with 64-bit values
8570 // then promote those registers to 64 bits
8573 uint64_t temp_is32=current.is32;
8576 if(ba[j]==start+i*4)
8577 temp_is32&=branch_regs[j].is32;
8581 if(ba[j]==start+i*4)
8585 if(temp_is32!=current.is32) {
8586 //printf("dumping 32-bit regs (%x)\n",start+i*4);
8587 #ifdef DESTRUCTIVE_WRITEBACK
8588 for(hr=0;hr<HOST_REGS;hr++)
8590 int r=current.regmap[hr];
8593 if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8595 //printf("restore %d\n",r);
8600 current.is32=temp_is32;
8607 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8608 regs[i].wasconst=current.isconst;
8609 regs[i].was32=current.is32;
8610 regs[i].wasdirty=current.dirty;
8611 #if defined(DESTRUCTIVE_WRITEBACK) && !defined(FORCE32)
8612 // To change a dirty register from 32 to 64 bits, we must write
8613 // it out during the previous cycle (for branches, 2 cycles)
8614 if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8616 uint64_t temp_is32=current.is32;
8619 if(ba[j]==start+i*4+4)
8620 temp_is32&=branch_regs[j].is32;
8624 if(ba[j]==start+i*4+4)
8628 if(temp_is32!=current.is32) {
8629 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8630 for(hr=0;hr<HOST_REGS;hr++)
8632 int r=current.regmap[hr];
8635 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8636 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
8638 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
8640 //printf("dump %d/r%d\n",hr,r);
8641 current.regmap[hr]=-1;
8642 if(get_reg(current.regmap,r|64)>=0)
8643 current.regmap[get_reg(current.regmap,r|64)]=-1;
8651 else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
8653 uint64_t temp_is32=current.is32;
8656 if(ba[j]==start+i*4+8)
8657 temp_is32&=branch_regs[j].is32;
8661 if(ba[j]==start+i*4+8)
8665 if(temp_is32!=current.is32) {
8666 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8667 for(hr=0;hr<HOST_REGS;hr++)
8669 int r=current.regmap[hr];
8672 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8673 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
8675 //printf("dump %d/r%d\n",hr,r);
8676 current.regmap[hr]=-1;
8677 if(get_reg(current.regmap,r|64)>=0)
8678 current.regmap[get_reg(current.regmap,r|64)]=-1;
8686 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8688 current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8689 current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8690 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8699 current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
8700 current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8701 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8702 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8703 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8706 } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
8710 ds=0; // Skip delay slot, already allocated as part of branch
8711 // ...but we need to alloc it in case something jumps here
8713 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
8714 current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
8716 current.u=branch_unneeded_reg[i-1];
8717 current.uu=branch_unneeded_reg_upper[i-1];
8719 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8720 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8721 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8724 struct regstat temp;
8725 memcpy(&temp,¤t,sizeof(current));
8726 temp.wasdirty=temp.dirty;
8727 temp.was32=temp.is32;
8728 // TODO: Take into account unconditional branches, as below
8729 delayslot_alloc(&temp,i);
8730 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
8731 regs[i].wasdirty=temp.wasdirty;
8732 regs[i].was32=temp.was32;
8733 regs[i].dirty=temp.dirty;
8734 regs[i].is32=temp.is32;
8738 // Create entry (branch target) regmap
8739 for(hr=0;hr<HOST_REGS;hr++)
8741 int r=temp.regmap[hr];
8743 if(r!=regmap_pre[i][hr]) {
8744 regs[i].regmap_entry[hr]=-1;
8749 if((current.u>>r)&1) {
8750 regs[i].regmap_entry[hr]=-1;
8751 regs[i].regmap[hr]=-1;
8752 //Don't clear regs in the delay slot as the branch might need them
8753 //current.regmap[hr]=-1;
8755 regs[i].regmap_entry[hr]=r;
8758 if((current.uu>>(r&63))&1) {
8759 regs[i].regmap_entry[hr]=-1;
8760 regs[i].regmap[hr]=-1;
8761 //Don't clear regs in the delay slot as the branch might need them
8762 //current.regmap[hr]=-1;
8764 regs[i].regmap_entry[hr]=r;
8768 // First instruction expects CCREG to be allocated
8769 if(i==0&&hr==HOST_CCREG)
8770 regs[i].regmap_entry[hr]=CCREG;
8772 regs[i].regmap_entry[hr]=-1;
8776 else { // Not delay slot
8779 //current.isconst=0; // DEBUG
8780 //current.wasconst=0; // DEBUG
8781 //regs[i].wasconst=0; // DEBUG
8782 clear_const(¤t,rt1[i]);
8783 alloc_cc(¤t,i);
8784 dirty_reg(¤t,CCREG);
8786 alloc_reg(¤t,i,31);
8787 dirty_reg(¤t,31);
8788 assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8789 assert(rt1[i+1]!=rt1[i]);
8791 alloc_reg(¤t,i,PTEMP);
8793 //current.is32|=1LL<<rt1[i];
8796 delayslot_alloc(¤t,i+1);
8797 //current.isconst=0; // DEBUG
8799 //printf("i=%d, isconst=%x\n",i,current.isconst);
8802 //current.isconst=0;
8803 //current.wasconst=0;
8804 //regs[i].wasconst=0;
8805 clear_const(¤t,rs1[i]);
8806 clear_const(¤t,rt1[i]);
8807 alloc_cc(¤t,i);
8808 dirty_reg(¤t,CCREG);
8809 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
8810 alloc_reg(¤t,i,rs1[i]);
8812 alloc_reg(¤t,i,rt1[i]);
8813 dirty_reg(¤t,rt1[i]);
8814 assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
8815 assert(rt1[i+1]!=rt1[i]);
8817 alloc_reg(¤t,i,PTEMP);
8821 if(rs1[i]==31) { // JALR
8822 alloc_reg(¤t,i,RHASH);
8823 #ifndef HOST_IMM_ADDR32
8824 alloc_reg(¤t,i,RHTBL);
8828 delayslot_alloc(¤t,i+1);
8830 // The delay slot overwrites our source register,
8831 // allocate a temporary register to hold the old value.
8835 delayslot_alloc(¤t,i+1);
8837 alloc_reg(¤t,i,RTEMP);
8839 //current.isconst=0; // DEBUG
8844 //current.isconst=0;
8845 //current.wasconst=0;
8846 //regs[i].wasconst=0;
8847 clear_const(¤t,rs1[i]);
8848 clear_const(¤t,rs2[i]);
8849 if((opcode[i]&0x3E)==4) // BEQ/BNE
8851 alloc_cc(¤t,i);
8852 dirty_reg(¤t,CCREG);
8853 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
8854 if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
8855 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8857 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
8858 if(rs2[i]) alloc_reg64(¤t,i,rs2[i]);
8860 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
8861 (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
8862 // The delay slot overwrites one of our conditions.
8863 // Allocate the branch condition registers instead.
8867 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
8868 if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
8869 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8871 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
8872 if(rs2[i]) alloc_reg64(¤t,i,rs2[i]);
8878 delayslot_alloc(¤t,i+1);
8882 if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
8884 alloc_cc(¤t,i);
8885 dirty_reg(¤t,CCREG);
8886 alloc_reg(¤t,i,rs1[i]);
8887 if(!(current.is32>>rs1[i]&1))
8889 alloc_reg64(¤t,i,rs1[i]);
8891 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
8892 // The delay slot overwrites one of our conditions.
8893 // Allocate the branch condition registers instead.
8897 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
8898 if(!((current.is32>>rs1[i])&1))
8900 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
8906 delayslot_alloc(¤t,i+1);
8910 // Don't alloc the delay slot yet because we might not execute it
8911 if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
8916 alloc_cc(¤t,i);
8917 dirty_reg(¤t,CCREG);
8918 alloc_reg(¤t,i,rs1[i]);
8919 alloc_reg(¤t,i,rs2[i]);
8920 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8922 alloc_reg64(¤t,i,rs1[i]);
8923 alloc_reg64(¤t,i,rs2[i]);
8927 if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
8932 alloc_cc(¤t,i);
8933 dirty_reg(¤t,CCREG);
8934 alloc_reg(¤t,i,rs1[i]);
8935 if(!(current.is32>>rs1[i]&1))
8937 alloc_reg64(¤t,i,rs1[i]);
8941 //current.isconst=0;
8944 //current.isconst=0;
8945 //current.wasconst=0;
8946 //regs[i].wasconst=0;
8947 clear_const(¤t,rs1[i]);
8948 clear_const(¤t,rt1[i]);
8949 //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
8950 if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
8952 alloc_cc(¤t,i);
8953 dirty_reg(¤t,CCREG);
8954 alloc_reg(¤t,i,rs1[i]);
8955 if(!(current.is32>>rs1[i]&1))
8957 alloc_reg64(¤t,i,rs1[i]);
8959 if (rt1[i]==31) { // BLTZAL/BGEZAL
8960 alloc_reg(¤t,i,31);
8961 dirty_reg(¤t,31);
8962 //#ifdef REG_PREFETCH
8963 //alloc_reg(¤t,i,PTEMP);
8965 //current.is32|=1LL<<rt1[i];
8967 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) // The delay slot overwrites the branch condition.
8968 ||(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))) { // DS touches $ra
8969 // Allocate the branch condition registers instead.
8973 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
8974 if(!((current.is32>>rs1[i])&1))
8976 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
8982 delayslot_alloc(¤t,i+1);
8986 // Don't alloc the delay slot yet because we might not execute it
8987 if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
8992 alloc_cc(¤t,i);
8993 dirty_reg(¤t,CCREG);
8994 alloc_reg(¤t,i,rs1[i]);
8995 if(!(current.is32>>rs1[i]&1))
8997 alloc_reg64(¤t,i,rs1[i]);
9001 //current.isconst=0;
9007 if(likely[i]==0) // BC1F/BC1T
9009 // TODO: Theoretically we can run out of registers here on x86.
9010 // The delay slot can allocate up to six, and we need to check
9011 // CSREG before executing the delay slot. Possibly we can drop
9012 // the cycle count and then reload it after checking that the
9013 // FPU is in a usable state, or don't do out-of-order execution.
9014 alloc_cc(¤t,i);
9015 dirty_reg(¤t,CCREG);
9016 alloc_reg(¤t,i,FSREG);
9017 alloc_reg(¤t,i,CSREG);
9018 if(itype[i+1]==FCOMP) {
9019 // The delay slot overwrites the branch condition.
9020 // Allocate the branch condition registers instead.
9021 alloc_cc(¤t,i);
9022 dirty_reg(¤t,CCREG);
9023 alloc_reg(¤t,i,CSREG);
9024 alloc_reg(¤t,i,FSREG);
9028 delayslot_alloc(¤t,i+1);
9029 alloc_reg(¤t,i+1,CSREG);
9033 // Don't alloc the delay slot yet because we might not execute it
9034 if(likely[i]) // BC1FL/BC1TL
9036 alloc_cc(¤t,i);
9037 dirty_reg(¤t,CCREG);
9038 alloc_reg(¤t,i,CSREG);
9039 alloc_reg(¤t,i,FSREG);
9045 imm16_alloc(¤t,i);
9049 load_alloc(¤t,i);
9053 store_alloc(¤t,i);
9056 alu_alloc(¤t,i);
9059 shift_alloc(¤t,i);
9062 multdiv_alloc(¤t,i);
9065 shiftimm_alloc(¤t,i);
9068 mov_alloc(¤t,i);
9071 cop0_alloc(¤t,i);
9075 cop1_alloc(¤t,i);
9078 c1ls_alloc(¤t,i);
9081 c2ls_alloc(¤t,i);
9084 c2op_alloc(¤t,i);
9087 fconv_alloc(¤t,i);
9090 float_alloc(¤t,i);
9093 fcomp_alloc(¤t,i);
9098 syscall_alloc(¤t,i);
9101 pagespan_alloc(¤t,i);
9105 // Drop the upper half of registers that have become 32-bit
9106 current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
9107 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9108 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9109 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9112 current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
9113 current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9114 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9115 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9119 // Create entry (branch target) regmap
9120 for(hr=0;hr<HOST_REGS;hr++)
9123 r=current.regmap[hr];
9125 if(r!=regmap_pre[i][hr]) {
9126 // TODO: delay slot (?)
9127 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9128 if(or<0||(r&63)>=TEMPREG){
9129 regs[i].regmap_entry[hr]=-1;
9133 // Just move it to a different register
9134 regs[i].regmap_entry[hr]=r;
9135 // If it was dirty before, it's still dirty
9136 if((regs[i].wasdirty>>or)&1) dirty_reg(¤t,r&63);
9143 regs[i].regmap_entry[hr]=0;
9147 if((current.u>>r)&1) {
9148 regs[i].regmap_entry[hr]=-1;
9149 //regs[i].regmap[hr]=-1;
9150 current.regmap[hr]=-1;
9152 regs[i].regmap_entry[hr]=r;
9155 if((current.uu>>(r&63))&1) {
9156 regs[i].regmap_entry[hr]=-1;
9157 //regs[i].regmap[hr]=-1;
9158 current.regmap[hr]=-1;
9160 regs[i].regmap_entry[hr]=r;
9164 // Branches expect CCREG to be allocated at the target
9165 if(regmap_pre[i][hr]==CCREG)
9166 regs[i].regmap_entry[hr]=CCREG;
9168 regs[i].regmap_entry[hr]=-1;
9171 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9173 /* Branch post-alloc */
9176 current.was32=current.is32;
9177 current.wasdirty=current.dirty;
9178 switch(itype[i-1]) {
9180 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9181 branch_regs[i-1].isconst=0;
9182 branch_regs[i-1].wasconst=0;
9183 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9184 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9185 alloc_cc(&branch_regs[i-1],i-1);
9186 dirty_reg(&branch_regs[i-1],CCREG);
9187 if(rt1[i-1]==31) { // JAL
9188 alloc_reg(&branch_regs[i-1],i-1,31);
9189 dirty_reg(&branch_regs[i-1],31);
9190 branch_regs[i-1].is32|=1LL<<31;
9192 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9193 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9196 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9197 branch_regs[i-1].isconst=0;
9198 branch_regs[i-1].wasconst=0;
9199 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9200 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9201 alloc_cc(&branch_regs[i-1],i-1);
9202 dirty_reg(&branch_regs[i-1],CCREG);
9203 alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
9204 if(rt1[i-1]!=0) { // JALR
9205 alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9206 dirty_reg(&branch_regs[i-1],rt1[i-1]);
9207 branch_regs[i-1].is32|=1LL<<rt1[i-1];
9210 if(rs1[i-1]==31) { // JALR
9211 alloc_reg(&branch_regs[i-1],i-1,RHASH);
9212 #ifndef HOST_IMM_ADDR32
9213 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9217 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9218 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9221 if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9223 alloc_cc(¤t,i-1);
9224 dirty_reg(¤t,CCREG);
9225 if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9226 (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9227 // The delay slot overwrote one of our conditions
9228 // Delay slot goes after the test (in order)
9229 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9230 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9231 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9234 delayslot_alloc(¤t,i);
9239 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9240 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9241 // Alloc the branch condition registers
9242 if(rs1[i-1]) alloc_reg(¤t,i-1,rs1[i-1]);
9243 if(rs2[i-1]) alloc_reg(¤t,i-1,rs2[i-1]);
9244 if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9246 if(rs1[i-1]) alloc_reg64(¤t,i-1,rs1[i-1]);
9247 if(rs2[i-1]) alloc_reg64(¤t,i-1,rs2[i-1]);
9250 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9251 branch_regs[i-1].isconst=0;
9252 branch_regs[i-1].wasconst=0;
9253 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9254 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9257 if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9259 alloc_cc(¤t,i-1);
9260 dirty_reg(¤t,CCREG);
9261 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9262 // The delay slot overwrote the branch condition
9263 // Delay slot goes after the test (in order)
9264 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9265 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9266 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9269 delayslot_alloc(¤t,i);
9274 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9275 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9276 // Alloc the branch condition register
9277 alloc_reg(¤t,i-1,rs1[i-1]);
9278 if(!(current.is32>>rs1[i-1]&1))
9280 alloc_reg64(¤t,i-1,rs1[i-1]);
9283 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9284 branch_regs[i-1].isconst=0;
9285 branch_regs[i-1].wasconst=0;
9286 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9287 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9290 // Alloc the delay slot in case the branch is taken
9291 if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9293 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9294 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9295 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9296 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9297 alloc_cc(&branch_regs[i-1],i);
9298 dirty_reg(&branch_regs[i-1],CCREG);
9299 delayslot_alloc(&branch_regs[i-1],i);
9300 branch_regs[i-1].isconst=0;
9301 alloc_reg(¤t,i,CCREG); // Not taken path
9302 dirty_reg(¤t,CCREG);
9303 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9306 if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9308 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9309 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9310 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9311 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9312 alloc_cc(&branch_regs[i-1],i);
9313 dirty_reg(&branch_regs[i-1],CCREG);
9314 delayslot_alloc(&branch_regs[i-1],i);
9315 branch_regs[i-1].isconst=0;
9316 alloc_reg(¤t,i,CCREG); // Not taken path
9317 dirty_reg(¤t,CCREG);
9318 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9322 //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9323 if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9325 alloc_cc(¤t,i-1);
9326 dirty_reg(¤t,CCREG);
9327 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9328 // The delay slot overwrote the branch condition
9329 // Delay slot goes after the test (in order)
9330 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9331 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9332 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9335 delayslot_alloc(¤t,i);
9340 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9341 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9342 // Alloc the branch condition register
9343 alloc_reg(¤t,i-1,rs1[i-1]);
9344 if(!(current.is32>>rs1[i-1]&1))
9346 alloc_reg64(¤t,i-1,rs1[i-1]);
9349 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9350 branch_regs[i-1].isconst=0;
9351 branch_regs[i-1].wasconst=0;
9352 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9353 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9356 // Alloc the delay slot in case the branch is taken
9357 if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9359 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9360 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9361 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9362 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9363 alloc_cc(&branch_regs[i-1],i);
9364 dirty_reg(&branch_regs[i-1],CCREG);
9365 delayslot_alloc(&branch_regs[i-1],i);
9366 branch_regs[i-1].isconst=0;
9367 alloc_reg(¤t,i,CCREG); // Not taken path
9368 dirty_reg(¤t,CCREG);
9369 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9371 // FIXME: BLTZAL/BGEZAL
9372 if(opcode2[i-1]&0x10) { // BxxZAL
9373 alloc_reg(&branch_regs[i-1],i-1,31);
9374 dirty_reg(&branch_regs[i-1],31);
9375 branch_regs[i-1].is32|=1LL<<31;
9379 if(likely[i-1]==0) // BC1F/BC1T
9381 alloc_cc(¤t,i-1);
9382 dirty_reg(¤t,CCREG);
9383 if(itype[i]==FCOMP) {
9384 // The delay slot overwrote the branch condition
9385 // Delay slot goes after the test (in order)
9386 delayslot_alloc(¤t,i);
9391 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9392 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9393 // Alloc the branch condition register
9394 alloc_reg(¤t,i-1,FSREG);
9396 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9397 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9401 // Alloc the delay slot in case the branch is taken
9402 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9403 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9404 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9405 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9406 alloc_cc(&branch_regs[i-1],i);
9407 dirty_reg(&branch_regs[i-1],CCREG);
9408 delayslot_alloc(&branch_regs[i-1],i);
9409 branch_regs[i-1].isconst=0;
9410 alloc_reg(¤t,i,CCREG); // Not taken path
9411 dirty_reg(¤t,CCREG);
9412 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9417 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9419 if(rt1[i-1]==31) // JAL/JALR
9421 // Subroutine call will return here, don't alloc any registers
9424 clear_all_regs(current.regmap);
9425 alloc_reg(¤t,i,CCREG);
9426 dirty_reg(¤t,CCREG);
9430 // Internal branch will jump here, match registers to caller
9431 current.is32=0x3FFFFFFFFLL;
9433 clear_all_regs(current.regmap);
9434 alloc_reg(¤t,i,CCREG);
9435 dirty_reg(¤t,CCREG);
9438 if(ba[j]==start+i*4+4) {
9439 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9440 current.is32=branch_regs[j].is32;
9441 current.dirty=branch_regs[j].dirty;
9446 if(ba[j]==start+i*4+4) {
9447 for(hr=0;hr<HOST_REGS;hr++) {
9448 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9449 current.regmap[hr]=-1;
9451 current.is32&=branch_regs[j].is32;
9452 current.dirty&=branch_regs[j].dirty;
9461 // Count cycles in between branches
9463 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
9472 flush_dirty_uppers(¤t);
9474 regs[i].is32=current.is32;
9475 regs[i].dirty=current.dirty;
9476 regs[i].isconst=current.isconst;
9477 memcpy(constmap[i],current.constmap,sizeof(current.constmap));
9479 for(hr=0;hr<HOST_REGS;hr++) {
9480 if(hr!=EXCLUDE_REG&®s[i].regmap[hr]>=0) {
9481 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9482 regs[i].wasconst&=~(1<<hr);
9486 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9489 /* Pass 4 - Cull unused host registers */
9493 for (i=slen-1;i>=0;i--)
9496 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9498 if(ba[i]<start || ba[i]>=(start+slen*4))
9500 // Branch out of this block, don't need anything
9506 // Need whatever matches the target
9508 int t=(ba[i]-start)>>2;
9509 for(hr=0;hr<HOST_REGS;hr++)
9511 if(regs[i].regmap_entry[hr]>=0) {
9512 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9516 // Conditional branch may need registers for following instructions
9517 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9520 nr|=needed_reg[i+2];
9521 for(hr=0;hr<HOST_REGS;hr++)
9523 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9524 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9528 // Don't need stuff which is overwritten
9529 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9530 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9531 // Merge in delay slot
9532 for(hr=0;hr<HOST_REGS;hr++)
9535 // These are overwritten unless the branch is "likely"
9536 // and the delay slot is nullified if not taken
9537 if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9538 if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9540 if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9541 if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9542 if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9543 if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9544 if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9545 if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9546 if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9547 if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9548 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9549 if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9550 if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9552 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9553 if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9554 if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9556 if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
9557 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9558 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9562 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
9564 // SYSCALL instruction (software interrupt)
9567 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9569 // ERET instruction (return from interrupt)
9575 for(hr=0;hr<HOST_REGS;hr++) {
9576 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9577 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9578 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9579 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9583 for(hr=0;hr<HOST_REGS;hr++)
9585 // Overwritten registers are not needed
9586 if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9587 if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9588 if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9589 // Source registers are needed
9590 if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9591 if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9592 if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9593 if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9594 if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9595 if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9596 if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9597 if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9598 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9599 if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9600 if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9602 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
9603 if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9604 if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9606 if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
9607 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9608 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9610 // Don't store a register immediately after writing it,
9611 // may prevent dual-issue.
9612 // But do so if this is a branch target, otherwise we
9613 // might have to load the register before the branch.
9614 if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
9615 if((regmap_pre[i][hr]>0&®map_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
9616 (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
9617 if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9618 if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9620 if((regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
9621 (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
9622 if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9623 if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9627 // Cycle count is needed at branches. Assume it is needed at the target too.
9628 if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
9629 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9630 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9635 // Deallocate unneeded registers
9636 for(hr=0;hr<HOST_REGS;hr++)
9639 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
9640 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9641 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9642 (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
9644 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9647 regs[i].regmap[hr]=-1;
9648 regs[i].isconst&=~(1<<hr);
9649 if(i<slen-2) regmap_pre[i+2][hr]=-1;
9653 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9655 int d1=0,d2=0,map=0,temp=0;
9656 if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
9662 if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
9663 itype[i+1]==STORE || itype[i+1]==STORELR ||
9664 itype[i+1]==C1LS || itype[i+1]==C2LS)
9667 if(itype[i+1]==STORE || itype[i+1]==STORELR ||
9668 (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
9671 if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
9672 itype[i+1]==C1LS || itype[i+1]==C2LS)
9674 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9675 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9676 (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
9677 (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
9678 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9679 regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
9680 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
9681 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
9682 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
9683 regs[i].regmap[hr]!=map )
9685 regs[i].regmap[hr]=-1;
9686 regs[i].isconst&=~(1<<hr);
9687 if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
9688 (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
9689 (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
9690 (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
9691 (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
9692 branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
9693 (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
9694 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
9695 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
9696 branch_regs[i].regmap[hr]!=map)
9698 branch_regs[i].regmap[hr]=-1;
9699 branch_regs[i].regmap_entry[hr]=-1;
9700 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9702 if(!likely[i]&&i<slen-2) {
9703 regmap_pre[i+2][hr]=-1;
9714 int d1=0,d2=0,map=-1,temp=-1;
9715 if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
9721 if(itype[i]==LOAD || itype[i]==LOADLR ||
9722 itype[i]==STORE || itype[i]==STORELR ||
9723 itype[i]==C1LS || itype[i]==C2LS)
9725 } else if(itype[i]==STORE || itype[i]==STORELR ||
9726 (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
9729 if(itype[i]==LOADLR || itype[i]==STORELR ||
9730 itype[i]==C1LS || itype[i]==C2LS)
9732 if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9733 (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
9734 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9735 regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
9736 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
9737 (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
9739 if(i<slen-1&&!is_ds[i]) {
9740 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
9741 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
9742 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
9744 printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
9745 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
9747 regmap_pre[i+1][hr]=-1;
9748 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
9750 regs[i].regmap[hr]=-1;
9751 regs[i].isconst&=~(1<<hr);
9759 /* Pass 5 - Pre-allocate registers */
9761 // If a register is allocated during a loop, try to allocate it for the
9762 // entire loop, if possible. This avoids loading/storing registers
9763 // inside of the loop.
9765 signed char f_regmap[HOST_REGS];
9766 clear_all_regs(f_regmap);
9767 for(i=0;i<slen-1;i++)
9769 if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9771 if(ba[i]>=start && ba[i]<(start+i*4))
9772 if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
9773 ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
9774 ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
9775 ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
9776 ||itype[i+1]==FCOMP||itype[i+1]==FCONV
9777 ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
9779 int t=(ba[i]-start)>>2;
9780 if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
9781 if(t<2||(itype[t-2]!=UJUMP)) // call/ret assumes no registers allocated
9782 for(hr=0;hr<HOST_REGS;hr++)
9784 if(regs[i].regmap[hr]>64) {
9785 if(!((regs[i].dirty>>hr)&1))
9786 f_regmap[hr]=regs[i].regmap[hr];
9787 else f_regmap[hr]=-1;
9789 else if(regs[i].regmap[hr]>=0) {
9790 if(f_regmap[hr]!=regs[i].regmap[hr]) {
9791 // dealloc old register
9793 for(n=0;n<HOST_REGS;n++)
9795 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
9797 // and alloc new one
9798 f_regmap[hr]=regs[i].regmap[hr];
9801 if(branch_regs[i].regmap[hr]>64) {
9802 if(!((branch_regs[i].dirty>>hr)&1))
9803 f_regmap[hr]=branch_regs[i].regmap[hr];
9804 else f_regmap[hr]=-1;
9806 else if(branch_regs[i].regmap[hr]>=0) {
9807 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
9808 // dealloc old register
9810 for(n=0;n<HOST_REGS;n++)
9812 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
9814 // and alloc new one
9815 f_regmap[hr]=branch_regs[i].regmap[hr];
9819 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
9820 f_regmap[hr]=branch_regs[i].regmap[hr];
9822 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
9823 f_regmap[hr]=branch_regs[i].regmap[hr];
9825 // Avoid dirty->clean transition
9826 #ifdef DESTRUCTIVE_WRITEBACK
9827 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
9829 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
9830 // case above, however it's always a good idea. We can't hoist the
9831 // load if the register was already allocated, so there's no point
9832 // wasting time analyzing most of these cases. It only "succeeds"
9833 // when the mapping was different and the load can be replaced with
9834 // a mov, which is of negligible benefit. So such cases are
9836 if(f_regmap[hr]>0) {
9837 if(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0) {
9841 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9842 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
9843 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
9845 // NB This can exclude the case where the upper-half
9846 // register is lower numbered than the lower-half
9847 // register. Not sure if it's worth fixing...
9848 if(get_reg(regs[j].regmap,r&63)<0) break;
9849 if(get_reg(regs[j].regmap_entry,r&63)<0) break;
9850 if(regs[j].is32&(1LL<<(r&63))) break;
9852 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
9853 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9855 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
9856 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
9858 if(get_reg(regs[i].regmap,r&63)<0) break;
9859 if(get_reg(branch_regs[i].regmap,r&63)<0) break;
9862 while(k>1&®s[k-1].regmap[hr]==-1) {
9863 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
9864 //printf("no free regs for store %x\n",start+(k-1)*4);
9867 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
9868 //printf("no-match due to different register\n");
9871 if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
9872 //printf("no-match due to branch\n");
9875 // call/ret fast path assumes no registers allocated
9876 if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)) {
9880 // NB This can exclude the case where the upper-half
9881 // register is lower numbered than the lower-half
9882 // register. Not sure if it's worth fixing...
9883 if(get_reg(regs[k-1].regmap,r&63)<0) break;
9884 if(regs[k-1].is32&(1LL<<(r&63))) break;
9889 if((regs[k].is32&(1LL<<f_regmap[hr]))!=
9890 (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
9891 //printf("bad match after branch\n");
9895 if(regs[k-1].regmap[hr]==f_regmap[hr]&®map_pre[k][hr]==f_regmap[hr]) {
9896 //printf("Extend r%d, %x ->\n",hr,start+k*4);
9898 regs[k].regmap_entry[hr]=f_regmap[hr];
9899 regs[k].regmap[hr]=f_regmap[hr];
9900 regmap_pre[k+1][hr]=f_regmap[hr];
9901 regs[k].wasdirty&=~(1<<hr);
9902 regs[k].dirty&=~(1<<hr);
9903 regs[k].wasdirty|=(1<<hr)®s[k-1].dirty;
9904 regs[k].dirty|=(1<<hr)®s[k].wasdirty;
9905 regs[k].wasconst&=~(1<<hr);
9906 regs[k].isconst&=~(1<<hr);
9911 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
9914 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
9915 if(regs[i-1].regmap[hr]==f_regmap[hr]&®map_pre[i][hr]==f_regmap[hr]) {
9916 //printf("OK fill %x (r%d)\n",start+i*4,hr);
9917 regs[i].regmap_entry[hr]=f_regmap[hr];
9918 regs[i].regmap[hr]=f_regmap[hr];
9919 regs[i].wasdirty&=~(1<<hr);
9920 regs[i].dirty&=~(1<<hr);
9921 regs[i].wasdirty|=(1<<hr)®s[i-1].dirty;
9922 regs[i].dirty|=(1<<hr)®s[i-1].dirty;
9923 regs[i].wasconst&=~(1<<hr);
9924 regs[i].isconst&=~(1<<hr);
9925 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
9926 branch_regs[i].wasdirty&=~(1<<hr);
9927 branch_regs[i].wasdirty|=(1<<hr)®s[i].dirty;
9928 branch_regs[i].regmap[hr]=f_regmap[hr];
9929 branch_regs[i].dirty&=~(1<<hr);
9930 branch_regs[i].dirty|=(1<<hr)®s[i].dirty;
9931 branch_regs[i].wasconst&=~(1<<hr);
9932 branch_regs[i].isconst&=~(1<<hr);
9933 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
9934 regmap_pre[i+2][hr]=f_regmap[hr];
9935 regs[i+2].wasdirty&=~(1<<hr);
9936 regs[i+2].wasdirty|=(1<<hr)®s[i].dirty;
9937 assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
9938 (regs[i+2].was32&(1LL<<f_regmap[hr])));
9943 // Alloc register clean at beginning of loop,
9944 // but may dirty it in pass 6
9945 regs[k].regmap_entry[hr]=f_regmap[hr];
9946 regs[k].regmap[hr]=f_regmap[hr];
9947 regs[k].dirty&=~(1<<hr);
9948 regs[k].wasconst&=~(1<<hr);
9949 regs[k].isconst&=~(1<<hr);
9950 if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) {
9951 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
9952 branch_regs[k].regmap[hr]=f_regmap[hr];
9953 branch_regs[k].dirty&=~(1<<hr);
9954 branch_regs[k].wasconst&=~(1<<hr);
9955 branch_regs[k].isconst&=~(1<<hr);
9956 if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
9957 regmap_pre[k+2][hr]=f_regmap[hr];
9958 regs[k+2].wasdirty&=~(1<<hr);
9959 assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))==
9960 (regs[k+2].was32&(1LL<<f_regmap[hr])));
9965 regmap_pre[k+1][hr]=f_regmap[hr];
9966 regs[k+1].wasdirty&=~(1<<hr);
9969 if(regs[j].regmap[hr]==f_regmap[hr])
9970 regs[j].regmap_entry[hr]=f_regmap[hr];
9974 if(regs[j].regmap[hr]>=0)
9976 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
9977 //printf("no-match due to different register\n");
9980 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
9981 //printf("32/64 mismatch %x %d\n",start+j*4,hr);
9984 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
9986 // Stop on unconditional branch
9989 if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
9992 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
9995 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
9998 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
9999 //printf("no-match due to different register (branch)\n");
10003 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10004 //printf("No free regs for store %x\n",start+j*4);
10007 if(f_regmap[hr]>=64) {
10008 if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
10013 if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
10025 for(hr=0;hr<HOST_REGS;hr++)
10027 if(hr!=EXCLUDE_REG) {
10028 if(regs[i].regmap[hr]>64) {
10029 if(!((regs[i].dirty>>hr)&1))
10030 f_regmap[hr]=regs[i].regmap[hr];
10032 else if(regs[i].regmap[hr]>=0) {
10033 if(f_regmap[hr]!=regs[i].regmap[hr]) {
10034 // dealloc old register
10036 for(n=0;n<HOST_REGS;n++)
10038 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10040 // and alloc new one
10041 f_regmap[hr]=regs[i].regmap[hr];
10044 else if(regs[i].regmap[hr]<0) count++;
10047 // Try to restore cycle count at branch targets
10049 for(j=i;j<slen-1;j++) {
10050 if(regs[j].regmap[HOST_CCREG]!=-1) break;
10051 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10052 //printf("no free regs for store %x\n",start+j*4);
10056 if(regs[j].regmap[HOST_CCREG]==CCREG) {
10058 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
10060 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10061 regs[k].regmap[HOST_CCREG]=CCREG;
10062 regmap_pre[k+1][HOST_CCREG]=CCREG;
10063 regs[k+1].wasdirty|=1<<HOST_CCREG;
10064 regs[k].dirty|=1<<HOST_CCREG;
10065 regs[k].wasconst&=~(1<<HOST_CCREG);
10066 regs[k].isconst&=~(1<<HOST_CCREG);
10069 regs[j].regmap_entry[HOST_CCREG]=CCREG;
10071 // Work backwards from the branch target
10072 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
10074 //printf("Extend backwards\n");
10077 while(regs[k-1].regmap[HOST_CCREG]==-1) {
10078 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10079 //printf("no free regs for store %x\n",start+(k-1)*4);
10084 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
10085 //printf("Extend CC, %x ->\n",start+k*4);
10087 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10088 regs[k].regmap[HOST_CCREG]=CCREG;
10089 regmap_pre[k+1][HOST_CCREG]=CCREG;
10090 regs[k+1].wasdirty|=1<<HOST_CCREG;
10091 regs[k].dirty|=1<<HOST_CCREG;
10092 regs[k].wasconst&=~(1<<HOST_CCREG);
10093 regs[k].isconst&=~(1<<HOST_CCREG);
10098 //printf("Fail Extend CC, %x ->\n",start+k*4);
10102 if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
10103 itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
10104 itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
10105 itype[i]!=FCONV&&itype[i]!=FCOMP)
10107 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
10112 // This allocates registers (if possible) one instruction prior
10113 // to use, which can avoid a load-use penalty on certain CPUs.
10114 for(i=0;i<slen-1;i++)
10116 if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10120 if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
10121 ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
10124 if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10126 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10128 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10129 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10130 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10131 regs[i].isconst&=~(1<<hr);
10132 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10133 constmap[i][hr]=constmap[i+1][hr];
10134 regs[i+1].wasdirty&=~(1<<hr);
10135 regs[i].dirty&=~(1<<hr);
10140 if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10142 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10144 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10145 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10146 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10147 regs[i].isconst&=~(1<<hr);
10148 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10149 constmap[i][hr]=constmap[i+1][hr];
10150 regs[i+1].wasdirty&=~(1<<hr);
10151 regs[i].dirty&=~(1<<hr);
10155 if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10156 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10158 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10160 regs[i].regmap[hr]=rs1[i+1];
10161 regmap_pre[i+1][hr]=rs1[i+1];
10162 regs[i+1].regmap_entry[hr]=rs1[i+1];
10163 regs[i].isconst&=~(1<<hr);
10164 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10165 constmap[i][hr]=constmap[i+1][hr];
10166 regs[i+1].wasdirty&=~(1<<hr);
10167 regs[i].dirty&=~(1<<hr);
10171 if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10172 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10174 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10176 regs[i].regmap[hr]=rs1[i+1];
10177 regmap_pre[i+1][hr]=rs1[i+1];
10178 regs[i+1].regmap_entry[hr]=rs1[i+1];
10179 regs[i].isconst&=~(1<<hr);
10180 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10181 constmap[i][hr]=constmap[i+1][hr];
10182 regs[i+1].wasdirty&=~(1<<hr);
10183 regs[i].dirty&=~(1<<hr);
10187 #ifndef HOST_IMM_ADDR32
10188 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
10189 hr=get_reg(regs[i+1].regmap,TLREG);
10191 int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10192 if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10194 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10196 regs[i].regmap[hr]=MGEN1+((i+1)&1);
10197 regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10198 regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10199 regs[i].isconst&=~(1<<hr);
10200 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10201 constmap[i][hr]=constmap[i+1][hr];
10202 regs[i+1].wasdirty&=~(1<<hr);
10203 regs[i].dirty&=~(1<<hr);
10205 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10207 // move it to another register
10208 regs[i+1].regmap[hr]=-1;
10209 regmap_pre[i+2][hr]=-1;
10210 regs[i+1].regmap[nr]=TLREG;
10211 regmap_pre[i+2][nr]=TLREG;
10212 regs[i].regmap[nr]=MGEN1+((i+1)&1);
10213 regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10214 regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10215 regs[i].isconst&=~(1<<nr);
10216 regs[i+1].isconst&=~(1<<nr);
10217 regs[i].dirty&=~(1<<nr);
10218 regs[i+1].wasdirty&=~(1<<nr);
10219 regs[i+1].dirty&=~(1<<nr);
10220 regs[i+2].wasdirty&=~(1<<nr);
10226 if(itype[i+1]==STORE||itype[i+1]==STORELR
10227 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
10228 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10229 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10230 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10231 else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10233 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10235 regs[i].regmap[hr]=rs1[i+1];
10236 regmap_pre[i+1][hr]=rs1[i+1];
10237 regs[i+1].regmap_entry[hr]=rs1[i+1];
10238 regs[i].isconst&=~(1<<hr);
10239 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10240 constmap[i][hr]=constmap[i+1][hr];
10241 regs[i+1].wasdirty&=~(1<<hr);
10242 regs[i].dirty&=~(1<<hr);
10246 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
10247 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10249 hr=get_reg(regs[i+1].regmap,FTEMP);
10251 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10253 regs[i].regmap[hr]=rs1[i+1];
10254 regmap_pre[i+1][hr]=rs1[i+1];
10255 regs[i+1].regmap_entry[hr]=rs1[i+1];
10256 regs[i].isconst&=~(1<<hr);
10257 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10258 constmap[i][hr]=constmap[i+1][hr];
10259 regs[i+1].wasdirty&=~(1<<hr);
10260 regs[i].dirty&=~(1<<hr);
10262 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10264 // move it to another register
10265 regs[i+1].regmap[hr]=-1;
10266 regmap_pre[i+2][hr]=-1;
10267 regs[i+1].regmap[nr]=FTEMP;
10268 regmap_pre[i+2][nr]=FTEMP;
10269 regs[i].regmap[nr]=rs1[i+1];
10270 regmap_pre[i+1][nr]=rs1[i+1];
10271 regs[i+1].regmap_entry[nr]=rs1[i+1];
10272 regs[i].isconst&=~(1<<nr);
10273 regs[i+1].isconst&=~(1<<nr);
10274 regs[i].dirty&=~(1<<nr);
10275 regs[i+1].wasdirty&=~(1<<nr);
10276 regs[i+1].dirty&=~(1<<nr);
10277 regs[i+2].wasdirty&=~(1<<nr);
10281 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
10282 if(itype[i+1]==LOAD)
10283 hr=get_reg(regs[i+1].regmap,rt1[i+1]);
10284 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
10285 hr=get_reg(regs[i+1].regmap,FTEMP);
10286 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
10287 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10288 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10290 if(hr>=0&®s[i].regmap[hr]<0) {
10291 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10292 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10293 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10294 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10295 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10296 regs[i].isconst&=~(1<<hr);
10297 regs[i+1].wasdirty&=~(1<<hr);
10298 regs[i].dirty&=~(1<<hr);
10307 /* Pass 6 - Optimize clean/dirty state */
10308 clean_registers(0,slen-1,1);
10310 /* Pass 7 - Identify 32-bit registers */
10316 for (i=slen-1;i>=0;i--)
10319 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10321 if(ba[i]<start || ba[i]>=(start+slen*4))
10323 // Branch out of this block, don't need anything
10329 // Need whatever matches the target
10330 // (and doesn't get overwritten by the delay slot instruction)
10332 int t=(ba[i]-start)>>2;
10333 if(ba[i]>start+i*4) {
10335 if(!(requires_32bit[t]&~regs[i].was32))
10336 r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10339 //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10340 // r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10341 if(!(pr32[t]&~regs[i].was32))
10342 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10345 // Conditional branch may need registers for following instructions
10346 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10349 r32|=requires_32bit[i+2];
10350 r32&=regs[i].was32;
10351 // Mark this address as a branch target since it may be called
10352 // upon return from interrupt
10356 // Merge in delay slot
10358 // These are overwritten unless the branch is "likely"
10359 // and the delay slot is nullified if not taken
10360 r32&=~(1LL<<rt1[i+1]);
10361 r32&=~(1LL<<rt2[i+1]);
10363 // Assume these are needed (delay slot)
10366 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10370 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10372 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10374 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10376 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10378 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10381 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
10383 // SYSCALL instruction (software interrupt)
10386 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10388 // ERET instruction (return from interrupt)
10392 r32&=~(1LL<<rt1[i]);
10393 r32&=~(1LL<<rt2[i]);
10396 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10400 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10402 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
10404 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
10406 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
10408 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
10410 requires_32bit[i]=r32;
10412 // Dirty registers which are 32-bit, require 32-bit input
10413 // as they will be written as 32-bit values
10414 for(hr=0;hr<HOST_REGS;hr++)
10416 if(regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64) {
10417 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
10418 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
10419 requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
10423 //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
10427 if(itype[slen-1]==SPAN) {
10428 bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
10431 /* Debug/disassembly */
10432 if((void*)assem_debug==(void*)printf)
10433 for(i=0;i<slen;i++)
10437 for(r=1;r<=CCREG;r++) {
10438 if((unneeded_reg[i]>>r)&1) {
10439 if(r==HIREG) printf(" HI");
10440 else if(r==LOREG) printf(" LO");
10441 else printf(" r%d",r);
10446 for(r=1;r<=CCREG;r++) {
10447 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
10448 if(r==HIREG) printf(" HI");
10449 else if(r==LOREG) printf(" LO");
10450 else printf(" r%d",r);
10454 for(r=0;r<=CCREG;r++) {
10455 //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10456 if((regs[i].was32>>r)&1) {
10457 if(r==CCREG) printf(" CC");
10458 else if(r==HIREG) printf(" HI");
10459 else if(r==LOREG) printf(" LO");
10460 else printf(" r%d",r);
10465 #if defined(__i386__) || defined(__x86_64__)
10466 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
10469 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
10472 if(needed_reg[i]&1) printf("eax ");
10473 if((needed_reg[i]>>1)&1) printf("ecx ");
10474 if((needed_reg[i]>>2)&1) printf("edx ");
10475 if((needed_reg[i]>>3)&1) printf("ebx ");
10476 if((needed_reg[i]>>5)&1) printf("ebp ");
10477 if((needed_reg[i]>>6)&1) printf("esi ");
10478 if((needed_reg[i]>>7)&1) printf("edi ");
10480 for(r=0;r<=CCREG;r++) {
10481 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10482 if((requires_32bit[i]>>r)&1) {
10483 if(r==CCREG) printf(" CC");
10484 else if(r==HIREG) printf(" HI");
10485 else if(r==LOREG) printf(" LO");
10486 else printf(" r%d",r);
10491 for(r=0;r<=CCREG;r++) {
10492 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10493 if((pr32[i]>>r)&1) {
10494 if(r==CCREG) printf(" CC");
10495 else if(r==HIREG) printf(" HI");
10496 else if(r==LOREG) printf(" LO");
10497 else printf(" r%d",r);
10500 if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
10502 #if defined(__i386__) || defined(__x86_64__)
10503 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
10505 if(regs[i].wasdirty&1) printf("eax ");
10506 if((regs[i].wasdirty>>1)&1) printf("ecx ");
10507 if((regs[i].wasdirty>>2)&1) printf("edx ");
10508 if((regs[i].wasdirty>>3)&1) printf("ebx ");
10509 if((regs[i].wasdirty>>5)&1) printf("ebp ");
10510 if((regs[i].wasdirty>>6)&1) printf("esi ");
10511 if((regs[i].wasdirty>>7)&1) printf("edi ");
10514 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
10516 if(regs[i].wasdirty&1) printf("r0 ");
10517 if((regs[i].wasdirty>>1)&1) printf("r1 ");
10518 if((regs[i].wasdirty>>2)&1) printf("r2 ");
10519 if((regs[i].wasdirty>>3)&1) printf("r3 ");
10520 if((regs[i].wasdirty>>4)&1) printf("r4 ");
10521 if((regs[i].wasdirty>>5)&1) printf("r5 ");
10522 if((regs[i].wasdirty>>6)&1) printf("r6 ");
10523 if((regs[i].wasdirty>>7)&1) printf("r7 ");
10524 if((regs[i].wasdirty>>8)&1) printf("r8 ");
10525 if((regs[i].wasdirty>>9)&1) printf("r9 ");
10526 if((regs[i].wasdirty>>10)&1) printf("r10 ");
10527 if((regs[i].wasdirty>>12)&1) printf("r12 ");
10530 disassemble_inst(i);
10531 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
10532 #if defined(__i386__) || defined(__x86_64__)
10533 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
10534 if(regs[i].dirty&1) printf("eax ");
10535 if((regs[i].dirty>>1)&1) printf("ecx ");
10536 if((regs[i].dirty>>2)&1) printf("edx ");
10537 if((regs[i].dirty>>3)&1) printf("ebx ");
10538 if((regs[i].dirty>>5)&1) printf("ebp ");
10539 if((regs[i].dirty>>6)&1) printf("esi ");
10540 if((regs[i].dirty>>7)&1) printf("edi ");
10543 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
10544 if(regs[i].dirty&1) printf("r0 ");
10545 if((regs[i].dirty>>1)&1) printf("r1 ");
10546 if((regs[i].dirty>>2)&1) printf("r2 ");
10547 if((regs[i].dirty>>3)&1) printf("r3 ");
10548 if((regs[i].dirty>>4)&1) printf("r4 ");
10549 if((regs[i].dirty>>5)&1) printf("r5 ");
10550 if((regs[i].dirty>>6)&1) printf("r6 ");
10551 if((regs[i].dirty>>7)&1) printf("r7 ");
10552 if((regs[i].dirty>>8)&1) printf("r8 ");
10553 if((regs[i].dirty>>9)&1) printf("r9 ");
10554 if((regs[i].dirty>>10)&1) printf("r10 ");
10555 if((regs[i].dirty>>12)&1) printf("r12 ");
10558 if(regs[i].isconst) {
10559 printf("constants: ");
10560 #if defined(__i386__) || defined(__x86_64__)
10561 if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
10562 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
10563 if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
10564 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
10565 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
10566 if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
10567 if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
10570 if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
10571 if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
10572 if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
10573 if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
10574 if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
10575 if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
10576 if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
10577 if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
10578 if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
10579 if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
10580 if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
10581 if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
10587 for(r=0;r<=CCREG;r++) {
10588 if((regs[i].is32>>r)&1) {
10589 if(r==CCREG) printf(" CC");
10590 else if(r==HIREG) printf(" HI");
10591 else if(r==LOREG) printf(" LO");
10592 else printf(" r%d",r);
10598 for(r=0;r<=CCREG;r++) {
10599 if((p32[i]>>r)&1) {
10600 if(r==CCREG) printf(" CC");
10601 else if(r==HIREG) printf(" HI");
10602 else if(r==LOREG) printf(" LO");
10603 else printf(" r%d",r);
10606 if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
10607 else printf("\n");*/
10608 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10609 #if defined(__i386__) || defined(__x86_64__)
10610 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
10611 if(branch_regs[i].dirty&1) printf("eax ");
10612 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
10613 if((branch_regs[i].dirty>>2)&1) printf("edx ");
10614 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
10615 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
10616 if((branch_regs[i].dirty>>6)&1) printf("esi ");
10617 if((branch_regs[i].dirty>>7)&1) printf("edi ");
10620 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
10621 if(branch_regs[i].dirty&1) printf("r0 ");
10622 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
10623 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
10624 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
10625 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
10626 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
10627 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
10628 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
10629 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
10630 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
10631 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
10632 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
10636 for(r=0;r<=CCREG;r++) {
10637 if((branch_regs[i].is32>>r)&1) {
10638 if(r==CCREG) printf(" CC");
10639 else if(r==HIREG) printf(" HI");
10640 else if(r==LOREG) printf(" LO");
10641 else printf(" r%d",r);
10649 /* Pass 8 - Assembly */
10650 linkcount=0;stubcount=0;
10651 ds=0;is_delayslot=0;
10653 uint64_t is32_pre=0;
10655 u_int beginning=(u_int)out;
10656 if((u_int)addr&1) {
10660 u_int instr_addr0_override=0;
10663 if (start == 0x80030000) {
10664 // nasty hack for fastbios thing
10665 instr_addr0_override=(u_int)out;
10666 emit_movimm(start,0);
10667 emit_readword((int)&pcaddr,1);
10668 emit_writeword(0,(int)&pcaddr);
10670 emit_jne((int)new_dyna_leave);
10673 for(i=0;i<slen;i++)
10675 //if(ds) printf("ds: ");
10676 if((void*)assem_debug==(void*)printf) disassemble_inst(i);
10678 ds=0; // Skip delay slot
10679 if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
10682 #ifndef DESTRUCTIVE_WRITEBACK
10683 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10685 wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
10686 unneeded_reg[i],unneeded_reg_upper[i]);
10687 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
10688 unneeded_reg[i],unneeded_reg_upper[i]);
10690 is32_pre=regs[i].is32;
10691 dirty_pre=regs[i].dirty;
10694 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10696 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
10697 unneeded_reg[i],unneeded_reg_upper[i]);
10698 loop_preload(regmap_pre[i],regs[i].regmap_entry);
10700 // branch target entry point
10701 instr_addr[i]=(u_int)out;
10702 assem_debug("<->\n");
10704 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&®s[i].regmap[HOST_CCREG]!=CCREG)
10705 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
10706 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
10707 address_generation(i,®s[i],regs[i].regmap_entry);
10708 load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
10709 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10711 // Load the delay slot registers if necessary
10712 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10713 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10714 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10715 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
10716 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
10717 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10721 // Preload registers for following instruction
10722 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10723 if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
10724 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10725 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10726 if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
10727 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
10729 // TODO: if(is_ooo(i)) address_generation(i+1);
10730 if(itype[i]==CJUMP||itype[i]==FJUMP)
10731 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
10732 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
10733 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10734 if(bt[i]) cop1_usable=0;
10738 alu_assemble(i,®s[i]);break;
10740 imm16_assemble(i,®s[i]);break;
10742 shift_assemble(i,®s[i]);break;
10744 shiftimm_assemble(i,®s[i]);break;
10746 load_assemble(i,®s[i]);break;
10748 loadlr_assemble(i,®s[i]);break;
10750 store_assemble(i,®s[i]);break;
10752 storelr_assemble(i,®s[i]);break;
10754 cop0_assemble(i,®s[i]);break;
10756 cop1_assemble(i,®s[i]);break;
10758 c1ls_assemble(i,®s[i]);break;
10760 cop2_assemble(i,®s[i]);break;
10762 c2ls_assemble(i,®s[i]);break;
10764 c2op_assemble(i,®s[i]);break;
10766 fconv_assemble(i,®s[i]);break;
10768 float_assemble(i,®s[i]);break;
10770 fcomp_assemble(i,®s[i]);break;
10772 multdiv_assemble(i,®s[i]);break;
10774 mov_assemble(i,®s[i]);break;
10776 syscall_assemble(i,®s[i]);break;
10778 hlecall_assemble(i,®s[i]);break;
10780 intcall_assemble(i,®s[i]);break;
10782 ujump_assemble(i,®s[i]);ds=1;break;
10784 rjump_assemble(i,®s[i]);ds=1;break;
10786 cjump_assemble(i,®s[i]);ds=1;break;
10788 sjump_assemble(i,®s[i]);ds=1;break;
10790 fjump_assemble(i,®s[i]);ds=1;break;
10792 pagespan_assemble(i,®s[i]);break;
10794 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10795 literal_pool(1024);
10797 literal_pool_jumpover(256);
10800 //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
10801 // If the block did not end with an unconditional branch,
10802 // add a jump to the next instruction.
10804 if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
10805 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10807 if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
10808 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10809 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10810 emit_loadreg(CCREG,HOST_CCREG);
10811 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10813 else if(!likely[i-2])
10815 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
10816 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
10820 store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
10821 assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
10823 add_to_linker((int)out,start+i*4,0);
10830 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10831 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10832 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10833 emit_loadreg(CCREG,HOST_CCREG);
10834 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10835 add_to_linker((int)out,start+i*4,0);
10839 // TODO: delay slot stubs?
10841 for(i=0;i<stubcount;i++)
10843 switch(stubs[i][0])
10851 do_readstub(i);break;
10856 do_writestub(i);break;
10858 do_ccstub(i);break;
10860 do_invstub(i);break;
10862 do_cop1stub(i);break;
10864 do_unalignedwritestub(i);break;
10868 if (instr_addr0_override)
10869 instr_addr[0] = instr_addr0_override;
10871 /* Pass 9 - Linker */
10872 for(i=0;i<linkcount;i++)
10874 assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
10876 if(!link_addr[i][2])
10879 void *addr=check_addr(link_addr[i][1]);
10880 emit_extjump(link_addr[i][0],link_addr[i][1]);
10882 set_jump_target(link_addr[i][0],(int)addr);
10883 add_link(link_addr[i][1],stub);
10885 else set_jump_target(link_addr[i][0],(int)stub);
10890 int target=(link_addr[i][1]-start)>>2;
10891 assert(target>=0&&target<slen);
10892 assert(instr_addr[target]);
10893 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10894 //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
10896 set_jump_target(link_addr[i][0],instr_addr[target]);
10900 // External Branch Targets (jump_in)
10901 if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
10902 for(i=0;i<slen;i++)
10906 if(instr_addr[i]) // TODO - delay slots (=null)
10908 u_int vaddr=start+i*4;
10909 u_int page=get_page(vaddr);
10910 u_int vpage=get_vpage(vaddr);
10912 //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
10914 if(!requires_32bit[i])
10919 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
10920 assem_debug("jump_in: %x\n",start+i*4);
10921 ll_add(jump_dirty+vpage,vaddr,(void *)out);
10922 int entry_point=do_dirty_stub(i);
10923 ll_add(jump_in+page,vaddr,(void *)entry_point);
10924 // If there was an existing entry in the hash table,
10925 // replace it with the new address.
10926 // Don't add new entries. We'll insert the
10927 // ones that actually get used in check_addr().
10928 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
10929 if(ht_bin[0]==vaddr) {
10930 ht_bin[1]=entry_point;
10932 if(ht_bin[2]==vaddr) {
10933 ht_bin[3]=entry_point;
10938 u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
10939 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
10940 assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
10941 //int entry_point=(int)out;
10942 ////assem_debug("entry_point: %x\n",entry_point);
10943 //load_regs_entry(i);
10944 //if(entry_point==(int)out)
10945 // entry_point=instr_addr[i];
10947 // emit_jmp(instr_addr[i]);
10948 //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
10949 ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
10950 int entry_point=do_dirty_stub(i);
10951 ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
10956 // Write out the literal pool if necessary
10958 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10960 if(((u_int)out)&7) emit_addnop(13);
10962 assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
10963 //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
10964 memcpy(copy,source,slen*4);
10968 __clear_cache((void *)beginning,out);
10971 // If we're within 256K of the end of the buffer,
10972 // start over from the beginning. (Is 256K enough?)
10973 if((int)out>BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
10975 // Trap writes to any of the pages we compiled
10976 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
10978 #ifndef DISABLE_TLB
10979 memory_map[i]|=0x40000000;
10980 if((signed int)start>=(signed int)0xC0000000) {
10982 j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
10984 memory_map[j]|=0x40000000;
10985 //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
10990 /* Pass 10 - Free memory by expiring oldest blocks */
10992 int end=((((int)out-BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
10993 while(expirep!=end)
10995 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
10996 int base=BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
10997 inv_debug("EXP: Phase %d\n",expirep);
10998 switch((expirep>>11)&3)
11001 // Clear jump_in and jump_dirty
11002 ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
11003 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
11004 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
11005 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
11009 ll_kill_pointers(jump_out[expirep&2047],base,shift);
11010 ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
11013 // Clear hash table
11014 for(i=0;i<32;i++) {
11015 int *ht_bin=hash_table[((expirep&2047)<<5)+i];
11016 if((ht_bin[3]>>shift)==(base>>shift) ||
11017 ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11018 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
11019 ht_bin[2]=ht_bin[3]=-1;
11021 if((ht_bin[1]>>shift)==(base>>shift) ||
11022 ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11023 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
11024 ht_bin[0]=ht_bin[2];
11025 ht_bin[1]=ht_bin[3];
11026 ht_bin[2]=ht_bin[3]=-1;
11033 if((expirep&2047)==0)
11036 ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
11037 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
11040 expirep=(expirep+1)&65535;
11045 // vim:shiftwidth=2:expandtab