libpcsxcore/new_dynarec/new_dynarec.c

   1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
   2  *   Mupen64plus - new_dynarec.c                                           *
   3  *   Copyright (C) 2009-2011 Ari64                                         *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.          *
  19  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
  20
  21 #include <stdlib.h>
  22 #include <stdint.h> //include for uint64_t
  23 #include <assert.h>
  24 #include <sys/mman.h>
  25
  26 #include "emu_if.h" //emulator interface
  27
  28 //#define DISASM
  29 //#define assem_debug printf
  30 //#define inv_debug printf
  31 #define assem_debug(...)
  32 #define inv_debug(...)
  33
  34 #ifdef __i386__
  35 #include "assem_x86.h"
  36 #endif
  37 #ifdef __x86_64__
  38 #include "assem_x64.h"
  39 #endif
  40 #ifdef __arm__
  41 #include "assem_arm.h"
  42 #endif
  43
  44 #define MAXBLOCK 4096
  45 #define MAX_OUTPUT_BLOCK_SIZE 262144
  46
  47 int cycle_multiplier; // 100 for 1.0
  48 #define CLOCK_ADJUST(x) (((x) * cycle_multiplier + 50) / 100)
  49
  50 struct regstat
  51 {
  52   signed char regmap_entry[HOST_REGS];
  53   signed char regmap[HOST_REGS];
  54   uint64_t was32;
  55   uint64_t is32;
  56   uint64_t wasdirty;
  57   uint64_t dirty;
  58   uint64_t u;
  59   uint64_t uu;
  60   u_int wasconst;
  61   u_int isconst;
  62   uint64_t constmap[HOST_REGS];
  63 };
  64
  65 struct ll_entry
  66 {
  67   u_int vaddr;
  68   u_int reg32;
  69   void *addr;
  70   struct ll_entry *next;
  71 };
  72
  73   u_int start;
  74   u_int *source;
  75   u_int pagelimit;
  76   char insn[MAXBLOCK][10];
  77   u_char itype[MAXBLOCK];
  78   u_char opcode[MAXBLOCK];
  79   u_char opcode2[MAXBLOCK];
  80   u_char bt[MAXBLOCK];
  81   u_char rs1[MAXBLOCK];
  82   u_char rs2[MAXBLOCK];
  83   u_char rt1[MAXBLOCK];
  84   u_char rt2[MAXBLOCK];
  85   u_char us1[MAXBLOCK];
  86   u_char us2[MAXBLOCK];
  87   u_char dep1[MAXBLOCK];
  88   u_char dep2[MAXBLOCK];
  89   u_char lt1[MAXBLOCK];
  90   static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
  91   static uint64_t gte_rt[MAXBLOCK];
  92   static uint64_t gte_unneeded[MAXBLOCK];
  93   static int gte_reads_flags; // gte flag read encountered
  94   static u_int smrv[32]; // speculated MIPS register values
  95   static u_int smrv_strong; // mask or regs that are likely to have correct values
  96   static u_int smrv_weak; // same, but somewhat less likely
  97   static u_int smrv_strong_next; // same, but after current insn executes
  98   static u_int smrv_weak_next;
  99   int imm[MAXBLOCK];
 100   u_int ba[MAXBLOCK];
 101   char likely[MAXBLOCK];
 102   char is_ds[MAXBLOCK];
 103   char ooo[MAXBLOCK];
 104   uint64_t unneeded_reg[MAXBLOCK];
 105   uint64_t unneeded_reg_upper[MAXBLOCK];
 106   uint64_t branch_unneeded_reg[MAXBLOCK];
 107   uint64_t branch_unneeded_reg_upper[MAXBLOCK];
 108   uint64_t p32[MAXBLOCK];
 109   uint64_t pr32[MAXBLOCK];
 110   signed char regmap_pre[MAXBLOCK][HOST_REGS];
 111   signed char regmap[MAXBLOCK][HOST_REGS];
 112   signed char regmap_entry[MAXBLOCK][HOST_REGS];
 113   uint64_t constmap[MAXBLOCK][HOST_REGS];
 114   struct regstat regs[MAXBLOCK];
 115   struct regstat branch_regs[MAXBLOCK];
 116   signed char minimum_free_regs[MAXBLOCK];
 117   u_int needed_reg[MAXBLOCK];
 118   uint64_t requires_32bit[MAXBLOCK];
 119   u_int wont_dirty[MAXBLOCK];
 120   u_int will_dirty[MAXBLOCK];
 121   int ccadj[MAXBLOCK];
 122   int slen;
 123   u_int instr_addr[MAXBLOCK];
 124   u_int link_addr[MAXBLOCK][3];
 125   int linkcount;
 126   u_int stubs[MAXBLOCK*3][8];
 127   int stubcount;
 128   u_int literals[1024][2];
 129   int literalcount;
 130   int is_delayslot;
 131   int cop1_usable;
 132   u_char *out;
 133   struct ll_entry *jump_in[4096];
 134   struct ll_entry *jump_out[4096];
 135   struct ll_entry *jump_dirty[4096];
 136   u_int hash_table[65536][4]  __attribute__((aligned(16)));
 137   char shadow[1048576]  __attribute__((aligned(16)));
 138   void *copy;
 139   int expirep;
 140 #ifndef PCSX
 141   u_int using_tlb;
 142 #else
 143   static const u_int using_tlb=0;
 144 #endif
 145   int new_dynarec_did_compile;
 146   u_int stop_after_jal;
 147   extern u_char restore_candidate[512];
 148   extern int cycle_count;
 149
 150   /* registers that may be allocated */
 151   /* 1-31 gpr */
 152 #define HIREG 32 // hi
 153 #define LOREG 33 // lo
 154 #define FSREG 34 // FPU status (FCSR)
 155 #define CSREG 35 // Coprocessor status
 156 #define CCREG 36 // Cycle count
 157 #define INVCP 37 // Pointer to invalid_code
 158 #define MMREG 38 // Pointer to memory_map
 159 #define ROREG 39 // ram offset (if rdram!=0x80000000)
 160 #define TEMPREG 40
 161 #define FTEMP 40 // FPU temporary register
 162 #define PTEMP 41 // Prefetch temporary register
 163 #define TLREG 42 // TLB mapping offset
 164 #define RHASH 43 // Return address hash
 165 #define RHTBL 44 // Return address hash table address
 166 #define RTEMP 45 // JR/JALR address register
 167 #define MAXREG 45
 168 #define AGEN1 46 // Address generation temporary register
 169 #define AGEN2 47 // Address generation temporary register
 170 #define MGEN1 48 // Maptable address generation temporary register
 171 #define MGEN2 49 // Maptable address generation temporary register
 172 #define BTREG 50 // Branch target temporary register
 173
 174   /* instruction types */
 175 #define NOP 0     // No operation
 176 #define LOAD 1    // Load
 177 #define STORE 2   // Store
 178 #define LOADLR 3  // Unaligned load
 179 #define STORELR 4 // Unaligned store
 180 #define MOV 5     // Move
 181 #define ALU 6     // Arithmetic/logic
 182 #define MULTDIV 7 // Multiply/divide
 183 #define SHIFT 8   // Shift by register
 184 #define SHIFTIMM 9// Shift by immediate
 185 #define IMM16 10  // 16-bit immediate
 186 #define RJUMP 11  // Unconditional jump to register
 187 #define UJUMP 12  // Unconditional jump
 188 #define CJUMP 13  // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
 189 #define SJUMP 14  // Conditional branch (regimm format)
 190 #define COP0 15   // Coprocessor 0
 191 #define COP1 16   // Coprocessor 1
 192 #define C1LS 17   // Coprocessor 1 load/store
 193 #define FJUMP 18  // Conditional branch (floating point)
 194 #define FLOAT 19  // Floating point unit
 195 #define FCONV 20  // Convert integer to float
 196 #define FCOMP 21  // Floating point compare (sets FSREG)
 197 #define SYSCALL 22// SYSCALL
 198 #define OTHER 23  // Other
 199 #define SPAN 24   // Branch/delay slot spans 2 pages
 200 #define NI 25     // Not implemented
 201 #define HLECALL 26// PCSX fake opcodes for HLE
 202 #define COP2 27   // Coprocessor 2 move
 203 #define C2LS 28   // Coprocessor 2 load/store
 204 #define C2OP 29   // Coprocessor 2 operation
 205 #define INTCALL 30// Call interpreter to handle rare corner cases
 206
 207   /* stubs */
 208 #define CC_STUB 1
 209 #define FP_STUB 2
 210 #define LOADB_STUB 3
 211 #define LOADH_STUB 4
 212 #define LOADW_STUB 5
 213 #define LOADD_STUB 6
 214 #define LOADBU_STUB 7
 215 #define LOADHU_STUB 8
 216 #define STOREB_STUB 9
 217 #define STOREH_STUB 10
 218 #define STOREW_STUB 11
 219 #define STORED_STUB 12
 220 #define STORELR_STUB 13
 221 #define INVCODE_STUB 14
 222
 223   /* branch codes */
 224 #define TAKEN 1
 225 #define NOTTAKEN 2
 226 #define NULLDS 3
 227
 228 // asm linkage
 229 int new_recompile_block(int addr);
 230 void *get_addr_ht(u_int vaddr);
 231 void invalidate_block(u_int block);
 232 void invalidate_addr(u_int addr);
 233 void remove_hash(int vaddr);
 234 void jump_vaddr();
 235 void dyna_linker();
 236 void dyna_linker_ds();
 237 void verify_code();
 238 void verify_code_vm();
 239 void verify_code_ds();
 240 void cc_interrupt();
 241 void fp_exception();
 242 void fp_exception_ds();
 243 void jump_syscall();
 244 void jump_syscall_hle();
 245 void jump_eret();
 246 void jump_hlecall();
 247 void jump_intcall();
 248 void new_dyna_leave();
 249
 250 // TLB
 251 void TLBWI_new();
 252 void TLBWR_new();
 253 void read_nomem_new();
 254 void read_nomemb_new();
 255 void read_nomemh_new();
 256 void read_nomemd_new();
 257 void write_nomem_new();
 258 void write_nomemb_new();
 259 void write_nomemh_new();
 260 void write_nomemd_new();
 261 void write_rdram_new();
 262 void write_rdramb_new();
 263 void write_rdramh_new();
 264 void write_rdramd_new();
 265 extern u_int memory_map[1048576];
 266
 267 // Needed by assembler
 268 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
 269 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
 270 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
 271 void load_all_regs(signed char i_regmap[]);
 272 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
 273 void load_regs_entry(int t);
 274 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
 275
 276 int tracedebug=0;
 277
 278 //#define DEBUG_CYCLE_COUNT 1
 279
 280 static void tlb_hacks()
 281 {
 282 #ifndef DISABLE_TLB
 283   // Goldeneye hack
 284   if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
 285   {
 286     u_int addr;
 287     int n;
 288     switch (ROM_HEADER->Country_code&0xFF)
 289     {
 290       case 0x45: // U
 291         addr=0x34b30;
 292         break;
 293       case 0x4A: // J
 294         addr=0x34b70;
 295         break;
 296       case 0x50: // E
 297         addr=0x329f0;
 298         break;
 299       default:
 300         // Unknown country code
 301         addr=0;
 302         break;
 303     }
 304     u_int rom_addr=(u_int)rom;
 305     #ifdef ROM_COPY
 306     // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
 307     // in the lower 4G of memory to use this hack.  Copy it if necessary.
 308     if((void *)rom>(void *)0xffffffff) {
 309       munmap(ROM_COPY, 67108864);
 310       if(mmap(ROM_COPY, 12582912,
 311               PROT_READ | PROT_WRITE,
 312               MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
 313               -1, 0) <= 0) {printf("mmap() failed\n");}
 314       memcpy(ROM_COPY,rom,12582912);
 315       rom_addr=(u_int)ROM_COPY;
 316     }
 317     #endif
 318     if(addr) {
 319       for(n=0x7F000;n<0x80000;n++) {
 320         memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
 321       }
 322     }
 323   }
 324 #endif
 325 }
 326
 327 static u_int get_page(u_int vaddr)
 328 {
 329 #ifndef PCSX
 330   u_int page=(vaddr^0x80000000)>>12;
 331 #else
 332   u_int page=vaddr&~0xe0000000;
 333   if (page < 0x1000000)
 334     page &= ~0x0e00000; // RAM mirrors
 335   page>>=12;
 336 #endif
 337 #ifndef DISABLE_TLB
 338   if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
 339 #endif
 340   if(page>2048) page=2048+(page&2047);
 341   return page;
 342 }
 343
 344 static u_int get_vpage(u_int vaddr)
 345 {
 346   u_int vpage=(vaddr^0x80000000)>>12;
 347 #ifndef DISABLE_TLB
 348   if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
 349 #endif
 350   if(vpage>2048) vpage=2048+(vpage&2047);
 351   return vpage;
 352 }
 353
 354 // Get address from virtual address
 355 // This is called from the recompiled JR/JALR instructions
 356 void *get_addr(u_int vaddr)
 357 {
 358   u_int page=get_page(vaddr);
 359   u_int vpage=get_vpage(vaddr);
 360   struct ll_entry *head;
 361   //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
 362   head=jump_in[page];
 363   while(head!=NULL) {
 364     if(head->vaddr==vaddr&&head->reg32==0) {
 365   //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 366       int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 367       ht_bin[3]=ht_bin[1];
 368       ht_bin[2]=ht_bin[0];
 369       ht_bin[1]=(int)head->addr;
 370       ht_bin[0]=vaddr;
 371       return head->addr;
 372     }
 373     head=head->next;
 374   }
 375   head=jump_dirty[vpage];
 376   while(head!=NULL) {
 377     if(head->vaddr==vaddr&&head->reg32==0) {
 378       //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 379       // Don't restore blocks which are about to expire from the cache
 380       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 381       if(verify_dirty(head->addr)) {
 382         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
 383         invalid_code[vaddr>>12]=0;
 384         inv_code_start=inv_code_end=~0;
 385 #ifndef DISABLE_TLB
 386         memory_map[vaddr>>12]|=0x40000000;
 387 #endif
 388         if(vpage<2048) {
 389 #ifndef DISABLE_TLB
 390           if(tlb_LUT_r[vaddr>>12]) {
 391             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
 392             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
 393           }
 394 #endif
 395           restore_candidate[vpage>>3]|=1<<(vpage&7);
 396         }
 397         else restore_candidate[page>>3]|=1<<(page&7);
 398         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 399         if(ht_bin[0]==vaddr) {
 400           ht_bin[1]=(int)head->addr; // Replace existing entry
 401         }
 402         else
 403         {
 404           ht_bin[3]=ht_bin[1];
 405           ht_bin[2]=ht_bin[0];
 406           ht_bin[1]=(int)head->addr;
 407           ht_bin[0]=vaddr;
 408         }
 409         return head->addr;
 410       }
 411     }
 412     head=head->next;
 413   }
 414   //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
 415   int r=new_recompile_block(vaddr);
 416   if(r==0) return get_addr(vaddr);
 417   // Execute in unmapped page, generate pagefault execption
 418   Status|=2;
 419   Cause=(vaddr<<31)|0x8;
 420   EPC=(vaddr&1)?vaddr-5:vaddr;
 421   BadVAddr=(vaddr&~1);
 422   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
 423   EntryHi=BadVAddr&0xFFFFE000;
 424   return get_addr_ht(0x80000000);
 425 }
 426 // Look up address in hash table first
 427 void *get_addr_ht(u_int vaddr)
 428 {
 429   //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
 430   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 431   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
 432   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
 433   return get_addr(vaddr);
 434 }
 435
 436 void *get_addr_32(u_int vaddr,u_int flags)
 437 {
 438 #ifdef FORCE32
 439   return get_addr(vaddr);
 440 #else
 441   //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
 442   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 443   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
 444   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
 445   u_int page=get_page(vaddr);
 446   u_int vpage=get_vpage(vaddr);
 447   struct ll_entry *head;
 448   head=jump_in[page];
 449   while(head!=NULL) {
 450     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
 451       //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 452       if(head->reg32==0) {
 453         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 454         if(ht_bin[0]==-1) {
 455           ht_bin[1]=(int)head->addr;
 456           ht_bin[0]=vaddr;
 457         }else if(ht_bin[2]==-1) {
 458           ht_bin[3]=(int)head->addr;
 459           ht_bin[2]=vaddr;
 460         }
 461         //ht_bin[3]=ht_bin[1];
 462         //ht_bin[2]=ht_bin[0];
 463         //ht_bin[1]=(int)head->addr;
 464         //ht_bin[0]=vaddr;
 465       }
 466       return head->addr;
 467     }
 468     head=head->next;
 469   }
 470   head=jump_dirty[vpage];
 471   while(head!=NULL) {
 472     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
 473       //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 474       // Don't restore blocks which are about to expire from the cache
 475       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 476       if(verify_dirty(head->addr)) {
 477         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
 478         invalid_code[vaddr>>12]=0;
 479         inv_code_start=inv_code_end=~0;
 480         memory_map[vaddr>>12]|=0x40000000;
 481         if(vpage<2048) {
 482 #ifndef DISABLE_TLB
 483           if(tlb_LUT_r[vaddr>>12]) {
 484             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
 485             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
 486           }
 487 #endif
 488           restore_candidate[vpage>>3]|=1<<(vpage&7);
 489         }
 490         else restore_candidate[page>>3]|=1<<(page&7);
 491         if(head->reg32==0) {
 492           int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 493           if(ht_bin[0]==-1) {
 494             ht_bin[1]=(int)head->addr;
 495             ht_bin[0]=vaddr;
 496           }else if(ht_bin[2]==-1) {
 497             ht_bin[3]=(int)head->addr;
 498             ht_bin[2]=vaddr;
 499           }
 500           //ht_bin[3]=ht_bin[1];
 501           //ht_bin[2]=ht_bin[0];
 502           //ht_bin[1]=(int)head->addr;
 503           //ht_bin[0]=vaddr;
 504         }
 505         return head->addr;
 506       }
 507     }
 508     head=head->next;
 509   }
 510   //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
 511   int r=new_recompile_block(vaddr);
 512   if(r==0) return get_addr(vaddr);
 513   // Execute in unmapped page, generate pagefault execption
 514   Status|=2;
 515   Cause=(vaddr<<31)|0x8;
 516   EPC=(vaddr&1)?vaddr-5:vaddr;
 517   BadVAddr=(vaddr&~1);
 518   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
 519   EntryHi=BadVAddr&0xFFFFE000;
 520   return get_addr_ht(0x80000000);
 521 #endif
 522 }
 523
 524 void clear_all_regs(signed char regmap[])
 525 {
 526   int hr;
 527   for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
 528 }
 529
 530 signed char get_reg(signed char regmap[],int r)
 531 {
 532   int hr;
 533   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
 534   return -1;
 535 }
 536
 537 // Find a register that is available for two consecutive cycles
 538 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
 539 {
 540   int hr;
 541   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
 542   return -1;
 543 }
 544
 545 int count_free_regs(signed char regmap[])
 546 {
 547   int count=0;
 548   int hr;
 549   for(hr=0;hr<HOST_REGS;hr++)
 550   {
 551     if(hr!=EXCLUDE_REG) {
 552       if(regmap[hr]<0) count++;
 553     }
 554   }
 555   return count;
 556 }
 557
 558 void dirty_reg(struct regstat *cur,signed char reg)
 559 {
 560   int hr;
 561   if(!reg) return;
 562   for (hr=0;hr<HOST_REGS;hr++) {
 563     if((cur->regmap[hr]&63)==reg) {
 564       cur->dirty|=1<<hr;
 565     }
 566   }
 567 }
 568
 569 // If we dirty the lower half of a 64 bit register which is now being
 570 // sign-extended, we need to dump the upper half.
 571 // Note: Do this only after completion of the instruction, because
 572 // some instructions may need to read the full 64-bit value even if
 573 // overwriting it (eg SLTI, DSRA32).
 574 static void flush_dirty_uppers(struct regstat *cur)
 575 {
 576   int hr,reg;
 577   for (hr=0;hr<HOST_REGS;hr++) {
 578     if((cur->dirty>>hr)&1) {
 579       reg=cur->regmap[hr];
 580       if(reg>=64)
 581         if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
 582     }
 583   }
 584 }
 585
 586 void set_const(struct regstat *cur,signed char reg,uint64_t value)
 587 {
 588   int hr;
 589   if(!reg) return;
 590   for (hr=0;hr<HOST_REGS;hr++) {
 591     if(cur->regmap[hr]==reg) {
 592       cur->isconst|=1<<hr;
 593       cur->constmap[hr]=value;
 594     }
 595     else if((cur->regmap[hr]^64)==reg) {
 596       cur->isconst|=1<<hr;
 597       cur->constmap[hr]=value>>32;
 598     }
 599   }
 600 }
 601
 602 void clear_const(struct regstat *cur,signed char reg)
 603 {
 604   int hr;
 605   if(!reg) return;
 606   for (hr=0;hr<HOST_REGS;hr++) {
 607     if((cur->regmap[hr]&63)==reg) {
 608       cur->isconst&=~(1<<hr);
 609     }
 610   }
 611 }
 612
 613 int is_const(struct regstat *cur,signed char reg)
 614 {
 615   int hr;
 616   if(reg<0) return 0;
 617   if(!reg) return 1;
 618   for (hr=0;hr<HOST_REGS;hr++) {
 619     if((cur->regmap[hr]&63)==reg) {
 620       return (cur->isconst>>hr)&1;
 621     }
 622   }
 623   return 0;
 624 }
 625 uint64_t get_const(struct regstat *cur,signed char reg)
 626 {
 627   int hr;
 628   if(!reg) return 0;
 629   for (hr=0;hr<HOST_REGS;hr++) {
 630     if(cur->regmap[hr]==reg) {
 631       return cur->constmap[hr];
 632     }
 633   }
 634   printf("Unknown constant in r%d\n",reg);
 635   exit(1);
 636 }
 637
 638 // Least soon needed registers
 639 // Look at the next ten instructions and see which registers
 640 // will be used.  Try not to reallocate these.
 641 void lsn(u_char hsn[], int i, int *preferred_reg)
 642 {
 643   int j;
 644   int b=-1;
 645   for(j=0;j<9;j++)
 646   {
 647     if(i+j>=slen) {
 648       j=slen-i-1;
 649       break;
 650     }
 651     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 652     {
 653       // Don't go past an unconditonal jump
 654       j++;
 655       break;
 656     }
 657   }
 658   for(;j>=0;j--)
 659   {
 660     if(rs1[i+j]) hsn[rs1[i+j]]=j;
 661     if(rs2[i+j]) hsn[rs2[i+j]]=j;
 662     if(rt1[i+j]) hsn[rt1[i+j]]=j;
 663     if(rt2[i+j]) hsn[rt2[i+j]]=j;
 664     if(itype[i+j]==STORE || itype[i+j]==STORELR) {
 665       // Stores can allocate zero
 666       hsn[rs1[i+j]]=j;
 667       hsn[rs2[i+j]]=j;
 668     }
 669     // On some architectures stores need invc_ptr
 670     #if defined(HOST_IMM8)
 671     if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
 672       hsn[INVCP]=j;
 673     }
 674     #endif
 675     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 676     {
 677       hsn[CCREG]=j;
 678       b=j;
 679     }
 680   }
 681   if(b>=0)
 682   {
 683     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 684     {
 685       // Follow first branch
 686       int t=(ba[i+b]-start)>>2;
 687       j=7-b;if(t+j>=slen) j=slen-t-1;
 688       for(;j>=0;j--)
 689       {
 690         if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
 691         if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
 692         //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
 693         //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
 694       }
 695     }
 696     // TODO: preferred register based on backward branch
 697   }
 698   // Delay slot should preferably not overwrite branch conditions or cycle count
 699   if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
 700     if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
 701     if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
 702     hsn[CCREG]=1;
 703     // ...or hash tables
 704     hsn[RHASH]=1;
 705     hsn[RHTBL]=1;
 706   }
 707   // Coprocessor load/store needs FTEMP, even if not declared
 708   if(itype[i]==C1LS||itype[i]==C2LS) {
 709     hsn[FTEMP]=0;
 710   }
 711   // Load L/R also uses FTEMP as a temporary register
 712   if(itype[i]==LOADLR) {
 713     hsn[FTEMP]=0;
 714   }
 715   // Also SWL/SWR/SDL/SDR
 716   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
 717     hsn[FTEMP]=0;
 718   }
 719   // Don't remove the TLB registers either
 720   if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
 721     hsn[TLREG]=0;
 722   }
 723   // Don't remove the miniht registers
 724   if(itype[i]==UJUMP||itype[i]==RJUMP)
 725   {
 726     hsn[RHASH]=0;
 727     hsn[RHTBL]=0;
 728   }
 729 }
 730
 731 // We only want to allocate registers if we're going to use them again soon
 732 int needed_again(int r, int i)
 733 {
 734   int j;
 735   int b=-1;
 736   int rn=10;
 737
 738   if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
 739   {
 740     if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
 741       return 0; // Don't need any registers if exiting the block
 742   }
 743   for(j=0;j<9;j++)
 744   {
 745     if(i+j>=slen) {
 746       j=slen-i-1;
 747       break;
 748     }
 749     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 750     {
 751       // Don't go past an unconditonal jump
 752       j++;
 753       break;
 754     }
 755     if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
 756     {
 757       break;
 758     }
 759   }
 760   for(;j>=1;j--)
 761   {
 762     if(rs1[i+j]==r) rn=j;
 763     if(rs2[i+j]==r) rn=j;
 764     if((unneeded_reg[i+j]>>r)&1) rn=10;
 765     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 766     {
 767       b=j;
 768     }
 769   }
 770   /*
 771   if(b>=0)
 772   {
 773     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 774     {
 775       // Follow first branch
 776       int o=rn;
 777       int t=(ba[i+b]-start)>>2;
 778       j=7-b;if(t+j>=slen) j=slen-t-1;
 779       for(;j>=0;j--)
 780       {
 781         if(!((unneeded_reg[t+j]>>r)&1)) {
 782           if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 783           if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 784         }
 785         else rn=o;
 786       }
 787     }
 788   }*/
 789   if(rn<10) return 1;
 790   return 0;
 791 }
 792
 793 // Try to match register allocations at the end of a loop with those
 794 // at the beginning
 795 int loop_reg(int i, int r, int hr)
 796 {
 797   int j,k;
 798   for(j=0;j<9;j++)
 799   {
 800     if(i+j>=slen) {
 801       j=slen-i-1;
 802       break;
 803     }
 804     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 805     {
 806       // Don't go past an unconditonal jump
 807       j++;
 808       break;
 809     }
 810   }
 811   k=0;
 812   if(i>0){
 813     if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
 814       k--;
 815   }
 816   for(;k<j;k++)
 817   {
 818     if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
 819     if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
 820     if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
 821     {
 822       if(ba[i+k]>=start && ba[i+k]<(start+i*4))
 823       {
 824         int t=(ba[i+k]-start)>>2;
 825         int reg=get_reg(regs[t].regmap_entry,r);
 826         if(reg>=0) return reg;
 827         //reg=get_reg(regs[t+1].regmap_entry,r);
 828         //if(reg>=0) return reg;
 829       }
 830     }
 831   }
 832   return hr;
 833 }
 834
 835
 836 // Allocate every register, preserving source/target regs
 837 void alloc_all(struct regstat *cur,int i)
 838 {
 839   int hr;
 840
 841   for(hr=0;hr<HOST_REGS;hr++) {
 842     if(hr!=EXCLUDE_REG) {
 843       if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
 844          ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
 845       {
 846         cur->regmap[hr]=-1;
 847         cur->dirty&=~(1<<hr);
 848       }
 849       // Don't need zeros
 850       if((cur->regmap[hr]&63)==0)
 851       {
 852         cur->regmap[hr]=-1;
 853         cur->dirty&=~(1<<hr);
 854       }
 855     }
 856   }
 857 }
 858
 859 #ifndef FORCE32
 860 void div64(int64_t dividend,int64_t divisor)
 861 {
 862   lo=dividend/divisor;
 863   hi=dividend%divisor;
 864   //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
 865   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 866 }
 867 void divu64(uint64_t dividend,uint64_t divisor)
 868 {
 869   lo=dividend/divisor;
 870   hi=dividend%divisor;
 871   //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 872   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 873 }
 874
 875 void mult64(uint64_t m1,uint64_t m2)
 876 {
 877    unsigned long long int op1, op2, op3, op4;
 878    unsigned long long int result1, result2, result3, result4;
 879    unsigned long long int temp1, temp2, temp3, temp4;
 880    int sign = 0;
 881
 882    if (m1 < 0)
 883      {
 884     op2 = -m1;
 885     sign = 1 - sign;
 886      }
 887    else op2 = m1;
 888    if (m2 < 0)
 889      {
 890     op4 = -m2;
 891     sign = 1 - sign;
 892      }
 893    else op4 = m2;
 894
 895    op1 = op2 & 0xFFFFFFFF;
 896    op2 = (op2 >> 32) & 0xFFFFFFFF;
 897    op3 = op4 & 0xFFFFFFFF;
 898    op4 = (op4 >> 32) & 0xFFFFFFFF;
 899
 900    temp1 = op1 * op3;
 901    temp2 = (temp1 >> 32) + op1 * op4;
 902    temp3 = op2 * op3;
 903    temp4 = (temp3 >> 32) + op2 * op4;
 904
 905    result1 = temp1 & 0xFFFFFFFF;
 906    result2 = temp2 + (temp3 & 0xFFFFFFFF);
 907    result3 = (result2 >> 32) + temp4;
 908    result4 = (result3 >> 32);
 909
 910    lo = result1 | (result2 << 32);
 911    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
 912    if (sign)
 913      {
 914     hi = ~hi;
 915     if (!lo) hi++;
 916     else lo = ~lo + 1;
 917      }
 918 }
 919
 920 void multu64(uint64_t m1,uint64_t m2)
 921 {
 922    unsigned long long int op1, op2, op3, op4;
 923    unsigned long long int result1, result2, result3, result4;
 924    unsigned long long int temp1, temp2, temp3, temp4;
 925
 926    op1 = m1 & 0xFFFFFFFF;
 927    op2 = (m1 >> 32) & 0xFFFFFFFF;
 928    op3 = m2 & 0xFFFFFFFF;
 929    op4 = (m2 >> 32) & 0xFFFFFFFF;
 930
 931    temp1 = op1 * op3;
 932    temp2 = (temp1 >> 32) + op1 * op4;
 933    temp3 = op2 * op3;
 934    temp4 = (temp3 >> 32) + op2 * op4;
 935
 936    result1 = temp1 & 0xFFFFFFFF;
 937    result2 = temp2 + (temp3 & 0xFFFFFFFF);
 938    result3 = (result2 >> 32) + temp4;
 939    result4 = (result3 >> 32);
 940
 941    lo = result1 | (result2 << 32);
 942    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
 943
 944   //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 945   //                                      ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 946 }
 947
 948 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
 949 {
 950   if(bits) {
 951     original<<=64-bits;
 952     original>>=64-bits;
 953     loaded<<=bits;
 954     original|=loaded;
 955   }
 956   else original=loaded;
 957   return original;
 958 }
 959 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
 960 {
 961   if(bits^56) {
 962     original>>=64-(bits^56);
 963     original<<=64-(bits^56);
 964     loaded>>=bits^56;
 965     original|=loaded;
 966   }
 967   else original=loaded;
 968   return original;
 969 }
 970 #endif
 971
 972 #ifdef __i386__
 973 #include "assem_x86.c"
 974 #endif
 975 #ifdef __x86_64__
 976 #include "assem_x64.c"
 977 #endif
 978 #ifdef __arm__
 979 #include "assem_arm.c"
 980 #endif
 981
 982 // Add virtual address mapping to linked list
 983 void ll_add(struct ll_entry **head,int vaddr,void *addr)
 984 {
 985   struct ll_entry *new_entry;
 986   new_entry=malloc(sizeof(struct ll_entry));
 987   assert(new_entry!=NULL);
 988   new_entry->vaddr=vaddr;
 989   new_entry->reg32=0;
 990   new_entry->addr=addr;
 991   new_entry->next=*head;
 992   *head=new_entry;
 993 }
 994
 995 // Add virtual address mapping for 32-bit compiled block
 996 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
 997 {
 998   ll_add(head,vaddr,addr);
 999 #ifndef FORCE32
1000   (*head)->reg32=reg32;
1001 #endif
1002 }
1003
1004 // Check if an address is already compiled
1005 // but don't return addresses which are about to expire from the cache
1006 void *check_addr(u_int vaddr)
1007 {
1008   u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
1009   if(ht_bin[0]==vaddr) {
1010     if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1011       if(isclean(ht_bin[1])) return (void *)ht_bin[1];
1012   }
1013   if(ht_bin[2]==vaddr) {
1014     if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1015       if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1016   }
1017   u_int page=get_page(vaddr);
1018   struct ll_entry *head;
1019   head=jump_in[page];
1020   while(head!=NULL) {
1021     if(head->vaddr==vaddr&&head->reg32==0) {
1022       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1023         // Update existing entry with current address
1024         if(ht_bin[0]==vaddr) {
1025           ht_bin[1]=(int)head->addr;
1026           return head->addr;
1027         }
1028         if(ht_bin[2]==vaddr) {
1029           ht_bin[3]=(int)head->addr;
1030           return head->addr;
1031         }
1032         // Insert into hash table with low priority.
1033         // Don't evict existing entries, as they are probably
1034         // addresses that are being accessed frequently.
1035         if(ht_bin[0]==-1) {
1036           ht_bin[1]=(int)head->addr;
1037           ht_bin[0]=vaddr;
1038         }else if(ht_bin[2]==-1) {
1039           ht_bin[3]=(int)head->addr;
1040           ht_bin[2]=vaddr;
1041         }
1042         return head->addr;
1043       }
1044     }
1045     head=head->next;
1046   }
1047   return 0;
1048 }
1049
1050 void remove_hash(int vaddr)
1051 {
1052   //printf("remove hash: %x\n",vaddr);
1053   int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1054   if(ht_bin[2]==vaddr) {
1055     ht_bin[2]=ht_bin[3]=-1;
1056   }
1057   if(ht_bin[0]==vaddr) {
1058     ht_bin[0]=ht_bin[2];
1059     ht_bin[1]=ht_bin[3];
1060     ht_bin[2]=ht_bin[3]=-1;
1061   }
1062 }
1063
1064 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1065 {
1066   struct ll_entry *next;
1067   while(*head) {
1068     if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1069        ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1070     {
1071       inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1072       remove_hash((*head)->vaddr);
1073       next=(*head)->next;
1074       free(*head);
1075       *head=next;
1076     }
1077     else
1078     {
1079       head=&((*head)->next);
1080     }
1081   }
1082 }
1083
1084 // Remove all entries from linked list
1085 void ll_clear(struct ll_entry **head)
1086 {
1087   struct ll_entry *cur;
1088   struct ll_entry *next;
1089   if(cur=*head) {
1090     *head=0;
1091     while(cur) {
1092       next=cur->next;
1093       free(cur);
1094       cur=next;
1095     }
1096   }
1097 }
1098
1099 // Dereference the pointers and remove if it matches
1100 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1101 {
1102   while(head) {
1103     int ptr=get_pointer(head->addr);
1104     inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1105     if(((ptr>>shift)==(addr>>shift)) ||
1106        (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1107     {
1108       inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1109       u_int host_addr=(u_int)kill_pointer(head->addr);
1110       #ifdef __arm__
1111         needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1112       #endif
1113     }
1114     head=head->next;
1115   }
1116 }
1117
1118 // This is called when we write to a compiled block (see do_invstub)
1119 void invalidate_page(u_int page)
1120 {
1121   struct ll_entry *head;
1122   struct ll_entry *next;
1123   head=jump_in[page];
1124   jump_in[page]=0;
1125   while(head!=NULL) {
1126     inv_debug("INVALIDATE: %x\n",head->vaddr);
1127     remove_hash(head->vaddr);
1128     next=head->next;
1129     free(head);
1130     head=next;
1131   }
1132   head=jump_out[page];
1133   jump_out[page]=0;
1134   while(head!=NULL) {
1135     inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1136     u_int host_addr=(u_int)kill_pointer(head->addr);
1137     #ifdef __arm__
1138       needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1139     #endif
1140     next=head->next;
1141     free(head);
1142     head=next;
1143   }
1144 }
1145
1146 static void invalidate_block_range(u_int block, u_int first, u_int last)
1147 {
1148   u_int page=get_page(block<<12);
1149   //printf("first=%d last=%d\n",first,last);
1150   invalidate_page(page);
1151   assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1152   assert(last<page+5);
1153   // Invalidate the adjacent pages if a block crosses a 4K boundary
1154   while(first<page) {
1155     invalidate_page(first);
1156     first++;
1157   }
1158   for(first=page+1;first<last;first++) {
1159     invalidate_page(first);
1160   }
1161   #ifdef __arm__
1162     do_clear_cache();
1163   #endif
1164
1165   // Don't trap writes
1166   invalid_code[block]=1;
1167 #ifndef DISABLE_TLB
1168   // If there is a valid TLB entry for this page, remove write protect
1169   if(tlb_LUT_w[block]) {
1170     assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1171     // CHECK: Is this right?
1172     memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1173     u_int real_block=tlb_LUT_w[block]>>12;
1174     invalid_code[real_block]=1;
1175     if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1176   }
1177   else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1178 #endif
1179
1180   #ifdef USE_MINI_HT
1181   memset(mini_ht,-1,sizeof(mini_ht));
1182   #endif
1183 }
1184
1185 void invalidate_block(u_int block)
1186 {
1187   u_int page=get_page(block<<12);
1188   u_int vpage=get_vpage(block<<12);
1189   inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1190   //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1191   u_int first,last;
1192   first=last=page;
1193   struct ll_entry *head;
1194   head=jump_dirty[vpage];
1195   //printf("page=%d vpage=%d\n",page,vpage);
1196   while(head!=NULL) {
1197     u_int start,end;
1198     if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1199       get_bounds((int)head->addr,&start,&end);
1200       //printf("start: %x end: %x\n",start,end);
1201       if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
1202         if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1203           if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1204           if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1205         }
1206       }
1207 #ifndef DISABLE_TLB
1208       if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1209         if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1210           if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1211           if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1212         }
1213       }
1214 #endif
1215     }
1216     head=head->next;
1217   }
1218   invalidate_block_range(block,first,last);
1219 }
1220
1221 void invalidate_addr(u_int addr)
1222 {
1223 #ifdef PCSX
1224   //static int rhits;
1225   // this check is done by the caller
1226   //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
1227   u_int page=get_page(addr);
1228   if(page<2048) { // RAM
1229     struct ll_entry *head;
1230     u_int addr_min=~0, addr_max=0;
1231     int mask=RAM_SIZE-1;
1232     int pg1;
1233     inv_code_start=addr&~0xfff;
1234     inv_code_end=addr|0xfff;
1235     pg1=page;
1236     if (pg1>0) {
1237       // must check previous page too because of spans..
1238       pg1--;
1239       inv_code_start-=0x1000;
1240     }
1241     for(;pg1<=page;pg1++) {
1242       for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
1243         u_int start,end;
1244         get_bounds((int)head->addr,&start,&end);
1245         if((start&mask)<=(addr&mask)&&(addr&mask)<(end&mask)) {
1246           if(start<addr_min) addr_min=start;
1247           if(end>addr_max) addr_max=end;
1248         }
1249         else if(addr<start) {
1250           if(start<inv_code_end)
1251             inv_code_end=start-1;
1252         }
1253         else {
1254           if(end>inv_code_start)
1255             inv_code_start=end;
1256         }
1257       }
1258     }
1259     if (addr_min!=~0) {
1260       inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1261       inv_code_start=inv_code_end=~0;
1262       invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1263       return;
1264     }
1265     else {
1266       inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);//rhits);
1267     }
1268     //rhits=0;
1269     if(page!=0) // FIXME: don't know what's up with page 0 (Klonoa)
1270       return;
1271   }
1272 #endif
1273   invalidate_block(addr>>12);
1274 }
1275
1276 // This is called when loading a save state.
1277 // Anything could have changed, so invalidate everything.
1278 void invalidate_all_pages()
1279 {
1280   u_int page,n;
1281   for(page=0;page<4096;page++)
1282     invalidate_page(page);
1283   for(page=0;page<1048576;page++)
1284     if(!invalid_code[page]) {
1285       restore_candidate[(page&2047)>>3]|=1<<(page&7);
1286       restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1287     }
1288   #ifdef __arm__
1289   __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1290   #endif
1291   #ifdef USE_MINI_HT
1292   memset(mini_ht,-1,sizeof(mini_ht));
1293   #endif
1294   #ifndef DISABLE_TLB
1295   // TLB
1296   for(page=0;page<0x100000;page++) {
1297     if(tlb_LUT_r[page]) {
1298       memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1299       if(!tlb_LUT_w[page]||!invalid_code[page])
1300         memory_map[page]|=0x40000000; // Write protect
1301     }
1302     else memory_map[page]=-1;
1303     if(page==0x80000) page=0xC0000;
1304   }
1305   tlb_hacks();
1306   #endif
1307 }
1308
1309 // Add an entry to jump_out after making a link
1310 void add_link(u_int vaddr,void *src)
1311 {
1312   u_int page=get_page(vaddr);
1313   inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1314   int *ptr=(int *)(src+4);
1315   assert((*ptr&0x0fff0000)==0x059f0000);
1316   ll_add(jump_out+page,vaddr,src);
1317   //int ptr=get_pointer(src);
1318   //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1319 }
1320
1321 // If a code block was found to be unmodified (bit was set in
1322 // restore_candidate) and it remains unmodified (bit is clear
1323 // in invalid_code) then move the entries for that 4K page from
1324 // the dirty list to the clean list.
1325 void clean_blocks(u_int page)
1326 {
1327   struct ll_entry *head;
1328   inv_debug("INV: clean_blocks page=%d\n",page);
1329   head=jump_dirty[page];
1330   while(head!=NULL) {
1331     if(!invalid_code[head->vaddr>>12]) {
1332       // Don't restore blocks which are about to expire from the cache
1333       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1334         u_int start,end;
1335         if(verify_dirty((int)head->addr)) {
1336           //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1337           u_int i;
1338           u_int inv=0;
1339           get_bounds((int)head->addr,&start,&end);
1340           if(start-(u_int)rdram<RAM_SIZE) {
1341             for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1342               inv|=invalid_code[i];
1343             }
1344           }
1345 #ifndef DISABLE_TLB
1346           if((signed int)head->vaddr>=(signed int)0xC0000000) {
1347             u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1348             //printf("addr=%x start=%x end=%x\n",addr,start,end);
1349             if(addr<start||addr>=end) inv=1;
1350           }
1351 #endif
1352           else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1353             inv=1;
1354           }
1355           if(!inv) {
1356             void * clean_addr=(void *)get_clean_addr((int)head->addr);
1357             if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1358               u_int ppage=page;
1359 #ifndef DISABLE_TLB
1360               if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1361 #endif
1362               inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1363               //printf("page=%x, addr=%x\n",page,head->vaddr);
1364               //assert(head->vaddr>>12==(page|0x80000));
1365               ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1366               int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1367               if(!head->reg32) {
1368                 if(ht_bin[0]==head->vaddr) {
1369                   ht_bin[1]=(int)clean_addr; // Replace existing entry
1370                 }
1371                 if(ht_bin[2]==head->vaddr) {
1372                   ht_bin[3]=(int)clean_addr; // Replace existing entry
1373                 }
1374               }
1375             }
1376           }
1377         }
1378       }
1379     }
1380     head=head->next;
1381   }
1382 }
1383
1384
1385 void mov_alloc(struct regstat *current,int i)
1386 {
1387   // Note: Don't need to actually alloc the source registers
1388   if((~current->is32>>rs1[i])&1) {
1389     //alloc_reg64(current,i,rs1[i]);
1390     alloc_reg64(current,i,rt1[i]);
1391     current->is32&=~(1LL<<rt1[i]);
1392   } else {
1393     //alloc_reg(current,i,rs1[i]);
1394     alloc_reg(current,i,rt1[i]);
1395     current->is32|=(1LL<<rt1[i]);
1396   }
1397   clear_const(current,rs1[i]);
1398   clear_const(current,rt1[i]);
1399   dirty_reg(current,rt1[i]);
1400 }
1401
1402 void shiftimm_alloc(struct regstat *current,int i)
1403 {
1404   if(opcode2[i]<=0x3) // SLL/SRL/SRA
1405   {
1406     if(rt1[i]) {
1407       if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1408       else lt1[i]=rs1[i];
1409       alloc_reg(current,i,rt1[i]);
1410       current->is32|=1LL<<rt1[i];
1411       dirty_reg(current,rt1[i]);
1412       if(is_const(current,rs1[i])) {
1413         int v=get_const(current,rs1[i]);
1414         if(opcode2[i]==0x00) set_const(current,rt1[i],v<<imm[i]);
1415         if(opcode2[i]==0x02) set_const(current,rt1[i],(u_int)v>>imm[i]);
1416         if(opcode2[i]==0x03) set_const(current,rt1[i],v>>imm[i]);
1417       }
1418       else clear_const(current,rt1[i]);
1419     }
1420   }
1421   else
1422   {
1423     clear_const(current,rs1[i]);
1424     clear_const(current,rt1[i]);
1425   }
1426
1427   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1428   {
1429     if(rt1[i]) {
1430       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1431       alloc_reg64(current,i,rt1[i]);
1432       current->is32&=~(1LL<<rt1[i]);
1433       dirty_reg(current,rt1[i]);
1434     }
1435   }
1436   if(opcode2[i]==0x3c) // DSLL32
1437   {
1438     if(rt1[i]) {
1439       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1440       alloc_reg64(current,i,rt1[i]);
1441       current->is32&=~(1LL<<rt1[i]);
1442       dirty_reg(current,rt1[i]);
1443     }
1444   }
1445   if(opcode2[i]==0x3e) // DSRL32
1446   {
1447     if(rt1[i]) {
1448       alloc_reg64(current,i,rs1[i]);
1449       if(imm[i]==32) {
1450         alloc_reg64(current,i,rt1[i]);
1451         current->is32&=~(1LL<<rt1[i]);
1452       } else {
1453         alloc_reg(current,i,rt1[i]);
1454         current->is32|=1LL<<rt1[i];
1455       }
1456       dirty_reg(current,rt1[i]);
1457     }
1458   }
1459   if(opcode2[i]==0x3f) // DSRA32
1460   {
1461     if(rt1[i]) {
1462       alloc_reg64(current,i,rs1[i]);
1463       alloc_reg(current,i,rt1[i]);
1464       current->is32|=1LL<<rt1[i];
1465       dirty_reg(current,rt1[i]);
1466     }
1467   }
1468 }
1469
1470 void shift_alloc(struct regstat *current,int i)
1471 {
1472   if(rt1[i]) {
1473     if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1474     {
1475       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1476       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1477       alloc_reg(current,i,rt1[i]);
1478       if(rt1[i]==rs2[i]) {
1479         alloc_reg_temp(current,i,-1);
1480         minimum_free_regs[i]=1;
1481       }
1482       current->is32|=1LL<<rt1[i];
1483     } else { // DSLLV/DSRLV/DSRAV
1484       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1485       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1486       alloc_reg64(current,i,rt1[i]);
1487       current->is32&=~(1LL<<rt1[i]);
1488       if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1489       {
1490         alloc_reg_temp(current,i,-1);
1491         minimum_free_regs[i]=1;
1492       }
1493     }
1494     clear_const(current,rs1[i]);
1495     clear_const(current,rs2[i]);
1496     clear_const(current,rt1[i]);
1497     dirty_reg(current,rt1[i]);
1498   }
1499 }
1500
1501 void alu_alloc(struct regstat *current,int i)
1502 {
1503   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1504     if(rt1[i]) {
1505       if(rs1[i]&&rs2[i]) {
1506         alloc_reg(current,i,rs1[i]);
1507         alloc_reg(current,i,rs2[i]);
1508       }
1509       else {
1510         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1511         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1512       }
1513       alloc_reg(current,i,rt1[i]);
1514     }
1515     current->is32|=1LL<<rt1[i];
1516   }
1517   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1518     if(rt1[i]) {
1519       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1520       {
1521         alloc_reg64(current,i,rs1[i]);
1522         alloc_reg64(current,i,rs2[i]);
1523         alloc_reg(current,i,rt1[i]);
1524       } else {
1525         alloc_reg(current,i,rs1[i]);
1526         alloc_reg(current,i,rs2[i]);
1527         alloc_reg(current,i,rt1[i]);
1528       }
1529     }
1530     current->is32|=1LL<<rt1[i];
1531   }
1532   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1533     if(rt1[i]) {
1534       if(rs1[i]&&rs2[i]) {
1535         alloc_reg(current,i,rs1[i]);
1536         alloc_reg(current,i,rs2[i]);
1537       }
1538       else
1539       {
1540         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1541         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1542       }
1543       alloc_reg(current,i,rt1[i]);
1544       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1545       {
1546         if(!((current->uu>>rt1[i])&1)) {
1547           alloc_reg64(current,i,rt1[i]);
1548         }
1549         if(get_reg(current->regmap,rt1[i]|64)>=0) {
1550           if(rs1[i]&&rs2[i]) {
1551             alloc_reg64(current,i,rs1[i]);
1552             alloc_reg64(current,i,rs2[i]);
1553           }
1554           else
1555           {
1556             // Is is really worth it to keep 64-bit values in registers?
1557             #ifdef NATIVE_64BIT
1558             if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1559             if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1560             #endif
1561           }
1562         }
1563         current->is32&=~(1LL<<rt1[i]);
1564       } else {
1565         current->is32|=1LL<<rt1[i];
1566       }
1567     }
1568   }
1569   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1570     if(rt1[i]) {
1571       if(rs1[i]&&rs2[i]) {
1572         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1573           alloc_reg64(current,i,rs1[i]);
1574           alloc_reg64(current,i,rs2[i]);
1575           alloc_reg64(current,i,rt1[i]);
1576         } else {
1577           alloc_reg(current,i,rs1[i]);
1578           alloc_reg(current,i,rs2[i]);
1579           alloc_reg(current,i,rt1[i]);
1580         }
1581       }
1582       else {
1583         alloc_reg(current,i,rt1[i]);
1584         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1585           // DADD used as move, or zeroing
1586           // If we have a 64-bit source, then make the target 64 bits too
1587           if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1588             if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1589             alloc_reg64(current,i,rt1[i]);
1590           } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1591             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1592             alloc_reg64(current,i,rt1[i]);
1593           }
1594           if(opcode2[i]>=0x2e&&rs2[i]) {
1595             // DSUB used as negation - 64-bit result
1596             // If we have a 32-bit register, extend it to 64 bits
1597             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1598             alloc_reg64(current,i,rt1[i]);
1599           }
1600         }
1601       }
1602       if(rs1[i]&&rs2[i]) {
1603         current->is32&=~(1LL<<rt1[i]);
1604       } else if(rs1[i]) {
1605         current->is32&=~(1LL<<rt1[i]);
1606         if((current->is32>>rs1[i])&1)
1607           current->is32|=1LL<<rt1[i];
1608       } else if(rs2[i]) {
1609         current->is32&=~(1LL<<rt1[i]);
1610         if((current->is32>>rs2[i])&1)
1611           current->is32|=1LL<<rt1[i];
1612       } else {
1613         current->is32|=1LL<<rt1[i];
1614       }
1615     }
1616   }
1617   clear_const(current,rs1[i]);
1618   clear_const(current,rs2[i]);
1619   clear_const(current,rt1[i]);
1620   dirty_reg(current,rt1[i]);
1621 }
1622
1623 void imm16_alloc(struct regstat *current,int i)
1624 {
1625   if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1626   else lt1[i]=rs1[i];
1627   if(rt1[i]) alloc_reg(current,i,rt1[i]);
1628   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1629     current->is32&=~(1LL<<rt1[i]);
1630     if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1631       // TODO: Could preserve the 32-bit flag if the immediate is zero
1632       alloc_reg64(current,i,rt1[i]);
1633       alloc_reg64(current,i,rs1[i]);
1634     }
1635     clear_const(current,rs1[i]);
1636     clear_const(current,rt1[i]);
1637   }
1638   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1639     if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1640     current->is32|=1LL<<rt1[i];
1641     clear_const(current,rs1[i]);
1642     clear_const(current,rt1[i]);
1643   }
1644   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1645     if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1646       if(rs1[i]!=rt1[i]) {
1647         if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1648         alloc_reg64(current,i,rt1[i]);
1649         current->is32&=~(1LL<<rt1[i]);
1650       }
1651     }
1652     else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1653     if(is_const(current,rs1[i])) {
1654       int v=get_const(current,rs1[i]);
1655       if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1656       if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1657       if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1658     }
1659     else clear_const(current,rt1[i]);
1660   }
1661   else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1662     if(is_const(current,rs1[i])) {
1663       int v=get_const(current,rs1[i]);
1664       set_const(current,rt1[i],v+imm[i]);
1665     }
1666     else clear_const(current,rt1[i]);
1667     current->is32|=1LL<<rt1[i];
1668   }
1669   else {
1670     set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1671     current->is32|=1LL<<rt1[i];
1672   }
1673   dirty_reg(current,rt1[i]);
1674 }
1675
1676 void load_alloc(struct regstat *current,int i)
1677 {
1678   clear_const(current,rt1[i]);
1679   //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1680   if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1681   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1682   if(rt1[i]&&!((current->u>>rt1[i])&1)) {
1683     alloc_reg(current,i,rt1[i]);
1684     assert(get_reg(current->regmap,rt1[i])>=0);
1685     if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1686     {
1687       current->is32&=~(1LL<<rt1[i]);
1688       alloc_reg64(current,i,rt1[i]);
1689     }
1690     else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1691     {
1692       current->is32&=~(1LL<<rt1[i]);
1693       alloc_reg64(current,i,rt1[i]);
1694       alloc_all(current,i);
1695       alloc_reg64(current,i,FTEMP);
1696       minimum_free_regs[i]=HOST_REGS;
1697     }
1698     else current->is32|=1LL<<rt1[i];
1699     dirty_reg(current,rt1[i]);
1700     // If using TLB, need a register for pointer to the mapping table
1701     if(using_tlb) alloc_reg(current,i,TLREG);
1702     // LWL/LWR need a temporary register for the old value
1703     if(opcode[i]==0x22||opcode[i]==0x26)
1704     {
1705       alloc_reg(current,i,FTEMP);
1706       alloc_reg_temp(current,i,-1);
1707       minimum_free_regs[i]=1;
1708     }
1709   }
1710   else
1711   {
1712     // Load to r0 or unneeded register (dummy load)
1713     // but we still need a register to calculate the address
1714     if(opcode[i]==0x22||opcode[i]==0x26)
1715     {
1716       alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1717     }
1718     // If using TLB, need a register for pointer to the mapping table
1719     if(using_tlb) alloc_reg(current,i,TLREG);
1720     alloc_reg_temp(current,i,-1);
1721     minimum_free_regs[i]=1;
1722     if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1723     {
1724       alloc_all(current,i);
1725       alloc_reg64(current,i,FTEMP);
1726       minimum_free_regs[i]=HOST_REGS;
1727     }
1728   }
1729 }
1730
1731 void store_alloc(struct regstat *current,int i)
1732 {
1733   clear_const(current,rs2[i]);
1734   if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1735   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1736   alloc_reg(current,i,rs2[i]);
1737   if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1738     alloc_reg64(current,i,rs2[i]);
1739     if(rs2[i]) alloc_reg(current,i,FTEMP);
1740   }
1741   // If using TLB, need a register for pointer to the mapping table
1742   if(using_tlb) alloc_reg(current,i,TLREG);
1743   #if defined(HOST_IMM8)
1744   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1745   else alloc_reg(current,i,INVCP);
1746   #endif
1747   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1748     alloc_reg(current,i,FTEMP);
1749   }
1750   // We need a temporary register for address generation
1751   alloc_reg_temp(current,i,-1);
1752   minimum_free_regs[i]=1;
1753 }
1754
1755 void c1ls_alloc(struct regstat *current,int i)
1756 {
1757   //clear_const(current,rs1[i]); // FIXME
1758   clear_const(current,rt1[i]);
1759   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1760   alloc_reg(current,i,CSREG); // Status
1761   alloc_reg(current,i,FTEMP);
1762   if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1763     alloc_reg64(current,i,FTEMP);
1764   }
1765   // If using TLB, need a register for pointer to the mapping table
1766   if(using_tlb) alloc_reg(current,i,TLREG);
1767   #if defined(HOST_IMM8)
1768   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1769   else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1770     alloc_reg(current,i,INVCP);
1771   #endif
1772   // We need a temporary register for address generation
1773   alloc_reg_temp(current,i,-1);
1774 }
1775
1776 void c2ls_alloc(struct regstat *current,int i)
1777 {
1778   clear_const(current,rt1[i]);
1779   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1780   alloc_reg(current,i,FTEMP);
1781   // If using TLB, need a register for pointer to the mapping table
1782   if(using_tlb) alloc_reg(current,i,TLREG);
1783   #if defined(HOST_IMM8)
1784   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1785   else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1786     alloc_reg(current,i,INVCP);
1787   #endif
1788   // We need a temporary register for address generation
1789   alloc_reg_temp(current,i,-1);
1790   minimum_free_regs[i]=1;
1791 }
1792
1793 #ifndef multdiv_alloc
1794 void multdiv_alloc(struct regstat *current,int i)
1795 {
1796   //  case 0x18: MULT
1797   //  case 0x19: MULTU
1798   //  case 0x1A: DIV
1799   //  case 0x1B: DIVU
1800   //  case 0x1C: DMULT
1801   //  case 0x1D: DMULTU
1802   //  case 0x1E: DDIV
1803   //  case 0x1F: DDIVU
1804   clear_const(current,rs1[i]);
1805   clear_const(current,rs2[i]);
1806   if(rs1[i]&&rs2[i])
1807   {
1808     if((opcode2[i]&4)==0) // 32-bit
1809     {
1810       current->u&=~(1LL<<HIREG);
1811       current->u&=~(1LL<<LOREG);
1812       alloc_reg(current,i,HIREG);
1813       alloc_reg(current,i,LOREG);
1814       alloc_reg(current,i,rs1[i]);
1815       alloc_reg(current,i,rs2[i]);
1816       current->is32|=1LL<<HIREG;
1817       current->is32|=1LL<<LOREG;
1818       dirty_reg(current,HIREG);
1819       dirty_reg(current,LOREG);
1820     }
1821     else // 64-bit
1822     {
1823       current->u&=~(1LL<<HIREG);
1824       current->u&=~(1LL<<LOREG);
1825       current->uu&=~(1LL<<HIREG);
1826       current->uu&=~(1LL<<LOREG);
1827       alloc_reg64(current,i,HIREG);
1828       //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1829       alloc_reg64(current,i,rs1[i]);
1830       alloc_reg64(current,i,rs2[i]);
1831       alloc_all(current,i);
1832       current->is32&=~(1LL<<HIREG);
1833       current->is32&=~(1LL<<LOREG);
1834       dirty_reg(current,HIREG);
1835       dirty_reg(current,LOREG);
1836       minimum_free_regs[i]=HOST_REGS;
1837     }
1838   }
1839   else
1840   {
1841     // Multiply by zero is zero.
1842     // MIPS does not have a divide by zero exception.
1843     // The result is undefined, we return zero.
1844     alloc_reg(current,i,HIREG);
1845     alloc_reg(current,i,LOREG);
1846     current->is32|=1LL<<HIREG;
1847     current->is32|=1LL<<LOREG;
1848     dirty_reg(current,HIREG);
1849     dirty_reg(current,LOREG);
1850   }
1851 }
1852 #endif
1853
1854 void cop0_alloc(struct regstat *current,int i)
1855 {
1856   if(opcode2[i]==0) // MFC0
1857   {
1858     if(rt1[i]) {
1859       clear_const(current,rt1[i]);
1860       alloc_all(current,i);
1861       alloc_reg(current,i,rt1[i]);
1862       current->is32|=1LL<<rt1[i];
1863       dirty_reg(current,rt1[i]);
1864     }
1865   }
1866   else if(opcode2[i]==4) // MTC0
1867   {
1868     if(rs1[i]){
1869       clear_const(current,rs1[i]);
1870       alloc_reg(current,i,rs1[i]);
1871       alloc_all(current,i);
1872     }
1873     else {
1874       alloc_all(current,i); // FIXME: Keep r0
1875       current->u&=~1LL;
1876       alloc_reg(current,i,0);
1877     }
1878   }
1879   else
1880   {
1881     // TLBR/TLBWI/TLBWR/TLBP/ERET
1882     assert(opcode2[i]==0x10);
1883     alloc_all(current,i);
1884   }
1885   minimum_free_regs[i]=HOST_REGS;
1886 }
1887
1888 void cop1_alloc(struct regstat *current,int i)
1889 {
1890   alloc_reg(current,i,CSREG); // Load status
1891   if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1892   {
1893     if(rt1[i]){
1894       clear_const(current,rt1[i]);
1895       if(opcode2[i]==1) {
1896         alloc_reg64(current,i,rt1[i]); // DMFC1
1897         current->is32&=~(1LL<<rt1[i]);
1898       }else{
1899         alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1900         current->is32|=1LL<<rt1[i];
1901       }
1902       dirty_reg(current,rt1[i]);
1903     }
1904     alloc_reg_temp(current,i,-1);
1905   }
1906   else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1907   {
1908     if(rs1[i]){
1909       clear_const(current,rs1[i]);
1910       if(opcode2[i]==5)
1911         alloc_reg64(current,i,rs1[i]); // DMTC1
1912       else
1913         alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1914       alloc_reg_temp(current,i,-1);
1915     }
1916     else {
1917       current->u&=~1LL;
1918       alloc_reg(current,i,0);
1919       alloc_reg_temp(current,i,-1);
1920     }
1921   }
1922   minimum_free_regs[i]=1;
1923 }
1924 void fconv_alloc(struct regstat *current,int i)
1925 {
1926   alloc_reg(current,i,CSREG); // Load status
1927   alloc_reg_temp(current,i,-1);
1928   minimum_free_regs[i]=1;
1929 }
1930 void float_alloc(struct regstat *current,int i)
1931 {
1932   alloc_reg(current,i,CSREG); // Load status
1933   alloc_reg_temp(current,i,-1);
1934   minimum_free_regs[i]=1;
1935 }
1936 void c2op_alloc(struct regstat *current,int i)
1937 {
1938   alloc_reg_temp(current,i,-1);
1939 }
1940 void fcomp_alloc(struct regstat *current,int i)
1941 {
1942   alloc_reg(current,i,CSREG); // Load status
1943   alloc_reg(current,i,FSREG); // Load flags
1944   dirty_reg(current,FSREG); // Flag will be modified
1945   alloc_reg_temp(current,i,-1);
1946   minimum_free_regs[i]=1;
1947 }
1948
1949 void syscall_alloc(struct regstat *current,int i)
1950 {
1951   alloc_cc(current,i);
1952   dirty_reg(current,CCREG);
1953   alloc_all(current,i);
1954   minimum_free_regs[i]=HOST_REGS;
1955   current->isconst=0;
1956 }
1957
1958 void delayslot_alloc(struct regstat *current,int i)
1959 {
1960   switch(itype[i]) {
1961     case UJUMP:
1962     case CJUMP:
1963     case SJUMP:
1964     case RJUMP:
1965     case FJUMP:
1966     case SYSCALL:
1967     case HLECALL:
1968     case SPAN:
1969       assem_debug("jump in the delay slot.  this shouldn't happen.\n");//exit(1);
1970       printf("Disabled speculative precompilation\n");
1971       stop_after_jal=1;
1972       break;
1973     case IMM16:
1974       imm16_alloc(current,i);
1975       break;
1976     case LOAD:
1977     case LOADLR:
1978       load_alloc(current,i);
1979       break;
1980     case STORE:
1981     case STORELR:
1982       store_alloc(current,i);
1983       break;
1984     case ALU:
1985       alu_alloc(current,i);
1986       break;
1987     case SHIFT:
1988       shift_alloc(current,i);
1989       break;
1990     case MULTDIV:
1991       multdiv_alloc(current,i);
1992       break;
1993     case SHIFTIMM:
1994       shiftimm_alloc(current,i);
1995       break;
1996     case MOV:
1997       mov_alloc(current,i);
1998       break;
1999     case COP0:
2000       cop0_alloc(current,i);
2001       break;
2002     case COP1:
2003     case COP2:
2004       cop1_alloc(current,i);
2005       break;
2006     case C1LS:
2007       c1ls_alloc(current,i);
2008       break;
2009     case C2LS:
2010       c2ls_alloc(current,i);
2011       break;
2012     case FCONV:
2013       fconv_alloc(current,i);
2014       break;
2015     case FLOAT:
2016       float_alloc(current,i);
2017       break;
2018     case FCOMP:
2019       fcomp_alloc(current,i);
2020       break;
2021     case C2OP:
2022       c2op_alloc(current,i);
2023       break;
2024   }
2025 }
2026
2027 // Special case where a branch and delay slot span two pages in virtual memory
2028 static void pagespan_alloc(struct regstat *current,int i)
2029 {
2030   current->isconst=0;
2031   current->wasconst=0;
2032   regs[i].wasconst=0;
2033   minimum_free_regs[i]=HOST_REGS;
2034   alloc_all(current,i);
2035   alloc_cc(current,i);
2036   dirty_reg(current,CCREG);
2037   if(opcode[i]==3) // JAL
2038   {
2039     alloc_reg(current,i,31);
2040     dirty_reg(current,31);
2041   }
2042   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
2043   {
2044     alloc_reg(current,i,rs1[i]);
2045     if (rt1[i]!=0) {
2046       alloc_reg(current,i,rt1[i]);
2047       dirty_reg(current,rt1[i]);
2048     }
2049   }
2050   if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
2051   {
2052     if(rs1[i]) alloc_reg(current,i,rs1[i]);
2053     if(rs2[i]) alloc_reg(current,i,rs2[i]);
2054     if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
2055     {
2056       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2057       if(rs2[i]) alloc_reg64(current,i,rs2[i]);
2058     }
2059   }
2060   else
2061   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
2062   {
2063     if(rs1[i]) alloc_reg(current,i,rs1[i]);
2064     if(!((current->is32>>rs1[i])&1))
2065     {
2066       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2067     }
2068   }
2069   else
2070   if(opcode[i]==0x11) // BC1
2071   {
2072     alloc_reg(current,i,FSREG);
2073     alloc_reg(current,i,CSREG);
2074   }
2075   //else ...
2076 }
2077
2078 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
2079 {
2080   stubs[stubcount][0]=type;
2081   stubs[stubcount][1]=addr;
2082   stubs[stubcount][2]=retaddr;
2083   stubs[stubcount][3]=a;
2084   stubs[stubcount][4]=b;
2085   stubs[stubcount][5]=c;
2086   stubs[stubcount][6]=d;
2087   stubs[stubcount][7]=e;
2088   stubcount++;
2089 }
2090
2091 // Write out a single register
2092 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2093 {
2094   int hr;
2095   for(hr=0;hr<HOST_REGS;hr++) {
2096     if(hr!=EXCLUDE_REG) {
2097       if((regmap[hr]&63)==r) {
2098         if((dirty>>hr)&1) {
2099           if(regmap[hr]<64) {
2100             emit_storereg(r,hr);
2101 #ifndef FORCE32
2102             if((is32>>regmap[hr])&1) {
2103               emit_sarimm(hr,31,hr);
2104               emit_storereg(r|64,hr);
2105             }
2106 #endif
2107           }else{
2108             emit_storereg(r|64,hr);
2109           }
2110         }
2111       }
2112     }
2113   }
2114 }
2115
2116 int mchecksum()
2117 {
2118   //if(!tracedebug) return 0;
2119   int i;
2120   int sum=0;
2121   for(i=0;i<2097152;i++) {
2122     unsigned int temp=sum;
2123     sum<<=1;
2124     sum|=(~temp)>>31;
2125     sum^=((u_int *)rdram)[i];
2126   }
2127   return sum;
2128 }
2129 int rchecksum()
2130 {
2131   int i;
2132   int sum=0;
2133   for(i=0;i<64;i++)
2134     sum^=((u_int *)reg)[i];
2135   return sum;
2136 }
2137 void rlist()
2138 {
2139   int i;
2140   printf("TRACE: ");
2141   for(i=0;i<32;i++)
2142     printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2143   printf("\n");
2144 #ifndef DISABLE_COP1
2145   printf("TRACE: ");
2146   for(i=0;i<32;i++)
2147     printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2148   printf("\n");
2149 #endif
2150 }
2151
2152 void enabletrace()
2153 {
2154   tracedebug=1;
2155 }
2156
2157 void memdebug(int i)
2158 {
2159   //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2160   //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2161   //rlist();
2162   //if(tracedebug) {
2163   //if(Count>=-2084597794) {
2164   if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2165   //if(0) {
2166     printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2167     //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2168     //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2169     rlist();
2170     #ifdef __i386__
2171     printf("TRACE: %x\n",(&i)[-1]);
2172     #endif
2173     #ifdef __arm__
2174     int j;
2175     printf("TRACE: %x \n",(&j)[10]);
2176     printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2177     #endif
2178     //fflush(stdout);
2179   }
2180   //printf("TRACE: %x\n",(&i)[-1]);
2181 }
2182
2183 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2184 {
2185   printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2186 }
2187
2188 void alu_assemble(int i,struct regstat *i_regs)
2189 {
2190   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2191     if(rt1[i]) {
2192       signed char s1,s2,t;
2193       t=get_reg(i_regs->regmap,rt1[i]);
2194       if(t>=0) {
2195         s1=get_reg(i_regs->regmap,rs1[i]);
2196         s2=get_reg(i_regs->regmap,rs2[i]);
2197         if(rs1[i]&&rs2[i]) {
2198           assert(s1>=0);
2199           assert(s2>=0);
2200           if(opcode2[i]&2) emit_sub(s1,s2,t);
2201           else emit_add(s1,s2,t);
2202         }
2203         else if(rs1[i]) {
2204           if(s1>=0) emit_mov(s1,t);
2205           else emit_loadreg(rs1[i],t);
2206         }
2207         else if(rs2[i]) {
2208           if(s2>=0) {
2209             if(opcode2[i]&2) emit_neg(s2,t);
2210             else emit_mov(s2,t);
2211           }
2212           else {
2213             emit_loadreg(rs2[i],t);
2214             if(opcode2[i]&2) emit_neg(t,t);
2215           }
2216         }
2217         else emit_zeroreg(t);
2218       }
2219     }
2220   }
2221   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2222     if(rt1[i]) {
2223       signed char s1l,s2l,s1h,s2h,tl,th;
2224       tl=get_reg(i_regs->regmap,rt1[i]);
2225       th=get_reg(i_regs->regmap,rt1[i]|64);
2226       if(tl>=0) {
2227         s1l=get_reg(i_regs->regmap,rs1[i]);
2228         s2l=get_reg(i_regs->regmap,rs2[i]);
2229         s1h=get_reg(i_regs->regmap,rs1[i]|64);
2230         s2h=get_reg(i_regs->regmap,rs2[i]|64);
2231         if(rs1[i]&&rs2[i]) {
2232           assert(s1l>=0);
2233           assert(s2l>=0);
2234           if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2235           else emit_adds(s1l,s2l,tl);
2236           if(th>=0) {
2237             #ifdef INVERTED_CARRY
2238             if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2239             #else
2240             if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2241             #endif
2242             else emit_add(s1h,s2h,th);
2243           }
2244         }
2245         else if(rs1[i]) {
2246           if(s1l>=0) emit_mov(s1l,tl);
2247           else emit_loadreg(rs1[i],tl);
2248           if(th>=0) {
2249             if(s1h>=0) emit_mov(s1h,th);
2250             else emit_loadreg(rs1[i]|64,th);
2251           }
2252         }
2253         else if(rs2[i]) {
2254           if(s2l>=0) {
2255             if(opcode2[i]&2) emit_negs(s2l,tl);
2256             else emit_mov(s2l,tl);
2257           }
2258           else {
2259             emit_loadreg(rs2[i],tl);
2260             if(opcode2[i]&2) emit_negs(tl,tl);
2261           }
2262           if(th>=0) {
2263             #ifdef INVERTED_CARRY
2264             if(s2h>=0) emit_mov(s2h,th);
2265             else emit_loadreg(rs2[i]|64,th);
2266             if(opcode2[i]&2) {
2267               emit_adcimm(-1,th); // x86 has inverted carry flag
2268               emit_not(th,th);
2269             }
2270             #else
2271             if(opcode2[i]&2) {
2272               if(s2h>=0) emit_rscimm(s2h,0,th);
2273               else {
2274                 emit_loadreg(rs2[i]|64,th);
2275                 emit_rscimm(th,0,th);
2276               }
2277             }else{
2278               if(s2h>=0) emit_mov(s2h,th);
2279               else emit_loadreg(rs2[i]|64,th);
2280             }
2281             #endif
2282           }
2283         }
2284         else {
2285           emit_zeroreg(tl);
2286           if(th>=0) emit_zeroreg(th);
2287         }
2288       }
2289     }
2290   }
2291   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2292     if(rt1[i]) {
2293       signed char s1l,s1h,s2l,s2h,t;
2294       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2295       {
2296         t=get_reg(i_regs->regmap,rt1[i]);
2297         //assert(t>=0);
2298         if(t>=0) {
2299           s1l=get_reg(i_regs->regmap,rs1[i]);
2300           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2301           s2l=get_reg(i_regs->regmap,rs2[i]);
2302           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2303           if(rs2[i]==0) // rx<r0
2304           {
2305             assert(s1h>=0);
2306             if(opcode2[i]==0x2a) // SLT
2307               emit_shrimm(s1h,31,t);
2308             else // SLTU (unsigned can not be less than zero)
2309               emit_zeroreg(t);
2310           }
2311           else if(rs1[i]==0) // r0<rx
2312           {
2313             assert(s2h>=0);
2314             if(opcode2[i]==0x2a) // SLT
2315               emit_set_gz64_32(s2h,s2l,t);
2316             else // SLTU (set if not zero)
2317               emit_set_nz64_32(s2h,s2l,t);
2318           }
2319           else {
2320             assert(s1l>=0);assert(s1h>=0);
2321             assert(s2l>=0);assert(s2h>=0);
2322             if(opcode2[i]==0x2a) // SLT
2323               emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2324             else // SLTU
2325               emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2326           }
2327         }
2328       } else {
2329         t=get_reg(i_regs->regmap,rt1[i]);
2330         //assert(t>=0);
2331         if(t>=0) {
2332           s1l=get_reg(i_regs->regmap,rs1[i]);
2333           s2l=get_reg(i_regs->regmap,rs2[i]);
2334           if(rs2[i]==0) // rx<r0
2335           {
2336             assert(s1l>=0);
2337             if(opcode2[i]==0x2a) // SLT
2338               emit_shrimm(s1l,31,t);
2339             else // SLTU (unsigned can not be less than zero)
2340               emit_zeroreg(t);
2341           }
2342           else if(rs1[i]==0) // r0<rx
2343           {
2344             assert(s2l>=0);
2345             if(opcode2[i]==0x2a) // SLT
2346               emit_set_gz32(s2l,t);
2347             else // SLTU (set if not zero)
2348               emit_set_nz32(s2l,t);
2349           }
2350           else{
2351             assert(s1l>=0);assert(s2l>=0);
2352             if(opcode2[i]==0x2a) // SLT
2353               emit_set_if_less32(s1l,s2l,t);
2354             else // SLTU
2355               emit_set_if_carry32(s1l,s2l,t);
2356           }
2357         }
2358       }
2359     }
2360   }
2361   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2362     if(rt1[i]) {
2363       signed char s1l,s1h,s2l,s2h,th,tl;
2364       tl=get_reg(i_regs->regmap,rt1[i]);
2365       th=get_reg(i_regs->regmap,rt1[i]|64);
2366       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2367       {
2368         assert(tl>=0);
2369         if(tl>=0) {
2370           s1l=get_reg(i_regs->regmap,rs1[i]);
2371           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2372           s2l=get_reg(i_regs->regmap,rs2[i]);
2373           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2374           if(rs1[i]&&rs2[i]) {
2375             assert(s1l>=0);assert(s1h>=0);
2376             assert(s2l>=0);assert(s2h>=0);
2377             if(opcode2[i]==0x24) { // AND
2378               emit_and(s1l,s2l,tl);
2379               emit_and(s1h,s2h,th);
2380             } else
2381             if(opcode2[i]==0x25) { // OR
2382               emit_or(s1l,s2l,tl);
2383               emit_or(s1h,s2h,th);
2384             } else
2385             if(opcode2[i]==0x26) { // XOR
2386               emit_xor(s1l,s2l,tl);
2387               emit_xor(s1h,s2h,th);
2388             } else
2389             if(opcode2[i]==0x27) { // NOR
2390               emit_or(s1l,s2l,tl);
2391               emit_or(s1h,s2h,th);
2392               emit_not(tl,tl);
2393               emit_not(th,th);
2394             }
2395           }
2396           else
2397           {
2398             if(opcode2[i]==0x24) { // AND
2399               emit_zeroreg(tl);
2400               emit_zeroreg(th);
2401             } else
2402             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2403               if(rs1[i]){
2404                 if(s1l>=0) emit_mov(s1l,tl);
2405                 else emit_loadreg(rs1[i],tl);
2406                 if(s1h>=0) emit_mov(s1h,th);
2407                 else emit_loadreg(rs1[i]|64,th);
2408               }
2409               else
2410               if(rs2[i]){
2411                 if(s2l>=0) emit_mov(s2l,tl);
2412                 else emit_loadreg(rs2[i],tl);
2413                 if(s2h>=0) emit_mov(s2h,th);
2414                 else emit_loadreg(rs2[i]|64,th);
2415               }
2416               else{
2417                 emit_zeroreg(tl);
2418                 emit_zeroreg(th);
2419               }
2420             } else
2421             if(opcode2[i]==0x27) { // NOR
2422               if(rs1[i]){
2423                 if(s1l>=0) emit_not(s1l,tl);
2424                 else{
2425                   emit_loadreg(rs1[i],tl);
2426                   emit_not(tl,tl);
2427                 }
2428                 if(s1h>=0) emit_not(s1h,th);
2429                 else{
2430                   emit_loadreg(rs1[i]|64,th);
2431                   emit_not(th,th);
2432                 }
2433               }
2434               else
2435               if(rs2[i]){
2436                 if(s2l>=0) emit_not(s2l,tl);
2437                 else{
2438                   emit_loadreg(rs2[i],tl);
2439                   emit_not(tl,tl);
2440                 }
2441                 if(s2h>=0) emit_not(s2h,th);
2442                 else{
2443                   emit_loadreg(rs2[i]|64,th);
2444                   emit_not(th,th);
2445                 }
2446               }
2447               else {
2448                 emit_movimm(-1,tl);
2449                 emit_movimm(-1,th);
2450               }
2451             }
2452           }
2453         }
2454       }
2455       else
2456       {
2457         // 32 bit
2458         if(tl>=0) {
2459           s1l=get_reg(i_regs->regmap,rs1[i]);
2460           s2l=get_reg(i_regs->regmap,rs2[i]);
2461           if(rs1[i]&&rs2[i]) {
2462             assert(s1l>=0);
2463             assert(s2l>=0);
2464             if(opcode2[i]==0x24) { // AND
2465               emit_and(s1l,s2l,tl);
2466             } else
2467             if(opcode2[i]==0x25) { // OR
2468               emit_or(s1l,s2l,tl);
2469             } else
2470             if(opcode2[i]==0x26) { // XOR
2471               emit_xor(s1l,s2l,tl);
2472             } else
2473             if(opcode2[i]==0x27) { // NOR
2474               emit_or(s1l,s2l,tl);
2475               emit_not(tl,tl);
2476             }
2477           }
2478           else
2479           {
2480             if(opcode2[i]==0x24) { // AND
2481               emit_zeroreg(tl);
2482             } else
2483             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2484               if(rs1[i]){
2485                 if(s1l>=0) emit_mov(s1l,tl);
2486                 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2487               }
2488               else
2489               if(rs2[i]){
2490                 if(s2l>=0) emit_mov(s2l,tl);
2491                 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2492               }
2493               else emit_zeroreg(tl);
2494             } else
2495             if(opcode2[i]==0x27) { // NOR
2496               if(rs1[i]){
2497                 if(s1l>=0) emit_not(s1l,tl);
2498                 else {
2499                   emit_loadreg(rs1[i],tl);
2500                   emit_not(tl,tl);
2501                 }
2502               }
2503               else
2504               if(rs2[i]){
2505                 if(s2l>=0) emit_not(s2l,tl);
2506                 else {
2507                   emit_loadreg(rs2[i],tl);
2508                   emit_not(tl,tl);
2509                 }
2510               }
2511               else emit_movimm(-1,tl);
2512             }
2513           }
2514         }
2515       }
2516     }
2517   }
2518 }
2519
2520 void imm16_assemble(int i,struct regstat *i_regs)
2521 {
2522   if (opcode[i]==0x0f) { // LUI
2523     if(rt1[i]) {
2524       signed char t;
2525       t=get_reg(i_regs->regmap,rt1[i]);
2526       //assert(t>=0);
2527       if(t>=0) {
2528         if(!((i_regs->isconst>>t)&1))
2529           emit_movimm(imm[i]<<16,t);
2530       }
2531     }
2532   }
2533   if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2534     if(rt1[i]) {
2535       signed char s,t;
2536       t=get_reg(i_regs->regmap,rt1[i]);
2537       s=get_reg(i_regs->regmap,rs1[i]);
2538       if(rs1[i]) {
2539         //assert(t>=0);
2540         //assert(s>=0);
2541         if(t>=0) {
2542           if(!((i_regs->isconst>>t)&1)) {
2543             if(s<0) {
2544               if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2545               emit_addimm(t,imm[i],t);
2546             }else{
2547               if(!((i_regs->wasconst>>s)&1))
2548                 emit_addimm(s,imm[i],t);
2549               else
2550                 emit_movimm(constmap[i][s]+imm[i],t);
2551             }
2552           }
2553         }
2554       } else {
2555         if(t>=0) {
2556           if(!((i_regs->isconst>>t)&1))
2557             emit_movimm(imm[i],t);
2558         }
2559       }
2560     }
2561   }
2562   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2563     if(rt1[i]) {
2564       signed char sh,sl,th,tl;
2565       th=get_reg(i_regs->regmap,rt1[i]|64);
2566       tl=get_reg(i_regs->regmap,rt1[i]);
2567       sh=get_reg(i_regs->regmap,rs1[i]|64);
2568       sl=get_reg(i_regs->regmap,rs1[i]);
2569       if(tl>=0) {
2570         if(rs1[i]) {
2571           assert(sh>=0);
2572           assert(sl>=0);
2573           if(th>=0) {
2574             emit_addimm64_32(sh,sl,imm[i],th,tl);
2575           }
2576           else {
2577             emit_addimm(sl,imm[i],tl);
2578           }
2579         } else {
2580           emit_movimm(imm[i],tl);
2581           if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2582         }
2583       }
2584     }
2585   }
2586   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2587     if(rt1[i]) {
2588       //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2589       signed char sh,sl,t;
2590       t=get_reg(i_regs->regmap,rt1[i]);
2591       sh=get_reg(i_regs->regmap,rs1[i]|64);
2592       sl=get_reg(i_regs->regmap,rs1[i]);
2593       //assert(t>=0);
2594       if(t>=0) {
2595         if(rs1[i]>0) {
2596           if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2597           if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2598             if(opcode[i]==0x0a) { // SLTI
2599               if(sl<0) {
2600                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2601                 emit_slti32(t,imm[i],t);
2602               }else{
2603                 emit_slti32(sl,imm[i],t);
2604               }
2605             }
2606             else { // SLTIU
2607               if(sl<0) {
2608                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2609                 emit_sltiu32(t,imm[i],t);
2610               }else{
2611                 emit_sltiu32(sl,imm[i],t);
2612               }
2613             }
2614           }else{ // 64-bit
2615             assert(sl>=0);
2616             if(opcode[i]==0x0a) // SLTI
2617               emit_slti64_32(sh,sl,imm[i],t);
2618             else // SLTIU
2619               emit_sltiu64_32(sh,sl,imm[i],t);
2620           }
2621         }else{
2622           // SLTI(U) with r0 is just stupid,
2623           // nonetheless examples can be found
2624           if(opcode[i]==0x0a) // SLTI
2625             if(0<imm[i]) emit_movimm(1,t);
2626             else emit_zeroreg(t);
2627           else // SLTIU
2628           {
2629             if(imm[i]) emit_movimm(1,t);
2630             else emit_zeroreg(t);
2631           }
2632         }
2633       }
2634     }
2635   }
2636   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2637     if(rt1[i]) {
2638       signed char sh,sl,th,tl;
2639       th=get_reg(i_regs->regmap,rt1[i]|64);
2640       tl=get_reg(i_regs->regmap,rt1[i]);
2641       sh=get_reg(i_regs->regmap,rs1[i]|64);
2642       sl=get_reg(i_regs->regmap,rs1[i]);
2643       if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2644         if(opcode[i]==0x0c) //ANDI
2645         {
2646           if(rs1[i]) {
2647             if(sl<0) {
2648               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2649               emit_andimm(tl,imm[i],tl);
2650             }else{
2651               if(!((i_regs->wasconst>>sl)&1))
2652                 emit_andimm(sl,imm[i],tl);
2653               else
2654                 emit_movimm(constmap[i][sl]&imm[i],tl);
2655             }
2656           }
2657           else
2658             emit_zeroreg(tl);
2659           if(th>=0) emit_zeroreg(th);
2660         }
2661         else
2662         {
2663           if(rs1[i]) {
2664             if(sl<0) {
2665               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2666             }
2667             if(th>=0) {
2668               if(sh<0) {
2669                 emit_loadreg(rs1[i]|64,th);
2670               }else{
2671                 emit_mov(sh,th);
2672               }
2673             }
2674             if(opcode[i]==0x0d) //ORI
2675             if(sl<0) {
2676               emit_orimm(tl,imm[i],tl);
2677             }else{
2678               if(!((i_regs->wasconst>>sl)&1))
2679                 emit_orimm(sl,imm[i],tl);
2680               else
2681                 emit_movimm(constmap[i][sl]|imm[i],tl);
2682             }
2683             if(opcode[i]==0x0e) //XORI
2684             if(sl<0) {
2685               emit_xorimm(tl,imm[i],tl);
2686             }else{
2687               if(!((i_regs->wasconst>>sl)&1))
2688                 emit_xorimm(sl,imm[i],tl);
2689               else
2690                 emit_movimm(constmap[i][sl]^imm[i],tl);
2691             }
2692           }
2693           else {
2694             emit_movimm(imm[i],tl);
2695             if(th>=0) emit_zeroreg(th);
2696           }
2697         }
2698       }
2699     }
2700   }
2701 }
2702
2703 void shiftimm_assemble(int i,struct regstat *i_regs)
2704 {
2705   if(opcode2[i]<=0x3) // SLL/SRL/SRA
2706   {
2707     if(rt1[i]) {
2708       signed char s,t;
2709       t=get_reg(i_regs->regmap,rt1[i]);
2710       s=get_reg(i_regs->regmap,rs1[i]);
2711       //assert(t>=0);
2712       if(t>=0&&!((i_regs->isconst>>t)&1)){
2713         if(rs1[i]==0)
2714         {
2715           emit_zeroreg(t);
2716         }
2717         else
2718         {
2719           if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2720           if(imm[i]) {
2721             if(opcode2[i]==0) // SLL
2722             {
2723               emit_shlimm(s<0?t:s,imm[i],t);
2724             }
2725             if(opcode2[i]==2) // SRL
2726             {
2727               emit_shrimm(s<0?t:s,imm[i],t);
2728             }
2729             if(opcode2[i]==3) // SRA
2730             {
2731               emit_sarimm(s<0?t:s,imm[i],t);
2732             }
2733           }else{
2734             // Shift by zero
2735             if(s>=0 && s!=t) emit_mov(s,t);
2736           }
2737         }
2738       }
2739       //emit_storereg(rt1[i],t); //DEBUG
2740     }
2741   }
2742   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2743   {
2744     if(rt1[i]) {
2745       signed char sh,sl,th,tl;
2746       th=get_reg(i_regs->regmap,rt1[i]|64);
2747       tl=get_reg(i_regs->regmap,rt1[i]);
2748       sh=get_reg(i_regs->regmap,rs1[i]|64);
2749       sl=get_reg(i_regs->regmap,rs1[i]);
2750       if(tl>=0) {
2751         if(rs1[i]==0)
2752         {
2753           emit_zeroreg(tl);
2754           if(th>=0) emit_zeroreg(th);
2755         }
2756         else
2757         {
2758           assert(sl>=0);
2759           assert(sh>=0);
2760           if(imm[i]) {
2761             if(opcode2[i]==0x38) // DSLL
2762             {
2763               if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2764               emit_shlimm(sl,imm[i],tl);
2765             }
2766             if(opcode2[i]==0x3a) // DSRL
2767             {
2768               emit_shrdimm(sl,sh,imm[i],tl);
2769               if(th>=0) emit_shrimm(sh,imm[i],th);
2770             }
2771             if(opcode2[i]==0x3b) // DSRA
2772             {
2773               emit_shrdimm(sl,sh,imm[i],tl);
2774               if(th>=0) emit_sarimm(sh,imm[i],th);
2775             }
2776           }else{
2777             // Shift by zero
2778             if(sl!=tl) emit_mov(sl,tl);
2779             if(th>=0&&sh!=th) emit_mov(sh,th);
2780           }
2781         }
2782       }
2783     }
2784   }
2785   if(opcode2[i]==0x3c) // DSLL32
2786   {
2787     if(rt1[i]) {
2788       signed char sl,tl,th;
2789       tl=get_reg(i_regs->regmap,rt1[i]);
2790       th=get_reg(i_regs->regmap,rt1[i]|64);
2791       sl=get_reg(i_regs->regmap,rs1[i]);
2792       if(th>=0||tl>=0){
2793         assert(tl>=0);
2794         assert(th>=0);
2795         assert(sl>=0);
2796         emit_mov(sl,th);
2797         emit_zeroreg(tl);
2798         if(imm[i]>32)
2799         {
2800           emit_shlimm(th,imm[i]&31,th);
2801         }
2802       }
2803     }
2804   }
2805   if(opcode2[i]==0x3e) // DSRL32
2806   {
2807     if(rt1[i]) {
2808       signed char sh,tl,th;
2809       tl=get_reg(i_regs->regmap,rt1[i]);
2810       th=get_reg(i_regs->regmap,rt1[i]|64);
2811       sh=get_reg(i_regs->regmap,rs1[i]|64);
2812       if(tl>=0){
2813         assert(sh>=0);
2814         emit_mov(sh,tl);
2815         if(th>=0) emit_zeroreg(th);
2816         if(imm[i]>32)
2817         {
2818           emit_shrimm(tl,imm[i]&31,tl);
2819         }
2820       }
2821     }
2822   }
2823   if(opcode2[i]==0x3f) // DSRA32
2824   {
2825     if(rt1[i]) {
2826       signed char sh,tl;
2827       tl=get_reg(i_regs->regmap,rt1[i]);
2828       sh=get_reg(i_regs->regmap,rs1[i]|64);
2829       if(tl>=0){
2830         assert(sh>=0);
2831         emit_mov(sh,tl);
2832         if(imm[i]>32)
2833         {
2834           emit_sarimm(tl,imm[i]&31,tl);
2835         }
2836       }
2837     }
2838   }
2839 }
2840
2841 #ifndef shift_assemble
2842 void shift_assemble(int i,struct regstat *i_regs)
2843 {
2844   printf("Need shift_assemble for this architecture.\n");
2845   exit(1);
2846 }
2847 #endif
2848
2849 void load_assemble(int i,struct regstat *i_regs)
2850 {
2851   int s,th,tl,addr,map=-1;
2852   int offset;
2853   int jaddr=0;
2854   int memtarget=0,c=0;
2855   int fastload_reg_override=0;
2856   u_int hr,reglist=0;
2857   th=get_reg(i_regs->regmap,rt1[i]|64);
2858   tl=get_reg(i_regs->regmap,rt1[i]);
2859   s=get_reg(i_regs->regmap,rs1[i]);
2860   offset=imm[i];
2861   for(hr=0;hr<HOST_REGS;hr++) {
2862     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2863   }
2864   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2865   if(s>=0) {
2866     c=(i_regs->wasconst>>s)&1;
2867     if (c) {
2868       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2869       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2870     }
2871   }
2872   //printf("load_assemble: c=%d\n",c);
2873   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2874   // FIXME: Even if the load is a NOP, we should check for pagefaults...
2875 #ifdef PCSX
2876   if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2877     ||rt1[i]==0) {
2878       // could be FIFO, must perform the read
2879       // ||dummy read
2880       assem_debug("(forced read)\n");
2881       tl=get_reg(i_regs->regmap,-1);
2882       assert(tl>=0);
2883   }
2884 #endif
2885   if(offset||s<0||c) addr=tl;
2886   else addr=s;
2887   //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2888  if(tl>=0) {
2889   //printf("load_assemble: c=%d\n",c);
2890   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2891   assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2892   reglist&=~(1<<tl);
2893   if(th>=0) reglist&=~(1<<th);
2894   if(!using_tlb) {
2895     if(!c) {
2896       #ifdef RAM_OFFSET
2897       map=get_reg(i_regs->regmap,ROREG);
2898       if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2899       #endif
2900 //#define R29_HACK 1
2901       #ifdef R29_HACK
2902       // Strmnnrmn's speed hack
2903       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2904       #endif
2905       {
2906         jaddr=emit_fastpath_cmp_jump(i,addr,&fastload_reg_override);
2907       }
2908     }
2909   }else{ // using tlb
2910     int x=0;
2911     if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2912     if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2913     map=get_reg(i_regs->regmap,TLREG);
2914     assert(map>=0);
2915     reglist&=~(1<<map);
2916     map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2917     do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2918   }
2919   int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2920   if (opcode[i]==0x20) { // LB
2921     if(!c||memtarget) {
2922       if(!dummy) {
2923         #ifdef HOST_IMM_ADDR32
2924         if(c)
2925           emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2926         else
2927         #endif
2928         {
2929           //emit_xorimm(addr,3,tl);
2930           //gen_tlb_addr_r(tl,map);
2931           //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2932           int x=0,a=tl;
2933 #ifdef BIG_ENDIAN_MIPS
2934           if(!c) emit_xorimm(addr,3,tl);
2935           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2936 #else
2937           if(!c) a=addr;
2938 #endif
2939           if(fastload_reg_override) a=fastload_reg_override;
2940
2941           emit_movsbl_indexed_tlb(x,a,map,tl);
2942         }
2943       }
2944       if(jaddr)
2945         add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2946     }
2947     else
2948       inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2949   }
2950   if (opcode[i]==0x21) { // LH
2951     if(!c||memtarget) {
2952       if(!dummy) {
2953         #ifdef HOST_IMM_ADDR32
2954         if(c)
2955           emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2956         else
2957         #endif
2958         {
2959           int x=0,a=tl;
2960 #ifdef BIG_ENDIAN_MIPS
2961           if(!c) emit_xorimm(addr,2,tl);
2962           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2963 #else
2964           if(!c) a=addr;
2965 #endif
2966           if(fastload_reg_override) a=fastload_reg_override;
2967           //#ifdef
2968           //emit_movswl_indexed_tlb(x,tl,map,tl);
2969           //else
2970           if(map>=0) {
2971             gen_tlb_addr_r(a,map);
2972             emit_movswl_indexed(x,a,tl);
2973           }else{
2974             #ifdef RAM_OFFSET
2975             emit_movswl_indexed(x,a,tl);
2976             #else
2977             emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2978             #endif
2979           }
2980         }
2981       }
2982       if(jaddr)
2983         add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2984     }
2985     else
2986       inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2987   }
2988   if (opcode[i]==0x23) { // LW
2989     if(!c||memtarget) {
2990       if(!dummy) {
2991         int a=addr;
2992         if(fastload_reg_override) a=fastload_reg_override;
2993         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2994         #ifdef HOST_IMM_ADDR32
2995         if(c)
2996           emit_readword_tlb(constmap[i][s]+offset,map,tl);
2997         else
2998         #endif
2999         emit_readword_indexed_tlb(0,a,map,tl);
3000       }
3001       if(jaddr)
3002         add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3003     }
3004     else
3005       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3006   }
3007   if (opcode[i]==0x24) { // LBU
3008     if(!c||memtarget) {
3009       if(!dummy) {
3010         #ifdef HOST_IMM_ADDR32
3011         if(c)
3012           emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
3013         else
3014         #endif
3015         {
3016           //emit_xorimm(addr,3,tl);
3017           //gen_tlb_addr_r(tl,map);
3018           //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
3019           int x=0,a=tl;
3020 #ifdef BIG_ENDIAN_MIPS
3021           if(!c) emit_xorimm(addr,3,tl);
3022           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3023 #else
3024           if(!c) a=addr;
3025 #endif
3026           if(fastload_reg_override) a=fastload_reg_override;
3027
3028           emit_movzbl_indexed_tlb(x,a,map,tl);
3029         }
3030       }
3031       if(jaddr)
3032         add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3033     }
3034     else
3035       inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3036   }
3037   if (opcode[i]==0x25) { // LHU
3038     if(!c||memtarget) {
3039       if(!dummy) {
3040         #ifdef HOST_IMM_ADDR32
3041         if(c)
3042           emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
3043         else
3044         #endif
3045         {
3046           int x=0,a=tl;
3047 #ifdef BIG_ENDIAN_MIPS
3048           if(!c) emit_xorimm(addr,2,tl);
3049           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3050 #else
3051           if(!c) a=addr;
3052 #endif
3053           if(fastload_reg_override) a=fastload_reg_override;
3054           //#ifdef
3055           //emit_movzwl_indexed_tlb(x,tl,map,tl);
3056           //#else
3057           if(map>=0) {
3058             gen_tlb_addr_r(a,map);
3059             emit_movzwl_indexed(x,a,tl);
3060           }else{
3061             #ifdef RAM_OFFSET
3062             emit_movzwl_indexed(x,a,tl);
3063             #else
3064             emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
3065             #endif
3066           }
3067         }
3068       }
3069       if(jaddr)
3070         add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3071     }
3072     else
3073       inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3074   }
3075   if (opcode[i]==0x27) { // LWU
3076     assert(th>=0);
3077     if(!c||memtarget) {
3078       if(!dummy) {
3079         int a=addr;
3080         if(fastload_reg_override) a=fastload_reg_override;
3081         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3082         #ifdef HOST_IMM_ADDR32
3083         if(c)
3084           emit_readword_tlb(constmap[i][s]+offset,map,tl);
3085         else
3086         #endif
3087         emit_readword_indexed_tlb(0,a,map,tl);
3088       }
3089       if(jaddr)
3090         add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3091     }
3092     else {
3093       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3094     }
3095     emit_zeroreg(th);
3096   }
3097   if (opcode[i]==0x37) { // LD
3098     if(!c||memtarget) {
3099       if(!dummy) {
3100         int a=addr;
3101         if(fastload_reg_override) a=fastload_reg_override;
3102         //gen_tlb_addr_r(tl,map);
3103         //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3104         //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3105         #ifdef HOST_IMM_ADDR32
3106         if(c)
3107           emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3108         else
3109         #endif
3110         emit_readdword_indexed_tlb(0,a,map,th,tl);
3111       }
3112       if(jaddr)
3113         add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3114     }
3115     else
3116       inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3117   }
3118  }
3119   //emit_storereg(rt1[i],tl); // DEBUG
3120   //if(opcode[i]==0x23)
3121   //if(opcode[i]==0x24)
3122   //if(opcode[i]==0x23||opcode[i]==0x24)
3123   /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3124   {
3125     //emit_pusha();
3126     save_regs(0x100f);
3127         emit_readword((int)&last_count,ECX);
3128         #ifdef __i386__
3129         if(get_reg(i_regs->regmap,CCREG)<0)
3130           emit_loadreg(CCREG,HOST_CCREG);
3131         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3132         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3133         emit_writeword(HOST_CCREG,(int)&Count);
3134         #endif
3135         #ifdef __arm__
3136         if(get_reg(i_regs->regmap,CCREG)<0)
3137           emit_loadreg(CCREG,0);
3138         else
3139           emit_mov(HOST_CCREG,0);
3140         emit_add(0,ECX,0);
3141         emit_addimm(0,2*ccadj[i],0);
3142         emit_writeword(0,(int)&Count);
3143         #endif
3144     emit_call((int)memdebug);
3145     //emit_popa();
3146     restore_regs(0x100f);
3147   }/**/
3148 }
3149
3150 #ifndef loadlr_assemble
3151 void loadlr_assemble(int i,struct regstat *i_regs)
3152 {
3153   printf("Need loadlr_assemble for this architecture.\n");
3154   exit(1);
3155 }
3156 #endif
3157
3158 void store_assemble(int i,struct regstat *i_regs)
3159 {
3160   int s,th,tl,map=-1;
3161   int addr,temp;
3162   int offset;
3163   int jaddr=0,jaddr2,type;
3164   int memtarget=0,c=0;
3165   int agr=AGEN1+(i&1);
3166   int faststore_reg_override=0;
3167   u_int hr,reglist=0;
3168   th=get_reg(i_regs->regmap,rs2[i]|64);
3169   tl=get_reg(i_regs->regmap,rs2[i]);
3170   s=get_reg(i_regs->regmap,rs1[i]);
3171   temp=get_reg(i_regs->regmap,agr);
3172   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3173   offset=imm[i];
3174   if(s>=0) {
3175     c=(i_regs->wasconst>>s)&1;
3176     if(c) {
3177       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3178       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3179     }
3180   }
3181   assert(tl>=0);
3182   assert(temp>=0);
3183   for(hr=0;hr<HOST_REGS;hr++) {
3184     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3185   }
3186   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3187   if(offset||s<0||c) addr=temp;
3188   else addr=s;
3189   if(!using_tlb) {
3190     if(!c) {
3191       #ifndef PCSX
3192       #ifdef R29_HACK
3193       // Strmnnrmn's speed hack
3194       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3195       #endif
3196       emit_cmpimm(addr,RAM_SIZE);
3197       #ifdef DESTRUCTIVE_SHIFT
3198       if(s==addr) emit_mov(s,temp);
3199       #endif
3200       #ifdef R29_HACK
3201       memtarget=1;
3202       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3203       #endif
3204       {
3205         jaddr=(int)out;
3206         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3207         // Hint to branch predictor that the branch is unlikely to be taken
3208         if(rs1[i]>=28)
3209           emit_jno_unlikely(0);
3210         else
3211         #endif
3212         emit_jno(0);
3213       }
3214       #else
3215         jaddr=emit_fastpath_cmp_jump(i,addr,&faststore_reg_override);
3216       #endif
3217     }
3218   }else{ // using tlb
3219     int x=0;
3220     if (opcode[i]==0x28) x=3; // SB
3221     if (opcode[i]==0x29) x=2; // SH
3222     map=get_reg(i_regs->regmap,TLREG);
3223     assert(map>=0);
3224     reglist&=~(1<<map);
3225     map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3226     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3227   }
3228
3229   if (opcode[i]==0x28) { // SB
3230     if(!c||memtarget) {
3231       int x=0,a=temp;
3232 #ifdef BIG_ENDIAN_MIPS
3233       if(!c) emit_xorimm(addr,3,temp);
3234       else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3235 #else
3236       if(!c) a=addr;
3237 #endif
3238       if(faststore_reg_override) a=faststore_reg_override;
3239       //gen_tlb_addr_w(temp,map);
3240       //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3241       emit_writebyte_indexed_tlb(tl,x,a,map,a);
3242     }
3243     type=STOREB_STUB;
3244   }
3245   if (opcode[i]==0x29) { // SH
3246     if(!c||memtarget) {
3247       int x=0,a=temp;
3248 #ifdef BIG_ENDIAN_MIPS
3249       if(!c) emit_xorimm(addr,2,temp);
3250       else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3251 #else
3252       if(!c) a=addr;
3253 #endif
3254       if(faststore_reg_override) a=faststore_reg_override;
3255       //#ifdef
3256       //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3257       //#else
3258       if(map>=0) {
3259         gen_tlb_addr_w(a,map);
3260         emit_writehword_indexed(tl,x,a);
3261       }else
3262         emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
3263     }
3264     type=STOREH_STUB;
3265   }
3266   if (opcode[i]==0x2B) { // SW
3267     if(!c||memtarget) {
3268       int a=addr;
3269       if(faststore_reg_override) a=faststore_reg_override;
3270       //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3271       emit_writeword_indexed_tlb(tl,0,a,map,temp);
3272     }
3273     type=STOREW_STUB;
3274   }
3275   if (opcode[i]==0x3F) { // SD
3276     if(!c||memtarget) {
3277       int a=addr;
3278       if(faststore_reg_override) a=faststore_reg_override;
3279       if(rs2[i]) {
3280         assert(th>=0);
3281         //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3282         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3283         emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
3284       }else{
3285         // Store zero
3286         //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3287         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3288         emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
3289       }
3290     }
3291     type=STORED_STUB;
3292   }
3293 #ifdef PCSX
3294   if(jaddr) {
3295     // PCSX store handlers don't check invcode again
3296     reglist|=1<<addr;
3297     add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3298     jaddr=0;
3299   }
3300 #endif
3301   if(!using_tlb) {
3302     if(!c||memtarget) {
3303       #ifdef DESTRUCTIVE_SHIFT
3304       // The x86 shift operation is 'destructive'; it overwrites the
3305       // source register, so we need to make a copy first and use that.
3306       addr=temp;
3307       #endif
3308       #if defined(HOST_IMM8)
3309       int ir=get_reg(i_regs->regmap,INVCP);
3310       assert(ir>=0);
3311       emit_cmpmem_indexedsr12_reg(ir,addr,1);
3312       #else
3313       emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3314       #endif
3315       #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3316       emit_callne(invalidate_addr_reg[addr]);
3317       #else
3318       jaddr2=(int)out;
3319       emit_jne(0);
3320       add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3321       #endif
3322     }
3323   }
3324   if(jaddr) {
3325     add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3326   } else if(c&&!memtarget) {
3327     inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3328   }
3329   //if(opcode[i]==0x2B || opcode[i]==0x3F)
3330   //if(opcode[i]==0x2B || opcode[i]==0x28)
3331   //if(opcode[i]==0x2B || opcode[i]==0x29)
3332   //if(opcode[i]==0x2B)
3333   /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3334   {
3335     #ifdef __i386__
3336     emit_pusha();
3337     #endif
3338     #ifdef __arm__
3339     save_regs(0x100f);
3340     #endif
3341         emit_readword((int)&last_count,ECX);
3342         #ifdef __i386__
3343         if(get_reg(i_regs->regmap,CCREG)<0)
3344           emit_loadreg(CCREG,HOST_CCREG);
3345         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3346         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3347         emit_writeword(HOST_CCREG,(int)&Count);
3348         #endif
3349         #ifdef __arm__
3350         if(get_reg(i_regs->regmap,CCREG)<0)
3351           emit_loadreg(CCREG,0);
3352         else
3353           emit_mov(HOST_CCREG,0);
3354         emit_add(0,ECX,0);
3355         emit_addimm(0,2*ccadj[i],0);
3356         emit_writeword(0,(int)&Count);
3357         #endif
3358     emit_call((int)memdebug);
3359     #ifdef __i386__
3360     emit_popa();
3361     #endif
3362     #ifdef __arm__
3363     restore_regs(0x100f);
3364     #endif
3365   }/**/
3366 }
3367
3368 void storelr_assemble(int i,struct regstat *i_regs)
3369 {
3370   int s,th,tl;
3371   int temp;
3372   int temp2;
3373   int offset;
3374   int jaddr=0,jaddr2;
3375   int case1,case2,case3;
3376   int done0,done1,done2;
3377   int memtarget=0,c=0;
3378   int agr=AGEN1+(i&1);
3379   u_int hr,reglist=0;
3380   th=get_reg(i_regs->regmap,rs2[i]|64);
3381   tl=get_reg(i_regs->regmap,rs2[i]);
3382   s=get_reg(i_regs->regmap,rs1[i]);
3383   temp=get_reg(i_regs->regmap,agr);
3384   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3385   offset=imm[i];
3386   if(s>=0) {
3387     c=(i_regs->isconst>>s)&1;
3388     if(c) {
3389       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3390       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3391     }
3392   }
3393   assert(tl>=0);
3394   for(hr=0;hr<HOST_REGS;hr++) {
3395     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3396   }
3397   assert(temp>=0);
3398   if(!using_tlb) {
3399     if(!c) {
3400       emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3401       if(!offset&&s!=temp) emit_mov(s,temp);
3402       jaddr=(int)out;
3403       emit_jno(0);
3404     }
3405     else
3406     {
3407       if(!memtarget||!rs1[i]) {
3408         jaddr=(int)out;
3409         emit_jmp(0);
3410       }
3411     }
3412     #ifdef RAM_OFFSET
3413     int map=get_reg(i_regs->regmap,ROREG);
3414     if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3415     gen_tlb_addr_w(temp,map);
3416     #else
3417     if((u_int)rdram!=0x80000000)
3418       emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3419     #endif
3420   }else{ // using tlb
3421     int map=get_reg(i_regs->regmap,TLREG);
3422     assert(map>=0);
3423     reglist&=~(1<<map);
3424     map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3425     if(!c&&!offset&&s>=0) emit_mov(s,temp);
3426     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3427     if(!jaddr&&!memtarget) {
3428       jaddr=(int)out;
3429       emit_jmp(0);
3430     }
3431     gen_tlb_addr_w(temp,map);
3432   }
3433
3434   if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3435     temp2=get_reg(i_regs->regmap,FTEMP);
3436     if(!rs2[i]) temp2=th=tl;
3437   }
3438
3439 #ifndef BIG_ENDIAN_MIPS
3440     emit_xorimm(temp,3,temp);
3441 #endif
3442   emit_testimm(temp,2);
3443   case2=(int)out;
3444   emit_jne(0);
3445   emit_testimm(temp,1);
3446   case1=(int)out;
3447   emit_jne(0);
3448   // 0
3449   if (opcode[i]==0x2A) { // SWL
3450     emit_writeword_indexed(tl,0,temp);
3451   }
3452   if (opcode[i]==0x2E) { // SWR
3453     emit_writebyte_indexed(tl,3,temp);
3454   }
3455   if (opcode[i]==0x2C) { // SDL
3456     emit_writeword_indexed(th,0,temp);
3457     if(rs2[i]) emit_mov(tl,temp2);
3458   }
3459   if (opcode[i]==0x2D) { // SDR
3460     emit_writebyte_indexed(tl,3,temp);
3461     if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3462   }
3463   done0=(int)out;
3464   emit_jmp(0);
3465   // 1
3466   set_jump_target(case1,(int)out);
3467   if (opcode[i]==0x2A) { // SWL
3468     // Write 3 msb into three least significant bytes
3469     if(rs2[i]) emit_rorimm(tl,8,tl);
3470     emit_writehword_indexed(tl,-1,temp);
3471     if(rs2[i]) emit_rorimm(tl,16,tl);
3472     emit_writebyte_indexed(tl,1,temp);
3473     if(rs2[i]) emit_rorimm(tl,8,tl);
3474   }
3475   if (opcode[i]==0x2E) { // SWR
3476     // Write two lsb into two most significant bytes
3477     emit_writehword_indexed(tl,1,temp);
3478   }
3479   if (opcode[i]==0x2C) { // SDL
3480     if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3481     // Write 3 msb into three least significant bytes
3482     if(rs2[i]) emit_rorimm(th,8,th);
3483     emit_writehword_indexed(th,-1,temp);
3484     if(rs2[i]) emit_rorimm(th,16,th);
3485     emit_writebyte_indexed(th,1,temp);
3486     if(rs2[i]) emit_rorimm(th,8,th);
3487   }
3488   if (opcode[i]==0x2D) { // SDR
3489     if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3490     // Write two lsb into two most significant bytes
3491     emit_writehword_indexed(tl,1,temp);
3492   }
3493   done1=(int)out;
3494   emit_jmp(0);
3495   // 2
3496   set_jump_target(case2,(int)out);
3497   emit_testimm(temp,1);
3498   case3=(int)out;
3499   emit_jne(0);
3500   if (opcode[i]==0x2A) { // SWL
3501     // Write two msb into two least significant bytes
3502     if(rs2[i]) emit_rorimm(tl,16,tl);
3503     emit_writehword_indexed(tl,-2,temp);
3504     if(rs2[i]) emit_rorimm(tl,16,tl);
3505   }
3506   if (opcode[i]==0x2E) { // SWR
3507     // Write 3 lsb into three most significant bytes
3508     emit_writebyte_indexed(tl,-1,temp);
3509     if(rs2[i]) emit_rorimm(tl,8,tl);
3510     emit_writehword_indexed(tl,0,temp);
3511     if(rs2[i]) emit_rorimm(tl,24,tl);
3512   }
3513   if (opcode[i]==0x2C) { // SDL
3514     if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3515     // Write two msb into two least significant bytes
3516     if(rs2[i]) emit_rorimm(th,16,th);
3517     emit_writehword_indexed(th,-2,temp);
3518     if(rs2[i]) emit_rorimm(th,16,th);
3519   }
3520   if (opcode[i]==0x2D) { // SDR
3521     if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3522     // Write 3 lsb into three most significant bytes
3523     emit_writebyte_indexed(tl,-1,temp);
3524     if(rs2[i]) emit_rorimm(tl,8,tl);
3525     emit_writehword_indexed(tl,0,temp);
3526     if(rs2[i]) emit_rorimm(tl,24,tl);
3527   }
3528   done2=(int)out;
3529   emit_jmp(0);
3530   // 3
3531   set_jump_target(case3,(int)out);
3532   if (opcode[i]==0x2A) { // SWL
3533     // Write msb into least significant byte
3534     if(rs2[i]) emit_rorimm(tl,24,tl);
3535     emit_writebyte_indexed(tl,-3,temp);
3536     if(rs2[i]) emit_rorimm(tl,8,tl);
3537   }
3538   if (opcode[i]==0x2E) { // SWR
3539     // Write entire word
3540     emit_writeword_indexed(tl,-3,temp);
3541   }
3542   if (opcode[i]==0x2C) { // SDL
3543     if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3544     // Write msb into least significant byte
3545     if(rs2[i]) emit_rorimm(th,24,th);
3546     emit_writebyte_indexed(th,-3,temp);
3547     if(rs2[i]) emit_rorimm(th,8,th);
3548   }
3549   if (opcode[i]==0x2D) { // SDR
3550     if(rs2[i]) emit_mov(th,temp2);
3551     // Write entire word
3552     emit_writeword_indexed(tl,-3,temp);
3553   }
3554   set_jump_target(done0,(int)out);
3555   set_jump_target(done1,(int)out);
3556   set_jump_target(done2,(int)out);
3557   if (opcode[i]==0x2C) { // SDL
3558     emit_testimm(temp,4);
3559     done0=(int)out;
3560     emit_jne(0);
3561     emit_andimm(temp,~3,temp);
3562     emit_writeword_indexed(temp2,4,temp);
3563     set_jump_target(done0,(int)out);
3564   }
3565   if (opcode[i]==0x2D) { // SDR
3566     emit_testimm(temp,4);
3567     done0=(int)out;
3568     emit_jeq(0);
3569     emit_andimm(temp,~3,temp);
3570     emit_writeword_indexed(temp2,-4,temp);
3571     set_jump_target(done0,(int)out);
3572   }
3573   if(!c||!memtarget)
3574     add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
3575   if(!using_tlb) {
3576     #ifdef RAM_OFFSET
3577     int map=get_reg(i_regs->regmap,ROREG);
3578     if(map<0) map=HOST_TEMPREG;
3579     gen_orig_addr_w(temp,map);
3580     #else
3581     emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3582     #endif
3583     #if defined(HOST_IMM8)
3584     int ir=get_reg(i_regs->regmap,INVCP);
3585     assert(ir>=0);
3586     emit_cmpmem_indexedsr12_reg(ir,temp,1);
3587     #else
3588     emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3589     #endif
3590     #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3591     emit_callne(invalidate_addr_reg[temp]);
3592     #else
3593     jaddr2=(int)out;
3594     emit_jne(0);
3595     add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3596     #endif
3597   }
3598   /*
3599     emit_pusha();
3600     //save_regs(0x100f);
3601         emit_readword((int)&last_count,ECX);
3602         if(get_reg(i_regs->regmap,CCREG)<0)
3603           emit_loadreg(CCREG,HOST_CCREG);
3604         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3605         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3606         emit_writeword(HOST_CCREG,(int)&Count);
3607     emit_call((int)memdebug);
3608     emit_popa();
3609     //restore_regs(0x100f);
3610   /**/
3611 }
3612
3613 void c1ls_assemble(int i,struct regstat *i_regs)
3614 {
3615 #ifndef DISABLE_COP1
3616   int s,th,tl;
3617   int temp,ar;
3618   int map=-1;
3619   int offset;
3620   int c=0;
3621   int jaddr,jaddr2=0,jaddr3,type;
3622   int agr=AGEN1+(i&1);
3623   u_int hr,reglist=0;
3624   th=get_reg(i_regs->regmap,FTEMP|64);
3625   tl=get_reg(i_regs->regmap,FTEMP);
3626   s=get_reg(i_regs->regmap,rs1[i]);
3627   temp=get_reg(i_regs->regmap,agr);
3628   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3629   offset=imm[i];
3630   assert(tl>=0);
3631   assert(rs1[i]>0);
3632   assert(temp>=0);
3633   for(hr=0;hr<HOST_REGS;hr++) {
3634     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3635   }
3636   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3637   if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3638   {
3639     // Loads use a temporary register which we need to save
3640     reglist|=1<<temp;
3641   }
3642   if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3643     ar=temp;
3644   else // LWC1/LDC1
3645     ar=tl;
3646   //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3647   //else c=(i_regs->wasconst>>s)&1;
3648   if(s>=0) c=(i_regs->wasconst>>s)&1;
3649   // Check cop1 unusable
3650   if(!cop1_usable) {
3651     signed char rs=get_reg(i_regs->regmap,CSREG);
3652     assert(rs>=0);
3653     emit_testimm(rs,0x20000000);
3654     jaddr=(int)out;
3655     emit_jeq(0);
3656     add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3657     cop1_usable=1;
3658   }
3659   if (opcode[i]==0x39) { // SWC1 (get float address)
3660     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],tl);
3661   }
3662   if (opcode[i]==0x3D) { // SDC1 (get double address)
3663     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],tl);
3664   }
3665   // Generate address + offset
3666   if(!using_tlb) {
3667     if(!c)
3668       emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3669   }
3670   else
3671   {
3672     map=get_reg(i_regs->regmap,TLREG);
3673     assert(map>=0);
3674     reglist&=~(1<<map);
3675     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3676       map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3677     }
3678     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3679       map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3680     }
3681   }
3682   if (opcode[i]==0x39) { // SWC1 (read float)
3683     emit_readword_indexed(0,tl,tl);
3684   }
3685   if (opcode[i]==0x3D) { // SDC1 (read double)
3686     emit_readword_indexed(4,tl,th);
3687     emit_readword_indexed(0,tl,tl);
3688   }
3689   if (opcode[i]==0x31) { // LWC1 (get target address)
3690     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],temp);
3691   }
3692   if (opcode[i]==0x35) { // LDC1 (get target address)
3693     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],temp);
3694   }
3695   if(!using_tlb) {
3696     if(!c) {
3697       jaddr2=(int)out;
3698       emit_jno(0);
3699     }
3700     else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
3701       jaddr2=(int)out;
3702       emit_jmp(0); // inline_readstub/inline_writestub?  Very rare case
3703     }
3704     #ifdef DESTRUCTIVE_SHIFT
3705     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3706       if(!offset&&!c&&s>=0) emit_mov(s,ar);
3707     }
3708     #endif
3709   }else{
3710     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3711       do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3712     }
3713     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3714       do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3715     }
3716   }
3717   if (opcode[i]==0x31) { // LWC1
3718     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3719     //gen_tlb_addr_r(ar,map);
3720     //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3721     #ifdef HOST_IMM_ADDR32
3722     if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3723     else
3724     #endif
3725     emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3726     type=LOADW_STUB;
3727   }
3728   if (opcode[i]==0x35) { // LDC1
3729     assert(th>=0);
3730     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3731     //gen_tlb_addr_r(ar,map);
3732     //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3733     //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3734     #ifdef HOST_IMM_ADDR32
3735     if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3736     else
3737     #endif
3738     emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3739     type=LOADD_STUB;
3740   }
3741   if (opcode[i]==0x39) { // SWC1
3742     //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3743     emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3744     type=STOREW_STUB;
3745   }
3746   if (opcode[i]==0x3D) { // SDC1
3747     assert(th>=0);
3748     //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3749     //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3750     emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3751     type=STORED_STUB;
3752   }
3753   if(!using_tlb) {
3754     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3755       #ifndef DESTRUCTIVE_SHIFT
3756       temp=offset||c||s<0?ar:s;
3757       #endif
3758       #if defined(HOST_IMM8)
3759       int ir=get_reg(i_regs->regmap,INVCP);
3760       assert(ir>=0);
3761       emit_cmpmem_indexedsr12_reg(ir,temp,1);
3762       #else
3763       emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3764       #endif
3765       #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3766       emit_callne(invalidate_addr_reg[temp]);
3767       #else
3768       jaddr3=(int)out;
3769       emit_jne(0);
3770       add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3771       #endif
3772     }
3773   }
3774   if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3775   if (opcode[i]==0x31) { // LWC1 (write float)
3776     emit_writeword_indexed(tl,0,temp);
3777   }
3778   if (opcode[i]==0x35) { // LDC1 (write double)
3779     emit_writeword_indexed(th,4,temp);
3780     emit_writeword_indexed(tl,0,temp);
3781   }
3782   //if(opcode[i]==0x39)
3783   /*if(opcode[i]==0x39||opcode[i]==0x31)
3784   {
3785     emit_pusha();
3786         emit_readword((int)&last_count,ECX);
3787         if(get_reg(i_regs->regmap,CCREG)<0)
3788           emit_loadreg(CCREG,HOST_CCREG);
3789         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3790         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3791         emit_writeword(HOST_CCREG,(int)&Count);
3792     emit_call((int)memdebug);
3793     emit_popa();
3794   }/**/
3795 #else
3796   cop1_unusable(i, i_regs);
3797 #endif
3798 }
3799
3800 void c2ls_assemble(int i,struct regstat *i_regs)
3801 {
3802   int s,tl;
3803   int ar;
3804   int offset;
3805   int memtarget=0,c=0;
3806   int jaddr2=0,jaddr3,type;
3807   int agr=AGEN1+(i&1);
3808   int fastio_reg_override=0;
3809   u_int hr,reglist=0;
3810   u_int copr=(source[i]>>16)&0x1f;
3811   s=get_reg(i_regs->regmap,rs1[i]);
3812   tl=get_reg(i_regs->regmap,FTEMP);
3813   offset=imm[i];
3814   assert(rs1[i]>0);
3815   assert(tl>=0);
3816   assert(!using_tlb);
3817
3818   for(hr=0;hr<HOST_REGS;hr++) {
3819     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3820   }
3821   if(i_regs->regmap[HOST_CCREG]==CCREG)
3822     reglist&=~(1<<HOST_CCREG);
3823
3824   // get the address
3825   if (opcode[i]==0x3a) { // SWC2
3826     ar=get_reg(i_regs->regmap,agr);
3827     if(ar<0) ar=get_reg(i_regs->regmap,-1);
3828     reglist|=1<<ar;
3829   } else { // LWC2
3830     ar=tl;
3831   }
3832   if(s>=0) c=(i_regs->wasconst>>s)&1;
3833   memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3834   if (!offset&&!c&&s>=0) ar=s;
3835   assert(ar>=0);
3836
3837   if (opcode[i]==0x3a) { // SWC2
3838     cop2_get_dreg(copr,tl,HOST_TEMPREG);
3839     type=STOREW_STUB;
3840   }
3841   else
3842     type=LOADW_STUB;
3843
3844   if(c&&!memtarget) {
3845     jaddr2=(int)out;
3846     emit_jmp(0); // inline_readstub/inline_writestub?
3847   }
3848   else {
3849     if(!c) {
3850       jaddr2=emit_fastpath_cmp_jump(i,ar,&fastio_reg_override);
3851     }
3852     if (opcode[i]==0x32) { // LWC2
3853       #ifdef HOST_IMM_ADDR32
3854       if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3855       else
3856       #endif
3857       int a=ar;
3858       if(fastio_reg_override) a=fastio_reg_override;
3859       emit_readword_indexed(0,a,tl);
3860     }
3861     if (opcode[i]==0x3a) { // SWC2
3862       #ifdef DESTRUCTIVE_SHIFT
3863       if(!offset&&!c&&s>=0) emit_mov(s,ar);
3864       #endif
3865       int a=ar;
3866       if(fastio_reg_override) a=fastio_reg_override;
3867       emit_writeword_indexed(tl,0,a);
3868     }
3869   }
3870   if(jaddr2)
3871     add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3872   if (opcode[i]==0x3a) { // SWC2
3873 #if defined(HOST_IMM8)
3874     int ir=get_reg(i_regs->regmap,INVCP);
3875     assert(ir>=0);
3876     emit_cmpmem_indexedsr12_reg(ir,ar,1);
3877 #else
3878     emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3879 #endif
3880     #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3881     emit_callne(invalidate_addr_reg[ar]);
3882     #else
3883     jaddr3=(int)out;
3884     emit_jne(0);
3885     add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3886     #endif
3887   }
3888   if (opcode[i]==0x32) { // LWC2
3889     cop2_put_dreg(copr,tl,HOST_TEMPREG);
3890   }
3891 }
3892
3893 #ifndef multdiv_assemble
3894 void multdiv_assemble(int i,struct regstat *i_regs)
3895 {
3896   printf("Need multdiv_assemble for this architecture.\n");
3897   exit(1);
3898 }
3899 #endif
3900
3901 void mov_assemble(int i,struct regstat *i_regs)
3902 {
3903   //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3904   //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3905   if(rt1[i]) {
3906     signed char sh,sl,th,tl;
3907     th=get_reg(i_regs->regmap,rt1[i]|64);
3908     tl=get_reg(i_regs->regmap,rt1[i]);
3909     //assert(tl>=0);
3910     if(tl>=0) {
3911       sh=get_reg(i_regs->regmap,rs1[i]|64);
3912       sl=get_reg(i_regs->regmap,rs1[i]);
3913       if(sl>=0) emit_mov(sl,tl);
3914       else emit_loadreg(rs1[i],tl);
3915       if(th>=0) {
3916         if(sh>=0) emit_mov(sh,th);
3917         else emit_loadreg(rs1[i]|64,th);
3918       }
3919     }
3920   }
3921 }
3922
3923 #ifndef fconv_assemble
3924 void fconv_assemble(int i,struct regstat *i_regs)
3925 {
3926   printf("Need fconv_assemble for this architecture.\n");
3927   exit(1);
3928 }
3929 #endif
3930
3931 #if 0
3932 void float_assemble(int i,struct regstat *i_regs)
3933 {
3934   printf("Need float_assemble for this architecture.\n");
3935   exit(1);
3936 }
3937 #endif
3938
3939 void syscall_assemble(int i,struct regstat *i_regs)
3940 {
3941   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3942   assert(ccreg==HOST_CCREG);
3943   assert(!is_delayslot);
3944   emit_movimm(start+i*4,EAX); // Get PC
3945   emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // CHECK: is this right?  There should probably be an extra cycle...
3946   emit_jmp((int)jump_syscall_hle); // XXX
3947 }
3948
3949 void hlecall_assemble(int i,struct regstat *i_regs)
3950 {
3951   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3952   assert(ccreg==HOST_CCREG);
3953   assert(!is_delayslot);
3954   emit_movimm(start+i*4+4,0); // Get PC
3955   emit_movimm((int)psxHLEt[source[i]&7],1);
3956   emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // XXX
3957   emit_jmp((int)jump_hlecall);
3958 }
3959
3960 void intcall_assemble(int i,struct regstat *i_regs)
3961 {
3962   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3963   assert(ccreg==HOST_CCREG);
3964   assert(!is_delayslot);
3965   emit_movimm(start+i*4,0); // Get PC
3966   emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
3967   emit_jmp((int)jump_intcall);
3968 }
3969
3970 void ds_assemble(int i,struct regstat *i_regs)
3971 {
3972   speculate_register_values(i);
3973   is_delayslot=1;
3974   switch(itype[i]) {
3975     case ALU:
3976       alu_assemble(i,i_regs);break;
3977     case IMM16:
3978       imm16_assemble(i,i_regs);break;
3979     case SHIFT:
3980       shift_assemble(i,i_regs);break;
3981     case SHIFTIMM:
3982       shiftimm_assemble(i,i_regs);break;
3983     case LOAD:
3984       load_assemble(i,i_regs);break;
3985     case LOADLR:
3986       loadlr_assemble(i,i_regs);break;
3987     case STORE:
3988       store_assemble(i,i_regs);break;
3989     case STORELR:
3990       storelr_assemble(i,i_regs);break;
3991     case COP0:
3992       cop0_assemble(i,i_regs);break;
3993     case COP1:
3994       cop1_assemble(i,i_regs);break;
3995     case C1LS:
3996       c1ls_assemble(i,i_regs);break;
3997     case COP2:
3998       cop2_assemble(i,i_regs);break;
3999     case C2LS:
4000       c2ls_assemble(i,i_regs);break;
4001     case C2OP:
4002       c2op_assemble(i,i_regs);break;
4003     case FCONV:
4004       fconv_assemble(i,i_regs);break;
4005     case FLOAT:
4006       float_assemble(i,i_regs);break;
4007     case FCOMP:
4008       fcomp_assemble(i,i_regs);break;
4009     case MULTDIV:
4010       multdiv_assemble(i,i_regs);break;
4011     case MOV:
4012       mov_assemble(i,i_regs);break;
4013     case SYSCALL:
4014     case HLECALL:
4015     case INTCALL:
4016     case SPAN:
4017     case UJUMP:
4018     case RJUMP:
4019     case CJUMP:
4020     case SJUMP:
4021     case FJUMP:
4022       printf("Jump in the delay slot.  This is probably a bug.\n");
4023   }
4024   is_delayslot=0;
4025 }
4026
4027 // Is the branch target a valid internal jump?
4028 int internal_branch(uint64_t i_is32,int addr)
4029 {
4030   if(addr&1) return 0; // Indirect (register) jump
4031   if(addr>=start && addr<start+slen*4-4)
4032   {
4033     int t=(addr-start)>>2;
4034     // Delay slots are not valid branch targets
4035     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4036     // 64 -> 32 bit transition requires a recompile
4037     /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
4038     {
4039       if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
4040       else printf("optimizable: yes\n");
4041     }*/
4042     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4043 #ifndef FORCE32
4044     if(requires_32bit[t]&~i_is32) return 0;
4045     else
4046 #endif
4047       return 1;
4048   }
4049   return 0;
4050 }
4051
4052 #ifndef wb_invalidate
4053 void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
4054   uint64_t u,uint64_t uu)
4055 {
4056   int hr;
4057   for(hr=0;hr<HOST_REGS;hr++) {
4058     if(hr!=EXCLUDE_REG) {
4059       if(pre[hr]!=entry[hr]) {
4060         if(pre[hr]>=0) {
4061           if((dirty>>hr)&1) {
4062             if(get_reg(entry,pre[hr])<0) {
4063               if(pre[hr]<64) {
4064                 if(!((u>>pre[hr])&1)) {
4065                   emit_storereg(pre[hr],hr);
4066                   if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
4067                     emit_sarimm(hr,31,hr);
4068                     emit_storereg(pre[hr]|64,hr);
4069                   }
4070                 }
4071               }else{
4072                 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
4073                   emit_storereg(pre[hr],hr);
4074                 }
4075               }
4076             }
4077           }
4078         }
4079       }
4080     }
4081   }
4082   // Move from one register to another (no writeback)
4083   for(hr=0;hr<HOST_REGS;hr++) {
4084     if(hr!=EXCLUDE_REG) {
4085       if(pre[hr]!=entry[hr]) {
4086         if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
4087           int nr;
4088           if((nr=get_reg(entry,pre[hr]))>=0) {
4089             emit_mov(hr,nr);
4090           }
4091         }
4092       }
4093     }
4094   }
4095 }
4096 #endif
4097
4098 // Load the specified registers
4099 // This only loads the registers given as arguments because
4100 // we don't want to load things that will be overwritten
4101 void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
4102 {
4103   int hr;
4104   // Load 32-bit regs
4105   for(hr=0;hr<HOST_REGS;hr++) {
4106     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4107       if(entry[hr]!=regmap[hr]) {
4108         if(regmap[hr]==rs1||regmap[hr]==rs2)
4109         {
4110           if(regmap[hr]==0) {
4111             emit_zeroreg(hr);
4112           }
4113           else
4114           {
4115             emit_loadreg(regmap[hr],hr);
4116           }
4117         }
4118       }
4119     }
4120   }
4121   //Load 64-bit regs
4122   for(hr=0;hr<HOST_REGS;hr++) {
4123     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4124       if(entry[hr]!=regmap[hr]) {
4125         if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
4126         {
4127           assert(regmap[hr]!=64);
4128           if((is32>>(regmap[hr]&63))&1) {
4129             int lr=get_reg(regmap,regmap[hr]-64);
4130             if(lr>=0)
4131               emit_sarimm(lr,31,hr);
4132             else
4133               emit_loadreg(regmap[hr],hr);
4134           }
4135           else
4136           {
4137             emit_loadreg(regmap[hr],hr);
4138           }
4139         }
4140       }
4141     }
4142   }
4143 }
4144
4145 // Load registers prior to the start of a loop
4146 // so that they are not loaded within the loop
4147 static void loop_preload(signed char pre[],signed char entry[])
4148 {
4149   int hr;
4150   for(hr=0;hr<HOST_REGS;hr++) {
4151     if(hr!=EXCLUDE_REG) {
4152       if(pre[hr]!=entry[hr]) {
4153         if(entry[hr]>=0) {
4154           if(get_reg(pre,entry[hr])<0) {
4155             assem_debug("loop preload:\n");
4156             //printf("loop preload: %d\n",hr);
4157             if(entry[hr]==0) {
4158               emit_zeroreg(hr);
4159             }
4160             else if(entry[hr]<TEMPREG)
4161             {
4162               emit_loadreg(entry[hr],hr);
4163             }
4164             else if(entry[hr]-64<TEMPREG)
4165             {
4166               emit_loadreg(entry[hr],hr);
4167             }
4168           }
4169         }
4170       }
4171     }
4172   }
4173 }
4174
4175 // Generate address for load/store instruction
4176 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
4177 void address_generation(int i,struct regstat *i_regs,signed char entry[])
4178 {
4179   if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
4180     int ra=-1;
4181     int agr=AGEN1+(i&1);
4182     int mgr=MGEN1+(i&1);
4183     if(itype[i]==LOAD) {
4184       ra=get_reg(i_regs->regmap,rt1[i]);
4185       if(ra<0) ra=get_reg(i_regs->regmap,-1);
4186       assert(ra>=0);
4187     }
4188     if(itype[i]==LOADLR) {
4189       ra=get_reg(i_regs->regmap,FTEMP);
4190     }
4191     if(itype[i]==STORE||itype[i]==STORELR) {
4192       ra=get_reg(i_regs->regmap,agr);
4193       if(ra<0) ra=get_reg(i_regs->regmap,-1);
4194     }
4195     if(itype[i]==C1LS||itype[i]==C2LS) {
4196       if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
4197         ra=get_reg(i_regs->regmap,FTEMP);
4198       else { // SWC1/SDC1/SWC2/SDC2
4199         ra=get_reg(i_regs->regmap,agr);
4200         if(ra<0) ra=get_reg(i_regs->regmap,-1);
4201       }
4202     }
4203     int rs=get_reg(i_regs->regmap,rs1[i]);
4204     int rm=get_reg(i_regs->regmap,TLREG);
4205     if(ra>=0) {
4206       int offset=imm[i];
4207       int c=(i_regs->wasconst>>rs)&1;
4208       if(rs1[i]==0) {
4209         // Using r0 as a base address
4210         /*if(rm>=0) {
4211           if(!entry||entry[rm]!=mgr) {
4212             generate_map_const(offset,rm);
4213           } // else did it in the previous cycle
4214         }*/
4215         if(!entry||entry[ra]!=agr) {
4216           if (opcode[i]==0x22||opcode[i]==0x26) {
4217             emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4218           }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4219             emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4220           }else{
4221             emit_movimm(offset,ra);
4222           }
4223         } // else did it in the previous cycle
4224       }
4225       else if(rs<0) {
4226         if(!entry||entry[ra]!=rs1[i])
4227           emit_loadreg(rs1[i],ra);
4228         //if(!entry||entry[ra]!=rs1[i])
4229         //  printf("poor load scheduling!\n");
4230       }
4231       else if(c) {
4232 #ifndef DISABLE_TLB
4233         if(rm>=0) {
4234           if(!entry||entry[rm]!=mgr) {
4235             if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
4236               // Stores to memory go thru the mapper to detect self-modifying
4237               // code, loads don't.
4238               if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
4239                  (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
4240                 generate_map_const(constmap[i][rs]+offset,rm);
4241             }else{
4242               if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
4243                 generate_map_const(constmap[i][rs]+offset,rm);
4244             }
4245           }
4246         }
4247 #endif
4248         if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
4249           if(!entry||entry[ra]!=agr) {
4250             if (opcode[i]==0x22||opcode[i]==0x26) {
4251               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4252             }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4253               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4254             }else{
4255               #ifdef HOST_IMM_ADDR32
4256               if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4257                  (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4258               #endif
4259               emit_movimm(constmap[i][rs]+offset,ra);
4260             }
4261           } // else did it in the previous cycle
4262         } // else load_consts already did it
4263       }
4264       if(offset&&!c&&rs1[i]) {
4265         if(rs>=0) {
4266           emit_addimm(rs,offset,ra);
4267         }else{
4268           emit_addimm(ra,offset,ra);
4269         }
4270       }
4271     }
4272   }
4273   // Preload constants for next instruction
4274   if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
4275     int agr,ra;
4276     #if !defined(HOST_IMM_ADDR32) && !defined(DISABLE_TLB)
4277     // Mapper entry
4278     agr=MGEN1+((i+1)&1);
4279     ra=get_reg(i_regs->regmap,agr);
4280     if(ra>=0) {
4281       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4282       int offset=imm[i+1];
4283       int c=(regs[i+1].wasconst>>rs)&1;
4284       if(c) {
4285         if(itype[i+1]==STORE||itype[i+1]==STORELR
4286            ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
4287           // Stores to memory go thru the mapper to detect self-modifying
4288           // code, loads don't.
4289           if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4290              (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
4291             generate_map_const(constmap[i+1][rs]+offset,ra);
4292         }else{
4293           if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4294             generate_map_const(constmap[i+1][rs]+offset,ra);
4295         }
4296       }
4297       /*else if(rs1[i]==0) {
4298         generate_map_const(offset,ra);
4299       }*/
4300     }
4301     #endif
4302     // Actual address
4303     agr=AGEN1+((i+1)&1);
4304     ra=get_reg(i_regs->regmap,agr);
4305     if(ra>=0) {
4306       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4307       int offset=imm[i+1];
4308       int c=(regs[i+1].wasconst>>rs)&1;
4309       if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4310         if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4311           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4312         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4313           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4314         }else{
4315           #ifdef HOST_IMM_ADDR32
4316           if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4317              (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4318           #endif
4319           emit_movimm(constmap[i+1][rs]+offset,ra);
4320         }
4321       }
4322       else if(rs1[i+1]==0) {
4323         // Using r0 as a base address
4324         if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4325           emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4326         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4327           emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4328         }else{
4329           emit_movimm(offset,ra);
4330         }
4331       }
4332     }
4333   }
4334 }
4335
4336 int get_final_value(int hr, int i, int *value)
4337 {
4338   int reg=regs[i].regmap[hr];
4339   while(i<slen-1) {
4340     if(regs[i+1].regmap[hr]!=reg) break;
4341     if(!((regs[i+1].isconst>>hr)&1)) break;
4342     if(bt[i+1]) break;
4343     i++;
4344   }
4345   if(i<slen-1) {
4346     if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4347       *value=constmap[i][hr];
4348       return 1;
4349     }
4350     if(!bt[i+1]) {
4351       if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4352         // Load in delay slot, out-of-order execution
4353         if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4354         {
4355           #ifdef HOST_IMM_ADDR32
4356           if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4357           #endif
4358           // Precompute load address
4359           *value=constmap[i][hr]+imm[i+2];
4360           return 1;
4361         }
4362       }
4363       if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4364       {
4365         #ifdef HOST_IMM_ADDR32
4366         if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4367         #endif
4368         // Precompute load address
4369         *value=constmap[i][hr]+imm[i+1];
4370         //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4371         return 1;
4372       }
4373     }
4374   }
4375   *value=constmap[i][hr];
4376   //printf("c=%x\n",(int)constmap[i][hr]);
4377   if(i==slen-1) return 1;
4378   if(reg<64) {
4379     return !((unneeded_reg[i+1]>>reg)&1);
4380   }else{
4381     return !((unneeded_reg_upper[i+1]>>reg)&1);
4382   }
4383 }
4384
4385 // Load registers with known constants
4386 void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4387 {
4388   int hr;
4389   // Load 32-bit regs
4390   for(hr=0;hr<HOST_REGS;hr++) {
4391     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4392       //if(entry[hr]!=regmap[hr]) {
4393       if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4394         if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4395           int value;
4396           if(get_final_value(hr,i,&value)) {
4397             if(value==0) {
4398               emit_zeroreg(hr);
4399             }
4400             else {
4401               emit_movimm(value,hr);
4402             }
4403           }
4404         }
4405       }
4406     }
4407   }
4408   // Load 64-bit regs
4409   for(hr=0;hr<HOST_REGS;hr++) {
4410     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4411       //if(entry[hr]!=regmap[hr]) {
4412       if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4413         if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4414           if((is32>>(regmap[hr]&63))&1) {
4415             int lr=get_reg(regmap,regmap[hr]-64);
4416             assert(lr>=0);
4417             emit_sarimm(lr,31,hr);
4418           }
4419           else
4420           {
4421             int value;
4422             if(get_final_value(hr,i,&value)) {
4423               if(value==0) {
4424                 emit_zeroreg(hr);
4425               }
4426               else {
4427                 emit_movimm(value,hr);
4428               }
4429             }
4430           }
4431         }
4432       }
4433     }
4434   }
4435 }
4436 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4437 {
4438   int hr;
4439   // Load 32-bit regs
4440   for(hr=0;hr<HOST_REGS;hr++) {
4441     if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4442       if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4443         int value=constmap[i][hr];
4444         if(value==0) {
4445           emit_zeroreg(hr);
4446         }
4447         else {
4448           emit_movimm(value,hr);
4449         }
4450       }
4451     }
4452   }
4453   // Load 64-bit regs
4454   for(hr=0;hr<HOST_REGS;hr++) {
4455     if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4456       if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4457         if((is32>>(regmap[hr]&63))&1) {
4458           int lr=get_reg(regmap,regmap[hr]-64);
4459           assert(lr>=0);
4460           emit_sarimm(lr,31,hr);
4461         }
4462         else
4463         {
4464           int value=constmap[i][hr];
4465           if(value==0) {
4466             emit_zeroreg(hr);
4467           }
4468           else {
4469             emit_movimm(value,hr);
4470           }
4471         }
4472       }
4473     }
4474   }
4475 }
4476
4477 // Write out all dirty registers (except cycle count)
4478 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4479 {
4480   int hr;
4481   for(hr=0;hr<HOST_REGS;hr++) {
4482     if(hr!=EXCLUDE_REG) {
4483       if(i_regmap[hr]>0) {
4484         if(i_regmap[hr]!=CCREG) {
4485           if((i_dirty>>hr)&1) {
4486             if(i_regmap[hr]<64) {
4487               emit_storereg(i_regmap[hr],hr);
4488 #ifndef FORCE32
4489               if( ((i_is32>>i_regmap[hr])&1) ) {
4490                 #ifdef DESTRUCTIVE_WRITEBACK
4491                 emit_sarimm(hr,31,hr);
4492                 emit_storereg(i_regmap[hr]|64,hr);
4493                 #else
4494                 emit_sarimm(hr,31,HOST_TEMPREG);
4495                 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4496                 #endif
4497               }
4498 #endif
4499             }else{
4500               if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4501                 emit_storereg(i_regmap[hr],hr);
4502               }
4503             }
4504           }
4505         }
4506       }
4507     }
4508   }
4509 }
4510 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4511 // This writes the registers not written by store_regs_bt
4512 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4513 {
4514   int hr;
4515   int t=(addr-start)>>2;
4516   for(hr=0;hr<HOST_REGS;hr++) {
4517     if(hr!=EXCLUDE_REG) {
4518       if(i_regmap[hr]>0) {
4519         if(i_regmap[hr]!=CCREG) {
4520           if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4521             if((i_dirty>>hr)&1) {
4522               if(i_regmap[hr]<64) {
4523                 emit_storereg(i_regmap[hr],hr);
4524 #ifndef FORCE32
4525                 if( ((i_is32>>i_regmap[hr])&1) ) {
4526                   #ifdef DESTRUCTIVE_WRITEBACK
4527                   emit_sarimm(hr,31,hr);
4528                   emit_storereg(i_regmap[hr]|64,hr);
4529                   #else
4530                   emit_sarimm(hr,31,HOST_TEMPREG);
4531                   emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4532                   #endif
4533                 }
4534 #endif
4535               }else{
4536                 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4537                   emit_storereg(i_regmap[hr],hr);
4538                 }
4539               }
4540             }
4541           }
4542         }
4543       }
4544     }
4545   }
4546 }
4547
4548 // Load all registers (except cycle count)
4549 void load_all_regs(signed char i_regmap[])
4550 {
4551   int hr;
4552   for(hr=0;hr<HOST_REGS;hr++) {
4553     if(hr!=EXCLUDE_REG) {
4554       if(i_regmap[hr]==0) {
4555         emit_zeroreg(hr);
4556       }
4557       else
4558       if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4559       {
4560         emit_loadreg(i_regmap[hr],hr);
4561       }
4562     }
4563   }
4564 }
4565
4566 // Load all current registers also needed by next instruction
4567 void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4568 {
4569   int hr;
4570   for(hr=0;hr<HOST_REGS;hr++) {
4571     if(hr!=EXCLUDE_REG) {
4572       if(get_reg(next_regmap,i_regmap[hr])>=0) {
4573         if(i_regmap[hr]==0) {
4574           emit_zeroreg(hr);
4575         }
4576         else
4577         if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4578         {
4579           emit_loadreg(i_regmap[hr],hr);
4580         }
4581       }
4582     }
4583   }
4584 }
4585
4586 // Load all regs, storing cycle count if necessary
4587 void load_regs_entry(int t)
4588 {
4589   int hr;
4590   if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
4591   else if(ccadj[t]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST(ccadj[t]),HOST_CCREG);
4592   if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4593     emit_storereg(CCREG,HOST_CCREG);
4594   }
4595   // Load 32-bit regs
4596   for(hr=0;hr<HOST_REGS;hr++) {
4597     if(regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
4598       if(regs[t].regmap_entry[hr]==0) {
4599         emit_zeroreg(hr);
4600       }
4601       else if(regs[t].regmap_entry[hr]!=CCREG)
4602       {
4603         emit_loadreg(regs[t].regmap_entry[hr],hr);
4604       }
4605     }
4606   }
4607   // Load 64-bit regs
4608   for(hr=0;hr<HOST_REGS;hr++) {
4609     if(regs[t].regmap_entry[hr]>=64&&regs[t].regmap_entry[hr]<TEMPREG+64) {
4610       assert(regs[t].regmap_entry[hr]!=64);
4611       if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4612         int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4613         if(lr<0) {
4614           emit_loadreg(regs[t].regmap_entry[hr],hr);
4615         }
4616         else
4617         {
4618           emit_sarimm(lr,31,hr);
4619         }
4620       }
4621       else
4622       {
4623         emit_loadreg(regs[t].regmap_entry[hr],hr);
4624       }
4625     }
4626   }
4627 }
4628
4629 // Store dirty registers prior to branch
4630 void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4631 {
4632   if(internal_branch(i_is32,addr))
4633   {
4634     int t=(addr-start)>>2;
4635     int hr;
4636     for(hr=0;hr<HOST_REGS;hr++) {
4637       if(hr!=EXCLUDE_REG) {
4638         if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4639           if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4640             if((i_dirty>>hr)&1) {
4641               if(i_regmap[hr]<64) {
4642                 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4643                   emit_storereg(i_regmap[hr],hr);
4644                   if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4645                     #ifdef DESTRUCTIVE_WRITEBACK
4646                     emit_sarimm(hr,31,hr);
4647                     emit_storereg(i_regmap[hr]|64,hr);
4648                     #else
4649                     emit_sarimm(hr,31,HOST_TEMPREG);
4650                     emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4651                     #endif
4652                   }
4653                 }
4654               }else{
4655                 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4656                   emit_storereg(i_regmap[hr],hr);
4657                 }
4658               }
4659             }
4660           }
4661         }
4662       }
4663     }
4664   }
4665   else
4666   {
4667     // Branch out of this block, write out all dirty regs
4668     wb_dirtys(i_regmap,i_is32,i_dirty);
4669   }
4670 }
4671
4672 // Load all needed registers for branch target
4673 void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4674 {
4675   //if(addr>=start && addr<(start+slen*4))
4676   if(internal_branch(i_is32,addr))
4677   {
4678     int t=(addr-start)>>2;
4679     int hr;
4680     // Store the cycle count before loading something else
4681     if(i_regmap[HOST_CCREG]!=CCREG) {
4682       assert(i_regmap[HOST_CCREG]==-1);
4683     }
4684     if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4685       emit_storereg(CCREG,HOST_CCREG);
4686     }
4687     // Load 32-bit regs
4688     for(hr=0;hr<HOST_REGS;hr++) {
4689       if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
4690         #ifdef DESTRUCTIVE_WRITEBACK
4691         if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4692         #else
4693         if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4694         #endif
4695           if(regs[t].regmap_entry[hr]==0) {
4696             emit_zeroreg(hr);
4697           }
4698           else if(regs[t].regmap_entry[hr]!=CCREG)
4699           {
4700             emit_loadreg(regs[t].regmap_entry[hr],hr);
4701           }
4702         }
4703       }
4704     }
4705     //Load 64-bit regs
4706     for(hr=0;hr<HOST_REGS;hr++) {
4707       if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=64&&regs[t].regmap_entry[hr]<TEMPREG+64) {
4708         if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4709           assert(regs[t].regmap_entry[hr]!=64);
4710           if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4711             int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4712             if(lr<0) {
4713               emit_loadreg(regs[t].regmap_entry[hr],hr);
4714             }
4715             else
4716             {
4717               emit_sarimm(lr,31,hr);
4718             }
4719           }
4720           else
4721           {
4722             emit_loadreg(regs[t].regmap_entry[hr],hr);
4723           }
4724         }
4725         else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4726           int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4727           assert(lr>=0);
4728           emit_sarimm(lr,31,hr);
4729         }
4730       }
4731     }
4732   }
4733 }
4734
4735 int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4736 {
4737   if(addr>=start && addr<start+slen*4-4)
4738   {
4739     int t=(addr-start)>>2;
4740     int hr;
4741     if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4742     for(hr=0;hr<HOST_REGS;hr++)
4743     {
4744       if(hr!=EXCLUDE_REG)
4745       {
4746         if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4747         {
4748           if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
4749           {
4750             return 0;
4751           }
4752           else
4753           if((i_dirty>>hr)&1)
4754           {
4755             if(i_regmap[hr]<TEMPREG)
4756             {
4757               if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4758                 return 0;
4759             }
4760             else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
4761             {
4762               if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4763                 return 0;
4764             }
4765           }
4766         }
4767         else // Same register but is it 32-bit or dirty?
4768         if(i_regmap[hr]>=0)
4769         {
4770           if(!((regs[t].dirty>>hr)&1))
4771           {
4772             if((i_dirty>>hr)&1)
4773             {
4774               if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4775               {
4776                 //printf("%x: dirty no match\n",addr);
4777                 return 0;
4778               }
4779             }
4780           }
4781           if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4782           {
4783             //printf("%x: is32 no match\n",addr);
4784             return 0;
4785           }
4786         }
4787       }
4788     }
4789     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4790 #ifndef FORCE32
4791     if(requires_32bit[t]&~i_is32) return 0;
4792 #endif
4793     // Delay slots are not valid branch targets
4794     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4795     // Delay slots require additional processing, so do not match
4796     if(is_ds[t]) return 0;
4797   }
4798   else
4799   {
4800     int hr;
4801     for(hr=0;hr<HOST_REGS;hr++)
4802     {
4803       if(hr!=EXCLUDE_REG)
4804       {
4805         if(i_regmap[hr]>=0)
4806         {
4807           if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4808           {
4809             if((i_dirty>>hr)&1)
4810             {
4811               return 0;
4812             }
4813           }
4814         }
4815       }
4816     }
4817   }
4818   return 1;
4819 }
4820
4821 // Used when a branch jumps into the delay slot of another branch
4822 void ds_assemble_entry(int i)
4823 {
4824   int t=(ba[i]-start)>>2;
4825   if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4826   assem_debug("Assemble delay slot at %x\n",ba[i]);
4827   assem_debug("<->\n");
4828   if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
4829     wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4830   load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4831   address_generation(t,&regs[t],regs[t].regmap_entry);
4832   if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
4833     load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4834   cop1_usable=0;
4835   is_delayslot=0;
4836   switch(itype[t]) {
4837     case ALU:
4838       alu_assemble(t,&regs[t]);break;
4839     case IMM16:
4840       imm16_assemble(t,&regs[t]);break;
4841     case SHIFT:
4842       shift_assemble(t,&regs[t]);break;
4843     case SHIFTIMM:
4844       shiftimm_assemble(t,&regs[t]);break;
4845     case LOAD:
4846       load_assemble(t,&regs[t]);break;
4847     case LOADLR:
4848       loadlr_assemble(t,&regs[t]);break;
4849     case STORE:
4850       store_assemble(t,&regs[t]);break;
4851     case STORELR:
4852       storelr_assemble(t,&regs[t]);break;
4853     case COP0:
4854       cop0_assemble(t,&regs[t]);break;
4855     case COP1:
4856       cop1_assemble(t,&regs[t]);break;
4857     case C1LS:
4858       c1ls_assemble(t,&regs[t]);break;
4859     case COP2:
4860       cop2_assemble(t,&regs[t]);break;
4861     case C2LS:
4862       c2ls_assemble(t,&regs[t]);break;
4863     case C2OP:
4864       c2op_assemble(t,&regs[t]);break;
4865     case FCONV:
4866       fconv_assemble(t,&regs[t]);break;
4867     case FLOAT:
4868       float_assemble(t,&regs[t]);break;
4869     case FCOMP:
4870       fcomp_assemble(t,&regs[t]);break;
4871     case MULTDIV:
4872       multdiv_assemble(t,&regs[t]);break;
4873     case MOV:
4874       mov_assemble(t,&regs[t]);break;
4875     case SYSCALL:
4876     case HLECALL:
4877     case INTCALL:
4878     case SPAN:
4879     case UJUMP:
4880     case RJUMP:
4881     case CJUMP:
4882     case SJUMP:
4883     case FJUMP:
4884       printf("Jump in the delay slot.  This is probably a bug.\n");
4885   }
4886   store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4887   load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4888   if(internal_branch(regs[t].is32,ba[i]+4))
4889     assem_debug("branch: internal\n");
4890   else
4891     assem_debug("branch: external\n");
4892   assert(internal_branch(regs[t].is32,ba[i]+4));
4893   add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4894   emit_jmp(0);
4895 }
4896
4897 void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4898 {
4899   int count;
4900   int jaddr;
4901   int idle=0;
4902   if(itype[i]==RJUMP)
4903   {
4904     *adj=0;
4905   }
4906   //if(ba[i]>=start && ba[i]<(start+slen*4))
4907   if(internal_branch(branch_regs[i].is32,ba[i]))
4908   {
4909     int t=(ba[i]-start)>>2;
4910     if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4911     else *adj=ccadj[t];
4912   }
4913   else
4914   {
4915     *adj=0;
4916   }
4917   count=ccadj[i];
4918   if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4919     // Idle loop
4920     if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4921     idle=(int)out;
4922     //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4923     emit_andimm(HOST_CCREG,3,HOST_CCREG);
4924     jaddr=(int)out;
4925     emit_jmp(0);
4926   }
4927   else if(*adj==0||invert) {
4928     emit_addimm_and_set_flags(CLOCK_ADJUST(count+2),HOST_CCREG);
4929     jaddr=(int)out;
4930     emit_jns(0);
4931   }
4932   else
4933   {
4934     emit_cmpimm(HOST_CCREG,-CLOCK_ADJUST(count+2));
4935     jaddr=(int)out;
4936     emit_jns(0);
4937   }
4938   add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4939 }
4940
4941 void do_ccstub(int n)
4942 {
4943   literal_pool(256);
4944   assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
4945   set_jump_target(stubs[n][1],(int)out);
4946   int i=stubs[n][4];
4947   if(stubs[n][6]==NULLDS) {
4948     // Delay slot instruction is nullified ("likely" branch)
4949     wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4950   }
4951   else if(stubs[n][6]!=TAKEN) {
4952     wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4953   }
4954   else {
4955     if(internal_branch(branch_regs[i].is32,ba[i]))
4956       wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4957   }
4958   if(stubs[n][5]!=-1)
4959   {
4960     // Save PC as return address
4961     emit_movimm(stubs[n][5],EAX);
4962     emit_writeword(EAX,(int)&pcaddr);
4963   }
4964   else
4965   {
4966     // Return address depends on which way the branch goes
4967     if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
4968     {
4969       int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4970       int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4971       int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4972       int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4973       if(rs1[i]==0)
4974       {
4975         s1l=s2l;s1h=s2h;
4976         s2l=s2h=-1;
4977       }
4978       else if(rs2[i]==0)
4979       {
4980         s2l=s2h=-1;
4981       }
4982       if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
4983         s1h=s2h=-1;
4984       }
4985       assert(s1l>=0);
4986       #ifdef DESTRUCTIVE_WRITEBACK
4987       if(rs1[i]) {
4988         if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
4989           emit_loadreg(rs1[i],s1l);
4990       }
4991       else {
4992         if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
4993           emit_loadreg(rs2[i],s1l);
4994       }
4995       if(s2l>=0)
4996         if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
4997           emit_loadreg(rs2[i],s2l);
4998       #endif
4999       int hr=0;
5000       int addr=-1,alt=-1,ntaddr=-1;
5001       while(hr<HOST_REGS)
5002       {
5003         if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5004            (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5005            (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5006         {
5007           addr=hr++;break;
5008         }
5009         hr++;
5010       }
5011       while(hr<HOST_REGS)
5012       {
5013         if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5014            (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5015            (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5016         {
5017           alt=hr++;break;
5018         }
5019         hr++;
5020       }
5021       if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
5022       {
5023         while(hr<HOST_REGS)
5024         {
5025           if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5026              (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5027              (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5028           {
5029             ntaddr=hr;break;
5030           }
5031           hr++;
5032         }
5033         assert(hr<HOST_REGS);
5034       }
5035       if((opcode[i]&0x2f)==4) // BEQ
5036       {
5037         #ifdef HAVE_CMOV_IMM
5038         if(s1h<0) {
5039           if(s2l>=0) emit_cmp(s1l,s2l);
5040           else emit_test(s1l,s1l);
5041           emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5042         }
5043         else
5044         #endif
5045         {
5046           emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5047           if(s1h>=0) {
5048             if(s2h>=0) emit_cmp(s1h,s2h);
5049             else emit_test(s1h,s1h);
5050             emit_cmovne_reg(alt,addr);
5051           }
5052           if(s2l>=0) emit_cmp(s1l,s2l);
5053           else emit_test(s1l,s1l);
5054           emit_cmovne_reg(alt,addr);
5055         }
5056       }
5057       if((opcode[i]&0x2f)==5) // BNE
5058       {
5059         #ifdef HAVE_CMOV_IMM
5060         if(s1h<0) {
5061           if(s2l>=0) emit_cmp(s1l,s2l);
5062           else emit_test(s1l,s1l);
5063           emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5064         }
5065         else
5066         #endif
5067         {
5068           emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5069           if(s1h>=0) {
5070             if(s2h>=0) emit_cmp(s1h,s2h);
5071             else emit_test(s1h,s1h);
5072             emit_cmovne_reg(alt,addr);
5073           }
5074           if(s2l>=0) emit_cmp(s1l,s2l);
5075           else emit_test(s1l,s1l);
5076           emit_cmovne_reg(alt,addr);
5077         }
5078       }
5079       if((opcode[i]&0x2f)==6) // BLEZ
5080       {
5081         //emit_movimm(ba[i],alt);
5082         //emit_movimm(start+i*4+8,addr);
5083         emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5084         emit_cmpimm(s1l,1);
5085         if(s1h>=0) emit_mov(addr,ntaddr);
5086         emit_cmovl_reg(alt,addr);
5087         if(s1h>=0) {
5088           emit_test(s1h,s1h);
5089           emit_cmovne_reg(ntaddr,addr);
5090           emit_cmovs_reg(alt,addr);
5091         }
5092       }
5093       if((opcode[i]&0x2f)==7) // BGTZ
5094       {
5095         //emit_movimm(ba[i],addr);
5096         //emit_movimm(start+i*4+8,ntaddr);
5097         emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5098         emit_cmpimm(s1l,1);
5099         if(s1h>=0) emit_mov(addr,alt);
5100         emit_cmovl_reg(ntaddr,addr);
5101         if(s1h>=0) {
5102           emit_test(s1h,s1h);
5103           emit_cmovne_reg(alt,addr);
5104           emit_cmovs_reg(ntaddr,addr);
5105         }
5106       }
5107       if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
5108       {
5109         //emit_movimm(ba[i],alt);
5110         //emit_movimm(start+i*4+8,addr);
5111         emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5112         if(s1h>=0) emit_test(s1h,s1h);
5113         else emit_test(s1l,s1l);
5114         emit_cmovs_reg(alt,addr);
5115       }
5116       if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
5117       {
5118         //emit_movimm(ba[i],addr);
5119         //emit_movimm(start+i*4+8,alt);
5120         emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5121         if(s1h>=0) emit_test(s1h,s1h);
5122         else emit_test(s1l,s1l);
5123         emit_cmovs_reg(alt,addr);
5124       }
5125       if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
5126         if(source[i]&0x10000) // BC1T
5127         {
5128           //emit_movimm(ba[i],alt);
5129           //emit_movimm(start+i*4+8,addr);
5130           emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5131           emit_testimm(s1l,0x800000);
5132           emit_cmovne_reg(alt,addr);
5133         }
5134         else // BC1F
5135         {
5136           //emit_movimm(ba[i],addr);
5137           //emit_movimm(start+i*4+8,alt);
5138           emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5139           emit_testimm(s1l,0x800000);
5140           emit_cmovne_reg(alt,addr);
5141         }
5142       }
5143       emit_writeword(addr,(int)&pcaddr);
5144     }
5145     else
5146     if(itype[i]==RJUMP)
5147     {
5148       int r=get_reg(branch_regs[i].regmap,rs1[i]);
5149       if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5150         r=get_reg(branch_regs[i].regmap,RTEMP);
5151       }
5152       emit_writeword(r,(int)&pcaddr);
5153     }
5154     else {printf("Unknown branch type in do_ccstub\n");exit(1);}
5155   }
5156   // Update cycle count
5157   assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5158   if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG);
5159   emit_call((int)cc_interrupt);
5160   if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG);
5161   if(stubs[n][6]==TAKEN) {
5162     if(internal_branch(branch_regs[i].is32,ba[i]))
5163       load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
5164     else if(itype[i]==RJUMP) {
5165       if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5166         emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5167       else
5168         emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
5169     }
5170   }else if(stubs[n][6]==NOTTAKEN) {
5171     if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5172     else load_all_regs(branch_regs[i].regmap);
5173   }else if(stubs[n][6]==NULLDS) {
5174     // Delay slot instruction is nullified ("likely" branch)
5175     if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5176     else load_all_regs(regs[i].regmap);
5177   }else{
5178     load_all_regs(branch_regs[i].regmap);
5179   }
5180   emit_jmp(stubs[n][2]); // return address
5181
5182   /* This works but uses a lot of memory...
5183   emit_readword((int)&last_count,ECX);
5184   emit_add(HOST_CCREG,ECX,EAX);
5185   emit_writeword(EAX,(int)&Count);
5186   emit_call((int)gen_interupt);
5187   emit_readword((int)&Count,HOST_CCREG);
5188   emit_readword((int)&next_interupt,EAX);
5189   emit_readword((int)&pending_exception,EBX);
5190   emit_writeword(EAX,(int)&last_count);
5191   emit_sub(HOST_CCREG,EAX,HOST_CCREG);
5192   emit_test(EBX,EBX);
5193   int jne_instr=(int)out;
5194   emit_jne(0);
5195   if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
5196   load_all_regs(branch_regs[i].regmap);
5197   emit_jmp(stubs[n][2]); // return address
5198   set_jump_target(jne_instr,(int)out);
5199   emit_readword((int)&pcaddr,EAX);
5200   // Call get_addr_ht instead of doing the hash table here.
5201   // This code is executed infrequently and takes up a lot of space
5202   // so smaller is better.
5203   emit_storereg(CCREG,HOST_CCREG);
5204   emit_pushreg(EAX);
5205   emit_call((int)get_addr_ht);
5206   emit_loadreg(CCREG,HOST_CCREG);
5207   emit_addimm(ESP,4,ESP);
5208   emit_jmpreg(EAX);*/
5209 }
5210
5211 add_to_linker(int addr,int target,int ext)
5212 {
5213   link_addr[linkcount][0]=addr;
5214   link_addr[linkcount][1]=target;
5215   link_addr[linkcount][2]=ext;
5216   linkcount++;
5217 }
5218
5219 static void ujump_assemble_write_ra(int i)
5220 {
5221   int rt;
5222   unsigned int return_address;
5223   rt=get_reg(branch_regs[i].regmap,31);
5224   assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5225   //assert(rt>=0);
5226   return_address=start+i*4+8;
5227   if(rt>=0) {
5228     #ifdef USE_MINI_HT
5229     if(internal_branch(branch_regs[i].is32,return_address)&&rt1[i+1]!=31) {
5230       int temp=-1; // note: must be ds-safe
5231       #ifdef HOST_TEMPREG
5232       temp=HOST_TEMPREG;
5233       #endif
5234       if(temp>=0) do_miniht_insert(return_address,rt,temp);
5235       else emit_movimm(return_address,rt);
5236     }
5237     else
5238     #endif
5239     {
5240       #ifdef REG_PREFETCH
5241       if(temp>=0)
5242       {
5243         if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5244       }
5245       #endif
5246       emit_movimm(return_address,rt); // PC into link register
5247       #ifdef IMM_PREFETCH
5248       emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5249       #endif
5250     }
5251   }
5252 }
5253
5254 void ujump_assemble(int i,struct regstat *i_regs)
5255 {
5256   signed char *i_regmap=i_regs->regmap;
5257   int ra_done=0;
5258   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5259   address_generation(i+1,i_regs,regs[i].regmap_entry);
5260   #ifdef REG_PREFETCH
5261   int temp=get_reg(branch_regs[i].regmap,PTEMP);
5262   if(rt1[i]==31&&temp>=0)
5263   {
5264     int return_address=start+i*4+8;
5265     if(get_reg(branch_regs[i].regmap,31)>0)
5266     if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5267   }
5268   #endif
5269   if(rt1[i]==31&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5270     ujump_assemble_write_ra(i); // writeback ra for DS
5271     ra_done=1;
5272   }
5273   ds_assemble(i+1,i_regs);
5274   uint64_t bc_unneeded=branch_regs[i].u;
5275   uint64_t bc_unneeded_upper=branch_regs[i].uu;
5276   bc_unneeded|=1|(1LL<<rt1[i]);
5277   bc_unneeded_upper|=1|(1LL<<rt1[i]);
5278   wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5279                 bc_unneeded,bc_unneeded_upper);
5280   load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5281   if(!ra_done&&rt1[i]==31)
5282     ujump_assemble_write_ra(i);
5283   int cc,adj;
5284   cc=get_reg(branch_regs[i].regmap,CCREG);
5285   assert(cc==HOST_CCREG);
5286   store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5287   #ifdef REG_PREFETCH
5288   if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5289   #endif
5290   do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5291   if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5292   load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5293   if(internal_branch(branch_regs[i].is32,ba[i]))
5294     assem_debug("branch: internal\n");
5295   else
5296     assem_debug("branch: external\n");
5297   if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5298     ds_assemble_entry(i);
5299   }
5300   else {
5301     add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5302     emit_jmp(0);
5303   }
5304 }
5305
5306 static void rjump_assemble_write_ra(int i)
5307 {
5308   int rt,return_address;
5309   assert(rt1[i+1]!=rt1[i]);
5310   assert(rt2[i+1]!=rt1[i]);
5311   rt=get_reg(branch_regs[i].regmap,rt1[i]);
5312   assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5313   assert(rt>=0);
5314   return_address=start+i*4+8;
5315   #ifdef REG_PREFETCH
5316   if(temp>=0)
5317   {
5318     if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5319   }
5320   #endif
5321   emit_movimm(return_address,rt); // PC into link register
5322   #ifdef IMM_PREFETCH
5323   emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5324   #endif
5325 }
5326
5327 void rjump_assemble(int i,struct regstat *i_regs)
5328 {
5329   signed char *i_regmap=i_regs->regmap;
5330   int temp;
5331   int rs,cc,adj;
5332   int ra_done=0;
5333   rs=get_reg(branch_regs[i].regmap,rs1[i]);
5334   assert(rs>=0);
5335   if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5336     // Delay slot abuse, make a copy of the branch address register
5337     temp=get_reg(branch_regs[i].regmap,RTEMP);
5338     assert(temp>=0);
5339     assert(regs[i].regmap[temp]==RTEMP);
5340     emit_mov(rs,temp);
5341     rs=temp;
5342   }
5343   address_generation(i+1,i_regs,regs[i].regmap_entry);
5344   #ifdef REG_PREFETCH
5345   if(rt1[i]==31)
5346   {
5347     if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5348       int return_address=start+i*4+8;
5349       if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5350     }
5351   }
5352   #endif
5353   #ifdef USE_MINI_HT
5354   if(rs1[i]==31) {
5355     int rh=get_reg(regs[i].regmap,RHASH);
5356     if(rh>=0) do_preload_rhash(rh);
5357   }
5358   #endif
5359   if(rt1[i]!=0&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5360     rjump_assemble_write_ra(i);
5361     ra_done=1;
5362   }
5363   ds_assemble(i+1,i_regs);
5364   uint64_t bc_unneeded=branch_regs[i].u;
5365   uint64_t bc_unneeded_upper=branch_regs[i].uu;
5366   bc_unneeded|=1|(1LL<<rt1[i]);
5367   bc_unneeded_upper|=1|(1LL<<rt1[i]);
5368   bc_unneeded&=~(1LL<<rs1[i]);
5369   wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5370                 bc_unneeded,bc_unneeded_upper);
5371   load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5372   if(!ra_done&&rt1[i]!=0)
5373     rjump_assemble_write_ra(i);
5374   cc=get_reg(branch_regs[i].regmap,CCREG);
5375   assert(cc==HOST_CCREG);
5376   #ifdef USE_MINI_HT
5377   int rh=get_reg(branch_regs[i].regmap,RHASH);
5378   int ht=get_reg(branch_regs[i].regmap,RHTBL);
5379   if(rs1[i]==31) {
5380     if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5381     do_preload_rhtbl(ht);
5382     do_rhash(rs,rh);
5383   }
5384   #endif
5385   store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5386   #ifdef DESTRUCTIVE_WRITEBACK
5387   if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5388     if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5389       emit_loadreg(rs1[i],rs);
5390     }
5391   }
5392   #endif
5393   #ifdef REG_PREFETCH
5394   if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5395   #endif
5396   #ifdef USE_MINI_HT
5397   if(rs1[i]==31) {
5398     do_miniht_load(ht,rh);
5399   }
5400   #endif
5401   //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5402   //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5403   //assert(adj==0);
5404   emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5405   add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5406 #ifdef PCSX
5407   if(itype[i+1]==COP0&&(source[i+1]&0x3f)==0x10)
5408     // special case for RFE
5409     emit_jmp(0);
5410   else
5411 #endif
5412   emit_jns(0);
5413   //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5414   #ifdef USE_MINI_HT
5415   if(rs1[i]==31) {
5416     do_miniht_jump(rs,rh,ht);
5417   }
5418   else
5419   #endif
5420   {
5421     //if(rs!=EAX) emit_mov(rs,EAX);
5422     //emit_jmp((int)jump_vaddr_eax);
5423     emit_jmp(jump_vaddr_reg[rs]);
5424   }
5425   /* Check hash table
5426   temp=!rs;
5427   emit_mov(rs,temp);
5428   emit_shrimm(rs,16,rs);
5429   emit_xor(temp,rs,rs);
5430   emit_movzwl_reg(rs,rs);
5431   emit_shlimm(rs,4,rs);
5432   emit_cmpmem_indexed((int)hash_table,rs,temp);
5433   emit_jne((int)out+14);
5434   emit_readword_indexed((int)hash_table+4,rs,rs);
5435   emit_jmpreg(rs);
5436   emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5437   emit_addimm_no_flags(8,rs);
5438   emit_jeq((int)out-17);
5439   // No hit on hash table, call compiler
5440   emit_pushreg(temp);
5441 //DEBUG >
5442 #ifdef DEBUG_CYCLE_COUNT
5443   emit_readword((int)&last_count,ECX);
5444   emit_add(HOST_CCREG,ECX,HOST_CCREG);
5445   emit_readword((int)&next_interupt,ECX);
5446   emit_writeword(HOST_CCREG,(int)&Count);
5447   emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5448   emit_writeword(ECX,(int)&last_count);
5449 #endif
5450 //DEBUG <
5451   emit_storereg(CCREG,HOST_CCREG);
5452   emit_call((int)get_addr);
5453   emit_loadreg(CCREG,HOST_CCREG);
5454   emit_addimm(ESP,4,ESP);
5455   emit_jmpreg(EAX);*/
5456   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5457   if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5458   #endif
5459 }
5460
5461 void cjump_assemble(int i,struct regstat *i_regs)
5462 {
5463   signed char *i_regmap=i_regs->regmap;
5464   int cc;
5465   int match;
5466   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5467   assem_debug("match=%d\n",match);
5468   int s1h,s1l,s2h,s2l;
5469   int prev_cop1_usable=cop1_usable;
5470   int unconditional=0,nop=0;
5471   int only32=0;
5472   int invert=0;
5473   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5474   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5475   if(!match) invert=1;
5476   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5477   if(i>(ba[i]-start)>>2) invert=1;
5478   #endif
5479
5480   if(ooo[i]) {
5481     s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5482     s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5483     s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5484     s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5485   }
5486   else {
5487     s1l=get_reg(i_regmap,rs1[i]);
5488     s1h=get_reg(i_regmap,rs1[i]|64);
5489     s2l=get_reg(i_regmap,rs2[i]);
5490     s2h=get_reg(i_regmap,rs2[i]|64);
5491   }
5492   if(rs1[i]==0&&rs2[i]==0)
5493   {
5494     if(opcode[i]&1) nop=1;
5495     else unconditional=1;
5496     //assert(opcode[i]!=5);
5497     //assert(opcode[i]!=7);
5498     //assert(opcode[i]!=0x15);
5499     //assert(opcode[i]!=0x17);
5500   }
5501   else if(rs1[i]==0)
5502   {
5503     s1l=s2l;s1h=s2h;
5504     s2l=s2h=-1;
5505     only32=(regs[i].was32>>rs2[i])&1;
5506   }
5507   else if(rs2[i]==0)
5508   {
5509     s2l=s2h=-1;
5510     only32=(regs[i].was32>>rs1[i])&1;
5511   }
5512   else {
5513     only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5514   }
5515
5516   if(ooo[i]) {
5517     // Out of order execution (delay slot first)
5518     //printf("OOOE\n");
5519     address_generation(i+1,i_regs,regs[i].regmap_entry);
5520     ds_assemble(i+1,i_regs);
5521     int adj;
5522     uint64_t bc_unneeded=branch_regs[i].u;
5523     uint64_t bc_unneeded_upper=branch_regs[i].uu;
5524     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5525     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5526     bc_unneeded|=1;
5527     bc_unneeded_upper|=1;
5528     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5529                   bc_unneeded,bc_unneeded_upper);
5530     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5531     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5532     cc=get_reg(branch_regs[i].regmap,CCREG);
5533     assert(cc==HOST_CCREG);
5534     if(unconditional)
5535       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5536     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5537     //assem_debug("cycle count (adj)\n");
5538     if(unconditional) {
5539       do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5540       if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5541         if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5542         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5543         if(internal)
5544           assem_debug("branch: internal\n");
5545         else
5546           assem_debug("branch: external\n");
5547         if(internal&&is_ds[(ba[i]-start)>>2]) {
5548           ds_assemble_entry(i);
5549         }
5550         else {
5551           add_to_linker((int)out,ba[i],internal);
5552           emit_jmp(0);
5553         }
5554         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5555         if(((u_int)out)&7) emit_addnop(0);
5556         #endif
5557       }
5558     }
5559     else if(nop) {
5560       emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5561       int jaddr=(int)out;
5562       emit_jns(0);
5563       add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5564     }
5565     else {
5566       int taken=0,nottaken=0,nottaken1=0;
5567       do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5568       if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5569       if(!only32)
5570       {
5571         assert(s1h>=0);
5572         if(opcode[i]==4) // BEQ
5573         {
5574           if(s2h>=0) emit_cmp(s1h,s2h);
5575           else emit_test(s1h,s1h);
5576           nottaken1=(int)out;
5577           emit_jne(1);
5578         }
5579         if(opcode[i]==5) // BNE
5580         {
5581           if(s2h>=0) emit_cmp(s1h,s2h);
5582           else emit_test(s1h,s1h);
5583           if(invert) taken=(int)out;
5584           else add_to_linker((int)out,ba[i],internal);
5585           emit_jne(0);
5586         }
5587         if(opcode[i]==6) // BLEZ
5588         {
5589           emit_test(s1h,s1h);
5590           if(invert) taken=(int)out;
5591           else add_to_linker((int)out,ba[i],internal);
5592           emit_js(0);
5593           nottaken1=(int)out;
5594           emit_jne(1);
5595         }
5596         if(opcode[i]==7) // BGTZ
5597         {
5598           emit_test(s1h,s1h);
5599           nottaken1=(int)out;
5600           emit_js(1);
5601           if(invert) taken=(int)out;
5602           else add_to_linker((int)out,ba[i],internal);
5603           emit_jne(0);
5604         }
5605       } // if(!only32)
5606
5607       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5608       assert(s1l>=0);
5609       if(opcode[i]==4) // BEQ
5610       {
5611         if(s2l>=0) emit_cmp(s1l,s2l);
5612         else emit_test(s1l,s1l);
5613         if(invert){
5614           nottaken=(int)out;
5615           emit_jne(1);
5616         }else{
5617           add_to_linker((int)out,ba[i],internal);
5618           emit_jeq(0);
5619         }
5620       }
5621       if(opcode[i]==5) // BNE
5622       {
5623         if(s2l>=0) emit_cmp(s1l,s2l);
5624         else emit_test(s1l,s1l);
5625         if(invert){
5626           nottaken=(int)out;
5627           emit_jeq(1);
5628         }else{
5629           add_to_linker((int)out,ba[i],internal);
5630           emit_jne(0);
5631         }
5632       }
5633       if(opcode[i]==6) // BLEZ
5634       {
5635         emit_cmpimm(s1l,1);
5636         if(invert){
5637           nottaken=(int)out;
5638           emit_jge(1);
5639         }else{
5640           add_to_linker((int)out,ba[i],internal);
5641           emit_jl(0);
5642         }
5643       }
5644       if(opcode[i]==7) // BGTZ
5645       {
5646         emit_cmpimm(s1l,1);
5647         if(invert){
5648           nottaken=(int)out;
5649           emit_jl(1);
5650         }else{
5651           add_to_linker((int)out,ba[i],internal);
5652           emit_jge(0);
5653         }
5654       }
5655       if(invert) {
5656         if(taken) set_jump_target(taken,(int)out);
5657         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5658         if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5659           if(adj) {
5660             emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5661             add_to_linker((int)out,ba[i],internal);
5662           }else{
5663             emit_addnop(13);
5664             add_to_linker((int)out,ba[i],internal*2);
5665           }
5666           emit_jmp(0);
5667         }else
5668         #endif
5669         {
5670           if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5671           store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5672           load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5673           if(internal)
5674             assem_debug("branch: internal\n");
5675           else
5676             assem_debug("branch: external\n");
5677           if(internal&&is_ds[(ba[i]-start)>>2]) {
5678             ds_assemble_entry(i);
5679           }
5680           else {
5681             add_to_linker((int)out,ba[i],internal);
5682             emit_jmp(0);
5683           }
5684         }
5685         set_jump_target(nottaken,(int)out);
5686       }
5687
5688       if(nottaken1) set_jump_target(nottaken1,(int)out);
5689       if(adj) {
5690         if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
5691       }
5692     } // (!unconditional)
5693   } // if(ooo)
5694   else
5695   {
5696     // In-order execution (branch first)
5697     //if(likely[i]) printf("IOL\n");
5698     //else
5699     //printf("IOE\n");
5700     int taken=0,nottaken=0,nottaken1=0;
5701     if(!unconditional&&!nop) {
5702       if(!only32)
5703       {
5704         assert(s1h>=0);
5705         if((opcode[i]&0x2f)==4) // BEQ
5706         {
5707           if(s2h>=0) emit_cmp(s1h,s2h);
5708           else emit_test(s1h,s1h);
5709           nottaken1=(int)out;
5710           emit_jne(2);
5711         }
5712         if((opcode[i]&0x2f)==5) // BNE
5713         {
5714           if(s2h>=0) emit_cmp(s1h,s2h);
5715           else emit_test(s1h,s1h);
5716           taken=(int)out;
5717           emit_jne(1);
5718         }
5719         if((opcode[i]&0x2f)==6) // BLEZ
5720         {
5721           emit_test(s1h,s1h);
5722           taken=(int)out;
5723           emit_js(1);
5724           nottaken1=(int)out;
5725           emit_jne(2);
5726         }
5727         if((opcode[i]&0x2f)==7) // BGTZ
5728         {
5729           emit_test(s1h,s1h);
5730           nottaken1=(int)out;
5731           emit_js(2);
5732           taken=(int)out;
5733           emit_jne(1);
5734         }
5735       } // if(!only32)
5736
5737       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5738       assert(s1l>=0);
5739       if((opcode[i]&0x2f)==4) // BEQ
5740       {
5741         if(s2l>=0) emit_cmp(s1l,s2l);
5742         else emit_test(s1l,s1l);
5743         nottaken=(int)out;
5744         emit_jne(2);
5745       }
5746       if((opcode[i]&0x2f)==5) // BNE
5747       {
5748         if(s2l>=0) emit_cmp(s1l,s2l);
5749         else emit_test(s1l,s1l);
5750         nottaken=(int)out;
5751         emit_jeq(2);
5752       }
5753       if((opcode[i]&0x2f)==6) // BLEZ
5754       {
5755         emit_cmpimm(s1l,1);
5756         nottaken=(int)out;
5757         emit_jge(2);
5758       }
5759       if((opcode[i]&0x2f)==7) // BGTZ
5760       {
5761         emit_cmpimm(s1l,1);
5762         nottaken=(int)out;
5763         emit_jl(2);
5764       }
5765     } // if(!unconditional)
5766     int adj;
5767     uint64_t ds_unneeded=branch_regs[i].u;
5768     uint64_t ds_unneeded_upper=branch_regs[i].uu;
5769     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5770     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5771     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5772     ds_unneeded|=1;
5773     ds_unneeded_upper|=1;
5774     // branch taken
5775     if(!nop) {
5776       if(taken) set_jump_target(taken,(int)out);
5777       assem_debug("1:\n");
5778       wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5779                     ds_unneeded,ds_unneeded_upper);
5780       // load regs
5781       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5782       address_generation(i+1,&branch_regs[i],0);
5783       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5784       ds_assemble(i+1,&branch_regs[i]);
5785       cc=get_reg(branch_regs[i].regmap,CCREG);
5786       if(cc==-1) {
5787         emit_loadreg(CCREG,cc=HOST_CCREG);
5788         // CHECK: Is the following instruction (fall thru) allocated ok?
5789       }
5790       assert(cc==HOST_CCREG);
5791       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5792       do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5793       assem_debug("cycle count (adj)\n");
5794       if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5795       load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5796       if(internal)
5797         assem_debug("branch: internal\n");
5798       else
5799         assem_debug("branch: external\n");
5800       if(internal&&is_ds[(ba[i]-start)>>2]) {
5801         ds_assemble_entry(i);
5802       }
5803       else {
5804         add_to_linker((int)out,ba[i],internal);
5805         emit_jmp(0);
5806       }
5807     }
5808     // branch not taken
5809     cop1_usable=prev_cop1_usable;
5810     if(!unconditional) {
5811       if(nottaken1) set_jump_target(nottaken1,(int)out);
5812       set_jump_target(nottaken,(int)out);
5813       assem_debug("2:\n");
5814       if(!likely[i]) {
5815         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5816                       ds_unneeded,ds_unneeded_upper);
5817         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5818         address_generation(i+1,&branch_regs[i],0);
5819         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5820         ds_assemble(i+1,&branch_regs[i]);
5821       }
5822       cc=get_reg(branch_regs[i].regmap,CCREG);
5823       if(cc==-1&&!likely[i]) {
5824         // Cycle count isn't in a register, temporarily load it then write it out
5825         emit_loadreg(CCREG,HOST_CCREG);
5826         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5827         int jaddr=(int)out;
5828         emit_jns(0);
5829         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5830         emit_storereg(CCREG,HOST_CCREG);
5831       }
5832       else{
5833         cc=get_reg(i_regmap,CCREG);
5834         assert(cc==HOST_CCREG);
5835         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5836         int jaddr=(int)out;
5837         emit_jns(0);
5838         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5839       }
5840     }
5841   }
5842 }
5843
5844 void sjump_assemble(int i,struct regstat *i_regs)
5845 {
5846   signed char *i_regmap=i_regs->regmap;
5847   int cc;
5848   int match;
5849   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5850   assem_debug("smatch=%d\n",match);
5851   int s1h,s1l;
5852   int prev_cop1_usable=cop1_usable;
5853   int unconditional=0,nevertaken=0;
5854   int only32=0;
5855   int invert=0;
5856   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5857   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5858   if(!match) invert=1;
5859   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5860   if(i>(ba[i]-start)>>2) invert=1;
5861   #endif
5862
5863   //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
5864   //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
5865
5866   if(ooo[i]) {
5867     s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5868     s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5869   }
5870   else {
5871     s1l=get_reg(i_regmap,rs1[i]);
5872     s1h=get_reg(i_regmap,rs1[i]|64);
5873   }
5874   if(rs1[i]==0)
5875   {
5876     if(opcode2[i]&1) unconditional=1;
5877     else nevertaken=1;
5878     // These are never taken (r0 is never less than zero)
5879     //assert(opcode2[i]!=0);
5880     //assert(opcode2[i]!=2);
5881     //assert(opcode2[i]!=0x10);
5882     //assert(opcode2[i]!=0x12);
5883   }
5884   else {
5885     only32=(regs[i].was32>>rs1[i])&1;
5886   }
5887
5888   if(ooo[i]) {
5889     // Out of order execution (delay slot first)
5890     //printf("OOOE\n");
5891     address_generation(i+1,i_regs,regs[i].regmap_entry);
5892     ds_assemble(i+1,i_regs);
5893     int adj;
5894     uint64_t bc_unneeded=branch_regs[i].u;
5895     uint64_t bc_unneeded_upper=branch_regs[i].uu;
5896     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5897     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5898     bc_unneeded|=1;
5899     bc_unneeded_upper|=1;
5900     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5901                   bc_unneeded,bc_unneeded_upper);
5902     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5903     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5904     if(rt1[i]==31) {
5905       int rt,return_address;
5906       rt=get_reg(branch_regs[i].regmap,31);
5907       assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5908       if(rt>=0) {
5909         // Save the PC even if the branch is not taken
5910         return_address=start+i*4+8;
5911         emit_movimm(return_address,rt); // PC into link register
5912         #ifdef IMM_PREFETCH
5913         if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5914         #endif
5915       }
5916     }
5917     cc=get_reg(branch_regs[i].regmap,CCREG);
5918     assert(cc==HOST_CCREG);
5919     if(unconditional)
5920       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5921     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5922     assem_debug("cycle count (adj)\n");
5923     if(unconditional) {
5924       do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5925       if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5926         if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5927         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5928         if(internal)
5929           assem_debug("branch: internal\n");
5930         else
5931           assem_debug("branch: external\n");
5932         if(internal&&is_ds[(ba[i]-start)>>2]) {
5933           ds_assemble_entry(i);
5934         }
5935         else {
5936           add_to_linker((int)out,ba[i],internal);
5937           emit_jmp(0);
5938         }
5939         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5940         if(((u_int)out)&7) emit_addnop(0);
5941         #endif
5942       }
5943     }
5944     else if(nevertaken) {
5945       emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5946       int jaddr=(int)out;
5947       emit_jns(0);
5948       add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5949     }
5950     else {
5951       int nottaken=0;
5952       do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5953       if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5954       if(!only32)
5955       {
5956         assert(s1h>=0);
5957         if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5958         {
5959           emit_test(s1h,s1h);
5960           if(invert){
5961             nottaken=(int)out;
5962             emit_jns(1);
5963           }else{
5964             add_to_linker((int)out,ba[i],internal);
5965             emit_js(0);
5966           }
5967         }
5968         if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5969         {
5970           emit_test(s1h,s1h);
5971           if(invert){
5972             nottaken=(int)out;
5973             emit_js(1);
5974           }else{
5975             add_to_linker((int)out,ba[i],internal);
5976             emit_jns(0);
5977           }
5978         }
5979       } // if(!only32)
5980       else
5981       {
5982         assert(s1l>=0);
5983         if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5984         {
5985           emit_test(s1l,s1l);
5986           if(invert){
5987             nottaken=(int)out;
5988             emit_jns(1);
5989           }else{
5990             add_to_linker((int)out,ba[i],internal);
5991             emit_js(0);
5992           }
5993         }
5994         if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5995         {
5996           emit_test(s1l,s1l);
5997           if(invert){
5998             nottaken=(int)out;
5999             emit_js(1);
6000           }else{
6001             add_to_linker((int)out,ba[i],internal);
6002             emit_jns(0);
6003           }
6004         }
6005       } // if(!only32)
6006
6007       if(invert) {
6008         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6009         if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
6010           if(adj) {
6011             emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6012             add_to_linker((int)out,ba[i],internal);
6013           }else{
6014             emit_addnop(13);
6015             add_to_linker((int)out,ba[i],internal*2);
6016           }
6017           emit_jmp(0);
6018         }else
6019         #endif
6020         {
6021           if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6022           store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6023           load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6024           if(internal)
6025             assem_debug("branch: internal\n");
6026           else
6027             assem_debug("branch: external\n");
6028           if(internal&&is_ds[(ba[i]-start)>>2]) {
6029             ds_assemble_entry(i);
6030           }
6031           else {
6032             add_to_linker((int)out,ba[i],internal);
6033             emit_jmp(0);
6034           }
6035         }
6036         set_jump_target(nottaken,(int)out);
6037       }
6038
6039       if(adj) {
6040         if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
6041       }
6042     } // (!unconditional)
6043   } // if(ooo)
6044   else
6045   {
6046     // In-order execution (branch first)
6047     //printf("IOE\n");
6048     int nottaken=0;
6049     if(rt1[i]==31) {
6050       int rt,return_address;
6051       rt=get_reg(branch_regs[i].regmap,31);
6052       if(rt>=0) {
6053         // Save the PC even if the branch is not taken
6054         return_address=start+i*4+8;
6055         emit_movimm(return_address,rt); // PC into link register
6056         #ifdef IMM_PREFETCH
6057         emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
6058         #endif
6059       }
6060     }
6061     if(!unconditional) {
6062       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6063       if(!only32)
6064       {
6065         assert(s1h>=0);
6066         if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
6067         {
6068           emit_test(s1h,s1h);
6069           nottaken=(int)out;
6070           emit_jns(1);
6071         }
6072         if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
6073         {
6074           emit_test(s1h,s1h);
6075           nottaken=(int)out;
6076           emit_js(1);
6077         }
6078       } // if(!only32)
6079       else
6080       {
6081         assert(s1l>=0);
6082         if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
6083         {
6084           emit_test(s1l,s1l);
6085           nottaken=(int)out;
6086           emit_jns(1);
6087         }
6088         if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
6089         {
6090           emit_test(s1l,s1l);
6091           nottaken=(int)out;
6092           emit_js(1);
6093         }
6094       }
6095     } // if(!unconditional)
6096     int adj;
6097     uint64_t ds_unneeded=branch_regs[i].u;
6098     uint64_t ds_unneeded_upper=branch_regs[i].uu;
6099     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6100     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6101     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6102     ds_unneeded|=1;
6103     ds_unneeded_upper|=1;
6104     // branch taken
6105     if(!nevertaken) {
6106       //assem_debug("1:\n");
6107       wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6108                     ds_unneeded,ds_unneeded_upper);
6109       // load regs
6110       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6111       address_generation(i+1,&branch_regs[i],0);
6112       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6113       ds_assemble(i+1,&branch_regs[i]);
6114       cc=get_reg(branch_regs[i].regmap,CCREG);
6115       if(cc==-1) {
6116         emit_loadreg(CCREG,cc=HOST_CCREG);
6117         // CHECK: Is the following instruction (fall thru) allocated ok?
6118       }
6119       assert(cc==HOST_CCREG);
6120       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6121       do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6122       assem_debug("cycle count (adj)\n");
6123       if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6124       load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6125       if(internal)
6126         assem_debug("branch: internal\n");
6127       else
6128         assem_debug("branch: external\n");
6129       if(internal&&is_ds[(ba[i]-start)>>2]) {
6130         ds_assemble_entry(i);
6131       }
6132       else {
6133         add_to_linker((int)out,ba[i],internal);
6134         emit_jmp(0);
6135       }
6136     }
6137     // branch not taken
6138     cop1_usable=prev_cop1_usable;
6139     if(!unconditional) {
6140       set_jump_target(nottaken,(int)out);
6141       assem_debug("1:\n");
6142       if(!likely[i]) {
6143         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6144                       ds_unneeded,ds_unneeded_upper);
6145         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6146         address_generation(i+1,&branch_regs[i],0);
6147         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6148         ds_assemble(i+1,&branch_regs[i]);
6149       }
6150       cc=get_reg(branch_regs[i].regmap,CCREG);
6151       if(cc==-1&&!likely[i]) {
6152         // Cycle count isn't in a register, temporarily load it then write it out
6153         emit_loadreg(CCREG,HOST_CCREG);
6154         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6155         int jaddr=(int)out;
6156         emit_jns(0);
6157         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6158         emit_storereg(CCREG,HOST_CCREG);
6159       }
6160       else{
6161         cc=get_reg(i_regmap,CCREG);
6162         assert(cc==HOST_CCREG);
6163         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
6164         int jaddr=(int)out;
6165         emit_jns(0);
6166         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6167       }
6168     }
6169   }
6170 }
6171
6172 void fjump_assemble(int i,struct regstat *i_regs)
6173 {
6174   signed char *i_regmap=i_regs->regmap;
6175   int cc;
6176   int match;
6177   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6178   assem_debug("fmatch=%d\n",match);
6179   int fs,cs;
6180   int eaddr;
6181   int invert=0;
6182   int internal=internal_branch(branch_regs[i].is32,ba[i]);
6183   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
6184   if(!match) invert=1;
6185   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6186   if(i>(ba[i]-start)>>2) invert=1;
6187   #endif
6188
6189   if(ooo[i]) {
6190     fs=get_reg(branch_regs[i].regmap,FSREG);
6191     address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
6192   }
6193   else {
6194     fs=get_reg(i_regmap,FSREG);
6195   }
6196
6197   // Check cop1 unusable
6198   if(!cop1_usable) {
6199     cs=get_reg(i_regmap,CSREG);
6200     assert(cs>=0);
6201     emit_testimm(cs,0x20000000);
6202     eaddr=(int)out;
6203     emit_jeq(0);
6204     add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
6205     cop1_usable=1;
6206   }
6207
6208   if(ooo[i]) {
6209     // Out of order execution (delay slot first)
6210     //printf("OOOE\n");
6211     ds_assemble(i+1,i_regs);
6212     int adj;
6213     uint64_t bc_unneeded=branch_regs[i].u;
6214     uint64_t bc_unneeded_upper=branch_regs[i].uu;
6215     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6216     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
6217     bc_unneeded|=1;
6218     bc_unneeded_upper|=1;
6219     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6220                   bc_unneeded,bc_unneeded_upper);
6221     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
6222     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6223     cc=get_reg(branch_regs[i].regmap,CCREG);
6224     assert(cc==HOST_CCREG);
6225     do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6226     assem_debug("cycle count (adj)\n");
6227     if(1) {
6228       int nottaken=0;
6229       if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6230       if(1) {
6231         assert(fs>=0);
6232         emit_testimm(fs,0x800000);
6233         if(source[i]&0x10000) // BC1T
6234         {
6235           if(invert){
6236             nottaken=(int)out;
6237             emit_jeq(1);
6238           }else{
6239             add_to_linker((int)out,ba[i],internal);
6240             emit_jne(0);
6241           }
6242         }
6243         else // BC1F
6244           if(invert){
6245             nottaken=(int)out;
6246             emit_jne(1);
6247           }else{
6248             add_to_linker((int)out,ba[i],internal);
6249             emit_jeq(0);
6250           }
6251         {
6252         }
6253       } // if(!only32)
6254
6255       if(invert) {
6256         if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6257         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6258         else if(match) emit_addnop(13);
6259         #endif
6260         store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6261         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6262         if(internal)
6263           assem_debug("branch: internal\n");
6264         else
6265           assem_debug("branch: external\n");
6266         if(internal&&is_ds[(ba[i]-start)>>2]) {
6267           ds_assemble_entry(i);
6268         }
6269         else {
6270           add_to_linker((int)out,ba[i],internal);
6271           emit_jmp(0);
6272         }
6273         set_jump_target(nottaken,(int)out);
6274       }
6275
6276       if(adj) {
6277         if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
6278       }
6279     } // (!unconditional)
6280   } // if(ooo)
6281   else
6282   {
6283     // In-order execution (branch first)
6284     //printf("IOE\n");
6285     int nottaken=0;
6286     if(1) {
6287       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6288       if(1) {
6289         assert(fs>=0);
6290         emit_testimm(fs,0x800000);
6291         if(source[i]&0x10000) // BC1T
6292         {
6293           nottaken=(int)out;
6294           emit_jeq(1);
6295         }
6296         else // BC1F
6297         {
6298           nottaken=(int)out;
6299           emit_jne(1);
6300         }
6301       }
6302     } // if(!unconditional)
6303     int adj;
6304     uint64_t ds_unneeded=branch_regs[i].u;
6305     uint64_t ds_unneeded_upper=branch_regs[i].uu;
6306     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6307     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6308     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6309     ds_unneeded|=1;
6310     ds_unneeded_upper|=1;
6311     // branch taken
6312     //assem_debug("1:\n");
6313     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6314                   ds_unneeded,ds_unneeded_upper);
6315     // load regs
6316     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6317     address_generation(i+1,&branch_regs[i],0);
6318     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6319     ds_assemble(i+1,&branch_regs[i]);
6320     cc=get_reg(branch_regs[i].regmap,CCREG);
6321     if(cc==-1) {
6322       emit_loadreg(CCREG,cc=HOST_CCREG);
6323       // CHECK: Is the following instruction (fall thru) allocated ok?
6324     }
6325     assert(cc==HOST_CCREG);
6326     store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6327     do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6328     assem_debug("cycle count (adj)\n");
6329     if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6330     load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6331     if(internal)
6332       assem_debug("branch: internal\n");
6333     else
6334       assem_debug("branch: external\n");
6335     if(internal&&is_ds[(ba[i]-start)>>2]) {
6336       ds_assemble_entry(i);
6337     }
6338     else {
6339       add_to_linker((int)out,ba[i],internal);
6340       emit_jmp(0);
6341     }
6342
6343     // branch not taken
6344     if(1) { // <- FIXME (don't need this)
6345       set_jump_target(nottaken,(int)out);
6346       assem_debug("1:\n");
6347       if(!likely[i]) {
6348         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6349                       ds_unneeded,ds_unneeded_upper);
6350         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6351         address_generation(i+1,&branch_regs[i],0);
6352         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6353         ds_assemble(i+1,&branch_regs[i]);
6354       }
6355       cc=get_reg(branch_regs[i].regmap,CCREG);
6356       if(cc==-1&&!likely[i]) {
6357         // Cycle count isn't in a register, temporarily load it then write it out
6358         emit_loadreg(CCREG,HOST_CCREG);
6359         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6360         int jaddr=(int)out;
6361         emit_jns(0);
6362         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6363         emit_storereg(CCREG,HOST_CCREG);
6364       }
6365       else{
6366         cc=get_reg(i_regmap,CCREG);
6367         assert(cc==HOST_CCREG);
6368         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
6369         int jaddr=(int)out;
6370         emit_jns(0);
6371         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6372       }
6373     }
6374   }
6375 }
6376
6377 static void pagespan_assemble(int i,struct regstat *i_regs)
6378 {
6379   int s1l=get_reg(i_regs->regmap,rs1[i]);
6380   int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6381   int s2l=get_reg(i_regs->regmap,rs2[i]);
6382   int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6383   void *nt_branch=NULL;
6384   int taken=0;
6385   int nottaken=0;
6386   int unconditional=0;
6387   if(rs1[i]==0)
6388   {
6389     s1l=s2l;s1h=s2h;
6390     s2l=s2h=-1;
6391   }
6392   else if(rs2[i]==0)
6393   {
6394     s2l=s2h=-1;
6395   }
6396   if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6397     s1h=s2h=-1;
6398   }
6399   int hr=0;
6400   int addr,alt,ntaddr;
6401   if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6402   else {
6403     while(hr<HOST_REGS)
6404     {
6405       if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6406          (i_regs->regmap[hr]&63)!=rs1[i] &&
6407          (i_regs->regmap[hr]&63)!=rs2[i] )
6408       {
6409         addr=hr++;break;
6410       }
6411       hr++;
6412     }
6413   }
6414   while(hr<HOST_REGS)
6415   {
6416     if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6417        (i_regs->regmap[hr]&63)!=rs1[i] &&
6418        (i_regs->regmap[hr]&63)!=rs2[i] )
6419     {
6420       alt=hr++;break;
6421     }
6422     hr++;
6423   }
6424   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6425   {
6426     while(hr<HOST_REGS)
6427     {
6428       if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6429          (i_regs->regmap[hr]&63)!=rs1[i] &&
6430          (i_regs->regmap[hr]&63)!=rs2[i] )
6431       {
6432         ntaddr=hr;break;
6433       }
6434       hr++;
6435     }
6436   }
6437   assert(hr<HOST_REGS);
6438   if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6439     load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6440   }
6441   emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6442   if(opcode[i]==2) // J
6443   {
6444     unconditional=1;
6445   }
6446   if(opcode[i]==3) // JAL
6447   {
6448     // TODO: mini_ht
6449     int rt=get_reg(i_regs->regmap,31);
6450     emit_movimm(start+i*4+8,rt);
6451     unconditional=1;
6452   }
6453   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6454   {
6455     emit_mov(s1l,addr);
6456     if(opcode2[i]==9) // JALR
6457     {
6458       int rt=get_reg(i_regs->regmap,rt1[i]);
6459       emit_movimm(start+i*4+8,rt);
6460     }
6461   }
6462   if((opcode[i]&0x3f)==4) // BEQ
6463   {
6464     if(rs1[i]==rs2[i])
6465     {
6466       unconditional=1;
6467     }
6468     else
6469     #ifdef HAVE_CMOV_IMM
6470     if(s1h<0) {
6471       if(s2l>=0) emit_cmp(s1l,s2l);
6472       else emit_test(s1l,s1l);
6473       emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6474     }
6475     else
6476     #endif
6477     {
6478       assert(s1l>=0);
6479       emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6480       if(s1h>=0) {
6481         if(s2h>=0) emit_cmp(s1h,s2h);
6482         else emit_test(s1h,s1h);
6483         emit_cmovne_reg(alt,addr);
6484       }
6485       if(s2l>=0) emit_cmp(s1l,s2l);
6486       else emit_test(s1l,s1l);
6487       emit_cmovne_reg(alt,addr);
6488     }
6489   }
6490   if((opcode[i]&0x3f)==5) // BNE
6491   {
6492     #ifdef HAVE_CMOV_IMM
6493     if(s1h<0) {
6494       if(s2l>=0) emit_cmp(s1l,s2l);
6495       else emit_test(s1l,s1l);
6496       emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6497     }
6498     else
6499     #endif
6500     {
6501       assert(s1l>=0);
6502       emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6503       if(s1h>=0) {
6504         if(s2h>=0) emit_cmp(s1h,s2h);
6505         else emit_test(s1h,s1h);
6506         emit_cmovne_reg(alt,addr);
6507       }
6508       if(s2l>=0) emit_cmp(s1l,s2l);
6509       else emit_test(s1l,s1l);
6510       emit_cmovne_reg(alt,addr);
6511     }
6512   }
6513   if((opcode[i]&0x3f)==0x14) // BEQL
6514   {
6515     if(s1h>=0) {
6516       if(s2h>=0) emit_cmp(s1h,s2h);
6517       else emit_test(s1h,s1h);
6518       nottaken=(int)out;
6519       emit_jne(0);
6520     }
6521     if(s2l>=0) emit_cmp(s1l,s2l);
6522     else emit_test(s1l,s1l);
6523     if(nottaken) set_jump_target(nottaken,(int)out);
6524     nottaken=(int)out;
6525     emit_jne(0);
6526   }
6527   if((opcode[i]&0x3f)==0x15) // BNEL
6528   {
6529     if(s1h>=0) {
6530       if(s2h>=0) emit_cmp(s1h,s2h);
6531       else emit_test(s1h,s1h);
6532       taken=(int)out;
6533       emit_jne(0);
6534     }
6535     if(s2l>=0) emit_cmp(s1l,s2l);
6536     else emit_test(s1l,s1l);
6537     nottaken=(int)out;
6538     emit_jeq(0);
6539     if(taken) set_jump_target(taken,(int)out);
6540   }
6541   if((opcode[i]&0x3f)==6) // BLEZ
6542   {
6543     emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6544     emit_cmpimm(s1l,1);
6545     if(s1h>=0) emit_mov(addr,ntaddr);
6546     emit_cmovl_reg(alt,addr);
6547     if(s1h>=0) {
6548       emit_test(s1h,s1h);
6549       emit_cmovne_reg(ntaddr,addr);
6550       emit_cmovs_reg(alt,addr);
6551     }
6552   }
6553   if((opcode[i]&0x3f)==7) // BGTZ
6554   {
6555     emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6556     emit_cmpimm(s1l,1);
6557     if(s1h>=0) emit_mov(addr,alt);
6558     emit_cmovl_reg(ntaddr,addr);
6559     if(s1h>=0) {
6560       emit_test(s1h,s1h);
6561       emit_cmovne_reg(alt,addr);
6562       emit_cmovs_reg(ntaddr,addr);
6563     }
6564   }
6565   if((opcode[i]&0x3f)==0x16) // BLEZL
6566   {
6567     assert((opcode[i]&0x3f)!=0x16);
6568   }
6569   if((opcode[i]&0x3f)==0x17) // BGTZL
6570   {
6571     assert((opcode[i]&0x3f)!=0x17);
6572   }
6573   assert(opcode[i]!=1); // BLTZ/BGEZ
6574
6575   //FIXME: Check CSREG
6576   if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6577     if((source[i]&0x30000)==0) // BC1F
6578     {
6579       emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6580       emit_testimm(s1l,0x800000);
6581       emit_cmovne_reg(alt,addr);
6582     }
6583     if((source[i]&0x30000)==0x10000) // BC1T
6584     {
6585       emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6586       emit_testimm(s1l,0x800000);
6587       emit_cmovne_reg(alt,addr);
6588     }
6589     if((source[i]&0x30000)==0x20000) // BC1FL
6590     {
6591       emit_testimm(s1l,0x800000);
6592       nottaken=(int)out;
6593       emit_jne(0);
6594     }
6595     if((source[i]&0x30000)==0x30000) // BC1TL
6596     {
6597       emit_testimm(s1l,0x800000);
6598       nottaken=(int)out;
6599       emit_jeq(0);
6600     }
6601   }
6602
6603   assert(i_regs->regmap[HOST_CCREG]==CCREG);
6604   wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6605   if(likely[i]||unconditional)
6606   {
6607     emit_movimm(ba[i],HOST_BTREG);
6608   }
6609   else if(addr!=HOST_BTREG)
6610   {
6611     emit_mov(addr,HOST_BTREG);
6612   }
6613   void *branch_addr=out;
6614   emit_jmp(0);
6615   int target_addr=start+i*4+5;
6616   void *stub=out;
6617   void *compiled_target_addr=check_addr(target_addr);
6618   emit_extjump_ds((int)branch_addr,target_addr);
6619   if(compiled_target_addr) {
6620     set_jump_target((int)branch_addr,(int)compiled_target_addr);
6621     add_link(target_addr,stub);
6622   }
6623   else set_jump_target((int)branch_addr,(int)stub);
6624   if(likely[i]) {
6625     // Not-taken path
6626     set_jump_target((int)nottaken,(int)out);
6627     wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6628     void *branch_addr=out;
6629     emit_jmp(0);
6630     int target_addr=start+i*4+8;
6631     void *stub=out;
6632     void *compiled_target_addr=check_addr(target_addr);
6633     emit_extjump_ds((int)branch_addr,target_addr);
6634     if(compiled_target_addr) {
6635       set_jump_target((int)branch_addr,(int)compiled_target_addr);
6636       add_link(target_addr,stub);
6637     }
6638     else set_jump_target((int)branch_addr,(int)stub);
6639   }
6640 }
6641
6642 // Assemble the delay slot for the above
6643 static void pagespan_ds()
6644 {
6645   assem_debug("initial delay slot:\n");
6646   u_int vaddr=start+1;
6647   u_int page=get_page(vaddr);
6648   u_int vpage=get_vpage(vaddr);
6649   ll_add(jump_dirty+vpage,vaddr,(void *)out);
6650   do_dirty_stub_ds();
6651   ll_add(jump_in+page,vaddr,(void *)out);
6652   assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6653   if(regs[0].regmap[HOST_CCREG]!=CCREG)
6654     wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6655   if(regs[0].regmap[HOST_BTREG]!=BTREG)
6656     emit_writeword(HOST_BTREG,(int)&branch_target);
6657   load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6658   address_generation(0,&regs[0],regs[0].regmap_entry);
6659   if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
6660     load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6661   cop1_usable=0;
6662   is_delayslot=0;
6663   switch(itype[0]) {
6664     case ALU:
6665       alu_assemble(0,&regs[0]);break;
6666     case IMM16:
6667       imm16_assemble(0,&regs[0]);break;
6668     case SHIFT:
6669       shift_assemble(0,&regs[0]);break;
6670     case SHIFTIMM:
6671       shiftimm_assemble(0,&regs[0]);break;
6672     case LOAD:
6673       load_assemble(0,&regs[0]);break;
6674     case LOADLR:
6675       loadlr_assemble(0,&regs[0]);break;
6676     case STORE:
6677       store_assemble(0,&regs[0]);break;
6678     case STORELR:
6679       storelr_assemble(0,&regs[0]);break;
6680     case COP0:
6681       cop0_assemble(0,&regs[0]);break;
6682     case COP1:
6683       cop1_assemble(0,&regs[0]);break;
6684     case C1LS:
6685       c1ls_assemble(0,&regs[0]);break;
6686     case COP2:
6687       cop2_assemble(0,&regs[0]);break;
6688     case C2LS:
6689       c2ls_assemble(0,&regs[0]);break;
6690     case C2OP:
6691       c2op_assemble(0,&regs[0]);break;
6692     case FCONV:
6693       fconv_assemble(0,&regs[0]);break;
6694     case FLOAT:
6695       float_assemble(0,&regs[0]);break;
6696     case FCOMP:
6697       fcomp_assemble(0,&regs[0]);break;
6698     case MULTDIV:
6699       multdiv_assemble(0,&regs[0]);break;
6700     case MOV:
6701       mov_assemble(0,&regs[0]);break;
6702     case SYSCALL:
6703     case HLECALL:
6704     case INTCALL:
6705     case SPAN:
6706     case UJUMP:
6707     case RJUMP:
6708     case CJUMP:
6709     case SJUMP:
6710     case FJUMP:
6711       printf("Jump in the delay slot.  This is probably a bug.\n");
6712   }
6713   int btaddr=get_reg(regs[0].regmap,BTREG);
6714   if(btaddr<0) {
6715     btaddr=get_reg(regs[0].regmap,-1);
6716     emit_readword((int)&branch_target,btaddr);
6717   }
6718   assert(btaddr!=HOST_CCREG);
6719   if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6720 #ifdef HOST_IMM8
6721   emit_movimm(start+4,HOST_TEMPREG);
6722   emit_cmp(btaddr,HOST_TEMPREG);
6723 #else
6724   emit_cmpimm(btaddr,start+4);
6725 #endif
6726   int branch=(int)out;
6727   emit_jeq(0);
6728   store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6729   emit_jmp(jump_vaddr_reg[btaddr]);
6730   set_jump_target(branch,(int)out);
6731   store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6732   load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6733 }
6734
6735 // Basic liveness analysis for MIPS registers
6736 void unneeded_registers(int istart,int iend,int r)
6737 {
6738   int i;
6739   uint64_t u,uu,gte_u,b,bu,gte_bu;
6740   uint64_t temp_u,temp_uu,temp_gte_u;
6741   uint64_t tdep;
6742   if(iend==slen-1) {
6743     u=1;uu=1;
6744   }else{
6745     u=unneeded_reg[iend+1];
6746     uu=unneeded_reg_upper[iend+1];
6747     u=1;uu=1;
6748   }
6749   gte_u=temp_gte_u=0;
6750
6751   for (i=iend;i>=istart;i--)
6752   {
6753     //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6754     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6755     {
6756       // If subroutine call, flag return address as a possible branch target
6757       if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6758
6759       if(ba[i]<start || ba[i]>=(start+slen*4))
6760       {
6761         // Branch out of this block, flush all regs
6762         u=1;
6763         uu=1;
6764         gte_u=0;
6765         /* Hexagon hack
6766         if(itype[i]==UJUMP&&rt1[i]==31)
6767         {
6768           uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6769         }
6770         if(itype[i]==RJUMP&&rs1[i]==31)
6771         {
6772           uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6773         }
6774         if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
6775           if(itype[i]==UJUMP&&rt1[i]==31)
6776           {
6777             //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6778             uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6779           }
6780           if(itype[i]==RJUMP&&rs1[i]==31)
6781           {
6782             //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6783             uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6784           }
6785         }*/
6786         branch_unneeded_reg[i]=u;
6787         branch_unneeded_reg_upper[i]=uu;
6788         // Merge in delay slot
6789         tdep=(~uu>>rt1[i+1])&1;
6790         u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6791         uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6792         u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6793         uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6794         uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6795         u|=1;uu|=1;
6796         gte_u|=gte_rt[i+1];
6797         gte_u&=~gte_rs[i+1];
6798         // If branch is "likely" (and conditional)
6799         // then we skip the delay slot on the fall-thru path
6800         if(likely[i]) {
6801           if(i<slen-1) {
6802             u&=unneeded_reg[i+2];
6803             uu&=unneeded_reg_upper[i+2];
6804             gte_u&=gte_unneeded[i+2];
6805           }
6806           else
6807           {
6808             u=1;
6809             uu=1;
6810             gte_u=0;
6811           }
6812         }
6813       }
6814       else
6815       {
6816         // Internal branch, flag target
6817         bt[(ba[i]-start)>>2]=1;
6818         if(ba[i]<=start+i*4) {
6819           // Backward branch
6820           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6821           {
6822             // Unconditional branch
6823             temp_u=1;temp_uu=1;
6824             temp_gte_u=0;
6825           } else {
6826             // Conditional branch (not taken case)
6827             temp_u=unneeded_reg[i+2];
6828             temp_uu=unneeded_reg_upper[i+2];
6829             temp_gte_u&=gte_unneeded[i+2];
6830           }
6831           // Merge in delay slot
6832           tdep=(~temp_uu>>rt1[i+1])&1;
6833           temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6834           temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6835           temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6836           temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6837           temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6838           temp_u|=1;temp_uu|=1;
6839           temp_gte_u|=gte_rt[i+1];
6840           temp_gte_u&=~gte_rs[i+1];
6841           // If branch is "likely" (and conditional)
6842           // then we skip the delay slot on the fall-thru path
6843           if(likely[i]) {
6844             if(i<slen-1) {
6845               temp_u&=unneeded_reg[i+2];
6846               temp_uu&=unneeded_reg_upper[i+2];
6847               temp_gte_u&=gte_unneeded[i+2];
6848             }
6849             else
6850             {
6851               temp_u=1;
6852               temp_uu=1;
6853               temp_gte_u=0;
6854             }
6855           }
6856           tdep=(~temp_uu>>rt1[i])&1;
6857           temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6858           temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6859           temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6860           temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6861           temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6862           temp_u|=1;temp_uu|=1;
6863           temp_gte_u|=gte_rt[i];
6864           temp_gte_u&=~gte_rs[i];
6865           unneeded_reg[i]=temp_u;
6866           unneeded_reg_upper[i]=temp_uu;
6867           gte_unneeded[i]=temp_gte_u;
6868           // Only go three levels deep.  This recursion can take an
6869           // excessive amount of time if there are a lot of nested loops.
6870           if(r<2) {
6871             unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6872           }else{
6873             unneeded_reg[(ba[i]-start)>>2]=1;
6874             unneeded_reg_upper[(ba[i]-start)>>2]=1;
6875             gte_unneeded[(ba[i]-start)>>2]=0;
6876           }
6877         } /*else*/ if(1) {
6878           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6879           {
6880             // Unconditional branch
6881             u=unneeded_reg[(ba[i]-start)>>2];
6882             uu=unneeded_reg_upper[(ba[i]-start)>>2];
6883             gte_u=gte_unneeded[(ba[i]-start)>>2];
6884             branch_unneeded_reg[i]=u;
6885             branch_unneeded_reg_upper[i]=uu;
6886         //u=1;
6887         //uu=1;
6888         //branch_unneeded_reg[i]=u;
6889         //branch_unneeded_reg_upper[i]=uu;
6890             // Merge in delay slot
6891             tdep=(~uu>>rt1[i+1])&1;
6892             u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6893             uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6894             u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6895             uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6896             uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6897             u|=1;uu|=1;
6898             gte_u|=gte_rt[i+1];
6899             gte_u&=~gte_rs[i+1];
6900           } else {
6901             // Conditional branch
6902             b=unneeded_reg[(ba[i]-start)>>2];
6903             bu=unneeded_reg_upper[(ba[i]-start)>>2];
6904             gte_bu=gte_unneeded[(ba[i]-start)>>2];
6905             branch_unneeded_reg[i]=b;
6906             branch_unneeded_reg_upper[i]=bu;
6907         //b=1;
6908         //bu=1;
6909         //branch_unneeded_reg[i]=b;
6910         //branch_unneeded_reg_upper[i]=bu;
6911             // Branch delay slot
6912             tdep=(~uu>>rt1[i+1])&1;
6913             b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6914             bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6915             b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6916             bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6917             bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6918             b|=1;bu|=1;
6919             gte_bu|=gte_rt[i+1];
6920             gte_bu&=~gte_rs[i+1];
6921             // If branch is "likely" then we skip the
6922             // delay slot on the fall-thru path
6923             if(likely[i]) {
6924               u=b;
6925               uu=bu;
6926               gte_u=gte_bu;
6927               if(i<slen-1) {
6928                 u&=unneeded_reg[i+2];
6929                 uu&=unneeded_reg_upper[i+2];
6930                 gte_u&=gte_unneeded[i+2];
6931         //u=1;
6932         //uu=1;
6933               }
6934             } else {
6935               u&=b;
6936               uu&=bu;
6937               gte_u&=gte_bu;
6938         //u=1;
6939         //uu=1;
6940             }
6941             if(i<slen-1) {
6942               branch_unneeded_reg[i]&=unneeded_reg[i+2];
6943               branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6944         //branch_unneeded_reg[i]=1;
6945         //branch_unneeded_reg_upper[i]=1;
6946             } else {
6947               branch_unneeded_reg[i]=1;
6948               branch_unneeded_reg_upper[i]=1;
6949             }
6950           }
6951         }
6952       }
6953     }
6954     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
6955     {
6956       // SYSCALL instruction (software interrupt)
6957       u=1;
6958       uu=1;
6959     }
6960     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6961     {
6962       // ERET instruction (return from interrupt)
6963       u=1;
6964       uu=1;
6965     }
6966     //u=uu=1; // DEBUG
6967     tdep=(~uu>>rt1[i])&1;
6968     // Written registers are unneeded
6969     u|=1LL<<rt1[i];
6970     u|=1LL<<rt2[i];
6971     uu|=1LL<<rt1[i];
6972     uu|=1LL<<rt2[i];
6973     gte_u|=gte_rt[i];
6974     // Accessed registers are needed
6975     u&=~(1LL<<rs1[i]);
6976     u&=~(1LL<<rs2[i]);
6977     uu&=~(1LL<<us1[i]);
6978     uu&=~(1LL<<us2[i]);
6979     gte_u&=~gte_rs[i];
6980     // Source-target dependencies
6981     uu&=~(tdep<<dep1[i]);
6982     uu&=~(tdep<<dep2[i]);
6983     // R0 is always unneeded
6984     u|=1;uu|=1;
6985     // Save it
6986     unneeded_reg[i]=u;
6987     unneeded_reg_upper[i]=uu;
6988     gte_unneeded[i]=gte_u;
6989     /*
6990     printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6991     printf("U:");
6992     int r;
6993     for(r=1;r<=CCREG;r++) {
6994       if((unneeded_reg[i]>>r)&1) {
6995         if(r==HIREG) printf(" HI");
6996         else if(r==LOREG) printf(" LO");
6997         else printf(" r%d",r);
6998       }
6999     }
7000     printf(" UU:");
7001     for(r=1;r<=CCREG;r++) {
7002       if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
7003         if(r==HIREG) printf(" HI");
7004         else if(r==LOREG) printf(" LO");
7005         else printf(" r%d",r);
7006       }
7007     }
7008     printf("\n");*/
7009   }
7010 #ifdef FORCE32
7011   for (i=iend;i>=istart;i--)
7012   {
7013     unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
7014   }
7015 #endif
7016 }
7017
7018 // Identify registers which are likely to contain 32-bit values
7019 // This is used to predict whether any branches will jump to a
7020 // location with 64-bit values in registers.
7021 static void provisional_32bit()
7022 {
7023   int i,j;
7024   uint64_t is32=1;
7025   uint64_t lastbranch=1;
7026
7027   for(i=0;i<slen;i++)
7028   {
7029     if(i>0) {
7030       if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
7031         if(i>1) is32=lastbranch;
7032         else is32=1;
7033       }
7034     }
7035     if(i>1)
7036     {
7037       if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
7038         if(likely[i-2]) {
7039           if(i>2) is32=lastbranch;
7040           else is32=1;
7041         }
7042       }
7043       if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
7044       {
7045         if(rs1[i-2]==0||rs2[i-2]==0)
7046         {
7047           if(rs1[i-2]) {
7048             is32|=1LL<<rs1[i-2];
7049           }
7050           if(rs2[i-2]) {
7051             is32|=1LL<<rs2[i-2];
7052           }
7053         }
7054       }
7055     }
7056     // If something jumps here with 64-bit values
7057     // then promote those registers to 64 bits
7058     if(bt[i])
7059     {
7060       uint64_t temp_is32=is32;
7061       for(j=i-1;j>=0;j--)
7062       {
7063         if(ba[j]==start+i*4)
7064           //temp_is32&=branch_regs[j].is32;
7065           temp_is32&=p32[j];
7066       }
7067       for(j=i;j<slen;j++)
7068       {
7069         if(ba[j]==start+i*4)
7070           temp_is32=1;
7071       }
7072       is32=temp_is32;
7073     }
7074     int type=itype[i];
7075     int op=opcode[i];
7076     int op2=opcode2[i];
7077     int rt=rt1[i];
7078     int s1=rs1[i];
7079     int s2=rs2[i];
7080     if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
7081       // Branches don't write registers, consider the delay slot instead.
7082       type=itype[i+1];
7083       op=opcode[i+1];
7084       op2=opcode2[i+1];
7085       rt=rt1[i+1];
7086       s1=rs1[i+1];
7087       s2=rs2[i+1];
7088       lastbranch=is32;
7089     }
7090     switch(type) {
7091       case LOAD:
7092         if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
7093            opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
7094           is32&=~(1LL<<rt);
7095         else
7096           is32|=1LL<<rt;
7097         break;
7098       case STORE:
7099       case STORELR:
7100         break;
7101       case LOADLR:
7102         if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
7103         if(op==0x22) is32|=1LL<<rt; // LWL
7104         break;
7105       case IMM16:
7106         if (op==0x08||op==0x09|| // ADDI/ADDIU
7107             op==0x0a||op==0x0b|| // SLTI/SLTIU
7108             op==0x0c|| // ANDI
7109             op==0x0f)  // LUI
7110         {
7111           is32|=1LL<<rt;
7112         }
7113         if(op==0x18||op==0x19) { // DADDI/DADDIU
7114           is32&=~(1LL<<rt);
7115           //if(imm[i]==0)
7116           //  is32|=((is32>>s1)&1LL)<<rt;
7117         }
7118         if(op==0x0d||op==0x0e) { // ORI/XORI
7119           uint64_t sr=((is32>>s1)&1LL);
7120           is32&=~(1LL<<rt);
7121           is32|=sr<<rt;
7122         }
7123         break;
7124       case UJUMP:
7125         break;
7126       case RJUMP:
7127         break;
7128       case CJUMP:
7129         break;
7130       case SJUMP:
7131         break;
7132       case FJUMP:
7133         break;
7134       case ALU:
7135         if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
7136           is32|=1LL<<rt;
7137         }
7138         if(op2==0x2a||op2==0x2b) { // SLT/SLTU
7139           is32|=1LL<<rt;
7140         }
7141         else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
7142           uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
7143           is32&=~(1LL<<rt);
7144           is32|=sr<<rt;
7145         }
7146         else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
7147           if(s1==0&&s2==0) {
7148             is32|=1LL<<rt;
7149           }
7150           else if(s2==0) {
7151             uint64_t sr=((is32>>s1)&1LL);
7152             is32&=~(1LL<<rt);
7153             is32|=sr<<rt;
7154           }
7155           else if(s1==0) {
7156             uint64_t sr=((is32>>s2)&1LL);
7157             is32&=~(1LL<<rt);
7158             is32|=sr<<rt;
7159           }
7160           else {
7161             is32&=~(1LL<<rt);
7162           }
7163         }
7164         else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
7165           if(s1==0&&s2==0) {
7166             is32|=1LL<<rt;
7167           }
7168           else if(s2==0) {
7169             uint64_t sr=((is32>>s1)&1LL);
7170             is32&=~(1LL<<rt);
7171             is32|=sr<<rt;
7172           }
7173           else {
7174             is32&=~(1LL<<rt);
7175           }
7176         }
7177         break;
7178       case MULTDIV:
7179         if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
7180           is32&=~((1LL<<HIREG)|(1LL<<LOREG));
7181         }
7182         else {
7183           is32|=(1LL<<HIREG)|(1LL<<LOREG);
7184         }
7185         break;
7186       case MOV:
7187         {
7188           uint64_t sr=((is32>>s1)&1LL);
7189           is32&=~(1LL<<rt);
7190           is32|=sr<<rt;
7191         }
7192         break;
7193       case SHIFT:
7194         if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
7195         else is32|=1LL<<rt; // SLLV/SRLV/SRAV
7196         break;
7197       case SHIFTIMM:
7198         is32|=1LL<<rt;
7199         // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
7200         if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
7201         break;
7202       case COP0:
7203         if(op2==0) is32|=1LL<<rt; // MFC0
7204         break;
7205       case COP1:
7206       case COP2:
7207         if(op2==0) is32|=1LL<<rt; // MFC1
7208         if(op2==1) is32&=~(1LL<<rt); // DMFC1
7209         if(op2==2) is32|=1LL<<rt; // CFC1
7210         break;
7211       case C1LS:
7212       case C2LS:
7213         break;
7214       case FLOAT:
7215       case FCONV:
7216         break;
7217       case FCOMP:
7218         break;
7219       case C2OP:
7220       case SYSCALL:
7221       case HLECALL:
7222         break;
7223       default:
7224         break;
7225     }
7226     is32|=1;
7227     p32[i]=is32;
7228
7229     if(i>0)
7230     {
7231       if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
7232       {
7233         if(rt1[i-1]==31) // JAL/JALR
7234         {
7235           // Subroutine call will return here, don't alloc any registers
7236           is32=1;
7237         }
7238         else if(i+1<slen)
7239         {
7240           // Internal branch will jump here, match registers to caller
7241           is32=0x3FFFFFFFFLL;
7242         }
7243       }
7244     }
7245   }
7246 }
7247
7248 // Identify registers which may be assumed to contain 32-bit values
7249 // and where optimizations will rely on this.
7250 // This is used to determine whether backward branches can safely
7251 // jump to a location with 64-bit values in registers.
7252 static void provisional_r32()
7253 {
7254   u_int r32=0;
7255   int i;
7256
7257   for (i=slen-1;i>=0;i--)
7258   {
7259     int hr;
7260     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7261     {
7262       if(ba[i]<start || ba[i]>=(start+slen*4))
7263       {
7264         // Branch out of this block, don't need anything
7265         r32=0;
7266       }
7267       else
7268       {
7269         // Internal branch
7270         // Need whatever matches the target
7271         // (and doesn't get overwritten by the delay slot instruction)
7272         r32=0;
7273         int t=(ba[i]-start)>>2;
7274         if(ba[i]>start+i*4) {
7275           // Forward branch
7276           //if(!(requires_32bit[t]&~regs[i].was32))
7277           //  r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7278           if(!(pr32[t]&~regs[i].was32))
7279             r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7280         }else{
7281           // Backward branch
7282           if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
7283             r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7284         }
7285       }
7286       // Conditional branch may need registers for following instructions
7287       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7288       {
7289         if(i<slen-2) {
7290           //r32|=requires_32bit[i+2];
7291           r32|=pr32[i+2];
7292           r32&=regs[i].was32;
7293           // Mark this address as a branch target since it may be called
7294           // upon return from interrupt
7295           //bt[i+2]=1;
7296         }
7297       }
7298       // Merge in delay slot
7299       if(!likely[i]) {
7300         // These are overwritten unless the branch is "likely"
7301         // and the delay slot is nullified if not taken
7302         r32&=~(1LL<<rt1[i+1]);
7303         r32&=~(1LL<<rt2[i+1]);
7304       }
7305       // Assume these are needed (delay slot)
7306       if(us1[i+1]>0)
7307       {
7308         if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7309       }
7310       if(us2[i+1]>0)
7311       {
7312         if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7313       }
7314       if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7315       {
7316         if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7317       }
7318       if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7319       {
7320         if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7321       }
7322     }
7323     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7324     {
7325       // SYSCALL instruction (software interrupt)
7326       r32=0;
7327     }
7328     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7329     {
7330       // ERET instruction (return from interrupt)
7331       r32=0;
7332     }
7333     // Check 32 bits
7334     r32&=~(1LL<<rt1[i]);
7335     r32&=~(1LL<<rt2[i]);
7336     if(us1[i]>0)
7337     {
7338       if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7339     }
7340     if(us2[i]>0)
7341     {
7342       if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7343     }
7344     if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7345     {
7346       if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7347     }
7348     if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7349     {
7350       if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7351     }
7352     //requires_32bit[i]=r32;
7353     pr32[i]=r32;
7354
7355     // Dirty registers which are 32-bit, require 32-bit input
7356     // as they will be written as 32-bit values
7357     for(hr=0;hr<HOST_REGS;hr++)
7358     {
7359       if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
7360         if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7361           if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7362           pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7363           //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7364         }
7365       }
7366     }
7367   }
7368 }
7369
7370 // Write back dirty registers as soon as we will no longer modify them,
7371 // so that we don't end up with lots of writes at the branches.
7372 void clean_registers(int istart,int iend,int wr)
7373 {
7374   int i;
7375   int r;
7376   u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7377   u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7378   if(iend==slen-1) {
7379     will_dirty_i=will_dirty_next=0;
7380     wont_dirty_i=wont_dirty_next=0;
7381   }else{
7382     will_dirty_i=will_dirty_next=will_dirty[iend+1];
7383     wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7384   }
7385   for (i=iend;i>=istart;i--)
7386   {
7387     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7388     {
7389       if(ba[i]<start || ba[i]>=(start+slen*4))
7390       {
7391         // Branch out of this block, flush all regs
7392         if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7393         {
7394           // Unconditional branch
7395           will_dirty_i=0;
7396           wont_dirty_i=0;
7397           // Merge in delay slot (will dirty)
7398           for(r=0;r<HOST_REGS;r++) {
7399             if(r!=EXCLUDE_REG) {
7400               if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7401               if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7402               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7403               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7404               if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7405               if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7406               if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7407               if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7408               if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7409               if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7410               if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7411               if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7412               if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7413               if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7414             }
7415           }
7416         }
7417         else
7418         {
7419           // Conditional branch
7420           will_dirty_i=0;
7421           wont_dirty_i=wont_dirty_next;
7422           // Merge in delay slot (will dirty)
7423           for(r=0;r<HOST_REGS;r++) {
7424             if(r!=EXCLUDE_REG) {
7425               if(!likely[i]) {
7426                 // Might not dirty if likely branch is not taken
7427                 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7428                 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7429                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7430                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7431                 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7432                 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7433                 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7434                 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7435                 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7436                 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7437                 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7438                 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7439                 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7440                 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7441               }
7442             }
7443           }
7444         }
7445         // Merge in delay slot (wont dirty)
7446         for(r=0;r<HOST_REGS;r++) {
7447           if(r!=EXCLUDE_REG) {
7448             if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7449             if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7450             if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7451             if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7452             if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7453             if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7454             if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7455             if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7456             if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7457             if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7458           }
7459         }
7460         if(wr) {
7461           #ifndef DESTRUCTIVE_WRITEBACK
7462           branch_regs[i].dirty&=wont_dirty_i;
7463           #endif
7464           branch_regs[i].dirty|=will_dirty_i;
7465         }
7466       }
7467       else
7468       {
7469         // Internal branch
7470         if(ba[i]<=start+i*4) {
7471           // Backward branch
7472           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7473           {
7474             // Unconditional branch
7475             temp_will_dirty=0;
7476             temp_wont_dirty=0;
7477             // Merge in delay slot (will dirty)
7478             for(r=0;r<HOST_REGS;r++) {
7479               if(r!=EXCLUDE_REG) {
7480                 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7481                 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7482                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7483                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7484                 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7485                 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7486                 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7487                 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7488                 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7489                 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7490                 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7491                 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7492                 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7493                 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7494               }
7495             }
7496           } else {
7497             // Conditional branch (not taken case)
7498             temp_will_dirty=will_dirty_next;
7499             temp_wont_dirty=wont_dirty_next;
7500             // Merge in delay slot (will dirty)
7501             for(r=0;r<HOST_REGS;r++) {
7502               if(r!=EXCLUDE_REG) {
7503                 if(!likely[i]) {
7504                   // Will not dirty if likely branch is not taken
7505                   if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7506                   if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7507                   if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7508                   if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7509                   if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7510                   if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7511                   if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7512                   //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7513                   //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7514                   if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7515                   if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7516                   if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7517                   if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7518                   if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7519                 }
7520               }
7521             }
7522           }
7523           // Merge in delay slot (wont dirty)
7524           for(r=0;r<HOST_REGS;r++) {
7525             if(r!=EXCLUDE_REG) {
7526               if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7527               if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7528               if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7529               if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7530               if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7531               if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7532               if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7533               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7534               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7535               if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7536             }
7537           }
7538           // Deal with changed mappings
7539           if(i<iend) {
7540             for(r=0;r<HOST_REGS;r++) {
7541               if(r!=EXCLUDE_REG) {
7542                 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7543                   temp_will_dirty&=~(1<<r);
7544                   temp_wont_dirty&=~(1<<r);
7545                   if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7546                     temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7547                     temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7548                   } else {
7549                     temp_will_dirty|=1<<r;
7550                     temp_wont_dirty|=1<<r;
7551                   }
7552                 }
7553               }
7554             }
7555           }
7556           if(wr) {
7557             will_dirty[i]=temp_will_dirty;
7558             wont_dirty[i]=temp_wont_dirty;
7559             clean_registers((ba[i]-start)>>2,i-1,0);
7560           }else{
7561             // Limit recursion.  It can take an excessive amount
7562             // of time if there are a lot of nested loops.
7563             will_dirty[(ba[i]-start)>>2]=0;
7564             wont_dirty[(ba[i]-start)>>2]=-1;
7565           }
7566         }
7567         /*else*/ if(1)
7568         {
7569           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7570           {
7571             // Unconditional branch
7572             will_dirty_i=0;
7573             wont_dirty_i=0;
7574           //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7575             for(r=0;r<HOST_REGS;r++) {
7576               if(r!=EXCLUDE_REG) {
7577                 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7578                   will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7579                   wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7580                 }
7581                 if(branch_regs[i].regmap[r]>=0) {
7582                   will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7583                   wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7584                 }
7585               }
7586             }
7587           //}
7588             // Merge in delay slot
7589             for(r=0;r<HOST_REGS;r++) {
7590               if(r!=EXCLUDE_REG) {
7591                 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7592                 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7593                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7594                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7595                 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7596                 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7597                 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7598                 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7599                 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7600                 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7601                 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7602                 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7603                 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7604                 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7605               }
7606             }
7607           } else {
7608             // Conditional branch
7609             will_dirty_i=will_dirty_next;
7610             wont_dirty_i=wont_dirty_next;
7611           //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7612             for(r=0;r<HOST_REGS;r++) {
7613               if(r!=EXCLUDE_REG) {
7614                 signed char target_reg=branch_regs[i].regmap[r];
7615                 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7616                   will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7617                   wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7618                 }
7619                 else if(target_reg>=0) {
7620                   will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7621                   wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7622                 }
7623                 // Treat delay slot as part of branch too
7624                 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7625                   will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7626                   wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7627                 }
7628                 else
7629                 {
7630                   will_dirty[i+1]&=~(1<<r);
7631                 }*/
7632               }
7633             }
7634           //}
7635             // Merge in delay slot
7636             for(r=0;r<HOST_REGS;r++) {
7637               if(r!=EXCLUDE_REG) {
7638                 if(!likely[i]) {
7639                   // Might not dirty if likely branch is not taken
7640                   if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7641                   if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7642                   if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7643                   if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7644                   if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7645                   if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7646                   if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7647                   //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7648                   //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7649                   if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7650                   if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7651                   if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7652                   if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7653                   if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7654                 }
7655               }
7656             }
7657           }
7658           // Merge in delay slot (won't dirty)
7659           for(r=0;r<HOST_REGS;r++) {
7660             if(r!=EXCLUDE_REG) {
7661               if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7662               if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7663               if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7664               if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7665               if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7666               if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7667               if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7668               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7669               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7670               if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7671             }
7672           }
7673           if(wr) {
7674             #ifndef DESTRUCTIVE_WRITEBACK
7675             branch_regs[i].dirty&=wont_dirty_i;
7676             #endif
7677             branch_regs[i].dirty|=will_dirty_i;
7678           }
7679         }
7680       }
7681     }
7682     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7683     {
7684       // SYSCALL instruction (software interrupt)
7685       will_dirty_i=0;
7686       wont_dirty_i=0;
7687     }
7688     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7689     {
7690       // ERET instruction (return from interrupt)
7691       will_dirty_i=0;
7692       wont_dirty_i=0;
7693     }
7694     will_dirty_next=will_dirty_i;
7695     wont_dirty_next=wont_dirty_i;
7696     for(r=0;r<HOST_REGS;r++) {
7697       if(r!=EXCLUDE_REG) {
7698         if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7699         if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7700         if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7701         if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7702         if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7703         if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7704         if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7705         if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7706         if(i>istart) {
7707           if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7708           {
7709             // Don't store a register immediately after writing it,
7710             // may prevent dual-issue.
7711             if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7712             if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7713           }
7714         }
7715       }
7716     }
7717     // Save it
7718     will_dirty[i]=will_dirty_i;
7719     wont_dirty[i]=wont_dirty_i;
7720     // Mark registers that won't be dirtied as not dirty
7721     if(wr) {
7722       /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7723       for(r=0;r<HOST_REGS;r++) {
7724         if((will_dirty_i>>r)&1) {
7725           printf(" r%d",r);
7726         }
7727       }
7728       printf("\n");*/
7729
7730       //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7731         regs[i].dirty|=will_dirty_i;
7732         #ifndef DESTRUCTIVE_WRITEBACK
7733         regs[i].dirty&=wont_dirty_i;
7734         if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7735         {
7736           if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7737             for(r=0;r<HOST_REGS;r++) {
7738               if(r!=EXCLUDE_REG) {
7739                 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7740                   regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7741                 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7742               }
7743             }
7744           }
7745         }
7746         else
7747         {
7748           if(i<iend) {
7749             for(r=0;r<HOST_REGS;r++) {
7750               if(r!=EXCLUDE_REG) {
7751                 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7752                   regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7753                 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7754               }
7755             }
7756           }
7757         }
7758         #endif
7759       //}
7760     }
7761     // Deal with changed mappings
7762     temp_will_dirty=will_dirty_i;
7763     temp_wont_dirty=wont_dirty_i;
7764     for(r=0;r<HOST_REGS;r++) {
7765       if(r!=EXCLUDE_REG) {
7766         int nr;
7767         if(regs[i].regmap[r]==regmap_pre[i][r]) {
7768           if(wr) {
7769             #ifndef DESTRUCTIVE_WRITEBACK
7770             regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7771             #endif
7772             regs[i].wasdirty|=will_dirty_i&(1<<r);
7773           }
7774         }
7775         else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7776           // Register moved to a different register
7777           will_dirty_i&=~(1<<r);
7778           wont_dirty_i&=~(1<<r);
7779           will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7780           wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7781           if(wr) {
7782             #ifndef DESTRUCTIVE_WRITEBACK
7783             regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7784             #endif
7785             regs[i].wasdirty|=will_dirty_i&(1<<r);
7786           }
7787         }
7788         else {
7789           will_dirty_i&=~(1<<r);
7790           wont_dirty_i&=~(1<<r);
7791           if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7792             will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7793             wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7794           } else {
7795             wont_dirty_i|=1<<r;
7796             /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7797           }
7798         }
7799       }
7800     }
7801   }
7802 }
7803
7804 #ifdef DISASM
7805   /* disassembly */
7806 void disassemble_inst(int i)
7807 {
7808     if (bt[i]) printf("*"); else printf(" ");
7809     switch(itype[i]) {
7810       case UJUMP:
7811         printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7812       case CJUMP:
7813         printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7814       case SJUMP:
7815         printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7816       case FJUMP:
7817         printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7818       case RJUMP:
7819         if (opcode[i]==0x9&&rt1[i]!=31)
7820           printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7821         else
7822           printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7823         break;
7824       case SPAN:
7825         printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7826       case IMM16:
7827         if(opcode[i]==0xf) //LUI
7828           printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7829         else
7830           printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7831         break;
7832       case LOAD:
7833       case LOADLR:
7834         printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7835         break;
7836       case STORE:
7837       case STORELR:
7838         printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7839         break;
7840       case ALU:
7841       case SHIFT:
7842         printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7843         break;
7844       case MULTDIV:
7845         printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7846         break;
7847       case SHIFTIMM:
7848         printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7849         break;
7850       case MOV:
7851         if((opcode2[i]&0x1d)==0x10)
7852           printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7853         else if((opcode2[i]&0x1d)==0x11)
7854           printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7855         else
7856           printf (" %x: %s\n",start+i*4,insn[i]);
7857         break;
7858       case COP0:
7859         if(opcode2[i]==0)
7860           printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7861         else if(opcode2[i]==4)
7862           printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7863         else printf (" %x: %s\n",start+i*4,insn[i]);
7864         break;
7865       case COP1:
7866         if(opcode2[i]<3)
7867           printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7868         else if(opcode2[i]>3)
7869           printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7870         else printf (" %x: %s\n",start+i*4,insn[i]);
7871         break;
7872       case COP2:
7873         if(opcode2[i]<3)
7874           printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7875         else if(opcode2[i]>3)
7876           printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7877         else printf (" %x: %s\n",start+i*4,insn[i]);
7878         break;
7879       case C1LS:
7880         printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7881         break;
7882       case C2LS:
7883         printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7884         break;
7885       case INTCALL:
7886         printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
7887         break;
7888       default:
7889         //printf (" %s %8x\n",insn[i],source[i]);
7890         printf (" %x: %s\n",start+i*4,insn[i]);
7891     }
7892 }
7893 #else
7894 static void disassemble_inst(int i) {}
7895 #endif // DISASM
7896
7897 // clear the state completely, instead of just marking
7898 // things invalid like invalidate_all_pages() does
7899 void new_dynarec_clear_full()
7900 {
7901   int n;
7902   out=(u_char *)BASE_ADDR;
7903   memset(invalid_code,1,sizeof(invalid_code));
7904   memset(hash_table,0xff,sizeof(hash_table));
7905   memset(mini_ht,-1,sizeof(mini_ht));
7906   memset(restore_candidate,0,sizeof(restore_candidate));
7907   memset(shadow,0,sizeof(shadow));
7908   copy=shadow;
7909   expirep=16384; // Expiry pointer, +2 blocks
7910   pending_exception=0;
7911   literalcount=0;
7912   stop_after_jal=0;
7913   inv_code_start=inv_code_end=~0;
7914   gte_reads_flags=0;
7915   // TLB
7916 #ifndef DISABLE_TLB
7917   using_tlb=0;
7918   for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7919     memory_map[n]=-1;
7920   for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7921     memory_map[n]=((u_int)rdram-0x80000000)>>2;
7922   for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7923     memory_map[n]=-1;
7924 #endif
7925   for(n=0;n<4096;n++) ll_clear(jump_in+n);
7926   for(n=0;n<4096;n++) ll_clear(jump_out+n);
7927   for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7928 }
7929
7930 void new_dynarec_init()
7931 {
7932   printf("Init new dynarec\n");
7933   out=(u_char *)BASE_ADDR;
7934   if (mmap (out, 1<<TARGET_SIZE_2,
7935             PROT_READ | PROT_WRITE | PROT_EXEC,
7936             MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
7937             -1, 0) <= 0) {printf("mmap() failed\n");}
7938 #ifdef MUPEN64
7939   rdword=&readmem_dword;
7940   fake_pc.f.r.rs=&readmem_dword;
7941   fake_pc.f.r.rt=&readmem_dword;
7942   fake_pc.f.r.rd=&readmem_dword;
7943 #endif
7944   int n;
7945   cycle_multiplier=200;
7946   new_dynarec_clear_full();
7947 #ifdef HOST_IMM8
7948   // Copy this into local area so we don't have to put it in every literal pool
7949   invc_ptr=invalid_code;
7950 #endif
7951 #ifdef MUPEN64
7952   for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
7953     writemem[n] = write_nomem_new;
7954     writememb[n] = write_nomemb_new;
7955     writememh[n] = write_nomemh_new;
7956 #ifndef FORCE32
7957     writememd[n] = write_nomemd_new;
7958 #endif
7959     readmem[n] = read_nomem_new;
7960     readmemb[n] = read_nomemb_new;
7961     readmemh[n] = read_nomemh_new;
7962 #ifndef FORCE32
7963     readmemd[n] = read_nomemd_new;
7964 #endif
7965   }
7966   for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
7967     writemem[n] = write_rdram_new;
7968     writememb[n] = write_rdramb_new;
7969     writememh[n] = write_rdramh_new;
7970 #ifndef FORCE32
7971     writememd[n] = write_rdramd_new;
7972 #endif
7973   }
7974   for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
7975     writemem[n] = write_nomem_new;
7976     writememb[n] = write_nomemb_new;
7977     writememh[n] = write_nomemh_new;
7978 #ifndef FORCE32
7979     writememd[n] = write_nomemd_new;
7980 #endif
7981     readmem[n] = read_nomem_new;
7982     readmemb[n] = read_nomemb_new;
7983     readmemh[n] = read_nomemh_new;
7984 #ifndef FORCE32
7985     readmemd[n] = read_nomemd_new;
7986 #endif
7987   }
7988 #endif
7989   tlb_hacks();
7990   arch_init();
7991 }
7992
7993 void new_dynarec_cleanup()
7994 {
7995   int n;
7996   if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
7997   for(n=0;n<4096;n++) ll_clear(jump_in+n);
7998   for(n=0;n<4096;n++) ll_clear(jump_out+n);
7999   for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
8000   #ifdef ROM_COPY
8001   if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
8002   #endif
8003 }
8004
8005 int new_recompile_block(int addr)
8006 {
8007 /*
8008   if(addr==0x800cd050) {
8009     int block;
8010     for(block=0x80000;block<0x80800;block++) invalidate_block(block);
8011     int n;
8012     for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
8013   }
8014 */
8015   //if(Count==365117028) tracedebug=1;
8016   assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
8017   //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
8018   //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
8019   //if(debug)
8020   //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
8021   //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
8022   /*if(Count>=312978186) {
8023     rlist();
8024   }*/
8025   //rlist();
8026   start = (u_int)addr&~3;
8027   //assert(((u_int)addr&1)==0);
8028   new_dynarec_did_compile=1;
8029 #ifdef PCSX
8030   if (Config.HLE && start == 0x80001000) // hlecall
8031   {
8032     // XXX: is this enough? Maybe check hleSoftCall?
8033     u_int beginning=(u_int)out;
8034     u_int page=get_page(start);
8035     invalid_code[start>>12]=0;
8036     emit_movimm(start,0);
8037     emit_writeword(0,(int)&pcaddr);
8038     emit_jmp((int)new_dyna_leave);
8039     literal_pool(0);
8040 #ifdef __arm__
8041     __clear_cache((void *)beginning,out);
8042 #endif
8043     ll_add(jump_in+page,start,(void *)beginning);
8044     return 0;
8045   }
8046   else if ((u_int)addr < 0x00200000 ||
8047     (0xa0000000 <= addr && addr < 0xa0200000)) {
8048     // used for BIOS calls mostly?
8049     source = (u_int *)((u_int)rdram+(start&0x1fffff));
8050     pagelimit = (addr&0xa0000000)|0x00200000;
8051   }
8052   else if (!Config.HLE && (
8053 /*    (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
8054     (0xbfc00000 <= addr && addr < 0xbfc80000))) {
8055     // BIOS
8056     source = (u_int *)((u_int)psxR+(start&0x7ffff));
8057     pagelimit = (addr&0xfff00000)|0x80000;
8058   }
8059   else
8060 #endif
8061 #ifdef MUPEN64
8062   if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
8063     source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
8064     pagelimit = 0xa4001000;
8065   }
8066   else
8067 #endif
8068   if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
8069     source = (u_int *)((u_int)rdram+start-0x80000000);
8070     pagelimit = 0x80000000+RAM_SIZE;
8071   }
8072 #ifndef DISABLE_TLB
8073   else if ((signed int)addr >= (signed int)0xC0000000) {
8074     //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
8075     //if(tlb_LUT_r[start>>12])
8076       //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
8077     if((signed int)memory_map[start>>12]>=0) {
8078       source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
8079       pagelimit=(start+4096)&0xFFFFF000;
8080       int map=memory_map[start>>12];
8081       int i;
8082       for(i=0;i<5;i++) {
8083         //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
8084         if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
8085       }
8086       assem_debug("pagelimit=%x\n",pagelimit);
8087       assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
8088     }
8089     else {
8090       assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
8091       //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
8092       return -1; // Caller will invoke exception handler
8093     }
8094     //printf("source= %x\n",(int)source);
8095   }
8096 #endif
8097   else {
8098     printf("Compile at bogus memory address: %x \n", (int)addr);
8099     exit(1);
8100   }
8101
8102   /* Pass 1: disassemble */
8103   /* Pass 2: register dependencies, branch targets */
8104   /* Pass 3: register allocation */
8105   /* Pass 4: branch dependencies */
8106   /* Pass 5: pre-alloc */
8107   /* Pass 6: optimize clean/dirty state */
8108   /* Pass 7: flag 32-bit registers */
8109   /* Pass 8: assembly */
8110   /* Pass 9: linker */
8111   /* Pass 10: garbage collection / free memory */
8112
8113   int i,j;
8114   int done=0;
8115   unsigned int type,op,op2;
8116
8117   //printf("addr = %x source = %x %x\n", addr,source,source[0]);
8118
8119   /* Pass 1 disassembly */
8120
8121   for(i=0;!done;i++) {
8122     bt[i]=0;likely[i]=0;ooo[i]=0;op2=0;
8123     minimum_free_regs[i]=0;
8124     opcode[i]=op=source[i]>>26;
8125     switch(op)
8126     {
8127       case 0x00: strcpy(insn[i],"special"); type=NI;
8128         op2=source[i]&0x3f;
8129         switch(op2)
8130         {
8131           case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
8132           case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
8133           case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
8134           case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
8135           case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
8136           case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
8137           case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
8138           case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
8139           case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
8140           case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
8141           case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
8142           case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
8143           case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
8144           case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
8145           case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
8146           case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
8147           case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
8148           case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
8149           case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
8150           case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
8151           case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
8152           case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
8153           case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
8154           case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
8155           case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
8156           case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
8157           case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
8158           case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
8159           case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
8160           case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
8161           case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
8162           case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
8163           case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
8164           case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
8165           case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
8166 #ifndef FORCE32
8167           case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
8168           case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
8169           case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
8170           case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
8171           case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
8172           case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
8173           case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
8174           case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
8175           case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
8176           case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
8177           case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
8178           case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
8179           case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
8180           case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
8181           case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
8182           case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
8183           case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
8184 #endif
8185         }
8186         break;
8187       case 0x01: strcpy(insn[i],"regimm"); type=NI;
8188         op2=(source[i]>>16)&0x1f;
8189         switch(op2)
8190         {
8191           case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
8192           case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
8193           case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
8194           case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
8195           case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
8196           case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
8197           case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
8198           case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
8199           case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
8200           case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
8201           case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
8202           case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
8203           case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
8204           case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
8205         }
8206         break;
8207       case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
8208       case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
8209       case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
8210       case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
8211       case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
8212       case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
8213       case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
8214       case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
8215       case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
8216       case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
8217       case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
8218       case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
8219       case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
8220       case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
8221       case 0x10: strcpy(insn[i],"cop0"); type=NI;
8222         op2=(source[i]>>21)&0x1f;
8223         switch(op2)
8224         {
8225           case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
8226           case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
8227           case 0x10: strcpy(insn[i],"tlb"); type=NI;
8228           switch(source[i]&0x3f)
8229           {
8230             case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
8231             case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
8232             case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
8233             case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
8234 #ifdef PCSX
8235             case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
8236 #else
8237             case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
8238 #endif
8239           }
8240         }
8241         break;
8242       case 0x11: strcpy(insn[i],"cop1"); type=NI;
8243         op2=(source[i]>>21)&0x1f;
8244         switch(op2)
8245         {
8246           case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
8247           case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
8248           case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
8249           case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
8250           case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
8251           case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
8252           case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
8253           switch((source[i]>>16)&0x3)
8254           {
8255             case 0x00: strcpy(insn[i],"BC1F"); break;
8256             case 0x01: strcpy(insn[i],"BC1T"); break;
8257             case 0x02: strcpy(insn[i],"BC1FL"); break;
8258             case 0x03: strcpy(insn[i],"BC1TL"); break;
8259           }
8260           break;
8261           case 0x10: strcpy(insn[i],"C1.S"); type=NI;
8262           switch(source[i]&0x3f)
8263           {
8264             case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
8265             case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
8266             case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
8267             case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
8268             case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
8269             case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
8270             case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
8271             case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
8272             case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
8273             case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
8274             case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
8275             case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
8276             case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
8277             case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
8278             case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
8279             case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
8280             case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
8281             case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
8282             case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
8283             case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
8284             case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
8285             case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
8286             case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
8287             case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
8288             case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
8289             case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
8290             case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
8291             case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
8292             case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
8293             case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
8294             case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
8295             case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
8296             case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
8297             case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
8298             case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
8299           }
8300           break;
8301           case 0x11: strcpy(insn[i],"C1.D"); type=NI;
8302           switch(source[i]&0x3f)
8303           {
8304             case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
8305             case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
8306             case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
8307             case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
8308             case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
8309             case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
8310             case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
8311             case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
8312             case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
8313             case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
8314             case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
8315             case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
8316             case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
8317             case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
8318             case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
8319             case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
8320             case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
8321             case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
8322             case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
8323             case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
8324             case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
8325             case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
8326             case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
8327             case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
8328             case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
8329             case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
8330             case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
8331             case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
8332             case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
8333             case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
8334             case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8335             case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8336             case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8337             case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8338             case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8339           }
8340           break;
8341           case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8342           switch(source[i]&0x3f)
8343           {
8344             case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8345             case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8346           }
8347           break;
8348           case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8349           switch(source[i]&0x3f)
8350           {
8351             case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8352             case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8353           }
8354           break;
8355         }
8356         break;
8357 #ifndef FORCE32
8358       case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8359       case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8360       case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8361       case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8362       case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8363       case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8364       case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8365       case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
8366 #endif
8367       case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8368       case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8369       case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8370       case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8371       case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8372       case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8373       case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
8374 #ifndef FORCE32
8375       case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
8376 #endif
8377       case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8378       case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8379       case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8380       case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
8381 #ifndef FORCE32
8382       case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8383       case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
8384 #endif
8385       case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8386       case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8387       case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8388       case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
8389 #ifndef FORCE32
8390       case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8391       case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8392       case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
8393 #endif
8394       case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8395       case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
8396 #ifndef FORCE32
8397       case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8398       case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8399       case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
8400 #endif
8401 #ifdef PCSX
8402       case 0x12: strcpy(insn[i],"COP2"); type=NI;
8403         op2=(source[i]>>21)&0x1f;
8404         //if (op2 & 0x10) {
8405         if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
8406           if (gte_handlers[source[i]&0x3f]!=NULL) {
8407             if (gte_regnames[source[i]&0x3f]!=NULL)
8408               strcpy(insn[i],gte_regnames[source[i]&0x3f]);
8409             else
8410               snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8411             type=C2OP;
8412           }
8413         }
8414         else switch(op2)
8415         {
8416           case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8417           case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8418           case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8419           case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
8420         }
8421         break;
8422       case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8423       case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8424       case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8425 #endif
8426       default: strcpy(insn[i],"???"); type=NI;
8427         printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
8428         break;
8429     }
8430     itype[i]=type;
8431     opcode2[i]=op2;
8432     /* Get registers/immediates */
8433     lt1[i]=0;
8434     us1[i]=0;
8435     us2[i]=0;
8436     dep1[i]=0;
8437     dep2[i]=0;
8438     gte_rs[i]=gte_rt[i]=0;
8439     switch(type) {
8440       case LOAD:
8441         rs1[i]=(source[i]>>21)&0x1f;
8442         rs2[i]=0;
8443         rt1[i]=(source[i]>>16)&0x1f;
8444         rt2[i]=0;
8445         imm[i]=(short)source[i];
8446         break;
8447       case STORE:
8448       case STORELR:
8449         rs1[i]=(source[i]>>21)&0x1f;
8450         rs2[i]=(source[i]>>16)&0x1f;
8451         rt1[i]=0;
8452         rt2[i]=0;
8453         imm[i]=(short)source[i];
8454         if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8455         break;
8456       case LOADLR:
8457         // LWL/LWR only load part of the register,
8458         // therefore the target register must be treated as a source too
8459         rs1[i]=(source[i]>>21)&0x1f;
8460         rs2[i]=(source[i]>>16)&0x1f;
8461         rt1[i]=(source[i]>>16)&0x1f;
8462         rt2[i]=0;
8463         imm[i]=(short)source[i];
8464         if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8465         if(op==0x26) dep1[i]=rt1[i]; // LWR
8466         break;
8467       case IMM16:
8468         if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8469         else rs1[i]=(source[i]>>21)&0x1f;
8470         rs2[i]=0;
8471         rt1[i]=(source[i]>>16)&0x1f;
8472         rt2[i]=0;
8473         if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8474           imm[i]=(unsigned short)source[i];
8475         }else{
8476           imm[i]=(short)source[i];
8477         }
8478         if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8479         if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8480         if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8481         break;
8482       case UJUMP:
8483         rs1[i]=0;
8484         rs2[i]=0;
8485         rt1[i]=0;
8486         rt2[i]=0;
8487         // The JAL instruction writes to r31.
8488         if (op&1) {
8489           rt1[i]=31;
8490         }
8491         rs2[i]=CCREG;
8492         break;
8493       case RJUMP:
8494         rs1[i]=(source[i]>>21)&0x1f;
8495         rs2[i]=0;
8496         rt1[i]=0;
8497         rt2[i]=0;
8498         // The JALR instruction writes to rd.
8499         if (op2&1) {
8500           rt1[i]=(source[i]>>11)&0x1f;
8501         }
8502         rs2[i]=CCREG;
8503         break;
8504       case CJUMP:
8505         rs1[i]=(source[i]>>21)&0x1f;
8506         rs2[i]=(source[i]>>16)&0x1f;
8507         rt1[i]=0;
8508         rt2[i]=0;
8509         if(op&2) { // BGTZ/BLEZ
8510           rs2[i]=0;
8511         }
8512         us1[i]=rs1[i];
8513         us2[i]=rs2[i];
8514         likely[i]=op>>4;
8515         break;
8516       case SJUMP:
8517         rs1[i]=(source[i]>>21)&0x1f;
8518         rs2[i]=CCREG;
8519         rt1[i]=0;
8520         rt2[i]=0;
8521         us1[i]=rs1[i];
8522         if(op2&0x10) { // BxxAL
8523           rt1[i]=31;
8524           // NOTE: If the branch is not taken, r31 is still overwritten
8525         }
8526         likely[i]=(op2&2)>>1;
8527         break;
8528       case FJUMP:
8529         rs1[i]=FSREG;
8530         rs2[i]=CSREG;
8531         rt1[i]=0;
8532         rt2[i]=0;
8533         likely[i]=((source[i])>>17)&1;
8534         break;
8535       case ALU:
8536         rs1[i]=(source[i]>>21)&0x1f; // source
8537         rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8538         rt1[i]=(source[i]>>11)&0x1f; // destination
8539         rt2[i]=0;
8540         if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8541           us1[i]=rs1[i];us2[i]=rs2[i];
8542         }
8543         else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8544           dep1[i]=rs1[i];dep2[i]=rs2[i];
8545         }
8546         else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8547           dep1[i]=rs1[i];dep2[i]=rs2[i];
8548         }
8549         break;
8550       case MULTDIV:
8551         rs1[i]=(source[i]>>21)&0x1f; // source
8552         rs2[i]=(source[i]>>16)&0x1f; // divisor
8553         rt1[i]=HIREG;
8554         rt2[i]=LOREG;
8555         if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8556           us1[i]=rs1[i];us2[i]=rs2[i];
8557         }
8558         break;
8559       case MOV:
8560         rs1[i]=0;
8561         rs2[i]=0;
8562         rt1[i]=0;
8563         rt2[i]=0;
8564         if(op2==0x10) rs1[i]=HIREG; // MFHI
8565         if(op2==0x11) rt1[i]=HIREG; // MTHI
8566         if(op2==0x12) rs1[i]=LOREG; // MFLO
8567         if(op2==0x13) rt1[i]=LOREG; // MTLO
8568         if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8569         if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8570         dep1[i]=rs1[i];
8571         break;
8572       case SHIFT:
8573         rs1[i]=(source[i]>>16)&0x1f; // target of shift
8574         rs2[i]=(source[i]>>21)&0x1f; // shift amount
8575         rt1[i]=(source[i]>>11)&0x1f; // destination
8576         rt2[i]=0;
8577         // DSLLV/DSRLV/DSRAV are 64-bit
8578         if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8579         break;
8580       case SHIFTIMM:
8581         rs1[i]=(source[i]>>16)&0x1f;
8582         rs2[i]=0;
8583         rt1[i]=(source[i]>>11)&0x1f;
8584         rt2[i]=0;
8585         imm[i]=(source[i]>>6)&0x1f;
8586         // DSxx32 instructions
8587         if(op2>=0x3c) imm[i]|=0x20;
8588         // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8589         if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8590         break;
8591       case COP0:
8592         rs1[i]=0;
8593         rs2[i]=0;
8594         rt1[i]=0;
8595         rt2[i]=0;
8596         if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8597         if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8598         if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8599         if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8600         break;
8601       case COP1:
8602         rs1[i]=0;
8603         rs2[i]=0;
8604         rt1[i]=0;
8605         rt2[i]=0;
8606         if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8607         if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8608         if(op2==5) us1[i]=rs1[i]; // DMTC1
8609         rs2[i]=CSREG;
8610         break;
8611       case COP2:
8612         rs1[i]=0;
8613         rs2[i]=0;
8614         rt1[i]=0;
8615         rt2[i]=0;
8616         if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC2/CFC2
8617         if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC2/CTC2
8618         rs2[i]=CSREG;
8619         int gr=(source[i]>>11)&0x1F;
8620         switch(op2)
8621         {
8622           case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
8623           case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
8624           case 0x02: gte_rs[i]=1ll<<(gr+32); // CFC2
8625             if(gr==31&&!gte_reads_flags) {
8626               assem_debug("gte flag read encountered @%08x\n",addr + i*4);
8627               gte_reads_flags=1;
8628             }
8629             break;
8630           case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
8631         }
8632         break;
8633       case C1LS:
8634         rs1[i]=(source[i]>>21)&0x1F;
8635         rs2[i]=CSREG;
8636         rt1[i]=0;
8637         rt2[i]=0;
8638         imm[i]=(short)source[i];
8639         break;
8640       case C2LS:
8641         rs1[i]=(source[i]>>21)&0x1F;
8642         rs2[i]=0;
8643         rt1[i]=0;
8644         rt2[i]=0;
8645         imm[i]=(short)source[i];
8646         if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
8647         else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
8648         break;
8649       case C2OP:
8650         rs1[i]=0;
8651         rs2[i]=0;
8652         rt1[i]=0;
8653         rt2[i]=0;
8654         gte_rt[i]=1ll<<63; // every op changes flags
8655         // TODO: other regs?
8656         break;
8657       case FLOAT:
8658       case FCONV:
8659         rs1[i]=0;
8660         rs2[i]=CSREG;
8661         rt1[i]=0;
8662         rt2[i]=0;
8663         break;
8664       case FCOMP:
8665         rs1[i]=FSREG;
8666         rs2[i]=CSREG;
8667         rt1[i]=FSREG;
8668         rt2[i]=0;
8669         break;
8670       case SYSCALL:
8671       case HLECALL:
8672       case INTCALL:
8673         rs1[i]=CCREG;
8674         rs2[i]=0;
8675         rt1[i]=0;
8676         rt2[i]=0;
8677         break;
8678       default:
8679         rs1[i]=0;
8680         rs2[i]=0;
8681         rt1[i]=0;
8682         rt2[i]=0;
8683     }
8684     /* Calculate branch target addresses */
8685     if(type==UJUMP)
8686       ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8687     else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8688       ba[i]=start+i*4+8; // Ignore never taken branch
8689     else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8690       ba[i]=start+i*4+8; // Ignore never taken branch
8691     else if(type==CJUMP||type==SJUMP||type==FJUMP)
8692       ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8693     else ba[i]=-1;
8694 #ifdef PCSX
8695     if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
8696       int do_in_intrp=0;
8697       // branch in delay slot?
8698       if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
8699         // don't handle first branch and call interpreter if it's hit
8700         printf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
8701         do_in_intrp=1;
8702       }
8703       // basic load delay detection
8704       else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&rt1[i]!=0) {
8705         int t=(ba[i-1]-start)/4;
8706         if(0 <= t && t < i &&(rt1[i]==rs1[t]||rt1[i]==rs2[t])&&itype[t]!=CJUMP&&itype[t]!=SJUMP) {
8707           // jump target wants DS result - potential load delay effect
8708           printf("load delay @%08x (%08x)\n", addr + i*4, addr);
8709           do_in_intrp=1;
8710           bt[t+1]=1; // expected return from interpreter
8711         }
8712         else if(i>=2&&rt1[i-2]==2&&rt1[i]==2&&rs1[i]!=2&&rs2[i]!=2&&rs1[i-1]!=2&&rs2[i-1]!=2&&
8713               !(i>=3&&(itype[i-3]==RJUMP||itype[i-3]==UJUMP||itype[i-3]==CJUMP||itype[i-3]==SJUMP))) {
8714           // v0 overwrite like this is a sign of trouble, bail out
8715           printf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
8716           do_in_intrp=1;
8717         }
8718       }
8719       if(do_in_intrp) {
8720         rs1[i-1]=CCREG;
8721         rs2[i-1]=rt1[i-1]=rt2[i-1]=0;
8722         ba[i-1]=-1;
8723         itype[i-1]=INTCALL;
8724         done=2;
8725         i--; // don't compile the DS
8726       }
8727     }
8728 #endif
8729     /* Is this the end of the block? */
8730     if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
8731       if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
8732         done=2;
8733       }
8734       else {
8735         if(stop_after_jal) done=1;
8736         // Stop on BREAK
8737         if((source[i+1]&0xfc00003f)==0x0d) done=1;
8738       }
8739       // Don't recompile stuff that's already compiled
8740       if(check_addr(start+i*4+4)) done=1;
8741       // Don't get too close to the limit
8742       if(i>MAXBLOCK/2) done=1;
8743     }
8744     if(itype[i]==SYSCALL&&stop_after_jal) done=1;
8745     if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
8746     if(done==2) {
8747       // Does the block continue due to a branch?
8748       for(j=i-1;j>=0;j--)
8749       {
8750         if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
8751         if(ba[j]==start+i*4+4) done=j=0;
8752         if(ba[j]==start+i*4+8) done=j=0;
8753       }
8754     }
8755     //assert(i<MAXBLOCK-1);
8756     if(start+i*4==pagelimit-4) done=1;
8757     assert(start+i*4<pagelimit);
8758     if (i==MAXBLOCK-1) done=1;
8759     // Stop if we're compiling junk
8760     if(itype[i]==NI&&opcode[i]==0x11) {
8761       done=stop_after_jal=1;
8762       printf("Disabled speculative precompilation\n");
8763     }
8764   }
8765   slen=i;
8766   if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8767     if(start+i*4==pagelimit) {
8768       itype[i-1]=SPAN;
8769     }
8770   }
8771   assert(slen>0);
8772
8773   /* Pass 2 - Register dependencies and branch targets */
8774
8775   unneeded_registers(0,slen-1,0);
8776
8777   /* Pass 3 - Register allocation */
8778
8779   struct regstat current; // Current register allocations/status
8780   current.is32=1;
8781   current.dirty=0;
8782   current.u=unneeded_reg[0];
8783   current.uu=unneeded_reg_upper[0];
8784   clear_all_regs(current.regmap);
8785   alloc_reg(&current,0,CCREG);
8786   dirty_reg(&current,CCREG);
8787   current.isconst=0;
8788   current.wasconst=0;
8789   int ds=0;
8790   int cc=0;
8791   int hr=-1;
8792
8793 #ifndef FORCE32
8794   provisional_32bit();
8795 #endif
8796   if((u_int)addr&1) {
8797     // First instruction is delay slot
8798     cc=-1;
8799     bt[1]=1;
8800     ds=1;
8801     unneeded_reg[0]=1;
8802     unneeded_reg_upper[0]=1;
8803     current.regmap[HOST_BTREG]=BTREG;
8804   }
8805
8806   for(i=0;i<slen;i++)
8807   {
8808     if(bt[i])
8809     {
8810       int hr;
8811       for(hr=0;hr<HOST_REGS;hr++)
8812       {
8813         // Is this really necessary?
8814         if(current.regmap[hr]==0) current.regmap[hr]=-1;
8815       }
8816       current.isconst=0;
8817     }
8818     if(i>1)
8819     {
8820       if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8821       {
8822         if(rs1[i-2]==0||rs2[i-2]==0)
8823         {
8824           if(rs1[i-2]) {
8825             current.is32|=1LL<<rs1[i-2];
8826             int hr=get_reg(current.regmap,rs1[i-2]|64);
8827             if(hr>=0) current.regmap[hr]=-1;
8828           }
8829           if(rs2[i-2]) {
8830             current.is32|=1LL<<rs2[i-2];
8831             int hr=get_reg(current.regmap,rs2[i-2]|64);
8832             if(hr>=0) current.regmap[hr]=-1;
8833           }
8834         }
8835       }
8836     }
8837 #ifndef FORCE32
8838     // If something jumps here with 64-bit values
8839     // then promote those registers to 64 bits
8840     if(bt[i])
8841     {
8842       uint64_t temp_is32=current.is32;
8843       for(j=i-1;j>=0;j--)
8844       {
8845         if(ba[j]==start+i*4)
8846           temp_is32&=branch_regs[j].is32;
8847       }
8848       for(j=i;j<slen;j++)
8849       {
8850         if(ba[j]==start+i*4)
8851           //temp_is32=1;
8852           temp_is32&=p32[j];
8853       }
8854       if(temp_is32!=current.is32) {
8855         //printf("dumping 32-bit regs (%x)\n",start+i*4);
8856         #ifndef DESTRUCTIVE_WRITEBACK
8857         if(ds)
8858         #endif
8859         for(hr=0;hr<HOST_REGS;hr++)
8860         {
8861           int r=current.regmap[hr];
8862           if(r>0&&r<64)
8863           {
8864             if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8865               temp_is32|=1LL<<r;
8866               //printf("restore %d\n",r);
8867             }
8868           }
8869         }
8870         current.is32=temp_is32;
8871       }
8872     }
8873 #else
8874     current.is32=-1LL;
8875 #endif
8876
8877     memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8878     regs[i].wasconst=current.isconst;
8879     regs[i].was32=current.is32;
8880     regs[i].wasdirty=current.dirty;
8881     #if defined(DESTRUCTIVE_WRITEBACK) && !defined(FORCE32)
8882     // To change a dirty register from 32 to 64 bits, we must write
8883     // it out during the previous cycle (for branches, 2 cycles)
8884     if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8885     {
8886       uint64_t temp_is32=current.is32;
8887       for(j=i-1;j>=0;j--)
8888       {
8889         if(ba[j]==start+i*4+4)
8890           temp_is32&=branch_regs[j].is32;
8891       }
8892       for(j=i;j<slen;j++)
8893       {
8894         if(ba[j]==start+i*4+4)
8895           //temp_is32=1;
8896           temp_is32&=p32[j];
8897       }
8898       if(temp_is32!=current.is32) {
8899         //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8900         for(hr=0;hr<HOST_REGS;hr++)
8901         {
8902           int r=current.regmap[hr];
8903           if(r>0)
8904           {
8905             if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8906               if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
8907               {
8908                 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
8909                 {
8910                   //printf("dump %d/r%d\n",hr,r);
8911                   current.regmap[hr]=-1;
8912                   if(get_reg(current.regmap,r|64)>=0)
8913                     current.regmap[get_reg(current.regmap,r|64)]=-1;
8914                 }
8915               }
8916             }
8917           }
8918         }
8919       }
8920     }
8921     else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
8922     {
8923       uint64_t temp_is32=current.is32;
8924       for(j=i-1;j>=0;j--)
8925       {
8926         if(ba[j]==start+i*4+8)
8927           temp_is32&=branch_regs[j].is32;
8928       }
8929       for(j=i;j<slen;j++)
8930       {
8931         if(ba[j]==start+i*4+8)
8932           //temp_is32=1;
8933           temp_is32&=p32[j];
8934       }
8935       if(temp_is32!=current.is32) {
8936         //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8937         for(hr=0;hr<HOST_REGS;hr++)
8938         {
8939           int r=current.regmap[hr];
8940           if(r>0)
8941           {
8942             if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8943               if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
8944               {
8945                 //printf("dump %d/r%d\n",hr,r);
8946                 current.regmap[hr]=-1;
8947                 if(get_reg(current.regmap,r|64)>=0)
8948                   current.regmap[get_reg(current.regmap,r|64)]=-1;
8949               }
8950             }
8951           }
8952         }
8953       }
8954     }
8955     #endif
8956     if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8957       if(i+1<slen) {
8958         current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8959         current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8960         if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8961         current.u|=1;
8962         current.uu|=1;
8963       } else {
8964         current.u=1;
8965         current.uu=1;
8966       }
8967     } else {
8968       if(i+1<slen) {
8969         current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
8970         current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8971         if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8972         current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8973         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8974         current.u|=1;
8975         current.uu|=1;
8976       } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
8977     }
8978     is_ds[i]=ds;
8979     if(ds) {
8980       ds=0; // Skip delay slot, already allocated as part of branch
8981       // ...but we need to alloc it in case something jumps here
8982       if(i+1<slen) {
8983         current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
8984         current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
8985       }else{
8986         current.u=branch_unneeded_reg[i-1];
8987         current.uu=branch_unneeded_reg_upper[i-1];
8988       }
8989       current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8990       current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8991       if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8992       current.u|=1;
8993       current.uu|=1;
8994       struct regstat temp;
8995       memcpy(&temp,&current,sizeof(current));
8996       temp.wasdirty=temp.dirty;
8997       temp.was32=temp.is32;
8998       // TODO: Take into account unconditional branches, as below
8999       delayslot_alloc(&temp,i);
9000       memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
9001       regs[i].wasdirty=temp.wasdirty;
9002       regs[i].was32=temp.was32;
9003       regs[i].dirty=temp.dirty;
9004       regs[i].is32=temp.is32;
9005       regs[i].isconst=0;
9006       regs[i].wasconst=0;
9007       current.isconst=0;
9008       // Create entry (branch target) regmap
9009       for(hr=0;hr<HOST_REGS;hr++)
9010       {
9011         int r=temp.regmap[hr];
9012         if(r>=0) {
9013           if(r!=regmap_pre[i][hr]) {
9014             regs[i].regmap_entry[hr]=-1;
9015           }
9016           else
9017           {
9018             if(r<64){
9019               if((current.u>>r)&1) {
9020                 regs[i].regmap_entry[hr]=-1;
9021                 regs[i].regmap[hr]=-1;
9022                 //Don't clear regs in the delay slot as the branch might need them
9023                 //current.regmap[hr]=-1;
9024               }else
9025                 regs[i].regmap_entry[hr]=r;
9026             }
9027             else {
9028               if((current.uu>>(r&63))&1) {
9029                 regs[i].regmap_entry[hr]=-1;
9030                 regs[i].regmap[hr]=-1;
9031                 //Don't clear regs in the delay slot as the branch might need them
9032                 //current.regmap[hr]=-1;
9033               }else
9034                 regs[i].regmap_entry[hr]=r;
9035             }
9036           }
9037         } else {
9038           // First instruction expects CCREG to be allocated
9039           if(i==0&&hr==HOST_CCREG)
9040             regs[i].regmap_entry[hr]=CCREG;
9041           else
9042             regs[i].regmap_entry[hr]=-1;
9043         }
9044       }
9045     }
9046     else { // Not delay slot
9047       switch(itype[i]) {
9048         case UJUMP:
9049           //current.isconst=0; // DEBUG
9050           //current.wasconst=0; // DEBUG
9051           //regs[i].wasconst=0; // DEBUG
9052           clear_const(&current,rt1[i]);
9053           alloc_cc(&current,i);
9054           dirty_reg(&current,CCREG);
9055           if (rt1[i]==31) {
9056             alloc_reg(&current,i,31);
9057             dirty_reg(&current,31);
9058             //assert(rs1[i+1]!=31&&rs2[i+1]!=31);
9059             //assert(rt1[i+1]!=rt1[i]);
9060             #ifdef REG_PREFETCH
9061             alloc_reg(&current,i,PTEMP);
9062             #endif
9063             //current.is32|=1LL<<rt1[i];
9064           }
9065           ooo[i]=1;
9066           delayslot_alloc(&current,i+1);
9067           //current.isconst=0; // DEBUG
9068           ds=1;
9069           //printf("i=%d, isconst=%x\n",i,current.isconst);
9070           break;
9071         case RJUMP:
9072           //current.isconst=0;
9073           //current.wasconst=0;
9074           //regs[i].wasconst=0;
9075           clear_const(&current,rs1[i]);
9076           clear_const(&current,rt1[i]);
9077           alloc_cc(&current,i);
9078           dirty_reg(&current,CCREG);
9079           if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
9080             alloc_reg(&current,i,rs1[i]);
9081             if (rt1[i]!=0) {
9082               alloc_reg(&current,i,rt1[i]);
9083               dirty_reg(&current,rt1[i]);
9084               assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
9085               assert(rt1[i+1]!=rt1[i]);
9086               #ifdef REG_PREFETCH
9087               alloc_reg(&current,i,PTEMP);
9088               #endif
9089             }
9090             #ifdef USE_MINI_HT
9091             if(rs1[i]==31) { // JALR
9092               alloc_reg(&current,i,RHASH);
9093               #ifndef HOST_IMM_ADDR32
9094               alloc_reg(&current,i,RHTBL);
9095               #endif
9096             }
9097             #endif
9098             delayslot_alloc(&current,i+1);
9099           } else {
9100             // The delay slot overwrites our source register,
9101             // allocate a temporary register to hold the old value.
9102             current.isconst=0;
9103             current.wasconst=0;
9104             regs[i].wasconst=0;
9105             delayslot_alloc(&current,i+1);
9106             current.isconst=0;
9107             alloc_reg(&current,i,RTEMP);
9108           }
9109           //current.isconst=0; // DEBUG
9110           ooo[i]=1;
9111           ds=1;
9112           break;
9113         case CJUMP:
9114           //current.isconst=0;
9115           //current.wasconst=0;
9116           //regs[i].wasconst=0;
9117           clear_const(&current,rs1[i]);
9118           clear_const(&current,rs2[i]);
9119           if((opcode[i]&0x3E)==4) // BEQ/BNE
9120           {
9121             alloc_cc(&current,i);
9122             dirty_reg(&current,CCREG);
9123             if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9124             if(rs2[i]) alloc_reg(&current,i,rs2[i]);
9125             if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9126             {
9127               if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9128               if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
9129             }
9130             if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
9131                (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
9132               // The delay slot overwrites one of our conditions.
9133               // Allocate the branch condition registers instead.
9134               current.isconst=0;
9135               current.wasconst=0;
9136               regs[i].wasconst=0;
9137               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9138               if(rs2[i]) alloc_reg(&current,i,rs2[i]);
9139               if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9140               {
9141                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9142                 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
9143               }
9144             }
9145             else
9146             {
9147               ooo[i]=1;
9148               delayslot_alloc(&current,i+1);
9149             }
9150           }
9151           else
9152           if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
9153           {
9154             alloc_cc(&current,i);
9155             dirty_reg(&current,CCREG);
9156             alloc_reg(&current,i,rs1[i]);
9157             if(!(current.is32>>rs1[i]&1))
9158             {
9159               alloc_reg64(&current,i,rs1[i]);
9160             }
9161             if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
9162               // The delay slot overwrites one of our conditions.
9163               // Allocate the branch condition registers instead.
9164               current.isconst=0;
9165               current.wasconst=0;
9166               regs[i].wasconst=0;
9167               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9168               if(!((current.is32>>rs1[i])&1))
9169               {
9170                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9171               }
9172             }
9173             else
9174             {
9175               ooo[i]=1;
9176               delayslot_alloc(&current,i+1);
9177             }
9178           }
9179           else
9180           // Don't alloc the delay slot yet because we might not execute it
9181           if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
9182           {
9183             current.isconst=0;
9184             current.wasconst=0;
9185             regs[i].wasconst=0;
9186             alloc_cc(&current,i);
9187             dirty_reg(&current,CCREG);
9188             alloc_reg(&current,i,rs1[i]);
9189             alloc_reg(&current,i,rs2[i]);
9190             if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9191             {
9192               alloc_reg64(&current,i,rs1[i]);
9193               alloc_reg64(&current,i,rs2[i]);
9194             }
9195           }
9196           else
9197           if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
9198           {
9199             current.isconst=0;
9200             current.wasconst=0;
9201             regs[i].wasconst=0;
9202             alloc_cc(&current,i);
9203             dirty_reg(&current,CCREG);
9204             alloc_reg(&current,i,rs1[i]);
9205             if(!(current.is32>>rs1[i]&1))
9206             {
9207               alloc_reg64(&current,i,rs1[i]);
9208             }
9209           }
9210           ds=1;
9211           //current.isconst=0;
9212           break;
9213         case SJUMP:
9214           //current.isconst=0;
9215           //current.wasconst=0;
9216           //regs[i].wasconst=0;
9217           clear_const(&current,rs1[i]);
9218           clear_const(&current,rt1[i]);
9219           //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
9220           if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
9221           {
9222             alloc_cc(&current,i);
9223             dirty_reg(&current,CCREG);
9224             alloc_reg(&current,i,rs1[i]);
9225             if(!(current.is32>>rs1[i]&1))
9226             {
9227               alloc_reg64(&current,i,rs1[i]);
9228             }
9229             if (rt1[i]==31) { // BLTZAL/BGEZAL
9230               alloc_reg(&current,i,31);
9231               dirty_reg(&current,31);
9232               //#ifdef REG_PREFETCH
9233               //alloc_reg(&current,i,PTEMP);
9234               //#endif
9235               //current.is32|=1LL<<rt1[i];
9236             }
9237             if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) // The delay slot overwrites the branch condition.
9238                ||(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))) { // DS touches $ra
9239               // Allocate the branch condition registers instead.
9240               current.isconst=0;
9241               current.wasconst=0;
9242               regs[i].wasconst=0;
9243               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9244               if(!((current.is32>>rs1[i])&1))
9245               {
9246                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9247               }
9248             }
9249             else
9250             {
9251               ooo[i]=1;
9252               delayslot_alloc(&current,i+1);
9253             }
9254           }
9255           else
9256           // Don't alloc the delay slot yet because we might not execute it
9257           if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
9258           {
9259             current.isconst=0;
9260             current.wasconst=0;
9261             regs[i].wasconst=0;
9262             alloc_cc(&current,i);
9263             dirty_reg(&current,CCREG);
9264             alloc_reg(&current,i,rs1[i]);
9265             if(!(current.is32>>rs1[i]&1))
9266             {
9267               alloc_reg64(&current,i,rs1[i]);
9268             }
9269           }
9270           ds=1;
9271           //current.isconst=0;
9272           break;
9273         case FJUMP:
9274           current.isconst=0;
9275           current.wasconst=0;
9276           regs[i].wasconst=0;
9277           if(likely[i]==0) // BC1F/BC1T
9278           {
9279             // TODO: Theoretically we can run out of registers here on x86.
9280             // The delay slot can allocate up to six, and we need to check
9281             // CSREG before executing the delay slot.  Possibly we can drop
9282             // the cycle count and then reload it after checking that the
9283             // FPU is in a usable state, or don't do out-of-order execution.
9284             alloc_cc(&current,i);
9285             dirty_reg(&current,CCREG);
9286             alloc_reg(&current,i,FSREG);
9287             alloc_reg(&current,i,CSREG);
9288             if(itype[i+1]==FCOMP) {
9289               // The delay slot overwrites the branch condition.
9290               // Allocate the branch condition registers instead.
9291               alloc_cc(&current,i);
9292               dirty_reg(&current,CCREG);
9293               alloc_reg(&current,i,CSREG);
9294               alloc_reg(&current,i,FSREG);
9295             }
9296             else {
9297               ooo[i]=1;
9298               delayslot_alloc(&current,i+1);
9299               alloc_reg(&current,i+1,CSREG);
9300             }
9301           }
9302           else
9303           // Don't alloc the delay slot yet because we might not execute it
9304           if(likely[i]) // BC1FL/BC1TL
9305           {
9306             alloc_cc(&current,i);
9307             dirty_reg(&current,CCREG);
9308             alloc_reg(&current,i,CSREG);
9309             alloc_reg(&current,i,FSREG);
9310           }
9311           ds=1;
9312           current.isconst=0;
9313           break;
9314         case IMM16:
9315           imm16_alloc(&current,i);
9316           break;
9317         case LOAD:
9318         case LOADLR:
9319           load_alloc(&current,i);
9320           break;
9321         case STORE:
9322         case STORELR:
9323           store_alloc(&current,i);
9324           break;
9325         case ALU:
9326           alu_alloc(&current,i);
9327           break;
9328         case SHIFT:
9329           shift_alloc(&current,i);
9330           break;
9331         case MULTDIV:
9332           multdiv_alloc(&current,i);
9333           break;
9334         case SHIFTIMM:
9335           shiftimm_alloc(&current,i);
9336           break;
9337         case MOV:
9338           mov_alloc(&current,i);
9339           break;
9340         case COP0:
9341           cop0_alloc(&current,i);
9342           break;
9343         case COP1:
9344         case COP2:
9345           cop1_alloc(&current,i);
9346           break;
9347         case C1LS:
9348           c1ls_alloc(&current,i);
9349           break;
9350         case C2LS:
9351           c2ls_alloc(&current,i);
9352           break;
9353         case C2OP:
9354           c2op_alloc(&current,i);
9355           break;
9356         case FCONV:
9357           fconv_alloc(&current,i);
9358           break;
9359         case FLOAT:
9360           float_alloc(&current,i);
9361           break;
9362         case FCOMP:
9363           fcomp_alloc(&current,i);
9364           break;
9365         case SYSCALL:
9366         case HLECALL:
9367         case INTCALL:
9368           syscall_alloc(&current,i);
9369           break;
9370         case SPAN:
9371           pagespan_alloc(&current,i);
9372           break;
9373       }
9374
9375       // Drop the upper half of registers that have become 32-bit
9376       current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
9377       if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9378         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9379         if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9380         current.uu|=1;
9381       } else {
9382         current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
9383         current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9384         if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9385         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9386         current.uu|=1;
9387       }
9388
9389       // Create entry (branch target) regmap
9390       for(hr=0;hr<HOST_REGS;hr++)
9391       {
9392         int r,or,er;
9393         r=current.regmap[hr];
9394         if(r>=0) {
9395           if(r!=regmap_pre[i][hr]) {
9396             // TODO: delay slot (?)
9397             or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9398             if(or<0||(r&63)>=TEMPREG){
9399               regs[i].regmap_entry[hr]=-1;
9400             }
9401             else
9402             {
9403               // Just move it to a different register
9404               regs[i].regmap_entry[hr]=r;
9405               // If it was dirty before, it's still dirty
9406               if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r&63);
9407             }
9408           }
9409           else
9410           {
9411             // Unneeded
9412             if(r==0){
9413               regs[i].regmap_entry[hr]=0;
9414             }
9415             else
9416             if(r<64){
9417               if((current.u>>r)&1) {
9418                 regs[i].regmap_entry[hr]=-1;
9419                 //regs[i].regmap[hr]=-1;
9420                 current.regmap[hr]=-1;
9421               }else
9422                 regs[i].regmap_entry[hr]=r;
9423             }
9424             else {
9425               if((current.uu>>(r&63))&1) {
9426                 regs[i].regmap_entry[hr]=-1;
9427                 //regs[i].regmap[hr]=-1;
9428                 current.regmap[hr]=-1;
9429               }else
9430                 regs[i].regmap_entry[hr]=r;
9431             }
9432           }
9433         } else {
9434           // Branches expect CCREG to be allocated at the target
9435           if(regmap_pre[i][hr]==CCREG)
9436             regs[i].regmap_entry[hr]=CCREG;
9437           else
9438             regs[i].regmap_entry[hr]=-1;
9439         }
9440       }
9441       memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9442     }
9443     /* Branch post-alloc */
9444     if(i>0)
9445     {
9446       current.was32=current.is32;
9447       current.wasdirty=current.dirty;
9448       switch(itype[i-1]) {
9449         case UJUMP:
9450           memcpy(&branch_regs[i-1],&current,sizeof(current));
9451           branch_regs[i-1].isconst=0;
9452           branch_regs[i-1].wasconst=0;
9453           branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9454           branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9455           alloc_cc(&branch_regs[i-1],i-1);
9456           dirty_reg(&branch_regs[i-1],CCREG);
9457           if(rt1[i-1]==31) { // JAL
9458             alloc_reg(&branch_regs[i-1],i-1,31);
9459             dirty_reg(&branch_regs[i-1],31);
9460             branch_regs[i-1].is32|=1LL<<31;
9461           }
9462           memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9463           memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9464           break;
9465         case RJUMP:
9466           memcpy(&branch_regs[i-1],&current,sizeof(current));
9467           branch_regs[i-1].isconst=0;
9468           branch_regs[i-1].wasconst=0;
9469           branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9470           branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9471           alloc_cc(&branch_regs[i-1],i-1);
9472           dirty_reg(&branch_regs[i-1],CCREG);
9473           alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
9474           if(rt1[i-1]!=0) { // JALR
9475             alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9476             dirty_reg(&branch_regs[i-1],rt1[i-1]);
9477             branch_regs[i-1].is32|=1LL<<rt1[i-1];
9478           }
9479           #ifdef USE_MINI_HT
9480           if(rs1[i-1]==31) { // JALR
9481             alloc_reg(&branch_regs[i-1],i-1,RHASH);
9482             #ifndef HOST_IMM_ADDR32
9483             alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9484             #endif
9485           }
9486           #endif
9487           memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9488           memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9489           break;
9490         case CJUMP:
9491           if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9492           {
9493             alloc_cc(&current,i-1);
9494             dirty_reg(&current,CCREG);
9495             if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9496                (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9497               // The delay slot overwrote one of our conditions
9498               // Delay slot goes after the test (in order)
9499               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9500               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9501               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9502               current.u|=1;
9503               current.uu|=1;
9504               delayslot_alloc(&current,i);
9505               current.isconst=0;
9506             }
9507             else
9508             {
9509               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9510               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9511               // Alloc the branch condition registers
9512               if(rs1[i-1]) alloc_reg(&current,i-1,rs1[i-1]);
9513               if(rs2[i-1]) alloc_reg(&current,i-1,rs2[i-1]);
9514               if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9515               {
9516                 if(rs1[i-1]) alloc_reg64(&current,i-1,rs1[i-1]);
9517                 if(rs2[i-1]) alloc_reg64(&current,i-1,rs2[i-1]);
9518               }
9519             }
9520             memcpy(&branch_regs[i-1],&current,sizeof(current));
9521             branch_regs[i-1].isconst=0;
9522             branch_regs[i-1].wasconst=0;
9523             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9524             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9525           }
9526           else
9527           if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9528           {
9529             alloc_cc(&current,i-1);
9530             dirty_reg(&current,CCREG);
9531             if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9532               // The delay slot overwrote the branch condition
9533               // Delay slot goes after the test (in order)
9534               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9535               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9536               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9537               current.u|=1;
9538               current.uu|=1;
9539               delayslot_alloc(&current,i);
9540               current.isconst=0;
9541             }
9542             else
9543             {
9544               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9545               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9546               // Alloc the branch condition register
9547               alloc_reg(&current,i-1,rs1[i-1]);
9548               if(!(current.is32>>rs1[i-1]&1))
9549               {
9550                 alloc_reg64(&current,i-1,rs1[i-1]);
9551               }
9552             }
9553             memcpy(&branch_regs[i-1],&current,sizeof(current));
9554             branch_regs[i-1].isconst=0;
9555             branch_regs[i-1].wasconst=0;
9556             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9557             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9558           }
9559           else
9560           // Alloc the delay slot in case the branch is taken
9561           if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9562           {
9563             memcpy(&branch_regs[i-1],&current,sizeof(current));
9564             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9565             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9566             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9567             alloc_cc(&branch_regs[i-1],i);
9568             dirty_reg(&branch_regs[i-1],CCREG);
9569             delayslot_alloc(&branch_regs[i-1],i);
9570             branch_regs[i-1].isconst=0;
9571             alloc_reg(&current,i,CCREG); // Not taken path
9572             dirty_reg(&current,CCREG);
9573             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9574           }
9575           else
9576           if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9577           {
9578             memcpy(&branch_regs[i-1],&current,sizeof(current));
9579             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9580             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9581             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9582             alloc_cc(&branch_regs[i-1],i);
9583             dirty_reg(&branch_regs[i-1],CCREG);
9584             delayslot_alloc(&branch_regs[i-1],i);
9585             branch_regs[i-1].isconst=0;
9586             alloc_reg(&current,i,CCREG); // Not taken path
9587             dirty_reg(&current,CCREG);
9588             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9589           }
9590           break;
9591         case SJUMP:
9592           //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9593           if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9594           {
9595             alloc_cc(&current,i-1);
9596             dirty_reg(&current,CCREG);
9597             if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9598               // The delay slot overwrote the branch condition
9599               // Delay slot goes after the test (in order)
9600               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9601               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9602               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9603               current.u|=1;
9604               current.uu|=1;
9605               delayslot_alloc(&current,i);
9606               current.isconst=0;
9607             }
9608             else
9609             {
9610               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9611               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9612               // Alloc the branch condition register
9613               alloc_reg(&current,i-1,rs1[i-1]);
9614               if(!(current.is32>>rs1[i-1]&1))
9615               {
9616                 alloc_reg64(&current,i-1,rs1[i-1]);
9617               }
9618             }
9619             memcpy(&branch_regs[i-1],&current,sizeof(current));
9620             branch_regs[i-1].isconst=0;
9621             branch_regs[i-1].wasconst=0;
9622             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9623             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9624           }
9625           else
9626           // Alloc the delay slot in case the branch is taken
9627           if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9628           {
9629             memcpy(&branch_regs[i-1],&current,sizeof(current));
9630             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9631             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9632             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9633             alloc_cc(&branch_regs[i-1],i);
9634             dirty_reg(&branch_regs[i-1],CCREG);
9635             delayslot_alloc(&branch_regs[i-1],i);
9636             branch_regs[i-1].isconst=0;
9637             alloc_reg(&current,i,CCREG); // Not taken path
9638             dirty_reg(&current,CCREG);
9639             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9640           }
9641           // FIXME: BLTZAL/BGEZAL
9642           if(opcode2[i-1]&0x10) { // BxxZAL
9643             alloc_reg(&branch_regs[i-1],i-1,31);
9644             dirty_reg(&branch_regs[i-1],31);
9645             branch_regs[i-1].is32|=1LL<<31;
9646           }
9647           break;
9648         case FJUMP:
9649           if(likely[i-1]==0) // BC1F/BC1T
9650           {
9651             alloc_cc(&current,i-1);
9652             dirty_reg(&current,CCREG);
9653             if(itype[i]==FCOMP) {
9654               // The delay slot overwrote the branch condition
9655               // Delay slot goes after the test (in order)
9656               delayslot_alloc(&current,i);
9657               current.isconst=0;
9658             }
9659             else
9660             {
9661               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9662               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9663               // Alloc the branch condition register
9664               alloc_reg(&current,i-1,FSREG);
9665             }
9666             memcpy(&branch_regs[i-1],&current,sizeof(current));
9667             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9668           }
9669           else // BC1FL/BC1TL
9670           {
9671             // Alloc the delay slot in case the branch is taken
9672             memcpy(&branch_regs[i-1],&current,sizeof(current));
9673             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9674             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9675             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9676             alloc_cc(&branch_regs[i-1],i);
9677             dirty_reg(&branch_regs[i-1],CCREG);
9678             delayslot_alloc(&branch_regs[i-1],i);
9679             branch_regs[i-1].isconst=0;
9680             alloc_reg(&current,i,CCREG); // Not taken path
9681             dirty_reg(&current,CCREG);
9682             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9683           }
9684           break;
9685       }
9686
9687       if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9688       {
9689         if(rt1[i-1]==31) // JAL/JALR
9690         {
9691           // Subroutine call will return here, don't alloc any registers
9692           current.is32=1;
9693           current.dirty=0;
9694           clear_all_regs(current.regmap);
9695           alloc_reg(&current,i,CCREG);
9696           dirty_reg(&current,CCREG);
9697         }
9698         else if(i+1<slen)
9699         {
9700           // Internal branch will jump here, match registers to caller
9701           current.is32=0x3FFFFFFFFLL;
9702           current.dirty=0;
9703           clear_all_regs(current.regmap);
9704           alloc_reg(&current,i,CCREG);
9705           dirty_reg(&current,CCREG);
9706           for(j=i-1;j>=0;j--)
9707           {
9708             if(ba[j]==start+i*4+4) {
9709               memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9710               current.is32=branch_regs[j].is32;
9711               current.dirty=branch_regs[j].dirty;
9712               break;
9713             }
9714           }
9715           while(j>=0) {
9716             if(ba[j]==start+i*4+4) {
9717               for(hr=0;hr<HOST_REGS;hr++) {
9718                 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9719                   current.regmap[hr]=-1;
9720                 }
9721                 current.is32&=branch_regs[j].is32;
9722                 current.dirty&=branch_regs[j].dirty;
9723               }
9724             }
9725             j--;
9726           }
9727         }
9728       }
9729     }
9730
9731     // Count cycles in between branches
9732     ccadj[i]=cc;
9733     if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
9734     {
9735       cc=0;
9736     }
9737 #ifdef PCSX
9738     else if(/*itype[i]==LOAD||*/itype[i]==STORE||itype[i]==C1LS) // load causes weird timing issues
9739     {
9740       cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
9741     }
9742     else if(itype[i]==C2LS)
9743     {
9744       cc+=4;
9745     }
9746 #endif
9747     else
9748     {
9749       cc++;
9750     }
9751
9752     flush_dirty_uppers(&current);
9753     if(!is_ds[i]) {
9754       regs[i].is32=current.is32;
9755       regs[i].dirty=current.dirty;
9756       regs[i].isconst=current.isconst;
9757       memcpy(constmap[i],current.constmap,sizeof(current.constmap));
9758     }
9759     for(hr=0;hr<HOST_REGS;hr++) {
9760       if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
9761         if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9762           regs[i].wasconst&=~(1<<hr);
9763         }
9764       }
9765     }
9766     if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9767   }
9768
9769   /* Pass 4 - Cull unused host registers */
9770
9771   uint64_t nr=0;
9772
9773   for (i=slen-1;i>=0;i--)
9774   {
9775     int hr;
9776     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9777     {
9778       if(ba[i]<start || ba[i]>=(start+slen*4))
9779       {
9780         // Branch out of this block, don't need anything
9781         nr=0;
9782       }
9783       else
9784       {
9785         // Internal branch
9786         // Need whatever matches the target
9787         nr=0;
9788         int t=(ba[i]-start)>>2;
9789         for(hr=0;hr<HOST_REGS;hr++)
9790         {
9791           if(regs[i].regmap_entry[hr]>=0) {
9792             if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9793           }
9794         }
9795       }
9796       // Conditional branch may need registers for following instructions
9797       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9798       {
9799         if(i<slen-2) {
9800           nr|=needed_reg[i+2];
9801           for(hr=0;hr<HOST_REGS;hr++)
9802           {
9803             if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9804             //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9805           }
9806         }
9807       }
9808       // Don't need stuff which is overwritten
9809       //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9810       //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9811       // Merge in delay slot
9812       for(hr=0;hr<HOST_REGS;hr++)
9813       {
9814         if(!likely[i]) {
9815           // These are overwritten unless the branch is "likely"
9816           // and the delay slot is nullified if not taken
9817           if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9818           if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9819         }
9820         if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9821         if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9822         if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9823         if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9824         if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9825         if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9826         if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9827         if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9828         if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9829           if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9830           if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9831         }
9832         if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9833           if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9834           if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9835         }
9836         if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
9837           if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9838           if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9839         }
9840       }
9841     }
9842     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
9843     {
9844       // SYSCALL instruction (software interrupt)
9845       nr=0;
9846     }
9847     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9848     {
9849       // ERET instruction (return from interrupt)
9850       nr=0;
9851     }
9852     else // Non-branch
9853     {
9854       if(i<slen-1) {
9855         for(hr=0;hr<HOST_REGS;hr++) {
9856           if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9857           if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9858           if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9859           if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9860         }
9861       }
9862     }
9863     for(hr=0;hr<HOST_REGS;hr++)
9864     {
9865       // Overwritten registers are not needed
9866       if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9867       if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9868       if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9869       // Source registers are needed
9870       if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9871       if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9872       if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9873       if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9874       if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9875       if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9876       if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9877       if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9878       if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9879         if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9880         if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9881       }
9882       if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
9883         if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9884         if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9885       }
9886       if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
9887         if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9888         if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9889       }
9890       // Don't store a register immediately after writing it,
9891       // may prevent dual-issue.
9892       // But do so if this is a branch target, otherwise we
9893       // might have to load the register before the branch.
9894       if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
9895         if((regmap_pre[i][hr]>0&&regmap_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
9896            (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
9897           if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9898           if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9899         }
9900         if((regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
9901            (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
9902           if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9903           if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9904         }
9905       }
9906     }
9907     // Cycle count is needed at branches.  Assume it is needed at the target too.
9908     if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
9909       if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9910       if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9911     }
9912     // Save it
9913     needed_reg[i]=nr;
9914
9915     // Deallocate unneeded registers
9916     for(hr=0;hr<HOST_REGS;hr++)
9917     {
9918       if(!((nr>>hr)&1)) {
9919         if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
9920         if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9921            (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9922            (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
9923         {
9924           if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9925           {
9926             if(likely[i]) {
9927               regs[i].regmap[hr]=-1;
9928               regs[i].isconst&=~(1<<hr);
9929               if(i<slen-2) {
9930                 regmap_pre[i+2][hr]=-1;
9931                 regs[i+2].wasconst&=~(1<<hr);
9932               }
9933             }
9934           }
9935         }
9936         if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9937         {
9938           int d1=0,d2=0,map=0,temp=0;
9939           if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
9940           {
9941             d1=dep1[i+1];
9942             d2=dep2[i+1];
9943           }
9944           if(using_tlb) {
9945             if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
9946                itype[i+1]==STORE || itype[i+1]==STORELR ||
9947                itype[i+1]==C1LS || itype[i+1]==C2LS)
9948             map=TLREG;
9949           } else
9950           if(itype[i+1]==STORE || itype[i+1]==STORELR ||
9951              (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
9952             map=INVCP;
9953           }
9954           if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
9955              itype[i+1]==C1LS || itype[i+1]==C2LS)
9956             temp=FTEMP;
9957           if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9958              (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9959              (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
9960              (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
9961              (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9962              regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
9963              (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
9964              regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
9965              regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
9966              regs[i].regmap[hr]!=map )
9967           {
9968             regs[i].regmap[hr]=-1;
9969             regs[i].isconst&=~(1<<hr);
9970             if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
9971                (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
9972                (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
9973                (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
9974                (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
9975                branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
9976                (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
9977                branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
9978                branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
9979                branch_regs[i].regmap[hr]!=map)
9980             {
9981               branch_regs[i].regmap[hr]=-1;
9982               branch_regs[i].regmap_entry[hr]=-1;
9983               if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9984               {
9985                 if(!likely[i]&&i<slen-2) {
9986                   regmap_pre[i+2][hr]=-1;
9987                   regs[i+2].wasconst&=~(1<<hr);
9988                 }
9989               }
9990             }
9991           }
9992         }
9993         else
9994         {
9995           // Non-branch
9996           if(i>0)
9997           {
9998             int d1=0,d2=0,map=-1,temp=-1;
9999             if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
10000             {
10001               d1=dep1[i];
10002               d2=dep2[i];
10003             }
10004             if(using_tlb) {
10005               if(itype[i]==LOAD || itype[i]==LOADLR ||
10006                  itype[i]==STORE || itype[i]==STORELR ||
10007                  itype[i]==C1LS || itype[i]==C2LS)
10008               map=TLREG;
10009             } else if(itype[i]==STORE || itype[i]==STORELR ||
10010                       (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
10011               map=INVCP;
10012             }
10013             if(itype[i]==LOADLR || itype[i]==STORELR ||
10014                itype[i]==C1LS || itype[i]==C2LS)
10015               temp=FTEMP;
10016             if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
10017                (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
10018                (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
10019                regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
10020                (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
10021                (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
10022             {
10023               if(i<slen-1&&!is_ds[i]) {
10024                 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
10025                 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
10026                 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
10027                 {
10028                   printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
10029                   assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
10030                 }
10031                 regmap_pre[i+1][hr]=-1;
10032                 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
10033                 regs[i+1].wasconst&=~(1<<hr);
10034               }
10035               regs[i].regmap[hr]=-1;
10036               regs[i].isconst&=~(1<<hr);
10037             }
10038           }
10039         }
10040       }
10041     }
10042   }
10043
10044   /* Pass 5 - Pre-allocate registers */
10045
10046   // If a register is allocated during a loop, try to allocate it for the
10047   // entire loop, if possible.  This avoids loading/storing registers
10048   // inside of the loop.
10049
10050   signed char f_regmap[HOST_REGS];
10051   clear_all_regs(f_regmap);
10052   for(i=0;i<slen-1;i++)
10053   {
10054     if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10055     {
10056       if(ba[i]>=start && ba[i]<(start+i*4))
10057       if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
10058       ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
10059       ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
10060       ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
10061       ||itype[i+1]==FCOMP||itype[i+1]==FCONV
10062       ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
10063       {
10064         int t=(ba[i]-start)>>2;
10065         if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
10066         if(t<2||(itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||rt1[t-2]!=31) // call/ret assumes no registers allocated
10067         for(hr=0;hr<HOST_REGS;hr++)
10068         {
10069           if(regs[i].regmap[hr]>64) {
10070             if(!((regs[i].dirty>>hr)&1))
10071               f_regmap[hr]=regs[i].regmap[hr];
10072             else f_regmap[hr]=-1;
10073           }
10074           else if(regs[i].regmap[hr]>=0) {
10075             if(f_regmap[hr]!=regs[i].regmap[hr]) {
10076               // dealloc old register
10077               int n;
10078               for(n=0;n<HOST_REGS;n++)
10079               {
10080                 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10081               }
10082               // and alloc new one
10083               f_regmap[hr]=regs[i].regmap[hr];
10084             }
10085           }
10086           if(branch_regs[i].regmap[hr]>64) {
10087             if(!((branch_regs[i].dirty>>hr)&1))
10088               f_regmap[hr]=branch_regs[i].regmap[hr];
10089             else f_regmap[hr]=-1;
10090           }
10091           else if(branch_regs[i].regmap[hr]>=0) {
10092             if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
10093               // dealloc old register
10094               int n;
10095               for(n=0;n<HOST_REGS;n++)
10096               {
10097                 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
10098               }
10099               // and alloc new one
10100               f_regmap[hr]=branch_regs[i].regmap[hr];
10101             }
10102           }
10103           if(ooo[i]) {
10104             if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
10105               f_regmap[hr]=branch_regs[i].regmap[hr];
10106           }else{
10107             if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
10108               f_regmap[hr]=branch_regs[i].regmap[hr];
10109           }
10110           // Avoid dirty->clean transition
10111           #ifdef DESTRUCTIVE_WRITEBACK
10112           if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
10113           #endif
10114           // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
10115           // case above, however it's always a good idea.  We can't hoist the
10116           // load if the register was already allocated, so there's no point
10117           // wasting time analyzing most of these cases.  It only "succeeds"
10118           // when the mapping was different and the load can be replaced with
10119           // a mov, which is of negligible benefit.  So such cases are
10120           // skipped below.
10121           if(f_regmap[hr]>0) {
10122             if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
10123               int r=f_regmap[hr];
10124               for(j=t;j<=i;j++)
10125               {
10126                 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10127                 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
10128                 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
10129                 if(r>63) {
10130                   // NB This can exclude the case where the upper-half
10131                   // register is lower numbered than the lower-half
10132                   // register.  Not sure if it's worth fixing...
10133                   if(get_reg(regs[j].regmap,r&63)<0) break;
10134                   if(get_reg(regs[j].regmap_entry,r&63)<0) break;
10135                   if(regs[j].is32&(1LL<<(r&63))) break;
10136                 }
10137                 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
10138                   //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10139                   int k;
10140                   if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
10141                     if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
10142                     if(r>63) {
10143                       if(get_reg(regs[i].regmap,r&63)<0) break;
10144                       if(get_reg(branch_regs[i].regmap,r&63)<0) break;
10145                     }
10146                     k=i;
10147                     while(k>1&&regs[k-1].regmap[hr]==-1) {
10148                       if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10149                         //printf("no free regs for store %x\n",start+(k-1)*4);
10150                         break;
10151                       }
10152                       if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
10153                         //printf("no-match due to different register\n");
10154                         break;
10155                       }
10156                       if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
10157                         //printf("no-match due to branch\n");
10158                         break;
10159                       }
10160                       // call/ret fast path assumes no registers allocated
10161                       if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)&&rt1[k-3]==31) {
10162                         break;
10163                       }
10164                       if(r>63) {
10165                         // NB This can exclude the case where the upper-half
10166                         // register is lower numbered than the lower-half
10167                         // register.  Not sure if it's worth fixing...
10168                         if(get_reg(regs[k-1].regmap,r&63)<0) break;
10169                         if(regs[k-1].is32&(1LL<<(r&63))) break;
10170                       }
10171                       k--;
10172                     }
10173                     if(i<slen-1) {
10174                       if((regs[k].is32&(1LL<<f_regmap[hr]))!=
10175                         (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
10176                         //printf("bad match after branch\n");
10177                         break;
10178                       }
10179                     }
10180                     if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
10181                       //printf("Extend r%d, %x ->\n",hr,start+k*4);
10182                       while(k<i) {
10183                         regs[k].regmap_entry[hr]=f_regmap[hr];
10184                         regs[k].regmap[hr]=f_regmap[hr];
10185                         regmap_pre[k+1][hr]=f_regmap[hr];
10186                         regs[k].wasdirty&=~(1<<hr);
10187                         regs[k].dirty&=~(1<<hr);
10188                         regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
10189                         regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
10190                         regs[k].wasconst&=~(1<<hr);
10191                         regs[k].isconst&=~(1<<hr);
10192                         k++;
10193                       }
10194                     }
10195                     else {
10196                       //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
10197                       break;
10198                     }
10199                     assert(regs[i-1].regmap[hr]==f_regmap[hr]);
10200                     if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
10201                       //printf("OK fill %x (r%d)\n",start+i*4,hr);
10202                       regs[i].regmap_entry[hr]=f_regmap[hr];
10203                       regs[i].regmap[hr]=f_regmap[hr];
10204                       regs[i].wasdirty&=~(1<<hr);
10205                       regs[i].dirty&=~(1<<hr);
10206                       regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
10207                       regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
10208                       regs[i].wasconst&=~(1<<hr);
10209                       regs[i].isconst&=~(1<<hr);
10210                       branch_regs[i].regmap_entry[hr]=f_regmap[hr];
10211                       branch_regs[i].wasdirty&=~(1<<hr);
10212                       branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
10213                       branch_regs[i].regmap[hr]=f_regmap[hr];
10214                       branch_regs[i].dirty&=~(1<<hr);
10215                       branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
10216                       branch_regs[i].wasconst&=~(1<<hr);
10217                       branch_regs[i].isconst&=~(1<<hr);
10218                       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
10219                         regmap_pre[i+2][hr]=f_regmap[hr];
10220                         regs[i+2].wasdirty&=~(1<<hr);
10221                         regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
10222                         assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
10223                           (regs[i+2].was32&(1LL<<f_regmap[hr])));
10224                       }
10225                     }
10226                   }
10227                   for(k=t;k<j;k++) {
10228                     // Alloc register clean at beginning of loop,
10229                     // but may dirty it in pass 6
10230                     regs[k].regmap_entry[hr]=f_regmap[hr];
10231                     regs[k].regmap[hr]=f_regmap[hr];
10232                     regs[k].dirty&=~(1<<hr);
10233                     regs[k].wasconst&=~(1<<hr);
10234                     regs[k].isconst&=~(1<<hr);
10235                     if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) {
10236                       branch_regs[k].regmap_entry[hr]=f_regmap[hr];
10237                       branch_regs[k].regmap[hr]=f_regmap[hr];
10238                       branch_regs[k].dirty&=~(1<<hr);
10239                       branch_regs[k].wasconst&=~(1<<hr);
10240                       branch_regs[k].isconst&=~(1<<hr);
10241                       if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
10242                         regmap_pre[k+2][hr]=f_regmap[hr];
10243                         regs[k+2].wasdirty&=~(1<<hr);
10244                         assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))==
10245                           (regs[k+2].was32&(1LL<<f_regmap[hr])));
10246                       }
10247                     }
10248                     else
10249                     {
10250                       regmap_pre[k+1][hr]=f_regmap[hr];
10251                       regs[k+1].wasdirty&=~(1<<hr);
10252                     }
10253                   }
10254                   if(regs[j].regmap[hr]==f_regmap[hr])
10255                     regs[j].regmap_entry[hr]=f_regmap[hr];
10256                   break;
10257                 }
10258                 if(j==i) break;
10259                 if(regs[j].regmap[hr]>=0)
10260                   break;
10261                 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
10262                   //printf("no-match due to different register\n");
10263                   break;
10264                 }
10265                 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
10266                   //printf("32/64 mismatch %x %d\n",start+j*4,hr);
10267                   break;
10268                 }
10269                 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10270                 {
10271                   // Stop on unconditional branch
10272                   break;
10273                 }
10274                 if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
10275                 {
10276                   if(ooo[j]) {
10277                     if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
10278                       break;
10279                   }else{
10280                     if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
10281                       break;
10282                   }
10283                   if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
10284                     //printf("no-match due to different register (branch)\n");
10285                     break;
10286                   }
10287                 }
10288                 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10289                   //printf("No free regs for store %x\n",start+j*4);
10290                   break;
10291                 }
10292                 if(f_regmap[hr]>=64) {
10293                   if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
10294                     break;
10295                   }
10296                   else
10297                   {
10298                     if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
10299                       break;
10300                     }
10301                   }
10302                 }
10303               }
10304             }
10305           }
10306         }
10307       }
10308     }else{
10309       // Non branch or undetermined branch target
10310       for(hr=0;hr<HOST_REGS;hr++)
10311       {
10312         if(hr!=EXCLUDE_REG) {
10313           if(regs[i].regmap[hr]>64) {
10314             if(!((regs[i].dirty>>hr)&1))
10315               f_regmap[hr]=regs[i].regmap[hr];
10316           }
10317           else if(regs[i].regmap[hr]>=0) {
10318             if(f_regmap[hr]!=regs[i].regmap[hr]) {
10319               // dealloc old register
10320               int n;
10321               for(n=0;n<HOST_REGS;n++)
10322               {
10323                 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10324               }
10325               // and alloc new one
10326               f_regmap[hr]=regs[i].regmap[hr];
10327             }
10328           }
10329         }
10330       }
10331       // Try to restore cycle count at branch targets
10332       if(bt[i]) {
10333         for(j=i;j<slen-1;j++) {
10334           if(regs[j].regmap[HOST_CCREG]!=-1) break;
10335           if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10336             //printf("no free regs for store %x\n",start+j*4);
10337             break;
10338           }
10339         }
10340         if(regs[j].regmap[HOST_CCREG]==CCREG) {
10341           int k=i;
10342           //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
10343           while(k<j) {
10344             regs[k].regmap_entry[HOST_CCREG]=CCREG;
10345             regs[k].regmap[HOST_CCREG]=CCREG;
10346             regmap_pre[k+1][HOST_CCREG]=CCREG;
10347             regs[k+1].wasdirty|=1<<HOST_CCREG;
10348             regs[k].dirty|=1<<HOST_CCREG;
10349             regs[k].wasconst&=~(1<<HOST_CCREG);
10350             regs[k].isconst&=~(1<<HOST_CCREG);
10351             k++;
10352           }
10353           regs[j].regmap_entry[HOST_CCREG]=CCREG;
10354         }
10355         // Work backwards from the branch target
10356         if(j>i&&f_regmap[HOST_CCREG]==CCREG)
10357         {
10358           //printf("Extend backwards\n");
10359           int k;
10360           k=i;
10361           while(regs[k-1].regmap[HOST_CCREG]==-1) {
10362             if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10363               //printf("no free regs for store %x\n",start+(k-1)*4);
10364               break;
10365             }
10366             k--;
10367           }
10368           if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
10369             //printf("Extend CC, %x ->\n",start+k*4);
10370             while(k<=i) {
10371               regs[k].regmap_entry[HOST_CCREG]=CCREG;
10372               regs[k].regmap[HOST_CCREG]=CCREG;
10373               regmap_pre[k+1][HOST_CCREG]=CCREG;
10374               regs[k+1].wasdirty|=1<<HOST_CCREG;
10375               regs[k].dirty|=1<<HOST_CCREG;
10376               regs[k].wasconst&=~(1<<HOST_CCREG);
10377               regs[k].isconst&=~(1<<HOST_CCREG);
10378               k++;
10379             }
10380           }
10381           else {
10382             //printf("Fail Extend CC, %x ->\n",start+k*4);
10383           }
10384         }
10385       }
10386       if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
10387          itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
10388          itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
10389          itype[i]!=FCONV&&itype[i]!=FCOMP)
10390       {
10391         memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
10392       }
10393     }
10394   }
10395
10396   // Cache memory offset or tlb map pointer if a register is available
10397   #ifndef HOST_IMM_ADDR32
10398   #ifndef RAM_OFFSET
10399   if(using_tlb)
10400   #endif
10401   {
10402     int earliest_available[HOST_REGS];
10403     int loop_start[HOST_REGS];
10404     int score[HOST_REGS];
10405     int end[HOST_REGS];
10406     int reg=using_tlb?MMREG:ROREG;
10407
10408     // Init
10409     for(hr=0;hr<HOST_REGS;hr++) {
10410       score[hr]=0;earliest_available[hr]=0;
10411       loop_start[hr]=MAXBLOCK;
10412     }
10413     for(i=0;i<slen-1;i++)
10414     {
10415       // Can't do anything if no registers are available
10416       if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i]) {
10417         for(hr=0;hr<HOST_REGS;hr++) {
10418           score[hr]=0;earliest_available[hr]=i+1;
10419           loop_start[hr]=MAXBLOCK;
10420         }
10421       }
10422       if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10423         if(!ooo[i]) {
10424           if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) {
10425             for(hr=0;hr<HOST_REGS;hr++) {
10426               score[hr]=0;earliest_available[hr]=i+1;
10427               loop_start[hr]=MAXBLOCK;
10428             }
10429           }
10430         }else{
10431           if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) {
10432             for(hr=0;hr<HOST_REGS;hr++) {
10433               score[hr]=0;earliest_available[hr]=i+1;
10434               loop_start[hr]=MAXBLOCK;
10435             }
10436           }
10437         }
10438       }
10439       // Mark unavailable registers
10440       for(hr=0;hr<HOST_REGS;hr++) {
10441         if(regs[i].regmap[hr]>=0) {
10442           score[hr]=0;earliest_available[hr]=i+1;
10443           loop_start[hr]=MAXBLOCK;
10444         }
10445         if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10446           if(branch_regs[i].regmap[hr]>=0) {
10447             score[hr]=0;earliest_available[hr]=i+2;
10448             loop_start[hr]=MAXBLOCK;
10449           }
10450         }
10451       }
10452       // No register allocations after unconditional jumps
10453       if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10454       {
10455         for(hr=0;hr<HOST_REGS;hr++) {
10456           score[hr]=0;earliest_available[hr]=i+2;
10457           loop_start[hr]=MAXBLOCK;
10458         }
10459         i++; // Skip delay slot too
10460         //printf("skip delay slot: %x\n",start+i*4);
10461       }
10462       else
10463       // Possible match
10464       if(itype[i]==LOAD||itype[i]==LOADLR||
10465          itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) {
10466         for(hr=0;hr<HOST_REGS;hr++) {
10467           if(hr!=EXCLUDE_REG) {
10468             end[hr]=i-1;
10469             for(j=i;j<slen-1;j++) {
10470               if(regs[j].regmap[hr]>=0) break;
10471               if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10472                 if(branch_regs[j].regmap[hr]>=0) break;
10473                 if(ooo[j]) {
10474                   if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) break;
10475                 }else{
10476                   if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) break;
10477                 }
10478               }
10479               else if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) break;
10480               if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10481                 int t=(ba[j]-start)>>2;
10482                 if(t<j&&t>=earliest_available[hr]) {
10483                   if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) { // call/ret assumes no registers allocated
10484                     // Score a point for hoisting loop invariant
10485                     if(t<loop_start[hr]) loop_start[hr]=t;
10486                     //printf("set loop_start: i=%x j=%x (%x)\n",start+i*4,start+j*4,start+t*4);
10487                     score[hr]++;
10488                     end[hr]=j;
10489                   }
10490                 }
10491                 else if(t<j) {
10492                   if(regs[t].regmap[hr]==reg) {
10493                     // Score a point if the branch target matches this register
10494                     score[hr]++;
10495                     end[hr]=j;
10496                   }
10497                 }
10498                 if(itype[j+1]==LOAD||itype[j+1]==LOADLR||
10499                    itype[j+1]==STORE||itype[j+1]==STORELR||itype[j+1]==C1LS) {
10500                   score[hr]++;
10501                   end[hr]=j;
10502                 }
10503               }
10504               if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10505               {
10506                 // Stop on unconditional branch
10507                 break;
10508               }
10509               else
10510               if(itype[j]==LOAD||itype[j]==LOADLR||
10511                  itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS) {
10512                 score[hr]++;
10513                 end[hr]=j;
10514               }
10515             }
10516           }
10517         }
10518         // Find highest score and allocate that register
10519         int maxscore=0;
10520         for(hr=0;hr<HOST_REGS;hr++) {
10521           if(hr!=EXCLUDE_REG) {
10522             if(score[hr]>score[maxscore]) {
10523               maxscore=hr;
10524               //printf("highest score: %d %d (%x->%x)\n",score[hr],hr,start+i*4,start+end[hr]*4);
10525             }
10526           }
10527         }
10528         if(score[maxscore]>1)
10529         {
10530           if(i<loop_start[maxscore]) loop_start[maxscore]=i;
10531           for(j=loop_start[maxscore];j<slen&&j<=end[maxscore];j++) {
10532             //if(regs[j].regmap[maxscore]>=0) {printf("oops: %x %x was %d=%d\n",loop_start[maxscore]*4+start,j*4+start,maxscore,regs[j].regmap[maxscore]);}
10533             assert(regs[j].regmap[maxscore]<0);
10534             if(j>loop_start[maxscore]) regs[j].regmap_entry[maxscore]=reg;
10535             regs[j].regmap[maxscore]=reg;
10536             regs[j].dirty&=~(1<<maxscore);
10537             regs[j].wasconst&=~(1<<maxscore);
10538             regs[j].isconst&=~(1<<maxscore);
10539             if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10540               branch_regs[j].regmap[maxscore]=reg;
10541               branch_regs[j].wasdirty&=~(1<<maxscore);
10542               branch_regs[j].dirty&=~(1<<maxscore);
10543               branch_regs[j].wasconst&=~(1<<maxscore);
10544               branch_regs[j].isconst&=~(1<<maxscore);
10545               if(itype[j]!=RJUMP&&itype[j]!=UJUMP&&(source[j]>>16)!=0x1000) {
10546                 regmap_pre[j+2][maxscore]=reg;
10547                 regs[j+2].wasdirty&=~(1<<maxscore);
10548               }
10549               // loop optimization (loop_preload)
10550               int t=(ba[j]-start)>>2;
10551               if(t==loop_start[maxscore]) {
10552                 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) // call/ret assumes no registers allocated
10553                   regs[t].regmap_entry[maxscore]=reg;
10554               }
10555             }
10556             else
10557             {
10558               if(j<1||(itype[j-1]!=RJUMP&&itype[j-1]!=UJUMP&&itype[j-1]!=CJUMP&&itype[j-1]!=SJUMP&&itype[j-1]!=FJUMP)) {
10559                 regmap_pre[j+1][maxscore]=reg;
10560                 regs[j+1].wasdirty&=~(1<<maxscore);
10561               }
10562             }
10563           }
10564           i=j-1;
10565           if(itype[j-1]==RJUMP||itype[j-1]==UJUMP||itype[j-1]==CJUMP||itype[j-1]==SJUMP||itype[j-1]==FJUMP) i++; // skip delay slot
10566           for(hr=0;hr<HOST_REGS;hr++) {
10567             score[hr]=0;earliest_available[hr]=i+i;
10568             loop_start[hr]=MAXBLOCK;
10569           }
10570         }
10571       }
10572     }
10573   }
10574   #endif
10575
10576   // This allocates registers (if possible) one instruction prior
10577   // to use, which can avoid a load-use penalty on certain CPUs.
10578   for(i=0;i<slen-1;i++)
10579   {
10580     if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10581     {
10582       if(!bt[i+1])
10583       {
10584         if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
10585            ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
10586         {
10587           if(rs1[i+1]) {
10588             if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10589             {
10590               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10591               {
10592                 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10593                 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10594                 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10595                 regs[i].isconst&=~(1<<hr);
10596                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10597                 constmap[i][hr]=constmap[i+1][hr];
10598                 regs[i+1].wasdirty&=~(1<<hr);
10599                 regs[i].dirty&=~(1<<hr);
10600               }
10601             }
10602           }
10603           if(rs2[i+1]) {
10604             if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10605             {
10606               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10607               {
10608                 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10609                 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10610                 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10611                 regs[i].isconst&=~(1<<hr);
10612                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10613                 constmap[i][hr]=constmap[i+1][hr];
10614                 regs[i+1].wasdirty&=~(1<<hr);
10615                 regs[i].dirty&=~(1<<hr);
10616               }
10617             }
10618           }
10619           // Preload target address for load instruction (non-constant)
10620           if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10621             if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10622             {
10623               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10624               {
10625                 regs[i].regmap[hr]=rs1[i+1];
10626                 regmap_pre[i+1][hr]=rs1[i+1];
10627                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10628                 regs[i].isconst&=~(1<<hr);
10629                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10630                 constmap[i][hr]=constmap[i+1][hr];
10631                 regs[i+1].wasdirty&=~(1<<hr);
10632                 regs[i].dirty&=~(1<<hr);
10633               }
10634             }
10635           }
10636           // Load source into target register
10637           if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10638             if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10639             {
10640               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10641               {
10642                 regs[i].regmap[hr]=rs1[i+1];
10643                 regmap_pre[i+1][hr]=rs1[i+1];
10644                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10645                 regs[i].isconst&=~(1<<hr);
10646                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10647                 constmap[i][hr]=constmap[i+1][hr];
10648                 regs[i+1].wasdirty&=~(1<<hr);
10649                 regs[i].dirty&=~(1<<hr);
10650               }
10651             }
10652           }
10653           // Preload map address
10654           #ifndef HOST_IMM_ADDR32
10655           if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
10656             hr=get_reg(regs[i+1].regmap,TLREG);
10657             if(hr>=0) {
10658               int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10659               if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10660                 int nr;
10661                 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10662                 {
10663                   regs[i].regmap[hr]=MGEN1+((i+1)&1);
10664                   regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10665                   regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10666                   regs[i].isconst&=~(1<<hr);
10667                   regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10668                   constmap[i][hr]=constmap[i+1][hr];
10669                   regs[i+1].wasdirty&=~(1<<hr);
10670                   regs[i].dirty&=~(1<<hr);
10671                 }
10672                 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10673                 {
10674                   // move it to another register
10675                   regs[i+1].regmap[hr]=-1;
10676                   regmap_pre[i+2][hr]=-1;
10677                   regs[i+1].regmap[nr]=TLREG;
10678                   regmap_pre[i+2][nr]=TLREG;
10679                   regs[i].regmap[nr]=MGEN1+((i+1)&1);
10680                   regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10681                   regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10682                   regs[i].isconst&=~(1<<nr);
10683                   regs[i+1].isconst&=~(1<<nr);
10684                   regs[i].dirty&=~(1<<nr);
10685                   regs[i+1].wasdirty&=~(1<<nr);
10686                   regs[i+1].dirty&=~(1<<nr);
10687                   regs[i+2].wasdirty&=~(1<<nr);
10688                 }
10689               }
10690             }
10691           }
10692           #endif
10693           // Address for store instruction (non-constant)
10694           if(itype[i+1]==STORE||itype[i+1]==STORELR
10695              ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
10696             if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10697               hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10698               if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10699               else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10700               assert(hr>=0);
10701               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10702               {
10703                 regs[i].regmap[hr]=rs1[i+1];
10704                 regmap_pre[i+1][hr]=rs1[i+1];
10705                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10706                 regs[i].isconst&=~(1<<hr);
10707                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10708                 constmap[i][hr]=constmap[i+1][hr];
10709                 regs[i+1].wasdirty&=~(1<<hr);
10710                 regs[i].dirty&=~(1<<hr);
10711               }
10712             }
10713           }
10714           if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
10715             if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10716               int nr;
10717               hr=get_reg(regs[i+1].regmap,FTEMP);
10718               assert(hr>=0);
10719               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10720               {
10721                 regs[i].regmap[hr]=rs1[i+1];
10722                 regmap_pre[i+1][hr]=rs1[i+1];
10723                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10724                 regs[i].isconst&=~(1<<hr);
10725                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10726                 constmap[i][hr]=constmap[i+1][hr];
10727                 regs[i+1].wasdirty&=~(1<<hr);
10728                 regs[i].dirty&=~(1<<hr);
10729               }
10730               else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10731               {
10732                 // move it to another register
10733                 regs[i+1].regmap[hr]=-1;
10734                 regmap_pre[i+2][hr]=-1;
10735                 regs[i+1].regmap[nr]=FTEMP;
10736                 regmap_pre[i+2][nr]=FTEMP;
10737                 regs[i].regmap[nr]=rs1[i+1];
10738                 regmap_pre[i+1][nr]=rs1[i+1];
10739                 regs[i+1].regmap_entry[nr]=rs1[i+1];
10740                 regs[i].isconst&=~(1<<nr);
10741                 regs[i+1].isconst&=~(1<<nr);
10742                 regs[i].dirty&=~(1<<nr);
10743                 regs[i+1].wasdirty&=~(1<<nr);
10744                 regs[i+1].dirty&=~(1<<nr);
10745                 regs[i+2].wasdirty&=~(1<<nr);
10746               }
10747             }
10748           }
10749           if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
10750             if(itype[i+1]==LOAD)
10751               hr=get_reg(regs[i+1].regmap,rt1[i+1]);
10752             if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
10753               hr=get_reg(regs[i+1].regmap,FTEMP);
10754             if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
10755               hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10756               if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10757             }
10758             if(hr>=0&&regs[i].regmap[hr]<0) {
10759               int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10760               if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10761                 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10762                 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10763                 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10764                 regs[i].isconst&=~(1<<hr);
10765                 regs[i+1].wasdirty&=~(1<<hr);
10766                 regs[i].dirty&=~(1<<hr);
10767               }
10768             }
10769           }
10770         }
10771       }
10772     }
10773   }
10774
10775   /* Pass 6 - Optimize clean/dirty state */
10776   clean_registers(0,slen-1,1);
10777
10778   /* Pass 7 - Identify 32-bit registers */
10779 #ifndef FORCE32
10780   provisional_r32();
10781
10782   u_int r32=0;
10783
10784   for (i=slen-1;i>=0;i--)
10785   {
10786     int hr;
10787     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10788     {
10789       if(ba[i]<start || ba[i]>=(start+slen*4))
10790       {
10791         // Branch out of this block, don't need anything
10792         r32=0;
10793       }
10794       else
10795       {
10796         // Internal branch
10797         // Need whatever matches the target
10798         // (and doesn't get overwritten by the delay slot instruction)
10799         r32=0;
10800         int t=(ba[i]-start)>>2;
10801         if(ba[i]>start+i*4) {
10802           // Forward branch
10803           if(!(requires_32bit[t]&~regs[i].was32))
10804             r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10805         }else{
10806           // Backward branch
10807           //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10808           //  r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10809           if(!(pr32[t]&~regs[i].was32))
10810             r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10811         }
10812       }
10813       // Conditional branch may need registers for following instructions
10814       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10815       {
10816         if(i<slen-2) {
10817           r32|=requires_32bit[i+2];
10818           r32&=regs[i].was32;
10819           // Mark this address as a branch target since it may be called
10820           // upon return from interrupt
10821           bt[i+2]=1;
10822         }
10823       }
10824       // Merge in delay slot
10825       if(!likely[i]) {
10826         // These are overwritten unless the branch is "likely"
10827         // and the delay slot is nullified if not taken
10828         r32&=~(1LL<<rt1[i+1]);
10829         r32&=~(1LL<<rt2[i+1]);
10830       }
10831       // Assume these are needed (delay slot)
10832       if(us1[i+1]>0)
10833       {
10834         if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10835       }
10836       if(us2[i+1]>0)
10837       {
10838         if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10839       }
10840       if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10841       {
10842         if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10843       }
10844       if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10845       {
10846         if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10847       }
10848     }
10849     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
10850     {
10851       // SYSCALL instruction (software interrupt)
10852       r32=0;
10853     }
10854     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10855     {
10856       // ERET instruction (return from interrupt)
10857       r32=0;
10858     }
10859     // Check 32 bits
10860     r32&=~(1LL<<rt1[i]);
10861     r32&=~(1LL<<rt2[i]);
10862     if(us1[i]>0)
10863     {
10864       if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10865     }
10866     if(us2[i]>0)
10867     {
10868       if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10869     }
10870     if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
10871     {
10872       if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
10873     }
10874     if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
10875     {
10876       if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
10877     }
10878     requires_32bit[i]=r32;
10879
10880     // Dirty registers which are 32-bit, require 32-bit input
10881     // as they will be written as 32-bit values
10882     for(hr=0;hr<HOST_REGS;hr++)
10883     {
10884       if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
10885         if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
10886           if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
10887           requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
10888         }
10889       }
10890     }
10891     //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
10892   }
10893 #else
10894   for (i=slen-1;i>=0;i--)
10895   {
10896     if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10897     {
10898       // Conditional branch
10899       if((source[i]>>16)!=0x1000&&i<slen-2) {
10900         // Mark this address as a branch target since it may be called
10901         // upon return from interrupt
10902         bt[i+2]=1;
10903       }
10904     }
10905   }
10906 #endif
10907
10908   if(itype[slen-1]==SPAN) {
10909     bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
10910   }
10911
10912 #ifdef DISASM
10913   /* Debug/disassembly */
10914   for(i=0;i<slen;i++)
10915   {
10916     printf("U:");
10917     int r;
10918     for(r=1;r<=CCREG;r++) {
10919       if((unneeded_reg[i]>>r)&1) {
10920         if(r==HIREG) printf(" HI");
10921         else if(r==LOREG) printf(" LO");
10922         else printf(" r%d",r);
10923       }
10924     }
10925 #ifndef FORCE32
10926     printf(" UU:");
10927     for(r=1;r<=CCREG;r++) {
10928       if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
10929         if(r==HIREG) printf(" HI");
10930         else if(r==LOREG) printf(" LO");
10931         else printf(" r%d",r);
10932       }
10933     }
10934     printf(" 32:");
10935     for(r=0;r<=CCREG;r++) {
10936       //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10937       if((regs[i].was32>>r)&1) {
10938         if(r==CCREG) printf(" CC");
10939         else if(r==HIREG) printf(" HI");
10940         else if(r==LOREG) printf(" LO");
10941         else printf(" r%d",r);
10942       }
10943     }
10944 #endif
10945     printf("\n");
10946     #if defined(__i386__) || defined(__x86_64__)
10947     printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
10948     #endif
10949     #ifdef __arm__
10950     printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
10951     #endif
10952     printf("needs: ");
10953     if(needed_reg[i]&1) printf("eax ");
10954     if((needed_reg[i]>>1)&1) printf("ecx ");
10955     if((needed_reg[i]>>2)&1) printf("edx ");
10956     if((needed_reg[i]>>3)&1) printf("ebx ");
10957     if((needed_reg[i]>>5)&1) printf("ebp ");
10958     if((needed_reg[i]>>6)&1) printf("esi ");
10959     if((needed_reg[i]>>7)&1) printf("edi ");
10960     printf("r:");
10961     for(r=0;r<=CCREG;r++) {
10962       //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10963       if((requires_32bit[i]>>r)&1) {
10964         if(r==CCREG) printf(" CC");
10965         else if(r==HIREG) printf(" HI");
10966         else if(r==LOREG) printf(" LO");
10967         else printf(" r%d",r);
10968       }
10969     }
10970     printf("\n");
10971     /*printf("pr:");
10972     for(r=0;r<=CCREG;r++) {
10973       //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10974       if((pr32[i]>>r)&1) {
10975         if(r==CCREG) printf(" CC");
10976         else if(r==HIREG) printf(" HI");
10977         else if(r==LOREG) printf(" LO");
10978         else printf(" r%d",r);
10979       }
10980     }
10981     if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
10982     printf("\n");*/
10983     #if defined(__i386__) || defined(__x86_64__)
10984     printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
10985     printf("dirty: ");
10986     if(regs[i].wasdirty&1) printf("eax ");
10987     if((regs[i].wasdirty>>1)&1) printf("ecx ");
10988     if((regs[i].wasdirty>>2)&1) printf("edx ");
10989     if((regs[i].wasdirty>>3)&1) printf("ebx ");
10990     if((regs[i].wasdirty>>5)&1) printf("ebp ");
10991     if((regs[i].wasdirty>>6)&1) printf("esi ");
10992     if((regs[i].wasdirty>>7)&1) printf("edi ");
10993     #endif
10994     #ifdef __arm__
10995     printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
10996     printf("dirty: ");
10997     if(regs[i].wasdirty&1) printf("r0 ");
10998     if((regs[i].wasdirty>>1)&1) printf("r1 ");
10999     if((regs[i].wasdirty>>2)&1) printf("r2 ");
11000     if((regs[i].wasdirty>>3)&1) printf("r3 ");
11001     if((regs[i].wasdirty>>4)&1) printf("r4 ");
11002     if((regs[i].wasdirty>>5)&1) printf("r5 ");
11003     if((regs[i].wasdirty>>6)&1) printf("r6 ");
11004     if((regs[i].wasdirty>>7)&1) printf("r7 ");
11005     if((regs[i].wasdirty>>8)&1) printf("r8 ");
11006     if((regs[i].wasdirty>>9)&1) printf("r9 ");
11007     if((regs[i].wasdirty>>10)&1) printf("r10 ");
11008     if((regs[i].wasdirty>>12)&1) printf("r12 ");
11009     #endif
11010     printf("\n");
11011     disassemble_inst(i);
11012     //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
11013     #if defined(__i386__) || defined(__x86_64__)
11014     printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
11015     if(regs[i].dirty&1) printf("eax ");
11016     if((regs[i].dirty>>1)&1) printf("ecx ");
11017     if((regs[i].dirty>>2)&1) printf("edx ");
11018     if((regs[i].dirty>>3)&1) printf("ebx ");
11019     if((regs[i].dirty>>5)&1) printf("ebp ");
11020     if((regs[i].dirty>>6)&1) printf("esi ");
11021     if((regs[i].dirty>>7)&1) printf("edi ");
11022     #endif
11023     #ifdef __arm__
11024     printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
11025     if(regs[i].dirty&1) printf("r0 ");
11026     if((regs[i].dirty>>1)&1) printf("r1 ");
11027     if((regs[i].dirty>>2)&1) printf("r2 ");
11028     if((regs[i].dirty>>3)&1) printf("r3 ");
11029     if((regs[i].dirty>>4)&1) printf("r4 ");
11030     if((regs[i].dirty>>5)&1) printf("r5 ");
11031     if((regs[i].dirty>>6)&1) printf("r6 ");
11032     if((regs[i].dirty>>7)&1) printf("r7 ");
11033     if((regs[i].dirty>>8)&1) printf("r8 ");
11034     if((regs[i].dirty>>9)&1) printf("r9 ");
11035     if((regs[i].dirty>>10)&1) printf("r10 ");
11036     if((regs[i].dirty>>12)&1) printf("r12 ");
11037     #endif
11038     printf("\n");
11039     if(regs[i].isconst) {
11040       printf("constants: ");
11041       #if defined(__i386__) || defined(__x86_64__)
11042       if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
11043       if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
11044       if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
11045       if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
11046       if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
11047       if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
11048       if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
11049       #endif
11050       #ifdef __arm__
11051       if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
11052       if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
11053       if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
11054       if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
11055       if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
11056       if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
11057       if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
11058       if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
11059       if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
11060       if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
11061       if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
11062       if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
11063       #endif
11064       printf("\n");
11065     }
11066 #ifndef FORCE32
11067     printf(" 32:");
11068     for(r=0;r<=CCREG;r++) {
11069       if((regs[i].is32>>r)&1) {
11070         if(r==CCREG) printf(" CC");
11071         else if(r==HIREG) printf(" HI");
11072         else if(r==LOREG) printf(" LO");
11073         else printf(" r%d",r);
11074       }
11075     }
11076     printf("\n");
11077 #endif
11078     /*printf(" p32:");
11079     for(r=0;r<=CCREG;r++) {
11080       if((p32[i]>>r)&1) {
11081         if(r==CCREG) printf(" CC");
11082         else if(r==HIREG) printf(" HI");
11083         else if(r==LOREG) printf(" LO");
11084         else printf(" r%d",r);
11085       }
11086     }
11087     if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
11088     else printf("\n");*/
11089     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
11090       #if defined(__i386__) || defined(__x86_64__)
11091       printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
11092       if(branch_regs[i].dirty&1) printf("eax ");
11093       if((branch_regs[i].dirty>>1)&1) printf("ecx ");
11094       if((branch_regs[i].dirty>>2)&1) printf("edx ");
11095       if((branch_regs[i].dirty>>3)&1) printf("ebx ");
11096       if((branch_regs[i].dirty>>5)&1) printf("ebp ");
11097       if((branch_regs[i].dirty>>6)&1) printf("esi ");
11098       if((branch_regs[i].dirty>>7)&1) printf("edi ");
11099       #endif
11100       #ifdef __arm__
11101       printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
11102       if(branch_regs[i].dirty&1) printf("r0 ");
11103       if((branch_regs[i].dirty>>1)&1) printf("r1 ");
11104       if((branch_regs[i].dirty>>2)&1) printf("r2 ");
11105       if((branch_regs[i].dirty>>3)&1) printf("r3 ");
11106       if((branch_regs[i].dirty>>4)&1) printf("r4 ");
11107       if((branch_regs[i].dirty>>5)&1) printf("r5 ");
11108       if((branch_regs[i].dirty>>6)&1) printf("r6 ");
11109       if((branch_regs[i].dirty>>7)&1) printf("r7 ");
11110       if((branch_regs[i].dirty>>8)&1) printf("r8 ");
11111       if((branch_regs[i].dirty>>9)&1) printf("r9 ");
11112       if((branch_regs[i].dirty>>10)&1) printf("r10 ");
11113       if((branch_regs[i].dirty>>12)&1) printf("r12 ");
11114       #endif
11115 #ifndef FORCE32
11116       printf(" 32:");
11117       for(r=0;r<=CCREG;r++) {
11118         if((branch_regs[i].is32>>r)&1) {
11119           if(r==CCREG) printf(" CC");
11120           else if(r==HIREG) printf(" HI");
11121           else if(r==LOREG) printf(" LO");
11122           else printf(" r%d",r);
11123         }
11124       }
11125       printf("\n");
11126 #endif
11127     }
11128   }
11129 #endif // DISASM
11130
11131   /* Pass 8 - Assembly */
11132   linkcount=0;stubcount=0;
11133   ds=0;is_delayslot=0;
11134   cop1_usable=0;
11135   uint64_t is32_pre=0;
11136   u_int dirty_pre=0;
11137   u_int beginning=(u_int)out;
11138   if((u_int)addr&1) {
11139     ds=1;
11140     pagespan_ds();
11141   }
11142   u_int instr_addr0_override=0;
11143
11144 #ifdef PCSX
11145   if (start == 0x80030000) {
11146     // nasty hack for fastbios thing
11147     // override block entry to this code
11148     instr_addr0_override=(u_int)out;
11149     emit_movimm(start,0);
11150     // abuse io address var as a flag that we
11151     // have already returned here once
11152     emit_readword((int)&address,1);
11153     emit_writeword(0,(int)&pcaddr);
11154     emit_writeword(0,(int)&address);
11155     emit_cmp(0,1);
11156     emit_jne((int)new_dyna_leave);
11157   }
11158 #endif
11159   for(i=0;i<slen;i++)
11160   {
11161     //if(ds) printf("ds: ");
11162     disassemble_inst(i);
11163     if(ds) {
11164       ds=0; // Skip delay slot
11165       if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
11166       instr_addr[i]=0;
11167     } else {
11168       speculate_register_values(i);
11169       #ifndef DESTRUCTIVE_WRITEBACK
11170       if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11171       {
11172         wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
11173               unneeded_reg[i],unneeded_reg_upper[i]);
11174         wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
11175               unneeded_reg[i],unneeded_reg_upper[i]);
11176       }
11177       if((itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)&&!likely[i]) {
11178         is32_pre=branch_regs[i].is32;
11179         dirty_pre=branch_regs[i].dirty;
11180       }else{
11181         is32_pre=regs[i].is32;
11182         dirty_pre=regs[i].dirty;
11183       }
11184       #endif
11185       // write back
11186       if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11187       {
11188         wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
11189                       unneeded_reg[i],unneeded_reg_upper[i]);
11190         loop_preload(regmap_pre[i],regs[i].regmap_entry);
11191       }
11192       // branch target entry point
11193       instr_addr[i]=(u_int)out;
11194       assem_debug("<->\n");
11195       // load regs
11196       if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
11197         wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
11198       load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
11199       address_generation(i,&regs[i],regs[i].regmap_entry);
11200       load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
11201       if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
11202       {
11203         // Load the delay slot registers if necessary
11204         if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i]&&(rs1[i+1]!=rt1[i]||rt1[i]==0))
11205           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11206         if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i]&&(rs2[i+1]!=rt1[i]||rt1[i]==0))
11207           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11208         if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
11209           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11210       }
11211       else if(i+1<slen)
11212       {
11213         // Preload registers for following instruction
11214         if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
11215           if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
11216             load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11217         if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
11218           if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
11219             load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11220       }
11221       // TODO: if(is_ooo(i)) address_generation(i+1);
11222       if(itype[i]==CJUMP||itype[i]==FJUMP)
11223         load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
11224       if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
11225         load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11226       if(bt[i]) cop1_usable=0;
11227       // assemble
11228       switch(itype[i]) {
11229         case ALU:
11230           alu_assemble(i,&regs[i]);break;
11231         case IMM16:
11232           imm16_assemble(i,&regs[i]);break;
11233         case SHIFT:
11234           shift_assemble(i,&regs[i]);break;
11235         case SHIFTIMM:
11236           shiftimm_assemble(i,&regs[i]);break;
11237         case LOAD:
11238           load_assemble(i,&regs[i]);break;
11239         case LOADLR:
11240           loadlr_assemble(i,&regs[i]);break;
11241         case STORE:
11242           store_assemble(i,&regs[i]);break;
11243         case STORELR:
11244           storelr_assemble(i,&regs[i]);break;
11245         case COP0:
11246           cop0_assemble(i,&regs[i]);break;
11247         case COP1:
11248           cop1_assemble(i,&regs[i]);break;
11249         case C1LS:
11250           c1ls_assemble(i,&regs[i]);break;
11251         case COP2:
11252           cop2_assemble(i,&regs[i]);break;
11253         case C2LS:
11254           c2ls_assemble(i,&regs[i]);break;
11255         case C2OP:
11256           c2op_assemble(i,&regs[i]);break;
11257         case FCONV:
11258           fconv_assemble(i,&regs[i]);break;
11259         case FLOAT:
11260           float_assemble(i,&regs[i]);break;
11261         case FCOMP:
11262           fcomp_assemble(i,&regs[i]);break;
11263         case MULTDIV:
11264           multdiv_assemble(i,&regs[i]);break;
11265         case MOV:
11266           mov_assemble(i,&regs[i]);break;
11267         case SYSCALL:
11268           syscall_assemble(i,&regs[i]);break;
11269         case HLECALL:
11270           hlecall_assemble(i,&regs[i]);break;
11271         case INTCALL:
11272           intcall_assemble(i,&regs[i]);break;
11273         case UJUMP:
11274           ujump_assemble(i,&regs[i]);ds=1;break;
11275         case RJUMP:
11276           rjump_assemble(i,&regs[i]);ds=1;break;
11277         case CJUMP:
11278           cjump_assemble(i,&regs[i]);ds=1;break;
11279         case SJUMP:
11280           sjump_assemble(i,&regs[i]);ds=1;break;
11281         case FJUMP:
11282           fjump_assemble(i,&regs[i]);ds=1;break;
11283         case SPAN:
11284           pagespan_assemble(i,&regs[i]);break;
11285       }
11286       if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
11287         literal_pool(1024);
11288       else
11289         literal_pool_jumpover(256);
11290     }
11291   }
11292   //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
11293   // If the block did not end with an unconditional branch,
11294   // add a jump to the next instruction.
11295   if(i>1) {
11296     if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
11297       assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11298       assert(i==slen);
11299       if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
11300         store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11301         if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11302           emit_loadreg(CCREG,HOST_CCREG);
11303         emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
11304       }
11305       else if(!likely[i-2])
11306       {
11307         store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
11308         assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
11309       }
11310       else
11311       {
11312         store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
11313         assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
11314       }
11315       add_to_linker((int)out,start+i*4,0);
11316       emit_jmp(0);
11317     }
11318   }
11319   else
11320   {
11321     assert(i>0);
11322     assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11323     store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11324     if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11325       emit_loadreg(CCREG,HOST_CCREG);
11326     emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
11327     add_to_linker((int)out,start+i*4,0);
11328     emit_jmp(0);
11329   }
11330
11331   // TODO: delay slot stubs?
11332   // Stubs
11333   for(i=0;i<stubcount;i++)
11334   {
11335     switch(stubs[i][0])
11336     {
11337       case LOADB_STUB:
11338       case LOADH_STUB:
11339       case LOADW_STUB:
11340       case LOADD_STUB:
11341       case LOADBU_STUB:
11342       case LOADHU_STUB:
11343         do_readstub(i);break;
11344       case STOREB_STUB:
11345       case STOREH_STUB:
11346       case STOREW_STUB:
11347       case STORED_STUB:
11348         do_writestub(i);break;
11349       case CC_STUB:
11350         do_ccstub(i);break;
11351       case INVCODE_STUB:
11352         do_invstub(i);break;
11353       case FP_STUB:
11354         do_cop1stub(i);break;
11355       case STORELR_STUB:
11356         do_unalignedwritestub(i);break;
11357     }
11358   }
11359
11360   if (instr_addr0_override)
11361     instr_addr[0] = instr_addr0_override;
11362
11363   /* Pass 9 - Linker */
11364   for(i=0;i<linkcount;i++)
11365   {
11366     assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
11367     literal_pool(64);
11368     if(!link_addr[i][2])
11369     {
11370       void *stub=out;
11371       void *addr=check_addr(link_addr[i][1]);
11372       emit_extjump(link_addr[i][0],link_addr[i][1]);
11373       if(addr) {
11374         set_jump_target(link_addr[i][0],(int)addr);
11375         add_link(link_addr[i][1],stub);
11376       }
11377       else set_jump_target(link_addr[i][0],(int)stub);
11378     }
11379     else
11380     {
11381       // Internal branch
11382       int target=(link_addr[i][1]-start)>>2;
11383       assert(target>=0&&target<slen);
11384       assert(instr_addr[target]);
11385       //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11386       //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
11387       //#else
11388       set_jump_target(link_addr[i][0],instr_addr[target]);
11389       //#endif
11390     }
11391   }
11392   // External Branch Targets (jump_in)
11393   if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
11394   for(i=0;i<slen;i++)
11395   {
11396     if(bt[i]||i==0)
11397     {
11398       if(instr_addr[i]) // TODO - delay slots (=null)
11399       {
11400         u_int vaddr=start+i*4;
11401         u_int page=get_page(vaddr);
11402         u_int vpage=get_vpage(vaddr);
11403         literal_pool(256);
11404         //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
11405 #ifndef FORCE32
11406         if(!requires_32bit[i])
11407 #else
11408         if(1)
11409 #endif
11410         {
11411           assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11412           assem_debug("jump_in: %x\n",start+i*4);
11413           ll_add(jump_dirty+vpage,vaddr,(void *)out);
11414           int entry_point=do_dirty_stub(i);
11415           ll_add(jump_in+page,vaddr,(void *)entry_point);
11416           // If there was an existing entry in the hash table,
11417           // replace it with the new address.
11418           // Don't add new entries.  We'll insert the
11419           // ones that actually get used in check_addr().
11420           int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
11421           if(ht_bin[0]==vaddr) {
11422             ht_bin[1]=entry_point;
11423           }
11424           if(ht_bin[2]==vaddr) {
11425             ht_bin[3]=entry_point;
11426           }
11427         }
11428         else
11429         {
11430           u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
11431           assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11432           assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
11433           //int entry_point=(int)out;
11434           ////assem_debug("entry_point: %x\n",entry_point);
11435           //load_regs_entry(i);
11436           //if(entry_point==(int)out)
11437           //  entry_point=instr_addr[i];
11438           //else
11439           //  emit_jmp(instr_addr[i]);
11440           //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11441           ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
11442           int entry_point=do_dirty_stub(i);
11443           ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11444         }
11445       }
11446     }
11447   }
11448   // Write out the literal pool if necessary
11449   literal_pool(0);
11450   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11451   // Align code
11452   if(((u_int)out)&7) emit_addnop(13);
11453   #endif
11454   assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
11455   //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
11456   memcpy(copy,source,slen*4);
11457   copy+=slen*4;
11458
11459   #ifdef __arm__
11460   __clear_cache((void *)beginning,out);
11461   #endif
11462
11463   // If we're within 256K of the end of the buffer,
11464   // start over from the beginning. (Is 256K enough?)
11465   if((int)out>BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
11466
11467   // Trap writes to any of the pages we compiled
11468   for(i=start>>12;i<=(start+slen*4)>>12;i++) {
11469     invalid_code[i]=0;
11470 #ifndef DISABLE_TLB
11471     memory_map[i]|=0x40000000;
11472     if((signed int)start>=(signed int)0xC0000000) {
11473       assert(using_tlb);
11474       j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
11475       invalid_code[j]=0;
11476       memory_map[j]|=0x40000000;
11477       //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
11478     }
11479 #endif
11480   }
11481   inv_code_start=inv_code_end=~0;
11482 #ifdef PCSX
11483   // for PCSX we need to mark all mirrors too
11484   if(get_page(start)<(RAM_SIZE>>12))
11485     for(i=start>>12;i<=(start+slen*4)>>12;i++)
11486       invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]=
11487       invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]=
11488       invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0;
11489 #endif
11490
11491   /* Pass 10 - Free memory by expiring oldest blocks */
11492
11493   int end=((((int)out-BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
11494   while(expirep!=end)
11495   {
11496     int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
11497     int base=BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
11498     inv_debug("EXP: Phase %d\n",expirep);
11499     switch((expirep>>11)&3)
11500     {
11501       case 0:
11502         // Clear jump_in and jump_dirty
11503         ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
11504         ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
11505         ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
11506         ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
11507         break;
11508       case 1:
11509         // Clear pointers
11510         ll_kill_pointers(jump_out[expirep&2047],base,shift);
11511         ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
11512         break;
11513       case 2:
11514         // Clear hash table
11515         for(i=0;i<32;i++) {
11516           int *ht_bin=hash_table[((expirep&2047)<<5)+i];
11517           if((ht_bin[3]>>shift)==(base>>shift) ||
11518              ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11519             inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
11520             ht_bin[2]=ht_bin[3]=-1;
11521           }
11522           if((ht_bin[1]>>shift)==(base>>shift) ||
11523              ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11524             inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
11525             ht_bin[0]=ht_bin[2];
11526             ht_bin[1]=ht_bin[3];
11527             ht_bin[2]=ht_bin[3]=-1;
11528           }
11529         }
11530         break;
11531       case 3:
11532         // Clear jump_out
11533         #ifdef __arm__
11534         if((expirep&2047)==0)
11535           do_clear_cache();
11536         #endif
11537         ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
11538         ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
11539         break;
11540     }
11541     expirep=(expirep+1)&65535;
11542   }
11543   return 0;
11544 }
11545
11546 // vim:shiftwidth=2:expandtab