libpcsxcore/new_dynarec/new_dynarec.c

   1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
   2  *   Mupen64plus - new_dynarec.c                                           *
   3  *   Copyright (C) 2009-2010 Ari64                                         *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.          *
  19  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
  20
  21 #include <stdlib.h>
  22 #include <stdint.h> //include for uint64_t
  23 #include <assert.h>
  24
  25 #include "emu_if.h" //emulator interface
  26
  27 #include <sys/mman.h>
  28
  29 #ifdef __i386__
  30 #include "assem_x86.h"
  31 #endif
  32 #ifdef __x86_64__
  33 #include "assem_x64.h"
  34 #endif
  35 #ifdef __arm__
  36 #include "assem_arm.h"
  37 #endif
  38
  39 #define MAXBLOCK 4096
  40 #define MAX_OUTPUT_BLOCK_SIZE 262144
  41 #define CLOCK_DIVIDER 2
  42
  43 struct regstat
  44 {
  45   signed char regmap_entry[HOST_REGS];
  46   signed char regmap[HOST_REGS];
  47   uint64_t was32;
  48   uint64_t is32;
  49   uint64_t wasdirty;
  50   uint64_t dirty;
  51   uint64_t u;
  52   uint64_t uu;
  53   u_int wasconst;
  54   u_int isconst;
  55   uint64_t constmap[HOST_REGS];
  56 };
  57
  58 struct ll_entry
  59 {
  60   u_int vaddr;
  61   u_int reg32;
  62   void *addr;
  63   struct ll_entry *next;
  64 };
  65
  66   u_int start;
  67   u_int *source;
  68   u_int pagelimit;
  69   char insn[MAXBLOCK][10];
  70   u_char itype[MAXBLOCK];
  71   u_char opcode[MAXBLOCK];
  72   u_char opcode2[MAXBLOCK];
  73   u_char bt[MAXBLOCK];
  74   u_char rs1[MAXBLOCK];
  75   u_char rs2[MAXBLOCK];
  76   u_char rt1[MAXBLOCK];
  77   u_char rt2[MAXBLOCK];
  78   u_char us1[MAXBLOCK];
  79   u_char us2[MAXBLOCK];
  80   u_char dep1[MAXBLOCK];
  81   u_char dep2[MAXBLOCK];
  82   u_char lt1[MAXBLOCK];
  83   int imm[MAXBLOCK];
  84   u_int ba[MAXBLOCK];
  85   char likely[MAXBLOCK];
  86   char is_ds[MAXBLOCK];
  87   uint64_t unneeded_reg[MAXBLOCK];
  88   uint64_t unneeded_reg_upper[MAXBLOCK];
  89   uint64_t branch_unneeded_reg[MAXBLOCK];
  90   uint64_t branch_unneeded_reg_upper[MAXBLOCK];
  91   uint64_t p32[MAXBLOCK];
  92   uint64_t pr32[MAXBLOCK];
  93   signed char regmap_pre[MAXBLOCK][HOST_REGS];
  94   signed char regmap[MAXBLOCK][HOST_REGS];
  95   signed char regmap_entry[MAXBLOCK][HOST_REGS];
  96   uint64_t constmap[MAXBLOCK][HOST_REGS];
  97   uint64_t known_value[HOST_REGS];
  98   u_int known_reg;
  99   struct regstat regs[MAXBLOCK];
 100   struct regstat branch_regs[MAXBLOCK];
 101   u_int needed_reg[MAXBLOCK];
 102   uint64_t requires_32bit[MAXBLOCK];
 103   u_int wont_dirty[MAXBLOCK];
 104   u_int will_dirty[MAXBLOCK];
 105   int ccadj[MAXBLOCK];
 106   int slen;
 107   u_int instr_addr[MAXBLOCK];
 108   u_int link_addr[MAXBLOCK][3];
 109   int linkcount;
 110   u_int stubs[MAXBLOCK*3][8];
 111   int stubcount;
 112   u_int literals[1024][2];
 113   int literalcount;
 114   int is_delayslot;
 115   int cop1_usable;
 116   u_char *out;
 117   struct ll_entry *jump_in[4096];
 118   struct ll_entry *jump_out[4096];
 119   struct ll_entry *jump_dirty[4096];
 120   u_int hash_table[65536][4]  __attribute__((aligned(16)));
 121   char shadow[1048576]  __attribute__((aligned(16)));
 122   void *copy;
 123   int expirep;
 124   u_int using_tlb;
 125   u_int stop_after_jal;
 126   extern u_char restore_candidate[512];
 127   extern int cycle_count;
 128
 129   /* registers that may be allocated */
 130   /* 1-31 gpr */
 131 #define HIREG 32 // hi
 132 #define LOREG 33 // lo
 133 #define FSREG 34 // FPU status (FCSR)
 134 #define CSREG 35 // Coprocessor status
 135 #define CCREG 36 // Cycle count
 136 #define INVCP 37 // Pointer to invalid_code
 137 #define TEMPREG 38
 138 #define FTEMP 38 // FPU/LDL/LDR temporary register
 139 #define PTEMP 39 // Prefetch temporary register
 140 #define TLREG 40 // TLB mapping offset
 141 #define RHASH 41 // Return address hash
 142 #define RHTBL 42 // Return address hash table address
 143 #define RTEMP 43 // JR/JALR address register
 144 #define MAXREG 43
 145 #define AGEN1 44 // Address generation temporary register
 146 #define AGEN2 45 // Address generation temporary register
 147 #define MGEN1 46 // Maptable address generation temporary register
 148 #define MGEN2 47 // Maptable address generation temporary register
 149 #define BTREG 48 // Branch target temporary register
 150
 151   /* instruction types */
 152 #define NOP 0     // No operation
 153 #define LOAD 1    // Load
 154 #define STORE 2   // Store
 155 #define LOADLR 3  // Unaligned load
 156 #define STORELR 4 // Unaligned store
 157 #define MOV 5     // Move
 158 #define ALU 6     // Arithmetic/logic
 159 #define MULTDIV 7 // Multiply/divide
 160 #define SHIFT 8   // Shift by register
 161 #define SHIFTIMM 9// Shift by immediate
 162 #define IMM16 10  // 16-bit immediate
 163 #define RJUMP 11  // Unconditional jump to register
 164 #define UJUMP 12  // Unconditional jump
 165 #define CJUMP 13  // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
 166 #define SJUMP 14  // Conditional branch (regimm format)
 167 #define COP0 15   // Coprocessor 0
 168 #define COP1 16   // Coprocessor 1
 169 #define C1LS 17   // Coprocessor 1 load/store
 170 #define FJUMP 18  // Conditional branch (floating point)
 171 #define FLOAT 19  // Floating point unit
 172 #define FCONV 20  // Convert integer to float
 173 #define FCOMP 21  // Floating point compare (sets FSREG)
 174 #define SYSCALL 22// SYSCALL
 175 #define OTHER 23  // Other
 176 #define SPAN 24   // Branch/delay slot spans 2 pages
 177 #define NI 25     // Not implemented
 178 #define HLECALL 26// PCSX fake opcodes for HLE
 179 #define COP2 27   // Coprocessor 2 move
 180 #define C2LS 28   // Coprocessor 2 load/store
 181 #define C2OP 29   // Coprocessor 2 operation
 182 #define INTCALL 30// Call interpreter to handle rare corner cases
 183
 184   /* stubs */
 185 #define CC_STUB 1
 186 #define FP_STUB 2
 187 #define LOADB_STUB 3
 188 #define LOADH_STUB 4
 189 #define LOADW_STUB 5
 190 #define LOADD_STUB 6
 191 #define LOADBU_STUB 7
 192 #define LOADHU_STUB 8
 193 #define STOREB_STUB 9
 194 #define STOREH_STUB 10
 195 #define STOREW_STUB 11
 196 #define STORED_STUB 12
 197 #define STORELR_STUB 13
 198 #define INVCODE_STUB 14
 199
 200   /* branch codes */
 201 #define TAKEN 1
 202 #define NOTTAKEN 2
 203 #define NULLDS 3
 204
 205 // asm linkage
 206 int new_recompile_block(int addr);
 207 void *get_addr_ht(u_int vaddr);
 208 void invalidate_block(u_int block);
 209 void invalidate_addr(u_int addr);
 210 void remove_hash(int vaddr);
 211 void jump_vaddr();
 212 void dyna_linker();
 213 void dyna_linker_ds();
 214 void verify_code();
 215 void verify_code_vm();
 216 void verify_code_ds();
 217 void cc_interrupt();
 218 void fp_exception();
 219 void fp_exception_ds();
 220 void jump_syscall();
 221 void jump_syscall_hle();
 222 void jump_eret();
 223 void jump_hlecall();
 224 void jump_intcall();
 225 void new_dyna_leave();
 226
 227 // TLB
 228 void TLBWI_new();
 229 void TLBWR_new();
 230 void read_nomem_new();
 231 void read_nomemb_new();
 232 void read_nomemh_new();
 233 void read_nomemd_new();
 234 void write_nomem_new();
 235 void write_nomemb_new();
 236 void write_nomemh_new();
 237 void write_nomemd_new();
 238 void write_rdram_new();
 239 void write_rdramb_new();
 240 void write_rdramh_new();
 241 void write_rdramd_new();
 242 extern u_int memory_map[1048576];
 243
 244 // Needed by assembler
 245 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
 246 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
 247 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
 248 void load_all_regs(signed char i_regmap[]);
 249 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
 250 void load_regs_entry(int t);
 251 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
 252
 253 int tracedebug=0;
 254
 255 //#define DEBUG_CYCLE_COUNT 1
 256
 257 void nullf() {}
 258 //#define assem_debug printf
 259 //#define inv_debug printf
 260 #define assem_debug nullf
 261 #define inv_debug nullf
 262
 263 static void tlb_hacks()
 264 {
 265 #ifndef DISABLE_TLB
 266   // Goldeneye hack
 267   if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
 268   {
 269     u_int addr;
 270     int n;
 271     switch (ROM_HEADER->Country_code&0xFF)
 272     {
 273       case 0x45: // U
 274         addr=0x34b30;
 275         break;
 276       case 0x4A: // J
 277         addr=0x34b70;
 278         break;
 279       case 0x50: // E
 280         addr=0x329f0;
 281         break;
 282       default:
 283         // Unknown country code
 284         addr=0;
 285         break;
 286     }
 287     u_int rom_addr=(u_int)rom;
 288     #ifdef ROM_COPY
 289     // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
 290     // in the lower 4G of memory to use this hack.  Copy it if necessary.
 291     if((void *)rom>(void *)0xffffffff) {
 292       munmap(ROM_COPY, 67108864);
 293       if(mmap(ROM_COPY, 12582912,
 294               PROT_READ | PROT_WRITE,
 295               MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
 296               -1, 0) <= 0) {printf("mmap() failed\n");}
 297       memcpy(ROM_COPY,rom,12582912);
 298       rom_addr=(u_int)ROM_COPY;
 299     }
 300     #endif
 301     if(addr) {
 302       for(n=0x7F000;n<0x80000;n++) {
 303         memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
 304       }
 305     }
 306   }
 307 #endif
 308 }
 309
 310 static u_int get_page(u_int vaddr)
 311 {
 312 #ifndef PCSX
 313   u_int page=(vaddr^0x80000000)>>12;
 314 #else
 315   u_int page=vaddr&~0xe0000000;
 316   if (page < 0x1000000)
 317     page &= ~0x0e00000; // RAM mirrors
 318   page>>=12;
 319 #endif
 320 #ifndef DISABLE_TLB
 321   if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
 322 #endif
 323   if(page>2048) page=2048+(page&2047);
 324   return page;
 325 }
 326
 327 static u_int get_vpage(u_int vaddr)
 328 {
 329   u_int vpage=(vaddr^0x80000000)>>12;
 330 #ifndef DISABLE_TLB
 331   if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
 332 #endif
 333   if(vpage>2048) vpage=2048+(vpage&2047);
 334   return vpage;
 335 }
 336
 337 // Get address from virtual address
 338 // This is called from the recompiled JR/JALR instructions
 339 void *get_addr(u_int vaddr)
 340 {
 341   u_int page=get_page(vaddr);
 342   u_int vpage=get_vpage(vaddr);
 343   struct ll_entry *head;
 344   //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
 345   head=jump_in[page];
 346   while(head!=NULL) {
 347     if(head->vaddr==vaddr&&head->reg32==0) {
 348   //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 349       int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 350       ht_bin[3]=ht_bin[1];
 351       ht_bin[2]=ht_bin[0];
 352       ht_bin[1]=(int)head->addr;
 353       ht_bin[0]=vaddr;
 354       return head->addr;
 355     }
 356     head=head->next;
 357   }
 358   head=jump_dirty[vpage];
 359   while(head!=NULL) {
 360     if(head->vaddr==vaddr&&head->reg32==0) {
 361       //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 362       // Don't restore blocks which are about to expire from the cache
 363       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 364       if(verify_dirty(head->addr)) {
 365         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
 366         invalid_code[vaddr>>12]=0;
 367         memory_map[vaddr>>12]|=0x40000000;
 368         if(vpage<2048) {
 369 #ifndef DISABLE_TLB
 370           if(tlb_LUT_r[vaddr>>12]) {
 371             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
 372             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
 373           }
 374 #endif
 375           restore_candidate[vpage>>3]|=1<<(vpage&7);
 376         }
 377         else restore_candidate[page>>3]|=1<<(page&7);
 378         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 379         if(ht_bin[0]==vaddr) {
 380           ht_bin[1]=(int)head->addr; // Replace existing entry
 381         }
 382         else
 383         {
 384           ht_bin[3]=ht_bin[1];
 385           ht_bin[2]=ht_bin[0];
 386           ht_bin[1]=(int)head->addr;
 387           ht_bin[0]=vaddr;
 388         }
 389         return head->addr;
 390       }
 391     }
 392     head=head->next;
 393   }
 394   //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
 395   int r=new_recompile_block(vaddr);
 396   if(r==0) return get_addr(vaddr);
 397   // Execute in unmapped page, generate pagefault execption
 398   Status|=2;
 399   Cause=(vaddr<<31)|0x8;
 400   EPC=(vaddr&1)?vaddr-5:vaddr;
 401   BadVAddr=(vaddr&~1);
 402   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
 403   EntryHi=BadVAddr&0xFFFFE000;
 404   return get_addr_ht(0x80000000);
 405 }
 406 // Look up address in hash table first
 407 void *get_addr_ht(u_int vaddr)
 408 {
 409   //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
 410   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 411   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
 412   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
 413   return get_addr(vaddr);
 414 }
 415
 416 void *get_addr_32(u_int vaddr,u_int flags)
 417 {
 418 #ifdef FORCE32
 419   return get_addr(vaddr);
 420 #else
 421   //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
 422   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 423   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
 424   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
 425   u_int page=get_page(vaddr);
 426   u_int vpage=get_vpage(vaddr);
 427   struct ll_entry *head;
 428   head=jump_in[page];
 429   while(head!=NULL) {
 430     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
 431       //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 432       if(head->reg32==0) {
 433         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 434         if(ht_bin[0]==-1) {
 435           ht_bin[1]=(int)head->addr;
 436           ht_bin[0]=vaddr;
 437         }else if(ht_bin[2]==-1) {
 438           ht_bin[3]=(int)head->addr;
 439           ht_bin[2]=vaddr;
 440         }
 441         //ht_bin[3]=ht_bin[1];
 442         //ht_bin[2]=ht_bin[0];
 443         //ht_bin[1]=(int)head->addr;
 444         //ht_bin[0]=vaddr;
 445       }
 446       return head->addr;
 447     }
 448     head=head->next;
 449   }
 450   head=jump_dirty[vpage];
 451   while(head!=NULL) {
 452     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
 453       //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 454       // Don't restore blocks which are about to expire from the cache
 455       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 456       if(verify_dirty(head->addr)) {
 457         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
 458         invalid_code[vaddr>>12]=0;
 459         memory_map[vaddr>>12]|=0x40000000;
 460         if(vpage<2048) {
 461 #ifndef DISABLE_TLB
 462           if(tlb_LUT_r[vaddr>>12]) {
 463             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
 464             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
 465           }
 466 #endif
 467           restore_candidate[vpage>>3]|=1<<(vpage&7);
 468         }
 469         else restore_candidate[page>>3]|=1<<(page&7);
 470         if(head->reg32==0) {
 471           int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 472           if(ht_bin[0]==-1) {
 473             ht_bin[1]=(int)head->addr;
 474             ht_bin[0]=vaddr;
 475           }else if(ht_bin[2]==-1) {
 476             ht_bin[3]=(int)head->addr;
 477             ht_bin[2]=vaddr;
 478           }
 479           //ht_bin[3]=ht_bin[1];
 480           //ht_bin[2]=ht_bin[0];
 481           //ht_bin[1]=(int)head->addr;
 482           //ht_bin[0]=vaddr;
 483         }
 484         return head->addr;
 485       }
 486     }
 487     head=head->next;
 488   }
 489   //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
 490   int r=new_recompile_block(vaddr);
 491   if(r==0) return get_addr(vaddr);
 492   // Execute in unmapped page, generate pagefault execption
 493   Status|=2;
 494   Cause=(vaddr<<31)|0x8;
 495   EPC=(vaddr&1)?vaddr-5:vaddr;
 496   BadVAddr=(vaddr&~1);
 497   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
 498   EntryHi=BadVAddr&0xFFFFE000;
 499   return get_addr_ht(0x80000000);
 500 #endif
 501 }
 502
 503 void clear_all_regs(signed char regmap[])
 504 {
 505   int hr;
 506   for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
 507 }
 508
 509 signed char get_reg(signed char regmap[],int r)
 510 {
 511   int hr;
 512   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
 513   return -1;
 514 }
 515
 516 // Find a register that is available for two consecutive cycles
 517 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
 518 {
 519   int hr;
 520   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
 521   return -1;
 522 }
 523
 524 int count_free_regs(signed char regmap[])
 525 {
 526   int count=0;
 527   int hr;
 528   for(hr=0;hr<HOST_REGS;hr++)
 529   {
 530     if(hr!=EXCLUDE_REG) {
 531       if(regmap[hr]<0) count++;
 532     }
 533   }
 534   return count;
 535 }
 536
 537 void dirty_reg(struct regstat *cur,signed char reg)
 538 {
 539   int hr;
 540   if(!reg) return;
 541   for (hr=0;hr<HOST_REGS;hr++) {
 542     if((cur->regmap[hr]&63)==reg) {
 543       cur->dirty|=1<<hr;
 544     }
 545   }
 546 }
 547
 548 // If we dirty the lower half of a 64 bit register which is now being
 549 // sign-extended, we need to dump the upper half.
 550 // Note: Do this only after completion of the instruction, because
 551 // some instructions may need to read the full 64-bit value even if
 552 // overwriting it (eg SLTI, DSRA32).
 553 static void flush_dirty_uppers(struct regstat *cur)
 554 {
 555   int hr,reg;
 556   for (hr=0;hr<HOST_REGS;hr++) {
 557     if((cur->dirty>>hr)&1) {
 558       reg=cur->regmap[hr];
 559       if(reg>=64)
 560         if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
 561     }
 562   }
 563 }
 564
 565 void set_const(struct regstat *cur,signed char reg,uint64_t value)
 566 {
 567   int hr;
 568   if(!reg) return;
 569   for (hr=0;hr<HOST_REGS;hr++) {
 570     if(cur->regmap[hr]==reg) {
 571       cur->isconst|=1<<hr;
 572       cur->constmap[hr]=value;
 573     }
 574     else if((cur->regmap[hr]^64)==reg) {
 575       cur->isconst|=1<<hr;
 576       cur->constmap[hr]=value>>32;
 577     }
 578   }
 579 }
 580
 581 void clear_const(struct regstat *cur,signed char reg)
 582 {
 583   int hr;
 584   if(!reg) return;
 585   for (hr=0;hr<HOST_REGS;hr++) {
 586     if((cur->regmap[hr]&63)==reg) {
 587       cur->isconst&=~(1<<hr);
 588     }
 589   }
 590 }
 591
 592 int is_const(struct regstat *cur,signed char reg)
 593 {
 594   int hr;
 595   if(!reg) return 1;
 596   for (hr=0;hr<HOST_REGS;hr++) {
 597     if((cur->regmap[hr]&63)==reg) {
 598       return (cur->isconst>>hr)&1;
 599     }
 600   }
 601   return 0;
 602 }
 603 uint64_t get_const(struct regstat *cur,signed char reg)
 604 {
 605   int hr;
 606   if(!reg) return 0;
 607   for (hr=0;hr<HOST_REGS;hr++) {
 608     if(cur->regmap[hr]==reg) {
 609       return cur->constmap[hr];
 610     }
 611   }
 612   printf("Unknown constant in r%d\n",reg);
 613   exit(1);
 614 }
 615
 616 // Least soon needed registers
 617 // Look at the next ten instructions and see which registers
 618 // will be used.  Try not to reallocate these.
 619 void lsn(u_char hsn[], int i, int *preferred_reg)
 620 {
 621   int j;
 622   int b=-1;
 623   for(j=0;j<9;j++)
 624   {
 625     if(i+j>=slen) {
 626       j=slen-i-1;
 627       break;
 628     }
 629     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 630     {
 631       // Don't go past an unconditonal jump
 632       j++;
 633       break;
 634     }
 635   }
 636   for(;j>=0;j--)
 637   {
 638     if(rs1[i+j]) hsn[rs1[i+j]]=j;
 639     if(rs2[i+j]) hsn[rs2[i+j]]=j;
 640     if(rt1[i+j]) hsn[rt1[i+j]]=j;
 641     if(rt2[i+j]) hsn[rt2[i+j]]=j;
 642     if(itype[i+j]==STORE || itype[i+j]==STORELR) {
 643       // Stores can allocate zero
 644       hsn[rs1[i+j]]=j;
 645       hsn[rs2[i+j]]=j;
 646     }
 647     // On some architectures stores need invc_ptr
 648     #if defined(HOST_IMM8)
 649     if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
 650       hsn[INVCP]=j;
 651     }
 652     #endif
 653     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 654     {
 655       hsn[CCREG]=j;
 656       b=j;
 657     }
 658   }
 659   if(b>=0)
 660   {
 661     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 662     {
 663       // Follow first branch
 664       int t=(ba[i+b]-start)>>2;
 665       j=7-b;if(t+j>=slen) j=slen-t-1;
 666       for(;j>=0;j--)
 667       {
 668         if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
 669         if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
 670         //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
 671         //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
 672       }
 673     }
 674     // TODO: preferred register based on backward branch
 675   }
 676   // Delay slot should preferably not overwrite branch conditions or cycle count
 677   if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
 678     if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
 679     if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
 680     hsn[CCREG]=1;
 681     // ...or hash tables
 682     hsn[RHASH]=1;
 683     hsn[RHTBL]=1;
 684   }
 685   // Coprocessor load/store needs FTEMP, even if not declared
 686   if(itype[i]==C1LS||itype[i]==C2LS) {
 687     hsn[FTEMP]=0;
 688   }
 689   // Load L/R also uses FTEMP as a temporary register
 690   if(itype[i]==LOADLR) {
 691     hsn[FTEMP]=0;
 692   }
 693   // Also SWL/SWR/SDL/SDR
 694   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
 695     hsn[FTEMP]=0;
 696   }
 697   // Don't remove the TLB registers either
 698   if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
 699     hsn[TLREG]=0;
 700   }
 701   // Don't remove the miniht registers
 702   if(itype[i]==UJUMP||itype[i]==RJUMP)
 703   {
 704     hsn[RHASH]=0;
 705     hsn[RHTBL]=0;
 706   }
 707 }
 708
 709 // We only want to allocate registers if we're going to use them again soon
 710 int needed_again(int r, int i)
 711 {
 712   int j;
 713   int b=-1;
 714   int rn=10;
 715   int hr;
 716   u_char hsn[MAXREG+1];
 717   int preferred_reg;
 718
 719   memset(hsn,10,sizeof(hsn));
 720   lsn(hsn,i,&preferred_reg);
 721
 722   if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
 723   {
 724     if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
 725       return 0; // Don't need any registers if exiting the block
 726   }
 727   for(j=0;j<9;j++)
 728   {
 729     if(i+j>=slen) {
 730       j=slen-i-1;
 731       break;
 732     }
 733     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 734     {
 735       // Don't go past an unconditonal jump
 736       j++;
 737       break;
 738     }
 739     if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
 740     {
 741       break;
 742     }
 743   }
 744   for(;j>=1;j--)
 745   {
 746     if(rs1[i+j]==r) rn=j;
 747     if(rs2[i+j]==r) rn=j;
 748     if((unneeded_reg[i+j]>>r)&1) rn=10;
 749     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 750     {
 751       b=j;
 752     }
 753   }
 754   /*
 755   if(b>=0)
 756   {
 757     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 758     {
 759       // Follow first branch
 760       int o=rn;
 761       int t=(ba[i+b]-start)>>2;
 762       j=7-b;if(t+j>=slen) j=slen-t-1;
 763       for(;j>=0;j--)
 764       {
 765         if(!((unneeded_reg[t+j]>>r)&1)) {
 766           if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 767           if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 768         }
 769         else rn=o;
 770       }
 771     }
 772   }*/
 773   for(hr=0;hr<HOST_REGS;hr++) {
 774     if(hr!=EXCLUDE_REG) {
 775       if(rn<hsn[hr]) return 1;
 776     }
 777   }
 778   return 0;
 779 }
 780
 781 // Try to match register allocations at the end of a loop with those
 782 // at the beginning
 783 int loop_reg(int i, int r, int hr)
 784 {
 785   int j,k;
 786   for(j=0;j<9;j++)
 787   {
 788     if(i+j>=slen) {
 789       j=slen-i-1;
 790       break;
 791     }
 792     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 793     {
 794       // Don't go past an unconditonal jump
 795       j++;
 796       break;
 797     }
 798   }
 799   k=0;
 800   if(i>0){
 801     if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
 802       k--;
 803   }
 804   for(;k<j;k++)
 805   {
 806     if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
 807     if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
 808     if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
 809     {
 810       if(ba[i+k]>=start && ba[i+k]<(start+i*4))
 811       {
 812         int t=(ba[i+k]-start)>>2;
 813         int reg=get_reg(regs[t].regmap_entry,r);
 814         if(reg>=0) return reg;
 815         //reg=get_reg(regs[t+1].regmap_entry,r);
 816         //if(reg>=0) return reg;
 817       }
 818     }
 819   }
 820   return hr;
 821 }
 822
 823
 824 // Allocate every register, preserving source/target regs
 825 void alloc_all(struct regstat *cur,int i)
 826 {
 827   int hr;
 828
 829   for(hr=0;hr<HOST_REGS;hr++) {
 830     if(hr!=EXCLUDE_REG) {
 831       if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
 832          ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
 833       {
 834         cur->regmap[hr]=-1;
 835         cur->dirty&=~(1<<hr);
 836       }
 837       // Don't need zeros
 838       if((cur->regmap[hr]&63)==0)
 839       {
 840         cur->regmap[hr]=-1;
 841         cur->dirty&=~(1<<hr);
 842       }
 843     }
 844   }
 845 }
 846
 847
 848 void div64(int64_t dividend,int64_t divisor)
 849 {
 850   lo=dividend/divisor;
 851   hi=dividend%divisor;
 852   //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
 853   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 854 }
 855 void divu64(uint64_t dividend,uint64_t divisor)
 856 {
 857   lo=dividend/divisor;
 858   hi=dividend%divisor;
 859   //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 860   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 861 }
 862
 863 void mult64(uint64_t m1,uint64_t m2)
 864 {
 865    unsigned long long int op1, op2, op3, op4;
 866    unsigned long long int result1, result2, result3, result4;
 867    unsigned long long int temp1, temp2, temp3, temp4;
 868    int sign = 0;
 869
 870    if (m1 < 0)
 871      {
 872     op2 = -m1;
 873     sign = 1 - sign;
 874      }
 875    else op2 = m1;
 876    if (m2 < 0)
 877      {
 878     op4 = -m2;
 879     sign = 1 - sign;
 880      }
 881    else op4 = m2;
 882
 883    op1 = op2 & 0xFFFFFFFF;
 884    op2 = (op2 >> 32) & 0xFFFFFFFF;
 885    op3 = op4 & 0xFFFFFFFF;
 886    op4 = (op4 >> 32) & 0xFFFFFFFF;
 887
 888    temp1 = op1 * op3;
 889    temp2 = (temp1 >> 32) + op1 * op4;
 890    temp3 = op2 * op3;
 891    temp4 = (temp3 >> 32) + op2 * op4;
 892
 893    result1 = temp1 & 0xFFFFFFFF;
 894    result2 = temp2 + (temp3 & 0xFFFFFFFF);
 895    result3 = (result2 >> 32) + temp4;
 896    result4 = (result3 >> 32);
 897
 898    lo = result1 | (result2 << 32);
 899    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
 900    if (sign)
 901      {
 902     hi = ~hi;
 903     if (!lo) hi++;
 904     else lo = ~lo + 1;
 905      }
 906 }
 907
 908 void multu64(uint64_t m1,uint64_t m2)
 909 {
 910    unsigned long long int op1, op2, op3, op4;
 911    unsigned long long int result1, result2, result3, result4;
 912    unsigned long long int temp1, temp2, temp3, temp4;
 913
 914    op1 = m1 & 0xFFFFFFFF;
 915    op2 = (m1 >> 32) & 0xFFFFFFFF;
 916    op3 = m2 & 0xFFFFFFFF;
 917    op4 = (m2 >> 32) & 0xFFFFFFFF;
 918
 919    temp1 = op1 * op3;
 920    temp2 = (temp1 >> 32) + op1 * op4;
 921    temp3 = op2 * op3;
 922    temp4 = (temp3 >> 32) + op2 * op4;
 923
 924    result1 = temp1 & 0xFFFFFFFF;
 925    result2 = temp2 + (temp3 & 0xFFFFFFFF);
 926    result3 = (result2 >> 32) + temp4;
 927    result4 = (result3 >> 32);
 928
 929    lo = result1 | (result2 << 32);
 930    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
 931
 932   //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 933   //                                      ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 934 }
 935
 936 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
 937 {
 938   if(bits) {
 939     original<<=64-bits;
 940     original>>=64-bits;
 941     loaded<<=bits;
 942     original|=loaded;
 943   }
 944   else original=loaded;
 945   return original;
 946 }
 947 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
 948 {
 949   if(bits^56) {
 950     original>>=64-(bits^56);
 951     original<<=64-(bits^56);
 952     loaded>>=bits^56;
 953     original|=loaded;
 954   }
 955   else original=loaded;
 956   return original;
 957 }
 958
 959 #ifdef __i386__
 960 #include "assem_x86.c"
 961 #endif
 962 #ifdef __x86_64__
 963 #include "assem_x64.c"
 964 #endif
 965 #ifdef __arm__
 966 #include "assem_arm.c"
 967 #endif
 968
 969 // Add virtual address mapping to linked list
 970 void ll_add(struct ll_entry **head,int vaddr,void *addr)
 971 {
 972   struct ll_entry *new_entry;
 973   new_entry=malloc(sizeof(struct ll_entry));
 974   assert(new_entry!=NULL);
 975   new_entry->vaddr=vaddr;
 976   new_entry->reg32=0;
 977   new_entry->addr=addr;
 978   new_entry->next=*head;
 979   *head=new_entry;
 980 }
 981
 982 // Add virtual address mapping for 32-bit compiled block
 983 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
 984 {
 985   ll_add(head,vaddr,addr);
 986 #ifndef FORCE32
 987   (*head)->reg32=reg32;
 988 #endif
 989 }
 990
 991 // Check if an address is already compiled
 992 // but don't return addresses which are about to expire from the cache
 993 void *check_addr(u_int vaddr)
 994 {
 995   u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 996   if(ht_bin[0]==vaddr) {
 997     if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 998       if(isclean(ht_bin[1])) return (void *)ht_bin[1];
 999   }
1000   if(ht_bin[2]==vaddr) {
1001     if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1002       if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1003   }
1004   u_int page=get_page(vaddr);
1005   struct ll_entry *head;
1006   head=jump_in[page];
1007   while(head!=NULL) {
1008     if(head->vaddr==vaddr&&head->reg32==0) {
1009       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1010         // Update existing entry with current address
1011         if(ht_bin[0]==vaddr) {
1012           ht_bin[1]=(int)head->addr;
1013           return head->addr;
1014         }
1015         if(ht_bin[2]==vaddr) {
1016           ht_bin[3]=(int)head->addr;
1017           return head->addr;
1018         }
1019         // Insert into hash table with low priority.
1020         // Don't evict existing entries, as they are probably
1021         // addresses that are being accessed frequently.
1022         if(ht_bin[0]==-1) {
1023           ht_bin[1]=(int)head->addr;
1024           ht_bin[0]=vaddr;
1025         }else if(ht_bin[2]==-1) {
1026           ht_bin[3]=(int)head->addr;
1027           ht_bin[2]=vaddr;
1028         }
1029         return head->addr;
1030       }
1031     }
1032     head=head->next;
1033   }
1034   return 0;
1035 }
1036
1037 void remove_hash(int vaddr)
1038 {
1039   //printf("remove hash: %x\n",vaddr);
1040   int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1041   if(ht_bin[2]==vaddr) {
1042     ht_bin[2]=ht_bin[3]=-1;
1043   }
1044   if(ht_bin[0]==vaddr) {
1045     ht_bin[0]=ht_bin[2];
1046     ht_bin[1]=ht_bin[3];
1047     ht_bin[2]=ht_bin[3]=-1;
1048   }
1049 }
1050
1051 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1052 {
1053   struct ll_entry *next;
1054   while(*head) {
1055     if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1056        ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1057     {
1058       inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1059       remove_hash((*head)->vaddr);
1060       next=(*head)->next;
1061       free(*head);
1062       *head=next;
1063     }
1064     else
1065     {
1066       head=&((*head)->next);
1067     }
1068   }
1069 }
1070
1071 // Remove all entries from linked list
1072 void ll_clear(struct ll_entry **head)
1073 {
1074   struct ll_entry *cur;
1075   struct ll_entry *next;
1076   if(cur=*head) {
1077     *head=0;
1078     while(cur) {
1079       next=cur->next;
1080       free(cur);
1081       cur=next;
1082     }
1083   }
1084 }
1085
1086 // Dereference the pointers and remove if it matches
1087 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1088 {
1089   u_int old_host_addr=0;
1090   while(head) {
1091     int ptr=get_pointer(head->addr);
1092     inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1093     if(((ptr>>shift)==(addr>>shift)) ||
1094        (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1095     {
1096       inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1097       u_int host_addr=(u_int)kill_pointer(head->addr);
1098
1099       if((host_addr>>12)!=(old_host_addr>>12)) {
1100         #ifdef __arm__
1101         __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1102         #endif
1103         old_host_addr=host_addr;
1104       }
1105     }
1106     head=head->next;
1107   }
1108   #ifdef __arm__
1109   if (old_host_addr)
1110     __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1111   #endif
1112 }
1113
1114 // This is called when we write to a compiled block (see do_invstub)
1115 void invalidate_page(u_int page)
1116 {
1117   struct ll_entry *head;
1118   struct ll_entry *next;
1119   u_int old_host_addr=0;
1120   head=jump_in[page];
1121   jump_in[page]=0;
1122   while(head!=NULL) {
1123     inv_debug("INVALIDATE: %x\n",head->vaddr);
1124     remove_hash(head->vaddr);
1125     next=head->next;
1126     free(head);
1127     head=next;
1128   }
1129   head=jump_out[page];
1130   jump_out[page]=0;
1131   while(head!=NULL) {
1132     inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1133     u_int host_addr=(u_int)kill_pointer(head->addr);
1134
1135     if((host_addr>>12)!=(old_host_addr>>12)) {
1136       #ifdef __arm__
1137       __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1138       #endif
1139       old_host_addr=host_addr;
1140     }
1141     next=head->next;
1142     free(head);
1143     head=next;
1144   }
1145   #ifdef __arm__
1146   if (old_host_addr)
1147     __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1148   #endif
1149 }
1150 void invalidate_block(u_int block)
1151 {
1152   u_int page=get_page(block<<12);
1153   u_int vpage=get_vpage(block<<12);
1154   inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1155   //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1156   u_int first,last;
1157   first=last=page;
1158   struct ll_entry *head;
1159   head=jump_dirty[vpage];
1160   //printf("page=%d vpage=%d\n",page,vpage);
1161   while(head!=NULL) {
1162     u_int start,end;
1163     if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1164       get_bounds((int)head->addr,&start,&end);
1165       //printf("start: %x end: %x\n",start,end);
1166       if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
1167         if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1168           if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1169           if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1170         }
1171       }
1172 #ifndef DISABLE_TLB
1173       if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1174         if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1175           if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1176           if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1177         }
1178       }
1179 #endif
1180     }
1181     head=head->next;
1182   }
1183   //printf("first=%d last=%d\n",first,last);
1184   invalidate_page(page);
1185   assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1186   assert(last<page+5);
1187   // Invalidate the adjacent pages if a block crosses a 4K boundary
1188   while(first<page) {
1189     invalidate_page(first);
1190     first++;
1191   }
1192   for(first=page+1;first<last;first++) {
1193     invalidate_page(first);
1194   }
1195
1196   // Don't trap writes
1197   invalid_code[block]=1;
1198 #ifndef DISABLE_TLB
1199   // If there is a valid TLB entry for this page, remove write protect
1200   if(tlb_LUT_w[block]) {
1201     assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1202     // CHECK: Is this right?
1203     memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1204     u_int real_block=tlb_LUT_w[block]>>12;
1205     invalid_code[real_block]=1;
1206     if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1207   }
1208   else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1209 #endif
1210
1211   #ifdef USE_MINI_HT
1212   memset(mini_ht,-1,sizeof(mini_ht));
1213   #endif
1214 }
1215 void invalidate_addr(u_int addr)
1216 {
1217   invalidate_block(addr>>12);
1218 }
1219 void invalidate_all_pages()
1220 {
1221   u_int page,n;
1222   for(page=0;page<4096;page++)
1223     invalidate_page(page);
1224   for(page=0;page<1048576;page++)
1225     if(!invalid_code[page]) {
1226       restore_candidate[(page&2047)>>3]|=1<<(page&7);
1227       restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1228     }
1229   #ifdef __arm__
1230   __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1231   #endif
1232   #ifdef USE_MINI_HT
1233   memset(mini_ht,-1,sizeof(mini_ht));
1234   #endif
1235   #ifndef DISABLE_TLB
1236   // TLB
1237   for(page=0;page<0x100000;page++) {
1238     if(tlb_LUT_r[page]) {
1239       memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1240       if(!tlb_LUT_w[page]||!invalid_code[page])
1241         memory_map[page]|=0x40000000; // Write protect
1242     }
1243     else memory_map[page]=-1;
1244     if(page==0x80000) page=0xC0000;
1245   }
1246   tlb_hacks();
1247   #endif
1248 }
1249
1250 // Add an entry to jump_out after making a link
1251 void add_link(u_int vaddr,void *src)
1252 {
1253   u_int page=get_page(vaddr);
1254   inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1255   ll_add(jump_out+page,vaddr,src);
1256   //int ptr=get_pointer(src);
1257   //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1258 }
1259
1260 // If a code block was found to be unmodified (bit was set in
1261 // restore_candidate) and it remains unmodified (bit is clear
1262 // in invalid_code) then move the entries for that 4K page from
1263 // the dirty list to the clean list.
1264 void clean_blocks(u_int page)
1265 {
1266   struct ll_entry *head;
1267   inv_debug("INV: clean_blocks page=%d\n",page);
1268   head=jump_dirty[page];
1269   while(head!=NULL) {
1270     if(!invalid_code[head->vaddr>>12]) {
1271       // Don't restore blocks which are about to expire from the cache
1272       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1273         u_int start,end;
1274         if(verify_dirty((int)head->addr)) {
1275           //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1276           u_int i;
1277           u_int inv=0;
1278           get_bounds((int)head->addr,&start,&end);
1279           if(start-(u_int)rdram<RAM_SIZE) {
1280             for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1281               inv|=invalid_code[i];
1282             }
1283           }
1284           if((signed int)head->vaddr>=(signed int)0xC0000000) {
1285             u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1286             //printf("addr=%x start=%x end=%x\n",addr,start,end);
1287             if(addr<start||addr>=end) inv=1;
1288           }
1289           else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1290             inv=1;
1291           }
1292           if(!inv) {
1293             void * clean_addr=(void *)get_clean_addr((int)head->addr);
1294             if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1295               u_int ppage=page;
1296 #ifndef DISABLE_TLB
1297               if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1298 #endif
1299               inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1300               //printf("page=%x, addr=%x\n",page,head->vaddr);
1301               //assert(head->vaddr>>12==(page|0x80000));
1302               ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1303               int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1304               if(!head->reg32) {
1305                 if(ht_bin[0]==head->vaddr) {
1306                   ht_bin[1]=(int)clean_addr; // Replace existing entry
1307                 }
1308                 if(ht_bin[2]==head->vaddr) {
1309                   ht_bin[3]=(int)clean_addr; // Replace existing entry
1310                 }
1311               }
1312             }
1313           }
1314         }
1315       }
1316     }
1317     head=head->next;
1318   }
1319 }
1320
1321
1322 void mov_alloc(struct regstat *current,int i)
1323 {
1324   // Note: Don't need to actually alloc the source registers
1325   if((~current->is32>>rs1[i])&1) {
1326     //alloc_reg64(current,i,rs1[i]);
1327     alloc_reg64(current,i,rt1[i]);
1328     current->is32&=~(1LL<<rt1[i]);
1329   } else {
1330     //alloc_reg(current,i,rs1[i]);
1331     alloc_reg(current,i,rt1[i]);
1332     current->is32|=(1LL<<rt1[i]);
1333   }
1334   clear_const(current,rs1[i]);
1335   clear_const(current,rt1[i]);
1336   dirty_reg(current,rt1[i]);
1337 }
1338
1339 void shiftimm_alloc(struct regstat *current,int i)
1340 {
1341   clear_const(current,rs1[i]);
1342   clear_const(current,rt1[i]);
1343   if(opcode2[i]<=0x3) // SLL/SRL/SRA
1344   {
1345     if(rt1[i]) {
1346       if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1347       else lt1[i]=rs1[i];
1348       alloc_reg(current,i,rt1[i]);
1349       current->is32|=1LL<<rt1[i];
1350       dirty_reg(current,rt1[i]);
1351     }
1352   }
1353   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1354   {
1355     if(rt1[i]) {
1356       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1357       alloc_reg64(current,i,rt1[i]);
1358       current->is32&=~(1LL<<rt1[i]);
1359       dirty_reg(current,rt1[i]);
1360     }
1361   }
1362   if(opcode2[i]==0x3c) // DSLL32
1363   {
1364     if(rt1[i]) {
1365       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1366       alloc_reg64(current,i,rt1[i]);
1367       current->is32&=~(1LL<<rt1[i]);
1368       dirty_reg(current,rt1[i]);
1369     }
1370   }
1371   if(opcode2[i]==0x3e) // DSRL32
1372   {
1373     if(rt1[i]) {
1374       alloc_reg64(current,i,rs1[i]);
1375       if(imm[i]==32) {
1376         alloc_reg64(current,i,rt1[i]);
1377         current->is32&=~(1LL<<rt1[i]);
1378       } else {
1379         alloc_reg(current,i,rt1[i]);
1380         current->is32|=1LL<<rt1[i];
1381       }
1382       dirty_reg(current,rt1[i]);
1383     }
1384   }
1385   if(opcode2[i]==0x3f) // DSRA32
1386   {
1387     if(rt1[i]) {
1388       alloc_reg64(current,i,rs1[i]);
1389       alloc_reg(current,i,rt1[i]);
1390       current->is32|=1LL<<rt1[i];
1391       dirty_reg(current,rt1[i]);
1392     }
1393   }
1394 }
1395
1396 void shift_alloc(struct regstat *current,int i)
1397 {
1398   if(rt1[i]) {
1399     if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1400     {
1401       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1402       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1403       alloc_reg(current,i,rt1[i]);
1404       if(rt1[i]==rs2[i]) alloc_reg_temp(current,i,-1);
1405       current->is32|=1LL<<rt1[i];
1406     } else { // DSLLV/DSRLV/DSRAV
1407       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1408       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1409       alloc_reg64(current,i,rt1[i]);
1410       current->is32&=~(1LL<<rt1[i]);
1411       if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1412         alloc_reg_temp(current,i,-1);
1413     }
1414     clear_const(current,rs1[i]);
1415     clear_const(current,rs2[i]);
1416     clear_const(current,rt1[i]);
1417     dirty_reg(current,rt1[i]);
1418   }
1419 }
1420
1421 void alu_alloc(struct regstat *current,int i)
1422 {
1423   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1424     if(rt1[i]) {
1425       if(rs1[i]&&rs2[i]) {
1426         alloc_reg(current,i,rs1[i]);
1427         alloc_reg(current,i,rs2[i]);
1428       }
1429       else {
1430         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1431         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1432       }
1433       alloc_reg(current,i,rt1[i]);
1434     }
1435     current->is32|=1LL<<rt1[i];
1436   }
1437   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1438     if(rt1[i]) {
1439       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1440       {
1441         alloc_reg64(current,i,rs1[i]);
1442         alloc_reg64(current,i,rs2[i]);
1443         alloc_reg(current,i,rt1[i]);
1444       } else {
1445         alloc_reg(current,i,rs1[i]);
1446         alloc_reg(current,i,rs2[i]);
1447         alloc_reg(current,i,rt1[i]);
1448       }
1449     }
1450     current->is32|=1LL<<rt1[i];
1451   }
1452   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1453     if(rt1[i]) {
1454       if(rs1[i]&&rs2[i]) {
1455         alloc_reg(current,i,rs1[i]);
1456         alloc_reg(current,i,rs2[i]);
1457       }
1458       else
1459       {
1460         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1461         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1462       }
1463       alloc_reg(current,i,rt1[i]);
1464       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1465       {
1466         if(!((current->uu>>rt1[i])&1)) {
1467           alloc_reg64(current,i,rt1[i]);
1468         }
1469         if(get_reg(current->regmap,rt1[i]|64)>=0) {
1470           if(rs1[i]&&rs2[i]) {
1471             alloc_reg64(current,i,rs1[i]);
1472             alloc_reg64(current,i,rs2[i]);
1473           }
1474           else
1475           {
1476             // Is is really worth it to keep 64-bit values in registers?
1477             #ifdef NATIVE_64BIT
1478             if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1479             if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1480             #endif
1481           }
1482         }
1483         current->is32&=~(1LL<<rt1[i]);
1484       } else {
1485         current->is32|=1LL<<rt1[i];
1486       }
1487     }
1488   }
1489   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1490     if(rt1[i]) {
1491       if(rs1[i]&&rs2[i]) {
1492         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1493           alloc_reg64(current,i,rs1[i]);
1494           alloc_reg64(current,i,rs2[i]);
1495           alloc_reg64(current,i,rt1[i]);
1496         } else {
1497           alloc_reg(current,i,rs1[i]);
1498           alloc_reg(current,i,rs2[i]);
1499           alloc_reg(current,i,rt1[i]);
1500         }
1501       }
1502       else {
1503         alloc_reg(current,i,rt1[i]);
1504         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1505           // DADD used as move, or zeroing
1506           // If we have a 64-bit source, then make the target 64 bits too
1507           if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1508             if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1509             alloc_reg64(current,i,rt1[i]);
1510           } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1511             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1512             alloc_reg64(current,i,rt1[i]);
1513           }
1514           if(opcode2[i]>=0x2e&&rs2[i]) {
1515             // DSUB used as negation - 64-bit result
1516             // If we have a 32-bit register, extend it to 64 bits
1517             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1518             alloc_reg64(current,i,rt1[i]);
1519           }
1520         }
1521       }
1522       if(rs1[i]&&rs2[i]) {
1523         current->is32&=~(1LL<<rt1[i]);
1524       } else if(rs1[i]) {
1525         current->is32&=~(1LL<<rt1[i]);
1526         if((current->is32>>rs1[i])&1)
1527           current->is32|=1LL<<rt1[i];
1528       } else if(rs2[i]) {
1529         current->is32&=~(1LL<<rt1[i]);
1530         if((current->is32>>rs2[i])&1)
1531           current->is32|=1LL<<rt1[i];
1532       } else {
1533         current->is32|=1LL<<rt1[i];
1534       }
1535     }
1536   }
1537   clear_const(current,rs1[i]);
1538   clear_const(current,rs2[i]);
1539   clear_const(current,rt1[i]);
1540   dirty_reg(current,rt1[i]);
1541 }
1542
1543 void imm16_alloc(struct regstat *current,int i)
1544 {
1545   if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1546   else lt1[i]=rs1[i];
1547   if(rt1[i]) alloc_reg(current,i,rt1[i]);
1548   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1549     current->is32&=~(1LL<<rt1[i]);
1550     if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1551       // TODO: Could preserve the 32-bit flag if the immediate is zero
1552       alloc_reg64(current,i,rt1[i]);
1553       alloc_reg64(current,i,rs1[i]);
1554     }
1555     clear_const(current,rs1[i]);
1556     clear_const(current,rt1[i]);
1557   }
1558   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1559     if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1560     current->is32|=1LL<<rt1[i];
1561     clear_const(current,rs1[i]);
1562     clear_const(current,rt1[i]);
1563   }
1564   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1565     if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1566       if(rs1[i]!=rt1[i]) {
1567         if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1568         alloc_reg64(current,i,rt1[i]);
1569         current->is32&=~(1LL<<rt1[i]);
1570       }
1571     }
1572     else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1573     if(is_const(current,rs1[i])) {
1574       int v=get_const(current,rs1[i]);
1575       if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1576       if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1577       if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1578     }
1579     else clear_const(current,rt1[i]);
1580   }
1581   else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1582     if(is_const(current,rs1[i])) {
1583       int v=get_const(current,rs1[i]);
1584       set_const(current,rt1[i],v+imm[i]);
1585     }
1586     else clear_const(current,rt1[i]);
1587     current->is32|=1LL<<rt1[i];
1588   }
1589   else {
1590     set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1591     current->is32|=1LL<<rt1[i];
1592   }
1593   dirty_reg(current,rt1[i]);
1594 }
1595
1596 void load_alloc(struct regstat *current,int i)
1597 {
1598   clear_const(current,rt1[i]);
1599   //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1600   if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1601   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1602   if(rt1[i]) {
1603     alloc_reg(current,i,rt1[i]);
1604     if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1605     {
1606       current->is32&=~(1LL<<rt1[i]);
1607       alloc_reg64(current,i,rt1[i]);
1608     }
1609     else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1610     {
1611       current->is32&=~(1LL<<rt1[i]);
1612       alloc_reg64(current,i,rt1[i]);
1613       alloc_all(current,i);
1614       alloc_reg64(current,i,FTEMP);
1615     }
1616     else current->is32|=1LL<<rt1[i];
1617     dirty_reg(current,rt1[i]);
1618     // If using TLB, need a register for pointer to the mapping table
1619     if(using_tlb) alloc_reg(current,i,TLREG);
1620     // LWL/LWR need a temporary register for the old value
1621     if(opcode[i]==0x22||opcode[i]==0x26)
1622     {
1623       alloc_reg(current,i,FTEMP);
1624       alloc_reg_temp(current,i,-1);
1625     }
1626   }
1627   else
1628   {
1629     // Load to r0 (dummy load)
1630     // but we still need a register to calculate the address
1631     alloc_reg_temp(current,i,-1);
1632   }
1633 }
1634
1635 void store_alloc(struct regstat *current,int i)
1636 {
1637   clear_const(current,rs2[i]);
1638   if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1639   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1640   alloc_reg(current,i,rs2[i]);
1641   if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1642     alloc_reg64(current,i,rs2[i]);
1643     if(rs2[i]) alloc_reg(current,i,FTEMP);
1644   }
1645   // If using TLB, need a register for pointer to the mapping table
1646   if(using_tlb) alloc_reg(current,i,TLREG);
1647   #if defined(HOST_IMM8)
1648   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1649   else alloc_reg(current,i,INVCP);
1650   #endif
1651   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1652     alloc_reg(current,i,FTEMP);
1653   }
1654   // We need a temporary register for address generation
1655   alloc_reg_temp(current,i,-1);
1656 }
1657
1658 void c1ls_alloc(struct regstat *current,int i)
1659 {
1660   //clear_const(current,rs1[i]); // FIXME
1661   clear_const(current,rt1[i]);
1662   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1663   alloc_reg(current,i,CSREG); // Status
1664   alloc_reg(current,i,FTEMP);
1665   if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1666     alloc_reg64(current,i,FTEMP);
1667   }
1668   // If using TLB, need a register for pointer to the mapping table
1669   if(using_tlb) alloc_reg(current,i,TLREG);
1670   #if defined(HOST_IMM8)
1671   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1672   else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1673     alloc_reg(current,i,INVCP);
1674   #endif
1675   // We need a temporary register for address generation
1676   alloc_reg_temp(current,i,-1);
1677 }
1678
1679 void c2ls_alloc(struct regstat *current,int i)
1680 {
1681   clear_const(current,rt1[i]);
1682   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1683   alloc_reg(current,i,FTEMP);
1684   // If using TLB, need a register for pointer to the mapping table
1685   if(using_tlb) alloc_reg(current,i,TLREG);
1686   #if defined(HOST_IMM8)
1687   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1688   else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1689     alloc_reg(current,i,INVCP);
1690   #endif
1691   // We need a temporary register for address generation
1692   alloc_reg_temp(current,i,-1);
1693 }
1694
1695 #ifndef multdiv_alloc
1696 void multdiv_alloc(struct regstat *current,int i)
1697 {
1698   //  case 0x18: MULT
1699   //  case 0x19: MULTU
1700   //  case 0x1A: DIV
1701   //  case 0x1B: DIVU
1702   //  case 0x1C: DMULT
1703   //  case 0x1D: DMULTU
1704   //  case 0x1E: DDIV
1705   //  case 0x1F: DDIVU
1706   clear_const(current,rs1[i]);
1707   clear_const(current,rs2[i]);
1708   if(rs1[i]&&rs2[i])
1709   {
1710     if((opcode2[i]&4)==0) // 32-bit
1711     {
1712       current->u&=~(1LL<<HIREG);
1713       current->u&=~(1LL<<LOREG);
1714       alloc_reg(current,i,HIREG);
1715       alloc_reg(current,i,LOREG);
1716       alloc_reg(current,i,rs1[i]);
1717       alloc_reg(current,i,rs2[i]);
1718       current->is32|=1LL<<HIREG;
1719       current->is32|=1LL<<LOREG;
1720       dirty_reg(current,HIREG);
1721       dirty_reg(current,LOREG);
1722     }
1723     else // 64-bit
1724     {
1725       current->u&=~(1LL<<HIREG);
1726       current->u&=~(1LL<<LOREG);
1727       current->uu&=~(1LL<<HIREG);
1728       current->uu&=~(1LL<<LOREG);
1729       alloc_reg64(current,i,HIREG);
1730       //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1731       alloc_reg64(current,i,rs1[i]);
1732       alloc_reg64(current,i,rs2[i]);
1733       alloc_all(current,i);
1734       current->is32&=~(1LL<<HIREG);
1735       current->is32&=~(1LL<<LOREG);
1736       dirty_reg(current,HIREG);
1737       dirty_reg(current,LOREG);
1738     }
1739   }
1740   else
1741   {
1742     // Multiply by zero is zero.
1743     // MIPS does not have a divide by zero exception.
1744     // The result is undefined, we return zero.
1745     alloc_reg(current,i,HIREG);
1746     alloc_reg(current,i,LOREG);
1747     current->is32|=1LL<<HIREG;
1748     current->is32|=1LL<<LOREG;
1749     dirty_reg(current,HIREG);
1750     dirty_reg(current,LOREG);
1751   }
1752 }
1753 #endif
1754
1755 void cop0_alloc(struct regstat *current,int i)
1756 {
1757   if(opcode2[i]==0) // MFC0
1758   {
1759     if(rt1[i]) {
1760       clear_const(current,rt1[i]);
1761       alloc_all(current,i);
1762       alloc_reg(current,i,rt1[i]);
1763       current->is32|=1LL<<rt1[i];
1764       dirty_reg(current,rt1[i]);
1765     }
1766   }
1767   else if(opcode2[i]==4) // MTC0
1768   {
1769     if(rs1[i]){
1770       clear_const(current,rs1[i]);
1771       alloc_reg(current,i,rs1[i]);
1772       alloc_all(current,i);
1773     }
1774     else {
1775       alloc_all(current,i); // FIXME: Keep r0
1776       current->u&=~1LL;
1777       alloc_reg(current,i,0);
1778     }
1779   }
1780   else
1781   {
1782     // TLBR/TLBWI/TLBWR/TLBP/ERET
1783     assert(opcode2[i]==0x10);
1784     alloc_all(current,i);
1785   }
1786 }
1787
1788 void cop1_alloc(struct regstat *current,int i)
1789 {
1790   alloc_reg(current,i,CSREG); // Load status
1791   if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1792   {
1793     if(rt1[i]){
1794       clear_const(current,rt1[i]);
1795       if(opcode2[i]==1) {
1796         alloc_reg64(current,i,rt1[i]); // DMFC1
1797         current->is32&=~(1LL<<rt1[i]);
1798       }else{
1799         alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1800         current->is32|=1LL<<rt1[i];
1801       }
1802       dirty_reg(current,rt1[i]);
1803     }
1804     alloc_reg_temp(current,i,-1);
1805   }
1806   else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1807   {
1808     if(rs1[i]){
1809       clear_const(current,rs1[i]);
1810       if(opcode2[i]==5)
1811         alloc_reg64(current,i,rs1[i]); // DMTC1
1812       else
1813         alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1814       alloc_reg_temp(current,i,-1);
1815     }
1816     else {
1817       current->u&=~1LL;
1818       alloc_reg(current,i,0);
1819       alloc_reg_temp(current,i,-1);
1820     }
1821   }
1822 }
1823 void fconv_alloc(struct regstat *current,int i)
1824 {
1825   alloc_reg(current,i,CSREG); // Load status
1826   alloc_reg_temp(current,i,-1);
1827 }
1828 void float_alloc(struct regstat *current,int i)
1829 {
1830   alloc_reg(current,i,CSREG); // Load status
1831   alloc_reg_temp(current,i,-1);
1832 }
1833 void c2op_alloc(struct regstat *current,int i)
1834 {
1835   alloc_reg_temp(current,i,-1);
1836 }
1837 void fcomp_alloc(struct regstat *current,int i)
1838 {
1839   alloc_reg(current,i,CSREG); // Load status
1840   alloc_reg(current,i,FSREG); // Load flags
1841   dirty_reg(current,FSREG); // Flag will be modified
1842   alloc_reg_temp(current,i,-1);
1843 }
1844
1845 void syscall_alloc(struct regstat *current,int i)
1846 {
1847   alloc_cc(current,i);
1848   dirty_reg(current,CCREG);
1849   alloc_all(current,i);
1850   current->isconst=0;
1851 }
1852
1853 void delayslot_alloc(struct regstat *current,int i)
1854 {
1855   switch(itype[i]) {
1856     case UJUMP:
1857     case CJUMP:
1858     case SJUMP:
1859     case RJUMP:
1860     case FJUMP:
1861     case SYSCALL:
1862     case HLECALL:
1863     case SPAN:
1864       assem_debug("jump in the delay slot.  this shouldn't happen.\n");//exit(1);
1865       printf("Disabled speculative precompilation\n");
1866       stop_after_jal=1;
1867       break;
1868     case IMM16:
1869       imm16_alloc(current,i);
1870       break;
1871     case LOAD:
1872     case LOADLR:
1873       load_alloc(current,i);
1874       break;
1875     case STORE:
1876     case STORELR:
1877       store_alloc(current,i);
1878       break;
1879     case ALU:
1880       alu_alloc(current,i);
1881       break;
1882     case SHIFT:
1883       shift_alloc(current,i);
1884       break;
1885     case MULTDIV:
1886       multdiv_alloc(current,i);
1887       break;
1888     case SHIFTIMM:
1889       shiftimm_alloc(current,i);
1890       break;
1891     case MOV:
1892       mov_alloc(current,i);
1893       break;
1894     case COP0:
1895       cop0_alloc(current,i);
1896       break;
1897     case COP1:
1898     case COP2:
1899       cop1_alloc(current,i);
1900       break;
1901     case C1LS:
1902       c1ls_alloc(current,i);
1903       break;
1904     case C2LS:
1905       c2ls_alloc(current,i);
1906       break;
1907     case FCONV:
1908       fconv_alloc(current,i);
1909       break;
1910     case FLOAT:
1911       float_alloc(current,i);
1912       break;
1913     case FCOMP:
1914       fcomp_alloc(current,i);
1915       break;
1916     case C2OP:
1917       c2op_alloc(current,i);
1918       break;
1919   }
1920 }
1921
1922 // Special case where a branch and delay slot span two pages in virtual memory
1923 static void pagespan_alloc(struct regstat *current,int i)
1924 {
1925   current->isconst=0;
1926   current->wasconst=0;
1927   regs[i].wasconst=0;
1928   alloc_all(current,i);
1929   alloc_cc(current,i);
1930   dirty_reg(current,CCREG);
1931   if(opcode[i]==3) // JAL
1932   {
1933     alloc_reg(current,i,31);
1934     dirty_reg(current,31);
1935   }
1936   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1937   {
1938     alloc_reg(current,i,rs1[i]);
1939     if (rt1[i]!=0) {
1940       alloc_reg(current,i,rt1[i]);
1941       dirty_reg(current,rt1[i]);
1942     }
1943   }
1944   if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1945   {
1946     if(rs1[i]) alloc_reg(current,i,rs1[i]);
1947     if(rs2[i]) alloc_reg(current,i,rs2[i]);
1948     if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1949     {
1950       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1951       if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1952     }
1953   }
1954   else
1955   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1956   {
1957     if(rs1[i]) alloc_reg(current,i,rs1[i]);
1958     if(!((current->is32>>rs1[i])&1))
1959     {
1960       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1961     }
1962   }
1963   else
1964   if(opcode[i]==0x11) // BC1
1965   {
1966     alloc_reg(current,i,FSREG);
1967     alloc_reg(current,i,CSREG);
1968   }
1969   //else ...
1970 }
1971
1972 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
1973 {
1974   stubs[stubcount][0]=type;
1975   stubs[stubcount][1]=addr;
1976   stubs[stubcount][2]=retaddr;
1977   stubs[stubcount][3]=a;
1978   stubs[stubcount][4]=b;
1979   stubs[stubcount][5]=c;
1980   stubs[stubcount][6]=d;
1981   stubs[stubcount][7]=e;
1982   stubcount++;
1983 }
1984
1985 // Write out a single register
1986 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
1987 {
1988   int hr;
1989   for(hr=0;hr<HOST_REGS;hr++) {
1990     if(hr!=EXCLUDE_REG) {
1991       if((regmap[hr]&63)==r) {
1992         if((dirty>>hr)&1) {
1993           if(regmap[hr]<64) {
1994             emit_storereg(r,hr);
1995 #ifndef FORCE32
1996             if((is32>>regmap[hr])&1) {
1997               emit_sarimm(hr,31,hr);
1998               emit_storereg(r|64,hr);
1999             }
2000 #endif
2001           }else{
2002             emit_storereg(r|64,hr);
2003           }
2004         }
2005       }
2006     }
2007   }
2008 }
2009
2010 int mchecksum()
2011 {
2012   //if(!tracedebug) return 0;
2013   int i;
2014   int sum=0;
2015   for(i=0;i<2097152;i++) {
2016     unsigned int temp=sum;
2017     sum<<=1;
2018     sum|=(~temp)>>31;
2019     sum^=((u_int *)rdram)[i];
2020   }
2021   return sum;
2022 }
2023 int rchecksum()
2024 {
2025   int i;
2026   int sum=0;
2027   for(i=0;i<64;i++)
2028     sum^=((u_int *)reg)[i];
2029   return sum;
2030 }
2031 void rlist()
2032 {
2033   int i;
2034   printf("TRACE: ");
2035   for(i=0;i<32;i++)
2036     printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2037   printf("\n");
2038 #ifndef DISABLE_COP1
2039   printf("TRACE: ");
2040   for(i=0;i<32;i++)
2041     printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2042   printf("\n");
2043 #endif
2044 }
2045
2046 void enabletrace()
2047 {
2048   tracedebug=1;
2049 }
2050
2051 void memdebug(int i)
2052 {
2053   //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2054   //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2055   //rlist();
2056   //if(tracedebug) {
2057   //if(Count>=-2084597794) {
2058   if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2059   //if(0) {
2060     printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2061     //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2062     //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2063     rlist();
2064     #ifdef __i386__
2065     printf("TRACE: %x\n",(&i)[-1]);
2066     #endif
2067     #ifdef __arm__
2068     int j;
2069     printf("TRACE: %x \n",(&j)[10]);
2070     printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2071     #endif
2072     //fflush(stdout);
2073   }
2074   //printf("TRACE: %x\n",(&i)[-1]);
2075 }
2076
2077 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2078 {
2079   printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2080 }
2081
2082 void alu_assemble(int i,struct regstat *i_regs)
2083 {
2084   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2085     if(rt1[i]) {
2086       signed char s1,s2,t;
2087       t=get_reg(i_regs->regmap,rt1[i]);
2088       if(t>=0) {
2089         s1=get_reg(i_regs->regmap,rs1[i]);
2090         s2=get_reg(i_regs->regmap,rs2[i]);
2091         if(rs1[i]&&rs2[i]) {
2092           assert(s1>=0);
2093           assert(s2>=0);
2094           if(opcode2[i]&2) emit_sub(s1,s2,t);
2095           else emit_add(s1,s2,t);
2096         }
2097         else if(rs1[i]) {
2098           if(s1>=0) emit_mov(s1,t);
2099           else emit_loadreg(rs1[i],t);
2100         }
2101         else if(rs2[i]) {
2102           if(s2>=0) {
2103             if(opcode2[i]&2) emit_neg(s2,t);
2104             else emit_mov(s2,t);
2105           }
2106           else {
2107             emit_loadreg(rs2[i],t);
2108             if(opcode2[i]&2) emit_neg(t,t);
2109           }
2110         }
2111         else emit_zeroreg(t);
2112       }
2113     }
2114   }
2115   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2116     if(rt1[i]) {
2117       signed char s1l,s2l,s1h,s2h,tl,th;
2118       tl=get_reg(i_regs->regmap,rt1[i]);
2119       th=get_reg(i_regs->regmap,rt1[i]|64);
2120       if(tl>=0) {
2121         s1l=get_reg(i_regs->regmap,rs1[i]);
2122         s2l=get_reg(i_regs->regmap,rs2[i]);
2123         s1h=get_reg(i_regs->regmap,rs1[i]|64);
2124         s2h=get_reg(i_regs->regmap,rs2[i]|64);
2125         if(rs1[i]&&rs2[i]) {
2126           assert(s1l>=0);
2127           assert(s2l>=0);
2128           if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2129           else emit_adds(s1l,s2l,tl);
2130           if(th>=0) {
2131             #ifdef INVERTED_CARRY
2132             if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2133             #else
2134             if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2135             #endif
2136             else emit_add(s1h,s2h,th);
2137           }
2138         }
2139         else if(rs1[i]) {
2140           if(s1l>=0) emit_mov(s1l,tl);
2141           else emit_loadreg(rs1[i],tl);
2142           if(th>=0) {
2143             if(s1h>=0) emit_mov(s1h,th);
2144             else emit_loadreg(rs1[i]|64,th);
2145           }
2146         }
2147         else if(rs2[i]) {
2148           if(s2l>=0) {
2149             if(opcode2[i]&2) emit_negs(s2l,tl);
2150             else emit_mov(s2l,tl);
2151           }
2152           else {
2153             emit_loadreg(rs2[i],tl);
2154             if(opcode2[i]&2) emit_negs(tl,tl);
2155           }
2156           if(th>=0) {
2157             #ifdef INVERTED_CARRY
2158             if(s2h>=0) emit_mov(s2h,th);
2159             else emit_loadreg(rs2[i]|64,th);
2160             if(opcode2[i]&2) {
2161               emit_adcimm(-1,th); // x86 has inverted carry flag
2162               emit_not(th,th);
2163             }
2164             #else
2165             if(opcode2[i]&2) {
2166               if(s2h>=0) emit_rscimm(s2h,0,th);
2167               else {
2168                 emit_loadreg(rs2[i]|64,th);
2169                 emit_rscimm(th,0,th);
2170               }
2171             }else{
2172               if(s2h>=0) emit_mov(s2h,th);
2173               else emit_loadreg(rs2[i]|64,th);
2174             }
2175             #endif
2176           }
2177         }
2178         else {
2179           emit_zeroreg(tl);
2180           if(th>=0) emit_zeroreg(th);
2181         }
2182       }
2183     }
2184   }
2185   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2186     if(rt1[i]) {
2187       signed char s1l,s1h,s2l,s2h,t;
2188       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2189       {
2190         t=get_reg(i_regs->regmap,rt1[i]);
2191         //assert(t>=0);
2192         if(t>=0) {
2193           s1l=get_reg(i_regs->regmap,rs1[i]);
2194           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2195           s2l=get_reg(i_regs->regmap,rs2[i]);
2196           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2197           if(rs2[i]==0) // rx<r0
2198           {
2199             assert(s1h>=0);
2200             if(opcode2[i]==0x2a) // SLT
2201               emit_shrimm(s1h,31,t);
2202             else // SLTU (unsigned can not be less than zero)
2203               emit_zeroreg(t);
2204           }
2205           else if(rs1[i]==0) // r0<rx
2206           {
2207             assert(s2h>=0);
2208             if(opcode2[i]==0x2a) // SLT
2209               emit_set_gz64_32(s2h,s2l,t);
2210             else // SLTU (set if not zero)
2211               emit_set_nz64_32(s2h,s2l,t);
2212           }
2213           else {
2214             assert(s1l>=0);assert(s1h>=0);
2215             assert(s2l>=0);assert(s2h>=0);
2216             if(opcode2[i]==0x2a) // SLT
2217               emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2218             else // SLTU
2219               emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2220           }
2221         }
2222       } else {
2223         t=get_reg(i_regs->regmap,rt1[i]);
2224         //assert(t>=0);
2225         if(t>=0) {
2226           s1l=get_reg(i_regs->regmap,rs1[i]);
2227           s2l=get_reg(i_regs->regmap,rs2[i]);
2228           if(rs2[i]==0) // rx<r0
2229           {
2230             assert(s1l>=0);
2231             if(opcode2[i]==0x2a) // SLT
2232               emit_shrimm(s1l,31,t);
2233             else // SLTU (unsigned can not be less than zero)
2234               emit_zeroreg(t);
2235           }
2236           else if(rs1[i]==0) // r0<rx
2237           {
2238             assert(s2l>=0);
2239             if(opcode2[i]==0x2a) // SLT
2240               emit_set_gz32(s2l,t);
2241             else // SLTU (set if not zero)
2242               emit_set_nz32(s2l,t);
2243           }
2244           else{
2245             assert(s1l>=0);assert(s2l>=0);
2246             if(opcode2[i]==0x2a) // SLT
2247               emit_set_if_less32(s1l,s2l,t);
2248             else // SLTU
2249               emit_set_if_carry32(s1l,s2l,t);
2250           }
2251         }
2252       }
2253     }
2254   }
2255   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2256     if(rt1[i]) {
2257       signed char s1l,s1h,s2l,s2h,th,tl;
2258       tl=get_reg(i_regs->regmap,rt1[i]);
2259       th=get_reg(i_regs->regmap,rt1[i]|64);
2260       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2261       {
2262         assert(tl>=0);
2263         if(tl>=0) {
2264           s1l=get_reg(i_regs->regmap,rs1[i]);
2265           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2266           s2l=get_reg(i_regs->regmap,rs2[i]);
2267           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2268           if(rs1[i]&&rs2[i]) {
2269             assert(s1l>=0);assert(s1h>=0);
2270             assert(s2l>=0);assert(s2h>=0);
2271             if(opcode2[i]==0x24) { // AND
2272               emit_and(s1l,s2l,tl);
2273               emit_and(s1h,s2h,th);
2274             } else
2275             if(opcode2[i]==0x25) { // OR
2276               emit_or(s1l,s2l,tl);
2277               emit_or(s1h,s2h,th);
2278             } else
2279             if(opcode2[i]==0x26) { // XOR
2280               emit_xor(s1l,s2l,tl);
2281               emit_xor(s1h,s2h,th);
2282             } else
2283             if(opcode2[i]==0x27) { // NOR
2284               emit_or(s1l,s2l,tl);
2285               emit_or(s1h,s2h,th);
2286               emit_not(tl,tl);
2287               emit_not(th,th);
2288             }
2289           }
2290           else
2291           {
2292             if(opcode2[i]==0x24) { // AND
2293               emit_zeroreg(tl);
2294               emit_zeroreg(th);
2295             } else
2296             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2297               if(rs1[i]){
2298                 if(s1l>=0) emit_mov(s1l,tl);
2299                 else emit_loadreg(rs1[i],tl);
2300                 if(s1h>=0) emit_mov(s1h,th);
2301                 else emit_loadreg(rs1[i]|64,th);
2302               }
2303               else
2304               if(rs2[i]){
2305                 if(s2l>=0) emit_mov(s2l,tl);
2306                 else emit_loadreg(rs2[i],tl);
2307                 if(s2h>=0) emit_mov(s2h,th);
2308                 else emit_loadreg(rs2[i]|64,th);
2309               }
2310               else{
2311                 emit_zeroreg(tl);
2312                 emit_zeroreg(th);
2313               }
2314             } else
2315             if(opcode2[i]==0x27) { // NOR
2316               if(rs1[i]){
2317                 if(s1l>=0) emit_not(s1l,tl);
2318                 else{
2319                   emit_loadreg(rs1[i],tl);
2320                   emit_not(tl,tl);
2321                 }
2322                 if(s1h>=0) emit_not(s1h,th);
2323                 else{
2324                   emit_loadreg(rs1[i]|64,th);
2325                   emit_not(th,th);
2326                 }
2327               }
2328               else
2329               if(rs2[i]){
2330                 if(s2l>=0) emit_not(s2l,tl);
2331                 else{
2332                   emit_loadreg(rs2[i],tl);
2333                   emit_not(tl,tl);
2334                 }
2335                 if(s2h>=0) emit_not(s2h,th);
2336                 else{
2337                   emit_loadreg(rs2[i]|64,th);
2338                   emit_not(th,th);
2339                 }
2340               }
2341               else {
2342                 emit_movimm(-1,tl);
2343                 emit_movimm(-1,th);
2344               }
2345             }
2346           }
2347         }
2348       }
2349       else
2350       {
2351         // 32 bit
2352         if(tl>=0) {
2353           s1l=get_reg(i_regs->regmap,rs1[i]);
2354           s2l=get_reg(i_regs->regmap,rs2[i]);
2355           if(rs1[i]&&rs2[i]) {
2356             assert(s1l>=0);
2357             assert(s2l>=0);
2358             if(opcode2[i]==0x24) { // AND
2359               emit_and(s1l,s2l,tl);
2360             } else
2361             if(opcode2[i]==0x25) { // OR
2362               emit_or(s1l,s2l,tl);
2363             } else
2364             if(opcode2[i]==0x26) { // XOR
2365               emit_xor(s1l,s2l,tl);
2366             } else
2367             if(opcode2[i]==0x27) { // NOR
2368               emit_or(s1l,s2l,tl);
2369               emit_not(tl,tl);
2370             }
2371           }
2372           else
2373           {
2374             if(opcode2[i]==0x24) { // AND
2375               emit_zeroreg(tl);
2376             } else
2377             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2378               if(rs1[i]){
2379                 if(s1l>=0) emit_mov(s1l,tl);
2380                 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2381               }
2382               else
2383               if(rs2[i]){
2384                 if(s2l>=0) emit_mov(s2l,tl);
2385                 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2386               }
2387               else emit_zeroreg(tl);
2388             } else
2389             if(opcode2[i]==0x27) { // NOR
2390               if(rs1[i]){
2391                 if(s1l>=0) emit_not(s1l,tl);
2392                 else {
2393                   emit_loadreg(rs1[i],tl);
2394                   emit_not(tl,tl);
2395                 }
2396               }
2397               else
2398               if(rs2[i]){
2399                 if(s2l>=0) emit_not(s2l,tl);
2400                 else {
2401                   emit_loadreg(rs2[i],tl);
2402                   emit_not(tl,tl);
2403                 }
2404               }
2405               else emit_movimm(-1,tl);
2406             }
2407           }
2408         }
2409       }
2410     }
2411   }
2412 }
2413
2414 void imm16_assemble(int i,struct regstat *i_regs)
2415 {
2416   if (opcode[i]==0x0f) { // LUI
2417     if(rt1[i]) {
2418       signed char t;
2419       t=get_reg(i_regs->regmap,rt1[i]);
2420       //assert(t>=0);
2421       if(t>=0) {
2422         if(!((i_regs->isconst>>t)&1))
2423           emit_movimm(imm[i]<<16,t);
2424       }
2425     }
2426   }
2427   if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2428     if(rt1[i]) {
2429       signed char s,t;
2430       t=get_reg(i_regs->regmap,rt1[i]);
2431       s=get_reg(i_regs->regmap,rs1[i]);
2432       if(rs1[i]) {
2433         //assert(t>=0);
2434         //assert(s>=0);
2435         if(t>=0) {
2436           if(!((i_regs->isconst>>t)&1)) {
2437             if(s<0) {
2438               if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2439               emit_addimm(t,imm[i],t);
2440             }else{
2441               if(!((i_regs->wasconst>>s)&1))
2442                 emit_addimm(s,imm[i],t);
2443               else
2444                 emit_movimm(constmap[i][s]+imm[i],t);
2445             }
2446           }
2447         }
2448       } else {
2449         if(t>=0) {
2450           if(!((i_regs->isconst>>t)&1))
2451             emit_movimm(imm[i],t);
2452         }
2453       }
2454     }
2455   }
2456   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2457     if(rt1[i]) {
2458       signed char sh,sl,th,tl;
2459       th=get_reg(i_regs->regmap,rt1[i]|64);
2460       tl=get_reg(i_regs->regmap,rt1[i]);
2461       sh=get_reg(i_regs->regmap,rs1[i]|64);
2462       sl=get_reg(i_regs->regmap,rs1[i]);
2463       if(tl>=0) {
2464         if(rs1[i]) {
2465           assert(sh>=0);
2466           assert(sl>=0);
2467           if(th>=0) {
2468             emit_addimm64_32(sh,sl,imm[i],th,tl);
2469           }
2470           else {
2471             emit_addimm(sl,imm[i],tl);
2472           }
2473         } else {
2474           emit_movimm(imm[i],tl);
2475           if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2476         }
2477       }
2478     }
2479   }
2480   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2481     if(rt1[i]) {
2482       //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2483       signed char sh,sl,t;
2484       t=get_reg(i_regs->regmap,rt1[i]);
2485       sh=get_reg(i_regs->regmap,rs1[i]|64);
2486       sl=get_reg(i_regs->regmap,rs1[i]);
2487       //assert(t>=0);
2488       if(t>=0) {
2489         if(rs1[i]>0) {
2490           if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2491           if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2492             if(opcode[i]==0x0a) { // SLTI
2493               if(sl<0) {
2494                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2495                 emit_slti32(t,imm[i],t);
2496               }else{
2497                 emit_slti32(sl,imm[i],t);
2498               }
2499             }
2500             else { // SLTIU
2501               if(sl<0) {
2502                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2503                 emit_sltiu32(t,imm[i],t);
2504               }else{
2505                 emit_sltiu32(sl,imm[i],t);
2506               }
2507             }
2508           }else{ // 64-bit
2509             assert(sl>=0);
2510             if(opcode[i]==0x0a) // SLTI
2511               emit_slti64_32(sh,sl,imm[i],t);
2512             else // SLTIU
2513               emit_sltiu64_32(sh,sl,imm[i],t);
2514           }
2515         }else{
2516           // SLTI(U) with r0 is just stupid,
2517           // nonetheless examples can be found
2518           if(opcode[i]==0x0a) // SLTI
2519             if(0<imm[i]) emit_movimm(1,t);
2520             else emit_zeroreg(t);
2521           else // SLTIU
2522           {
2523             if(imm[i]) emit_movimm(1,t);
2524             else emit_zeroreg(t);
2525           }
2526         }
2527       }
2528     }
2529   }
2530   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2531     if(rt1[i]) {
2532       signed char sh,sl,th,tl;
2533       th=get_reg(i_regs->regmap,rt1[i]|64);
2534       tl=get_reg(i_regs->regmap,rt1[i]);
2535       sh=get_reg(i_regs->regmap,rs1[i]|64);
2536       sl=get_reg(i_regs->regmap,rs1[i]);
2537       if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2538         if(opcode[i]==0x0c) //ANDI
2539         {
2540           if(rs1[i]) {
2541             if(sl<0) {
2542               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2543               emit_andimm(tl,imm[i],tl);
2544             }else{
2545               if(!((i_regs->wasconst>>sl)&1))
2546                 emit_andimm(sl,imm[i],tl);
2547               else
2548                 emit_movimm(constmap[i][sl]&imm[i],tl);
2549             }
2550           }
2551           else
2552             emit_zeroreg(tl);
2553           if(th>=0) emit_zeroreg(th);
2554         }
2555         else
2556         {
2557           if(rs1[i]) {
2558             if(sl<0) {
2559               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2560             }
2561             if(th>=0) {
2562               if(sh<0) {
2563                 emit_loadreg(rs1[i]|64,th);
2564               }else{
2565                 emit_mov(sh,th);
2566               }
2567             }
2568             if(opcode[i]==0x0d) //ORI
2569             if(sl<0) {
2570               emit_orimm(tl,imm[i],tl);
2571             }else{
2572               if(!((i_regs->wasconst>>sl)&1))
2573                 emit_orimm(sl,imm[i],tl);
2574               else
2575                 emit_movimm(constmap[i][sl]|imm[i],tl);
2576             }
2577             if(opcode[i]==0x0e) //XORI
2578             if(sl<0) {
2579               emit_xorimm(tl,imm[i],tl);
2580             }else{
2581               if(!((i_regs->wasconst>>sl)&1))
2582                 emit_xorimm(sl,imm[i],tl);
2583               else
2584                 emit_movimm(constmap[i][sl]^imm[i],tl);
2585             }
2586           }
2587           else {
2588             emit_movimm(imm[i],tl);
2589             if(th>=0) emit_zeroreg(th);
2590           }
2591         }
2592       }
2593     }
2594   }
2595 }
2596
2597 void shiftimm_assemble(int i,struct regstat *i_regs)
2598 {
2599   if(opcode2[i]<=0x3) // SLL/SRL/SRA
2600   {
2601     if(rt1[i]) {
2602       signed char s,t;
2603       t=get_reg(i_regs->regmap,rt1[i]);
2604       s=get_reg(i_regs->regmap,rs1[i]);
2605       //assert(t>=0);
2606       if(t>=0){
2607         if(rs1[i]==0)
2608         {
2609           emit_zeroreg(t);
2610         }
2611         else
2612         {
2613           if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2614           if(imm[i]) {
2615             if(opcode2[i]==0) // SLL
2616             {
2617               emit_shlimm(s<0?t:s,imm[i],t);
2618             }
2619             if(opcode2[i]==2) // SRL
2620             {
2621               emit_shrimm(s<0?t:s,imm[i],t);
2622             }
2623             if(opcode2[i]==3) // SRA
2624             {
2625               emit_sarimm(s<0?t:s,imm[i],t);
2626             }
2627           }else{
2628             // Shift by zero
2629             if(s>=0 && s!=t) emit_mov(s,t);
2630           }
2631         }
2632       }
2633       //emit_storereg(rt1[i],t); //DEBUG
2634     }
2635   }
2636   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2637   {
2638     if(rt1[i]) {
2639       signed char sh,sl,th,tl;
2640       th=get_reg(i_regs->regmap,rt1[i]|64);
2641       tl=get_reg(i_regs->regmap,rt1[i]);
2642       sh=get_reg(i_regs->regmap,rs1[i]|64);
2643       sl=get_reg(i_regs->regmap,rs1[i]);
2644       if(tl>=0) {
2645         if(rs1[i]==0)
2646         {
2647           emit_zeroreg(tl);
2648           if(th>=0) emit_zeroreg(th);
2649         }
2650         else
2651         {
2652           assert(sl>=0);
2653           assert(sh>=0);
2654           if(imm[i]) {
2655             if(opcode2[i]==0x38) // DSLL
2656             {
2657               if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2658               emit_shlimm(sl,imm[i],tl);
2659             }
2660             if(opcode2[i]==0x3a) // DSRL
2661             {
2662               emit_shrdimm(sl,sh,imm[i],tl);
2663               if(th>=0) emit_shrimm(sh,imm[i],th);
2664             }
2665             if(opcode2[i]==0x3b) // DSRA
2666             {
2667               emit_shrdimm(sl,sh,imm[i],tl);
2668               if(th>=0) emit_sarimm(sh,imm[i],th);
2669             }
2670           }else{
2671             // Shift by zero
2672             if(sl!=tl) emit_mov(sl,tl);
2673             if(th>=0&&sh!=th) emit_mov(sh,th);
2674           }
2675         }
2676       }
2677     }
2678   }
2679   if(opcode2[i]==0x3c) // DSLL32
2680   {
2681     if(rt1[i]) {
2682       signed char sl,tl,th;
2683       tl=get_reg(i_regs->regmap,rt1[i]);
2684       th=get_reg(i_regs->regmap,rt1[i]|64);
2685       sl=get_reg(i_regs->regmap,rs1[i]);
2686       if(th>=0||tl>=0){
2687         assert(tl>=0);
2688         assert(th>=0);
2689         assert(sl>=0);
2690         emit_mov(sl,th);
2691         emit_zeroreg(tl);
2692         if(imm[i]>32)
2693         {
2694           emit_shlimm(th,imm[i]&31,th);
2695         }
2696       }
2697     }
2698   }
2699   if(opcode2[i]==0x3e) // DSRL32
2700   {
2701     if(rt1[i]) {
2702       signed char sh,tl,th;
2703       tl=get_reg(i_regs->regmap,rt1[i]);
2704       th=get_reg(i_regs->regmap,rt1[i]|64);
2705       sh=get_reg(i_regs->regmap,rs1[i]|64);
2706       if(tl>=0){
2707         assert(sh>=0);
2708         emit_mov(sh,tl);
2709         if(th>=0) emit_zeroreg(th);
2710         if(imm[i]>32)
2711         {
2712           emit_shrimm(tl,imm[i]&31,tl);
2713         }
2714       }
2715     }
2716   }
2717   if(opcode2[i]==0x3f) // DSRA32
2718   {
2719     if(rt1[i]) {
2720       signed char sh,tl;
2721       tl=get_reg(i_regs->regmap,rt1[i]);
2722       sh=get_reg(i_regs->regmap,rs1[i]|64);
2723       if(tl>=0){
2724         assert(sh>=0);
2725         emit_mov(sh,tl);
2726         if(imm[i]>32)
2727         {
2728           emit_sarimm(tl,imm[i]&31,tl);
2729         }
2730       }
2731     }
2732   }
2733 }
2734
2735 #ifndef shift_assemble
2736 void shift_assemble(int i,struct regstat *i_regs)
2737 {
2738   printf("Need shift_assemble for this architecture.\n");
2739   exit(1);
2740 }
2741 #endif
2742
2743 void load_assemble(int i,struct regstat *i_regs)
2744 {
2745   int s,th,tl,addr,map=-1;
2746   int offset;
2747   int jaddr=0;
2748   int memtarget=0,c=0;
2749   u_int hr,reglist=0;
2750   th=get_reg(i_regs->regmap,rt1[i]|64);
2751   tl=get_reg(i_regs->regmap,rt1[i]);
2752   s=get_reg(i_regs->regmap,rs1[i]);
2753   offset=imm[i];
2754   for(hr=0;hr<HOST_REGS;hr++) {
2755     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2756   }
2757   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2758   if(s>=0) {
2759     c=(i_regs->wasconst>>s)&1;
2760     memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2761     if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2762   }
2763   //printf("load_assemble: c=%d\n",c);
2764   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2765   // FIXME: Even if the load is a NOP, we should check for pagefaults...
2766 #ifdef PCSX
2767   if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2768     ||rt1[i]==0) {
2769       // could be FIFO, must perform the read
2770       // ||dummy read
2771       assem_debug("(forced read)\n");
2772       tl=get_reg(i_regs->regmap,-1);
2773       assert(tl>=0);
2774   }
2775 #endif
2776   if(offset||s<0||c) addr=tl;
2777   else addr=s;
2778   if(tl>=0) {
2779     //assert(tl>=0);
2780     //assert(rt1[i]);
2781     reglist&=~(1<<tl);
2782     if(th>=0) reglist&=~(1<<th);
2783     if(!using_tlb) {
2784       if(!c) {
2785 //#define R29_HACK 1
2786         #ifdef R29_HACK
2787         // Strmnnrmn's speed hack
2788         if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2789         #endif
2790         {
2791           emit_cmpimm(addr,RAM_SIZE);
2792           jaddr=(int)out;
2793           #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2794           // Hint to branch predictor that the branch is unlikely to be taken
2795           if(rs1[i]>=28)
2796             emit_jno_unlikely(0);
2797           else
2798           #endif
2799           emit_jno(0);
2800         }
2801       }
2802     }else{ // using tlb
2803       int x=0;
2804       if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2805       if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2806       map=get_reg(i_regs->regmap,TLREG);
2807       assert(map>=0);
2808       map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2809       do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2810     }
2811     if (opcode[i]==0x20) { // LB
2812       if(!c||memtarget) {
2813         #ifdef HOST_IMM_ADDR32
2814         if(c)
2815           emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2816         else
2817         #endif
2818         {
2819           //emit_xorimm(addr,3,tl);
2820           //gen_tlb_addr_r(tl,map);
2821           //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2822           int x=0;
2823 #ifdef BIG_ENDIAN_MIPS
2824           if(!c) emit_xorimm(addr,3,tl);
2825           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2826 #else
2827           if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2828           else if (tl!=addr) emit_mov(addr,tl);
2829 #endif
2830           emit_movsbl_indexed_tlb(x,tl,map,tl);
2831         }
2832         if(jaddr)
2833           add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2834       }
2835       else
2836         inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2837     }
2838     if (opcode[i]==0x21) { // LH
2839       if(!c||memtarget) {
2840         #ifdef HOST_IMM_ADDR32
2841         if(c)
2842           emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2843         else
2844         #endif
2845         {
2846           int x=0;
2847 #ifdef BIG_ENDIAN_MIPS
2848           if(!c) emit_xorimm(addr,2,tl);
2849           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2850 #else
2851           if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2852           else if (tl!=addr) emit_mov(addr,tl);
2853 #endif
2854           //#ifdef
2855           //emit_movswl_indexed_tlb(x,tl,map,tl);
2856           //else
2857           if(map>=0) {
2858             gen_tlb_addr_r(tl,map);
2859             emit_movswl_indexed(x,tl,tl);
2860           }else
2861             emit_movswl_indexed((int)rdram-0x80000000+x,tl,tl);
2862         }
2863         if(jaddr)
2864           add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2865       }
2866       else
2867         inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2868     }
2869     if (opcode[i]==0x23) { // LW
2870       if(!c||memtarget) {
2871         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2872         #ifdef HOST_IMM_ADDR32
2873         if(c)
2874           emit_readword_tlb(constmap[i][s]+offset,map,tl);
2875         else
2876         #endif
2877         emit_readword_indexed_tlb(0,addr,map,tl);
2878         if(jaddr)
2879           add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2880       }
2881       else
2882         inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2883     }
2884     if (opcode[i]==0x24) { // LBU
2885       if(!c||memtarget) {
2886         #ifdef HOST_IMM_ADDR32
2887         if(c)
2888           emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2889         else
2890         #endif
2891         {
2892           //emit_xorimm(addr,3,tl);
2893           //gen_tlb_addr_r(tl,map);
2894           //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
2895           int x=0;
2896 #ifdef BIG_ENDIAN_MIPS
2897           if(!c) emit_xorimm(addr,3,tl);
2898           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2899 #else
2900           if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2901           else if (tl!=addr) emit_mov(addr,tl);
2902 #endif
2903           emit_movzbl_indexed_tlb(x,tl,map,tl);
2904         }
2905         if(jaddr)
2906           add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2907       }
2908       else
2909         inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2910     }
2911     if (opcode[i]==0x25) { // LHU
2912       if(!c||memtarget) {
2913         #ifdef HOST_IMM_ADDR32
2914         if(c)
2915           emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2916         else
2917         #endif
2918         {
2919           int x=0;
2920 #ifdef BIG_ENDIAN_MIPS
2921           if(!c) emit_xorimm(addr,2,tl);
2922           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2923 #else
2924           if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2925           else if (tl!=addr) emit_mov(addr,tl);
2926 #endif
2927           //#ifdef
2928           //emit_movzwl_indexed_tlb(x,tl,map,tl);
2929           //#else
2930           if(map>=0) {
2931             gen_tlb_addr_r(tl,map);
2932             emit_movzwl_indexed(x,tl,tl);
2933           }else
2934             emit_movzwl_indexed((int)rdram-0x80000000+x,tl,tl);
2935           if(jaddr)
2936             add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2937         }
2938       }
2939       else
2940         inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2941     }
2942     if (opcode[i]==0x27) { // LWU
2943       assert(th>=0);
2944       if(!c||memtarget) {
2945         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2946         #ifdef HOST_IMM_ADDR32
2947         if(c)
2948           emit_readword_tlb(constmap[i][s]+offset,map,tl);
2949         else
2950         #endif
2951         emit_readword_indexed_tlb(0,addr,map,tl);
2952         if(jaddr)
2953           add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2954       }
2955       else {
2956         inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2957       }
2958       emit_zeroreg(th);
2959     }
2960     if (opcode[i]==0x37) { // LD
2961       if(!c||memtarget) {
2962         //gen_tlb_addr_r(tl,map);
2963         //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
2964         //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
2965         #ifdef HOST_IMM_ADDR32
2966         if(c)
2967           emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
2968         else
2969         #endif
2970         emit_readdword_indexed_tlb(0,addr,map,th,tl);
2971         if(jaddr)
2972           add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2973       }
2974       else
2975         inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2976     }
2977     //emit_storereg(rt1[i],tl); // DEBUG
2978   }
2979   //if(opcode[i]==0x23)
2980   //if(opcode[i]==0x24)
2981   //if(opcode[i]==0x23||opcode[i]==0x24)
2982   /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
2983   {
2984     //emit_pusha();
2985     save_regs(0x100f);
2986         emit_readword((int)&last_count,ECX);
2987         #ifdef __i386__
2988         if(get_reg(i_regs->regmap,CCREG)<0)
2989           emit_loadreg(CCREG,HOST_CCREG);
2990         emit_add(HOST_CCREG,ECX,HOST_CCREG);
2991         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
2992         emit_writeword(HOST_CCREG,(int)&Count);
2993         #endif
2994         #ifdef __arm__
2995         if(get_reg(i_regs->regmap,CCREG)<0)
2996           emit_loadreg(CCREG,0);
2997         else
2998           emit_mov(HOST_CCREG,0);
2999         emit_add(0,ECX,0);
3000         emit_addimm(0,2*ccadj[i],0);
3001         emit_writeword(0,(int)&Count);
3002         #endif
3003     emit_call((int)memdebug);
3004     //emit_popa();
3005     restore_regs(0x100f);
3006   }/**/
3007 }
3008
3009 #ifndef loadlr_assemble
3010 void loadlr_assemble(int i,struct regstat *i_regs)
3011 {
3012   printf("Need loadlr_assemble for this architecture.\n");
3013   exit(1);
3014 }
3015 #endif
3016
3017 void store_assemble(int i,struct regstat *i_regs)
3018 {
3019   int s,th,tl,map=-1;
3020   int addr,temp;
3021   int offset;
3022   int jaddr=0,jaddr2,type;
3023   int memtarget=0,c=0;
3024   int agr=AGEN1+(i&1);
3025   u_int hr,reglist=0;
3026   th=get_reg(i_regs->regmap,rs2[i]|64);
3027   tl=get_reg(i_regs->regmap,rs2[i]);
3028   s=get_reg(i_regs->regmap,rs1[i]);
3029   temp=get_reg(i_regs->regmap,agr);
3030   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3031   offset=imm[i];
3032   if(s>=0) {
3033     c=(i_regs->wasconst>>s)&1;
3034     memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3035     if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3036   }
3037   assert(tl>=0);
3038   assert(temp>=0);
3039   for(hr=0;hr<HOST_REGS;hr++) {
3040     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3041   }
3042   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3043   if(offset||s<0||c) addr=temp;
3044   else addr=s;
3045   if(!using_tlb) {
3046     if(!c) {
3047       #ifdef R29_HACK
3048       // Strmnnrmn's speed hack
3049       memtarget=1;
3050       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3051       #endif
3052       emit_cmpimm(addr,RAM_SIZE);
3053       #ifdef DESTRUCTIVE_SHIFT
3054       if(s==addr) emit_mov(s,temp);
3055       #endif
3056       #ifdef R29_HACK
3057       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3058       #endif
3059       {
3060         jaddr=(int)out;
3061         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3062         // Hint to branch predictor that the branch is unlikely to be taken
3063         if(rs1[i]>=28)
3064           emit_jno_unlikely(0);
3065         else
3066         #endif
3067         emit_jno(0);
3068       }
3069     }
3070   }else{ // using tlb
3071     int x=0;
3072     if (opcode[i]==0x28) x=3; // SB
3073     if (opcode[i]==0x29) x=2; // SH
3074     map=get_reg(i_regs->regmap,TLREG);
3075     assert(map>=0);
3076     map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3077     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3078   }
3079
3080   if (opcode[i]==0x28) { // SB
3081     if(!c||memtarget) {
3082       int x=0;
3083 #ifdef BIG_ENDIAN_MIPS
3084       if(!c) emit_xorimm(addr,3,temp);
3085       else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3086 #else
3087       if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3088       else if (addr!=temp) emit_mov(addr,temp);
3089 #endif
3090       //gen_tlb_addr_w(temp,map);
3091       //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3092       emit_writebyte_indexed_tlb(tl,x,temp,map,temp);
3093     }
3094     type=STOREB_STUB;
3095   }
3096   if (opcode[i]==0x29) { // SH
3097     if(!c||memtarget) {
3098       int x=0;
3099 #ifdef BIG_ENDIAN_MIPS
3100       if(!c) emit_xorimm(addr,2,temp);
3101       else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3102 #else
3103       if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3104       else if (addr!=temp) emit_mov(addr,temp);
3105 #endif
3106       //#ifdef
3107       //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3108       //#else
3109       if(map>=0) {
3110         gen_tlb_addr_w(temp,map);
3111         emit_writehword_indexed(tl,x,temp);
3112       }else
3113         emit_writehword_indexed(tl,(int)rdram-0x80000000+x,temp);
3114     }
3115     type=STOREH_STUB;
3116   }
3117   if (opcode[i]==0x2B) { // SW
3118     if(!c||memtarget)
3119       //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3120       emit_writeword_indexed_tlb(tl,0,addr,map,temp);
3121     type=STOREW_STUB;
3122   }
3123   if (opcode[i]==0x3F) { // SD
3124     if(!c||memtarget) {
3125       if(rs2[i]) {
3126         assert(th>=0);
3127         //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3128         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3129         emit_writedword_indexed_tlb(th,tl,0,addr,map,temp);
3130       }else{
3131         // Store zero
3132         //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3133         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3134         emit_writedword_indexed_tlb(tl,tl,0,addr,map,temp);
3135       }
3136     }
3137     type=STORED_STUB;
3138   }
3139   if(!using_tlb&&(!c||memtarget))
3140     // addr could be a temp, make sure it survives STORE*_STUB
3141     reglist|=1<<addr;
3142   if(jaddr) {
3143     add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3144   } else if(!memtarget) {
3145     inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3146   }
3147   if(!using_tlb) {
3148     if(!c||memtarget) {
3149       #ifdef DESTRUCTIVE_SHIFT
3150       // The x86 shift operation is 'destructive'; it overwrites the
3151       // source register, so we need to make a copy first and use that.
3152       addr=temp;
3153       #endif
3154       #if defined(HOST_IMM8)
3155       int ir=get_reg(i_regs->regmap,INVCP);
3156       assert(ir>=0);
3157       emit_cmpmem_indexedsr12_reg(ir,addr,1);
3158       #else
3159       emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3160       #endif
3161       jaddr2=(int)out;
3162       emit_jne(0);
3163       add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3164     }
3165   }
3166   //if(opcode[i]==0x2B || opcode[i]==0x3F)
3167   //if(opcode[i]==0x2B || opcode[i]==0x28)
3168   //if(opcode[i]==0x2B || opcode[i]==0x29)
3169   //if(opcode[i]==0x2B)
3170   /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3171   {
3172     //emit_pusha();
3173     save_regs(0x100f);
3174         emit_readword((int)&last_count,ECX);
3175         #ifdef __i386__
3176         if(get_reg(i_regs->regmap,CCREG)<0)
3177           emit_loadreg(CCREG,HOST_CCREG);
3178         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3179         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3180         emit_writeword(HOST_CCREG,(int)&Count);
3181         #endif
3182         #ifdef __arm__
3183         if(get_reg(i_regs->regmap,CCREG)<0)
3184           emit_loadreg(CCREG,0);
3185         else
3186           emit_mov(HOST_CCREG,0);
3187         emit_add(0,ECX,0);
3188         emit_addimm(0,2*ccadj[i],0);
3189         emit_writeword(0,(int)&Count);
3190         #endif
3191     emit_call((int)memdebug);
3192     //emit_popa();
3193     restore_regs(0x100f);
3194   }/**/
3195 }
3196
3197 void storelr_assemble(int i,struct regstat *i_regs)
3198 {
3199   int s,th,tl;
3200   int temp;
3201   int temp2;
3202   int offset;
3203   int jaddr=0,jaddr2;
3204   int case1,case2,case3;
3205   int done0,done1,done2;
3206   int memtarget,c=0;
3207   int agr=AGEN1+(i&1);
3208   u_int hr,reglist=0;
3209   th=get_reg(i_regs->regmap,rs2[i]|64);
3210   tl=get_reg(i_regs->regmap,rs2[i]);
3211   s=get_reg(i_regs->regmap,rs1[i]);
3212   temp=get_reg(i_regs->regmap,agr);
3213   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3214   offset=imm[i];
3215   if(s>=0) {
3216     c=(i_regs->isconst>>s)&1;
3217     memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3218     if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3219   }
3220   assert(tl>=0);
3221   for(hr=0;hr<HOST_REGS;hr++) {
3222     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3223   }
3224   if(tl>=0) {
3225     assert(temp>=0);
3226     if(!using_tlb) {
3227       if(!c) {
3228         emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3229         if(!offset&&s!=temp) emit_mov(s,temp);
3230         jaddr=(int)out;
3231         emit_jno(0);
3232       }
3233       else
3234       {
3235         if(!memtarget||!rs1[i]) {
3236           jaddr=(int)out;
3237           emit_jmp(0);
3238         }
3239       }
3240       if((u_int)rdram!=0x80000000)
3241         emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3242     }else{ // using tlb
3243       int map=get_reg(i_regs->regmap,TLREG);
3244       assert(map>=0);
3245       map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3246       if(!c&&!offset&&s>=0) emit_mov(s,temp);
3247       do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3248       if(!jaddr&&!memtarget) {
3249         jaddr=(int)out;
3250         emit_jmp(0);
3251       }
3252       gen_tlb_addr_w(temp,map);
3253     }
3254
3255     if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3256       temp2=get_reg(i_regs->regmap,FTEMP);
3257       if(!rs2[i]) temp2=th=tl;
3258     }
3259
3260 #ifndef BIG_ENDIAN_MIPS
3261     emit_xorimm(temp,3,temp);
3262 #endif
3263     emit_testimm(temp,2);
3264     case2=(int)out;
3265     emit_jne(0);
3266     emit_testimm(temp,1);
3267     case1=(int)out;
3268     emit_jne(0);
3269     // 0
3270     if (opcode[i]==0x2A) { // SWL
3271       emit_writeword_indexed(tl,0,temp);
3272     }
3273     if (opcode[i]==0x2E) { // SWR
3274       emit_writebyte_indexed(tl,3,temp);
3275     }
3276     if (opcode[i]==0x2C) { // SDL
3277       emit_writeword_indexed(th,0,temp);
3278       if(rs2[i]) emit_mov(tl,temp2);
3279     }
3280     if (opcode[i]==0x2D) { // SDR
3281       emit_writebyte_indexed(tl,3,temp);
3282       if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3283     }
3284     done0=(int)out;
3285     emit_jmp(0);
3286     // 1
3287     set_jump_target(case1,(int)out);
3288     if (opcode[i]==0x2A) { // SWL
3289       // Write 3 msb into three least significant bytes
3290       if(rs2[i]) emit_rorimm(tl,8,tl);
3291       emit_writehword_indexed(tl,-1,temp);
3292       if(rs2[i]) emit_rorimm(tl,16,tl);
3293       emit_writebyte_indexed(tl,1,temp);
3294       if(rs2[i]) emit_rorimm(tl,8,tl);
3295     }
3296     if (opcode[i]==0x2E) { // SWR
3297       // Write two lsb into two most significant bytes
3298       emit_writehword_indexed(tl,1,temp);
3299     }
3300     if (opcode[i]==0x2C) { // SDL
3301       if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3302       // Write 3 msb into three least significant bytes
3303       if(rs2[i]) emit_rorimm(th,8,th);
3304       emit_writehword_indexed(th,-1,temp);
3305       if(rs2[i]) emit_rorimm(th,16,th);
3306       emit_writebyte_indexed(th,1,temp);
3307       if(rs2[i]) emit_rorimm(th,8,th);
3308     }
3309     if (opcode[i]==0x2D) { // SDR
3310       if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3311       // Write two lsb into two most significant bytes
3312       emit_writehword_indexed(tl,1,temp);
3313     }
3314     done1=(int)out;
3315     emit_jmp(0);
3316     // 2
3317     set_jump_target(case2,(int)out);
3318     emit_testimm(temp,1);
3319     case3=(int)out;
3320     emit_jne(0);
3321     if (opcode[i]==0x2A) { // SWL
3322       // Write two msb into two least significant bytes
3323       if(rs2[i]) emit_rorimm(tl,16,tl);
3324       emit_writehword_indexed(tl,-2,temp);
3325       if(rs2[i]) emit_rorimm(tl,16,tl);
3326     }
3327     if (opcode[i]==0x2E) { // SWR
3328       // Write 3 lsb into three most significant bytes
3329       emit_writebyte_indexed(tl,-1,temp);
3330       if(rs2[i]) emit_rorimm(tl,8,tl);
3331       emit_writehword_indexed(tl,0,temp);
3332       if(rs2[i]) emit_rorimm(tl,24,tl);
3333     }
3334     if (opcode[i]==0x2C) { // SDL
3335       if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3336       // Write two msb into two least significant bytes
3337       if(rs2[i]) emit_rorimm(th,16,th);
3338       emit_writehword_indexed(th,-2,temp);
3339       if(rs2[i]) emit_rorimm(th,16,th);
3340     }
3341     if (opcode[i]==0x2D) { // SDR
3342       if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3343       // Write 3 lsb into three most significant bytes
3344       emit_writebyte_indexed(tl,-1,temp);
3345       if(rs2[i]) emit_rorimm(tl,8,tl);
3346       emit_writehword_indexed(tl,0,temp);
3347       if(rs2[i]) emit_rorimm(tl,24,tl);
3348     }
3349     done2=(int)out;
3350     emit_jmp(0);
3351     // 3
3352     set_jump_target(case3,(int)out);
3353     if (opcode[i]==0x2A) { // SWL
3354       // Write msb into least significant byte
3355       if(rs2[i]) emit_rorimm(tl,24,tl);
3356       emit_writebyte_indexed(tl,-3,temp);
3357       if(rs2[i]) emit_rorimm(tl,8,tl);
3358     }
3359     if (opcode[i]==0x2E) { // SWR
3360       // Write entire word
3361       emit_writeword_indexed(tl,-3,temp);
3362     }
3363     if (opcode[i]==0x2C) { // SDL
3364       if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3365       // Write msb into least significant byte
3366       if(rs2[i]) emit_rorimm(th,24,th);
3367       emit_writebyte_indexed(th,-3,temp);
3368       if(rs2[i]) emit_rorimm(th,8,th);
3369     }
3370     if (opcode[i]==0x2D) { // SDR
3371       if(rs2[i]) emit_mov(th,temp2);
3372       // Write entire word
3373       emit_writeword_indexed(tl,-3,temp);
3374     }
3375     set_jump_target(done0,(int)out);
3376     set_jump_target(done1,(int)out);
3377     set_jump_target(done2,(int)out);
3378     if (opcode[i]==0x2C) { // SDL
3379       emit_testimm(temp,4);
3380       done0=(int)out;
3381       emit_jne(0);
3382       emit_andimm(temp,~3,temp);
3383       emit_writeword_indexed(temp2,4,temp);
3384       set_jump_target(done0,(int)out);
3385     }
3386     if (opcode[i]==0x2D) { // SDR
3387       emit_testimm(temp,4);
3388       done0=(int)out;
3389       emit_jeq(0);
3390       emit_andimm(temp,~3,temp);
3391       emit_writeword_indexed(temp2,-4,temp);
3392       set_jump_target(done0,(int)out);
3393     }
3394     if(!c||!memtarget)
3395       add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
3396   }
3397   if(!using_tlb) {
3398     emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3399     #if defined(HOST_IMM8)
3400     int ir=get_reg(i_regs->regmap,INVCP);
3401     assert(ir>=0);
3402     emit_cmpmem_indexedsr12_reg(ir,temp,1);
3403     #else
3404     emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3405     #endif
3406     jaddr2=(int)out;
3407     emit_jne(0);
3408     add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3409   }
3410   /*
3411     emit_pusha();
3412     //save_regs(0x100f);
3413         emit_readword((int)&last_count,ECX);
3414         if(get_reg(i_regs->regmap,CCREG)<0)
3415           emit_loadreg(CCREG,HOST_CCREG);
3416         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3417         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3418         emit_writeword(HOST_CCREG,(int)&Count);
3419     emit_call((int)memdebug);
3420     emit_popa();
3421     //restore_regs(0x100f);
3422   /**/
3423 }
3424
3425 void c1ls_assemble(int i,struct regstat *i_regs)
3426 {
3427 #ifndef DISABLE_COP1
3428   int s,th,tl;
3429   int temp,ar;
3430   int map=-1;
3431   int offset;
3432   int c=0;
3433   int jaddr,jaddr2=0,jaddr3,type;
3434   int agr=AGEN1+(i&1);
3435   u_int hr,reglist=0;
3436   th=get_reg(i_regs->regmap,FTEMP|64);
3437   tl=get_reg(i_regs->regmap,FTEMP);
3438   s=get_reg(i_regs->regmap,rs1[i]);
3439   temp=get_reg(i_regs->regmap,agr);
3440   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3441   offset=imm[i];
3442   assert(tl>=0);
3443   assert(rs1[i]>0);
3444   assert(temp>=0);
3445   for(hr=0;hr<HOST_REGS;hr++) {
3446     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3447   }
3448   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3449   if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3450   {
3451     // Loads use a temporary register which we need to save
3452     reglist|=1<<temp;
3453   }
3454   if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3455     ar=temp;
3456   else // LWC1/LDC1
3457     ar=tl;
3458   //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3459   //else c=(i_regs->wasconst>>s)&1;
3460   if(s>=0) c=(i_regs->wasconst>>s)&1;
3461   // Check cop1 unusable
3462   if(!cop1_usable) {
3463     signed char rs=get_reg(i_regs->regmap,CSREG);
3464     assert(rs>=0);
3465     emit_testimm(rs,0x20000000);
3466     jaddr=(int)out;
3467     emit_jeq(0);
3468     add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3469     cop1_usable=1;
3470   }
3471   if (opcode[i]==0x39) { // SWC1 (get float address)
3472     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],tl);
3473   }
3474   if (opcode[i]==0x3D) { // SDC1 (get double address)
3475     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],tl);
3476   }
3477   // Generate address + offset
3478   if(!using_tlb) {
3479     if(!c)
3480       emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3481   }
3482   else
3483   {
3484     map=get_reg(i_regs->regmap,TLREG);
3485     assert(map>=0);
3486     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3487       map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3488     }
3489     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3490       map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3491     }
3492   }
3493   if (opcode[i]==0x39) { // SWC1 (read float)
3494     emit_readword_indexed(0,tl,tl);
3495   }
3496   if (opcode[i]==0x3D) { // SDC1 (read double)
3497     emit_readword_indexed(4,tl,th);
3498     emit_readword_indexed(0,tl,tl);
3499   }
3500   if (opcode[i]==0x31) { // LWC1 (get target address)
3501     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],temp);
3502   }
3503   if (opcode[i]==0x35) { // LDC1 (get target address)
3504     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],temp);
3505   }
3506   if(!using_tlb) {
3507     if(!c) {
3508       jaddr2=(int)out;
3509       emit_jno(0);
3510     }
3511     else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
3512       jaddr2=(int)out;
3513       emit_jmp(0); // inline_readstub/inline_writestub?  Very rare case
3514     }
3515     #ifdef DESTRUCTIVE_SHIFT
3516     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3517       if(!offset&&!c&&s>=0) emit_mov(s,ar);
3518     }
3519     #endif
3520   }else{
3521     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3522       do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3523     }
3524     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3525       do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3526     }
3527   }
3528   if (opcode[i]==0x31) { // LWC1
3529     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3530     //gen_tlb_addr_r(ar,map);
3531     //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3532     #ifdef HOST_IMM_ADDR32
3533     if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3534     else
3535     #endif
3536     emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3537     type=LOADW_STUB;
3538   }
3539   if (opcode[i]==0x35) { // LDC1
3540     assert(th>=0);
3541     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3542     //gen_tlb_addr_r(ar,map);
3543     //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3544     //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3545     #ifdef HOST_IMM_ADDR32
3546     if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3547     else
3548     #endif
3549     emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3550     type=LOADD_STUB;
3551   }
3552   if (opcode[i]==0x39) { // SWC1
3553     //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3554     emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3555     type=STOREW_STUB;
3556   }
3557   if (opcode[i]==0x3D) { // SDC1
3558     assert(th>=0);
3559     //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3560     //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3561     emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3562     type=STORED_STUB;
3563   }
3564   if(!using_tlb) {
3565     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3566       #ifndef DESTRUCTIVE_SHIFT
3567       temp=offset||c||s<0?ar:s;
3568       #endif
3569       #if defined(HOST_IMM8)
3570       int ir=get_reg(i_regs->regmap,INVCP);
3571       assert(ir>=0);
3572       emit_cmpmem_indexedsr12_reg(ir,temp,1);
3573       #else
3574       emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3575       #endif
3576       jaddr3=(int)out;
3577       emit_jne(0);
3578       add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3579     }
3580   }
3581   if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3582   if (opcode[i]==0x31) { // LWC1 (write float)
3583     emit_writeword_indexed(tl,0,temp);
3584   }
3585   if (opcode[i]==0x35) { // LDC1 (write double)
3586     emit_writeword_indexed(th,4,temp);
3587     emit_writeword_indexed(tl,0,temp);
3588   }
3589   //if(opcode[i]==0x39)
3590   /*if(opcode[i]==0x39||opcode[i]==0x31)
3591   {
3592     emit_pusha();
3593         emit_readword((int)&last_count,ECX);
3594         if(get_reg(i_regs->regmap,CCREG)<0)
3595           emit_loadreg(CCREG,HOST_CCREG);
3596         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3597         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3598         emit_writeword(HOST_CCREG,(int)&Count);
3599     emit_call((int)memdebug);
3600     emit_popa();
3601   }/**/
3602 #else
3603   cop1_unusable(i, i_regs);
3604 #endif
3605 }
3606
3607 void c2ls_assemble(int i,struct regstat *i_regs)
3608 {
3609   int s,tl;
3610   int ar;
3611   int offset;
3612   int memtarget=0,c=0;
3613   int jaddr,jaddr2=0,jaddr3,type;
3614   int agr=AGEN1+(i&1);
3615   u_int hr,reglist=0;
3616   u_int copr=(source[i]>>16)&0x1f;
3617   s=get_reg(i_regs->regmap,rs1[i]);
3618   tl=get_reg(i_regs->regmap,FTEMP);
3619   offset=imm[i];
3620   assert(rs1[i]>0);
3621   assert(tl>=0);
3622   assert(!using_tlb);
3623
3624   for(hr=0;hr<HOST_REGS;hr++) {
3625     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3626   }
3627   if(i_regs->regmap[HOST_CCREG]==CCREG)
3628     reglist&=~(1<<HOST_CCREG);
3629
3630   // get the address
3631   if (opcode[i]==0x3a) { // SWC2
3632     ar=get_reg(i_regs->regmap,agr);
3633     if(ar<0) ar=get_reg(i_regs->regmap,-1);
3634     reglist|=1<<ar;
3635   } else { // LWC2
3636     ar=tl;
3637   }
3638   if(s>=0) c=(i_regs->wasconst>>s)&1;
3639   memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3640   if (!offset&&!c&&s>=0) ar=s;
3641   assert(ar>=0);
3642
3643   if (opcode[i]==0x3a) { // SWC2
3644     cop2_get_dreg(copr,tl,HOST_TEMPREG);
3645     type=STOREW_STUB;
3646   }
3647   else
3648     type=LOADW_STUB;
3649
3650   if(c&&!memtarget) {
3651     jaddr2=(int)out;
3652     emit_jmp(0); // inline_readstub/inline_writestub?
3653   }
3654   else {
3655     if(!c) {
3656       emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3657       jaddr2=(int)out;
3658       emit_jno(0);
3659     }
3660     if (opcode[i]==0x32) { // LWC2
3661       #ifdef HOST_IMM_ADDR32
3662       if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3663       else
3664       #endif
3665       emit_readword_indexed(0,ar,tl);
3666     }
3667     if (opcode[i]==0x3a) { // SWC2
3668       #ifdef DESTRUCTIVE_SHIFT
3669       if(!offset&&!c&&s>=0) emit_mov(s,ar);
3670       #endif
3671       emit_writeword_indexed(tl,0,ar);
3672     }
3673   }
3674   if(jaddr2)
3675     add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3676   if (opcode[i]==0x3a) { // SWC2
3677 #if defined(HOST_IMM8)
3678     int ir=get_reg(i_regs->regmap,INVCP);
3679     assert(ir>=0);
3680     emit_cmpmem_indexedsr12_reg(ir,ar,1);
3681 #else
3682     emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3683 #endif
3684     jaddr3=(int)out;
3685     emit_jne(0);
3686     add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3687   }
3688   if (opcode[i]==0x32) { // LWC2
3689     cop2_put_dreg(copr,tl,HOST_TEMPREG);
3690   }
3691 }
3692
3693 #ifndef multdiv_assemble
3694 void multdiv_assemble(int i,struct regstat *i_regs)
3695 {
3696   printf("Need multdiv_assemble for this architecture.\n");
3697   exit(1);
3698 }
3699 #endif
3700
3701 void mov_assemble(int i,struct regstat *i_regs)
3702 {
3703   //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3704   //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3705   //assert(rt1[i]>0);
3706   if(rt1[i]) {
3707     signed char sh,sl,th,tl;
3708     th=get_reg(i_regs->regmap,rt1[i]|64);
3709     tl=get_reg(i_regs->regmap,rt1[i]);
3710     //assert(tl>=0);
3711     if(tl>=0) {
3712       sh=get_reg(i_regs->regmap,rs1[i]|64);
3713       sl=get_reg(i_regs->regmap,rs1[i]);
3714       if(sl>=0) emit_mov(sl,tl);
3715       else emit_loadreg(rs1[i],tl);
3716       if(th>=0) {
3717         if(sh>=0) emit_mov(sh,th);
3718         else emit_loadreg(rs1[i]|64,th);
3719       }
3720     }
3721   }
3722 }
3723
3724 #ifndef fconv_assemble
3725 void fconv_assemble(int i,struct regstat *i_regs)
3726 {
3727   printf("Need fconv_assemble for this architecture.\n");
3728   exit(1);
3729 }
3730 #endif
3731
3732 #if 0
3733 void float_assemble(int i,struct regstat *i_regs)
3734 {
3735   printf("Need float_assemble for this architecture.\n");
3736   exit(1);
3737 }
3738 #endif
3739
3740 void syscall_assemble(int i,struct regstat *i_regs)
3741 {
3742   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3743   assert(ccreg==HOST_CCREG);
3744   assert(!is_delayslot);
3745   emit_movimm(start+i*4,EAX); // Get PC
3746   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right?  There should probably be an extra cycle...
3747   emit_jmp((int)jump_syscall_hle); // XXX
3748 }
3749
3750 void hlecall_assemble(int i,struct regstat *i_regs)
3751 {
3752   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3753   assert(ccreg==HOST_CCREG);
3754   assert(!is_delayslot);
3755   emit_movimm(start+i*4+4,0); // Get PC
3756   emit_movimm((int)psxHLEt[source[i]&7],1);
3757   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // XXX
3758   emit_jmp((int)jump_hlecall);
3759 }
3760
3761 void intcall_assemble(int i,struct regstat *i_regs)
3762 {
3763   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3764   assert(ccreg==HOST_CCREG);
3765   assert(!is_delayslot);
3766   emit_movimm(start+i*4,0); // Get PC
3767   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3768   emit_jmp((int)jump_intcall);
3769 }
3770
3771 void ds_assemble(int i,struct regstat *i_regs)
3772 {
3773   is_delayslot=1;
3774   switch(itype[i]) {
3775     case ALU:
3776       alu_assemble(i,i_regs);break;
3777     case IMM16:
3778       imm16_assemble(i,i_regs);break;
3779     case SHIFT:
3780       shift_assemble(i,i_regs);break;
3781     case SHIFTIMM:
3782       shiftimm_assemble(i,i_regs);break;
3783     case LOAD:
3784       load_assemble(i,i_regs);break;
3785     case LOADLR:
3786       loadlr_assemble(i,i_regs);break;
3787     case STORE:
3788       store_assemble(i,i_regs);break;
3789     case STORELR:
3790       storelr_assemble(i,i_regs);break;
3791     case COP0:
3792       cop0_assemble(i,i_regs);break;
3793     case COP1:
3794       cop1_assemble(i,i_regs);break;
3795     case C1LS:
3796       c1ls_assemble(i,i_regs);break;
3797     case COP2:
3798       cop2_assemble(i,i_regs);break;
3799     case C2LS:
3800       c2ls_assemble(i,i_regs);break;
3801     case C2OP:
3802       c2op_assemble(i,i_regs);break;
3803     case FCONV:
3804       fconv_assemble(i,i_regs);break;
3805     case FLOAT:
3806       float_assemble(i,i_regs);break;
3807     case FCOMP:
3808       fcomp_assemble(i,i_regs);break;
3809     case MULTDIV:
3810       multdiv_assemble(i,i_regs);break;
3811     case MOV:
3812       mov_assemble(i,i_regs);break;
3813     case SYSCALL:
3814     case HLECALL:
3815     case INTCALL:
3816     case SPAN:
3817     case UJUMP:
3818     case RJUMP:
3819     case CJUMP:
3820     case SJUMP:
3821     case FJUMP:
3822       printf("Jump in the delay slot.  This is probably a bug.\n");
3823   }
3824   is_delayslot=0;
3825 }
3826
3827 // Is the branch target a valid internal jump?
3828 int internal_branch(uint64_t i_is32,int addr)
3829 {
3830   if(addr&1) return 0; // Indirect (register) jump
3831   if(addr>=start && addr<start+slen*4-4)
3832   {
3833     int t=(addr-start)>>2;
3834     // Delay slots are not valid branch targets
3835     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
3836     // 64 -> 32 bit transition requires a recompile
3837     /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
3838     {
3839       if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
3840       else printf("optimizable: yes\n");
3841     }*/
3842     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
3843     if(requires_32bit[t]&~i_is32) return 0;
3844     else return 1;
3845   }
3846   return 0;
3847 }
3848
3849 #ifndef wb_invalidate
3850 void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
3851   uint64_t u,uint64_t uu)
3852 {
3853   int hr;
3854   for(hr=0;hr<HOST_REGS;hr++) {
3855     if(hr!=EXCLUDE_REG) {
3856       if(pre[hr]!=entry[hr]) {
3857         if(pre[hr]>=0) {
3858           if((dirty>>hr)&1) {
3859             if(get_reg(entry,pre[hr])<0) {
3860               if(pre[hr]<64) {
3861                 if(!((u>>pre[hr])&1)) {
3862                   emit_storereg(pre[hr],hr);
3863                   if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
3864                     emit_sarimm(hr,31,hr);
3865                     emit_storereg(pre[hr]|64,hr);
3866                   }
3867                 }
3868               }else{
3869                 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
3870                   emit_storereg(pre[hr],hr);
3871                 }
3872               }
3873             }
3874           }
3875         }
3876       }
3877     }
3878   }
3879   // Move from one register to another (no writeback)
3880   for(hr=0;hr<HOST_REGS;hr++) {
3881     if(hr!=EXCLUDE_REG) {
3882       if(pre[hr]!=entry[hr]) {
3883         if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
3884           int nr;
3885           if((nr=get_reg(entry,pre[hr]))>=0) {
3886             emit_mov(hr,nr);
3887           }
3888         }
3889       }
3890     }
3891   }
3892 }
3893 #endif
3894
3895 // Load the specified registers
3896 // This only loads the registers given as arguments because
3897 // we don't want to load things that will be overwritten
3898 void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
3899 {
3900   int hr;
3901   // Load 32-bit regs
3902   for(hr=0;hr<HOST_REGS;hr++) {
3903     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
3904       if(entry[hr]!=regmap[hr]) {
3905         if(regmap[hr]==rs1||regmap[hr]==rs2)
3906         {
3907           if(regmap[hr]==0) {
3908             emit_zeroreg(hr);
3909           }
3910           else
3911           {
3912             emit_loadreg(regmap[hr],hr);
3913           }
3914         }
3915       }
3916     }
3917   }
3918   //Load 64-bit regs
3919   for(hr=0;hr<HOST_REGS;hr++) {
3920     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
3921       if(entry[hr]!=regmap[hr]) {
3922         if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
3923         {
3924           assert(regmap[hr]!=64);
3925           if((is32>>(regmap[hr]&63))&1) {
3926             int lr=get_reg(regmap,regmap[hr]-64);
3927             if(lr>=0)
3928               emit_sarimm(lr,31,hr);
3929             else
3930               emit_loadreg(regmap[hr],hr);
3931           }
3932           else
3933           {
3934             emit_loadreg(regmap[hr],hr);
3935           }
3936         }
3937       }
3938     }
3939   }
3940 }
3941
3942 // Load registers prior to the start of a loop
3943 // so that they are not loaded within the loop
3944 static void loop_preload(signed char pre[],signed char entry[])
3945 {
3946   int hr;
3947   for(hr=0;hr<HOST_REGS;hr++) {
3948     if(hr!=EXCLUDE_REG) {
3949       if(pre[hr]!=entry[hr]) {
3950         if(entry[hr]>=0) {
3951           if(get_reg(pre,entry[hr])<0) {
3952             assem_debug("loop preload:\n");
3953             //printf("loop preload: %d\n",hr);
3954             if(entry[hr]==0) {
3955               emit_zeroreg(hr);
3956             }
3957             else if(entry[hr]<TEMPREG)
3958             {
3959               emit_loadreg(entry[hr],hr);
3960             }
3961             else if(entry[hr]-64<TEMPREG)
3962             {
3963               emit_loadreg(entry[hr],hr);
3964             }
3965           }
3966         }
3967       }
3968     }
3969   }
3970 }
3971
3972 // Generate address for load/store instruction
3973 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
3974 void address_generation(int i,struct regstat *i_regs,signed char entry[])
3975 {
3976   if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
3977     int ra;
3978     int agr=AGEN1+(i&1);
3979     int mgr=MGEN1+(i&1);
3980     if(itype[i]==LOAD) {
3981       ra=get_reg(i_regs->regmap,rt1[i]);
3982       //if(rt1[i]) assert(ra>=0);
3983     }
3984     if(itype[i]==LOADLR) {
3985       ra=get_reg(i_regs->regmap,FTEMP);
3986     }
3987     if(itype[i]==STORE||itype[i]==STORELR) {
3988       ra=get_reg(i_regs->regmap,agr);
3989       if(ra<0) ra=get_reg(i_regs->regmap,-1);
3990     }
3991     if(itype[i]==C1LS||itype[i]==C2LS) {
3992       if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
3993         ra=get_reg(i_regs->regmap,FTEMP);
3994       else { // SWC1/SDC1/SWC2/SDC2
3995         ra=get_reg(i_regs->regmap,agr);
3996         if(ra<0) ra=get_reg(i_regs->regmap,-1);
3997       }
3998     }
3999     int rs=get_reg(i_regs->regmap,rs1[i]);
4000     int rm=get_reg(i_regs->regmap,TLREG);
4001     if(ra>=0) {
4002       int offset=imm[i];
4003       int c=(i_regs->wasconst>>rs)&1;
4004       if(rs1[i]==0) {
4005         // Using r0 as a base address
4006         /*if(rm>=0) {
4007           if(!entry||entry[rm]!=mgr) {
4008             generate_map_const(offset,rm);
4009           } // else did it in the previous cycle
4010         }*/
4011         if(!entry||entry[ra]!=agr) {
4012           if (opcode[i]==0x22||opcode[i]==0x26) {
4013             emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4014           }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4015             emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4016           }else{
4017             emit_movimm(offset,ra);
4018           }
4019         } // else did it in the previous cycle
4020       }
4021       else if(rs<0) {
4022         if(!entry||entry[ra]!=rs1[i])
4023           emit_loadreg(rs1[i],ra);
4024         //if(!entry||entry[ra]!=rs1[i])
4025         //  printf("poor load scheduling!\n");
4026       }
4027       else if(c) {
4028         if(rm>=0) {
4029           if(!entry||entry[rm]!=mgr) {
4030             if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
4031               // Stores to memory go thru the mapper to detect self-modifying
4032               // code, loads don't.
4033               if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
4034                  (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
4035                 generate_map_const(constmap[i][rs]+offset,rm);
4036             }else{
4037               if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
4038                 generate_map_const(constmap[i][rs]+offset,rm);
4039             }
4040           }
4041         }
4042         if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
4043           if(!entry||entry[ra]!=agr) {
4044             if (opcode[i]==0x22||opcode[i]==0x26) {
4045               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4046             }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4047               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4048             }else{
4049               #ifdef HOST_IMM_ADDR32
4050               if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4051                  (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4052               #endif
4053               emit_movimm(constmap[i][rs]+offset,ra);
4054             }
4055           } // else did it in the previous cycle
4056         } // else load_consts already did it
4057       }
4058       if(offset&&!c&&rs1[i]) {
4059         if(rs>=0) {
4060           emit_addimm(rs,offset,ra);
4061         }else{
4062           emit_addimm(ra,offset,ra);
4063         }
4064       }
4065     }
4066   }
4067   // Preload constants for next instruction
4068   if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
4069     int agr,ra;
4070     #ifndef HOST_IMM_ADDR32
4071     // Mapper entry
4072     agr=MGEN1+((i+1)&1);
4073     ra=get_reg(i_regs->regmap,agr);
4074     if(ra>=0) {
4075       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4076       int offset=imm[i+1];
4077       int c=(regs[i+1].wasconst>>rs)&1;
4078       if(c) {
4079         if(itype[i+1]==STORE||itype[i+1]==STORELR
4080            ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
4081           // Stores to memory go thru the mapper to detect self-modifying
4082           // code, loads don't.
4083           if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4084              (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
4085             generate_map_const(constmap[i+1][rs]+offset,ra);
4086         }else{
4087           if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4088             generate_map_const(constmap[i+1][rs]+offset,ra);
4089         }
4090       }
4091       /*else if(rs1[i]==0) {
4092         generate_map_const(offset,ra);
4093       }*/
4094     }
4095     #endif
4096     // Actual address
4097     agr=AGEN1+((i+1)&1);
4098     ra=get_reg(i_regs->regmap,agr);
4099     if(ra>=0) {
4100       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4101       int offset=imm[i+1];
4102       int c=(regs[i+1].wasconst>>rs)&1;
4103       if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4104         if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4105           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4106         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4107           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4108         }else{
4109           #ifdef HOST_IMM_ADDR32
4110           if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4111              (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4112           #endif
4113           emit_movimm(constmap[i+1][rs]+offset,ra);
4114         }
4115       }
4116       else if(rs1[i+1]==0) {
4117         // Using r0 as a base address
4118         if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4119           emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4120         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4121           emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4122         }else{
4123           emit_movimm(offset,ra);
4124         }
4125       }
4126     }
4127   }
4128 }
4129
4130 int get_final_value(int hr, int i, int *value)
4131 {
4132   int reg=regs[i].regmap[hr];
4133   while(i<slen-1) {
4134     if(regs[i+1].regmap[hr]!=reg) break;
4135     if(!((regs[i+1].isconst>>hr)&1)) break;
4136     if(bt[i+1]) break;
4137     i++;
4138   }
4139   if(i<slen-1) {
4140     if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4141       *value=constmap[i][hr];
4142       return 1;
4143     }
4144     if(!bt[i+1]) {
4145       if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4146         // Load in delay slot, out-of-order execution
4147         if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4148         {
4149           #ifdef HOST_IMM_ADDR32
4150           if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4151           #endif
4152           // Precompute load address
4153           *value=constmap[i][hr]+imm[i+2];
4154           return 1;
4155         }
4156       }
4157       if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4158       {
4159         #ifdef HOST_IMM_ADDR32
4160         if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4161         #endif
4162         // Precompute load address
4163         *value=constmap[i][hr]+imm[i+1];
4164         //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4165         return 1;
4166       }
4167     }
4168   }
4169   *value=constmap[i][hr];
4170   //printf("c=%x\n",(int)constmap[i][hr]);
4171   if(i==slen-1) return 1;
4172   if(reg<64) {
4173     return !((unneeded_reg[i+1]>>reg)&1);
4174   }else{
4175     return !((unneeded_reg_upper[i+1]>>reg)&1);
4176   }
4177 }
4178
4179 // Load registers with known constants
4180 void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4181 {
4182   int hr;
4183   // Load 32-bit regs
4184   for(hr=0;hr<HOST_REGS;hr++) {
4185     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4186       //if(entry[hr]!=regmap[hr]) {
4187       if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4188         if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4189           int value;
4190           if(get_final_value(hr,i,&value)) {
4191             if(value==0) {
4192               emit_zeroreg(hr);
4193             }
4194             else {
4195               emit_movimm(value,hr);
4196             }
4197           }
4198         }
4199       }
4200     }
4201   }
4202   // Load 64-bit regs
4203   for(hr=0;hr<HOST_REGS;hr++) {
4204     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4205       //if(entry[hr]!=regmap[hr]) {
4206       if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4207         if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4208           if((is32>>(regmap[hr]&63))&1) {
4209             int lr=get_reg(regmap,regmap[hr]-64);
4210             assert(lr>=0);
4211             emit_sarimm(lr,31,hr);
4212           }
4213           else
4214           {
4215             int value;
4216             if(get_final_value(hr,i,&value)) {
4217               if(value==0) {
4218                 emit_zeroreg(hr);
4219               }
4220               else {
4221                 emit_movimm(value,hr);
4222               }
4223             }
4224           }
4225         }
4226       }
4227     }
4228   }
4229 }
4230 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4231 {
4232   int hr;
4233   // Load 32-bit regs
4234   for(hr=0;hr<HOST_REGS;hr++) {
4235     if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4236       if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4237         int value=constmap[i][hr];
4238         if(value==0) {
4239           emit_zeroreg(hr);
4240         }
4241         else {
4242           emit_movimm(value,hr);
4243         }
4244       }
4245     }
4246   }
4247   // Load 64-bit regs
4248   for(hr=0;hr<HOST_REGS;hr++) {
4249     if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4250       if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4251         if((is32>>(regmap[hr]&63))&1) {
4252           int lr=get_reg(regmap,regmap[hr]-64);
4253           assert(lr>=0);
4254           emit_sarimm(lr,31,hr);
4255         }
4256         else
4257         {
4258           int value=constmap[i][hr];
4259           if(value==0) {
4260             emit_zeroreg(hr);
4261           }
4262           else {
4263             emit_movimm(value,hr);
4264           }
4265         }
4266       }
4267     }
4268   }
4269 }
4270
4271 // Write out all dirty registers (except cycle count)
4272 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4273 {
4274   int hr;
4275   for(hr=0;hr<HOST_REGS;hr++) {
4276     if(hr!=EXCLUDE_REG) {
4277       if(i_regmap[hr]>0) {
4278         if(i_regmap[hr]!=CCREG) {
4279           if((i_dirty>>hr)&1) {
4280             if(i_regmap[hr]<64) {
4281               emit_storereg(i_regmap[hr],hr);
4282 #ifndef FORCE32
4283               if( ((i_is32>>i_regmap[hr])&1) ) {
4284                 #ifdef DESTRUCTIVE_WRITEBACK
4285                 emit_sarimm(hr,31,hr);
4286                 emit_storereg(i_regmap[hr]|64,hr);
4287                 #else
4288                 emit_sarimm(hr,31,HOST_TEMPREG);
4289                 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4290                 #endif
4291               }
4292 #endif
4293             }else{
4294               if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4295                 emit_storereg(i_regmap[hr],hr);
4296               }
4297             }
4298           }
4299         }
4300       }
4301     }
4302   }
4303 }
4304 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4305 // This writes the registers not written by store_regs_bt
4306 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4307 {
4308   int hr;
4309   int t=(addr-start)>>2;
4310   for(hr=0;hr<HOST_REGS;hr++) {
4311     if(hr!=EXCLUDE_REG) {
4312       if(i_regmap[hr]>0) {
4313         if(i_regmap[hr]!=CCREG) {
4314           if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4315             if((i_dirty>>hr)&1) {
4316               if(i_regmap[hr]<64) {
4317                 emit_storereg(i_regmap[hr],hr);
4318 #ifndef FORCE32
4319                 if( ((i_is32>>i_regmap[hr])&1) ) {
4320                   #ifdef DESTRUCTIVE_WRITEBACK
4321                   emit_sarimm(hr,31,hr);
4322                   emit_storereg(i_regmap[hr]|64,hr);
4323                   #else
4324                   emit_sarimm(hr,31,HOST_TEMPREG);
4325                   emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4326                   #endif
4327                 }
4328 #endif
4329               }else{
4330                 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4331                   emit_storereg(i_regmap[hr],hr);
4332                 }
4333               }
4334             }
4335           }
4336         }
4337       }
4338     }
4339   }
4340 }
4341
4342 // Load all registers (except cycle count)
4343 void load_all_regs(signed char i_regmap[])
4344 {
4345   int hr;
4346   for(hr=0;hr<HOST_REGS;hr++) {
4347     if(hr!=EXCLUDE_REG) {
4348       if(i_regmap[hr]==0) {
4349         emit_zeroreg(hr);
4350       }
4351       else
4352       if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG)
4353       {
4354         emit_loadreg(i_regmap[hr],hr);
4355       }
4356     }
4357   }
4358 }
4359
4360 // Load all current registers also needed by next instruction
4361 void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4362 {
4363   int hr;
4364   for(hr=0;hr<HOST_REGS;hr++) {
4365     if(hr!=EXCLUDE_REG) {
4366       if(get_reg(next_regmap,i_regmap[hr])>=0) {
4367         if(i_regmap[hr]==0) {
4368           emit_zeroreg(hr);
4369         }
4370         else
4371         if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG)
4372         {
4373           emit_loadreg(i_regmap[hr],hr);
4374         }
4375       }
4376     }
4377   }
4378 }
4379
4380 // Load all regs, storing cycle count if necessary
4381 void load_regs_entry(int t)
4382 {
4383   int hr;
4384   if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER,HOST_CCREG);
4385   else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t]*CLOCK_DIVIDER,HOST_CCREG);
4386   if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4387     emit_storereg(CCREG,HOST_CCREG);
4388   }
4389   // Load 32-bit regs
4390   for(hr=0;hr<HOST_REGS;hr++) {
4391     if(regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<64) {
4392       if(regs[t].regmap_entry[hr]==0) {
4393         emit_zeroreg(hr);
4394       }
4395       else if(regs[t].regmap_entry[hr]!=CCREG)
4396       {
4397         emit_loadreg(regs[t].regmap_entry[hr],hr);
4398       }
4399     }
4400   }
4401   // Load 64-bit regs
4402   for(hr=0;hr<HOST_REGS;hr++) {
4403     if(regs[t].regmap_entry[hr]>=64) {
4404       assert(regs[t].regmap_entry[hr]!=64);
4405       if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4406         int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4407         if(lr<0) {
4408           emit_loadreg(regs[t].regmap_entry[hr],hr);
4409         }
4410         else
4411         {
4412           emit_sarimm(lr,31,hr);
4413         }
4414       }
4415       else
4416       {
4417         emit_loadreg(regs[t].regmap_entry[hr],hr);
4418       }
4419     }
4420   }
4421 }
4422
4423 // Store dirty registers prior to branch
4424 void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4425 {
4426   if(internal_branch(i_is32,addr))
4427   {
4428     int t=(addr-start)>>2;
4429     int hr;
4430     for(hr=0;hr<HOST_REGS;hr++) {
4431       if(hr!=EXCLUDE_REG) {
4432         if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4433           if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4434             if((i_dirty>>hr)&1) {
4435               if(i_regmap[hr]<64) {
4436                 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4437                   emit_storereg(i_regmap[hr],hr);
4438                   if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4439                     #ifdef DESTRUCTIVE_WRITEBACK
4440                     emit_sarimm(hr,31,hr);
4441                     emit_storereg(i_regmap[hr]|64,hr);
4442                     #else
4443                     emit_sarimm(hr,31,HOST_TEMPREG);
4444                     emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4445                     #endif
4446                   }
4447                 }
4448               }else{
4449                 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4450                   emit_storereg(i_regmap[hr],hr);
4451                 }
4452               }
4453             }
4454           }
4455         }
4456       }
4457     }
4458   }
4459   else
4460   {
4461     // Branch out of this block, write out all dirty regs
4462     wb_dirtys(i_regmap,i_is32,i_dirty);
4463   }
4464 }
4465
4466 // Load all needed registers for branch target
4467 void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4468 {
4469   //if(addr>=start && addr<(start+slen*4))
4470   if(internal_branch(i_is32,addr))
4471   {
4472     int t=(addr-start)>>2;
4473     int hr;
4474     // Store the cycle count before loading something else
4475     if(i_regmap[HOST_CCREG]!=CCREG) {
4476       assert(i_regmap[HOST_CCREG]==-1);
4477     }
4478     if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4479       emit_storereg(CCREG,HOST_CCREG);
4480     }
4481     // Load 32-bit regs
4482     for(hr=0;hr<HOST_REGS;hr++) {
4483       if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<64) {
4484         #ifdef DESTRUCTIVE_WRITEBACK
4485         if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4486         #else
4487         if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4488         #endif
4489           if(regs[t].regmap_entry[hr]==0) {
4490             emit_zeroreg(hr);
4491           }
4492           else if(regs[t].regmap_entry[hr]!=CCREG)
4493           {
4494             emit_loadreg(regs[t].regmap_entry[hr],hr);
4495           }
4496         }
4497       }
4498     }
4499     //Load 64-bit regs
4500     for(hr=0;hr<HOST_REGS;hr++) {
4501       if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=64) {
4502         if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4503           assert(regs[t].regmap_entry[hr]!=64);
4504           if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4505             int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4506             if(lr<0) {
4507               emit_loadreg(regs[t].regmap_entry[hr],hr);
4508             }
4509             else
4510             {
4511               emit_sarimm(lr,31,hr);
4512             }
4513           }
4514           else
4515           {
4516             emit_loadreg(regs[t].regmap_entry[hr],hr);
4517           }
4518         }
4519         else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4520           int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4521           assert(lr>=0);
4522           emit_sarimm(lr,31,hr);
4523         }
4524       }
4525     }
4526   }
4527 }
4528
4529 int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4530 {
4531   if(addr>=start && addr<start+slen*4-4)
4532   {
4533     int t=(addr-start)>>2;
4534     int hr;
4535     if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4536     for(hr=0;hr<HOST_REGS;hr++)
4537     {
4538       if(hr!=EXCLUDE_REG)
4539       {
4540         if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4541         {
4542           if(regs[t].regmap_entry[hr]!=-1)
4543           {
4544             return 0;
4545           }
4546           else
4547           if((i_dirty>>hr)&1)
4548           {
4549             if(i_regmap[hr]<64)
4550             {
4551               if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4552                 return 0;
4553             }
4554             else
4555             {
4556               if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4557                 return 0;
4558             }
4559           }
4560         }
4561         else // Same register but is it 32-bit or dirty?
4562         if(i_regmap[hr]>=0)
4563         {
4564           if(!((regs[t].dirty>>hr)&1))
4565           {
4566             if((i_dirty>>hr)&1)
4567             {
4568               if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4569               {
4570                 //printf("%x: dirty no match\n",addr);
4571                 return 0;
4572               }
4573             }
4574           }
4575           if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4576           {
4577             //printf("%x: is32 no match\n",addr);
4578             return 0;
4579           }
4580         }
4581       }
4582     }
4583     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4584     if(requires_32bit[t]&~i_is32) return 0;
4585     // Delay slots are not valid branch targets
4586     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4587     // Delay slots require additional processing, so do not match
4588     if(is_ds[t]) return 0;
4589   }
4590   else
4591   {
4592     int hr;
4593     for(hr=0;hr<HOST_REGS;hr++)
4594     {
4595       if(hr!=EXCLUDE_REG)
4596       {
4597         if(i_regmap[hr]>=0)
4598         {
4599           if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4600           {
4601             if((i_dirty>>hr)&1)
4602             {
4603               return 0;
4604             }
4605           }
4606         }
4607       }
4608     }
4609   }
4610   return 1;
4611 }
4612
4613 // Used when a branch jumps into the delay slot of another branch
4614 void ds_assemble_entry(int i)
4615 {
4616   int t=(ba[i]-start)>>2;
4617   if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4618   assem_debug("Assemble delay slot at %x\n",ba[i]);
4619   assem_debug("<->\n");
4620   if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
4621     wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4622   load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4623   address_generation(t,&regs[t],regs[t].regmap_entry);
4624   if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
4625     load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4626   cop1_usable=0;
4627   is_delayslot=0;
4628   switch(itype[t]) {
4629     case ALU:
4630       alu_assemble(t,&regs[t]);break;
4631     case IMM16:
4632       imm16_assemble(t,&regs[t]);break;
4633     case SHIFT:
4634       shift_assemble(t,&regs[t]);break;
4635     case SHIFTIMM:
4636       shiftimm_assemble(t,&regs[t]);break;
4637     case LOAD:
4638       load_assemble(t,&regs[t]);break;
4639     case LOADLR:
4640       loadlr_assemble(t,&regs[t]);break;
4641     case STORE:
4642       store_assemble(t,&regs[t]);break;
4643     case STORELR:
4644       storelr_assemble(t,&regs[t]);break;
4645     case COP0:
4646       cop0_assemble(t,&regs[t]);break;
4647     case COP1:
4648       cop1_assemble(t,&regs[t]);break;
4649     case C1LS:
4650       c1ls_assemble(t,&regs[t]);break;
4651     case COP2:
4652       cop2_assemble(t,&regs[t]);break;
4653     case C2LS:
4654       c2ls_assemble(t,&regs[t]);break;
4655     case C2OP:
4656       c2op_assemble(t,&regs[t]);break;
4657     case FCONV:
4658       fconv_assemble(t,&regs[t]);break;
4659     case FLOAT:
4660       float_assemble(t,&regs[t]);break;
4661     case FCOMP:
4662       fcomp_assemble(t,&regs[t]);break;
4663     case MULTDIV:
4664       multdiv_assemble(t,&regs[t]);break;
4665     case MOV:
4666       mov_assemble(t,&regs[t]);break;
4667     case SYSCALL:
4668     case HLECALL:
4669     case INTCALL:
4670     case SPAN:
4671     case UJUMP:
4672     case RJUMP:
4673     case CJUMP:
4674     case SJUMP:
4675     case FJUMP:
4676       printf("Jump in the delay slot.  This is probably a bug.\n");
4677   }
4678   store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4679   load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4680   if(internal_branch(regs[t].is32,ba[i]+4))
4681     assem_debug("branch: internal\n");
4682   else
4683     assem_debug("branch: external\n");
4684   assert(internal_branch(regs[t].is32,ba[i]+4));
4685   add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4686   emit_jmp(0);
4687 }
4688
4689 void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4690 {
4691   int count;
4692   int jaddr;
4693   int idle=0;
4694   if(itype[i]==RJUMP)
4695   {
4696     *adj=0;
4697   }
4698   //if(ba[i]>=start && ba[i]<(start+slen*4))
4699   if(internal_branch(branch_regs[i].is32,ba[i]))
4700   {
4701     int t=(ba[i]-start)>>2;
4702     if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4703     else *adj=ccadj[t];
4704   }
4705   else
4706   {
4707     *adj=0;
4708   }
4709   count=ccadj[i];
4710   if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4711     // Idle loop
4712     if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4713     idle=(int)out;
4714     //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4715     emit_andimm(HOST_CCREG,3,HOST_CCREG);
4716     jaddr=(int)out;
4717     emit_jmp(0);
4718   }
4719   else if(*adj==0||invert) {
4720     emit_addimm_and_set_flags(CLOCK_DIVIDER*(count+2),HOST_CCREG);
4721     jaddr=(int)out;
4722     emit_jns(0);
4723   }
4724   else
4725   {
4726     emit_cmpimm(HOST_CCREG,-2*(count+2));
4727     jaddr=(int)out;
4728     emit_jns(0);
4729   }
4730   add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4731 }
4732
4733 void do_ccstub(int n)
4734 {
4735   literal_pool(256);
4736   assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
4737   set_jump_target(stubs[n][1],(int)out);
4738   int i=stubs[n][4];
4739   if(stubs[n][6]==NULLDS) {
4740     // Delay slot instruction is nullified ("likely" branch)
4741     wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4742   }
4743   else if(stubs[n][6]!=TAKEN) {
4744     wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4745   }
4746   else {
4747     if(internal_branch(branch_regs[i].is32,ba[i]))
4748       wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4749   }
4750   if(stubs[n][5]!=-1)
4751   {
4752     // Save PC as return address
4753     emit_movimm(stubs[n][5],EAX);
4754     emit_writeword(EAX,(int)&pcaddr);
4755   }
4756   else
4757   {
4758     // Return address depends on which way the branch goes
4759     if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
4760     {
4761       int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4762       int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4763       int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4764       int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4765       if(rs1[i]==0)
4766       {
4767         s1l=s2l;s1h=s2h;
4768         s2l=s2h=-1;
4769       }
4770       else if(rs2[i]==0)
4771       {
4772         s2l=s2h=-1;
4773       }
4774       if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
4775         s1h=s2h=-1;
4776       }
4777       assert(s1l>=0);
4778       #ifdef DESTRUCTIVE_WRITEBACK
4779       if(rs1[i]) {
4780         if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
4781           emit_loadreg(rs1[i],s1l);
4782       }
4783       else {
4784         if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
4785           emit_loadreg(rs2[i],s1l);
4786       }
4787       if(s2l>=0)
4788         if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
4789           emit_loadreg(rs2[i],s2l);
4790       #endif
4791       int hr=0;
4792       int addr,alt,ntaddr;
4793       while(hr<HOST_REGS)
4794       {
4795         if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4796            (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4797            (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4798         {
4799           addr=hr++;break;
4800         }
4801         hr++;
4802       }
4803       while(hr<HOST_REGS)
4804       {
4805         if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4806            (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4807            (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4808         {
4809           alt=hr++;break;
4810         }
4811         hr++;
4812       }
4813       if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
4814       {
4815         while(hr<HOST_REGS)
4816         {
4817           if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4818              (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4819              (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4820           {
4821             ntaddr=hr;break;
4822           }
4823           hr++;
4824         }
4825         assert(hr<HOST_REGS);
4826       }
4827       if((opcode[i]&0x2f)==4) // BEQ
4828       {
4829         #ifdef HAVE_CMOV_IMM
4830         if(s1h<0) {
4831           if(s2l>=0) emit_cmp(s1l,s2l);
4832           else emit_test(s1l,s1l);
4833           emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
4834         }
4835         else
4836         #endif
4837         {
4838           emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4839           if(s1h>=0) {
4840             if(s2h>=0) emit_cmp(s1h,s2h);
4841             else emit_test(s1h,s1h);
4842             emit_cmovne_reg(alt,addr);
4843           }
4844           if(s2l>=0) emit_cmp(s1l,s2l);
4845           else emit_test(s1l,s1l);
4846           emit_cmovne_reg(alt,addr);
4847         }
4848       }
4849       if((opcode[i]&0x2f)==5) // BNE
4850       {
4851         #ifdef HAVE_CMOV_IMM
4852         if(s1h<0) {
4853           if(s2l>=0) emit_cmp(s1l,s2l);
4854           else emit_test(s1l,s1l);
4855           emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
4856         }
4857         else
4858         #endif
4859         {
4860           emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
4861           if(s1h>=0) {
4862             if(s2h>=0) emit_cmp(s1h,s2h);
4863             else emit_test(s1h,s1h);
4864             emit_cmovne_reg(alt,addr);
4865           }
4866           if(s2l>=0) emit_cmp(s1l,s2l);
4867           else emit_test(s1l,s1l);
4868           emit_cmovne_reg(alt,addr);
4869         }
4870       }
4871       if((opcode[i]&0x2f)==6) // BLEZ
4872       {
4873         //emit_movimm(ba[i],alt);
4874         //emit_movimm(start+i*4+8,addr);
4875         emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4876         emit_cmpimm(s1l,1);
4877         if(s1h>=0) emit_mov(addr,ntaddr);
4878         emit_cmovl_reg(alt,addr);
4879         if(s1h>=0) {
4880           emit_test(s1h,s1h);
4881           emit_cmovne_reg(ntaddr,addr);
4882           emit_cmovs_reg(alt,addr);
4883         }
4884       }
4885       if((opcode[i]&0x2f)==7) // BGTZ
4886       {
4887         //emit_movimm(ba[i],addr);
4888         //emit_movimm(start+i*4+8,ntaddr);
4889         emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
4890         emit_cmpimm(s1l,1);
4891         if(s1h>=0) emit_mov(addr,alt);
4892         emit_cmovl_reg(ntaddr,addr);
4893         if(s1h>=0) {
4894           emit_test(s1h,s1h);
4895           emit_cmovne_reg(alt,addr);
4896           emit_cmovs_reg(ntaddr,addr);
4897         }
4898       }
4899       if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
4900       {
4901         //emit_movimm(ba[i],alt);
4902         //emit_movimm(start+i*4+8,addr);
4903         emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4904         if(s1h>=0) emit_test(s1h,s1h);
4905         else emit_test(s1l,s1l);
4906         emit_cmovs_reg(alt,addr);
4907       }
4908       if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
4909       {
4910         //emit_movimm(ba[i],addr);
4911         //emit_movimm(start+i*4+8,alt);
4912         emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4913         if(s1h>=0) emit_test(s1h,s1h);
4914         else emit_test(s1l,s1l);
4915         emit_cmovs_reg(alt,addr);
4916       }
4917       if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
4918         if(source[i]&0x10000) // BC1T
4919         {
4920           //emit_movimm(ba[i],alt);
4921           //emit_movimm(start+i*4+8,addr);
4922           emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4923           emit_testimm(s1l,0x800000);
4924           emit_cmovne_reg(alt,addr);
4925         }
4926         else // BC1F
4927         {
4928           //emit_movimm(ba[i],addr);
4929           //emit_movimm(start+i*4+8,alt);
4930           emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4931           emit_testimm(s1l,0x800000);
4932           emit_cmovne_reg(alt,addr);
4933         }
4934       }
4935       emit_writeword(addr,(int)&pcaddr);
4936     }
4937     else
4938     if(itype[i]==RJUMP)
4939     {
4940       int r=get_reg(branch_regs[i].regmap,rs1[i]);
4941       if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
4942         r=get_reg(branch_regs[i].regmap,RTEMP);
4943       }
4944       emit_writeword(r,(int)&pcaddr);
4945     }
4946     else {printf("Unknown branch type in do_ccstub\n");exit(1);}
4947   }
4948   // Update cycle count
4949   assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
4950   if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
4951   emit_call((int)cc_interrupt);
4952   if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
4953   if(stubs[n][6]==TAKEN) {
4954     if(internal_branch(branch_regs[i].is32,ba[i]))
4955       load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
4956     else if(itype[i]==RJUMP) {
4957       if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
4958         emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
4959       else
4960         emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
4961     }
4962   }else if(stubs[n][6]==NOTTAKEN) {
4963     if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
4964     else load_all_regs(branch_regs[i].regmap);
4965   }else if(stubs[n][6]==NULLDS) {
4966     // Delay slot instruction is nullified ("likely" branch)
4967     if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
4968     else load_all_regs(regs[i].regmap);
4969   }else{
4970     load_all_regs(branch_regs[i].regmap);
4971   }
4972   emit_jmp(stubs[n][2]); // return address
4973
4974   /* This works but uses a lot of memory...
4975   emit_readword((int)&last_count,ECX);
4976   emit_add(HOST_CCREG,ECX,EAX);
4977   emit_writeword(EAX,(int)&Count);
4978   emit_call((int)gen_interupt);
4979   emit_readword((int)&Count,HOST_CCREG);
4980   emit_readword((int)&next_interupt,EAX);
4981   emit_readword((int)&pending_exception,EBX);
4982   emit_writeword(EAX,(int)&last_count);
4983   emit_sub(HOST_CCREG,EAX,HOST_CCREG);
4984   emit_test(EBX,EBX);
4985   int jne_instr=(int)out;
4986   emit_jne(0);
4987   if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
4988   load_all_regs(branch_regs[i].regmap);
4989   emit_jmp(stubs[n][2]); // return address
4990   set_jump_target(jne_instr,(int)out);
4991   emit_readword((int)&pcaddr,EAX);
4992   // Call get_addr_ht instead of doing the hash table here.
4993   // This code is executed infrequently and takes up a lot of space
4994   // so smaller is better.
4995   emit_storereg(CCREG,HOST_CCREG);
4996   emit_pushreg(EAX);
4997   emit_call((int)get_addr_ht);
4998   emit_loadreg(CCREG,HOST_CCREG);
4999   emit_addimm(ESP,4,ESP);
5000   emit_jmpreg(EAX);*/
5001 }
5002
5003 add_to_linker(int addr,int target,int ext)
5004 {
5005   link_addr[linkcount][0]=addr;
5006   link_addr[linkcount][1]=target;
5007   link_addr[linkcount][2]=ext;
5008   linkcount++;
5009 }
5010
5011 void ujump_assemble(int i,struct regstat *i_regs)
5012 {
5013   signed char *i_regmap=i_regs->regmap;
5014   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5015   address_generation(i+1,i_regs,regs[i].regmap_entry);
5016   #ifdef REG_PREFETCH
5017   int temp=get_reg(branch_regs[i].regmap,PTEMP);
5018   if(rt1[i]==31&&temp>=0)
5019   {
5020     int return_address=start+i*4+8;
5021     if(get_reg(branch_regs[i].regmap,31)>0)
5022     if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5023   }
5024   #endif
5025   ds_assemble(i+1,i_regs);
5026   uint64_t bc_unneeded=branch_regs[i].u;
5027   uint64_t bc_unneeded_upper=branch_regs[i].uu;
5028   bc_unneeded|=1|(1LL<<rt1[i]);
5029   bc_unneeded_upper|=1|(1LL<<rt1[i]);
5030   wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5031                 bc_unneeded,bc_unneeded_upper);
5032   load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5033   if(rt1[i]==31) {
5034     int rt;
5035     unsigned int return_address;
5036     assert(rt1[i+1]!=31);
5037     assert(rt2[i+1]!=31);
5038     rt=get_reg(branch_regs[i].regmap,31);
5039     assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5040     //assert(rt>=0);
5041     return_address=start+i*4+8;
5042     if(rt>=0) {
5043       #ifdef USE_MINI_HT
5044       if(internal_branch(branch_regs[i].is32,return_address)) {
5045         int temp=rt+1;
5046         if(temp==EXCLUDE_REG||temp>=HOST_REGS||
5047            branch_regs[i].regmap[temp]>=0)
5048         {
5049           temp=get_reg(branch_regs[i].regmap,-1);
5050         }
5051         #ifdef HOST_TEMPREG
5052         if(temp<0) temp=HOST_TEMPREG;
5053         #endif
5054         if(temp>=0) do_miniht_insert(return_address,rt,temp);
5055         else emit_movimm(return_address,rt);
5056       }
5057       else
5058       #endif
5059       {
5060         #ifdef REG_PREFETCH
5061         if(temp>=0)
5062         {
5063           if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5064         }
5065         #endif
5066         emit_movimm(return_address,rt); // PC into link register
5067         #ifdef IMM_PREFETCH
5068         emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5069         #endif
5070       }
5071     }
5072   }
5073   int cc,adj;
5074   cc=get_reg(branch_regs[i].regmap,CCREG);
5075   assert(cc==HOST_CCREG);
5076   store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5077   #ifdef REG_PREFETCH
5078   if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5079   #endif
5080   do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5081   if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5082   load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5083   if(internal_branch(branch_regs[i].is32,ba[i]))
5084     assem_debug("branch: internal\n");
5085   else
5086     assem_debug("branch: external\n");
5087   if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5088     ds_assemble_entry(i);
5089   }
5090   else {
5091     add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5092     emit_jmp(0);
5093   }
5094 }
5095
5096 void rjump_assemble(int i,struct regstat *i_regs)
5097 {
5098   signed char *i_regmap=i_regs->regmap;
5099   int temp;
5100   int rs,cc,adj;
5101   rs=get_reg(branch_regs[i].regmap,rs1[i]);
5102   assert(rs>=0);
5103   if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5104     // Delay slot abuse, make a copy of the branch address register
5105     temp=get_reg(branch_regs[i].regmap,RTEMP);
5106     assert(temp>=0);
5107     assert(regs[i].regmap[temp]==RTEMP);
5108     emit_mov(rs,temp);
5109     rs=temp;
5110   }
5111   address_generation(i+1,i_regs,regs[i].regmap_entry);
5112   #ifdef REG_PREFETCH
5113   if(rt1[i]==31)
5114   {
5115     if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5116       int return_address=start+i*4+8;
5117       if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5118     }
5119   }
5120   #endif
5121   #ifdef USE_MINI_HT
5122   if(rs1[i]==31) {
5123     int rh=get_reg(regs[i].regmap,RHASH);
5124     if(rh>=0) do_preload_rhash(rh);
5125   }
5126   #endif
5127   ds_assemble(i+1,i_regs);
5128   uint64_t bc_unneeded=branch_regs[i].u;
5129   uint64_t bc_unneeded_upper=branch_regs[i].uu;
5130   bc_unneeded|=1|(1LL<<rt1[i]);
5131   bc_unneeded_upper|=1|(1LL<<rt1[i]);
5132   bc_unneeded&=~(1LL<<rs1[i]);
5133   wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5134                 bc_unneeded,bc_unneeded_upper);
5135   load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5136   if(rt1[i]!=0) {
5137     int rt,return_address;
5138     assert(rt1[i+1]!=rt1[i]);
5139     assert(rt2[i+1]!=rt1[i]);
5140     rt=get_reg(branch_regs[i].regmap,rt1[i]);
5141     assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5142     assert(rt>=0);
5143     return_address=start+i*4+8;
5144     #ifdef REG_PREFETCH
5145     if(temp>=0)
5146     {
5147       if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5148     }
5149     #endif
5150     emit_movimm(return_address,rt); // PC into link register
5151     #ifdef IMM_PREFETCH
5152     emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5153     #endif
5154   }
5155   cc=get_reg(branch_regs[i].regmap,CCREG);
5156   assert(cc==HOST_CCREG);
5157   #ifdef USE_MINI_HT
5158   int rh=get_reg(branch_regs[i].regmap,RHASH);
5159   int ht=get_reg(branch_regs[i].regmap,RHTBL);
5160   if(rs1[i]==31) {
5161     if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5162     do_preload_rhtbl(ht);
5163     do_rhash(rs,rh);
5164   }
5165   #endif
5166   store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5167   #ifdef DESTRUCTIVE_WRITEBACK
5168   if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5169     if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5170       emit_loadreg(rs1[i],rs);
5171     }
5172   }
5173   #endif
5174   #ifdef REG_PREFETCH
5175   if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5176   #endif
5177   #ifdef USE_MINI_HT
5178   if(rs1[i]==31) {
5179     do_miniht_load(ht,rh);
5180   }
5181   #endif
5182   //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5183   //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5184   //assert(adj==0);
5185   emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5186   add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5187   emit_jns(0);
5188   //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5189   #ifdef USE_MINI_HT
5190   if(rs1[i]==31) {
5191     do_miniht_jump(rs,rh,ht);
5192   }
5193   else
5194   #endif
5195   {
5196     //if(rs!=EAX) emit_mov(rs,EAX);
5197     //emit_jmp((int)jump_vaddr_eax);
5198     emit_jmp(jump_vaddr_reg[rs]);
5199   }
5200   /* Check hash table
5201   temp=!rs;
5202   emit_mov(rs,temp);
5203   emit_shrimm(rs,16,rs);
5204   emit_xor(temp,rs,rs);
5205   emit_movzwl_reg(rs,rs);
5206   emit_shlimm(rs,4,rs);
5207   emit_cmpmem_indexed((int)hash_table,rs,temp);
5208   emit_jne((int)out+14);
5209   emit_readword_indexed((int)hash_table+4,rs,rs);
5210   emit_jmpreg(rs);
5211   emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5212   emit_addimm_no_flags(8,rs);
5213   emit_jeq((int)out-17);
5214   // No hit on hash table, call compiler
5215   emit_pushreg(temp);
5216 //DEBUG >
5217 #ifdef DEBUG_CYCLE_COUNT
5218   emit_readword((int)&last_count,ECX);
5219   emit_add(HOST_CCREG,ECX,HOST_CCREG);
5220   emit_readword((int)&next_interupt,ECX);
5221   emit_writeword(HOST_CCREG,(int)&Count);
5222   emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5223   emit_writeword(ECX,(int)&last_count);
5224 #endif
5225 //DEBUG <
5226   emit_storereg(CCREG,HOST_CCREG);
5227   emit_call((int)get_addr);
5228   emit_loadreg(CCREG,HOST_CCREG);
5229   emit_addimm(ESP,4,ESP);
5230   emit_jmpreg(EAX);*/
5231   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5232   if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5233   #endif
5234 }
5235
5236 void cjump_assemble(int i,struct regstat *i_regs)
5237 {
5238   signed char *i_regmap=i_regs->regmap;
5239   int cc;
5240   int match;
5241   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5242   assem_debug("match=%d\n",match);
5243   int s1h,s1l,s2h,s2l;
5244   int prev_cop1_usable=cop1_usable;
5245   int unconditional=0,nop=0;
5246   int only32=0;
5247   int ooo=1;
5248   int invert=0;
5249   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5250   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5251   if(likely[i]) ooo=0;
5252   if(!match) invert=1;
5253   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5254   if(i>(ba[i]-start)>>2) invert=1;
5255   #endif
5256
5257   if(ooo)
5258     if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
5259        (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1])))
5260   {
5261     // Write-after-read dependency prevents out of order execution
5262     // First test branch condition, then execute delay slot, then branch
5263     ooo=0;
5264   }
5265
5266   if(ooo) {
5267     s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5268     s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5269     s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5270     s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5271   }
5272   else {
5273     s1l=get_reg(i_regmap,rs1[i]);
5274     s1h=get_reg(i_regmap,rs1[i]|64);
5275     s2l=get_reg(i_regmap,rs2[i]);
5276     s2h=get_reg(i_regmap,rs2[i]|64);
5277   }
5278   if(rs1[i]==0&&rs2[i]==0)
5279   {
5280     if(opcode[i]&1) nop=1;
5281     else unconditional=1;
5282     //assert(opcode[i]!=5);
5283     //assert(opcode[i]!=7);
5284     //assert(opcode[i]!=0x15);
5285     //assert(opcode[i]!=0x17);
5286   }
5287   else if(rs1[i]==0)
5288   {
5289     s1l=s2l;s1h=s2h;
5290     s2l=s2h=-1;
5291     only32=(regs[i].was32>>rs2[i])&1;
5292   }
5293   else if(rs2[i]==0)
5294   {
5295     s2l=s2h=-1;
5296     only32=(regs[i].was32>>rs1[i])&1;
5297   }
5298   else {
5299     only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5300   }
5301
5302   if(ooo) {
5303     // Out of order execution (delay slot first)
5304     //printf("OOOE\n");
5305     address_generation(i+1,i_regs,regs[i].regmap_entry);
5306     ds_assemble(i+1,i_regs);
5307     int adj;
5308     uint64_t bc_unneeded=branch_regs[i].u;
5309     uint64_t bc_unneeded_upper=branch_regs[i].uu;
5310     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5311     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5312     bc_unneeded|=1;
5313     bc_unneeded_upper|=1;
5314     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5315                   bc_unneeded,bc_unneeded_upper);
5316     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5317     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5318     cc=get_reg(branch_regs[i].regmap,CCREG);
5319     assert(cc==HOST_CCREG);
5320     if(unconditional)
5321       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5322     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5323     //assem_debug("cycle count (adj)\n");
5324     if(unconditional) {
5325       do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5326       if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5327         if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5328         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5329         if(internal)
5330           assem_debug("branch: internal\n");
5331         else
5332           assem_debug("branch: external\n");
5333         if(internal&&is_ds[(ba[i]-start)>>2]) {
5334           ds_assemble_entry(i);
5335         }
5336         else {
5337           add_to_linker((int)out,ba[i],internal);
5338           emit_jmp(0);
5339         }
5340         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5341         if(((u_int)out)&7) emit_addnop(0);
5342         #endif
5343       }
5344     }
5345     else if(nop) {
5346       emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5347       int jaddr=(int)out;
5348       emit_jns(0);
5349       add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5350     }
5351     else {
5352       int taken=0,nottaken=0,nottaken1=0;
5353       do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5354       if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5355       if(!only32)
5356       {
5357         assert(s1h>=0);
5358         if(opcode[i]==4) // BEQ
5359         {
5360           if(s2h>=0) emit_cmp(s1h,s2h);
5361           else emit_test(s1h,s1h);
5362           nottaken1=(int)out;
5363           emit_jne(1);
5364         }
5365         if(opcode[i]==5) // BNE
5366         {
5367           if(s2h>=0) emit_cmp(s1h,s2h);
5368           else emit_test(s1h,s1h);
5369           if(invert) taken=(int)out;
5370           else add_to_linker((int)out,ba[i],internal);
5371           emit_jne(0);
5372         }
5373         if(opcode[i]==6) // BLEZ
5374         {
5375           emit_test(s1h,s1h);
5376           if(invert) taken=(int)out;
5377           else add_to_linker((int)out,ba[i],internal);
5378           emit_js(0);
5379           nottaken1=(int)out;
5380           emit_jne(1);
5381         }
5382         if(opcode[i]==7) // BGTZ
5383         {
5384           emit_test(s1h,s1h);
5385           nottaken1=(int)out;
5386           emit_js(1);
5387           if(invert) taken=(int)out;
5388           else add_to_linker((int)out,ba[i],internal);
5389           emit_jne(0);
5390         }
5391       } // if(!only32)
5392
5393       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5394       assert(s1l>=0);
5395       if(opcode[i]==4) // BEQ
5396       {
5397         if(s2l>=0) emit_cmp(s1l,s2l);
5398         else emit_test(s1l,s1l);
5399         if(invert){
5400           nottaken=(int)out;
5401           emit_jne(1);
5402         }else{
5403           add_to_linker((int)out,ba[i],internal);
5404           emit_jeq(0);
5405         }
5406       }
5407       if(opcode[i]==5) // BNE
5408       {
5409         if(s2l>=0) emit_cmp(s1l,s2l);
5410         else emit_test(s1l,s1l);
5411         if(invert){
5412           nottaken=(int)out;
5413           emit_jeq(1);
5414         }else{
5415           add_to_linker((int)out,ba[i],internal);
5416           emit_jne(0);
5417         }
5418       }
5419       if(opcode[i]==6) // BLEZ
5420       {
5421         emit_cmpimm(s1l,1);
5422         if(invert){
5423           nottaken=(int)out;
5424           emit_jge(1);
5425         }else{
5426           add_to_linker((int)out,ba[i],internal);
5427           emit_jl(0);
5428         }
5429       }
5430       if(opcode[i]==7) // BGTZ
5431       {
5432         emit_cmpimm(s1l,1);
5433         if(invert){
5434           nottaken=(int)out;
5435           emit_jl(1);
5436         }else{
5437           add_to_linker((int)out,ba[i],internal);
5438           emit_jge(0);
5439         }
5440       }
5441       if(invert) {
5442         if(taken) set_jump_target(taken,(int)out);
5443         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5444         if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5445           if(adj) {
5446             emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5447             add_to_linker((int)out,ba[i],internal);
5448           }else{
5449             emit_addnop(13);
5450             add_to_linker((int)out,ba[i],internal*2);
5451           }
5452           emit_jmp(0);
5453         }else
5454         #endif
5455         {
5456           if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5457           store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5458           load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5459           if(internal)
5460             assem_debug("branch: internal\n");
5461           else
5462             assem_debug("branch: external\n");
5463           if(internal&&is_ds[(ba[i]-start)>>2]) {
5464             ds_assemble_entry(i);
5465           }
5466           else {
5467             add_to_linker((int)out,ba[i],internal);
5468             emit_jmp(0);
5469           }
5470         }
5471         set_jump_target(nottaken,(int)out);
5472       }
5473
5474       if(nottaken1) set_jump_target(nottaken1,(int)out);
5475       if(adj) {
5476         if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5477       }
5478     } // (!unconditional)
5479   } // if(ooo)
5480   else
5481   {
5482     // In-order execution (branch first)
5483     //if(likely[i]) printf("IOL\n");
5484     //else
5485     //printf("IOE\n");
5486     int taken=0,nottaken=0,nottaken1=0;
5487     if(!unconditional&&!nop) {
5488       if(!only32)
5489       {
5490         assert(s1h>=0);
5491         if((opcode[i]&0x2f)==4) // BEQ
5492         {
5493           if(s2h>=0) emit_cmp(s1h,s2h);
5494           else emit_test(s1h,s1h);
5495           nottaken1=(int)out;
5496           emit_jne(2);
5497         }
5498         if((opcode[i]&0x2f)==5) // BNE
5499         {
5500           if(s2h>=0) emit_cmp(s1h,s2h);
5501           else emit_test(s1h,s1h);
5502           taken=(int)out;
5503           emit_jne(1);
5504         }
5505         if((opcode[i]&0x2f)==6) // BLEZ
5506         {
5507           emit_test(s1h,s1h);
5508           taken=(int)out;
5509           emit_js(1);
5510           nottaken1=(int)out;
5511           emit_jne(2);
5512         }
5513         if((opcode[i]&0x2f)==7) // BGTZ
5514         {
5515           emit_test(s1h,s1h);
5516           nottaken1=(int)out;
5517           emit_js(2);
5518           taken=(int)out;
5519           emit_jne(1);
5520         }
5521       } // if(!only32)
5522
5523       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5524       assert(s1l>=0);
5525       if((opcode[i]&0x2f)==4) // BEQ
5526       {
5527         if(s2l>=0) emit_cmp(s1l,s2l);
5528         else emit_test(s1l,s1l);
5529         nottaken=(int)out;
5530         emit_jne(2);
5531       }
5532       if((opcode[i]&0x2f)==5) // BNE
5533       {
5534         if(s2l>=0) emit_cmp(s1l,s2l);
5535         else emit_test(s1l,s1l);
5536         nottaken=(int)out;
5537         emit_jeq(2);
5538       }
5539       if((opcode[i]&0x2f)==6) // BLEZ
5540       {
5541         emit_cmpimm(s1l,1);
5542         nottaken=(int)out;
5543         emit_jge(2);
5544       }
5545       if((opcode[i]&0x2f)==7) // BGTZ
5546       {
5547         emit_cmpimm(s1l,1);
5548         nottaken=(int)out;
5549         emit_jl(2);
5550       }
5551     } // if(!unconditional)
5552     int adj;
5553     uint64_t ds_unneeded=branch_regs[i].u;
5554     uint64_t ds_unneeded_upper=branch_regs[i].uu;
5555     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5556     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5557     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5558     ds_unneeded|=1;
5559     ds_unneeded_upper|=1;
5560     // branch taken
5561     if(!nop) {
5562       if(taken) set_jump_target(taken,(int)out);
5563       assem_debug("1:\n");
5564       wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5565                     ds_unneeded,ds_unneeded_upper);
5566       // load regs
5567       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5568       address_generation(i+1,&branch_regs[i],0);
5569       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5570       ds_assemble(i+1,&branch_regs[i]);
5571       cc=get_reg(branch_regs[i].regmap,CCREG);
5572       if(cc==-1) {
5573         emit_loadreg(CCREG,cc=HOST_CCREG);
5574         // CHECK: Is the following instruction (fall thru) allocated ok?
5575       }
5576       assert(cc==HOST_CCREG);
5577       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5578       do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5579       assem_debug("cycle count (adj)\n");
5580       if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5581       load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5582       if(internal)
5583         assem_debug("branch: internal\n");
5584       else
5585         assem_debug("branch: external\n");
5586       if(internal&&is_ds[(ba[i]-start)>>2]) {
5587         ds_assemble_entry(i);
5588       }
5589       else {
5590         add_to_linker((int)out,ba[i],internal);
5591         emit_jmp(0);
5592       }
5593     }
5594     // branch not taken
5595     cop1_usable=prev_cop1_usable;
5596     if(!unconditional) {
5597       if(nottaken1) set_jump_target(nottaken1,(int)out);
5598       set_jump_target(nottaken,(int)out);
5599       assem_debug("2:\n");
5600       if(!likely[i]) {
5601         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5602                       ds_unneeded,ds_unneeded_upper);
5603         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5604         address_generation(i+1,&branch_regs[i],0);
5605         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5606         ds_assemble(i+1,&branch_regs[i]);
5607       }
5608       cc=get_reg(branch_regs[i].regmap,CCREG);
5609       if(cc==-1&&!likely[i]) {
5610         // Cycle count isn't in a register, temporarily load it then write it out
5611         emit_loadreg(CCREG,HOST_CCREG);
5612         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5613         int jaddr=(int)out;
5614         emit_jns(0);
5615         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5616         emit_storereg(CCREG,HOST_CCREG);
5617       }
5618       else{
5619         cc=get_reg(i_regmap,CCREG);
5620         assert(cc==HOST_CCREG);
5621         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5622         int jaddr=(int)out;
5623         emit_jns(0);
5624         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5625       }
5626     }
5627   }
5628 }
5629
5630 void sjump_assemble(int i,struct regstat *i_regs)
5631 {
5632   signed char *i_regmap=i_regs->regmap;
5633   int cc;
5634   int match;
5635   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5636   assem_debug("smatch=%d\n",match);
5637   int s1h,s1l;
5638   int prev_cop1_usable=cop1_usable;
5639   int unconditional=0,nevertaken=0;
5640   int only32=0;
5641   int ooo=1;
5642   int invert=0;
5643   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5644   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5645   if(likely[i]) ooo=0;
5646   if(!match) invert=1;
5647   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5648   if(i>(ba[i]-start)>>2) invert=1;
5649   #endif
5650
5651   //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
5652   //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
5653
5654   if(ooo) {
5655     if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))
5656     {
5657       // Write-after-read dependency prevents out of order execution
5658       // First test branch condition, then execute delay slot, then branch
5659       ooo=0;
5660     }
5661     if(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))
5662       // BxxZAL $ra is available to delay insn, so do it in order
5663       ooo=0;
5664   }
5665
5666   if(ooo) {
5667     s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5668     s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5669   }
5670   else {
5671     s1l=get_reg(i_regmap,rs1[i]);
5672     s1h=get_reg(i_regmap,rs1[i]|64);
5673   }
5674   if(rs1[i]==0)
5675   {
5676     if(opcode2[i]&1) unconditional=1;
5677     else nevertaken=1;
5678     // These are never taken (r0 is never less than zero)
5679     //assert(opcode2[i]!=0);
5680     //assert(opcode2[i]!=2);
5681     //assert(opcode2[i]!=0x10);
5682     //assert(opcode2[i]!=0x12);
5683   }
5684   else {
5685     only32=(regs[i].was32>>rs1[i])&1;
5686   }
5687
5688   if(ooo) {
5689     // Out of order execution (delay slot first)
5690     //printf("OOOE\n");
5691     address_generation(i+1,i_regs,regs[i].regmap_entry);
5692     ds_assemble(i+1,i_regs);
5693     int adj;
5694     uint64_t bc_unneeded=branch_regs[i].u;
5695     uint64_t bc_unneeded_upper=branch_regs[i].uu;
5696     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5697     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5698     bc_unneeded|=1;
5699     bc_unneeded_upper|=1;
5700     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5701                   bc_unneeded,bc_unneeded_upper);
5702     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5703     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5704     if(rt1[i]==31) {
5705       int rt,return_address;
5706       rt=get_reg(branch_regs[i].regmap,31);
5707       assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5708       if(rt>=0) {
5709         // Save the PC even if the branch is not taken
5710         return_address=start+i*4+8;
5711         emit_movimm(return_address,rt); // PC into link register
5712         #ifdef IMM_PREFETCH
5713         if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5714         #endif
5715       }
5716     }
5717     cc=get_reg(branch_regs[i].regmap,CCREG);
5718     assert(cc==HOST_CCREG);
5719     if(unconditional)
5720       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5721     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5722     assem_debug("cycle count (adj)\n");
5723     if(unconditional) {
5724       do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5725       if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5726         if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5727         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5728         if(internal)
5729           assem_debug("branch: internal\n");
5730         else
5731           assem_debug("branch: external\n");
5732         if(internal&&is_ds[(ba[i]-start)>>2]) {
5733           ds_assemble_entry(i);
5734         }
5735         else {
5736           add_to_linker((int)out,ba[i],internal);
5737           emit_jmp(0);
5738         }
5739         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5740         if(((u_int)out)&7) emit_addnop(0);
5741         #endif
5742       }
5743     }
5744     else if(nevertaken) {
5745       emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5746       int jaddr=(int)out;
5747       emit_jns(0);
5748       add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5749     }
5750     else {
5751       int nottaken=0;
5752       do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5753       if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5754       if(!only32)
5755       {
5756         assert(s1h>=0);
5757         if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5758         {
5759           emit_test(s1h,s1h);
5760           if(invert){
5761             nottaken=(int)out;
5762             emit_jns(1);
5763           }else{
5764             add_to_linker((int)out,ba[i],internal);
5765             emit_js(0);
5766           }
5767         }
5768         if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5769         {
5770           emit_test(s1h,s1h);
5771           if(invert){
5772             nottaken=(int)out;
5773             emit_js(1);
5774           }else{
5775             add_to_linker((int)out,ba[i],internal);
5776             emit_jns(0);
5777           }
5778         }
5779       } // if(!only32)
5780       else
5781       {
5782         assert(s1l>=0);
5783         if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5784         {
5785           emit_test(s1l,s1l);
5786           if(invert){
5787             nottaken=(int)out;
5788             emit_jns(1);
5789           }else{
5790             add_to_linker((int)out,ba[i],internal);
5791             emit_js(0);
5792           }
5793         }
5794         if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5795         {
5796           emit_test(s1l,s1l);
5797           if(invert){
5798             nottaken=(int)out;
5799             emit_js(1);
5800           }else{
5801             add_to_linker((int)out,ba[i],internal);
5802             emit_jns(0);
5803           }
5804         }
5805       } // if(!only32)
5806
5807       if(invert) {
5808         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5809         if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5810           if(adj) {
5811             emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5812             add_to_linker((int)out,ba[i],internal);
5813           }else{
5814             emit_addnop(13);
5815             add_to_linker((int)out,ba[i],internal*2);
5816           }
5817           emit_jmp(0);
5818         }else
5819         #endif
5820         {
5821           if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5822           store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5823           load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5824           if(internal)
5825             assem_debug("branch: internal\n");
5826           else
5827             assem_debug("branch: external\n");
5828           if(internal&&is_ds[(ba[i]-start)>>2]) {
5829             ds_assemble_entry(i);
5830           }
5831           else {
5832             add_to_linker((int)out,ba[i],internal);
5833             emit_jmp(0);
5834           }
5835         }
5836         set_jump_target(nottaken,(int)out);
5837       }
5838
5839       if(adj) {
5840         if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5841       }
5842     } // (!unconditional)
5843   } // if(ooo)
5844   else
5845   {
5846     // In-order execution (branch first)
5847     //printf("IOE\n");
5848     int nottaken=0;
5849     if(rt1[i]==31) {
5850       int rt,return_address;
5851       rt=get_reg(branch_regs[i].regmap,31);
5852       if(rt>=0) {
5853         // Save the PC even if the branch is not taken
5854         return_address=start+i*4+8;
5855         emit_movimm(return_address,rt); // PC into link register
5856         #ifdef IMM_PREFETCH
5857         emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5858         #endif
5859       }
5860     }
5861     if(!unconditional) {
5862       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5863       if(!only32)
5864       {
5865         assert(s1h>=0);
5866         if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
5867         {
5868           emit_test(s1h,s1h);
5869           nottaken=(int)out;
5870           emit_jns(1);
5871         }
5872         if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
5873         {
5874           emit_test(s1h,s1h);
5875           nottaken=(int)out;
5876           emit_js(1);
5877         }
5878       } // if(!only32)
5879       else
5880       {
5881         assert(s1l>=0);
5882         if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
5883         {
5884           emit_test(s1l,s1l);
5885           nottaken=(int)out;
5886           emit_jns(1);
5887         }
5888         if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
5889         {
5890           emit_test(s1l,s1l);
5891           nottaken=(int)out;
5892           emit_js(1);
5893         }
5894       }
5895     } // if(!unconditional)
5896     int adj;
5897     uint64_t ds_unneeded=branch_regs[i].u;
5898     uint64_t ds_unneeded_upper=branch_regs[i].uu;
5899     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5900     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5901     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5902     ds_unneeded|=1;
5903     ds_unneeded_upper|=1;
5904     // branch taken
5905     if(!nevertaken) {
5906       //assem_debug("1:\n");
5907       wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5908                     ds_unneeded,ds_unneeded_upper);
5909       // load regs
5910       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5911       address_generation(i+1,&branch_regs[i],0);
5912       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5913       ds_assemble(i+1,&branch_regs[i]);
5914       cc=get_reg(branch_regs[i].regmap,CCREG);
5915       if(cc==-1) {
5916         emit_loadreg(CCREG,cc=HOST_CCREG);
5917         // CHECK: Is the following instruction (fall thru) allocated ok?
5918       }
5919       assert(cc==HOST_CCREG);
5920       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5921       do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5922       assem_debug("cycle count (adj)\n");
5923       if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5924       load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5925       if(internal)
5926         assem_debug("branch: internal\n");
5927       else
5928         assem_debug("branch: external\n");
5929       if(internal&&is_ds[(ba[i]-start)>>2]) {
5930         ds_assemble_entry(i);
5931       }
5932       else {
5933         add_to_linker((int)out,ba[i],internal);
5934         emit_jmp(0);
5935       }
5936     }
5937     // branch not taken
5938     cop1_usable=prev_cop1_usable;
5939     if(!unconditional) {
5940       set_jump_target(nottaken,(int)out);
5941       assem_debug("1:\n");
5942       if(!likely[i]) {
5943         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5944                       ds_unneeded,ds_unneeded_upper);
5945         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5946         address_generation(i+1,&branch_regs[i],0);
5947         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5948         ds_assemble(i+1,&branch_regs[i]);
5949       }
5950       cc=get_reg(branch_regs[i].regmap,CCREG);
5951       if(cc==-1&&!likely[i]) {
5952         // Cycle count isn't in a register, temporarily load it then write it out
5953         emit_loadreg(CCREG,HOST_CCREG);
5954         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5955         int jaddr=(int)out;
5956         emit_jns(0);
5957         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5958         emit_storereg(CCREG,HOST_CCREG);
5959       }
5960       else{
5961         cc=get_reg(i_regmap,CCREG);
5962         assert(cc==HOST_CCREG);
5963         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5964         int jaddr=(int)out;
5965         emit_jns(0);
5966         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5967       }
5968     }
5969   }
5970 }
5971
5972 void fjump_assemble(int i,struct regstat *i_regs)
5973 {
5974   signed char *i_regmap=i_regs->regmap;
5975   int cc;
5976   int match;
5977   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5978   assem_debug("fmatch=%d\n",match);
5979   int fs,cs;
5980   int eaddr;
5981   int ooo=1;
5982   int invert=0;
5983   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5984   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5985   if(likely[i]) ooo=0;
5986   if(!match) invert=1;
5987   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5988   if(i>(ba[i]-start)>>2) invert=1;
5989   #endif
5990
5991   if(ooo)
5992     if(itype[i+1]==FCOMP)
5993   {
5994     // Write-after-read dependency prevents out of order execution
5995     // First test branch condition, then execute delay slot, then branch
5996     ooo=0;
5997   }
5998
5999   if(ooo) {
6000     fs=get_reg(branch_regs[i].regmap,FSREG);
6001     address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
6002   }
6003   else {
6004     fs=get_reg(i_regmap,FSREG);
6005   }
6006
6007   // Check cop1 unusable
6008   if(!cop1_usable) {
6009     cs=get_reg(i_regmap,CSREG);
6010     assert(cs>=0);
6011     emit_testimm(cs,0x20000000);
6012     eaddr=(int)out;
6013     emit_jeq(0);
6014     add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
6015     cop1_usable=1;
6016   }
6017
6018   if(ooo) {
6019     // Out of order execution (delay slot first)
6020     //printf("OOOE\n");
6021     ds_assemble(i+1,i_regs);
6022     int adj;
6023     uint64_t bc_unneeded=branch_regs[i].u;
6024     uint64_t bc_unneeded_upper=branch_regs[i].uu;
6025     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6026     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
6027     bc_unneeded|=1;
6028     bc_unneeded_upper|=1;
6029     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6030                   bc_unneeded,bc_unneeded_upper);
6031     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
6032     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6033     cc=get_reg(branch_regs[i].regmap,CCREG);
6034     assert(cc==HOST_CCREG);
6035     do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6036     assem_debug("cycle count (adj)\n");
6037     if(1) {
6038       int nottaken=0;
6039       if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6040       if(1) {
6041         assert(fs>=0);
6042         emit_testimm(fs,0x800000);
6043         if(source[i]&0x10000) // BC1T
6044         {
6045           if(invert){
6046             nottaken=(int)out;
6047             emit_jeq(1);
6048           }else{
6049             add_to_linker((int)out,ba[i],internal);
6050             emit_jne(0);
6051           }
6052         }
6053         else // BC1F
6054           if(invert){
6055             nottaken=(int)out;
6056             emit_jne(1);
6057           }else{
6058             add_to_linker((int)out,ba[i],internal);
6059             emit_jeq(0);
6060           }
6061         {
6062         }
6063       } // if(!only32)
6064
6065       if(invert) {
6066         if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
6067         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6068         else if(match) emit_addnop(13);
6069         #endif
6070         store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6071         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6072         if(internal)
6073           assem_debug("branch: internal\n");
6074         else
6075           assem_debug("branch: external\n");
6076         if(internal&&is_ds[(ba[i]-start)>>2]) {
6077           ds_assemble_entry(i);
6078         }
6079         else {
6080           add_to_linker((int)out,ba[i],internal);
6081           emit_jmp(0);
6082         }
6083         set_jump_target(nottaken,(int)out);
6084       }
6085
6086       if(adj) {
6087         if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
6088       }
6089     } // (!unconditional)
6090   } // if(ooo)
6091   else
6092   {
6093     // In-order execution (branch first)
6094     //printf("IOE\n");
6095     int nottaken=0;
6096     if(1) {
6097       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6098       if(1) {
6099         assert(fs>=0);
6100         emit_testimm(fs,0x800000);
6101         if(source[i]&0x10000) // BC1T
6102         {
6103           nottaken=(int)out;
6104           emit_jeq(1);
6105         }
6106         else // BC1F
6107         {
6108           nottaken=(int)out;
6109           emit_jne(1);
6110         }
6111       }
6112     } // if(!unconditional)
6113     int adj;
6114     uint64_t ds_unneeded=branch_regs[i].u;
6115     uint64_t ds_unneeded_upper=branch_regs[i].uu;
6116     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6117     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6118     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6119     ds_unneeded|=1;
6120     ds_unneeded_upper|=1;
6121     // branch taken
6122     //assem_debug("1:\n");
6123     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6124                   ds_unneeded,ds_unneeded_upper);
6125     // load regs
6126     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6127     address_generation(i+1,&branch_regs[i],0);
6128     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6129     ds_assemble(i+1,&branch_regs[i]);
6130     cc=get_reg(branch_regs[i].regmap,CCREG);
6131     if(cc==-1) {
6132       emit_loadreg(CCREG,cc=HOST_CCREG);
6133       // CHECK: Is the following instruction (fall thru) allocated ok?
6134     }
6135     assert(cc==HOST_CCREG);
6136     store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6137     do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6138     assem_debug("cycle count (adj)\n");
6139     if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6140     load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6141     if(internal)
6142       assem_debug("branch: internal\n");
6143     else
6144       assem_debug("branch: external\n");
6145     if(internal&&is_ds[(ba[i]-start)>>2]) {
6146       ds_assemble_entry(i);
6147     }
6148     else {
6149       add_to_linker((int)out,ba[i],internal);
6150       emit_jmp(0);
6151     }
6152
6153     // branch not taken
6154     if(1) { // <- FIXME (don't need this)
6155       set_jump_target(nottaken,(int)out);
6156       assem_debug("1:\n");
6157       if(!likely[i]) {
6158         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6159                       ds_unneeded,ds_unneeded_upper);
6160         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6161         address_generation(i+1,&branch_regs[i],0);
6162         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6163         ds_assemble(i+1,&branch_regs[i]);
6164       }
6165       cc=get_reg(branch_regs[i].regmap,CCREG);
6166       if(cc==-1&&!likely[i]) {
6167         // Cycle count isn't in a register, temporarily load it then write it out
6168         emit_loadreg(CCREG,HOST_CCREG);
6169         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6170         int jaddr=(int)out;
6171         emit_jns(0);
6172         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6173         emit_storereg(CCREG,HOST_CCREG);
6174       }
6175       else{
6176         cc=get_reg(i_regmap,CCREG);
6177         assert(cc==HOST_CCREG);
6178         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6179         int jaddr=(int)out;
6180         emit_jns(0);
6181         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6182       }
6183     }
6184   }
6185 }
6186
6187 static void pagespan_assemble(int i,struct regstat *i_regs)
6188 {
6189   int s1l=get_reg(i_regs->regmap,rs1[i]);
6190   int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6191   int s2l=get_reg(i_regs->regmap,rs2[i]);
6192   int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6193   void *nt_branch=NULL;
6194   int taken=0;
6195   int nottaken=0;
6196   int unconditional=0;
6197   if(rs1[i]==0)
6198   {
6199     s1l=s2l;s1h=s2h;
6200     s2l=s2h=-1;
6201   }
6202   else if(rs2[i]==0)
6203   {
6204     s2l=s2h=-1;
6205   }
6206   if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6207     s1h=s2h=-1;
6208   }
6209   int hr=0;
6210   int addr,alt,ntaddr;
6211   if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6212   else {
6213     while(hr<HOST_REGS)
6214     {
6215       if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6216          (i_regs->regmap[hr]&63)!=rs1[i] &&
6217          (i_regs->regmap[hr]&63)!=rs2[i] )
6218       {
6219         addr=hr++;break;
6220       }
6221       hr++;
6222     }
6223   }
6224   while(hr<HOST_REGS)
6225   {
6226     if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6227        (i_regs->regmap[hr]&63)!=rs1[i] &&
6228        (i_regs->regmap[hr]&63)!=rs2[i] )
6229     {
6230       alt=hr++;break;
6231     }
6232     hr++;
6233   }
6234   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6235   {
6236     while(hr<HOST_REGS)
6237     {
6238       if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6239          (i_regs->regmap[hr]&63)!=rs1[i] &&
6240          (i_regs->regmap[hr]&63)!=rs2[i] )
6241       {
6242         ntaddr=hr;break;
6243       }
6244       hr++;
6245     }
6246   }
6247   assert(hr<HOST_REGS);
6248   if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6249     load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6250   }
6251   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6252   if(opcode[i]==2) // J
6253   {
6254     unconditional=1;
6255   }
6256   if(opcode[i]==3) // JAL
6257   {
6258     // TODO: mini_ht
6259     int rt=get_reg(i_regs->regmap,31);
6260     emit_movimm(start+i*4+8,rt);
6261     unconditional=1;
6262   }
6263   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6264   {
6265     emit_mov(s1l,addr);
6266     if(opcode2[i]==9) // JALR
6267     {
6268       int rt=get_reg(i_regs->regmap,rt1[i]);
6269       emit_movimm(start+i*4+8,rt);
6270     }
6271   }
6272   if((opcode[i]&0x3f)==4) // BEQ
6273   {
6274     if(rs1[i]==rs2[i])
6275     {
6276       unconditional=1;
6277     }
6278     else
6279     #ifdef HAVE_CMOV_IMM
6280     if(s1h<0) {
6281       if(s2l>=0) emit_cmp(s1l,s2l);
6282       else emit_test(s1l,s1l);
6283       emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6284     }
6285     else
6286     #endif
6287     {
6288       assert(s1l>=0);
6289       emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6290       if(s1h>=0) {
6291         if(s2h>=0) emit_cmp(s1h,s2h);
6292         else emit_test(s1h,s1h);
6293         emit_cmovne_reg(alt,addr);
6294       }
6295       if(s2l>=0) emit_cmp(s1l,s2l);
6296       else emit_test(s1l,s1l);
6297       emit_cmovne_reg(alt,addr);
6298     }
6299   }
6300   if((opcode[i]&0x3f)==5) // BNE
6301   {
6302     #ifdef HAVE_CMOV_IMM
6303     if(s1h<0) {
6304       if(s2l>=0) emit_cmp(s1l,s2l);
6305       else emit_test(s1l,s1l);
6306       emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6307     }
6308     else
6309     #endif
6310     {
6311       assert(s1l>=0);
6312       emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6313       if(s1h>=0) {
6314         if(s2h>=0) emit_cmp(s1h,s2h);
6315         else emit_test(s1h,s1h);
6316         emit_cmovne_reg(alt,addr);
6317       }
6318       if(s2l>=0) emit_cmp(s1l,s2l);
6319       else emit_test(s1l,s1l);
6320       emit_cmovne_reg(alt,addr);
6321     }
6322   }
6323   if((opcode[i]&0x3f)==0x14) // BEQL
6324   {
6325     if(s1h>=0) {
6326       if(s2h>=0) emit_cmp(s1h,s2h);
6327       else emit_test(s1h,s1h);
6328       nottaken=(int)out;
6329       emit_jne(0);
6330     }
6331     if(s2l>=0) emit_cmp(s1l,s2l);
6332     else emit_test(s1l,s1l);
6333     if(nottaken) set_jump_target(nottaken,(int)out);
6334     nottaken=(int)out;
6335     emit_jne(0);
6336   }
6337   if((opcode[i]&0x3f)==0x15) // BNEL
6338   {
6339     if(s1h>=0) {
6340       if(s2h>=0) emit_cmp(s1h,s2h);
6341       else emit_test(s1h,s1h);
6342       taken=(int)out;
6343       emit_jne(0);
6344     }
6345     if(s2l>=0) emit_cmp(s1l,s2l);
6346     else emit_test(s1l,s1l);
6347     nottaken=(int)out;
6348     emit_jeq(0);
6349     if(taken) set_jump_target(taken,(int)out);
6350   }
6351   if((opcode[i]&0x3f)==6) // BLEZ
6352   {
6353     emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6354     emit_cmpimm(s1l,1);
6355     if(s1h>=0) emit_mov(addr,ntaddr);
6356     emit_cmovl_reg(alt,addr);
6357     if(s1h>=0) {
6358       emit_test(s1h,s1h);
6359       emit_cmovne_reg(ntaddr,addr);
6360       emit_cmovs_reg(alt,addr);
6361     }
6362   }
6363   if((opcode[i]&0x3f)==7) // BGTZ
6364   {
6365     emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6366     emit_cmpimm(s1l,1);
6367     if(s1h>=0) emit_mov(addr,alt);
6368     emit_cmovl_reg(ntaddr,addr);
6369     if(s1h>=0) {
6370       emit_test(s1h,s1h);
6371       emit_cmovne_reg(alt,addr);
6372       emit_cmovs_reg(ntaddr,addr);
6373     }
6374   }
6375   if((opcode[i]&0x3f)==0x16) // BLEZL
6376   {
6377     assert((opcode[i]&0x3f)!=0x16);
6378   }
6379   if((opcode[i]&0x3f)==0x17) // BGTZL
6380   {
6381     assert((opcode[i]&0x3f)!=0x17);
6382   }
6383   assert(opcode[i]!=1); // BLTZ/BGEZ
6384
6385   //FIXME: Check CSREG
6386   if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6387     if((source[i]&0x30000)==0) // BC1F
6388     {
6389       emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6390       emit_testimm(s1l,0x800000);
6391       emit_cmovne_reg(alt,addr);
6392     }
6393     if((source[i]&0x30000)==0x10000) // BC1T
6394     {
6395       emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6396       emit_testimm(s1l,0x800000);
6397       emit_cmovne_reg(alt,addr);
6398     }
6399     if((source[i]&0x30000)==0x20000) // BC1FL
6400     {
6401       emit_testimm(s1l,0x800000);
6402       nottaken=(int)out;
6403       emit_jne(0);
6404     }
6405     if((source[i]&0x30000)==0x30000) // BC1TL
6406     {
6407       emit_testimm(s1l,0x800000);
6408       nottaken=(int)out;
6409       emit_jeq(0);
6410     }
6411   }
6412
6413   assert(i_regs->regmap[HOST_CCREG]==CCREG);
6414   wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6415   if(likely[i]||unconditional)
6416   {
6417     emit_movimm(ba[i],HOST_BTREG);
6418   }
6419   else if(addr!=HOST_BTREG)
6420   {
6421     emit_mov(addr,HOST_BTREG);
6422   }
6423   void *branch_addr=out;
6424   emit_jmp(0);
6425   int target_addr=start+i*4+5;
6426   void *stub=out;
6427   void *compiled_target_addr=check_addr(target_addr);
6428   emit_extjump_ds((int)branch_addr,target_addr);
6429   if(compiled_target_addr) {
6430     set_jump_target((int)branch_addr,(int)compiled_target_addr);
6431     add_link(target_addr,stub);
6432   }
6433   else set_jump_target((int)branch_addr,(int)stub);
6434   if(likely[i]) {
6435     // Not-taken path
6436     set_jump_target((int)nottaken,(int)out);
6437     wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6438     void *branch_addr=out;
6439     emit_jmp(0);
6440     int target_addr=start+i*4+8;
6441     void *stub=out;
6442     void *compiled_target_addr=check_addr(target_addr);
6443     emit_extjump_ds((int)branch_addr,target_addr);
6444     if(compiled_target_addr) {
6445       set_jump_target((int)branch_addr,(int)compiled_target_addr);
6446       add_link(target_addr,stub);
6447     }
6448     else set_jump_target((int)branch_addr,(int)stub);
6449   }
6450 }
6451
6452 // Assemble the delay slot for the above
6453 static void pagespan_ds()
6454 {
6455   assem_debug("initial delay slot:\n");
6456   u_int vaddr=start+1;
6457   u_int page=get_page(vaddr);
6458   u_int vpage=get_vpage(vaddr);
6459   ll_add(jump_dirty+vpage,vaddr,(void *)out);
6460   do_dirty_stub_ds();
6461   ll_add(jump_in+page,vaddr,(void *)out);
6462   assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6463   if(regs[0].regmap[HOST_CCREG]!=CCREG)
6464     wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6465   if(regs[0].regmap[HOST_BTREG]!=BTREG)
6466     emit_writeword(HOST_BTREG,(int)&branch_target);
6467   load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6468   address_generation(0,&regs[0],regs[0].regmap_entry);
6469   if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
6470     load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6471   cop1_usable=0;
6472   is_delayslot=0;
6473   switch(itype[0]) {
6474     case ALU:
6475       alu_assemble(0,&regs[0]);break;
6476     case IMM16:
6477       imm16_assemble(0,&regs[0]);break;
6478     case SHIFT:
6479       shift_assemble(0,&regs[0]);break;
6480     case SHIFTIMM:
6481       shiftimm_assemble(0,&regs[0]);break;
6482     case LOAD:
6483       load_assemble(0,&regs[0]);break;
6484     case LOADLR:
6485       loadlr_assemble(0,&regs[0]);break;
6486     case STORE:
6487       store_assemble(0,&regs[0]);break;
6488     case STORELR:
6489       storelr_assemble(0,&regs[0]);break;
6490     case COP0:
6491       cop0_assemble(0,&regs[0]);break;
6492     case COP1:
6493       cop1_assemble(0,&regs[0]);break;
6494     case C1LS:
6495       c1ls_assemble(0,&regs[0]);break;
6496     case COP2:
6497       cop2_assemble(0,&regs[0]);break;
6498     case C2LS:
6499       c2ls_assemble(0,&regs[0]);break;
6500     case C2OP:
6501       c2op_assemble(0,&regs[0]);break;
6502     case FCONV:
6503       fconv_assemble(0,&regs[0]);break;
6504     case FLOAT:
6505       float_assemble(0,&regs[0]);break;
6506     case FCOMP:
6507       fcomp_assemble(0,&regs[0]);break;
6508     case MULTDIV:
6509       multdiv_assemble(0,&regs[0]);break;
6510     case MOV:
6511       mov_assemble(0,&regs[0]);break;
6512     case SYSCALL:
6513     case HLECALL:
6514     case INTCALL:
6515     case SPAN:
6516     case UJUMP:
6517     case RJUMP:
6518     case CJUMP:
6519     case SJUMP:
6520     case FJUMP:
6521       printf("Jump in the delay slot.  This is probably a bug.\n");
6522   }
6523   int btaddr=get_reg(regs[0].regmap,BTREG);
6524   if(btaddr<0) {
6525     btaddr=get_reg(regs[0].regmap,-1);
6526     emit_readword((int)&branch_target,btaddr);
6527   }
6528   assert(btaddr!=HOST_CCREG);
6529   if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6530 #ifdef HOST_IMM8
6531   emit_movimm(start+4,HOST_TEMPREG);
6532   emit_cmp(btaddr,HOST_TEMPREG);
6533 #else
6534   emit_cmpimm(btaddr,start+4);
6535 #endif
6536   int branch=(int)out;
6537   emit_jeq(0);
6538   store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6539   emit_jmp(jump_vaddr_reg[btaddr]);
6540   set_jump_target(branch,(int)out);
6541   store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6542   load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6543 }
6544
6545 // Basic liveness analysis for MIPS registers
6546 void unneeded_registers(int istart,int iend,int r)
6547 {
6548   int i;
6549   uint64_t u,uu,b,bu;
6550   uint64_t temp_u,temp_uu;
6551   uint64_t tdep;
6552   if(iend==slen-1) {
6553     u=1;uu=1;
6554   }else{
6555     u=unneeded_reg[iend+1];
6556     uu=unneeded_reg_upper[iend+1];
6557     u=1;uu=1;
6558   }
6559   for (i=iend;i>=istart;i--)
6560   {
6561     //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6562     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6563     {
6564       // If subroutine call, flag return address as a possible branch target
6565       if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6566
6567       if(ba[i]<start || ba[i]>=(start+slen*4))
6568       {
6569         // Branch out of this block, flush all regs
6570         u=1;
6571         uu=1;
6572         /* Hexagon hack
6573         if(itype[i]==UJUMP&&rt1[i]==31)
6574         {
6575           uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6576         }
6577         if(itype[i]==RJUMP&&rs1[i]==31)
6578         {
6579           uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6580         }
6581         if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
6582           if(itype[i]==UJUMP&&rt1[i]==31)
6583           {
6584             //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6585             uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6586           }
6587           if(itype[i]==RJUMP&&rs1[i]==31)
6588           {
6589             //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6590             uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6591           }
6592         }*/
6593         branch_unneeded_reg[i]=u;
6594         branch_unneeded_reg_upper[i]=uu;
6595         // Merge in delay slot
6596         tdep=(~uu>>rt1[i+1])&1;
6597         u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6598         uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6599         u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6600         uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6601         uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6602         u|=1;uu|=1;
6603         // If branch is "likely" (and conditional)
6604         // then we skip the delay slot on the fall-thru path
6605         if(likely[i]) {
6606           if(i<slen-1) {
6607             u&=unneeded_reg[i+2];
6608             uu&=unneeded_reg_upper[i+2];
6609           }
6610           else
6611           {
6612             u=1;
6613             uu=1;
6614           }
6615         }
6616       }
6617       else
6618       {
6619         // Internal branch, flag target
6620         bt[(ba[i]-start)>>2]=1;
6621         if(ba[i]<=start+i*4) {
6622           // Backward branch
6623           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6624           {
6625             // Unconditional branch
6626             temp_u=1;temp_uu=1;
6627           } else {
6628             // Conditional branch (not taken case)
6629             temp_u=unneeded_reg[i+2];
6630             temp_uu=unneeded_reg_upper[i+2];
6631           }
6632           // Merge in delay slot
6633           tdep=(~temp_uu>>rt1[i+1])&1;
6634           temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6635           temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6636           temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6637           temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6638           temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6639           temp_u|=1;temp_uu|=1;
6640           // If branch is "likely" (and conditional)
6641           // then we skip the delay slot on the fall-thru path
6642           if(likely[i]) {
6643             if(i<slen-1) {
6644               temp_u&=unneeded_reg[i+2];
6645               temp_uu&=unneeded_reg_upper[i+2];
6646             }
6647             else
6648             {
6649               temp_u=1;
6650               temp_uu=1;
6651             }
6652           }
6653           tdep=(~temp_uu>>rt1[i])&1;
6654           temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6655           temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6656           temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6657           temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6658           temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6659           temp_u|=1;temp_uu|=1;
6660           unneeded_reg[i]=temp_u;
6661           unneeded_reg_upper[i]=temp_uu;
6662           // Only go three levels deep.  This recursion can take an
6663           // excessive amount of time if there are a lot of nested loops.
6664           if(r<2) {
6665             unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6666           }else{
6667             unneeded_reg[(ba[i]-start)>>2]=1;
6668             unneeded_reg_upper[(ba[i]-start)>>2]=1;
6669           }
6670         } /*else*/ if(1) {
6671           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6672           {
6673             // Unconditional branch
6674             u=unneeded_reg[(ba[i]-start)>>2];
6675             uu=unneeded_reg_upper[(ba[i]-start)>>2];
6676             branch_unneeded_reg[i]=u;
6677             branch_unneeded_reg_upper[i]=uu;
6678         //u=1;
6679         //uu=1;
6680         //branch_unneeded_reg[i]=u;
6681         //branch_unneeded_reg_upper[i]=uu;
6682             // Merge in delay slot
6683             tdep=(~uu>>rt1[i+1])&1;
6684             u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6685             uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6686             u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6687             uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6688             uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6689             u|=1;uu|=1;
6690           } else {
6691             // Conditional branch
6692             b=unneeded_reg[(ba[i]-start)>>2];
6693             bu=unneeded_reg_upper[(ba[i]-start)>>2];
6694             branch_unneeded_reg[i]=b;
6695             branch_unneeded_reg_upper[i]=bu;
6696         //b=1;
6697         //bu=1;
6698         //branch_unneeded_reg[i]=b;
6699         //branch_unneeded_reg_upper[i]=bu;
6700             // Branch delay slot
6701             tdep=(~uu>>rt1[i+1])&1;
6702             b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6703             bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6704             b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6705             bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6706             bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6707             b|=1;bu|=1;
6708             // If branch is "likely" then we skip the
6709             // delay slot on the fall-thru path
6710             if(likely[i]) {
6711               u=b;
6712               uu=bu;
6713               if(i<slen-1) {
6714                 u&=unneeded_reg[i+2];
6715                 uu&=unneeded_reg_upper[i+2];
6716         //u=1;
6717         //uu=1;
6718               }
6719             } else {
6720               u&=b;
6721               uu&=bu;
6722         //u=1;
6723         //uu=1;
6724             }
6725             if(i<slen-1) {
6726               branch_unneeded_reg[i]&=unneeded_reg[i+2];
6727               branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6728         //branch_unneeded_reg[i]=1;
6729         //branch_unneeded_reg_upper[i]=1;
6730             } else {
6731               branch_unneeded_reg[i]=1;
6732               branch_unneeded_reg_upper[i]=1;
6733             }
6734           }
6735         }
6736       }
6737     }
6738     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
6739     {
6740       // SYSCALL instruction (software interrupt)
6741       u=1;
6742       uu=1;
6743     }
6744     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6745     {
6746       // ERET instruction (return from interrupt)
6747       u=1;
6748       uu=1;
6749     }
6750     //u=uu=1; // DEBUG
6751     tdep=(~uu>>rt1[i])&1;
6752     // Written registers are unneeded
6753     u|=1LL<<rt1[i];
6754     u|=1LL<<rt2[i];
6755     uu|=1LL<<rt1[i];
6756     uu|=1LL<<rt2[i];
6757     // Accessed registers are needed
6758     u&=~(1LL<<rs1[i]);
6759     u&=~(1LL<<rs2[i]);
6760     uu&=~(1LL<<us1[i]);
6761     uu&=~(1LL<<us2[i]);
6762     // Source-target dependencies
6763     uu&=~(tdep<<dep1[i]);
6764     uu&=~(tdep<<dep2[i]);
6765     // R0 is always unneeded
6766     u|=1;uu|=1;
6767     // Save it
6768     unneeded_reg[i]=u;
6769     unneeded_reg_upper[i]=uu;
6770     /*
6771     printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6772     printf("U:");
6773     int r;
6774     for(r=1;r<=CCREG;r++) {
6775       if((unneeded_reg[i]>>r)&1) {
6776         if(r==HIREG) printf(" HI");
6777         else if(r==LOREG) printf(" LO");
6778         else printf(" r%d",r);
6779       }
6780     }
6781     printf(" UU:");
6782     for(r=1;r<=CCREG;r++) {
6783       if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
6784         if(r==HIREG) printf(" HI");
6785         else if(r==LOREG) printf(" LO");
6786         else printf(" r%d",r);
6787       }
6788     }
6789     printf("\n");*/
6790   }
6791 #ifdef FORCE32
6792   for (i=iend;i>=istart;i--)
6793   {
6794     unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
6795   }
6796 #endif
6797 }
6798
6799 // Identify registers which are likely to contain 32-bit values
6800 // This is used to predict whether any branches will jump to a
6801 // location with 64-bit values in registers.
6802 static void provisional_32bit()
6803 {
6804   int i,j;
6805   uint64_t is32=1;
6806   uint64_t lastbranch=1;
6807
6808   for(i=0;i<slen;i++)
6809   {
6810     if(i>0) {
6811       if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
6812         if(i>1) is32=lastbranch;
6813         else is32=1;
6814       }
6815     }
6816     if(i>1)
6817     {
6818       if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
6819         if(likely[i-2]) {
6820           if(i>2) is32=lastbranch;
6821           else is32=1;
6822         }
6823       }
6824       if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
6825       {
6826         if(rs1[i-2]==0||rs2[i-2]==0)
6827         {
6828           if(rs1[i-2]) {
6829             is32|=1LL<<rs1[i-2];
6830           }
6831           if(rs2[i-2]) {
6832             is32|=1LL<<rs2[i-2];
6833           }
6834         }
6835       }
6836     }
6837     // If something jumps here with 64-bit values
6838     // then promote those registers to 64 bits
6839     if(bt[i])
6840     {
6841       uint64_t temp_is32=is32;
6842       for(j=i-1;j>=0;j--)
6843       {
6844         if(ba[j]==start+i*4)
6845           //temp_is32&=branch_regs[j].is32;
6846           temp_is32&=p32[j];
6847       }
6848       for(j=i;j<slen;j++)
6849       {
6850         if(ba[j]==start+i*4)
6851           temp_is32=1;
6852       }
6853       is32=temp_is32;
6854     }
6855     int type=itype[i];
6856     int op=opcode[i];
6857     int op2=opcode2[i];
6858     int rt=rt1[i];
6859     int s1=rs1[i];
6860     int s2=rs2[i];
6861     if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
6862       // Branches don't write registers, consider the delay slot instead.
6863       type=itype[i+1];
6864       op=opcode[i+1];
6865       op2=opcode2[i+1];
6866       rt=rt1[i+1];
6867       s1=rs1[i+1];
6868       s2=rs2[i+1];
6869       lastbranch=is32;
6870     }
6871     switch(type) {
6872       case LOAD:
6873         if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
6874            opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
6875           is32&=~(1LL<<rt);
6876         else
6877           is32|=1LL<<rt;
6878         break;
6879       case STORE:
6880       case STORELR:
6881         break;
6882       case LOADLR:
6883         if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
6884         if(op==0x22) is32|=1LL<<rt; // LWL
6885         break;
6886       case IMM16:
6887         if (op==0x08||op==0x09|| // ADDI/ADDIU
6888             op==0x0a||op==0x0b|| // SLTI/SLTIU
6889             op==0x0c|| // ANDI
6890             op==0x0f)  // LUI
6891         {
6892           is32|=1LL<<rt;
6893         }
6894         if(op==0x18||op==0x19) { // DADDI/DADDIU
6895           is32&=~(1LL<<rt);
6896           //if(imm[i]==0)
6897           //  is32|=((is32>>s1)&1LL)<<rt;
6898         }
6899         if(op==0x0d||op==0x0e) { // ORI/XORI
6900           uint64_t sr=((is32>>s1)&1LL);
6901           is32&=~(1LL<<rt);
6902           is32|=sr<<rt;
6903         }
6904         break;
6905       case UJUMP:
6906         break;
6907       case RJUMP:
6908         break;
6909       case CJUMP:
6910         break;
6911       case SJUMP:
6912         break;
6913       case FJUMP:
6914         break;
6915       case ALU:
6916         if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
6917           is32|=1LL<<rt;
6918         }
6919         if(op2==0x2a||op2==0x2b) { // SLT/SLTU
6920           is32|=1LL<<rt;
6921         }
6922         else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
6923           uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
6924           is32&=~(1LL<<rt);
6925           is32|=sr<<rt;
6926         }
6927         else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
6928           if(s1==0&&s2==0) {
6929             is32|=1LL<<rt;
6930           }
6931           else if(s2==0) {
6932             uint64_t sr=((is32>>s1)&1LL);
6933             is32&=~(1LL<<rt);
6934             is32|=sr<<rt;
6935           }
6936           else if(s1==0) {
6937             uint64_t sr=((is32>>s2)&1LL);
6938             is32&=~(1LL<<rt);
6939             is32|=sr<<rt;
6940           }
6941           else {
6942             is32&=~(1LL<<rt);
6943           }
6944         }
6945         else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
6946           if(s1==0&&s2==0) {
6947             is32|=1LL<<rt;
6948           }
6949           else if(s2==0) {
6950             uint64_t sr=((is32>>s1)&1LL);
6951             is32&=~(1LL<<rt);
6952             is32|=sr<<rt;
6953           }
6954           else {
6955             is32&=~(1LL<<rt);
6956           }
6957         }
6958         break;
6959       case MULTDIV:
6960         if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
6961           is32&=~((1LL<<HIREG)|(1LL<<LOREG));
6962         }
6963         else {
6964           is32|=(1LL<<HIREG)|(1LL<<LOREG);
6965         }
6966         break;
6967       case MOV:
6968         {
6969           uint64_t sr=((is32>>s1)&1LL);
6970           is32&=~(1LL<<rt);
6971           is32|=sr<<rt;
6972         }
6973         break;
6974       case SHIFT:
6975         if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
6976         else is32|=1LL<<rt; // SLLV/SRLV/SRAV
6977         break;
6978       case SHIFTIMM:
6979         is32|=1LL<<rt;
6980         // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
6981         if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
6982         break;
6983       case COP0:
6984         if(op2==0) is32|=1LL<<rt; // MFC0
6985         break;
6986       case COP1:
6987       case COP2:
6988         if(op2==0) is32|=1LL<<rt; // MFC1
6989         if(op2==1) is32&=~(1LL<<rt); // DMFC1
6990         if(op2==2) is32|=1LL<<rt; // CFC1
6991         break;
6992       case C1LS:
6993       case C2LS:
6994         break;
6995       case FLOAT:
6996       case FCONV:
6997         break;
6998       case FCOMP:
6999         break;
7000       case C2OP:
7001       case SYSCALL:
7002       case HLECALL:
7003         break;
7004       default:
7005         break;
7006     }
7007     is32|=1;
7008     p32[i]=is32;
7009
7010     if(i>0)
7011     {
7012       if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
7013       {
7014         if(rt1[i-1]==31) // JAL/JALR
7015         {
7016           // Subroutine call will return here, don't alloc any registers
7017           is32=1;
7018         }
7019         else if(i+1<slen)
7020         {
7021           // Internal branch will jump here, match registers to caller
7022           is32=0x3FFFFFFFFLL;
7023         }
7024       }
7025     }
7026   }
7027 }
7028
7029 // Identify registers which may be assumed to contain 32-bit values
7030 // and where optimizations will rely on this.
7031 // This is used to determine whether backward branches can safely
7032 // jump to a location with 64-bit values in registers.
7033 static void provisional_r32()
7034 {
7035   u_int r32=0;
7036   int i;
7037
7038   for (i=slen-1;i>=0;i--)
7039   {
7040     int hr;
7041     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7042     {
7043       if(ba[i]<start || ba[i]>=(start+slen*4))
7044       {
7045         // Branch out of this block, don't need anything
7046         r32=0;
7047       }
7048       else
7049       {
7050         // Internal branch
7051         // Need whatever matches the target
7052         // (and doesn't get overwritten by the delay slot instruction)
7053         r32=0;
7054         int t=(ba[i]-start)>>2;
7055         if(ba[i]>start+i*4) {
7056           // Forward branch
7057           //if(!(requires_32bit[t]&~regs[i].was32))
7058           //  r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7059           if(!(pr32[t]&~regs[i].was32))
7060             r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7061         }else{
7062           // Backward branch
7063           if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
7064             r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7065         }
7066       }
7067       // Conditional branch may need registers for following instructions
7068       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7069       {
7070         if(i<slen-2) {
7071           //r32|=requires_32bit[i+2];
7072           r32|=pr32[i+2];
7073           r32&=regs[i].was32;
7074           // Mark this address as a branch target since it may be called
7075           // upon return from interrupt
7076           //bt[i+2]=1;
7077         }
7078       }
7079       // Merge in delay slot
7080       if(!likely[i]) {
7081         // These are overwritten unless the branch is "likely"
7082         // and the delay slot is nullified if not taken
7083         r32&=~(1LL<<rt1[i+1]);
7084         r32&=~(1LL<<rt2[i+1]);
7085       }
7086       // Assume these are needed (delay slot)
7087       if(us1[i+1]>0)
7088       {
7089         if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7090       }
7091       if(us2[i+1]>0)
7092       {
7093         if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7094       }
7095       if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7096       {
7097         if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7098       }
7099       if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7100       {
7101         if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7102       }
7103     }
7104     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7105     {
7106       // SYSCALL instruction (software interrupt)
7107       r32=0;
7108     }
7109     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7110     {
7111       // ERET instruction (return from interrupt)
7112       r32=0;
7113     }
7114     // Check 32 bits
7115     r32&=~(1LL<<rt1[i]);
7116     r32&=~(1LL<<rt2[i]);
7117     if(us1[i]>0)
7118     {
7119       if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7120     }
7121     if(us2[i]>0)
7122     {
7123       if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7124     }
7125     if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7126     {
7127       if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7128     }
7129     if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7130     {
7131       if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7132     }
7133     //requires_32bit[i]=r32;
7134     pr32[i]=r32;
7135
7136     // Dirty registers which are 32-bit, require 32-bit input
7137     // as they will be written as 32-bit values
7138     for(hr=0;hr<HOST_REGS;hr++)
7139     {
7140       if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
7141         if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7142           if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7143           pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7144           //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7145         }
7146       }
7147     }
7148   }
7149 }
7150
7151 // Write back dirty registers as soon as we will no longer modify them,
7152 // so that we don't end up with lots of writes at the branches.
7153 void clean_registers(int istart,int iend,int wr)
7154 {
7155   int i;
7156   int r;
7157   u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7158   u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7159   if(iend==slen-1) {
7160     will_dirty_i=will_dirty_next=0;
7161     wont_dirty_i=wont_dirty_next=0;
7162   }else{
7163     will_dirty_i=will_dirty_next=will_dirty[iend+1];
7164     wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7165   }
7166   for (i=iend;i>=istart;i--)
7167   {
7168     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7169     {
7170       if(ba[i]<start || ba[i]>=(start+slen*4))
7171       {
7172         // Branch out of this block, flush all regs
7173         if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7174         {
7175           // Unconditional branch
7176           will_dirty_i=0;
7177           wont_dirty_i=0;
7178           // Merge in delay slot (will dirty)
7179           for(r=0;r<HOST_REGS;r++) {
7180             if(r!=EXCLUDE_REG) {
7181               if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7182               if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7183               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7184               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7185               if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7186               if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7187               if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7188               if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7189               if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7190               if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7191               if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7192               if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7193               if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7194               if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7195             }
7196           }
7197         }
7198         else
7199         {
7200           // Conditional branch
7201           will_dirty_i=0;
7202           wont_dirty_i=wont_dirty_next;
7203           // Merge in delay slot (will dirty)
7204           for(r=0;r<HOST_REGS;r++) {
7205             if(r!=EXCLUDE_REG) {
7206               if(!likely[i]) {
7207                 // Might not dirty if likely branch is not taken
7208                 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7209                 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7210                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7211                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7212                 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7213                 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7214                 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7215                 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7216                 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7217                 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7218                 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7219                 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7220                 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7221                 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7222               }
7223             }
7224           }
7225         }
7226         // Merge in delay slot (wont dirty)
7227         for(r=0;r<HOST_REGS;r++) {
7228           if(r!=EXCLUDE_REG) {
7229             if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7230             if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7231             if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7232             if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7233             if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7234             if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7235             if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7236             if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7237             if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7238             if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7239           }
7240         }
7241         if(wr) {
7242           #ifndef DESTRUCTIVE_WRITEBACK
7243           branch_regs[i].dirty&=wont_dirty_i;
7244           #endif
7245           branch_regs[i].dirty|=will_dirty_i;
7246         }
7247       }
7248       else
7249       {
7250         // Internal branch
7251         if(ba[i]<=start+i*4) {
7252           // Backward branch
7253           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7254           {
7255             // Unconditional branch
7256             temp_will_dirty=0;
7257             temp_wont_dirty=0;
7258             // Merge in delay slot (will dirty)
7259             for(r=0;r<HOST_REGS;r++) {
7260               if(r!=EXCLUDE_REG) {
7261                 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7262                 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7263                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7264                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7265                 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7266                 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7267                 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7268                 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7269                 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7270                 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7271                 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7272                 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7273                 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7274                 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7275               }
7276             }
7277           } else {
7278             // Conditional branch (not taken case)
7279             temp_will_dirty=will_dirty_next;
7280             temp_wont_dirty=wont_dirty_next;
7281             // Merge in delay slot (will dirty)
7282             for(r=0;r<HOST_REGS;r++) {
7283               if(r!=EXCLUDE_REG) {
7284                 if(!likely[i]) {
7285                   // Will not dirty if likely branch is not taken
7286                   if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7287                   if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7288                   if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7289                   if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7290                   if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7291                   if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7292                   if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7293                   //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7294                   //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7295                   if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7296                   if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7297                   if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7298                   if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7299                   if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7300                 }
7301               }
7302             }
7303           }
7304           // Merge in delay slot (wont dirty)
7305           for(r=0;r<HOST_REGS;r++) {
7306             if(r!=EXCLUDE_REG) {
7307               if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7308               if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7309               if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7310               if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7311               if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7312               if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7313               if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7314               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7315               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7316               if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7317             }
7318           }
7319           // Deal with changed mappings
7320           if(i<iend) {
7321             for(r=0;r<HOST_REGS;r++) {
7322               if(r!=EXCLUDE_REG) {
7323                 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7324                   temp_will_dirty&=~(1<<r);
7325                   temp_wont_dirty&=~(1<<r);
7326                   if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7327                     temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7328                     temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7329                   } else {
7330                     temp_will_dirty|=1<<r;
7331                     temp_wont_dirty|=1<<r;
7332                   }
7333                 }
7334               }
7335             }
7336           }
7337           if(wr) {
7338             will_dirty[i]=temp_will_dirty;
7339             wont_dirty[i]=temp_wont_dirty;
7340             clean_registers((ba[i]-start)>>2,i-1,0);
7341           }else{
7342             // Limit recursion.  It can take an excessive amount
7343             // of time if there are a lot of nested loops.
7344             will_dirty[(ba[i]-start)>>2]=0;
7345             wont_dirty[(ba[i]-start)>>2]=-1;
7346           }
7347         }
7348         /*else*/ if(1)
7349         {
7350           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7351           {
7352             // Unconditional branch
7353             will_dirty_i=0;
7354             wont_dirty_i=0;
7355           //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7356             for(r=0;r<HOST_REGS;r++) {
7357               if(r!=EXCLUDE_REG) {
7358                 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7359                   will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7360                   wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7361                 }
7362               }
7363             }
7364           //}
7365             // Merge in delay slot
7366             for(r=0;r<HOST_REGS;r++) {
7367               if(r!=EXCLUDE_REG) {
7368                 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7369                 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7370                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7371                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7372                 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7373                 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7374                 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7375                 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7376                 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7377                 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7378                 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7379                 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7380                 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7381                 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7382               }
7383             }
7384           } else {
7385             // Conditional branch
7386             will_dirty_i=will_dirty_next;
7387             wont_dirty_i=wont_dirty_next;
7388           //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7389             for(r=0;r<HOST_REGS;r++) {
7390               if(r!=EXCLUDE_REG) {
7391                 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7392                   will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7393                   wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7394                 }
7395                 else
7396                 {
7397                   will_dirty_i&=~(1<<r);
7398                 }
7399                 // Treat delay slot as part of branch too
7400                 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7401                   will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7402                   wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7403                 }
7404                 else
7405                 {
7406                   will_dirty[i+1]&=~(1<<r);
7407                 }*/
7408               }
7409             }
7410           //}
7411             // Merge in delay slot
7412             for(r=0;r<HOST_REGS;r++) {
7413               if(r!=EXCLUDE_REG) {
7414                 if(!likely[i]) {
7415                   // Might not dirty if likely branch is not taken
7416                   if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7417                   if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7418                   if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7419                   if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7420                   if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7421                   if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7422                   if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7423                   //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7424                   //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7425                   if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7426                   if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7427                   if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7428                   if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7429                   if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7430                 }
7431               }
7432             }
7433           }
7434           // Merge in delay slot
7435           for(r=0;r<HOST_REGS;r++) {
7436             if(r!=EXCLUDE_REG) {
7437               if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7438               if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7439               if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7440               if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7441               if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7442               if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7443               if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7444               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7445               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7446               if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7447             }
7448           }
7449           if(wr) {
7450             #ifndef DESTRUCTIVE_WRITEBACK
7451             branch_regs[i].dirty&=wont_dirty_i;
7452             #endif
7453             branch_regs[i].dirty|=will_dirty_i;
7454           }
7455         }
7456       }
7457     }
7458     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7459     {
7460       // SYSCALL instruction (software interrupt)
7461       will_dirty_i=0;
7462       wont_dirty_i=0;
7463     }
7464     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7465     {
7466       // ERET instruction (return from interrupt)
7467       will_dirty_i=0;
7468       wont_dirty_i=0;
7469     }
7470     will_dirty_next=will_dirty_i;
7471     wont_dirty_next=wont_dirty_i;
7472     for(r=0;r<HOST_REGS;r++) {
7473       if(r!=EXCLUDE_REG) {
7474         if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7475         if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7476         if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7477         if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7478         if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7479         if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7480         if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7481         if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7482         if(i>istart) {
7483           if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7484           {
7485             // Don't store a register immediately after writing it,
7486             // may prevent dual-issue.
7487             if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7488             if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7489           }
7490         }
7491       }
7492     }
7493     // Save it
7494     will_dirty[i]=will_dirty_i;
7495     wont_dirty[i]=wont_dirty_i;
7496     // Mark registers that won't be dirtied as not dirty
7497     if(wr) {
7498       /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7499       for(r=0;r<HOST_REGS;r++) {
7500         if((will_dirty_i>>r)&1) {
7501           printf(" r%d",r);
7502         }
7503       }
7504       printf("\n");*/
7505
7506       //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7507         regs[i].dirty|=will_dirty_i;
7508         #ifndef DESTRUCTIVE_WRITEBACK
7509         regs[i].dirty&=wont_dirty_i;
7510         if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7511         {
7512           if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7513             for(r=0;r<HOST_REGS;r++) {
7514               if(r!=EXCLUDE_REG) {
7515                 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7516                   regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7517                 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7518               }
7519             }
7520           }
7521         }
7522         else
7523         {
7524           if(i<iend) {
7525             for(r=0;r<HOST_REGS;r++) {
7526               if(r!=EXCLUDE_REG) {
7527                 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7528                   regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7529                 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7530               }
7531             }
7532           }
7533         }
7534         #endif
7535       //}
7536     }
7537     // Deal with changed mappings
7538     temp_will_dirty=will_dirty_i;
7539     temp_wont_dirty=wont_dirty_i;
7540     for(r=0;r<HOST_REGS;r++) {
7541       if(r!=EXCLUDE_REG) {
7542         int nr;
7543         if(regs[i].regmap[r]==regmap_pre[i][r]) {
7544           if(wr) {
7545             #ifndef DESTRUCTIVE_WRITEBACK
7546             regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7547             #endif
7548             regs[i].wasdirty|=will_dirty_i&(1<<r);
7549           }
7550         }
7551         else if((nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7552           // Register moved to a different register
7553           will_dirty_i&=~(1<<r);
7554           wont_dirty_i&=~(1<<r);
7555           will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7556           wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7557           if(wr) {
7558             #ifndef DESTRUCTIVE_WRITEBACK
7559             regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7560             #endif
7561             regs[i].wasdirty|=will_dirty_i&(1<<r);
7562           }
7563         }
7564         else {
7565           will_dirty_i&=~(1<<r);
7566           wont_dirty_i&=~(1<<r);
7567           if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7568             will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7569             wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7570           } else {
7571             wont_dirty_i|=1<<r;
7572             /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7573           }
7574         }
7575       }
7576     }
7577   }
7578 }
7579
7580   /* disassembly */
7581 void disassemble_inst(int i)
7582 {
7583     if (bt[i]) printf("*"); else printf(" ");
7584     switch(itype[i]) {
7585       case UJUMP:
7586         printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7587       case CJUMP:
7588         printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7589       case SJUMP:
7590         printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7591       case FJUMP:
7592         printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7593       case RJUMP:
7594         if (opcode[i]==0x9&&rt1[i]!=31)
7595           printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7596         else
7597           printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7598         break;
7599       case SPAN:
7600         printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7601       case IMM16:
7602         if(opcode[i]==0xf) //LUI
7603           printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7604         else
7605           printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7606         break;
7607       case LOAD:
7608       case LOADLR:
7609         printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7610         break;
7611       case STORE:
7612       case STORELR:
7613         printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7614         break;
7615       case ALU:
7616       case SHIFT:
7617         printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7618         break;
7619       case MULTDIV:
7620         printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7621         break;
7622       case SHIFTIMM:
7623         printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7624         break;
7625       case MOV:
7626         if((opcode2[i]&0x1d)==0x10)
7627           printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7628         else if((opcode2[i]&0x1d)==0x11)
7629           printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7630         else
7631           printf (" %x: %s\n",start+i*4,insn[i]);
7632         break;
7633       case COP0:
7634         if(opcode2[i]==0)
7635           printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7636         else if(opcode2[i]==4)
7637           printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7638         else printf (" %x: %s\n",start+i*4,insn[i]);
7639         break;
7640       case COP1:
7641         if(opcode2[i]<3)
7642           printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7643         else if(opcode2[i]>3)
7644           printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7645         else printf (" %x: %s\n",start+i*4,insn[i]);
7646         break;
7647       case COP2:
7648         if(opcode2[i]<3)
7649           printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7650         else if(opcode2[i]>3)
7651           printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7652         else printf (" %x: %s\n",start+i*4,insn[i]);
7653         break;
7654       case C1LS:
7655         printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7656         break;
7657       case C2LS:
7658         printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7659         break;
7660       case INTCALL:
7661         printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
7662         break;
7663       default:
7664         //printf (" %s %8x\n",insn[i],source[i]);
7665         printf (" %x: %s\n",start+i*4,insn[i]);
7666     }
7667 }
7668
7669 void new_dynarec_init()
7670 {
7671   printf("Init new dynarec\n");
7672   out=(u_char *)BASE_ADDR;
7673   if (mmap (out, 1<<TARGET_SIZE_2,
7674             PROT_READ | PROT_WRITE | PROT_EXEC,
7675             MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
7676             -1, 0) <= 0) {printf("mmap() failed\n");}
7677 #ifdef MUPEN64
7678   rdword=&readmem_dword;
7679   fake_pc.f.r.rs=&readmem_dword;
7680   fake_pc.f.r.rt=&readmem_dword;
7681   fake_pc.f.r.rd=&readmem_dword;
7682 #endif
7683   int n;
7684   for(n=0x80000;n<0x80800;n++)
7685     invalid_code[n]=1;
7686   for(n=0;n<65536;n++)
7687     hash_table[n][0]=hash_table[n][2]=-1;
7688   memset(mini_ht,-1,sizeof(mini_ht));
7689   memset(restore_candidate,0,sizeof(restore_candidate));
7690   copy=shadow;
7691   expirep=16384; // Expiry pointer, +2 blocks
7692   pending_exception=0;
7693   literalcount=0;
7694 #ifdef HOST_IMM8
7695   // Copy this into local area so we don't have to put it in every literal pool
7696   invc_ptr=invalid_code;
7697 #endif
7698   stop_after_jal=0;
7699   // TLB
7700   using_tlb=0;
7701   for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7702     memory_map[n]=-1;
7703   for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7704     memory_map[n]=((u_int)rdram-0x80000000)>>2;
7705   for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7706     memory_map[n]=-1;
7707 #ifdef MUPEN64
7708   for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
7709     writemem[n] = write_nomem_new;
7710     writememb[n] = write_nomemb_new;
7711     writememh[n] = write_nomemh_new;
7712 #ifndef FORCE32
7713     writememd[n] = write_nomemd_new;
7714 #endif
7715     readmem[n] = read_nomem_new;
7716     readmemb[n] = read_nomemb_new;
7717     readmemh[n] = read_nomemh_new;
7718 #ifndef FORCE32
7719     readmemd[n] = read_nomemd_new;
7720 #endif
7721   }
7722   for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
7723     writemem[n] = write_rdram_new;
7724     writememb[n] = write_rdramb_new;
7725     writememh[n] = write_rdramh_new;
7726 #ifndef FORCE32
7727     writememd[n] = write_rdramd_new;
7728 #endif
7729   }
7730   for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
7731     writemem[n] = write_nomem_new;
7732     writememb[n] = write_nomemb_new;
7733     writememh[n] = write_nomemh_new;
7734 #ifndef FORCE32
7735     writememd[n] = write_nomemd_new;
7736 #endif
7737     readmem[n] = read_nomem_new;
7738     readmemb[n] = read_nomemb_new;
7739     readmemh[n] = read_nomemh_new;
7740 #ifndef FORCE32
7741     readmemd[n] = read_nomemd_new;
7742 #endif
7743   }
7744 #endif
7745   tlb_hacks();
7746   arch_init();
7747 }
7748
7749 void new_dynarec_cleanup()
7750 {
7751   int n;
7752   if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
7753   for(n=0;n<4096;n++) ll_clear(jump_in+n);
7754   for(n=0;n<4096;n++) ll_clear(jump_out+n);
7755   for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7756   #ifdef ROM_COPY
7757   if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
7758   #endif
7759 }
7760
7761 int new_recompile_block(int addr)
7762 {
7763 /*
7764   if(addr==0x800cd050) {
7765     int block;
7766     for(block=0x80000;block<0x80800;block++) invalidate_block(block);
7767     int n;
7768     for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
7769   }
7770 */
7771   //if(Count==365117028) tracedebug=1;
7772   assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7773   //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7774   //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
7775   //if(debug)
7776   //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
7777   //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
7778   /*if(Count>=312978186) {
7779     rlist();
7780   }*/
7781   //rlist();
7782   start = (u_int)addr&~3;
7783   //assert(((u_int)addr&1)==0);
7784 #ifdef PCSX
7785   if (Config.HLE && start == 0x80001000) // hlecall
7786   {
7787     // XXX: is this enough? Maybe check hleSoftCall?
7788     u_int beginning=(u_int)out;
7789     u_int page=get_page(start);
7790     invalid_code[start>>12]=0;
7791     emit_movimm(start,0);
7792     emit_writeword(0,(int)&pcaddr);
7793     emit_jmp((int)new_dyna_leave);
7794 #ifdef __arm__
7795     __clear_cache((void *)beginning,out);
7796 #endif
7797     ll_add(jump_in+page,start,(void *)beginning);
7798     return 0;
7799   }
7800   else if ((u_int)addr < 0x00200000 ||
7801     (0xa0000000 <= addr && addr < 0xa0200000)) {
7802     // used for BIOS calls mostly?
7803     source = (u_int *)((u_int)rdram+(start&0x1fffff));
7804     pagelimit = (addr&0xa0000000)|0x00200000;
7805   }
7806   else if (!Config.HLE && (
7807 /*    (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
7808     (0xbfc00000 <= addr && addr < 0xbfc80000))) {
7809     // BIOS
7810     source = (u_int *)((u_int)psxR+(start&0x7ffff));
7811     pagelimit = (addr&0xfff00000)|0x80000;
7812   }
7813   else
7814 #endif
7815 #ifdef MUPEN64
7816   if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
7817     source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
7818     pagelimit = 0xa4001000;
7819   }
7820   else
7821 #endif
7822   if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
7823     source = (u_int *)((u_int)rdram+start-0x80000000);
7824     pagelimit = 0x80000000+RAM_SIZE;
7825   }
7826 #ifndef DISABLE_TLB
7827   else if ((signed int)addr >= (signed int)0xC0000000) {
7828     //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
7829     //if(tlb_LUT_r[start>>12])
7830       //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
7831     if((signed int)memory_map[start>>12]>=0) {
7832       source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
7833       pagelimit=(start+4096)&0xFFFFF000;
7834       int map=memory_map[start>>12];
7835       int i;
7836       for(i=0;i<5;i++) {
7837         //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
7838         if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
7839       }
7840       assem_debug("pagelimit=%x\n",pagelimit);
7841       assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
7842     }
7843     else {
7844       assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
7845       //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
7846       return -1; // Caller will invoke exception handler
7847     }
7848     //printf("source= %x\n",(int)source);
7849   }
7850 #endif
7851   else {
7852     printf("Compile at bogus memory address: %x \n", (int)addr);
7853     exit(1);
7854   }
7855
7856   /* Pass 1: disassemble */
7857   /* Pass 2: register dependencies, branch targets */
7858   /* Pass 3: register allocation */
7859   /* Pass 4: branch dependencies */
7860   /* Pass 5: pre-alloc */
7861   /* Pass 6: optimize clean/dirty state */
7862   /* Pass 7: flag 32-bit registers */
7863   /* Pass 8: assembly */
7864   /* Pass 9: linker */
7865   /* Pass 10: garbage collection / free memory */
7866
7867   int i,j;
7868   int done=0;
7869   unsigned int type,op,op2;
7870
7871   //printf("addr = %x source = %x %x\n", addr,source,source[0]);
7872
7873   /* Pass 1 disassembly */
7874
7875   for(i=0;!done;i++) {
7876     bt[i]=0;likely[i]=0;op2=0;
7877     opcode[i]=op=source[i]>>26;
7878     switch(op)
7879     {
7880       case 0x00: strcpy(insn[i],"special"); type=NI;
7881         op2=source[i]&0x3f;
7882         switch(op2)
7883         {
7884           case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
7885           case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
7886           case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
7887           case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
7888           case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
7889           case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
7890           case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
7891           case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
7892           case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
7893           case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
7894           case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
7895           case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
7896           case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
7897           case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
7898           case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
7899           case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
7900           case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
7901           case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
7902           case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
7903           case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
7904           case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
7905           case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
7906           case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
7907           case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
7908           case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
7909           case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
7910           case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
7911           case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
7912           case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
7913           case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
7914           case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
7915           case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
7916           case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
7917           case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
7918           case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
7919           case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
7920           case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
7921           case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
7922           case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
7923           case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
7924           case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
7925           case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
7926           case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
7927           case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
7928           case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
7929           case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
7930           case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
7931           case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
7932           case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
7933           case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
7934           case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
7935           case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
7936         }
7937         break;
7938       case 0x01: strcpy(insn[i],"regimm"); type=NI;
7939         op2=(source[i]>>16)&0x1f;
7940         switch(op2)
7941         {
7942           case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
7943           case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
7944           case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
7945           case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
7946           case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
7947           case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
7948           case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
7949           case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
7950           case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
7951           case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
7952           case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
7953           case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
7954           case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
7955           case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
7956         }
7957         break;
7958       case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
7959       case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
7960       case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
7961       case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
7962       case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
7963       case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
7964       case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
7965       case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
7966       case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
7967       case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
7968       case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
7969       case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
7970       case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
7971       case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
7972       case 0x10: strcpy(insn[i],"cop0"); type=NI;
7973         op2=(source[i]>>21)&0x1f;
7974         switch(op2)
7975         {
7976           case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
7977           case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
7978           case 0x10: strcpy(insn[i],"tlb"); type=NI;
7979           switch(source[i]&0x3f)
7980           {
7981             case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
7982             case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
7983             case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
7984             case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
7985 #ifdef PCSX
7986             case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
7987 #else
7988             case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
7989 #endif
7990           }
7991         }
7992         break;
7993       case 0x11: strcpy(insn[i],"cop1"); type=NI;
7994         op2=(source[i]>>21)&0x1f;
7995         switch(op2)
7996         {
7997           case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
7998           case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
7999           case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
8000           case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
8001           case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
8002           case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
8003           case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
8004           switch((source[i]>>16)&0x3)
8005           {
8006             case 0x00: strcpy(insn[i],"BC1F"); break;
8007             case 0x01: strcpy(insn[i],"BC1T"); break;
8008             case 0x02: strcpy(insn[i],"BC1FL"); break;
8009             case 0x03: strcpy(insn[i],"BC1TL"); break;
8010           }
8011           break;
8012           case 0x10: strcpy(insn[i],"C1.S"); type=NI;
8013           switch(source[i]&0x3f)
8014           {
8015             case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
8016             case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
8017             case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
8018             case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
8019             case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
8020             case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
8021             case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
8022             case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
8023             case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
8024             case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
8025             case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
8026             case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
8027             case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
8028             case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
8029             case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
8030             case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
8031             case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
8032             case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
8033             case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
8034             case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
8035             case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
8036             case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
8037             case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
8038             case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
8039             case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
8040             case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
8041             case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
8042             case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
8043             case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
8044             case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
8045             case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
8046             case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
8047             case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
8048             case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
8049             case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
8050           }
8051           break;
8052           case 0x11: strcpy(insn[i],"C1.D"); type=NI;
8053           switch(source[i]&0x3f)
8054           {
8055             case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
8056             case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
8057             case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
8058             case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
8059             case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
8060             case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
8061             case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
8062             case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
8063             case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
8064             case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
8065             case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
8066             case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
8067             case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
8068             case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
8069             case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
8070             case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
8071             case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
8072             case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
8073             case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
8074             case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
8075             case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
8076             case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
8077             case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
8078             case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
8079             case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
8080             case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
8081             case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
8082             case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
8083             case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
8084             case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
8085             case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8086             case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8087             case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8088             case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8089             case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8090           }
8091           break;
8092           case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8093           switch(source[i]&0x3f)
8094           {
8095             case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8096             case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8097           }
8098           break;
8099           case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8100           switch(source[i]&0x3f)
8101           {
8102             case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8103             case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8104           }
8105           break;
8106         }
8107         break;
8108 #ifndef FORCE32
8109       case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8110       case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8111       case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8112       case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8113       case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8114       case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8115       case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8116       case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
8117 #endif
8118       case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8119       case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8120       case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8121       case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8122       case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8123       case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8124       case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
8125       case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
8126       case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8127       case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8128       case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8129       case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
8130 #ifndef FORCE32
8131       case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8132       case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
8133 #endif
8134       case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8135       case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8136       case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8137       case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
8138 #ifndef FORCE32
8139       case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8140       case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8141       case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
8142 #endif
8143       case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8144       case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
8145 #ifndef FORCE32
8146       case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8147       case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8148       case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
8149 #endif
8150 #ifdef PCSX
8151       case 0x12: strcpy(insn[i],"COP2"); type=NI;
8152         // note: COP MIPS-1 encoding differs from MIPS32
8153         op2=(source[i]>>21)&0x1f;
8154         if (source[i]&0x3f) {
8155           if (gte_handlers[source[i]&0x3f]!=NULL) {
8156             snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8157             type=C2OP;
8158           }
8159         }
8160         else switch(op2)
8161         {
8162           case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8163           case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8164           case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8165           case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
8166         }
8167         break;
8168       case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8169       case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8170       case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8171 #endif
8172       default: strcpy(insn[i],"???"); type=NI;
8173         printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
8174         break;
8175     }
8176 #ifdef PCSX
8177     /* detect branch in delay slot early */
8178     if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
8179       opcode[i+1]=source[i+1]>>26;
8180       opcode2[i+1]=source[i+1]&0x3f;
8181       if((0<opcode[i+1]&&opcode[i+1]<8)||(opcode[i+1]==0&&(opcode2[i+1]==8||opcode2[i+1]==9))) {
8182         printf("branch in delay slot @%08x (%08x)\n", addr + i*4+4, addr);
8183         // don't handle first branch and call interpreter if it's hit
8184         type=INTCALL;
8185       }
8186     }
8187 #endif
8188     itype[i]=type;
8189     opcode2[i]=op2;
8190     /* Get registers/immediates */
8191     lt1[i]=0;
8192     us1[i]=0;
8193     us2[i]=0;
8194     dep1[i]=0;
8195     dep2[i]=0;
8196     switch(type) {
8197       case LOAD:
8198         rs1[i]=(source[i]>>21)&0x1f;
8199         rs2[i]=0;
8200         rt1[i]=(source[i]>>16)&0x1f;
8201         rt2[i]=0;
8202         imm[i]=(short)source[i];
8203         break;
8204       case STORE:
8205       case STORELR:
8206         rs1[i]=(source[i]>>21)&0x1f;
8207         rs2[i]=(source[i]>>16)&0x1f;
8208         rt1[i]=0;
8209         rt2[i]=0;
8210         imm[i]=(short)source[i];
8211         if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8212         break;
8213       case LOADLR:
8214         // LWL/LWR only load part of the register,
8215         // therefore the target register must be treated as a source too
8216         rs1[i]=(source[i]>>21)&0x1f;
8217         rs2[i]=(source[i]>>16)&0x1f;
8218         rt1[i]=(source[i]>>16)&0x1f;
8219         rt2[i]=0;
8220         imm[i]=(short)source[i];
8221         if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8222         if(op==0x26) dep1[i]=rt1[i]; // LWR
8223         break;
8224       case IMM16:
8225         if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8226         else rs1[i]=(source[i]>>21)&0x1f;
8227         rs2[i]=0;
8228         rt1[i]=(source[i]>>16)&0x1f;
8229         rt2[i]=0;
8230         if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8231           imm[i]=(unsigned short)source[i];
8232         }else{
8233           imm[i]=(short)source[i];
8234         }
8235         if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8236         if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8237         if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8238         break;
8239       case UJUMP:
8240         rs1[i]=0;
8241         rs2[i]=0;
8242         rt1[i]=0;
8243         rt2[i]=0;
8244         // The JAL instruction writes to r31.
8245         if (op&1) {
8246           rt1[i]=31;
8247         }
8248         rs2[i]=CCREG;
8249         break;
8250       case RJUMP:
8251         rs1[i]=(source[i]>>21)&0x1f;
8252         rs2[i]=0;
8253         rt1[i]=0;
8254         rt2[i]=0;
8255         // The JALR instruction writes to rd.
8256         if (op2&1) {
8257           rt1[i]=(source[i]>>11)&0x1f;
8258         }
8259         rs2[i]=CCREG;
8260         break;
8261       case CJUMP:
8262         rs1[i]=(source[i]>>21)&0x1f;
8263         rs2[i]=(source[i]>>16)&0x1f;
8264         rt1[i]=0;
8265         rt2[i]=0;
8266         if(op&2) { // BGTZ/BLEZ
8267           rs2[i]=0;
8268         }
8269         us1[i]=rs1[i];
8270         us2[i]=rs2[i];
8271         likely[i]=op>>4;
8272         break;
8273       case SJUMP:
8274         rs1[i]=(source[i]>>21)&0x1f;
8275         rs2[i]=CCREG;
8276         rt1[i]=0;
8277         rt2[i]=0;
8278         us1[i]=rs1[i];
8279         if(op2&0x10) { // BxxAL
8280           rt1[i]=31;
8281           // NOTE: If the branch is not taken, r31 is still overwritten
8282         }
8283         likely[i]=(op2&2)>>1;
8284         break;
8285       case FJUMP:
8286         rs1[i]=FSREG;
8287         rs2[i]=CSREG;
8288         rt1[i]=0;
8289         rt2[i]=0;
8290         likely[i]=((source[i])>>17)&1;
8291         break;
8292       case ALU:
8293         rs1[i]=(source[i]>>21)&0x1f; // source
8294         rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8295         rt1[i]=(source[i]>>11)&0x1f; // destination
8296         rt2[i]=0;
8297         if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8298           us1[i]=rs1[i];us2[i]=rs2[i];
8299         }
8300         else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8301           dep1[i]=rs1[i];dep2[i]=rs2[i];
8302         }
8303         else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8304           dep1[i]=rs1[i];dep2[i]=rs2[i];
8305         }
8306         break;
8307       case MULTDIV:
8308         rs1[i]=(source[i]>>21)&0x1f; // source
8309         rs2[i]=(source[i]>>16)&0x1f; // divisor
8310         rt1[i]=HIREG;
8311         rt2[i]=LOREG;
8312         if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8313           us1[i]=rs1[i];us2[i]=rs2[i];
8314         }
8315         break;
8316       case MOV:
8317         rs1[i]=0;
8318         rs2[i]=0;
8319         rt1[i]=0;
8320         rt2[i]=0;
8321         if(op2==0x10) rs1[i]=HIREG; // MFHI
8322         if(op2==0x11) rt1[i]=HIREG; // MTHI
8323         if(op2==0x12) rs1[i]=LOREG; // MFLO
8324         if(op2==0x13) rt1[i]=LOREG; // MTLO
8325         if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8326         if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8327         dep1[i]=rs1[i];
8328         break;
8329       case SHIFT:
8330         rs1[i]=(source[i]>>16)&0x1f; // target of shift
8331         rs2[i]=(source[i]>>21)&0x1f; // shift amount
8332         rt1[i]=(source[i]>>11)&0x1f; // destination
8333         rt2[i]=0;
8334         // DSLLV/DSRLV/DSRAV are 64-bit
8335         if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8336         break;
8337       case SHIFTIMM:
8338         rs1[i]=(source[i]>>16)&0x1f;
8339         rs2[i]=0;
8340         rt1[i]=(source[i]>>11)&0x1f;
8341         rt2[i]=0;
8342         imm[i]=(source[i]>>6)&0x1f;
8343         // DSxx32 instructions
8344         if(op2>=0x3c) imm[i]|=0x20;
8345         // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8346         if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8347         break;
8348       case COP0:
8349         rs1[i]=0;
8350         rs2[i]=0;
8351         rt1[i]=0;
8352         rt2[i]=0;
8353         if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8354         if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8355         if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8356         if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8357         break;
8358       case COP1:
8359       case COP2:
8360         rs1[i]=0;
8361         rs2[i]=0;
8362         rt1[i]=0;
8363         rt2[i]=0;
8364         if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8365         if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8366         if(op2==5) us1[i]=rs1[i]; // DMTC1
8367         rs2[i]=CSREG;
8368         break;
8369       case C1LS:
8370         rs1[i]=(source[i]>>21)&0x1F;
8371         rs2[i]=CSREG;
8372         rt1[i]=0;
8373         rt2[i]=0;
8374         imm[i]=(short)source[i];
8375         break;
8376       case C2LS:
8377         rs1[i]=(source[i]>>21)&0x1F;
8378         rs2[i]=0;
8379         rt1[i]=0;
8380         rt2[i]=0;
8381         imm[i]=(short)source[i];
8382         break;
8383       case FLOAT:
8384       case FCONV:
8385         rs1[i]=0;
8386         rs2[i]=CSREG;
8387         rt1[i]=0;
8388         rt2[i]=0;
8389         break;
8390       case FCOMP:
8391         rs1[i]=FSREG;
8392         rs2[i]=CSREG;
8393         rt1[i]=FSREG;
8394         rt2[i]=0;
8395         break;
8396       case SYSCALL:
8397       case HLECALL:
8398       case INTCALL:
8399         rs1[i]=CCREG;
8400         rs2[i]=0;
8401         rt1[i]=0;
8402         rt2[i]=0;
8403         break;
8404       default:
8405         rs1[i]=0;
8406         rs2[i]=0;
8407         rt1[i]=0;
8408         rt2[i]=0;
8409     }
8410     /* Calculate branch target addresses */
8411     if(type==UJUMP)
8412       ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8413     else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8414       ba[i]=start+i*4+8; // Ignore never taken branch
8415     else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8416       ba[i]=start+i*4+8; // Ignore never taken branch
8417     else if(type==CJUMP||type==SJUMP||type==FJUMP)
8418       ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8419     else ba[i]=-1;
8420     /* Is this the end of the block? */
8421     if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
8422 #ifdef PCSX
8423       // check for link register access in delay slot
8424       int rt1_=rt1[i-1];
8425       if(rt1_!=0&&(rs1[i]==rt1_||rs2[i]==rt1_||rt1[i]==rt1_||rt2[i]==rt1_)) {
8426         printf("link access in delay slot @%08x (%08x)\n", addr + i*4, addr);
8427         ba[i-1]=-1;
8428         itype[i-1]=INTCALL;
8429         done=2;
8430       }
8431       else
8432 #endif
8433       if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
8434         done=2;
8435       }
8436       else {
8437         if(stop_after_jal) done=1;
8438         // Stop on BREAK
8439         if((source[i+1]&0xfc00003f)==0x0d) done=1;
8440       }
8441       // Don't recompile stuff that's already compiled
8442       if(check_addr(start+i*4+4)) done=1;
8443       // Don't get too close to the limit
8444       if(i>MAXBLOCK/2) done=1;
8445     }
8446     if(itype[i]==SYSCALL&&stop_after_jal) done=1;
8447     if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
8448     if(done==2) {
8449       // Does the block continue due to a branch?
8450       for(j=i-1;j>=0;j--)
8451       {
8452         if(ba[j]==start+i*4+4) done=j=0;
8453         if(ba[j]==start+i*4+8) done=j=0;
8454       }
8455     }
8456     //assert(i<MAXBLOCK-1);
8457     if(start+i*4==pagelimit-4) done=1;
8458     assert(start+i*4<pagelimit);
8459     if (i==MAXBLOCK-1) done=1;
8460     // Stop if we're compiling junk
8461     if(itype[i]==NI&&opcode[i]==0x11) {
8462       done=stop_after_jal=1;
8463       printf("Disabled speculative precompilation\n");
8464     }
8465   }
8466   slen=i;
8467   if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8468     if(start+i*4==pagelimit) {
8469       itype[i-1]=SPAN;
8470     }
8471   }
8472   assert(slen>0);
8473
8474   /* Pass 2 - Register dependencies and branch targets */
8475
8476   unneeded_registers(0,slen-1,0);
8477
8478   /* Pass 3 - Register allocation */
8479
8480   struct regstat current; // Current register allocations/status
8481   current.is32=1;
8482   current.dirty=0;
8483   current.u=unneeded_reg[0];
8484   current.uu=unneeded_reg_upper[0];
8485   clear_all_regs(current.regmap);
8486   alloc_reg(&current,0,CCREG);
8487   dirty_reg(&current,CCREG);
8488   current.isconst=0;
8489   current.wasconst=0;
8490   int ds=0;
8491   int cc=0;
8492   int hr;
8493
8494 #ifndef FORCE32
8495   provisional_32bit();
8496 #endif
8497   if((u_int)addr&1) {
8498     // First instruction is delay slot
8499     cc=-1;
8500     bt[1]=1;
8501     ds=1;
8502     unneeded_reg[0]=1;
8503     unneeded_reg_upper[0]=1;
8504     current.regmap[HOST_BTREG]=BTREG;
8505   }
8506
8507   for(i=0;i<slen;i++)
8508   {
8509     if(bt[i])
8510     {
8511       int hr;
8512       for(hr=0;hr<HOST_REGS;hr++)
8513       {
8514         // Is this really necessary?
8515         if(current.regmap[hr]==0) current.regmap[hr]=-1;
8516       }
8517       current.isconst=0;
8518     }
8519     if(i>1)
8520     {
8521       if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8522       {
8523         if(rs1[i-2]==0||rs2[i-2]==0)
8524         {
8525           if(rs1[i-2]) {
8526             current.is32|=1LL<<rs1[i-2];
8527             int hr=get_reg(current.regmap,rs1[i-2]|64);
8528             if(hr>=0) current.regmap[hr]=-1;
8529           }
8530           if(rs2[i-2]) {
8531             current.is32|=1LL<<rs2[i-2];
8532             int hr=get_reg(current.regmap,rs2[i-2]|64);
8533             if(hr>=0) current.regmap[hr]=-1;
8534           }
8535         }
8536       }
8537     }
8538 #ifndef FORCE32
8539     // If something jumps here with 64-bit values
8540     // then promote those registers to 64 bits
8541     if(bt[i])
8542     {
8543       uint64_t temp_is32=current.is32;
8544       for(j=i-1;j>=0;j--)
8545       {
8546         if(ba[j]==start+i*4)
8547           temp_is32&=branch_regs[j].is32;
8548       }
8549       for(j=i;j<slen;j++)
8550       {
8551         if(ba[j]==start+i*4)
8552           //temp_is32=1;
8553           temp_is32&=p32[j];
8554       }
8555       if(temp_is32!=current.is32) {
8556         //printf("dumping 32-bit regs (%x)\n",start+i*4);
8557         #ifdef DESTRUCTIVE_WRITEBACK
8558         for(hr=0;hr<HOST_REGS;hr++)
8559         {
8560           int r=current.regmap[hr];
8561           if(r>0&&r<64)
8562           {
8563             if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8564               temp_is32|=1LL<<r;
8565               //printf("restore %d\n",r);
8566             }
8567           }
8568         }
8569         #endif
8570         current.is32=temp_is32;
8571       }
8572     }
8573 #else
8574     current.is32=-1LL;
8575 #endif
8576
8577     memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8578     regs[i].wasconst=current.isconst;
8579     regs[i].was32=current.is32;
8580     regs[i].wasdirty=current.dirty;
8581     #if defined(DESTRUCTIVE_WRITEBACK) && !defined(FORCE32)
8582     // To change a dirty register from 32 to 64 bits, we must write
8583     // it out during the previous cycle (for branches, 2 cycles)
8584     if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8585     {
8586       uint64_t temp_is32=current.is32;
8587       for(j=i-1;j>=0;j--)
8588       {
8589         if(ba[j]==start+i*4+4)
8590           temp_is32&=branch_regs[j].is32;
8591       }
8592       for(j=i;j<slen;j++)
8593       {
8594         if(ba[j]==start+i*4+4)
8595           //temp_is32=1;
8596           temp_is32&=p32[j];
8597       }
8598       if(temp_is32!=current.is32) {
8599         //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8600         for(hr=0;hr<HOST_REGS;hr++)
8601         {
8602           int r=current.regmap[hr];
8603           if(r>0)
8604           {
8605             if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8606               if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
8607               {
8608                 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
8609                 {
8610                   //printf("dump %d/r%d\n",hr,r);
8611                   current.regmap[hr]=-1;
8612                   if(get_reg(current.regmap,r|64)>=0)
8613                     current.regmap[get_reg(current.regmap,r|64)]=-1;
8614                 }
8615               }
8616             }
8617           }
8618         }
8619       }
8620     }
8621     else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
8622     {
8623       uint64_t temp_is32=current.is32;
8624       for(j=i-1;j>=0;j--)
8625       {
8626         if(ba[j]==start+i*4+8)
8627           temp_is32&=branch_regs[j].is32;
8628       }
8629       for(j=i;j<slen;j++)
8630       {
8631         if(ba[j]==start+i*4+8)
8632           //temp_is32=1;
8633           temp_is32&=p32[j];
8634       }
8635       if(temp_is32!=current.is32) {
8636         //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8637         for(hr=0;hr<HOST_REGS;hr++)
8638         {
8639           int r=current.regmap[hr];
8640           if(r>0)
8641           {
8642             if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8643               if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
8644               {
8645                 //printf("dump %d/r%d\n",hr,r);
8646                 current.regmap[hr]=-1;
8647                 if(get_reg(current.regmap,r|64)>=0)
8648                   current.regmap[get_reg(current.regmap,r|64)]=-1;
8649               }
8650             }
8651           }
8652         }
8653       }
8654     }
8655     #endif
8656     if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8657       if(i+1<slen) {
8658         current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8659         current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8660         if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8661         current.u|=1;
8662         current.uu|=1;
8663       } else {
8664         current.u=1;
8665         current.uu=1;
8666       }
8667     } else {
8668       if(i+1<slen) {
8669         current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
8670         current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8671         if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8672         current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8673         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8674         current.u|=1;
8675         current.uu|=1;
8676       } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
8677     }
8678     is_ds[i]=ds;
8679     if(ds) {
8680       ds=0; // Skip delay slot, already allocated as part of branch
8681       // ...but we need to alloc it in case something jumps here
8682       if(i+1<slen) {
8683         current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
8684         current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
8685       }else{
8686         current.u=branch_unneeded_reg[i-1];
8687         current.uu=branch_unneeded_reg_upper[i-1];
8688       }
8689       current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8690       current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8691       if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8692       current.u|=1;
8693       current.uu|=1;
8694       struct regstat temp;
8695       memcpy(&temp,&current,sizeof(current));
8696       temp.wasdirty=temp.dirty;
8697       temp.was32=temp.is32;
8698       // TODO: Take into account unconditional branches, as below
8699       delayslot_alloc(&temp,i);
8700       memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
8701       regs[i].wasdirty=temp.wasdirty;
8702       regs[i].was32=temp.was32;
8703       regs[i].dirty=temp.dirty;
8704       regs[i].is32=temp.is32;
8705       regs[i].isconst=0;
8706       regs[i].wasconst=0;
8707       current.isconst=0;
8708       // Create entry (branch target) regmap
8709       for(hr=0;hr<HOST_REGS;hr++)
8710       {
8711         int r=temp.regmap[hr];
8712         if(r>=0) {
8713           if(r!=regmap_pre[i][hr]) {
8714             regs[i].regmap_entry[hr]=-1;
8715           }
8716           else
8717           {
8718             if(r<64){
8719               if((current.u>>r)&1) {
8720                 regs[i].regmap_entry[hr]=-1;
8721                 regs[i].regmap[hr]=-1;
8722                 //Don't clear regs in the delay slot as the branch might need them
8723                 //current.regmap[hr]=-1;
8724               }else
8725                 regs[i].regmap_entry[hr]=r;
8726             }
8727             else {
8728               if((current.uu>>(r&63))&1) {
8729                 regs[i].regmap_entry[hr]=-1;
8730                 regs[i].regmap[hr]=-1;
8731                 //Don't clear regs in the delay slot as the branch might need them
8732                 //current.regmap[hr]=-1;
8733               }else
8734                 regs[i].regmap_entry[hr]=r;
8735             }
8736           }
8737         } else {
8738           // First instruction expects CCREG to be allocated
8739           if(i==0&&hr==HOST_CCREG)
8740             regs[i].regmap_entry[hr]=CCREG;
8741           else
8742             regs[i].regmap_entry[hr]=-1;
8743         }
8744       }
8745     }
8746     else { // Not delay slot
8747       switch(itype[i]) {
8748         case UJUMP:
8749           //current.isconst=0; // DEBUG
8750           //current.wasconst=0; // DEBUG
8751           //regs[i].wasconst=0; // DEBUG
8752           clear_const(&current,rt1[i]);
8753           alloc_cc(&current,i);
8754           dirty_reg(&current,CCREG);
8755           if (rt1[i]==31) {
8756             alloc_reg(&current,i,31);
8757             dirty_reg(&current,31);
8758             assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8759             assert(rt1[i+1]!=rt1[i]);
8760             #ifdef REG_PREFETCH
8761             alloc_reg(&current,i,PTEMP);
8762             #endif
8763             //current.is32|=1LL<<rt1[i];
8764           }
8765           delayslot_alloc(&current,i+1);
8766           //current.isconst=0; // DEBUG
8767           ds=1;
8768           //printf("i=%d, isconst=%x\n",i,current.isconst);
8769           break;
8770         case RJUMP:
8771           //current.isconst=0;
8772           //current.wasconst=0;
8773           //regs[i].wasconst=0;
8774           clear_const(&current,rs1[i]);
8775           clear_const(&current,rt1[i]);
8776           alloc_cc(&current,i);
8777           dirty_reg(&current,CCREG);
8778           if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
8779             alloc_reg(&current,i,rs1[i]);
8780             if (rt1[i]!=0) {
8781               alloc_reg(&current,i,rt1[i]);
8782               dirty_reg(&current,rt1[i]);
8783               assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
8784               assert(rt1[i+1]!=rt1[i]);
8785               #ifdef REG_PREFETCH
8786               alloc_reg(&current,i,PTEMP);
8787               #endif
8788             }
8789             #ifdef USE_MINI_HT
8790             if(rs1[i]==31) { // JALR
8791               alloc_reg(&current,i,RHASH);
8792               #ifndef HOST_IMM_ADDR32
8793               alloc_reg(&current,i,RHTBL);
8794               #endif
8795             }
8796             #endif
8797             delayslot_alloc(&current,i+1);
8798           } else {
8799             // The delay slot overwrites our source register,
8800             // allocate a temporary register to hold the old value.
8801             current.isconst=0;
8802             current.wasconst=0;
8803             regs[i].wasconst=0;
8804             delayslot_alloc(&current,i+1);
8805             current.isconst=0;
8806             alloc_reg(&current,i,RTEMP);
8807           }
8808           //current.isconst=0; // DEBUG
8809           ds=1;
8810           break;
8811         case CJUMP:
8812           //current.isconst=0;
8813           //current.wasconst=0;
8814           //regs[i].wasconst=0;
8815           clear_const(&current,rs1[i]);
8816           clear_const(&current,rs2[i]);
8817           if((opcode[i]&0x3E)==4) // BEQ/BNE
8818           {
8819             alloc_cc(&current,i);
8820             dirty_reg(&current,CCREG);
8821             if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8822             if(rs2[i]) alloc_reg(&current,i,rs2[i]);
8823             if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8824             {
8825               if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8826               if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
8827             }
8828             if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
8829                (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
8830               // The delay slot overwrites one of our conditions.
8831               // Allocate the branch condition registers instead.
8832               // Note that such a sequence of instructions could
8833               // be considered a bug since the branch can not be
8834               // re-executed if an exception occurs.
8835               current.isconst=0;
8836               current.wasconst=0;
8837               regs[i].wasconst=0;
8838               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8839               if(rs2[i]) alloc_reg(&current,i,rs2[i]);
8840               if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8841               {
8842                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8843                 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
8844               }
8845             }
8846             else delayslot_alloc(&current,i+1);
8847           }
8848           else
8849           if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
8850           {
8851             alloc_cc(&current,i);
8852             dirty_reg(&current,CCREG);
8853             alloc_reg(&current,i,rs1[i]);
8854             if(!(current.is32>>rs1[i]&1))
8855             {
8856               alloc_reg64(&current,i,rs1[i]);
8857             }
8858             if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
8859               // The delay slot overwrites one of our conditions.
8860               // Allocate the branch condition registers instead.
8861               // Note that such a sequence of instructions could
8862               // be considered a bug since the branch can not be
8863               // re-executed if an exception occurs.
8864               current.isconst=0;
8865               current.wasconst=0;
8866               regs[i].wasconst=0;
8867               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8868               if(!((current.is32>>rs1[i])&1))
8869               {
8870                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8871               }
8872             }
8873             else delayslot_alloc(&current,i+1);
8874           }
8875           else
8876           // Don't alloc the delay slot yet because we might not execute it
8877           if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
8878           {
8879             current.isconst=0;
8880             current.wasconst=0;
8881             regs[i].wasconst=0;
8882             alloc_cc(&current,i);
8883             dirty_reg(&current,CCREG);
8884             alloc_reg(&current,i,rs1[i]);
8885             alloc_reg(&current,i,rs2[i]);
8886             if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8887             {
8888               alloc_reg64(&current,i,rs1[i]);
8889               alloc_reg64(&current,i,rs2[i]);
8890             }
8891           }
8892           else
8893           if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
8894           {
8895             current.isconst=0;
8896             current.wasconst=0;
8897             regs[i].wasconst=0;
8898             alloc_cc(&current,i);
8899             dirty_reg(&current,CCREG);
8900             alloc_reg(&current,i,rs1[i]);
8901             if(!(current.is32>>rs1[i]&1))
8902             {
8903               alloc_reg64(&current,i,rs1[i]);
8904             }
8905           }
8906           ds=1;
8907           //current.isconst=0;
8908           break;
8909         case SJUMP:
8910           //current.isconst=0;
8911           //current.wasconst=0;
8912           //regs[i].wasconst=0;
8913           clear_const(&current,rs1[i]);
8914           clear_const(&current,rt1[i]);
8915           //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
8916           if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
8917           {
8918             alloc_cc(&current,i);
8919             dirty_reg(&current,CCREG);
8920             alloc_reg(&current,i,rs1[i]);
8921             if(!(current.is32>>rs1[i]&1))
8922             {
8923               alloc_reg64(&current,i,rs1[i]);
8924             }
8925             if (rt1[i]==31) { // BLTZAL/BGEZAL
8926               alloc_reg(&current,i,31);
8927               dirty_reg(&current,31);
8928               //#ifdef REG_PREFETCH
8929               //alloc_reg(&current,i,PTEMP);
8930               //#endif
8931               //current.is32|=1LL<<rt1[i];
8932             }
8933             if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
8934               // The delay slot overwrites the branch condition.
8935               // Allocate the branch condition registers instead.
8936               // Note that such a sequence of instructions could
8937               // be considered a bug since the branch can not be
8938               // re-executed if an exception occurs.
8939               current.isconst=0;
8940               current.wasconst=0;
8941               regs[i].wasconst=0;
8942               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8943               if(!((current.is32>>rs1[i])&1))
8944               {
8945                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8946               }
8947             }
8948             else delayslot_alloc(&current,i+1);
8949           }
8950           else
8951           // Don't alloc the delay slot yet because we might not execute it
8952           if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
8953           {
8954             current.isconst=0;
8955             current.wasconst=0;
8956             regs[i].wasconst=0;
8957             alloc_cc(&current,i);
8958             dirty_reg(&current,CCREG);
8959             alloc_reg(&current,i,rs1[i]);
8960             if(!(current.is32>>rs1[i]&1))
8961             {
8962               alloc_reg64(&current,i,rs1[i]);
8963             }
8964           }
8965           ds=1;
8966           //current.isconst=0;
8967           break;
8968         case FJUMP:
8969           current.isconst=0;
8970           current.wasconst=0;
8971           regs[i].wasconst=0;
8972           if(likely[i]==0) // BC1F/BC1T
8973           {
8974             // TODO: Theoretically we can run out of registers here on x86.
8975             // The delay slot can allocate up to six, and we need to check
8976             // CSREG before executing the delay slot.  Possibly we can drop
8977             // the cycle count and then reload it after checking that the
8978             // FPU is in a usable state, or don't do out-of-order execution.
8979             alloc_cc(&current,i);
8980             dirty_reg(&current,CCREG);
8981             alloc_reg(&current,i,FSREG);
8982             alloc_reg(&current,i,CSREG);
8983             if(itype[i+1]==FCOMP) {
8984               // The delay slot overwrites the branch condition.
8985               // Allocate the branch condition registers instead.
8986               // Note that such a sequence of instructions could
8987               // be considered a bug since the branch can not be
8988               // re-executed if an exception occurs.
8989               alloc_cc(&current,i);
8990               dirty_reg(&current,CCREG);
8991               alloc_reg(&current,i,CSREG);
8992               alloc_reg(&current,i,FSREG);
8993             }
8994             else {
8995               delayslot_alloc(&current,i+1);
8996               alloc_reg(&current,i+1,CSREG);
8997             }
8998           }
8999           else
9000           // Don't alloc the delay slot yet because we might not execute it
9001           if(likely[i]) // BC1FL/BC1TL
9002           {
9003             alloc_cc(&current,i);
9004             dirty_reg(&current,CCREG);
9005             alloc_reg(&current,i,CSREG);
9006             alloc_reg(&current,i,FSREG);
9007           }
9008           ds=1;
9009           current.isconst=0;
9010           break;
9011         case IMM16:
9012           imm16_alloc(&current,i);
9013           break;
9014         case LOAD:
9015         case LOADLR:
9016           load_alloc(&current,i);
9017           break;
9018         case STORE:
9019         case STORELR:
9020           store_alloc(&current,i);
9021           break;
9022         case ALU:
9023           alu_alloc(&current,i);
9024           break;
9025         case SHIFT:
9026           shift_alloc(&current,i);
9027           break;
9028         case MULTDIV:
9029           multdiv_alloc(&current,i);
9030           break;
9031         case SHIFTIMM:
9032           shiftimm_alloc(&current,i);
9033           break;
9034         case MOV:
9035           mov_alloc(&current,i);
9036           break;
9037         case COP0:
9038           cop0_alloc(&current,i);
9039           break;
9040         case COP1:
9041         case COP2:
9042           cop1_alloc(&current,i);
9043           break;
9044         case C1LS:
9045           c1ls_alloc(&current,i);
9046           break;
9047         case C2LS:
9048           c2ls_alloc(&current,i);
9049           break;
9050         case C2OP:
9051           c2op_alloc(&current,i);
9052           break;
9053         case FCONV:
9054           fconv_alloc(&current,i);
9055           break;
9056         case FLOAT:
9057           float_alloc(&current,i);
9058           break;
9059         case FCOMP:
9060           fcomp_alloc(&current,i);
9061           break;
9062         case SYSCALL:
9063         case HLECALL:
9064         case INTCALL:
9065           syscall_alloc(&current,i);
9066           break;
9067         case SPAN:
9068           pagespan_alloc(&current,i);
9069           break;
9070       }
9071
9072       // Drop the upper half of registers that have become 32-bit
9073       current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
9074       if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9075         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9076         if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9077         current.uu|=1;
9078       } else {
9079         current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
9080         current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9081         if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9082         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9083         current.uu|=1;
9084       }
9085
9086       // Create entry (branch target) regmap
9087       for(hr=0;hr<HOST_REGS;hr++)
9088       {
9089         int r,or,er;
9090         r=current.regmap[hr];
9091         if(r>=0) {
9092           if(r!=regmap_pre[i][hr]) {
9093             // TODO: delay slot (?)
9094             or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9095             if(or<0||(r&63)>=TEMPREG){
9096               regs[i].regmap_entry[hr]=-1;
9097             }
9098             else
9099             {
9100               // Just move it to a different register
9101               regs[i].regmap_entry[hr]=r;
9102               // If it was dirty before, it's still dirty
9103               if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r&63);
9104             }
9105           }
9106           else
9107           {
9108             // Unneeded
9109             if(r==0){
9110               regs[i].regmap_entry[hr]=0;
9111             }
9112             else
9113             if(r<64){
9114               if((current.u>>r)&1) {
9115                 regs[i].regmap_entry[hr]=-1;
9116                 //regs[i].regmap[hr]=-1;
9117                 current.regmap[hr]=-1;
9118               }else
9119                 regs[i].regmap_entry[hr]=r;
9120             }
9121             else {
9122               if((current.uu>>(r&63))&1) {
9123                 regs[i].regmap_entry[hr]=-1;
9124                 //regs[i].regmap[hr]=-1;
9125                 current.regmap[hr]=-1;
9126               }else
9127                 regs[i].regmap_entry[hr]=r;
9128             }
9129           }
9130         } else {
9131           // Branches expect CCREG to be allocated at the target
9132           if(regmap_pre[i][hr]==CCREG)
9133             regs[i].regmap_entry[hr]=CCREG;
9134           else
9135             regs[i].regmap_entry[hr]=-1;
9136         }
9137       }
9138       memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9139     }
9140     /* Branch post-alloc */
9141     if(i>0)
9142     {
9143       current.was32=current.is32;
9144       current.wasdirty=current.dirty;
9145       switch(itype[i-1]) {
9146         case UJUMP:
9147           memcpy(&branch_regs[i-1],&current,sizeof(current));
9148           branch_regs[i-1].isconst=0;
9149           branch_regs[i-1].wasconst=0;
9150           branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9151           branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9152           alloc_cc(&branch_regs[i-1],i-1);
9153           dirty_reg(&branch_regs[i-1],CCREG);
9154           if(rt1[i-1]==31) { // JAL
9155             alloc_reg(&branch_regs[i-1],i-1,31);
9156             dirty_reg(&branch_regs[i-1],31);
9157             branch_regs[i-1].is32|=1LL<<31;
9158           }
9159           memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9160           memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9161           break;
9162         case RJUMP:
9163           memcpy(&branch_regs[i-1],&current,sizeof(current));
9164           branch_regs[i-1].isconst=0;
9165           branch_regs[i-1].wasconst=0;
9166           branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9167           branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9168           alloc_cc(&branch_regs[i-1],i-1);
9169           dirty_reg(&branch_regs[i-1],CCREG);
9170           alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
9171           if(rt1[i-1]!=0) { // JALR
9172             alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9173             dirty_reg(&branch_regs[i-1],rt1[i-1]);
9174             branch_regs[i-1].is32|=1LL<<rt1[i-1];
9175           }
9176           #ifdef USE_MINI_HT
9177           if(rs1[i-1]==31) { // JALR
9178             alloc_reg(&branch_regs[i-1],i-1,RHASH);
9179             #ifndef HOST_IMM_ADDR32
9180             alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9181             #endif
9182           }
9183           #endif
9184           memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9185           memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9186           break;
9187         case CJUMP:
9188           if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9189           {
9190             alloc_cc(&current,i-1);
9191             dirty_reg(&current,CCREG);
9192             if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9193                (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9194               // The delay slot overwrote one of our conditions
9195               // Delay slot goes after the test (in order)
9196               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9197               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9198               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9199               current.u|=1;
9200               current.uu|=1;
9201               delayslot_alloc(&current,i);
9202               current.isconst=0;
9203             }
9204             else
9205             {
9206               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9207               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9208               // Alloc the branch condition registers
9209               if(rs1[i-1]) alloc_reg(&current,i-1,rs1[i-1]);
9210               if(rs2[i-1]) alloc_reg(&current,i-1,rs2[i-1]);
9211               if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9212               {
9213                 if(rs1[i-1]) alloc_reg64(&current,i-1,rs1[i-1]);
9214                 if(rs2[i-1]) alloc_reg64(&current,i-1,rs2[i-1]);
9215               }
9216             }
9217             memcpy(&branch_regs[i-1],&current,sizeof(current));
9218             branch_regs[i-1].isconst=0;
9219             branch_regs[i-1].wasconst=0;
9220             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9221             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9222           }
9223           else
9224           if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9225           {
9226             alloc_cc(&current,i-1);
9227             dirty_reg(&current,CCREG);
9228             if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9229               // The delay slot overwrote the branch condition
9230               // Delay slot goes after the test (in order)
9231               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9232               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9233               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9234               current.u|=1;
9235               current.uu|=1;
9236               delayslot_alloc(&current,i);
9237               current.isconst=0;
9238             }
9239             else
9240             {
9241               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9242               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9243               // Alloc the branch condition register
9244               alloc_reg(&current,i-1,rs1[i-1]);
9245               if(!(current.is32>>rs1[i-1]&1))
9246               {
9247                 alloc_reg64(&current,i-1,rs1[i-1]);
9248               }
9249             }
9250             memcpy(&branch_regs[i-1],&current,sizeof(current));
9251             branch_regs[i-1].isconst=0;
9252             branch_regs[i-1].wasconst=0;
9253             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9254             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9255           }
9256           else
9257           // Alloc the delay slot in case the branch is taken
9258           if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9259           {
9260             memcpy(&branch_regs[i-1],&current,sizeof(current));
9261             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9262             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9263             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9264             alloc_cc(&branch_regs[i-1],i);
9265             dirty_reg(&branch_regs[i-1],CCREG);
9266             delayslot_alloc(&branch_regs[i-1],i);
9267             branch_regs[i-1].isconst=0;
9268             alloc_reg(&current,i,CCREG); // Not taken path
9269             dirty_reg(&current,CCREG);
9270             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9271           }
9272           else
9273           if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9274           {
9275             memcpy(&branch_regs[i-1],&current,sizeof(current));
9276             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9277             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9278             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9279             alloc_cc(&branch_regs[i-1],i);
9280             dirty_reg(&branch_regs[i-1],CCREG);
9281             delayslot_alloc(&branch_regs[i-1],i);
9282             branch_regs[i-1].isconst=0;
9283             alloc_reg(&current,i,CCREG); // Not taken path
9284             dirty_reg(&current,CCREG);
9285             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9286           }
9287           break;
9288         case SJUMP:
9289           //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9290           if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9291           {
9292             alloc_cc(&current,i-1);
9293             dirty_reg(&current,CCREG);
9294             if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9295               // The delay slot overwrote the branch condition
9296               // Delay slot goes after the test (in order)
9297               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9298               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9299               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9300               current.u|=1;
9301               current.uu|=1;
9302               delayslot_alloc(&current,i);
9303               current.isconst=0;
9304             }
9305             else
9306             {
9307               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9308               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9309               // Alloc the branch condition register
9310               alloc_reg(&current,i-1,rs1[i-1]);
9311               if(!(current.is32>>rs1[i-1]&1))
9312               {
9313                 alloc_reg64(&current,i-1,rs1[i-1]);
9314               }
9315             }
9316             memcpy(&branch_regs[i-1],&current,sizeof(current));
9317             branch_regs[i-1].isconst=0;
9318             branch_regs[i-1].wasconst=0;
9319             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9320             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9321           }
9322           else
9323           // Alloc the delay slot in case the branch is taken
9324           if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9325           {
9326             memcpy(&branch_regs[i-1],&current,sizeof(current));
9327             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9328             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9329             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9330             alloc_cc(&branch_regs[i-1],i);
9331             dirty_reg(&branch_regs[i-1],CCREG);
9332             delayslot_alloc(&branch_regs[i-1],i);
9333             branch_regs[i-1].isconst=0;
9334             alloc_reg(&current,i,CCREG); // Not taken path
9335             dirty_reg(&current,CCREG);
9336             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9337           }
9338           // FIXME: BLTZAL/BGEZAL
9339           if(opcode2[i-1]&0x10) { // BxxZAL
9340             alloc_reg(&branch_regs[i-1],i-1,31);
9341             dirty_reg(&branch_regs[i-1],31);
9342             branch_regs[i-1].is32|=1LL<<31;
9343           }
9344           break;
9345         case FJUMP:
9346           if(likely[i-1]==0) // BC1F/BC1T
9347           {
9348             alloc_cc(&current,i-1);
9349             dirty_reg(&current,CCREG);
9350             if(itype[i]==FCOMP) {
9351               // The delay slot overwrote the branch condition
9352               // Delay slot goes after the test (in order)
9353               delayslot_alloc(&current,i);
9354               current.isconst=0;
9355             }
9356             else
9357             {
9358               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9359               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9360               // Alloc the branch condition register
9361               alloc_reg(&current,i-1,FSREG);
9362             }
9363             memcpy(&branch_regs[i-1],&current,sizeof(current));
9364             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9365           }
9366           else // BC1FL/BC1TL
9367           {
9368             // Alloc the delay slot in case the branch is taken
9369             memcpy(&branch_regs[i-1],&current,sizeof(current));
9370             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9371             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9372             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9373             alloc_cc(&branch_regs[i-1],i);
9374             dirty_reg(&branch_regs[i-1],CCREG);
9375             delayslot_alloc(&branch_regs[i-1],i);
9376             branch_regs[i-1].isconst=0;
9377             alloc_reg(&current,i,CCREG); // Not taken path
9378             dirty_reg(&current,CCREG);
9379             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9380           }
9381           break;
9382       }
9383
9384       if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9385       {
9386         if(rt1[i-1]==31) // JAL/JALR
9387         {
9388           // Subroutine call will return here, don't alloc any registers
9389           current.is32=1;
9390           current.dirty=0;
9391           clear_all_regs(current.regmap);
9392           alloc_reg(&current,i,CCREG);
9393           dirty_reg(&current,CCREG);
9394         }
9395         else if(i+1<slen)
9396         {
9397           // Internal branch will jump here, match registers to caller
9398           current.is32=0x3FFFFFFFFLL;
9399           current.dirty=0;
9400           clear_all_regs(current.regmap);
9401           alloc_reg(&current,i,CCREG);
9402           dirty_reg(&current,CCREG);
9403           for(j=i-1;j>=0;j--)
9404           {
9405             if(ba[j]==start+i*4+4) {
9406               memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9407               current.is32=branch_regs[j].is32;
9408               current.dirty=branch_regs[j].dirty;
9409               break;
9410             }
9411           }
9412           while(j>=0) {
9413             if(ba[j]==start+i*4+4) {
9414               for(hr=0;hr<HOST_REGS;hr++) {
9415                 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9416                   current.regmap[hr]=-1;
9417                 }
9418                 current.is32&=branch_regs[j].is32;
9419                 current.dirty&=branch_regs[j].dirty;
9420               }
9421             }
9422             j--;
9423           }
9424         }
9425       }
9426     }
9427
9428     // Count cycles in between branches
9429     ccadj[i]=cc;
9430     if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
9431     {
9432       cc=0;
9433     }
9434     else
9435     {
9436       cc++;
9437     }
9438
9439     flush_dirty_uppers(&current);
9440     if(!is_ds[i]) {
9441       regs[i].is32=current.is32;
9442       regs[i].dirty=current.dirty;
9443       regs[i].isconst=current.isconst;
9444       memcpy(constmap[i],current.constmap,sizeof(current.constmap));
9445     }
9446     for(hr=0;hr<HOST_REGS;hr++) {
9447       if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
9448         if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9449           regs[i].wasconst&=~(1<<hr);
9450         }
9451       }
9452     }
9453     if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9454   }
9455
9456   /* Pass 4 - Cull unused host registers */
9457
9458   uint64_t nr=0;
9459
9460   for (i=slen-1;i>=0;i--)
9461   {
9462     int hr;
9463     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9464     {
9465       if(ba[i]<start || ba[i]>=(start+slen*4))
9466       {
9467         // Branch out of this block, don't need anything
9468         nr=0;
9469       }
9470       else
9471       {
9472         // Internal branch
9473         // Need whatever matches the target
9474         nr=0;
9475         int t=(ba[i]-start)>>2;
9476         for(hr=0;hr<HOST_REGS;hr++)
9477         {
9478           if(regs[i].regmap_entry[hr]>=0) {
9479             if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9480           }
9481         }
9482       }
9483       // Conditional branch may need registers for following instructions
9484       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9485       {
9486         if(i<slen-2) {
9487           nr|=needed_reg[i+2];
9488           for(hr=0;hr<HOST_REGS;hr++)
9489           {
9490             if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9491             //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9492           }
9493         }
9494       }
9495       // Don't need stuff which is overwritten
9496       if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9497       if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9498       // Merge in delay slot
9499       for(hr=0;hr<HOST_REGS;hr++)
9500       {
9501         if(!likely[i]) {
9502           // These are overwritten unless the branch is "likely"
9503           // and the delay slot is nullified if not taken
9504           if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9505           if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9506         }
9507         if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9508         if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9509         if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9510         if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9511         if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9512         if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9513         if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9514         if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9515         if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9516           if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9517           if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9518         }
9519         if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9520           if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9521           if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9522         }
9523         if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
9524           if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9525           if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9526         }
9527       }
9528     }
9529     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
9530     {
9531       // SYSCALL instruction (software interrupt)
9532       nr=0;
9533     }
9534     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9535     {
9536       // ERET instruction (return from interrupt)
9537       nr=0;
9538     }
9539     else // Non-branch
9540     {
9541       if(i<slen-1) {
9542         for(hr=0;hr<HOST_REGS;hr++) {
9543           if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9544           if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9545           if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9546           if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9547         }
9548       }
9549     }
9550     for(hr=0;hr<HOST_REGS;hr++)
9551     {
9552       // Overwritten registers are not needed
9553       if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9554       if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9555       if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9556       // Source registers are needed
9557       if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9558       if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9559       if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9560       if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9561       if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9562       if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9563       if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9564       if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9565       if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9566         if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9567         if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9568       }
9569       if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
9570         if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9571         if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9572       }
9573       if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
9574         if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9575         if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9576       }
9577       // Don't store a register immediately after writing it,
9578       // may prevent dual-issue.
9579       // But do so if this is a branch target, otherwise we
9580       // might have to load the register before the branch.
9581       if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
9582         if((regmap_pre[i][hr]>0&&regmap_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
9583            (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
9584           if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9585           if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9586         }
9587         if((regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
9588            (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
9589           if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9590           if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9591         }
9592       }
9593     }
9594     // Cycle count is needed at branches.  Assume it is needed at the target too.
9595     if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
9596       if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9597       if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9598     }
9599     // Save it
9600     needed_reg[i]=nr;
9601
9602     // Deallocate unneeded registers
9603     for(hr=0;hr<HOST_REGS;hr++)
9604     {
9605       if(!((nr>>hr)&1)) {
9606         if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
9607         if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9608            (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9609            (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
9610         {
9611           if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9612           {
9613             if(likely[i]) {
9614               regs[i].regmap[hr]=-1;
9615               regs[i].isconst&=~(1<<hr);
9616               if(i<slen-2) regmap_pre[i+2][hr]=-1;
9617             }
9618           }
9619         }
9620         if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9621         {
9622           int d1=0,d2=0,map=0,temp=0;
9623           if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
9624           {
9625             d1=dep1[i+1];
9626             d2=dep2[i+1];
9627           }
9628           if(using_tlb) {
9629             if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
9630                itype[i+1]==STORE || itype[i+1]==STORELR ||
9631                itype[i+1]==C1LS || itype[i+1]==C2LS)
9632             map=TLREG;
9633           } else
9634           if(itype[i+1]==STORE || itype[i+1]==STORELR ||
9635              (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
9636             map=INVCP;
9637           }
9638           if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
9639              itype[i+1]==C1LS || itype[i+1]==C2LS)
9640             temp=FTEMP;
9641           if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9642              (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9643              (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
9644              (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
9645              (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9646              regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
9647              (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
9648              regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
9649              regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
9650              regs[i].regmap[hr]!=map )
9651           {
9652             regs[i].regmap[hr]=-1;
9653             regs[i].isconst&=~(1<<hr);
9654             if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
9655                (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
9656                (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
9657                (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
9658                (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
9659                branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
9660                (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
9661                branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
9662                branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
9663                branch_regs[i].regmap[hr]!=map)
9664             {
9665               branch_regs[i].regmap[hr]=-1;
9666               branch_regs[i].regmap_entry[hr]=-1;
9667               if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9668               {
9669                 if(!likely[i]&&i<slen-2) {
9670                   regmap_pre[i+2][hr]=-1;
9671                 }
9672               }
9673             }
9674           }
9675         }
9676         else
9677         {
9678           // Non-branch
9679           if(i>0)
9680           {
9681             int d1=0,d2=0,map=-1,temp=-1;
9682             if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
9683             {
9684               d1=dep1[i];
9685               d2=dep2[i];
9686             }
9687             if(using_tlb) {
9688               if(itype[i]==LOAD || itype[i]==LOADLR ||
9689                  itype[i]==STORE || itype[i]==STORELR ||
9690                  itype[i]==C1LS || itype[i]==C2LS)
9691               map=TLREG;
9692             } else if(itype[i]==STORE || itype[i]==STORELR ||
9693                       (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
9694               map=INVCP;
9695             }
9696             if(itype[i]==LOADLR || itype[i]==STORELR ||
9697                itype[i]==C1LS || itype[i]==C2LS)
9698               temp=FTEMP;
9699             if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9700                (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
9701                (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9702                regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
9703                (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
9704                (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
9705             {
9706               if(i<slen-1&&!is_ds[i]) {
9707                 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
9708                 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
9709                 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
9710                 {
9711                   printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
9712                   assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
9713                 }
9714                 regmap_pre[i+1][hr]=-1;
9715                 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
9716               }
9717               regs[i].regmap[hr]=-1;
9718               regs[i].isconst&=~(1<<hr);
9719             }
9720           }
9721         }
9722       }
9723     }
9724   }
9725
9726   /* Pass 5 - Pre-allocate registers */
9727
9728   // If a register is allocated during a loop, try to allocate it for the
9729   // entire loop, if possible.  This avoids loading/storing registers
9730   // inside of the loop.
9731
9732   signed char f_regmap[HOST_REGS];
9733   clear_all_regs(f_regmap);
9734   for(i=0;i<slen-1;i++)
9735   {
9736     if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9737     {
9738       if(ba[i]>=start && ba[i]<(start+i*4))
9739       if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
9740       ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
9741       ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
9742       ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
9743       ||itype[i+1]==FCOMP||itype[i+1]==FCONV
9744       ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
9745       {
9746         int t=(ba[i]-start)>>2;
9747         if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
9748         if(t<2||(itype[t-2]!=UJUMP)) // call/ret assumes no registers allocated
9749         for(hr=0;hr<HOST_REGS;hr++)
9750         {
9751           if(regs[i].regmap[hr]>64) {
9752             if(!((regs[i].dirty>>hr)&1))
9753               f_regmap[hr]=regs[i].regmap[hr];
9754             else f_regmap[hr]=-1;
9755           }
9756           else if(regs[i].regmap[hr]>=0) {
9757             if(f_regmap[hr]!=regs[i].regmap[hr]) {
9758               // dealloc old register
9759               int n;
9760               for(n=0;n<HOST_REGS;n++)
9761               {
9762                 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
9763               }
9764               // and alloc new one
9765               f_regmap[hr]=regs[i].regmap[hr];
9766             }
9767           }
9768           if(branch_regs[i].regmap[hr]>64) {
9769             if(!((branch_regs[i].dirty>>hr)&1))
9770               f_regmap[hr]=branch_regs[i].regmap[hr];
9771             else f_regmap[hr]=-1;
9772           }
9773           else if(branch_regs[i].regmap[hr]>=0) {
9774             if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
9775               // dealloc old register
9776               int n;
9777               for(n=0;n<HOST_REGS;n++)
9778               {
9779                 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
9780               }
9781               // and alloc new one
9782               f_regmap[hr]=branch_regs[i].regmap[hr];
9783             }
9784           }
9785           if(itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
9786           ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
9787           ||itype[i+1]==FCOMP||itype[i+1]==FCONV
9788           ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
9789           {
9790             // Test both in case the delay slot is ooo,
9791             // could be done better...
9792             if(count_free_regs(branch_regs[i].regmap)<2
9793              ||count_free_regs(regs[i].regmap)<2)
9794               f_regmap[hr]=branch_regs[i].regmap[hr];
9795           }
9796           // Avoid dirty->clean transition
9797           // #ifdef DESTRUCTIVE_WRITEBACK here?
9798           if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
9799           if(f_regmap[hr]>0) {
9800             if(regs[t].regmap_entry[hr]<0) {
9801               int r=f_regmap[hr];
9802               for(j=t;j<=i;j++)
9803               {
9804                 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9805                 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
9806                 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
9807                 if(r>63) {
9808                   // NB This can exclude the case where the upper-half
9809                   // register is lower numbered than the lower-half
9810                   // register.  Not sure if it's worth fixing...
9811                   if(get_reg(regs[j].regmap,r&63)<0) break;
9812                   if(regs[j].is32&(1LL<<(r&63))) break;
9813                 }
9814                 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
9815                   //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9816                   int k;
9817                   if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
9818                     if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
9819                     if(r>63) {
9820                       if(get_reg(regs[i].regmap,r&63)<0) break;
9821                       if(get_reg(branch_regs[i].regmap,r&63)<0) break;
9822                     }
9823                     k=i;
9824                     while(k>1&&regs[k-1].regmap[hr]==-1) {
9825                       if(itype[k-1]==STORE||itype[k-1]==STORELR
9826                       ||itype[k-1]==C1LS||itype[k-1]==SHIFT||itype[k-1]==COP1
9827                       ||itype[k-1]==FLOAT||itype[k-1]==FCONV||itype[k-1]==FCOMP
9828                       ||itype[k-1]==COP2||itype[k-1]==C2LS||itype[k-1]==C2OP) {
9829                         if(count_free_regs(regs[k-1].regmap)<2) {
9830                           //printf("no free regs for store %x\n",start+(k-1)*4);
9831                           break;
9832                         }
9833                       }
9834                       else
9835                       if(itype[k-1]!=NOP&&itype[k-1]!=MOV&&itype[k-1]!=ALU&&itype[k-1]!=SHIFTIMM&&itype[k-1]!=IMM16&&itype[k-1]!=LOAD) break;
9836                       if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
9837                         //printf("no-match due to different register\n");
9838                         break;
9839                       }
9840                       if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
9841                         //printf("no-match due to branch\n");
9842                         break;
9843                       }
9844                       // call/ret fast path assumes no registers allocated
9845                       if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)) {
9846                         break;
9847                       }
9848                       if(r>63) {
9849                         // NB This can exclude the case where the upper-half
9850                         // register is lower numbered than the lower-half
9851                         // register.  Not sure if it's worth fixing...
9852                         if(get_reg(regs[k-1].regmap,r&63)<0) break;
9853                         if(regs[k-1].is32&(1LL<<(r&63))) break;
9854                       }
9855                       k--;
9856                     }
9857                     if(i<slen-1) {
9858                       if((regs[k].is32&(1LL<<f_regmap[hr]))!=
9859                         (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
9860                         //printf("bad match after branch\n");
9861                         break;
9862                       }
9863                     }
9864                     if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
9865                       //printf("Extend r%d, %x ->\n",hr,start+k*4);
9866                       while(k<i) {
9867                         regs[k].regmap_entry[hr]=f_regmap[hr];
9868                         regs[k].regmap[hr]=f_regmap[hr];
9869                         regmap_pre[k+1][hr]=f_regmap[hr];
9870                         regs[k].wasdirty&=~(1<<hr);
9871                         regs[k].dirty&=~(1<<hr);
9872                         regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
9873                         regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
9874                         regs[k].wasconst&=~(1<<hr);
9875                         regs[k].isconst&=~(1<<hr);
9876                         k++;
9877                       }
9878                     }
9879                     else {
9880                       //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
9881                       break;
9882                     }
9883                     assert(regs[i-1].regmap[hr]==f_regmap[hr]);
9884                     if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
9885                       //printf("OK fill %x (r%d)\n",start+i*4,hr);
9886                       regs[i].regmap_entry[hr]=f_regmap[hr];
9887                       regs[i].regmap[hr]=f_regmap[hr];
9888                       regs[i].wasdirty&=~(1<<hr);
9889                       regs[i].dirty&=~(1<<hr);
9890                       regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
9891                       regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
9892                       regs[i].wasconst&=~(1<<hr);
9893                       regs[i].isconst&=~(1<<hr);
9894                       branch_regs[i].regmap_entry[hr]=f_regmap[hr];
9895                       branch_regs[i].wasdirty&=~(1<<hr);
9896                       branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
9897                       branch_regs[i].regmap[hr]=f_regmap[hr];
9898                       branch_regs[i].dirty&=~(1<<hr);
9899                       branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
9900                       branch_regs[i].wasconst&=~(1<<hr);
9901                       branch_regs[i].isconst&=~(1<<hr);
9902                       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
9903                         regmap_pre[i+2][hr]=f_regmap[hr];
9904                         regs[i+2].wasdirty&=~(1<<hr);
9905                         regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
9906                         assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
9907                           (regs[i+2].was32&(1LL<<f_regmap[hr])));
9908                       }
9909                     }
9910                   }
9911                   for(k=t;k<j;k++) {
9912                     regs[k].regmap_entry[hr]=f_regmap[hr];
9913                     regs[k].regmap[hr]=f_regmap[hr];
9914                     regmap_pre[k+1][hr]=f_regmap[hr];
9915                     regs[k+1].wasdirty&=~(1<<hr);
9916                     regs[k].dirty&=~(1<<hr);
9917                     regs[k].wasconst&=~(1<<hr);
9918                     regs[k].isconst&=~(1<<hr);
9919                   }
9920                   if(regs[j].regmap[hr]==f_regmap[hr])
9921                     regs[j].regmap_entry[hr]=f_regmap[hr];
9922                   break;
9923                 }
9924                 if(j==i) break;
9925                 if(regs[j].regmap[hr]>=0)
9926                   break;
9927                 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
9928                   //printf("no-match due to different register\n");
9929                   break;
9930                 }
9931                 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
9932                   //printf("32/64 mismatch %x %d\n",start+j*4,hr);
9933                   break;
9934                 }
9935                 if(itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS
9936                 ||itype[j]==SHIFT||itype[j]==COP1||itype[j]==FLOAT
9937                 ||itype[j]==FCOMP||itype[j]==FCONV
9938                 ||itype[j]==COP2||itype[j]==C2LS||itype[j]==C2OP) {
9939                   if(count_free_regs(regs[j].regmap)<2) {
9940                     //printf("No free regs for store %x\n",start+j*4);
9941                     break;
9942                   }
9943                 }
9944                 else if(itype[j]!=NOP&&itype[j]!=MOV&&itype[j]!=ALU&&itype[j]!=SHIFTIMM&&itype[j]!=IMM16&&itype[j]!=LOAD) break;
9945                 if(f_regmap[hr]>=64) {
9946                   if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
9947                     break;
9948                   }
9949                   else
9950                   {
9951                     if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
9952                       break;
9953                     }
9954                   }
9955                 }
9956               }
9957             }
9958           }
9959         }
9960       }
9961     }else{
9962       int count=0;
9963       for(hr=0;hr<HOST_REGS;hr++)
9964       {
9965         if(hr!=EXCLUDE_REG) {
9966           if(regs[i].regmap[hr]>64) {
9967             if(!((regs[i].dirty>>hr)&1))
9968               f_regmap[hr]=regs[i].regmap[hr];
9969           }
9970           else if(regs[i].regmap[hr]>=0) {
9971             if(f_regmap[hr]!=regs[i].regmap[hr]) {
9972               // dealloc old register
9973               int n;
9974               for(n=0;n<HOST_REGS;n++)
9975               {
9976                 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
9977               }
9978               // and alloc new one
9979               f_regmap[hr]=regs[i].regmap[hr];
9980             }
9981           }
9982           else if(regs[i].regmap[hr]<0) count++;
9983         }
9984       }
9985       // Try to restore cycle count at branch targets
9986       if(bt[i]) {
9987         for(j=i;j<slen-1;j++) {
9988           if(regs[j].regmap[HOST_CCREG]!=-1) break;
9989           if(itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS
9990           ||itype[j]==SHIFT||itype[j]==COP1||itype[j]==FLOAT
9991           ||itype[j]==FCOMP||itype[j]==FCONV
9992           ||itype[j]==COP2||itype[j]==C2LS||itype[j]==C2OP) {
9993             if(count_free_regs(regs[j].regmap)<2) {
9994               //printf("no free regs for store %x\n",start+j*4);
9995               break;
9996             }
9997           }
9998           else
9999           if(itype[j]!=NOP&&itype[j]!=MOV&&itype[j]!=ALU&&itype[j]!=SHIFTIMM&&itype[j]!=IMM16&&itype[j]!=LOAD) break;
10000         }
10001         if(regs[j].regmap[HOST_CCREG]==CCREG) {
10002           int k=i;
10003           //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
10004           while(k<j) {
10005             regs[k].regmap_entry[HOST_CCREG]=CCREG;
10006             regs[k].regmap[HOST_CCREG]=CCREG;
10007             regmap_pre[k+1][HOST_CCREG]=CCREG;
10008             regs[k+1].wasdirty|=1<<HOST_CCREG;
10009             regs[k].dirty|=1<<HOST_CCREG;
10010             regs[k].wasconst&=~(1<<HOST_CCREG);
10011             regs[k].isconst&=~(1<<HOST_CCREG);
10012             k++;
10013           }
10014           regs[j].regmap_entry[HOST_CCREG]=CCREG;
10015         }
10016         // Work backwards from the branch target
10017         if(j>i&&f_regmap[HOST_CCREG]==CCREG)
10018         {
10019           //printf("Extend backwards\n");
10020           int k;
10021           k=i;
10022           while(regs[k-1].regmap[HOST_CCREG]==-1) {
10023             if(itype[k-1]==STORE||itype[k-1]==STORELR||itype[k-1]==C1LS
10024             ||itype[k-1]==SHIFT||itype[k-1]==COP1||itype[k-1]==FLOAT
10025             ||itype[k-1]==FCONV||itype[k-1]==FCOMP
10026             ||itype[k-1]==COP2||itype[k-1]==C2LS||itype[k-1]==C2OP) {
10027               if(count_free_regs(regs[k-1].regmap)<2) {
10028                 //printf("no free regs for store %x\n",start+(k-1)*4);
10029                 break;
10030               }
10031             }
10032             else
10033             if(itype[k-1]!=NOP&&itype[k-1]!=MOV&&itype[k-1]!=ALU&&itype[k-1]!=SHIFTIMM&&itype[k-1]!=IMM16&&itype[k-1]!=LOAD) break;
10034             k--;
10035           }
10036           if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
10037             //printf("Extend CC, %x ->\n",start+k*4);
10038             while(k<=i) {
10039               regs[k].regmap_entry[HOST_CCREG]=CCREG;
10040               regs[k].regmap[HOST_CCREG]=CCREG;
10041               regmap_pre[k+1][HOST_CCREG]=CCREG;
10042               regs[k+1].wasdirty|=1<<HOST_CCREG;
10043               regs[k].dirty|=1<<HOST_CCREG;
10044               regs[k].wasconst&=~(1<<HOST_CCREG);
10045               regs[k].isconst&=~(1<<HOST_CCREG);
10046               k++;
10047             }
10048           }
10049           else {
10050             //printf("Fail Extend CC, %x ->\n",start+k*4);
10051           }
10052         }
10053       }
10054       if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
10055          itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
10056          itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
10057          itype[i]!=FCONV&&itype[i]!=FCOMP&&
10058          itype[i]!=COP2&&itype[i]!=C2LS&&itype[i]!=C2OP)
10059       {
10060         memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
10061       }
10062     }
10063   }
10064
10065   // This allocates registers (if possible) one instruction prior
10066   // to use, which can avoid a load-use penalty on certain CPUs.
10067   for(i=0;i<slen-1;i++)
10068   {
10069     if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10070     {
10071       if(!bt[i+1])
10072       {
10073         if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
10074            ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
10075         {
10076           if(rs1[i+1]) {
10077             if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10078             {
10079               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10080               {
10081                 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10082                 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10083                 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10084                 regs[i].isconst&=~(1<<hr);
10085                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10086                 constmap[i][hr]=constmap[i+1][hr];
10087                 regs[i+1].wasdirty&=~(1<<hr);
10088                 regs[i].dirty&=~(1<<hr);
10089               }
10090             }
10091           }
10092           if(rs2[i+1]) {
10093             if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10094             {
10095               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10096               {
10097                 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10098                 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10099                 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10100                 regs[i].isconst&=~(1<<hr);
10101                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10102                 constmap[i][hr]=constmap[i+1][hr];
10103                 regs[i+1].wasdirty&=~(1<<hr);
10104                 regs[i].dirty&=~(1<<hr);
10105               }
10106             }
10107           }
10108           if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10109             if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10110             {
10111               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10112               {
10113                 regs[i].regmap[hr]=rs1[i+1];
10114                 regmap_pre[i+1][hr]=rs1[i+1];
10115                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10116                 regs[i].isconst&=~(1<<hr);
10117                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10118                 constmap[i][hr]=constmap[i+1][hr];
10119                 regs[i+1].wasdirty&=~(1<<hr);
10120                 regs[i].dirty&=~(1<<hr);
10121               }
10122             }
10123           }
10124           if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10125             if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10126             {
10127               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10128               {
10129                 regs[i].regmap[hr]=rs1[i+1];
10130                 regmap_pre[i+1][hr]=rs1[i+1];
10131                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10132                 regs[i].isconst&=~(1<<hr);
10133                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10134                 constmap[i][hr]=constmap[i+1][hr];
10135                 regs[i+1].wasdirty&=~(1<<hr);
10136                 regs[i].dirty&=~(1<<hr);
10137               }
10138             }
10139           }
10140           #ifndef HOST_IMM_ADDR32
10141           if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
10142             hr=get_reg(regs[i+1].regmap,TLREG);
10143             if(hr>=0) {
10144               int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10145               if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10146                 int nr;
10147                 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10148                 {
10149                   regs[i].regmap[hr]=MGEN1+((i+1)&1);
10150                   regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10151                   regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10152                   regs[i].isconst&=~(1<<hr);
10153                   regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10154                   constmap[i][hr]=constmap[i+1][hr];
10155                   regs[i+1].wasdirty&=~(1<<hr);
10156                   regs[i].dirty&=~(1<<hr);
10157                 }
10158                 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10159                 {
10160                   // move it to another register
10161                   regs[i+1].regmap[hr]=-1;
10162                   regmap_pre[i+2][hr]=-1;
10163                   regs[i+1].regmap[nr]=TLREG;
10164                   regmap_pre[i+2][nr]=TLREG;
10165                   regs[i].regmap[nr]=MGEN1+((i+1)&1);
10166                   regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10167                   regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10168                   regs[i].isconst&=~(1<<nr);
10169                   regs[i+1].isconst&=~(1<<nr);
10170                   regs[i].dirty&=~(1<<nr);
10171                   regs[i+1].wasdirty&=~(1<<nr);
10172                   regs[i+1].dirty&=~(1<<nr);
10173                   regs[i+2].wasdirty&=~(1<<nr);
10174                 }
10175               }
10176             }
10177           }
10178           #endif
10179           if(itype[i+1]==STORE||itype[i+1]==STORELR
10180              ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
10181             if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10182               hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10183               if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10184               else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10185               assert(hr>=0);
10186               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10187               {
10188                 regs[i].regmap[hr]=rs1[i+1];
10189                 regmap_pre[i+1][hr]=rs1[i+1];
10190                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10191                 regs[i].isconst&=~(1<<hr);
10192                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10193                 constmap[i][hr]=constmap[i+1][hr];
10194                 regs[i+1].wasdirty&=~(1<<hr);
10195                 regs[i].dirty&=~(1<<hr);
10196               }
10197             }
10198           }
10199           if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
10200             if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10201               int nr;
10202               hr=get_reg(regs[i+1].regmap,FTEMP);
10203               assert(hr>=0);
10204               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10205               {
10206                 regs[i].regmap[hr]=rs1[i+1];
10207                 regmap_pre[i+1][hr]=rs1[i+1];
10208                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10209                 regs[i].isconst&=~(1<<hr);
10210                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10211                 constmap[i][hr]=constmap[i+1][hr];
10212                 regs[i+1].wasdirty&=~(1<<hr);
10213                 regs[i].dirty&=~(1<<hr);
10214               }
10215               else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10216               {
10217                 // move it to another register
10218                 regs[i+1].regmap[hr]=-1;
10219                 regmap_pre[i+2][hr]=-1;
10220                 regs[i+1].regmap[nr]=FTEMP;
10221                 regmap_pre[i+2][nr]=FTEMP;
10222                 regs[i].regmap[nr]=rs1[i+1];
10223                 regmap_pre[i+1][nr]=rs1[i+1];
10224                 regs[i+1].regmap_entry[nr]=rs1[i+1];
10225                 regs[i].isconst&=~(1<<nr);
10226                 regs[i+1].isconst&=~(1<<nr);
10227                 regs[i].dirty&=~(1<<nr);
10228                 regs[i+1].wasdirty&=~(1<<nr);
10229                 regs[i+1].dirty&=~(1<<nr);
10230                 regs[i+2].wasdirty&=~(1<<nr);
10231               }
10232             }
10233           }
10234           if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
10235             if(itype[i+1]==LOAD)
10236               hr=get_reg(regs[i+1].regmap,rt1[i+1]);
10237             if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
10238               hr=get_reg(regs[i+1].regmap,FTEMP);
10239             if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
10240               hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10241               if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10242             }
10243             if(hr>=0&&regs[i].regmap[hr]<0) {
10244               int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10245               if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10246                 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10247                 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10248                 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10249                 regs[i].isconst&=~(1<<hr);
10250                 regs[i+1].wasdirty&=~(1<<hr);
10251                 regs[i].dirty&=~(1<<hr);
10252               }
10253             }
10254           }
10255         }
10256       }
10257     }
10258   }
10259
10260   /* Pass 6 - Optimize clean/dirty state */
10261   clean_registers(0,slen-1,1);
10262
10263   /* Pass 7 - Identify 32-bit registers */
10264
10265   provisional_r32();
10266
10267   u_int r32=0;
10268
10269   for (i=slen-1;i>=0;i--)
10270   {
10271     int hr;
10272     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10273     {
10274       if(ba[i]<start || ba[i]>=(start+slen*4))
10275       {
10276         // Branch out of this block, don't need anything
10277         r32=0;
10278       }
10279       else
10280       {
10281         // Internal branch
10282         // Need whatever matches the target
10283         // (and doesn't get overwritten by the delay slot instruction)
10284         r32=0;
10285         int t=(ba[i]-start)>>2;
10286         if(ba[i]>start+i*4) {
10287           // Forward branch
10288           if(!(requires_32bit[t]&~regs[i].was32))
10289             r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10290         }else{
10291           // Backward branch
10292           //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10293           //  r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10294           if(!(pr32[t]&~regs[i].was32))
10295             r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10296         }
10297       }
10298       // Conditional branch may need registers for following instructions
10299       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10300       {
10301         if(i<slen-2) {
10302           r32|=requires_32bit[i+2];
10303           r32&=regs[i].was32;
10304           // Mark this address as a branch target since it may be called
10305           // upon return from interrupt
10306           bt[i+2]=1;
10307         }
10308       }
10309       // Merge in delay slot
10310       if(!likely[i]) {
10311         // These are overwritten unless the branch is "likely"
10312         // and the delay slot is nullified if not taken
10313         r32&=~(1LL<<rt1[i+1]);
10314         r32&=~(1LL<<rt2[i+1]);
10315       }
10316       // Assume these are needed (delay slot)
10317       if(us1[i+1]>0)
10318       {
10319         if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10320       }
10321       if(us2[i+1]>0)
10322       {
10323         if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10324       }
10325       if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10326       {
10327         if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10328       }
10329       if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10330       {
10331         if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10332       }
10333     }
10334     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
10335     {
10336       // SYSCALL instruction (software interrupt)
10337       r32=0;
10338     }
10339     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10340     {
10341       // ERET instruction (return from interrupt)
10342       r32=0;
10343     }
10344     // Check 32 bits
10345     r32&=~(1LL<<rt1[i]);
10346     r32&=~(1LL<<rt2[i]);
10347     if(us1[i]>0)
10348     {
10349       if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10350     }
10351     if(us2[i]>0)
10352     {
10353       if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10354     }
10355     if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
10356     {
10357       if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
10358     }
10359     if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
10360     {
10361       if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
10362     }
10363     requires_32bit[i]=r32;
10364
10365     // Dirty registers which are 32-bit, require 32-bit input
10366     // as they will be written as 32-bit values
10367     for(hr=0;hr<HOST_REGS;hr++)
10368     {
10369       if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
10370         if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
10371           if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
10372           requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
10373         }
10374       }
10375     }
10376     //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
10377   }
10378
10379   if(itype[slen-1]==SPAN) {
10380     bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
10381   }
10382
10383   /* Debug/disassembly */
10384   if((void*)assem_debug==(void*)printf)
10385   for(i=0;i<slen;i++)
10386   {
10387     printf("U:");
10388     int r;
10389     for(r=1;r<=CCREG;r++) {
10390       if((unneeded_reg[i]>>r)&1) {
10391         if(r==HIREG) printf(" HI");
10392         else if(r==LOREG) printf(" LO");
10393         else printf(" r%d",r);
10394       }
10395     }
10396 #ifndef FORCE32
10397     printf(" UU:");
10398     for(r=1;r<=CCREG;r++) {
10399       if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
10400         if(r==HIREG) printf(" HI");
10401         else if(r==LOREG) printf(" LO");
10402         else printf(" r%d",r);
10403       }
10404     }
10405     printf(" 32:");
10406     for(r=0;r<=CCREG;r++) {
10407       //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10408       if((regs[i].was32>>r)&1) {
10409         if(r==CCREG) printf(" CC");
10410         else if(r==HIREG) printf(" HI");
10411         else if(r==LOREG) printf(" LO");
10412         else printf(" r%d",r);
10413       }
10414     }
10415 #endif
10416     printf("\n");
10417     #if defined(__i386__) || defined(__x86_64__)
10418     printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
10419     #endif
10420     #ifdef __arm__
10421     printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
10422     #endif
10423     printf("needs: ");
10424     if(needed_reg[i]&1) printf("eax ");
10425     if((needed_reg[i]>>1)&1) printf("ecx ");
10426     if((needed_reg[i]>>2)&1) printf("edx ");
10427     if((needed_reg[i]>>3)&1) printf("ebx ");
10428     if((needed_reg[i]>>5)&1) printf("ebp ");
10429     if((needed_reg[i]>>6)&1) printf("esi ");
10430     if((needed_reg[i]>>7)&1) printf("edi ");
10431     printf("r:");
10432     for(r=0;r<=CCREG;r++) {
10433       //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10434       if((requires_32bit[i]>>r)&1) {
10435         if(r==CCREG) printf(" CC");
10436         else if(r==HIREG) printf(" HI");
10437         else if(r==LOREG) printf(" LO");
10438         else printf(" r%d",r);
10439       }
10440     }
10441     printf("\n");
10442     /*printf("pr:");
10443     for(r=0;r<=CCREG;r++) {
10444       //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10445       if((pr32[i]>>r)&1) {
10446         if(r==CCREG) printf(" CC");
10447         else if(r==HIREG) printf(" HI");
10448         else if(r==LOREG) printf(" LO");
10449         else printf(" r%d",r);
10450       }
10451     }
10452     if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
10453     printf("\n");*/
10454     #if defined(__i386__) || defined(__x86_64__)
10455     printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
10456     printf("dirty: ");
10457     if(regs[i].wasdirty&1) printf("eax ");
10458     if((regs[i].wasdirty>>1)&1) printf("ecx ");
10459     if((regs[i].wasdirty>>2)&1) printf("edx ");
10460     if((regs[i].wasdirty>>3)&1) printf("ebx ");
10461     if((regs[i].wasdirty>>5)&1) printf("ebp ");
10462     if((regs[i].wasdirty>>6)&1) printf("esi ");
10463     if((regs[i].wasdirty>>7)&1) printf("edi ");
10464     #endif
10465     #ifdef __arm__
10466     printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
10467     printf("dirty: ");
10468     if(regs[i].wasdirty&1) printf("r0 ");
10469     if((regs[i].wasdirty>>1)&1) printf("r1 ");
10470     if((regs[i].wasdirty>>2)&1) printf("r2 ");
10471     if((regs[i].wasdirty>>3)&1) printf("r3 ");
10472     if((regs[i].wasdirty>>4)&1) printf("r4 ");
10473     if((regs[i].wasdirty>>5)&1) printf("r5 ");
10474     if((regs[i].wasdirty>>6)&1) printf("r6 ");
10475     if((regs[i].wasdirty>>7)&1) printf("r7 ");
10476     if((regs[i].wasdirty>>8)&1) printf("r8 ");
10477     if((regs[i].wasdirty>>9)&1) printf("r9 ");
10478     if((regs[i].wasdirty>>10)&1) printf("r10 ");
10479     if((regs[i].wasdirty>>12)&1) printf("r12 ");
10480     #endif
10481     printf("\n");
10482     disassemble_inst(i);
10483     //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
10484     #if defined(__i386__) || defined(__x86_64__)
10485     printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
10486     if(regs[i].dirty&1) printf("eax ");
10487     if((regs[i].dirty>>1)&1) printf("ecx ");
10488     if((regs[i].dirty>>2)&1) printf("edx ");
10489     if((regs[i].dirty>>3)&1) printf("ebx ");
10490     if((regs[i].dirty>>5)&1) printf("ebp ");
10491     if((regs[i].dirty>>6)&1) printf("esi ");
10492     if((regs[i].dirty>>7)&1) printf("edi ");
10493     #endif
10494     #ifdef __arm__
10495     printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
10496     if(regs[i].dirty&1) printf("r0 ");
10497     if((regs[i].dirty>>1)&1) printf("r1 ");
10498     if((regs[i].dirty>>2)&1) printf("r2 ");
10499     if((regs[i].dirty>>3)&1) printf("r3 ");
10500     if((regs[i].dirty>>4)&1) printf("r4 ");
10501     if((regs[i].dirty>>5)&1) printf("r5 ");
10502     if((regs[i].dirty>>6)&1) printf("r6 ");
10503     if((regs[i].dirty>>7)&1) printf("r7 ");
10504     if((regs[i].dirty>>8)&1) printf("r8 ");
10505     if((regs[i].dirty>>9)&1) printf("r9 ");
10506     if((regs[i].dirty>>10)&1) printf("r10 ");
10507     if((regs[i].dirty>>12)&1) printf("r12 ");
10508     #endif
10509     printf("\n");
10510     if(regs[i].isconst) {
10511       printf("constants: ");
10512       #if defined(__i386__) || defined(__x86_64__)
10513       if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
10514       if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
10515       if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
10516       if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
10517       if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
10518       if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
10519       if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
10520       #endif
10521       #ifdef __arm__
10522       if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
10523       if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
10524       if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
10525       if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
10526       if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
10527       if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
10528       if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
10529       if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
10530       if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
10531       if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
10532       if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
10533       if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
10534       #endif
10535       printf("\n");
10536     }
10537 #ifndef FORCE32
10538     printf(" 32:");
10539     for(r=0;r<=CCREG;r++) {
10540       if((regs[i].is32>>r)&1) {
10541         if(r==CCREG) printf(" CC");
10542         else if(r==HIREG) printf(" HI");
10543         else if(r==LOREG) printf(" LO");
10544         else printf(" r%d",r);
10545       }
10546     }
10547     printf("\n");
10548 #endif
10549     /*printf(" p32:");
10550     for(r=0;r<=CCREG;r++) {
10551       if((p32[i]>>r)&1) {
10552         if(r==CCREG) printf(" CC");
10553         else if(r==HIREG) printf(" HI");
10554         else if(r==LOREG) printf(" LO");
10555         else printf(" r%d",r);
10556       }
10557     }
10558     if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
10559     else printf("\n");*/
10560     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10561       #if defined(__i386__) || defined(__x86_64__)
10562       printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
10563       if(branch_regs[i].dirty&1) printf("eax ");
10564       if((branch_regs[i].dirty>>1)&1) printf("ecx ");
10565       if((branch_regs[i].dirty>>2)&1) printf("edx ");
10566       if((branch_regs[i].dirty>>3)&1) printf("ebx ");
10567       if((branch_regs[i].dirty>>5)&1) printf("ebp ");
10568       if((branch_regs[i].dirty>>6)&1) printf("esi ");
10569       if((branch_regs[i].dirty>>7)&1) printf("edi ");
10570       #endif
10571       #ifdef __arm__
10572       printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
10573       if(branch_regs[i].dirty&1) printf("r0 ");
10574       if((branch_regs[i].dirty>>1)&1) printf("r1 ");
10575       if((branch_regs[i].dirty>>2)&1) printf("r2 ");
10576       if((branch_regs[i].dirty>>3)&1) printf("r3 ");
10577       if((branch_regs[i].dirty>>4)&1) printf("r4 ");
10578       if((branch_regs[i].dirty>>5)&1) printf("r5 ");
10579       if((branch_regs[i].dirty>>6)&1) printf("r6 ");
10580       if((branch_regs[i].dirty>>7)&1) printf("r7 ");
10581       if((branch_regs[i].dirty>>8)&1) printf("r8 ");
10582       if((branch_regs[i].dirty>>9)&1) printf("r9 ");
10583       if((branch_regs[i].dirty>>10)&1) printf("r10 ");
10584       if((branch_regs[i].dirty>>12)&1) printf("r12 ");
10585       #endif
10586 #ifndef FORCE32
10587       printf(" 32:");
10588       for(r=0;r<=CCREG;r++) {
10589         if((branch_regs[i].is32>>r)&1) {
10590           if(r==CCREG) printf(" CC");
10591           else if(r==HIREG) printf(" HI");
10592           else if(r==LOREG) printf(" LO");
10593           else printf(" r%d",r);
10594         }
10595       }
10596       printf("\n");
10597 #endif
10598     }
10599   }
10600
10601   /* Pass 8 - Assembly */
10602   linkcount=0;stubcount=0;
10603   ds=0;is_delayslot=0;
10604   cop1_usable=0;
10605   uint64_t is32_pre=0;
10606   u_int dirty_pre=0;
10607   u_int beginning=(u_int)out;
10608   if((u_int)addr&1) {
10609     ds=1;
10610     pagespan_ds();
10611   }
10612   u_int instr_addr0_override=0;
10613
10614 #ifdef PCSX
10615   if (start == 0x80030000) {
10616     // nasty hack for fastbios thing
10617     instr_addr0_override=(u_int)out;
10618     emit_movimm(start,0);
10619     emit_readword((int)&pcaddr,1);
10620     emit_writeword(0,(int)&pcaddr);
10621     emit_cmp(0,1);
10622     emit_jne((int)new_dyna_leave);
10623   }
10624 #endif
10625   for(i=0;i<slen;i++)
10626   {
10627     //if(ds) printf("ds: ");
10628     if((void*)assem_debug==(void*)printf) disassemble_inst(i);
10629     if(ds) {
10630       ds=0; // Skip delay slot
10631       if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
10632       instr_addr[i]=0;
10633     } else {
10634       #ifndef DESTRUCTIVE_WRITEBACK
10635       if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10636       {
10637         wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
10638               unneeded_reg[i],unneeded_reg_upper[i]);
10639         wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
10640               unneeded_reg[i],unneeded_reg_upper[i]);
10641       }
10642       is32_pre=regs[i].is32;
10643       dirty_pre=regs[i].dirty;
10644       #endif
10645       // write back
10646       if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10647       {
10648         wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
10649                       unneeded_reg[i],unneeded_reg_upper[i]);
10650         loop_preload(regmap_pre[i],regs[i].regmap_entry);
10651       }
10652       // branch target entry point
10653       instr_addr[i]=(u_int)out;
10654       assem_debug("<->\n");
10655       // load regs
10656       if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
10657         wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
10658       load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
10659       address_generation(i,&regs[i],regs[i].regmap_entry);
10660       load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
10661       if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10662       {
10663         // Load the delay slot registers if necessary
10664         if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10665           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10666         if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10667           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
10668         if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
10669           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10670       }
10671       else if(i+1<slen)
10672       {
10673         // Preload registers for following instruction
10674         if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10675           if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
10676             load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10677         if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10678           if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
10679             load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
10680       }
10681       // TODO: if(is_ooo(i)) address_generation(i+1);
10682       if(itype[i]==CJUMP||itype[i]==FJUMP)
10683         load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
10684       if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
10685         load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10686       if(bt[i]) cop1_usable=0;
10687       // assemble
10688       switch(itype[i]) {
10689         case ALU:
10690           alu_assemble(i,&regs[i]);break;
10691         case IMM16:
10692           imm16_assemble(i,&regs[i]);break;
10693         case SHIFT:
10694           shift_assemble(i,&regs[i]);break;
10695         case SHIFTIMM:
10696           shiftimm_assemble(i,&regs[i]);break;
10697         case LOAD:
10698           load_assemble(i,&regs[i]);break;
10699         case LOADLR:
10700           loadlr_assemble(i,&regs[i]);break;
10701         case STORE:
10702           store_assemble(i,&regs[i]);break;
10703         case STORELR:
10704           storelr_assemble(i,&regs[i]);break;
10705         case COP0:
10706           cop0_assemble(i,&regs[i]);break;
10707         case COP1:
10708           cop1_assemble(i,&regs[i]);break;
10709         case C1LS:
10710           c1ls_assemble(i,&regs[i]);break;
10711         case COP2:
10712           cop2_assemble(i,&regs[i]);break;
10713         case C2LS:
10714           c2ls_assemble(i,&regs[i]);break;
10715         case C2OP:
10716           c2op_assemble(i,&regs[i]);break;
10717         case FCONV:
10718           fconv_assemble(i,&regs[i]);break;
10719         case FLOAT:
10720           float_assemble(i,&regs[i]);break;
10721         case FCOMP:
10722           fcomp_assemble(i,&regs[i]);break;
10723         case MULTDIV:
10724           multdiv_assemble(i,&regs[i]);break;
10725         case MOV:
10726           mov_assemble(i,&regs[i]);break;
10727         case SYSCALL:
10728           syscall_assemble(i,&regs[i]);break;
10729         case HLECALL:
10730           hlecall_assemble(i,&regs[i]);break;
10731         case INTCALL:
10732           intcall_assemble(i,&regs[i]);break;
10733         case UJUMP:
10734           ujump_assemble(i,&regs[i]);ds=1;break;
10735         case RJUMP:
10736           rjump_assemble(i,&regs[i]);ds=1;break;
10737         case CJUMP:
10738           cjump_assemble(i,&regs[i]);ds=1;break;
10739         case SJUMP:
10740           sjump_assemble(i,&regs[i]);ds=1;break;
10741         case FJUMP:
10742           fjump_assemble(i,&regs[i]);ds=1;break;
10743         case SPAN:
10744           pagespan_assemble(i,&regs[i]);break;
10745       }
10746       if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10747         literal_pool(1024);
10748       else
10749         literal_pool_jumpover(256);
10750     }
10751   }
10752   //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
10753   // If the block did not end with an unconditional branch,
10754   // add a jump to the next instruction.
10755   if(i>1) {
10756     if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
10757       assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10758       assert(i==slen);
10759       if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
10760         store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10761         if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10762           emit_loadreg(CCREG,HOST_CCREG);
10763         emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10764       }
10765       else if(!likely[i-2])
10766       {
10767         store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
10768         assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
10769       }
10770       else
10771       {
10772         store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
10773         assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
10774       }
10775       add_to_linker((int)out,start+i*4,0);
10776       emit_jmp(0);
10777     }
10778   }
10779   else
10780   {
10781     assert(i>0);
10782     assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10783     store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10784     if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10785       emit_loadreg(CCREG,HOST_CCREG);
10786     emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10787     add_to_linker((int)out,start+i*4,0);
10788     emit_jmp(0);
10789   }
10790
10791   // TODO: delay slot stubs?
10792   // Stubs
10793   for(i=0;i<stubcount;i++)
10794   {
10795     switch(stubs[i][0])
10796     {
10797       case LOADB_STUB:
10798       case LOADH_STUB:
10799       case LOADW_STUB:
10800       case LOADD_STUB:
10801       case LOADBU_STUB:
10802       case LOADHU_STUB:
10803         do_readstub(i);break;
10804       case STOREB_STUB:
10805       case STOREH_STUB:
10806       case STOREW_STUB:
10807       case STORED_STUB:
10808         do_writestub(i);break;
10809       case CC_STUB:
10810         do_ccstub(i);break;
10811       case INVCODE_STUB:
10812         do_invstub(i);break;
10813       case FP_STUB:
10814         do_cop1stub(i);break;
10815       case STORELR_STUB:
10816         do_unalignedwritestub(i);break;
10817     }
10818   }
10819
10820   if (instr_addr0_override)
10821     instr_addr[0] = instr_addr0_override;
10822
10823   /* Pass 9 - Linker */
10824   for(i=0;i<linkcount;i++)
10825   {
10826     assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
10827     literal_pool(64);
10828     if(!link_addr[i][2])
10829     {
10830       void *stub=out;
10831       void *addr=check_addr(link_addr[i][1]);
10832       emit_extjump(link_addr[i][0],link_addr[i][1]);
10833       if(addr) {
10834         set_jump_target(link_addr[i][0],(int)addr);
10835         add_link(link_addr[i][1],stub);
10836       }
10837       else set_jump_target(link_addr[i][0],(int)stub);
10838     }
10839     else
10840     {
10841       // Internal branch
10842       int target=(link_addr[i][1]-start)>>2;
10843       assert(target>=0&&target<slen);
10844       assert(instr_addr[target]);
10845       //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10846       //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
10847       //#else
10848       set_jump_target(link_addr[i][0],instr_addr[target]);
10849       //#endif
10850     }
10851   }
10852   // External Branch Targets (jump_in)
10853   if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
10854   for(i=0;i<slen;i++)
10855   {
10856     if(bt[i]||i==0)
10857     {
10858       if(instr_addr[i]) // TODO - delay slots (=null)
10859       {
10860         u_int vaddr=start+i*4;
10861         u_int page=get_page(vaddr);
10862         u_int vpage=get_vpage(vaddr);
10863         literal_pool(256);
10864         //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
10865         if(!requires_32bit[i])
10866         {
10867           assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
10868           assem_debug("jump_in: %x\n",start+i*4);
10869           ll_add(jump_dirty+vpage,vaddr,(void *)out);
10870           int entry_point=do_dirty_stub(i);
10871           ll_add(jump_in+page,vaddr,(void *)entry_point);
10872           // If there was an existing entry in the hash table,
10873           // replace it with the new address.
10874           // Don't add new entries.  We'll insert the
10875           // ones that actually get used in check_addr().
10876           int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
10877           if(ht_bin[0]==vaddr) {
10878             ht_bin[1]=entry_point;
10879           }
10880           if(ht_bin[2]==vaddr) {
10881             ht_bin[3]=entry_point;
10882           }
10883         }
10884         else
10885         {
10886           u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
10887           assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
10888           assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
10889           //int entry_point=(int)out;
10890           ////assem_debug("entry_point: %x\n",entry_point);
10891           //load_regs_entry(i);
10892           //if(entry_point==(int)out)
10893           //  entry_point=instr_addr[i];
10894           //else
10895           //  emit_jmp(instr_addr[i]);
10896           //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
10897           ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
10898           int entry_point=do_dirty_stub(i);
10899           ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
10900         }
10901       }
10902     }
10903   }
10904   // Write out the literal pool if necessary
10905   literal_pool(0);
10906   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10907   // Align code
10908   if(((u_int)out)&7) emit_addnop(13);
10909   #endif
10910   assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
10911   //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
10912   memcpy(copy,source,slen*4);
10913   copy+=slen*4;
10914
10915   #ifdef __arm__
10916   __clear_cache((void *)beginning,out);
10917   #endif
10918
10919   // If we're within 256K of the end of the buffer,
10920   // start over from the beginning. (Is 256K enough?)
10921   if((int)out>BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
10922
10923   // Trap writes to any of the pages we compiled
10924   for(i=start>>12;i<=(start+slen*4)>>12;i++) {
10925     invalid_code[i]=0;
10926 #ifndef DISABLE_TLB
10927     memory_map[i]|=0x40000000;
10928     if((signed int)start>=(signed int)0xC0000000) {
10929       assert(using_tlb);
10930       j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
10931       invalid_code[j]=0;
10932       memory_map[j]|=0x40000000;
10933       //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
10934     }
10935 #endif
10936   }
10937
10938   /* Pass 10 - Free memory by expiring oldest blocks */
10939
10940   int end=((((int)out-BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
10941   while(expirep!=end)
10942   {
10943     int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
10944     int base=BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
10945     inv_debug("EXP: Phase %d\n",expirep);
10946     switch((expirep>>11)&3)
10947     {
10948       case 0:
10949         // Clear jump_in and jump_dirty
10950         ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
10951         ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
10952         ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
10953         ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
10954         break;
10955       case 1:
10956         // Clear pointers
10957         ll_kill_pointers(jump_out[expirep&2047],base,shift);
10958         ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
10959         break;
10960       case 2:
10961         // Clear hash table
10962         for(i=0;i<32;i++) {
10963           int *ht_bin=hash_table[((expirep&2047)<<5)+i];
10964           if((ht_bin[3]>>shift)==(base>>shift) ||
10965              ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
10966             inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
10967             ht_bin[2]=ht_bin[3]=-1;
10968           }
10969           if((ht_bin[1]>>shift)==(base>>shift) ||
10970              ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
10971             inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
10972             ht_bin[0]=ht_bin[2];
10973             ht_bin[1]=ht_bin[3];
10974             ht_bin[2]=ht_bin[3]=-1;
10975           }
10976         }
10977         break;
10978       case 3:
10979         // Clear jump_out
10980         ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
10981         ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
10982         break;
10983     }
10984     expirep=(expirep+1)&65535;
10985   }
10986   return 0;
10987 }
10988
10989 // vim:shiftwidth=2:expandtab