libpcsxcore/new_dynarec/new_dynarec.c

   1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
   2  *   Mupen64plus - new_dynarec.c                                           *
   3  *   Copyright (C) 2009-2011 Ari64                                         *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.          *
  19  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
  20
  21 #include <stdlib.h>
  22 #include <stdint.h> //include for uint64_t
  23 #include <assert.h>
  24
  25 #include "emu_if.h" //emulator interface
  26
  27 #include <sys/mman.h>
  28
  29 #ifdef __i386__
  30 #include "assem_x86.h"
  31 #endif
  32 #ifdef __x86_64__
  33 #include "assem_x64.h"
  34 #endif
  35 #ifdef __arm__
  36 #include "assem_arm.h"
  37 #endif
  38
  39 #define MAXBLOCK 4096
  40 #define MAX_OUTPUT_BLOCK_SIZE 262144
  41 #define CLOCK_DIVIDER 2
  42
  43 struct regstat
  44 {
  45   signed char regmap_entry[HOST_REGS];
  46   signed char regmap[HOST_REGS];
  47   uint64_t was32;
  48   uint64_t is32;
  49   uint64_t wasdirty;
  50   uint64_t dirty;
  51   uint64_t u;
  52   uint64_t uu;
  53   u_int wasconst;
  54   u_int isconst;
  55   uint64_t constmap[HOST_REGS];
  56 };
  57
  58 struct ll_entry
  59 {
  60   u_int vaddr;
  61   u_int reg32;
  62   void *addr;
  63   struct ll_entry *next;
  64 };
  65
  66   u_int start;
  67   u_int *source;
  68   u_int pagelimit;
  69   char insn[MAXBLOCK][10];
  70   u_char itype[MAXBLOCK];
  71   u_char opcode[MAXBLOCK];
  72   u_char opcode2[MAXBLOCK];
  73   u_char bt[MAXBLOCK];
  74   u_char rs1[MAXBLOCK];
  75   u_char rs2[MAXBLOCK];
  76   u_char rt1[MAXBLOCK];
  77   u_char rt2[MAXBLOCK];
  78   u_char us1[MAXBLOCK];
  79   u_char us2[MAXBLOCK];
  80   u_char dep1[MAXBLOCK];
  81   u_char dep2[MAXBLOCK];
  82   u_char lt1[MAXBLOCK];
  83   static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
  84   static uint64_t gte_rt[MAXBLOCK];
  85   static uint64_t gte_unneeded[MAXBLOCK];
  86   static int gte_reads_flags; // gte flag read encountered
  87   int imm[MAXBLOCK];
  88   u_int ba[MAXBLOCK];
  89   char likely[MAXBLOCK];
  90   char is_ds[MAXBLOCK];
  91   char ooo[MAXBLOCK];
  92   uint64_t unneeded_reg[MAXBLOCK];
  93   uint64_t unneeded_reg_upper[MAXBLOCK];
  94   uint64_t branch_unneeded_reg[MAXBLOCK];
  95   uint64_t branch_unneeded_reg_upper[MAXBLOCK];
  96   uint64_t p32[MAXBLOCK];
  97   uint64_t pr32[MAXBLOCK];
  98   signed char regmap_pre[MAXBLOCK][HOST_REGS];
  99   signed char regmap[MAXBLOCK][HOST_REGS];
 100   signed char regmap_entry[MAXBLOCK][HOST_REGS];
 101   uint64_t constmap[MAXBLOCK][HOST_REGS];
 102   struct regstat regs[MAXBLOCK];
 103   struct regstat branch_regs[MAXBLOCK];
 104   signed char minimum_free_regs[MAXBLOCK];
 105   u_int needed_reg[MAXBLOCK];
 106   uint64_t requires_32bit[MAXBLOCK];
 107   u_int wont_dirty[MAXBLOCK];
 108   u_int will_dirty[MAXBLOCK];
 109   int ccadj[MAXBLOCK];
 110   int slen;
 111   u_int instr_addr[MAXBLOCK];
 112   u_int link_addr[MAXBLOCK][3];
 113   int linkcount;
 114   u_int stubs[MAXBLOCK*3][8];
 115   int stubcount;
 116   u_int literals[1024][2];
 117   int literalcount;
 118   int is_delayslot;
 119   int cop1_usable;
 120   u_char *out;
 121   struct ll_entry *jump_in[4096];
 122   struct ll_entry *jump_out[4096];
 123   struct ll_entry *jump_dirty[4096];
 124   u_int hash_table[65536][4]  __attribute__((aligned(16)));
 125   char shadow[1048576]  __attribute__((aligned(16)));
 126   void *copy;
 127   int expirep;
 128 #ifndef PCSX
 129   u_int using_tlb;
 130 #else
 131   static const u_int using_tlb=0;
 132 #endif
 133   static u_int sp_in_mirror;
 134   u_int stop_after_jal;
 135   extern u_char restore_candidate[512];
 136   extern int cycle_count;
 137
 138   /* registers that may be allocated */
 139   /* 1-31 gpr */
 140 #define HIREG 32 // hi
 141 #define LOREG 33 // lo
 142 #define FSREG 34 // FPU status (FCSR)
 143 #define CSREG 35 // Coprocessor status
 144 #define CCREG 36 // Cycle count
 145 #define INVCP 37 // Pointer to invalid_code
 146 #define MMREG 38 // Pointer to memory_map
 147 #define ROREG 39 // ram offset (if rdram!=0x80000000)
 148 #define TEMPREG 40
 149 #define FTEMP 40 // FPU temporary register
 150 #define PTEMP 41 // Prefetch temporary register
 151 #define TLREG 42 // TLB mapping offset
 152 #define RHASH 43 // Return address hash
 153 #define RHTBL 44 // Return address hash table address
 154 #define RTEMP 45 // JR/JALR address register
 155 #define MAXREG 45
 156 #define AGEN1 46 // Address generation temporary register
 157 #define AGEN2 47 // Address generation temporary register
 158 #define MGEN1 48 // Maptable address generation temporary register
 159 #define MGEN2 49 // Maptable address generation temporary register
 160 #define BTREG 50 // Branch target temporary register
 161
 162   /* instruction types */
 163 #define NOP 0     // No operation
 164 #define LOAD 1    // Load
 165 #define STORE 2   // Store
 166 #define LOADLR 3  // Unaligned load
 167 #define STORELR 4 // Unaligned store
 168 #define MOV 5     // Move
 169 #define ALU 6     // Arithmetic/logic
 170 #define MULTDIV 7 // Multiply/divide
 171 #define SHIFT 8   // Shift by register
 172 #define SHIFTIMM 9// Shift by immediate
 173 #define IMM16 10  // 16-bit immediate
 174 #define RJUMP 11  // Unconditional jump to register
 175 #define UJUMP 12  // Unconditional jump
 176 #define CJUMP 13  // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
 177 #define SJUMP 14  // Conditional branch (regimm format)
 178 #define COP0 15   // Coprocessor 0
 179 #define COP1 16   // Coprocessor 1
 180 #define C1LS 17   // Coprocessor 1 load/store
 181 #define FJUMP 18  // Conditional branch (floating point)
 182 #define FLOAT 19  // Floating point unit
 183 #define FCONV 20  // Convert integer to float
 184 #define FCOMP 21  // Floating point compare (sets FSREG)
 185 #define SYSCALL 22// SYSCALL
 186 #define OTHER 23  // Other
 187 #define SPAN 24   // Branch/delay slot spans 2 pages
 188 #define NI 25     // Not implemented
 189 #define HLECALL 26// PCSX fake opcodes for HLE
 190 #define COP2 27   // Coprocessor 2 move
 191 #define C2LS 28   // Coprocessor 2 load/store
 192 #define C2OP 29   // Coprocessor 2 operation
 193 #define INTCALL 30// Call interpreter to handle rare corner cases
 194
 195   /* stubs */
 196 #define CC_STUB 1
 197 #define FP_STUB 2
 198 #define LOADB_STUB 3
 199 #define LOADH_STUB 4
 200 #define LOADW_STUB 5
 201 #define LOADD_STUB 6
 202 #define LOADBU_STUB 7
 203 #define LOADHU_STUB 8
 204 #define STOREB_STUB 9
 205 #define STOREH_STUB 10
 206 #define STOREW_STUB 11
 207 #define STORED_STUB 12
 208 #define STORELR_STUB 13
 209 #define INVCODE_STUB 14
 210
 211   /* branch codes */
 212 #define TAKEN 1
 213 #define NOTTAKEN 2
 214 #define NULLDS 3
 215
 216 // asm linkage
 217 int new_recompile_block(int addr);
 218 void *get_addr_ht(u_int vaddr);
 219 void invalidate_block(u_int block);
 220 void invalidate_addr(u_int addr);
 221 void remove_hash(int vaddr);
 222 void jump_vaddr();
 223 void dyna_linker();
 224 void dyna_linker_ds();
 225 void verify_code();
 226 void verify_code_vm();
 227 void verify_code_ds();
 228 void cc_interrupt();
 229 void fp_exception();
 230 void fp_exception_ds();
 231 void jump_syscall();
 232 void jump_syscall_hle();
 233 void jump_eret();
 234 void jump_hlecall();
 235 void jump_intcall();
 236 void new_dyna_leave();
 237
 238 // TLB
 239 void TLBWI_new();
 240 void TLBWR_new();
 241 void read_nomem_new();
 242 void read_nomemb_new();
 243 void read_nomemh_new();
 244 void read_nomemd_new();
 245 void write_nomem_new();
 246 void write_nomemb_new();
 247 void write_nomemh_new();
 248 void write_nomemd_new();
 249 void write_rdram_new();
 250 void write_rdramb_new();
 251 void write_rdramh_new();
 252 void write_rdramd_new();
 253 extern u_int memory_map[1048576];
 254
 255 // Needed by assembler
 256 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
 257 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
 258 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
 259 void load_all_regs(signed char i_regmap[]);
 260 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
 261 void load_regs_entry(int t);
 262 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
 263
 264 int tracedebug=0;
 265
 266 //#define DEBUG_CYCLE_COUNT 1
 267
 268 void nullf() {}
 269 //#define assem_debug printf
 270 //#define inv_debug printf
 271 #define assem_debug nullf
 272 #define inv_debug nullf
 273
 274 static void tlb_hacks()
 275 {
 276 #ifndef DISABLE_TLB
 277   // Goldeneye hack
 278   if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
 279   {
 280     u_int addr;
 281     int n;
 282     switch (ROM_HEADER->Country_code&0xFF)
 283     {
 284       case 0x45: // U
 285         addr=0x34b30;
 286         break;
 287       case 0x4A: // J
 288         addr=0x34b70;
 289         break;
 290       case 0x50: // E
 291         addr=0x329f0;
 292         break;
 293       default:
 294         // Unknown country code
 295         addr=0;
 296         break;
 297     }
 298     u_int rom_addr=(u_int)rom;
 299     #ifdef ROM_COPY
 300     // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
 301     // in the lower 4G of memory to use this hack.  Copy it if necessary.
 302     if((void *)rom>(void *)0xffffffff) {
 303       munmap(ROM_COPY, 67108864);
 304       if(mmap(ROM_COPY, 12582912,
 305               PROT_READ | PROT_WRITE,
 306               MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
 307               -1, 0) <= 0) {printf("mmap() failed\n");}
 308       memcpy(ROM_COPY,rom,12582912);
 309       rom_addr=(u_int)ROM_COPY;
 310     }
 311     #endif
 312     if(addr) {
 313       for(n=0x7F000;n<0x80000;n++) {
 314         memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
 315       }
 316     }
 317   }
 318 #endif
 319 }
 320
 321 static u_int get_page(u_int vaddr)
 322 {
 323 #ifndef PCSX
 324   u_int page=(vaddr^0x80000000)>>12;
 325 #else
 326   u_int page=vaddr&~0xe0000000;
 327   if (page < 0x1000000)
 328     page &= ~0x0e00000; // RAM mirrors
 329   page>>=12;
 330 #endif
 331 #ifndef DISABLE_TLB
 332   if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
 333 #endif
 334   if(page>2048) page=2048+(page&2047);
 335   return page;
 336 }
 337
 338 static u_int get_vpage(u_int vaddr)
 339 {
 340   u_int vpage=(vaddr^0x80000000)>>12;
 341 #ifndef DISABLE_TLB
 342   if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
 343 #endif
 344   if(vpage>2048) vpage=2048+(vpage&2047);
 345   return vpage;
 346 }
 347
 348 // Get address from virtual address
 349 // This is called from the recompiled JR/JALR instructions
 350 void *get_addr(u_int vaddr)
 351 {
 352   u_int page=get_page(vaddr);
 353   u_int vpage=get_vpage(vaddr);
 354   struct ll_entry *head;
 355   //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
 356   head=jump_in[page];
 357   while(head!=NULL) {
 358     if(head->vaddr==vaddr&&head->reg32==0) {
 359   //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 360       int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 361       ht_bin[3]=ht_bin[1];
 362       ht_bin[2]=ht_bin[0];
 363       ht_bin[1]=(int)head->addr;
 364       ht_bin[0]=vaddr;
 365       return head->addr;
 366     }
 367     head=head->next;
 368   }
 369   head=jump_dirty[vpage];
 370   while(head!=NULL) {
 371     if(head->vaddr==vaddr&&head->reg32==0) {
 372       //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 373       // Don't restore blocks which are about to expire from the cache
 374       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 375       if(verify_dirty(head->addr)) {
 376         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
 377         invalid_code[vaddr>>12]=0;
 378         inv_code_start=inv_code_end=~0;
 379         memory_map[vaddr>>12]|=0x40000000;
 380         if(vpage<2048) {
 381 #ifndef DISABLE_TLB
 382           if(tlb_LUT_r[vaddr>>12]) {
 383             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
 384             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
 385           }
 386 #endif
 387           restore_candidate[vpage>>3]|=1<<(vpage&7);
 388         }
 389         else restore_candidate[page>>3]|=1<<(page&7);
 390         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 391         if(ht_bin[0]==vaddr) {
 392           ht_bin[1]=(int)head->addr; // Replace existing entry
 393         }
 394         else
 395         {
 396           ht_bin[3]=ht_bin[1];
 397           ht_bin[2]=ht_bin[0];
 398           ht_bin[1]=(int)head->addr;
 399           ht_bin[0]=vaddr;
 400         }
 401         return head->addr;
 402       }
 403     }
 404     head=head->next;
 405   }
 406   //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
 407   int r=new_recompile_block(vaddr);
 408   if(r==0) return get_addr(vaddr);
 409   // Execute in unmapped page, generate pagefault execption
 410   Status|=2;
 411   Cause=(vaddr<<31)|0x8;
 412   EPC=(vaddr&1)?vaddr-5:vaddr;
 413   BadVAddr=(vaddr&~1);
 414   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
 415   EntryHi=BadVAddr&0xFFFFE000;
 416   return get_addr_ht(0x80000000);
 417 }
 418 // Look up address in hash table first
 419 void *get_addr_ht(u_int vaddr)
 420 {
 421   //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
 422   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 423   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
 424   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
 425   return get_addr(vaddr);
 426 }
 427
 428 void *get_addr_32(u_int vaddr,u_int flags)
 429 {
 430 #ifdef FORCE32
 431   return get_addr(vaddr);
 432 #else
 433   //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
 434   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 435   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
 436   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
 437   u_int page=get_page(vaddr);
 438   u_int vpage=get_vpage(vaddr);
 439   struct ll_entry *head;
 440   head=jump_in[page];
 441   while(head!=NULL) {
 442     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
 443       //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 444       if(head->reg32==0) {
 445         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 446         if(ht_bin[0]==-1) {
 447           ht_bin[1]=(int)head->addr;
 448           ht_bin[0]=vaddr;
 449         }else if(ht_bin[2]==-1) {
 450           ht_bin[3]=(int)head->addr;
 451           ht_bin[2]=vaddr;
 452         }
 453         //ht_bin[3]=ht_bin[1];
 454         //ht_bin[2]=ht_bin[0];
 455         //ht_bin[1]=(int)head->addr;
 456         //ht_bin[0]=vaddr;
 457       }
 458       return head->addr;
 459     }
 460     head=head->next;
 461   }
 462   head=jump_dirty[vpage];
 463   while(head!=NULL) {
 464     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
 465       //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 466       // Don't restore blocks which are about to expire from the cache
 467       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 468       if(verify_dirty(head->addr)) {
 469         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
 470         invalid_code[vaddr>>12]=0;
 471         inv_code_start=inv_code_end=~0;
 472         memory_map[vaddr>>12]|=0x40000000;
 473         if(vpage<2048) {
 474 #ifndef DISABLE_TLB
 475           if(tlb_LUT_r[vaddr>>12]) {
 476             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
 477             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
 478           }
 479 #endif
 480           restore_candidate[vpage>>3]|=1<<(vpage&7);
 481         }
 482         else restore_candidate[page>>3]|=1<<(page&7);
 483         if(head->reg32==0) {
 484           int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 485           if(ht_bin[0]==-1) {
 486             ht_bin[1]=(int)head->addr;
 487             ht_bin[0]=vaddr;
 488           }else if(ht_bin[2]==-1) {
 489             ht_bin[3]=(int)head->addr;
 490             ht_bin[2]=vaddr;
 491           }
 492           //ht_bin[3]=ht_bin[1];
 493           //ht_bin[2]=ht_bin[0];
 494           //ht_bin[1]=(int)head->addr;
 495           //ht_bin[0]=vaddr;
 496         }
 497         return head->addr;
 498       }
 499     }
 500     head=head->next;
 501   }
 502   //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
 503   int r=new_recompile_block(vaddr);
 504   if(r==0) return get_addr(vaddr);
 505   // Execute in unmapped page, generate pagefault execption
 506   Status|=2;
 507   Cause=(vaddr<<31)|0x8;
 508   EPC=(vaddr&1)?vaddr-5:vaddr;
 509   BadVAddr=(vaddr&~1);
 510   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
 511   EntryHi=BadVAddr&0xFFFFE000;
 512   return get_addr_ht(0x80000000);
 513 #endif
 514 }
 515
 516 void clear_all_regs(signed char regmap[])
 517 {
 518   int hr;
 519   for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
 520 }
 521
 522 signed char get_reg(signed char regmap[],int r)
 523 {
 524   int hr;
 525   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
 526   return -1;
 527 }
 528
 529 // Find a register that is available for two consecutive cycles
 530 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
 531 {
 532   int hr;
 533   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
 534   return -1;
 535 }
 536
 537 int count_free_regs(signed char regmap[])
 538 {
 539   int count=0;
 540   int hr;
 541   for(hr=0;hr<HOST_REGS;hr++)
 542   {
 543     if(hr!=EXCLUDE_REG) {
 544       if(regmap[hr]<0) count++;
 545     }
 546   }
 547   return count;
 548 }
 549
 550 void dirty_reg(struct regstat *cur,signed char reg)
 551 {
 552   int hr;
 553   if(!reg) return;
 554   for (hr=0;hr<HOST_REGS;hr++) {
 555     if((cur->regmap[hr]&63)==reg) {
 556       cur->dirty|=1<<hr;
 557     }
 558   }
 559 }
 560
 561 // If we dirty the lower half of a 64 bit register which is now being
 562 // sign-extended, we need to dump the upper half.
 563 // Note: Do this only after completion of the instruction, because
 564 // some instructions may need to read the full 64-bit value even if
 565 // overwriting it (eg SLTI, DSRA32).
 566 static void flush_dirty_uppers(struct regstat *cur)
 567 {
 568   int hr,reg;
 569   for (hr=0;hr<HOST_REGS;hr++) {
 570     if((cur->dirty>>hr)&1) {
 571       reg=cur->regmap[hr];
 572       if(reg>=64)
 573         if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
 574     }
 575   }
 576 }
 577
 578 void set_const(struct regstat *cur,signed char reg,uint64_t value)
 579 {
 580   int hr;
 581   if(!reg) return;
 582   for (hr=0;hr<HOST_REGS;hr++) {
 583     if(cur->regmap[hr]==reg) {
 584       cur->isconst|=1<<hr;
 585       cur->constmap[hr]=value;
 586     }
 587     else if((cur->regmap[hr]^64)==reg) {
 588       cur->isconst|=1<<hr;
 589       cur->constmap[hr]=value>>32;
 590     }
 591   }
 592 }
 593
 594 void clear_const(struct regstat *cur,signed char reg)
 595 {
 596   int hr;
 597   if(!reg) return;
 598   for (hr=0;hr<HOST_REGS;hr++) {
 599     if((cur->regmap[hr]&63)==reg) {
 600       cur->isconst&=~(1<<hr);
 601     }
 602   }
 603 }
 604
 605 int is_const(struct regstat *cur,signed char reg)
 606 {
 607   int hr;
 608   if(reg<0) return 0;
 609   if(!reg) return 1;
 610   for (hr=0;hr<HOST_REGS;hr++) {
 611     if((cur->regmap[hr]&63)==reg) {
 612       return (cur->isconst>>hr)&1;
 613     }
 614   }
 615   return 0;
 616 }
 617 uint64_t get_const(struct regstat *cur,signed char reg)
 618 {
 619   int hr;
 620   if(!reg) return 0;
 621   for (hr=0;hr<HOST_REGS;hr++) {
 622     if(cur->regmap[hr]==reg) {
 623       return cur->constmap[hr];
 624     }
 625   }
 626   printf("Unknown constant in r%d\n",reg);
 627   exit(1);
 628 }
 629
 630 // Least soon needed registers
 631 // Look at the next ten instructions and see which registers
 632 // will be used.  Try not to reallocate these.
 633 void lsn(u_char hsn[], int i, int *preferred_reg)
 634 {
 635   int j;
 636   int b=-1;
 637   for(j=0;j<9;j++)
 638   {
 639     if(i+j>=slen) {
 640       j=slen-i-1;
 641       break;
 642     }
 643     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 644     {
 645       // Don't go past an unconditonal jump
 646       j++;
 647       break;
 648     }
 649   }
 650   for(;j>=0;j--)
 651   {
 652     if(rs1[i+j]) hsn[rs1[i+j]]=j;
 653     if(rs2[i+j]) hsn[rs2[i+j]]=j;
 654     if(rt1[i+j]) hsn[rt1[i+j]]=j;
 655     if(rt2[i+j]) hsn[rt2[i+j]]=j;
 656     if(itype[i+j]==STORE || itype[i+j]==STORELR) {
 657       // Stores can allocate zero
 658       hsn[rs1[i+j]]=j;
 659       hsn[rs2[i+j]]=j;
 660     }
 661     // On some architectures stores need invc_ptr
 662     #if defined(HOST_IMM8)
 663     if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
 664       hsn[INVCP]=j;
 665     }
 666     #endif
 667     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 668     {
 669       hsn[CCREG]=j;
 670       b=j;
 671     }
 672   }
 673   if(b>=0)
 674   {
 675     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 676     {
 677       // Follow first branch
 678       int t=(ba[i+b]-start)>>2;
 679       j=7-b;if(t+j>=slen) j=slen-t-1;
 680       for(;j>=0;j--)
 681       {
 682         if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
 683         if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
 684         //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
 685         //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
 686       }
 687     }
 688     // TODO: preferred register based on backward branch
 689   }
 690   // Delay slot should preferably not overwrite branch conditions or cycle count
 691   if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
 692     if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
 693     if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
 694     hsn[CCREG]=1;
 695     // ...or hash tables
 696     hsn[RHASH]=1;
 697     hsn[RHTBL]=1;
 698   }
 699   // Coprocessor load/store needs FTEMP, even if not declared
 700   if(itype[i]==C1LS||itype[i]==C2LS) {
 701     hsn[FTEMP]=0;
 702   }
 703   // Load L/R also uses FTEMP as a temporary register
 704   if(itype[i]==LOADLR) {
 705     hsn[FTEMP]=0;
 706   }
 707   // Also SWL/SWR/SDL/SDR
 708   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
 709     hsn[FTEMP]=0;
 710   }
 711   // Don't remove the TLB registers either
 712   if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
 713     hsn[TLREG]=0;
 714   }
 715   // Don't remove the miniht registers
 716   if(itype[i]==UJUMP||itype[i]==RJUMP)
 717   {
 718     hsn[RHASH]=0;
 719     hsn[RHTBL]=0;
 720   }
 721 }
 722
 723 // We only want to allocate registers if we're going to use them again soon
 724 int needed_again(int r, int i)
 725 {
 726   int j;
 727   int b=-1;
 728   int rn=10;
 729
 730   if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
 731   {
 732     if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
 733       return 0; // Don't need any registers if exiting the block
 734   }
 735   for(j=0;j<9;j++)
 736   {
 737     if(i+j>=slen) {
 738       j=slen-i-1;
 739       break;
 740     }
 741     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 742     {
 743       // Don't go past an unconditonal jump
 744       j++;
 745       break;
 746     }
 747     if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
 748     {
 749       break;
 750     }
 751   }
 752   for(;j>=1;j--)
 753   {
 754     if(rs1[i+j]==r) rn=j;
 755     if(rs2[i+j]==r) rn=j;
 756     if((unneeded_reg[i+j]>>r)&1) rn=10;
 757     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 758     {
 759       b=j;
 760     }
 761   }
 762   /*
 763   if(b>=0)
 764   {
 765     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 766     {
 767       // Follow first branch
 768       int o=rn;
 769       int t=(ba[i+b]-start)>>2;
 770       j=7-b;if(t+j>=slen) j=slen-t-1;
 771       for(;j>=0;j--)
 772       {
 773         if(!((unneeded_reg[t+j]>>r)&1)) {
 774           if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 775           if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 776         }
 777         else rn=o;
 778       }
 779     }
 780   }*/
 781   if(rn<10) return 1;
 782   return 0;
 783 }
 784
 785 // Try to match register allocations at the end of a loop with those
 786 // at the beginning
 787 int loop_reg(int i, int r, int hr)
 788 {
 789   int j,k;
 790   for(j=0;j<9;j++)
 791   {
 792     if(i+j>=slen) {
 793       j=slen-i-1;
 794       break;
 795     }
 796     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 797     {
 798       // Don't go past an unconditonal jump
 799       j++;
 800       break;
 801     }
 802   }
 803   k=0;
 804   if(i>0){
 805     if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
 806       k--;
 807   }
 808   for(;k<j;k++)
 809   {
 810     if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
 811     if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
 812     if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
 813     {
 814       if(ba[i+k]>=start && ba[i+k]<(start+i*4))
 815       {
 816         int t=(ba[i+k]-start)>>2;
 817         int reg=get_reg(regs[t].regmap_entry,r);
 818         if(reg>=0) return reg;
 819         //reg=get_reg(regs[t+1].regmap_entry,r);
 820         //if(reg>=0) return reg;
 821       }
 822     }
 823   }
 824   return hr;
 825 }
 826
 827
 828 // Allocate every register, preserving source/target regs
 829 void alloc_all(struct regstat *cur,int i)
 830 {
 831   int hr;
 832
 833   for(hr=0;hr<HOST_REGS;hr++) {
 834     if(hr!=EXCLUDE_REG) {
 835       if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
 836          ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
 837       {
 838         cur->regmap[hr]=-1;
 839         cur->dirty&=~(1<<hr);
 840       }
 841       // Don't need zeros
 842       if((cur->regmap[hr]&63)==0)
 843       {
 844         cur->regmap[hr]=-1;
 845         cur->dirty&=~(1<<hr);
 846       }
 847     }
 848   }
 849 }
 850
 851
 852 void div64(int64_t dividend,int64_t divisor)
 853 {
 854   lo=dividend/divisor;
 855   hi=dividend%divisor;
 856   //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
 857   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 858 }
 859 void divu64(uint64_t dividend,uint64_t divisor)
 860 {
 861   lo=dividend/divisor;
 862   hi=dividend%divisor;
 863   //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 864   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 865 }
 866
 867 void mult64(uint64_t m1,uint64_t m2)
 868 {
 869    unsigned long long int op1, op2, op3, op4;
 870    unsigned long long int result1, result2, result3, result4;
 871    unsigned long long int temp1, temp2, temp3, temp4;
 872    int sign = 0;
 873
 874    if (m1 < 0)
 875      {
 876     op2 = -m1;
 877     sign = 1 - sign;
 878      }
 879    else op2 = m1;
 880    if (m2 < 0)
 881      {
 882     op4 = -m2;
 883     sign = 1 - sign;
 884      }
 885    else op4 = m2;
 886
 887    op1 = op2 & 0xFFFFFFFF;
 888    op2 = (op2 >> 32) & 0xFFFFFFFF;
 889    op3 = op4 & 0xFFFFFFFF;
 890    op4 = (op4 >> 32) & 0xFFFFFFFF;
 891
 892    temp1 = op1 * op3;
 893    temp2 = (temp1 >> 32) + op1 * op4;
 894    temp3 = op2 * op3;
 895    temp4 = (temp3 >> 32) + op2 * op4;
 896
 897    result1 = temp1 & 0xFFFFFFFF;
 898    result2 = temp2 + (temp3 & 0xFFFFFFFF);
 899    result3 = (result2 >> 32) + temp4;
 900    result4 = (result3 >> 32);
 901
 902    lo = result1 | (result2 << 32);
 903    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
 904    if (sign)
 905      {
 906     hi = ~hi;
 907     if (!lo) hi++;
 908     else lo = ~lo + 1;
 909      }
 910 }
 911
 912 void multu64(uint64_t m1,uint64_t m2)
 913 {
 914    unsigned long long int op1, op2, op3, op4;
 915    unsigned long long int result1, result2, result3, result4;
 916    unsigned long long int temp1, temp2, temp3, temp4;
 917
 918    op1 = m1 & 0xFFFFFFFF;
 919    op2 = (m1 >> 32) & 0xFFFFFFFF;
 920    op3 = m2 & 0xFFFFFFFF;
 921    op4 = (m2 >> 32) & 0xFFFFFFFF;
 922
 923    temp1 = op1 * op3;
 924    temp2 = (temp1 >> 32) + op1 * op4;
 925    temp3 = op2 * op3;
 926    temp4 = (temp3 >> 32) + op2 * op4;
 927
 928    result1 = temp1 & 0xFFFFFFFF;
 929    result2 = temp2 + (temp3 & 0xFFFFFFFF);
 930    result3 = (result2 >> 32) + temp4;
 931    result4 = (result3 >> 32);
 932
 933    lo = result1 | (result2 << 32);
 934    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
 935
 936   //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 937   //                                      ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 938 }
 939
 940 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
 941 {
 942   if(bits) {
 943     original<<=64-bits;
 944     original>>=64-bits;
 945     loaded<<=bits;
 946     original|=loaded;
 947   }
 948   else original=loaded;
 949   return original;
 950 }
 951 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
 952 {
 953   if(bits^56) {
 954     original>>=64-(bits^56);
 955     original<<=64-(bits^56);
 956     loaded>>=bits^56;
 957     original|=loaded;
 958   }
 959   else original=loaded;
 960   return original;
 961 }
 962
 963 #ifdef __i386__
 964 #include "assem_x86.c"
 965 #endif
 966 #ifdef __x86_64__
 967 #include "assem_x64.c"
 968 #endif
 969 #ifdef __arm__
 970 #include "assem_arm.c"
 971 #endif
 972
 973 // Add virtual address mapping to linked list
 974 void ll_add(struct ll_entry **head,int vaddr,void *addr)
 975 {
 976   struct ll_entry *new_entry;
 977   new_entry=malloc(sizeof(struct ll_entry));
 978   assert(new_entry!=NULL);
 979   new_entry->vaddr=vaddr;
 980   new_entry->reg32=0;
 981   new_entry->addr=addr;
 982   new_entry->next=*head;
 983   *head=new_entry;
 984 }
 985
 986 // Add virtual address mapping for 32-bit compiled block
 987 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
 988 {
 989   ll_add(head,vaddr,addr);
 990 #ifndef FORCE32
 991   (*head)->reg32=reg32;
 992 #endif
 993 }
 994
 995 // Check if an address is already compiled
 996 // but don't return addresses which are about to expire from the cache
 997 void *check_addr(u_int vaddr)
 998 {
 999   u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
1000   if(ht_bin[0]==vaddr) {
1001     if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1002       if(isclean(ht_bin[1])) return (void *)ht_bin[1];
1003   }
1004   if(ht_bin[2]==vaddr) {
1005     if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1006       if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1007   }
1008   u_int page=get_page(vaddr);
1009   struct ll_entry *head;
1010   head=jump_in[page];
1011   while(head!=NULL) {
1012     if(head->vaddr==vaddr&&head->reg32==0) {
1013       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1014         // Update existing entry with current address
1015         if(ht_bin[0]==vaddr) {
1016           ht_bin[1]=(int)head->addr;
1017           return head->addr;
1018         }
1019         if(ht_bin[2]==vaddr) {
1020           ht_bin[3]=(int)head->addr;
1021           return head->addr;
1022         }
1023         // Insert into hash table with low priority.
1024         // Don't evict existing entries, as they are probably
1025         // addresses that are being accessed frequently.
1026         if(ht_bin[0]==-1) {
1027           ht_bin[1]=(int)head->addr;
1028           ht_bin[0]=vaddr;
1029         }else if(ht_bin[2]==-1) {
1030           ht_bin[3]=(int)head->addr;
1031           ht_bin[2]=vaddr;
1032         }
1033         return head->addr;
1034       }
1035     }
1036     head=head->next;
1037   }
1038   return 0;
1039 }
1040
1041 void remove_hash(int vaddr)
1042 {
1043   //printf("remove hash: %x\n",vaddr);
1044   int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1045   if(ht_bin[2]==vaddr) {
1046     ht_bin[2]=ht_bin[3]=-1;
1047   }
1048   if(ht_bin[0]==vaddr) {
1049     ht_bin[0]=ht_bin[2];
1050     ht_bin[1]=ht_bin[3];
1051     ht_bin[2]=ht_bin[3]=-1;
1052   }
1053 }
1054
1055 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1056 {
1057   struct ll_entry *next;
1058   while(*head) {
1059     if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1060        ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1061     {
1062       inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1063       remove_hash((*head)->vaddr);
1064       next=(*head)->next;
1065       free(*head);
1066       *head=next;
1067     }
1068     else
1069     {
1070       head=&((*head)->next);
1071     }
1072   }
1073 }
1074
1075 // Remove all entries from linked list
1076 void ll_clear(struct ll_entry **head)
1077 {
1078   struct ll_entry *cur;
1079   struct ll_entry *next;
1080   if(cur=*head) {
1081     *head=0;
1082     while(cur) {
1083       next=cur->next;
1084       free(cur);
1085       cur=next;
1086     }
1087   }
1088 }
1089
1090 // Dereference the pointers and remove if it matches
1091 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1092 {
1093   while(head) {
1094     int ptr=get_pointer(head->addr);
1095     inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1096     if(((ptr>>shift)==(addr>>shift)) ||
1097        (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1098     {
1099       inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1100       u_int host_addr=(u_int)kill_pointer(head->addr);
1101       #ifdef __arm__
1102         needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1103       #endif
1104     }
1105     head=head->next;
1106   }
1107 }
1108
1109 // This is called when we write to a compiled block (see do_invstub)
1110 void invalidate_page(u_int page)
1111 {
1112   struct ll_entry *head;
1113   struct ll_entry *next;
1114   head=jump_in[page];
1115   jump_in[page]=0;
1116   while(head!=NULL) {
1117     inv_debug("INVALIDATE: %x\n",head->vaddr);
1118     remove_hash(head->vaddr);
1119     next=head->next;
1120     free(head);
1121     head=next;
1122   }
1123   head=jump_out[page];
1124   jump_out[page]=0;
1125   while(head!=NULL) {
1126     inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1127     u_int host_addr=(u_int)kill_pointer(head->addr);
1128     #ifdef __arm__
1129       needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1130     #endif
1131     next=head->next;
1132     free(head);
1133     head=next;
1134   }
1135 }
1136
1137 static void invalidate_block_range(u_int block, u_int first, u_int last)
1138 {
1139   u_int page=get_page(block<<12);
1140   //printf("first=%d last=%d\n",first,last);
1141   invalidate_page(page);
1142   assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1143   assert(last<page+5);
1144   // Invalidate the adjacent pages if a block crosses a 4K boundary
1145   while(first<page) {
1146     invalidate_page(first);
1147     first++;
1148   }
1149   for(first=page+1;first<last;first++) {
1150     invalidate_page(first);
1151   }
1152   #ifdef __arm__
1153     do_clear_cache();
1154   #endif
1155
1156   // Don't trap writes
1157   invalid_code[block]=1;
1158 #ifndef DISABLE_TLB
1159   // If there is a valid TLB entry for this page, remove write protect
1160   if(tlb_LUT_w[block]) {
1161     assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1162     // CHECK: Is this right?
1163     memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1164     u_int real_block=tlb_LUT_w[block]>>12;
1165     invalid_code[real_block]=1;
1166     if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1167   }
1168   else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1169 #endif
1170
1171   #ifdef USE_MINI_HT
1172   memset(mini_ht,-1,sizeof(mini_ht));
1173   #endif
1174 }
1175
1176 void invalidate_block(u_int block)
1177 {
1178   u_int page=get_page(block<<12);
1179   u_int vpage=get_vpage(block<<12);
1180   inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1181   //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1182   u_int first,last;
1183   first=last=page;
1184   struct ll_entry *head;
1185   head=jump_dirty[vpage];
1186   //printf("page=%d vpage=%d\n",page,vpage);
1187   while(head!=NULL) {
1188     u_int start,end;
1189     if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1190       get_bounds((int)head->addr,&start,&end);
1191       //printf("start: %x end: %x\n",start,end);
1192       if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
1193         if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1194           if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1195           if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1196         }
1197       }
1198 #ifndef DISABLE_TLB
1199       if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1200         if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1201           if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1202           if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1203         }
1204       }
1205 #endif
1206     }
1207     head=head->next;
1208   }
1209   invalidate_block_range(block,first,last);
1210 }
1211
1212 void invalidate_addr(u_int addr)
1213 {
1214 #ifdef PCSX
1215   //static int rhits;
1216   // this check is done by the caller
1217   //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
1218   u_int page=get_page(addr);
1219   if(page<2048) { // RAM
1220     struct ll_entry *head;
1221     u_int addr_min=~0, addr_max=0;
1222     int mask=RAM_SIZE-1;
1223     int pg1;
1224     inv_code_start=addr&~0xfff;
1225     inv_code_end=addr|0xfff;
1226     pg1=page;
1227     if (pg1>0) {
1228       // must check previous page too because of spans..
1229       pg1--;
1230       inv_code_start-=0x1000;
1231     }
1232     for(;pg1<=page;pg1++) {
1233       for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
1234         u_int start,end;
1235         get_bounds((int)head->addr,&start,&end);
1236         if((start&mask)<=(addr&mask)&&(addr&mask)<(end&mask)) {
1237           if(start<addr_min) addr_min=start;
1238           if(end>addr_max) addr_max=end;
1239         }
1240         else if(addr<start) {
1241           if(start<inv_code_end)
1242             inv_code_end=start-1;
1243         }
1244         else {
1245           if(end>inv_code_start)
1246             inv_code_start=end;
1247         }
1248       }
1249     }
1250     if (addr_min!=~0) {
1251       inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1252       inv_code_start=inv_code_end=~0;
1253       invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1254       return;
1255     }
1256     else {
1257       inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);//rhits);
1258     }
1259     //rhits=0;
1260     if(page!=0) // FIXME: don't know what's up with page 0 (Klonoa)
1261       return;
1262   }
1263 #endif
1264   invalidate_block(addr>>12);
1265 }
1266
1267 // This is called when loading a save state.
1268 // Anything could have changed, so invalidate everything.
1269 void invalidate_all_pages()
1270 {
1271   u_int page,n;
1272   for(page=0;page<4096;page++)
1273     invalidate_page(page);
1274   for(page=0;page<1048576;page++)
1275     if(!invalid_code[page]) {
1276       restore_candidate[(page&2047)>>3]|=1<<(page&7);
1277       restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1278     }
1279   #ifdef __arm__
1280   __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1281   #endif
1282   #ifdef USE_MINI_HT
1283   memset(mini_ht,-1,sizeof(mini_ht));
1284   #endif
1285   #ifndef DISABLE_TLB
1286   // TLB
1287   for(page=0;page<0x100000;page++) {
1288     if(tlb_LUT_r[page]) {
1289       memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1290       if(!tlb_LUT_w[page]||!invalid_code[page])
1291         memory_map[page]|=0x40000000; // Write protect
1292     }
1293     else memory_map[page]=-1;
1294     if(page==0x80000) page=0xC0000;
1295   }
1296   tlb_hacks();
1297   #endif
1298 }
1299
1300 // Add an entry to jump_out after making a link
1301 void add_link(u_int vaddr,void *src)
1302 {
1303   u_int page=get_page(vaddr);
1304   inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1305   int *ptr=(int *)(src+4);
1306   assert((*ptr&0x0fff0000)==0x059f0000);
1307   ll_add(jump_out+page,vaddr,src);
1308   //int ptr=get_pointer(src);
1309   //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1310 }
1311
1312 // If a code block was found to be unmodified (bit was set in
1313 // restore_candidate) and it remains unmodified (bit is clear
1314 // in invalid_code) then move the entries for that 4K page from
1315 // the dirty list to the clean list.
1316 void clean_blocks(u_int page)
1317 {
1318   struct ll_entry *head;
1319   inv_debug("INV: clean_blocks page=%d\n",page);
1320   head=jump_dirty[page];
1321   while(head!=NULL) {
1322     if(!invalid_code[head->vaddr>>12]) {
1323       // Don't restore blocks which are about to expire from the cache
1324       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1325         u_int start,end;
1326         if(verify_dirty((int)head->addr)) {
1327           //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1328           u_int i;
1329           u_int inv=0;
1330           get_bounds((int)head->addr,&start,&end);
1331           if(start-(u_int)rdram<RAM_SIZE) {
1332             for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1333               inv|=invalid_code[i];
1334             }
1335           }
1336           if((signed int)head->vaddr>=(signed int)0xC0000000) {
1337             u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1338             //printf("addr=%x start=%x end=%x\n",addr,start,end);
1339             if(addr<start||addr>=end) inv=1;
1340           }
1341           else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1342             inv=1;
1343           }
1344           if(!inv) {
1345             void * clean_addr=(void *)get_clean_addr((int)head->addr);
1346             if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1347               u_int ppage=page;
1348 #ifndef DISABLE_TLB
1349               if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1350 #endif
1351               inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1352               //printf("page=%x, addr=%x\n",page,head->vaddr);
1353               //assert(head->vaddr>>12==(page|0x80000));
1354               ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1355               int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1356               if(!head->reg32) {
1357                 if(ht_bin[0]==head->vaddr) {
1358                   ht_bin[1]=(int)clean_addr; // Replace existing entry
1359                 }
1360                 if(ht_bin[2]==head->vaddr) {
1361                   ht_bin[3]=(int)clean_addr; // Replace existing entry
1362                 }
1363               }
1364             }
1365           }
1366         }
1367       }
1368     }
1369     head=head->next;
1370   }
1371 }
1372
1373
1374 void mov_alloc(struct regstat *current,int i)
1375 {
1376   // Note: Don't need to actually alloc the source registers
1377   if((~current->is32>>rs1[i])&1) {
1378     //alloc_reg64(current,i,rs1[i]);
1379     alloc_reg64(current,i,rt1[i]);
1380     current->is32&=~(1LL<<rt1[i]);
1381   } else {
1382     //alloc_reg(current,i,rs1[i]);
1383     alloc_reg(current,i,rt1[i]);
1384     current->is32|=(1LL<<rt1[i]);
1385   }
1386   clear_const(current,rs1[i]);
1387   clear_const(current,rt1[i]);
1388   dirty_reg(current,rt1[i]);
1389 }
1390
1391 void shiftimm_alloc(struct regstat *current,int i)
1392 {
1393   clear_const(current,rs1[i]);
1394   clear_const(current,rt1[i]);
1395   if(opcode2[i]<=0x3) // SLL/SRL/SRA
1396   {
1397     if(rt1[i]) {
1398       if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1399       else lt1[i]=rs1[i];
1400       alloc_reg(current,i,rt1[i]);
1401       current->is32|=1LL<<rt1[i];
1402       dirty_reg(current,rt1[i]);
1403     }
1404   }
1405   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1406   {
1407     if(rt1[i]) {
1408       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1409       alloc_reg64(current,i,rt1[i]);
1410       current->is32&=~(1LL<<rt1[i]);
1411       dirty_reg(current,rt1[i]);
1412     }
1413   }
1414   if(opcode2[i]==0x3c) // DSLL32
1415   {
1416     if(rt1[i]) {
1417       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1418       alloc_reg64(current,i,rt1[i]);
1419       current->is32&=~(1LL<<rt1[i]);
1420       dirty_reg(current,rt1[i]);
1421     }
1422   }
1423   if(opcode2[i]==0x3e) // DSRL32
1424   {
1425     if(rt1[i]) {
1426       alloc_reg64(current,i,rs1[i]);
1427       if(imm[i]==32) {
1428         alloc_reg64(current,i,rt1[i]);
1429         current->is32&=~(1LL<<rt1[i]);
1430       } else {
1431         alloc_reg(current,i,rt1[i]);
1432         current->is32|=1LL<<rt1[i];
1433       }
1434       dirty_reg(current,rt1[i]);
1435     }
1436   }
1437   if(opcode2[i]==0x3f) // DSRA32
1438   {
1439     if(rt1[i]) {
1440       alloc_reg64(current,i,rs1[i]);
1441       alloc_reg(current,i,rt1[i]);
1442       current->is32|=1LL<<rt1[i];
1443       dirty_reg(current,rt1[i]);
1444     }
1445   }
1446 }
1447
1448 void shift_alloc(struct regstat *current,int i)
1449 {
1450   if(rt1[i]) {
1451     if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1452     {
1453       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1454       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1455       alloc_reg(current,i,rt1[i]);
1456       if(rt1[i]==rs2[i]) {
1457         alloc_reg_temp(current,i,-1);
1458         minimum_free_regs[i]=1;
1459       }
1460       current->is32|=1LL<<rt1[i];
1461     } else { // DSLLV/DSRLV/DSRAV
1462       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1463       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1464       alloc_reg64(current,i,rt1[i]);
1465       current->is32&=~(1LL<<rt1[i]);
1466       if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1467       {
1468         alloc_reg_temp(current,i,-1);
1469         minimum_free_regs[i]=1;
1470       }
1471     }
1472     clear_const(current,rs1[i]);
1473     clear_const(current,rs2[i]);
1474     clear_const(current,rt1[i]);
1475     dirty_reg(current,rt1[i]);
1476   }
1477 }
1478
1479 void alu_alloc(struct regstat *current,int i)
1480 {
1481   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1482     if(rt1[i]) {
1483       if(rs1[i]&&rs2[i]) {
1484         alloc_reg(current,i,rs1[i]);
1485         alloc_reg(current,i,rs2[i]);
1486       }
1487       else {
1488         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1489         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1490       }
1491       alloc_reg(current,i,rt1[i]);
1492     }
1493     current->is32|=1LL<<rt1[i];
1494   }
1495   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1496     if(rt1[i]) {
1497       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1498       {
1499         alloc_reg64(current,i,rs1[i]);
1500         alloc_reg64(current,i,rs2[i]);
1501         alloc_reg(current,i,rt1[i]);
1502       } else {
1503         alloc_reg(current,i,rs1[i]);
1504         alloc_reg(current,i,rs2[i]);
1505         alloc_reg(current,i,rt1[i]);
1506       }
1507     }
1508     current->is32|=1LL<<rt1[i];
1509   }
1510   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1511     if(rt1[i]) {
1512       if(rs1[i]&&rs2[i]) {
1513         alloc_reg(current,i,rs1[i]);
1514         alloc_reg(current,i,rs2[i]);
1515       }
1516       else
1517       {
1518         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1519         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1520       }
1521       alloc_reg(current,i,rt1[i]);
1522       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1523       {
1524         if(!((current->uu>>rt1[i])&1)) {
1525           alloc_reg64(current,i,rt1[i]);
1526         }
1527         if(get_reg(current->regmap,rt1[i]|64)>=0) {
1528           if(rs1[i]&&rs2[i]) {
1529             alloc_reg64(current,i,rs1[i]);
1530             alloc_reg64(current,i,rs2[i]);
1531           }
1532           else
1533           {
1534             // Is is really worth it to keep 64-bit values in registers?
1535             #ifdef NATIVE_64BIT
1536             if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1537             if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1538             #endif
1539           }
1540         }
1541         current->is32&=~(1LL<<rt1[i]);
1542       } else {
1543         current->is32|=1LL<<rt1[i];
1544       }
1545     }
1546   }
1547   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1548     if(rt1[i]) {
1549       if(rs1[i]&&rs2[i]) {
1550         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1551           alloc_reg64(current,i,rs1[i]);
1552           alloc_reg64(current,i,rs2[i]);
1553           alloc_reg64(current,i,rt1[i]);
1554         } else {
1555           alloc_reg(current,i,rs1[i]);
1556           alloc_reg(current,i,rs2[i]);
1557           alloc_reg(current,i,rt1[i]);
1558         }
1559       }
1560       else {
1561         alloc_reg(current,i,rt1[i]);
1562         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1563           // DADD used as move, or zeroing
1564           // If we have a 64-bit source, then make the target 64 bits too
1565           if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1566             if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1567             alloc_reg64(current,i,rt1[i]);
1568           } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1569             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1570             alloc_reg64(current,i,rt1[i]);
1571           }
1572           if(opcode2[i]>=0x2e&&rs2[i]) {
1573             // DSUB used as negation - 64-bit result
1574             // If we have a 32-bit register, extend it to 64 bits
1575             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1576             alloc_reg64(current,i,rt1[i]);
1577           }
1578         }
1579       }
1580       if(rs1[i]&&rs2[i]) {
1581         current->is32&=~(1LL<<rt1[i]);
1582       } else if(rs1[i]) {
1583         current->is32&=~(1LL<<rt1[i]);
1584         if((current->is32>>rs1[i])&1)
1585           current->is32|=1LL<<rt1[i];
1586       } else if(rs2[i]) {
1587         current->is32&=~(1LL<<rt1[i]);
1588         if((current->is32>>rs2[i])&1)
1589           current->is32|=1LL<<rt1[i];
1590       } else {
1591         current->is32|=1LL<<rt1[i];
1592       }
1593     }
1594   }
1595   clear_const(current,rs1[i]);
1596   clear_const(current,rs2[i]);
1597   clear_const(current,rt1[i]);
1598   dirty_reg(current,rt1[i]);
1599 }
1600
1601 void imm16_alloc(struct regstat *current,int i)
1602 {
1603   if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1604   else lt1[i]=rs1[i];
1605   if(rt1[i]) alloc_reg(current,i,rt1[i]);
1606   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1607     current->is32&=~(1LL<<rt1[i]);
1608     if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1609       // TODO: Could preserve the 32-bit flag if the immediate is zero
1610       alloc_reg64(current,i,rt1[i]);
1611       alloc_reg64(current,i,rs1[i]);
1612     }
1613     clear_const(current,rs1[i]);
1614     clear_const(current,rt1[i]);
1615   }
1616   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1617     if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1618     current->is32|=1LL<<rt1[i];
1619     clear_const(current,rs1[i]);
1620     clear_const(current,rt1[i]);
1621   }
1622   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1623     if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1624       if(rs1[i]!=rt1[i]) {
1625         if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1626         alloc_reg64(current,i,rt1[i]);
1627         current->is32&=~(1LL<<rt1[i]);
1628       }
1629     }
1630     else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1631     if(is_const(current,rs1[i])) {
1632       int v=get_const(current,rs1[i]);
1633       if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1634       if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1635       if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1636     }
1637     else clear_const(current,rt1[i]);
1638   }
1639   else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1640     if(is_const(current,rs1[i])) {
1641       int v=get_const(current,rs1[i]);
1642       set_const(current,rt1[i],v+imm[i]);
1643     }
1644     else clear_const(current,rt1[i]);
1645     current->is32|=1LL<<rt1[i];
1646   }
1647   else {
1648     set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1649     current->is32|=1LL<<rt1[i];
1650   }
1651   dirty_reg(current,rt1[i]);
1652 }
1653
1654 void load_alloc(struct regstat *current,int i)
1655 {
1656   clear_const(current,rt1[i]);
1657   //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1658   if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1659   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1660   if(rt1[i]&&!((current->u>>rt1[i])&1)) {
1661     alloc_reg(current,i,rt1[i]);
1662     assert(get_reg(current->regmap,rt1[i])>=0);
1663     if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1664     {
1665       current->is32&=~(1LL<<rt1[i]);
1666       alloc_reg64(current,i,rt1[i]);
1667     }
1668     else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1669     {
1670       current->is32&=~(1LL<<rt1[i]);
1671       alloc_reg64(current,i,rt1[i]);
1672       alloc_all(current,i);
1673       alloc_reg64(current,i,FTEMP);
1674       minimum_free_regs[i]=HOST_REGS;
1675     }
1676     else current->is32|=1LL<<rt1[i];
1677     dirty_reg(current,rt1[i]);
1678     // If using TLB, need a register for pointer to the mapping table
1679     if(using_tlb) alloc_reg(current,i,TLREG);
1680     // LWL/LWR need a temporary register for the old value
1681     if(opcode[i]==0x22||opcode[i]==0x26)
1682     {
1683       alloc_reg(current,i,FTEMP);
1684       alloc_reg_temp(current,i,-1);
1685       minimum_free_regs[i]=1;
1686     }
1687   }
1688   else
1689   {
1690     // Load to r0 or unneeded register (dummy load)
1691     // but we still need a register to calculate the address
1692     if(opcode[i]==0x22||opcode[i]==0x26)
1693     {
1694       alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1695     }
1696     // If using TLB, need a register for pointer to the mapping table
1697     if(using_tlb) alloc_reg(current,i,TLREG);
1698     alloc_reg_temp(current,i,-1);
1699     minimum_free_regs[i]=1;
1700     if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1701     {
1702       alloc_all(current,i);
1703       alloc_reg64(current,i,FTEMP);
1704       minimum_free_regs[i]=HOST_REGS;
1705     }
1706   }
1707 }
1708
1709 void store_alloc(struct regstat *current,int i)
1710 {
1711   clear_const(current,rs2[i]);
1712   if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1713   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1714   alloc_reg(current,i,rs2[i]);
1715   if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1716     alloc_reg64(current,i,rs2[i]);
1717     if(rs2[i]) alloc_reg(current,i,FTEMP);
1718   }
1719   // If using TLB, need a register for pointer to the mapping table
1720   if(using_tlb) alloc_reg(current,i,TLREG);
1721   #if defined(HOST_IMM8)
1722   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1723   else alloc_reg(current,i,INVCP);
1724   #endif
1725   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1726     alloc_reg(current,i,FTEMP);
1727   }
1728   // We need a temporary register for address generation
1729   alloc_reg_temp(current,i,-1);
1730   minimum_free_regs[i]=1;
1731 }
1732
1733 void c1ls_alloc(struct regstat *current,int i)
1734 {
1735   //clear_const(current,rs1[i]); // FIXME
1736   clear_const(current,rt1[i]);
1737   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1738   alloc_reg(current,i,CSREG); // Status
1739   alloc_reg(current,i,FTEMP);
1740   if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1741     alloc_reg64(current,i,FTEMP);
1742   }
1743   // If using TLB, need a register for pointer to the mapping table
1744   if(using_tlb) alloc_reg(current,i,TLREG);
1745   #if defined(HOST_IMM8)
1746   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1747   else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1748     alloc_reg(current,i,INVCP);
1749   #endif
1750   // We need a temporary register for address generation
1751   alloc_reg_temp(current,i,-1);
1752 }
1753
1754 void c2ls_alloc(struct regstat *current,int i)
1755 {
1756   clear_const(current,rt1[i]);
1757   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1758   alloc_reg(current,i,FTEMP);
1759   // If using TLB, need a register for pointer to the mapping table
1760   if(using_tlb) alloc_reg(current,i,TLREG);
1761   #if defined(HOST_IMM8)
1762   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1763   else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1764     alloc_reg(current,i,INVCP);
1765   #endif
1766   // We need a temporary register for address generation
1767   alloc_reg_temp(current,i,-1);
1768   minimum_free_regs[i]=1;
1769 }
1770
1771 #ifndef multdiv_alloc
1772 void multdiv_alloc(struct regstat *current,int i)
1773 {
1774   //  case 0x18: MULT
1775   //  case 0x19: MULTU
1776   //  case 0x1A: DIV
1777   //  case 0x1B: DIVU
1778   //  case 0x1C: DMULT
1779   //  case 0x1D: DMULTU
1780   //  case 0x1E: DDIV
1781   //  case 0x1F: DDIVU
1782   clear_const(current,rs1[i]);
1783   clear_const(current,rs2[i]);
1784   if(rs1[i]&&rs2[i])
1785   {
1786     if((opcode2[i]&4)==0) // 32-bit
1787     {
1788       current->u&=~(1LL<<HIREG);
1789       current->u&=~(1LL<<LOREG);
1790       alloc_reg(current,i,HIREG);
1791       alloc_reg(current,i,LOREG);
1792       alloc_reg(current,i,rs1[i]);
1793       alloc_reg(current,i,rs2[i]);
1794       current->is32|=1LL<<HIREG;
1795       current->is32|=1LL<<LOREG;
1796       dirty_reg(current,HIREG);
1797       dirty_reg(current,LOREG);
1798     }
1799     else // 64-bit
1800     {
1801       current->u&=~(1LL<<HIREG);
1802       current->u&=~(1LL<<LOREG);
1803       current->uu&=~(1LL<<HIREG);
1804       current->uu&=~(1LL<<LOREG);
1805       alloc_reg64(current,i,HIREG);
1806       //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1807       alloc_reg64(current,i,rs1[i]);
1808       alloc_reg64(current,i,rs2[i]);
1809       alloc_all(current,i);
1810       current->is32&=~(1LL<<HIREG);
1811       current->is32&=~(1LL<<LOREG);
1812       dirty_reg(current,HIREG);
1813       dirty_reg(current,LOREG);
1814       minimum_free_regs[i]=HOST_REGS;
1815     }
1816   }
1817   else
1818   {
1819     // Multiply by zero is zero.
1820     // MIPS does not have a divide by zero exception.
1821     // The result is undefined, we return zero.
1822     alloc_reg(current,i,HIREG);
1823     alloc_reg(current,i,LOREG);
1824     current->is32|=1LL<<HIREG;
1825     current->is32|=1LL<<LOREG;
1826     dirty_reg(current,HIREG);
1827     dirty_reg(current,LOREG);
1828   }
1829 }
1830 #endif
1831
1832 void cop0_alloc(struct regstat *current,int i)
1833 {
1834   if(opcode2[i]==0) // MFC0
1835   {
1836     if(rt1[i]) {
1837       clear_const(current,rt1[i]);
1838       alloc_all(current,i);
1839       alloc_reg(current,i,rt1[i]);
1840       current->is32|=1LL<<rt1[i];
1841       dirty_reg(current,rt1[i]);
1842     }
1843   }
1844   else if(opcode2[i]==4) // MTC0
1845   {
1846     if(rs1[i]){
1847       clear_const(current,rs1[i]);
1848       alloc_reg(current,i,rs1[i]);
1849       alloc_all(current,i);
1850     }
1851     else {
1852       alloc_all(current,i); // FIXME: Keep r0
1853       current->u&=~1LL;
1854       alloc_reg(current,i,0);
1855     }
1856   }
1857   else
1858   {
1859     // TLBR/TLBWI/TLBWR/TLBP/ERET
1860     assert(opcode2[i]==0x10);
1861     alloc_all(current,i);
1862   }
1863   minimum_free_regs[i]=HOST_REGS;
1864 }
1865
1866 void cop1_alloc(struct regstat *current,int i)
1867 {
1868   alloc_reg(current,i,CSREG); // Load status
1869   if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1870   {
1871     if(rt1[i]){
1872       clear_const(current,rt1[i]);
1873       if(opcode2[i]==1) {
1874         alloc_reg64(current,i,rt1[i]); // DMFC1
1875         current->is32&=~(1LL<<rt1[i]);
1876       }else{
1877         alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1878         current->is32|=1LL<<rt1[i];
1879       }
1880       dirty_reg(current,rt1[i]);
1881     }
1882     alloc_reg_temp(current,i,-1);
1883   }
1884   else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1885   {
1886     if(rs1[i]){
1887       clear_const(current,rs1[i]);
1888       if(opcode2[i]==5)
1889         alloc_reg64(current,i,rs1[i]); // DMTC1
1890       else
1891         alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1892       alloc_reg_temp(current,i,-1);
1893     }
1894     else {
1895       current->u&=~1LL;
1896       alloc_reg(current,i,0);
1897       alloc_reg_temp(current,i,-1);
1898     }
1899   }
1900   minimum_free_regs[i]=1;
1901 }
1902 void fconv_alloc(struct regstat *current,int i)
1903 {
1904   alloc_reg(current,i,CSREG); // Load status
1905   alloc_reg_temp(current,i,-1);
1906   minimum_free_regs[i]=1;
1907 }
1908 void float_alloc(struct regstat *current,int i)
1909 {
1910   alloc_reg(current,i,CSREG); // Load status
1911   alloc_reg_temp(current,i,-1);
1912   minimum_free_regs[i]=1;
1913 }
1914 void c2op_alloc(struct regstat *current,int i)
1915 {
1916   alloc_reg_temp(current,i,-1);
1917 }
1918 void fcomp_alloc(struct regstat *current,int i)
1919 {
1920   alloc_reg(current,i,CSREG); // Load status
1921   alloc_reg(current,i,FSREG); // Load flags
1922   dirty_reg(current,FSREG); // Flag will be modified
1923   alloc_reg_temp(current,i,-1);
1924   minimum_free_regs[i]=1;
1925 }
1926
1927 void syscall_alloc(struct regstat *current,int i)
1928 {
1929   alloc_cc(current,i);
1930   dirty_reg(current,CCREG);
1931   alloc_all(current,i);
1932   minimum_free_regs[i]=HOST_REGS;
1933   current->isconst=0;
1934 }
1935
1936 void delayslot_alloc(struct regstat *current,int i)
1937 {
1938   switch(itype[i]) {
1939     case UJUMP:
1940     case CJUMP:
1941     case SJUMP:
1942     case RJUMP:
1943     case FJUMP:
1944     case SYSCALL:
1945     case HLECALL:
1946     case SPAN:
1947       assem_debug("jump in the delay slot.  this shouldn't happen.\n");//exit(1);
1948       printf("Disabled speculative precompilation\n");
1949       stop_after_jal=1;
1950       break;
1951     case IMM16:
1952       imm16_alloc(current,i);
1953       break;
1954     case LOAD:
1955     case LOADLR:
1956       load_alloc(current,i);
1957       break;
1958     case STORE:
1959     case STORELR:
1960       store_alloc(current,i);
1961       break;
1962     case ALU:
1963       alu_alloc(current,i);
1964       break;
1965     case SHIFT:
1966       shift_alloc(current,i);
1967       break;
1968     case MULTDIV:
1969       multdiv_alloc(current,i);
1970       break;
1971     case SHIFTIMM:
1972       shiftimm_alloc(current,i);
1973       break;
1974     case MOV:
1975       mov_alloc(current,i);
1976       break;
1977     case COP0:
1978       cop0_alloc(current,i);
1979       break;
1980     case COP1:
1981     case COP2:
1982       cop1_alloc(current,i);
1983       break;
1984     case C1LS:
1985       c1ls_alloc(current,i);
1986       break;
1987     case C2LS:
1988       c2ls_alloc(current,i);
1989       break;
1990     case FCONV:
1991       fconv_alloc(current,i);
1992       break;
1993     case FLOAT:
1994       float_alloc(current,i);
1995       break;
1996     case FCOMP:
1997       fcomp_alloc(current,i);
1998       break;
1999     case C2OP:
2000       c2op_alloc(current,i);
2001       break;
2002   }
2003 }
2004
2005 // Special case where a branch and delay slot span two pages in virtual memory
2006 static void pagespan_alloc(struct regstat *current,int i)
2007 {
2008   current->isconst=0;
2009   current->wasconst=0;
2010   regs[i].wasconst=0;
2011   minimum_free_regs[i]=HOST_REGS;
2012   alloc_all(current,i);
2013   alloc_cc(current,i);
2014   dirty_reg(current,CCREG);
2015   if(opcode[i]==3) // JAL
2016   {
2017     alloc_reg(current,i,31);
2018     dirty_reg(current,31);
2019   }
2020   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
2021   {
2022     alloc_reg(current,i,rs1[i]);
2023     if (rt1[i]!=0) {
2024       alloc_reg(current,i,rt1[i]);
2025       dirty_reg(current,rt1[i]);
2026     }
2027   }
2028   if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
2029   {
2030     if(rs1[i]) alloc_reg(current,i,rs1[i]);
2031     if(rs2[i]) alloc_reg(current,i,rs2[i]);
2032     if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
2033     {
2034       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2035       if(rs2[i]) alloc_reg64(current,i,rs2[i]);
2036     }
2037   }
2038   else
2039   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
2040   {
2041     if(rs1[i]) alloc_reg(current,i,rs1[i]);
2042     if(!((current->is32>>rs1[i])&1))
2043     {
2044       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2045     }
2046   }
2047   else
2048   if(opcode[i]==0x11) // BC1
2049   {
2050     alloc_reg(current,i,FSREG);
2051     alloc_reg(current,i,CSREG);
2052   }
2053   //else ...
2054 }
2055
2056 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
2057 {
2058   stubs[stubcount][0]=type;
2059   stubs[stubcount][1]=addr;
2060   stubs[stubcount][2]=retaddr;
2061   stubs[stubcount][3]=a;
2062   stubs[stubcount][4]=b;
2063   stubs[stubcount][5]=c;
2064   stubs[stubcount][6]=d;
2065   stubs[stubcount][7]=e;
2066   stubcount++;
2067 }
2068
2069 // Write out a single register
2070 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2071 {
2072   int hr;
2073   for(hr=0;hr<HOST_REGS;hr++) {
2074     if(hr!=EXCLUDE_REG) {
2075       if((regmap[hr]&63)==r) {
2076         if((dirty>>hr)&1) {
2077           if(regmap[hr]<64) {
2078             emit_storereg(r,hr);
2079 #ifndef FORCE32
2080             if((is32>>regmap[hr])&1) {
2081               emit_sarimm(hr,31,hr);
2082               emit_storereg(r|64,hr);
2083             }
2084 #endif
2085           }else{
2086             emit_storereg(r|64,hr);
2087           }
2088         }
2089       }
2090     }
2091   }
2092 }
2093
2094 int mchecksum()
2095 {
2096   //if(!tracedebug) return 0;
2097   int i;
2098   int sum=0;
2099   for(i=0;i<2097152;i++) {
2100     unsigned int temp=sum;
2101     sum<<=1;
2102     sum|=(~temp)>>31;
2103     sum^=((u_int *)rdram)[i];
2104   }
2105   return sum;
2106 }
2107 int rchecksum()
2108 {
2109   int i;
2110   int sum=0;
2111   for(i=0;i<64;i++)
2112     sum^=((u_int *)reg)[i];
2113   return sum;
2114 }
2115 void rlist()
2116 {
2117   int i;
2118   printf("TRACE: ");
2119   for(i=0;i<32;i++)
2120     printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2121   printf("\n");
2122 #ifndef DISABLE_COP1
2123   printf("TRACE: ");
2124   for(i=0;i<32;i++)
2125     printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2126   printf("\n");
2127 #endif
2128 }
2129
2130 void enabletrace()
2131 {
2132   tracedebug=1;
2133 }
2134
2135 void memdebug(int i)
2136 {
2137   //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2138   //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2139   //rlist();
2140   //if(tracedebug) {
2141   //if(Count>=-2084597794) {
2142   if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2143   //if(0) {
2144     printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2145     //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2146     //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2147     rlist();
2148     #ifdef __i386__
2149     printf("TRACE: %x\n",(&i)[-1]);
2150     #endif
2151     #ifdef __arm__
2152     int j;
2153     printf("TRACE: %x \n",(&j)[10]);
2154     printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2155     #endif
2156     //fflush(stdout);
2157   }
2158   //printf("TRACE: %x\n",(&i)[-1]);
2159 }
2160
2161 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2162 {
2163   printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2164 }
2165
2166 void alu_assemble(int i,struct regstat *i_regs)
2167 {
2168   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2169     if(rt1[i]) {
2170       signed char s1,s2,t;
2171       t=get_reg(i_regs->regmap,rt1[i]);
2172       if(t>=0) {
2173         s1=get_reg(i_regs->regmap,rs1[i]);
2174         s2=get_reg(i_regs->regmap,rs2[i]);
2175         if(rs1[i]&&rs2[i]) {
2176           assert(s1>=0);
2177           assert(s2>=0);
2178           if(opcode2[i]&2) emit_sub(s1,s2,t);
2179           else emit_add(s1,s2,t);
2180         }
2181         else if(rs1[i]) {
2182           if(s1>=0) emit_mov(s1,t);
2183           else emit_loadreg(rs1[i],t);
2184         }
2185         else if(rs2[i]) {
2186           if(s2>=0) {
2187             if(opcode2[i]&2) emit_neg(s2,t);
2188             else emit_mov(s2,t);
2189           }
2190           else {
2191             emit_loadreg(rs2[i],t);
2192             if(opcode2[i]&2) emit_neg(t,t);
2193           }
2194         }
2195         else emit_zeroreg(t);
2196       }
2197     }
2198   }
2199   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2200     if(rt1[i]) {
2201       signed char s1l,s2l,s1h,s2h,tl,th;
2202       tl=get_reg(i_regs->regmap,rt1[i]);
2203       th=get_reg(i_regs->regmap,rt1[i]|64);
2204       if(tl>=0) {
2205         s1l=get_reg(i_regs->regmap,rs1[i]);
2206         s2l=get_reg(i_regs->regmap,rs2[i]);
2207         s1h=get_reg(i_regs->regmap,rs1[i]|64);
2208         s2h=get_reg(i_regs->regmap,rs2[i]|64);
2209         if(rs1[i]&&rs2[i]) {
2210           assert(s1l>=0);
2211           assert(s2l>=0);
2212           if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2213           else emit_adds(s1l,s2l,tl);
2214           if(th>=0) {
2215             #ifdef INVERTED_CARRY
2216             if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2217             #else
2218             if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2219             #endif
2220             else emit_add(s1h,s2h,th);
2221           }
2222         }
2223         else if(rs1[i]) {
2224           if(s1l>=0) emit_mov(s1l,tl);
2225           else emit_loadreg(rs1[i],tl);
2226           if(th>=0) {
2227             if(s1h>=0) emit_mov(s1h,th);
2228             else emit_loadreg(rs1[i]|64,th);
2229           }
2230         }
2231         else if(rs2[i]) {
2232           if(s2l>=0) {
2233             if(opcode2[i]&2) emit_negs(s2l,tl);
2234             else emit_mov(s2l,tl);
2235           }
2236           else {
2237             emit_loadreg(rs2[i],tl);
2238             if(opcode2[i]&2) emit_negs(tl,tl);
2239           }
2240           if(th>=0) {
2241             #ifdef INVERTED_CARRY
2242             if(s2h>=0) emit_mov(s2h,th);
2243             else emit_loadreg(rs2[i]|64,th);
2244             if(opcode2[i]&2) {
2245               emit_adcimm(-1,th); // x86 has inverted carry flag
2246               emit_not(th,th);
2247             }
2248             #else
2249             if(opcode2[i]&2) {
2250               if(s2h>=0) emit_rscimm(s2h,0,th);
2251               else {
2252                 emit_loadreg(rs2[i]|64,th);
2253                 emit_rscimm(th,0,th);
2254               }
2255             }else{
2256               if(s2h>=0) emit_mov(s2h,th);
2257               else emit_loadreg(rs2[i]|64,th);
2258             }
2259             #endif
2260           }
2261         }
2262         else {
2263           emit_zeroreg(tl);
2264           if(th>=0) emit_zeroreg(th);
2265         }
2266       }
2267     }
2268   }
2269   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2270     if(rt1[i]) {
2271       signed char s1l,s1h,s2l,s2h,t;
2272       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2273       {
2274         t=get_reg(i_regs->regmap,rt1[i]);
2275         //assert(t>=0);
2276         if(t>=0) {
2277           s1l=get_reg(i_regs->regmap,rs1[i]);
2278           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2279           s2l=get_reg(i_regs->regmap,rs2[i]);
2280           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2281           if(rs2[i]==0) // rx<r0
2282           {
2283             assert(s1h>=0);
2284             if(opcode2[i]==0x2a) // SLT
2285               emit_shrimm(s1h,31,t);
2286             else // SLTU (unsigned can not be less than zero)
2287               emit_zeroreg(t);
2288           }
2289           else if(rs1[i]==0) // r0<rx
2290           {
2291             assert(s2h>=0);
2292             if(opcode2[i]==0x2a) // SLT
2293               emit_set_gz64_32(s2h,s2l,t);
2294             else // SLTU (set if not zero)
2295               emit_set_nz64_32(s2h,s2l,t);
2296           }
2297           else {
2298             assert(s1l>=0);assert(s1h>=0);
2299             assert(s2l>=0);assert(s2h>=0);
2300             if(opcode2[i]==0x2a) // SLT
2301               emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2302             else // SLTU
2303               emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2304           }
2305         }
2306       } else {
2307         t=get_reg(i_regs->regmap,rt1[i]);
2308         //assert(t>=0);
2309         if(t>=0) {
2310           s1l=get_reg(i_regs->regmap,rs1[i]);
2311           s2l=get_reg(i_regs->regmap,rs2[i]);
2312           if(rs2[i]==0) // rx<r0
2313           {
2314             assert(s1l>=0);
2315             if(opcode2[i]==0x2a) // SLT
2316               emit_shrimm(s1l,31,t);
2317             else // SLTU (unsigned can not be less than zero)
2318               emit_zeroreg(t);
2319           }
2320           else if(rs1[i]==0) // r0<rx
2321           {
2322             assert(s2l>=0);
2323             if(opcode2[i]==0x2a) // SLT
2324               emit_set_gz32(s2l,t);
2325             else // SLTU (set if not zero)
2326               emit_set_nz32(s2l,t);
2327           }
2328           else{
2329             assert(s1l>=0);assert(s2l>=0);
2330             if(opcode2[i]==0x2a) // SLT
2331               emit_set_if_less32(s1l,s2l,t);
2332             else // SLTU
2333               emit_set_if_carry32(s1l,s2l,t);
2334           }
2335         }
2336       }
2337     }
2338   }
2339   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2340     if(rt1[i]) {
2341       signed char s1l,s1h,s2l,s2h,th,tl;
2342       tl=get_reg(i_regs->regmap,rt1[i]);
2343       th=get_reg(i_regs->regmap,rt1[i]|64);
2344       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2345       {
2346         assert(tl>=0);
2347         if(tl>=0) {
2348           s1l=get_reg(i_regs->regmap,rs1[i]);
2349           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2350           s2l=get_reg(i_regs->regmap,rs2[i]);
2351           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2352           if(rs1[i]&&rs2[i]) {
2353             assert(s1l>=0);assert(s1h>=0);
2354             assert(s2l>=0);assert(s2h>=0);
2355             if(opcode2[i]==0x24) { // AND
2356               emit_and(s1l,s2l,tl);
2357               emit_and(s1h,s2h,th);
2358             } else
2359             if(opcode2[i]==0x25) { // OR
2360               emit_or(s1l,s2l,tl);
2361               emit_or(s1h,s2h,th);
2362             } else
2363             if(opcode2[i]==0x26) { // XOR
2364               emit_xor(s1l,s2l,tl);
2365               emit_xor(s1h,s2h,th);
2366             } else
2367             if(opcode2[i]==0x27) { // NOR
2368               emit_or(s1l,s2l,tl);
2369               emit_or(s1h,s2h,th);
2370               emit_not(tl,tl);
2371               emit_not(th,th);
2372             }
2373           }
2374           else
2375           {
2376             if(opcode2[i]==0x24) { // AND
2377               emit_zeroreg(tl);
2378               emit_zeroreg(th);
2379             } else
2380             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2381               if(rs1[i]){
2382                 if(s1l>=0) emit_mov(s1l,tl);
2383                 else emit_loadreg(rs1[i],tl);
2384                 if(s1h>=0) emit_mov(s1h,th);
2385                 else emit_loadreg(rs1[i]|64,th);
2386               }
2387               else
2388               if(rs2[i]){
2389                 if(s2l>=0) emit_mov(s2l,tl);
2390                 else emit_loadreg(rs2[i],tl);
2391                 if(s2h>=0) emit_mov(s2h,th);
2392                 else emit_loadreg(rs2[i]|64,th);
2393               }
2394               else{
2395                 emit_zeroreg(tl);
2396                 emit_zeroreg(th);
2397               }
2398             } else
2399             if(opcode2[i]==0x27) { // NOR
2400               if(rs1[i]){
2401                 if(s1l>=0) emit_not(s1l,tl);
2402                 else{
2403                   emit_loadreg(rs1[i],tl);
2404                   emit_not(tl,tl);
2405                 }
2406                 if(s1h>=0) emit_not(s1h,th);
2407                 else{
2408                   emit_loadreg(rs1[i]|64,th);
2409                   emit_not(th,th);
2410                 }
2411               }
2412               else
2413               if(rs2[i]){
2414                 if(s2l>=0) emit_not(s2l,tl);
2415                 else{
2416                   emit_loadreg(rs2[i],tl);
2417                   emit_not(tl,tl);
2418                 }
2419                 if(s2h>=0) emit_not(s2h,th);
2420                 else{
2421                   emit_loadreg(rs2[i]|64,th);
2422                   emit_not(th,th);
2423                 }
2424               }
2425               else {
2426                 emit_movimm(-1,tl);
2427                 emit_movimm(-1,th);
2428               }
2429             }
2430           }
2431         }
2432       }
2433       else
2434       {
2435         // 32 bit
2436         if(tl>=0) {
2437           s1l=get_reg(i_regs->regmap,rs1[i]);
2438           s2l=get_reg(i_regs->regmap,rs2[i]);
2439           if(rs1[i]&&rs2[i]) {
2440             assert(s1l>=0);
2441             assert(s2l>=0);
2442             if(opcode2[i]==0x24) { // AND
2443               emit_and(s1l,s2l,tl);
2444             } else
2445             if(opcode2[i]==0x25) { // OR
2446               emit_or(s1l,s2l,tl);
2447             } else
2448             if(opcode2[i]==0x26) { // XOR
2449               emit_xor(s1l,s2l,tl);
2450             } else
2451             if(opcode2[i]==0x27) { // NOR
2452               emit_or(s1l,s2l,tl);
2453               emit_not(tl,tl);
2454             }
2455           }
2456           else
2457           {
2458             if(opcode2[i]==0x24) { // AND
2459               emit_zeroreg(tl);
2460             } else
2461             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2462               if(rs1[i]){
2463                 if(s1l>=0) emit_mov(s1l,tl);
2464                 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2465               }
2466               else
2467               if(rs2[i]){
2468                 if(s2l>=0) emit_mov(s2l,tl);
2469                 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2470               }
2471               else emit_zeroreg(tl);
2472             } else
2473             if(opcode2[i]==0x27) { // NOR
2474               if(rs1[i]){
2475                 if(s1l>=0) emit_not(s1l,tl);
2476                 else {
2477                   emit_loadreg(rs1[i],tl);
2478                   emit_not(tl,tl);
2479                 }
2480               }
2481               else
2482               if(rs2[i]){
2483                 if(s2l>=0) emit_not(s2l,tl);
2484                 else {
2485                   emit_loadreg(rs2[i],tl);
2486                   emit_not(tl,tl);
2487                 }
2488               }
2489               else emit_movimm(-1,tl);
2490             }
2491           }
2492         }
2493       }
2494     }
2495   }
2496 }
2497
2498 void imm16_assemble(int i,struct regstat *i_regs)
2499 {
2500   if (opcode[i]==0x0f) { // LUI
2501     if(rt1[i]) {
2502       signed char t;
2503       t=get_reg(i_regs->regmap,rt1[i]);
2504       //assert(t>=0);
2505       if(t>=0) {
2506         if(!((i_regs->isconst>>t)&1))
2507           emit_movimm(imm[i]<<16,t);
2508       }
2509     }
2510   }
2511   if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2512     if(rt1[i]) {
2513       signed char s,t;
2514       t=get_reg(i_regs->regmap,rt1[i]);
2515       s=get_reg(i_regs->regmap,rs1[i]);
2516       if(rs1[i]) {
2517         //assert(t>=0);
2518         //assert(s>=0);
2519         if(t>=0) {
2520           if(!((i_regs->isconst>>t)&1)) {
2521             if(s<0) {
2522               if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2523               emit_addimm(t,imm[i],t);
2524             }else{
2525               if(!((i_regs->wasconst>>s)&1))
2526                 emit_addimm(s,imm[i],t);
2527               else
2528                 emit_movimm(constmap[i][s]+imm[i],t);
2529             }
2530           }
2531         }
2532       } else {
2533         if(t>=0) {
2534           if(!((i_regs->isconst>>t)&1))
2535             emit_movimm(imm[i],t);
2536         }
2537       }
2538     }
2539   }
2540   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2541     if(rt1[i]) {
2542       signed char sh,sl,th,tl;
2543       th=get_reg(i_regs->regmap,rt1[i]|64);
2544       tl=get_reg(i_regs->regmap,rt1[i]);
2545       sh=get_reg(i_regs->regmap,rs1[i]|64);
2546       sl=get_reg(i_regs->regmap,rs1[i]);
2547       if(tl>=0) {
2548         if(rs1[i]) {
2549           assert(sh>=0);
2550           assert(sl>=0);
2551           if(th>=0) {
2552             emit_addimm64_32(sh,sl,imm[i],th,tl);
2553           }
2554           else {
2555             emit_addimm(sl,imm[i],tl);
2556           }
2557         } else {
2558           emit_movimm(imm[i],tl);
2559           if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2560         }
2561       }
2562     }
2563   }
2564   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2565     if(rt1[i]) {
2566       //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2567       signed char sh,sl,t;
2568       t=get_reg(i_regs->regmap,rt1[i]);
2569       sh=get_reg(i_regs->regmap,rs1[i]|64);
2570       sl=get_reg(i_regs->regmap,rs1[i]);
2571       //assert(t>=0);
2572       if(t>=0) {
2573         if(rs1[i]>0) {
2574           if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2575           if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2576             if(opcode[i]==0x0a) { // SLTI
2577               if(sl<0) {
2578                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2579                 emit_slti32(t,imm[i],t);
2580               }else{
2581                 emit_slti32(sl,imm[i],t);
2582               }
2583             }
2584             else { // SLTIU
2585               if(sl<0) {
2586                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2587                 emit_sltiu32(t,imm[i],t);
2588               }else{
2589                 emit_sltiu32(sl,imm[i],t);
2590               }
2591             }
2592           }else{ // 64-bit
2593             assert(sl>=0);
2594             if(opcode[i]==0x0a) // SLTI
2595               emit_slti64_32(sh,sl,imm[i],t);
2596             else // SLTIU
2597               emit_sltiu64_32(sh,sl,imm[i],t);
2598           }
2599         }else{
2600           // SLTI(U) with r0 is just stupid,
2601           // nonetheless examples can be found
2602           if(opcode[i]==0x0a) // SLTI
2603             if(0<imm[i]) emit_movimm(1,t);
2604             else emit_zeroreg(t);
2605           else // SLTIU
2606           {
2607             if(imm[i]) emit_movimm(1,t);
2608             else emit_zeroreg(t);
2609           }
2610         }
2611       }
2612     }
2613   }
2614   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2615     if(rt1[i]) {
2616       signed char sh,sl,th,tl;
2617       th=get_reg(i_regs->regmap,rt1[i]|64);
2618       tl=get_reg(i_regs->regmap,rt1[i]);
2619       sh=get_reg(i_regs->regmap,rs1[i]|64);
2620       sl=get_reg(i_regs->regmap,rs1[i]);
2621       if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2622         if(opcode[i]==0x0c) //ANDI
2623         {
2624           if(rs1[i]) {
2625             if(sl<0) {
2626               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2627               emit_andimm(tl,imm[i],tl);
2628             }else{
2629               if(!((i_regs->wasconst>>sl)&1))
2630                 emit_andimm(sl,imm[i],tl);
2631               else
2632                 emit_movimm(constmap[i][sl]&imm[i],tl);
2633             }
2634           }
2635           else
2636             emit_zeroreg(tl);
2637           if(th>=0) emit_zeroreg(th);
2638         }
2639         else
2640         {
2641           if(rs1[i]) {
2642             if(sl<0) {
2643               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2644             }
2645             if(th>=0) {
2646               if(sh<0) {
2647                 emit_loadreg(rs1[i]|64,th);
2648               }else{
2649                 emit_mov(sh,th);
2650               }
2651             }
2652             if(opcode[i]==0x0d) //ORI
2653             if(sl<0) {
2654               emit_orimm(tl,imm[i],tl);
2655             }else{
2656               if(!((i_regs->wasconst>>sl)&1))
2657                 emit_orimm(sl,imm[i],tl);
2658               else
2659                 emit_movimm(constmap[i][sl]|imm[i],tl);
2660             }
2661             if(opcode[i]==0x0e) //XORI
2662             if(sl<0) {
2663               emit_xorimm(tl,imm[i],tl);
2664             }else{
2665               if(!((i_regs->wasconst>>sl)&1))
2666                 emit_xorimm(sl,imm[i],tl);
2667               else
2668                 emit_movimm(constmap[i][sl]^imm[i],tl);
2669             }
2670           }
2671           else {
2672             emit_movimm(imm[i],tl);
2673             if(th>=0) emit_zeroreg(th);
2674           }
2675         }
2676       }
2677     }
2678   }
2679 }
2680
2681 void shiftimm_assemble(int i,struct regstat *i_regs)
2682 {
2683   if(opcode2[i]<=0x3) // SLL/SRL/SRA
2684   {
2685     if(rt1[i]) {
2686       signed char s,t;
2687       t=get_reg(i_regs->regmap,rt1[i]);
2688       s=get_reg(i_regs->regmap,rs1[i]);
2689       //assert(t>=0);
2690       if(t>=0){
2691         if(rs1[i]==0)
2692         {
2693           emit_zeroreg(t);
2694         }
2695         else
2696         {
2697           if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2698           if(imm[i]) {
2699             if(opcode2[i]==0) // SLL
2700             {
2701               emit_shlimm(s<0?t:s,imm[i],t);
2702             }
2703             if(opcode2[i]==2) // SRL
2704             {
2705               emit_shrimm(s<0?t:s,imm[i],t);
2706             }
2707             if(opcode2[i]==3) // SRA
2708             {
2709               emit_sarimm(s<0?t:s,imm[i],t);
2710             }
2711           }else{
2712             // Shift by zero
2713             if(s>=0 && s!=t) emit_mov(s,t);
2714           }
2715         }
2716       }
2717       //emit_storereg(rt1[i],t); //DEBUG
2718     }
2719   }
2720   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2721   {
2722     if(rt1[i]) {
2723       signed char sh,sl,th,tl;
2724       th=get_reg(i_regs->regmap,rt1[i]|64);
2725       tl=get_reg(i_regs->regmap,rt1[i]);
2726       sh=get_reg(i_regs->regmap,rs1[i]|64);
2727       sl=get_reg(i_regs->regmap,rs1[i]);
2728       if(tl>=0) {
2729         if(rs1[i]==0)
2730         {
2731           emit_zeroreg(tl);
2732           if(th>=0) emit_zeroreg(th);
2733         }
2734         else
2735         {
2736           assert(sl>=0);
2737           assert(sh>=0);
2738           if(imm[i]) {
2739             if(opcode2[i]==0x38) // DSLL
2740             {
2741               if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2742               emit_shlimm(sl,imm[i],tl);
2743             }
2744             if(opcode2[i]==0x3a) // DSRL
2745             {
2746               emit_shrdimm(sl,sh,imm[i],tl);
2747               if(th>=0) emit_shrimm(sh,imm[i],th);
2748             }
2749             if(opcode2[i]==0x3b) // DSRA
2750             {
2751               emit_shrdimm(sl,sh,imm[i],tl);
2752               if(th>=0) emit_sarimm(sh,imm[i],th);
2753             }
2754           }else{
2755             // Shift by zero
2756             if(sl!=tl) emit_mov(sl,tl);
2757             if(th>=0&&sh!=th) emit_mov(sh,th);
2758           }
2759         }
2760       }
2761     }
2762   }
2763   if(opcode2[i]==0x3c) // DSLL32
2764   {
2765     if(rt1[i]) {
2766       signed char sl,tl,th;
2767       tl=get_reg(i_regs->regmap,rt1[i]);
2768       th=get_reg(i_regs->regmap,rt1[i]|64);
2769       sl=get_reg(i_regs->regmap,rs1[i]);
2770       if(th>=0||tl>=0){
2771         assert(tl>=0);
2772         assert(th>=0);
2773         assert(sl>=0);
2774         emit_mov(sl,th);
2775         emit_zeroreg(tl);
2776         if(imm[i]>32)
2777         {
2778           emit_shlimm(th,imm[i]&31,th);
2779         }
2780       }
2781     }
2782   }
2783   if(opcode2[i]==0x3e) // DSRL32
2784   {
2785     if(rt1[i]) {
2786       signed char sh,tl,th;
2787       tl=get_reg(i_regs->regmap,rt1[i]);
2788       th=get_reg(i_regs->regmap,rt1[i]|64);
2789       sh=get_reg(i_regs->regmap,rs1[i]|64);
2790       if(tl>=0){
2791         assert(sh>=0);
2792         emit_mov(sh,tl);
2793         if(th>=0) emit_zeroreg(th);
2794         if(imm[i]>32)
2795         {
2796           emit_shrimm(tl,imm[i]&31,tl);
2797         }
2798       }
2799     }
2800   }
2801   if(opcode2[i]==0x3f) // DSRA32
2802   {
2803     if(rt1[i]) {
2804       signed char sh,tl;
2805       tl=get_reg(i_regs->regmap,rt1[i]);
2806       sh=get_reg(i_regs->regmap,rs1[i]|64);
2807       if(tl>=0){
2808         assert(sh>=0);
2809         emit_mov(sh,tl);
2810         if(imm[i]>32)
2811         {
2812           emit_sarimm(tl,imm[i]&31,tl);
2813         }
2814       }
2815     }
2816   }
2817 }
2818
2819 #ifndef shift_assemble
2820 void shift_assemble(int i,struct regstat *i_regs)
2821 {
2822   printf("Need shift_assemble for this architecture.\n");
2823   exit(1);
2824 }
2825 #endif
2826
2827 void load_assemble(int i,struct regstat *i_regs)
2828 {
2829   int s,th,tl,addr,map=-1;
2830   int offset;
2831   int jaddr=0;
2832   int memtarget=0,c=0;
2833   int fastload_reg_override=0;
2834   u_int hr,reglist=0;
2835   th=get_reg(i_regs->regmap,rt1[i]|64);
2836   tl=get_reg(i_regs->regmap,rt1[i]);
2837   s=get_reg(i_regs->regmap,rs1[i]);
2838   offset=imm[i];
2839   for(hr=0;hr<HOST_REGS;hr++) {
2840     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2841   }
2842   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2843   if(s>=0) {
2844     c=(i_regs->wasconst>>s)&1;
2845     if (c) {
2846       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2847       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2848     }
2849   }
2850   //printf("load_assemble: c=%d\n",c);
2851   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2852   // FIXME: Even if the load is a NOP, we should check for pagefaults...
2853 #ifdef PCSX
2854   if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2855     ||rt1[i]==0) {
2856       // could be FIFO, must perform the read
2857       // ||dummy read
2858       assem_debug("(forced read)\n");
2859       tl=get_reg(i_regs->regmap,-1);
2860       assert(tl>=0);
2861   }
2862 #endif
2863   if(offset||s<0||c) addr=tl;
2864   else addr=s;
2865   //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2866  if(tl>=0) {
2867   //printf("load_assemble: c=%d\n",c);
2868   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2869   assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2870   reglist&=~(1<<tl);
2871   if(th>=0) reglist&=~(1<<th);
2872   if(!using_tlb) {
2873     if(!c) {
2874       #ifdef RAM_OFFSET
2875       map=get_reg(i_regs->regmap,ROREG);
2876       if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2877       #endif
2878 //#define R29_HACK 1
2879       #ifdef R29_HACK
2880       // Strmnnrmn's speed hack
2881       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2882       #endif
2883       {
2884         #ifdef PCSX
2885         if(sp_in_mirror&&rs1[i]==29) {
2886           emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
2887           emit_cmpimm(HOST_TEMPREG,RAM_SIZE);
2888           fastload_reg_override=HOST_TEMPREG;
2889         }
2890         else
2891         #endif
2892         emit_cmpimm(addr,RAM_SIZE);
2893         jaddr=(int)out;
2894         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2895         // Hint to branch predictor that the branch is unlikely to be taken
2896         if(rs1[i]>=28)
2897           emit_jno_unlikely(0);
2898         else
2899         #endif
2900         emit_jno(0);
2901       }
2902     }
2903   }else{ // using tlb
2904     int x=0;
2905     if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2906     if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2907     map=get_reg(i_regs->regmap,TLREG);
2908     assert(map>=0);
2909     reglist&=~(1<<map);
2910     map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2911     do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2912   }
2913   int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2914   if (opcode[i]==0x20) { // LB
2915     if(!c||memtarget) {
2916       if(!dummy) {
2917         #ifdef HOST_IMM_ADDR32
2918         if(c)
2919           emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2920         else
2921         #endif
2922         {
2923           //emit_xorimm(addr,3,tl);
2924           //gen_tlb_addr_r(tl,map);
2925           //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2926           int x=0,a=tl;
2927 #ifdef BIG_ENDIAN_MIPS
2928           if(!c) emit_xorimm(addr,3,tl);
2929           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2930 #else
2931           if(!c) a=addr;
2932 #endif
2933           if(fastload_reg_override) a=fastload_reg_override;
2934
2935           emit_movsbl_indexed_tlb(x,a,map,tl);
2936         }
2937       }
2938       if(jaddr)
2939         add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2940     }
2941     else
2942       inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2943   }
2944   if (opcode[i]==0x21) { // LH
2945     if(!c||memtarget) {
2946       if(!dummy) {
2947         #ifdef HOST_IMM_ADDR32
2948         if(c)
2949           emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2950         else
2951         #endif
2952         {
2953           int x=0,a=tl;
2954 #ifdef BIG_ENDIAN_MIPS
2955           if(!c) emit_xorimm(addr,2,tl);
2956           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2957 #else
2958           if(!c) a=addr;
2959 #endif
2960           if(fastload_reg_override) a=fastload_reg_override;
2961           //#ifdef
2962           //emit_movswl_indexed_tlb(x,tl,map,tl);
2963           //else
2964           if(map>=0) {
2965             gen_tlb_addr_r(a,map);
2966             emit_movswl_indexed(x,a,tl);
2967           }else{
2968             #ifdef RAM_OFFSET
2969             emit_movswl_indexed(x,a,tl);
2970             #else
2971             emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2972             #endif
2973           }
2974         }
2975       }
2976       if(jaddr)
2977         add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2978     }
2979     else
2980       inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2981   }
2982   if (opcode[i]==0x23) { // LW
2983     if(!c||memtarget) {
2984       if(!dummy) {
2985         int a=addr;
2986         if(fastload_reg_override) a=fastload_reg_override;
2987         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2988         #ifdef HOST_IMM_ADDR32
2989         if(c)
2990           emit_readword_tlb(constmap[i][s]+offset,map,tl);
2991         else
2992         #endif
2993         emit_readword_indexed_tlb(0,a,map,tl);
2994       }
2995       if(jaddr)
2996         add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2997     }
2998     else
2999       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3000   }
3001   if (opcode[i]==0x24) { // LBU
3002     if(!c||memtarget) {
3003       if(!dummy) {
3004         #ifdef HOST_IMM_ADDR32
3005         if(c)
3006           emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
3007         else
3008         #endif
3009         {
3010           //emit_xorimm(addr,3,tl);
3011           //gen_tlb_addr_r(tl,map);
3012           //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
3013           int x=0,a=tl;
3014 #ifdef BIG_ENDIAN_MIPS
3015           if(!c) emit_xorimm(addr,3,tl);
3016           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3017 #else
3018           if(!c) a=addr;
3019 #endif
3020           if(fastload_reg_override) a=fastload_reg_override;
3021
3022           emit_movzbl_indexed_tlb(x,a,map,tl);
3023         }
3024       }
3025       if(jaddr)
3026         add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3027     }
3028     else
3029       inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3030   }
3031   if (opcode[i]==0x25) { // LHU
3032     if(!c||memtarget) {
3033       if(!dummy) {
3034         #ifdef HOST_IMM_ADDR32
3035         if(c)
3036           emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
3037         else
3038         #endif
3039         {
3040           int x=0,a=tl;
3041 #ifdef BIG_ENDIAN_MIPS
3042           if(!c) emit_xorimm(addr,2,tl);
3043           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3044 #else
3045           if(!c) a=addr;
3046 #endif
3047           if(fastload_reg_override) a=fastload_reg_override;
3048           //#ifdef
3049           //emit_movzwl_indexed_tlb(x,tl,map,tl);
3050           //#else
3051           if(map>=0) {
3052             gen_tlb_addr_r(a,map);
3053             emit_movzwl_indexed(x,a,tl);
3054           }else{
3055             #ifdef RAM_OFFSET
3056             emit_movzwl_indexed(x,a,tl);
3057             #else
3058             emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
3059             #endif
3060           }
3061         }
3062       }
3063       if(jaddr)
3064         add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3065     }
3066     else
3067       inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3068   }
3069   if (opcode[i]==0x27) { // LWU
3070     assert(th>=0);
3071     if(!c||memtarget) {
3072       if(!dummy) {
3073         int a=addr;
3074         if(fastload_reg_override) a=fastload_reg_override;
3075         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3076         #ifdef HOST_IMM_ADDR32
3077         if(c)
3078           emit_readword_tlb(constmap[i][s]+offset,map,tl);
3079         else
3080         #endif
3081         emit_readword_indexed_tlb(0,a,map,tl);
3082       }
3083       if(jaddr)
3084         add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3085     }
3086     else {
3087       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3088     }
3089     emit_zeroreg(th);
3090   }
3091   if (opcode[i]==0x37) { // LD
3092     if(!c||memtarget) {
3093       if(!dummy) {
3094         int a=addr;
3095         if(fastload_reg_override) a=fastload_reg_override;
3096         //gen_tlb_addr_r(tl,map);
3097         //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3098         //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3099         #ifdef HOST_IMM_ADDR32
3100         if(c)
3101           emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3102         else
3103         #endif
3104         emit_readdword_indexed_tlb(0,a,map,th,tl);
3105       }
3106       if(jaddr)
3107         add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3108     }
3109     else
3110       inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3111   }
3112  }
3113   //emit_storereg(rt1[i],tl); // DEBUG
3114   //if(opcode[i]==0x23)
3115   //if(opcode[i]==0x24)
3116   //if(opcode[i]==0x23||opcode[i]==0x24)
3117   /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3118   {
3119     //emit_pusha();
3120     save_regs(0x100f);
3121         emit_readword((int)&last_count,ECX);
3122         #ifdef __i386__
3123         if(get_reg(i_regs->regmap,CCREG)<0)
3124           emit_loadreg(CCREG,HOST_CCREG);
3125         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3126         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3127         emit_writeword(HOST_CCREG,(int)&Count);
3128         #endif
3129         #ifdef __arm__
3130         if(get_reg(i_regs->regmap,CCREG)<0)
3131           emit_loadreg(CCREG,0);
3132         else
3133           emit_mov(HOST_CCREG,0);
3134         emit_add(0,ECX,0);
3135         emit_addimm(0,2*ccadj[i],0);
3136         emit_writeword(0,(int)&Count);
3137         #endif
3138     emit_call((int)memdebug);
3139     //emit_popa();
3140     restore_regs(0x100f);
3141   }/**/
3142 }
3143
3144 #ifndef loadlr_assemble
3145 void loadlr_assemble(int i,struct regstat *i_regs)
3146 {
3147   printf("Need loadlr_assemble for this architecture.\n");
3148   exit(1);
3149 }
3150 #endif
3151
3152 void store_assemble(int i,struct regstat *i_regs)
3153 {
3154   int s,th,tl,map=-1;
3155   int addr,temp;
3156   int offset;
3157   int jaddr=0,jaddr2,type;
3158   int memtarget=0,c=0;
3159   int agr=AGEN1+(i&1);
3160   int faststore_reg_override=0;
3161   u_int hr,reglist=0;
3162   th=get_reg(i_regs->regmap,rs2[i]|64);
3163   tl=get_reg(i_regs->regmap,rs2[i]);
3164   s=get_reg(i_regs->regmap,rs1[i]);
3165   temp=get_reg(i_regs->regmap,agr);
3166   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3167   offset=imm[i];
3168   if(s>=0) {
3169     c=(i_regs->wasconst>>s)&1;
3170     if(c) {
3171       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3172       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3173     }
3174   }
3175   assert(tl>=0);
3176   assert(temp>=0);
3177   for(hr=0;hr<HOST_REGS;hr++) {
3178     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3179   }
3180   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3181   if(offset||s<0||c) addr=temp;
3182   else addr=s;
3183   if(!using_tlb) {
3184     if(!c) {
3185       #ifdef PCSX
3186       if(sp_in_mirror&&rs1[i]==29) {
3187         emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
3188         emit_cmpimm(HOST_TEMPREG,RAM_SIZE);
3189         faststore_reg_override=HOST_TEMPREG;
3190       }
3191       else
3192       #endif
3193       #ifdef R29_HACK
3194       // Strmnnrmn's speed hack
3195       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3196       #endif
3197       emit_cmpimm(addr,RAM_SIZE);
3198       #ifdef DESTRUCTIVE_SHIFT
3199       if(s==addr) emit_mov(s,temp);
3200       #endif
3201       #ifdef R29_HACK
3202       memtarget=1;
3203       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3204       #endif
3205       {
3206         jaddr=(int)out;
3207         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3208         // Hint to branch predictor that the branch is unlikely to be taken
3209         if(rs1[i]>=28)
3210           emit_jno_unlikely(0);
3211         else
3212         #endif
3213         emit_jno(0);
3214       }
3215     }
3216   }else{ // using tlb
3217     int x=0;
3218     if (opcode[i]==0x28) x=3; // SB
3219     if (opcode[i]==0x29) x=2; // SH
3220     map=get_reg(i_regs->regmap,TLREG);
3221     assert(map>=0);
3222     reglist&=~(1<<map);
3223     map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3224     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3225   }
3226
3227   if (opcode[i]==0x28) { // SB
3228     if(!c||memtarget) {
3229       int x=0,a=temp;
3230 #ifdef BIG_ENDIAN_MIPS
3231       if(!c) emit_xorimm(addr,3,temp);
3232       else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3233 #else
3234       if(!c) a=addr;
3235 #endif
3236       if(faststore_reg_override) a=faststore_reg_override;
3237       //gen_tlb_addr_w(temp,map);
3238       //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3239       emit_writebyte_indexed_tlb(tl,x,a,map,a);
3240     }
3241     type=STOREB_STUB;
3242   }
3243   if (opcode[i]==0x29) { // SH
3244     if(!c||memtarget) {
3245       int x=0,a=temp;
3246 #ifdef BIG_ENDIAN_MIPS
3247       if(!c) emit_xorimm(addr,2,temp);
3248       else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3249 #else
3250       if(!c) a=addr;
3251 #endif
3252       if(faststore_reg_override) a=faststore_reg_override;
3253       //#ifdef
3254       //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3255       //#else
3256       if(map>=0) {
3257         gen_tlb_addr_w(a,map);
3258         emit_writehword_indexed(tl,x,a);
3259       }else
3260         emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
3261     }
3262     type=STOREH_STUB;
3263   }
3264   if (opcode[i]==0x2B) { // SW
3265     if(!c||memtarget) {
3266       int a=addr;
3267       if(faststore_reg_override) a=faststore_reg_override;
3268       //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3269       emit_writeword_indexed_tlb(tl,0,a,map,temp);
3270     }
3271     type=STOREW_STUB;
3272   }
3273   if (opcode[i]==0x3F) { // SD
3274     if(!c||memtarget) {
3275       int a=addr;
3276       if(faststore_reg_override) a=faststore_reg_override;
3277       if(rs2[i]) {
3278         assert(th>=0);
3279         //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3280         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3281         emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
3282       }else{
3283         // Store zero
3284         //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3285         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3286         emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
3287       }
3288     }
3289     type=STORED_STUB;
3290   }
3291   if(!using_tlb) {
3292     if(!c||memtarget) {
3293       #ifdef DESTRUCTIVE_SHIFT
3294       // The x86 shift operation is 'destructive'; it overwrites the
3295       // source register, so we need to make a copy first and use that.
3296       addr=temp;
3297       #endif
3298       #if defined(HOST_IMM8)
3299       int ir=get_reg(i_regs->regmap,INVCP);
3300       assert(ir>=0);
3301       emit_cmpmem_indexedsr12_reg(ir,addr,1);
3302       #else
3303       emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3304       #endif
3305       #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3306       emit_callne(invalidate_addr_reg[addr]);
3307       #else
3308       jaddr2=(int)out;
3309       emit_jne(0);
3310       add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3311       #endif
3312     }
3313   }
3314   if(jaddr) {
3315     add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3316   } else if(c&&!memtarget) {
3317     inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3318   }
3319   //if(opcode[i]==0x2B || opcode[i]==0x3F)
3320   //if(opcode[i]==0x2B || opcode[i]==0x28)
3321   //if(opcode[i]==0x2B || opcode[i]==0x29)
3322   //if(opcode[i]==0x2B)
3323   /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3324   {
3325     #ifdef __i386__
3326     emit_pusha();
3327     #endif
3328     #ifdef __arm__
3329     save_regs(0x100f);
3330     #endif
3331         emit_readword((int)&last_count,ECX);
3332         #ifdef __i386__
3333         if(get_reg(i_regs->regmap,CCREG)<0)
3334           emit_loadreg(CCREG,HOST_CCREG);
3335         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3336         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3337         emit_writeword(HOST_CCREG,(int)&Count);
3338         #endif
3339         #ifdef __arm__
3340         if(get_reg(i_regs->regmap,CCREG)<0)
3341           emit_loadreg(CCREG,0);
3342         else
3343           emit_mov(HOST_CCREG,0);
3344         emit_add(0,ECX,0);
3345         emit_addimm(0,2*ccadj[i],0);
3346         emit_writeword(0,(int)&Count);
3347         #endif
3348     emit_call((int)memdebug);
3349     #ifdef __i386__
3350     emit_popa();
3351     #endif
3352     #ifdef __arm__
3353     restore_regs(0x100f);
3354     #endif
3355   }/**/
3356 }
3357
3358 void storelr_assemble(int i,struct regstat *i_regs)
3359 {
3360   int s,th,tl;
3361   int temp;
3362   int temp2;
3363   int offset;
3364   int jaddr=0,jaddr2;
3365   int case1,case2,case3;
3366   int done0,done1,done2;
3367   int memtarget=0,c=0;
3368   int agr=AGEN1+(i&1);
3369   u_int hr,reglist=0;
3370   th=get_reg(i_regs->regmap,rs2[i]|64);
3371   tl=get_reg(i_regs->regmap,rs2[i]);
3372   s=get_reg(i_regs->regmap,rs1[i]);
3373   temp=get_reg(i_regs->regmap,agr);
3374   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3375   offset=imm[i];
3376   if(s>=0) {
3377     c=(i_regs->isconst>>s)&1;
3378     if(c) {
3379       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3380       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3381     }
3382   }
3383   assert(tl>=0);
3384   for(hr=0;hr<HOST_REGS;hr++) {
3385     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3386   }
3387   assert(temp>=0);
3388   if(!using_tlb) {
3389     if(!c) {
3390       emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3391       if(!offset&&s!=temp) emit_mov(s,temp);
3392       jaddr=(int)out;
3393       emit_jno(0);
3394     }
3395     else
3396     {
3397       if(!memtarget||!rs1[i]) {
3398         jaddr=(int)out;
3399         emit_jmp(0);
3400       }
3401     }
3402     #ifdef RAM_OFFSET
3403     int map=get_reg(i_regs->regmap,ROREG);
3404     if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3405     gen_tlb_addr_w(temp,map);
3406     #else
3407     if((u_int)rdram!=0x80000000)
3408       emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3409     #endif
3410   }else{ // using tlb
3411     int map=get_reg(i_regs->regmap,TLREG);
3412     assert(map>=0);
3413     reglist&=~(1<<map);
3414     map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3415     if(!c&&!offset&&s>=0) emit_mov(s,temp);
3416     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3417     if(!jaddr&&!memtarget) {
3418       jaddr=(int)out;
3419       emit_jmp(0);
3420     }
3421     gen_tlb_addr_w(temp,map);
3422   }
3423
3424   if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3425     temp2=get_reg(i_regs->regmap,FTEMP);
3426     if(!rs2[i]) temp2=th=tl;
3427   }
3428
3429 #ifndef BIG_ENDIAN_MIPS
3430     emit_xorimm(temp,3,temp);
3431 #endif
3432   emit_testimm(temp,2);
3433   case2=(int)out;
3434   emit_jne(0);
3435   emit_testimm(temp,1);
3436   case1=(int)out;
3437   emit_jne(0);
3438   // 0
3439   if (opcode[i]==0x2A) { // SWL
3440     emit_writeword_indexed(tl,0,temp);
3441   }
3442   if (opcode[i]==0x2E) { // SWR
3443     emit_writebyte_indexed(tl,3,temp);
3444   }
3445   if (opcode[i]==0x2C) { // SDL
3446     emit_writeword_indexed(th,0,temp);
3447     if(rs2[i]) emit_mov(tl,temp2);
3448   }
3449   if (opcode[i]==0x2D) { // SDR
3450     emit_writebyte_indexed(tl,3,temp);
3451     if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3452   }
3453   done0=(int)out;
3454   emit_jmp(0);
3455   // 1
3456   set_jump_target(case1,(int)out);
3457   if (opcode[i]==0x2A) { // SWL
3458     // Write 3 msb into three least significant bytes
3459     if(rs2[i]) emit_rorimm(tl,8,tl);
3460     emit_writehword_indexed(tl,-1,temp);
3461     if(rs2[i]) emit_rorimm(tl,16,tl);
3462     emit_writebyte_indexed(tl,1,temp);
3463     if(rs2[i]) emit_rorimm(tl,8,tl);
3464   }
3465   if (opcode[i]==0x2E) { // SWR
3466     // Write two lsb into two most significant bytes
3467     emit_writehword_indexed(tl,1,temp);
3468   }
3469   if (opcode[i]==0x2C) { // SDL
3470     if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3471     // Write 3 msb into three least significant bytes
3472     if(rs2[i]) emit_rorimm(th,8,th);
3473     emit_writehword_indexed(th,-1,temp);
3474     if(rs2[i]) emit_rorimm(th,16,th);
3475     emit_writebyte_indexed(th,1,temp);
3476     if(rs2[i]) emit_rorimm(th,8,th);
3477   }
3478   if (opcode[i]==0x2D) { // SDR
3479     if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3480     // Write two lsb into two most significant bytes
3481     emit_writehword_indexed(tl,1,temp);
3482   }
3483   done1=(int)out;
3484   emit_jmp(0);
3485   // 2
3486   set_jump_target(case2,(int)out);
3487   emit_testimm(temp,1);
3488   case3=(int)out;
3489   emit_jne(0);
3490   if (opcode[i]==0x2A) { // SWL
3491     // Write two msb into two least significant bytes
3492     if(rs2[i]) emit_rorimm(tl,16,tl);
3493     emit_writehword_indexed(tl,-2,temp);
3494     if(rs2[i]) emit_rorimm(tl,16,tl);
3495   }
3496   if (opcode[i]==0x2E) { // SWR
3497     // Write 3 lsb into three most significant bytes
3498     emit_writebyte_indexed(tl,-1,temp);
3499     if(rs2[i]) emit_rorimm(tl,8,tl);
3500     emit_writehword_indexed(tl,0,temp);
3501     if(rs2[i]) emit_rorimm(tl,24,tl);
3502   }
3503   if (opcode[i]==0x2C) { // SDL
3504     if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3505     // Write two msb into two least significant bytes
3506     if(rs2[i]) emit_rorimm(th,16,th);
3507     emit_writehword_indexed(th,-2,temp);
3508     if(rs2[i]) emit_rorimm(th,16,th);
3509   }
3510   if (opcode[i]==0x2D) { // SDR
3511     if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3512     // Write 3 lsb into three most significant bytes
3513     emit_writebyte_indexed(tl,-1,temp);
3514     if(rs2[i]) emit_rorimm(tl,8,tl);
3515     emit_writehword_indexed(tl,0,temp);
3516     if(rs2[i]) emit_rorimm(tl,24,tl);
3517   }
3518   done2=(int)out;
3519   emit_jmp(0);
3520   // 3
3521   set_jump_target(case3,(int)out);
3522   if (opcode[i]==0x2A) { // SWL
3523     // Write msb into least significant byte
3524     if(rs2[i]) emit_rorimm(tl,24,tl);
3525     emit_writebyte_indexed(tl,-3,temp);
3526     if(rs2[i]) emit_rorimm(tl,8,tl);
3527   }
3528   if (opcode[i]==0x2E) { // SWR
3529     // Write entire word
3530     emit_writeword_indexed(tl,-3,temp);
3531   }
3532   if (opcode[i]==0x2C) { // SDL
3533     if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3534     // Write msb into least significant byte
3535     if(rs2[i]) emit_rorimm(th,24,th);
3536     emit_writebyte_indexed(th,-3,temp);
3537     if(rs2[i]) emit_rorimm(th,8,th);
3538   }
3539   if (opcode[i]==0x2D) { // SDR
3540     if(rs2[i]) emit_mov(th,temp2);
3541     // Write entire word
3542     emit_writeword_indexed(tl,-3,temp);
3543   }
3544   set_jump_target(done0,(int)out);
3545   set_jump_target(done1,(int)out);
3546   set_jump_target(done2,(int)out);
3547   if (opcode[i]==0x2C) { // SDL
3548     emit_testimm(temp,4);
3549     done0=(int)out;
3550     emit_jne(0);
3551     emit_andimm(temp,~3,temp);
3552     emit_writeword_indexed(temp2,4,temp);
3553     set_jump_target(done0,(int)out);
3554   }
3555   if (opcode[i]==0x2D) { // SDR
3556     emit_testimm(temp,4);
3557     done0=(int)out;
3558     emit_jeq(0);
3559     emit_andimm(temp,~3,temp);
3560     emit_writeword_indexed(temp2,-4,temp);
3561     set_jump_target(done0,(int)out);
3562   }
3563   if(!c||!memtarget)
3564     add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
3565   if(!using_tlb) {
3566     #ifdef RAM_OFFSET
3567     int map=get_reg(i_regs->regmap,ROREG);
3568     if(map<0) map=HOST_TEMPREG;
3569     gen_orig_addr_w(temp,map);
3570     #else
3571     emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3572     #endif
3573     #if defined(HOST_IMM8)
3574     int ir=get_reg(i_regs->regmap,INVCP);
3575     assert(ir>=0);
3576     emit_cmpmem_indexedsr12_reg(ir,temp,1);
3577     #else
3578     emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3579     #endif
3580     #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3581     emit_callne(invalidate_addr_reg[temp]);
3582     #else
3583     jaddr2=(int)out;
3584     emit_jne(0);
3585     add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3586     #endif
3587   }
3588   /*
3589     emit_pusha();
3590     //save_regs(0x100f);
3591         emit_readword((int)&last_count,ECX);
3592         if(get_reg(i_regs->regmap,CCREG)<0)
3593           emit_loadreg(CCREG,HOST_CCREG);
3594         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3595         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3596         emit_writeword(HOST_CCREG,(int)&Count);
3597     emit_call((int)memdebug);
3598     emit_popa();
3599     //restore_regs(0x100f);
3600   /**/
3601 }
3602
3603 void c1ls_assemble(int i,struct regstat *i_regs)
3604 {
3605 #ifndef DISABLE_COP1
3606   int s,th,tl;
3607   int temp,ar;
3608   int map=-1;
3609   int offset;
3610   int c=0;
3611   int jaddr,jaddr2=0,jaddr3,type;
3612   int agr=AGEN1+(i&1);
3613   u_int hr,reglist=0;
3614   th=get_reg(i_regs->regmap,FTEMP|64);
3615   tl=get_reg(i_regs->regmap,FTEMP);
3616   s=get_reg(i_regs->regmap,rs1[i]);
3617   temp=get_reg(i_regs->regmap,agr);
3618   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3619   offset=imm[i];
3620   assert(tl>=0);
3621   assert(rs1[i]>0);
3622   assert(temp>=0);
3623   for(hr=0;hr<HOST_REGS;hr++) {
3624     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3625   }
3626   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3627   if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3628   {
3629     // Loads use a temporary register which we need to save
3630     reglist|=1<<temp;
3631   }
3632   if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3633     ar=temp;
3634   else // LWC1/LDC1
3635     ar=tl;
3636   //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3637   //else c=(i_regs->wasconst>>s)&1;
3638   if(s>=0) c=(i_regs->wasconst>>s)&1;
3639   // Check cop1 unusable
3640   if(!cop1_usable) {
3641     signed char rs=get_reg(i_regs->regmap,CSREG);
3642     assert(rs>=0);
3643     emit_testimm(rs,0x20000000);
3644     jaddr=(int)out;
3645     emit_jeq(0);
3646     add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3647     cop1_usable=1;
3648   }
3649   if (opcode[i]==0x39) { // SWC1 (get float address)
3650     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],tl);
3651   }
3652   if (opcode[i]==0x3D) { // SDC1 (get double address)
3653     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],tl);
3654   }
3655   // Generate address + offset
3656   if(!using_tlb) {
3657     if(!c)
3658       emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3659   }
3660   else
3661   {
3662     map=get_reg(i_regs->regmap,TLREG);
3663     assert(map>=0);
3664     reglist&=~(1<<map);
3665     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3666       map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3667     }
3668     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3669       map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3670     }
3671   }
3672   if (opcode[i]==0x39) { // SWC1 (read float)
3673     emit_readword_indexed(0,tl,tl);
3674   }
3675   if (opcode[i]==0x3D) { // SDC1 (read double)
3676     emit_readword_indexed(4,tl,th);
3677     emit_readword_indexed(0,tl,tl);
3678   }
3679   if (opcode[i]==0x31) { // LWC1 (get target address)
3680     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],temp);
3681   }
3682   if (opcode[i]==0x35) { // LDC1 (get target address)
3683     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],temp);
3684   }
3685   if(!using_tlb) {
3686     if(!c) {
3687       jaddr2=(int)out;
3688       emit_jno(0);
3689     }
3690     else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
3691       jaddr2=(int)out;
3692       emit_jmp(0); // inline_readstub/inline_writestub?  Very rare case
3693     }
3694     #ifdef DESTRUCTIVE_SHIFT
3695     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3696       if(!offset&&!c&&s>=0) emit_mov(s,ar);
3697     }
3698     #endif
3699   }else{
3700     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3701       do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3702     }
3703     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3704       do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3705     }
3706   }
3707   if (opcode[i]==0x31) { // LWC1
3708     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3709     //gen_tlb_addr_r(ar,map);
3710     //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3711     #ifdef HOST_IMM_ADDR32
3712     if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3713     else
3714     #endif
3715     emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3716     type=LOADW_STUB;
3717   }
3718   if (opcode[i]==0x35) { // LDC1
3719     assert(th>=0);
3720     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3721     //gen_tlb_addr_r(ar,map);
3722     //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3723     //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3724     #ifdef HOST_IMM_ADDR32
3725     if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3726     else
3727     #endif
3728     emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3729     type=LOADD_STUB;
3730   }
3731   if (opcode[i]==0x39) { // SWC1
3732     //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3733     emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3734     type=STOREW_STUB;
3735   }
3736   if (opcode[i]==0x3D) { // SDC1
3737     assert(th>=0);
3738     //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3739     //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3740     emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3741     type=STORED_STUB;
3742   }
3743   if(!using_tlb) {
3744     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3745       #ifndef DESTRUCTIVE_SHIFT
3746       temp=offset||c||s<0?ar:s;
3747       #endif
3748       #if defined(HOST_IMM8)
3749       int ir=get_reg(i_regs->regmap,INVCP);
3750       assert(ir>=0);
3751       emit_cmpmem_indexedsr12_reg(ir,temp,1);
3752       #else
3753       emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3754       #endif
3755       #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3756       emit_callne(invalidate_addr_reg[temp]);
3757       #else
3758       jaddr3=(int)out;
3759       emit_jne(0);
3760       add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3761       #endif
3762     }
3763   }
3764   if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3765   if (opcode[i]==0x31) { // LWC1 (write float)
3766     emit_writeword_indexed(tl,0,temp);
3767   }
3768   if (opcode[i]==0x35) { // LDC1 (write double)
3769     emit_writeword_indexed(th,4,temp);
3770     emit_writeword_indexed(tl,0,temp);
3771   }
3772   //if(opcode[i]==0x39)
3773   /*if(opcode[i]==0x39||opcode[i]==0x31)
3774   {
3775     emit_pusha();
3776         emit_readword((int)&last_count,ECX);
3777         if(get_reg(i_regs->regmap,CCREG)<0)
3778           emit_loadreg(CCREG,HOST_CCREG);
3779         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3780         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3781         emit_writeword(HOST_CCREG,(int)&Count);
3782     emit_call((int)memdebug);
3783     emit_popa();
3784   }/**/
3785 #else
3786   cop1_unusable(i, i_regs);
3787 #endif
3788 }
3789
3790 void c2ls_assemble(int i,struct regstat *i_regs)
3791 {
3792   int s,tl;
3793   int ar;
3794   int offset;
3795   int memtarget=0,c=0;
3796   int jaddr2=0,jaddr3,type;
3797   int agr=AGEN1+(i&1);
3798   u_int hr,reglist=0;
3799   u_int copr=(source[i]>>16)&0x1f;
3800   s=get_reg(i_regs->regmap,rs1[i]);
3801   tl=get_reg(i_regs->regmap,FTEMP);
3802   offset=imm[i];
3803   assert(rs1[i]>0);
3804   assert(tl>=0);
3805   assert(!using_tlb);
3806
3807   for(hr=0;hr<HOST_REGS;hr++) {
3808     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3809   }
3810   if(i_regs->regmap[HOST_CCREG]==CCREG)
3811     reglist&=~(1<<HOST_CCREG);
3812
3813   // get the address
3814   if (opcode[i]==0x3a) { // SWC2
3815     ar=get_reg(i_regs->regmap,agr);
3816     if(ar<0) ar=get_reg(i_regs->regmap,-1);
3817     reglist|=1<<ar;
3818   } else { // LWC2
3819     ar=tl;
3820   }
3821   if(s>=0) c=(i_regs->wasconst>>s)&1;
3822   memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3823   if (!offset&&!c&&s>=0) ar=s;
3824   assert(ar>=0);
3825
3826   if (opcode[i]==0x3a) { // SWC2
3827     cop2_get_dreg(copr,tl,HOST_TEMPREG);
3828     type=STOREW_STUB;
3829   }
3830   else
3831     type=LOADW_STUB;
3832
3833   if(c&&!memtarget) {
3834     jaddr2=(int)out;
3835     emit_jmp(0); // inline_readstub/inline_writestub?
3836   }
3837   else {
3838     if(!c) {
3839       emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3840       jaddr2=(int)out;
3841       emit_jno(0);
3842     }
3843     if (opcode[i]==0x32) { // LWC2
3844       #ifdef HOST_IMM_ADDR32
3845       if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3846       else
3847       #endif
3848       emit_readword_indexed(0,ar,tl);
3849     }
3850     if (opcode[i]==0x3a) { // SWC2
3851       #ifdef DESTRUCTIVE_SHIFT
3852       if(!offset&&!c&&s>=0) emit_mov(s,ar);
3853       #endif
3854       emit_writeword_indexed(tl,0,ar);
3855     }
3856   }
3857   if(jaddr2)
3858     add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3859   if (opcode[i]==0x3a) { // SWC2
3860 #if defined(HOST_IMM8)
3861     int ir=get_reg(i_regs->regmap,INVCP);
3862     assert(ir>=0);
3863     emit_cmpmem_indexedsr12_reg(ir,ar,1);
3864 #else
3865     emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3866 #endif
3867     #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3868     emit_callne(invalidate_addr_reg[ar]);
3869     #else
3870     jaddr3=(int)out;
3871     emit_jne(0);
3872     add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3873     #endif
3874   }
3875   if (opcode[i]==0x32) { // LWC2
3876     cop2_put_dreg(copr,tl,HOST_TEMPREG);
3877   }
3878 }
3879
3880 #ifndef multdiv_assemble
3881 void multdiv_assemble(int i,struct regstat *i_regs)
3882 {
3883   printf("Need multdiv_assemble for this architecture.\n");
3884   exit(1);
3885 }
3886 #endif
3887
3888 void mov_assemble(int i,struct regstat *i_regs)
3889 {
3890   //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3891   //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3892   if(rt1[i]) {
3893     signed char sh,sl,th,tl;
3894     th=get_reg(i_regs->regmap,rt1[i]|64);
3895     tl=get_reg(i_regs->regmap,rt1[i]);
3896     //assert(tl>=0);
3897     if(tl>=0) {
3898       sh=get_reg(i_regs->regmap,rs1[i]|64);
3899       sl=get_reg(i_regs->regmap,rs1[i]);
3900       if(sl>=0) emit_mov(sl,tl);
3901       else emit_loadreg(rs1[i],tl);
3902       if(th>=0) {
3903         if(sh>=0) emit_mov(sh,th);
3904         else emit_loadreg(rs1[i]|64,th);
3905       }
3906     }
3907   }
3908 }
3909
3910 #ifndef fconv_assemble
3911 void fconv_assemble(int i,struct regstat *i_regs)
3912 {
3913   printf("Need fconv_assemble for this architecture.\n");
3914   exit(1);
3915 }
3916 #endif
3917
3918 #if 0
3919 void float_assemble(int i,struct regstat *i_regs)
3920 {
3921   printf("Need float_assemble for this architecture.\n");
3922   exit(1);
3923 }
3924 #endif
3925
3926 void syscall_assemble(int i,struct regstat *i_regs)
3927 {
3928   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3929   assert(ccreg==HOST_CCREG);
3930   assert(!is_delayslot);
3931   emit_movimm(start+i*4,EAX); // Get PC
3932   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right?  There should probably be an extra cycle...
3933   emit_jmp((int)jump_syscall_hle); // XXX
3934 }
3935
3936 void hlecall_assemble(int i,struct regstat *i_regs)
3937 {
3938   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3939   assert(ccreg==HOST_CCREG);
3940   assert(!is_delayslot);
3941   emit_movimm(start+i*4+4,0); // Get PC
3942   emit_movimm((int)psxHLEt[source[i]&7],1);
3943   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // XXX
3944   emit_jmp((int)jump_hlecall);
3945 }
3946
3947 void intcall_assemble(int i,struct regstat *i_regs)
3948 {
3949   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3950   assert(ccreg==HOST_CCREG);
3951   assert(!is_delayslot);
3952   emit_movimm(start+i*4,0); // Get PC
3953   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3954   emit_jmp((int)jump_intcall);
3955 }
3956
3957 void ds_assemble(int i,struct regstat *i_regs)
3958 {
3959   is_delayslot=1;
3960   switch(itype[i]) {
3961     case ALU:
3962       alu_assemble(i,i_regs);break;
3963     case IMM16:
3964       imm16_assemble(i,i_regs);break;
3965     case SHIFT:
3966       shift_assemble(i,i_regs);break;
3967     case SHIFTIMM:
3968       shiftimm_assemble(i,i_regs);break;
3969     case LOAD:
3970       load_assemble(i,i_regs);break;
3971     case LOADLR:
3972       loadlr_assemble(i,i_regs);break;
3973     case STORE:
3974       store_assemble(i,i_regs);break;
3975     case STORELR:
3976       storelr_assemble(i,i_regs);break;
3977     case COP0:
3978       cop0_assemble(i,i_regs);break;
3979     case COP1:
3980       cop1_assemble(i,i_regs);break;
3981     case C1LS:
3982       c1ls_assemble(i,i_regs);break;
3983     case COP2:
3984       cop2_assemble(i,i_regs);break;
3985     case C2LS:
3986       c2ls_assemble(i,i_regs);break;
3987     case C2OP:
3988       c2op_assemble(i,i_regs);break;
3989     case FCONV:
3990       fconv_assemble(i,i_regs);break;
3991     case FLOAT:
3992       float_assemble(i,i_regs);break;
3993     case FCOMP:
3994       fcomp_assemble(i,i_regs);break;
3995     case MULTDIV:
3996       multdiv_assemble(i,i_regs);break;
3997     case MOV:
3998       mov_assemble(i,i_regs);break;
3999     case SYSCALL:
4000     case HLECALL:
4001     case INTCALL:
4002     case SPAN:
4003     case UJUMP:
4004     case RJUMP:
4005     case CJUMP:
4006     case SJUMP:
4007     case FJUMP:
4008       printf("Jump in the delay slot.  This is probably a bug.\n");
4009   }
4010   is_delayslot=0;
4011 }
4012
4013 // Is the branch target a valid internal jump?
4014 int internal_branch(uint64_t i_is32,int addr)
4015 {
4016   if(addr&1) return 0; // Indirect (register) jump
4017   if(addr>=start && addr<start+slen*4-4)
4018   {
4019     int t=(addr-start)>>2;
4020     // Delay slots are not valid branch targets
4021     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4022     // 64 -> 32 bit transition requires a recompile
4023     /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
4024     {
4025       if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
4026       else printf("optimizable: yes\n");
4027     }*/
4028     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4029 #ifndef FORCE32
4030     if(requires_32bit[t]&~i_is32) return 0;
4031     else
4032 #endif
4033       return 1;
4034   }
4035   return 0;
4036 }
4037
4038 #ifndef wb_invalidate
4039 void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
4040   uint64_t u,uint64_t uu)
4041 {
4042   int hr;
4043   for(hr=0;hr<HOST_REGS;hr++) {
4044     if(hr!=EXCLUDE_REG) {
4045       if(pre[hr]!=entry[hr]) {
4046         if(pre[hr]>=0) {
4047           if((dirty>>hr)&1) {
4048             if(get_reg(entry,pre[hr])<0) {
4049               if(pre[hr]<64) {
4050                 if(!((u>>pre[hr])&1)) {
4051                   emit_storereg(pre[hr],hr);
4052                   if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
4053                     emit_sarimm(hr,31,hr);
4054                     emit_storereg(pre[hr]|64,hr);
4055                   }
4056                 }
4057               }else{
4058                 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
4059                   emit_storereg(pre[hr],hr);
4060                 }
4061               }
4062             }
4063           }
4064         }
4065       }
4066     }
4067   }
4068   // Move from one register to another (no writeback)
4069   for(hr=0;hr<HOST_REGS;hr++) {
4070     if(hr!=EXCLUDE_REG) {
4071       if(pre[hr]!=entry[hr]) {
4072         if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
4073           int nr;
4074           if((nr=get_reg(entry,pre[hr]))>=0) {
4075             emit_mov(hr,nr);
4076           }
4077         }
4078       }
4079     }
4080   }
4081 }
4082 #endif
4083
4084 // Load the specified registers
4085 // This only loads the registers given as arguments because
4086 // we don't want to load things that will be overwritten
4087 void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
4088 {
4089   int hr;
4090   // Load 32-bit regs
4091   for(hr=0;hr<HOST_REGS;hr++) {
4092     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4093       if(entry[hr]!=regmap[hr]) {
4094         if(regmap[hr]==rs1||regmap[hr]==rs2)
4095         {
4096           if(regmap[hr]==0) {
4097             emit_zeroreg(hr);
4098           }
4099           else
4100           {
4101             emit_loadreg(regmap[hr],hr);
4102           }
4103         }
4104       }
4105     }
4106   }
4107   //Load 64-bit regs
4108   for(hr=0;hr<HOST_REGS;hr++) {
4109     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4110       if(entry[hr]!=regmap[hr]) {
4111         if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
4112         {
4113           assert(regmap[hr]!=64);
4114           if((is32>>(regmap[hr]&63))&1) {
4115             int lr=get_reg(regmap,regmap[hr]-64);
4116             if(lr>=0)
4117               emit_sarimm(lr,31,hr);
4118             else
4119               emit_loadreg(regmap[hr],hr);
4120           }
4121           else
4122           {
4123             emit_loadreg(regmap[hr],hr);
4124           }
4125         }
4126       }
4127     }
4128   }
4129 }
4130
4131 // Load registers prior to the start of a loop
4132 // so that they are not loaded within the loop
4133 static void loop_preload(signed char pre[],signed char entry[])
4134 {
4135   int hr;
4136   for(hr=0;hr<HOST_REGS;hr++) {
4137     if(hr!=EXCLUDE_REG) {
4138       if(pre[hr]!=entry[hr]) {
4139         if(entry[hr]>=0) {
4140           if(get_reg(pre,entry[hr])<0) {
4141             assem_debug("loop preload:\n");
4142             //printf("loop preload: %d\n",hr);
4143             if(entry[hr]==0) {
4144               emit_zeroreg(hr);
4145             }
4146             else if(entry[hr]<TEMPREG)
4147             {
4148               emit_loadreg(entry[hr],hr);
4149             }
4150             else if(entry[hr]-64<TEMPREG)
4151             {
4152               emit_loadreg(entry[hr],hr);
4153             }
4154           }
4155         }
4156       }
4157     }
4158   }
4159 }
4160
4161 // Generate address for load/store instruction
4162 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
4163 void address_generation(int i,struct regstat *i_regs,signed char entry[])
4164 {
4165   if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
4166     int ra=-1;
4167     int agr=AGEN1+(i&1);
4168     int mgr=MGEN1+(i&1);
4169     if(itype[i]==LOAD) {
4170       ra=get_reg(i_regs->regmap,rt1[i]);
4171       if(ra<0) ra=get_reg(i_regs->regmap,-1);
4172       assert(ra>=0);
4173     }
4174     if(itype[i]==LOADLR) {
4175       ra=get_reg(i_regs->regmap,FTEMP);
4176     }
4177     if(itype[i]==STORE||itype[i]==STORELR) {
4178       ra=get_reg(i_regs->regmap,agr);
4179       if(ra<0) ra=get_reg(i_regs->regmap,-1);
4180     }
4181     if(itype[i]==C1LS||itype[i]==C2LS) {
4182       if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
4183         ra=get_reg(i_regs->regmap,FTEMP);
4184       else { // SWC1/SDC1/SWC2/SDC2
4185         ra=get_reg(i_regs->regmap,agr);
4186         if(ra<0) ra=get_reg(i_regs->regmap,-1);
4187       }
4188     }
4189     int rs=get_reg(i_regs->regmap,rs1[i]);
4190     int rm=get_reg(i_regs->regmap,TLREG);
4191     if(ra>=0) {
4192       int offset=imm[i];
4193       int c=(i_regs->wasconst>>rs)&1;
4194       if(rs1[i]==0) {
4195         // Using r0 as a base address
4196         /*if(rm>=0) {
4197           if(!entry||entry[rm]!=mgr) {
4198             generate_map_const(offset,rm);
4199           } // else did it in the previous cycle
4200         }*/
4201         if(!entry||entry[ra]!=agr) {
4202           if (opcode[i]==0x22||opcode[i]==0x26) {
4203             emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4204           }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4205             emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4206           }else{
4207             emit_movimm(offset,ra);
4208           }
4209         } // else did it in the previous cycle
4210       }
4211       else if(rs<0) {
4212         if(!entry||entry[ra]!=rs1[i])
4213           emit_loadreg(rs1[i],ra);
4214         //if(!entry||entry[ra]!=rs1[i])
4215         //  printf("poor load scheduling!\n");
4216       }
4217       else if(c) {
4218         if(rm>=0) {
4219           if(!entry||entry[rm]!=mgr) {
4220             if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
4221               // Stores to memory go thru the mapper to detect self-modifying
4222               // code, loads don't.
4223               if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
4224                  (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
4225                 generate_map_const(constmap[i][rs]+offset,rm);
4226             }else{
4227               if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
4228                 generate_map_const(constmap[i][rs]+offset,rm);
4229             }
4230           }
4231         }
4232         if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
4233           if(!entry||entry[ra]!=agr) {
4234             if (opcode[i]==0x22||opcode[i]==0x26) {
4235               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4236             }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4237               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4238             }else{
4239               #ifdef HOST_IMM_ADDR32
4240               if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4241                  (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4242               #endif
4243               emit_movimm(constmap[i][rs]+offset,ra);
4244             }
4245           } // else did it in the previous cycle
4246         } // else load_consts already did it
4247       }
4248       if(offset&&!c&&rs1[i]) {
4249         if(rs>=0) {
4250           emit_addimm(rs,offset,ra);
4251         }else{
4252           emit_addimm(ra,offset,ra);
4253         }
4254       }
4255     }
4256   }
4257   // Preload constants for next instruction
4258   if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
4259     int agr,ra;
4260     #ifndef HOST_IMM_ADDR32
4261     // Mapper entry
4262     agr=MGEN1+((i+1)&1);
4263     ra=get_reg(i_regs->regmap,agr);
4264     if(ra>=0) {
4265       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4266       int offset=imm[i+1];
4267       int c=(regs[i+1].wasconst>>rs)&1;
4268       if(c) {
4269         if(itype[i+1]==STORE||itype[i+1]==STORELR
4270            ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
4271           // Stores to memory go thru the mapper to detect self-modifying
4272           // code, loads don't.
4273           if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4274              (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
4275             generate_map_const(constmap[i+1][rs]+offset,ra);
4276         }else{
4277           if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4278             generate_map_const(constmap[i+1][rs]+offset,ra);
4279         }
4280       }
4281       /*else if(rs1[i]==0) {
4282         generate_map_const(offset,ra);
4283       }*/
4284     }
4285     #endif
4286     // Actual address
4287     agr=AGEN1+((i+1)&1);
4288     ra=get_reg(i_regs->regmap,agr);
4289     if(ra>=0) {
4290       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4291       int offset=imm[i+1];
4292       int c=(regs[i+1].wasconst>>rs)&1;
4293       if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4294         if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4295           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4296         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4297           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4298         }else{
4299           #ifdef HOST_IMM_ADDR32
4300           if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4301              (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4302           #endif
4303           emit_movimm(constmap[i+1][rs]+offset,ra);
4304         }
4305       }
4306       else if(rs1[i+1]==0) {
4307         // Using r0 as a base address
4308         if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4309           emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4310         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4311           emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4312         }else{
4313           emit_movimm(offset,ra);
4314         }
4315       }
4316     }
4317   }
4318 }
4319
4320 int get_final_value(int hr, int i, int *value)
4321 {
4322   int reg=regs[i].regmap[hr];
4323   while(i<slen-1) {
4324     if(regs[i+1].regmap[hr]!=reg) break;
4325     if(!((regs[i+1].isconst>>hr)&1)) break;
4326     if(bt[i+1]) break;
4327     i++;
4328   }
4329   if(i<slen-1) {
4330     if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4331       *value=constmap[i][hr];
4332       return 1;
4333     }
4334     if(!bt[i+1]) {
4335       if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4336         // Load in delay slot, out-of-order execution
4337         if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4338         {
4339           #ifdef HOST_IMM_ADDR32
4340           if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4341           #endif
4342           // Precompute load address
4343           *value=constmap[i][hr]+imm[i+2];
4344           return 1;
4345         }
4346       }
4347       if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4348       {
4349         #ifdef HOST_IMM_ADDR32
4350         if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4351         #endif
4352         // Precompute load address
4353         *value=constmap[i][hr]+imm[i+1];
4354         //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4355         return 1;
4356       }
4357     }
4358   }
4359   *value=constmap[i][hr];
4360   //printf("c=%x\n",(int)constmap[i][hr]);
4361   if(i==slen-1) return 1;
4362   if(reg<64) {
4363     return !((unneeded_reg[i+1]>>reg)&1);
4364   }else{
4365     return !((unneeded_reg_upper[i+1]>>reg)&1);
4366   }
4367 }
4368
4369 // Load registers with known constants
4370 void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4371 {
4372   int hr;
4373   // Load 32-bit regs
4374   for(hr=0;hr<HOST_REGS;hr++) {
4375     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4376       //if(entry[hr]!=regmap[hr]) {
4377       if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4378         if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4379           int value;
4380           if(get_final_value(hr,i,&value)) {
4381             if(value==0) {
4382               emit_zeroreg(hr);
4383             }
4384             else {
4385               emit_movimm(value,hr);
4386             }
4387           }
4388         }
4389       }
4390     }
4391   }
4392   // Load 64-bit regs
4393   for(hr=0;hr<HOST_REGS;hr++) {
4394     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4395       //if(entry[hr]!=regmap[hr]) {
4396       if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4397         if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4398           if((is32>>(regmap[hr]&63))&1) {
4399             int lr=get_reg(regmap,regmap[hr]-64);
4400             assert(lr>=0);
4401             emit_sarimm(lr,31,hr);
4402           }
4403           else
4404           {
4405             int value;
4406             if(get_final_value(hr,i,&value)) {
4407               if(value==0) {
4408                 emit_zeroreg(hr);
4409               }
4410               else {
4411                 emit_movimm(value,hr);
4412               }
4413             }
4414           }
4415         }
4416       }
4417     }
4418   }
4419 }
4420 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4421 {
4422   int hr;
4423   // Load 32-bit regs
4424   for(hr=0;hr<HOST_REGS;hr++) {
4425     if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4426       if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4427         int value=constmap[i][hr];
4428         if(value==0) {
4429           emit_zeroreg(hr);
4430         }
4431         else {
4432           emit_movimm(value,hr);
4433         }
4434       }
4435     }
4436   }
4437   // Load 64-bit regs
4438   for(hr=0;hr<HOST_REGS;hr++) {
4439     if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4440       if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4441         if((is32>>(regmap[hr]&63))&1) {
4442           int lr=get_reg(regmap,regmap[hr]-64);
4443           assert(lr>=0);
4444           emit_sarimm(lr,31,hr);
4445         }
4446         else
4447         {
4448           int value=constmap[i][hr];
4449           if(value==0) {
4450             emit_zeroreg(hr);
4451           }
4452           else {
4453             emit_movimm(value,hr);
4454           }
4455         }
4456       }
4457     }
4458   }
4459 }
4460
4461 // Write out all dirty registers (except cycle count)
4462 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4463 {
4464   int hr;
4465   for(hr=0;hr<HOST_REGS;hr++) {
4466     if(hr!=EXCLUDE_REG) {
4467       if(i_regmap[hr]>0) {
4468         if(i_regmap[hr]!=CCREG) {
4469           if((i_dirty>>hr)&1) {
4470             if(i_regmap[hr]<64) {
4471               emit_storereg(i_regmap[hr],hr);
4472 #ifndef FORCE32
4473               if( ((i_is32>>i_regmap[hr])&1) ) {
4474                 #ifdef DESTRUCTIVE_WRITEBACK
4475                 emit_sarimm(hr,31,hr);
4476                 emit_storereg(i_regmap[hr]|64,hr);
4477                 #else
4478                 emit_sarimm(hr,31,HOST_TEMPREG);
4479                 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4480                 #endif
4481               }
4482 #endif
4483             }else{
4484               if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4485                 emit_storereg(i_regmap[hr],hr);
4486               }
4487             }
4488           }
4489         }
4490       }
4491     }
4492   }
4493 }
4494 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4495 // This writes the registers not written by store_regs_bt
4496 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4497 {
4498   int hr;
4499   int t=(addr-start)>>2;
4500   for(hr=0;hr<HOST_REGS;hr++) {
4501     if(hr!=EXCLUDE_REG) {
4502       if(i_regmap[hr]>0) {
4503         if(i_regmap[hr]!=CCREG) {
4504           if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4505             if((i_dirty>>hr)&1) {
4506               if(i_regmap[hr]<64) {
4507                 emit_storereg(i_regmap[hr],hr);
4508 #ifndef FORCE32
4509                 if( ((i_is32>>i_regmap[hr])&1) ) {
4510                   #ifdef DESTRUCTIVE_WRITEBACK
4511                   emit_sarimm(hr,31,hr);
4512                   emit_storereg(i_regmap[hr]|64,hr);
4513                   #else
4514                   emit_sarimm(hr,31,HOST_TEMPREG);
4515                   emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4516                   #endif
4517                 }
4518 #endif
4519               }else{
4520                 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4521                   emit_storereg(i_regmap[hr],hr);
4522                 }
4523               }
4524             }
4525           }
4526         }
4527       }
4528     }
4529   }
4530 }
4531
4532 // Load all registers (except cycle count)
4533 void load_all_regs(signed char i_regmap[])
4534 {
4535   int hr;
4536   for(hr=0;hr<HOST_REGS;hr++) {
4537     if(hr!=EXCLUDE_REG) {
4538       if(i_regmap[hr]==0) {
4539         emit_zeroreg(hr);
4540       }
4541       else
4542       if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4543       {
4544         emit_loadreg(i_regmap[hr],hr);
4545       }
4546     }
4547   }
4548 }
4549
4550 // Load all current registers also needed by next instruction
4551 void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4552 {
4553   int hr;
4554   for(hr=0;hr<HOST_REGS;hr++) {
4555     if(hr!=EXCLUDE_REG) {
4556       if(get_reg(next_regmap,i_regmap[hr])>=0) {
4557         if(i_regmap[hr]==0) {
4558           emit_zeroreg(hr);
4559         }
4560         else
4561         if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4562         {
4563           emit_loadreg(i_regmap[hr],hr);
4564         }
4565       }
4566     }
4567   }
4568 }
4569
4570 // Load all regs, storing cycle count if necessary
4571 void load_regs_entry(int t)
4572 {
4573   int hr;
4574   if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER,HOST_CCREG);
4575   else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t]*CLOCK_DIVIDER,HOST_CCREG);
4576   if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4577     emit_storereg(CCREG,HOST_CCREG);
4578   }
4579   // Load 32-bit regs
4580   for(hr=0;hr<HOST_REGS;hr++) {
4581     if(regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
4582       if(regs[t].regmap_entry[hr]==0) {
4583         emit_zeroreg(hr);
4584       }
4585       else if(regs[t].regmap_entry[hr]!=CCREG)
4586       {
4587         emit_loadreg(regs[t].regmap_entry[hr],hr);
4588       }
4589     }
4590   }
4591   // Load 64-bit regs
4592   for(hr=0;hr<HOST_REGS;hr++) {
4593     if(regs[t].regmap_entry[hr]>=64&&regs[t].regmap_entry[hr]<TEMPREG+64) {
4594       assert(regs[t].regmap_entry[hr]!=64);
4595       if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4596         int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4597         if(lr<0) {
4598           emit_loadreg(regs[t].regmap_entry[hr],hr);
4599         }
4600         else
4601         {
4602           emit_sarimm(lr,31,hr);
4603         }
4604       }
4605       else
4606       {
4607         emit_loadreg(regs[t].regmap_entry[hr],hr);
4608       }
4609     }
4610   }
4611 }
4612
4613 // Store dirty registers prior to branch
4614 void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4615 {
4616   if(internal_branch(i_is32,addr))
4617   {
4618     int t=(addr-start)>>2;
4619     int hr;
4620     for(hr=0;hr<HOST_REGS;hr++) {
4621       if(hr!=EXCLUDE_REG) {
4622         if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4623           if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4624             if((i_dirty>>hr)&1) {
4625               if(i_regmap[hr]<64) {
4626                 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4627                   emit_storereg(i_regmap[hr],hr);
4628                   if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4629                     #ifdef DESTRUCTIVE_WRITEBACK
4630                     emit_sarimm(hr,31,hr);
4631                     emit_storereg(i_regmap[hr]|64,hr);
4632                     #else
4633                     emit_sarimm(hr,31,HOST_TEMPREG);
4634                     emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4635                     #endif
4636                   }
4637                 }
4638               }else{
4639                 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4640                   emit_storereg(i_regmap[hr],hr);
4641                 }
4642               }
4643             }
4644           }
4645         }
4646       }
4647     }
4648   }
4649   else
4650   {
4651     // Branch out of this block, write out all dirty regs
4652     wb_dirtys(i_regmap,i_is32,i_dirty);
4653   }
4654 }
4655
4656 // Load all needed registers for branch target
4657 void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4658 {
4659   //if(addr>=start && addr<(start+slen*4))
4660   if(internal_branch(i_is32,addr))
4661   {
4662     int t=(addr-start)>>2;
4663     int hr;
4664     // Store the cycle count before loading something else
4665     if(i_regmap[HOST_CCREG]!=CCREG) {
4666       assert(i_regmap[HOST_CCREG]==-1);
4667     }
4668     if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4669       emit_storereg(CCREG,HOST_CCREG);
4670     }
4671     // Load 32-bit regs
4672     for(hr=0;hr<HOST_REGS;hr++) {
4673       if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
4674         #ifdef DESTRUCTIVE_WRITEBACK
4675         if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4676         #else
4677         if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4678         #endif
4679           if(regs[t].regmap_entry[hr]==0) {
4680             emit_zeroreg(hr);
4681           }
4682           else if(regs[t].regmap_entry[hr]!=CCREG)
4683           {
4684             emit_loadreg(regs[t].regmap_entry[hr],hr);
4685           }
4686         }
4687       }
4688     }
4689     //Load 64-bit regs
4690     for(hr=0;hr<HOST_REGS;hr++) {
4691       if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=64&&regs[t].regmap_entry[hr]<TEMPREG+64) {
4692         if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4693           assert(regs[t].regmap_entry[hr]!=64);
4694           if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4695             int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4696             if(lr<0) {
4697               emit_loadreg(regs[t].regmap_entry[hr],hr);
4698             }
4699             else
4700             {
4701               emit_sarimm(lr,31,hr);
4702             }
4703           }
4704           else
4705           {
4706             emit_loadreg(regs[t].regmap_entry[hr],hr);
4707           }
4708         }
4709         else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4710           int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4711           assert(lr>=0);
4712           emit_sarimm(lr,31,hr);
4713         }
4714       }
4715     }
4716   }
4717 }
4718
4719 int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4720 {
4721   if(addr>=start && addr<start+slen*4-4)
4722   {
4723     int t=(addr-start)>>2;
4724     int hr;
4725     if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4726     for(hr=0;hr<HOST_REGS;hr++)
4727     {
4728       if(hr!=EXCLUDE_REG)
4729       {
4730         if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4731         {
4732           if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
4733           {
4734             return 0;
4735           }
4736           else
4737           if((i_dirty>>hr)&1)
4738           {
4739             if(i_regmap[hr]<TEMPREG)
4740             {
4741               if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4742                 return 0;
4743             }
4744             else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
4745             {
4746               if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4747                 return 0;
4748             }
4749           }
4750         }
4751         else // Same register but is it 32-bit or dirty?
4752         if(i_regmap[hr]>=0)
4753         {
4754           if(!((regs[t].dirty>>hr)&1))
4755           {
4756             if((i_dirty>>hr)&1)
4757             {
4758               if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4759               {
4760                 //printf("%x: dirty no match\n",addr);
4761                 return 0;
4762               }
4763             }
4764           }
4765           if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4766           {
4767             //printf("%x: is32 no match\n",addr);
4768             return 0;
4769           }
4770         }
4771       }
4772     }
4773     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4774 #ifndef FORCE32
4775     if(requires_32bit[t]&~i_is32) return 0;
4776 #endif
4777     // Delay slots are not valid branch targets
4778     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4779     // Delay slots require additional processing, so do not match
4780     if(is_ds[t]) return 0;
4781   }
4782   else
4783   {
4784     int hr;
4785     for(hr=0;hr<HOST_REGS;hr++)
4786     {
4787       if(hr!=EXCLUDE_REG)
4788       {
4789         if(i_regmap[hr]>=0)
4790         {
4791           if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4792           {
4793             if((i_dirty>>hr)&1)
4794             {
4795               return 0;
4796             }
4797           }
4798         }
4799       }
4800     }
4801   }
4802   return 1;
4803 }
4804
4805 // Used when a branch jumps into the delay slot of another branch
4806 void ds_assemble_entry(int i)
4807 {
4808   int t=(ba[i]-start)>>2;
4809   if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4810   assem_debug("Assemble delay slot at %x\n",ba[i]);
4811   assem_debug("<->\n");
4812   if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
4813     wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4814   load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4815   address_generation(t,&regs[t],regs[t].regmap_entry);
4816   if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
4817     load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4818   cop1_usable=0;
4819   is_delayslot=0;
4820   switch(itype[t]) {
4821     case ALU:
4822       alu_assemble(t,&regs[t]);break;
4823     case IMM16:
4824       imm16_assemble(t,&regs[t]);break;
4825     case SHIFT:
4826       shift_assemble(t,&regs[t]);break;
4827     case SHIFTIMM:
4828       shiftimm_assemble(t,&regs[t]);break;
4829     case LOAD:
4830       load_assemble(t,&regs[t]);break;
4831     case LOADLR:
4832       loadlr_assemble(t,&regs[t]);break;
4833     case STORE:
4834       store_assemble(t,&regs[t]);break;
4835     case STORELR:
4836       storelr_assemble(t,&regs[t]);break;
4837     case COP0:
4838       cop0_assemble(t,&regs[t]);break;
4839     case COP1:
4840       cop1_assemble(t,&regs[t]);break;
4841     case C1LS:
4842       c1ls_assemble(t,&regs[t]);break;
4843     case COP2:
4844       cop2_assemble(t,&regs[t]);break;
4845     case C2LS:
4846       c2ls_assemble(t,&regs[t]);break;
4847     case C2OP:
4848       c2op_assemble(t,&regs[t]);break;
4849     case FCONV:
4850       fconv_assemble(t,&regs[t]);break;
4851     case FLOAT:
4852       float_assemble(t,&regs[t]);break;
4853     case FCOMP:
4854       fcomp_assemble(t,&regs[t]);break;
4855     case MULTDIV:
4856       multdiv_assemble(t,&regs[t]);break;
4857     case MOV:
4858       mov_assemble(t,&regs[t]);break;
4859     case SYSCALL:
4860     case HLECALL:
4861     case INTCALL:
4862     case SPAN:
4863     case UJUMP:
4864     case RJUMP:
4865     case CJUMP:
4866     case SJUMP:
4867     case FJUMP:
4868       printf("Jump in the delay slot.  This is probably a bug.\n");
4869   }
4870   store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4871   load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4872   if(internal_branch(regs[t].is32,ba[i]+4))
4873     assem_debug("branch: internal\n");
4874   else
4875     assem_debug("branch: external\n");
4876   assert(internal_branch(regs[t].is32,ba[i]+4));
4877   add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4878   emit_jmp(0);
4879 }
4880
4881 void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4882 {
4883   int count;
4884   int jaddr;
4885   int idle=0;
4886   if(itype[i]==RJUMP)
4887   {
4888     *adj=0;
4889   }
4890   //if(ba[i]>=start && ba[i]<(start+slen*4))
4891   if(internal_branch(branch_regs[i].is32,ba[i]))
4892   {
4893     int t=(ba[i]-start)>>2;
4894     if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4895     else *adj=ccadj[t];
4896   }
4897   else
4898   {
4899     *adj=0;
4900   }
4901   count=ccadj[i];
4902   if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4903     // Idle loop
4904     if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4905     idle=(int)out;
4906     //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4907     emit_andimm(HOST_CCREG,3,HOST_CCREG);
4908     jaddr=(int)out;
4909     emit_jmp(0);
4910   }
4911   else if(*adj==0||invert) {
4912     emit_addimm_and_set_flags(CLOCK_DIVIDER*(count+2),HOST_CCREG);
4913     jaddr=(int)out;
4914     emit_jns(0);
4915   }
4916   else
4917   {
4918     emit_cmpimm(HOST_CCREG,-CLOCK_DIVIDER*(count+2));
4919     jaddr=(int)out;
4920     emit_jns(0);
4921   }
4922   add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4923 }
4924
4925 void do_ccstub(int n)
4926 {
4927   literal_pool(256);
4928   assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
4929   set_jump_target(stubs[n][1],(int)out);
4930   int i=stubs[n][4];
4931   if(stubs[n][6]==NULLDS) {
4932     // Delay slot instruction is nullified ("likely" branch)
4933     wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4934   }
4935   else if(stubs[n][6]!=TAKEN) {
4936     wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4937   }
4938   else {
4939     if(internal_branch(branch_regs[i].is32,ba[i]))
4940       wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4941   }
4942   if(stubs[n][5]!=-1)
4943   {
4944     // Save PC as return address
4945     emit_movimm(stubs[n][5],EAX);
4946     emit_writeword(EAX,(int)&pcaddr);
4947   }
4948   else
4949   {
4950     // Return address depends on which way the branch goes
4951     if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
4952     {
4953       int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4954       int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4955       int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4956       int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4957       if(rs1[i]==0)
4958       {
4959         s1l=s2l;s1h=s2h;
4960         s2l=s2h=-1;
4961       }
4962       else if(rs2[i]==0)
4963       {
4964         s2l=s2h=-1;
4965       }
4966       if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
4967         s1h=s2h=-1;
4968       }
4969       assert(s1l>=0);
4970       #ifdef DESTRUCTIVE_WRITEBACK
4971       if(rs1[i]) {
4972         if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
4973           emit_loadreg(rs1[i],s1l);
4974       }
4975       else {
4976         if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
4977           emit_loadreg(rs2[i],s1l);
4978       }
4979       if(s2l>=0)
4980         if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
4981           emit_loadreg(rs2[i],s2l);
4982       #endif
4983       int hr=0;
4984       int addr=-1,alt=-1,ntaddr=-1;
4985       while(hr<HOST_REGS)
4986       {
4987         if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4988            (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4989            (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4990         {
4991           addr=hr++;break;
4992         }
4993         hr++;
4994       }
4995       while(hr<HOST_REGS)
4996       {
4997         if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4998            (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4999            (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5000         {
5001           alt=hr++;break;
5002         }
5003         hr++;
5004       }
5005       if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
5006       {
5007         while(hr<HOST_REGS)
5008         {
5009           if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5010              (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5011              (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5012           {
5013             ntaddr=hr;break;
5014           }
5015           hr++;
5016         }
5017         assert(hr<HOST_REGS);
5018       }
5019       if((opcode[i]&0x2f)==4) // BEQ
5020       {
5021         #ifdef HAVE_CMOV_IMM
5022         if(s1h<0) {
5023           if(s2l>=0) emit_cmp(s1l,s2l);
5024           else emit_test(s1l,s1l);
5025           emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5026         }
5027         else
5028         #endif
5029         {
5030           emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5031           if(s1h>=0) {
5032             if(s2h>=0) emit_cmp(s1h,s2h);
5033             else emit_test(s1h,s1h);
5034             emit_cmovne_reg(alt,addr);
5035           }
5036           if(s2l>=0) emit_cmp(s1l,s2l);
5037           else emit_test(s1l,s1l);
5038           emit_cmovne_reg(alt,addr);
5039         }
5040       }
5041       if((opcode[i]&0x2f)==5) // BNE
5042       {
5043         #ifdef HAVE_CMOV_IMM
5044         if(s1h<0) {
5045           if(s2l>=0) emit_cmp(s1l,s2l);
5046           else emit_test(s1l,s1l);
5047           emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5048         }
5049         else
5050         #endif
5051         {
5052           emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5053           if(s1h>=0) {
5054             if(s2h>=0) emit_cmp(s1h,s2h);
5055             else emit_test(s1h,s1h);
5056             emit_cmovne_reg(alt,addr);
5057           }
5058           if(s2l>=0) emit_cmp(s1l,s2l);
5059           else emit_test(s1l,s1l);
5060           emit_cmovne_reg(alt,addr);
5061         }
5062       }
5063       if((opcode[i]&0x2f)==6) // BLEZ
5064       {
5065         //emit_movimm(ba[i],alt);
5066         //emit_movimm(start+i*4+8,addr);
5067         emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5068         emit_cmpimm(s1l,1);
5069         if(s1h>=0) emit_mov(addr,ntaddr);
5070         emit_cmovl_reg(alt,addr);
5071         if(s1h>=0) {
5072           emit_test(s1h,s1h);
5073           emit_cmovne_reg(ntaddr,addr);
5074           emit_cmovs_reg(alt,addr);
5075         }
5076       }
5077       if((opcode[i]&0x2f)==7) // BGTZ
5078       {
5079         //emit_movimm(ba[i],addr);
5080         //emit_movimm(start+i*4+8,ntaddr);
5081         emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5082         emit_cmpimm(s1l,1);
5083         if(s1h>=0) emit_mov(addr,alt);
5084         emit_cmovl_reg(ntaddr,addr);
5085         if(s1h>=0) {
5086           emit_test(s1h,s1h);
5087           emit_cmovne_reg(alt,addr);
5088           emit_cmovs_reg(ntaddr,addr);
5089         }
5090       }
5091       if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
5092       {
5093         //emit_movimm(ba[i],alt);
5094         //emit_movimm(start+i*4+8,addr);
5095         emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5096         if(s1h>=0) emit_test(s1h,s1h);
5097         else emit_test(s1l,s1l);
5098         emit_cmovs_reg(alt,addr);
5099       }
5100       if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
5101       {
5102         //emit_movimm(ba[i],addr);
5103         //emit_movimm(start+i*4+8,alt);
5104         emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5105         if(s1h>=0) emit_test(s1h,s1h);
5106         else emit_test(s1l,s1l);
5107         emit_cmovs_reg(alt,addr);
5108       }
5109       if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
5110         if(source[i]&0x10000) // BC1T
5111         {
5112           //emit_movimm(ba[i],alt);
5113           //emit_movimm(start+i*4+8,addr);
5114           emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5115           emit_testimm(s1l,0x800000);
5116           emit_cmovne_reg(alt,addr);
5117         }
5118         else // BC1F
5119         {
5120           //emit_movimm(ba[i],addr);
5121           //emit_movimm(start+i*4+8,alt);
5122           emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5123           emit_testimm(s1l,0x800000);
5124           emit_cmovne_reg(alt,addr);
5125         }
5126       }
5127       emit_writeword(addr,(int)&pcaddr);
5128     }
5129     else
5130     if(itype[i]==RJUMP)
5131     {
5132       int r=get_reg(branch_regs[i].regmap,rs1[i]);
5133       if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5134         r=get_reg(branch_regs[i].regmap,RTEMP);
5135       }
5136       emit_writeword(r,(int)&pcaddr);
5137     }
5138     else {printf("Unknown branch type in do_ccstub\n");exit(1);}
5139   }
5140   // Update cycle count
5141   assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5142   if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
5143   emit_call((int)cc_interrupt);
5144   if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
5145   if(stubs[n][6]==TAKEN) {
5146     if(internal_branch(branch_regs[i].is32,ba[i]))
5147       load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
5148     else if(itype[i]==RJUMP) {
5149       if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5150         emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5151       else
5152         emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
5153     }
5154   }else if(stubs[n][6]==NOTTAKEN) {
5155     if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5156     else load_all_regs(branch_regs[i].regmap);
5157   }else if(stubs[n][6]==NULLDS) {
5158     // Delay slot instruction is nullified ("likely" branch)
5159     if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5160     else load_all_regs(regs[i].regmap);
5161   }else{
5162     load_all_regs(branch_regs[i].regmap);
5163   }
5164   emit_jmp(stubs[n][2]); // return address
5165
5166   /* This works but uses a lot of memory...
5167   emit_readword((int)&last_count,ECX);
5168   emit_add(HOST_CCREG,ECX,EAX);
5169   emit_writeword(EAX,(int)&Count);
5170   emit_call((int)gen_interupt);
5171   emit_readword((int)&Count,HOST_CCREG);
5172   emit_readword((int)&next_interupt,EAX);
5173   emit_readword((int)&pending_exception,EBX);
5174   emit_writeword(EAX,(int)&last_count);
5175   emit_sub(HOST_CCREG,EAX,HOST_CCREG);
5176   emit_test(EBX,EBX);
5177   int jne_instr=(int)out;
5178   emit_jne(0);
5179   if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
5180   load_all_regs(branch_regs[i].regmap);
5181   emit_jmp(stubs[n][2]); // return address
5182   set_jump_target(jne_instr,(int)out);
5183   emit_readword((int)&pcaddr,EAX);
5184   // Call get_addr_ht instead of doing the hash table here.
5185   // This code is executed infrequently and takes up a lot of space
5186   // so smaller is better.
5187   emit_storereg(CCREG,HOST_CCREG);
5188   emit_pushreg(EAX);
5189   emit_call((int)get_addr_ht);
5190   emit_loadreg(CCREG,HOST_CCREG);
5191   emit_addimm(ESP,4,ESP);
5192   emit_jmpreg(EAX);*/
5193 }
5194
5195 add_to_linker(int addr,int target,int ext)
5196 {
5197   link_addr[linkcount][0]=addr;
5198   link_addr[linkcount][1]=target;
5199   link_addr[linkcount][2]=ext;
5200   linkcount++;
5201 }
5202
5203 static void ujump_assemble_write_ra(int i)
5204 {
5205   int rt;
5206   unsigned int return_address;
5207   rt=get_reg(branch_regs[i].regmap,31);
5208   assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5209   //assert(rt>=0);
5210   return_address=start+i*4+8;
5211   if(rt>=0) {
5212     #ifdef USE_MINI_HT
5213     if(internal_branch(branch_regs[i].is32,return_address)&&rt1[i+1]!=31) {
5214       int temp=-1; // note: must be ds-safe
5215       #ifdef HOST_TEMPREG
5216       temp=HOST_TEMPREG;
5217       #endif
5218       if(temp>=0) do_miniht_insert(return_address,rt,temp);
5219       else emit_movimm(return_address,rt);
5220     }
5221     else
5222     #endif
5223     {
5224       #ifdef REG_PREFETCH
5225       if(temp>=0)
5226       {
5227         if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5228       }
5229       #endif
5230       emit_movimm(return_address,rt); // PC into link register
5231       #ifdef IMM_PREFETCH
5232       emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5233       #endif
5234     }
5235   }
5236 }
5237
5238 void ujump_assemble(int i,struct regstat *i_regs)
5239 {
5240   signed char *i_regmap=i_regs->regmap;
5241   int ra_done=0;
5242   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5243   address_generation(i+1,i_regs,regs[i].regmap_entry);
5244   #ifdef REG_PREFETCH
5245   int temp=get_reg(branch_regs[i].regmap,PTEMP);
5246   if(rt1[i]==31&&temp>=0)
5247   {
5248     int return_address=start+i*4+8;
5249     if(get_reg(branch_regs[i].regmap,31)>0)
5250     if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5251   }
5252   #endif
5253   if(rt1[i]==31&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5254     ujump_assemble_write_ra(i); // writeback ra for DS
5255     ra_done=1;
5256   }
5257   ds_assemble(i+1,i_regs);
5258   uint64_t bc_unneeded=branch_regs[i].u;
5259   uint64_t bc_unneeded_upper=branch_regs[i].uu;
5260   bc_unneeded|=1|(1LL<<rt1[i]);
5261   bc_unneeded_upper|=1|(1LL<<rt1[i]);
5262   wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5263                 bc_unneeded,bc_unneeded_upper);
5264   load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5265   if(!ra_done&&rt1[i]==31)
5266     ujump_assemble_write_ra(i);
5267   int cc,adj;
5268   cc=get_reg(branch_regs[i].regmap,CCREG);
5269   assert(cc==HOST_CCREG);
5270   store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5271   #ifdef REG_PREFETCH
5272   if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5273   #endif
5274   do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5275   if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5276   load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5277   if(internal_branch(branch_regs[i].is32,ba[i]))
5278     assem_debug("branch: internal\n");
5279   else
5280     assem_debug("branch: external\n");
5281   if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5282     ds_assemble_entry(i);
5283   }
5284   else {
5285     add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5286     emit_jmp(0);
5287   }
5288 }
5289
5290 static void rjump_assemble_write_ra(int i)
5291 {
5292   int rt,return_address;
5293   assert(rt1[i+1]!=rt1[i]);
5294   assert(rt2[i+1]!=rt1[i]);
5295   rt=get_reg(branch_regs[i].regmap,rt1[i]);
5296   assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5297   assert(rt>=0);
5298   return_address=start+i*4+8;
5299   #ifdef REG_PREFETCH
5300   if(temp>=0)
5301   {
5302     if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5303   }
5304   #endif
5305   emit_movimm(return_address,rt); // PC into link register
5306   #ifdef IMM_PREFETCH
5307   emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5308   #endif
5309 }
5310
5311 void rjump_assemble(int i,struct regstat *i_regs)
5312 {
5313   signed char *i_regmap=i_regs->regmap;
5314   int temp;
5315   int rs,cc,adj;
5316   int ra_done=0;
5317   rs=get_reg(branch_regs[i].regmap,rs1[i]);
5318   assert(rs>=0);
5319   if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5320     // Delay slot abuse, make a copy of the branch address register
5321     temp=get_reg(branch_regs[i].regmap,RTEMP);
5322     assert(temp>=0);
5323     assert(regs[i].regmap[temp]==RTEMP);
5324     emit_mov(rs,temp);
5325     rs=temp;
5326   }
5327   address_generation(i+1,i_regs,regs[i].regmap_entry);
5328   #ifdef REG_PREFETCH
5329   if(rt1[i]==31)
5330   {
5331     if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5332       int return_address=start+i*4+8;
5333       if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5334     }
5335   }
5336   #endif
5337   #ifdef USE_MINI_HT
5338   if(rs1[i]==31) {
5339     int rh=get_reg(regs[i].regmap,RHASH);
5340     if(rh>=0) do_preload_rhash(rh);
5341   }
5342   #endif
5343   if(rt1[i]!=0&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5344     rjump_assemble_write_ra(i);
5345     ra_done=1;
5346   }
5347   ds_assemble(i+1,i_regs);
5348   uint64_t bc_unneeded=branch_regs[i].u;
5349   uint64_t bc_unneeded_upper=branch_regs[i].uu;
5350   bc_unneeded|=1|(1LL<<rt1[i]);
5351   bc_unneeded_upper|=1|(1LL<<rt1[i]);
5352   bc_unneeded&=~(1LL<<rs1[i]);
5353   wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5354                 bc_unneeded,bc_unneeded_upper);
5355   load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5356   if(!ra_done&&rt1[i]!=0)
5357     rjump_assemble_write_ra(i);
5358   cc=get_reg(branch_regs[i].regmap,CCREG);
5359   assert(cc==HOST_CCREG);
5360   #ifdef USE_MINI_HT
5361   int rh=get_reg(branch_regs[i].regmap,RHASH);
5362   int ht=get_reg(branch_regs[i].regmap,RHTBL);
5363   if(rs1[i]==31) {
5364     if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5365     do_preload_rhtbl(ht);
5366     do_rhash(rs,rh);
5367   }
5368   #endif
5369   store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5370   #ifdef DESTRUCTIVE_WRITEBACK
5371   if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5372     if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5373       emit_loadreg(rs1[i],rs);
5374     }
5375   }
5376   #endif
5377   #ifdef REG_PREFETCH
5378   if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5379   #endif
5380   #ifdef USE_MINI_HT
5381   if(rs1[i]==31) {
5382     do_miniht_load(ht,rh);
5383   }
5384   #endif
5385   //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5386   //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5387   //assert(adj==0);
5388   emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5389   add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5390   emit_jns(0);
5391   //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5392   #ifdef USE_MINI_HT
5393   if(rs1[i]==31) {
5394     do_miniht_jump(rs,rh,ht);
5395   }
5396   else
5397   #endif
5398   {
5399     //if(rs!=EAX) emit_mov(rs,EAX);
5400     //emit_jmp((int)jump_vaddr_eax);
5401     emit_jmp(jump_vaddr_reg[rs]);
5402   }
5403   /* Check hash table
5404   temp=!rs;
5405   emit_mov(rs,temp);
5406   emit_shrimm(rs,16,rs);
5407   emit_xor(temp,rs,rs);
5408   emit_movzwl_reg(rs,rs);
5409   emit_shlimm(rs,4,rs);
5410   emit_cmpmem_indexed((int)hash_table,rs,temp);
5411   emit_jne((int)out+14);
5412   emit_readword_indexed((int)hash_table+4,rs,rs);
5413   emit_jmpreg(rs);
5414   emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5415   emit_addimm_no_flags(8,rs);
5416   emit_jeq((int)out-17);
5417   // No hit on hash table, call compiler
5418   emit_pushreg(temp);
5419 //DEBUG >
5420 #ifdef DEBUG_CYCLE_COUNT
5421   emit_readword((int)&last_count,ECX);
5422   emit_add(HOST_CCREG,ECX,HOST_CCREG);
5423   emit_readword((int)&next_interupt,ECX);
5424   emit_writeword(HOST_CCREG,(int)&Count);
5425   emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5426   emit_writeword(ECX,(int)&last_count);
5427 #endif
5428 //DEBUG <
5429   emit_storereg(CCREG,HOST_CCREG);
5430   emit_call((int)get_addr);
5431   emit_loadreg(CCREG,HOST_CCREG);
5432   emit_addimm(ESP,4,ESP);
5433   emit_jmpreg(EAX);*/
5434   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5435   if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5436   #endif
5437 }
5438
5439 void cjump_assemble(int i,struct regstat *i_regs)
5440 {
5441   signed char *i_regmap=i_regs->regmap;
5442   int cc;
5443   int match;
5444   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5445   assem_debug("match=%d\n",match);
5446   int s1h,s1l,s2h,s2l;
5447   int prev_cop1_usable=cop1_usable;
5448   int unconditional=0,nop=0;
5449   int only32=0;
5450   int invert=0;
5451   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5452   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5453   if(!match) invert=1;
5454   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5455   if(i>(ba[i]-start)>>2) invert=1;
5456   #endif
5457
5458   if(ooo[i]) {
5459     s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5460     s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5461     s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5462     s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5463   }
5464   else {
5465     s1l=get_reg(i_regmap,rs1[i]);
5466     s1h=get_reg(i_regmap,rs1[i]|64);
5467     s2l=get_reg(i_regmap,rs2[i]);
5468     s2h=get_reg(i_regmap,rs2[i]|64);
5469   }
5470   if(rs1[i]==0&&rs2[i]==0)
5471   {
5472     if(opcode[i]&1) nop=1;
5473     else unconditional=1;
5474     //assert(opcode[i]!=5);
5475     //assert(opcode[i]!=7);
5476     //assert(opcode[i]!=0x15);
5477     //assert(opcode[i]!=0x17);
5478   }
5479   else if(rs1[i]==0)
5480   {
5481     s1l=s2l;s1h=s2h;
5482     s2l=s2h=-1;
5483     only32=(regs[i].was32>>rs2[i])&1;
5484   }
5485   else if(rs2[i]==0)
5486   {
5487     s2l=s2h=-1;
5488     only32=(regs[i].was32>>rs1[i])&1;
5489   }
5490   else {
5491     only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5492   }
5493
5494   if(ooo[i]) {
5495     // Out of order execution (delay slot first)
5496     //printf("OOOE\n");
5497     address_generation(i+1,i_regs,regs[i].regmap_entry);
5498     ds_assemble(i+1,i_regs);
5499     int adj;
5500     uint64_t bc_unneeded=branch_regs[i].u;
5501     uint64_t bc_unneeded_upper=branch_regs[i].uu;
5502     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5503     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5504     bc_unneeded|=1;
5505     bc_unneeded_upper|=1;
5506     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5507                   bc_unneeded,bc_unneeded_upper);
5508     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5509     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5510     cc=get_reg(branch_regs[i].regmap,CCREG);
5511     assert(cc==HOST_CCREG);
5512     if(unconditional)
5513       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5514     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5515     //assem_debug("cycle count (adj)\n");
5516     if(unconditional) {
5517       do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5518       if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5519         if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5520         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5521         if(internal)
5522           assem_debug("branch: internal\n");
5523         else
5524           assem_debug("branch: external\n");
5525         if(internal&&is_ds[(ba[i]-start)>>2]) {
5526           ds_assemble_entry(i);
5527         }
5528         else {
5529           add_to_linker((int)out,ba[i],internal);
5530           emit_jmp(0);
5531         }
5532         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5533         if(((u_int)out)&7) emit_addnop(0);
5534         #endif
5535       }
5536     }
5537     else if(nop) {
5538       emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5539       int jaddr=(int)out;
5540       emit_jns(0);
5541       add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5542     }
5543     else {
5544       int taken=0,nottaken=0,nottaken1=0;
5545       do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5546       if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5547       if(!only32)
5548       {
5549         assert(s1h>=0);
5550         if(opcode[i]==4) // BEQ
5551         {
5552           if(s2h>=0) emit_cmp(s1h,s2h);
5553           else emit_test(s1h,s1h);
5554           nottaken1=(int)out;
5555           emit_jne(1);
5556         }
5557         if(opcode[i]==5) // BNE
5558         {
5559           if(s2h>=0) emit_cmp(s1h,s2h);
5560           else emit_test(s1h,s1h);
5561           if(invert) taken=(int)out;
5562           else add_to_linker((int)out,ba[i],internal);
5563           emit_jne(0);
5564         }
5565         if(opcode[i]==6) // BLEZ
5566         {
5567           emit_test(s1h,s1h);
5568           if(invert) taken=(int)out;
5569           else add_to_linker((int)out,ba[i],internal);
5570           emit_js(0);
5571           nottaken1=(int)out;
5572           emit_jne(1);
5573         }
5574         if(opcode[i]==7) // BGTZ
5575         {
5576           emit_test(s1h,s1h);
5577           nottaken1=(int)out;
5578           emit_js(1);
5579           if(invert) taken=(int)out;
5580           else add_to_linker((int)out,ba[i],internal);
5581           emit_jne(0);
5582         }
5583       } // if(!only32)
5584
5585       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5586       assert(s1l>=0);
5587       if(opcode[i]==4) // BEQ
5588       {
5589         if(s2l>=0) emit_cmp(s1l,s2l);
5590         else emit_test(s1l,s1l);
5591         if(invert){
5592           nottaken=(int)out;
5593           emit_jne(1);
5594         }else{
5595           add_to_linker((int)out,ba[i],internal);
5596           emit_jeq(0);
5597         }
5598       }
5599       if(opcode[i]==5) // BNE
5600       {
5601         if(s2l>=0) emit_cmp(s1l,s2l);
5602         else emit_test(s1l,s1l);
5603         if(invert){
5604           nottaken=(int)out;
5605           emit_jeq(1);
5606         }else{
5607           add_to_linker((int)out,ba[i],internal);
5608           emit_jne(0);
5609         }
5610       }
5611       if(opcode[i]==6) // BLEZ
5612       {
5613         emit_cmpimm(s1l,1);
5614         if(invert){
5615           nottaken=(int)out;
5616           emit_jge(1);
5617         }else{
5618           add_to_linker((int)out,ba[i],internal);
5619           emit_jl(0);
5620         }
5621       }
5622       if(opcode[i]==7) // BGTZ
5623       {
5624         emit_cmpimm(s1l,1);
5625         if(invert){
5626           nottaken=(int)out;
5627           emit_jl(1);
5628         }else{
5629           add_to_linker((int)out,ba[i],internal);
5630           emit_jge(0);
5631         }
5632       }
5633       if(invert) {
5634         if(taken) set_jump_target(taken,(int)out);
5635         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5636         if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5637           if(adj) {
5638             emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5639             add_to_linker((int)out,ba[i],internal);
5640           }else{
5641             emit_addnop(13);
5642             add_to_linker((int)out,ba[i],internal*2);
5643           }
5644           emit_jmp(0);
5645         }else
5646         #endif
5647         {
5648           if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5649           store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5650           load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5651           if(internal)
5652             assem_debug("branch: internal\n");
5653           else
5654             assem_debug("branch: external\n");
5655           if(internal&&is_ds[(ba[i]-start)>>2]) {
5656             ds_assemble_entry(i);
5657           }
5658           else {
5659             add_to_linker((int)out,ba[i],internal);
5660             emit_jmp(0);
5661           }
5662         }
5663         set_jump_target(nottaken,(int)out);
5664       }
5665
5666       if(nottaken1) set_jump_target(nottaken1,(int)out);
5667       if(adj) {
5668         if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5669       }
5670     } // (!unconditional)
5671   } // if(ooo)
5672   else
5673   {
5674     // In-order execution (branch first)
5675     //if(likely[i]) printf("IOL\n");
5676     //else
5677     //printf("IOE\n");
5678     int taken=0,nottaken=0,nottaken1=0;
5679     if(!unconditional&&!nop) {
5680       if(!only32)
5681       {
5682         assert(s1h>=0);
5683         if((opcode[i]&0x2f)==4) // BEQ
5684         {
5685           if(s2h>=0) emit_cmp(s1h,s2h);
5686           else emit_test(s1h,s1h);
5687           nottaken1=(int)out;
5688           emit_jne(2);
5689         }
5690         if((opcode[i]&0x2f)==5) // BNE
5691         {
5692           if(s2h>=0) emit_cmp(s1h,s2h);
5693           else emit_test(s1h,s1h);
5694           taken=(int)out;
5695           emit_jne(1);
5696         }
5697         if((opcode[i]&0x2f)==6) // BLEZ
5698         {
5699           emit_test(s1h,s1h);
5700           taken=(int)out;
5701           emit_js(1);
5702           nottaken1=(int)out;
5703           emit_jne(2);
5704         }
5705         if((opcode[i]&0x2f)==7) // BGTZ
5706         {
5707           emit_test(s1h,s1h);
5708           nottaken1=(int)out;
5709           emit_js(2);
5710           taken=(int)out;
5711           emit_jne(1);
5712         }
5713       } // if(!only32)
5714
5715       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5716       assert(s1l>=0);
5717       if((opcode[i]&0x2f)==4) // BEQ
5718       {
5719         if(s2l>=0) emit_cmp(s1l,s2l);
5720         else emit_test(s1l,s1l);
5721         nottaken=(int)out;
5722         emit_jne(2);
5723       }
5724       if((opcode[i]&0x2f)==5) // BNE
5725       {
5726         if(s2l>=0) emit_cmp(s1l,s2l);
5727         else emit_test(s1l,s1l);
5728         nottaken=(int)out;
5729         emit_jeq(2);
5730       }
5731       if((opcode[i]&0x2f)==6) // BLEZ
5732       {
5733         emit_cmpimm(s1l,1);
5734         nottaken=(int)out;
5735         emit_jge(2);
5736       }
5737       if((opcode[i]&0x2f)==7) // BGTZ
5738       {
5739         emit_cmpimm(s1l,1);
5740         nottaken=(int)out;
5741         emit_jl(2);
5742       }
5743     } // if(!unconditional)
5744     int adj;
5745     uint64_t ds_unneeded=branch_regs[i].u;
5746     uint64_t ds_unneeded_upper=branch_regs[i].uu;
5747     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5748     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5749     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5750     ds_unneeded|=1;
5751     ds_unneeded_upper|=1;
5752     // branch taken
5753     if(!nop) {
5754       if(taken) set_jump_target(taken,(int)out);
5755       assem_debug("1:\n");
5756       wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5757                     ds_unneeded,ds_unneeded_upper);
5758       // load regs
5759       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5760       address_generation(i+1,&branch_regs[i],0);
5761       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5762       ds_assemble(i+1,&branch_regs[i]);
5763       cc=get_reg(branch_regs[i].regmap,CCREG);
5764       if(cc==-1) {
5765         emit_loadreg(CCREG,cc=HOST_CCREG);
5766         // CHECK: Is the following instruction (fall thru) allocated ok?
5767       }
5768       assert(cc==HOST_CCREG);
5769       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5770       do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5771       assem_debug("cycle count (adj)\n");
5772       if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5773       load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5774       if(internal)
5775         assem_debug("branch: internal\n");
5776       else
5777         assem_debug("branch: external\n");
5778       if(internal&&is_ds[(ba[i]-start)>>2]) {
5779         ds_assemble_entry(i);
5780       }
5781       else {
5782         add_to_linker((int)out,ba[i],internal);
5783         emit_jmp(0);
5784       }
5785     }
5786     // branch not taken
5787     cop1_usable=prev_cop1_usable;
5788     if(!unconditional) {
5789       if(nottaken1) set_jump_target(nottaken1,(int)out);
5790       set_jump_target(nottaken,(int)out);
5791       assem_debug("2:\n");
5792       if(!likely[i]) {
5793         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5794                       ds_unneeded,ds_unneeded_upper);
5795         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5796         address_generation(i+1,&branch_regs[i],0);
5797         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5798         ds_assemble(i+1,&branch_regs[i]);
5799       }
5800       cc=get_reg(branch_regs[i].regmap,CCREG);
5801       if(cc==-1&&!likely[i]) {
5802         // Cycle count isn't in a register, temporarily load it then write it out
5803         emit_loadreg(CCREG,HOST_CCREG);
5804         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5805         int jaddr=(int)out;
5806         emit_jns(0);
5807         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5808         emit_storereg(CCREG,HOST_CCREG);
5809       }
5810       else{
5811         cc=get_reg(i_regmap,CCREG);
5812         assert(cc==HOST_CCREG);
5813         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5814         int jaddr=(int)out;
5815         emit_jns(0);
5816         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5817       }
5818     }
5819   }
5820 }
5821
5822 void sjump_assemble(int i,struct regstat *i_regs)
5823 {
5824   signed char *i_regmap=i_regs->regmap;
5825   int cc;
5826   int match;
5827   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5828   assem_debug("smatch=%d\n",match);
5829   int s1h,s1l;
5830   int prev_cop1_usable=cop1_usable;
5831   int unconditional=0,nevertaken=0;
5832   int only32=0;
5833   int invert=0;
5834   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5835   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5836   if(!match) invert=1;
5837   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5838   if(i>(ba[i]-start)>>2) invert=1;
5839   #endif
5840
5841   //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
5842   //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
5843
5844   if(ooo[i]) {
5845     s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5846     s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5847   }
5848   else {
5849     s1l=get_reg(i_regmap,rs1[i]);
5850     s1h=get_reg(i_regmap,rs1[i]|64);
5851   }
5852   if(rs1[i]==0)
5853   {
5854     if(opcode2[i]&1) unconditional=1;
5855     else nevertaken=1;
5856     // These are never taken (r0 is never less than zero)
5857     //assert(opcode2[i]!=0);
5858     //assert(opcode2[i]!=2);
5859     //assert(opcode2[i]!=0x10);
5860     //assert(opcode2[i]!=0x12);
5861   }
5862   else {
5863     only32=(regs[i].was32>>rs1[i])&1;
5864   }
5865
5866   if(ooo[i]) {
5867     // Out of order execution (delay slot first)
5868     //printf("OOOE\n");
5869     address_generation(i+1,i_regs,regs[i].regmap_entry);
5870     ds_assemble(i+1,i_regs);
5871     int adj;
5872     uint64_t bc_unneeded=branch_regs[i].u;
5873     uint64_t bc_unneeded_upper=branch_regs[i].uu;
5874     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5875     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5876     bc_unneeded|=1;
5877     bc_unneeded_upper|=1;
5878     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5879                   bc_unneeded,bc_unneeded_upper);
5880     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5881     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5882     if(rt1[i]==31) {
5883       int rt,return_address;
5884       rt=get_reg(branch_regs[i].regmap,31);
5885       assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5886       if(rt>=0) {
5887         // Save the PC even if the branch is not taken
5888         return_address=start+i*4+8;
5889         emit_movimm(return_address,rt); // PC into link register
5890         #ifdef IMM_PREFETCH
5891         if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5892         #endif
5893       }
5894     }
5895     cc=get_reg(branch_regs[i].regmap,CCREG);
5896     assert(cc==HOST_CCREG);
5897     if(unconditional)
5898       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5899     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5900     assem_debug("cycle count (adj)\n");
5901     if(unconditional) {
5902       do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5903       if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5904         if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5905         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5906         if(internal)
5907           assem_debug("branch: internal\n");
5908         else
5909           assem_debug("branch: external\n");
5910         if(internal&&is_ds[(ba[i]-start)>>2]) {
5911           ds_assemble_entry(i);
5912         }
5913         else {
5914           add_to_linker((int)out,ba[i],internal);
5915           emit_jmp(0);
5916         }
5917         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5918         if(((u_int)out)&7) emit_addnop(0);
5919         #endif
5920       }
5921     }
5922     else if(nevertaken) {
5923       emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5924       int jaddr=(int)out;
5925       emit_jns(0);
5926       add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5927     }
5928     else {
5929       int nottaken=0;
5930       do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5931       if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5932       if(!only32)
5933       {
5934         assert(s1h>=0);
5935         if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5936         {
5937           emit_test(s1h,s1h);
5938           if(invert){
5939             nottaken=(int)out;
5940             emit_jns(1);
5941           }else{
5942             add_to_linker((int)out,ba[i],internal);
5943             emit_js(0);
5944           }
5945         }
5946         if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5947         {
5948           emit_test(s1h,s1h);
5949           if(invert){
5950             nottaken=(int)out;
5951             emit_js(1);
5952           }else{
5953             add_to_linker((int)out,ba[i],internal);
5954             emit_jns(0);
5955           }
5956         }
5957       } // if(!only32)
5958       else
5959       {
5960         assert(s1l>=0);
5961         if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5962         {
5963           emit_test(s1l,s1l);
5964           if(invert){
5965             nottaken=(int)out;
5966             emit_jns(1);
5967           }else{
5968             add_to_linker((int)out,ba[i],internal);
5969             emit_js(0);
5970           }
5971         }
5972         if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5973         {
5974           emit_test(s1l,s1l);
5975           if(invert){
5976             nottaken=(int)out;
5977             emit_js(1);
5978           }else{
5979             add_to_linker((int)out,ba[i],internal);
5980             emit_jns(0);
5981           }
5982         }
5983       } // if(!only32)
5984
5985       if(invert) {
5986         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5987         if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5988           if(adj) {
5989             emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5990             add_to_linker((int)out,ba[i],internal);
5991           }else{
5992             emit_addnop(13);
5993             add_to_linker((int)out,ba[i],internal*2);
5994           }
5995           emit_jmp(0);
5996         }else
5997         #endif
5998         {
5999           if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
6000           store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6001           load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6002           if(internal)
6003             assem_debug("branch: internal\n");
6004           else
6005             assem_debug("branch: external\n");
6006           if(internal&&is_ds[(ba[i]-start)>>2]) {
6007             ds_assemble_entry(i);
6008           }
6009           else {
6010             add_to_linker((int)out,ba[i],internal);
6011             emit_jmp(0);
6012           }
6013         }
6014         set_jump_target(nottaken,(int)out);
6015       }
6016
6017       if(adj) {
6018         if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
6019       }
6020     } // (!unconditional)
6021   } // if(ooo)
6022   else
6023   {
6024     // In-order execution (branch first)
6025     //printf("IOE\n");
6026     int nottaken=0;
6027     if(rt1[i]==31) {
6028       int rt,return_address;
6029       rt=get_reg(branch_regs[i].regmap,31);
6030       if(rt>=0) {
6031         // Save the PC even if the branch is not taken
6032         return_address=start+i*4+8;
6033         emit_movimm(return_address,rt); // PC into link register
6034         #ifdef IMM_PREFETCH
6035         emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
6036         #endif
6037       }
6038     }
6039     if(!unconditional) {
6040       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6041       if(!only32)
6042       {
6043         assert(s1h>=0);
6044         if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
6045         {
6046           emit_test(s1h,s1h);
6047           nottaken=(int)out;
6048           emit_jns(1);
6049         }
6050         if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
6051         {
6052           emit_test(s1h,s1h);
6053           nottaken=(int)out;
6054           emit_js(1);
6055         }
6056       } // if(!only32)
6057       else
6058       {
6059         assert(s1l>=0);
6060         if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
6061         {
6062           emit_test(s1l,s1l);
6063           nottaken=(int)out;
6064           emit_jns(1);
6065         }
6066         if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
6067         {
6068           emit_test(s1l,s1l);
6069           nottaken=(int)out;
6070           emit_js(1);
6071         }
6072       }
6073     } // if(!unconditional)
6074     int adj;
6075     uint64_t ds_unneeded=branch_regs[i].u;
6076     uint64_t ds_unneeded_upper=branch_regs[i].uu;
6077     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6078     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6079     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6080     ds_unneeded|=1;
6081     ds_unneeded_upper|=1;
6082     // branch taken
6083     if(!nevertaken) {
6084       //assem_debug("1:\n");
6085       wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6086                     ds_unneeded,ds_unneeded_upper);
6087       // load regs
6088       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6089       address_generation(i+1,&branch_regs[i],0);
6090       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6091       ds_assemble(i+1,&branch_regs[i]);
6092       cc=get_reg(branch_regs[i].regmap,CCREG);
6093       if(cc==-1) {
6094         emit_loadreg(CCREG,cc=HOST_CCREG);
6095         // CHECK: Is the following instruction (fall thru) allocated ok?
6096       }
6097       assert(cc==HOST_CCREG);
6098       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6099       do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6100       assem_debug("cycle count (adj)\n");
6101       if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6102       load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6103       if(internal)
6104         assem_debug("branch: internal\n");
6105       else
6106         assem_debug("branch: external\n");
6107       if(internal&&is_ds[(ba[i]-start)>>2]) {
6108         ds_assemble_entry(i);
6109       }
6110       else {
6111         add_to_linker((int)out,ba[i],internal);
6112         emit_jmp(0);
6113       }
6114     }
6115     // branch not taken
6116     cop1_usable=prev_cop1_usable;
6117     if(!unconditional) {
6118       set_jump_target(nottaken,(int)out);
6119       assem_debug("1:\n");
6120       if(!likely[i]) {
6121         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6122                       ds_unneeded,ds_unneeded_upper);
6123         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6124         address_generation(i+1,&branch_regs[i],0);
6125         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6126         ds_assemble(i+1,&branch_regs[i]);
6127       }
6128       cc=get_reg(branch_regs[i].regmap,CCREG);
6129       if(cc==-1&&!likely[i]) {
6130         // Cycle count isn't in a register, temporarily load it then write it out
6131         emit_loadreg(CCREG,HOST_CCREG);
6132         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6133         int jaddr=(int)out;
6134         emit_jns(0);
6135         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6136         emit_storereg(CCREG,HOST_CCREG);
6137       }
6138       else{
6139         cc=get_reg(i_regmap,CCREG);
6140         assert(cc==HOST_CCREG);
6141         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6142         int jaddr=(int)out;
6143         emit_jns(0);
6144         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6145       }
6146     }
6147   }
6148 }
6149
6150 void fjump_assemble(int i,struct regstat *i_regs)
6151 {
6152   signed char *i_regmap=i_regs->regmap;
6153   int cc;
6154   int match;
6155   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6156   assem_debug("fmatch=%d\n",match);
6157   int fs,cs;
6158   int eaddr;
6159   int invert=0;
6160   int internal=internal_branch(branch_regs[i].is32,ba[i]);
6161   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
6162   if(!match) invert=1;
6163   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6164   if(i>(ba[i]-start)>>2) invert=1;
6165   #endif
6166
6167   if(ooo[i]) {
6168     fs=get_reg(branch_regs[i].regmap,FSREG);
6169     address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
6170   }
6171   else {
6172     fs=get_reg(i_regmap,FSREG);
6173   }
6174
6175   // Check cop1 unusable
6176   if(!cop1_usable) {
6177     cs=get_reg(i_regmap,CSREG);
6178     assert(cs>=0);
6179     emit_testimm(cs,0x20000000);
6180     eaddr=(int)out;
6181     emit_jeq(0);
6182     add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
6183     cop1_usable=1;
6184   }
6185
6186   if(ooo[i]) {
6187     // Out of order execution (delay slot first)
6188     //printf("OOOE\n");
6189     ds_assemble(i+1,i_regs);
6190     int adj;
6191     uint64_t bc_unneeded=branch_regs[i].u;
6192     uint64_t bc_unneeded_upper=branch_regs[i].uu;
6193     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6194     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
6195     bc_unneeded|=1;
6196     bc_unneeded_upper|=1;
6197     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6198                   bc_unneeded,bc_unneeded_upper);
6199     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
6200     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6201     cc=get_reg(branch_regs[i].regmap,CCREG);
6202     assert(cc==HOST_CCREG);
6203     do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6204     assem_debug("cycle count (adj)\n");
6205     if(1) {
6206       int nottaken=0;
6207       if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6208       if(1) {
6209         assert(fs>=0);
6210         emit_testimm(fs,0x800000);
6211         if(source[i]&0x10000) // BC1T
6212         {
6213           if(invert){
6214             nottaken=(int)out;
6215             emit_jeq(1);
6216           }else{
6217             add_to_linker((int)out,ba[i],internal);
6218             emit_jne(0);
6219           }
6220         }
6221         else // BC1F
6222           if(invert){
6223             nottaken=(int)out;
6224             emit_jne(1);
6225           }else{
6226             add_to_linker((int)out,ba[i],internal);
6227             emit_jeq(0);
6228           }
6229         {
6230         }
6231       } // if(!only32)
6232
6233       if(invert) {
6234         if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
6235         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6236         else if(match) emit_addnop(13);
6237         #endif
6238         store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6239         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6240         if(internal)
6241           assem_debug("branch: internal\n");
6242         else
6243           assem_debug("branch: external\n");
6244         if(internal&&is_ds[(ba[i]-start)>>2]) {
6245           ds_assemble_entry(i);
6246         }
6247         else {
6248           add_to_linker((int)out,ba[i],internal);
6249           emit_jmp(0);
6250         }
6251         set_jump_target(nottaken,(int)out);
6252       }
6253
6254       if(adj) {
6255         if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
6256       }
6257     } // (!unconditional)
6258   } // if(ooo)
6259   else
6260   {
6261     // In-order execution (branch first)
6262     //printf("IOE\n");
6263     int nottaken=0;
6264     if(1) {
6265       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6266       if(1) {
6267         assert(fs>=0);
6268         emit_testimm(fs,0x800000);
6269         if(source[i]&0x10000) // BC1T
6270         {
6271           nottaken=(int)out;
6272           emit_jeq(1);
6273         }
6274         else // BC1F
6275         {
6276           nottaken=(int)out;
6277           emit_jne(1);
6278         }
6279       }
6280     } // if(!unconditional)
6281     int adj;
6282     uint64_t ds_unneeded=branch_regs[i].u;
6283     uint64_t ds_unneeded_upper=branch_regs[i].uu;
6284     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6285     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6286     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6287     ds_unneeded|=1;
6288     ds_unneeded_upper|=1;
6289     // branch taken
6290     //assem_debug("1:\n");
6291     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6292                   ds_unneeded,ds_unneeded_upper);
6293     // load regs
6294     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6295     address_generation(i+1,&branch_regs[i],0);
6296     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6297     ds_assemble(i+1,&branch_regs[i]);
6298     cc=get_reg(branch_regs[i].regmap,CCREG);
6299     if(cc==-1) {
6300       emit_loadreg(CCREG,cc=HOST_CCREG);
6301       // CHECK: Is the following instruction (fall thru) allocated ok?
6302     }
6303     assert(cc==HOST_CCREG);
6304     store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6305     do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6306     assem_debug("cycle count (adj)\n");
6307     if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6308     load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6309     if(internal)
6310       assem_debug("branch: internal\n");
6311     else
6312       assem_debug("branch: external\n");
6313     if(internal&&is_ds[(ba[i]-start)>>2]) {
6314       ds_assemble_entry(i);
6315     }
6316     else {
6317       add_to_linker((int)out,ba[i],internal);
6318       emit_jmp(0);
6319     }
6320
6321     // branch not taken
6322     if(1) { // <- FIXME (don't need this)
6323       set_jump_target(nottaken,(int)out);
6324       assem_debug("1:\n");
6325       if(!likely[i]) {
6326         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6327                       ds_unneeded,ds_unneeded_upper);
6328         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6329         address_generation(i+1,&branch_regs[i],0);
6330         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6331         ds_assemble(i+1,&branch_regs[i]);
6332       }
6333       cc=get_reg(branch_regs[i].regmap,CCREG);
6334       if(cc==-1&&!likely[i]) {
6335         // Cycle count isn't in a register, temporarily load it then write it out
6336         emit_loadreg(CCREG,HOST_CCREG);
6337         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6338         int jaddr=(int)out;
6339         emit_jns(0);
6340         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6341         emit_storereg(CCREG,HOST_CCREG);
6342       }
6343       else{
6344         cc=get_reg(i_regmap,CCREG);
6345         assert(cc==HOST_CCREG);
6346         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6347         int jaddr=(int)out;
6348         emit_jns(0);
6349         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6350       }
6351     }
6352   }
6353 }
6354
6355 static void pagespan_assemble(int i,struct regstat *i_regs)
6356 {
6357   int s1l=get_reg(i_regs->regmap,rs1[i]);
6358   int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6359   int s2l=get_reg(i_regs->regmap,rs2[i]);
6360   int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6361   void *nt_branch=NULL;
6362   int taken=0;
6363   int nottaken=0;
6364   int unconditional=0;
6365   if(rs1[i]==0)
6366   {
6367     s1l=s2l;s1h=s2h;
6368     s2l=s2h=-1;
6369   }
6370   else if(rs2[i]==0)
6371   {
6372     s2l=s2h=-1;
6373   }
6374   if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6375     s1h=s2h=-1;
6376   }
6377   int hr=0;
6378   int addr,alt,ntaddr;
6379   if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6380   else {
6381     while(hr<HOST_REGS)
6382     {
6383       if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6384          (i_regs->regmap[hr]&63)!=rs1[i] &&
6385          (i_regs->regmap[hr]&63)!=rs2[i] )
6386       {
6387         addr=hr++;break;
6388       }
6389       hr++;
6390     }
6391   }
6392   while(hr<HOST_REGS)
6393   {
6394     if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6395        (i_regs->regmap[hr]&63)!=rs1[i] &&
6396        (i_regs->regmap[hr]&63)!=rs2[i] )
6397     {
6398       alt=hr++;break;
6399     }
6400     hr++;
6401   }
6402   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6403   {
6404     while(hr<HOST_REGS)
6405     {
6406       if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6407          (i_regs->regmap[hr]&63)!=rs1[i] &&
6408          (i_regs->regmap[hr]&63)!=rs2[i] )
6409       {
6410         ntaddr=hr;break;
6411       }
6412       hr++;
6413     }
6414   }
6415   assert(hr<HOST_REGS);
6416   if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6417     load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6418   }
6419   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6420   if(opcode[i]==2) // J
6421   {
6422     unconditional=1;
6423   }
6424   if(opcode[i]==3) // JAL
6425   {
6426     // TODO: mini_ht
6427     int rt=get_reg(i_regs->regmap,31);
6428     emit_movimm(start+i*4+8,rt);
6429     unconditional=1;
6430   }
6431   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6432   {
6433     emit_mov(s1l,addr);
6434     if(opcode2[i]==9) // JALR
6435     {
6436       int rt=get_reg(i_regs->regmap,rt1[i]);
6437       emit_movimm(start+i*4+8,rt);
6438     }
6439   }
6440   if((opcode[i]&0x3f)==4) // BEQ
6441   {
6442     if(rs1[i]==rs2[i])
6443     {
6444       unconditional=1;
6445     }
6446     else
6447     #ifdef HAVE_CMOV_IMM
6448     if(s1h<0) {
6449       if(s2l>=0) emit_cmp(s1l,s2l);
6450       else emit_test(s1l,s1l);
6451       emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6452     }
6453     else
6454     #endif
6455     {
6456       assert(s1l>=0);
6457       emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6458       if(s1h>=0) {
6459         if(s2h>=0) emit_cmp(s1h,s2h);
6460         else emit_test(s1h,s1h);
6461         emit_cmovne_reg(alt,addr);
6462       }
6463       if(s2l>=0) emit_cmp(s1l,s2l);
6464       else emit_test(s1l,s1l);
6465       emit_cmovne_reg(alt,addr);
6466     }
6467   }
6468   if((opcode[i]&0x3f)==5) // BNE
6469   {
6470     #ifdef HAVE_CMOV_IMM
6471     if(s1h<0) {
6472       if(s2l>=0) emit_cmp(s1l,s2l);
6473       else emit_test(s1l,s1l);
6474       emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6475     }
6476     else
6477     #endif
6478     {
6479       assert(s1l>=0);
6480       emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6481       if(s1h>=0) {
6482         if(s2h>=0) emit_cmp(s1h,s2h);
6483         else emit_test(s1h,s1h);
6484         emit_cmovne_reg(alt,addr);
6485       }
6486       if(s2l>=0) emit_cmp(s1l,s2l);
6487       else emit_test(s1l,s1l);
6488       emit_cmovne_reg(alt,addr);
6489     }
6490   }
6491   if((opcode[i]&0x3f)==0x14) // BEQL
6492   {
6493     if(s1h>=0) {
6494       if(s2h>=0) emit_cmp(s1h,s2h);
6495       else emit_test(s1h,s1h);
6496       nottaken=(int)out;
6497       emit_jne(0);
6498     }
6499     if(s2l>=0) emit_cmp(s1l,s2l);
6500     else emit_test(s1l,s1l);
6501     if(nottaken) set_jump_target(nottaken,(int)out);
6502     nottaken=(int)out;
6503     emit_jne(0);
6504   }
6505   if((opcode[i]&0x3f)==0x15) // BNEL
6506   {
6507     if(s1h>=0) {
6508       if(s2h>=0) emit_cmp(s1h,s2h);
6509       else emit_test(s1h,s1h);
6510       taken=(int)out;
6511       emit_jne(0);
6512     }
6513     if(s2l>=0) emit_cmp(s1l,s2l);
6514     else emit_test(s1l,s1l);
6515     nottaken=(int)out;
6516     emit_jeq(0);
6517     if(taken) set_jump_target(taken,(int)out);
6518   }
6519   if((opcode[i]&0x3f)==6) // BLEZ
6520   {
6521     emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6522     emit_cmpimm(s1l,1);
6523     if(s1h>=0) emit_mov(addr,ntaddr);
6524     emit_cmovl_reg(alt,addr);
6525     if(s1h>=0) {
6526       emit_test(s1h,s1h);
6527       emit_cmovne_reg(ntaddr,addr);
6528       emit_cmovs_reg(alt,addr);
6529     }
6530   }
6531   if((opcode[i]&0x3f)==7) // BGTZ
6532   {
6533     emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6534     emit_cmpimm(s1l,1);
6535     if(s1h>=0) emit_mov(addr,alt);
6536     emit_cmovl_reg(ntaddr,addr);
6537     if(s1h>=0) {
6538       emit_test(s1h,s1h);
6539       emit_cmovne_reg(alt,addr);
6540       emit_cmovs_reg(ntaddr,addr);
6541     }
6542   }
6543   if((opcode[i]&0x3f)==0x16) // BLEZL
6544   {
6545     assert((opcode[i]&0x3f)!=0x16);
6546   }
6547   if((opcode[i]&0x3f)==0x17) // BGTZL
6548   {
6549     assert((opcode[i]&0x3f)!=0x17);
6550   }
6551   assert(opcode[i]!=1); // BLTZ/BGEZ
6552
6553   //FIXME: Check CSREG
6554   if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6555     if((source[i]&0x30000)==0) // BC1F
6556     {
6557       emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6558       emit_testimm(s1l,0x800000);
6559       emit_cmovne_reg(alt,addr);
6560     }
6561     if((source[i]&0x30000)==0x10000) // BC1T
6562     {
6563       emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6564       emit_testimm(s1l,0x800000);
6565       emit_cmovne_reg(alt,addr);
6566     }
6567     if((source[i]&0x30000)==0x20000) // BC1FL
6568     {
6569       emit_testimm(s1l,0x800000);
6570       nottaken=(int)out;
6571       emit_jne(0);
6572     }
6573     if((source[i]&0x30000)==0x30000) // BC1TL
6574     {
6575       emit_testimm(s1l,0x800000);
6576       nottaken=(int)out;
6577       emit_jeq(0);
6578     }
6579   }
6580
6581   assert(i_regs->regmap[HOST_CCREG]==CCREG);
6582   wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6583   if(likely[i]||unconditional)
6584   {
6585     emit_movimm(ba[i],HOST_BTREG);
6586   }
6587   else if(addr!=HOST_BTREG)
6588   {
6589     emit_mov(addr,HOST_BTREG);
6590   }
6591   void *branch_addr=out;
6592   emit_jmp(0);
6593   int target_addr=start+i*4+5;
6594   void *stub=out;
6595   void *compiled_target_addr=check_addr(target_addr);
6596   emit_extjump_ds((int)branch_addr,target_addr);
6597   if(compiled_target_addr) {
6598     set_jump_target((int)branch_addr,(int)compiled_target_addr);
6599     add_link(target_addr,stub);
6600   }
6601   else set_jump_target((int)branch_addr,(int)stub);
6602   if(likely[i]) {
6603     // Not-taken path
6604     set_jump_target((int)nottaken,(int)out);
6605     wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6606     void *branch_addr=out;
6607     emit_jmp(0);
6608     int target_addr=start+i*4+8;
6609     void *stub=out;
6610     void *compiled_target_addr=check_addr(target_addr);
6611     emit_extjump_ds((int)branch_addr,target_addr);
6612     if(compiled_target_addr) {
6613       set_jump_target((int)branch_addr,(int)compiled_target_addr);
6614       add_link(target_addr,stub);
6615     }
6616     else set_jump_target((int)branch_addr,(int)stub);
6617   }
6618 }
6619
6620 // Assemble the delay slot for the above
6621 static void pagespan_ds()
6622 {
6623   assem_debug("initial delay slot:\n");
6624   u_int vaddr=start+1;
6625   u_int page=get_page(vaddr);
6626   u_int vpage=get_vpage(vaddr);
6627   ll_add(jump_dirty+vpage,vaddr,(void *)out);
6628   do_dirty_stub_ds();
6629   ll_add(jump_in+page,vaddr,(void *)out);
6630   assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6631   if(regs[0].regmap[HOST_CCREG]!=CCREG)
6632     wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6633   if(regs[0].regmap[HOST_BTREG]!=BTREG)
6634     emit_writeword(HOST_BTREG,(int)&branch_target);
6635   load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6636   address_generation(0,&regs[0],regs[0].regmap_entry);
6637   if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
6638     load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6639   cop1_usable=0;
6640   is_delayslot=0;
6641   switch(itype[0]) {
6642     case ALU:
6643       alu_assemble(0,&regs[0]);break;
6644     case IMM16:
6645       imm16_assemble(0,&regs[0]);break;
6646     case SHIFT:
6647       shift_assemble(0,&regs[0]);break;
6648     case SHIFTIMM:
6649       shiftimm_assemble(0,&regs[0]);break;
6650     case LOAD:
6651       load_assemble(0,&regs[0]);break;
6652     case LOADLR:
6653       loadlr_assemble(0,&regs[0]);break;
6654     case STORE:
6655       store_assemble(0,&regs[0]);break;
6656     case STORELR:
6657       storelr_assemble(0,&regs[0]);break;
6658     case COP0:
6659       cop0_assemble(0,&regs[0]);break;
6660     case COP1:
6661       cop1_assemble(0,&regs[0]);break;
6662     case C1LS:
6663       c1ls_assemble(0,&regs[0]);break;
6664     case COP2:
6665       cop2_assemble(0,&regs[0]);break;
6666     case C2LS:
6667       c2ls_assemble(0,&regs[0]);break;
6668     case C2OP:
6669       c2op_assemble(0,&regs[0]);break;
6670     case FCONV:
6671       fconv_assemble(0,&regs[0]);break;
6672     case FLOAT:
6673       float_assemble(0,&regs[0]);break;
6674     case FCOMP:
6675       fcomp_assemble(0,&regs[0]);break;
6676     case MULTDIV:
6677       multdiv_assemble(0,&regs[0]);break;
6678     case MOV:
6679       mov_assemble(0,&regs[0]);break;
6680     case SYSCALL:
6681     case HLECALL:
6682     case INTCALL:
6683     case SPAN:
6684     case UJUMP:
6685     case RJUMP:
6686     case CJUMP:
6687     case SJUMP:
6688     case FJUMP:
6689       printf("Jump in the delay slot.  This is probably a bug.\n");
6690   }
6691   int btaddr=get_reg(regs[0].regmap,BTREG);
6692   if(btaddr<0) {
6693     btaddr=get_reg(regs[0].regmap,-1);
6694     emit_readword((int)&branch_target,btaddr);
6695   }
6696   assert(btaddr!=HOST_CCREG);
6697   if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6698 #ifdef HOST_IMM8
6699   emit_movimm(start+4,HOST_TEMPREG);
6700   emit_cmp(btaddr,HOST_TEMPREG);
6701 #else
6702   emit_cmpimm(btaddr,start+4);
6703 #endif
6704   int branch=(int)out;
6705   emit_jeq(0);
6706   store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6707   emit_jmp(jump_vaddr_reg[btaddr]);
6708   set_jump_target(branch,(int)out);
6709   store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6710   load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6711 }
6712
6713 // Basic liveness analysis for MIPS registers
6714 void unneeded_registers(int istart,int iend,int r)
6715 {
6716   int i;
6717   uint64_t u,uu,gte_u,b,bu,gte_bu;
6718   uint64_t temp_u,temp_uu,temp_gte_u;
6719   uint64_t tdep;
6720   if(iend==slen-1) {
6721     u=1;uu=1;
6722   }else{
6723     u=unneeded_reg[iend+1];
6724     uu=unneeded_reg_upper[iend+1];
6725     u=1;uu=1;
6726   }
6727   gte_u=temp_gte_u=0;
6728
6729   for (i=iend;i>=istart;i--)
6730   {
6731     //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6732     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6733     {
6734       // If subroutine call, flag return address as a possible branch target
6735       if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6736
6737       if(ba[i]<start || ba[i]>=(start+slen*4))
6738       {
6739         // Branch out of this block, flush all regs
6740         u=1;
6741         uu=1;
6742         gte_u=0;
6743         /* Hexagon hack
6744         if(itype[i]==UJUMP&&rt1[i]==31)
6745         {
6746           uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6747         }
6748         if(itype[i]==RJUMP&&rs1[i]==31)
6749         {
6750           uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6751         }
6752         if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
6753           if(itype[i]==UJUMP&&rt1[i]==31)
6754           {
6755             //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6756             uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6757           }
6758           if(itype[i]==RJUMP&&rs1[i]==31)
6759           {
6760             //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6761             uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6762           }
6763         }*/
6764         branch_unneeded_reg[i]=u;
6765         branch_unneeded_reg_upper[i]=uu;
6766         // Merge in delay slot
6767         tdep=(~uu>>rt1[i+1])&1;
6768         u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6769         uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6770         u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6771         uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6772         uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6773         u|=1;uu|=1;
6774         gte_u|=gte_rt[i+1];
6775         gte_u&=~gte_rs[i+1];
6776         // If branch is "likely" (and conditional)
6777         // then we skip the delay slot on the fall-thru path
6778         if(likely[i]) {
6779           if(i<slen-1) {
6780             u&=unneeded_reg[i+2];
6781             uu&=unneeded_reg_upper[i+2];
6782             gte_u&=gte_unneeded[i+2];
6783           }
6784           else
6785           {
6786             u=1;
6787             uu=1;
6788             gte_u=0;
6789           }
6790         }
6791       }
6792       else
6793       {
6794         // Internal branch, flag target
6795         bt[(ba[i]-start)>>2]=1;
6796         if(ba[i]<=start+i*4) {
6797           // Backward branch
6798           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6799           {
6800             // Unconditional branch
6801             temp_u=1;temp_uu=1;
6802             temp_gte_u=0;
6803           } else {
6804             // Conditional branch (not taken case)
6805             temp_u=unneeded_reg[i+2];
6806             temp_uu=unneeded_reg_upper[i+2];
6807             temp_gte_u&=gte_unneeded[i+2];
6808           }
6809           // Merge in delay slot
6810           tdep=(~temp_uu>>rt1[i+1])&1;
6811           temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6812           temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6813           temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6814           temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6815           temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6816           temp_u|=1;temp_uu|=1;
6817           temp_gte_u|=gte_rt[i+1];
6818           temp_gte_u&=~gte_rs[i+1];
6819           // If branch is "likely" (and conditional)
6820           // then we skip the delay slot on the fall-thru path
6821           if(likely[i]) {
6822             if(i<slen-1) {
6823               temp_u&=unneeded_reg[i+2];
6824               temp_uu&=unneeded_reg_upper[i+2];
6825               temp_gte_u&=gte_unneeded[i+2];
6826             }
6827             else
6828             {
6829               temp_u=1;
6830               temp_uu=1;
6831               temp_gte_u=0;
6832             }
6833           }
6834           tdep=(~temp_uu>>rt1[i])&1;
6835           temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6836           temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6837           temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6838           temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6839           temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6840           temp_u|=1;temp_uu|=1;
6841           temp_gte_u|=gte_rt[i];
6842           temp_gte_u&=~gte_rs[i];
6843           unneeded_reg[i]=temp_u;
6844           unneeded_reg_upper[i]=temp_uu;
6845           gte_unneeded[i]=temp_gte_u;
6846           // Only go three levels deep.  This recursion can take an
6847           // excessive amount of time if there are a lot of nested loops.
6848           if(r<2) {
6849             unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6850           }else{
6851             unneeded_reg[(ba[i]-start)>>2]=1;
6852             unneeded_reg_upper[(ba[i]-start)>>2]=1;
6853             gte_unneeded[(ba[i]-start)>>2]=0;
6854           }
6855         } /*else*/ if(1) {
6856           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6857           {
6858             // Unconditional branch
6859             u=unneeded_reg[(ba[i]-start)>>2];
6860             uu=unneeded_reg_upper[(ba[i]-start)>>2];
6861             gte_u=gte_unneeded[(ba[i]-start)>>2];
6862             branch_unneeded_reg[i]=u;
6863             branch_unneeded_reg_upper[i]=uu;
6864         //u=1;
6865         //uu=1;
6866         //branch_unneeded_reg[i]=u;
6867         //branch_unneeded_reg_upper[i]=uu;
6868             // Merge in delay slot
6869             tdep=(~uu>>rt1[i+1])&1;
6870             u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6871             uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6872             u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6873             uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6874             uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6875             u|=1;uu|=1;
6876             gte_u|=gte_rt[i+1];
6877             gte_u&=~gte_rs[i+1];
6878           } else {
6879             // Conditional branch
6880             b=unneeded_reg[(ba[i]-start)>>2];
6881             bu=unneeded_reg_upper[(ba[i]-start)>>2];
6882             gte_bu=gte_unneeded[(ba[i]-start)>>2];
6883             branch_unneeded_reg[i]=b;
6884             branch_unneeded_reg_upper[i]=bu;
6885         //b=1;
6886         //bu=1;
6887         //branch_unneeded_reg[i]=b;
6888         //branch_unneeded_reg_upper[i]=bu;
6889             // Branch delay slot
6890             tdep=(~uu>>rt1[i+1])&1;
6891             b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6892             bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6893             b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6894             bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6895             bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6896             b|=1;bu|=1;
6897             gte_bu|=gte_rt[i+1];
6898             gte_bu&=~gte_rs[i+1];
6899             // If branch is "likely" then we skip the
6900             // delay slot on the fall-thru path
6901             if(likely[i]) {
6902               u=b;
6903               uu=bu;
6904               gte_u=gte_bu;
6905               if(i<slen-1) {
6906                 u&=unneeded_reg[i+2];
6907                 uu&=unneeded_reg_upper[i+2];
6908                 gte_u&=gte_unneeded[i+2];
6909         //u=1;
6910         //uu=1;
6911               }
6912             } else {
6913               u&=b;
6914               uu&=bu;
6915               gte_u&=gte_bu;
6916         //u=1;
6917         //uu=1;
6918             }
6919             if(i<slen-1) {
6920               branch_unneeded_reg[i]&=unneeded_reg[i+2];
6921               branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6922         //branch_unneeded_reg[i]=1;
6923         //branch_unneeded_reg_upper[i]=1;
6924             } else {
6925               branch_unneeded_reg[i]=1;
6926               branch_unneeded_reg_upper[i]=1;
6927             }
6928           }
6929         }
6930       }
6931     }
6932     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
6933     {
6934       // SYSCALL instruction (software interrupt)
6935       u=1;
6936       uu=1;
6937     }
6938     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6939     {
6940       // ERET instruction (return from interrupt)
6941       u=1;
6942       uu=1;
6943     }
6944     //u=uu=1; // DEBUG
6945     tdep=(~uu>>rt1[i])&1;
6946     // Written registers are unneeded
6947     u|=1LL<<rt1[i];
6948     u|=1LL<<rt2[i];
6949     uu|=1LL<<rt1[i];
6950     uu|=1LL<<rt2[i];
6951     gte_u|=gte_rt[i];
6952     // Accessed registers are needed
6953     u&=~(1LL<<rs1[i]);
6954     u&=~(1LL<<rs2[i]);
6955     uu&=~(1LL<<us1[i]);
6956     uu&=~(1LL<<us2[i]);
6957     gte_u&=~gte_rs[i];
6958     // Source-target dependencies
6959     uu&=~(tdep<<dep1[i]);
6960     uu&=~(tdep<<dep2[i]);
6961     // R0 is always unneeded
6962     u|=1;uu|=1;
6963     // Save it
6964     unneeded_reg[i]=u;
6965     unneeded_reg_upper[i]=uu;
6966     gte_unneeded[i]=gte_u;
6967     /*
6968     printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6969     printf("U:");
6970     int r;
6971     for(r=1;r<=CCREG;r++) {
6972       if((unneeded_reg[i]>>r)&1) {
6973         if(r==HIREG) printf(" HI");
6974         else if(r==LOREG) printf(" LO");
6975         else printf(" r%d",r);
6976       }
6977     }
6978     printf(" UU:");
6979     for(r=1;r<=CCREG;r++) {
6980       if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
6981         if(r==HIREG) printf(" HI");
6982         else if(r==LOREG) printf(" LO");
6983         else printf(" r%d",r);
6984       }
6985     }
6986     printf("\n");*/
6987   }
6988 #ifdef FORCE32
6989   for (i=iend;i>=istart;i--)
6990   {
6991     unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
6992   }
6993 #endif
6994 }
6995
6996 // Identify registers which are likely to contain 32-bit values
6997 // This is used to predict whether any branches will jump to a
6998 // location with 64-bit values in registers.
6999 static void provisional_32bit()
7000 {
7001   int i,j;
7002   uint64_t is32=1;
7003   uint64_t lastbranch=1;
7004
7005   for(i=0;i<slen;i++)
7006   {
7007     if(i>0) {
7008       if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
7009         if(i>1) is32=lastbranch;
7010         else is32=1;
7011       }
7012     }
7013     if(i>1)
7014     {
7015       if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
7016         if(likely[i-2]) {
7017           if(i>2) is32=lastbranch;
7018           else is32=1;
7019         }
7020       }
7021       if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
7022       {
7023         if(rs1[i-2]==0||rs2[i-2]==0)
7024         {
7025           if(rs1[i-2]) {
7026             is32|=1LL<<rs1[i-2];
7027           }
7028           if(rs2[i-2]) {
7029             is32|=1LL<<rs2[i-2];
7030           }
7031         }
7032       }
7033     }
7034     // If something jumps here with 64-bit values
7035     // then promote those registers to 64 bits
7036     if(bt[i])
7037     {
7038       uint64_t temp_is32=is32;
7039       for(j=i-1;j>=0;j--)
7040       {
7041         if(ba[j]==start+i*4)
7042           //temp_is32&=branch_regs[j].is32;
7043           temp_is32&=p32[j];
7044       }
7045       for(j=i;j<slen;j++)
7046       {
7047         if(ba[j]==start+i*4)
7048           temp_is32=1;
7049       }
7050       is32=temp_is32;
7051     }
7052     int type=itype[i];
7053     int op=opcode[i];
7054     int op2=opcode2[i];
7055     int rt=rt1[i];
7056     int s1=rs1[i];
7057     int s2=rs2[i];
7058     if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
7059       // Branches don't write registers, consider the delay slot instead.
7060       type=itype[i+1];
7061       op=opcode[i+1];
7062       op2=opcode2[i+1];
7063       rt=rt1[i+1];
7064       s1=rs1[i+1];
7065       s2=rs2[i+1];
7066       lastbranch=is32;
7067     }
7068     switch(type) {
7069       case LOAD:
7070         if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
7071            opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
7072           is32&=~(1LL<<rt);
7073         else
7074           is32|=1LL<<rt;
7075         break;
7076       case STORE:
7077       case STORELR:
7078         break;
7079       case LOADLR:
7080         if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
7081         if(op==0x22) is32|=1LL<<rt; // LWL
7082         break;
7083       case IMM16:
7084         if (op==0x08||op==0x09|| // ADDI/ADDIU
7085             op==0x0a||op==0x0b|| // SLTI/SLTIU
7086             op==0x0c|| // ANDI
7087             op==0x0f)  // LUI
7088         {
7089           is32|=1LL<<rt;
7090         }
7091         if(op==0x18||op==0x19) { // DADDI/DADDIU
7092           is32&=~(1LL<<rt);
7093           //if(imm[i]==0)
7094           //  is32|=((is32>>s1)&1LL)<<rt;
7095         }
7096         if(op==0x0d||op==0x0e) { // ORI/XORI
7097           uint64_t sr=((is32>>s1)&1LL);
7098           is32&=~(1LL<<rt);
7099           is32|=sr<<rt;
7100         }
7101         break;
7102       case UJUMP:
7103         break;
7104       case RJUMP:
7105         break;
7106       case CJUMP:
7107         break;
7108       case SJUMP:
7109         break;
7110       case FJUMP:
7111         break;
7112       case ALU:
7113         if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
7114           is32|=1LL<<rt;
7115         }
7116         if(op2==0x2a||op2==0x2b) { // SLT/SLTU
7117           is32|=1LL<<rt;
7118         }
7119         else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
7120           uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
7121           is32&=~(1LL<<rt);
7122           is32|=sr<<rt;
7123         }
7124         else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
7125           if(s1==0&&s2==0) {
7126             is32|=1LL<<rt;
7127           }
7128           else if(s2==0) {
7129             uint64_t sr=((is32>>s1)&1LL);
7130             is32&=~(1LL<<rt);
7131             is32|=sr<<rt;
7132           }
7133           else if(s1==0) {
7134             uint64_t sr=((is32>>s2)&1LL);
7135             is32&=~(1LL<<rt);
7136             is32|=sr<<rt;
7137           }
7138           else {
7139             is32&=~(1LL<<rt);
7140           }
7141         }
7142         else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
7143           if(s1==0&&s2==0) {
7144             is32|=1LL<<rt;
7145           }
7146           else if(s2==0) {
7147             uint64_t sr=((is32>>s1)&1LL);
7148             is32&=~(1LL<<rt);
7149             is32|=sr<<rt;
7150           }
7151           else {
7152             is32&=~(1LL<<rt);
7153           }
7154         }
7155         break;
7156       case MULTDIV:
7157         if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
7158           is32&=~((1LL<<HIREG)|(1LL<<LOREG));
7159         }
7160         else {
7161           is32|=(1LL<<HIREG)|(1LL<<LOREG);
7162         }
7163         break;
7164       case MOV:
7165         {
7166           uint64_t sr=((is32>>s1)&1LL);
7167           is32&=~(1LL<<rt);
7168           is32|=sr<<rt;
7169         }
7170         break;
7171       case SHIFT:
7172         if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
7173         else is32|=1LL<<rt; // SLLV/SRLV/SRAV
7174         break;
7175       case SHIFTIMM:
7176         is32|=1LL<<rt;
7177         // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
7178         if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
7179         break;
7180       case COP0:
7181         if(op2==0) is32|=1LL<<rt; // MFC0
7182         break;
7183       case COP1:
7184       case COP2:
7185         if(op2==0) is32|=1LL<<rt; // MFC1
7186         if(op2==1) is32&=~(1LL<<rt); // DMFC1
7187         if(op2==2) is32|=1LL<<rt; // CFC1
7188         break;
7189       case C1LS:
7190       case C2LS:
7191         break;
7192       case FLOAT:
7193       case FCONV:
7194         break;
7195       case FCOMP:
7196         break;
7197       case C2OP:
7198       case SYSCALL:
7199       case HLECALL:
7200         break;
7201       default:
7202         break;
7203     }
7204     is32|=1;
7205     p32[i]=is32;
7206
7207     if(i>0)
7208     {
7209       if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
7210       {
7211         if(rt1[i-1]==31) // JAL/JALR
7212         {
7213           // Subroutine call will return here, don't alloc any registers
7214           is32=1;
7215         }
7216         else if(i+1<slen)
7217         {
7218           // Internal branch will jump here, match registers to caller
7219           is32=0x3FFFFFFFFLL;
7220         }
7221       }
7222     }
7223   }
7224 }
7225
7226 // Identify registers which may be assumed to contain 32-bit values
7227 // and where optimizations will rely on this.
7228 // This is used to determine whether backward branches can safely
7229 // jump to a location with 64-bit values in registers.
7230 static void provisional_r32()
7231 {
7232   u_int r32=0;
7233   int i;
7234
7235   for (i=slen-1;i>=0;i--)
7236   {
7237     int hr;
7238     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7239     {
7240       if(ba[i]<start || ba[i]>=(start+slen*4))
7241       {
7242         // Branch out of this block, don't need anything
7243         r32=0;
7244       }
7245       else
7246       {
7247         // Internal branch
7248         // Need whatever matches the target
7249         // (and doesn't get overwritten by the delay slot instruction)
7250         r32=0;
7251         int t=(ba[i]-start)>>2;
7252         if(ba[i]>start+i*4) {
7253           // Forward branch
7254           //if(!(requires_32bit[t]&~regs[i].was32))
7255           //  r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7256           if(!(pr32[t]&~regs[i].was32))
7257             r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7258         }else{
7259           // Backward branch
7260           if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
7261             r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7262         }
7263       }
7264       // Conditional branch may need registers for following instructions
7265       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7266       {
7267         if(i<slen-2) {
7268           //r32|=requires_32bit[i+2];
7269           r32|=pr32[i+2];
7270           r32&=regs[i].was32;
7271           // Mark this address as a branch target since it may be called
7272           // upon return from interrupt
7273           //bt[i+2]=1;
7274         }
7275       }
7276       // Merge in delay slot
7277       if(!likely[i]) {
7278         // These are overwritten unless the branch is "likely"
7279         // and the delay slot is nullified if not taken
7280         r32&=~(1LL<<rt1[i+1]);
7281         r32&=~(1LL<<rt2[i+1]);
7282       }
7283       // Assume these are needed (delay slot)
7284       if(us1[i+1]>0)
7285       {
7286         if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7287       }
7288       if(us2[i+1]>0)
7289       {
7290         if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7291       }
7292       if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7293       {
7294         if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7295       }
7296       if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7297       {
7298         if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7299       }
7300     }
7301     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7302     {
7303       // SYSCALL instruction (software interrupt)
7304       r32=0;
7305     }
7306     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7307     {
7308       // ERET instruction (return from interrupt)
7309       r32=0;
7310     }
7311     // Check 32 bits
7312     r32&=~(1LL<<rt1[i]);
7313     r32&=~(1LL<<rt2[i]);
7314     if(us1[i]>0)
7315     {
7316       if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7317     }
7318     if(us2[i]>0)
7319     {
7320       if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7321     }
7322     if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7323     {
7324       if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7325     }
7326     if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7327     {
7328       if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7329     }
7330     //requires_32bit[i]=r32;
7331     pr32[i]=r32;
7332
7333     // Dirty registers which are 32-bit, require 32-bit input
7334     // as they will be written as 32-bit values
7335     for(hr=0;hr<HOST_REGS;hr++)
7336     {
7337       if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
7338         if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7339           if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7340           pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7341           //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7342         }
7343       }
7344     }
7345   }
7346 }
7347
7348 // Write back dirty registers as soon as we will no longer modify them,
7349 // so that we don't end up with lots of writes at the branches.
7350 void clean_registers(int istart,int iend,int wr)
7351 {
7352   int i;
7353   int r;
7354   u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7355   u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7356   if(iend==slen-1) {
7357     will_dirty_i=will_dirty_next=0;
7358     wont_dirty_i=wont_dirty_next=0;
7359   }else{
7360     will_dirty_i=will_dirty_next=will_dirty[iend+1];
7361     wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7362   }
7363   for (i=iend;i>=istart;i--)
7364   {
7365     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7366     {
7367       if(ba[i]<start || ba[i]>=(start+slen*4))
7368       {
7369         // Branch out of this block, flush all regs
7370         if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7371         {
7372           // Unconditional branch
7373           will_dirty_i=0;
7374           wont_dirty_i=0;
7375           // Merge in delay slot (will dirty)
7376           for(r=0;r<HOST_REGS;r++) {
7377             if(r!=EXCLUDE_REG) {
7378               if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7379               if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7380               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7381               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7382               if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7383               if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7384               if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7385               if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7386               if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7387               if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7388               if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7389               if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7390               if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7391               if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7392             }
7393           }
7394         }
7395         else
7396         {
7397           // Conditional branch
7398           will_dirty_i=0;
7399           wont_dirty_i=wont_dirty_next;
7400           // Merge in delay slot (will dirty)
7401           for(r=0;r<HOST_REGS;r++) {
7402             if(r!=EXCLUDE_REG) {
7403               if(!likely[i]) {
7404                 // Might not dirty if likely branch is not taken
7405                 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7406                 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7407                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7408                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7409                 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7410                 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7411                 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7412                 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7413                 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7414                 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7415                 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7416                 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7417                 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7418                 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7419               }
7420             }
7421           }
7422         }
7423         // Merge in delay slot (wont dirty)
7424         for(r=0;r<HOST_REGS;r++) {
7425           if(r!=EXCLUDE_REG) {
7426             if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7427             if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7428             if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7429             if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7430             if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7431             if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7432             if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7433             if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7434             if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7435             if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7436           }
7437         }
7438         if(wr) {
7439           #ifndef DESTRUCTIVE_WRITEBACK
7440           branch_regs[i].dirty&=wont_dirty_i;
7441           #endif
7442           branch_regs[i].dirty|=will_dirty_i;
7443         }
7444       }
7445       else
7446       {
7447         // Internal branch
7448         if(ba[i]<=start+i*4) {
7449           // Backward branch
7450           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7451           {
7452             // Unconditional branch
7453             temp_will_dirty=0;
7454             temp_wont_dirty=0;
7455             // Merge in delay slot (will dirty)
7456             for(r=0;r<HOST_REGS;r++) {
7457               if(r!=EXCLUDE_REG) {
7458                 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7459                 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7460                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7461                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7462                 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7463                 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7464                 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7465                 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7466                 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7467                 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7468                 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7469                 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7470                 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7471                 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7472               }
7473             }
7474           } else {
7475             // Conditional branch (not taken case)
7476             temp_will_dirty=will_dirty_next;
7477             temp_wont_dirty=wont_dirty_next;
7478             // Merge in delay slot (will dirty)
7479             for(r=0;r<HOST_REGS;r++) {
7480               if(r!=EXCLUDE_REG) {
7481                 if(!likely[i]) {
7482                   // Will not dirty if likely branch is not taken
7483                   if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7484                   if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7485                   if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7486                   if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7487                   if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7488                   if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7489                   if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7490                   //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7491                   //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7492                   if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7493                   if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7494                   if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7495                   if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7496                   if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7497                 }
7498               }
7499             }
7500           }
7501           // Merge in delay slot (wont dirty)
7502           for(r=0;r<HOST_REGS;r++) {
7503             if(r!=EXCLUDE_REG) {
7504               if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7505               if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7506               if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7507               if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7508               if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7509               if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7510               if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7511               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7512               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7513               if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7514             }
7515           }
7516           // Deal with changed mappings
7517           if(i<iend) {
7518             for(r=0;r<HOST_REGS;r++) {
7519               if(r!=EXCLUDE_REG) {
7520                 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7521                   temp_will_dirty&=~(1<<r);
7522                   temp_wont_dirty&=~(1<<r);
7523                   if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7524                     temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7525                     temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7526                   } else {
7527                     temp_will_dirty|=1<<r;
7528                     temp_wont_dirty|=1<<r;
7529                   }
7530                 }
7531               }
7532             }
7533           }
7534           if(wr) {
7535             will_dirty[i]=temp_will_dirty;
7536             wont_dirty[i]=temp_wont_dirty;
7537             clean_registers((ba[i]-start)>>2,i-1,0);
7538           }else{
7539             // Limit recursion.  It can take an excessive amount
7540             // of time if there are a lot of nested loops.
7541             will_dirty[(ba[i]-start)>>2]=0;
7542             wont_dirty[(ba[i]-start)>>2]=-1;
7543           }
7544         }
7545         /*else*/ if(1)
7546         {
7547           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7548           {
7549             // Unconditional branch
7550             will_dirty_i=0;
7551             wont_dirty_i=0;
7552           //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7553             for(r=0;r<HOST_REGS;r++) {
7554               if(r!=EXCLUDE_REG) {
7555                 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7556                   will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7557                   wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7558                 }
7559                 if(branch_regs[i].regmap[r]>=0) {
7560                   will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7561                   wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7562                 }
7563               }
7564             }
7565           //}
7566             // Merge in delay slot
7567             for(r=0;r<HOST_REGS;r++) {
7568               if(r!=EXCLUDE_REG) {
7569                 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7570                 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7571                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7572                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7573                 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7574                 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7575                 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7576                 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7577                 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7578                 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7579                 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7580                 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7581                 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7582                 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7583               }
7584             }
7585           } else {
7586             // Conditional branch
7587             will_dirty_i=will_dirty_next;
7588             wont_dirty_i=wont_dirty_next;
7589           //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7590             for(r=0;r<HOST_REGS;r++) {
7591               if(r!=EXCLUDE_REG) {
7592                 signed char target_reg=branch_regs[i].regmap[r];
7593                 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7594                   will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7595                   wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7596                 }
7597                 else if(target_reg>=0) {
7598                   will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7599                   wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7600                 }
7601                 // Treat delay slot as part of branch too
7602                 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7603                   will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7604                   wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7605                 }
7606                 else
7607                 {
7608                   will_dirty[i+1]&=~(1<<r);
7609                 }*/
7610               }
7611             }
7612           //}
7613             // Merge in delay slot
7614             for(r=0;r<HOST_REGS;r++) {
7615               if(r!=EXCLUDE_REG) {
7616                 if(!likely[i]) {
7617                   // Might not dirty if likely branch is not taken
7618                   if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7619                   if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7620                   if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7621                   if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7622                   if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7623                   if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7624                   if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7625                   //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7626                   //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7627                   if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7628                   if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7629                   if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7630                   if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7631                   if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7632                 }
7633               }
7634             }
7635           }
7636           // Merge in delay slot (won't dirty)
7637           for(r=0;r<HOST_REGS;r++) {
7638             if(r!=EXCLUDE_REG) {
7639               if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7640               if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7641               if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7642               if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7643               if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7644               if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7645               if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7646               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7647               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7648               if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7649             }
7650           }
7651           if(wr) {
7652             #ifndef DESTRUCTIVE_WRITEBACK
7653             branch_regs[i].dirty&=wont_dirty_i;
7654             #endif
7655             branch_regs[i].dirty|=will_dirty_i;
7656           }
7657         }
7658       }
7659     }
7660     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7661     {
7662       // SYSCALL instruction (software interrupt)
7663       will_dirty_i=0;
7664       wont_dirty_i=0;
7665     }
7666     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7667     {
7668       // ERET instruction (return from interrupt)
7669       will_dirty_i=0;
7670       wont_dirty_i=0;
7671     }
7672     will_dirty_next=will_dirty_i;
7673     wont_dirty_next=wont_dirty_i;
7674     for(r=0;r<HOST_REGS;r++) {
7675       if(r!=EXCLUDE_REG) {
7676         if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7677         if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7678         if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7679         if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7680         if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7681         if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7682         if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7683         if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7684         if(i>istart) {
7685           if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7686           {
7687             // Don't store a register immediately after writing it,
7688             // may prevent dual-issue.
7689             if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7690             if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7691           }
7692         }
7693       }
7694     }
7695     // Save it
7696     will_dirty[i]=will_dirty_i;
7697     wont_dirty[i]=wont_dirty_i;
7698     // Mark registers that won't be dirtied as not dirty
7699     if(wr) {
7700       /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7701       for(r=0;r<HOST_REGS;r++) {
7702         if((will_dirty_i>>r)&1) {
7703           printf(" r%d",r);
7704         }
7705       }
7706       printf("\n");*/
7707
7708       //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7709         regs[i].dirty|=will_dirty_i;
7710         #ifndef DESTRUCTIVE_WRITEBACK
7711         regs[i].dirty&=wont_dirty_i;
7712         if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7713         {
7714           if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7715             for(r=0;r<HOST_REGS;r++) {
7716               if(r!=EXCLUDE_REG) {
7717                 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7718                   regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7719                 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7720               }
7721             }
7722           }
7723         }
7724         else
7725         {
7726           if(i<iend) {
7727             for(r=0;r<HOST_REGS;r++) {
7728               if(r!=EXCLUDE_REG) {
7729                 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7730                   regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7731                 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7732               }
7733             }
7734           }
7735         }
7736         #endif
7737       //}
7738     }
7739     // Deal with changed mappings
7740     temp_will_dirty=will_dirty_i;
7741     temp_wont_dirty=wont_dirty_i;
7742     for(r=0;r<HOST_REGS;r++) {
7743       if(r!=EXCLUDE_REG) {
7744         int nr;
7745         if(regs[i].regmap[r]==regmap_pre[i][r]) {
7746           if(wr) {
7747             #ifndef DESTRUCTIVE_WRITEBACK
7748             regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7749             #endif
7750             regs[i].wasdirty|=will_dirty_i&(1<<r);
7751           }
7752         }
7753         else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7754           // Register moved to a different register
7755           will_dirty_i&=~(1<<r);
7756           wont_dirty_i&=~(1<<r);
7757           will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7758           wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7759           if(wr) {
7760             #ifndef DESTRUCTIVE_WRITEBACK
7761             regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7762             #endif
7763             regs[i].wasdirty|=will_dirty_i&(1<<r);
7764           }
7765         }
7766         else {
7767           will_dirty_i&=~(1<<r);
7768           wont_dirty_i&=~(1<<r);
7769           if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7770             will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7771             wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7772           } else {
7773             wont_dirty_i|=1<<r;
7774             /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7775           }
7776         }
7777       }
7778     }
7779   }
7780 }
7781
7782   /* disassembly */
7783 void disassemble_inst(int i)
7784 {
7785     if (bt[i]) printf("*"); else printf(" ");
7786     switch(itype[i]) {
7787       case UJUMP:
7788         printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7789       case CJUMP:
7790         printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7791       case SJUMP:
7792         printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7793       case FJUMP:
7794         printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7795       case RJUMP:
7796         if (opcode[i]==0x9&&rt1[i]!=31)
7797           printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7798         else
7799           printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7800         break;
7801       case SPAN:
7802         printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7803       case IMM16:
7804         if(opcode[i]==0xf) //LUI
7805           printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7806         else
7807           printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7808         break;
7809       case LOAD:
7810       case LOADLR:
7811         printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7812         break;
7813       case STORE:
7814       case STORELR:
7815         printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7816         break;
7817       case ALU:
7818       case SHIFT:
7819         printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7820         break;
7821       case MULTDIV:
7822         printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7823         break;
7824       case SHIFTIMM:
7825         printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7826         break;
7827       case MOV:
7828         if((opcode2[i]&0x1d)==0x10)
7829           printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7830         else if((opcode2[i]&0x1d)==0x11)
7831           printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7832         else
7833           printf (" %x: %s\n",start+i*4,insn[i]);
7834         break;
7835       case COP0:
7836         if(opcode2[i]==0)
7837           printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7838         else if(opcode2[i]==4)
7839           printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7840         else printf (" %x: %s\n",start+i*4,insn[i]);
7841         break;
7842       case COP1:
7843         if(opcode2[i]<3)
7844           printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7845         else if(opcode2[i]>3)
7846           printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7847         else printf (" %x: %s\n",start+i*4,insn[i]);
7848         break;
7849       case COP2:
7850         if(opcode2[i]<3)
7851           printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7852         else if(opcode2[i]>3)
7853           printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7854         else printf (" %x: %s\n",start+i*4,insn[i]);
7855         break;
7856       case C1LS:
7857         printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7858         break;
7859       case C2LS:
7860         printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7861         break;
7862       case INTCALL:
7863         printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
7864         break;
7865       default:
7866         //printf (" %s %8x\n",insn[i],source[i]);
7867         printf (" %x: %s\n",start+i*4,insn[i]);
7868     }
7869 }
7870
7871 // clear the state completely, instead of just marking
7872 // things invalid like invalidate_all_pages() does
7873 void new_dynarec_clear_full()
7874 {
7875   int n;
7876   out=(u_char *)BASE_ADDR;
7877   memset(invalid_code,1,sizeof(invalid_code));
7878   memset(hash_table,0xff,sizeof(hash_table));
7879   memset(mini_ht,-1,sizeof(mini_ht));
7880   memset(restore_candidate,0,sizeof(restore_candidate));
7881   memset(shadow,0,sizeof(shadow));
7882   copy=shadow;
7883   expirep=16384; // Expiry pointer, +2 blocks
7884   pending_exception=0;
7885   literalcount=0;
7886   stop_after_jal=0;
7887   inv_code_start=inv_code_end=~0;
7888   gte_reads_flags=0;
7889   // TLB
7890 #ifndef DISABLE_TLB
7891   using_tlb=0;
7892 #endif
7893   sp_in_mirror=0;
7894   for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7895     memory_map[n]=-1;
7896   for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7897     memory_map[n]=((u_int)rdram-0x80000000)>>2;
7898   for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7899     memory_map[n]=-1;
7900   for(n=0;n<4096;n++) ll_clear(jump_in+n);
7901   for(n=0;n<4096;n++) ll_clear(jump_out+n);
7902   for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7903 }
7904
7905 void new_dynarec_init()
7906 {
7907   printf("Init new dynarec\n");
7908   out=(u_char *)BASE_ADDR;
7909   if (mmap (out, 1<<TARGET_SIZE_2,
7910             PROT_READ | PROT_WRITE | PROT_EXEC,
7911             MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
7912             -1, 0) <= 0) {printf("mmap() failed\n");}
7913 #ifdef MUPEN64
7914   rdword=&readmem_dword;
7915   fake_pc.f.r.rs=&readmem_dword;
7916   fake_pc.f.r.rt=&readmem_dword;
7917   fake_pc.f.r.rd=&readmem_dword;
7918 #endif
7919   int n;
7920   new_dynarec_clear_full();
7921 #ifdef HOST_IMM8
7922   // Copy this into local area so we don't have to put it in every literal pool
7923   invc_ptr=invalid_code;
7924 #endif
7925 #ifdef MUPEN64
7926   for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
7927     writemem[n] = write_nomem_new;
7928     writememb[n] = write_nomemb_new;
7929     writememh[n] = write_nomemh_new;
7930 #ifndef FORCE32
7931     writememd[n] = write_nomemd_new;
7932 #endif
7933     readmem[n] = read_nomem_new;
7934     readmemb[n] = read_nomemb_new;
7935     readmemh[n] = read_nomemh_new;
7936 #ifndef FORCE32
7937     readmemd[n] = read_nomemd_new;
7938 #endif
7939   }
7940   for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
7941     writemem[n] = write_rdram_new;
7942     writememb[n] = write_rdramb_new;
7943     writememh[n] = write_rdramh_new;
7944 #ifndef FORCE32
7945     writememd[n] = write_rdramd_new;
7946 #endif
7947   }
7948   for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
7949     writemem[n] = write_nomem_new;
7950     writememb[n] = write_nomemb_new;
7951     writememh[n] = write_nomemh_new;
7952 #ifndef FORCE32
7953     writememd[n] = write_nomemd_new;
7954 #endif
7955     readmem[n] = read_nomem_new;
7956     readmemb[n] = read_nomemb_new;
7957     readmemh[n] = read_nomemh_new;
7958 #ifndef FORCE32
7959     readmemd[n] = read_nomemd_new;
7960 #endif
7961   }
7962 #endif
7963   tlb_hacks();
7964   arch_init();
7965 }
7966
7967 void new_dynarec_cleanup()
7968 {
7969   int n;
7970   if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
7971   for(n=0;n<4096;n++) ll_clear(jump_in+n);
7972   for(n=0;n<4096;n++) ll_clear(jump_out+n);
7973   for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7974   #ifdef ROM_COPY
7975   if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
7976   #endif
7977 }
7978
7979 int new_recompile_block(int addr)
7980 {
7981 /*
7982   if(addr==0x800cd050) {
7983     int block;
7984     for(block=0x80000;block<0x80800;block++) invalidate_block(block);
7985     int n;
7986     for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
7987   }
7988 */
7989   //if(Count==365117028) tracedebug=1;
7990   assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7991   //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7992   //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
7993   //if(debug)
7994   //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
7995   //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
7996   /*if(Count>=312978186) {
7997     rlist();
7998   }*/
7999   //rlist();
8000   start = (u_int)addr&~3;
8001   //assert(((u_int)addr&1)==0);
8002 #ifdef PCSX
8003   if(!sp_in_mirror&&(signed int)(psxRegs.GPR.n.sp&0xffe00000)>0x80200000&&
8004      0x10000<=psxRegs.GPR.n.sp&&(psxRegs.GPR.n.sp&~0xe0e00000)<RAM_SIZE) {
8005     printf("SP hack enabled (%08x), @%08x\n", psxRegs.GPR.n.sp, psxRegs.pc);
8006     sp_in_mirror=1;
8007   }
8008   if (Config.HLE && start == 0x80001000) // hlecall
8009   {
8010     // XXX: is this enough? Maybe check hleSoftCall?
8011     u_int beginning=(u_int)out;
8012     u_int page=get_page(start);
8013     invalid_code[start>>12]=0;
8014     emit_movimm(start,0);
8015     emit_writeword(0,(int)&pcaddr);
8016     emit_jmp((int)new_dyna_leave);
8017     literal_pool(0);
8018 #ifdef __arm__
8019     __clear_cache((void *)beginning,out);
8020 #endif
8021     ll_add(jump_in+page,start,(void *)beginning);
8022     return 0;
8023   }
8024   else if ((u_int)addr < 0x00200000 ||
8025     (0xa0000000 <= addr && addr < 0xa0200000)) {
8026     // used for BIOS calls mostly?
8027     source = (u_int *)((u_int)rdram+(start&0x1fffff));
8028     pagelimit = (addr&0xa0000000)|0x00200000;
8029   }
8030   else if (!Config.HLE && (
8031 /*    (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
8032     (0xbfc00000 <= addr && addr < 0xbfc80000))) {
8033     // BIOS
8034     source = (u_int *)((u_int)psxR+(start&0x7ffff));
8035     pagelimit = (addr&0xfff00000)|0x80000;
8036   }
8037   else
8038 #endif
8039 #ifdef MUPEN64
8040   if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
8041     source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
8042     pagelimit = 0xa4001000;
8043   }
8044   else
8045 #endif
8046   if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
8047     source = (u_int *)((u_int)rdram+start-0x80000000);
8048     pagelimit = 0x80000000+RAM_SIZE;
8049   }
8050 #ifndef DISABLE_TLB
8051   else if ((signed int)addr >= (signed int)0xC0000000) {
8052     //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
8053     //if(tlb_LUT_r[start>>12])
8054       //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
8055     if((signed int)memory_map[start>>12]>=0) {
8056       source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
8057       pagelimit=(start+4096)&0xFFFFF000;
8058       int map=memory_map[start>>12];
8059       int i;
8060       for(i=0;i<5;i++) {
8061         //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
8062         if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
8063       }
8064       assem_debug("pagelimit=%x\n",pagelimit);
8065       assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
8066     }
8067     else {
8068       assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
8069       //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
8070       return -1; // Caller will invoke exception handler
8071     }
8072     //printf("source= %x\n",(int)source);
8073   }
8074 #endif
8075   else {
8076     printf("Compile at bogus memory address: %x \n", (int)addr);
8077     exit(1);
8078   }
8079
8080   /* Pass 1: disassemble */
8081   /* Pass 2: register dependencies, branch targets */
8082   /* Pass 3: register allocation */
8083   /* Pass 4: branch dependencies */
8084   /* Pass 5: pre-alloc */
8085   /* Pass 6: optimize clean/dirty state */
8086   /* Pass 7: flag 32-bit registers */
8087   /* Pass 8: assembly */
8088   /* Pass 9: linker */
8089   /* Pass 10: garbage collection / free memory */
8090
8091   int i,j;
8092   int done=0;
8093   unsigned int type,op,op2;
8094
8095   //printf("addr = %x source = %x %x\n", addr,source,source[0]);
8096
8097   /* Pass 1 disassembly */
8098
8099   for(i=0;!done;i++) {
8100     bt[i]=0;likely[i]=0;ooo[i]=0;op2=0;
8101     minimum_free_regs[i]=0;
8102     opcode[i]=op=source[i]>>26;
8103     switch(op)
8104     {
8105       case 0x00: strcpy(insn[i],"special"); type=NI;
8106         op2=source[i]&0x3f;
8107         switch(op2)
8108         {
8109           case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
8110           case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
8111           case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
8112           case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
8113           case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
8114           case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
8115           case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
8116           case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
8117           case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
8118           case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
8119           case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
8120           case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
8121           case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
8122           case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
8123           case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
8124           case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
8125           case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
8126           case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
8127           case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
8128           case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
8129           case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
8130           case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
8131           case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
8132           case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
8133           case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
8134           case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
8135           case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
8136           case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
8137           case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
8138           case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
8139           case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
8140           case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
8141           case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
8142           case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
8143           case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
8144 #ifndef FORCE32
8145           case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
8146           case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
8147           case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
8148           case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
8149           case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
8150           case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
8151           case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
8152           case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
8153           case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
8154           case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
8155           case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
8156           case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
8157           case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
8158           case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
8159           case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
8160           case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
8161           case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
8162 #endif
8163         }
8164         break;
8165       case 0x01: strcpy(insn[i],"regimm"); type=NI;
8166         op2=(source[i]>>16)&0x1f;
8167         switch(op2)
8168         {
8169           case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
8170           case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
8171           case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
8172           case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
8173           case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
8174           case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
8175           case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
8176           case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
8177           case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
8178           case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
8179           case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
8180           case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
8181           case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
8182           case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
8183         }
8184         break;
8185       case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
8186       case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
8187       case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
8188       case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
8189       case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
8190       case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
8191       case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
8192       case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
8193       case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
8194       case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
8195       case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
8196       case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
8197       case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
8198       case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
8199       case 0x10: strcpy(insn[i],"cop0"); type=NI;
8200         op2=(source[i]>>21)&0x1f;
8201         switch(op2)
8202         {
8203           case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
8204           case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
8205           case 0x10: strcpy(insn[i],"tlb"); type=NI;
8206           switch(source[i]&0x3f)
8207           {
8208             case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
8209             case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
8210             case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
8211             case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
8212 #ifdef PCSX
8213             case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
8214 #else
8215             case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
8216 #endif
8217           }
8218         }
8219         break;
8220       case 0x11: strcpy(insn[i],"cop1"); type=NI;
8221         op2=(source[i]>>21)&0x1f;
8222         switch(op2)
8223         {
8224           case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
8225           case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
8226           case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
8227           case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
8228           case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
8229           case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
8230           case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
8231           switch((source[i]>>16)&0x3)
8232           {
8233             case 0x00: strcpy(insn[i],"BC1F"); break;
8234             case 0x01: strcpy(insn[i],"BC1T"); break;
8235             case 0x02: strcpy(insn[i],"BC1FL"); break;
8236             case 0x03: strcpy(insn[i],"BC1TL"); break;
8237           }
8238           break;
8239           case 0x10: strcpy(insn[i],"C1.S"); type=NI;
8240           switch(source[i]&0x3f)
8241           {
8242             case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
8243             case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
8244             case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
8245             case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
8246             case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
8247             case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
8248             case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
8249             case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
8250             case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
8251             case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
8252             case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
8253             case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
8254             case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
8255             case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
8256             case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
8257             case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
8258             case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
8259             case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
8260             case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
8261             case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
8262             case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
8263             case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
8264             case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
8265             case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
8266             case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
8267             case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
8268             case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
8269             case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
8270             case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
8271             case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
8272             case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
8273             case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
8274             case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
8275             case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
8276             case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
8277           }
8278           break;
8279           case 0x11: strcpy(insn[i],"C1.D"); type=NI;
8280           switch(source[i]&0x3f)
8281           {
8282             case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
8283             case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
8284             case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
8285             case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
8286             case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
8287             case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
8288             case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
8289             case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
8290             case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
8291             case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
8292             case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
8293             case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
8294             case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
8295             case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
8296             case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
8297             case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
8298             case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
8299             case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
8300             case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
8301             case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
8302             case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
8303             case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
8304             case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
8305             case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
8306             case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
8307             case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
8308             case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
8309             case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
8310             case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
8311             case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
8312             case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8313             case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8314             case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8315             case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8316             case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8317           }
8318           break;
8319           case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8320           switch(source[i]&0x3f)
8321           {
8322             case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8323             case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8324           }
8325           break;
8326           case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8327           switch(source[i]&0x3f)
8328           {
8329             case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8330             case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8331           }
8332           break;
8333         }
8334         break;
8335 #ifndef FORCE32
8336       case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8337       case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8338       case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8339       case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8340       case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8341       case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8342       case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8343       case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
8344 #endif
8345       case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8346       case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8347       case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8348       case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8349       case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8350       case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8351       case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
8352 #ifndef FORCE32
8353       case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
8354 #endif
8355       case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8356       case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8357       case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8358       case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
8359 #ifndef FORCE32
8360       case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8361       case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
8362 #endif
8363       case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8364       case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8365       case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8366       case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
8367 #ifndef FORCE32
8368       case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8369       case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8370       case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
8371 #endif
8372       case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8373       case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
8374 #ifndef FORCE32
8375       case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8376       case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8377       case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
8378 #endif
8379 #ifdef PCSX
8380       case 0x12: strcpy(insn[i],"COP2"); type=NI;
8381         op2=(source[i]>>21)&0x1f;
8382         //if (op2 & 0x10) {
8383         if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
8384           if (gte_handlers[source[i]&0x3f]!=NULL) {
8385             if (gte_regnames[source[i]&0x3f]!=NULL)
8386               strcpy(insn[i],gte_regnames[source[i]&0x3f]);
8387             else
8388               snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8389             type=C2OP;
8390           }
8391         }
8392         else switch(op2)
8393         {
8394           case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8395           case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8396           case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8397           case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
8398         }
8399         break;
8400       case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8401       case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8402       case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8403 #endif
8404       default: strcpy(insn[i],"???"); type=NI;
8405         printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
8406         break;
8407     }
8408     itype[i]=type;
8409     opcode2[i]=op2;
8410     /* Get registers/immediates */
8411     lt1[i]=0;
8412     us1[i]=0;
8413     us2[i]=0;
8414     dep1[i]=0;
8415     dep2[i]=0;
8416     gte_rs[i]=gte_rt[i]=0;
8417     switch(type) {
8418       case LOAD:
8419         rs1[i]=(source[i]>>21)&0x1f;
8420         rs2[i]=0;
8421         rt1[i]=(source[i]>>16)&0x1f;
8422         rt2[i]=0;
8423         imm[i]=(short)source[i];
8424         break;
8425       case STORE:
8426       case STORELR:
8427         rs1[i]=(source[i]>>21)&0x1f;
8428         rs2[i]=(source[i]>>16)&0x1f;
8429         rt1[i]=0;
8430         rt2[i]=0;
8431         imm[i]=(short)source[i];
8432         if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8433         break;
8434       case LOADLR:
8435         // LWL/LWR only load part of the register,
8436         // therefore the target register must be treated as a source too
8437         rs1[i]=(source[i]>>21)&0x1f;
8438         rs2[i]=(source[i]>>16)&0x1f;
8439         rt1[i]=(source[i]>>16)&0x1f;
8440         rt2[i]=0;
8441         imm[i]=(short)source[i];
8442         if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8443         if(op==0x26) dep1[i]=rt1[i]; // LWR
8444         break;
8445       case IMM16:
8446         if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8447         else rs1[i]=(source[i]>>21)&0x1f;
8448         rs2[i]=0;
8449         rt1[i]=(source[i]>>16)&0x1f;
8450         rt2[i]=0;
8451         if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8452           imm[i]=(unsigned short)source[i];
8453         }else{
8454           imm[i]=(short)source[i];
8455         }
8456         if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8457         if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8458         if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8459         break;
8460       case UJUMP:
8461         rs1[i]=0;
8462         rs2[i]=0;
8463         rt1[i]=0;
8464         rt2[i]=0;
8465         // The JAL instruction writes to r31.
8466         if (op&1) {
8467           rt1[i]=31;
8468         }
8469         rs2[i]=CCREG;
8470         break;
8471       case RJUMP:
8472         rs1[i]=(source[i]>>21)&0x1f;
8473         rs2[i]=0;
8474         rt1[i]=0;
8475         rt2[i]=0;
8476         // The JALR instruction writes to rd.
8477         if (op2&1) {
8478           rt1[i]=(source[i]>>11)&0x1f;
8479         }
8480         rs2[i]=CCREG;
8481         break;
8482       case CJUMP:
8483         rs1[i]=(source[i]>>21)&0x1f;
8484         rs2[i]=(source[i]>>16)&0x1f;
8485         rt1[i]=0;
8486         rt2[i]=0;
8487         if(op&2) { // BGTZ/BLEZ
8488           rs2[i]=0;
8489         }
8490         us1[i]=rs1[i];
8491         us2[i]=rs2[i];
8492         likely[i]=op>>4;
8493         break;
8494       case SJUMP:
8495         rs1[i]=(source[i]>>21)&0x1f;
8496         rs2[i]=CCREG;
8497         rt1[i]=0;
8498         rt2[i]=0;
8499         us1[i]=rs1[i];
8500         if(op2&0x10) { // BxxAL
8501           rt1[i]=31;
8502           // NOTE: If the branch is not taken, r31 is still overwritten
8503         }
8504         likely[i]=(op2&2)>>1;
8505         break;
8506       case FJUMP:
8507         rs1[i]=FSREG;
8508         rs2[i]=CSREG;
8509         rt1[i]=0;
8510         rt2[i]=0;
8511         likely[i]=((source[i])>>17)&1;
8512         break;
8513       case ALU:
8514         rs1[i]=(source[i]>>21)&0x1f; // source
8515         rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8516         rt1[i]=(source[i]>>11)&0x1f; // destination
8517         rt2[i]=0;
8518         if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8519           us1[i]=rs1[i];us2[i]=rs2[i];
8520         }
8521         else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8522           dep1[i]=rs1[i];dep2[i]=rs2[i];
8523         }
8524         else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8525           dep1[i]=rs1[i];dep2[i]=rs2[i];
8526         }
8527         break;
8528       case MULTDIV:
8529         rs1[i]=(source[i]>>21)&0x1f; // source
8530         rs2[i]=(source[i]>>16)&0x1f; // divisor
8531         rt1[i]=HIREG;
8532         rt2[i]=LOREG;
8533         if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8534           us1[i]=rs1[i];us2[i]=rs2[i];
8535         }
8536         break;
8537       case MOV:
8538         rs1[i]=0;
8539         rs2[i]=0;
8540         rt1[i]=0;
8541         rt2[i]=0;
8542         if(op2==0x10) rs1[i]=HIREG; // MFHI
8543         if(op2==0x11) rt1[i]=HIREG; // MTHI
8544         if(op2==0x12) rs1[i]=LOREG; // MFLO
8545         if(op2==0x13) rt1[i]=LOREG; // MTLO
8546         if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8547         if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8548         dep1[i]=rs1[i];
8549         break;
8550       case SHIFT:
8551         rs1[i]=(source[i]>>16)&0x1f; // target of shift
8552         rs2[i]=(source[i]>>21)&0x1f; // shift amount
8553         rt1[i]=(source[i]>>11)&0x1f; // destination
8554         rt2[i]=0;
8555         // DSLLV/DSRLV/DSRAV are 64-bit
8556         if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8557         break;
8558       case SHIFTIMM:
8559         rs1[i]=(source[i]>>16)&0x1f;
8560         rs2[i]=0;
8561         rt1[i]=(source[i]>>11)&0x1f;
8562         rt2[i]=0;
8563         imm[i]=(source[i]>>6)&0x1f;
8564         // DSxx32 instructions
8565         if(op2>=0x3c) imm[i]|=0x20;
8566         // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8567         if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8568         break;
8569       case COP0:
8570         rs1[i]=0;
8571         rs2[i]=0;
8572         rt1[i]=0;
8573         rt2[i]=0;
8574         if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8575         if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8576         if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8577         if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8578         break;
8579       case COP1:
8580         rs1[i]=0;
8581         rs2[i]=0;
8582         rt1[i]=0;
8583         rt2[i]=0;
8584         if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8585         if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8586         if(op2==5) us1[i]=rs1[i]; // DMTC1
8587         rs2[i]=CSREG;
8588         break;
8589       case COP2:
8590         rs1[i]=0;
8591         rs2[i]=0;
8592         rt1[i]=0;
8593         rt2[i]=0;
8594         if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC2/CFC2
8595         if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC2/CTC2
8596         rs2[i]=CSREG;
8597         int gr=(source[i]>>11)&0x1F;
8598         switch(op2)
8599         {
8600           case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
8601           case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
8602           case 0x02: gte_rs[i]=1ll<<(gr+32); // CFC2
8603             if(gr==31&&!gte_reads_flags) {
8604               assem_debug("gte flag read encountered @%08x\n",addr + i*4);
8605               gte_reads_flags=1;
8606             }
8607             break;
8608           case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
8609         }
8610         break;
8611       case C1LS:
8612         rs1[i]=(source[i]>>21)&0x1F;
8613         rs2[i]=CSREG;
8614         rt1[i]=0;
8615         rt2[i]=0;
8616         imm[i]=(short)source[i];
8617         break;
8618       case C2LS:
8619         rs1[i]=(source[i]>>21)&0x1F;
8620         rs2[i]=0;
8621         rt1[i]=0;
8622         rt2[i]=0;
8623         imm[i]=(short)source[i];
8624         if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
8625         else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
8626         break;
8627       case C2OP:
8628         rs1[i]=0;
8629         rs2[i]=0;
8630         rt1[i]=0;
8631         rt2[i]=0;
8632         gte_rt[i]=1ll<<63; // every op changes flags
8633         // TODO: other regs?
8634         break;
8635       case FLOAT:
8636       case FCONV:
8637         rs1[i]=0;
8638         rs2[i]=CSREG;
8639         rt1[i]=0;
8640         rt2[i]=0;
8641         break;
8642       case FCOMP:
8643         rs1[i]=FSREG;
8644         rs2[i]=CSREG;
8645         rt1[i]=FSREG;
8646         rt2[i]=0;
8647         break;
8648       case SYSCALL:
8649       case HLECALL:
8650       case INTCALL:
8651         rs1[i]=CCREG;
8652         rs2[i]=0;
8653         rt1[i]=0;
8654         rt2[i]=0;
8655         break;
8656       default:
8657         rs1[i]=0;
8658         rs2[i]=0;
8659         rt1[i]=0;
8660         rt2[i]=0;
8661     }
8662     /* Calculate branch target addresses */
8663     if(type==UJUMP)
8664       ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8665     else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8666       ba[i]=start+i*4+8; // Ignore never taken branch
8667     else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8668       ba[i]=start+i*4+8; // Ignore never taken branch
8669     else if(type==CJUMP||type==SJUMP||type==FJUMP)
8670       ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8671     else ba[i]=-1;
8672 #ifdef PCSX
8673     if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
8674       int do_in_intrp=0;
8675       // branch in delay slot?
8676       if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
8677         // don't handle first branch and call interpreter if it's hit
8678         printf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
8679         do_in_intrp=1;
8680       }
8681       // basic load delay detection
8682       else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&rt1[i]!=0) {
8683         int t=(ba[i-1]-start)/4;
8684         if(0 <= t && t < i &&(rt1[i]==rs1[t]||rt1[i]==rs2[t])&&itype[t]!=CJUMP&&itype[t]!=SJUMP) {
8685           // jump target wants DS result - potential load delay effect
8686           printf("load delay @%08x (%08x)\n", addr + i*4, addr);
8687           do_in_intrp=1;
8688           bt[t+1]=1; // expected return from interpreter
8689         }
8690         else if(i>=2&&rt1[i-2]==2&&rt1[i]==2&&rs1[i]!=2&&rs2[i]!=2&&rs1[i-1]!=2&&rs2[i-1]!=2&&
8691               !(i>=3&&(itype[i-3]==RJUMP||itype[i-3]==UJUMP||itype[i-3]==CJUMP||itype[i-3]==SJUMP))) {
8692           // v0 overwrite like this is a sign of trouble, bail out
8693           printf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
8694           do_in_intrp=1;
8695         }
8696       }
8697       if(do_in_intrp) {
8698         rs1[i-1]=CCREG;
8699         rs2[i-1]=rt1[i-1]=rt2[i-1]=0;
8700         ba[i-1]=-1;
8701         itype[i-1]=INTCALL;
8702         done=2;
8703         i--; // don't compile the DS
8704       }
8705     }
8706 #endif
8707     /* Is this the end of the block? */
8708     if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
8709       if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
8710         done=2;
8711       }
8712       else {
8713         if(stop_after_jal) done=1;
8714         // Stop on BREAK
8715         if((source[i+1]&0xfc00003f)==0x0d) done=1;
8716       }
8717       // Don't recompile stuff that's already compiled
8718       if(check_addr(start+i*4+4)) done=1;
8719       // Don't get too close to the limit
8720       if(i>MAXBLOCK/2) done=1;
8721     }
8722     if(itype[i]==SYSCALL&&stop_after_jal) done=1;
8723     if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
8724     if(done==2) {
8725       // Does the block continue due to a branch?
8726       for(j=i-1;j>=0;j--)
8727       {
8728         if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
8729         if(ba[j]==start+i*4+4) done=j=0;
8730         if(ba[j]==start+i*4+8) done=j=0;
8731       }
8732     }
8733     //assert(i<MAXBLOCK-1);
8734     if(start+i*4==pagelimit-4) done=1;
8735     assert(start+i*4<pagelimit);
8736     if (i==MAXBLOCK-1) done=1;
8737     // Stop if we're compiling junk
8738     if(itype[i]==NI&&opcode[i]==0x11) {
8739       done=stop_after_jal=1;
8740       printf("Disabled speculative precompilation\n");
8741     }
8742   }
8743   slen=i;
8744   if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8745     if(start+i*4==pagelimit) {
8746       itype[i-1]=SPAN;
8747     }
8748   }
8749   assert(slen>0);
8750
8751   /* Pass 2 - Register dependencies and branch targets */
8752
8753   unneeded_registers(0,slen-1,0);
8754
8755   /* Pass 3 - Register allocation */
8756
8757   struct regstat current; // Current register allocations/status
8758   current.is32=1;
8759   current.dirty=0;
8760   current.u=unneeded_reg[0];
8761   current.uu=unneeded_reg_upper[0];
8762   clear_all_regs(current.regmap);
8763   alloc_reg(&current,0,CCREG);
8764   dirty_reg(&current,CCREG);
8765   current.isconst=0;
8766   current.wasconst=0;
8767   int ds=0;
8768   int cc=0;
8769   int hr=-1;
8770
8771 #ifndef FORCE32
8772   provisional_32bit();
8773 #endif
8774   if((u_int)addr&1) {
8775     // First instruction is delay slot
8776     cc=-1;
8777     bt[1]=1;
8778     ds=1;
8779     unneeded_reg[0]=1;
8780     unneeded_reg_upper[0]=1;
8781     current.regmap[HOST_BTREG]=BTREG;
8782   }
8783
8784   for(i=0;i<slen;i++)
8785   {
8786     if(bt[i])
8787     {
8788       int hr;
8789       for(hr=0;hr<HOST_REGS;hr++)
8790       {
8791         // Is this really necessary?
8792         if(current.regmap[hr]==0) current.regmap[hr]=-1;
8793       }
8794       current.isconst=0;
8795     }
8796     if(i>1)
8797     {
8798       if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8799       {
8800         if(rs1[i-2]==0||rs2[i-2]==0)
8801         {
8802           if(rs1[i-2]) {
8803             current.is32|=1LL<<rs1[i-2];
8804             int hr=get_reg(current.regmap,rs1[i-2]|64);
8805             if(hr>=0) current.regmap[hr]=-1;
8806           }
8807           if(rs2[i-2]) {
8808             current.is32|=1LL<<rs2[i-2];
8809             int hr=get_reg(current.regmap,rs2[i-2]|64);
8810             if(hr>=0) current.regmap[hr]=-1;
8811           }
8812         }
8813       }
8814     }
8815 #ifndef FORCE32
8816     // If something jumps here with 64-bit values
8817     // then promote those registers to 64 bits
8818     if(bt[i])
8819     {
8820       uint64_t temp_is32=current.is32;
8821       for(j=i-1;j>=0;j--)
8822       {
8823         if(ba[j]==start+i*4)
8824           temp_is32&=branch_regs[j].is32;
8825       }
8826       for(j=i;j<slen;j++)
8827       {
8828         if(ba[j]==start+i*4)
8829           //temp_is32=1;
8830           temp_is32&=p32[j];
8831       }
8832       if(temp_is32!=current.is32) {
8833         //printf("dumping 32-bit regs (%x)\n",start+i*4);
8834         #ifndef DESTRUCTIVE_WRITEBACK
8835         if(ds)
8836         #endif
8837         for(hr=0;hr<HOST_REGS;hr++)
8838         {
8839           int r=current.regmap[hr];
8840           if(r>0&&r<64)
8841           {
8842             if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8843               temp_is32|=1LL<<r;
8844               //printf("restore %d\n",r);
8845             }
8846           }
8847         }
8848         current.is32=temp_is32;
8849       }
8850     }
8851 #else
8852     current.is32=-1LL;
8853 #endif
8854
8855     memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8856     regs[i].wasconst=current.isconst;
8857     regs[i].was32=current.is32;
8858     regs[i].wasdirty=current.dirty;
8859     #if defined(DESTRUCTIVE_WRITEBACK) && !defined(FORCE32)
8860     // To change a dirty register from 32 to 64 bits, we must write
8861     // it out during the previous cycle (for branches, 2 cycles)
8862     if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8863     {
8864       uint64_t temp_is32=current.is32;
8865       for(j=i-1;j>=0;j--)
8866       {
8867         if(ba[j]==start+i*4+4)
8868           temp_is32&=branch_regs[j].is32;
8869       }
8870       for(j=i;j<slen;j++)
8871       {
8872         if(ba[j]==start+i*4+4)
8873           //temp_is32=1;
8874           temp_is32&=p32[j];
8875       }
8876       if(temp_is32!=current.is32) {
8877         //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8878         for(hr=0;hr<HOST_REGS;hr++)
8879         {
8880           int r=current.regmap[hr];
8881           if(r>0)
8882           {
8883             if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8884               if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
8885               {
8886                 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
8887                 {
8888                   //printf("dump %d/r%d\n",hr,r);
8889                   current.regmap[hr]=-1;
8890                   if(get_reg(current.regmap,r|64)>=0)
8891                     current.regmap[get_reg(current.regmap,r|64)]=-1;
8892                 }
8893               }
8894             }
8895           }
8896         }
8897       }
8898     }
8899     else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
8900     {
8901       uint64_t temp_is32=current.is32;
8902       for(j=i-1;j>=0;j--)
8903       {
8904         if(ba[j]==start+i*4+8)
8905           temp_is32&=branch_regs[j].is32;
8906       }
8907       for(j=i;j<slen;j++)
8908       {
8909         if(ba[j]==start+i*4+8)
8910           //temp_is32=1;
8911           temp_is32&=p32[j];
8912       }
8913       if(temp_is32!=current.is32) {
8914         //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8915         for(hr=0;hr<HOST_REGS;hr++)
8916         {
8917           int r=current.regmap[hr];
8918           if(r>0)
8919           {
8920             if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8921               if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
8922               {
8923                 //printf("dump %d/r%d\n",hr,r);
8924                 current.regmap[hr]=-1;
8925                 if(get_reg(current.regmap,r|64)>=0)
8926                   current.regmap[get_reg(current.regmap,r|64)]=-1;
8927               }
8928             }
8929           }
8930         }
8931       }
8932     }
8933     #endif
8934     if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8935       if(i+1<slen) {
8936         current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8937         current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8938         if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8939         current.u|=1;
8940         current.uu|=1;
8941       } else {
8942         current.u=1;
8943         current.uu=1;
8944       }
8945     } else {
8946       if(i+1<slen) {
8947         current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
8948         current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8949         if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8950         current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8951         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8952         current.u|=1;
8953         current.uu|=1;
8954       } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
8955     }
8956     is_ds[i]=ds;
8957     if(ds) {
8958       ds=0; // Skip delay slot, already allocated as part of branch
8959       // ...but we need to alloc it in case something jumps here
8960       if(i+1<slen) {
8961         current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
8962         current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
8963       }else{
8964         current.u=branch_unneeded_reg[i-1];
8965         current.uu=branch_unneeded_reg_upper[i-1];
8966       }
8967       current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8968       current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8969       if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8970       current.u|=1;
8971       current.uu|=1;
8972       struct regstat temp;
8973       memcpy(&temp,&current,sizeof(current));
8974       temp.wasdirty=temp.dirty;
8975       temp.was32=temp.is32;
8976       // TODO: Take into account unconditional branches, as below
8977       delayslot_alloc(&temp,i);
8978       memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
8979       regs[i].wasdirty=temp.wasdirty;
8980       regs[i].was32=temp.was32;
8981       regs[i].dirty=temp.dirty;
8982       regs[i].is32=temp.is32;
8983       regs[i].isconst=0;
8984       regs[i].wasconst=0;
8985       current.isconst=0;
8986       // Create entry (branch target) regmap
8987       for(hr=0;hr<HOST_REGS;hr++)
8988       {
8989         int r=temp.regmap[hr];
8990         if(r>=0) {
8991           if(r!=regmap_pre[i][hr]) {
8992             regs[i].regmap_entry[hr]=-1;
8993           }
8994           else
8995           {
8996             if(r<64){
8997               if((current.u>>r)&1) {
8998                 regs[i].regmap_entry[hr]=-1;
8999                 regs[i].regmap[hr]=-1;
9000                 //Don't clear regs in the delay slot as the branch might need them
9001                 //current.regmap[hr]=-1;
9002               }else
9003                 regs[i].regmap_entry[hr]=r;
9004             }
9005             else {
9006               if((current.uu>>(r&63))&1) {
9007                 regs[i].regmap_entry[hr]=-1;
9008                 regs[i].regmap[hr]=-1;
9009                 //Don't clear regs in the delay slot as the branch might need them
9010                 //current.regmap[hr]=-1;
9011               }else
9012                 regs[i].regmap_entry[hr]=r;
9013             }
9014           }
9015         } else {
9016           // First instruction expects CCREG to be allocated
9017           if(i==0&&hr==HOST_CCREG)
9018             regs[i].regmap_entry[hr]=CCREG;
9019           else
9020             regs[i].regmap_entry[hr]=-1;
9021         }
9022       }
9023     }
9024     else { // Not delay slot
9025       switch(itype[i]) {
9026         case UJUMP:
9027           //current.isconst=0; // DEBUG
9028           //current.wasconst=0; // DEBUG
9029           //regs[i].wasconst=0; // DEBUG
9030           clear_const(&current,rt1[i]);
9031           alloc_cc(&current,i);
9032           dirty_reg(&current,CCREG);
9033           if (rt1[i]==31) {
9034             alloc_reg(&current,i,31);
9035             dirty_reg(&current,31);
9036             //assert(rs1[i+1]!=31&&rs2[i+1]!=31);
9037             //assert(rt1[i+1]!=rt1[i]);
9038             #ifdef REG_PREFETCH
9039             alloc_reg(&current,i,PTEMP);
9040             #endif
9041             //current.is32|=1LL<<rt1[i];
9042           }
9043           ooo[i]=1;
9044           delayslot_alloc(&current,i+1);
9045           //current.isconst=0; // DEBUG
9046           ds=1;
9047           //printf("i=%d, isconst=%x\n",i,current.isconst);
9048           break;
9049         case RJUMP:
9050           //current.isconst=0;
9051           //current.wasconst=0;
9052           //regs[i].wasconst=0;
9053           clear_const(&current,rs1[i]);
9054           clear_const(&current,rt1[i]);
9055           alloc_cc(&current,i);
9056           dirty_reg(&current,CCREG);
9057           if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
9058             alloc_reg(&current,i,rs1[i]);
9059             if (rt1[i]!=0) {
9060               alloc_reg(&current,i,rt1[i]);
9061               dirty_reg(&current,rt1[i]);
9062               assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
9063               assert(rt1[i+1]!=rt1[i]);
9064               #ifdef REG_PREFETCH
9065               alloc_reg(&current,i,PTEMP);
9066               #endif
9067             }
9068             #ifdef USE_MINI_HT
9069             if(rs1[i]==31) { // JALR
9070               alloc_reg(&current,i,RHASH);
9071               #ifndef HOST_IMM_ADDR32
9072               alloc_reg(&current,i,RHTBL);
9073               #endif
9074             }
9075             #endif
9076             delayslot_alloc(&current,i+1);
9077           } else {
9078             // The delay slot overwrites our source register,
9079             // allocate a temporary register to hold the old value.
9080             current.isconst=0;
9081             current.wasconst=0;
9082             regs[i].wasconst=0;
9083             delayslot_alloc(&current,i+1);
9084             current.isconst=0;
9085             alloc_reg(&current,i,RTEMP);
9086           }
9087           //current.isconst=0; // DEBUG
9088           ooo[i]=1;
9089           ds=1;
9090           break;
9091         case CJUMP:
9092           //current.isconst=0;
9093           //current.wasconst=0;
9094           //regs[i].wasconst=0;
9095           clear_const(&current,rs1[i]);
9096           clear_const(&current,rs2[i]);
9097           if((opcode[i]&0x3E)==4) // BEQ/BNE
9098           {
9099             alloc_cc(&current,i);
9100             dirty_reg(&current,CCREG);
9101             if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9102             if(rs2[i]) alloc_reg(&current,i,rs2[i]);
9103             if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9104             {
9105               if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9106               if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
9107             }
9108             if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
9109                (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
9110               // The delay slot overwrites one of our conditions.
9111               // Allocate the branch condition registers instead.
9112               current.isconst=0;
9113               current.wasconst=0;
9114               regs[i].wasconst=0;
9115               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9116               if(rs2[i]) alloc_reg(&current,i,rs2[i]);
9117               if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9118               {
9119                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9120                 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
9121               }
9122             }
9123             else
9124             {
9125               ooo[i]=1;
9126               delayslot_alloc(&current,i+1);
9127             }
9128           }
9129           else
9130           if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
9131           {
9132             alloc_cc(&current,i);
9133             dirty_reg(&current,CCREG);
9134             alloc_reg(&current,i,rs1[i]);
9135             if(!(current.is32>>rs1[i]&1))
9136             {
9137               alloc_reg64(&current,i,rs1[i]);
9138             }
9139             if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
9140               // The delay slot overwrites one of our conditions.
9141               // Allocate the branch condition registers instead.
9142               current.isconst=0;
9143               current.wasconst=0;
9144               regs[i].wasconst=0;
9145               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9146               if(!((current.is32>>rs1[i])&1))
9147               {
9148                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9149               }
9150             }
9151             else
9152             {
9153               ooo[i]=1;
9154               delayslot_alloc(&current,i+1);
9155             }
9156           }
9157           else
9158           // Don't alloc the delay slot yet because we might not execute it
9159           if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
9160           {
9161             current.isconst=0;
9162             current.wasconst=0;
9163             regs[i].wasconst=0;
9164             alloc_cc(&current,i);
9165             dirty_reg(&current,CCREG);
9166             alloc_reg(&current,i,rs1[i]);
9167             alloc_reg(&current,i,rs2[i]);
9168             if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9169             {
9170               alloc_reg64(&current,i,rs1[i]);
9171               alloc_reg64(&current,i,rs2[i]);
9172             }
9173           }
9174           else
9175           if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
9176           {
9177             current.isconst=0;
9178             current.wasconst=0;
9179             regs[i].wasconst=0;
9180             alloc_cc(&current,i);
9181             dirty_reg(&current,CCREG);
9182             alloc_reg(&current,i,rs1[i]);
9183             if(!(current.is32>>rs1[i]&1))
9184             {
9185               alloc_reg64(&current,i,rs1[i]);
9186             }
9187           }
9188           ds=1;
9189           //current.isconst=0;
9190           break;
9191         case SJUMP:
9192           //current.isconst=0;
9193           //current.wasconst=0;
9194           //regs[i].wasconst=0;
9195           clear_const(&current,rs1[i]);
9196           clear_const(&current,rt1[i]);
9197           //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
9198           if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
9199           {
9200             alloc_cc(&current,i);
9201             dirty_reg(&current,CCREG);
9202             alloc_reg(&current,i,rs1[i]);
9203             if(!(current.is32>>rs1[i]&1))
9204             {
9205               alloc_reg64(&current,i,rs1[i]);
9206             }
9207             if (rt1[i]==31) { // BLTZAL/BGEZAL
9208               alloc_reg(&current,i,31);
9209               dirty_reg(&current,31);
9210               //#ifdef REG_PREFETCH
9211               //alloc_reg(&current,i,PTEMP);
9212               //#endif
9213               //current.is32|=1LL<<rt1[i];
9214             }
9215             if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) // The delay slot overwrites the branch condition.
9216                ||(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))) { // DS touches $ra
9217               // Allocate the branch condition registers instead.
9218               current.isconst=0;
9219               current.wasconst=0;
9220               regs[i].wasconst=0;
9221               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9222               if(!((current.is32>>rs1[i])&1))
9223               {
9224                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9225               }
9226             }
9227             else
9228             {
9229               ooo[i]=1;
9230               delayslot_alloc(&current,i+1);
9231             }
9232           }
9233           else
9234           // Don't alloc the delay slot yet because we might not execute it
9235           if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
9236           {
9237             current.isconst=0;
9238             current.wasconst=0;
9239             regs[i].wasconst=0;
9240             alloc_cc(&current,i);
9241             dirty_reg(&current,CCREG);
9242             alloc_reg(&current,i,rs1[i]);
9243             if(!(current.is32>>rs1[i]&1))
9244             {
9245               alloc_reg64(&current,i,rs1[i]);
9246             }
9247           }
9248           ds=1;
9249           //current.isconst=0;
9250           break;
9251         case FJUMP:
9252           current.isconst=0;
9253           current.wasconst=0;
9254           regs[i].wasconst=0;
9255           if(likely[i]==0) // BC1F/BC1T
9256           {
9257             // TODO: Theoretically we can run out of registers here on x86.
9258             // The delay slot can allocate up to six, and we need to check
9259             // CSREG before executing the delay slot.  Possibly we can drop
9260             // the cycle count and then reload it after checking that the
9261             // FPU is in a usable state, or don't do out-of-order execution.
9262             alloc_cc(&current,i);
9263             dirty_reg(&current,CCREG);
9264             alloc_reg(&current,i,FSREG);
9265             alloc_reg(&current,i,CSREG);
9266             if(itype[i+1]==FCOMP) {
9267               // The delay slot overwrites the branch condition.
9268               // Allocate the branch condition registers instead.
9269               alloc_cc(&current,i);
9270               dirty_reg(&current,CCREG);
9271               alloc_reg(&current,i,CSREG);
9272               alloc_reg(&current,i,FSREG);
9273             }
9274             else {
9275               ooo[i]=1;
9276               delayslot_alloc(&current,i+1);
9277               alloc_reg(&current,i+1,CSREG);
9278             }
9279           }
9280           else
9281           // Don't alloc the delay slot yet because we might not execute it
9282           if(likely[i]) // BC1FL/BC1TL
9283           {
9284             alloc_cc(&current,i);
9285             dirty_reg(&current,CCREG);
9286             alloc_reg(&current,i,CSREG);
9287             alloc_reg(&current,i,FSREG);
9288           }
9289           ds=1;
9290           current.isconst=0;
9291           break;
9292         case IMM16:
9293           imm16_alloc(&current,i);
9294           break;
9295         case LOAD:
9296         case LOADLR:
9297           load_alloc(&current,i);
9298           break;
9299         case STORE:
9300         case STORELR:
9301           store_alloc(&current,i);
9302           break;
9303         case ALU:
9304           alu_alloc(&current,i);
9305           break;
9306         case SHIFT:
9307           shift_alloc(&current,i);
9308           break;
9309         case MULTDIV:
9310           multdiv_alloc(&current,i);
9311           break;
9312         case SHIFTIMM:
9313           shiftimm_alloc(&current,i);
9314           break;
9315         case MOV:
9316           mov_alloc(&current,i);
9317           break;
9318         case COP0:
9319           cop0_alloc(&current,i);
9320           break;
9321         case COP1:
9322         case COP2:
9323           cop1_alloc(&current,i);
9324           break;
9325         case C1LS:
9326           c1ls_alloc(&current,i);
9327           break;
9328         case C2LS:
9329           c2ls_alloc(&current,i);
9330           break;
9331         case C2OP:
9332           c2op_alloc(&current,i);
9333           break;
9334         case FCONV:
9335           fconv_alloc(&current,i);
9336           break;
9337         case FLOAT:
9338           float_alloc(&current,i);
9339           break;
9340         case FCOMP:
9341           fcomp_alloc(&current,i);
9342           break;
9343         case SYSCALL:
9344         case HLECALL:
9345         case INTCALL:
9346           syscall_alloc(&current,i);
9347           break;
9348         case SPAN:
9349           pagespan_alloc(&current,i);
9350           break;
9351       }
9352
9353       // Drop the upper half of registers that have become 32-bit
9354       current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
9355       if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9356         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9357         if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9358         current.uu|=1;
9359       } else {
9360         current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
9361         current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9362         if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9363         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9364         current.uu|=1;
9365       }
9366
9367       // Create entry (branch target) regmap
9368       for(hr=0;hr<HOST_REGS;hr++)
9369       {
9370         int r,or,er;
9371         r=current.regmap[hr];
9372         if(r>=0) {
9373           if(r!=regmap_pre[i][hr]) {
9374             // TODO: delay slot (?)
9375             or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9376             if(or<0||(r&63)>=TEMPREG){
9377               regs[i].regmap_entry[hr]=-1;
9378             }
9379             else
9380             {
9381               // Just move it to a different register
9382               regs[i].regmap_entry[hr]=r;
9383               // If it was dirty before, it's still dirty
9384               if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r&63);
9385             }
9386           }
9387           else
9388           {
9389             // Unneeded
9390             if(r==0){
9391               regs[i].regmap_entry[hr]=0;
9392             }
9393             else
9394             if(r<64){
9395               if((current.u>>r)&1) {
9396                 regs[i].regmap_entry[hr]=-1;
9397                 //regs[i].regmap[hr]=-1;
9398                 current.regmap[hr]=-1;
9399               }else
9400                 regs[i].regmap_entry[hr]=r;
9401             }
9402             else {
9403               if((current.uu>>(r&63))&1) {
9404                 regs[i].regmap_entry[hr]=-1;
9405                 //regs[i].regmap[hr]=-1;
9406                 current.regmap[hr]=-1;
9407               }else
9408                 regs[i].regmap_entry[hr]=r;
9409             }
9410           }
9411         } else {
9412           // Branches expect CCREG to be allocated at the target
9413           if(regmap_pre[i][hr]==CCREG)
9414             regs[i].regmap_entry[hr]=CCREG;
9415           else
9416             regs[i].regmap_entry[hr]=-1;
9417         }
9418       }
9419       memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9420     }
9421     /* Branch post-alloc */
9422     if(i>0)
9423     {
9424       current.was32=current.is32;
9425       current.wasdirty=current.dirty;
9426       switch(itype[i-1]) {
9427         case UJUMP:
9428           memcpy(&branch_regs[i-1],&current,sizeof(current));
9429           branch_regs[i-1].isconst=0;
9430           branch_regs[i-1].wasconst=0;
9431           branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9432           branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9433           alloc_cc(&branch_regs[i-1],i-1);
9434           dirty_reg(&branch_regs[i-1],CCREG);
9435           if(rt1[i-1]==31) { // JAL
9436             alloc_reg(&branch_regs[i-1],i-1,31);
9437             dirty_reg(&branch_regs[i-1],31);
9438             branch_regs[i-1].is32|=1LL<<31;
9439           }
9440           memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9441           memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9442           break;
9443         case RJUMP:
9444           memcpy(&branch_regs[i-1],&current,sizeof(current));
9445           branch_regs[i-1].isconst=0;
9446           branch_regs[i-1].wasconst=0;
9447           branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9448           branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9449           alloc_cc(&branch_regs[i-1],i-1);
9450           dirty_reg(&branch_regs[i-1],CCREG);
9451           alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
9452           if(rt1[i-1]!=0) { // JALR
9453             alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9454             dirty_reg(&branch_regs[i-1],rt1[i-1]);
9455             branch_regs[i-1].is32|=1LL<<rt1[i-1];
9456           }
9457           #ifdef USE_MINI_HT
9458           if(rs1[i-1]==31) { // JALR
9459             alloc_reg(&branch_regs[i-1],i-1,RHASH);
9460             #ifndef HOST_IMM_ADDR32
9461             alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9462             #endif
9463           }
9464           #endif
9465           memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9466           memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9467           break;
9468         case CJUMP:
9469           if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9470           {
9471             alloc_cc(&current,i-1);
9472             dirty_reg(&current,CCREG);
9473             if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9474                (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9475               // The delay slot overwrote one of our conditions
9476               // Delay slot goes after the test (in order)
9477               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9478               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9479               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9480               current.u|=1;
9481               current.uu|=1;
9482               delayslot_alloc(&current,i);
9483               current.isconst=0;
9484             }
9485             else
9486             {
9487               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9488               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9489               // Alloc the branch condition registers
9490               if(rs1[i-1]) alloc_reg(&current,i-1,rs1[i-1]);
9491               if(rs2[i-1]) alloc_reg(&current,i-1,rs2[i-1]);
9492               if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9493               {
9494                 if(rs1[i-1]) alloc_reg64(&current,i-1,rs1[i-1]);
9495                 if(rs2[i-1]) alloc_reg64(&current,i-1,rs2[i-1]);
9496               }
9497             }
9498             memcpy(&branch_regs[i-1],&current,sizeof(current));
9499             branch_regs[i-1].isconst=0;
9500             branch_regs[i-1].wasconst=0;
9501             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9502             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9503           }
9504           else
9505           if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9506           {
9507             alloc_cc(&current,i-1);
9508             dirty_reg(&current,CCREG);
9509             if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9510               // The delay slot overwrote the branch condition
9511               // Delay slot goes after the test (in order)
9512               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9513               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9514               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9515               current.u|=1;
9516               current.uu|=1;
9517               delayslot_alloc(&current,i);
9518               current.isconst=0;
9519             }
9520             else
9521             {
9522               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9523               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9524               // Alloc the branch condition register
9525               alloc_reg(&current,i-1,rs1[i-1]);
9526               if(!(current.is32>>rs1[i-1]&1))
9527               {
9528                 alloc_reg64(&current,i-1,rs1[i-1]);
9529               }
9530             }
9531             memcpy(&branch_regs[i-1],&current,sizeof(current));
9532             branch_regs[i-1].isconst=0;
9533             branch_regs[i-1].wasconst=0;
9534             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9535             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9536           }
9537           else
9538           // Alloc the delay slot in case the branch is taken
9539           if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9540           {
9541             memcpy(&branch_regs[i-1],&current,sizeof(current));
9542             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9543             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9544             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9545             alloc_cc(&branch_regs[i-1],i);
9546             dirty_reg(&branch_regs[i-1],CCREG);
9547             delayslot_alloc(&branch_regs[i-1],i);
9548             branch_regs[i-1].isconst=0;
9549             alloc_reg(&current,i,CCREG); // Not taken path
9550             dirty_reg(&current,CCREG);
9551             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9552           }
9553           else
9554           if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9555           {
9556             memcpy(&branch_regs[i-1],&current,sizeof(current));
9557             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9558             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9559             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9560             alloc_cc(&branch_regs[i-1],i);
9561             dirty_reg(&branch_regs[i-1],CCREG);
9562             delayslot_alloc(&branch_regs[i-1],i);
9563             branch_regs[i-1].isconst=0;
9564             alloc_reg(&current,i,CCREG); // Not taken path
9565             dirty_reg(&current,CCREG);
9566             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9567           }
9568           break;
9569         case SJUMP:
9570           //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9571           if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9572           {
9573             alloc_cc(&current,i-1);
9574             dirty_reg(&current,CCREG);
9575             if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9576               // The delay slot overwrote the branch condition
9577               // Delay slot goes after the test (in order)
9578               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9579               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9580               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9581               current.u|=1;
9582               current.uu|=1;
9583               delayslot_alloc(&current,i);
9584               current.isconst=0;
9585             }
9586             else
9587             {
9588               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9589               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9590               // Alloc the branch condition register
9591               alloc_reg(&current,i-1,rs1[i-1]);
9592               if(!(current.is32>>rs1[i-1]&1))
9593               {
9594                 alloc_reg64(&current,i-1,rs1[i-1]);
9595               }
9596             }
9597             memcpy(&branch_regs[i-1],&current,sizeof(current));
9598             branch_regs[i-1].isconst=0;
9599             branch_regs[i-1].wasconst=0;
9600             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9601             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9602           }
9603           else
9604           // Alloc the delay slot in case the branch is taken
9605           if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9606           {
9607             memcpy(&branch_regs[i-1],&current,sizeof(current));
9608             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9609             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9610             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9611             alloc_cc(&branch_regs[i-1],i);
9612             dirty_reg(&branch_regs[i-1],CCREG);
9613             delayslot_alloc(&branch_regs[i-1],i);
9614             branch_regs[i-1].isconst=0;
9615             alloc_reg(&current,i,CCREG); // Not taken path
9616             dirty_reg(&current,CCREG);
9617             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9618           }
9619           // FIXME: BLTZAL/BGEZAL
9620           if(opcode2[i-1]&0x10) { // BxxZAL
9621             alloc_reg(&branch_regs[i-1],i-1,31);
9622             dirty_reg(&branch_regs[i-1],31);
9623             branch_regs[i-1].is32|=1LL<<31;
9624           }
9625           break;
9626         case FJUMP:
9627           if(likely[i-1]==0) // BC1F/BC1T
9628           {
9629             alloc_cc(&current,i-1);
9630             dirty_reg(&current,CCREG);
9631             if(itype[i]==FCOMP) {
9632               // The delay slot overwrote the branch condition
9633               // Delay slot goes after the test (in order)
9634               delayslot_alloc(&current,i);
9635               current.isconst=0;
9636             }
9637             else
9638             {
9639               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9640               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9641               // Alloc the branch condition register
9642               alloc_reg(&current,i-1,FSREG);
9643             }
9644             memcpy(&branch_regs[i-1],&current,sizeof(current));
9645             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9646           }
9647           else // BC1FL/BC1TL
9648           {
9649             // Alloc the delay slot in case the branch is taken
9650             memcpy(&branch_regs[i-1],&current,sizeof(current));
9651             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9652             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9653             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9654             alloc_cc(&branch_regs[i-1],i);
9655             dirty_reg(&branch_regs[i-1],CCREG);
9656             delayslot_alloc(&branch_regs[i-1],i);
9657             branch_regs[i-1].isconst=0;
9658             alloc_reg(&current,i,CCREG); // Not taken path
9659             dirty_reg(&current,CCREG);
9660             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9661           }
9662           break;
9663       }
9664
9665       if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9666       {
9667         if(rt1[i-1]==31) // JAL/JALR
9668         {
9669           // Subroutine call will return here, don't alloc any registers
9670           current.is32=1;
9671           current.dirty=0;
9672           clear_all_regs(current.regmap);
9673           alloc_reg(&current,i,CCREG);
9674           dirty_reg(&current,CCREG);
9675         }
9676         else if(i+1<slen)
9677         {
9678           // Internal branch will jump here, match registers to caller
9679           current.is32=0x3FFFFFFFFLL;
9680           current.dirty=0;
9681           clear_all_regs(current.regmap);
9682           alloc_reg(&current,i,CCREG);
9683           dirty_reg(&current,CCREG);
9684           for(j=i-1;j>=0;j--)
9685           {
9686             if(ba[j]==start+i*4+4) {
9687               memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9688               current.is32=branch_regs[j].is32;
9689               current.dirty=branch_regs[j].dirty;
9690               break;
9691             }
9692           }
9693           while(j>=0) {
9694             if(ba[j]==start+i*4+4) {
9695               for(hr=0;hr<HOST_REGS;hr++) {
9696                 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9697                   current.regmap[hr]=-1;
9698                 }
9699                 current.is32&=branch_regs[j].is32;
9700                 current.dirty&=branch_regs[j].dirty;
9701               }
9702             }
9703             j--;
9704           }
9705         }
9706       }
9707     }
9708
9709     // Count cycles in between branches
9710     ccadj[i]=cc;
9711     if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
9712     {
9713       cc=0;
9714     }
9715 #ifdef PCSX
9716     else if(/*itype[i]==LOAD||*/itype[i]==STORE||itype[i]==C1LS) // load causes weird timing issues
9717     {
9718       cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
9719     }
9720     else if(itype[i]==C2LS)
9721     {
9722       cc+=4;
9723     }
9724 #endif
9725     else
9726     {
9727       cc++;
9728     }
9729
9730     flush_dirty_uppers(&current);
9731     if(!is_ds[i]) {
9732       regs[i].is32=current.is32;
9733       regs[i].dirty=current.dirty;
9734       regs[i].isconst=current.isconst;
9735       memcpy(constmap[i],current.constmap,sizeof(current.constmap));
9736     }
9737     for(hr=0;hr<HOST_REGS;hr++) {
9738       if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
9739         if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9740           regs[i].wasconst&=~(1<<hr);
9741         }
9742       }
9743     }
9744     if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9745   }
9746
9747   /* Pass 4 - Cull unused host registers */
9748
9749   uint64_t nr=0;
9750
9751   for (i=slen-1;i>=0;i--)
9752   {
9753     int hr;
9754     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9755     {
9756       if(ba[i]<start || ba[i]>=(start+slen*4))
9757       {
9758         // Branch out of this block, don't need anything
9759         nr=0;
9760       }
9761       else
9762       {
9763         // Internal branch
9764         // Need whatever matches the target
9765         nr=0;
9766         int t=(ba[i]-start)>>2;
9767         for(hr=0;hr<HOST_REGS;hr++)
9768         {
9769           if(regs[i].regmap_entry[hr]>=0) {
9770             if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9771           }
9772         }
9773       }
9774       // Conditional branch may need registers for following instructions
9775       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9776       {
9777         if(i<slen-2) {
9778           nr|=needed_reg[i+2];
9779           for(hr=0;hr<HOST_REGS;hr++)
9780           {
9781             if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9782             //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9783           }
9784         }
9785       }
9786       // Don't need stuff which is overwritten
9787       //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9788       //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9789       // Merge in delay slot
9790       for(hr=0;hr<HOST_REGS;hr++)
9791       {
9792         if(!likely[i]) {
9793           // These are overwritten unless the branch is "likely"
9794           // and the delay slot is nullified if not taken
9795           if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9796           if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9797         }
9798         if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9799         if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9800         if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9801         if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9802         if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9803         if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9804         if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9805         if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9806         if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9807           if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9808           if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9809         }
9810         if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9811           if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9812           if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9813         }
9814         if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
9815           if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9816           if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9817         }
9818       }
9819     }
9820     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
9821     {
9822       // SYSCALL instruction (software interrupt)
9823       nr=0;
9824     }
9825     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9826     {
9827       // ERET instruction (return from interrupt)
9828       nr=0;
9829     }
9830     else // Non-branch
9831     {
9832       if(i<slen-1) {
9833         for(hr=0;hr<HOST_REGS;hr++) {
9834           if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9835           if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9836           if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9837           if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9838         }
9839       }
9840     }
9841     for(hr=0;hr<HOST_REGS;hr++)
9842     {
9843       // Overwritten registers are not needed
9844       if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9845       if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9846       if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9847       // Source registers are needed
9848       if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9849       if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9850       if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9851       if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9852       if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9853       if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9854       if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9855       if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9856       if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9857         if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9858         if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9859       }
9860       if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
9861         if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9862         if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9863       }
9864       if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
9865         if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9866         if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9867       }
9868       // Don't store a register immediately after writing it,
9869       // may prevent dual-issue.
9870       // But do so if this is a branch target, otherwise we
9871       // might have to load the register before the branch.
9872       if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
9873         if((regmap_pre[i][hr]>0&&regmap_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
9874            (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
9875           if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9876           if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9877         }
9878         if((regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
9879            (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
9880           if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9881           if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9882         }
9883       }
9884     }
9885     // Cycle count is needed at branches.  Assume it is needed at the target too.
9886     if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
9887       if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9888       if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9889     }
9890     // Save it
9891     needed_reg[i]=nr;
9892
9893     // Deallocate unneeded registers
9894     for(hr=0;hr<HOST_REGS;hr++)
9895     {
9896       if(!((nr>>hr)&1)) {
9897         if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
9898         if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9899            (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9900            (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
9901         {
9902           if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9903           {
9904             if(likely[i]) {
9905               regs[i].regmap[hr]=-1;
9906               regs[i].isconst&=~(1<<hr);
9907               if(i<slen-2) {
9908                 regmap_pre[i+2][hr]=-1;
9909                 regs[i+2].wasconst&=~(1<<hr);
9910               }
9911             }
9912           }
9913         }
9914         if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9915         {
9916           int d1=0,d2=0,map=0,temp=0;
9917           if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
9918           {
9919             d1=dep1[i+1];
9920             d2=dep2[i+1];
9921           }
9922           if(using_tlb) {
9923             if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
9924                itype[i+1]==STORE || itype[i+1]==STORELR ||
9925                itype[i+1]==C1LS || itype[i+1]==C2LS)
9926             map=TLREG;
9927           } else
9928           if(itype[i+1]==STORE || itype[i+1]==STORELR ||
9929              (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
9930             map=INVCP;
9931           }
9932           if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
9933              itype[i+1]==C1LS || itype[i+1]==C2LS)
9934             temp=FTEMP;
9935           if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9936              (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9937              (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
9938              (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
9939              (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9940              regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
9941              (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
9942              regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
9943              regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
9944              regs[i].regmap[hr]!=map )
9945           {
9946             regs[i].regmap[hr]=-1;
9947             regs[i].isconst&=~(1<<hr);
9948             if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
9949                (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
9950                (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
9951                (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
9952                (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
9953                branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
9954                (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
9955                branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
9956                branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
9957                branch_regs[i].regmap[hr]!=map)
9958             {
9959               branch_regs[i].regmap[hr]=-1;
9960               branch_regs[i].regmap_entry[hr]=-1;
9961               if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9962               {
9963                 if(!likely[i]&&i<slen-2) {
9964                   regmap_pre[i+2][hr]=-1;
9965                   regs[i+2].wasconst&=~(1<<hr);
9966                 }
9967               }
9968             }
9969           }
9970         }
9971         else
9972         {
9973           // Non-branch
9974           if(i>0)
9975           {
9976             int d1=0,d2=0,map=-1,temp=-1;
9977             if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
9978             {
9979               d1=dep1[i];
9980               d2=dep2[i];
9981             }
9982             if(using_tlb) {
9983               if(itype[i]==LOAD || itype[i]==LOADLR ||
9984                  itype[i]==STORE || itype[i]==STORELR ||
9985                  itype[i]==C1LS || itype[i]==C2LS)
9986               map=TLREG;
9987             } else if(itype[i]==STORE || itype[i]==STORELR ||
9988                       (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
9989               map=INVCP;
9990             }
9991             if(itype[i]==LOADLR || itype[i]==STORELR ||
9992                itype[i]==C1LS || itype[i]==C2LS)
9993               temp=FTEMP;
9994             if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9995                (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
9996                (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9997                regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
9998                (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
9999                (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
10000             {
10001               if(i<slen-1&&!is_ds[i]) {
10002                 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
10003                 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
10004                 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
10005                 {
10006                   printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
10007                   assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
10008                 }
10009                 regmap_pre[i+1][hr]=-1;
10010                 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
10011                 regs[i+1].wasconst&=~(1<<hr);
10012               }
10013               regs[i].regmap[hr]=-1;
10014               regs[i].isconst&=~(1<<hr);
10015             }
10016           }
10017         }
10018       }
10019     }
10020   }
10021
10022   /* Pass 5 - Pre-allocate registers */
10023
10024   // If a register is allocated during a loop, try to allocate it for the
10025   // entire loop, if possible.  This avoids loading/storing registers
10026   // inside of the loop.
10027
10028   signed char f_regmap[HOST_REGS];
10029   clear_all_regs(f_regmap);
10030   for(i=0;i<slen-1;i++)
10031   {
10032     if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10033     {
10034       if(ba[i]>=start && ba[i]<(start+i*4))
10035       if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
10036       ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
10037       ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
10038       ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
10039       ||itype[i+1]==FCOMP||itype[i+1]==FCONV
10040       ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
10041       {
10042         int t=(ba[i]-start)>>2;
10043         if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
10044         if(t<2||(itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||rt1[t-2]!=31) // call/ret assumes no registers allocated
10045         for(hr=0;hr<HOST_REGS;hr++)
10046         {
10047           if(regs[i].regmap[hr]>64) {
10048             if(!((regs[i].dirty>>hr)&1))
10049               f_regmap[hr]=regs[i].regmap[hr];
10050             else f_regmap[hr]=-1;
10051           }
10052           else if(regs[i].regmap[hr]>=0) {
10053             if(f_regmap[hr]!=regs[i].regmap[hr]) {
10054               // dealloc old register
10055               int n;
10056               for(n=0;n<HOST_REGS;n++)
10057               {
10058                 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10059               }
10060               // and alloc new one
10061               f_regmap[hr]=regs[i].regmap[hr];
10062             }
10063           }
10064           if(branch_regs[i].regmap[hr]>64) {
10065             if(!((branch_regs[i].dirty>>hr)&1))
10066               f_regmap[hr]=branch_regs[i].regmap[hr];
10067             else f_regmap[hr]=-1;
10068           }
10069           else if(branch_regs[i].regmap[hr]>=0) {
10070             if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
10071               // dealloc old register
10072               int n;
10073               for(n=0;n<HOST_REGS;n++)
10074               {
10075                 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
10076               }
10077               // and alloc new one
10078               f_regmap[hr]=branch_regs[i].regmap[hr];
10079             }
10080           }
10081           if(ooo[i]) {
10082             if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
10083               f_regmap[hr]=branch_regs[i].regmap[hr];
10084           }else{
10085             if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
10086               f_regmap[hr]=branch_regs[i].regmap[hr];
10087           }
10088           // Avoid dirty->clean transition
10089           #ifdef DESTRUCTIVE_WRITEBACK
10090           if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
10091           #endif
10092           // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
10093           // case above, however it's always a good idea.  We can't hoist the
10094           // load if the register was already allocated, so there's no point
10095           // wasting time analyzing most of these cases.  It only "succeeds"
10096           // when the mapping was different and the load can be replaced with
10097           // a mov, which is of negligible benefit.  So such cases are
10098           // skipped below.
10099           if(f_regmap[hr]>0) {
10100             if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
10101               int r=f_regmap[hr];
10102               for(j=t;j<=i;j++)
10103               {
10104                 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10105                 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
10106                 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
10107                 if(r>63) {
10108                   // NB This can exclude the case where the upper-half
10109                   // register is lower numbered than the lower-half
10110                   // register.  Not sure if it's worth fixing...
10111                   if(get_reg(regs[j].regmap,r&63)<0) break;
10112                   if(get_reg(regs[j].regmap_entry,r&63)<0) break;
10113                   if(regs[j].is32&(1LL<<(r&63))) break;
10114                 }
10115                 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
10116                   //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10117                   int k;
10118                   if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
10119                     if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
10120                     if(r>63) {
10121                       if(get_reg(regs[i].regmap,r&63)<0) break;
10122                       if(get_reg(branch_regs[i].regmap,r&63)<0) break;
10123                     }
10124                     k=i;
10125                     while(k>1&&regs[k-1].regmap[hr]==-1) {
10126                       if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10127                         //printf("no free regs for store %x\n",start+(k-1)*4);
10128                         break;
10129                       }
10130                       if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
10131                         //printf("no-match due to different register\n");
10132                         break;
10133                       }
10134                       if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
10135                         //printf("no-match due to branch\n");
10136                         break;
10137                       }
10138                       // call/ret fast path assumes no registers allocated
10139                       if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)&&rt1[k-3]==31) {
10140                         break;
10141                       }
10142                       if(r>63) {
10143                         // NB This can exclude the case where the upper-half
10144                         // register is lower numbered than the lower-half
10145                         // register.  Not sure if it's worth fixing...
10146                         if(get_reg(regs[k-1].regmap,r&63)<0) break;
10147                         if(regs[k-1].is32&(1LL<<(r&63))) break;
10148                       }
10149                       k--;
10150                     }
10151                     if(i<slen-1) {
10152                       if((regs[k].is32&(1LL<<f_regmap[hr]))!=
10153                         (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
10154                         //printf("bad match after branch\n");
10155                         break;
10156                       }
10157                     }
10158                     if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
10159                       //printf("Extend r%d, %x ->\n",hr,start+k*4);
10160                       while(k<i) {
10161                         regs[k].regmap_entry[hr]=f_regmap[hr];
10162                         regs[k].regmap[hr]=f_regmap[hr];
10163                         regmap_pre[k+1][hr]=f_regmap[hr];
10164                         regs[k].wasdirty&=~(1<<hr);
10165                         regs[k].dirty&=~(1<<hr);
10166                         regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
10167                         regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
10168                         regs[k].wasconst&=~(1<<hr);
10169                         regs[k].isconst&=~(1<<hr);
10170                         k++;
10171                       }
10172                     }
10173                     else {
10174                       //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
10175                       break;
10176                     }
10177                     assert(regs[i-1].regmap[hr]==f_regmap[hr]);
10178                     if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
10179                       //printf("OK fill %x (r%d)\n",start+i*4,hr);
10180                       regs[i].regmap_entry[hr]=f_regmap[hr];
10181                       regs[i].regmap[hr]=f_regmap[hr];
10182                       regs[i].wasdirty&=~(1<<hr);
10183                       regs[i].dirty&=~(1<<hr);
10184                       regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
10185                       regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
10186                       regs[i].wasconst&=~(1<<hr);
10187                       regs[i].isconst&=~(1<<hr);
10188                       branch_regs[i].regmap_entry[hr]=f_regmap[hr];
10189                       branch_regs[i].wasdirty&=~(1<<hr);
10190                       branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
10191                       branch_regs[i].regmap[hr]=f_regmap[hr];
10192                       branch_regs[i].dirty&=~(1<<hr);
10193                       branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
10194                       branch_regs[i].wasconst&=~(1<<hr);
10195                       branch_regs[i].isconst&=~(1<<hr);
10196                       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
10197                         regmap_pre[i+2][hr]=f_regmap[hr];
10198                         regs[i+2].wasdirty&=~(1<<hr);
10199                         regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
10200                         assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
10201                           (regs[i+2].was32&(1LL<<f_regmap[hr])));
10202                       }
10203                     }
10204                   }
10205                   for(k=t;k<j;k++) {
10206                     // Alloc register clean at beginning of loop,
10207                     // but may dirty it in pass 6
10208                     regs[k].regmap_entry[hr]=f_regmap[hr];
10209                     regs[k].regmap[hr]=f_regmap[hr];
10210                     regs[k].dirty&=~(1<<hr);
10211                     regs[k].wasconst&=~(1<<hr);
10212                     regs[k].isconst&=~(1<<hr);
10213                     if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) {
10214                       branch_regs[k].regmap_entry[hr]=f_regmap[hr];
10215                       branch_regs[k].regmap[hr]=f_regmap[hr];
10216                       branch_regs[k].dirty&=~(1<<hr);
10217                       branch_regs[k].wasconst&=~(1<<hr);
10218                       branch_regs[k].isconst&=~(1<<hr);
10219                       if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
10220                         regmap_pre[k+2][hr]=f_regmap[hr];
10221                         regs[k+2].wasdirty&=~(1<<hr);
10222                         assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))==
10223                           (regs[k+2].was32&(1LL<<f_regmap[hr])));
10224                       }
10225                     }
10226                     else
10227                     {
10228                       regmap_pre[k+1][hr]=f_regmap[hr];
10229                       regs[k+1].wasdirty&=~(1<<hr);
10230                     }
10231                   }
10232                   if(regs[j].regmap[hr]==f_regmap[hr])
10233                     regs[j].regmap_entry[hr]=f_regmap[hr];
10234                   break;
10235                 }
10236                 if(j==i) break;
10237                 if(regs[j].regmap[hr]>=0)
10238                   break;
10239                 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
10240                   //printf("no-match due to different register\n");
10241                   break;
10242                 }
10243                 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
10244                   //printf("32/64 mismatch %x %d\n",start+j*4,hr);
10245                   break;
10246                 }
10247                 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10248                 {
10249                   // Stop on unconditional branch
10250                   break;
10251                 }
10252                 if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
10253                 {
10254                   if(ooo[j]) {
10255                     if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
10256                       break;
10257                   }else{
10258                     if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
10259                       break;
10260                   }
10261                   if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
10262                     //printf("no-match due to different register (branch)\n");
10263                     break;
10264                   }
10265                 }
10266                 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10267                   //printf("No free regs for store %x\n",start+j*4);
10268                   break;
10269                 }
10270                 if(f_regmap[hr]>=64) {
10271                   if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
10272                     break;
10273                   }
10274                   else
10275                   {
10276                     if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
10277                       break;
10278                     }
10279                   }
10280                 }
10281               }
10282             }
10283           }
10284         }
10285       }
10286     }else{
10287       // Non branch or undetermined branch target
10288       for(hr=0;hr<HOST_REGS;hr++)
10289       {
10290         if(hr!=EXCLUDE_REG) {
10291           if(regs[i].regmap[hr]>64) {
10292             if(!((regs[i].dirty>>hr)&1))
10293               f_regmap[hr]=regs[i].regmap[hr];
10294           }
10295           else if(regs[i].regmap[hr]>=0) {
10296             if(f_regmap[hr]!=regs[i].regmap[hr]) {
10297               // dealloc old register
10298               int n;
10299               for(n=0;n<HOST_REGS;n++)
10300               {
10301                 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10302               }
10303               // and alloc new one
10304               f_regmap[hr]=regs[i].regmap[hr];
10305             }
10306           }
10307         }
10308       }
10309       // Try to restore cycle count at branch targets
10310       if(bt[i]) {
10311         for(j=i;j<slen-1;j++) {
10312           if(regs[j].regmap[HOST_CCREG]!=-1) break;
10313           if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10314             //printf("no free regs for store %x\n",start+j*4);
10315             break;
10316           }
10317         }
10318         if(regs[j].regmap[HOST_CCREG]==CCREG) {
10319           int k=i;
10320           //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
10321           while(k<j) {
10322             regs[k].regmap_entry[HOST_CCREG]=CCREG;
10323             regs[k].regmap[HOST_CCREG]=CCREG;
10324             regmap_pre[k+1][HOST_CCREG]=CCREG;
10325             regs[k+1].wasdirty|=1<<HOST_CCREG;
10326             regs[k].dirty|=1<<HOST_CCREG;
10327             regs[k].wasconst&=~(1<<HOST_CCREG);
10328             regs[k].isconst&=~(1<<HOST_CCREG);
10329             k++;
10330           }
10331           regs[j].regmap_entry[HOST_CCREG]=CCREG;
10332         }
10333         // Work backwards from the branch target
10334         if(j>i&&f_regmap[HOST_CCREG]==CCREG)
10335         {
10336           //printf("Extend backwards\n");
10337           int k;
10338           k=i;
10339           while(regs[k-1].regmap[HOST_CCREG]==-1) {
10340             if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10341               //printf("no free regs for store %x\n",start+(k-1)*4);
10342               break;
10343             }
10344             k--;
10345           }
10346           if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
10347             //printf("Extend CC, %x ->\n",start+k*4);
10348             while(k<=i) {
10349               regs[k].regmap_entry[HOST_CCREG]=CCREG;
10350               regs[k].regmap[HOST_CCREG]=CCREG;
10351               regmap_pre[k+1][HOST_CCREG]=CCREG;
10352               regs[k+1].wasdirty|=1<<HOST_CCREG;
10353               regs[k].dirty|=1<<HOST_CCREG;
10354               regs[k].wasconst&=~(1<<HOST_CCREG);
10355               regs[k].isconst&=~(1<<HOST_CCREG);
10356               k++;
10357             }
10358           }
10359           else {
10360             //printf("Fail Extend CC, %x ->\n",start+k*4);
10361           }
10362         }
10363       }
10364       if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
10365          itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
10366          itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
10367          itype[i]!=FCONV&&itype[i]!=FCOMP)
10368       {
10369         memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
10370       }
10371     }
10372   }
10373
10374   // Cache memory offset or tlb map pointer if a register is available
10375   #ifndef HOST_IMM_ADDR32
10376   #ifndef RAM_OFFSET
10377   if(using_tlb)
10378   #endif
10379   {
10380     int earliest_available[HOST_REGS];
10381     int loop_start[HOST_REGS];
10382     int score[HOST_REGS];
10383     int end[HOST_REGS];
10384     int reg=using_tlb?MMREG:ROREG;
10385
10386     // Init
10387     for(hr=0;hr<HOST_REGS;hr++) {
10388       score[hr]=0;earliest_available[hr]=0;
10389       loop_start[hr]=MAXBLOCK;
10390     }
10391     for(i=0;i<slen-1;i++)
10392     {
10393       // Can't do anything if no registers are available
10394       if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i]) {
10395         for(hr=0;hr<HOST_REGS;hr++) {
10396           score[hr]=0;earliest_available[hr]=i+1;
10397           loop_start[hr]=MAXBLOCK;
10398         }
10399       }
10400       if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10401         if(!ooo[i]) {
10402           if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) {
10403             for(hr=0;hr<HOST_REGS;hr++) {
10404               score[hr]=0;earliest_available[hr]=i+1;
10405               loop_start[hr]=MAXBLOCK;
10406             }
10407           }
10408         }else{
10409           if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) {
10410             for(hr=0;hr<HOST_REGS;hr++) {
10411               score[hr]=0;earliest_available[hr]=i+1;
10412               loop_start[hr]=MAXBLOCK;
10413             }
10414           }
10415         }
10416       }
10417       // Mark unavailable registers
10418       for(hr=0;hr<HOST_REGS;hr++) {
10419         if(regs[i].regmap[hr]>=0) {
10420           score[hr]=0;earliest_available[hr]=i+1;
10421           loop_start[hr]=MAXBLOCK;
10422         }
10423         if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10424           if(branch_regs[i].regmap[hr]>=0) {
10425             score[hr]=0;earliest_available[hr]=i+2;
10426             loop_start[hr]=MAXBLOCK;
10427           }
10428         }
10429       }
10430       // No register allocations after unconditional jumps
10431       if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10432       {
10433         for(hr=0;hr<HOST_REGS;hr++) {
10434           score[hr]=0;earliest_available[hr]=i+2;
10435           loop_start[hr]=MAXBLOCK;
10436         }
10437         i++; // Skip delay slot too
10438         //printf("skip delay slot: %x\n",start+i*4);
10439       }
10440       else
10441       // Possible match
10442       if(itype[i]==LOAD||itype[i]==LOADLR||
10443          itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) {
10444         for(hr=0;hr<HOST_REGS;hr++) {
10445           if(hr!=EXCLUDE_REG) {
10446             end[hr]=i-1;
10447             for(j=i;j<slen-1;j++) {
10448               if(regs[j].regmap[hr]>=0) break;
10449               if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10450                 if(branch_regs[j].regmap[hr]>=0) break;
10451                 if(ooo[j]) {
10452                   if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) break;
10453                 }else{
10454                   if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) break;
10455                 }
10456               }
10457               else if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) break;
10458               if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10459                 int t=(ba[j]-start)>>2;
10460                 if(t<j&&t>=earliest_available[hr]) {
10461                   if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) { // call/ret assumes no registers allocated
10462                     // Score a point for hoisting loop invariant
10463                     if(t<loop_start[hr]) loop_start[hr]=t;
10464                     //printf("set loop_start: i=%x j=%x (%x)\n",start+i*4,start+j*4,start+t*4);
10465                     score[hr]++;
10466                     end[hr]=j;
10467                   }
10468                 }
10469                 else if(t<j) {
10470                   if(regs[t].regmap[hr]==reg) {
10471                     // Score a point if the branch target matches this register
10472                     score[hr]++;
10473                     end[hr]=j;
10474                   }
10475                 }
10476                 if(itype[j+1]==LOAD||itype[j+1]==LOADLR||
10477                    itype[j+1]==STORE||itype[j+1]==STORELR||itype[j+1]==C1LS) {
10478                   score[hr]++;
10479                   end[hr]=j;
10480                 }
10481               }
10482               if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10483               {
10484                 // Stop on unconditional branch
10485                 break;
10486               }
10487               else
10488               if(itype[j]==LOAD||itype[j]==LOADLR||
10489                  itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS) {
10490                 score[hr]++;
10491                 end[hr]=j;
10492               }
10493             }
10494           }
10495         }
10496         // Find highest score and allocate that register
10497         int maxscore=0;
10498         for(hr=0;hr<HOST_REGS;hr++) {
10499           if(hr!=EXCLUDE_REG) {
10500             if(score[hr]>score[maxscore]) {
10501               maxscore=hr;
10502               //printf("highest score: %d %d (%x->%x)\n",score[hr],hr,start+i*4,start+end[hr]*4);
10503             }
10504           }
10505         }
10506         if(score[maxscore]>1)
10507         {
10508           if(i<loop_start[maxscore]) loop_start[maxscore]=i;
10509           for(j=loop_start[maxscore];j<slen&&j<=end[maxscore];j++) {
10510             //if(regs[j].regmap[maxscore]>=0) {printf("oops: %x %x was %d=%d\n",loop_start[maxscore]*4+start,j*4+start,maxscore,regs[j].regmap[maxscore]);}
10511             assert(regs[j].regmap[maxscore]<0);
10512             if(j>loop_start[maxscore]) regs[j].regmap_entry[maxscore]=reg;
10513             regs[j].regmap[maxscore]=reg;
10514             regs[j].dirty&=~(1<<maxscore);
10515             regs[j].wasconst&=~(1<<maxscore);
10516             regs[j].isconst&=~(1<<maxscore);
10517             if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10518               branch_regs[j].regmap[maxscore]=reg;
10519               branch_regs[j].wasdirty&=~(1<<maxscore);
10520               branch_regs[j].dirty&=~(1<<maxscore);
10521               branch_regs[j].wasconst&=~(1<<maxscore);
10522               branch_regs[j].isconst&=~(1<<maxscore);
10523               if(itype[j]!=RJUMP&&itype[j]!=UJUMP&&(source[j]>>16)!=0x1000) {
10524                 regmap_pre[j+2][maxscore]=reg;
10525                 regs[j+2].wasdirty&=~(1<<maxscore);
10526               }
10527               // loop optimization (loop_preload)
10528               int t=(ba[j]-start)>>2;
10529               if(t==loop_start[maxscore]) {
10530                 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) // call/ret assumes no registers allocated
10531                   regs[t].regmap_entry[maxscore]=reg;
10532               }
10533             }
10534             else
10535             {
10536               if(j<1||(itype[j-1]!=RJUMP&&itype[j-1]!=UJUMP&&itype[j-1]!=CJUMP&&itype[j-1]!=SJUMP&&itype[j-1]!=FJUMP)) {
10537                 regmap_pre[j+1][maxscore]=reg;
10538                 regs[j+1].wasdirty&=~(1<<maxscore);
10539               }
10540             }
10541           }
10542           i=j-1;
10543           if(itype[j-1]==RJUMP||itype[j-1]==UJUMP||itype[j-1]==CJUMP||itype[j-1]==SJUMP||itype[j-1]==FJUMP) i++; // skip delay slot
10544           for(hr=0;hr<HOST_REGS;hr++) {
10545             score[hr]=0;earliest_available[hr]=i+i;
10546             loop_start[hr]=MAXBLOCK;
10547           }
10548         }
10549       }
10550     }
10551   }
10552   #endif
10553
10554   // This allocates registers (if possible) one instruction prior
10555   // to use, which can avoid a load-use penalty on certain CPUs.
10556   for(i=0;i<slen-1;i++)
10557   {
10558     if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10559     {
10560       if(!bt[i+1])
10561       {
10562         if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
10563            ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
10564         {
10565           if(rs1[i+1]) {
10566             if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10567             {
10568               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10569               {
10570                 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10571                 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10572                 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10573                 regs[i].isconst&=~(1<<hr);
10574                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10575                 constmap[i][hr]=constmap[i+1][hr];
10576                 regs[i+1].wasdirty&=~(1<<hr);
10577                 regs[i].dirty&=~(1<<hr);
10578               }
10579             }
10580           }
10581           if(rs2[i+1]) {
10582             if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10583             {
10584               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10585               {
10586                 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10587                 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10588                 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10589                 regs[i].isconst&=~(1<<hr);
10590                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10591                 constmap[i][hr]=constmap[i+1][hr];
10592                 regs[i+1].wasdirty&=~(1<<hr);
10593                 regs[i].dirty&=~(1<<hr);
10594               }
10595             }
10596           }
10597           // Preload target address for load instruction (non-constant)
10598           if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10599             if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10600             {
10601               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10602               {
10603                 regs[i].regmap[hr]=rs1[i+1];
10604                 regmap_pre[i+1][hr]=rs1[i+1];
10605                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10606                 regs[i].isconst&=~(1<<hr);
10607                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10608                 constmap[i][hr]=constmap[i+1][hr];
10609                 regs[i+1].wasdirty&=~(1<<hr);
10610                 regs[i].dirty&=~(1<<hr);
10611               }
10612             }
10613           }
10614           // Load source into target register
10615           if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10616             if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10617             {
10618               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10619               {
10620                 regs[i].regmap[hr]=rs1[i+1];
10621                 regmap_pre[i+1][hr]=rs1[i+1];
10622                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10623                 regs[i].isconst&=~(1<<hr);
10624                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10625                 constmap[i][hr]=constmap[i+1][hr];
10626                 regs[i+1].wasdirty&=~(1<<hr);
10627                 regs[i].dirty&=~(1<<hr);
10628               }
10629             }
10630           }
10631           // Preload map address
10632           #ifndef HOST_IMM_ADDR32
10633           if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
10634             hr=get_reg(regs[i+1].regmap,TLREG);
10635             if(hr>=0) {
10636               int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10637               if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10638                 int nr;
10639                 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10640                 {
10641                   regs[i].regmap[hr]=MGEN1+((i+1)&1);
10642                   regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10643                   regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10644                   regs[i].isconst&=~(1<<hr);
10645                   regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10646                   constmap[i][hr]=constmap[i+1][hr];
10647                   regs[i+1].wasdirty&=~(1<<hr);
10648                   regs[i].dirty&=~(1<<hr);
10649                 }
10650                 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10651                 {
10652                   // move it to another register
10653                   regs[i+1].regmap[hr]=-1;
10654                   regmap_pre[i+2][hr]=-1;
10655                   regs[i+1].regmap[nr]=TLREG;
10656                   regmap_pre[i+2][nr]=TLREG;
10657                   regs[i].regmap[nr]=MGEN1+((i+1)&1);
10658                   regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10659                   regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10660                   regs[i].isconst&=~(1<<nr);
10661                   regs[i+1].isconst&=~(1<<nr);
10662                   regs[i].dirty&=~(1<<nr);
10663                   regs[i+1].wasdirty&=~(1<<nr);
10664                   regs[i+1].dirty&=~(1<<nr);
10665                   regs[i+2].wasdirty&=~(1<<nr);
10666                 }
10667               }
10668             }
10669           }
10670           #endif
10671           // Address for store instruction (non-constant)
10672           if(itype[i+1]==STORE||itype[i+1]==STORELR
10673              ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
10674             if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10675               hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10676               if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10677               else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10678               assert(hr>=0);
10679               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10680               {
10681                 regs[i].regmap[hr]=rs1[i+1];
10682                 regmap_pre[i+1][hr]=rs1[i+1];
10683                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10684                 regs[i].isconst&=~(1<<hr);
10685                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10686                 constmap[i][hr]=constmap[i+1][hr];
10687                 regs[i+1].wasdirty&=~(1<<hr);
10688                 regs[i].dirty&=~(1<<hr);
10689               }
10690             }
10691           }
10692           if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
10693             if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10694               int nr;
10695               hr=get_reg(regs[i+1].regmap,FTEMP);
10696               assert(hr>=0);
10697               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10698               {
10699                 regs[i].regmap[hr]=rs1[i+1];
10700                 regmap_pre[i+1][hr]=rs1[i+1];
10701                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10702                 regs[i].isconst&=~(1<<hr);
10703                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10704                 constmap[i][hr]=constmap[i+1][hr];
10705                 regs[i+1].wasdirty&=~(1<<hr);
10706                 regs[i].dirty&=~(1<<hr);
10707               }
10708               else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10709               {
10710                 // move it to another register
10711                 regs[i+1].regmap[hr]=-1;
10712                 regmap_pre[i+2][hr]=-1;
10713                 regs[i+1].regmap[nr]=FTEMP;
10714                 regmap_pre[i+2][nr]=FTEMP;
10715                 regs[i].regmap[nr]=rs1[i+1];
10716                 regmap_pre[i+1][nr]=rs1[i+1];
10717                 regs[i+1].regmap_entry[nr]=rs1[i+1];
10718                 regs[i].isconst&=~(1<<nr);
10719                 regs[i+1].isconst&=~(1<<nr);
10720                 regs[i].dirty&=~(1<<nr);
10721                 regs[i+1].wasdirty&=~(1<<nr);
10722                 regs[i+1].dirty&=~(1<<nr);
10723                 regs[i+2].wasdirty&=~(1<<nr);
10724               }
10725             }
10726           }
10727           if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
10728             if(itype[i+1]==LOAD)
10729               hr=get_reg(regs[i+1].regmap,rt1[i+1]);
10730             if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
10731               hr=get_reg(regs[i+1].regmap,FTEMP);
10732             if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
10733               hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10734               if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10735             }
10736             if(hr>=0&&regs[i].regmap[hr]<0) {
10737               int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10738               if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10739                 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10740                 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10741                 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10742                 regs[i].isconst&=~(1<<hr);
10743                 regs[i+1].wasdirty&=~(1<<hr);
10744                 regs[i].dirty&=~(1<<hr);
10745               }
10746             }
10747           }
10748         }
10749       }
10750     }
10751   }
10752
10753   /* Pass 6 - Optimize clean/dirty state */
10754   clean_registers(0,slen-1,1);
10755
10756   /* Pass 7 - Identify 32-bit registers */
10757 #ifndef FORCE32
10758   provisional_r32();
10759
10760   u_int r32=0;
10761
10762   for (i=slen-1;i>=0;i--)
10763   {
10764     int hr;
10765     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10766     {
10767       if(ba[i]<start || ba[i]>=(start+slen*4))
10768       {
10769         // Branch out of this block, don't need anything
10770         r32=0;
10771       }
10772       else
10773       {
10774         // Internal branch
10775         // Need whatever matches the target
10776         // (and doesn't get overwritten by the delay slot instruction)
10777         r32=0;
10778         int t=(ba[i]-start)>>2;
10779         if(ba[i]>start+i*4) {
10780           // Forward branch
10781           if(!(requires_32bit[t]&~regs[i].was32))
10782             r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10783         }else{
10784           // Backward branch
10785           //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10786           //  r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10787           if(!(pr32[t]&~regs[i].was32))
10788             r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10789         }
10790       }
10791       // Conditional branch may need registers for following instructions
10792       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10793       {
10794         if(i<slen-2) {
10795           r32|=requires_32bit[i+2];
10796           r32&=regs[i].was32;
10797           // Mark this address as a branch target since it may be called
10798           // upon return from interrupt
10799           bt[i+2]=1;
10800         }
10801       }
10802       // Merge in delay slot
10803       if(!likely[i]) {
10804         // These are overwritten unless the branch is "likely"
10805         // and the delay slot is nullified if not taken
10806         r32&=~(1LL<<rt1[i+1]);
10807         r32&=~(1LL<<rt2[i+1]);
10808       }
10809       // Assume these are needed (delay slot)
10810       if(us1[i+1]>0)
10811       {
10812         if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10813       }
10814       if(us2[i+1]>0)
10815       {
10816         if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10817       }
10818       if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10819       {
10820         if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10821       }
10822       if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10823       {
10824         if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10825       }
10826     }
10827     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
10828     {
10829       // SYSCALL instruction (software interrupt)
10830       r32=0;
10831     }
10832     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10833     {
10834       // ERET instruction (return from interrupt)
10835       r32=0;
10836     }
10837     // Check 32 bits
10838     r32&=~(1LL<<rt1[i]);
10839     r32&=~(1LL<<rt2[i]);
10840     if(us1[i]>0)
10841     {
10842       if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10843     }
10844     if(us2[i]>0)
10845     {
10846       if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10847     }
10848     if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
10849     {
10850       if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
10851     }
10852     if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
10853     {
10854       if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
10855     }
10856     requires_32bit[i]=r32;
10857
10858     // Dirty registers which are 32-bit, require 32-bit input
10859     // as they will be written as 32-bit values
10860     for(hr=0;hr<HOST_REGS;hr++)
10861     {
10862       if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
10863         if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
10864           if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
10865           requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
10866         }
10867       }
10868     }
10869     //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
10870   }
10871 #else
10872   for (i=slen-1;i>=0;i--)
10873   {
10874     if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10875     {
10876       // Conditional branch
10877       if((source[i]>>16)!=0x1000&&i<slen-2) {
10878         // Mark this address as a branch target since it may be called
10879         // upon return from interrupt
10880         bt[i+2]=1;
10881       }
10882     }
10883   }
10884 #endif
10885
10886   if(itype[slen-1]==SPAN) {
10887     bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
10888   }
10889
10890   /* Debug/disassembly */
10891   if((void*)assem_debug==(void*)printf)
10892   for(i=0;i<slen;i++)
10893   {
10894     printf("U:");
10895     int r;
10896     for(r=1;r<=CCREG;r++) {
10897       if((unneeded_reg[i]>>r)&1) {
10898         if(r==HIREG) printf(" HI");
10899         else if(r==LOREG) printf(" LO");
10900         else printf(" r%d",r);
10901       }
10902     }
10903 #ifndef FORCE32
10904     printf(" UU:");
10905     for(r=1;r<=CCREG;r++) {
10906       if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
10907         if(r==HIREG) printf(" HI");
10908         else if(r==LOREG) printf(" LO");
10909         else printf(" r%d",r);
10910       }
10911     }
10912     printf(" 32:");
10913     for(r=0;r<=CCREG;r++) {
10914       //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10915       if((regs[i].was32>>r)&1) {
10916         if(r==CCREG) printf(" CC");
10917         else if(r==HIREG) printf(" HI");
10918         else if(r==LOREG) printf(" LO");
10919         else printf(" r%d",r);
10920       }
10921     }
10922 #endif
10923     printf("\n");
10924     #if defined(__i386__) || defined(__x86_64__)
10925     printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
10926     #endif
10927     #ifdef __arm__
10928     printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
10929     #endif
10930     printf("needs: ");
10931     if(needed_reg[i]&1) printf("eax ");
10932     if((needed_reg[i]>>1)&1) printf("ecx ");
10933     if((needed_reg[i]>>2)&1) printf("edx ");
10934     if((needed_reg[i]>>3)&1) printf("ebx ");
10935     if((needed_reg[i]>>5)&1) printf("ebp ");
10936     if((needed_reg[i]>>6)&1) printf("esi ");
10937     if((needed_reg[i]>>7)&1) printf("edi ");
10938     printf("r:");
10939     for(r=0;r<=CCREG;r++) {
10940       //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10941       if((requires_32bit[i]>>r)&1) {
10942         if(r==CCREG) printf(" CC");
10943         else if(r==HIREG) printf(" HI");
10944         else if(r==LOREG) printf(" LO");
10945         else printf(" r%d",r);
10946       }
10947     }
10948     printf("\n");
10949     /*printf("pr:");
10950     for(r=0;r<=CCREG;r++) {
10951       //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10952       if((pr32[i]>>r)&1) {
10953         if(r==CCREG) printf(" CC");
10954         else if(r==HIREG) printf(" HI");
10955         else if(r==LOREG) printf(" LO");
10956         else printf(" r%d",r);
10957       }
10958     }
10959     if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
10960     printf("\n");*/
10961     #if defined(__i386__) || defined(__x86_64__)
10962     printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
10963     printf("dirty: ");
10964     if(regs[i].wasdirty&1) printf("eax ");
10965     if((regs[i].wasdirty>>1)&1) printf("ecx ");
10966     if((regs[i].wasdirty>>2)&1) printf("edx ");
10967     if((regs[i].wasdirty>>3)&1) printf("ebx ");
10968     if((regs[i].wasdirty>>5)&1) printf("ebp ");
10969     if((regs[i].wasdirty>>6)&1) printf("esi ");
10970     if((regs[i].wasdirty>>7)&1) printf("edi ");
10971     #endif
10972     #ifdef __arm__
10973     printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
10974     printf("dirty: ");
10975     if(regs[i].wasdirty&1) printf("r0 ");
10976     if((regs[i].wasdirty>>1)&1) printf("r1 ");
10977     if((regs[i].wasdirty>>2)&1) printf("r2 ");
10978     if((regs[i].wasdirty>>3)&1) printf("r3 ");
10979     if((regs[i].wasdirty>>4)&1) printf("r4 ");
10980     if((regs[i].wasdirty>>5)&1) printf("r5 ");
10981     if((regs[i].wasdirty>>6)&1) printf("r6 ");
10982     if((regs[i].wasdirty>>7)&1) printf("r7 ");
10983     if((regs[i].wasdirty>>8)&1) printf("r8 ");
10984     if((regs[i].wasdirty>>9)&1) printf("r9 ");
10985     if((regs[i].wasdirty>>10)&1) printf("r10 ");
10986     if((regs[i].wasdirty>>12)&1) printf("r12 ");
10987     #endif
10988     printf("\n");
10989     disassemble_inst(i);
10990     //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
10991     #if defined(__i386__) || defined(__x86_64__)
10992     printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
10993     if(regs[i].dirty&1) printf("eax ");
10994     if((regs[i].dirty>>1)&1) printf("ecx ");
10995     if((regs[i].dirty>>2)&1) printf("edx ");
10996     if((regs[i].dirty>>3)&1) printf("ebx ");
10997     if((regs[i].dirty>>5)&1) printf("ebp ");
10998     if((regs[i].dirty>>6)&1) printf("esi ");
10999     if((regs[i].dirty>>7)&1) printf("edi ");
11000     #endif
11001     #ifdef __arm__
11002     printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
11003     if(regs[i].dirty&1) printf("r0 ");
11004     if((regs[i].dirty>>1)&1) printf("r1 ");
11005     if((regs[i].dirty>>2)&1) printf("r2 ");
11006     if((regs[i].dirty>>3)&1) printf("r3 ");
11007     if((regs[i].dirty>>4)&1) printf("r4 ");
11008     if((regs[i].dirty>>5)&1) printf("r5 ");
11009     if((regs[i].dirty>>6)&1) printf("r6 ");
11010     if((regs[i].dirty>>7)&1) printf("r7 ");
11011     if((regs[i].dirty>>8)&1) printf("r8 ");
11012     if((regs[i].dirty>>9)&1) printf("r9 ");
11013     if((regs[i].dirty>>10)&1) printf("r10 ");
11014     if((regs[i].dirty>>12)&1) printf("r12 ");
11015     #endif
11016     printf("\n");
11017     if(regs[i].isconst) {
11018       printf("constants: ");
11019       #if defined(__i386__) || defined(__x86_64__)
11020       if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
11021       if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
11022       if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
11023       if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
11024       if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
11025       if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
11026       if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
11027       #endif
11028       #ifdef __arm__
11029       if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
11030       if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
11031       if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
11032       if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
11033       if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
11034       if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
11035       if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
11036       if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
11037       if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
11038       if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
11039       if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
11040       if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
11041       #endif
11042       printf("\n");
11043     }
11044 #ifndef FORCE32
11045     printf(" 32:");
11046     for(r=0;r<=CCREG;r++) {
11047       if((regs[i].is32>>r)&1) {
11048         if(r==CCREG) printf(" CC");
11049         else if(r==HIREG) printf(" HI");
11050         else if(r==LOREG) printf(" LO");
11051         else printf(" r%d",r);
11052       }
11053     }
11054     printf("\n");
11055 #endif
11056     /*printf(" p32:");
11057     for(r=0;r<=CCREG;r++) {
11058       if((p32[i]>>r)&1) {
11059         if(r==CCREG) printf(" CC");
11060         else if(r==HIREG) printf(" HI");
11061         else if(r==LOREG) printf(" LO");
11062         else printf(" r%d",r);
11063       }
11064     }
11065     if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
11066     else printf("\n");*/
11067     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
11068       #if defined(__i386__) || defined(__x86_64__)
11069       printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
11070       if(branch_regs[i].dirty&1) printf("eax ");
11071       if((branch_regs[i].dirty>>1)&1) printf("ecx ");
11072       if((branch_regs[i].dirty>>2)&1) printf("edx ");
11073       if((branch_regs[i].dirty>>3)&1) printf("ebx ");
11074       if((branch_regs[i].dirty>>5)&1) printf("ebp ");
11075       if((branch_regs[i].dirty>>6)&1) printf("esi ");
11076       if((branch_regs[i].dirty>>7)&1) printf("edi ");
11077       #endif
11078       #ifdef __arm__
11079       printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
11080       if(branch_regs[i].dirty&1) printf("r0 ");
11081       if((branch_regs[i].dirty>>1)&1) printf("r1 ");
11082       if((branch_regs[i].dirty>>2)&1) printf("r2 ");
11083       if((branch_regs[i].dirty>>3)&1) printf("r3 ");
11084       if((branch_regs[i].dirty>>4)&1) printf("r4 ");
11085       if((branch_regs[i].dirty>>5)&1) printf("r5 ");
11086       if((branch_regs[i].dirty>>6)&1) printf("r6 ");
11087       if((branch_regs[i].dirty>>7)&1) printf("r7 ");
11088       if((branch_regs[i].dirty>>8)&1) printf("r8 ");
11089       if((branch_regs[i].dirty>>9)&1) printf("r9 ");
11090       if((branch_regs[i].dirty>>10)&1) printf("r10 ");
11091       if((branch_regs[i].dirty>>12)&1) printf("r12 ");
11092       #endif
11093 #ifndef FORCE32
11094       printf(" 32:");
11095       for(r=0;r<=CCREG;r++) {
11096         if((branch_regs[i].is32>>r)&1) {
11097           if(r==CCREG) printf(" CC");
11098           else if(r==HIREG) printf(" HI");
11099           else if(r==LOREG) printf(" LO");
11100           else printf(" r%d",r);
11101         }
11102       }
11103       printf("\n");
11104 #endif
11105     }
11106   }
11107
11108   /* Pass 8 - Assembly */
11109   linkcount=0;stubcount=0;
11110   ds=0;is_delayslot=0;
11111   cop1_usable=0;
11112   uint64_t is32_pre=0;
11113   u_int dirty_pre=0;
11114   u_int beginning=(u_int)out;
11115   if((u_int)addr&1) {
11116     ds=1;
11117     pagespan_ds();
11118   }
11119   u_int instr_addr0_override=0;
11120
11121 #ifdef PCSX
11122   if (start == 0x80030000) {
11123     // nasty hack for fastbios thing
11124     // override block entry to this code
11125     instr_addr0_override=(u_int)out;
11126     emit_movimm(start,0);
11127     // abuse io address var as a flag that we
11128     // have already returned here once
11129     emit_readword((int)&address,1);
11130     emit_writeword(0,(int)&pcaddr);
11131     emit_writeword(0,(int)&address);
11132     emit_cmp(0,1);
11133     emit_jne((int)new_dyna_leave);
11134   }
11135 #endif
11136   for(i=0;i<slen;i++)
11137   {
11138     //if(ds) printf("ds: ");
11139     if((void*)assem_debug==(void*)printf) disassemble_inst(i);
11140     if(ds) {
11141       ds=0; // Skip delay slot
11142       if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
11143       instr_addr[i]=0;
11144     } else {
11145       #ifndef DESTRUCTIVE_WRITEBACK
11146       if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11147       {
11148         wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
11149               unneeded_reg[i],unneeded_reg_upper[i]);
11150         wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
11151               unneeded_reg[i],unneeded_reg_upper[i]);
11152       }
11153       if((itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)&&!likely[i]) {
11154         is32_pre=branch_regs[i].is32;
11155         dirty_pre=branch_regs[i].dirty;
11156       }else{
11157         is32_pre=regs[i].is32;
11158         dirty_pre=regs[i].dirty;
11159       }
11160       #endif
11161       // write back
11162       if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11163       {
11164         wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
11165                       unneeded_reg[i],unneeded_reg_upper[i]);
11166         loop_preload(regmap_pre[i],regs[i].regmap_entry);
11167       }
11168       // branch target entry point
11169       instr_addr[i]=(u_int)out;
11170       assem_debug("<->\n");
11171       // load regs
11172       if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
11173         wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
11174       load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
11175       address_generation(i,&regs[i],regs[i].regmap_entry);
11176       load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
11177       if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
11178       {
11179         // Load the delay slot registers if necessary
11180         if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i]&&(rs1[i+1]!=rt1[i]||rt1[i]==0))
11181           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11182         if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i]&&(rs2[i+1]!=rt1[i]||rt1[i]==0))
11183           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11184         if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
11185           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11186       }
11187       else if(i+1<slen)
11188       {
11189         // Preload registers for following instruction
11190         if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
11191           if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
11192             load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11193         if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
11194           if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
11195             load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11196       }
11197       // TODO: if(is_ooo(i)) address_generation(i+1);
11198       if(itype[i]==CJUMP||itype[i]==FJUMP)
11199         load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
11200       if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
11201         load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11202       if(bt[i]) cop1_usable=0;
11203       // assemble
11204       switch(itype[i]) {
11205         case ALU:
11206           alu_assemble(i,&regs[i]);break;
11207         case IMM16:
11208           imm16_assemble(i,&regs[i]);break;
11209         case SHIFT:
11210           shift_assemble(i,&regs[i]);break;
11211         case SHIFTIMM:
11212           shiftimm_assemble(i,&regs[i]);break;
11213         case LOAD:
11214           load_assemble(i,&regs[i]);break;
11215         case LOADLR:
11216           loadlr_assemble(i,&regs[i]);break;
11217         case STORE:
11218           store_assemble(i,&regs[i]);break;
11219         case STORELR:
11220           storelr_assemble(i,&regs[i]);break;
11221         case COP0:
11222           cop0_assemble(i,&regs[i]);break;
11223         case COP1:
11224           cop1_assemble(i,&regs[i]);break;
11225         case C1LS:
11226           c1ls_assemble(i,&regs[i]);break;
11227         case COP2:
11228           cop2_assemble(i,&regs[i]);break;
11229         case C2LS:
11230           c2ls_assemble(i,&regs[i]);break;
11231         case C2OP:
11232           c2op_assemble(i,&regs[i]);break;
11233         case FCONV:
11234           fconv_assemble(i,&regs[i]);break;
11235         case FLOAT:
11236           float_assemble(i,&regs[i]);break;
11237         case FCOMP:
11238           fcomp_assemble(i,&regs[i]);break;
11239         case MULTDIV:
11240           multdiv_assemble(i,&regs[i]);break;
11241         case MOV:
11242           mov_assemble(i,&regs[i]);break;
11243         case SYSCALL:
11244           syscall_assemble(i,&regs[i]);break;
11245         case HLECALL:
11246           hlecall_assemble(i,&regs[i]);break;
11247         case INTCALL:
11248           intcall_assemble(i,&regs[i]);break;
11249         case UJUMP:
11250           ujump_assemble(i,&regs[i]);ds=1;break;
11251         case RJUMP:
11252           rjump_assemble(i,&regs[i]);ds=1;break;
11253         case CJUMP:
11254           cjump_assemble(i,&regs[i]);ds=1;break;
11255         case SJUMP:
11256           sjump_assemble(i,&regs[i]);ds=1;break;
11257         case FJUMP:
11258           fjump_assemble(i,&regs[i]);ds=1;break;
11259         case SPAN:
11260           pagespan_assemble(i,&regs[i]);break;
11261       }
11262       if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
11263         literal_pool(1024);
11264       else
11265         literal_pool_jumpover(256);
11266     }
11267   }
11268   //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
11269   // If the block did not end with an unconditional branch,
11270   // add a jump to the next instruction.
11271   if(i>1) {
11272     if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
11273       assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11274       assert(i==slen);
11275       if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
11276         store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11277         if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11278           emit_loadreg(CCREG,HOST_CCREG);
11279         emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
11280       }
11281       else if(!likely[i-2])
11282       {
11283         store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
11284         assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
11285       }
11286       else
11287       {
11288         store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
11289         assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
11290       }
11291       add_to_linker((int)out,start+i*4,0);
11292       emit_jmp(0);
11293     }
11294   }
11295   else
11296   {
11297     assert(i>0);
11298     assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11299     store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11300     if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11301       emit_loadreg(CCREG,HOST_CCREG);
11302     emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
11303     add_to_linker((int)out,start+i*4,0);
11304     emit_jmp(0);
11305   }
11306
11307   // TODO: delay slot stubs?
11308   // Stubs
11309   for(i=0;i<stubcount;i++)
11310   {
11311     switch(stubs[i][0])
11312     {
11313       case LOADB_STUB:
11314       case LOADH_STUB:
11315       case LOADW_STUB:
11316       case LOADD_STUB:
11317       case LOADBU_STUB:
11318       case LOADHU_STUB:
11319         do_readstub(i);break;
11320       case STOREB_STUB:
11321       case STOREH_STUB:
11322       case STOREW_STUB:
11323       case STORED_STUB:
11324         do_writestub(i);break;
11325       case CC_STUB:
11326         do_ccstub(i);break;
11327       case INVCODE_STUB:
11328         do_invstub(i);break;
11329       case FP_STUB:
11330         do_cop1stub(i);break;
11331       case STORELR_STUB:
11332         do_unalignedwritestub(i);break;
11333     }
11334   }
11335
11336   if (instr_addr0_override)
11337     instr_addr[0] = instr_addr0_override;
11338
11339   /* Pass 9 - Linker */
11340   for(i=0;i<linkcount;i++)
11341   {
11342     assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
11343     literal_pool(64);
11344     if(!link_addr[i][2])
11345     {
11346       void *stub=out;
11347       void *addr=check_addr(link_addr[i][1]);
11348       emit_extjump(link_addr[i][0],link_addr[i][1]);
11349       if(addr) {
11350         set_jump_target(link_addr[i][0],(int)addr);
11351         add_link(link_addr[i][1],stub);
11352       }
11353       else set_jump_target(link_addr[i][0],(int)stub);
11354     }
11355     else
11356     {
11357       // Internal branch
11358       int target=(link_addr[i][1]-start)>>2;
11359       assert(target>=0&&target<slen);
11360       assert(instr_addr[target]);
11361       //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11362       //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
11363       //#else
11364       set_jump_target(link_addr[i][0],instr_addr[target]);
11365       //#endif
11366     }
11367   }
11368   // External Branch Targets (jump_in)
11369   if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
11370   for(i=0;i<slen;i++)
11371   {
11372     if(bt[i]||i==0)
11373     {
11374       if(instr_addr[i]) // TODO - delay slots (=null)
11375       {
11376         u_int vaddr=start+i*4;
11377         u_int page=get_page(vaddr);
11378         u_int vpage=get_vpage(vaddr);
11379         literal_pool(256);
11380         //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
11381 #ifndef FORCE32
11382         if(!requires_32bit[i])
11383 #else
11384         if(1)
11385 #endif
11386         {
11387           assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11388           assem_debug("jump_in: %x\n",start+i*4);
11389           ll_add(jump_dirty+vpage,vaddr,(void *)out);
11390           int entry_point=do_dirty_stub(i);
11391           ll_add(jump_in+page,vaddr,(void *)entry_point);
11392           // If there was an existing entry in the hash table,
11393           // replace it with the new address.
11394           // Don't add new entries.  We'll insert the
11395           // ones that actually get used in check_addr().
11396           int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
11397           if(ht_bin[0]==vaddr) {
11398             ht_bin[1]=entry_point;
11399           }
11400           if(ht_bin[2]==vaddr) {
11401             ht_bin[3]=entry_point;
11402           }
11403         }
11404         else
11405         {
11406           u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
11407           assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11408           assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
11409           //int entry_point=(int)out;
11410           ////assem_debug("entry_point: %x\n",entry_point);
11411           //load_regs_entry(i);
11412           //if(entry_point==(int)out)
11413           //  entry_point=instr_addr[i];
11414           //else
11415           //  emit_jmp(instr_addr[i]);
11416           //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11417           ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
11418           int entry_point=do_dirty_stub(i);
11419           ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11420         }
11421       }
11422     }
11423   }
11424   // Write out the literal pool if necessary
11425   literal_pool(0);
11426   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11427   // Align code
11428   if(((u_int)out)&7) emit_addnop(13);
11429   #endif
11430   assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
11431   //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
11432   memcpy(copy,source,slen*4);
11433   copy+=slen*4;
11434
11435   #ifdef __arm__
11436   __clear_cache((void *)beginning,out);
11437   #endif
11438
11439   // If we're within 256K of the end of the buffer,
11440   // start over from the beginning. (Is 256K enough?)
11441   if((int)out>BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
11442
11443   // Trap writes to any of the pages we compiled
11444   for(i=start>>12;i<=(start+slen*4)>>12;i++) {
11445     invalid_code[i]=0;
11446 #ifndef DISABLE_TLB
11447     memory_map[i]|=0x40000000;
11448     if((signed int)start>=(signed int)0xC0000000) {
11449       assert(using_tlb);
11450       j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
11451       invalid_code[j]=0;
11452       memory_map[j]|=0x40000000;
11453       //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
11454     }
11455 #endif
11456   }
11457   inv_code_start=inv_code_end=~0;
11458 #ifdef PCSX
11459   // PCSX maps all RAM mirror invalid_code tests to 0x80000000..0x80000000+RAM_SIZE
11460   if(get_page(start)<(RAM_SIZE>>12))
11461     for(i=start>>12;i<=(start+slen*4)>>12;i++)
11462       invalid_code[((u_int)0x80000000>>12)|i]=0;
11463 #endif
11464
11465   /* Pass 10 - Free memory by expiring oldest blocks */
11466
11467   int end=((((int)out-BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
11468   while(expirep!=end)
11469   {
11470     int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
11471     int base=BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
11472     inv_debug("EXP: Phase %d\n",expirep);
11473     switch((expirep>>11)&3)
11474     {
11475       case 0:
11476         // Clear jump_in and jump_dirty
11477         ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
11478         ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
11479         ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
11480         ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
11481         break;
11482       case 1:
11483         // Clear pointers
11484         ll_kill_pointers(jump_out[expirep&2047],base,shift);
11485         ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
11486         break;
11487       case 2:
11488         // Clear hash table
11489         for(i=0;i<32;i++) {
11490           int *ht_bin=hash_table[((expirep&2047)<<5)+i];
11491           if((ht_bin[3]>>shift)==(base>>shift) ||
11492              ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11493             inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
11494             ht_bin[2]=ht_bin[3]=-1;
11495           }
11496           if((ht_bin[1]>>shift)==(base>>shift) ||
11497              ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11498             inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
11499             ht_bin[0]=ht_bin[2];
11500             ht_bin[1]=ht_bin[3];
11501             ht_bin[2]=ht_bin[3]=-1;
11502           }
11503         }
11504         break;
11505       case 3:
11506         // Clear jump_out
11507         #ifdef __arm__
11508         if((expirep&2047)==0)
11509           do_clear_cache();
11510         #endif
11511         ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
11512         ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
11513         break;
11514     }
11515     expirep=(expirep+1)&65535;
11516   }
11517   return 0;
11518 }
11519
11520 // vim:shiftwidth=2:expandtab