1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2011 Ari64 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include <stdint.h> //include for uint64_t
27 #include <libkern/OSCacheControl.h>
30 #include <3ds_utils.h>
33 #include <psp2/kernel/sysmem.h>
37 #include "new_dynarec_config.h"
38 #include "../psxhle.h"
39 #include "../psxinterpreter.h"
40 #include "emu_if.h" //emulator interface
42 #define noinline __attribute__((noinline,noclone))
44 #define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
48 //#define assem_debug printf
49 //#define inv_debug printf
50 #define assem_debug(...)
51 #define inv_debug(...)
54 #include "assem_x86.h"
57 #include "assem_x64.h"
60 #include "assem_arm.h"
63 #include "assem_arm64.h"
67 #define MAX_OUTPUT_BLOCK_SIZE 262144
71 u_char translation_cache[1 << TARGET_SIZE_2];
74 struct tramp_insns ops[2048 / sizeof(struct tramp_insns)];
75 const void *f[2048 / sizeof(void *)];
79 #ifdef BASE_ADDR_DYNAMIC
80 static struct ndrc_mem *ndrc;
82 static struct ndrc_mem ndrc_ __attribute__((aligned(4096)));
83 static struct ndrc_mem *ndrc = &ndrc_;
106 signed char regmap_entry[HOST_REGS];
107 signed char regmap[HOST_REGS];
113 u_int loadedconst; // host regs that have constants loaded
114 u_int waswritten; // MIPS regs that were used as store base before
117 // note: asm depends on this layout
123 struct ll_entry *next;
153 struct ht_entry hash_table[65536] __attribute__((aligned(16)));
154 struct ll_entry *jump_in[4096] __attribute__((aligned(16)));
155 struct ll_entry *jump_dirty[4096];
157 static struct ll_entry *jump_out[4096];
159 static u_int *source;
160 static char insn[MAXBLOCK][10];
161 static u_char itype[MAXBLOCK];
162 static u_char opcode[MAXBLOCK];
163 static u_char opcode2[MAXBLOCK];
164 static u_char bt[MAXBLOCK];
165 static u_char rs1[MAXBLOCK];
166 static u_char rs2[MAXBLOCK];
167 static u_char rt1[MAXBLOCK];
168 static u_char rt2[MAXBLOCK];
169 static u_char dep1[MAXBLOCK];
170 static u_char dep2[MAXBLOCK];
171 static u_char lt1[MAXBLOCK];
172 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
173 static uint64_t gte_rt[MAXBLOCK];
174 static uint64_t gte_unneeded[MAXBLOCK];
175 static u_int smrv[32]; // speculated MIPS register values
176 static u_int smrv_strong; // mask or regs that are likely to have correct values
177 static u_int smrv_weak; // same, but somewhat less likely
178 static u_int smrv_strong_next; // same, but after current insn executes
179 static u_int smrv_weak_next;
180 static int imm[MAXBLOCK];
181 static u_int ba[MAXBLOCK];
182 static char likely[MAXBLOCK];
183 static char is_ds[MAXBLOCK];
184 static char ooo[MAXBLOCK];
185 static uint64_t unneeded_reg[MAXBLOCK];
186 static uint64_t branch_unneeded_reg[MAXBLOCK];
187 static signed char regmap_pre[MAXBLOCK][HOST_REGS]; // pre-instruction i?
188 static uint64_t current_constmap[HOST_REGS];
189 static uint64_t constmap[MAXBLOCK][HOST_REGS];
190 static struct regstat regs[MAXBLOCK];
191 static struct regstat branch_regs[MAXBLOCK];
192 static signed char minimum_free_regs[MAXBLOCK];
193 static u_int needed_reg[MAXBLOCK];
194 static u_int wont_dirty[MAXBLOCK];
195 static u_int will_dirty[MAXBLOCK];
196 static int ccadj[MAXBLOCK];
198 static void *instr_addr[MAXBLOCK];
199 static struct link_entry link_addr[MAXBLOCK];
200 static int linkcount;
201 static struct code_stub stubs[MAXBLOCK*3];
202 static int stubcount;
203 static u_int literals[1024][2];
204 static int literalcount;
205 static int is_delayslot;
206 static char shadow[1048576] __attribute__((aligned(16)));
209 static u_int stop_after_jal;
211 static uintptr_t ram_offset;
213 static const uintptr_t ram_offset=0;
216 int new_dynarec_hacks;
217 int new_dynarec_did_compile;
219 extern int cycle_count; // ... until end of the timeslice, counts -N -> 0
220 extern int last_count; // last absolute target, often = next_interupt
222 extern int pending_exception;
223 extern int branch_target;
224 extern uintptr_t mini_ht[32][2];
225 extern u_char restore_candidate[512];
227 /* registers that may be allocated */
229 #define LOREG 32 // lo
230 #define HIREG 33 // hi
231 //#define FSREG 34 // FPU status (FCSR)
232 #define CSREG 35 // Coprocessor status
233 #define CCREG 36 // Cycle count
234 #define INVCP 37 // Pointer to invalid_code
235 //#define MMREG 38 // Pointer to memory_map
236 //#define ROREG 39 // ram offset (if rdram!=0x80000000)
238 #define FTEMP 40 // FPU temporary register
239 #define PTEMP 41 // Prefetch temporary register
240 //#define TLREG 42 // TLB mapping offset
241 #define RHASH 43 // Return address hash
242 #define RHTBL 44 // Return address hash table address
243 #define RTEMP 45 // JR/JALR address register
245 #define AGEN1 46 // Address generation temporary register
246 //#define AGEN2 47 // Address generation temporary register
247 //#define MGEN1 48 // Maptable address generation temporary register
248 //#define MGEN2 49 // Maptable address generation temporary register
249 #define BTREG 50 // Branch target temporary register
251 /* instruction types */
252 #define NOP 0 // No operation
253 #define LOAD 1 // Load
254 #define STORE 2 // Store
255 #define LOADLR 3 // Unaligned load
256 #define STORELR 4 // Unaligned store
257 #define MOV 5 // Move
258 #define ALU 6 // Arithmetic/logic
259 #define MULTDIV 7 // Multiply/divide
260 #define SHIFT 8 // Shift by register
261 #define SHIFTIMM 9// Shift by immediate
262 #define IMM16 10 // 16-bit immediate
263 #define RJUMP 11 // Unconditional jump to register
264 #define UJUMP 12 // Unconditional jump
265 #define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
266 #define SJUMP 14 // Conditional branch (regimm format)
267 #define COP0 15 // Coprocessor 0
268 #define COP1 16 // Coprocessor 1
269 #define C1LS 17 // Coprocessor 1 load/store
270 //#define FJUMP 18 // Conditional branch (floating point)
271 //#define FLOAT 19 // Floating point unit
272 //#define FCONV 20 // Convert integer to float
273 //#define FCOMP 21 // Floating point compare (sets FSREG)
274 #define SYSCALL 22// SYSCALL
275 #define OTHER 23 // Other
276 #define SPAN 24 // Branch/delay slot spans 2 pages
277 #define NI 25 // Not implemented
278 #define HLECALL 26// PCSX fake opcodes for HLE
279 #define COP2 27 // Coprocessor 2 move
280 #define C2LS 28 // Coprocessor 2 load/store
281 #define C2OP 29 // Coprocessor 2 operation
282 #define INTCALL 30// Call interpreter to handle rare corner cases
289 #define DJT_1 (void *)1l // no function, just a label in assem_debug log
290 #define DJT_2 (void *)2l
293 int new_recompile_block(u_int addr);
294 void *get_addr_ht(u_int vaddr);
295 void invalidate_block(u_int block);
296 void invalidate_addr(u_int addr);
297 void remove_hash(int vaddr);
299 void dyna_linker_ds();
301 void verify_code_ds();
304 void fp_exception_ds();
305 void jump_to_new_pc();
306 void new_dyna_leave();
308 // Needed by assembler
309 static void wb_register(signed char r,signed char regmap[],uint64_t dirty);
310 static void wb_dirtys(signed char i_regmap[],uint64_t i_dirty);
311 static void wb_needed_dirtys(signed char i_regmap[],uint64_t i_dirty,int addr);
312 static void load_all_regs(signed char i_regmap[]);
313 static void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
314 static void load_regs_entry(int t);
315 static void load_all_consts(signed char regmap[],u_int dirty,int i);
317 static int verify_dirty(const u_int *ptr);
318 static int get_final_value(int hr, int i, int *value);
319 static void add_stub(enum stub_type type, void *addr, void *retaddr,
320 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e);
321 static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
322 int i, int addr_reg, struct regstat *i_regs, int ccadj, u_int reglist);
323 static void add_to_linker(void *addr, u_int target, int ext);
324 static void *emit_fastpath_cmp_jump(int i,int addr,int *addr_reg_override);
325 static void *get_direct_memhandler(void *table, u_int addr,
326 enum stub_type type, uintptr_t *addr_host);
327 static void pass_args(int a0, int a1);
328 static void emit_far_jump(const void *f);
329 static void emit_far_call(const void *f);
331 static void mprotect_w_x(void *start, void *end, int is_x)
335 // *Open* enables write on all memory that was
336 // allocated by sceKernelAllocMemBlockForVM()?
338 sceKernelCloseVMDomain();
340 sceKernelOpenVMDomain();
342 u_long mstart = (u_long)start & ~4095ul;
343 u_long mend = (u_long)end;
344 if (mprotect((void *)mstart, mend - mstart,
345 PROT_READ | (is_x ? PROT_EXEC : PROT_WRITE)) != 0)
346 SysPrintf("mprotect(%c) failed: %s\n", is_x ? 'x' : 'w', strerror(errno));
351 static void start_tcache_write(void *start, void *end)
353 mprotect_w_x(start, end, 0);
356 static void end_tcache_write(void *start, void *end)
358 #if defined(__arm__) || defined(__aarch64__)
359 size_t len = (char *)end - (char *)start;
360 #if defined(__BLACKBERRY_QNX__)
361 msync(start, len, MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE);
362 #elif defined(__MACH__)
363 sys_cache_control(kCacheFunctionPrepareForExecution, start, len);
365 sceKernelSyncVMDomain(sceBlock, start, len);
367 ctr_flush_invalidate_cache();
368 #elif defined(__aarch64__)
369 // as of 2021, __clear_cache() is still broken on arm64
370 // so here is a custom one :(
371 clear_cache_arm64(start, end);
373 __clear_cache(start, end);
378 mprotect_w_x(start, end, 1);
381 static void *start_block(void)
383 u_char *end = out + MAX_OUTPUT_BLOCK_SIZE;
384 if (end > ndrc->translation_cache + sizeof(ndrc->translation_cache))
385 end = ndrc->translation_cache + sizeof(ndrc->translation_cache);
386 start_tcache_write(out, end);
390 static void end_block(void *start)
392 end_tcache_write(start, out);
395 // also takes care of w^x mappings when patching code
396 static u_int needs_clear_cache[1<<(TARGET_SIZE_2-17)];
398 static void mark_clear_cache(void *target)
400 uintptr_t offset = (u_char *)target - ndrc->translation_cache;
401 u_int mask = 1u << ((offset >> 12) & 31);
402 if (!(needs_clear_cache[offset >> 17] & mask)) {
403 char *start = (char *)((uintptr_t)target & ~4095l);
404 start_tcache_write(start, start + 4095);
405 needs_clear_cache[offset >> 17] |= mask;
409 // Clearing the cache is rather slow on ARM Linux, so mark the areas
410 // that need to be cleared, and then only clear these areas once.
411 static void do_clear_cache(void)
414 for (i = 0; i < (1<<(TARGET_SIZE_2-17)); i++)
416 u_int bitmap = needs_clear_cache[i];
419 for (j = 0; j < 32; j++)
422 if (!(bitmap & (1<<j)))
425 start = ndrc->translation_cache + i*131072 + j*4096;
427 for (j++; j < 32; j++) {
428 if (!(bitmap & (1<<j)))
432 end_tcache_write(start, end);
434 needs_clear_cache[i] = 0;
438 //#define DEBUG_CYCLE_COUNT 1
440 #define NO_CYCLE_PENALTY_THR 12
442 int cycle_multiplier; // 100 for 1.0
444 static int CLOCK_ADJUST(int x)
447 return (x * cycle_multiplier + s * 50) / 100;
450 static u_int get_page(u_int vaddr)
452 u_int page=vaddr&~0xe0000000;
453 if (page < 0x1000000)
454 page &= ~0x0e00000; // RAM mirrors
456 if(page>2048) page=2048+(page&2047);
460 // no virtual mem in PCSX
461 static u_int get_vpage(u_int vaddr)
463 return get_page(vaddr);
466 static struct ht_entry *hash_table_get(u_int vaddr)
468 return &hash_table[((vaddr>>16)^vaddr)&0xFFFF];
471 static void hash_table_add(struct ht_entry *ht_bin, u_int vaddr, void *tcaddr)
473 ht_bin->vaddr[1] = ht_bin->vaddr[0];
474 ht_bin->tcaddr[1] = ht_bin->tcaddr[0];
475 ht_bin->vaddr[0] = vaddr;
476 ht_bin->tcaddr[0] = tcaddr;
479 // some messy ari64's code, seems to rely on unsigned 32bit overflow
480 static int doesnt_expire_soon(void *tcaddr)
482 u_int diff = (u_int)((u_char *)tcaddr - out) << (32-TARGET_SIZE_2);
483 return diff > (u_int)(0x60000000 + (MAX_OUTPUT_BLOCK_SIZE << (32-TARGET_SIZE_2)));
486 // Get address from virtual address
487 // This is called from the recompiled JR/JALR instructions
488 void noinline *get_addr(u_int vaddr)
490 u_int page=get_page(vaddr);
491 u_int vpage=get_vpage(vaddr);
492 struct ll_entry *head;
493 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
496 if(head->vaddr==vaddr) {
497 //printf("TRACE: count=%d next=%d (get_addr match %x: %p)\n",Count,next_interupt,vaddr,head->addr);
498 hash_table_add(hash_table_get(vaddr), vaddr, head->addr);
503 head=jump_dirty[vpage];
505 if(head->vaddr==vaddr) {
506 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %p)\n",Count,next_interupt,vaddr,head->addr);
507 // Don't restore blocks which are about to expire from the cache
508 if (doesnt_expire_soon(head->addr))
509 if (verify_dirty(head->addr)) {
510 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
511 invalid_code[vaddr>>12]=0;
512 inv_code_start=inv_code_end=~0;
514 restore_candidate[vpage>>3]|=1<<(vpage&7);
516 else restore_candidate[page>>3]|=1<<(page&7);
517 struct ht_entry *ht_bin = hash_table_get(vaddr);
518 if (ht_bin->vaddr[0] == vaddr)
519 ht_bin->tcaddr[0] = head->addr; // Replace existing entry
521 hash_table_add(ht_bin, vaddr, head->addr);
528 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
529 int r=new_recompile_block(vaddr);
530 if(r==0) return get_addr(vaddr);
531 // Execute in unmapped page, generate pagefault execption
533 Cause=(vaddr<<31)|0x8;
534 EPC=(vaddr&1)?vaddr-5:vaddr;
536 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
537 EntryHi=BadVAddr&0xFFFFE000;
538 return get_addr_ht(0x80000000);
540 // Look up address in hash table first
541 void *get_addr_ht(u_int vaddr)
543 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
544 const struct ht_entry *ht_bin = hash_table_get(vaddr);
545 if (ht_bin->vaddr[0] == vaddr) return ht_bin->tcaddr[0];
546 if (ht_bin->vaddr[1] == vaddr) return ht_bin->tcaddr[1];
547 return get_addr(vaddr);
550 void clear_all_regs(signed char regmap[])
553 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
556 static signed char get_reg(const signed char regmap[],int r)
559 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map[hr]==r) return hr;
563 // Find a register that is available for two consecutive cycles
564 static signed char get_reg2(signed char regmap1[], const signed char regmap2[], int r)
567 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr;
571 int count_free_regs(signed char regmap[])
575 for(hr=0;hr<HOST_REGS;hr++)
577 if(hr!=EXCLUDE_REG) {
578 if(regmap[hr]<0) count++;
584 void dirty_reg(struct regstat *cur,signed char reg)
588 for (hr=0;hr<HOST_REGS;hr++) {
589 if((cur->regmap[hr]&63)==reg) {
595 void set_const(struct regstat *cur,signed char reg,uint64_t value)
599 for (hr=0;hr<HOST_REGS;hr++) {
600 if(cur->regmap[hr]==reg) {
602 current_constmap[hr]=value;
607 void clear_const(struct regstat *cur,signed char reg)
611 for (hr=0;hr<HOST_REGS;hr++) {
612 if((cur->regmap[hr]&63)==reg) {
613 cur->isconst&=~(1<<hr);
618 int is_const(struct regstat *cur,signed char reg)
623 for (hr=0;hr<HOST_REGS;hr++) {
624 if((cur->regmap[hr]&63)==reg) {
625 return (cur->isconst>>hr)&1;
630 uint64_t get_const(struct regstat *cur,signed char reg)
634 for (hr=0;hr<HOST_REGS;hr++) {
635 if(cur->regmap[hr]==reg) {
636 return current_constmap[hr];
639 SysPrintf("Unknown constant in r%d\n",reg);
643 // Least soon needed registers
644 // Look at the next ten instructions and see which registers
645 // will be used. Try not to reallocate these.
646 void lsn(u_char hsn[], int i, int *preferred_reg)
656 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
658 // Don't go past an unconditonal jump
665 if(rs1[i+j]) hsn[rs1[i+j]]=j;
666 if(rs2[i+j]) hsn[rs2[i+j]]=j;
667 if(rt1[i+j]) hsn[rt1[i+j]]=j;
668 if(rt2[i+j]) hsn[rt2[i+j]]=j;
669 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
670 // Stores can allocate zero
674 // On some architectures stores need invc_ptr
675 #if defined(HOST_IMM8)
676 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
680 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP))
688 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
690 // Follow first branch
691 int t=(ba[i+b]-start)>>2;
692 j=7-b;if(t+j>=slen) j=slen-t-1;
695 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
696 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
697 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
698 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
701 // TODO: preferred register based on backward branch
703 // Delay slot should preferably not overwrite branch conditions or cycle count
704 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP)) {
705 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
706 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
712 // Coprocessor load/store needs FTEMP, even if not declared
713 if(itype[i]==C1LS||itype[i]==C2LS) {
716 // Load L/R also uses FTEMP as a temporary register
717 if(itype[i]==LOADLR) {
720 // Also SWL/SWR/SDL/SDR
721 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
724 // Don't remove the miniht registers
725 if(itype[i]==UJUMP||itype[i]==RJUMP)
732 // We only want to allocate registers if we're going to use them again soon
733 int needed_again(int r, int i)
739 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
741 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
742 return 0; // Don't need any registers if exiting the block
750 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
752 // Don't go past an unconditonal jump
756 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
763 if(rs1[i+j]==r) rn=j;
764 if(rs2[i+j]==r) rn=j;
765 if((unneeded_reg[i+j]>>r)&1) rn=10;
766 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP))
774 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
776 // Follow first branch
778 int t=(ba[i+b]-start)>>2;
779 j=7-b;if(t+j>=slen) j=slen-t-1;
782 if(!((unneeded_reg[t+j]>>r)&1)) {
783 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
784 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
795 // Try to match register allocations at the end of a loop with those
797 int loop_reg(int i, int r, int hr)
806 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
808 // Don't go past an unconditonal jump
815 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP)
821 if((unneeded_reg[i+k]>>r)&1) return hr;
822 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP))
824 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
826 int t=(ba[i+k]-start)>>2;
827 int reg=get_reg(regs[t].regmap_entry,r);
828 if(reg>=0) return reg;
829 //reg=get_reg(regs[t+1].regmap_entry,r);
830 //if(reg>=0) return reg;
838 // Allocate every register, preserving source/target regs
839 void alloc_all(struct regstat *cur,int i)
843 for(hr=0;hr<HOST_REGS;hr++) {
844 if(hr!=EXCLUDE_REG) {
845 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
846 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
849 cur->dirty&=~(1<<hr);
852 if((cur->regmap[hr]&63)==0)
855 cur->dirty&=~(1<<hr);
862 static int host_tempreg_in_use;
864 static void host_tempreg_acquire(void)
866 assert(!host_tempreg_in_use);
867 host_tempreg_in_use = 1;
870 static void host_tempreg_release(void)
872 host_tempreg_in_use = 0;
875 static void host_tempreg_acquire(void) {}
876 static void host_tempreg_release(void) {}
880 extern void gen_interupt();
881 extern void do_insn_cmp();
882 #define FUNCNAME(f) { f, " " #f }
883 static const struct {
886 } function_names[] = {
887 FUNCNAME(cc_interrupt),
888 FUNCNAME(gen_interupt),
889 FUNCNAME(get_addr_ht),
891 FUNCNAME(jump_handler_read8),
892 FUNCNAME(jump_handler_read16),
893 FUNCNAME(jump_handler_read32),
894 FUNCNAME(jump_handler_write8),
895 FUNCNAME(jump_handler_write16),
896 FUNCNAME(jump_handler_write32),
897 FUNCNAME(invalidate_addr),
898 FUNCNAME(jump_to_new_pc),
899 FUNCNAME(new_dyna_leave),
901 FUNCNAME(pcsx_mtc0_ds),
902 FUNCNAME(do_insn_cmp),
904 FUNCNAME(verify_code),
908 static const char *func_name(const void *a)
911 for (i = 0; i < sizeof(function_names)/sizeof(function_names[0]); i++)
912 if (function_names[i].addr == a)
913 return function_names[i].name;
917 #define func_name(x) ""
921 #include "assem_x86.c"
924 #include "assem_x64.c"
927 #include "assem_arm.c"
930 #include "assem_arm64.c"
933 static void *get_trampoline(const void *f)
937 for (i = 0; i < ARRAY_SIZE(ndrc->tramp.f); i++) {
938 if (ndrc->tramp.f[i] == f || ndrc->tramp.f[i] == NULL)
941 if (i == ARRAY_SIZE(ndrc->tramp.f)) {
942 SysPrintf("trampoline table is full, last func %p\n", f);
945 if (ndrc->tramp.f[i] == NULL) {
946 start_tcache_write(&ndrc->tramp.f[i], &ndrc->tramp.f[i + 1]);
947 ndrc->tramp.f[i] = f;
948 end_tcache_write(&ndrc->tramp.f[i], &ndrc->tramp.f[i + 1]);
950 return &ndrc->tramp.ops[i];
953 static void emit_far_jump(const void *f)
955 if (can_jump_or_call(f)) {
960 f = get_trampoline(f);
964 static void emit_far_call(const void *f)
966 if (can_jump_or_call(f)) {
971 f = get_trampoline(f);
975 // Add virtual address mapping to linked list
976 void ll_add(struct ll_entry **head,int vaddr,void *addr)
978 struct ll_entry *new_entry;
979 new_entry=malloc(sizeof(struct ll_entry));
980 assert(new_entry!=NULL);
981 new_entry->vaddr=vaddr;
982 new_entry->reg_sv_flags=0;
983 new_entry->addr=addr;
984 new_entry->next=*head;
988 void ll_add_flags(struct ll_entry **head,int vaddr,u_int reg_sv_flags,void *addr)
990 ll_add(head,vaddr,addr);
991 (*head)->reg_sv_flags=reg_sv_flags;
994 // Check if an address is already compiled
995 // but don't return addresses which are about to expire from the cache
996 void *check_addr(u_int vaddr)
998 struct ht_entry *ht_bin = hash_table_get(vaddr);
1000 for (i = 0; i < ARRAY_SIZE(ht_bin->vaddr); i++) {
1001 if (ht_bin->vaddr[i] == vaddr)
1002 if (doesnt_expire_soon((u_char *)ht_bin->tcaddr[i] - MAX_OUTPUT_BLOCK_SIZE))
1003 if (isclean(ht_bin->tcaddr[i]))
1004 return ht_bin->tcaddr[i];
1006 u_int page=get_page(vaddr);
1007 struct ll_entry *head;
1009 while (head != NULL) {
1010 if (head->vaddr == vaddr) {
1011 if (doesnt_expire_soon(head->addr)) {
1012 // Update existing entry with current address
1013 if (ht_bin->vaddr[0] == vaddr) {
1014 ht_bin->tcaddr[0] = head->addr;
1017 if (ht_bin->vaddr[1] == vaddr) {
1018 ht_bin->tcaddr[1] = head->addr;
1021 // Insert into hash table with low priority.
1022 // Don't evict existing entries, as they are probably
1023 // addresses that are being accessed frequently.
1024 if (ht_bin->vaddr[0] == -1) {
1025 ht_bin->vaddr[0] = vaddr;
1026 ht_bin->tcaddr[0] = head->addr;
1028 else if (ht_bin->vaddr[1] == -1) {
1029 ht_bin->vaddr[1] = vaddr;
1030 ht_bin->tcaddr[1] = head->addr;
1040 void remove_hash(int vaddr)
1042 //printf("remove hash: %x\n",vaddr);
1043 struct ht_entry *ht_bin = hash_table_get(vaddr);
1044 if (ht_bin->vaddr[1] == vaddr) {
1045 ht_bin->vaddr[1] = -1;
1046 ht_bin->tcaddr[1] = NULL;
1048 if (ht_bin->vaddr[0] == vaddr) {
1049 ht_bin->vaddr[0] = ht_bin->vaddr[1];
1050 ht_bin->tcaddr[0] = ht_bin->tcaddr[1];
1051 ht_bin->vaddr[1] = -1;
1052 ht_bin->tcaddr[1] = NULL;
1056 void ll_remove_matching_addrs(struct ll_entry **head,uintptr_t addr,int shift)
1058 struct ll_entry *next;
1060 if(((uintptr_t)((*head)->addr)>>shift)==(addr>>shift) ||
1061 ((uintptr_t)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1063 inv_debug("EXP: Remove pointer to %p (%x)\n",(*head)->addr,(*head)->vaddr);
1064 remove_hash((*head)->vaddr);
1071 head=&((*head)->next);
1076 // Remove all entries from linked list
1077 void ll_clear(struct ll_entry **head)
1079 struct ll_entry *cur;
1080 struct ll_entry *next;
1091 // Dereference the pointers and remove if it matches
1092 static void ll_kill_pointers(struct ll_entry *head,uintptr_t addr,int shift)
1095 uintptr_t ptr = (uintptr_t)get_pointer(head->addr);
1096 inv_debug("EXP: Lookup pointer to %lx at %p (%x)\n",(long)ptr,head->addr,head->vaddr);
1097 if(((ptr>>shift)==(addr>>shift)) ||
1098 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1100 inv_debug("EXP: Kill pointer at %p (%x)\n",head->addr,head->vaddr);
1101 void *host_addr=find_extjump_insn(head->addr);
1102 mark_clear_cache(host_addr);
1103 set_jump_target(host_addr, head->addr);
1109 // This is called when we write to a compiled block (see do_invstub)
1110 static void invalidate_page(u_int page)
1112 struct ll_entry *head;
1113 struct ll_entry *next;
1117 inv_debug("INVALIDATE: %x\n",head->vaddr);
1118 remove_hash(head->vaddr);
1123 head=jump_out[page];
1126 inv_debug("INVALIDATE: kill pointer to %x (%p)\n",head->vaddr,head->addr);
1127 void *host_addr=find_extjump_insn(head->addr);
1128 mark_clear_cache(host_addr);
1129 set_jump_target(host_addr, head->addr);
1136 static void invalidate_block_range(u_int block, u_int first, u_int last)
1138 u_int page=get_page(block<<12);
1139 //printf("first=%d last=%d\n",first,last);
1140 invalidate_page(page);
1141 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1142 assert(last<page+5);
1143 // Invalidate the adjacent pages if a block crosses a 4K boundary
1145 invalidate_page(first);
1148 for(first=page+1;first<last;first++) {
1149 invalidate_page(first);
1153 // Don't trap writes
1154 invalid_code[block]=1;
1157 memset(mini_ht,-1,sizeof(mini_ht));
1161 void invalidate_block(u_int block)
1163 u_int page=get_page(block<<12);
1164 u_int vpage=get_vpage(block<<12);
1165 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1166 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1169 struct ll_entry *head;
1170 head=jump_dirty[vpage];
1171 //printf("page=%d vpage=%d\n",page,vpage);
1173 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1174 u_char *start, *end;
1175 get_bounds(head->addr, &start, &end);
1176 //printf("start: %p end: %p\n", start, end);
1177 if (page < 2048 && start >= rdram && end < rdram+RAM_SIZE) {
1178 if (((start-rdram)>>12) <= page && ((end-1-rdram)>>12) >= page) {
1179 if ((((start-rdram)>>12)&2047) < first) first = ((start-rdram)>>12)&2047;
1180 if ((((end-1-rdram)>>12)&2047) > last) last = ((end-1-rdram)>>12)&2047;
1186 invalidate_block_range(block,first,last);
1189 void invalidate_addr(u_int addr)
1192 // this check is done by the caller
1193 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
1194 u_int page=get_vpage(addr);
1195 if(page<2048) { // RAM
1196 struct ll_entry *head;
1197 u_int addr_min=~0, addr_max=0;
1198 u_int mask=RAM_SIZE-1;
1199 u_int addr_main=0x80000000|(addr&mask);
1201 inv_code_start=addr_main&~0xfff;
1202 inv_code_end=addr_main|0xfff;
1205 // must check previous page too because of spans..
1207 inv_code_start-=0x1000;
1209 for(;pg1<=page;pg1++) {
1210 for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
1211 u_char *start_h, *end_h;
1213 get_bounds(head->addr, &start_h, &end_h);
1214 start = (uintptr_t)start_h - ram_offset;
1215 end = (uintptr_t)end_h - ram_offset;
1216 if(start<=addr_main&&addr_main<end) {
1217 if(start<addr_min) addr_min=start;
1218 if(end>addr_max) addr_max=end;
1220 else if(addr_main<start) {
1221 if(start<inv_code_end)
1222 inv_code_end=start-1;
1225 if(end>inv_code_start)
1231 inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1232 inv_code_start=inv_code_end=~0;
1233 invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1237 inv_code_start=(addr&~mask)|(inv_code_start&mask);
1238 inv_code_end=(addr&~mask)|(inv_code_end&mask);
1239 inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);
1243 invalidate_block(addr>>12);
1246 // This is called when loading a save state.
1247 // Anything could have changed, so invalidate everything.
1248 void invalidate_all_pages(void)
1251 for(page=0;page<4096;page++)
1252 invalidate_page(page);
1253 for(page=0;page<1048576;page++)
1254 if(!invalid_code[page]) {
1255 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1256 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1259 memset(mini_ht,-1,sizeof(mini_ht));
1264 static void do_invstub(int n)
1267 u_int reglist=stubs[n].a;
1268 set_jump_target(stubs[n].addr, out);
1270 if(stubs[n].b!=0) emit_mov(stubs[n].b,0);
1271 emit_far_call(invalidate_addr);
1272 restore_regs(reglist);
1273 emit_jmp(stubs[n].retaddr); // return address
1276 // Add an entry to jump_out after making a link
1277 // src should point to code by emit_extjump2()
1278 void add_link(u_int vaddr,void *src)
1280 u_int page=get_page(vaddr);
1281 inv_debug("add_link: %p -> %x (%d)\n",src,vaddr,page);
1282 check_extjump2(src);
1283 ll_add(jump_out+page,vaddr,src);
1284 //void *ptr=get_pointer(src);
1285 //inv_debug("add_link: Pointer is to %p\n",ptr);
1288 // If a code block was found to be unmodified (bit was set in
1289 // restore_candidate) and it remains unmodified (bit is clear
1290 // in invalid_code) then move the entries for that 4K page from
1291 // the dirty list to the clean list.
1292 void clean_blocks(u_int page)
1294 struct ll_entry *head;
1295 inv_debug("INV: clean_blocks page=%d\n",page);
1296 head=jump_dirty[page];
1298 if(!invalid_code[head->vaddr>>12]) {
1299 // Don't restore blocks which are about to expire from the cache
1300 if (doesnt_expire_soon(head->addr)) {
1301 if(verify_dirty(head->addr)) {
1302 u_char *start, *end;
1303 //printf("Possibly Restore %x (%p)\n",head->vaddr, head->addr);
1306 get_bounds(head->addr, &start, &end);
1307 if (start - rdram < RAM_SIZE) {
1308 for (i = (start-rdram+0x80000000)>>12; i <= (end-1-rdram+0x80000000)>>12; i++) {
1309 inv|=invalid_code[i];
1312 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1316 void *clean_addr = get_clean_addr(head->addr);
1317 if (doesnt_expire_soon(clean_addr)) {
1319 inv_debug("INV: Restored %x (%p/%p)\n",head->vaddr, head->addr, clean_addr);
1320 //printf("page=%x, addr=%x\n",page,head->vaddr);
1321 //assert(head->vaddr>>12==(page|0x80000));
1322 ll_add_flags(jump_in+ppage,head->vaddr,head->reg_sv_flags,clean_addr);
1323 struct ht_entry *ht_bin = hash_table_get(head->vaddr);
1324 if (ht_bin->vaddr[0] == head->vaddr)
1325 ht_bin->tcaddr[0] = clean_addr; // Replace existing entry
1326 if (ht_bin->vaddr[1] == head->vaddr)
1327 ht_bin->tcaddr[1] = clean_addr; // Replace existing entry
1337 /* Register allocation */
1339 // Note: registers are allocated clean (unmodified state)
1340 // if you intend to modify the register, you must call dirty_reg().
1341 static void alloc_reg(struct regstat *cur,int i,signed char reg)
1344 int preferred_reg = (reg&7);
1345 if(reg==CCREG) preferred_reg=HOST_CCREG;
1346 if(reg==PTEMP||reg==FTEMP) preferred_reg=12;
1348 // Don't allocate unused registers
1349 if((cur->u>>reg)&1) return;
1351 // see if it's already allocated
1352 for(hr=0;hr<HOST_REGS;hr++)
1354 if(cur->regmap[hr]==reg) return;
1357 // Keep the same mapping if the register was already allocated in a loop
1358 preferred_reg = loop_reg(i,reg,preferred_reg);
1360 // Try to allocate the preferred register
1361 if(cur->regmap[preferred_reg]==-1) {
1362 cur->regmap[preferred_reg]=reg;
1363 cur->dirty&=~(1<<preferred_reg);
1364 cur->isconst&=~(1<<preferred_reg);
1367 r=cur->regmap[preferred_reg];
1370 cur->regmap[preferred_reg]=reg;
1371 cur->dirty&=~(1<<preferred_reg);
1372 cur->isconst&=~(1<<preferred_reg);
1376 // Clear any unneeded registers
1377 // We try to keep the mapping consistent, if possible, because it
1378 // makes branches easier (especially loops). So we try to allocate
1379 // first (see above) before removing old mappings. If this is not
1380 // possible then go ahead and clear out the registers that are no
1382 for(hr=0;hr<HOST_REGS;hr++)
1387 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
1390 // Try to allocate any available register, but prefer
1391 // registers that have not been used recently.
1393 for(hr=0;hr<HOST_REGS;hr++) {
1394 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
1395 if(regs[i-1].regmap[hr]!=rs1[i-1]&®s[i-1].regmap[hr]!=rs2[i-1]&®s[i-1].regmap[hr]!=rt1[i-1]&®s[i-1].regmap[hr]!=rt2[i-1]) {
1396 cur->regmap[hr]=reg;
1397 cur->dirty&=~(1<<hr);
1398 cur->isconst&=~(1<<hr);
1404 // Try to allocate any available register
1405 for(hr=0;hr<HOST_REGS;hr++) {
1406 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
1407 cur->regmap[hr]=reg;
1408 cur->dirty&=~(1<<hr);
1409 cur->isconst&=~(1<<hr);
1414 // Ok, now we have to evict someone
1415 // Pick a register we hopefully won't need soon
1416 u_char hsn[MAXREG+1];
1417 memset(hsn,10,sizeof(hsn));
1419 lsn(hsn,i,&preferred_reg);
1420 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
1421 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
1423 // Don't evict the cycle count at entry points, otherwise the entry
1424 // stub will have to write it.
1425 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
1426 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP)) hsn[CCREG]=2;
1429 // Alloc preferred register if available
1430 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
1431 for(hr=0;hr<HOST_REGS;hr++) {
1432 // Evict both parts of a 64-bit register
1433 if((cur->regmap[hr]&63)==r) {
1435 cur->dirty&=~(1<<hr);
1436 cur->isconst&=~(1<<hr);
1439 cur->regmap[preferred_reg]=reg;
1442 for(r=1;r<=MAXREG;r++)
1444 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
1445 for(hr=0;hr<HOST_REGS;hr++) {
1446 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
1447 if(cur->regmap[hr]==r) {
1448 cur->regmap[hr]=reg;
1449 cur->dirty&=~(1<<hr);
1450 cur->isconst&=~(1<<hr);
1461 for(r=1;r<=MAXREG;r++)
1464 for(hr=0;hr<HOST_REGS;hr++) {
1465 if(cur->regmap[hr]==r) {
1466 cur->regmap[hr]=reg;
1467 cur->dirty&=~(1<<hr);
1468 cur->isconst&=~(1<<hr);
1475 SysPrintf("This shouldn't happen (alloc_reg)");abort();
1478 // Allocate a temporary register. This is done without regard to
1479 // dirty status or whether the register we request is on the unneeded list
1480 // Note: This will only allocate one register, even if called multiple times
1481 static void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
1484 int preferred_reg = -1;
1486 // see if it's already allocated
1487 for(hr=0;hr<HOST_REGS;hr++)
1489 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==reg) return;
1492 // Try to allocate any available register
1493 for(hr=HOST_REGS-1;hr>=0;hr--) {
1494 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
1495 cur->regmap[hr]=reg;
1496 cur->dirty&=~(1<<hr);
1497 cur->isconst&=~(1<<hr);
1502 // Find an unneeded register
1503 for(hr=HOST_REGS-1;hr>=0;hr--)
1509 if(i==0||((unneeded_reg[i-1]>>r)&1)) {
1510 cur->regmap[hr]=reg;
1511 cur->dirty&=~(1<<hr);
1512 cur->isconst&=~(1<<hr);
1519 // Ok, now we have to evict someone
1520 // Pick a register we hopefully won't need soon
1521 // TODO: we might want to follow unconditional jumps here
1522 // TODO: get rid of dupe code and make this into a function
1523 u_char hsn[MAXREG+1];
1524 memset(hsn,10,sizeof(hsn));
1526 lsn(hsn,i,&preferred_reg);
1527 //printf("hsn: %d %d %d %d %d %d %d\n",hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
1529 // Don't evict the cycle count at entry points, otherwise the entry
1530 // stub will have to write it.
1531 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
1532 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP)) hsn[CCREG]=2;
1535 for(r=1;r<=MAXREG;r++)
1537 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
1538 for(hr=0;hr<HOST_REGS;hr++) {
1539 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
1540 if(cur->regmap[hr]==r) {
1541 cur->regmap[hr]=reg;
1542 cur->dirty&=~(1<<hr);
1543 cur->isconst&=~(1<<hr);
1554 for(r=1;r<=MAXREG;r++)
1557 for(hr=0;hr<HOST_REGS;hr++) {
1558 if(cur->regmap[hr]==r) {
1559 cur->regmap[hr]=reg;
1560 cur->dirty&=~(1<<hr);
1561 cur->isconst&=~(1<<hr);
1568 SysPrintf("This shouldn't happen");abort();
1571 static void mov_alloc(struct regstat *current,int i)
1573 // Note: Don't need to actually alloc the source registers
1574 //alloc_reg(current,i,rs1[i]);
1575 alloc_reg(current,i,rt1[i]);
1577 clear_const(current,rs1[i]);
1578 clear_const(current,rt1[i]);
1579 dirty_reg(current,rt1[i]);
1582 static void shiftimm_alloc(struct regstat *current,int i)
1584 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1587 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1589 alloc_reg(current,i,rt1[i]);
1590 dirty_reg(current,rt1[i]);
1591 if(is_const(current,rs1[i])) {
1592 int v=get_const(current,rs1[i]);
1593 if(opcode2[i]==0x00) set_const(current,rt1[i],v<<imm[i]);
1594 if(opcode2[i]==0x02) set_const(current,rt1[i],(u_int)v>>imm[i]);
1595 if(opcode2[i]==0x03) set_const(current,rt1[i],v>>imm[i]);
1597 else clear_const(current,rt1[i]);
1602 clear_const(current,rs1[i]);
1603 clear_const(current,rt1[i]);
1606 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1610 if(opcode2[i]==0x3c) // DSLL32
1614 if(opcode2[i]==0x3e) // DSRL32
1618 if(opcode2[i]==0x3f) // DSRA32
1624 static void shift_alloc(struct regstat *current,int i)
1627 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1629 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1630 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1631 alloc_reg(current,i,rt1[i]);
1632 if(rt1[i]==rs2[i]) {
1633 alloc_reg_temp(current,i,-1);
1634 minimum_free_regs[i]=1;
1636 } else { // DSLLV/DSRLV/DSRAV
1639 clear_const(current,rs1[i]);
1640 clear_const(current,rs2[i]);
1641 clear_const(current,rt1[i]);
1642 dirty_reg(current,rt1[i]);
1646 static void alu_alloc(struct regstat *current,int i)
1648 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1650 if(rs1[i]&&rs2[i]) {
1651 alloc_reg(current,i,rs1[i]);
1652 alloc_reg(current,i,rs2[i]);
1655 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1656 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1658 alloc_reg(current,i,rt1[i]);
1661 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1663 alloc_reg(current,i,rs1[i]);
1664 alloc_reg(current,i,rs2[i]);
1665 alloc_reg(current,i,rt1[i]);
1668 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1670 if(rs1[i]&&rs2[i]) {
1671 alloc_reg(current,i,rs1[i]);
1672 alloc_reg(current,i,rs2[i]);
1676 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1677 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1679 alloc_reg(current,i,rt1[i]);
1682 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1685 clear_const(current,rs1[i]);
1686 clear_const(current,rs2[i]);
1687 clear_const(current,rt1[i]);
1688 dirty_reg(current,rt1[i]);
1691 static void imm16_alloc(struct regstat *current,int i)
1693 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1695 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1696 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1699 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1700 clear_const(current,rs1[i]);
1701 clear_const(current,rt1[i]);
1703 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1704 if(is_const(current,rs1[i])) {
1705 int v=get_const(current,rs1[i]);
1706 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1707 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1708 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1710 else clear_const(current,rt1[i]);
1712 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1713 if(is_const(current,rs1[i])) {
1714 int v=get_const(current,rs1[i]);
1715 set_const(current,rt1[i],v+imm[i]);
1717 else clear_const(current,rt1[i]);
1720 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1722 dirty_reg(current,rt1[i]);
1725 static void load_alloc(struct regstat *current,int i)
1727 clear_const(current,rt1[i]);
1728 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1729 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1730 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1731 if(rt1[i]&&!((current->u>>rt1[i])&1)) {
1732 alloc_reg(current,i,rt1[i]);
1733 assert(get_reg(current->regmap,rt1[i])>=0);
1734 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1738 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1742 dirty_reg(current,rt1[i]);
1743 // LWL/LWR need a temporary register for the old value
1744 if(opcode[i]==0x22||opcode[i]==0x26)
1746 alloc_reg(current,i,FTEMP);
1747 alloc_reg_temp(current,i,-1);
1748 minimum_free_regs[i]=1;
1753 // Load to r0 or unneeded register (dummy load)
1754 // but we still need a register to calculate the address
1755 if(opcode[i]==0x22||opcode[i]==0x26)
1757 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1759 alloc_reg_temp(current,i,-1);
1760 minimum_free_regs[i]=1;
1761 if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1768 void store_alloc(struct regstat *current,int i)
1770 clear_const(current,rs2[i]);
1771 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1772 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1773 alloc_reg(current,i,rs2[i]);
1774 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1777 #if defined(HOST_IMM8)
1778 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1779 else alloc_reg(current,i,INVCP);
1781 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1782 alloc_reg(current,i,FTEMP);
1784 // We need a temporary register for address generation
1785 alloc_reg_temp(current,i,-1);
1786 minimum_free_regs[i]=1;
1789 void c1ls_alloc(struct regstat *current,int i)
1791 //clear_const(current,rs1[i]); // FIXME
1792 clear_const(current,rt1[i]);
1793 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1794 alloc_reg(current,i,CSREG); // Status
1795 alloc_reg(current,i,FTEMP);
1796 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1799 #if defined(HOST_IMM8)
1800 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1801 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1802 alloc_reg(current,i,INVCP);
1804 // We need a temporary register for address generation
1805 alloc_reg_temp(current,i,-1);
1808 void c2ls_alloc(struct regstat *current,int i)
1810 clear_const(current,rt1[i]);
1811 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1812 alloc_reg(current,i,FTEMP);
1813 #if defined(HOST_IMM8)
1814 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1815 if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1816 alloc_reg(current,i,INVCP);
1818 // We need a temporary register for address generation
1819 alloc_reg_temp(current,i,-1);
1820 minimum_free_regs[i]=1;
1823 #ifndef multdiv_alloc
1824 void multdiv_alloc(struct regstat *current,int i)
1831 // case 0x1D: DMULTU
1834 clear_const(current,rs1[i]);
1835 clear_const(current,rs2[i]);
1838 if((opcode2[i]&4)==0) // 32-bit
1840 current->u&=~(1LL<<HIREG);
1841 current->u&=~(1LL<<LOREG);
1842 alloc_reg(current,i,HIREG);
1843 alloc_reg(current,i,LOREG);
1844 alloc_reg(current,i,rs1[i]);
1845 alloc_reg(current,i,rs2[i]);
1846 dirty_reg(current,HIREG);
1847 dirty_reg(current,LOREG);
1856 // Multiply by zero is zero.
1857 // MIPS does not have a divide by zero exception.
1858 // The result is undefined, we return zero.
1859 alloc_reg(current,i,HIREG);
1860 alloc_reg(current,i,LOREG);
1861 dirty_reg(current,HIREG);
1862 dirty_reg(current,LOREG);
1867 void cop0_alloc(struct regstat *current,int i)
1869 if(opcode2[i]==0) // MFC0
1872 clear_const(current,rt1[i]);
1873 alloc_all(current,i);
1874 alloc_reg(current,i,rt1[i]);
1875 dirty_reg(current,rt1[i]);
1878 else if(opcode2[i]==4) // MTC0
1881 clear_const(current,rs1[i]);
1882 alloc_reg(current,i,rs1[i]);
1883 alloc_all(current,i);
1886 alloc_all(current,i); // FIXME: Keep r0
1888 alloc_reg(current,i,0);
1893 // TLBR/TLBWI/TLBWR/TLBP/ERET
1894 assert(opcode2[i]==0x10);
1895 alloc_all(current,i);
1897 minimum_free_regs[i]=HOST_REGS;
1900 static void cop12_alloc(struct regstat *current,int i)
1902 alloc_reg(current,i,CSREG); // Load status
1903 if(opcode2[i]<3) // MFC1/CFC1
1906 clear_const(current,rt1[i]);
1907 alloc_reg(current,i,rt1[i]);
1908 dirty_reg(current,rt1[i]);
1910 alloc_reg_temp(current,i,-1);
1912 else if(opcode2[i]>3) // MTC1/CTC1
1915 clear_const(current,rs1[i]);
1916 alloc_reg(current,i,rs1[i]);
1920 alloc_reg(current,i,0);
1922 alloc_reg_temp(current,i,-1);
1924 minimum_free_regs[i]=1;
1927 void c2op_alloc(struct regstat *current,int i)
1929 alloc_reg_temp(current,i,-1);
1932 void syscall_alloc(struct regstat *current,int i)
1934 alloc_cc(current,i);
1935 dirty_reg(current,CCREG);
1936 alloc_all(current,i);
1937 minimum_free_regs[i]=HOST_REGS;
1941 void delayslot_alloc(struct regstat *current,int i)
1951 assem_debug("jump in the delay slot. this shouldn't happen.\n");//abort();
1952 SysPrintf("Disabled speculative precompilation\n");
1956 imm16_alloc(current,i);
1960 load_alloc(current,i);
1964 store_alloc(current,i);
1967 alu_alloc(current,i);
1970 shift_alloc(current,i);
1973 multdiv_alloc(current,i);
1976 shiftimm_alloc(current,i);
1979 mov_alloc(current,i);
1982 cop0_alloc(current,i);
1986 cop12_alloc(current,i);
1989 c1ls_alloc(current,i);
1992 c2ls_alloc(current,i);
1995 c2op_alloc(current,i);
2000 // Special case where a branch and delay slot span two pages in virtual memory
2001 static void pagespan_alloc(struct regstat *current,int i)
2004 current->wasconst=0;
2006 minimum_free_regs[i]=HOST_REGS;
2007 alloc_all(current,i);
2008 alloc_cc(current,i);
2009 dirty_reg(current,CCREG);
2010 if(opcode[i]==3) // JAL
2012 alloc_reg(current,i,31);
2013 dirty_reg(current,31);
2015 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
2017 alloc_reg(current,i,rs1[i]);
2019 alloc_reg(current,i,rt1[i]);
2020 dirty_reg(current,rt1[i]);
2023 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
2025 if(rs1[i]) alloc_reg(current,i,rs1[i]);
2026 if(rs2[i]) alloc_reg(current,i,rs2[i]);
2029 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
2031 if(rs1[i]) alloc_reg(current,i,rs1[i]);
2036 static void add_stub(enum stub_type type, void *addr, void *retaddr,
2037 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e)
2039 assert(stubcount < ARRAY_SIZE(stubs));
2040 stubs[stubcount].type = type;
2041 stubs[stubcount].addr = addr;
2042 stubs[stubcount].retaddr = retaddr;
2043 stubs[stubcount].a = a;
2044 stubs[stubcount].b = b;
2045 stubs[stubcount].c = c;
2046 stubs[stubcount].d = d;
2047 stubs[stubcount].e = e;
2051 static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
2052 int i, int addr_reg, struct regstat *i_regs, int ccadj, u_int reglist)
2054 add_stub(type, addr, retaddr, i, addr_reg, (uintptr_t)i_regs, ccadj, reglist);
2057 // Write out a single register
2058 static void wb_register(signed char r,signed char regmap[],uint64_t dirty)
2061 for(hr=0;hr<HOST_REGS;hr++) {
2062 if(hr!=EXCLUDE_REG) {
2063 if((regmap[hr]&63)==r) {
2065 assert(regmap[hr]<64);
2066 emit_storereg(r,hr);
2073 static void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t u)
2075 //if(dirty_pre==dirty) return;
2077 for(hr=0;hr<HOST_REGS;hr++) {
2078 if(hr!=EXCLUDE_REG) {
2080 if(((~u)>>(reg&63))&1) {
2082 if(((dirty_pre&~dirty)>>hr)&1) {
2084 emit_storereg(reg,hr);
2097 static void pass_args(int a0, int a1)
2101 emit_mov(a0,2); emit_mov(a1,1); emit_mov(2,0);
2103 else if(a0!=0&&a1==0) {
2105 if (a0>=0) emit_mov(a0,0);
2108 if(a0>=0&&a0!=0) emit_mov(a0,0);
2109 if(a1>=0&&a1!=1) emit_mov(a1,1);
2113 static void alu_assemble(int i,struct regstat *i_regs)
2115 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2117 signed char s1,s2,t;
2118 t=get_reg(i_regs->regmap,rt1[i]);
2120 s1=get_reg(i_regs->regmap,rs1[i]);
2121 s2=get_reg(i_regs->regmap,rs2[i]);
2122 if(rs1[i]&&rs2[i]) {
2125 if(opcode2[i]&2) emit_sub(s1,s2,t);
2126 else emit_add(s1,s2,t);
2129 if(s1>=0) emit_mov(s1,t);
2130 else emit_loadreg(rs1[i],t);
2134 if(opcode2[i]&2) emit_neg(s2,t);
2135 else emit_mov(s2,t);
2138 emit_loadreg(rs2[i],t);
2139 if(opcode2[i]&2) emit_neg(t,t);
2142 else emit_zeroreg(t);
2146 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2149 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2151 signed char s1l,s2l,t;
2153 t=get_reg(i_regs->regmap,rt1[i]);
2156 s1l=get_reg(i_regs->regmap,rs1[i]);
2157 s2l=get_reg(i_regs->regmap,rs2[i]);
2158 if(rs2[i]==0) // rx<r0
2160 if(opcode2[i]==0x2a&&rs1[i]!=0) { // SLT
2162 emit_shrimm(s1l,31,t);
2164 else // SLTU (unsigned can not be less than zero, 0<0)
2167 else if(rs1[i]==0) // r0<rx
2170 if(opcode2[i]==0x2a) // SLT
2171 emit_set_gz32(s2l,t);
2172 else // SLTU (set if not zero)
2173 emit_set_nz32(s2l,t);
2176 assert(s1l>=0);assert(s2l>=0);
2177 if(opcode2[i]==0x2a) // SLT
2178 emit_set_if_less32(s1l,s2l,t);
2180 emit_set_if_carry32(s1l,s2l,t);
2186 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2188 signed char s1l,s2l,tl;
2189 tl=get_reg(i_regs->regmap,rt1[i]);
2192 s1l=get_reg(i_regs->regmap,rs1[i]);
2193 s2l=get_reg(i_regs->regmap,rs2[i]);
2194 if(rs1[i]&&rs2[i]) {
2197 if(opcode2[i]==0x24) { // AND
2198 emit_and(s1l,s2l,tl);
2200 if(opcode2[i]==0x25) { // OR
2201 emit_or(s1l,s2l,tl);
2203 if(opcode2[i]==0x26) { // XOR
2204 emit_xor(s1l,s2l,tl);
2206 if(opcode2[i]==0x27) { // NOR
2207 emit_or(s1l,s2l,tl);
2213 if(opcode2[i]==0x24) { // AND
2216 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2218 if(s1l>=0) emit_mov(s1l,tl);
2219 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2223 if(s2l>=0) emit_mov(s2l,tl);
2224 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2226 else emit_zeroreg(tl);
2228 if(opcode2[i]==0x27) { // NOR
2230 if(s1l>=0) emit_not(s1l,tl);
2232 emit_loadreg(rs1[i],tl);
2238 if(s2l>=0) emit_not(s2l,tl);
2240 emit_loadreg(rs2[i],tl);
2244 else emit_movimm(-1,tl);
2253 void imm16_assemble(int i,struct regstat *i_regs)
2255 if (opcode[i]==0x0f) { // LUI
2258 t=get_reg(i_regs->regmap,rt1[i]);
2261 if(!((i_regs->isconst>>t)&1))
2262 emit_movimm(imm[i]<<16,t);
2266 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2269 t=get_reg(i_regs->regmap,rt1[i]);
2270 s=get_reg(i_regs->regmap,rs1[i]);
2275 if(!((i_regs->isconst>>t)&1)) {
2277 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2278 emit_addimm(t,imm[i],t);
2280 if(!((i_regs->wasconst>>s)&1))
2281 emit_addimm(s,imm[i],t);
2283 emit_movimm(constmap[i][s]+imm[i],t);
2289 if(!((i_regs->isconst>>t)&1))
2290 emit_movimm(imm[i],t);
2295 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2298 tl=get_reg(i_regs->regmap,rt1[i]);
2299 sl=get_reg(i_regs->regmap,rs1[i]);
2303 emit_addimm(sl,imm[i],tl);
2305 emit_movimm(imm[i],tl);
2310 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2312 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2314 t=get_reg(i_regs->regmap,rt1[i]);
2315 sl=get_reg(i_regs->regmap,rs1[i]);
2319 if(opcode[i]==0x0a) { // SLTI
2321 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2322 emit_slti32(t,imm[i],t);
2324 emit_slti32(sl,imm[i],t);
2329 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2330 emit_sltiu32(t,imm[i],t);
2332 emit_sltiu32(sl,imm[i],t);
2336 // SLTI(U) with r0 is just stupid,
2337 // nonetheless examples can be found
2338 if(opcode[i]==0x0a) // SLTI
2339 if(0<imm[i]) emit_movimm(1,t);
2340 else emit_zeroreg(t);
2343 if(imm[i]) emit_movimm(1,t);
2344 else emit_zeroreg(t);
2350 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2353 tl=get_reg(i_regs->regmap,rt1[i]);
2354 sl=get_reg(i_regs->regmap,rs1[i]);
2355 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2356 if(opcode[i]==0x0c) //ANDI
2360 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2361 emit_andimm(tl,imm[i],tl);
2363 if(!((i_regs->wasconst>>sl)&1))
2364 emit_andimm(sl,imm[i],tl);
2366 emit_movimm(constmap[i][sl]&imm[i],tl);
2376 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2378 if(opcode[i]==0x0d) { // ORI
2380 emit_orimm(tl,imm[i],tl);
2382 if(!((i_regs->wasconst>>sl)&1))
2383 emit_orimm(sl,imm[i],tl);
2385 emit_movimm(constmap[i][sl]|imm[i],tl);
2388 if(opcode[i]==0x0e) { // XORI
2390 emit_xorimm(tl,imm[i],tl);
2392 if(!((i_regs->wasconst>>sl)&1))
2393 emit_xorimm(sl,imm[i],tl);
2395 emit_movimm(constmap[i][sl]^imm[i],tl);
2400 emit_movimm(imm[i],tl);
2408 void shiftimm_assemble(int i,struct regstat *i_regs)
2410 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2414 t=get_reg(i_regs->regmap,rt1[i]);
2415 s=get_reg(i_regs->regmap,rs1[i]);
2417 if(t>=0&&!((i_regs->isconst>>t)&1)){
2424 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2426 if(opcode2[i]==0) // SLL
2428 emit_shlimm(s<0?t:s,imm[i],t);
2430 if(opcode2[i]==2) // SRL
2432 emit_shrimm(s<0?t:s,imm[i],t);
2434 if(opcode2[i]==3) // SRA
2436 emit_sarimm(s<0?t:s,imm[i],t);
2440 if(s>=0 && s!=t) emit_mov(s,t);
2444 //emit_storereg(rt1[i],t); //DEBUG
2447 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2451 if(opcode2[i]==0x3c) // DSLL32
2455 if(opcode2[i]==0x3e) // DSRL32
2459 if(opcode2[i]==0x3f) // DSRA32
2465 #ifndef shift_assemble
2466 static void shift_assemble(int i,struct regstat *i_regs)
2468 signed char s,t,shift;
2471 assert(opcode2[i]<=0x07); // SLLV/SRLV/SRAV
2472 t = get_reg(i_regs->regmap, rt1[i]);
2473 s = get_reg(i_regs->regmap, rs1[i]);
2474 shift = get_reg(i_regs->regmap, rs2[i]);
2480 else if(rs2[i]==0) {
2482 if(s!=t) emit_mov(s,t);
2485 host_tempreg_acquire();
2486 emit_andimm(shift,31,HOST_TEMPREG);
2487 switch(opcode2[i]) {
2489 emit_shl(s,HOST_TEMPREG,t);
2492 emit_shr(s,HOST_TEMPREG,t);
2495 emit_sar(s,HOST_TEMPREG,t);
2500 host_tempreg_release();
2514 static int get_ptr_mem_type(u_int a)
2516 if(a < 0x00200000) {
2517 if(a<0x1000&&((start>>20)==0xbfc||(start>>24)==0xa0))
2518 // return wrong, must use memhandler for BIOS self-test to pass
2519 // 007 does similar stuff from a00 mirror, weird stuff
2523 if(0x1f800000 <= a && a < 0x1f801000)
2525 if(0x80200000 <= a && a < 0x80800000)
2527 if(0xa0000000 <= a && a < 0xa0200000)
2532 static void *emit_fastpath_cmp_jump(int i,int addr,int *addr_reg_override)
2537 if(((smrv_strong|smrv_weak)>>mr)&1) {
2538 type=get_ptr_mem_type(smrv[mr]);
2539 //printf("set %08x @%08x r%d %d\n", smrv[mr], start+i*4, mr, type);
2542 // use the mirror we are running on
2543 type=get_ptr_mem_type(start);
2544 //printf("set nospec @%08x r%d %d\n", start+i*4, mr, type);
2547 if(type==MTYPE_8020) { // RAM 80200000+ mirror
2548 host_tempreg_acquire();
2549 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
2550 addr=*addr_reg_override=HOST_TEMPREG;
2553 else if(type==MTYPE_0000) { // RAM 0 mirror
2554 host_tempreg_acquire();
2555 emit_orimm(addr,0x80000000,HOST_TEMPREG);
2556 addr=*addr_reg_override=HOST_TEMPREG;
2559 else if(type==MTYPE_A000) { // RAM A mirror
2560 host_tempreg_acquire();
2561 emit_andimm(addr,~0x20000000,HOST_TEMPREG);
2562 addr=*addr_reg_override=HOST_TEMPREG;
2565 else if(type==MTYPE_1F80) { // scratchpad
2566 if (psxH == (void *)0x1f800000) {
2567 host_tempreg_acquire();
2568 emit_xorimm(addr,0x1f800000,HOST_TEMPREG);
2569 emit_cmpimm(HOST_TEMPREG,0x1000);
2570 host_tempreg_release();
2575 // do the usual RAM check, jump will go to the right handler
2582 emit_cmpimm(addr,RAM_SIZE);
2584 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2585 // Hint to branch predictor that the branch is unlikely to be taken
2587 emit_jno_unlikely(0);
2592 host_tempreg_acquire();
2593 emit_addimm(addr,ram_offset,HOST_TEMPREG);
2594 addr=*addr_reg_override=HOST_TEMPREG;
2601 // return memhandler, or get directly accessable address and return 0
2602 static void *get_direct_memhandler(void *table, u_int addr,
2603 enum stub_type type, uintptr_t *addr_host)
2605 uintptr_t l1, l2 = 0;
2606 l1 = ((uintptr_t *)table)[addr>>12];
2607 if ((l1 & (1ul << (sizeof(l1)*8-1))) == 0) {
2608 uintptr_t v = l1 << 1;
2609 *addr_host = v + addr;
2614 if (type == LOADB_STUB || type == LOADBU_STUB || type == STOREB_STUB)
2615 l2 = ((uintptr_t *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)];
2616 else if (type == LOADH_STUB || type == LOADHU_STUB || type == STOREH_STUB)
2617 l2=((uintptr_t *)l1)[0x1000/4 + (addr&0xfff)/2];
2619 l2=((uintptr_t *)l1)[(addr&0xfff)/4];
2620 if ((l2 & (1<<31)) == 0) {
2621 uintptr_t v = l2 << 1;
2622 *addr_host = v + (addr&0xfff);
2625 return (void *)(l2 << 1);
2629 static void load_assemble(int i,struct regstat *i_regs)
2634 int memtarget=0,c=0;
2635 int fastio_reg_override=-1;
2637 tl=get_reg(i_regs->regmap,rt1[i]);
2638 s=get_reg(i_regs->regmap,rs1[i]);
2640 for(hr=0;hr<HOST_REGS;hr++) {
2641 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2643 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2645 c=(i_regs->wasconst>>s)&1;
2647 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2650 //printf("load_assemble: c=%d\n",c);
2651 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
2652 // FIXME: Even if the load is a NOP, we should check for pagefaults...
2653 if((tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80))
2655 // could be FIFO, must perform the read
2657 assem_debug("(forced read)\n");
2658 tl=get_reg(i_regs->regmap,-1);
2661 if(offset||s<0||c) addr=tl;
2663 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2665 //printf("load_assemble: c=%d\n",c);
2666 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
2667 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2671 // Strmnnrmn's speed hack
2672 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2675 jaddr=emit_fastpath_cmp_jump(i,addr,&fastio_reg_override);
2678 else if(ram_offset&&memtarget) {
2679 host_tempreg_acquire();
2680 emit_addimm(addr,ram_offset,HOST_TEMPREG);
2681 fastio_reg_override=HOST_TEMPREG;
2683 int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2684 if (opcode[i]==0x20) { // LB
2690 if(fastio_reg_override>=0) a=fastio_reg_override;
2692 emit_movsbl_indexed(x,a,tl);
2696 add_stub_r(LOADB_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist);
2699 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2701 if (opcode[i]==0x21) { // LH
2706 if(fastio_reg_override>=0) a=fastio_reg_override;
2707 emit_movswl_indexed(x,a,tl);
2710 add_stub_r(LOADH_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist);
2713 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2715 if (opcode[i]==0x23) { // LW
2719 if(fastio_reg_override>=0) a=fastio_reg_override;
2720 emit_readword_indexed(0,a,tl);
2723 add_stub_r(LOADW_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist);
2726 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2728 if (opcode[i]==0x24) { // LBU
2733 if(fastio_reg_override>=0) a=fastio_reg_override;
2735 emit_movzbl_indexed(x,a,tl);
2738 add_stub_r(LOADBU_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist);
2741 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2743 if (opcode[i]==0x25) { // LHU
2748 if(fastio_reg_override>=0) a=fastio_reg_override;
2749 emit_movzwl_indexed(x,a,tl);
2752 add_stub_r(LOADHU_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist);
2755 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2757 if (opcode[i]==0x27) { // LWU
2760 if (opcode[i]==0x37) { // LD
2764 if (fastio_reg_override == HOST_TEMPREG)
2765 host_tempreg_release();
2768 #ifndef loadlr_assemble
2769 static void loadlr_assemble(int i,struct regstat *i_regs)
2771 int s,tl,temp,temp2,addr;
2774 int memtarget=0,c=0;
2775 int fastio_reg_override=-1;
2777 tl=get_reg(i_regs->regmap,rt1[i]);
2778 s=get_reg(i_regs->regmap,rs1[i]);
2779 temp=get_reg(i_regs->regmap,-1);
2780 temp2=get_reg(i_regs->regmap,FTEMP);
2781 addr=get_reg(i_regs->regmap,AGEN1+(i&1));
2784 for(hr=0;hr<HOST_REGS;hr++) {
2785 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2788 if(offset||s<0||c) addr=temp2;
2791 c=(i_regs->wasconst>>s)&1;
2793 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2797 emit_shlimm(addr,3,temp);
2798 if (opcode[i]==0x22||opcode[i]==0x26) {
2799 emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR
2801 emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR
2803 jaddr=emit_fastpath_cmp_jump(i,temp2,&fastio_reg_override);
2806 if(ram_offset&&memtarget) {
2807 host_tempreg_acquire();
2808 emit_addimm(temp2,ram_offset,HOST_TEMPREG);
2809 fastio_reg_override=HOST_TEMPREG;
2811 if (opcode[i]==0x22||opcode[i]==0x26) {
2812 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
2814 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
2817 if (opcode[i]==0x22||opcode[i]==0x26) { // LWL/LWR
2820 if(fastio_reg_override>=0) a=fastio_reg_override;
2821 emit_readword_indexed(0,a,temp2);
2822 if(fastio_reg_override==HOST_TEMPREG) host_tempreg_release();
2823 if(jaddr) add_stub_r(LOADW_STUB,jaddr,out,i,temp2,i_regs,ccadj[i],reglist);
2826 inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj[i],reglist);
2829 emit_andimm(temp,24,temp);
2830 if (opcode[i]==0x22) // LWL
2831 emit_xorimm(temp,24,temp);
2832 host_tempreg_acquire();
2833 emit_movimm(-1,HOST_TEMPREG);
2834 if (opcode[i]==0x26) {
2835 emit_shr(temp2,temp,temp2);
2836 emit_bic_lsr(tl,HOST_TEMPREG,temp,tl);
2838 emit_shl(temp2,temp,temp2);
2839 emit_bic_lsl(tl,HOST_TEMPREG,temp,tl);
2841 host_tempreg_release();
2842 emit_or(temp2,tl,tl);
2844 //emit_storereg(rt1[i],tl); // DEBUG
2846 if (opcode[i]==0x1A||opcode[i]==0x1B) { // LDL/LDR
2852 void store_assemble(int i,struct regstat *i_regs)
2858 enum stub_type type;
2859 int memtarget=0,c=0;
2860 int agr=AGEN1+(i&1);
2861 int fastio_reg_override=-1;
2863 tl=get_reg(i_regs->regmap,rs2[i]);
2864 s=get_reg(i_regs->regmap,rs1[i]);
2865 temp=get_reg(i_regs->regmap,agr);
2866 if(temp<0) temp=get_reg(i_regs->regmap,-1);
2869 c=(i_regs->wasconst>>s)&1;
2871 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2876 for(hr=0;hr<HOST_REGS;hr++) {
2877 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2879 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2880 if(offset||s<0||c) addr=temp;
2883 jaddr=emit_fastpath_cmp_jump(i,addr,&fastio_reg_override);
2885 else if(ram_offset&&memtarget) {
2886 host_tempreg_acquire();
2887 emit_addimm(addr,ram_offset,HOST_TEMPREG);
2888 fastio_reg_override=HOST_TEMPREG;
2891 if (opcode[i]==0x28) { // SB
2895 if(fastio_reg_override>=0) a=fastio_reg_override;
2896 emit_writebyte_indexed(tl,x,a);
2900 if (opcode[i]==0x29) { // SH
2904 if(fastio_reg_override>=0) a=fastio_reg_override;
2905 emit_writehword_indexed(tl,x,a);
2909 if (opcode[i]==0x2B) { // SW
2912 if(fastio_reg_override>=0) a=fastio_reg_override;
2913 emit_writeword_indexed(tl,0,a);
2917 if (opcode[i]==0x3F) { // SD
2921 if(fastio_reg_override==HOST_TEMPREG)
2922 host_tempreg_release();
2924 // PCSX store handlers don't check invcode again
2926 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj[i],reglist);
2929 if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
2931 #ifdef DESTRUCTIVE_SHIFT
2932 // The x86 shift operation is 'destructive'; it overwrites the
2933 // source register, so we need to make a copy first and use that.
2936 #if defined(HOST_IMM8)
2937 int ir=get_reg(i_regs->regmap,INVCP);
2939 emit_cmpmem_indexedsr12_reg(ir,addr,1);
2941 emit_cmpmem_indexedsr12_imm(invalid_code,addr,1);
2943 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
2944 emit_callne(invalidate_addr_reg[addr]);
2948 add_stub(INVCODE_STUB,jaddr2,out,reglist|(1<<HOST_CCREG),addr,0,0,0);
2952 u_int addr_val=constmap[i][s]+offset;
2954 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj[i],reglist);
2955 } else if(c&&!memtarget) {
2956 inline_writestub(type,i,addr_val,i_regs->regmap,rs2[i],ccadj[i],reglist);
2958 // basic current block modification detection..
2959 // not looking back as that should be in mips cache already
2960 // (see Spyro2 title->attract mode)
2961 if(c&&start+i*4<addr_val&&addr_val<start+slen*4) {
2962 SysPrintf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4);
2963 assert(i_regs->regmap==regs[i].regmap); // not delay slot
2964 if(i_regs->regmap==regs[i].regmap) {
2965 load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
2966 wb_dirtys(regs[i].regmap_entry,regs[i].wasdirty);
2967 emit_movimm(start+i*4+4,0);
2968 emit_writeword(0,&pcaddr);
2969 emit_addimm(HOST_CCREG,2,HOST_CCREG);
2970 emit_far_call(get_addr_ht);
2976 static void storelr_assemble(int i,struct regstat *i_regs)
2982 void *case1, *case2, *case3;
2983 void *done0, *done1, *done2;
2984 int memtarget=0,c=0;
2985 int agr=AGEN1+(i&1);
2987 tl=get_reg(i_regs->regmap,rs2[i]);
2988 s=get_reg(i_regs->regmap,rs1[i]);
2989 temp=get_reg(i_regs->regmap,agr);
2990 if(temp<0) temp=get_reg(i_regs->regmap,-1);
2993 c=(i_regs->isconst>>s)&1;
2995 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2999 for(hr=0;hr<HOST_REGS;hr++) {
3000 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3004 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3005 if(!offset&&s!=temp) emit_mov(s,temp);
3011 if(!memtarget||!rs1[i]) {
3017 emit_addimm_no_flags(ram_offset,temp);
3019 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3023 emit_xorimm(temp,3,temp);
3024 emit_testimm(temp,2);
3027 emit_testimm(temp,1);
3031 if (opcode[i]==0x2A) { // SWL
3032 emit_writeword_indexed(tl,0,temp);
3034 else if (opcode[i]==0x2E) { // SWR
3035 emit_writebyte_indexed(tl,3,temp);
3042 set_jump_target(case1, out);
3043 if (opcode[i]==0x2A) { // SWL
3044 // Write 3 msb into three least significant bytes
3045 if(rs2[i]) emit_rorimm(tl,8,tl);
3046 emit_writehword_indexed(tl,-1,temp);
3047 if(rs2[i]) emit_rorimm(tl,16,tl);
3048 emit_writebyte_indexed(tl,1,temp);
3049 if(rs2[i]) emit_rorimm(tl,8,tl);
3051 else if (opcode[i]==0x2E) { // SWR
3052 // Write two lsb into two most significant bytes
3053 emit_writehword_indexed(tl,1,temp);
3058 set_jump_target(case2, out);
3059 emit_testimm(temp,1);
3062 if (opcode[i]==0x2A) { // SWL
3063 // Write two msb into two least significant bytes
3064 if(rs2[i]) emit_rorimm(tl,16,tl);
3065 emit_writehword_indexed(tl,-2,temp);
3066 if(rs2[i]) emit_rorimm(tl,16,tl);
3068 else if (opcode[i]==0x2E) { // SWR
3069 // Write 3 lsb into three most significant bytes
3070 emit_writebyte_indexed(tl,-1,temp);
3071 if(rs2[i]) emit_rorimm(tl,8,tl);
3072 emit_writehword_indexed(tl,0,temp);
3073 if(rs2[i]) emit_rorimm(tl,24,tl);
3078 set_jump_target(case3, out);
3079 if (opcode[i]==0x2A) { // SWL
3080 // Write msb into least significant byte
3081 if(rs2[i]) emit_rorimm(tl,24,tl);
3082 emit_writebyte_indexed(tl,-3,temp);
3083 if(rs2[i]) emit_rorimm(tl,8,tl);
3085 else if (opcode[i]==0x2E) { // SWR
3086 // Write entire word
3087 emit_writeword_indexed(tl,-3,temp);
3089 set_jump_target(done0, out);
3090 set_jump_target(done1, out);
3091 set_jump_target(done2, out);
3093 add_stub_r(STORELR_STUB,jaddr,out,i,temp,i_regs,ccadj[i],reglist);
3094 if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3095 emit_addimm_no_flags(-ram_offset,temp);
3096 #if defined(HOST_IMM8)
3097 int ir=get_reg(i_regs->regmap,INVCP);
3099 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3101 emit_cmpmem_indexedsr12_imm(invalid_code,temp,1);
3103 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3104 emit_callne(invalidate_addr_reg[temp]);
3108 add_stub(INVCODE_STUB,jaddr2,out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3113 static void cop0_assemble(int i,struct regstat *i_regs)
3115 if(opcode2[i]==0) // MFC0
3117 signed char t=get_reg(i_regs->regmap,rt1[i]);
3118 u_int copr=(source[i]>>11)&0x1f;
3119 //assert(t>=0); // Why does this happen? OOT is weird
3120 if(t>=0&&rt1[i]!=0) {
3121 emit_readword(®_cop0[copr],t);
3124 else if(opcode2[i]==4) // MTC0
3126 signed char s=get_reg(i_regs->regmap,rs1[i]);
3127 char copr=(source[i]>>11)&0x1f;
3129 wb_register(rs1[i],i_regs->regmap,i_regs->dirty);
3130 if(copr==9||copr==11||copr==12||copr==13) {
3131 emit_readword(&last_count,HOST_TEMPREG);
3132 emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
3133 emit_add(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
3134 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
3135 emit_writeword(HOST_CCREG,&Count);
3137 // What a mess. The status register (12) can enable interrupts,
3138 // so needs a special case to handle a pending interrupt.
3139 // The interrupt must be taken immediately, because a subsequent
3140 // instruction might disable interrupts again.
3141 if(copr==12||copr==13) {
3143 // burn cycles to cause cc_interrupt, which will
3144 // reschedule next_interupt. Relies on CCREG from above.
3145 assem_debug("MTC0 DS %d\n", copr);
3146 emit_writeword(HOST_CCREG,&last_count);
3147 emit_movimm(0,HOST_CCREG);
3148 emit_storereg(CCREG,HOST_CCREG);
3149 emit_loadreg(rs1[i],1);
3150 emit_movimm(copr,0);
3151 emit_far_call(pcsx_mtc0_ds);
3152 emit_loadreg(rs1[i],s);
3155 emit_movimm(start+i*4+4,HOST_TEMPREG);
3156 emit_writeword(HOST_TEMPREG,&pcaddr);
3157 emit_movimm(0,HOST_TEMPREG);
3158 emit_writeword(HOST_TEMPREG,&pending_exception);
3161 emit_loadreg(rs1[i],1);
3164 emit_movimm(copr,0);
3165 emit_far_call(pcsx_mtc0);
3166 if(copr==9||copr==11||copr==12||copr==13) {
3167 emit_readword(&Count,HOST_CCREG);
3168 emit_readword(&next_interupt,HOST_TEMPREG);
3169 emit_addimm(HOST_CCREG,-CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
3170 emit_sub(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
3171 emit_writeword(HOST_TEMPREG,&last_count);
3172 emit_storereg(CCREG,HOST_CCREG);
3174 if(copr==12||copr==13) {
3175 assert(!is_delayslot);
3176 emit_readword(&pending_exception,14);
3180 emit_readword(&pcaddr, 0);
3181 emit_addimm(HOST_CCREG,2,HOST_CCREG);
3182 emit_far_call(get_addr_ht);
3184 set_jump_target(jaddr, out);
3186 emit_loadreg(rs1[i],s);
3190 assert(opcode2[i]==0x10);
3191 //if((source[i]&0x3f)==0x10) // RFE
3193 emit_readword(&Status,0);
3194 emit_andimm(0,0x3c,1);
3195 emit_andimm(0,~0xf,0);
3196 emit_orrshr_imm(1,2,0);
3197 emit_writeword(0,&Status);
3202 static void cop1_unusable(int i,struct regstat *i_regs)
3204 // XXX: should just just do the exception instead
3209 add_stub_r(FP_STUB,jaddr,out,i,0,i_regs,is_delayslot,0);
3213 static void cop1_assemble(int i,struct regstat *i_regs)
3215 cop1_unusable(i, i_regs);
3218 static void c1ls_assemble(int i,struct regstat *i_regs)
3220 cop1_unusable(i, i_regs);
3224 static void do_cop1stub(int n)
3227 assem_debug("do_cop1stub %x\n",start+stubs[n].a*4);
3228 set_jump_target(stubs[n].addr, out);
3230 // int rs=stubs[n].b;
3231 struct regstat *i_regs=(struct regstat *)stubs[n].c;
3234 load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
3235 //if(i_regs!=®s[i]) printf("oops: regs[i]=%x i_regs=%x",(int)®s[i],(int)i_regs);
3237 //else {printf("fp exception in delay slot\n");}
3238 wb_dirtys(i_regs->regmap_entry,i_regs->wasdirty);
3239 if(regs[i].regmap_entry[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
3240 emit_movimm(start+(i-ds)*4,EAX); // Get PC
3241 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
3242 emit_far_jump(ds?fp_exception_ds:fp_exception);
3245 static void cop2_get_dreg(u_int copr,signed char tl,signed char temp)
3255 emit_readword(®_cop2d[copr],tl);
3256 emit_signextend16(tl,tl);
3257 emit_writeword(tl,®_cop2d[copr]); // hmh
3264 emit_readword(®_cop2d[copr],tl);
3265 emit_andimm(tl,0xffff,tl);
3266 emit_writeword(tl,®_cop2d[copr]);
3269 emit_readword(®_cop2d[14],tl); // SXY2
3270 emit_writeword(tl,®_cop2d[copr]);
3274 c2op_mfc2_29_assemble(tl,temp);
3277 emit_readword(®_cop2d[copr],tl);
3282 static void cop2_put_dreg(u_int copr,signed char sl,signed char temp)
3286 emit_readword(®_cop2d[13],temp); // SXY1
3287 emit_writeword(sl,®_cop2d[copr]);
3288 emit_writeword(temp,®_cop2d[12]); // SXY0
3289 emit_readword(®_cop2d[14],temp); // SXY2
3290 emit_writeword(sl,®_cop2d[14]);
3291 emit_writeword(temp,®_cop2d[13]); // SXY1
3294 emit_andimm(sl,0x001f,temp);
3295 emit_shlimm(temp,7,temp);
3296 emit_writeword(temp,®_cop2d[9]);
3297 emit_andimm(sl,0x03e0,temp);
3298 emit_shlimm(temp,2,temp);
3299 emit_writeword(temp,®_cop2d[10]);
3300 emit_andimm(sl,0x7c00,temp);
3301 emit_shrimm(temp,3,temp);
3302 emit_writeword(temp,®_cop2d[11]);
3303 emit_writeword(sl,®_cop2d[28]);
3306 emit_xorsar_imm(sl,sl,31,temp);
3307 #if defined(HAVE_ARMV5) || defined(__aarch64__)
3308 emit_clz(temp,temp);
3310 emit_movs(temp,HOST_TEMPREG);
3311 emit_movimm(0,temp);
3312 emit_jeq((int)out+4*4);
3313 emit_addpl_imm(temp,1,temp);
3314 emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG);
3315 emit_jns((int)out-2*4);
3317 emit_writeword(sl,®_cop2d[30]);
3318 emit_writeword(temp,®_cop2d[31]);
3323 emit_writeword(sl,®_cop2d[copr]);
3328 static void c2ls_assemble(int i,struct regstat *i_regs)
3333 int memtarget=0,c=0;
3335 enum stub_type type;
3336 int agr=AGEN1+(i&1);
3337 int fastio_reg_override=-1;
3339 u_int copr=(source[i]>>16)&0x1f;
3340 s=get_reg(i_regs->regmap,rs1[i]);
3341 tl=get_reg(i_regs->regmap,FTEMP);
3346 for(hr=0;hr<HOST_REGS;hr++) {
3347 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3349 if(i_regs->regmap[HOST_CCREG]==CCREG)
3350 reglist&=~(1<<HOST_CCREG);
3353 if (opcode[i]==0x3a) { // SWC2
3354 ar=get_reg(i_regs->regmap,agr);
3355 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3360 if(s>=0) c=(i_regs->wasconst>>s)&1;
3361 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3362 if (!offset&&!c&&s>=0) ar=s;
3365 if (opcode[i]==0x3a) { // SWC2
3366 cop2_get_dreg(copr,tl,-1);
3374 emit_jmp(0); // inline_readstub/inline_writestub?
3378 jaddr2=emit_fastpath_cmp_jump(i,ar,&fastio_reg_override);
3380 else if(ram_offset&&memtarget) {
3381 host_tempreg_acquire();
3382 emit_addimm(ar,ram_offset,HOST_TEMPREG);
3383 fastio_reg_override=HOST_TEMPREG;
3385 if (opcode[i]==0x32) { // LWC2
3387 if(fastio_reg_override>=0) a=fastio_reg_override;
3388 emit_readword_indexed(0,a,tl);
3390 if (opcode[i]==0x3a) { // SWC2
3391 #ifdef DESTRUCTIVE_SHIFT
3392 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3395 if(fastio_reg_override>=0) a=fastio_reg_override;
3396 emit_writeword_indexed(tl,0,a);
3399 if(fastio_reg_override==HOST_TEMPREG)
3400 host_tempreg_release();
3402 add_stub_r(type,jaddr2,out,i,ar,i_regs,ccadj[i],reglist);
3403 if(opcode[i]==0x3a) // SWC2
3404 if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3405 #if defined(HOST_IMM8)
3406 int ir=get_reg(i_regs->regmap,INVCP);
3408 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3410 emit_cmpmem_indexedsr12_imm(invalid_code,ar,1);
3412 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3413 emit_callne(invalidate_addr_reg[ar]);
3417 add_stub(INVCODE_STUB,jaddr3,out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3420 if (opcode[i]==0x32) { // LWC2
3421 host_tempreg_acquire();
3422 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3423 host_tempreg_release();
3427 static void cop2_assemble(int i,struct regstat *i_regs)
3429 u_int copr=(source[i]>>11)&0x1f;
3430 signed char temp=get_reg(i_regs->regmap,-1);
3431 if (opcode2[i]==0) { // MFC2
3432 signed char tl=get_reg(i_regs->regmap,rt1[i]);
3433 if(tl>=0&&rt1[i]!=0)
3434 cop2_get_dreg(copr,tl,temp);
3436 else if (opcode2[i]==4) { // MTC2
3437 signed char sl=get_reg(i_regs->regmap,rs1[i]);
3438 cop2_put_dreg(copr,sl,temp);
3440 else if (opcode2[i]==2) // CFC2
3442 signed char tl=get_reg(i_regs->regmap,rt1[i]);
3443 if(tl>=0&&rt1[i]!=0)
3444 emit_readword(®_cop2c[copr],tl);
3446 else if (opcode2[i]==6) // CTC2
3448 signed char sl=get_reg(i_regs->regmap,rs1[i]);
3457 emit_signextend16(sl,temp);
3460 c2op_ctc2_31_assemble(sl,temp);
3466 emit_writeword(temp,®_cop2c[copr]);
3471 static void do_unalignedwritestub(int n)
3473 assem_debug("do_unalignedwritestub %x\n",start+stubs[n].a*4);
3475 set_jump_target(stubs[n].addr, out);
3478 struct regstat *i_regs=(struct regstat *)stubs[n].c;
3479 int addr=stubs[n].b;
3480 u_int reglist=stubs[n].e;
3481 signed char *i_regmap=i_regs->regmap;
3482 int temp2=get_reg(i_regmap,FTEMP);
3484 rt=get_reg(i_regmap,rs2[i]);
3487 assert(opcode[i]==0x2a||opcode[i]==0x2e); // SWL/SWR only implemented
3489 reglist&=~(1<<temp2);
3492 // don't bother with it and call write handler
3495 int cc=get_reg(i_regmap,CCREG);
3497 emit_loadreg(CCREG,2);
3498 emit_addimm(cc<0?2:cc,CLOCK_ADJUST((int)stubs[n].d+1),2);
3499 emit_far_call((opcode[i]==0x2a?jump_handle_swl:jump_handle_swr));
3500 emit_addimm(0,-CLOCK_ADJUST((int)stubs[n].d+1),cc<0?2:cc);
3502 emit_storereg(CCREG,2);
3503 restore_regs(reglist);
3504 emit_jmp(stubs[n].retaddr); // return address
3506 emit_andimm(addr,0xfffffffc,temp2);
3507 emit_writeword(temp2,&address);
3510 emit_shrimm(addr,16,1);
3511 int cc=get_reg(i_regmap,CCREG);
3513 emit_loadreg(CCREG,2);
3515 emit_movimm((u_int)readmem,0);
3516 emit_addimm(cc<0?2:cc,2*stubs[n].d+2,2);
3517 emit_call((int)&indirect_jump_indexed);
3518 restore_regs(reglist);
3520 emit_readword(&readmem_dword,temp2);
3521 int temp=addr; //hmh
3522 emit_shlimm(addr,3,temp);
3523 emit_andimm(temp,24,temp);
3524 if (opcode[i]==0x2a) // SWL
3525 emit_xorimm(temp,24,temp);
3526 emit_movimm(-1,HOST_TEMPREG);
3527 if (opcode[i]==0x2a) { // SWL
3528 emit_bic_lsr(temp2,HOST_TEMPREG,temp,temp2);
3529 emit_orrshr(rt,temp,temp2);
3531 emit_bic_lsl(temp2,HOST_TEMPREG,temp,temp2);
3532 emit_orrshl(rt,temp,temp2);
3534 emit_readword(&address,addr);
3535 emit_writeword(temp2,&word);
3536 //save_regs(reglist); // don't need to, no state changes
3537 emit_shrimm(addr,16,1);
3538 emit_movimm((u_int)writemem,0);
3539 //emit_call((int)&indirect_jump_indexed);
3541 emit_readword_dualindexedx4(0,1,15);
3542 emit_readword(&Count,HOST_TEMPREG);
3543 emit_readword(&next_interupt,2);
3544 emit_addimm(HOST_TEMPREG,-2*stubs[n].d-2,HOST_TEMPREG);
3545 emit_writeword(2,&last_count);
3546 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
3548 emit_storereg(CCREG,HOST_TEMPREG);
3550 restore_regs(reglist);
3551 emit_jmp(stubs[n].retaddr); // return address
3555 #ifndef multdiv_assemble
3556 void multdiv_assemble(int i,struct regstat *i_regs)
3558 printf("Need multdiv_assemble for this architecture.\n");
3563 static void mov_assemble(int i,struct regstat *i_regs)
3565 //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3566 //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3569 tl=get_reg(i_regs->regmap,rt1[i]);
3572 sl=get_reg(i_regs->regmap,rs1[i]);
3573 if(sl>=0) emit_mov(sl,tl);
3574 else emit_loadreg(rs1[i],tl);
3579 // call interpreter, exception handler, things that change pc/regs/cycles ...
3580 static void call_c_cpu_handler(int i, const struct regstat *i_regs, u_int pc, void *func)
3582 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3583 assert(ccreg==HOST_CCREG);
3584 assert(!is_delayslot);
3587 emit_movimm(pc,3); // Get PC
3588 emit_readword(&last_count,2);
3589 emit_writeword(3,&psxRegs.pc);
3590 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // XXX
3591 emit_add(2,HOST_CCREG,2);
3592 emit_writeword(2,&psxRegs.cycle);
3593 emit_far_call(func);
3594 emit_far_jump(jump_to_new_pc);
3597 static void syscall_assemble(int i,struct regstat *i_regs)
3599 emit_movimm(0x20,0); // cause code
3600 emit_movimm(0,1); // not in delay slot
3601 call_c_cpu_handler(i,i_regs,start+i*4,psxException);
3604 static void hlecall_assemble(int i,struct regstat *i_regs)
3606 void *hlefunc = psxNULL;
3607 uint32_t hleCode = source[i] & 0x03ffffff;
3608 if (hleCode < ARRAY_SIZE(psxHLEt))
3609 hlefunc = psxHLEt[hleCode];
3611 call_c_cpu_handler(i,i_regs,start+i*4+4,hlefunc);
3614 static void intcall_assemble(int i,struct regstat *i_regs)
3616 call_c_cpu_handler(i,i_regs,start+i*4,execI);
3619 static void speculate_mov(int rs,int rt)
3622 smrv_strong_next|=1<<rt;
3627 static void speculate_mov_weak(int rs,int rt)
3630 smrv_weak_next|=1<<rt;
3635 static void speculate_register_values(int i)
3638 memcpy(smrv,psxRegs.GPR.r,sizeof(smrv));
3639 // gp,sp are likely to stay the same throughout the block
3640 smrv_strong_next=(1<<28)|(1<<29)|(1<<30);
3641 smrv_weak_next=~smrv_strong_next;
3642 //printf(" llr %08x\n", smrv[4]);
3644 smrv_strong=smrv_strong_next;
3645 smrv_weak=smrv_weak_next;
3648 if ((smrv_strong>>rs1[i])&1) speculate_mov(rs1[i],rt1[i]);
3649 else if((smrv_strong>>rs2[i])&1) speculate_mov(rs2[i],rt1[i]);
3650 else if((smrv_weak>>rs1[i])&1) speculate_mov_weak(rs1[i],rt1[i]);
3651 else if((smrv_weak>>rs2[i])&1) speculate_mov_weak(rs2[i],rt1[i]);
3653 smrv_strong_next&=~(1<<rt1[i]);
3654 smrv_weak_next&=~(1<<rt1[i]);
3658 smrv_strong_next&=~(1<<rt1[i]);
3659 smrv_weak_next&=~(1<<rt1[i]);
3662 if(rt1[i]&&is_const(®s[i],rt1[i])) {
3663 int value,hr=get_reg(regs[i].regmap,rt1[i]);
3665 if(get_final_value(hr,i,&value))
3667 else smrv[rt1[i]]=constmap[i][hr];
3668 smrv_strong_next|=1<<rt1[i];
3672 if ((smrv_strong>>rs1[i])&1) speculate_mov(rs1[i],rt1[i]);
3673 else if((smrv_weak>>rs1[i])&1) speculate_mov_weak(rs1[i],rt1[i]);
3677 if(start<0x2000&&(rt1[i]==26||(smrv[rt1[i]]>>24)==0xa0)) {
3678 // special case for BIOS
3679 smrv[rt1[i]]=0xa0000000;
3680 smrv_strong_next|=1<<rt1[i];
3687 smrv_strong_next&=~(1<<rt1[i]);
3688 smrv_weak_next&=~(1<<rt1[i]);
3692 if(opcode2[i]==0||opcode2[i]==2) { // MFC/CFC
3693 smrv_strong_next&=~(1<<rt1[i]);
3694 smrv_weak_next&=~(1<<rt1[i]);
3698 if (opcode[i]==0x32) { // LWC2
3699 smrv_strong_next&=~(1<<rt1[i]);
3700 smrv_weak_next&=~(1<<rt1[i]);
3706 printf("x %08x %08x %d %d c %08x %08x\n",smrv[r],start+i*4,
3707 ((smrv_strong>>r)&1),(smrv_weak>>r)&1,regs[i].isconst,regs[i].wasconst);
3711 static void ds_assemble(int i,struct regstat *i_regs)
3713 speculate_register_values(i);
3717 alu_assemble(i,i_regs);break;
3719 imm16_assemble(i,i_regs);break;
3721 shift_assemble(i,i_regs);break;
3723 shiftimm_assemble(i,i_regs);break;
3725 load_assemble(i,i_regs);break;
3727 loadlr_assemble(i,i_regs);break;
3729 store_assemble(i,i_regs);break;
3731 storelr_assemble(i,i_regs);break;
3733 cop0_assemble(i,i_regs);break;
3735 cop1_assemble(i,i_regs);break;
3737 c1ls_assemble(i,i_regs);break;
3739 cop2_assemble(i,i_regs);break;
3741 c2ls_assemble(i,i_regs);break;
3743 c2op_assemble(i,i_regs);break;
3745 multdiv_assemble(i,i_regs);break;
3747 mov_assemble(i,i_regs);break;
3756 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
3761 // Is the branch target a valid internal jump?
3762 static int internal_branch(int addr)
3764 if(addr&1) return 0; // Indirect (register) jump
3765 if(addr>=start && addr<start+slen*4-4)
3772 static void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t u)
3775 for(hr=0;hr<HOST_REGS;hr++) {
3776 if(hr!=EXCLUDE_REG) {
3777 if(pre[hr]!=entry[hr]) {
3780 if(get_reg(entry,pre[hr])<0) {
3782 if(!((u>>pre[hr])&1))
3783 emit_storereg(pre[hr],hr);
3790 // Move from one register to another (no writeback)
3791 for(hr=0;hr<HOST_REGS;hr++) {
3792 if(hr!=EXCLUDE_REG) {
3793 if(pre[hr]!=entry[hr]) {
3794 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
3796 if((nr=get_reg(entry,pre[hr]))>=0) {
3805 // Load the specified registers
3806 // This only loads the registers given as arguments because
3807 // we don't want to load things that will be overwritten
3808 static void load_regs(signed char entry[],signed char regmap[],int rs1,int rs2)
3812 for(hr=0;hr<HOST_REGS;hr++) {
3813 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
3814 if(entry[hr]!=regmap[hr]) {
3815 if(regmap[hr]==rs1||regmap[hr]==rs2)
3822 emit_loadreg(regmap[hr],hr);
3830 // Load registers prior to the start of a loop
3831 // so that they are not loaded within the loop
3832 static void loop_preload(signed char pre[],signed char entry[])
3835 for(hr=0;hr<HOST_REGS;hr++) {
3836 if(hr!=EXCLUDE_REG) {
3837 if(pre[hr]!=entry[hr]) {
3839 if(get_reg(pre,entry[hr])<0) {
3840 assem_debug("loop preload:\n");
3841 //printf("loop preload: %d\n",hr);
3845 else if(entry[hr]<TEMPREG)
3847 emit_loadreg(entry[hr],hr);
3849 else if(entry[hr]-64<TEMPREG)
3851 emit_loadreg(entry[hr],hr);
3860 // Generate address for load/store instruction
3861 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
3862 void address_generation(int i,struct regstat *i_regs,signed char entry[])
3864 if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
3866 int agr=AGEN1+(i&1);
3867 if(itype[i]==LOAD) {
3868 ra=get_reg(i_regs->regmap,rt1[i]);
3869 if(ra<0) ra=get_reg(i_regs->regmap,-1);
3872 if(itype[i]==LOADLR) {
3873 ra=get_reg(i_regs->regmap,FTEMP);
3875 if(itype[i]==STORE||itype[i]==STORELR) {
3876 ra=get_reg(i_regs->regmap,agr);
3877 if(ra<0) ra=get_reg(i_regs->regmap,-1);
3879 if(itype[i]==C1LS||itype[i]==C2LS) {
3880 if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
3881 ra=get_reg(i_regs->regmap,FTEMP);
3882 else { // SWC1/SDC1/SWC2/SDC2
3883 ra=get_reg(i_regs->regmap,agr);
3884 if(ra<0) ra=get_reg(i_regs->regmap,-1);
3887 int rs=get_reg(i_regs->regmap,rs1[i]);
3890 int c=(i_regs->wasconst>>rs)&1;
3892 // Using r0 as a base address
3893 if(!entry||entry[ra]!=agr) {
3894 if (opcode[i]==0x22||opcode[i]==0x26) {
3895 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
3896 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
3897 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
3899 emit_movimm(offset,ra);
3901 } // else did it in the previous cycle
3904 if(!entry||entry[ra]!=rs1[i])
3905 emit_loadreg(rs1[i],ra);
3906 //if(!entry||entry[ra]!=rs1[i])
3907 // printf("poor load scheduling!\n");
3910 if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
3911 if(!entry||entry[ra]!=agr) {
3912 if (opcode[i]==0x22||opcode[i]==0x26) {
3913 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
3914 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
3915 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
3917 emit_movimm(constmap[i][rs]+offset,ra);
3918 regs[i].loadedconst|=1<<ra;
3920 } // else did it in the previous cycle
3921 } // else load_consts already did it
3923 if(offset&&!c&&rs1[i]) {
3925 emit_addimm(rs,offset,ra);
3927 emit_addimm(ra,offset,ra);
3932 // Preload constants for next instruction
3933 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
3936 agr=AGEN1+((i+1)&1);
3937 ra=get_reg(i_regs->regmap,agr);
3939 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
3940 int offset=imm[i+1];
3941 int c=(regs[i+1].wasconst>>rs)&1;
3942 if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
3943 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
3944 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
3945 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
3946 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
3948 emit_movimm(constmap[i+1][rs]+offset,ra);
3949 regs[i+1].loadedconst|=1<<ra;
3952 else if(rs1[i+1]==0) {
3953 // Using r0 as a base address
3954 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
3955 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
3956 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
3957 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
3959 emit_movimm(offset,ra);
3966 static int get_final_value(int hr, int i, int *value)
3968 int reg=regs[i].regmap[hr];
3970 if(regs[i+1].regmap[hr]!=reg) break;
3971 if(!((regs[i+1].isconst>>hr)&1)) break;
3976 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
3977 *value=constmap[i][hr];
3981 if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
3982 // Load in delay slot, out-of-order execution
3983 if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
3985 // Precompute load address
3986 *value=constmap[i][hr]+imm[i+2];
3990 if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
3992 // Precompute load address
3993 *value=constmap[i][hr]+imm[i+1];
3994 //printf("c=%x imm=%lx\n",(long)constmap[i][hr],imm[i+1]);
3999 *value=constmap[i][hr];
4000 //printf("c=%lx\n",(long)constmap[i][hr]);
4001 if(i==slen-1) return 1;
4003 return !((unneeded_reg[i+1]>>reg)&1);
4006 // Load registers with known constants
4007 static void load_consts(signed char pre[],signed char regmap[],int i)
4010 // propagate loaded constant flags
4012 regs[i].loadedconst=0;
4014 for(hr=0;hr<HOST_REGS;hr++) {
4015 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((regs[i-1].isconst>>hr)&1)&&pre[hr]==regmap[hr]
4016 &®map[hr]==regs[i-1].regmap[hr]&&((regs[i-1].loadedconst>>hr)&1))
4018 regs[i].loadedconst|=1<<hr;
4023 for(hr=0;hr<HOST_REGS;hr++) {
4024 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4025 //if(entry[hr]!=regmap[hr]) {
4026 if(!((regs[i].loadedconst>>hr)&1)) {
4027 assert(regmap[hr]<64);
4028 if(((regs[i].isconst>>hr)&1)&®map[hr]>0) {
4029 int value,similar=0;
4030 if(get_final_value(hr,i,&value)) {
4031 // see if some other register has similar value
4032 for(hr2=0;hr2<HOST_REGS;hr2++) {
4033 if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
4034 if(is_similar_value(value,constmap[i][hr2])) {
4042 if(get_final_value(hr2,i,&value2)) // is this needed?
4043 emit_movimm_from(value2,hr2,value,hr);
4045 emit_movimm(value,hr);
4051 emit_movimm(value,hr);
4054 regs[i].loadedconst|=1<<hr;
4061 void load_all_consts(signed char regmap[], u_int dirty, int i)
4065 for(hr=0;hr<HOST_REGS;hr++) {
4066 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4067 assert(regmap[hr] < 64);
4068 if(((regs[i].isconst>>hr)&1)&®map[hr]>0) {
4069 int value=constmap[i][hr];
4074 emit_movimm(value,hr);
4081 // Write out all dirty registers (except cycle count)
4082 static void wb_dirtys(signed char i_regmap[],uint64_t i_dirty)
4085 for(hr=0;hr<HOST_REGS;hr++) {
4086 if(hr!=EXCLUDE_REG) {
4087 if(i_regmap[hr]>0) {
4088 if(i_regmap[hr]!=CCREG) {
4089 if((i_dirty>>hr)&1) {
4090 assert(i_regmap[hr]<64);
4091 emit_storereg(i_regmap[hr],hr);
4099 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4100 // This writes the registers not written by store_regs_bt
4101 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_dirty,int addr)
4104 int t=(addr-start)>>2;
4105 for(hr=0;hr<HOST_REGS;hr++) {
4106 if(hr!=EXCLUDE_REG) {
4107 if(i_regmap[hr]>0) {
4108 if(i_regmap[hr]!=CCREG) {
4109 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1)) {
4110 if((i_dirty>>hr)&1) {
4111 assert(i_regmap[hr]<64);
4112 emit_storereg(i_regmap[hr],hr);
4121 // Load all registers (except cycle count)
4122 void load_all_regs(signed char i_regmap[])
4125 for(hr=0;hr<HOST_REGS;hr++) {
4126 if(hr!=EXCLUDE_REG) {
4127 if(i_regmap[hr]==0) {
4131 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4133 emit_loadreg(i_regmap[hr],hr);
4139 // Load all current registers also needed by next instruction
4140 void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4143 for(hr=0;hr<HOST_REGS;hr++) {
4144 if(hr!=EXCLUDE_REG) {
4145 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4146 if(i_regmap[hr]==0) {
4150 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4152 emit_loadreg(i_regmap[hr],hr);
4159 // Load all regs, storing cycle count if necessary
4160 void load_regs_entry(int t)
4163 if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
4164 else if(ccadj[t]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST(ccadj[t]),HOST_CCREG);
4165 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4166 emit_storereg(CCREG,HOST_CCREG);
4169 for(hr=0;hr<HOST_REGS;hr++) {
4170 if(regs[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4171 if(regs[t].regmap_entry[hr]==0) {
4174 else if(regs[t].regmap_entry[hr]!=CCREG)
4176 emit_loadreg(regs[t].regmap_entry[hr],hr);
4182 // Store dirty registers prior to branch
4183 void store_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
4185 if(internal_branch(addr))
4187 int t=(addr-start)>>2;
4189 for(hr=0;hr<HOST_REGS;hr++) {
4190 if(hr!=EXCLUDE_REG) {
4191 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4192 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1)) {
4193 if((i_dirty>>hr)&1) {
4194 assert(i_regmap[hr]<64);
4195 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4196 emit_storereg(i_regmap[hr],hr);
4205 // Branch out of this block, write out all dirty regs
4206 wb_dirtys(i_regmap,i_dirty);
4210 // Load all needed registers for branch target
4211 static void load_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
4213 //if(addr>=start && addr<(start+slen*4))
4214 if(internal_branch(addr))
4216 int t=(addr-start)>>2;
4218 // Store the cycle count before loading something else
4219 if(i_regmap[HOST_CCREG]!=CCREG) {
4220 assert(i_regmap[HOST_CCREG]==-1);
4222 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4223 emit_storereg(CCREG,HOST_CCREG);
4226 for(hr=0;hr<HOST_REGS;hr++) {
4227 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4228 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4229 if(regs[t].regmap_entry[hr]==0) {
4232 else if(regs[t].regmap_entry[hr]!=CCREG)
4234 emit_loadreg(regs[t].regmap_entry[hr],hr);
4242 static int match_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
4244 if(addr>=start && addr<start+slen*4-4)
4246 int t=(addr-start)>>2;
4248 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4249 for(hr=0;hr<HOST_REGS;hr++)
4253 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4255 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
4262 if(i_regmap[hr]<TEMPREG)
4264 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4267 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
4273 else // Same register but is it 32-bit or dirty?
4276 if(!((regs[t].dirty>>hr)&1))
4280 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4282 //printf("%x: dirty no match\n",addr);
4290 // Delay slots are not valid branch targets
4291 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP)) return 0;
4292 // Delay slots require additional processing, so do not match
4293 if(is_ds[t]) return 0;
4298 for(hr=0;hr<HOST_REGS;hr++)
4304 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4319 static void drc_dbg_emit_do_cmp(int i)
4321 extern void do_insn_cmp();
4325 for(hr=0;hr<HOST_REGS;hr++)
4326 if(regs[i].regmap[hr]>=0) reglist|=1<<hr;
4328 emit_movimm(start+i*4,0);
4329 emit_writeword(0,&pcaddr);
4330 emit_far_call(do_insn_cmp);
4331 //emit_readword(&cycle,0);
4332 //emit_addimm(0,2,0);
4333 //emit_writeword(0,&cycle);
4335 restore_regs(reglist);
4338 #define drc_dbg_emit_do_cmp(x)
4341 // Used when a branch jumps into the delay slot of another branch
4342 static void ds_assemble_entry(int i)
4344 int t=(ba[i]-start)>>2;
4346 instr_addr[t] = out;
4347 assem_debug("Assemble delay slot at %x\n",ba[i]);
4348 assem_debug("<->\n");
4349 drc_dbg_emit_do_cmp(t);
4350 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&®s[t].regmap[HOST_CCREG]!=CCREG)
4351 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty);
4352 load_regs(regs[t].regmap_entry,regs[t].regmap,rs1[t],rs2[t]);
4353 address_generation(t,®s[t],regs[t].regmap_entry);
4354 if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
4355 load_regs(regs[t].regmap_entry,regs[t].regmap,INVCP,INVCP);
4359 alu_assemble(t,®s[t]);break;
4361 imm16_assemble(t,®s[t]);break;
4363 shift_assemble(t,®s[t]);break;
4365 shiftimm_assemble(t,®s[t]);break;
4367 load_assemble(t,®s[t]);break;
4369 loadlr_assemble(t,®s[t]);break;
4371 store_assemble(t,®s[t]);break;
4373 storelr_assemble(t,®s[t]);break;
4375 cop0_assemble(t,®s[t]);break;
4377 cop1_assemble(t,®s[t]);break;
4379 c1ls_assemble(t,®s[t]);break;
4381 cop2_assemble(t,®s[t]);break;
4383 c2ls_assemble(t,®s[t]);break;
4385 c2op_assemble(t,®s[t]);break;
4387 multdiv_assemble(t,®s[t]);break;
4389 mov_assemble(t,®s[t]);break;
4398 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
4400 store_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4);
4401 load_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4);
4402 if(internal_branch(ba[i]+4))
4403 assem_debug("branch: internal\n");
4405 assem_debug("branch: external\n");
4406 assert(internal_branch(ba[i]+4));
4407 add_to_linker(out,ba[i]+4,internal_branch(ba[i]+4));
4411 static void emit_extjump(void *addr, u_int target)
4413 emit_extjump2(addr, target, dyna_linker);
4416 static void emit_extjump_ds(void *addr, u_int target)
4418 emit_extjump2(addr, target, dyna_linker_ds);
4421 // Load 2 immediates optimizing for small code size
4422 static void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
4424 emit_movimm(imm1,rt1);
4425 emit_movimm_from(imm1,rt1,imm2,rt2);
4428 void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4438 //if(ba[i]>=start && ba[i]<(start+slen*4))
4439 if(internal_branch(ba[i]))
4442 if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4450 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4452 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4454 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4455 emit_andimm(HOST_CCREG,3,HOST_CCREG);
4459 else if(*adj==0||invert) {
4460 int cycles=CLOCK_ADJUST(count+2);
4464 if(-NO_CYCLE_PENALTY_THR<rel&&rel<0)
4465 cycles=CLOCK_ADJUST(*adj)+count+2-*adj;
4467 emit_addimm_and_set_flags(cycles,HOST_CCREG);
4473 emit_cmpimm(HOST_CCREG,-CLOCK_ADJUST(count+2));
4477 add_stub(CC_STUB,jaddr,idle?idle:out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4480 static void do_ccstub(int n)
4483 assem_debug("do_ccstub %x\n",start+(u_int)stubs[n].b*4);
4484 set_jump_target(stubs[n].addr, out);
4486 if(stubs[n].d==NULLDS) {
4487 // Delay slot instruction is nullified ("likely" branch)
4488 wb_dirtys(regs[i].regmap,regs[i].dirty);
4490 else if(stubs[n].d!=TAKEN) {
4491 wb_dirtys(branch_regs[i].regmap,branch_regs[i].dirty);
4494 if(internal_branch(ba[i]))
4495 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
4499 // Save PC as return address
4500 emit_movimm(stubs[n].c,EAX);
4501 emit_writeword(EAX,&pcaddr);
4505 // Return address depends on which way the branch goes
4506 if(itype[i]==CJUMP||itype[i]==SJUMP)
4508 int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4509 int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4520 #ifdef DESTRUCTIVE_WRITEBACK
4522 if((branch_regs[i].dirty>>s1l)&&1)
4523 emit_loadreg(rs1[i],s1l);
4526 if((branch_regs[i].dirty>>s1l)&1)
4527 emit_loadreg(rs2[i],s1l);
4530 if((branch_regs[i].dirty>>s2l)&1)
4531 emit_loadreg(rs2[i],s2l);
4534 int addr=-1,alt=-1,ntaddr=-1;
4537 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4538 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4539 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4547 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4548 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4549 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4555 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
4559 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4560 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4561 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4567 assert(hr<HOST_REGS);
4569 if((opcode[i]&0x2f)==4) // BEQ
4571 #ifdef HAVE_CMOV_IMM
4572 if(s2l>=0) emit_cmp(s1l,s2l);
4573 else emit_test(s1l,s1l);
4574 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
4576 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4577 if(s2l>=0) emit_cmp(s1l,s2l);
4578 else emit_test(s1l,s1l);
4579 emit_cmovne_reg(alt,addr);
4582 if((opcode[i]&0x2f)==5) // BNE
4584 #ifdef HAVE_CMOV_IMM
4585 if(s2l>=0) emit_cmp(s1l,s2l);
4586 else emit_test(s1l,s1l);
4587 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
4589 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
4590 if(s2l>=0) emit_cmp(s1l,s2l);
4591 else emit_test(s1l,s1l);
4592 emit_cmovne_reg(alt,addr);
4595 if((opcode[i]&0x2f)==6) // BLEZ
4597 //emit_movimm(ba[i],alt);
4598 //emit_movimm(start+i*4+8,addr);
4599 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4601 emit_cmovl_reg(alt,addr);
4603 if((opcode[i]&0x2f)==7) // BGTZ
4605 //emit_movimm(ba[i],addr);
4606 //emit_movimm(start+i*4+8,ntaddr);
4607 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
4609 emit_cmovl_reg(ntaddr,addr);
4611 if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
4613 //emit_movimm(ba[i],alt);
4614 //emit_movimm(start+i*4+8,addr);
4615 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4617 emit_cmovs_reg(alt,addr);
4619 if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
4621 //emit_movimm(ba[i],addr);
4622 //emit_movimm(start+i*4+8,alt);
4623 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4625 emit_cmovs_reg(alt,addr);
4627 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
4628 if(source[i]&0x10000) // BC1T
4630 //emit_movimm(ba[i],alt);
4631 //emit_movimm(start+i*4+8,addr);
4632 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4633 emit_testimm(s1l,0x800000);
4634 emit_cmovne_reg(alt,addr);
4638 //emit_movimm(ba[i],addr);
4639 //emit_movimm(start+i*4+8,alt);
4640 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4641 emit_testimm(s1l,0x800000);
4642 emit_cmovne_reg(alt,addr);
4645 emit_writeword(addr,&pcaddr);
4650 int r=get_reg(branch_regs[i].regmap,rs1[i]);
4651 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
4652 r=get_reg(branch_regs[i].regmap,RTEMP);
4654 emit_writeword(r,&pcaddr);
4656 else {SysPrintf("Unknown branch type in do_ccstub\n");abort();}
4658 // Update cycle count
4659 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
4660 if(stubs[n].a) emit_addimm(HOST_CCREG,CLOCK_ADJUST((signed int)stubs[n].a),HOST_CCREG);
4661 emit_far_call(cc_interrupt);
4662 if(stubs[n].a) emit_addimm(HOST_CCREG,-CLOCK_ADJUST((signed int)stubs[n].a),HOST_CCREG);
4663 if(stubs[n].d==TAKEN) {
4664 if(internal_branch(ba[i]))
4665 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
4666 else if(itype[i]==RJUMP) {
4667 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
4668 emit_readword(&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
4670 emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
4672 }else if(stubs[n].d==NOTTAKEN) {
4673 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
4674 else load_all_regs(branch_regs[i].regmap);
4675 }else if(stubs[n].d==NULLDS) {
4676 // Delay slot instruction is nullified ("likely" branch)
4677 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
4678 else load_all_regs(regs[i].regmap);
4680 load_all_regs(branch_regs[i].regmap);
4682 if (stubs[n].retaddr)
4683 emit_jmp(stubs[n].retaddr);
4685 do_jump_vaddr(stubs[n].e);
4688 static void add_to_linker(void *addr, u_int target, int ext)
4690 assert(linkcount < ARRAY_SIZE(link_addr));
4691 link_addr[linkcount].addr = addr;
4692 link_addr[linkcount].target = target;
4693 link_addr[linkcount].ext = ext;
4697 static void ujump_assemble_write_ra(int i)
4700 unsigned int return_address;
4701 rt=get_reg(branch_regs[i].regmap,31);
4702 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
4704 return_address=start+i*4+8;
4707 if(internal_branch(return_address)&&rt1[i+1]!=31) {
4708 int temp=-1; // note: must be ds-safe
4712 if(temp>=0) do_miniht_insert(return_address,rt,temp);
4713 else emit_movimm(return_address,rt);
4721 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
4724 emit_movimm(return_address,rt); // PC into link register
4726 emit_prefetch(hash_table_get(return_address));
4732 static void ujump_assemble(int i,struct regstat *i_regs)
4735 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
4736 address_generation(i+1,i_regs,regs[i].regmap_entry);
4738 int temp=get_reg(branch_regs[i].regmap,PTEMP);
4739 if(rt1[i]==31&&temp>=0)
4741 signed char *i_regmap=i_regs->regmap;
4742 int return_address=start+i*4+8;
4743 if(get_reg(branch_regs[i].regmap,31)>0)
4744 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
4747 if(rt1[i]==31&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
4748 ujump_assemble_write_ra(i); // writeback ra for DS
4751 ds_assemble(i+1,i_regs);
4752 uint64_t bc_unneeded=branch_regs[i].u;
4753 bc_unneeded|=1|(1LL<<rt1[i]);
4754 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
4755 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
4756 if(!ra_done&&rt1[i]==31)
4757 ujump_assemble_write_ra(i);
4759 cc=get_reg(branch_regs[i].regmap,CCREG);
4760 assert(cc==HOST_CCREG);
4761 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
4763 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
4765 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
4766 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
4767 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
4768 if(internal_branch(ba[i]))
4769 assem_debug("branch: internal\n");
4771 assem_debug("branch: external\n");
4772 if(internal_branch(ba[i])&&is_ds[(ba[i]-start)>>2]) {
4773 ds_assemble_entry(i);
4776 add_to_linker(out,ba[i],internal_branch(ba[i]));
4781 static void rjump_assemble_write_ra(int i)
4783 int rt,return_address;
4784 assert(rt1[i+1]!=rt1[i]);
4785 assert(rt2[i+1]!=rt1[i]);
4786 rt=get_reg(branch_regs[i].regmap,rt1[i]);
4787 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
4789 return_address=start+i*4+8;
4793 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
4796 emit_movimm(return_address,rt); // PC into link register
4798 emit_prefetch(hash_table_get(return_address));
4802 static void rjump_assemble(int i,struct regstat *i_regs)
4807 rs=get_reg(branch_regs[i].regmap,rs1[i]);
4809 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
4810 // Delay slot abuse, make a copy of the branch address register
4811 temp=get_reg(branch_regs[i].regmap,RTEMP);
4813 assert(regs[i].regmap[temp]==RTEMP);
4817 address_generation(i+1,i_regs,regs[i].regmap_entry);
4821 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
4822 signed char *i_regmap=i_regs->regmap;
4823 int return_address=start+i*4+8;
4824 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
4830 int rh=get_reg(regs[i].regmap,RHASH);
4831 if(rh>=0) do_preload_rhash(rh);
4834 if(rt1[i]!=0&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
4835 rjump_assemble_write_ra(i);
4838 ds_assemble(i+1,i_regs);
4839 uint64_t bc_unneeded=branch_regs[i].u;
4840 bc_unneeded|=1|(1LL<<rt1[i]);
4841 bc_unneeded&=~(1LL<<rs1[i]);
4842 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
4843 load_regs(regs[i].regmap,branch_regs[i].regmap,rs1[i],CCREG);
4844 if(!ra_done&&rt1[i]!=0)
4845 rjump_assemble_write_ra(i);
4846 cc=get_reg(branch_regs[i].regmap,CCREG);
4847 assert(cc==HOST_CCREG);
4850 int rh=get_reg(branch_regs[i].regmap,RHASH);
4851 int ht=get_reg(branch_regs[i].regmap,RHTBL);
4853 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
4854 do_preload_rhtbl(ht);
4858 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
4859 #ifdef DESTRUCTIVE_WRITEBACK
4860 if((branch_regs[i].dirty>>rs)&1) {
4861 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
4862 emit_loadreg(rs1[i],rs);
4867 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
4871 do_miniht_load(ht,rh);
4874 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
4875 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
4877 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
4878 add_stub(CC_STUB,out,NULL,0,i,-1,TAKEN,rs);
4879 if(itype[i+1]==COP0&&(source[i+1]&0x3f)==0x10)
4880 // special case for RFE
4884 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
4887 do_miniht_jump(rs,rh,ht);
4894 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
4895 if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
4899 static void cjump_assemble(int i,struct regstat *i_regs)
4901 signed char *i_regmap=i_regs->regmap;
4904 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
4905 assem_debug("match=%d\n",match);
4907 int unconditional=0,nop=0;
4909 int internal=internal_branch(ba[i]);
4910 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
4911 if(!match) invert=1;
4912 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
4913 if(i>(ba[i]-start)>>2) invert=1;
4916 invert=1; // because of near cond. branches
4920 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4921 s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4924 s1l=get_reg(i_regmap,rs1[i]);
4925 s2l=get_reg(i_regmap,rs2[i]);
4927 if(rs1[i]==0&&rs2[i]==0)
4929 if(opcode[i]&1) nop=1;
4930 else unconditional=1;
4931 //assert(opcode[i]!=5);
4932 //assert(opcode[i]!=7);
4933 //assert(opcode[i]!=0x15);
4934 //assert(opcode[i]!=0x17);
4947 // Out of order execution (delay slot first)
4949 address_generation(i+1,i_regs,regs[i].regmap_entry);
4950 ds_assemble(i+1,i_regs);
4952 uint64_t bc_unneeded=branch_regs[i].u;
4953 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
4955 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
4956 load_regs(regs[i].regmap,branch_regs[i].regmap,rs1[i],rs2[i]);
4957 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
4958 cc=get_reg(branch_regs[i].regmap,CCREG);
4959 assert(cc==HOST_CCREG);
4961 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
4962 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
4963 //assem_debug("cycle count (adj)\n");
4965 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
4966 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
4967 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
4968 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
4970 assem_debug("branch: internal\n");
4972 assem_debug("branch: external\n");
4973 if(internal&&is_ds[(ba[i]-start)>>2]) {
4974 ds_assemble_entry(i);
4977 add_to_linker(out,ba[i],internal);
4980 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
4981 if(((u_int)out)&7) emit_addnop(0);
4986 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
4989 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
4992 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
4993 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
4994 if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
4996 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
4998 if(opcode[i]==4) // BEQ
5000 if(s2l>=0) emit_cmp(s1l,s2l);
5001 else emit_test(s1l,s1l);
5006 add_to_linker(out,ba[i],internal);
5010 if(opcode[i]==5) // BNE
5012 if(s2l>=0) emit_cmp(s1l,s2l);
5013 else emit_test(s1l,s1l);
5018 add_to_linker(out,ba[i],internal);
5022 if(opcode[i]==6) // BLEZ
5029 add_to_linker(out,ba[i],internal);
5033 if(opcode[i]==7) // BGTZ
5040 add_to_linker(out,ba[i],internal);
5045 if(taken) set_jump_target(taken, out);
5046 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5047 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5049 emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5050 add_to_linker(out,ba[i],internal);
5053 add_to_linker(out,ba[i],internal*2);
5059 if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5060 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5061 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5063 assem_debug("branch: internal\n");
5065 assem_debug("branch: external\n");
5066 if(internal&&is_ds[(ba[i]-start)>>2]) {
5067 ds_assemble_entry(i);
5070 add_to_linker(out,ba[i],internal);
5074 set_jump_target(nottaken, out);
5077 if(nottaken1) set_jump_target(nottaken1, out);
5079 if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
5081 } // (!unconditional)
5085 // In-order execution (branch first)
5086 //if(likely[i]) printf("IOL\n");
5089 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
5090 if(!unconditional&&!nop) {
5091 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5093 if((opcode[i]&0x2f)==4) // BEQ
5095 if(s2l>=0) emit_cmp(s1l,s2l);
5096 else emit_test(s1l,s1l);
5100 if((opcode[i]&0x2f)==5) // BNE
5102 if(s2l>=0) emit_cmp(s1l,s2l);
5103 else emit_test(s1l,s1l);
5107 if((opcode[i]&0x2f)==6) // BLEZ
5113 if((opcode[i]&0x2f)==7) // BGTZ
5119 } // if(!unconditional)
5121 uint64_t ds_unneeded=branch_regs[i].u;
5122 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5126 if(taken) set_jump_target(taken, out);
5127 assem_debug("1:\n");
5128 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5130 load_regs(regs[i].regmap,branch_regs[i].regmap,rs1[i+1],rs2[i+1]);
5131 address_generation(i+1,&branch_regs[i],0);
5132 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
5133 ds_assemble(i+1,&branch_regs[i]);
5134 cc=get_reg(branch_regs[i].regmap,CCREG);
5136 emit_loadreg(CCREG,cc=HOST_CCREG);
5137 // CHECK: Is the following instruction (fall thru) allocated ok?
5139 assert(cc==HOST_CCREG);
5140 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5141 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5142 assem_debug("cycle count (adj)\n");
5143 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5144 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5146 assem_debug("branch: internal\n");
5148 assem_debug("branch: external\n");
5149 if(internal&&is_ds[(ba[i]-start)>>2]) {
5150 ds_assemble_entry(i);
5153 add_to_linker(out,ba[i],internal);
5158 if(!unconditional) {
5159 if(nottaken1) set_jump_target(nottaken1, out);
5160 set_jump_target(nottaken, out);
5161 assem_debug("2:\n");
5163 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5164 load_regs(regs[i].regmap,branch_regs[i].regmap,rs1[i+1],rs2[i+1]);
5165 address_generation(i+1,&branch_regs[i],0);
5166 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
5167 ds_assemble(i+1,&branch_regs[i]);
5169 cc=get_reg(branch_regs[i].regmap,CCREG);
5170 if(cc==-1&&!likely[i]) {
5171 // Cycle count isn't in a register, temporarily load it then write it out
5172 emit_loadreg(CCREG,HOST_CCREG);
5173 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5176 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5177 emit_storereg(CCREG,HOST_CCREG);
5180 cc=get_reg(i_regmap,CCREG);
5181 assert(cc==HOST_CCREG);
5182 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5185 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5191 static void sjump_assemble(int i,struct regstat *i_regs)
5193 signed char *i_regmap=i_regs->regmap;
5196 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5197 assem_debug("smatch=%d\n",match);
5199 int unconditional=0,nevertaken=0;
5201 int internal=internal_branch(ba[i]);
5202 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5203 if(!match) invert=1;
5204 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5205 if(i>(ba[i]-start)>>2) invert=1;
5208 invert=1; // because of near cond. branches
5211 //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
5212 //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
5215 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5218 s1l=get_reg(i_regmap,rs1[i]);
5222 if(opcode2[i]&1) unconditional=1;
5224 // These are never taken (r0 is never less than zero)
5225 //assert(opcode2[i]!=0);
5226 //assert(opcode2[i]!=2);
5227 //assert(opcode2[i]!=0x10);
5228 //assert(opcode2[i]!=0x12);
5232 // Out of order execution (delay slot first)
5234 address_generation(i+1,i_regs,regs[i].regmap_entry);
5235 ds_assemble(i+1,i_regs);
5237 uint64_t bc_unneeded=branch_regs[i].u;
5238 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5240 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5241 load_regs(regs[i].regmap,branch_regs[i].regmap,rs1[i],rs1[i]);
5242 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
5244 int rt,return_address;
5245 rt=get_reg(branch_regs[i].regmap,31);
5246 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5248 // Save the PC even if the branch is not taken
5249 return_address=start+i*4+8;
5250 emit_movimm(return_address,rt); // PC into link register
5252 if(!nevertaken) emit_prefetch(hash_table_get(return_address));
5256 cc=get_reg(branch_regs[i].regmap,CCREG);
5257 assert(cc==HOST_CCREG);
5259 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5260 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5261 assem_debug("cycle count (adj)\n");
5263 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5264 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5265 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5266 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5268 assem_debug("branch: internal\n");
5270 assem_debug("branch: external\n");
5271 if(internal&&is_ds[(ba[i]-start)>>2]) {
5272 ds_assemble_entry(i);
5275 add_to_linker(out,ba[i],internal);
5278 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5279 if(((u_int)out)&7) emit_addnop(0);
5283 else if(nevertaken) {
5284 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5287 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5290 void *nottaken = NULL;
5291 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5292 if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5295 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5302 add_to_linker(out,ba[i],internal);
5306 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5313 add_to_linker(out,ba[i],internal);
5320 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5321 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5323 emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5324 add_to_linker(out,ba[i],internal);
5327 add_to_linker(out,ba[i],internal*2);
5333 if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5334 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5335 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5337 assem_debug("branch: internal\n");
5339 assem_debug("branch: external\n");
5340 if(internal&&is_ds[(ba[i]-start)>>2]) {
5341 ds_assemble_entry(i);
5344 add_to_linker(out,ba[i],internal);
5348 set_jump_target(nottaken, out);
5352 if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
5354 } // (!unconditional)
5358 // In-order execution (branch first)
5360 void *nottaken = NULL;
5362 int rt,return_address;
5363 rt=get_reg(branch_regs[i].regmap,31);
5365 // Save the PC even if the branch is not taken
5366 return_address=start+i*4+8;
5367 emit_movimm(return_address,rt); // PC into link register
5369 emit_prefetch(hash_table_get(return_address));
5373 if(!unconditional) {
5374 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5376 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
5382 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
5388 } // if(!unconditional)
5390 uint64_t ds_unneeded=branch_regs[i].u;
5391 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5395 //assem_debug("1:\n");
5396 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5398 load_regs(regs[i].regmap,branch_regs[i].regmap,rs1[i+1],rs2[i+1]);
5399 address_generation(i+1,&branch_regs[i],0);
5400 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
5401 ds_assemble(i+1,&branch_regs[i]);
5402 cc=get_reg(branch_regs[i].regmap,CCREG);
5404 emit_loadreg(CCREG,cc=HOST_CCREG);
5405 // CHECK: Is the following instruction (fall thru) allocated ok?
5407 assert(cc==HOST_CCREG);
5408 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5409 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5410 assem_debug("cycle count (adj)\n");
5411 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5412 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5414 assem_debug("branch: internal\n");
5416 assem_debug("branch: external\n");
5417 if(internal&&is_ds[(ba[i]-start)>>2]) {
5418 ds_assemble_entry(i);
5421 add_to_linker(out,ba[i],internal);
5426 if(!unconditional) {
5427 set_jump_target(nottaken, out);
5428 assem_debug("1:\n");
5430 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5431 load_regs(regs[i].regmap,branch_regs[i].regmap,rs1[i+1],rs2[i+1]);
5432 address_generation(i+1,&branch_regs[i],0);
5433 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
5434 ds_assemble(i+1,&branch_regs[i]);
5436 cc=get_reg(branch_regs[i].regmap,CCREG);
5437 if(cc==-1&&!likely[i]) {
5438 // Cycle count isn't in a register, temporarily load it then write it out
5439 emit_loadreg(CCREG,HOST_CCREG);
5440 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5443 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5444 emit_storereg(CCREG,HOST_CCREG);
5447 cc=get_reg(i_regmap,CCREG);
5448 assert(cc==HOST_CCREG);
5449 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5452 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5458 static void pagespan_assemble(int i,struct regstat *i_regs)
5460 int s1l=get_reg(i_regs->regmap,rs1[i]);
5461 int s2l=get_reg(i_regs->regmap,rs2[i]);
5463 void *nottaken = NULL;
5464 int unconditional=0;
5475 int addr=-1,alt=-1,ntaddr=-1;
5476 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
5480 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5481 (i_regs->regmap[hr]&63)!=rs1[i] &&
5482 (i_regs->regmap[hr]&63)!=rs2[i] )
5491 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
5492 (i_regs->regmap[hr]&63)!=rs1[i] &&
5493 (i_regs->regmap[hr]&63)!=rs2[i] )
5499 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
5503 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
5504 (i_regs->regmap[hr]&63)!=rs1[i] &&
5505 (i_regs->regmap[hr]&63)!=rs2[i] )
5512 assert(hr<HOST_REGS);
5513 if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
5514 load_regs(regs[i].regmap_entry,regs[i].regmap,CCREG,CCREG);
5516 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5517 if(opcode[i]==2) // J
5521 if(opcode[i]==3) // JAL
5524 int rt=get_reg(i_regs->regmap,31);
5525 emit_movimm(start+i*4+8,rt);
5528 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
5531 if(opcode2[i]==9) // JALR
5533 int rt=get_reg(i_regs->regmap,rt1[i]);
5534 emit_movimm(start+i*4+8,rt);
5537 if((opcode[i]&0x3f)==4) // BEQ
5544 #ifdef HAVE_CMOV_IMM
5546 if(s2l>=0) emit_cmp(s1l,s2l);
5547 else emit_test(s1l,s1l);
5548 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5554 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5555 if(s2l>=0) emit_cmp(s1l,s2l);
5556 else emit_test(s1l,s1l);
5557 emit_cmovne_reg(alt,addr);
5560 if((opcode[i]&0x3f)==5) // BNE
5562 #ifdef HAVE_CMOV_IMM
5563 if(s2l>=0) emit_cmp(s1l,s2l);
5564 else emit_test(s1l,s1l);
5565 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5568 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5569 if(s2l>=0) emit_cmp(s1l,s2l);
5570 else emit_test(s1l,s1l);
5571 emit_cmovne_reg(alt,addr);
5574 if((opcode[i]&0x3f)==0x14) // BEQL
5576 if(s2l>=0) emit_cmp(s1l,s2l);
5577 else emit_test(s1l,s1l);
5578 if(nottaken) set_jump_target(nottaken, out);
5582 if((opcode[i]&0x3f)==0x15) // BNEL
5584 if(s2l>=0) emit_cmp(s1l,s2l);
5585 else emit_test(s1l,s1l);
5588 if(taken) set_jump_target(taken, out);
5590 if((opcode[i]&0x3f)==6) // BLEZ
5592 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5594 emit_cmovl_reg(alt,addr);
5596 if((opcode[i]&0x3f)==7) // BGTZ
5598 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5600 emit_cmovl_reg(ntaddr,addr);
5602 if((opcode[i]&0x3f)==0x16) // BLEZL
5604 assert((opcode[i]&0x3f)!=0x16);
5606 if((opcode[i]&0x3f)==0x17) // BGTZL
5608 assert((opcode[i]&0x3f)!=0x17);
5610 assert(opcode[i]!=1); // BLTZ/BGEZ
5612 //FIXME: Check CSREG
5613 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
5614 if((source[i]&0x30000)==0) // BC1F
5616 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5617 emit_testimm(s1l,0x800000);
5618 emit_cmovne_reg(alt,addr);
5620 if((source[i]&0x30000)==0x10000) // BC1T
5622 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5623 emit_testimm(s1l,0x800000);
5624 emit_cmovne_reg(alt,addr);
5626 if((source[i]&0x30000)==0x20000) // BC1FL
5628 emit_testimm(s1l,0x800000);
5632 if((source[i]&0x30000)==0x30000) // BC1TL
5634 emit_testimm(s1l,0x800000);
5640 assert(i_regs->regmap[HOST_CCREG]==CCREG);
5641 wb_dirtys(regs[i].regmap,regs[i].dirty);
5642 if(likely[i]||unconditional)
5644 emit_movimm(ba[i],HOST_BTREG);
5646 else if(addr!=HOST_BTREG)
5648 emit_mov(addr,HOST_BTREG);
5650 void *branch_addr=out;
5652 int target_addr=start+i*4+5;
5654 void *compiled_target_addr=check_addr(target_addr);
5655 emit_extjump_ds(branch_addr, target_addr);
5656 if(compiled_target_addr) {
5657 set_jump_target(branch_addr, compiled_target_addr);
5658 add_link(target_addr,stub);
5660 else set_jump_target(branch_addr, stub);
5663 set_jump_target(nottaken, out);
5664 wb_dirtys(regs[i].regmap,regs[i].dirty);
5665 void *branch_addr=out;
5667 int target_addr=start+i*4+8;
5669 void *compiled_target_addr=check_addr(target_addr);
5670 emit_extjump_ds(branch_addr, target_addr);
5671 if(compiled_target_addr) {
5672 set_jump_target(branch_addr, compiled_target_addr);
5673 add_link(target_addr,stub);
5675 else set_jump_target(branch_addr, stub);
5679 // Assemble the delay slot for the above
5680 static void pagespan_ds()
5682 assem_debug("initial delay slot:\n");
5683 u_int vaddr=start+1;
5684 u_int page=get_page(vaddr);
5685 u_int vpage=get_vpage(vaddr);
5686 ll_add(jump_dirty+vpage,vaddr,(void *)out);
5688 ll_add(jump_in+page,vaddr,(void *)out);
5689 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
5690 if(regs[0].regmap[HOST_CCREG]!=CCREG)
5691 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty);
5692 if(regs[0].regmap[HOST_BTREG]!=BTREG)
5693 emit_writeword(HOST_BTREG,&branch_target);
5694 load_regs(regs[0].regmap_entry,regs[0].regmap,rs1[0],rs2[0]);
5695 address_generation(0,®s[0],regs[0].regmap_entry);
5696 if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
5697 load_regs(regs[0].regmap_entry,regs[0].regmap,INVCP,INVCP);
5701 alu_assemble(0,®s[0]);break;
5703 imm16_assemble(0,®s[0]);break;
5705 shift_assemble(0,®s[0]);break;
5707 shiftimm_assemble(0,®s[0]);break;
5709 load_assemble(0,®s[0]);break;
5711 loadlr_assemble(0,®s[0]);break;
5713 store_assemble(0,®s[0]);break;
5715 storelr_assemble(0,®s[0]);break;
5717 cop0_assemble(0,®s[0]);break;
5719 cop1_assemble(0,®s[0]);break;
5721 c1ls_assemble(0,®s[0]);break;
5723 cop2_assemble(0,®s[0]);break;
5725 c2ls_assemble(0,®s[0]);break;
5727 c2op_assemble(0,®s[0]);break;
5729 multdiv_assemble(0,®s[0]);break;
5731 mov_assemble(0,®s[0]);break;
5740 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
5742 int btaddr=get_reg(regs[0].regmap,BTREG);
5744 btaddr=get_reg(regs[0].regmap,-1);
5745 emit_readword(&branch_target,btaddr);
5747 assert(btaddr!=HOST_CCREG);
5748 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
5750 host_tempreg_acquire();
5751 emit_movimm(start+4,HOST_TEMPREG);
5752 emit_cmp(btaddr,HOST_TEMPREG);
5753 host_tempreg_release();
5755 emit_cmpimm(btaddr,start+4);
5759 store_regs_bt(regs[0].regmap,regs[0].dirty,-1);
5760 do_jump_vaddr(btaddr);
5761 set_jump_target(branch, out);
5762 store_regs_bt(regs[0].regmap,regs[0].dirty,start+4);
5763 load_regs_bt(regs[0].regmap,regs[0].dirty,start+4);
5766 // Basic liveness analysis for MIPS registers
5767 void unneeded_registers(int istart,int iend,int r)
5770 uint64_t u,gte_u,b,gte_b;
5771 uint64_t temp_u,temp_gte_u=0;
5772 uint64_t gte_u_unknown=0;
5773 if(new_dynarec_hacks&NDHACK_GTE_UNNEEDED)
5777 gte_u=gte_u_unknown;
5779 //u=unneeded_reg[iend+1];
5781 gte_u=gte_unneeded[iend+1];
5784 for (i=iend;i>=istart;i--)
5786 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
5787 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP)
5789 // If subroutine call, flag return address as a possible branch target
5790 if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
5792 if(ba[i]<start || ba[i]>=(start+slen*4))
5794 // Branch out of this block, flush all regs
5796 gte_u=gte_u_unknown;
5797 branch_unneeded_reg[i]=u;
5798 // Merge in delay slot
5799 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
5800 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5803 gte_u&=~gte_rs[i+1];
5804 // If branch is "likely" (and conditional)
5805 // then we skip the delay slot on the fall-thru path
5808 u&=unneeded_reg[i+2];
5809 gte_u&=gte_unneeded[i+2];
5814 gte_u=gte_u_unknown;
5820 // Internal branch, flag target
5821 bt[(ba[i]-start)>>2]=1;
5822 if(ba[i]<=start+i*4) {
5824 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
5826 // Unconditional branch
5830 // Conditional branch (not taken case)
5831 temp_u=unneeded_reg[i+2];
5832 temp_gte_u&=gte_unneeded[i+2];
5834 // Merge in delay slot
5835 temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
5836 temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5838 temp_gte_u|=gte_rt[i+1];
5839 temp_gte_u&=~gte_rs[i+1];
5840 // If branch is "likely" (and conditional)
5841 // then we skip the delay slot on the fall-thru path
5844 temp_u&=unneeded_reg[i+2];
5845 temp_gte_u&=gte_unneeded[i+2];
5850 temp_gte_u=gte_u_unknown;
5853 temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
5854 temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5856 temp_gte_u|=gte_rt[i];
5857 temp_gte_u&=~gte_rs[i];
5858 unneeded_reg[i]=temp_u;
5859 gte_unneeded[i]=temp_gte_u;
5860 // Only go three levels deep. This recursion can take an
5861 // excessive amount of time if there are a lot of nested loops.
5863 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
5865 unneeded_reg[(ba[i]-start)>>2]=1;
5866 gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown;
5869 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
5871 // Unconditional branch
5872 u=unneeded_reg[(ba[i]-start)>>2];
5873 gte_u=gte_unneeded[(ba[i]-start)>>2];
5874 branch_unneeded_reg[i]=u;
5875 // Merge in delay slot
5876 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
5877 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5880 gte_u&=~gte_rs[i+1];
5882 // Conditional branch
5883 b=unneeded_reg[(ba[i]-start)>>2];
5884 gte_b=gte_unneeded[(ba[i]-start)>>2];
5885 branch_unneeded_reg[i]=b;
5886 // Branch delay slot
5887 b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
5888 b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5891 gte_b&=~gte_rs[i+1];
5892 // If branch is "likely" then we skip the
5893 // delay slot on the fall-thru path
5898 u&=unneeded_reg[i+2];
5899 gte_u&=gte_unneeded[i+2];
5906 branch_unneeded_reg[i]&=unneeded_reg[i+2];
5908 branch_unneeded_reg[i]=1;
5914 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
5916 // SYSCALL instruction (software interrupt)
5919 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
5921 // ERET instruction (return from interrupt)
5925 // Written registers are unneeded
5929 // Accessed registers are needed
5933 if(gte_rs[i]&&rt1[i]&&(unneeded_reg[i+1]&(1ll<<rt1[i])))
5934 gte_u|=gte_rs[i]>e_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded
5935 // Source-target dependencies
5936 // R0 is always unneeded
5940 gte_unneeded[i]=gte_u;
5942 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
5945 for(r=1;r<=CCREG;r++) {
5946 if((unneeded_reg[i]>>r)&1) {
5947 if(r==HIREG) printf(" HI");
5948 else if(r==LOREG) printf(" LO");
5949 else printf(" r%d",r);
5957 // Write back dirty registers as soon as we will no longer modify them,
5958 // so that we don't end up with lots of writes at the branches.
5959 void clean_registers(int istart,int iend,int wr)
5963 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
5964 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
5966 will_dirty_i=will_dirty_next=0;
5967 wont_dirty_i=wont_dirty_next=0;
5969 will_dirty_i=will_dirty_next=will_dirty[iend+1];
5970 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
5972 for (i=iend;i>=istart;i--)
5974 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP)
5976 if(ba[i]<start || ba[i]>=(start+slen*4))
5978 // Branch out of this block, flush all regs
5979 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
5981 // Unconditional branch
5984 // Merge in delay slot (will dirty)
5985 for(r=0;r<HOST_REGS;r++) {
5986 if(r!=EXCLUDE_REG) {
5987 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
5988 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
5989 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
5990 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
5991 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
5992 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
5993 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
5994 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
5995 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
5996 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
5997 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
5998 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
5999 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6000 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6006 // Conditional branch
6008 wont_dirty_i=wont_dirty_next;
6009 // Merge in delay slot (will dirty)
6010 for(r=0;r<HOST_REGS;r++) {
6011 if(r!=EXCLUDE_REG) {
6013 // Might not dirty if likely branch is not taken
6014 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6015 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6016 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
6017 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
6018 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6019 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
6020 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6021 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6022 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6023 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
6024 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
6025 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6026 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6027 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6032 // Merge in delay slot (wont dirty)
6033 for(r=0;r<HOST_REGS;r++) {
6034 if(r!=EXCLUDE_REG) {
6035 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
6036 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
6037 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
6038 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
6039 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6040 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
6041 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
6042 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
6043 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
6044 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6048 #ifndef DESTRUCTIVE_WRITEBACK
6049 branch_regs[i].dirty&=wont_dirty_i;
6051 branch_regs[i].dirty|=will_dirty_i;
6057 if(ba[i]<=start+i*4) {
6059 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6061 // Unconditional branch
6064 // Merge in delay slot (will dirty)
6065 for(r=0;r<HOST_REGS;r++) {
6066 if(r!=EXCLUDE_REG) {
6067 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
6068 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
6069 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
6070 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
6071 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6072 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6073 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6074 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
6075 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
6076 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
6077 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
6078 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6079 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6080 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6084 // Conditional branch (not taken case)
6085 temp_will_dirty=will_dirty_next;
6086 temp_wont_dirty=wont_dirty_next;
6087 // Merge in delay slot (will dirty)
6088 for(r=0;r<HOST_REGS;r++) {
6089 if(r!=EXCLUDE_REG) {
6091 // Will not dirty if likely branch is not taken
6092 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
6093 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
6094 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
6095 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
6096 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6097 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
6098 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6099 //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
6100 //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
6101 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
6102 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
6103 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6104 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6105 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6110 // Merge in delay slot (wont dirty)
6111 for(r=0;r<HOST_REGS;r++) {
6112 if(r!=EXCLUDE_REG) {
6113 if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
6114 if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
6115 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
6116 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
6117 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
6118 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
6119 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
6120 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
6121 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
6122 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
6125 // Deal with changed mappings
6127 for(r=0;r<HOST_REGS;r++) {
6128 if(r!=EXCLUDE_REG) {
6129 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
6130 temp_will_dirty&=~(1<<r);
6131 temp_wont_dirty&=~(1<<r);
6132 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
6133 temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6134 temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6136 temp_will_dirty|=1<<r;
6137 temp_wont_dirty|=1<<r;
6144 will_dirty[i]=temp_will_dirty;
6145 wont_dirty[i]=temp_wont_dirty;
6146 clean_registers((ba[i]-start)>>2,i-1,0);
6148 // Limit recursion. It can take an excessive amount
6149 // of time if there are a lot of nested loops.
6150 will_dirty[(ba[i]-start)>>2]=0;
6151 wont_dirty[(ba[i]-start)>>2]=-1;
6156 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6158 // Unconditional branch
6161 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
6162 for(r=0;r<HOST_REGS;r++) {
6163 if(r!=EXCLUDE_REG) {
6164 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
6165 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
6166 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
6168 if(branch_regs[i].regmap[r]>=0) {
6169 will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
6170 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
6175 // Merge in delay slot
6176 for(r=0;r<HOST_REGS;r++) {
6177 if(r!=EXCLUDE_REG) {
6178 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6179 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6180 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
6181 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
6182 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6183 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6184 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6185 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6186 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6187 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
6188 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
6189 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6190 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6191 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6195 // Conditional branch
6196 will_dirty_i=will_dirty_next;
6197 wont_dirty_i=wont_dirty_next;
6198 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
6199 for(r=0;r<HOST_REGS;r++) {
6200 if(r!=EXCLUDE_REG) {
6201 signed char target_reg=branch_regs[i].regmap[r];
6202 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
6203 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
6204 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
6206 else if(target_reg>=0) {
6207 will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
6208 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
6210 // Treat delay slot as part of branch too
6211 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
6212 will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
6213 wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
6217 will_dirty[i+1]&=~(1<<r);
6222 // Merge in delay slot
6223 for(r=0;r<HOST_REGS;r++) {
6224 if(r!=EXCLUDE_REG) {
6226 // Might not dirty if likely branch is not taken
6227 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6228 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6229 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
6230 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
6231 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6232 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6233 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6234 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6235 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6236 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
6237 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
6238 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6239 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6240 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6245 // Merge in delay slot (won't dirty)
6246 for(r=0;r<HOST_REGS;r++) {
6247 if(r!=EXCLUDE_REG) {
6248 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
6249 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
6250 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
6251 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
6252 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6253 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
6254 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
6255 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
6256 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
6257 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6261 #ifndef DESTRUCTIVE_WRITEBACK
6262 branch_regs[i].dirty&=wont_dirty_i;
6264 branch_regs[i].dirty|=will_dirty_i;
6269 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
6271 // SYSCALL instruction (software interrupt)
6275 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6277 // ERET instruction (return from interrupt)
6281 will_dirty_next=will_dirty_i;
6282 wont_dirty_next=wont_dirty_i;
6283 for(r=0;r<HOST_REGS;r++) {
6284 if(r!=EXCLUDE_REG) {
6285 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6286 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6287 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6288 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6289 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6290 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
6291 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
6292 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6294 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP)
6296 // Don't store a register immediately after writing it,
6297 // may prevent dual-issue.
6298 if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
6299 if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
6305 will_dirty[i]=will_dirty_i;
6306 wont_dirty[i]=wont_dirty_i;
6307 // Mark registers that won't be dirtied as not dirty
6309 /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
6310 for(r=0;r<HOST_REGS;r++) {
6311 if((will_dirty_i>>r)&1) {
6317 //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP)) {
6318 regs[i].dirty|=will_dirty_i;
6319 #ifndef DESTRUCTIVE_WRITEBACK
6320 regs[i].dirty&=wont_dirty_i;
6321 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP)
6323 if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
6324 for(r=0;r<HOST_REGS;r++) {
6325 if(r!=EXCLUDE_REG) {
6326 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
6327 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
6328 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
6336 for(r=0;r<HOST_REGS;r++) {
6337 if(r!=EXCLUDE_REG) {
6338 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
6339 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
6340 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
6348 // Deal with changed mappings
6349 temp_will_dirty=will_dirty_i;
6350 temp_wont_dirty=wont_dirty_i;
6351 for(r=0;r<HOST_REGS;r++) {
6352 if(r!=EXCLUDE_REG) {
6354 if(regs[i].regmap[r]==regmap_pre[i][r]) {
6356 #ifndef DESTRUCTIVE_WRITEBACK
6357 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
6359 regs[i].wasdirty|=will_dirty_i&(1<<r);
6362 else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
6363 // Register moved to a different register
6364 will_dirty_i&=~(1<<r);
6365 wont_dirty_i&=~(1<<r);
6366 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
6367 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
6369 #ifndef DESTRUCTIVE_WRITEBACK
6370 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
6372 regs[i].wasdirty|=will_dirty_i&(1<<r);
6376 will_dirty_i&=~(1<<r);
6377 wont_dirty_i&=~(1<<r);
6378 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
6379 will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6380 wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6383 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);assert(!((will_dirty>>r)&1));*/
6393 void disassemble_inst(int i)
6395 if (bt[i]) printf("*"); else printf(" ");
6398 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
6400 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
6402 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
6404 if (opcode[i]==0x9&&rt1[i]!=31)
6405 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
6407 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
6410 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
6412 if(opcode[i]==0xf) //LUI
6413 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
6415 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
6419 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
6423 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
6427 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
6430 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
6433 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
6436 if((opcode2[i]&0x1d)==0x10)
6437 printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
6438 else if((opcode2[i]&0x1d)==0x11)
6439 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
6441 printf (" %x: %s\n",start+i*4,insn[i]);
6445 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
6446 else if(opcode2[i]==4)
6447 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
6448 else printf (" %x: %s\n",start+i*4,insn[i]);
6452 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
6453 else if(opcode2[i]>3)
6454 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
6455 else printf (" %x: %s\n",start+i*4,insn[i]);
6459 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
6460 else if(opcode2[i]>3)
6461 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
6462 else printf (" %x: %s\n",start+i*4,insn[i]);
6465 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
6468 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
6471 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
6474 //printf (" %s %8x\n",insn[i],source[i]);
6475 printf (" %x: %s\n",start+i*4,insn[i]);
6479 static void disassemble_inst(int i) {}
6482 #define DRC_TEST_VAL 0x74657374
6484 static void new_dynarec_test(void)
6486 int (*testfunc)(void);
6491 // check structure linkage
6492 if ((u_char *)rcnts - (u_char *)&psxRegs != sizeof(psxRegs))
6494 SysPrintf("linkage_arm* miscompilation/breakage detected.\n");
6497 SysPrintf("testing if we can run recompiled code...\n");
6498 ((volatile u_int *)out)[0]++; // make cache dirty
6500 for (i = 0; i < ARRAY_SIZE(ret); i++) {
6501 out = ndrc->translation_cache;
6502 beginning = start_block();
6503 emit_movimm(DRC_TEST_VAL + i, 0); // test
6506 end_block(beginning);
6507 testfunc = beginning;
6508 ret[i] = testfunc();
6511 if (ret[0] == DRC_TEST_VAL && ret[1] == DRC_TEST_VAL + 1)
6512 SysPrintf("test passed.\n");
6514 SysPrintf("test failed, will likely crash soon (r=%08x %08x)\n", ret[0], ret[1]);
6515 out = ndrc->translation_cache;
6518 // clear the state completely, instead of just marking
6519 // things invalid like invalidate_all_pages() does
6520 void new_dynarec_clear_full(void)
6523 out = ndrc->translation_cache;
6524 memset(invalid_code,1,sizeof(invalid_code));
6525 memset(hash_table,0xff,sizeof(hash_table));
6526 memset(mini_ht,-1,sizeof(mini_ht));
6527 memset(restore_candidate,0,sizeof(restore_candidate));
6528 memset(shadow,0,sizeof(shadow));
6530 expirep=16384; // Expiry pointer, +2 blocks
6531 pending_exception=0;
6534 inv_code_start=inv_code_end=~0;
6536 for(n=0;n<4096;n++) ll_clear(jump_in+n);
6537 for(n=0;n<4096;n++) ll_clear(jump_out+n);
6538 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
6541 void new_dynarec_init(void)
6543 SysPrintf("Init new dynarec\n");
6545 #ifdef BASE_ADDR_DYNAMIC
6547 sceBlock = sceKernelAllocMemBlockForVM("code", 1 << TARGET_SIZE_2);
6549 SysPrintf("sceKernelAllocMemBlockForVM failed\n");
6550 int ret = sceKernelGetMemBlockBase(sceBlock, (void **)&ndrc);
6552 SysPrintf("sceKernelGetMemBlockBase failed\n");
6554 uintptr_t desired_addr = 0;
6557 desired_addr = ((uintptr_t)&_end + 0xffffff) & ~0xffffffl;
6559 ndrc = mmap((void *)desired_addr, sizeof(*ndrc),
6560 PROT_READ | PROT_WRITE | PROT_EXEC,
6561 MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
6562 if (ndrc == MAP_FAILED) {
6563 SysPrintf("mmap() failed: %s\n", strerror(errno));
6568 #ifndef NO_WRITE_EXEC
6569 // not all systems allow execute in data segment by default
6570 if (mprotect(ndrc, sizeof(ndrc->translation_cache) + sizeof(ndrc->tramp.ops),
6571 PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
6572 SysPrintf("mprotect() failed: %s\n", strerror(errno));
6575 out = ndrc->translation_cache;
6576 cycle_multiplier=200;
6577 new_dynarec_clear_full();
6579 // Copy this into local area so we don't have to put it in every literal pool
6580 invc_ptr=invalid_code;
6585 ram_offset=(uintptr_t)rdram-0x80000000;
6588 SysPrintf("warning: RAM is not directly mapped, performance will suffer\n");
6591 void new_dynarec_cleanup(void)
6594 #ifdef BASE_ADDR_DYNAMIC
6596 sceKernelFreeMemBlock(sceBlock);
6599 if (munmap(ndrc, sizeof(*ndrc)) < 0)
6600 SysPrintf("munmap() failed\n");
6603 for(n=0;n<4096;n++) ll_clear(jump_in+n);
6604 for(n=0;n<4096;n++) ll_clear(jump_out+n);
6605 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
6607 if (munmap (ROM_COPY, 67108864) < 0) {SysPrintf("munmap() failed\n");}
6611 static u_int *get_source_start(u_int addr, u_int *limit)
6613 if (addr < 0x00200000 ||
6614 (0xa0000000 <= addr && addr < 0xa0200000)) {
6615 // used for BIOS calls mostly?
6616 *limit = (addr&0xa0000000)|0x00200000;
6617 return (u_int *)(rdram + (addr&0x1fffff));
6619 else if (!Config.HLE && (
6620 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
6621 (0xbfc00000 <= addr && addr < 0xbfc80000))) {
6623 *limit = (addr & 0xfff00000) | 0x80000;
6624 return (u_int *)((u_char *)psxR + (addr&0x7ffff));
6626 else if (addr >= 0x80000000 && addr < 0x80000000+RAM_SIZE) {
6627 *limit = (addr & 0x80600000) + 0x00200000;
6628 return (u_int *)(rdram + (addr&0x1fffff));
6633 static u_int scan_for_ret(u_int addr)
6638 mem = get_source_start(addr, &limit);
6642 if (limit > addr + 0x1000)
6643 limit = addr + 0x1000;
6644 for (; addr < limit; addr += 4, mem++) {
6645 if (*mem == 0x03e00008) // jr $ra
6651 struct savestate_block {
6656 static int addr_cmp(const void *p1_, const void *p2_)
6658 const struct savestate_block *p1 = p1_, *p2 = p2_;
6659 return p1->addr - p2->addr;
6662 int new_dynarec_save_blocks(void *save, int size)
6664 struct savestate_block *blocks = save;
6665 int maxcount = size / sizeof(blocks[0]);
6666 struct savestate_block tmp_blocks[1024];
6667 struct ll_entry *head;
6668 int p, s, d, o, bcnt;
6672 for (p = 0; p < ARRAY_SIZE(jump_in); p++) {
6674 for (head = jump_in[p]; head != NULL; head = head->next) {
6675 tmp_blocks[bcnt].addr = head->vaddr;
6676 tmp_blocks[bcnt].regflags = head->reg_sv_flags;
6681 qsort(tmp_blocks, bcnt, sizeof(tmp_blocks[0]), addr_cmp);
6683 addr = tmp_blocks[0].addr;
6684 for (s = d = 0; s < bcnt; s++) {
6685 if (tmp_blocks[s].addr < addr)
6687 if (d == 0 || tmp_blocks[d-1].addr != tmp_blocks[s].addr)
6688 tmp_blocks[d++] = tmp_blocks[s];
6689 addr = scan_for_ret(tmp_blocks[s].addr);
6692 if (o + d > maxcount)
6694 memcpy(&blocks[o], tmp_blocks, d * sizeof(blocks[0]));
6698 return o * sizeof(blocks[0]);
6701 void new_dynarec_load_blocks(const void *save, int size)
6703 const struct savestate_block *blocks = save;
6704 int count = size / sizeof(blocks[0]);
6705 u_int regs_save[32];
6709 get_addr(psxRegs.pc);
6711 // change GPRs for speculation to at least partially work..
6712 memcpy(regs_save, &psxRegs.GPR, sizeof(regs_save));
6713 for (i = 1; i < 32; i++)
6714 psxRegs.GPR.r[i] = 0x80000000;
6716 for (b = 0; b < count; b++) {
6717 for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) {
6719 psxRegs.GPR.r[i] = 0x1f800000;
6722 get_addr(blocks[b].addr);
6724 for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) {
6726 psxRegs.GPR.r[i] = 0x80000000;
6730 memcpy(&psxRegs.GPR, regs_save, sizeof(regs_save));
6733 int new_recompile_block(u_int addr)
6735 u_int pagelimit = 0;
6736 u_int state_rflags = 0;
6739 assem_debug("NOTCOMPILED: addr = %x -> %p\n", addr, out);
6740 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
6742 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
6744 // this is just for speculation
6745 for (i = 1; i < 32; i++) {
6746 if ((psxRegs.GPR.r[i] & 0xffff0000) == 0x1f800000)
6747 state_rflags |= 1 << i;
6750 start = (u_int)addr&~3;
6751 //assert(((u_int)addr&1)==0); // start-in-delay-slot flag
6752 new_dynarec_did_compile=1;
6753 if (Config.HLE && start == 0x80001000) // hlecall
6755 // XXX: is this enough? Maybe check hleSoftCall?
6756 void *beginning=start_block();
6757 u_int page=get_page(start);
6759 invalid_code[start>>12]=0;
6760 emit_movimm(start,0);
6761 emit_writeword(0,&pcaddr);
6762 emit_far_jump(new_dyna_leave);
6764 end_block(beginning);
6765 ll_add_flags(jump_in+page,start,state_rflags,(void *)beginning);
6769 source = get_source_start(start, &pagelimit);
6770 if (source == NULL) {
6771 SysPrintf("Compile at bogus memory address: %08x\n", addr);
6775 /* Pass 1: disassemble */
6776 /* Pass 2: register dependencies, branch targets */
6777 /* Pass 3: register allocation */
6778 /* Pass 4: branch dependencies */
6779 /* Pass 5: pre-alloc */
6780 /* Pass 6: optimize clean/dirty state */
6781 /* Pass 7: flag 32-bit registers */
6782 /* Pass 8: assembly */
6783 /* Pass 9: linker */
6784 /* Pass 10: garbage collection / free memory */
6788 unsigned int type,op,op2;
6790 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
6792 /* Pass 1 disassembly */
6794 for(i=0;!done;i++) {
6795 bt[i]=0;likely[i]=0;ooo[i]=0;op2=0;
6796 minimum_free_regs[i]=0;
6797 opcode[i]=op=source[i]>>26;
6800 case 0x00: strcpy(insn[i],"special"); type=NI;
6804 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
6805 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
6806 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
6807 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
6808 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
6809 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
6810 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
6811 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
6812 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
6813 case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
6814 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
6815 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
6816 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
6817 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
6818 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
6819 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
6820 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
6821 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
6822 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
6823 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
6824 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
6825 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
6826 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
6827 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
6828 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
6829 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
6830 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
6831 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
6832 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
6833 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
6834 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
6835 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
6836 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
6837 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
6838 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
6840 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
6841 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
6842 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
6843 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
6844 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
6845 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
6846 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
6847 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
6848 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
6849 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
6850 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
6851 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
6852 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
6853 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
6854 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
6855 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
6856 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
6860 case 0x01: strcpy(insn[i],"regimm"); type=NI;
6861 op2=(source[i]>>16)&0x1f;
6864 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
6865 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
6866 case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
6867 case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
6868 case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
6869 case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
6870 case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
6871 case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
6872 case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
6873 case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
6874 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
6875 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
6876 case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
6877 case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
6880 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
6881 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
6882 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
6883 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
6884 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
6885 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
6886 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
6887 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
6888 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
6889 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
6890 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
6891 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
6892 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
6893 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
6894 case 0x10: strcpy(insn[i],"cop0"); type=NI;
6895 op2=(source[i]>>21)&0x1f;
6898 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
6899 case 0x02: strcpy(insn[i],"CFC0"); type=COP0; break;
6900 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
6901 case 0x06: strcpy(insn[i],"CTC0"); type=COP0; break;
6902 case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
6905 case 0x11: strcpy(insn[i],"cop1"); type=COP1;
6906 op2=(source[i]>>21)&0x1f;
6909 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
6910 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
6911 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
6912 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
6913 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
6914 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
6915 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
6916 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
6918 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
6919 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
6920 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
6921 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
6922 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
6923 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
6924 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
6926 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
6928 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
6929 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
6930 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
6931 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
6933 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
6934 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
6936 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
6937 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
6938 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
6939 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
6941 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
6942 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
6943 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
6945 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
6946 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
6948 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
6949 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
6950 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
6952 case 0x12: strcpy(insn[i],"COP2"); type=NI;
6953 op2=(source[i]>>21)&0x1f;
6955 if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
6956 if (gte_handlers[source[i]&0x3f]!=NULL) {
6957 if (gte_regnames[source[i]&0x3f]!=NULL)
6958 strcpy(insn[i],gte_regnames[source[i]&0x3f]);
6960 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
6966 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
6967 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
6968 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
6969 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
6972 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
6973 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
6974 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
6975 default: strcpy(insn[i],"???"); type=NI;
6976 SysPrintf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
6981 /* Get registers/immediates */
6985 gte_rs[i]=gte_rt[i]=0;
6988 rs1[i]=(source[i]>>21)&0x1f;
6990 rt1[i]=(source[i]>>16)&0x1f;
6992 imm[i]=(short)source[i];
6996 rs1[i]=(source[i]>>21)&0x1f;
6997 rs2[i]=(source[i]>>16)&0x1f;
7000 imm[i]=(short)source[i];
7003 // LWL/LWR only load part of the register,
7004 // therefore the target register must be treated as a source too
7005 rs1[i]=(source[i]>>21)&0x1f;
7006 rs2[i]=(source[i]>>16)&0x1f;
7007 rt1[i]=(source[i]>>16)&0x1f;
7009 imm[i]=(short)source[i];
7010 if(op==0x26) dep1[i]=rt1[i]; // LWR
7013 if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
7014 else rs1[i]=(source[i]>>21)&0x1f;
7016 rt1[i]=(source[i]>>16)&0x1f;
7018 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
7019 imm[i]=(unsigned short)source[i];
7021 imm[i]=(short)source[i];
7023 if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
7030 // The JAL instruction writes to r31.
7037 rs1[i]=(source[i]>>21)&0x1f;
7041 // The JALR instruction writes to rd.
7043 rt1[i]=(source[i]>>11)&0x1f;
7048 rs1[i]=(source[i]>>21)&0x1f;
7049 rs2[i]=(source[i]>>16)&0x1f;
7052 if(op&2) { // BGTZ/BLEZ
7058 rs1[i]=(source[i]>>21)&0x1f;
7062 if(op2&0x10) { // BxxAL
7064 // NOTE: If the branch is not taken, r31 is still overwritten
7066 likely[i]=(op2&2)>>1;
7069 rs1[i]=(source[i]>>21)&0x1f; // source
7070 rs2[i]=(source[i]>>16)&0x1f; // subtract amount
7071 rt1[i]=(source[i]>>11)&0x1f; // destination
7073 if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
7074 dep1[i]=rs1[i];dep2[i]=rs2[i];
7076 else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
7077 dep1[i]=rs1[i];dep2[i]=rs2[i];
7081 rs1[i]=(source[i]>>21)&0x1f; // source
7082 rs2[i]=(source[i]>>16)&0x1f; // divisor
7091 if(op2==0x10) rs1[i]=HIREG; // MFHI
7092 if(op2==0x11) rt1[i]=HIREG; // MTHI
7093 if(op2==0x12) rs1[i]=LOREG; // MFLO
7094 if(op2==0x13) rt1[i]=LOREG; // MTLO
7095 if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
7096 if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
7100 rs1[i]=(source[i]>>16)&0x1f; // target of shift
7101 rs2[i]=(source[i]>>21)&0x1f; // shift amount
7102 rt1[i]=(source[i]>>11)&0x1f; // destination
7106 rs1[i]=(source[i]>>16)&0x1f;
7108 rt1[i]=(source[i]>>11)&0x1f;
7110 imm[i]=(source[i]>>6)&0x1f;
7111 // DSxx32 instructions
7112 if(op2>=0x3c) imm[i]|=0x20;
7119 if(op2==0||op2==2) rt1[i]=(source[i]>>16)&0x1F; // MFC0/CFC0
7120 if(op2==4||op2==6) rs1[i]=(source[i]>>16)&0x1F; // MTC0/CTC0
7121 if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
7122 if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
7129 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
7130 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
7138 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC2/CFC2
7139 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC2/CTC2
7141 int gr=(source[i]>>11)&0x1F;
7144 case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
7145 case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
7146 case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2
7147 case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
7151 rs1[i]=(source[i]>>21)&0x1F;
7155 imm[i]=(short)source[i];
7158 rs1[i]=(source[i]>>21)&0x1F;
7162 imm[i]=(short)source[i];
7163 if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
7164 else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
7171 gte_rs[i]=gte_reg_reads[source[i]&0x3f];
7172 gte_rt[i]=gte_reg_writes[source[i]&0x3f];
7173 gte_rt[i]|=1ll<<63; // every op changes flags
7174 if((source[i]&0x3f)==GTE_MVMVA) {
7175 int v = (source[i] >> 15) & 3;
7176 gte_rs[i]&=~0xe3fll;
7177 if(v==3) gte_rs[i]|=0xe00ll;
7178 else gte_rs[i]|=3ll<<(v*2);
7195 /* Calculate branch target addresses */
7197 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
7198 else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
7199 ba[i]=start+i*4+8; // Ignore never taken branch
7200 else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
7201 ba[i]=start+i*4+8; // Ignore never taken branch
7202 else if(type==CJUMP||type==SJUMP)
7203 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
7205 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP)) {
7207 // branch in delay slot?
7208 if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP) {
7209 // don't handle first branch and call interpreter if it's hit
7210 SysPrintf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
7213 // basic load delay detection
7214 else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&rt1[i]!=0) {
7215 int t=(ba[i-1]-start)/4;
7216 if(0 <= t && t < i &&(rt1[i]==rs1[t]||rt1[i]==rs2[t])&&itype[t]!=CJUMP&&itype[t]!=SJUMP) {
7217 // jump target wants DS result - potential load delay effect
7218 SysPrintf("load delay @%08x (%08x)\n", addr + i*4, addr);
7220 bt[t+1]=1; // expected return from interpreter
7222 else if(i>=2&&rt1[i-2]==2&&rt1[i]==2&&rs1[i]!=2&&rs2[i]!=2&&rs1[i-1]!=2&&rs2[i-1]!=2&&
7223 !(i>=3&&(itype[i-3]==RJUMP||itype[i-3]==UJUMP||itype[i-3]==CJUMP||itype[i-3]==SJUMP))) {
7224 // v0 overwrite like this is a sign of trouble, bail out
7225 SysPrintf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
7231 rs2[i-1]=rt1[i-1]=rt2[i-1]=0;
7235 i--; // don't compile the DS
7238 /* Is this the end of the block? */
7239 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
7240 if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
7244 if(stop_after_jal) done=1;
7246 if((source[i+1]&0xfc00003f)==0x0d) done=1;
7248 // Don't recompile stuff that's already compiled
7249 if(check_addr(start+i*4+4)) done=1;
7250 // Don't get too close to the limit
7251 if(i>MAXBLOCK/2) done=1;
7253 if(itype[i]==SYSCALL&&stop_after_jal) done=1;
7254 if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
7256 // Does the block continue due to a branch?
7259 if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
7260 if(ba[j]==start+i*4+4) done=j=0;
7261 if(ba[j]==start+i*4+8) done=j=0;
7264 //assert(i<MAXBLOCK-1);
7265 if(start+i*4==pagelimit-4) done=1;
7266 assert(start+i*4<pagelimit);
7267 if (i==MAXBLOCK-1) done=1;
7268 // Stop if we're compiling junk
7269 if(itype[i]==NI&&opcode[i]==0x11) {
7270 done=stop_after_jal=1;
7271 SysPrintf("Disabled speculative precompilation\n");
7275 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP) {
7276 if(start+i*4==pagelimit) {
7282 /* Pass 2 - Register dependencies and branch targets */
7284 unneeded_registers(0,slen-1,0);
7286 /* Pass 3 - Register allocation */
7288 struct regstat current; // Current register allocations/status
7290 current.u=unneeded_reg[0];
7291 clear_all_regs(current.regmap);
7292 alloc_reg(¤t,0,CCREG);
7293 dirty_reg(¤t,CCREG);
7296 current.waswritten=0;
7302 // First instruction is delay slot
7307 current.regmap[HOST_BTREG]=BTREG;
7315 for(hr=0;hr<HOST_REGS;hr++)
7317 // Is this really necessary?
7318 if(current.regmap[hr]==0) current.regmap[hr]=-1;
7321 current.waswritten=0;
7324 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
7325 regs[i].wasconst=current.isconst;
7326 regs[i].wasdirty=current.dirty;
7327 regs[i].loadedconst=0;
7328 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP) {
7330 current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
7337 current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
7338 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
7340 } else { SysPrintf("oops, branch at end of block with no delay slot\n");abort(); }
7344 ds=0; // Skip delay slot, already allocated as part of branch
7345 // ...but we need to alloc it in case something jumps here
7347 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
7349 current.u=branch_unneeded_reg[i-1];
7351 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
7353 struct regstat temp;
7354 memcpy(&temp,¤t,sizeof(current));
7355 temp.wasdirty=temp.dirty;
7356 // TODO: Take into account unconditional branches, as below
7357 delayslot_alloc(&temp,i);
7358 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
7359 regs[i].wasdirty=temp.wasdirty;
7360 regs[i].dirty=temp.dirty;
7364 // Create entry (branch target) regmap
7365 for(hr=0;hr<HOST_REGS;hr++)
7367 int r=temp.regmap[hr];
7369 if(r!=regmap_pre[i][hr]) {
7370 regs[i].regmap_entry[hr]=-1;
7375 if((current.u>>r)&1) {
7376 regs[i].regmap_entry[hr]=-1;
7377 regs[i].regmap[hr]=-1;
7378 //Don't clear regs in the delay slot as the branch might need them
7379 //current.regmap[hr]=-1;
7381 regs[i].regmap_entry[hr]=r;
7384 // First instruction expects CCREG to be allocated
7385 if(i==0&&hr==HOST_CCREG)
7386 regs[i].regmap_entry[hr]=CCREG;
7388 regs[i].regmap_entry[hr]=-1;
7392 else { // Not delay slot
7395 //current.isconst=0; // DEBUG
7396 //current.wasconst=0; // DEBUG
7397 //regs[i].wasconst=0; // DEBUG
7398 clear_const(¤t,rt1[i]);
7399 alloc_cc(¤t,i);
7400 dirty_reg(¤t,CCREG);
7402 alloc_reg(¤t,i,31);
7403 dirty_reg(¤t,31);
7404 //assert(rs1[i+1]!=31&&rs2[i+1]!=31);
7405 //assert(rt1[i+1]!=rt1[i]);
7407 alloc_reg(¤t,i,PTEMP);
7411 delayslot_alloc(¤t,i+1);
7412 //current.isconst=0; // DEBUG
7414 //printf("i=%d, isconst=%x\n",i,current.isconst);
7417 //current.isconst=0;
7418 //current.wasconst=0;
7419 //regs[i].wasconst=0;
7420 clear_const(¤t,rs1[i]);
7421 clear_const(¤t,rt1[i]);
7422 alloc_cc(¤t,i);
7423 dirty_reg(¤t,CCREG);
7424 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
7425 alloc_reg(¤t,i,rs1[i]);
7427 alloc_reg(¤t,i,rt1[i]);
7428 dirty_reg(¤t,rt1[i]);
7429 assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
7430 assert(rt1[i+1]!=rt1[i]);
7432 alloc_reg(¤t,i,PTEMP);
7436 if(rs1[i]==31) { // JALR
7437 alloc_reg(¤t,i,RHASH);
7438 alloc_reg(¤t,i,RHTBL);
7441 delayslot_alloc(¤t,i+1);
7443 // The delay slot overwrites our source register,
7444 // allocate a temporary register to hold the old value.
7448 delayslot_alloc(¤t,i+1);
7450 alloc_reg(¤t,i,RTEMP);
7452 //current.isconst=0; // DEBUG
7457 //current.isconst=0;
7458 //current.wasconst=0;
7459 //regs[i].wasconst=0;
7460 clear_const(¤t,rs1[i]);
7461 clear_const(¤t,rs2[i]);
7462 if((opcode[i]&0x3E)==4) // BEQ/BNE
7464 alloc_cc(¤t,i);
7465 dirty_reg(¤t,CCREG);
7466 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
7467 if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
7468 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
7469 (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
7470 // The delay slot overwrites one of our conditions.
7471 // Allocate the branch condition registers instead.
7475 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
7476 if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
7481 delayslot_alloc(¤t,i+1);
7485 if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
7487 alloc_cc(¤t,i);
7488 dirty_reg(¤t,CCREG);
7489 alloc_reg(¤t,i,rs1[i]);
7490 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
7491 // The delay slot overwrites one of our conditions.
7492 // Allocate the branch condition registers instead.
7496 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
7501 delayslot_alloc(¤t,i+1);
7505 // Don't alloc the delay slot yet because we might not execute it
7506 if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
7511 alloc_cc(¤t,i);
7512 dirty_reg(¤t,CCREG);
7513 alloc_reg(¤t,i,rs1[i]);
7514 alloc_reg(¤t,i,rs2[i]);
7517 if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
7522 alloc_cc(¤t,i);
7523 dirty_reg(¤t,CCREG);
7524 alloc_reg(¤t,i,rs1[i]);
7527 //current.isconst=0;
7530 //current.isconst=0;
7531 //current.wasconst=0;
7532 //regs[i].wasconst=0;
7533 clear_const(¤t,rs1[i]);
7534 clear_const(¤t,rt1[i]);
7535 //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
7536 if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
7538 alloc_cc(¤t,i);
7539 dirty_reg(¤t,CCREG);
7540 alloc_reg(¤t,i,rs1[i]);
7541 if (rt1[i]==31) { // BLTZAL/BGEZAL
7542 alloc_reg(¤t,i,31);
7543 dirty_reg(¤t,31);
7544 //#ifdef REG_PREFETCH
7545 //alloc_reg(¤t,i,PTEMP);
7548 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) // The delay slot overwrites the branch condition.
7549 ||(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))) { // DS touches $ra
7550 // Allocate the branch condition registers instead.
7554 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
7559 delayslot_alloc(¤t,i+1);
7563 // Don't alloc the delay slot yet because we might not execute it
7564 if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
7569 alloc_cc(¤t,i);
7570 dirty_reg(¤t,CCREG);
7571 alloc_reg(¤t,i,rs1[i]);
7574 //current.isconst=0;
7577 imm16_alloc(¤t,i);
7581 load_alloc(¤t,i);
7585 store_alloc(¤t,i);
7588 alu_alloc(¤t,i);
7591 shift_alloc(¤t,i);
7594 multdiv_alloc(¤t,i);
7597 shiftimm_alloc(¤t,i);
7600 mov_alloc(¤t,i);
7603 cop0_alloc(¤t,i);
7607 cop12_alloc(¤t,i);
7610 c1ls_alloc(¤t,i);
7613 c2ls_alloc(¤t,i);
7616 c2op_alloc(¤t,i);
7621 syscall_alloc(¤t,i);
7624 pagespan_alloc(¤t,i);
7628 // Create entry (branch target) regmap
7629 for(hr=0;hr<HOST_REGS;hr++)
7632 r=current.regmap[hr];
7634 if(r!=regmap_pre[i][hr]) {
7635 // TODO: delay slot (?)
7636 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
7637 if(or<0||(r&63)>=TEMPREG){
7638 regs[i].regmap_entry[hr]=-1;
7642 // Just move it to a different register
7643 regs[i].regmap_entry[hr]=r;
7644 // If it was dirty before, it's still dirty
7645 if((regs[i].wasdirty>>or)&1) dirty_reg(¤t,r&63);
7652 regs[i].regmap_entry[hr]=0;
7657 if((current.u>>r)&1) {
7658 regs[i].regmap_entry[hr]=-1;
7659 //regs[i].regmap[hr]=-1;
7660 current.regmap[hr]=-1;
7662 regs[i].regmap_entry[hr]=r;
7666 // Branches expect CCREG to be allocated at the target
7667 if(regmap_pre[i][hr]==CCREG)
7668 regs[i].regmap_entry[hr]=CCREG;
7670 regs[i].regmap_entry[hr]=-1;
7673 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
7676 if(i>0&&(itype[i-1]==STORE||itype[i-1]==STORELR||(itype[i-1]==C2LS&&opcode[i-1]==0x3a))&&(u_int)imm[i-1]<0x800)
7677 current.waswritten|=1<<rs1[i-1];
7678 current.waswritten&=~(1<<rt1[i]);
7679 current.waswritten&=~(1<<rt2[i]);
7680 if((itype[i]==STORE||itype[i]==STORELR||(itype[i]==C2LS&&opcode[i]==0x3a))&&(u_int)imm[i]>=0x800)
7681 current.waswritten&=~(1<<rs1[i]);
7683 /* Branch post-alloc */
7686 current.wasdirty=current.dirty;
7687 switch(itype[i-1]) {
7689 memcpy(&branch_regs[i-1],¤t,sizeof(current));
7690 branch_regs[i-1].isconst=0;
7691 branch_regs[i-1].wasconst=0;
7692 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
7693 alloc_cc(&branch_regs[i-1],i-1);
7694 dirty_reg(&branch_regs[i-1],CCREG);
7695 if(rt1[i-1]==31) { // JAL
7696 alloc_reg(&branch_regs[i-1],i-1,31);
7697 dirty_reg(&branch_regs[i-1],31);
7699 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
7700 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
7703 memcpy(&branch_regs[i-1],¤t,sizeof(current));
7704 branch_regs[i-1].isconst=0;
7705 branch_regs[i-1].wasconst=0;
7706 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
7707 alloc_cc(&branch_regs[i-1],i-1);
7708 dirty_reg(&branch_regs[i-1],CCREG);
7709 alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
7710 if(rt1[i-1]!=0) { // JALR
7711 alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
7712 dirty_reg(&branch_regs[i-1],rt1[i-1]);
7715 if(rs1[i-1]==31) { // JALR
7716 alloc_reg(&branch_regs[i-1],i-1,RHASH);
7717 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
7720 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
7721 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
7724 if((opcode[i-1]&0x3E)==4) // BEQ/BNE
7726 alloc_cc(¤t,i-1);
7727 dirty_reg(¤t,CCREG);
7728 if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
7729 (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
7730 // The delay slot overwrote one of our conditions
7731 // Delay slot goes after the test (in order)
7732 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
7734 delayslot_alloc(¤t,i);
7739 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
7740 // Alloc the branch condition registers
7741 if(rs1[i-1]) alloc_reg(¤t,i-1,rs1[i-1]);
7742 if(rs2[i-1]) alloc_reg(¤t,i-1,rs2[i-1]);
7744 memcpy(&branch_regs[i-1],¤t,sizeof(current));
7745 branch_regs[i-1].isconst=0;
7746 branch_regs[i-1].wasconst=0;
7747 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
7748 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
7751 if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
7753 alloc_cc(¤t,i-1);
7754 dirty_reg(¤t,CCREG);
7755 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
7756 // The delay slot overwrote the branch condition
7757 // Delay slot goes after the test (in order)
7758 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
7760 delayslot_alloc(¤t,i);
7765 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
7766 // Alloc the branch condition register
7767 alloc_reg(¤t,i-1,rs1[i-1]);
7769 memcpy(&branch_regs[i-1],¤t,sizeof(current));
7770 branch_regs[i-1].isconst=0;
7771 branch_regs[i-1].wasconst=0;
7772 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
7773 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
7776 // Alloc the delay slot in case the branch is taken
7777 if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
7779 memcpy(&branch_regs[i-1],¤t,sizeof(current));
7780 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
7781 alloc_cc(&branch_regs[i-1],i);
7782 dirty_reg(&branch_regs[i-1],CCREG);
7783 delayslot_alloc(&branch_regs[i-1],i);
7784 branch_regs[i-1].isconst=0;
7785 alloc_reg(¤t,i,CCREG); // Not taken path
7786 dirty_reg(¤t,CCREG);
7787 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
7790 if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
7792 memcpy(&branch_regs[i-1],¤t,sizeof(current));
7793 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
7794 alloc_cc(&branch_regs[i-1],i);
7795 dirty_reg(&branch_regs[i-1],CCREG);
7796 delayslot_alloc(&branch_regs[i-1],i);
7797 branch_regs[i-1].isconst=0;
7798 alloc_reg(¤t,i,CCREG); // Not taken path
7799 dirty_reg(¤t,CCREG);
7800 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
7804 //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
7805 if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
7807 alloc_cc(¤t,i-1);
7808 dirty_reg(¤t,CCREG);
7809 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
7810 // The delay slot overwrote the branch condition
7811 // Delay slot goes after the test (in order)
7812 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
7814 delayslot_alloc(¤t,i);
7819 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
7820 // Alloc the branch condition register
7821 alloc_reg(¤t,i-1,rs1[i-1]);
7823 memcpy(&branch_regs[i-1],¤t,sizeof(current));
7824 branch_regs[i-1].isconst=0;
7825 branch_regs[i-1].wasconst=0;
7826 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
7827 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
7830 // Alloc the delay slot in case the branch is taken
7831 if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
7833 memcpy(&branch_regs[i-1],¤t,sizeof(current));
7834 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
7835 alloc_cc(&branch_regs[i-1],i);
7836 dirty_reg(&branch_regs[i-1],CCREG);
7837 delayslot_alloc(&branch_regs[i-1],i);
7838 branch_regs[i-1].isconst=0;
7839 alloc_reg(¤t,i,CCREG); // Not taken path
7840 dirty_reg(¤t,CCREG);
7841 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
7843 // FIXME: BLTZAL/BGEZAL
7844 if(opcode2[i-1]&0x10) { // BxxZAL
7845 alloc_reg(&branch_regs[i-1],i-1,31);
7846 dirty_reg(&branch_regs[i-1],31);
7851 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
7853 if(rt1[i-1]==31) // JAL/JALR
7855 // Subroutine call will return here, don't alloc any registers
7857 clear_all_regs(current.regmap);
7858 alloc_reg(¤t,i,CCREG);
7859 dirty_reg(¤t,CCREG);
7863 // Internal branch will jump here, match registers to caller
7865 clear_all_regs(current.regmap);
7866 alloc_reg(¤t,i,CCREG);
7867 dirty_reg(¤t,CCREG);
7870 if(ba[j]==start+i*4+4) {
7871 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
7872 current.dirty=branch_regs[j].dirty;
7877 if(ba[j]==start+i*4+4) {
7878 for(hr=0;hr<HOST_REGS;hr++) {
7879 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
7880 current.regmap[hr]=-1;
7882 current.dirty&=branch_regs[j].dirty;
7891 // Count cycles in between branches
7893 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
7897 #if !defined(DRC_DBG)
7898 else if(itype[i]==C2OP&>e_cycletab[source[i]&0x3f]>2)
7900 // GTE runs in parallel until accessed, divide by 2 for a rough guess
7901 cc+=gte_cycletab[source[i]&0x3f]/2;
7903 else if(/*itype[i]==LOAD||itype[i]==STORE||*/itype[i]==C1LS) // load,store causes weird timing issues
7905 cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
7907 else if(i>1&&itype[i]==STORE&&itype[i-1]==STORE&&itype[i-2]==STORE&&!bt[i])
7911 else if(itype[i]==C2LS)
7922 regs[i].dirty=current.dirty;
7923 regs[i].isconst=current.isconst;
7924 memcpy(constmap[i],current_constmap,sizeof(current_constmap));
7926 for(hr=0;hr<HOST_REGS;hr++) {
7927 if(hr!=EXCLUDE_REG&®s[i].regmap[hr]>=0) {
7928 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
7929 regs[i].wasconst&=~(1<<hr);
7933 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
7934 regs[i].waswritten=current.waswritten;
7937 /* Pass 4 - Cull unused host registers */
7941 for (i=slen-1;i>=0;i--)
7944 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP)
7946 if(ba[i]<start || ba[i]>=(start+slen*4))
7948 // Branch out of this block, don't need anything
7954 // Need whatever matches the target
7956 int t=(ba[i]-start)>>2;
7957 for(hr=0;hr<HOST_REGS;hr++)
7959 if(regs[i].regmap_entry[hr]>=0) {
7960 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
7964 // Conditional branch may need registers for following instructions
7965 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7968 nr|=needed_reg[i+2];
7969 for(hr=0;hr<HOST_REGS;hr++)
7971 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
7972 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
7976 // Don't need stuff which is overwritten
7977 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
7978 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
7979 // Merge in delay slot
7980 for(hr=0;hr<HOST_REGS;hr++)
7983 // These are overwritten unless the branch is "likely"
7984 // and the delay slot is nullified if not taken
7985 if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
7986 if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
7988 if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
7989 if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
7990 if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
7991 if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
7992 if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
7993 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
7994 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
7998 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
8000 // SYSCALL instruction (software interrupt)
8003 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
8005 // ERET instruction (return from interrupt)
8011 for(hr=0;hr<HOST_REGS;hr++) {
8012 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
8013 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
8014 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
8015 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
8019 for(hr=0;hr<HOST_REGS;hr++)
8021 // Overwritten registers are not needed
8022 if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8023 if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8024 if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8025 // Source registers are needed
8026 if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
8027 if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
8028 if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
8029 if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
8030 if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
8031 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
8032 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
8034 // Don't store a register immediately after writing it,
8035 // may prevent dual-issue.
8036 // But do so if this is a branch target, otherwise we
8037 // might have to load the register before the branch.
8038 if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
8039 if((regmap_pre[i][hr]>0&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1))) {
8040 if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8041 if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8043 if((regs[i].regmap_entry[hr]>0&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1))) {
8044 if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8045 if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8049 // Cycle count is needed at branches. Assume it is needed at the target too.
8050 if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==SPAN) {
8051 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
8052 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
8057 // Deallocate unneeded registers
8058 for(hr=0;hr<HOST_REGS;hr++)
8061 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
8062 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
8063 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
8064 (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
8066 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
8069 regs[i].regmap[hr]=-1;
8070 regs[i].isconst&=~(1<<hr);
8072 regmap_pre[i+2][hr]=-1;
8073 regs[i+2].wasconst&=~(1<<hr);
8078 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP)
8081 if(itype[i+1]==STORE || itype[i+1]==STORELR ||
8082 (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
8085 if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
8086 itype[i+1]==C1LS || itype[i+1]==C2LS)
8088 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
8089 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
8090 (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
8091 regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
8092 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
8093 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
8094 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
8095 regs[i].regmap[hr]!=map )
8097 regs[i].regmap[hr]=-1;
8098 regs[i].isconst&=~(1<<hr);
8099 if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
8100 (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
8101 (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
8102 branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
8103 (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
8104 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
8105 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
8106 branch_regs[i].regmap[hr]!=map)
8108 branch_regs[i].regmap[hr]=-1;
8109 branch_regs[i].regmap_entry[hr]=-1;
8110 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
8112 if(!likely[i]&&i<slen-2) {
8113 regmap_pre[i+2][hr]=-1;
8114 regs[i+2].wasconst&=~(1<<hr);
8126 if(itype[i]==STORE || itype[i]==STORELR ||
8127 (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
8130 if(itype[i]==LOADLR || itype[i]==STORELR ||
8131 itype[i]==C1LS || itype[i]==C2LS)
8133 if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
8134 regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
8135 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
8136 (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
8138 if(i<slen-1&&!is_ds[i]) {
8139 assert(regs[i].regmap[hr]<64);
8140 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]>0)
8141 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
8143 SysPrintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
8144 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
8146 regmap_pre[i+1][hr]=-1;
8147 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
8148 regs[i+1].wasconst&=~(1<<hr);
8150 regs[i].regmap[hr]=-1;
8151 regs[i].isconst&=~(1<<hr);
8159 /* Pass 5 - Pre-allocate registers */
8161 // If a register is allocated during a loop, try to allocate it for the
8162 // entire loop, if possible. This avoids loading/storing registers
8163 // inside of the loop.
8165 signed char f_regmap[HOST_REGS];
8166 clear_all_regs(f_regmap);
8167 for(i=0;i<slen-1;i++)
8169 if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP)
8171 if(ba[i]>=start && ba[i]<(start+i*4))
8172 if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
8173 ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
8174 ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
8175 ||itype[i+1]==SHIFT||itype[i+1]==COP1
8176 ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
8178 int t=(ba[i]-start)>>2;
8179 if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP)) // loop_preload can't handle jumps into delay slots
8180 if(t<2||(itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||rt1[t-2]!=31) // call/ret assumes no registers allocated
8181 for(hr=0;hr<HOST_REGS;hr++)
8183 if(regs[i].regmap[hr]>=0) {
8184 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8185 // dealloc old register
8187 for(n=0;n<HOST_REGS;n++)
8189 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8191 // and alloc new one
8192 f_regmap[hr]=regs[i].regmap[hr];
8195 if(branch_regs[i].regmap[hr]>=0) {
8196 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
8197 // dealloc old register
8199 for(n=0;n<HOST_REGS;n++)
8201 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
8203 // and alloc new one
8204 f_regmap[hr]=branch_regs[i].regmap[hr];
8208 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
8209 f_regmap[hr]=branch_regs[i].regmap[hr];
8211 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
8212 f_regmap[hr]=branch_regs[i].regmap[hr];
8214 // Avoid dirty->clean transition
8215 #ifdef DESTRUCTIVE_WRITEBACK
8216 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
8218 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
8219 // case above, however it's always a good idea. We can't hoist the
8220 // load if the register was already allocated, so there's no point
8221 // wasting time analyzing most of these cases. It only "succeeds"
8222 // when the mapping was different and the load can be replaced with
8223 // a mov, which is of negligible benefit. So such cases are
8225 if(f_regmap[hr]>0) {
8226 if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
8230 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
8231 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
8233 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
8234 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
8236 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
8237 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
8239 if(get_reg(regs[i].regmap,r&63)<0) break;
8240 if(get_reg(branch_regs[i].regmap,r&63)<0) break;
8243 while(k>1&®s[k-1].regmap[hr]==-1) {
8244 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
8245 //printf("no free regs for store %x\n",start+(k-1)*4);
8248 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
8249 //printf("no-match due to different register\n");
8252 if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP) {
8253 //printf("no-match due to branch\n");
8256 // call/ret fast path assumes no registers allocated
8257 if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)&&rt1[k-3]==31) {
8263 if(regs[k-1].regmap[hr]==f_regmap[hr]&®map_pre[k][hr]==f_regmap[hr]) {
8264 //printf("Extend r%d, %x ->\n",hr,start+k*4);
8266 regs[k].regmap_entry[hr]=f_regmap[hr];
8267 regs[k].regmap[hr]=f_regmap[hr];
8268 regmap_pre[k+1][hr]=f_regmap[hr];
8269 regs[k].wasdirty&=~(1<<hr);
8270 regs[k].dirty&=~(1<<hr);
8271 regs[k].wasdirty|=(1<<hr)®s[k-1].dirty;
8272 regs[k].dirty|=(1<<hr)®s[k].wasdirty;
8273 regs[k].wasconst&=~(1<<hr);
8274 regs[k].isconst&=~(1<<hr);
8279 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
8282 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
8283 if(regs[i-1].regmap[hr]==f_regmap[hr]&®map_pre[i][hr]==f_regmap[hr]) {
8284 //printf("OK fill %x (r%d)\n",start+i*4,hr);
8285 regs[i].regmap_entry[hr]=f_regmap[hr];
8286 regs[i].regmap[hr]=f_regmap[hr];
8287 regs[i].wasdirty&=~(1<<hr);
8288 regs[i].dirty&=~(1<<hr);
8289 regs[i].wasdirty|=(1<<hr)®s[i-1].dirty;
8290 regs[i].dirty|=(1<<hr)®s[i-1].dirty;
8291 regs[i].wasconst&=~(1<<hr);
8292 regs[i].isconst&=~(1<<hr);
8293 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
8294 branch_regs[i].wasdirty&=~(1<<hr);
8295 branch_regs[i].wasdirty|=(1<<hr)®s[i].dirty;
8296 branch_regs[i].regmap[hr]=f_regmap[hr];
8297 branch_regs[i].dirty&=~(1<<hr);
8298 branch_regs[i].dirty|=(1<<hr)®s[i].dirty;
8299 branch_regs[i].wasconst&=~(1<<hr);
8300 branch_regs[i].isconst&=~(1<<hr);
8301 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
8302 regmap_pre[i+2][hr]=f_regmap[hr];
8303 regs[i+2].wasdirty&=~(1<<hr);
8304 regs[i+2].wasdirty|=(1<<hr)®s[i].dirty;
8309 // Alloc register clean at beginning of loop,
8310 // but may dirty it in pass 6
8311 regs[k].regmap_entry[hr]=f_regmap[hr];
8312 regs[k].regmap[hr]=f_regmap[hr];
8313 regs[k].dirty&=~(1<<hr);
8314 regs[k].wasconst&=~(1<<hr);
8315 regs[k].isconst&=~(1<<hr);
8316 if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP) {
8317 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
8318 branch_regs[k].regmap[hr]=f_regmap[hr];
8319 branch_regs[k].dirty&=~(1<<hr);
8320 branch_regs[k].wasconst&=~(1<<hr);
8321 branch_regs[k].isconst&=~(1<<hr);
8322 if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
8323 regmap_pre[k+2][hr]=f_regmap[hr];
8324 regs[k+2].wasdirty&=~(1<<hr);
8329 regmap_pre[k+1][hr]=f_regmap[hr];
8330 regs[k+1].wasdirty&=~(1<<hr);
8333 if(regs[j].regmap[hr]==f_regmap[hr])
8334 regs[j].regmap_entry[hr]=f_regmap[hr];
8338 if(regs[j].regmap[hr]>=0)
8340 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
8341 //printf("no-match due to different register\n");
8344 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
8346 // Stop on unconditional branch
8349 if(itype[j]==CJUMP||itype[j]==SJUMP)
8352 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
8355 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
8358 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
8359 //printf("no-match due to different register (branch)\n");
8363 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
8364 //printf("No free regs for store %x\n",start+j*4);
8367 assert(f_regmap[hr]<64);
8374 // Non branch or undetermined branch target
8375 for(hr=0;hr<HOST_REGS;hr++)
8377 if(hr!=EXCLUDE_REG) {
8378 if(regs[i].regmap[hr]>=0) {
8379 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8380 // dealloc old register
8382 for(n=0;n<HOST_REGS;n++)
8384 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8386 // and alloc new one
8387 f_regmap[hr]=regs[i].regmap[hr];
8392 // Try to restore cycle count at branch targets
8394 for(j=i;j<slen-1;j++) {
8395 if(regs[j].regmap[HOST_CCREG]!=-1) break;
8396 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
8397 //printf("no free regs for store %x\n",start+j*4);
8401 if(regs[j].regmap[HOST_CCREG]==CCREG) {
8403 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
8405 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8406 regs[k].regmap[HOST_CCREG]=CCREG;
8407 regmap_pre[k+1][HOST_CCREG]=CCREG;
8408 regs[k+1].wasdirty|=1<<HOST_CCREG;
8409 regs[k].dirty|=1<<HOST_CCREG;
8410 regs[k].wasconst&=~(1<<HOST_CCREG);
8411 regs[k].isconst&=~(1<<HOST_CCREG);
8414 regs[j].regmap_entry[HOST_CCREG]=CCREG;
8416 // Work backwards from the branch target
8417 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
8419 //printf("Extend backwards\n");
8422 while(regs[k-1].regmap[HOST_CCREG]==-1) {
8423 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
8424 //printf("no free regs for store %x\n",start+(k-1)*4);
8429 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
8430 //printf("Extend CC, %x ->\n",start+k*4);
8432 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8433 regs[k].regmap[HOST_CCREG]=CCREG;
8434 regmap_pre[k+1][HOST_CCREG]=CCREG;
8435 regs[k+1].wasdirty|=1<<HOST_CCREG;
8436 regs[k].dirty|=1<<HOST_CCREG;
8437 regs[k].wasconst&=~(1<<HOST_CCREG);
8438 regs[k].isconst&=~(1<<HOST_CCREG);
8443 //printf("Fail Extend CC, %x ->\n",start+k*4);
8447 if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
8448 itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
8449 itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1)
8451 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
8456 // This allocates registers (if possible) one instruction prior
8457 // to use, which can avoid a load-use penalty on certain CPUs.
8458 for(i=0;i<slen-1;i++)
8460 if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP))
8464 if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
8465 ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
8468 if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
8470 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8472 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8473 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8474 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8475 regs[i].isconst&=~(1<<hr);
8476 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8477 constmap[i][hr]=constmap[i+1][hr];
8478 regs[i+1].wasdirty&=~(1<<hr);
8479 regs[i].dirty&=~(1<<hr);
8484 if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
8486 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8488 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8489 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8490 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8491 regs[i].isconst&=~(1<<hr);
8492 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8493 constmap[i][hr]=constmap[i+1][hr];
8494 regs[i+1].wasdirty&=~(1<<hr);
8495 regs[i].dirty&=~(1<<hr);
8499 // Preload target address for load instruction (non-constant)
8500 if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
8501 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
8503 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8505 regs[i].regmap[hr]=rs1[i+1];
8506 regmap_pre[i+1][hr]=rs1[i+1];
8507 regs[i+1].regmap_entry[hr]=rs1[i+1];
8508 regs[i].isconst&=~(1<<hr);
8509 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8510 constmap[i][hr]=constmap[i+1][hr];
8511 regs[i+1].wasdirty&=~(1<<hr);
8512 regs[i].dirty&=~(1<<hr);
8516 // Load source into target register
8517 if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
8518 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
8520 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8522 regs[i].regmap[hr]=rs1[i+1];
8523 regmap_pre[i+1][hr]=rs1[i+1];
8524 regs[i+1].regmap_entry[hr]=rs1[i+1];
8525 regs[i].isconst&=~(1<<hr);
8526 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8527 constmap[i][hr]=constmap[i+1][hr];
8528 regs[i+1].wasdirty&=~(1<<hr);
8529 regs[i].dirty&=~(1<<hr);
8533 // Address for store instruction (non-constant)
8534 if(itype[i+1]==STORE||itype[i+1]==STORELR
8535 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
8536 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
8537 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
8538 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
8539 else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
8541 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8543 regs[i].regmap[hr]=rs1[i+1];
8544 regmap_pre[i+1][hr]=rs1[i+1];
8545 regs[i+1].regmap_entry[hr]=rs1[i+1];
8546 regs[i].isconst&=~(1<<hr);
8547 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8548 constmap[i][hr]=constmap[i+1][hr];
8549 regs[i+1].wasdirty&=~(1<<hr);
8550 regs[i].dirty&=~(1<<hr);
8554 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
8555 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
8557 hr=get_reg(regs[i+1].regmap,FTEMP);
8559 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8561 regs[i].regmap[hr]=rs1[i+1];
8562 regmap_pre[i+1][hr]=rs1[i+1];
8563 regs[i+1].regmap_entry[hr]=rs1[i+1];
8564 regs[i].isconst&=~(1<<hr);
8565 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8566 constmap[i][hr]=constmap[i+1][hr];
8567 regs[i+1].wasdirty&=~(1<<hr);
8568 regs[i].dirty&=~(1<<hr);
8570 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
8572 // move it to another register
8573 regs[i+1].regmap[hr]=-1;
8574 regmap_pre[i+2][hr]=-1;
8575 regs[i+1].regmap[nr]=FTEMP;
8576 regmap_pre[i+2][nr]=FTEMP;
8577 regs[i].regmap[nr]=rs1[i+1];
8578 regmap_pre[i+1][nr]=rs1[i+1];
8579 regs[i+1].regmap_entry[nr]=rs1[i+1];
8580 regs[i].isconst&=~(1<<nr);
8581 regs[i+1].isconst&=~(1<<nr);
8582 regs[i].dirty&=~(1<<nr);
8583 regs[i+1].wasdirty&=~(1<<nr);
8584 regs[i+1].dirty&=~(1<<nr);
8585 regs[i+2].wasdirty&=~(1<<nr);
8589 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
8590 if(itype[i+1]==LOAD)
8591 hr=get_reg(regs[i+1].regmap,rt1[i+1]);
8592 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
8593 hr=get_reg(regs[i+1].regmap,FTEMP);
8594 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
8595 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
8596 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
8598 if(hr>=0&®s[i].regmap[hr]<0) {
8599 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
8600 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
8601 regs[i].regmap[hr]=AGEN1+((i+1)&1);
8602 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
8603 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
8604 regs[i].isconst&=~(1<<hr);
8605 regs[i+1].wasdirty&=~(1<<hr);
8606 regs[i].dirty&=~(1<<hr);
8615 /* Pass 6 - Optimize clean/dirty state */
8616 clean_registers(0,slen-1,1);
8618 /* Pass 7 - Identify 32-bit registers */
8619 for (i=slen-1;i>=0;i--)
8621 if(itype[i]==CJUMP||itype[i]==SJUMP)
8623 // Conditional branch
8624 if((source[i]>>16)!=0x1000&&i<slen-2) {
8625 // Mark this address as a branch target since it may be called
8626 // upon return from interrupt
8632 if(itype[slen-1]==SPAN) {
8633 bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
8637 /* Debug/disassembly */
8642 for(r=1;r<=CCREG;r++) {
8643 if((unneeded_reg[i]>>r)&1) {
8644 if(r==HIREG) printf(" HI");
8645 else if(r==LOREG) printf(" LO");
8646 else printf(" r%d",r);
8650 #if defined(__i386__) || defined(__x86_64__)
8651 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
8654 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
8656 #if defined(__i386__) || defined(__x86_64__)
8658 if(needed_reg[i]&1) printf("eax ");
8659 if((needed_reg[i]>>1)&1) printf("ecx ");
8660 if((needed_reg[i]>>2)&1) printf("edx ");
8661 if((needed_reg[i]>>3)&1) printf("ebx ");
8662 if((needed_reg[i]>>5)&1) printf("ebp ");
8663 if((needed_reg[i]>>6)&1) printf("esi ");
8664 if((needed_reg[i]>>7)&1) printf("edi ");
8666 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
8668 if(regs[i].wasdirty&1) printf("eax ");
8669 if((regs[i].wasdirty>>1)&1) printf("ecx ");
8670 if((regs[i].wasdirty>>2)&1) printf("edx ");
8671 if((regs[i].wasdirty>>3)&1) printf("ebx ");
8672 if((regs[i].wasdirty>>5)&1) printf("ebp ");
8673 if((regs[i].wasdirty>>6)&1) printf("esi ");
8674 if((regs[i].wasdirty>>7)&1) printf("edi ");
8677 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
8679 if(regs[i].wasdirty&1) printf("r0 ");
8680 if((regs[i].wasdirty>>1)&1) printf("r1 ");
8681 if((regs[i].wasdirty>>2)&1) printf("r2 ");
8682 if((regs[i].wasdirty>>3)&1) printf("r3 ");
8683 if((regs[i].wasdirty>>4)&1) printf("r4 ");
8684 if((regs[i].wasdirty>>5)&1) printf("r5 ");
8685 if((regs[i].wasdirty>>6)&1) printf("r6 ");
8686 if((regs[i].wasdirty>>7)&1) printf("r7 ");
8687 if((regs[i].wasdirty>>8)&1) printf("r8 ");
8688 if((regs[i].wasdirty>>9)&1) printf("r9 ");
8689 if((regs[i].wasdirty>>10)&1) printf("r10 ");
8690 if((regs[i].wasdirty>>12)&1) printf("r12 ");
8693 disassemble_inst(i);
8694 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
8695 #if defined(__i386__) || defined(__x86_64__)
8696 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
8697 if(regs[i].dirty&1) printf("eax ");
8698 if((regs[i].dirty>>1)&1) printf("ecx ");
8699 if((regs[i].dirty>>2)&1) printf("edx ");
8700 if((regs[i].dirty>>3)&1) printf("ebx ");
8701 if((regs[i].dirty>>5)&1) printf("ebp ");
8702 if((regs[i].dirty>>6)&1) printf("esi ");
8703 if((regs[i].dirty>>7)&1) printf("edi ");
8706 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
8707 if(regs[i].dirty&1) printf("r0 ");
8708 if((regs[i].dirty>>1)&1) printf("r1 ");
8709 if((regs[i].dirty>>2)&1) printf("r2 ");
8710 if((regs[i].dirty>>3)&1) printf("r3 ");
8711 if((regs[i].dirty>>4)&1) printf("r4 ");
8712 if((regs[i].dirty>>5)&1) printf("r5 ");
8713 if((regs[i].dirty>>6)&1) printf("r6 ");
8714 if((regs[i].dirty>>7)&1) printf("r7 ");
8715 if((regs[i].dirty>>8)&1) printf("r8 ");
8716 if((regs[i].dirty>>9)&1) printf("r9 ");
8717 if((regs[i].dirty>>10)&1) printf("r10 ");
8718 if((regs[i].dirty>>12)&1) printf("r12 ");
8721 if(regs[i].isconst) {
8722 printf("constants: ");
8723 #if defined(__i386__) || defined(__x86_64__)
8724 if(regs[i].isconst&1) printf("eax=%x ",(u_int)constmap[i][0]);
8725 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(u_int)constmap[i][1]);
8726 if((regs[i].isconst>>2)&1) printf("edx=%x ",(u_int)constmap[i][2]);
8727 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(u_int)constmap[i][3]);
8728 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(u_int)constmap[i][5]);
8729 if((regs[i].isconst>>6)&1) printf("esi=%x ",(u_int)constmap[i][6]);
8730 if((regs[i].isconst>>7)&1) printf("edi=%x ",(u_int)constmap[i][7]);
8732 #if defined(__arm__) || defined(__aarch64__)
8734 for (r = 0; r < ARRAY_SIZE(constmap[i]); r++)
8735 if ((regs[i].isconst >> r) & 1)
8736 printf(" r%d=%x", r, (u_int)constmap[i][r]);
8740 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
8741 #if defined(__i386__) || defined(__x86_64__)
8742 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
8743 if(branch_regs[i].dirty&1) printf("eax ");
8744 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
8745 if((branch_regs[i].dirty>>2)&1) printf("edx ");
8746 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
8747 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
8748 if((branch_regs[i].dirty>>6)&1) printf("esi ");
8749 if((branch_regs[i].dirty>>7)&1) printf("edi ");
8752 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
8753 if(branch_regs[i].dirty&1) printf("r0 ");
8754 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
8755 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
8756 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
8757 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
8758 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
8759 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
8760 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
8761 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
8762 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
8763 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
8764 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
8770 /* Pass 8 - Assembly */
8771 linkcount=0;stubcount=0;
8772 ds=0;is_delayslot=0;
8774 void *beginning=start_block();
8779 void *instr_addr0_override = NULL;
8781 if (start == 0x80030000) {
8782 // nasty hack for the fastbios thing
8783 // override block entry to this code
8784 instr_addr0_override = out;
8785 emit_movimm(start,0);
8786 // abuse io address var as a flag that we
8787 // have already returned here once
8788 emit_readword(&address,1);
8789 emit_writeword(0,&pcaddr);
8790 emit_writeword(0,&address);
8793 emit_jeq(out + 4*2);
8794 emit_far_jump(new_dyna_leave);
8796 emit_jne(new_dyna_leave);
8801 //if(ds) printf("ds: ");
8802 disassemble_inst(i);
8804 ds=0; // Skip delay slot
8805 if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
8806 instr_addr[i] = NULL;
8808 speculate_register_values(i);
8809 #ifndef DESTRUCTIVE_WRITEBACK
8810 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
8812 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,unneeded_reg[i]);
8814 if((itype[i]==CJUMP||itype[i]==SJUMP)&&!likely[i]) {
8815 dirty_pre=branch_regs[i].dirty;
8817 dirty_pre=regs[i].dirty;
8821 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
8823 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,unneeded_reg[i]);
8824 loop_preload(regmap_pre[i],regs[i].regmap_entry);
8826 // branch target entry point
8827 instr_addr[i] = out;
8828 assem_debug("<->\n");
8829 drc_dbg_emit_do_cmp(i);
8832 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&®s[i].regmap[HOST_CCREG]!=CCREG)
8833 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty);
8834 load_regs(regs[i].regmap_entry,regs[i].regmap,rs1[i],rs2[i]);
8835 address_generation(i,®s[i],regs[i].regmap_entry);
8836 load_consts(regmap_pre[i],regs[i].regmap,i);
8837 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP)
8839 // Load the delay slot registers if necessary
8840 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i]&&(rs1[i+1]!=rt1[i]||rt1[i]==0))
8841 load_regs(regs[i].regmap_entry,regs[i].regmap,rs1[i+1],rs1[i+1]);
8842 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i]&&(rs2[i+1]!=rt1[i]||rt1[i]==0))
8843 load_regs(regs[i].regmap_entry,regs[i].regmap,rs2[i+1],rs2[i+1]);
8844 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
8845 load_regs(regs[i].regmap_entry,regs[i].regmap,INVCP,INVCP);
8849 // Preload registers for following instruction
8850 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
8851 if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
8852 load_regs(regs[i].regmap_entry,regs[i].regmap,rs1[i+1],rs1[i+1]);
8853 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
8854 if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
8855 load_regs(regs[i].regmap_entry,regs[i].regmap,rs2[i+1],rs2[i+1]);
8857 // TODO: if(is_ooo(i)) address_generation(i+1);
8859 load_regs(regs[i].regmap_entry,regs[i].regmap,CCREG,CCREG);
8860 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
8861 load_regs(regs[i].regmap_entry,regs[i].regmap,INVCP,INVCP);
8865 alu_assemble(i,®s[i]);break;
8867 imm16_assemble(i,®s[i]);break;
8869 shift_assemble(i,®s[i]);break;
8871 shiftimm_assemble(i,®s[i]);break;
8873 load_assemble(i,®s[i]);break;
8875 loadlr_assemble(i,®s[i]);break;
8877 store_assemble(i,®s[i]);break;
8879 storelr_assemble(i,®s[i]);break;
8881 cop0_assemble(i,®s[i]);break;
8883 cop1_assemble(i,®s[i]);break;
8885 c1ls_assemble(i,®s[i]);break;
8887 cop2_assemble(i,®s[i]);break;
8889 c2ls_assemble(i,®s[i]);break;
8891 c2op_assemble(i,®s[i]);break;
8893 multdiv_assemble(i,®s[i]);break;
8895 mov_assemble(i,®s[i]);break;
8897 syscall_assemble(i,®s[i]);break;
8899 hlecall_assemble(i,®s[i]);break;
8901 intcall_assemble(i,®s[i]);break;
8903 ujump_assemble(i,®s[i]);ds=1;break;
8905 rjump_assemble(i,®s[i]);ds=1;break;
8907 cjump_assemble(i,®s[i]);ds=1;break;
8909 sjump_assemble(i,®s[i]);ds=1;break;
8911 pagespan_assemble(i,®s[i]);break;
8913 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
8916 literal_pool_jumpover(256);
8919 //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
8920 // If the block did not end with an unconditional branch,
8921 // add a jump to the next instruction.
8923 if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
8924 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP);
8926 if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP) {
8927 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
8928 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
8929 emit_loadreg(CCREG,HOST_CCREG);
8930 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
8932 else if(!likely[i-2])
8934 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].dirty,start+i*4);
8935 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
8939 store_regs_bt(regs[i-2].regmap,regs[i-2].dirty,start+i*4);
8940 assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
8942 add_to_linker(out,start+i*4,0);
8949 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP);
8950 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
8951 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
8952 emit_loadreg(CCREG,HOST_CCREG);
8953 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
8954 add_to_linker(out,start+i*4,0);
8958 // TODO: delay slot stubs?
8960 for(i=0;i<stubcount;i++)
8962 switch(stubs[i].type)
8970 do_readstub(i);break;
8975 do_writestub(i);break;
8979 do_invstub(i);break;
8981 do_cop1stub(i);break;
8983 do_unalignedwritestub(i);break;
8987 if (instr_addr0_override)
8988 instr_addr[0] = instr_addr0_override;
8990 /* Pass 9 - Linker */
8991 for(i=0;i<linkcount;i++)
8993 assem_debug("%p -> %8x\n",link_addr[i].addr,link_addr[i].target);
8995 if (!link_addr[i].ext)
8998 void *addr = check_addr(link_addr[i].target);
8999 emit_extjump(link_addr[i].addr, link_addr[i].target);
9001 set_jump_target(link_addr[i].addr, addr);
9002 add_link(link_addr[i].target,stub);
9005 set_jump_target(link_addr[i].addr, stub);
9010 int target=(link_addr[i].target-start)>>2;
9011 assert(target>=0&&target<slen);
9012 assert(instr_addr[target]);
9013 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
9014 //set_jump_target_fillslot(link_addr[i].addr,instr_addr[target],link_addr[i].ext>>1);
9016 set_jump_target(link_addr[i].addr, instr_addr[target]);
9020 // External Branch Targets (jump_in)
9021 if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
9026 if(instr_addr[i]) // TODO - delay slots (=null)
9028 u_int vaddr=start+i*4;
9029 u_int page=get_page(vaddr);
9030 u_int vpage=get_vpage(vaddr);
9033 assem_debug("%p (%d) <- %8x\n",instr_addr[i],i,start+i*4);
9034 assem_debug("jump_in: %x\n",start+i*4);
9035 ll_add(jump_dirty+vpage,vaddr,out);
9036 void *entry_point = do_dirty_stub(i);
9037 ll_add_flags(jump_in+page,vaddr,state_rflags,entry_point);
9038 // If there was an existing entry in the hash table,
9039 // replace it with the new address.
9040 // Don't add new entries. We'll insert the
9041 // ones that actually get used in check_addr().
9042 struct ht_entry *ht_bin = hash_table_get(vaddr);
9043 if (ht_bin->vaddr[0] == vaddr)
9044 ht_bin->tcaddr[0] = entry_point;
9045 if (ht_bin->vaddr[1] == vaddr)
9046 ht_bin->tcaddr[1] = entry_point;
9051 // Write out the literal pool if necessary
9053 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
9055 if(((u_int)out)&7) emit_addnop(13);
9057 assert(out - (u_char *)beginning < MAX_OUTPUT_BLOCK_SIZE);
9058 //printf("shadow buffer: %p-%p\n",copy,(u_char *)copy+slen*4);
9059 memcpy(copy,source,slen*4);
9062 end_block(beginning);
9064 // If we're within 256K of the end of the buffer,
9065 // start over from the beginning. (Is 256K enough?)
9066 if (out > ndrc->translation_cache + sizeof(ndrc->translation_cache) - MAX_OUTPUT_BLOCK_SIZE)
9067 out = ndrc->translation_cache;
9069 // Trap writes to any of the pages we compiled
9070 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
9073 inv_code_start=inv_code_end=~0;
9075 // for PCSX we need to mark all mirrors too
9076 if(get_page(start)<(RAM_SIZE>>12))
9077 for(i=start>>12;i<=(start+slen*4)>>12;i++)
9078 invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]=
9079 invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]=
9080 invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0;
9082 /* Pass 10 - Free memory by expiring oldest blocks */
9084 int end=(((out-ndrc->translation_cache)>>(TARGET_SIZE_2-16))+16384)&65535;
9087 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
9088 uintptr_t base=(uintptr_t)ndrc->translation_cache+((expirep>>13)<<shift); // Base address of this block
9089 inv_debug("EXP: Phase %d\n",expirep);
9090 switch((expirep>>11)&3)
9093 // Clear jump_in and jump_dirty
9094 ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
9095 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
9096 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
9097 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
9101 ll_kill_pointers(jump_out[expirep&2047],base,shift);
9102 ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
9107 struct ht_entry *ht_bin = &hash_table[((expirep&2047)<<5)+i];
9108 if (((uintptr_t)ht_bin->tcaddr[1]>>shift) == (base>>shift) ||
9109 (((uintptr_t)ht_bin->tcaddr[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
9110 inv_debug("EXP: Remove hash %x -> %p\n",ht_bin->vaddr[1],ht_bin->tcaddr[1]);
9111 ht_bin->vaddr[1] = -1;
9112 ht_bin->tcaddr[1] = NULL;
9114 if (((uintptr_t)ht_bin->tcaddr[0]>>shift) == (base>>shift) ||
9115 (((uintptr_t)ht_bin->tcaddr[0]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
9116 inv_debug("EXP: Remove hash %x -> %p\n",ht_bin->vaddr[0],ht_bin->tcaddr[0]);
9117 ht_bin->vaddr[0] = ht_bin->vaddr[1];
9118 ht_bin->tcaddr[0] = ht_bin->tcaddr[1];
9119 ht_bin->vaddr[1] = -1;
9120 ht_bin->tcaddr[1] = NULL;
9126 if((expirep&2047)==0)
9128 ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
9129 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
9132 expirep=(expirep+1)&65535;
9137 // vim:shiftwidth=2:expandtab