1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2010 Ari64 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include <stdint.h> //include for uint64_t
25 #include "emu_if.h" //emulator interface
30 #include "assem_x86.h"
33 #include "assem_x64.h"
36 #include "assem_arm.h"
40 #define MAX_OUTPUT_BLOCK_SIZE 262144
41 #define CLOCK_DIVIDER 2
45 signed char regmap_entry[HOST_REGS];
46 signed char regmap[HOST_REGS];
55 uint64_t constmap[HOST_REGS];
63 struct ll_entry *next;
69 char insn[MAXBLOCK][10];
70 u_char itype[MAXBLOCK];
71 u_char opcode[MAXBLOCK];
72 u_char opcode2[MAXBLOCK];
80 u_char dep1[MAXBLOCK];
81 u_char dep2[MAXBLOCK];
85 char likely[MAXBLOCK];
88 uint64_t unneeded_reg[MAXBLOCK];
89 uint64_t unneeded_reg_upper[MAXBLOCK];
90 uint64_t branch_unneeded_reg[MAXBLOCK];
91 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
92 uint64_t p32[MAXBLOCK];
93 uint64_t pr32[MAXBLOCK];
94 signed char regmap_pre[MAXBLOCK][HOST_REGS];
95 signed char regmap[MAXBLOCK][HOST_REGS];
96 signed char regmap_entry[MAXBLOCK][HOST_REGS];
97 uint64_t constmap[MAXBLOCK][HOST_REGS];
98 struct regstat regs[MAXBLOCK];
99 struct regstat branch_regs[MAXBLOCK];
100 signed char minimum_free_regs[MAXBLOCK];
101 u_int needed_reg[MAXBLOCK];
102 uint64_t requires_32bit[MAXBLOCK];
103 u_int wont_dirty[MAXBLOCK];
104 u_int will_dirty[MAXBLOCK];
107 u_int instr_addr[MAXBLOCK];
108 u_int link_addr[MAXBLOCK][3];
110 u_int stubs[MAXBLOCK*3][8];
112 u_int literals[1024][2];
117 struct ll_entry *jump_in[4096];
118 struct ll_entry *jump_out[4096];
119 struct ll_entry *jump_dirty[4096];
120 u_int hash_table[65536][4] __attribute__((aligned(16)));
121 char shadow[1048576] __attribute__((aligned(16)));
127 static const u_int using_tlb=0;
129 u_int stop_after_jal;
130 extern u_char restore_candidate[512];
131 extern int cycle_count;
133 /* registers that may be allocated */
135 #define HIREG 32 // hi
136 #define LOREG 33 // lo
137 #define FSREG 34 // FPU status (FCSR)
138 #define CSREG 35 // Coprocessor status
139 #define CCREG 36 // Cycle count
140 #define INVCP 37 // Pointer to invalid_code
141 #define MMREG 38 // Pointer to memory_map
142 #define ROREG 39 // ram offset (if rdram!=0x80000000)
144 #define FTEMP 40 // FPU temporary register
145 #define PTEMP 41 // Prefetch temporary register
146 #define TLREG 42 // TLB mapping offset
147 #define RHASH 43 // Return address hash
148 #define RHTBL 44 // Return address hash table address
149 #define RTEMP 45 // JR/JALR address register
151 #define AGEN1 46 // Address generation temporary register
152 #define AGEN2 47 // Address generation temporary register
153 #define MGEN1 48 // Maptable address generation temporary register
154 #define MGEN2 49 // Maptable address generation temporary register
155 #define BTREG 50 // Branch target temporary register
157 /* instruction types */
158 #define NOP 0 // No operation
159 #define LOAD 1 // Load
160 #define STORE 2 // Store
161 #define LOADLR 3 // Unaligned load
162 #define STORELR 4 // Unaligned store
163 #define MOV 5 // Move
164 #define ALU 6 // Arithmetic/logic
165 #define MULTDIV 7 // Multiply/divide
166 #define SHIFT 8 // Shift by register
167 #define SHIFTIMM 9// Shift by immediate
168 #define IMM16 10 // 16-bit immediate
169 #define RJUMP 11 // Unconditional jump to register
170 #define UJUMP 12 // Unconditional jump
171 #define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
172 #define SJUMP 14 // Conditional branch (regimm format)
173 #define COP0 15 // Coprocessor 0
174 #define COP1 16 // Coprocessor 1
175 #define C1LS 17 // Coprocessor 1 load/store
176 #define FJUMP 18 // Conditional branch (floating point)
177 #define FLOAT 19 // Floating point unit
178 #define FCONV 20 // Convert integer to float
179 #define FCOMP 21 // Floating point compare (sets FSREG)
180 #define SYSCALL 22// SYSCALL
181 #define OTHER 23 // Other
182 #define SPAN 24 // Branch/delay slot spans 2 pages
183 #define NI 25 // Not implemented
184 #define HLECALL 26// PCSX fake opcodes for HLE
185 #define COP2 27 // Coprocessor 2 move
186 #define C2LS 28 // Coprocessor 2 load/store
187 #define C2OP 29 // Coprocessor 2 operation
188 #define INTCALL 30// Call interpreter to handle rare corner cases
197 #define LOADBU_STUB 7
198 #define LOADHU_STUB 8
199 #define STOREB_STUB 9
200 #define STOREH_STUB 10
201 #define STOREW_STUB 11
202 #define STORED_STUB 12
203 #define STORELR_STUB 13
204 #define INVCODE_STUB 14
212 int new_recompile_block(int addr);
213 void *get_addr_ht(u_int vaddr);
214 void invalidate_block(u_int block);
215 void invalidate_addr(u_int addr);
216 void remove_hash(int vaddr);
219 void dyna_linker_ds();
221 void verify_code_vm();
222 void verify_code_ds();
225 void fp_exception_ds();
227 void jump_syscall_hle();
231 void new_dyna_leave();
236 void read_nomem_new();
237 void read_nomemb_new();
238 void read_nomemh_new();
239 void read_nomemd_new();
240 void write_nomem_new();
241 void write_nomemb_new();
242 void write_nomemh_new();
243 void write_nomemd_new();
244 void write_rdram_new();
245 void write_rdramb_new();
246 void write_rdramh_new();
247 void write_rdramd_new();
248 extern u_int memory_map[1048576];
250 // Needed by assembler
251 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
252 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
253 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
254 void load_all_regs(signed char i_regmap[]);
255 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
256 void load_regs_entry(int t);
257 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
261 //#define DEBUG_CYCLE_COUNT 1
264 //#define assem_debug printf
265 //#define inv_debug printf
266 #define assem_debug nullf
267 #define inv_debug nullf
269 static void tlb_hacks()
273 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
277 switch (ROM_HEADER->Country_code&0xFF)
289 // Unknown country code
293 u_int rom_addr=(u_int)rom;
295 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
296 // in the lower 4G of memory to use this hack. Copy it if necessary.
297 if((void *)rom>(void *)0xffffffff) {
298 munmap(ROM_COPY, 67108864);
299 if(mmap(ROM_COPY, 12582912,
300 PROT_READ | PROT_WRITE,
301 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
302 -1, 0) <= 0) {printf("mmap() failed\n");}
303 memcpy(ROM_COPY,rom,12582912);
304 rom_addr=(u_int)ROM_COPY;
308 for(n=0x7F000;n<0x80000;n++) {
309 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
316 static u_int get_page(u_int vaddr)
319 u_int page=(vaddr^0x80000000)>>12;
321 u_int page=vaddr&~0xe0000000;
322 if (page < 0x1000000)
323 page &= ~0x0e00000; // RAM mirrors
327 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
329 if(page>2048) page=2048+(page&2047);
333 static u_int get_vpage(u_int vaddr)
335 u_int vpage=(vaddr^0x80000000)>>12;
337 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
339 if(vpage>2048) vpage=2048+(vpage&2047);
343 // Get address from virtual address
344 // This is called from the recompiled JR/JALR instructions
345 void *get_addr(u_int vaddr)
347 u_int page=get_page(vaddr);
348 u_int vpage=get_vpage(vaddr);
349 struct ll_entry *head;
350 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
353 if(head->vaddr==vaddr&&head->reg32==0) {
354 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
355 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
358 ht_bin[1]=(int)head->addr;
364 head=jump_dirty[vpage];
366 if(head->vaddr==vaddr&&head->reg32==0) {
367 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
368 // Don't restore blocks which are about to expire from the cache
369 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
370 if(verify_dirty(head->addr)) {
371 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
372 invalid_code[vaddr>>12]=0;
373 memory_map[vaddr>>12]|=0x40000000;
376 if(tlb_LUT_r[vaddr>>12]) {
377 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
378 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
381 restore_candidate[vpage>>3]|=1<<(vpage&7);
383 else restore_candidate[page>>3]|=1<<(page&7);
384 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
385 if(ht_bin[0]==vaddr) {
386 ht_bin[1]=(int)head->addr; // Replace existing entry
392 ht_bin[1]=(int)head->addr;
400 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
401 int r=new_recompile_block(vaddr);
402 if(r==0) return get_addr(vaddr);
403 // Execute in unmapped page, generate pagefault execption
405 Cause=(vaddr<<31)|0x8;
406 EPC=(vaddr&1)?vaddr-5:vaddr;
408 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
409 EntryHi=BadVAddr&0xFFFFE000;
410 return get_addr_ht(0x80000000);
412 // Look up address in hash table first
413 void *get_addr_ht(u_int vaddr)
415 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
416 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
417 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
418 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
419 return get_addr(vaddr);
422 void *get_addr_32(u_int vaddr,u_int flags)
425 return get_addr(vaddr);
427 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
428 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
429 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
430 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
431 u_int page=get_page(vaddr);
432 u_int vpage=get_vpage(vaddr);
433 struct ll_entry *head;
436 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
437 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
439 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
441 ht_bin[1]=(int)head->addr;
443 }else if(ht_bin[2]==-1) {
444 ht_bin[3]=(int)head->addr;
447 //ht_bin[3]=ht_bin[1];
448 //ht_bin[2]=ht_bin[0];
449 //ht_bin[1]=(int)head->addr;
456 head=jump_dirty[vpage];
458 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
459 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
460 // Don't restore blocks which are about to expire from the cache
461 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
462 if(verify_dirty(head->addr)) {
463 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
464 invalid_code[vaddr>>12]=0;
465 memory_map[vaddr>>12]|=0x40000000;
468 if(tlb_LUT_r[vaddr>>12]) {
469 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
470 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
473 restore_candidate[vpage>>3]|=1<<(vpage&7);
475 else restore_candidate[page>>3]|=1<<(page&7);
477 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
479 ht_bin[1]=(int)head->addr;
481 }else if(ht_bin[2]==-1) {
482 ht_bin[3]=(int)head->addr;
485 //ht_bin[3]=ht_bin[1];
486 //ht_bin[2]=ht_bin[0];
487 //ht_bin[1]=(int)head->addr;
495 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
496 int r=new_recompile_block(vaddr);
497 if(r==0) return get_addr(vaddr);
498 // Execute in unmapped page, generate pagefault execption
500 Cause=(vaddr<<31)|0x8;
501 EPC=(vaddr&1)?vaddr-5:vaddr;
503 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
504 EntryHi=BadVAddr&0xFFFFE000;
505 return get_addr_ht(0x80000000);
509 void clear_all_regs(signed char regmap[])
512 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
515 signed char get_reg(signed char regmap[],int r)
518 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map[hr]==r) return hr;
522 // Find a register that is available for two consecutive cycles
523 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
526 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr;
530 int count_free_regs(signed char regmap[])
534 for(hr=0;hr<HOST_REGS;hr++)
536 if(hr!=EXCLUDE_REG) {
537 if(regmap[hr]<0) count++;
543 void dirty_reg(struct regstat *cur,signed char reg)
547 for (hr=0;hr<HOST_REGS;hr++) {
548 if((cur->regmap[hr]&63)==reg) {
554 // If we dirty the lower half of a 64 bit register which is now being
555 // sign-extended, we need to dump the upper half.
556 // Note: Do this only after completion of the instruction, because
557 // some instructions may need to read the full 64-bit value even if
558 // overwriting it (eg SLTI, DSRA32).
559 static void flush_dirty_uppers(struct regstat *cur)
562 for (hr=0;hr<HOST_REGS;hr++) {
563 if((cur->dirty>>hr)&1) {
566 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
571 void set_const(struct regstat *cur,signed char reg,uint64_t value)
575 for (hr=0;hr<HOST_REGS;hr++) {
576 if(cur->regmap[hr]==reg) {
578 cur->constmap[hr]=value;
580 else if((cur->regmap[hr]^64)==reg) {
582 cur->constmap[hr]=value>>32;
587 void clear_const(struct regstat *cur,signed char reg)
591 for (hr=0;hr<HOST_REGS;hr++) {
592 if((cur->regmap[hr]&63)==reg) {
593 cur->isconst&=~(1<<hr);
598 int is_const(struct regstat *cur,signed char reg)
602 for (hr=0;hr<HOST_REGS;hr++) {
603 if((cur->regmap[hr]&63)==reg) {
604 return (cur->isconst>>hr)&1;
609 uint64_t get_const(struct regstat *cur,signed char reg)
613 for (hr=0;hr<HOST_REGS;hr++) {
614 if(cur->regmap[hr]==reg) {
615 return cur->constmap[hr];
618 printf("Unknown constant in r%d\n",reg);
622 // Least soon needed registers
623 // Look at the next ten instructions and see which registers
624 // will be used. Try not to reallocate these.
625 void lsn(u_char hsn[], int i, int *preferred_reg)
635 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
637 // Don't go past an unconditonal jump
644 if(rs1[i+j]) hsn[rs1[i+j]]=j;
645 if(rs2[i+j]) hsn[rs2[i+j]]=j;
646 if(rt1[i+j]) hsn[rt1[i+j]]=j;
647 if(rt2[i+j]) hsn[rt2[i+j]]=j;
648 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
649 // Stores can allocate zero
653 // On some architectures stores need invc_ptr
654 #if defined(HOST_IMM8)
655 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
659 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
667 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
669 // Follow first branch
670 int t=(ba[i+b]-start)>>2;
671 j=7-b;if(t+j>=slen) j=slen-t-1;
674 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
675 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
676 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
677 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
680 // TODO: preferred register based on backward branch
682 // Delay slot should preferably not overwrite branch conditions or cycle count
683 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
684 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
685 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
691 // Coprocessor load/store needs FTEMP, even if not declared
692 if(itype[i]==C1LS||itype[i]==C2LS) {
695 // Load L/R also uses FTEMP as a temporary register
696 if(itype[i]==LOADLR) {
699 // Also SWL/SWR/SDL/SDR
700 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
703 // Don't remove the TLB registers either
704 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
707 // Don't remove the miniht registers
708 if(itype[i]==UJUMP||itype[i]==RJUMP)
715 // We only want to allocate registers if we're going to use them again soon
716 int needed_again(int r, int i)
722 u_char hsn[MAXREG+1];
725 memset(hsn,10,sizeof(hsn));
726 lsn(hsn,i,&preferred_reg);
728 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
730 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
731 return 0; // Don't need any registers if exiting the block
739 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
741 // Don't go past an unconditonal jump
745 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
752 if(rs1[i+j]==r) rn=j;
753 if(rs2[i+j]==r) rn=j;
754 if((unneeded_reg[i+j]>>r)&1) rn=10;
755 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
763 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
765 // Follow first branch
767 int t=(ba[i+b]-start)>>2;
768 j=7-b;if(t+j>=slen) j=slen-t-1;
771 if(!((unneeded_reg[t+j]>>r)&1)) {
772 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
773 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
779 for(hr=0;hr<HOST_REGS;hr++) {
780 if(hr!=EXCLUDE_REG) {
781 if(rn<hsn[hr]) return 1;
787 // Try to match register allocations at the end of a loop with those
789 int loop_reg(int i, int r, int hr)
798 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
800 // Don't go past an unconditonal jump
807 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
812 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
813 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
814 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
816 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
818 int t=(ba[i+k]-start)>>2;
819 int reg=get_reg(regs[t].regmap_entry,r);
820 if(reg>=0) return reg;
821 //reg=get_reg(regs[t+1].regmap_entry,r);
822 //if(reg>=0) return reg;
830 // Allocate every register, preserving source/target regs
831 void alloc_all(struct regstat *cur,int i)
835 for(hr=0;hr<HOST_REGS;hr++) {
836 if(hr!=EXCLUDE_REG) {
837 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
838 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
841 cur->dirty&=~(1<<hr);
844 if((cur->regmap[hr]&63)==0)
847 cur->dirty&=~(1<<hr);
854 void div64(int64_t dividend,int64_t divisor)
858 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
859 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
861 void divu64(uint64_t dividend,uint64_t divisor)
865 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
866 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
869 void mult64(uint64_t m1,uint64_t m2)
871 unsigned long long int op1, op2, op3, op4;
872 unsigned long long int result1, result2, result3, result4;
873 unsigned long long int temp1, temp2, temp3, temp4;
889 op1 = op2 & 0xFFFFFFFF;
890 op2 = (op2 >> 32) & 0xFFFFFFFF;
891 op3 = op4 & 0xFFFFFFFF;
892 op4 = (op4 >> 32) & 0xFFFFFFFF;
895 temp2 = (temp1 >> 32) + op1 * op4;
897 temp4 = (temp3 >> 32) + op2 * op4;
899 result1 = temp1 & 0xFFFFFFFF;
900 result2 = temp2 + (temp3 & 0xFFFFFFFF);
901 result3 = (result2 >> 32) + temp4;
902 result4 = (result3 >> 32);
904 lo = result1 | (result2 << 32);
905 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
914 void multu64(uint64_t m1,uint64_t m2)
916 unsigned long long int op1, op2, op3, op4;
917 unsigned long long int result1, result2, result3, result4;
918 unsigned long long int temp1, temp2, temp3, temp4;
920 op1 = m1 & 0xFFFFFFFF;
921 op2 = (m1 >> 32) & 0xFFFFFFFF;
922 op3 = m2 & 0xFFFFFFFF;
923 op4 = (m2 >> 32) & 0xFFFFFFFF;
926 temp2 = (temp1 >> 32) + op1 * op4;
928 temp4 = (temp3 >> 32) + op2 * op4;
930 result1 = temp1 & 0xFFFFFFFF;
931 result2 = temp2 + (temp3 & 0xFFFFFFFF);
932 result3 = (result2 >> 32) + temp4;
933 result4 = (result3 >> 32);
935 lo = result1 | (result2 << 32);
936 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
938 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
939 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
942 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
950 else original=loaded;
953 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
956 original>>=64-(bits^56);
957 original<<=64-(bits^56);
961 else original=loaded;
966 #include "assem_x86.c"
969 #include "assem_x64.c"
972 #include "assem_arm.c"
975 // Add virtual address mapping to linked list
976 void ll_add(struct ll_entry **head,int vaddr,void *addr)
978 struct ll_entry *new_entry;
979 new_entry=malloc(sizeof(struct ll_entry));
980 assert(new_entry!=NULL);
981 new_entry->vaddr=vaddr;
983 new_entry->addr=addr;
984 new_entry->next=*head;
988 // Add virtual address mapping for 32-bit compiled block
989 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
991 ll_add(head,vaddr,addr);
993 (*head)->reg32=reg32;
997 // Check if an address is already compiled
998 // but don't return addresses which are about to expire from the cache
999 void *check_addr(u_int vaddr)
1001 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
1002 if(ht_bin[0]==vaddr) {
1003 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1004 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
1006 if(ht_bin[2]==vaddr) {
1007 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1008 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1010 u_int page=get_page(vaddr);
1011 struct ll_entry *head;
1014 if(head->vaddr==vaddr&&head->reg32==0) {
1015 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1016 // Update existing entry with current address
1017 if(ht_bin[0]==vaddr) {
1018 ht_bin[1]=(int)head->addr;
1021 if(ht_bin[2]==vaddr) {
1022 ht_bin[3]=(int)head->addr;
1025 // Insert into hash table with low priority.
1026 // Don't evict existing entries, as they are probably
1027 // addresses that are being accessed frequently.
1029 ht_bin[1]=(int)head->addr;
1031 }else if(ht_bin[2]==-1) {
1032 ht_bin[3]=(int)head->addr;
1043 void remove_hash(int vaddr)
1045 //printf("remove hash: %x\n",vaddr);
1046 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1047 if(ht_bin[2]==vaddr) {
1048 ht_bin[2]=ht_bin[3]=-1;
1050 if(ht_bin[0]==vaddr) {
1051 ht_bin[0]=ht_bin[2];
1052 ht_bin[1]=ht_bin[3];
1053 ht_bin[2]=ht_bin[3]=-1;
1057 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1059 struct ll_entry *next;
1061 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1062 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1064 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1065 remove_hash((*head)->vaddr);
1072 head=&((*head)->next);
1077 // Remove all entries from linked list
1078 void ll_clear(struct ll_entry **head)
1080 struct ll_entry *cur;
1081 struct ll_entry *next;
1092 // Dereference the pointers and remove if it matches
1093 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1096 int ptr=get_pointer(head->addr);
1097 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1098 if(((ptr>>shift)==(addr>>shift)) ||
1099 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1101 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1102 u_int host_addr=(u_int)kill_pointer(head->addr);
1104 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1111 // This is called when we write to a compiled block (see do_invstub)
1112 void invalidate_page(u_int page)
1114 struct ll_entry *head;
1115 struct ll_entry *next;
1119 inv_debug("INVALIDATE: %x\n",head->vaddr);
1120 remove_hash(head->vaddr);
1125 head=jump_out[page];
1128 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1129 u_int host_addr=(u_int)kill_pointer(head->addr);
1131 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1138 void invalidate_block(u_int block)
1140 u_int page=get_page(block<<12);
1141 u_int vpage=get_vpage(block<<12);
1142 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1143 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1146 struct ll_entry *head;
1147 head=jump_dirty[vpage];
1148 //printf("page=%d vpage=%d\n",page,vpage);
1151 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1152 get_bounds((int)head->addr,&start,&end);
1153 //printf("start: %x end: %x\n",start,end);
1154 if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
1155 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1156 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1157 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1161 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1162 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1163 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1164 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1171 //printf("first=%d last=%d\n",first,last);
1172 invalidate_page(page);
1173 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1174 assert(last<page+5);
1175 // Invalidate the adjacent pages if a block crosses a 4K boundary
1177 invalidate_page(first);
1180 for(first=page+1;first<last;first++) {
1181 invalidate_page(first);
1187 // Don't trap writes
1188 invalid_code[block]=1;
1190 // If there is a valid TLB entry for this page, remove write protect
1191 if(tlb_LUT_w[block]) {
1192 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1193 // CHECK: Is this right?
1194 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1195 u_int real_block=tlb_LUT_w[block]>>12;
1196 invalid_code[real_block]=1;
1197 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1199 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1203 memset(mini_ht,-1,sizeof(mini_ht));
1206 void invalidate_addr(u_int addr)
1208 invalidate_block(addr>>12);
1210 // This is called when loading a save state.
1211 // Anything could have changed, so invalidate everything.
1212 void invalidate_all_pages()
1215 for(page=0;page<4096;page++)
1216 invalidate_page(page);
1217 for(page=0;page<1048576;page++)
1218 if(!invalid_code[page]) {
1219 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1220 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1223 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1226 memset(mini_ht,-1,sizeof(mini_ht));
1230 for(page=0;page<0x100000;page++) {
1231 if(tlb_LUT_r[page]) {
1232 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1233 if(!tlb_LUT_w[page]||!invalid_code[page])
1234 memory_map[page]|=0x40000000; // Write protect
1236 else memory_map[page]=-1;
1237 if(page==0x80000) page=0xC0000;
1243 // Add an entry to jump_out after making a link
1244 void add_link(u_int vaddr,void *src)
1246 u_int page=get_page(vaddr);
1247 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1248 ll_add(jump_out+page,vaddr,src);
1249 //int ptr=get_pointer(src);
1250 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1253 // If a code block was found to be unmodified (bit was set in
1254 // restore_candidate) and it remains unmodified (bit is clear
1255 // in invalid_code) then move the entries for that 4K page from
1256 // the dirty list to the clean list.
1257 void clean_blocks(u_int page)
1259 struct ll_entry *head;
1260 inv_debug("INV: clean_blocks page=%d\n",page);
1261 head=jump_dirty[page];
1263 if(!invalid_code[head->vaddr>>12]) {
1264 // Don't restore blocks which are about to expire from the cache
1265 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1267 if(verify_dirty((int)head->addr)) {
1268 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1271 get_bounds((int)head->addr,&start,&end);
1272 if(start-(u_int)rdram<RAM_SIZE) {
1273 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1274 inv|=invalid_code[i];
1277 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1278 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1279 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1280 if(addr<start||addr>=end) inv=1;
1282 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1286 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1287 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1290 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1292 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1293 //printf("page=%x, addr=%x\n",page,head->vaddr);
1294 //assert(head->vaddr>>12==(page|0x80000));
1295 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1296 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1298 if(ht_bin[0]==head->vaddr) {
1299 ht_bin[1]=(int)clean_addr; // Replace existing entry
1301 if(ht_bin[2]==head->vaddr) {
1302 ht_bin[3]=(int)clean_addr; // Replace existing entry
1315 void mov_alloc(struct regstat *current,int i)
1317 // Note: Don't need to actually alloc the source registers
1318 if((~current->is32>>rs1[i])&1) {
1319 //alloc_reg64(current,i,rs1[i]);
1320 alloc_reg64(current,i,rt1[i]);
1321 current->is32&=~(1LL<<rt1[i]);
1323 //alloc_reg(current,i,rs1[i]);
1324 alloc_reg(current,i,rt1[i]);
1325 current->is32|=(1LL<<rt1[i]);
1327 clear_const(current,rs1[i]);
1328 clear_const(current,rt1[i]);
1329 dirty_reg(current,rt1[i]);
1332 void shiftimm_alloc(struct regstat *current,int i)
1334 clear_const(current,rs1[i]);
1335 clear_const(current,rt1[i]);
1336 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1339 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1341 alloc_reg(current,i,rt1[i]);
1342 current->is32|=1LL<<rt1[i];
1343 dirty_reg(current,rt1[i]);
1346 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1349 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1350 alloc_reg64(current,i,rt1[i]);
1351 current->is32&=~(1LL<<rt1[i]);
1352 dirty_reg(current,rt1[i]);
1355 if(opcode2[i]==0x3c) // DSLL32
1358 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1359 alloc_reg64(current,i,rt1[i]);
1360 current->is32&=~(1LL<<rt1[i]);
1361 dirty_reg(current,rt1[i]);
1364 if(opcode2[i]==0x3e) // DSRL32
1367 alloc_reg64(current,i,rs1[i]);
1369 alloc_reg64(current,i,rt1[i]);
1370 current->is32&=~(1LL<<rt1[i]);
1372 alloc_reg(current,i,rt1[i]);
1373 current->is32|=1LL<<rt1[i];
1375 dirty_reg(current,rt1[i]);
1378 if(opcode2[i]==0x3f) // DSRA32
1381 alloc_reg64(current,i,rs1[i]);
1382 alloc_reg(current,i,rt1[i]);
1383 current->is32|=1LL<<rt1[i];
1384 dirty_reg(current,rt1[i]);
1389 void shift_alloc(struct regstat *current,int i)
1392 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1394 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1395 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1396 alloc_reg(current,i,rt1[i]);
1397 if(rt1[i]==rs2[i]) {
1398 alloc_reg_temp(current,i,-1);
1399 minimum_free_regs[i]=1;
1401 current->is32|=1LL<<rt1[i];
1402 } else { // DSLLV/DSRLV/DSRAV
1403 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1404 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1405 alloc_reg64(current,i,rt1[i]);
1406 current->is32&=~(1LL<<rt1[i]);
1407 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1409 alloc_reg_temp(current,i,-1);
1410 minimum_free_regs[i]=1;
1413 clear_const(current,rs1[i]);
1414 clear_const(current,rs2[i]);
1415 clear_const(current,rt1[i]);
1416 dirty_reg(current,rt1[i]);
1420 void alu_alloc(struct regstat *current,int i)
1422 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1424 if(rs1[i]&&rs2[i]) {
1425 alloc_reg(current,i,rs1[i]);
1426 alloc_reg(current,i,rs2[i]);
1429 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1430 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1432 alloc_reg(current,i,rt1[i]);
1434 current->is32|=1LL<<rt1[i];
1436 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1438 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1440 alloc_reg64(current,i,rs1[i]);
1441 alloc_reg64(current,i,rs2[i]);
1442 alloc_reg(current,i,rt1[i]);
1444 alloc_reg(current,i,rs1[i]);
1445 alloc_reg(current,i,rs2[i]);
1446 alloc_reg(current,i,rt1[i]);
1449 current->is32|=1LL<<rt1[i];
1451 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1453 if(rs1[i]&&rs2[i]) {
1454 alloc_reg(current,i,rs1[i]);
1455 alloc_reg(current,i,rs2[i]);
1459 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1460 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1462 alloc_reg(current,i,rt1[i]);
1463 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1465 if(!((current->uu>>rt1[i])&1)) {
1466 alloc_reg64(current,i,rt1[i]);
1468 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1469 if(rs1[i]&&rs2[i]) {
1470 alloc_reg64(current,i,rs1[i]);
1471 alloc_reg64(current,i,rs2[i]);
1475 // Is is really worth it to keep 64-bit values in registers?
1477 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1478 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1482 current->is32&=~(1LL<<rt1[i]);
1484 current->is32|=1LL<<rt1[i];
1488 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1490 if(rs1[i]&&rs2[i]) {
1491 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1492 alloc_reg64(current,i,rs1[i]);
1493 alloc_reg64(current,i,rs2[i]);
1494 alloc_reg64(current,i,rt1[i]);
1496 alloc_reg(current,i,rs1[i]);
1497 alloc_reg(current,i,rs2[i]);
1498 alloc_reg(current,i,rt1[i]);
1502 alloc_reg(current,i,rt1[i]);
1503 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1504 // DADD used as move, or zeroing
1505 // If we have a 64-bit source, then make the target 64 bits too
1506 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1507 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1508 alloc_reg64(current,i,rt1[i]);
1509 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1510 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1511 alloc_reg64(current,i,rt1[i]);
1513 if(opcode2[i]>=0x2e&&rs2[i]) {
1514 // DSUB used as negation - 64-bit result
1515 // If we have a 32-bit register, extend it to 64 bits
1516 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1517 alloc_reg64(current,i,rt1[i]);
1521 if(rs1[i]&&rs2[i]) {
1522 current->is32&=~(1LL<<rt1[i]);
1524 current->is32&=~(1LL<<rt1[i]);
1525 if((current->is32>>rs1[i])&1)
1526 current->is32|=1LL<<rt1[i];
1528 current->is32&=~(1LL<<rt1[i]);
1529 if((current->is32>>rs2[i])&1)
1530 current->is32|=1LL<<rt1[i];
1532 current->is32|=1LL<<rt1[i];
1536 clear_const(current,rs1[i]);
1537 clear_const(current,rs2[i]);
1538 clear_const(current,rt1[i]);
1539 dirty_reg(current,rt1[i]);
1542 void imm16_alloc(struct regstat *current,int i)
1544 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1546 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1547 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1548 current->is32&=~(1LL<<rt1[i]);
1549 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1550 // TODO: Could preserve the 32-bit flag if the immediate is zero
1551 alloc_reg64(current,i,rt1[i]);
1552 alloc_reg64(current,i,rs1[i]);
1554 clear_const(current,rs1[i]);
1555 clear_const(current,rt1[i]);
1557 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1558 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1559 current->is32|=1LL<<rt1[i];
1560 clear_const(current,rs1[i]);
1561 clear_const(current,rt1[i]);
1563 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1564 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1565 if(rs1[i]!=rt1[i]) {
1566 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1567 alloc_reg64(current,i,rt1[i]);
1568 current->is32&=~(1LL<<rt1[i]);
1571 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1572 if(is_const(current,rs1[i])) {
1573 int v=get_const(current,rs1[i]);
1574 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1575 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1576 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1578 else clear_const(current,rt1[i]);
1580 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1581 if(is_const(current,rs1[i])) {
1582 int v=get_const(current,rs1[i]);
1583 set_const(current,rt1[i],v+imm[i]);
1585 else clear_const(current,rt1[i]);
1586 current->is32|=1LL<<rt1[i];
1589 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1590 current->is32|=1LL<<rt1[i];
1592 dirty_reg(current,rt1[i]);
1595 void load_alloc(struct regstat *current,int i)
1597 clear_const(current,rt1[i]);
1598 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1599 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1600 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1602 alloc_reg(current,i,rt1[i]);
1603 if(get_reg(current->regmap,rt1[i])<0) {
1604 // dummy load, but we still need a register to calculate the address
1605 alloc_reg_temp(current,i,-1);
1606 minimum_free_regs[i]=1;
1608 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1610 current->is32&=~(1LL<<rt1[i]);
1611 alloc_reg64(current,i,rt1[i]);
1613 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1615 current->is32&=~(1LL<<rt1[i]);
1616 alloc_reg64(current,i,rt1[i]);
1617 alloc_all(current,i);
1618 alloc_reg64(current,i,FTEMP);
1619 minimum_free_regs[i]=HOST_REGS;
1621 else current->is32|=1LL<<rt1[i];
1622 dirty_reg(current,rt1[i]);
1623 // If using TLB, need a register for pointer to the mapping table
1624 if(using_tlb) alloc_reg(current,i,TLREG);
1625 // LWL/LWR need a temporary register for the old value
1626 if(opcode[i]==0x22||opcode[i]==0x26)
1628 alloc_reg(current,i,FTEMP);
1629 alloc_reg_temp(current,i,-1);
1630 minimum_free_regs[i]=1;
1635 // Load to r0 (dummy load)
1636 // but we still need a register to calculate the address
1637 if(opcode[i]==0x22||opcode[i]==0x26)
1639 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1641 alloc_reg_temp(current,i,-1);
1642 minimum_free_regs[i]=1;
1643 if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1645 alloc_all(current,i);
1646 alloc_reg64(current,i,FTEMP);
1647 minimum_free_regs[i]=HOST_REGS;
1652 void store_alloc(struct regstat *current,int i)
1654 clear_const(current,rs2[i]);
1655 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1656 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1657 alloc_reg(current,i,rs2[i]);
1658 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1659 alloc_reg64(current,i,rs2[i]);
1660 if(rs2[i]) alloc_reg(current,i,FTEMP);
1662 // If using TLB, need a register for pointer to the mapping table
1663 if(using_tlb) alloc_reg(current,i,TLREG);
1664 #if defined(HOST_IMM8)
1665 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1666 else alloc_reg(current,i,INVCP);
1668 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1669 alloc_reg(current,i,FTEMP);
1671 // We need a temporary register for address generation
1672 alloc_reg_temp(current,i,-1);
1673 minimum_free_regs[i]=1;
1676 void c1ls_alloc(struct regstat *current,int i)
1678 //clear_const(current,rs1[i]); // FIXME
1679 clear_const(current,rt1[i]);
1680 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1681 alloc_reg(current,i,CSREG); // Status
1682 alloc_reg(current,i,FTEMP);
1683 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1684 alloc_reg64(current,i,FTEMP);
1686 // If using TLB, need a register for pointer to the mapping table
1687 if(using_tlb) alloc_reg(current,i,TLREG);
1688 #if defined(HOST_IMM8)
1689 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1690 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1691 alloc_reg(current,i,INVCP);
1693 // We need a temporary register for address generation
1694 alloc_reg_temp(current,i,-1);
1697 void c2ls_alloc(struct regstat *current,int i)
1699 clear_const(current,rt1[i]);
1700 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1701 alloc_reg(current,i,FTEMP);
1702 // If using TLB, need a register for pointer to the mapping table
1703 if(using_tlb) alloc_reg(current,i,TLREG);
1704 #if defined(HOST_IMM8)
1705 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1706 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1707 alloc_reg(current,i,INVCP);
1709 // We need a temporary register for address generation
1710 alloc_reg_temp(current,i,-1);
1711 minimum_free_regs[i]=1;
1714 #ifndef multdiv_alloc
1715 void multdiv_alloc(struct regstat *current,int i)
1722 // case 0x1D: DMULTU
1725 clear_const(current,rs1[i]);
1726 clear_const(current,rs2[i]);
1729 if((opcode2[i]&4)==0) // 32-bit
1731 current->u&=~(1LL<<HIREG);
1732 current->u&=~(1LL<<LOREG);
1733 alloc_reg(current,i,HIREG);
1734 alloc_reg(current,i,LOREG);
1735 alloc_reg(current,i,rs1[i]);
1736 alloc_reg(current,i,rs2[i]);
1737 current->is32|=1LL<<HIREG;
1738 current->is32|=1LL<<LOREG;
1739 dirty_reg(current,HIREG);
1740 dirty_reg(current,LOREG);
1744 current->u&=~(1LL<<HIREG);
1745 current->u&=~(1LL<<LOREG);
1746 current->uu&=~(1LL<<HIREG);
1747 current->uu&=~(1LL<<LOREG);
1748 alloc_reg64(current,i,HIREG);
1749 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1750 alloc_reg64(current,i,rs1[i]);
1751 alloc_reg64(current,i,rs2[i]);
1752 alloc_all(current,i);
1753 current->is32&=~(1LL<<HIREG);
1754 current->is32&=~(1LL<<LOREG);
1755 dirty_reg(current,HIREG);
1756 dirty_reg(current,LOREG);
1757 minimum_free_regs[i]=HOST_REGS;
1762 // Multiply by zero is zero.
1763 // MIPS does not have a divide by zero exception.
1764 // The result is undefined, we return zero.
1765 alloc_reg(current,i,HIREG);
1766 alloc_reg(current,i,LOREG);
1767 current->is32|=1LL<<HIREG;
1768 current->is32|=1LL<<LOREG;
1769 dirty_reg(current,HIREG);
1770 dirty_reg(current,LOREG);
1775 void cop0_alloc(struct regstat *current,int i)
1777 if(opcode2[i]==0) // MFC0
1780 clear_const(current,rt1[i]);
1781 alloc_all(current,i);
1782 alloc_reg(current,i,rt1[i]);
1783 current->is32|=1LL<<rt1[i];
1784 dirty_reg(current,rt1[i]);
1787 else if(opcode2[i]==4) // MTC0
1790 clear_const(current,rs1[i]);
1791 alloc_reg(current,i,rs1[i]);
1792 alloc_all(current,i);
1795 alloc_all(current,i); // FIXME: Keep r0
1797 alloc_reg(current,i,0);
1802 // TLBR/TLBWI/TLBWR/TLBP/ERET
1803 assert(opcode2[i]==0x10);
1804 alloc_all(current,i);
1806 minimum_free_regs[i]=HOST_REGS;
1809 void cop1_alloc(struct regstat *current,int i)
1811 alloc_reg(current,i,CSREG); // Load status
1812 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1815 clear_const(current,rt1[i]);
1817 alloc_reg64(current,i,rt1[i]); // DMFC1
1818 current->is32&=~(1LL<<rt1[i]);
1820 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1821 current->is32|=1LL<<rt1[i];
1823 dirty_reg(current,rt1[i]);
1825 alloc_reg_temp(current,i,-1);
1827 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1830 clear_const(current,rs1[i]);
1832 alloc_reg64(current,i,rs1[i]); // DMTC1
1834 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1835 alloc_reg_temp(current,i,-1);
1839 alloc_reg(current,i,0);
1840 alloc_reg_temp(current,i,-1);
1843 minimum_free_regs[i]=1;
1845 void fconv_alloc(struct regstat *current,int i)
1847 alloc_reg(current,i,CSREG); // Load status
1848 alloc_reg_temp(current,i,-1);
1849 minimum_free_regs[i]=1;
1851 void float_alloc(struct regstat *current,int i)
1853 alloc_reg(current,i,CSREG); // Load status
1854 alloc_reg_temp(current,i,-1);
1855 minimum_free_regs[i]=1;
1857 void c2op_alloc(struct regstat *current,int i)
1859 alloc_reg_temp(current,i,-1);
1861 void fcomp_alloc(struct regstat *current,int i)
1863 alloc_reg(current,i,CSREG); // Load status
1864 alloc_reg(current,i,FSREG); // Load flags
1865 dirty_reg(current,FSREG); // Flag will be modified
1866 alloc_reg_temp(current,i,-1);
1867 minimum_free_regs[i]=1;
1870 void syscall_alloc(struct regstat *current,int i)
1872 alloc_cc(current,i);
1873 dirty_reg(current,CCREG);
1874 alloc_all(current,i);
1875 minimum_free_regs[i]=HOST_REGS;
1879 void delayslot_alloc(struct regstat *current,int i)
1890 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1891 printf("Disabled speculative precompilation\n");
1895 imm16_alloc(current,i);
1899 load_alloc(current,i);
1903 store_alloc(current,i);
1906 alu_alloc(current,i);
1909 shift_alloc(current,i);
1912 multdiv_alloc(current,i);
1915 shiftimm_alloc(current,i);
1918 mov_alloc(current,i);
1921 cop0_alloc(current,i);
1925 cop1_alloc(current,i);
1928 c1ls_alloc(current,i);
1931 c2ls_alloc(current,i);
1934 fconv_alloc(current,i);
1937 float_alloc(current,i);
1940 fcomp_alloc(current,i);
1943 c2op_alloc(current,i);
1948 // Special case where a branch and delay slot span two pages in virtual memory
1949 static void pagespan_alloc(struct regstat *current,int i)
1952 current->wasconst=0;
1954 minimum_free_regs[i]=HOST_REGS;
1955 alloc_all(current,i);
1956 alloc_cc(current,i);
1957 dirty_reg(current,CCREG);
1958 if(opcode[i]==3) // JAL
1960 alloc_reg(current,i,31);
1961 dirty_reg(current,31);
1963 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1965 alloc_reg(current,i,rs1[i]);
1967 alloc_reg(current,i,rt1[i]);
1968 dirty_reg(current,rt1[i]);
1971 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1973 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1974 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1975 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1977 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1978 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1982 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1984 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1985 if(!((current->is32>>rs1[i])&1))
1987 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1991 if(opcode[i]==0x11) // BC1
1993 alloc_reg(current,i,FSREG);
1994 alloc_reg(current,i,CSREG);
1999 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
2001 stubs[stubcount][0]=type;
2002 stubs[stubcount][1]=addr;
2003 stubs[stubcount][2]=retaddr;
2004 stubs[stubcount][3]=a;
2005 stubs[stubcount][4]=b;
2006 stubs[stubcount][5]=c;
2007 stubs[stubcount][6]=d;
2008 stubs[stubcount][7]=e;
2012 // Write out a single register
2013 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2016 for(hr=0;hr<HOST_REGS;hr++) {
2017 if(hr!=EXCLUDE_REG) {
2018 if((regmap[hr]&63)==r) {
2021 emit_storereg(r,hr);
2023 if((is32>>regmap[hr])&1) {
2024 emit_sarimm(hr,31,hr);
2025 emit_storereg(r|64,hr);
2029 emit_storereg(r|64,hr);
2039 //if(!tracedebug) return 0;
2042 for(i=0;i<2097152;i++) {
2043 unsigned int temp=sum;
2046 sum^=((u_int *)rdram)[i];
2055 sum^=((u_int *)reg)[i];
2063 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2065 #ifndef DISABLE_COP1
2068 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2078 void memdebug(int i)
2080 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2081 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2084 //if(Count>=-2084597794) {
2085 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2087 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2088 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2089 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2092 printf("TRACE: %x\n",(&i)[-1]);
2096 printf("TRACE: %x \n",(&j)[10]);
2097 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2101 //printf("TRACE: %x\n",(&i)[-1]);
2104 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2106 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2109 void alu_assemble(int i,struct regstat *i_regs)
2111 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2113 signed char s1,s2,t;
2114 t=get_reg(i_regs->regmap,rt1[i]);
2116 s1=get_reg(i_regs->regmap,rs1[i]);
2117 s2=get_reg(i_regs->regmap,rs2[i]);
2118 if(rs1[i]&&rs2[i]) {
2121 if(opcode2[i]&2) emit_sub(s1,s2,t);
2122 else emit_add(s1,s2,t);
2125 if(s1>=0) emit_mov(s1,t);
2126 else emit_loadreg(rs1[i],t);
2130 if(opcode2[i]&2) emit_neg(s2,t);
2131 else emit_mov(s2,t);
2134 emit_loadreg(rs2[i],t);
2135 if(opcode2[i]&2) emit_neg(t,t);
2138 else emit_zeroreg(t);
2142 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2144 signed char s1l,s2l,s1h,s2h,tl,th;
2145 tl=get_reg(i_regs->regmap,rt1[i]);
2146 th=get_reg(i_regs->regmap,rt1[i]|64);
2148 s1l=get_reg(i_regs->regmap,rs1[i]);
2149 s2l=get_reg(i_regs->regmap,rs2[i]);
2150 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2151 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2152 if(rs1[i]&&rs2[i]) {
2155 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2156 else emit_adds(s1l,s2l,tl);
2158 #ifdef INVERTED_CARRY
2159 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2161 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2163 else emit_add(s1h,s2h,th);
2167 if(s1l>=0) emit_mov(s1l,tl);
2168 else emit_loadreg(rs1[i],tl);
2170 if(s1h>=0) emit_mov(s1h,th);
2171 else emit_loadreg(rs1[i]|64,th);
2176 if(opcode2[i]&2) emit_negs(s2l,tl);
2177 else emit_mov(s2l,tl);
2180 emit_loadreg(rs2[i],tl);
2181 if(opcode2[i]&2) emit_negs(tl,tl);
2184 #ifdef INVERTED_CARRY
2185 if(s2h>=0) emit_mov(s2h,th);
2186 else emit_loadreg(rs2[i]|64,th);
2188 emit_adcimm(-1,th); // x86 has inverted carry flag
2193 if(s2h>=0) emit_rscimm(s2h,0,th);
2195 emit_loadreg(rs2[i]|64,th);
2196 emit_rscimm(th,0,th);
2199 if(s2h>=0) emit_mov(s2h,th);
2200 else emit_loadreg(rs2[i]|64,th);
2207 if(th>=0) emit_zeroreg(th);
2212 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2214 signed char s1l,s1h,s2l,s2h,t;
2215 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2217 t=get_reg(i_regs->regmap,rt1[i]);
2220 s1l=get_reg(i_regs->regmap,rs1[i]);
2221 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2222 s2l=get_reg(i_regs->regmap,rs2[i]);
2223 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2224 if(rs2[i]==0) // rx<r0
2227 if(opcode2[i]==0x2a) // SLT
2228 emit_shrimm(s1h,31,t);
2229 else // SLTU (unsigned can not be less than zero)
2232 else if(rs1[i]==0) // r0<rx
2235 if(opcode2[i]==0x2a) // SLT
2236 emit_set_gz64_32(s2h,s2l,t);
2237 else // SLTU (set if not zero)
2238 emit_set_nz64_32(s2h,s2l,t);
2241 assert(s1l>=0);assert(s1h>=0);
2242 assert(s2l>=0);assert(s2h>=0);
2243 if(opcode2[i]==0x2a) // SLT
2244 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2246 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2250 t=get_reg(i_regs->regmap,rt1[i]);
2253 s1l=get_reg(i_regs->regmap,rs1[i]);
2254 s2l=get_reg(i_regs->regmap,rs2[i]);
2255 if(rs2[i]==0) // rx<r0
2258 if(opcode2[i]==0x2a) // SLT
2259 emit_shrimm(s1l,31,t);
2260 else // SLTU (unsigned can not be less than zero)
2263 else if(rs1[i]==0) // r0<rx
2266 if(opcode2[i]==0x2a) // SLT
2267 emit_set_gz32(s2l,t);
2268 else // SLTU (set if not zero)
2269 emit_set_nz32(s2l,t);
2272 assert(s1l>=0);assert(s2l>=0);
2273 if(opcode2[i]==0x2a) // SLT
2274 emit_set_if_less32(s1l,s2l,t);
2276 emit_set_if_carry32(s1l,s2l,t);
2282 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2284 signed char s1l,s1h,s2l,s2h,th,tl;
2285 tl=get_reg(i_regs->regmap,rt1[i]);
2286 th=get_reg(i_regs->regmap,rt1[i]|64);
2287 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2291 s1l=get_reg(i_regs->regmap,rs1[i]);
2292 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2293 s2l=get_reg(i_regs->regmap,rs2[i]);
2294 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2295 if(rs1[i]&&rs2[i]) {
2296 assert(s1l>=0);assert(s1h>=0);
2297 assert(s2l>=0);assert(s2h>=0);
2298 if(opcode2[i]==0x24) { // AND
2299 emit_and(s1l,s2l,tl);
2300 emit_and(s1h,s2h,th);
2302 if(opcode2[i]==0x25) { // OR
2303 emit_or(s1l,s2l,tl);
2304 emit_or(s1h,s2h,th);
2306 if(opcode2[i]==0x26) { // XOR
2307 emit_xor(s1l,s2l,tl);
2308 emit_xor(s1h,s2h,th);
2310 if(opcode2[i]==0x27) { // NOR
2311 emit_or(s1l,s2l,tl);
2312 emit_or(s1h,s2h,th);
2319 if(opcode2[i]==0x24) { // AND
2323 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2325 if(s1l>=0) emit_mov(s1l,tl);
2326 else emit_loadreg(rs1[i],tl);
2327 if(s1h>=0) emit_mov(s1h,th);
2328 else emit_loadreg(rs1[i]|64,th);
2332 if(s2l>=0) emit_mov(s2l,tl);
2333 else emit_loadreg(rs2[i],tl);
2334 if(s2h>=0) emit_mov(s2h,th);
2335 else emit_loadreg(rs2[i]|64,th);
2342 if(opcode2[i]==0x27) { // NOR
2344 if(s1l>=0) emit_not(s1l,tl);
2346 emit_loadreg(rs1[i],tl);
2349 if(s1h>=0) emit_not(s1h,th);
2351 emit_loadreg(rs1[i]|64,th);
2357 if(s2l>=0) emit_not(s2l,tl);
2359 emit_loadreg(rs2[i],tl);
2362 if(s2h>=0) emit_not(s2h,th);
2364 emit_loadreg(rs2[i]|64,th);
2380 s1l=get_reg(i_regs->regmap,rs1[i]);
2381 s2l=get_reg(i_regs->regmap,rs2[i]);
2382 if(rs1[i]&&rs2[i]) {
2385 if(opcode2[i]==0x24) { // AND
2386 emit_and(s1l,s2l,tl);
2388 if(opcode2[i]==0x25) { // OR
2389 emit_or(s1l,s2l,tl);
2391 if(opcode2[i]==0x26) { // XOR
2392 emit_xor(s1l,s2l,tl);
2394 if(opcode2[i]==0x27) { // NOR
2395 emit_or(s1l,s2l,tl);
2401 if(opcode2[i]==0x24) { // AND
2404 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2406 if(s1l>=0) emit_mov(s1l,tl);
2407 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2411 if(s2l>=0) emit_mov(s2l,tl);
2412 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2414 else emit_zeroreg(tl);
2416 if(opcode2[i]==0x27) { // NOR
2418 if(s1l>=0) emit_not(s1l,tl);
2420 emit_loadreg(rs1[i],tl);
2426 if(s2l>=0) emit_not(s2l,tl);
2428 emit_loadreg(rs2[i],tl);
2432 else emit_movimm(-1,tl);
2441 void imm16_assemble(int i,struct regstat *i_regs)
2443 if (opcode[i]==0x0f) { // LUI
2446 t=get_reg(i_regs->regmap,rt1[i]);
2449 if(!((i_regs->isconst>>t)&1))
2450 emit_movimm(imm[i]<<16,t);
2454 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2457 t=get_reg(i_regs->regmap,rt1[i]);
2458 s=get_reg(i_regs->regmap,rs1[i]);
2463 if(!((i_regs->isconst>>t)&1)) {
2465 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2466 emit_addimm(t,imm[i],t);
2468 if(!((i_regs->wasconst>>s)&1))
2469 emit_addimm(s,imm[i],t);
2471 emit_movimm(constmap[i][s]+imm[i],t);
2477 if(!((i_regs->isconst>>t)&1))
2478 emit_movimm(imm[i],t);
2483 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2485 signed char sh,sl,th,tl;
2486 th=get_reg(i_regs->regmap,rt1[i]|64);
2487 tl=get_reg(i_regs->regmap,rt1[i]);
2488 sh=get_reg(i_regs->regmap,rs1[i]|64);
2489 sl=get_reg(i_regs->regmap,rs1[i]);
2495 emit_addimm64_32(sh,sl,imm[i],th,tl);
2498 emit_addimm(sl,imm[i],tl);
2501 emit_movimm(imm[i],tl);
2502 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2507 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2509 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2510 signed char sh,sl,t;
2511 t=get_reg(i_regs->regmap,rt1[i]);
2512 sh=get_reg(i_regs->regmap,rs1[i]|64);
2513 sl=get_reg(i_regs->regmap,rs1[i]);
2517 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2518 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2519 if(opcode[i]==0x0a) { // SLTI
2521 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2522 emit_slti32(t,imm[i],t);
2524 emit_slti32(sl,imm[i],t);
2529 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2530 emit_sltiu32(t,imm[i],t);
2532 emit_sltiu32(sl,imm[i],t);
2537 if(opcode[i]==0x0a) // SLTI
2538 emit_slti64_32(sh,sl,imm[i],t);
2540 emit_sltiu64_32(sh,sl,imm[i],t);
2543 // SLTI(U) with r0 is just stupid,
2544 // nonetheless examples can be found
2545 if(opcode[i]==0x0a) // SLTI
2546 if(0<imm[i]) emit_movimm(1,t);
2547 else emit_zeroreg(t);
2550 if(imm[i]) emit_movimm(1,t);
2551 else emit_zeroreg(t);
2557 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2559 signed char sh,sl,th,tl;
2560 th=get_reg(i_regs->regmap,rt1[i]|64);
2561 tl=get_reg(i_regs->regmap,rt1[i]);
2562 sh=get_reg(i_regs->regmap,rs1[i]|64);
2563 sl=get_reg(i_regs->regmap,rs1[i]);
2564 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2565 if(opcode[i]==0x0c) //ANDI
2569 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2570 emit_andimm(tl,imm[i],tl);
2572 if(!((i_regs->wasconst>>sl)&1))
2573 emit_andimm(sl,imm[i],tl);
2575 emit_movimm(constmap[i][sl]&imm[i],tl);
2580 if(th>=0) emit_zeroreg(th);
2586 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2590 emit_loadreg(rs1[i]|64,th);
2595 if(opcode[i]==0x0d) //ORI
2597 emit_orimm(tl,imm[i],tl);
2599 if(!((i_regs->wasconst>>sl)&1))
2600 emit_orimm(sl,imm[i],tl);
2602 emit_movimm(constmap[i][sl]|imm[i],tl);
2604 if(opcode[i]==0x0e) //XORI
2606 emit_xorimm(tl,imm[i],tl);
2608 if(!((i_regs->wasconst>>sl)&1))
2609 emit_xorimm(sl,imm[i],tl);
2611 emit_movimm(constmap[i][sl]^imm[i],tl);
2615 emit_movimm(imm[i],tl);
2616 if(th>=0) emit_zeroreg(th);
2624 void shiftimm_assemble(int i,struct regstat *i_regs)
2626 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2630 t=get_reg(i_regs->regmap,rt1[i]);
2631 s=get_reg(i_regs->regmap,rs1[i]);
2640 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2642 if(opcode2[i]==0) // SLL
2644 emit_shlimm(s<0?t:s,imm[i],t);
2646 if(opcode2[i]==2) // SRL
2648 emit_shrimm(s<0?t:s,imm[i],t);
2650 if(opcode2[i]==3) // SRA
2652 emit_sarimm(s<0?t:s,imm[i],t);
2656 if(s>=0 && s!=t) emit_mov(s,t);
2660 //emit_storereg(rt1[i],t); //DEBUG
2663 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2666 signed char sh,sl,th,tl;
2667 th=get_reg(i_regs->regmap,rt1[i]|64);
2668 tl=get_reg(i_regs->regmap,rt1[i]);
2669 sh=get_reg(i_regs->regmap,rs1[i]|64);
2670 sl=get_reg(i_regs->regmap,rs1[i]);
2675 if(th>=0) emit_zeroreg(th);
2682 if(opcode2[i]==0x38) // DSLL
2684 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2685 emit_shlimm(sl,imm[i],tl);
2687 if(opcode2[i]==0x3a) // DSRL
2689 emit_shrdimm(sl,sh,imm[i],tl);
2690 if(th>=0) emit_shrimm(sh,imm[i],th);
2692 if(opcode2[i]==0x3b) // DSRA
2694 emit_shrdimm(sl,sh,imm[i],tl);
2695 if(th>=0) emit_sarimm(sh,imm[i],th);
2699 if(sl!=tl) emit_mov(sl,tl);
2700 if(th>=0&&sh!=th) emit_mov(sh,th);
2706 if(opcode2[i]==0x3c) // DSLL32
2709 signed char sl,tl,th;
2710 tl=get_reg(i_regs->regmap,rt1[i]);
2711 th=get_reg(i_regs->regmap,rt1[i]|64);
2712 sl=get_reg(i_regs->regmap,rs1[i]);
2721 emit_shlimm(th,imm[i]&31,th);
2726 if(opcode2[i]==0x3e) // DSRL32
2729 signed char sh,tl,th;
2730 tl=get_reg(i_regs->regmap,rt1[i]);
2731 th=get_reg(i_regs->regmap,rt1[i]|64);
2732 sh=get_reg(i_regs->regmap,rs1[i]|64);
2736 if(th>=0) emit_zeroreg(th);
2739 emit_shrimm(tl,imm[i]&31,tl);
2744 if(opcode2[i]==0x3f) // DSRA32
2748 tl=get_reg(i_regs->regmap,rt1[i]);
2749 sh=get_reg(i_regs->regmap,rs1[i]|64);
2755 emit_sarimm(tl,imm[i]&31,tl);
2762 #ifndef shift_assemble
2763 void shift_assemble(int i,struct regstat *i_regs)
2765 printf("Need shift_assemble for this architecture.\n");
2770 void load_assemble(int i,struct regstat *i_regs)
2772 int s,th,tl,addr,map=-1;
2775 int memtarget=0,c=0;
2777 th=get_reg(i_regs->regmap,rt1[i]|64);
2778 tl=get_reg(i_regs->regmap,rt1[i]);
2779 s=get_reg(i_regs->regmap,rs1[i]);
2781 for(hr=0;hr<HOST_REGS;hr++) {
2782 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2784 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2786 c=(i_regs->wasconst>>s)&1;
2788 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2789 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2792 //printf("load_assemble: c=%d\n",c);
2793 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2794 // FIXME: Even if the load is a NOP, we should check for pagefaults...
2796 if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2798 // could be FIFO, must perform the read
2800 assem_debug("(forced read)\n");
2801 tl=get_reg(i_regs->regmap,-1);
2805 if(offset||s<0||c) addr=tl;
2807 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2809 //printf("load_assemble: c=%d\n",c);
2810 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2811 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2813 if(th>=0) reglist&=~(1<<th);
2817 map=get_reg(i_regs->regmap,ROREG);
2818 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2820 //#define R29_HACK 1
2822 // Strmnnrmn's speed hack
2823 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2826 emit_cmpimm(addr,RAM_SIZE);
2828 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2829 // Hint to branch predictor that the branch is unlikely to be taken
2831 emit_jno_unlikely(0);
2839 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2840 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2841 map=get_reg(i_regs->regmap,TLREG);
2843 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2844 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2846 int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2847 if (opcode[i]==0x20) { // LB
2850 #ifdef HOST_IMM_ADDR32
2852 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2856 //emit_xorimm(addr,3,tl);
2857 //gen_tlb_addr_r(tl,map);
2858 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2860 #ifdef BIG_ENDIAN_MIPS
2861 if(!c) emit_xorimm(addr,3,tl);
2862 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2866 emit_movsbl_indexed_tlb(x,a,map,tl);
2870 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2873 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2875 if (opcode[i]==0x21) { // LH
2878 #ifdef HOST_IMM_ADDR32
2880 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2885 #ifdef BIG_ENDIAN_MIPS
2886 if(!c) emit_xorimm(addr,2,tl);
2887 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2892 //emit_movswl_indexed_tlb(x,tl,map,tl);
2895 gen_tlb_addr_r(a,map);
2896 emit_movswl_indexed(x,a,tl);
2899 emit_movswl_indexed(x,a,tl);
2901 emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2907 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2910 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2912 if (opcode[i]==0x23) { // LW
2915 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2916 #ifdef HOST_IMM_ADDR32
2918 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2921 emit_readword_indexed_tlb(0,addr,map,tl);
2924 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2927 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2929 if (opcode[i]==0x24) { // LBU
2932 #ifdef HOST_IMM_ADDR32
2934 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2938 //emit_xorimm(addr,3,tl);
2939 //gen_tlb_addr_r(tl,map);
2940 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
2942 #ifdef BIG_ENDIAN_MIPS
2943 if(!c) emit_xorimm(addr,3,tl);
2944 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2948 emit_movzbl_indexed_tlb(x,a,map,tl);
2952 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2955 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2957 if (opcode[i]==0x25) { // LHU
2960 #ifdef HOST_IMM_ADDR32
2962 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2967 #ifdef BIG_ENDIAN_MIPS
2968 if(!c) emit_xorimm(addr,2,tl);
2969 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2974 //emit_movzwl_indexed_tlb(x,tl,map,tl);
2977 gen_tlb_addr_r(a,map);
2978 emit_movzwl_indexed(x,a,tl);
2981 emit_movzwl_indexed(x,a,tl);
2983 emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
2989 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2992 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2994 if (opcode[i]==0x27) { // LWU
2998 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2999 #ifdef HOST_IMM_ADDR32
3001 emit_readword_tlb(constmap[i][s]+offset,map,tl);
3004 emit_readword_indexed_tlb(0,addr,map,tl);
3007 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3010 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3014 if (opcode[i]==0x37) { // LD
3017 //gen_tlb_addr_r(tl,map);
3018 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3019 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3020 #ifdef HOST_IMM_ADDR32
3022 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3025 emit_readdword_indexed_tlb(0,addr,map,th,tl);
3028 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3031 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3034 //emit_storereg(rt1[i],tl); // DEBUG
3035 //if(opcode[i]==0x23)
3036 //if(opcode[i]==0x24)
3037 //if(opcode[i]==0x23||opcode[i]==0x24)
3038 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3042 emit_readword((int)&last_count,ECX);
3044 if(get_reg(i_regs->regmap,CCREG)<0)
3045 emit_loadreg(CCREG,HOST_CCREG);
3046 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3047 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3048 emit_writeword(HOST_CCREG,(int)&Count);
3051 if(get_reg(i_regs->regmap,CCREG)<0)
3052 emit_loadreg(CCREG,0);
3054 emit_mov(HOST_CCREG,0);
3056 emit_addimm(0,2*ccadj[i],0);
3057 emit_writeword(0,(int)&Count);
3059 emit_call((int)memdebug);
3061 restore_regs(0x100f);
3065 #ifndef loadlr_assemble
3066 void loadlr_assemble(int i,struct regstat *i_regs)
3068 printf("Need loadlr_assemble for this architecture.\n");
3073 void store_assemble(int i,struct regstat *i_regs)
3078 int jaddr=0,jaddr2,type;
3079 int memtarget=0,c=0;
3080 int agr=AGEN1+(i&1);
3082 th=get_reg(i_regs->regmap,rs2[i]|64);
3083 tl=get_reg(i_regs->regmap,rs2[i]);
3084 s=get_reg(i_regs->regmap,rs1[i]);
3085 temp=get_reg(i_regs->regmap,agr);
3086 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3089 c=(i_regs->wasconst>>s)&1;
3091 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3092 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3097 for(hr=0;hr<HOST_REGS;hr++) {
3098 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3100 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3101 if(offset||s<0||c) addr=temp;
3106 // Strmnnrmn's speed hack
3108 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3110 emit_cmpimm(addr,RAM_SIZE);
3111 #ifdef DESTRUCTIVE_SHIFT
3112 if(s==addr) emit_mov(s,temp);
3115 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3119 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3120 // Hint to branch predictor that the branch is unlikely to be taken
3122 emit_jno_unlikely(0);
3130 if (opcode[i]==0x28) x=3; // SB
3131 if (opcode[i]==0x29) x=2; // SH
3132 map=get_reg(i_regs->regmap,TLREG);
3134 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3135 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3138 if (opcode[i]==0x28) { // SB
3141 #ifdef BIG_ENDIAN_MIPS
3142 if(!c) emit_xorimm(addr,3,temp);
3143 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3147 //gen_tlb_addr_w(temp,map);
3148 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3149 emit_writebyte_indexed_tlb(tl,x,a,map,a);
3153 if (opcode[i]==0x29) { // SH
3156 #ifdef BIG_ENDIAN_MIPS
3157 if(!c) emit_xorimm(addr,2,temp);
3158 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3163 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3166 gen_tlb_addr_w(a,map);
3167 emit_writehword_indexed(tl,x,a);
3169 emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
3173 if (opcode[i]==0x2B) { // SW
3175 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3176 emit_writeword_indexed_tlb(tl,0,addr,map,temp);
3179 if (opcode[i]==0x3F) { // SD
3183 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3184 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3185 emit_writedword_indexed_tlb(th,tl,0,addr,map,temp);
3188 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3189 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3190 emit_writedword_indexed_tlb(tl,tl,0,addr,map,temp);
3197 #ifdef DESTRUCTIVE_SHIFT
3198 // The x86 shift operation is 'destructive'; it overwrites the
3199 // source register, so we need to make a copy first and use that.
3202 #if defined(HOST_IMM8)
3203 int ir=get_reg(i_regs->regmap,INVCP);
3205 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3207 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3209 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3210 emit_callne(invalidate_addr_reg[addr]);
3214 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3219 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3220 } else if(c&&!memtarget) {
3221 inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3223 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3224 //if(opcode[i]==0x2B || opcode[i]==0x28)
3225 //if(opcode[i]==0x2B || opcode[i]==0x29)
3226 //if(opcode[i]==0x2B)
3227 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3231 emit_readword((int)&last_count,ECX);
3233 if(get_reg(i_regs->regmap,CCREG)<0)
3234 emit_loadreg(CCREG,HOST_CCREG);
3235 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3236 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3237 emit_writeword(HOST_CCREG,(int)&Count);
3240 if(get_reg(i_regs->regmap,CCREG)<0)
3241 emit_loadreg(CCREG,0);
3243 emit_mov(HOST_CCREG,0);
3245 emit_addimm(0,2*ccadj[i],0);
3246 emit_writeword(0,(int)&Count);
3248 emit_call((int)memdebug);
3250 restore_regs(0x100f);
3254 void storelr_assemble(int i,struct regstat *i_regs)
3261 int case1,case2,case3;
3262 int done0,done1,done2;
3263 int memtarget=0,c=0;
3264 int agr=AGEN1+(i&1);
3266 th=get_reg(i_regs->regmap,rs2[i]|64);
3267 tl=get_reg(i_regs->regmap,rs2[i]);
3268 s=get_reg(i_regs->regmap,rs1[i]);
3269 temp=get_reg(i_regs->regmap,agr);
3270 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3273 c=(i_regs->isconst>>s)&1;
3275 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3276 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3280 for(hr=0;hr<HOST_REGS;hr++) {
3281 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3286 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3287 if(!offset&&s!=temp) emit_mov(s,temp);
3293 if(!memtarget||!rs1[i]) {
3299 int map=get_reg(i_regs->regmap,ROREG);
3300 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3301 gen_tlb_addr_w(temp,map);
3303 if((u_int)rdram!=0x80000000)
3304 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3307 int map=get_reg(i_regs->regmap,TLREG);
3309 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3310 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3311 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3312 if(!jaddr&&!memtarget) {
3316 gen_tlb_addr_w(temp,map);
3319 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3320 temp2=get_reg(i_regs->regmap,FTEMP);
3321 if(!rs2[i]) temp2=th=tl;
3324 #ifndef BIG_ENDIAN_MIPS
3325 emit_xorimm(temp,3,temp);
3327 emit_testimm(temp,2);
3330 emit_testimm(temp,1);
3334 if (opcode[i]==0x2A) { // SWL
3335 emit_writeword_indexed(tl,0,temp);
3337 if (opcode[i]==0x2E) { // SWR
3338 emit_writebyte_indexed(tl,3,temp);
3340 if (opcode[i]==0x2C) { // SDL
3341 emit_writeword_indexed(th,0,temp);
3342 if(rs2[i]) emit_mov(tl,temp2);
3344 if (opcode[i]==0x2D) { // SDR
3345 emit_writebyte_indexed(tl,3,temp);
3346 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3351 set_jump_target(case1,(int)out);
3352 if (opcode[i]==0x2A) { // SWL
3353 // Write 3 msb into three least significant bytes
3354 if(rs2[i]) emit_rorimm(tl,8,tl);
3355 emit_writehword_indexed(tl,-1,temp);
3356 if(rs2[i]) emit_rorimm(tl,16,tl);
3357 emit_writebyte_indexed(tl,1,temp);
3358 if(rs2[i]) emit_rorimm(tl,8,tl);
3360 if (opcode[i]==0x2E) { // SWR
3361 // Write two lsb into two most significant bytes
3362 emit_writehword_indexed(tl,1,temp);
3364 if (opcode[i]==0x2C) { // SDL
3365 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3366 // Write 3 msb into three least significant bytes
3367 if(rs2[i]) emit_rorimm(th,8,th);
3368 emit_writehword_indexed(th,-1,temp);
3369 if(rs2[i]) emit_rorimm(th,16,th);
3370 emit_writebyte_indexed(th,1,temp);
3371 if(rs2[i]) emit_rorimm(th,8,th);
3373 if (opcode[i]==0x2D) { // SDR
3374 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3375 // Write two lsb into two most significant bytes
3376 emit_writehword_indexed(tl,1,temp);
3381 set_jump_target(case2,(int)out);
3382 emit_testimm(temp,1);
3385 if (opcode[i]==0x2A) { // SWL
3386 // Write two msb into two least significant bytes
3387 if(rs2[i]) emit_rorimm(tl,16,tl);
3388 emit_writehword_indexed(tl,-2,temp);
3389 if(rs2[i]) emit_rorimm(tl,16,tl);
3391 if (opcode[i]==0x2E) { // SWR
3392 // Write 3 lsb into three most significant bytes
3393 emit_writebyte_indexed(tl,-1,temp);
3394 if(rs2[i]) emit_rorimm(tl,8,tl);
3395 emit_writehword_indexed(tl,0,temp);
3396 if(rs2[i]) emit_rorimm(tl,24,tl);
3398 if (opcode[i]==0x2C) { // SDL
3399 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3400 // Write two msb into two least significant bytes
3401 if(rs2[i]) emit_rorimm(th,16,th);
3402 emit_writehword_indexed(th,-2,temp);
3403 if(rs2[i]) emit_rorimm(th,16,th);
3405 if (opcode[i]==0x2D) { // SDR
3406 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3407 // Write 3 lsb into three most significant bytes
3408 emit_writebyte_indexed(tl,-1,temp);
3409 if(rs2[i]) emit_rorimm(tl,8,tl);
3410 emit_writehword_indexed(tl,0,temp);
3411 if(rs2[i]) emit_rorimm(tl,24,tl);
3416 set_jump_target(case3,(int)out);
3417 if (opcode[i]==0x2A) { // SWL
3418 // Write msb into least significant byte
3419 if(rs2[i]) emit_rorimm(tl,24,tl);
3420 emit_writebyte_indexed(tl,-3,temp);
3421 if(rs2[i]) emit_rorimm(tl,8,tl);
3423 if (opcode[i]==0x2E) { // SWR
3424 // Write entire word
3425 emit_writeword_indexed(tl,-3,temp);
3427 if (opcode[i]==0x2C) { // SDL
3428 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3429 // Write msb into least significant byte
3430 if(rs2[i]) emit_rorimm(th,24,th);
3431 emit_writebyte_indexed(th,-3,temp);
3432 if(rs2[i]) emit_rorimm(th,8,th);
3434 if (opcode[i]==0x2D) { // SDR
3435 if(rs2[i]) emit_mov(th,temp2);
3436 // Write entire word
3437 emit_writeword_indexed(tl,-3,temp);
3439 set_jump_target(done0,(int)out);
3440 set_jump_target(done1,(int)out);
3441 set_jump_target(done2,(int)out);
3442 if (opcode[i]==0x2C) { // SDL
3443 emit_testimm(temp,4);
3446 emit_andimm(temp,~3,temp);
3447 emit_writeword_indexed(temp2,4,temp);
3448 set_jump_target(done0,(int)out);
3450 if (opcode[i]==0x2D) { // SDR
3451 emit_testimm(temp,4);
3454 emit_andimm(temp,~3,temp);
3455 emit_writeword_indexed(temp2,-4,temp);
3456 set_jump_target(done0,(int)out);
3459 add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
3462 int map=get_reg(i_regs->regmap,ROREG);
3463 if(map<0) map=HOST_TEMPREG;
3464 gen_orig_addr_w(temp,map);
3466 emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3468 #if defined(HOST_IMM8)
3469 int ir=get_reg(i_regs->regmap,INVCP);
3471 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3473 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3475 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3476 emit_callne(invalidate_addr_reg[temp]);
3480 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3485 //save_regs(0x100f);
3486 emit_readword((int)&last_count,ECX);
3487 if(get_reg(i_regs->regmap,CCREG)<0)
3488 emit_loadreg(CCREG,HOST_CCREG);
3489 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3490 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3491 emit_writeword(HOST_CCREG,(int)&Count);
3492 emit_call((int)memdebug);
3494 //restore_regs(0x100f);
3498 void c1ls_assemble(int i,struct regstat *i_regs)
3500 #ifndef DISABLE_COP1
3506 int jaddr,jaddr2=0,jaddr3,type;
3507 int agr=AGEN1+(i&1);
3509 th=get_reg(i_regs->regmap,FTEMP|64);
3510 tl=get_reg(i_regs->regmap,FTEMP);
3511 s=get_reg(i_regs->regmap,rs1[i]);
3512 temp=get_reg(i_regs->regmap,agr);
3513 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3518 for(hr=0;hr<HOST_REGS;hr++) {
3519 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3521 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3522 if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3524 // Loads use a temporary register which we need to save
3527 if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3531 //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3532 //else c=(i_regs->wasconst>>s)&1;
3533 if(s>=0) c=(i_regs->wasconst>>s)&1;
3534 // Check cop1 unusable
3536 signed char rs=get_reg(i_regs->regmap,CSREG);
3538 emit_testimm(rs,0x20000000);
3541 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3544 if (opcode[i]==0x39) { // SWC1 (get float address)
3545 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],tl);
3547 if (opcode[i]==0x3D) { // SDC1 (get double address)
3548 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],tl);
3550 // Generate address + offset
3553 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3557 map=get_reg(i_regs->regmap,TLREG);
3559 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3560 map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3562 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3563 map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3566 if (opcode[i]==0x39) { // SWC1 (read float)
3567 emit_readword_indexed(0,tl,tl);
3569 if (opcode[i]==0x3D) { // SDC1 (read double)
3570 emit_readword_indexed(4,tl,th);
3571 emit_readword_indexed(0,tl,tl);
3573 if (opcode[i]==0x31) { // LWC1 (get target address)
3574 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],temp);
3576 if (opcode[i]==0x35) { // LDC1 (get target address)
3577 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],temp);
3584 else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
3586 emit_jmp(0); // inline_readstub/inline_writestub? Very rare case
3588 #ifdef DESTRUCTIVE_SHIFT
3589 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3590 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3594 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3595 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3597 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3598 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3601 if (opcode[i]==0x31) { // LWC1
3602 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3603 //gen_tlb_addr_r(ar,map);
3604 //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3605 #ifdef HOST_IMM_ADDR32
3606 if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3609 emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3612 if (opcode[i]==0x35) { // LDC1
3614 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3615 //gen_tlb_addr_r(ar,map);
3616 //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3617 //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3618 #ifdef HOST_IMM_ADDR32
3619 if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3622 emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3625 if (opcode[i]==0x39) { // SWC1
3626 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3627 emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3630 if (opcode[i]==0x3D) { // SDC1
3632 //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3633 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3634 emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3638 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3639 #ifndef DESTRUCTIVE_SHIFT
3640 temp=offset||c||s<0?ar:s;
3642 #if defined(HOST_IMM8)
3643 int ir=get_reg(i_regs->regmap,INVCP);
3645 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3647 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3649 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3650 emit_callne(invalidate_addr_reg[temp]);
3654 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3658 if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3659 if (opcode[i]==0x31) { // LWC1 (write float)
3660 emit_writeword_indexed(tl,0,temp);
3662 if (opcode[i]==0x35) { // LDC1 (write double)
3663 emit_writeword_indexed(th,4,temp);
3664 emit_writeword_indexed(tl,0,temp);
3666 //if(opcode[i]==0x39)
3667 /*if(opcode[i]==0x39||opcode[i]==0x31)
3670 emit_readword((int)&last_count,ECX);
3671 if(get_reg(i_regs->regmap,CCREG)<0)
3672 emit_loadreg(CCREG,HOST_CCREG);
3673 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3674 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3675 emit_writeword(HOST_CCREG,(int)&Count);
3676 emit_call((int)memdebug);
3680 cop1_unusable(i, i_regs);
3684 void c2ls_assemble(int i,struct regstat *i_regs)
3689 int memtarget=0,c=0;
3690 int jaddr,jaddr2=0,jaddr3,type;
3691 int agr=AGEN1+(i&1);
3693 u_int copr=(source[i]>>16)&0x1f;
3694 s=get_reg(i_regs->regmap,rs1[i]);
3695 tl=get_reg(i_regs->regmap,FTEMP);
3701 for(hr=0;hr<HOST_REGS;hr++) {
3702 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3704 if(i_regs->regmap[HOST_CCREG]==CCREG)
3705 reglist&=~(1<<HOST_CCREG);
3708 if (opcode[i]==0x3a) { // SWC2
3709 ar=get_reg(i_regs->regmap,agr);
3710 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3715 if(s>=0) c=(i_regs->wasconst>>s)&1;
3716 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3717 if (!offset&&!c&&s>=0) ar=s;
3720 if (opcode[i]==0x3a) { // SWC2
3721 cop2_get_dreg(copr,tl,HOST_TEMPREG);
3729 emit_jmp(0); // inline_readstub/inline_writestub?
3733 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3737 if (opcode[i]==0x32) { // LWC2
3738 #ifdef HOST_IMM_ADDR32
3739 if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3742 emit_readword_indexed(0,ar,tl);
3744 if (opcode[i]==0x3a) { // SWC2
3745 #ifdef DESTRUCTIVE_SHIFT
3746 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3748 emit_writeword_indexed(tl,0,ar);
3752 add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3753 if (opcode[i]==0x3a) { // SWC2
3754 #if defined(HOST_IMM8)
3755 int ir=get_reg(i_regs->regmap,INVCP);
3757 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3759 emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3761 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3762 emit_callne(invalidate_addr_reg[ar]);
3766 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3769 if (opcode[i]==0x32) { // LWC2
3770 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3774 #ifndef multdiv_assemble
3775 void multdiv_assemble(int i,struct regstat *i_regs)
3777 printf("Need multdiv_assemble for this architecture.\n");
3782 void mov_assemble(int i,struct regstat *i_regs)
3784 //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3785 //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3787 signed char sh,sl,th,tl;
3788 th=get_reg(i_regs->regmap,rt1[i]|64);
3789 tl=get_reg(i_regs->regmap,rt1[i]);
3792 sh=get_reg(i_regs->regmap,rs1[i]|64);
3793 sl=get_reg(i_regs->regmap,rs1[i]);
3794 if(sl>=0) emit_mov(sl,tl);
3795 else emit_loadreg(rs1[i],tl);
3797 if(sh>=0) emit_mov(sh,th);
3798 else emit_loadreg(rs1[i]|64,th);
3804 #ifndef fconv_assemble
3805 void fconv_assemble(int i,struct regstat *i_regs)
3807 printf("Need fconv_assemble for this architecture.\n");
3813 void float_assemble(int i,struct regstat *i_regs)
3815 printf("Need float_assemble for this architecture.\n");
3820 void syscall_assemble(int i,struct regstat *i_regs)
3822 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3823 assert(ccreg==HOST_CCREG);
3824 assert(!is_delayslot);
3825 emit_movimm(start+i*4,EAX); // Get PC
3826 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
3827 emit_jmp((int)jump_syscall_hle); // XXX
3830 void hlecall_assemble(int i,struct regstat *i_regs)
3832 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3833 assert(ccreg==HOST_CCREG);
3834 assert(!is_delayslot);
3835 emit_movimm(start+i*4+4,0); // Get PC
3836 emit_movimm((int)psxHLEt[source[i]&7],1);
3837 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // XXX
3838 emit_jmp((int)jump_hlecall);
3841 void intcall_assemble(int i,struct regstat *i_regs)
3843 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3844 assert(ccreg==HOST_CCREG);
3845 assert(!is_delayslot);
3846 emit_movimm(start+i*4,0); // Get PC
3847 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3848 emit_jmp((int)jump_intcall);
3851 void ds_assemble(int i,struct regstat *i_regs)
3856 alu_assemble(i,i_regs);break;
3858 imm16_assemble(i,i_regs);break;
3860 shift_assemble(i,i_regs);break;
3862 shiftimm_assemble(i,i_regs);break;
3864 load_assemble(i,i_regs);break;
3866 loadlr_assemble(i,i_regs);break;
3868 store_assemble(i,i_regs);break;
3870 storelr_assemble(i,i_regs);break;
3872 cop0_assemble(i,i_regs);break;
3874 cop1_assemble(i,i_regs);break;
3876 c1ls_assemble(i,i_regs);break;
3878 cop2_assemble(i,i_regs);break;
3880 c2ls_assemble(i,i_regs);break;
3882 c2op_assemble(i,i_regs);break;
3884 fconv_assemble(i,i_regs);break;
3886 float_assemble(i,i_regs);break;
3888 fcomp_assemble(i,i_regs);break;
3890 multdiv_assemble(i,i_regs);break;
3892 mov_assemble(i,i_regs);break;
3902 printf("Jump in the delay slot. This is probably a bug.\n");
3907 // Is the branch target a valid internal jump?
3908 int internal_branch(uint64_t i_is32,int addr)
3910 if(addr&1) return 0; // Indirect (register) jump
3911 if(addr>=start && addr<start+slen*4-4)
3913 int t=(addr-start)>>2;
3914 // Delay slots are not valid branch targets
3915 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
3916 // 64 -> 32 bit transition requires a recompile
3917 /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
3919 if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
3920 else printf("optimizable: yes\n");
3922 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
3924 if(requires_32bit[t]&~i_is32) return 0;
3932 #ifndef wb_invalidate
3933 void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
3934 uint64_t u,uint64_t uu)
3937 for(hr=0;hr<HOST_REGS;hr++) {
3938 if(hr!=EXCLUDE_REG) {
3939 if(pre[hr]!=entry[hr]) {
3942 if(get_reg(entry,pre[hr])<0) {
3944 if(!((u>>pre[hr])&1)) {
3945 emit_storereg(pre[hr],hr);
3946 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
3947 emit_sarimm(hr,31,hr);
3948 emit_storereg(pre[hr]|64,hr);
3952 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
3953 emit_storereg(pre[hr],hr);
3962 // Move from one register to another (no writeback)
3963 for(hr=0;hr<HOST_REGS;hr++) {
3964 if(hr!=EXCLUDE_REG) {
3965 if(pre[hr]!=entry[hr]) {
3966 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
3968 if((nr=get_reg(entry,pre[hr]))>=0) {
3978 // Load the specified registers
3979 // This only loads the registers given as arguments because
3980 // we don't want to load things that will be overwritten
3981 void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
3985 for(hr=0;hr<HOST_REGS;hr++) {
3986 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
3987 if(entry[hr]!=regmap[hr]) {
3988 if(regmap[hr]==rs1||regmap[hr]==rs2)
3995 emit_loadreg(regmap[hr],hr);
4002 for(hr=0;hr<HOST_REGS;hr++) {
4003 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4004 if(entry[hr]!=regmap[hr]) {
4005 if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
4007 assert(regmap[hr]!=64);
4008 if((is32>>(regmap[hr]&63))&1) {
4009 int lr=get_reg(regmap,regmap[hr]-64);
4011 emit_sarimm(lr,31,hr);
4013 emit_loadreg(regmap[hr],hr);
4017 emit_loadreg(regmap[hr],hr);
4025 // Load registers prior to the start of a loop
4026 // so that they are not loaded within the loop
4027 static void loop_preload(signed char pre[],signed char entry[])
4030 for(hr=0;hr<HOST_REGS;hr++) {
4031 if(hr!=EXCLUDE_REG) {
4032 if(pre[hr]!=entry[hr]) {
4034 if(get_reg(pre,entry[hr])<0) {
4035 assem_debug("loop preload:\n");
4036 //printf("loop preload: %d\n",hr);
4040 else if(entry[hr]<TEMPREG)
4042 emit_loadreg(entry[hr],hr);
4044 else if(entry[hr]-64<TEMPREG)
4046 emit_loadreg(entry[hr],hr);
4055 // Generate address for load/store instruction
4056 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
4057 void address_generation(int i,struct regstat *i_regs,signed char entry[])
4059 if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
4061 int agr=AGEN1+(i&1);
4062 int mgr=MGEN1+(i&1);
4063 if(itype[i]==LOAD) {
4064 ra=get_reg(i_regs->regmap,rt1[i]);
4065 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4068 if(itype[i]==LOADLR) {
4069 ra=get_reg(i_regs->regmap,FTEMP);
4071 if(itype[i]==STORE||itype[i]==STORELR) {
4072 ra=get_reg(i_regs->regmap,agr);
4073 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4075 if(itype[i]==C1LS||itype[i]==C2LS) {
4076 if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
4077 ra=get_reg(i_regs->regmap,FTEMP);
4078 else { // SWC1/SDC1/SWC2/SDC2
4079 ra=get_reg(i_regs->regmap,agr);
4080 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4083 int rs=get_reg(i_regs->regmap,rs1[i]);
4084 int rm=get_reg(i_regs->regmap,TLREG);
4087 int c=(i_regs->wasconst>>rs)&1;
4089 // Using r0 as a base address
4091 if(!entry||entry[rm]!=mgr) {
4092 generate_map_const(offset,rm);
4093 } // else did it in the previous cycle
4095 if(!entry||entry[ra]!=agr) {
4096 if (opcode[i]==0x22||opcode[i]==0x26) {
4097 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4098 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4099 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4101 emit_movimm(offset,ra);
4103 } // else did it in the previous cycle
4106 if(!entry||entry[ra]!=rs1[i])
4107 emit_loadreg(rs1[i],ra);
4108 //if(!entry||entry[ra]!=rs1[i])
4109 // printf("poor load scheduling!\n");
4113 if(!entry||entry[rm]!=mgr) {
4114 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
4115 // Stores to memory go thru the mapper to detect self-modifying
4116 // code, loads don't.
4117 if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
4118 (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
4119 generate_map_const(constmap[i][rs]+offset,rm);
4121 if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
4122 generate_map_const(constmap[i][rs]+offset,rm);
4126 if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
4127 if(!entry||entry[ra]!=agr) {
4128 if (opcode[i]==0x22||opcode[i]==0x26) {
4129 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4130 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4131 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4133 #ifdef HOST_IMM_ADDR32
4134 if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4135 (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4137 emit_movimm(constmap[i][rs]+offset,ra);
4139 } // else did it in the previous cycle
4140 } // else load_consts already did it
4142 if(offset&&!c&&rs1[i]) {
4144 emit_addimm(rs,offset,ra);
4146 emit_addimm(ra,offset,ra);
4151 // Preload constants for next instruction
4152 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
4154 #ifndef HOST_IMM_ADDR32
4156 agr=MGEN1+((i+1)&1);
4157 ra=get_reg(i_regs->regmap,agr);
4159 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4160 int offset=imm[i+1];
4161 int c=(regs[i+1].wasconst>>rs)&1;
4163 if(itype[i+1]==STORE||itype[i+1]==STORELR
4164 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
4165 // Stores to memory go thru the mapper to detect self-modifying
4166 // code, loads don't.
4167 if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4168 (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
4169 generate_map_const(constmap[i+1][rs]+offset,ra);
4171 if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4172 generate_map_const(constmap[i+1][rs]+offset,ra);
4175 /*else if(rs1[i]==0) {
4176 generate_map_const(offset,ra);
4181 agr=AGEN1+((i+1)&1);
4182 ra=get_reg(i_regs->regmap,agr);
4184 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4185 int offset=imm[i+1];
4186 int c=(regs[i+1].wasconst>>rs)&1;
4187 if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4188 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4189 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4190 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4191 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4193 #ifdef HOST_IMM_ADDR32
4194 if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4195 (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4197 emit_movimm(constmap[i+1][rs]+offset,ra);
4200 else if(rs1[i+1]==0) {
4201 // Using r0 as a base address
4202 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4203 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4204 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4205 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4207 emit_movimm(offset,ra);
4214 int get_final_value(int hr, int i, int *value)
4216 int reg=regs[i].regmap[hr];
4218 if(regs[i+1].regmap[hr]!=reg) break;
4219 if(!((regs[i+1].isconst>>hr)&1)) break;
4224 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4225 *value=constmap[i][hr];
4229 if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4230 // Load in delay slot, out-of-order execution
4231 if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4233 #ifdef HOST_IMM_ADDR32
4234 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4236 // Precompute load address
4237 *value=constmap[i][hr]+imm[i+2];
4241 if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4243 #ifdef HOST_IMM_ADDR32
4244 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4246 // Precompute load address
4247 *value=constmap[i][hr]+imm[i+1];
4248 //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4253 *value=constmap[i][hr];
4254 //printf("c=%x\n",(int)constmap[i][hr]);
4255 if(i==slen-1) return 1;
4257 return !((unneeded_reg[i+1]>>reg)&1);
4259 return !((unneeded_reg_upper[i+1]>>reg)&1);
4263 // Load registers with known constants
4264 void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4268 for(hr=0;hr<HOST_REGS;hr++) {
4269 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4270 //if(entry[hr]!=regmap[hr]) {
4271 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4272 if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) {
4274 if(get_final_value(hr,i,&value)) {
4279 emit_movimm(value,hr);
4287 for(hr=0;hr<HOST_REGS;hr++) {
4288 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4289 //if(entry[hr]!=regmap[hr]) {
4290 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4291 if(((regs[i].isconst>>hr)&1)&®map[hr]>64) {
4292 if((is32>>(regmap[hr]&63))&1) {
4293 int lr=get_reg(regmap,regmap[hr]-64);
4295 emit_sarimm(lr,31,hr);
4300 if(get_final_value(hr,i,&value)) {
4305 emit_movimm(value,hr);
4314 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4318 for(hr=0;hr<HOST_REGS;hr++) {
4319 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4320 if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) {
4321 int value=constmap[i][hr];
4326 emit_movimm(value,hr);
4332 for(hr=0;hr<HOST_REGS;hr++) {
4333 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4334 if(((regs[i].isconst>>hr)&1)&®map[hr]>64) {
4335 if((is32>>(regmap[hr]&63))&1) {
4336 int lr=get_reg(regmap,regmap[hr]-64);
4338 emit_sarimm(lr,31,hr);
4342 int value=constmap[i][hr];
4347 emit_movimm(value,hr);
4355 // Write out all dirty registers (except cycle count)
4356 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4359 for(hr=0;hr<HOST_REGS;hr++) {
4360 if(hr!=EXCLUDE_REG) {
4361 if(i_regmap[hr]>0) {
4362 if(i_regmap[hr]!=CCREG) {
4363 if((i_dirty>>hr)&1) {
4364 if(i_regmap[hr]<64) {
4365 emit_storereg(i_regmap[hr],hr);
4367 if( ((i_is32>>i_regmap[hr])&1) ) {
4368 #ifdef DESTRUCTIVE_WRITEBACK
4369 emit_sarimm(hr,31,hr);
4370 emit_storereg(i_regmap[hr]|64,hr);
4372 emit_sarimm(hr,31,HOST_TEMPREG);
4373 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4378 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4379 emit_storereg(i_regmap[hr],hr);
4388 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4389 // This writes the registers not written by store_regs_bt
4390 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4393 int t=(addr-start)>>2;
4394 for(hr=0;hr<HOST_REGS;hr++) {
4395 if(hr!=EXCLUDE_REG) {
4396 if(i_regmap[hr]>0) {
4397 if(i_regmap[hr]!=CCREG) {
4398 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4399 if((i_dirty>>hr)&1) {
4400 if(i_regmap[hr]<64) {
4401 emit_storereg(i_regmap[hr],hr);
4403 if( ((i_is32>>i_regmap[hr])&1) ) {
4404 #ifdef DESTRUCTIVE_WRITEBACK
4405 emit_sarimm(hr,31,hr);
4406 emit_storereg(i_regmap[hr]|64,hr);
4408 emit_sarimm(hr,31,HOST_TEMPREG);
4409 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4414 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4415 emit_storereg(i_regmap[hr],hr);
4426 // Load all registers (except cycle count)
4427 void load_all_regs(signed char i_regmap[])
4430 for(hr=0;hr<HOST_REGS;hr++) {
4431 if(hr!=EXCLUDE_REG) {
4432 if(i_regmap[hr]==0) {
4436 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG)
4438 emit_loadreg(i_regmap[hr],hr);
4444 // Load all current registers also needed by next instruction
4445 void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4448 for(hr=0;hr<HOST_REGS;hr++) {
4449 if(hr!=EXCLUDE_REG) {
4450 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4451 if(i_regmap[hr]==0) {
4455 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG)
4457 emit_loadreg(i_regmap[hr],hr);
4464 // Load all regs, storing cycle count if necessary
4465 void load_regs_entry(int t)
4468 if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER,HOST_CCREG);
4469 else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t]*CLOCK_DIVIDER,HOST_CCREG);
4470 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4471 emit_storereg(CCREG,HOST_CCREG);
4474 for(hr=0;hr<HOST_REGS;hr++) {
4475 if(regs[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<64) {
4476 if(regs[t].regmap_entry[hr]==0) {
4479 else if(regs[t].regmap_entry[hr]!=CCREG)
4481 emit_loadreg(regs[t].regmap_entry[hr],hr);
4486 for(hr=0;hr<HOST_REGS;hr++) {
4487 if(regs[t].regmap_entry[hr]>=64) {
4488 assert(regs[t].regmap_entry[hr]!=64);
4489 if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4490 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4492 emit_loadreg(regs[t].regmap_entry[hr],hr);
4496 emit_sarimm(lr,31,hr);
4501 emit_loadreg(regs[t].regmap_entry[hr],hr);
4507 // Store dirty registers prior to branch
4508 void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4510 if(internal_branch(i_is32,addr))
4512 int t=(addr-start)>>2;
4514 for(hr=0;hr<HOST_REGS;hr++) {
4515 if(hr!=EXCLUDE_REG) {
4516 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4517 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4518 if((i_dirty>>hr)&1) {
4519 if(i_regmap[hr]<64) {
4520 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4521 emit_storereg(i_regmap[hr],hr);
4522 if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4523 #ifdef DESTRUCTIVE_WRITEBACK
4524 emit_sarimm(hr,31,hr);
4525 emit_storereg(i_regmap[hr]|64,hr);
4527 emit_sarimm(hr,31,HOST_TEMPREG);
4528 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4533 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4534 emit_storereg(i_regmap[hr],hr);
4545 // Branch out of this block, write out all dirty regs
4546 wb_dirtys(i_regmap,i_is32,i_dirty);
4550 // Load all needed registers for branch target
4551 void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4553 //if(addr>=start && addr<(start+slen*4))
4554 if(internal_branch(i_is32,addr))
4556 int t=(addr-start)>>2;
4558 // Store the cycle count before loading something else
4559 if(i_regmap[HOST_CCREG]!=CCREG) {
4560 assert(i_regmap[HOST_CCREG]==-1);
4562 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4563 emit_storereg(CCREG,HOST_CCREG);
4566 for(hr=0;hr<HOST_REGS;hr++) {
4567 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<64) {
4568 #ifdef DESTRUCTIVE_WRITEBACK
4569 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4571 if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4573 if(regs[t].regmap_entry[hr]==0) {
4576 else if(regs[t].regmap_entry[hr]!=CCREG)
4578 emit_loadreg(regs[t].regmap_entry[hr],hr);
4584 for(hr=0;hr<HOST_REGS;hr++) {
4585 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=64) {
4586 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4587 assert(regs[t].regmap_entry[hr]!=64);
4588 if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4589 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4591 emit_loadreg(regs[t].regmap_entry[hr],hr);
4595 emit_sarimm(lr,31,hr);
4600 emit_loadreg(regs[t].regmap_entry[hr],hr);
4603 else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4604 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4606 emit_sarimm(lr,31,hr);
4613 int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4615 if(addr>=start && addr<start+slen*4-4)
4617 int t=(addr-start)>>2;
4619 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4620 for(hr=0;hr<HOST_REGS;hr++)
4624 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4626 if(regs[t].regmap_entry[hr]!=-1)
4635 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4640 if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4645 else // Same register but is it 32-bit or dirty?
4648 if(!((regs[t].dirty>>hr)&1))
4652 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4654 //printf("%x: dirty no match\n",addr);
4659 if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4661 //printf("%x: is32 no match\n",addr);
4667 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4669 if(requires_32bit[t]&~i_is32) return 0;
4671 // Delay slots are not valid branch targets
4672 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4673 // Delay slots require additional processing, so do not match
4674 if(is_ds[t]) return 0;
4679 for(hr=0;hr<HOST_REGS;hr++)
4685 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4699 // Used when a branch jumps into the delay slot of another branch
4700 void ds_assemble_entry(int i)
4702 int t=(ba[i]-start)>>2;
4703 if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4704 assem_debug("Assemble delay slot at %x\n",ba[i]);
4705 assem_debug("<->\n");
4706 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&®s[t].regmap[HOST_CCREG]!=CCREG)
4707 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4708 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4709 address_generation(t,®s[t],regs[t].regmap_entry);
4710 if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
4711 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4716 alu_assemble(t,®s[t]);break;
4718 imm16_assemble(t,®s[t]);break;
4720 shift_assemble(t,®s[t]);break;
4722 shiftimm_assemble(t,®s[t]);break;
4724 load_assemble(t,®s[t]);break;
4726 loadlr_assemble(t,®s[t]);break;
4728 store_assemble(t,®s[t]);break;
4730 storelr_assemble(t,®s[t]);break;
4732 cop0_assemble(t,®s[t]);break;
4734 cop1_assemble(t,®s[t]);break;
4736 c1ls_assemble(t,®s[t]);break;
4738 cop2_assemble(t,®s[t]);break;
4740 c2ls_assemble(t,®s[t]);break;
4742 c2op_assemble(t,®s[t]);break;
4744 fconv_assemble(t,®s[t]);break;
4746 float_assemble(t,®s[t]);break;
4748 fcomp_assemble(t,®s[t]);break;
4750 multdiv_assemble(t,®s[t]);break;
4752 mov_assemble(t,®s[t]);break;
4762 printf("Jump in the delay slot. This is probably a bug.\n");
4764 store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4765 load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4766 if(internal_branch(regs[t].is32,ba[i]+4))
4767 assem_debug("branch: internal\n");
4769 assem_debug("branch: external\n");
4770 assert(internal_branch(regs[t].is32,ba[i]+4));
4771 add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4775 void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4784 //if(ba[i]>=start && ba[i]<(start+slen*4))
4785 if(internal_branch(branch_regs[i].is32,ba[i]))
4787 int t=(ba[i]-start)>>2;
4788 if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4796 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4798 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4800 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4801 emit_andimm(HOST_CCREG,3,HOST_CCREG);
4805 else if(*adj==0||invert) {
4806 emit_addimm_and_set_flags(CLOCK_DIVIDER*(count+2),HOST_CCREG);
4812 emit_cmpimm(HOST_CCREG,-2*(count+2));
4816 add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4819 void do_ccstub(int n)
4822 assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
4823 set_jump_target(stubs[n][1],(int)out);
4825 if(stubs[n][6]==NULLDS) {
4826 // Delay slot instruction is nullified ("likely" branch)
4827 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4829 else if(stubs[n][6]!=TAKEN) {
4830 wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4833 if(internal_branch(branch_regs[i].is32,ba[i]))
4834 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4838 // Save PC as return address
4839 emit_movimm(stubs[n][5],EAX);
4840 emit_writeword(EAX,(int)&pcaddr);
4844 // Return address depends on which way the branch goes
4845 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
4847 int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4848 int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4849 int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4850 int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4860 if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
4864 #ifdef DESTRUCTIVE_WRITEBACK
4866 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
4867 emit_loadreg(rs1[i],s1l);
4870 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
4871 emit_loadreg(rs2[i],s1l);
4874 if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
4875 emit_loadreg(rs2[i],s2l);
4878 int addr,alt,ntaddr;
4881 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4882 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4883 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4891 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4892 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4893 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4899 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
4903 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4904 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4905 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4911 assert(hr<HOST_REGS);
4913 if((opcode[i]&0x2f)==4) // BEQ
4915 #ifdef HAVE_CMOV_IMM
4917 if(s2l>=0) emit_cmp(s1l,s2l);
4918 else emit_test(s1l,s1l);
4919 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
4924 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4926 if(s2h>=0) emit_cmp(s1h,s2h);
4927 else emit_test(s1h,s1h);
4928 emit_cmovne_reg(alt,addr);
4930 if(s2l>=0) emit_cmp(s1l,s2l);
4931 else emit_test(s1l,s1l);
4932 emit_cmovne_reg(alt,addr);
4935 if((opcode[i]&0x2f)==5) // BNE
4937 #ifdef HAVE_CMOV_IMM
4939 if(s2l>=0) emit_cmp(s1l,s2l);
4940 else emit_test(s1l,s1l);
4941 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
4946 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
4948 if(s2h>=0) emit_cmp(s1h,s2h);
4949 else emit_test(s1h,s1h);
4950 emit_cmovne_reg(alt,addr);
4952 if(s2l>=0) emit_cmp(s1l,s2l);
4953 else emit_test(s1l,s1l);
4954 emit_cmovne_reg(alt,addr);
4957 if((opcode[i]&0x2f)==6) // BLEZ
4959 //emit_movimm(ba[i],alt);
4960 //emit_movimm(start+i*4+8,addr);
4961 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4963 if(s1h>=0) emit_mov(addr,ntaddr);
4964 emit_cmovl_reg(alt,addr);
4967 emit_cmovne_reg(ntaddr,addr);
4968 emit_cmovs_reg(alt,addr);
4971 if((opcode[i]&0x2f)==7) // BGTZ
4973 //emit_movimm(ba[i],addr);
4974 //emit_movimm(start+i*4+8,ntaddr);
4975 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
4977 if(s1h>=0) emit_mov(addr,alt);
4978 emit_cmovl_reg(ntaddr,addr);
4981 emit_cmovne_reg(alt,addr);
4982 emit_cmovs_reg(ntaddr,addr);
4985 if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
4987 //emit_movimm(ba[i],alt);
4988 //emit_movimm(start+i*4+8,addr);
4989 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4990 if(s1h>=0) emit_test(s1h,s1h);
4991 else emit_test(s1l,s1l);
4992 emit_cmovs_reg(alt,addr);
4994 if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
4996 //emit_movimm(ba[i],addr);
4997 //emit_movimm(start+i*4+8,alt);
4998 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4999 if(s1h>=0) emit_test(s1h,s1h);
5000 else emit_test(s1l,s1l);
5001 emit_cmovs_reg(alt,addr);
5003 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
5004 if(source[i]&0x10000) // BC1T
5006 //emit_movimm(ba[i],alt);
5007 //emit_movimm(start+i*4+8,addr);
5008 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5009 emit_testimm(s1l,0x800000);
5010 emit_cmovne_reg(alt,addr);
5014 //emit_movimm(ba[i],addr);
5015 //emit_movimm(start+i*4+8,alt);
5016 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5017 emit_testimm(s1l,0x800000);
5018 emit_cmovne_reg(alt,addr);
5021 emit_writeword(addr,(int)&pcaddr);
5026 int r=get_reg(branch_regs[i].regmap,rs1[i]);
5027 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5028 r=get_reg(branch_regs[i].regmap,RTEMP);
5030 emit_writeword(r,(int)&pcaddr);
5032 else {printf("Unknown branch type in do_ccstub\n");exit(1);}
5034 // Update cycle count
5035 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5036 if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
5037 emit_call((int)cc_interrupt);
5038 if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
5039 if(stubs[n][6]==TAKEN) {
5040 if(internal_branch(branch_regs[i].is32,ba[i]))
5041 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
5042 else if(itype[i]==RJUMP) {
5043 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5044 emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5046 emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
5048 }else if(stubs[n][6]==NOTTAKEN) {
5049 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5050 else load_all_regs(branch_regs[i].regmap);
5051 }else if(stubs[n][6]==NULLDS) {
5052 // Delay slot instruction is nullified ("likely" branch)
5053 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5054 else load_all_regs(regs[i].regmap);
5056 load_all_regs(branch_regs[i].regmap);
5058 emit_jmp(stubs[n][2]); // return address
5060 /* This works but uses a lot of memory...
5061 emit_readword((int)&last_count,ECX);
5062 emit_add(HOST_CCREG,ECX,EAX);
5063 emit_writeword(EAX,(int)&Count);
5064 emit_call((int)gen_interupt);
5065 emit_readword((int)&Count,HOST_CCREG);
5066 emit_readword((int)&next_interupt,EAX);
5067 emit_readword((int)&pending_exception,EBX);
5068 emit_writeword(EAX,(int)&last_count);
5069 emit_sub(HOST_CCREG,EAX,HOST_CCREG);
5071 int jne_instr=(int)out;
5073 if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
5074 load_all_regs(branch_regs[i].regmap);
5075 emit_jmp(stubs[n][2]); // return address
5076 set_jump_target(jne_instr,(int)out);
5077 emit_readword((int)&pcaddr,EAX);
5078 // Call get_addr_ht instead of doing the hash table here.
5079 // This code is executed infrequently and takes up a lot of space
5080 // so smaller is better.
5081 emit_storereg(CCREG,HOST_CCREG);
5083 emit_call((int)get_addr_ht);
5084 emit_loadreg(CCREG,HOST_CCREG);
5085 emit_addimm(ESP,4,ESP);
5089 add_to_linker(int addr,int target,int ext)
5091 link_addr[linkcount][0]=addr;
5092 link_addr[linkcount][1]=target;
5093 link_addr[linkcount][2]=ext;
5097 void ujump_assemble(int i,struct regstat *i_regs)
5099 signed char *i_regmap=i_regs->regmap;
5100 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5101 address_generation(i+1,i_regs,regs[i].regmap_entry);
5103 int temp=get_reg(branch_regs[i].regmap,PTEMP);
5104 if(rt1[i]==31&&temp>=0)
5106 int return_address=start+i*4+8;
5107 if(get_reg(branch_regs[i].regmap,31)>0)
5108 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5111 ds_assemble(i+1,i_regs);
5112 uint64_t bc_unneeded=branch_regs[i].u;
5113 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5114 bc_unneeded|=1|(1LL<<rt1[i]);
5115 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5116 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5117 bc_unneeded,bc_unneeded_upper);
5118 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5121 unsigned int return_address;
5122 assert(rt1[i+1]!=31);
5123 assert(rt2[i+1]!=31);
5124 rt=get_reg(branch_regs[i].regmap,31);
5125 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5127 return_address=start+i*4+8;
5130 if(internal_branch(branch_regs[i].is32,return_address)) {
5132 if(temp==EXCLUDE_REG||temp>=HOST_REGS||
5133 branch_regs[i].regmap[temp]>=0)
5135 temp=get_reg(branch_regs[i].regmap,-1);
5138 if(temp<0) temp=HOST_TEMPREG;
5140 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5141 else emit_movimm(return_address,rt);
5149 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5152 emit_movimm(return_address,rt); // PC into link register
5154 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5160 cc=get_reg(branch_regs[i].regmap,CCREG);
5161 assert(cc==HOST_CCREG);
5162 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5164 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5166 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5167 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5168 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5169 if(internal_branch(branch_regs[i].is32,ba[i]))
5170 assem_debug("branch: internal\n");
5172 assem_debug("branch: external\n");
5173 if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5174 ds_assemble_entry(i);
5177 add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5182 void rjump_assemble(int i,struct regstat *i_regs)
5184 signed char *i_regmap=i_regs->regmap;
5187 rs=get_reg(branch_regs[i].regmap,rs1[i]);
5189 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5190 // Delay slot abuse, make a copy of the branch address register
5191 temp=get_reg(branch_regs[i].regmap,RTEMP);
5193 assert(regs[i].regmap[temp]==RTEMP);
5197 address_generation(i+1,i_regs,regs[i].regmap_entry);
5201 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5202 int return_address=start+i*4+8;
5203 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5209 int rh=get_reg(regs[i].regmap,RHASH);
5210 if(rh>=0) do_preload_rhash(rh);
5213 ds_assemble(i+1,i_regs);
5214 uint64_t bc_unneeded=branch_regs[i].u;
5215 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5216 bc_unneeded|=1|(1LL<<rt1[i]);
5217 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5218 bc_unneeded&=~(1LL<<rs1[i]);
5219 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5220 bc_unneeded,bc_unneeded_upper);
5221 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5223 int rt,return_address;
5224 assert(rt1[i+1]!=rt1[i]);
5225 assert(rt2[i+1]!=rt1[i]);
5226 rt=get_reg(branch_regs[i].regmap,rt1[i]);
5227 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5229 return_address=start+i*4+8;
5233 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5236 emit_movimm(return_address,rt); // PC into link register
5238 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5241 cc=get_reg(branch_regs[i].regmap,CCREG);
5242 assert(cc==HOST_CCREG);
5244 int rh=get_reg(branch_regs[i].regmap,RHASH);
5245 int ht=get_reg(branch_regs[i].regmap,RHTBL);
5247 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5248 do_preload_rhtbl(ht);
5252 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5253 #ifdef DESTRUCTIVE_WRITEBACK
5254 if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5255 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5256 emit_loadreg(rs1[i],rs);
5261 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5265 do_miniht_load(ht,rh);
5268 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5269 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5271 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5272 add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5274 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5277 do_miniht_jump(rs,rh,ht);
5282 //if(rs!=EAX) emit_mov(rs,EAX);
5283 //emit_jmp((int)jump_vaddr_eax);
5284 emit_jmp(jump_vaddr_reg[rs]);
5289 emit_shrimm(rs,16,rs);
5290 emit_xor(temp,rs,rs);
5291 emit_movzwl_reg(rs,rs);
5292 emit_shlimm(rs,4,rs);
5293 emit_cmpmem_indexed((int)hash_table,rs,temp);
5294 emit_jne((int)out+14);
5295 emit_readword_indexed((int)hash_table+4,rs,rs);
5297 emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5298 emit_addimm_no_flags(8,rs);
5299 emit_jeq((int)out-17);
5300 // No hit on hash table, call compiler
5303 #ifdef DEBUG_CYCLE_COUNT
5304 emit_readword((int)&last_count,ECX);
5305 emit_add(HOST_CCREG,ECX,HOST_CCREG);
5306 emit_readword((int)&next_interupt,ECX);
5307 emit_writeword(HOST_CCREG,(int)&Count);
5308 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5309 emit_writeword(ECX,(int)&last_count);
5312 emit_storereg(CCREG,HOST_CCREG);
5313 emit_call((int)get_addr);
5314 emit_loadreg(CCREG,HOST_CCREG);
5315 emit_addimm(ESP,4,ESP);
5317 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5318 if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5322 void cjump_assemble(int i,struct regstat *i_regs)
5324 signed char *i_regmap=i_regs->regmap;
5327 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5328 assem_debug("match=%d\n",match);
5329 int s1h,s1l,s2h,s2l;
5330 int prev_cop1_usable=cop1_usable;
5331 int unconditional=0,nop=0;
5334 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5335 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5336 if(!match) invert=1;
5337 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5338 if(i>(ba[i]-start)>>2) invert=1;
5342 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5343 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5344 s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5345 s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5348 s1l=get_reg(i_regmap,rs1[i]);
5349 s1h=get_reg(i_regmap,rs1[i]|64);
5350 s2l=get_reg(i_regmap,rs2[i]);
5351 s2h=get_reg(i_regmap,rs2[i]|64);
5353 if(rs1[i]==0&&rs2[i]==0)
5355 if(opcode[i]&1) nop=1;
5356 else unconditional=1;
5357 //assert(opcode[i]!=5);
5358 //assert(opcode[i]!=7);
5359 //assert(opcode[i]!=0x15);
5360 //assert(opcode[i]!=0x17);
5366 only32=(regs[i].was32>>rs2[i])&1;
5371 only32=(regs[i].was32>>rs1[i])&1;
5374 only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5378 // Out of order execution (delay slot first)
5380 address_generation(i+1,i_regs,regs[i].regmap_entry);
5381 ds_assemble(i+1,i_regs);
5383 uint64_t bc_unneeded=branch_regs[i].u;
5384 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5385 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5386 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5388 bc_unneeded_upper|=1;
5389 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5390 bc_unneeded,bc_unneeded_upper);
5391 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5392 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5393 cc=get_reg(branch_regs[i].regmap,CCREG);
5394 assert(cc==HOST_CCREG);
5396 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5397 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5398 //assem_debug("cycle count (adj)\n");
5400 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5401 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5402 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5403 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5405 assem_debug("branch: internal\n");
5407 assem_debug("branch: external\n");
5408 if(internal&&is_ds[(ba[i]-start)>>2]) {
5409 ds_assemble_entry(i);
5412 add_to_linker((int)out,ba[i],internal);
5415 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5416 if(((u_int)out)&7) emit_addnop(0);
5421 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5424 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5427 int taken=0,nottaken=0,nottaken1=0;
5428 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5429 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5433 if(opcode[i]==4) // BEQ
5435 if(s2h>=0) emit_cmp(s1h,s2h);
5436 else emit_test(s1h,s1h);
5440 if(opcode[i]==5) // BNE
5442 if(s2h>=0) emit_cmp(s1h,s2h);
5443 else emit_test(s1h,s1h);
5444 if(invert) taken=(int)out;
5445 else add_to_linker((int)out,ba[i],internal);
5448 if(opcode[i]==6) // BLEZ
5451 if(invert) taken=(int)out;
5452 else add_to_linker((int)out,ba[i],internal);
5457 if(opcode[i]==7) // BGTZ
5462 if(invert) taken=(int)out;
5463 else add_to_linker((int)out,ba[i],internal);
5468 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5470 if(opcode[i]==4) // BEQ
5472 if(s2l>=0) emit_cmp(s1l,s2l);
5473 else emit_test(s1l,s1l);
5478 add_to_linker((int)out,ba[i],internal);
5482 if(opcode[i]==5) // BNE
5484 if(s2l>=0) emit_cmp(s1l,s2l);
5485 else emit_test(s1l,s1l);
5490 add_to_linker((int)out,ba[i],internal);
5494 if(opcode[i]==6) // BLEZ
5501 add_to_linker((int)out,ba[i],internal);
5505 if(opcode[i]==7) // BGTZ
5512 add_to_linker((int)out,ba[i],internal);
5517 if(taken) set_jump_target(taken,(int)out);
5518 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5519 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5521 emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5522 add_to_linker((int)out,ba[i],internal);
5525 add_to_linker((int)out,ba[i],internal*2);
5531 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5532 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5533 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5535 assem_debug("branch: internal\n");
5537 assem_debug("branch: external\n");
5538 if(internal&&is_ds[(ba[i]-start)>>2]) {
5539 ds_assemble_entry(i);
5542 add_to_linker((int)out,ba[i],internal);
5546 set_jump_target(nottaken,(int)out);
5549 if(nottaken1) set_jump_target(nottaken1,(int)out);
5551 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5553 } // (!unconditional)
5557 // In-order execution (branch first)
5558 //if(likely[i]) printf("IOL\n");
5561 int taken=0,nottaken=0,nottaken1=0;
5562 if(!unconditional&&!nop) {
5566 if((opcode[i]&0x2f)==4) // BEQ
5568 if(s2h>=0) emit_cmp(s1h,s2h);
5569 else emit_test(s1h,s1h);
5573 if((opcode[i]&0x2f)==5) // BNE
5575 if(s2h>=0) emit_cmp(s1h,s2h);
5576 else emit_test(s1h,s1h);
5580 if((opcode[i]&0x2f)==6) // BLEZ
5588 if((opcode[i]&0x2f)==7) // BGTZ
5598 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5600 if((opcode[i]&0x2f)==4) // BEQ
5602 if(s2l>=0) emit_cmp(s1l,s2l);
5603 else emit_test(s1l,s1l);
5607 if((opcode[i]&0x2f)==5) // BNE
5609 if(s2l>=0) emit_cmp(s1l,s2l);
5610 else emit_test(s1l,s1l);
5614 if((opcode[i]&0x2f)==6) // BLEZ
5620 if((opcode[i]&0x2f)==7) // BGTZ
5626 } // if(!unconditional)
5628 uint64_t ds_unneeded=branch_regs[i].u;
5629 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5630 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5631 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5632 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5634 ds_unneeded_upper|=1;
5637 if(taken) set_jump_target(taken,(int)out);
5638 assem_debug("1:\n");
5639 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5640 ds_unneeded,ds_unneeded_upper);
5642 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5643 address_generation(i+1,&branch_regs[i],0);
5644 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5645 ds_assemble(i+1,&branch_regs[i]);
5646 cc=get_reg(branch_regs[i].regmap,CCREG);
5648 emit_loadreg(CCREG,cc=HOST_CCREG);
5649 // CHECK: Is the following instruction (fall thru) allocated ok?
5651 assert(cc==HOST_CCREG);
5652 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5653 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5654 assem_debug("cycle count (adj)\n");
5655 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5656 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5658 assem_debug("branch: internal\n");
5660 assem_debug("branch: external\n");
5661 if(internal&&is_ds[(ba[i]-start)>>2]) {
5662 ds_assemble_entry(i);
5665 add_to_linker((int)out,ba[i],internal);
5670 cop1_usable=prev_cop1_usable;
5671 if(!unconditional) {
5672 if(nottaken1) set_jump_target(nottaken1,(int)out);
5673 set_jump_target(nottaken,(int)out);
5674 assem_debug("2:\n");
5676 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5677 ds_unneeded,ds_unneeded_upper);
5678 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5679 address_generation(i+1,&branch_regs[i],0);
5680 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5681 ds_assemble(i+1,&branch_regs[i]);
5683 cc=get_reg(branch_regs[i].regmap,CCREG);
5684 if(cc==-1&&!likely[i]) {
5685 // Cycle count isn't in a register, temporarily load it then write it out
5686 emit_loadreg(CCREG,HOST_CCREG);
5687 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5690 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5691 emit_storereg(CCREG,HOST_CCREG);
5694 cc=get_reg(i_regmap,CCREG);
5695 assert(cc==HOST_CCREG);
5696 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5699 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5705 void sjump_assemble(int i,struct regstat *i_regs)
5707 signed char *i_regmap=i_regs->regmap;
5710 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5711 assem_debug("smatch=%d\n",match);
5713 int prev_cop1_usable=cop1_usable;
5714 int unconditional=0,nevertaken=0;
5717 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5718 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5719 if(!match) invert=1;
5720 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5721 if(i>(ba[i]-start)>>2) invert=1;
5724 //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
5725 //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
5728 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5729 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5732 s1l=get_reg(i_regmap,rs1[i]);
5733 s1h=get_reg(i_regmap,rs1[i]|64);
5737 if(opcode2[i]&1) unconditional=1;
5739 // These are never taken (r0 is never less than zero)
5740 //assert(opcode2[i]!=0);
5741 //assert(opcode2[i]!=2);
5742 //assert(opcode2[i]!=0x10);
5743 //assert(opcode2[i]!=0x12);
5746 only32=(regs[i].was32>>rs1[i])&1;
5750 // Out of order execution (delay slot first)
5752 address_generation(i+1,i_regs,regs[i].regmap_entry);
5753 ds_assemble(i+1,i_regs);
5755 uint64_t bc_unneeded=branch_regs[i].u;
5756 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5757 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5758 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5760 bc_unneeded_upper|=1;
5761 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5762 bc_unneeded,bc_unneeded_upper);
5763 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5764 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5766 int rt,return_address;
5767 rt=get_reg(branch_regs[i].regmap,31);
5768 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5770 // Save the PC even if the branch is not taken
5771 return_address=start+i*4+8;
5772 emit_movimm(return_address,rt); // PC into link register
5774 if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5778 cc=get_reg(branch_regs[i].regmap,CCREG);
5779 assert(cc==HOST_CCREG);
5781 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5782 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5783 assem_debug("cycle count (adj)\n");
5785 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5786 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5787 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5788 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5790 assem_debug("branch: internal\n");
5792 assem_debug("branch: external\n");
5793 if(internal&&is_ds[(ba[i]-start)>>2]) {
5794 ds_assemble_entry(i);
5797 add_to_linker((int)out,ba[i],internal);
5800 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5801 if(((u_int)out)&7) emit_addnop(0);
5805 else if(nevertaken) {
5806 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5809 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5813 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5814 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5818 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5825 add_to_linker((int)out,ba[i],internal);
5829 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5836 add_to_linker((int)out,ba[i],internal);
5844 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5851 add_to_linker((int)out,ba[i],internal);
5855 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5862 add_to_linker((int)out,ba[i],internal);
5869 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5870 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5872 emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5873 add_to_linker((int)out,ba[i],internal);
5876 add_to_linker((int)out,ba[i],internal*2);
5882 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5883 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5884 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5886 assem_debug("branch: internal\n");
5888 assem_debug("branch: external\n");
5889 if(internal&&is_ds[(ba[i]-start)>>2]) {
5890 ds_assemble_entry(i);
5893 add_to_linker((int)out,ba[i],internal);
5897 set_jump_target(nottaken,(int)out);
5901 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5903 } // (!unconditional)
5907 // In-order execution (branch first)
5911 int rt,return_address;
5912 rt=get_reg(branch_regs[i].regmap,31);
5914 // Save the PC even if the branch is not taken
5915 return_address=start+i*4+8;
5916 emit_movimm(return_address,rt); // PC into link register
5918 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5922 if(!unconditional) {
5923 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5927 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
5933 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
5943 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
5949 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
5956 } // if(!unconditional)
5958 uint64_t ds_unneeded=branch_regs[i].u;
5959 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5960 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5961 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5962 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5964 ds_unneeded_upper|=1;
5967 //assem_debug("1:\n");
5968 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5969 ds_unneeded,ds_unneeded_upper);
5971 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5972 address_generation(i+1,&branch_regs[i],0);
5973 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5974 ds_assemble(i+1,&branch_regs[i]);
5975 cc=get_reg(branch_regs[i].regmap,CCREG);
5977 emit_loadreg(CCREG,cc=HOST_CCREG);
5978 // CHECK: Is the following instruction (fall thru) allocated ok?
5980 assert(cc==HOST_CCREG);
5981 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5982 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5983 assem_debug("cycle count (adj)\n");
5984 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5985 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5987 assem_debug("branch: internal\n");
5989 assem_debug("branch: external\n");
5990 if(internal&&is_ds[(ba[i]-start)>>2]) {
5991 ds_assemble_entry(i);
5994 add_to_linker((int)out,ba[i],internal);
5999 cop1_usable=prev_cop1_usable;
6000 if(!unconditional) {
6001 set_jump_target(nottaken,(int)out);
6002 assem_debug("1:\n");
6004 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6005 ds_unneeded,ds_unneeded_upper);
6006 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6007 address_generation(i+1,&branch_regs[i],0);
6008 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6009 ds_assemble(i+1,&branch_regs[i]);
6011 cc=get_reg(branch_regs[i].regmap,CCREG);
6012 if(cc==-1&&!likely[i]) {
6013 // Cycle count isn't in a register, temporarily load it then write it out
6014 emit_loadreg(CCREG,HOST_CCREG);
6015 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6018 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6019 emit_storereg(CCREG,HOST_CCREG);
6022 cc=get_reg(i_regmap,CCREG);
6023 assert(cc==HOST_CCREG);
6024 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6027 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6033 void fjump_assemble(int i,struct regstat *i_regs)
6035 signed char *i_regmap=i_regs->regmap;
6038 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6039 assem_debug("fmatch=%d\n",match);
6043 int internal=internal_branch(branch_regs[i].is32,ba[i]);
6044 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
6045 if(!match) invert=1;
6046 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6047 if(i>(ba[i]-start)>>2) invert=1;
6051 fs=get_reg(branch_regs[i].regmap,FSREG);
6052 address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
6055 fs=get_reg(i_regmap,FSREG);
6058 // Check cop1 unusable
6060 cs=get_reg(i_regmap,CSREG);
6062 emit_testimm(cs,0x20000000);
6065 add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
6070 // Out of order execution (delay slot first)
6072 ds_assemble(i+1,i_regs);
6074 uint64_t bc_unneeded=branch_regs[i].u;
6075 uint64_t bc_unneeded_upper=branch_regs[i].uu;
6076 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6077 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
6079 bc_unneeded_upper|=1;
6080 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6081 bc_unneeded,bc_unneeded_upper);
6082 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
6083 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6084 cc=get_reg(branch_regs[i].regmap,CCREG);
6085 assert(cc==HOST_CCREG);
6086 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6087 assem_debug("cycle count (adj)\n");
6090 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6093 emit_testimm(fs,0x800000);
6094 if(source[i]&0x10000) // BC1T
6100 add_to_linker((int)out,ba[i],internal);
6109 add_to_linker((int)out,ba[i],internal);
6117 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
6118 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6119 else if(match) emit_addnop(13);
6121 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6122 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6124 assem_debug("branch: internal\n");
6126 assem_debug("branch: external\n");
6127 if(internal&&is_ds[(ba[i]-start)>>2]) {
6128 ds_assemble_entry(i);
6131 add_to_linker((int)out,ba[i],internal);
6134 set_jump_target(nottaken,(int)out);
6138 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
6140 } // (!unconditional)
6144 // In-order execution (branch first)
6148 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6151 emit_testimm(fs,0x800000);
6152 if(source[i]&0x10000) // BC1T
6163 } // if(!unconditional)
6165 uint64_t ds_unneeded=branch_regs[i].u;
6166 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6167 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6168 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6169 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6171 ds_unneeded_upper|=1;
6173 //assem_debug("1:\n");
6174 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6175 ds_unneeded,ds_unneeded_upper);
6177 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6178 address_generation(i+1,&branch_regs[i],0);
6179 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6180 ds_assemble(i+1,&branch_regs[i]);
6181 cc=get_reg(branch_regs[i].regmap,CCREG);
6183 emit_loadreg(CCREG,cc=HOST_CCREG);
6184 // CHECK: Is the following instruction (fall thru) allocated ok?
6186 assert(cc==HOST_CCREG);
6187 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6188 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6189 assem_debug("cycle count (adj)\n");
6190 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6191 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6193 assem_debug("branch: internal\n");
6195 assem_debug("branch: external\n");
6196 if(internal&&is_ds[(ba[i]-start)>>2]) {
6197 ds_assemble_entry(i);
6200 add_to_linker((int)out,ba[i],internal);
6205 if(1) { // <- FIXME (don't need this)
6206 set_jump_target(nottaken,(int)out);
6207 assem_debug("1:\n");
6209 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6210 ds_unneeded,ds_unneeded_upper);
6211 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6212 address_generation(i+1,&branch_regs[i],0);
6213 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6214 ds_assemble(i+1,&branch_regs[i]);
6216 cc=get_reg(branch_regs[i].regmap,CCREG);
6217 if(cc==-1&&!likely[i]) {
6218 // Cycle count isn't in a register, temporarily load it then write it out
6219 emit_loadreg(CCREG,HOST_CCREG);
6220 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6223 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6224 emit_storereg(CCREG,HOST_CCREG);
6227 cc=get_reg(i_regmap,CCREG);
6228 assert(cc==HOST_CCREG);
6229 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6232 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6238 static void pagespan_assemble(int i,struct regstat *i_regs)
6240 int s1l=get_reg(i_regs->regmap,rs1[i]);
6241 int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6242 int s2l=get_reg(i_regs->regmap,rs2[i]);
6243 int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6244 void *nt_branch=NULL;
6247 int unconditional=0;
6257 if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6261 int addr,alt,ntaddr;
6262 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6266 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6267 (i_regs->regmap[hr]&63)!=rs1[i] &&
6268 (i_regs->regmap[hr]&63)!=rs2[i] )
6277 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6278 (i_regs->regmap[hr]&63)!=rs1[i] &&
6279 (i_regs->regmap[hr]&63)!=rs2[i] )
6285 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6289 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6290 (i_regs->regmap[hr]&63)!=rs1[i] &&
6291 (i_regs->regmap[hr]&63)!=rs2[i] )
6298 assert(hr<HOST_REGS);
6299 if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6300 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6302 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6303 if(opcode[i]==2) // J
6307 if(opcode[i]==3) // JAL
6310 int rt=get_reg(i_regs->regmap,31);
6311 emit_movimm(start+i*4+8,rt);
6314 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6317 if(opcode2[i]==9) // JALR
6319 int rt=get_reg(i_regs->regmap,rt1[i]);
6320 emit_movimm(start+i*4+8,rt);
6323 if((opcode[i]&0x3f)==4) // BEQ
6330 #ifdef HAVE_CMOV_IMM
6332 if(s2l>=0) emit_cmp(s1l,s2l);
6333 else emit_test(s1l,s1l);
6334 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6340 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6342 if(s2h>=0) emit_cmp(s1h,s2h);
6343 else emit_test(s1h,s1h);
6344 emit_cmovne_reg(alt,addr);
6346 if(s2l>=0) emit_cmp(s1l,s2l);
6347 else emit_test(s1l,s1l);
6348 emit_cmovne_reg(alt,addr);
6351 if((opcode[i]&0x3f)==5) // BNE
6353 #ifdef HAVE_CMOV_IMM
6355 if(s2l>=0) emit_cmp(s1l,s2l);
6356 else emit_test(s1l,s1l);
6357 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6363 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6365 if(s2h>=0) emit_cmp(s1h,s2h);
6366 else emit_test(s1h,s1h);
6367 emit_cmovne_reg(alt,addr);
6369 if(s2l>=0) emit_cmp(s1l,s2l);
6370 else emit_test(s1l,s1l);
6371 emit_cmovne_reg(alt,addr);
6374 if((opcode[i]&0x3f)==0x14) // BEQL
6377 if(s2h>=0) emit_cmp(s1h,s2h);
6378 else emit_test(s1h,s1h);
6382 if(s2l>=0) emit_cmp(s1l,s2l);
6383 else emit_test(s1l,s1l);
6384 if(nottaken) set_jump_target(nottaken,(int)out);
6388 if((opcode[i]&0x3f)==0x15) // BNEL
6391 if(s2h>=0) emit_cmp(s1h,s2h);
6392 else emit_test(s1h,s1h);
6396 if(s2l>=0) emit_cmp(s1l,s2l);
6397 else emit_test(s1l,s1l);
6400 if(taken) set_jump_target(taken,(int)out);
6402 if((opcode[i]&0x3f)==6) // BLEZ
6404 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6406 if(s1h>=0) emit_mov(addr,ntaddr);
6407 emit_cmovl_reg(alt,addr);
6410 emit_cmovne_reg(ntaddr,addr);
6411 emit_cmovs_reg(alt,addr);
6414 if((opcode[i]&0x3f)==7) // BGTZ
6416 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6418 if(s1h>=0) emit_mov(addr,alt);
6419 emit_cmovl_reg(ntaddr,addr);
6422 emit_cmovne_reg(alt,addr);
6423 emit_cmovs_reg(ntaddr,addr);
6426 if((opcode[i]&0x3f)==0x16) // BLEZL
6428 assert((opcode[i]&0x3f)!=0x16);
6430 if((opcode[i]&0x3f)==0x17) // BGTZL
6432 assert((opcode[i]&0x3f)!=0x17);
6434 assert(opcode[i]!=1); // BLTZ/BGEZ
6436 //FIXME: Check CSREG
6437 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6438 if((source[i]&0x30000)==0) // BC1F
6440 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6441 emit_testimm(s1l,0x800000);
6442 emit_cmovne_reg(alt,addr);
6444 if((source[i]&0x30000)==0x10000) // BC1T
6446 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6447 emit_testimm(s1l,0x800000);
6448 emit_cmovne_reg(alt,addr);
6450 if((source[i]&0x30000)==0x20000) // BC1FL
6452 emit_testimm(s1l,0x800000);
6456 if((source[i]&0x30000)==0x30000) // BC1TL
6458 emit_testimm(s1l,0x800000);
6464 assert(i_regs->regmap[HOST_CCREG]==CCREG);
6465 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6466 if(likely[i]||unconditional)
6468 emit_movimm(ba[i],HOST_BTREG);
6470 else if(addr!=HOST_BTREG)
6472 emit_mov(addr,HOST_BTREG);
6474 void *branch_addr=out;
6476 int target_addr=start+i*4+5;
6478 void *compiled_target_addr=check_addr(target_addr);
6479 emit_extjump_ds((int)branch_addr,target_addr);
6480 if(compiled_target_addr) {
6481 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6482 add_link(target_addr,stub);
6484 else set_jump_target((int)branch_addr,(int)stub);
6487 set_jump_target((int)nottaken,(int)out);
6488 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6489 void *branch_addr=out;
6491 int target_addr=start+i*4+8;
6493 void *compiled_target_addr=check_addr(target_addr);
6494 emit_extjump_ds((int)branch_addr,target_addr);
6495 if(compiled_target_addr) {
6496 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6497 add_link(target_addr,stub);
6499 else set_jump_target((int)branch_addr,(int)stub);
6503 // Assemble the delay slot for the above
6504 static void pagespan_ds()
6506 assem_debug("initial delay slot:\n");
6507 u_int vaddr=start+1;
6508 u_int page=get_page(vaddr);
6509 u_int vpage=get_vpage(vaddr);
6510 ll_add(jump_dirty+vpage,vaddr,(void *)out);
6512 ll_add(jump_in+page,vaddr,(void *)out);
6513 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6514 if(regs[0].regmap[HOST_CCREG]!=CCREG)
6515 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6516 if(regs[0].regmap[HOST_BTREG]!=BTREG)
6517 emit_writeword(HOST_BTREG,(int)&branch_target);
6518 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6519 address_generation(0,®s[0],regs[0].regmap_entry);
6520 if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
6521 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6526 alu_assemble(0,®s[0]);break;
6528 imm16_assemble(0,®s[0]);break;
6530 shift_assemble(0,®s[0]);break;
6532 shiftimm_assemble(0,®s[0]);break;
6534 load_assemble(0,®s[0]);break;
6536 loadlr_assemble(0,®s[0]);break;
6538 store_assemble(0,®s[0]);break;
6540 storelr_assemble(0,®s[0]);break;
6542 cop0_assemble(0,®s[0]);break;
6544 cop1_assemble(0,®s[0]);break;
6546 c1ls_assemble(0,®s[0]);break;
6548 cop2_assemble(0,®s[0]);break;
6550 c2ls_assemble(0,®s[0]);break;
6552 c2op_assemble(0,®s[0]);break;
6554 fconv_assemble(0,®s[0]);break;
6556 float_assemble(0,®s[0]);break;
6558 fcomp_assemble(0,®s[0]);break;
6560 multdiv_assemble(0,®s[0]);break;
6562 mov_assemble(0,®s[0]);break;
6572 printf("Jump in the delay slot. This is probably a bug.\n");
6574 int btaddr=get_reg(regs[0].regmap,BTREG);
6576 btaddr=get_reg(regs[0].regmap,-1);
6577 emit_readword((int)&branch_target,btaddr);
6579 assert(btaddr!=HOST_CCREG);
6580 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6582 emit_movimm(start+4,HOST_TEMPREG);
6583 emit_cmp(btaddr,HOST_TEMPREG);
6585 emit_cmpimm(btaddr,start+4);
6587 int branch=(int)out;
6589 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6590 emit_jmp(jump_vaddr_reg[btaddr]);
6591 set_jump_target(branch,(int)out);
6592 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6593 load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6596 // Basic liveness analysis for MIPS registers
6597 void unneeded_registers(int istart,int iend,int r)
6601 uint64_t temp_u,temp_uu;
6606 u=unneeded_reg[iend+1];
6607 uu=unneeded_reg_upper[iend+1];
6610 for (i=iend;i>=istart;i--)
6612 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6613 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6615 // If subroutine call, flag return address as a possible branch target
6616 if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6618 if(ba[i]<start || ba[i]>=(start+slen*4))
6620 // Branch out of this block, flush all regs
6624 if(itype[i]==UJUMP&&rt1[i]==31)
6626 uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6628 if(itype[i]==RJUMP&&rs1[i]==31)
6630 uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6632 if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
6633 if(itype[i]==UJUMP&&rt1[i]==31)
6635 //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6636 uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6638 if(itype[i]==RJUMP&&rs1[i]==31)
6640 //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6641 uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6644 branch_unneeded_reg[i]=u;
6645 branch_unneeded_reg_upper[i]=uu;
6646 // Merge in delay slot
6647 tdep=(~uu>>rt1[i+1])&1;
6648 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6649 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6650 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6651 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6652 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6654 // If branch is "likely" (and conditional)
6655 // then we skip the delay slot on the fall-thru path
6658 u&=unneeded_reg[i+2];
6659 uu&=unneeded_reg_upper[i+2];
6670 // Internal branch, flag target
6671 bt[(ba[i]-start)>>2]=1;
6672 if(ba[i]<=start+i*4) {
6674 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6676 // Unconditional branch
6679 // Conditional branch (not taken case)
6680 temp_u=unneeded_reg[i+2];
6681 temp_uu=unneeded_reg_upper[i+2];
6683 // Merge in delay slot
6684 tdep=(~temp_uu>>rt1[i+1])&1;
6685 temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6686 temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6687 temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6688 temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6689 temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6690 temp_u|=1;temp_uu|=1;
6691 // If branch is "likely" (and conditional)
6692 // then we skip the delay slot on the fall-thru path
6695 temp_u&=unneeded_reg[i+2];
6696 temp_uu&=unneeded_reg_upper[i+2];
6704 tdep=(~temp_uu>>rt1[i])&1;
6705 temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6706 temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6707 temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6708 temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6709 temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6710 temp_u|=1;temp_uu|=1;
6711 unneeded_reg[i]=temp_u;
6712 unneeded_reg_upper[i]=temp_uu;
6713 // Only go three levels deep. This recursion can take an
6714 // excessive amount of time if there are a lot of nested loops.
6716 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6718 unneeded_reg[(ba[i]-start)>>2]=1;
6719 unneeded_reg_upper[(ba[i]-start)>>2]=1;
6722 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6724 // Unconditional branch
6725 u=unneeded_reg[(ba[i]-start)>>2];
6726 uu=unneeded_reg_upper[(ba[i]-start)>>2];
6727 branch_unneeded_reg[i]=u;
6728 branch_unneeded_reg_upper[i]=uu;
6731 //branch_unneeded_reg[i]=u;
6732 //branch_unneeded_reg_upper[i]=uu;
6733 // Merge in delay slot
6734 tdep=(~uu>>rt1[i+1])&1;
6735 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6736 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6737 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6738 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6739 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6742 // Conditional branch
6743 b=unneeded_reg[(ba[i]-start)>>2];
6744 bu=unneeded_reg_upper[(ba[i]-start)>>2];
6745 branch_unneeded_reg[i]=b;
6746 branch_unneeded_reg_upper[i]=bu;
6749 //branch_unneeded_reg[i]=b;
6750 //branch_unneeded_reg_upper[i]=bu;
6751 // Branch delay slot
6752 tdep=(~uu>>rt1[i+1])&1;
6753 b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6754 bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6755 b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6756 bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6757 bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6759 // If branch is "likely" then we skip the
6760 // delay slot on the fall-thru path
6765 u&=unneeded_reg[i+2];
6766 uu&=unneeded_reg_upper[i+2];
6777 branch_unneeded_reg[i]&=unneeded_reg[i+2];
6778 branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6779 //branch_unneeded_reg[i]=1;
6780 //branch_unneeded_reg_upper[i]=1;
6782 branch_unneeded_reg[i]=1;
6783 branch_unneeded_reg_upper[i]=1;
6789 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
6791 // SYSCALL instruction (software interrupt)
6795 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6797 // ERET instruction (return from interrupt)
6802 tdep=(~uu>>rt1[i])&1;
6803 // Written registers are unneeded
6808 // Accessed registers are needed
6813 // Source-target dependencies
6814 uu&=~(tdep<<dep1[i]);
6815 uu&=~(tdep<<dep2[i]);
6816 // R0 is always unneeded
6820 unneeded_reg_upper[i]=uu;
6822 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6825 for(r=1;r<=CCREG;r++) {
6826 if((unneeded_reg[i]>>r)&1) {
6827 if(r==HIREG) printf(" HI");
6828 else if(r==LOREG) printf(" LO");
6829 else printf(" r%d",r);
6833 for(r=1;r<=CCREG;r++) {
6834 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
6835 if(r==HIREG) printf(" HI");
6836 else if(r==LOREG) printf(" LO");
6837 else printf(" r%d",r);
6843 for (i=iend;i>=istart;i--)
6845 unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
6850 // Identify registers which are likely to contain 32-bit values
6851 // This is used to predict whether any branches will jump to a
6852 // location with 64-bit values in registers.
6853 static void provisional_32bit()
6857 uint64_t lastbranch=1;
6862 if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
6863 if(i>1) is32=lastbranch;
6869 if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
6871 if(i>2) is32=lastbranch;
6875 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
6877 if(rs1[i-2]==0||rs2[i-2]==0)
6880 is32|=1LL<<rs1[i-2];
6883 is32|=1LL<<rs2[i-2];
6888 // If something jumps here with 64-bit values
6889 // then promote those registers to 64 bits
6892 uint64_t temp_is32=is32;
6895 if(ba[j]==start+i*4)
6896 //temp_is32&=branch_regs[j].is32;
6901 if(ba[j]==start+i*4)
6912 if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
6913 // Branches don't write registers, consider the delay slot instead.
6924 if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
6925 opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
6934 if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
6935 if(op==0x22) is32|=1LL<<rt; // LWL
6938 if (op==0x08||op==0x09|| // ADDI/ADDIU
6939 op==0x0a||op==0x0b|| // SLTI/SLTIU
6945 if(op==0x18||op==0x19) { // DADDI/DADDIU
6948 // is32|=((is32>>s1)&1LL)<<rt;
6950 if(op==0x0d||op==0x0e) { // ORI/XORI
6951 uint64_t sr=((is32>>s1)&1LL);
6967 if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
6970 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
6973 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
6974 uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
6978 else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
6983 uint64_t sr=((is32>>s1)&1LL);
6988 uint64_t sr=((is32>>s2)&1LL);
6996 else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
7001 uint64_t sr=((is32>>s1)&1LL);
7011 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
7012 is32&=~((1LL<<HIREG)|(1LL<<LOREG));
7015 is32|=(1LL<<HIREG)|(1LL<<LOREG);
7020 uint64_t sr=((is32>>s1)&1LL);
7026 if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
7027 else is32|=1LL<<rt; // SLLV/SRLV/SRAV
7031 // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
7032 if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
7035 if(op2==0) is32|=1LL<<rt; // MFC0
7039 if(op2==0) is32|=1LL<<rt; // MFC1
7040 if(op2==1) is32&=~(1LL<<rt); // DMFC1
7041 if(op2==2) is32|=1LL<<rt; // CFC1
7063 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
7065 if(rt1[i-1]==31) // JAL/JALR
7067 // Subroutine call will return here, don't alloc any registers
7072 // Internal branch will jump here, match registers to caller
7080 // Identify registers which may be assumed to contain 32-bit values
7081 // and where optimizations will rely on this.
7082 // This is used to determine whether backward branches can safely
7083 // jump to a location with 64-bit values in registers.
7084 static void provisional_r32()
7089 for (i=slen-1;i>=0;i--)
7092 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7094 if(ba[i]<start || ba[i]>=(start+slen*4))
7096 // Branch out of this block, don't need anything
7102 // Need whatever matches the target
7103 // (and doesn't get overwritten by the delay slot instruction)
7105 int t=(ba[i]-start)>>2;
7106 if(ba[i]>start+i*4) {
7108 //if(!(requires_32bit[t]&~regs[i].was32))
7109 // r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7110 if(!(pr32[t]&~regs[i].was32))
7111 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7114 if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
7115 r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7118 // Conditional branch may need registers for following instructions
7119 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7122 //r32|=requires_32bit[i+2];
7125 // Mark this address as a branch target since it may be called
7126 // upon return from interrupt
7130 // Merge in delay slot
7132 // These are overwritten unless the branch is "likely"
7133 // and the delay slot is nullified if not taken
7134 r32&=~(1LL<<rt1[i+1]);
7135 r32&=~(1LL<<rt2[i+1]);
7137 // Assume these are needed (delay slot)
7140 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7144 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7146 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7148 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7150 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7152 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7155 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7157 // SYSCALL instruction (software interrupt)
7160 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7162 // ERET instruction (return from interrupt)
7166 r32&=~(1LL<<rt1[i]);
7167 r32&=~(1LL<<rt2[i]);
7170 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7174 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7176 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7178 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7180 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7182 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7184 //requires_32bit[i]=r32;
7187 // Dirty registers which are 32-bit, require 32-bit input
7188 // as they will be written as 32-bit values
7189 for(hr=0;hr<HOST_REGS;hr++)
7191 if(regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64) {
7192 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7193 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7194 pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7195 //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7202 // Write back dirty registers as soon as we will no longer modify them,
7203 // so that we don't end up with lots of writes at the branches.
7204 void clean_registers(int istart,int iend,int wr)
7208 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7209 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7211 will_dirty_i=will_dirty_next=0;
7212 wont_dirty_i=wont_dirty_next=0;
7214 will_dirty_i=will_dirty_next=will_dirty[iend+1];
7215 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7217 for (i=iend;i>=istart;i--)
7219 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7221 if(ba[i]<start || ba[i]>=(start+slen*4))
7223 // Branch out of this block, flush all regs
7224 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7226 // Unconditional branch
7229 // Merge in delay slot (will dirty)
7230 for(r=0;r<HOST_REGS;r++) {
7231 if(r!=EXCLUDE_REG) {
7232 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7233 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7234 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7235 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7236 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7237 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7238 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7239 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7240 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7241 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7242 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7243 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7244 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7245 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7251 // Conditional branch
7253 wont_dirty_i=wont_dirty_next;
7254 // Merge in delay slot (will dirty)
7255 for(r=0;r<HOST_REGS;r++) {
7256 if(r!=EXCLUDE_REG) {
7258 // Might not dirty if likely branch is not taken
7259 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7260 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7261 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7262 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7263 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7264 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7265 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7266 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7267 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7268 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7269 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7270 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7271 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7272 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7277 // Merge in delay slot (wont dirty)
7278 for(r=0;r<HOST_REGS;r++) {
7279 if(r!=EXCLUDE_REG) {
7280 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7281 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7282 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7283 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7284 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7285 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7286 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7287 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7288 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7289 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7293 #ifndef DESTRUCTIVE_WRITEBACK
7294 branch_regs[i].dirty&=wont_dirty_i;
7296 branch_regs[i].dirty|=will_dirty_i;
7302 if(ba[i]<=start+i*4) {
7304 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7306 // Unconditional branch
7309 // Merge in delay slot (will dirty)
7310 for(r=0;r<HOST_REGS;r++) {
7311 if(r!=EXCLUDE_REG) {
7312 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7313 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7314 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7315 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7316 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7317 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7318 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7319 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7320 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7321 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7322 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7323 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7324 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7325 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7329 // Conditional branch (not taken case)
7330 temp_will_dirty=will_dirty_next;
7331 temp_wont_dirty=wont_dirty_next;
7332 // Merge in delay slot (will dirty)
7333 for(r=0;r<HOST_REGS;r++) {
7334 if(r!=EXCLUDE_REG) {
7336 // Will not dirty if likely branch is not taken
7337 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7338 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7339 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7340 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7341 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7342 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7343 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7344 //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7345 //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7346 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7347 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7348 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7349 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7350 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7355 // Merge in delay slot (wont dirty)
7356 for(r=0;r<HOST_REGS;r++) {
7357 if(r!=EXCLUDE_REG) {
7358 if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7359 if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7360 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7361 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7362 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7363 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7364 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7365 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7366 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7367 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7370 // Deal with changed mappings
7372 for(r=0;r<HOST_REGS;r++) {
7373 if(r!=EXCLUDE_REG) {
7374 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7375 temp_will_dirty&=~(1<<r);
7376 temp_wont_dirty&=~(1<<r);
7377 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7378 temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7379 temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7381 temp_will_dirty|=1<<r;
7382 temp_wont_dirty|=1<<r;
7389 will_dirty[i]=temp_will_dirty;
7390 wont_dirty[i]=temp_wont_dirty;
7391 clean_registers((ba[i]-start)>>2,i-1,0);
7393 // Limit recursion. It can take an excessive amount
7394 // of time if there are a lot of nested loops.
7395 will_dirty[(ba[i]-start)>>2]=0;
7396 wont_dirty[(ba[i]-start)>>2]=-1;
7401 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7403 // Unconditional branch
7406 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7407 for(r=0;r<HOST_REGS;r++) {
7408 if(r!=EXCLUDE_REG) {
7409 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7410 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7411 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7416 // Merge in delay slot
7417 for(r=0;r<HOST_REGS;r++) {
7418 if(r!=EXCLUDE_REG) {
7419 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7420 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7421 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7422 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7423 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7424 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7425 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7426 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7427 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7428 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7429 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7430 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7431 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7432 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7436 // Conditional branch
7437 will_dirty_i=will_dirty_next;
7438 wont_dirty_i=wont_dirty_next;
7439 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7440 for(r=0;r<HOST_REGS;r++) {
7441 if(r!=EXCLUDE_REG) {
7442 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7443 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7444 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7448 will_dirty_i&=~(1<<r);
7450 // Treat delay slot as part of branch too
7451 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7452 will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7453 wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7457 will_dirty[i+1]&=~(1<<r);
7462 // Merge in delay slot
7463 for(r=0;r<HOST_REGS;r++) {
7464 if(r!=EXCLUDE_REG) {
7466 // Might not dirty if likely branch is not taken
7467 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7468 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7469 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7470 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7471 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7472 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7473 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7474 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7475 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7476 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7477 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7478 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7479 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7480 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7485 // Merge in delay slot
7486 for(r=0;r<HOST_REGS;r++) {
7487 if(r!=EXCLUDE_REG) {
7488 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7489 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7490 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7491 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7492 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7493 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7494 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7495 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7496 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7497 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7501 #ifndef DESTRUCTIVE_WRITEBACK
7502 branch_regs[i].dirty&=wont_dirty_i;
7504 branch_regs[i].dirty|=will_dirty_i;
7509 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7511 // SYSCALL instruction (software interrupt)
7515 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7517 // ERET instruction (return from interrupt)
7521 will_dirty_next=will_dirty_i;
7522 wont_dirty_next=wont_dirty_i;
7523 for(r=0;r<HOST_REGS;r++) {
7524 if(r!=EXCLUDE_REG) {
7525 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7526 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7527 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7528 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7529 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7530 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7531 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7532 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7534 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7536 // Don't store a register immediately after writing it,
7537 // may prevent dual-issue.
7538 if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7539 if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7545 will_dirty[i]=will_dirty_i;
7546 wont_dirty[i]=wont_dirty_i;
7547 // Mark registers that won't be dirtied as not dirty
7549 /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7550 for(r=0;r<HOST_REGS;r++) {
7551 if((will_dirty_i>>r)&1) {
7557 //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7558 regs[i].dirty|=will_dirty_i;
7559 #ifndef DESTRUCTIVE_WRITEBACK
7560 regs[i].dirty&=wont_dirty_i;
7561 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7563 if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7564 for(r=0;r<HOST_REGS;r++) {
7565 if(r!=EXCLUDE_REG) {
7566 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7567 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7568 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7576 for(r=0;r<HOST_REGS;r++) {
7577 if(r!=EXCLUDE_REG) {
7578 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7579 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7580 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7588 // Deal with changed mappings
7589 temp_will_dirty=will_dirty_i;
7590 temp_wont_dirty=wont_dirty_i;
7591 for(r=0;r<HOST_REGS;r++) {
7592 if(r!=EXCLUDE_REG) {
7594 if(regs[i].regmap[r]==regmap_pre[i][r]) {
7596 #ifndef DESTRUCTIVE_WRITEBACK
7597 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7599 regs[i].wasdirty|=will_dirty_i&(1<<r);
7602 else if((nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7603 // Register moved to a different register
7604 will_dirty_i&=~(1<<r);
7605 wont_dirty_i&=~(1<<r);
7606 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7607 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7609 #ifndef DESTRUCTIVE_WRITEBACK
7610 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7612 regs[i].wasdirty|=will_dirty_i&(1<<r);
7616 will_dirty_i&=~(1<<r);
7617 wont_dirty_i&=~(1<<r);
7618 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7619 will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7620 wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7623 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7632 void disassemble_inst(int i)
7634 if (bt[i]) printf("*"); else printf(" ");
7637 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7639 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7641 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7643 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7645 if (opcode[i]==0x9&&rt1[i]!=31)
7646 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7648 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7651 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7653 if(opcode[i]==0xf) //LUI
7654 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7656 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7660 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7664 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7668 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7671 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7674 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7677 if((opcode2[i]&0x1d)==0x10)
7678 printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7679 else if((opcode2[i]&0x1d)==0x11)
7680 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7682 printf (" %x: %s\n",start+i*4,insn[i]);
7686 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7687 else if(opcode2[i]==4)
7688 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7689 else printf (" %x: %s\n",start+i*4,insn[i]);
7693 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7694 else if(opcode2[i]>3)
7695 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7696 else printf (" %x: %s\n",start+i*4,insn[i]);
7700 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7701 else if(opcode2[i]>3)
7702 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7703 else printf (" %x: %s\n",start+i*4,insn[i]);
7706 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7709 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7712 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
7715 //printf (" %s %8x\n",insn[i],source[i]);
7716 printf (" %x: %s\n",start+i*4,insn[i]);
7720 // clear the state completely, instead of just marking
7721 // things invalid like invalidate_all_pages() does
7722 void new_dynarec_clear_full()
7725 for(n=0x80000;n<0x80800;n++)
7727 for(n=0;n<65536;n++)
7728 hash_table[n][0]=hash_table[n][2]=-1;
7729 memset(mini_ht,-1,sizeof(mini_ht));
7730 memset(restore_candidate,0,sizeof(restore_candidate));
7731 memset(shadow,0,sizeof(shadow));
7733 expirep=16384; // Expiry pointer, +2 blocks
7734 pending_exception=0;
7741 for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7743 for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7744 memory_map[n]=((u_int)rdram-0x80000000)>>2;
7745 for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7747 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7748 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7749 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7752 void new_dynarec_init()
7754 printf("Init new dynarec\n");
7755 out=(u_char *)BASE_ADDR;
7756 if (mmap (out, 1<<TARGET_SIZE_2,
7757 PROT_READ | PROT_WRITE | PROT_EXEC,
7758 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
7759 -1, 0) <= 0) {printf("mmap() failed\n");}
7761 rdword=&readmem_dword;
7762 fake_pc.f.r.rs=&readmem_dword;
7763 fake_pc.f.r.rt=&readmem_dword;
7764 fake_pc.f.r.rd=&readmem_dword;
7767 new_dynarec_clear_full();
7769 // Copy this into local area so we don't have to put it in every literal pool
7770 invc_ptr=invalid_code;
7773 for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
7774 writemem[n] = write_nomem_new;
7775 writememb[n] = write_nomemb_new;
7776 writememh[n] = write_nomemh_new;
7778 writememd[n] = write_nomemd_new;
7780 readmem[n] = read_nomem_new;
7781 readmemb[n] = read_nomemb_new;
7782 readmemh[n] = read_nomemh_new;
7784 readmemd[n] = read_nomemd_new;
7787 for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
7788 writemem[n] = write_rdram_new;
7789 writememb[n] = write_rdramb_new;
7790 writememh[n] = write_rdramh_new;
7792 writememd[n] = write_rdramd_new;
7795 for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
7796 writemem[n] = write_nomem_new;
7797 writememb[n] = write_nomemb_new;
7798 writememh[n] = write_nomemh_new;
7800 writememd[n] = write_nomemd_new;
7802 readmem[n] = read_nomem_new;
7803 readmemb[n] = read_nomemb_new;
7804 readmemh[n] = read_nomemh_new;
7806 readmemd[n] = read_nomemd_new;
7814 void new_dynarec_cleanup()
7817 if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
7818 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7819 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7820 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7822 if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
7826 int new_recompile_block(int addr)
7829 if(addr==0x800cd050) {
7831 for(block=0x80000;block<0x80800;block++) invalidate_block(block);
7833 for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
7836 //if(Count==365117028) tracedebug=1;
7837 assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7838 //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7839 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
7841 //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
7842 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
7843 /*if(Count>=312978186) {
7847 start = (u_int)addr&~3;
7848 //assert(((u_int)addr&1)==0);
7850 if (Config.HLE && start == 0x80001000) // hlecall
7852 // XXX: is this enough? Maybe check hleSoftCall?
7853 u_int beginning=(u_int)out;
7854 u_int page=get_page(start);
7855 invalid_code[start>>12]=0;
7856 emit_movimm(start,0);
7857 emit_writeword(0,(int)&pcaddr);
7858 emit_jmp((int)new_dyna_leave);
7860 __clear_cache((void *)beginning,out);
7862 ll_add(jump_in+page,start,(void *)beginning);
7865 else if ((u_int)addr < 0x00200000 ||
7866 (0xa0000000 <= addr && addr < 0xa0200000)) {
7867 // used for BIOS calls mostly?
7868 source = (u_int *)((u_int)rdram+(start&0x1fffff));
7869 pagelimit = (addr&0xa0000000)|0x00200000;
7871 else if (!Config.HLE && (
7872 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
7873 (0xbfc00000 <= addr && addr < 0xbfc80000))) {
7875 source = (u_int *)((u_int)psxR+(start&0x7ffff));
7876 pagelimit = (addr&0xfff00000)|0x80000;
7881 if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
7882 source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
7883 pagelimit = 0xa4001000;
7887 if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
7888 source = (u_int *)((u_int)rdram+start-0x80000000);
7889 pagelimit = 0x80000000+RAM_SIZE;
7892 else if ((signed int)addr >= (signed int)0xC0000000) {
7893 //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
7894 //if(tlb_LUT_r[start>>12])
7895 //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
7896 if((signed int)memory_map[start>>12]>=0) {
7897 source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
7898 pagelimit=(start+4096)&0xFFFFF000;
7899 int map=memory_map[start>>12];
7902 //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
7903 if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
7905 assem_debug("pagelimit=%x\n",pagelimit);
7906 assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
7909 assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
7910 //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
7911 return -1; // Caller will invoke exception handler
7913 //printf("source= %x\n",(int)source);
7917 printf("Compile at bogus memory address: %x \n", (int)addr);
7921 /* Pass 1: disassemble */
7922 /* Pass 2: register dependencies, branch targets */
7923 /* Pass 3: register allocation */
7924 /* Pass 4: branch dependencies */
7925 /* Pass 5: pre-alloc */
7926 /* Pass 6: optimize clean/dirty state */
7927 /* Pass 7: flag 32-bit registers */
7928 /* Pass 8: assembly */
7929 /* Pass 9: linker */
7930 /* Pass 10: garbage collection / free memory */
7934 unsigned int type,op,op2;
7936 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
7938 /* Pass 1 disassembly */
7940 for(i=0;!done;i++) {
7941 bt[i]=0;likely[i]=0;ooo[i]=0;op2=0;
7942 minimum_free_regs[i]=0;
7943 opcode[i]=op=source[i]>>26;
7946 case 0x00: strcpy(insn[i],"special"); type=NI;
7950 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
7951 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
7952 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
7953 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
7954 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
7955 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
7956 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
7957 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
7958 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
7959 case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
7960 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
7961 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
7962 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
7963 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
7964 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
7965 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
7966 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
7967 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
7968 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
7969 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
7970 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
7971 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
7972 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
7973 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
7974 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
7975 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
7976 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
7977 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
7978 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
7979 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
7980 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
7981 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
7982 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
7983 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
7984 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
7985 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
7986 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
7987 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
7988 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
7989 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
7990 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
7991 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
7992 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
7993 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
7994 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
7995 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
7996 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
7997 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
7998 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
7999 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
8000 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
8001 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
8004 case 0x01: strcpy(insn[i],"regimm"); type=NI;
8005 op2=(source[i]>>16)&0x1f;
8008 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
8009 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
8010 case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
8011 case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
8012 case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
8013 case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
8014 case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
8015 case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
8016 case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
8017 case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
8018 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
8019 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
8020 case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
8021 case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
8024 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
8025 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
8026 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
8027 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
8028 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
8029 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
8030 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
8031 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
8032 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
8033 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
8034 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
8035 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
8036 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
8037 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
8038 case 0x10: strcpy(insn[i],"cop0"); type=NI;
8039 op2=(source[i]>>21)&0x1f;
8042 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
8043 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
8044 case 0x10: strcpy(insn[i],"tlb"); type=NI;
8045 switch(source[i]&0x3f)
8047 case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
8048 case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
8049 case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
8050 case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
8052 case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
8054 case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
8059 case 0x11: strcpy(insn[i],"cop1"); type=NI;
8060 op2=(source[i]>>21)&0x1f;
8063 case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
8064 case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
8065 case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
8066 case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
8067 case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
8068 case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
8069 case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
8070 switch((source[i]>>16)&0x3)
8072 case 0x00: strcpy(insn[i],"BC1F"); break;
8073 case 0x01: strcpy(insn[i],"BC1T"); break;
8074 case 0x02: strcpy(insn[i],"BC1FL"); break;
8075 case 0x03: strcpy(insn[i],"BC1TL"); break;
8078 case 0x10: strcpy(insn[i],"C1.S"); type=NI;
8079 switch(source[i]&0x3f)
8081 case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
8082 case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
8083 case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
8084 case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
8085 case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
8086 case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
8087 case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
8088 case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
8089 case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
8090 case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
8091 case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
8092 case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
8093 case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
8094 case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
8095 case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
8096 case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
8097 case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
8098 case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
8099 case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
8100 case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
8101 case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
8102 case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
8103 case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
8104 case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
8105 case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
8106 case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
8107 case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
8108 case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
8109 case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
8110 case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
8111 case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
8112 case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
8113 case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
8114 case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
8115 case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
8118 case 0x11: strcpy(insn[i],"C1.D"); type=NI;
8119 switch(source[i]&0x3f)
8121 case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
8122 case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
8123 case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
8124 case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
8125 case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
8126 case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
8127 case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
8128 case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
8129 case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
8130 case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
8131 case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
8132 case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
8133 case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
8134 case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
8135 case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
8136 case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
8137 case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
8138 case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
8139 case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
8140 case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
8141 case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
8142 case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
8143 case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
8144 case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
8145 case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
8146 case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
8147 case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
8148 case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
8149 case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
8150 case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
8151 case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8152 case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8153 case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8154 case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8155 case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8158 case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8159 switch(source[i]&0x3f)
8161 case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8162 case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8165 case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8166 switch(source[i]&0x3f)
8168 case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8169 case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8175 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8176 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8177 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8178 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8179 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8180 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8181 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8182 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
8184 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8185 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8186 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8187 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8188 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8189 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8190 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
8191 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
8192 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8193 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8194 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8195 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
8197 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8198 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
8200 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8201 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8202 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8203 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
8205 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8206 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8207 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
8209 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8210 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
8212 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8213 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8214 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
8217 case 0x12: strcpy(insn[i],"COP2"); type=NI;
8218 // note: COP MIPS-1 encoding differs from MIPS32
8219 op2=(source[i]>>21)&0x1f;
8220 if (source[i]&0x3f) {
8221 if (gte_handlers[source[i]&0x3f]!=NULL) {
8222 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8228 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8229 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8230 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8231 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
8234 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8235 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8236 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8238 default: strcpy(insn[i],"???"); type=NI;
8239 printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
8243 /* detect branch in delay slot early */
8244 if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
8245 opcode[i+1]=source[i+1]>>26;
8246 opcode2[i+1]=source[i+1]&0x3f;
8247 if((0<opcode[i+1]&&opcode[i+1]<8)||(opcode[i+1]==0&&(opcode2[i+1]==8||opcode2[i+1]==9))) {
8248 printf("branch in delay slot @%08x (%08x)\n", addr + i*4+4, addr);
8249 // don't handle first branch and call interpreter if it's hit
8256 /* Get registers/immediates */
8264 rs1[i]=(source[i]>>21)&0x1f;
8266 rt1[i]=(source[i]>>16)&0x1f;
8268 imm[i]=(short)source[i];
8272 rs1[i]=(source[i]>>21)&0x1f;
8273 rs2[i]=(source[i]>>16)&0x1f;
8276 imm[i]=(short)source[i];
8277 if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8280 // LWL/LWR only load part of the register,
8281 // therefore the target register must be treated as a source too
8282 rs1[i]=(source[i]>>21)&0x1f;
8283 rs2[i]=(source[i]>>16)&0x1f;
8284 rt1[i]=(source[i]>>16)&0x1f;
8286 imm[i]=(short)source[i];
8287 if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8288 if(op==0x26) dep1[i]=rt1[i]; // LWR
8291 if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8292 else rs1[i]=(source[i]>>21)&0x1f;
8294 rt1[i]=(source[i]>>16)&0x1f;
8296 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8297 imm[i]=(unsigned short)source[i];
8299 imm[i]=(short)source[i];
8301 if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8302 if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8303 if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8310 // The JAL instruction writes to r31.
8317 rs1[i]=(source[i]>>21)&0x1f;
8321 // The JALR instruction writes to rd.
8323 rt1[i]=(source[i]>>11)&0x1f;
8328 rs1[i]=(source[i]>>21)&0x1f;
8329 rs2[i]=(source[i]>>16)&0x1f;
8332 if(op&2) { // BGTZ/BLEZ
8340 rs1[i]=(source[i]>>21)&0x1f;
8345 if(op2&0x10) { // BxxAL
8347 // NOTE: If the branch is not taken, r31 is still overwritten
8349 likely[i]=(op2&2)>>1;
8356 likely[i]=((source[i])>>17)&1;
8359 rs1[i]=(source[i]>>21)&0x1f; // source
8360 rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8361 rt1[i]=(source[i]>>11)&0x1f; // destination
8363 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8364 us1[i]=rs1[i];us2[i]=rs2[i];
8366 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8367 dep1[i]=rs1[i];dep2[i]=rs2[i];
8369 else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8370 dep1[i]=rs1[i];dep2[i]=rs2[i];
8374 rs1[i]=(source[i]>>21)&0x1f; // source
8375 rs2[i]=(source[i]>>16)&0x1f; // divisor
8378 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8379 us1[i]=rs1[i];us2[i]=rs2[i];
8387 if(op2==0x10) rs1[i]=HIREG; // MFHI
8388 if(op2==0x11) rt1[i]=HIREG; // MTHI
8389 if(op2==0x12) rs1[i]=LOREG; // MFLO
8390 if(op2==0x13) rt1[i]=LOREG; // MTLO
8391 if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8392 if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8396 rs1[i]=(source[i]>>16)&0x1f; // target of shift
8397 rs2[i]=(source[i]>>21)&0x1f; // shift amount
8398 rt1[i]=(source[i]>>11)&0x1f; // destination
8400 // DSLLV/DSRLV/DSRAV are 64-bit
8401 if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8404 rs1[i]=(source[i]>>16)&0x1f;
8406 rt1[i]=(source[i]>>11)&0x1f;
8408 imm[i]=(source[i]>>6)&0x1f;
8409 // DSxx32 instructions
8410 if(op2>=0x3c) imm[i]|=0x20;
8411 // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8412 if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8419 if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8420 if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8421 if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8422 if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8430 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8431 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8432 if(op2==5) us1[i]=rs1[i]; // DMTC1
8436 rs1[i]=(source[i]>>21)&0x1F;
8440 imm[i]=(short)source[i];
8443 rs1[i]=(source[i]>>21)&0x1F;
8447 imm[i]=(short)source[i];
8476 /* Calculate branch target addresses */
8478 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8479 else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8480 ba[i]=start+i*4+8; // Ignore never taken branch
8481 else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8482 ba[i]=start+i*4+8; // Ignore never taken branch
8483 else if(type==CJUMP||type==SJUMP||type==FJUMP)
8484 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8486 /* Is this the end of the block? */
8487 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
8489 // check for link register access in delay slot
8491 if(rt1_!=0&&(rs1[i]==rt1_||rs2[i]==rt1_||rt1[i]==rt1_||rt2[i]==rt1_)) {
8492 printf("link access in delay slot @%08x (%08x)\n", addr + i*4, addr);
8499 if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
8503 if(stop_after_jal) done=1;
8505 if((source[i+1]&0xfc00003f)==0x0d) done=1;
8507 // Don't recompile stuff that's already compiled
8508 if(check_addr(start+i*4+4)) done=1;
8509 // Don't get too close to the limit
8510 if(i>MAXBLOCK/2) done=1;
8512 if(itype[i]==SYSCALL&&stop_after_jal) done=1;
8513 if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
8515 // Does the block continue due to a branch?
8518 if(ba[j]==start+i*4+4) done=j=0;
8519 if(ba[j]==start+i*4+8) done=j=0;
8522 //assert(i<MAXBLOCK-1);
8523 if(start+i*4==pagelimit-4) done=1;
8524 assert(start+i*4<pagelimit);
8525 if (i==MAXBLOCK-1) done=1;
8526 // Stop if we're compiling junk
8527 if(itype[i]==NI&&opcode[i]==0x11) {
8528 done=stop_after_jal=1;
8529 printf("Disabled speculative precompilation\n");
8533 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8534 if(start+i*4==pagelimit) {
8540 /* Pass 2 - Register dependencies and branch targets */
8542 unneeded_registers(0,slen-1,0);
8544 /* Pass 3 - Register allocation */
8546 struct regstat current; // Current register allocations/status
8549 current.u=unneeded_reg[0];
8550 current.uu=unneeded_reg_upper[0];
8551 clear_all_regs(current.regmap);
8552 alloc_reg(¤t,0,CCREG);
8553 dirty_reg(¤t,CCREG);
8561 provisional_32bit();
8564 // First instruction is delay slot
8569 unneeded_reg_upper[0]=1;
8570 current.regmap[HOST_BTREG]=BTREG;
8578 for(hr=0;hr<HOST_REGS;hr++)
8580 // Is this really necessary?
8581 if(current.regmap[hr]==0) current.regmap[hr]=-1;
8587 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8589 if(rs1[i-2]==0||rs2[i-2]==0)
8592 current.is32|=1LL<<rs1[i-2];
8593 int hr=get_reg(current.regmap,rs1[i-2]|64);
8594 if(hr>=0) current.regmap[hr]=-1;
8597 current.is32|=1LL<<rs2[i-2];
8598 int hr=get_reg(current.regmap,rs2[i-2]|64);
8599 if(hr>=0) current.regmap[hr]=-1;
8605 // If something jumps here with 64-bit values
8606 // then promote those registers to 64 bits
8609 uint64_t temp_is32=current.is32;
8612 if(ba[j]==start+i*4)
8613 temp_is32&=branch_regs[j].is32;
8617 if(ba[j]==start+i*4)
8621 if(temp_is32!=current.is32) {
8622 //printf("dumping 32-bit regs (%x)\n",start+i*4);
8623 #ifdef DESTRUCTIVE_WRITEBACK
8624 for(hr=0;hr<HOST_REGS;hr++)
8626 int r=current.regmap[hr];
8629 if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8631 //printf("restore %d\n",r);
8636 current.is32=temp_is32;
8643 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8644 regs[i].wasconst=current.isconst;
8645 regs[i].was32=current.is32;
8646 regs[i].wasdirty=current.dirty;
8647 #if defined(DESTRUCTIVE_WRITEBACK) && !defined(FORCE32)
8648 // To change a dirty register from 32 to 64 bits, we must write
8649 // it out during the previous cycle (for branches, 2 cycles)
8650 if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8652 uint64_t temp_is32=current.is32;
8655 if(ba[j]==start+i*4+4)
8656 temp_is32&=branch_regs[j].is32;
8660 if(ba[j]==start+i*4+4)
8664 if(temp_is32!=current.is32) {
8665 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8666 for(hr=0;hr<HOST_REGS;hr++)
8668 int r=current.regmap[hr];
8671 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8672 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
8674 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
8676 //printf("dump %d/r%d\n",hr,r);
8677 current.regmap[hr]=-1;
8678 if(get_reg(current.regmap,r|64)>=0)
8679 current.regmap[get_reg(current.regmap,r|64)]=-1;
8687 else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
8689 uint64_t temp_is32=current.is32;
8692 if(ba[j]==start+i*4+8)
8693 temp_is32&=branch_regs[j].is32;
8697 if(ba[j]==start+i*4+8)
8701 if(temp_is32!=current.is32) {
8702 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8703 for(hr=0;hr<HOST_REGS;hr++)
8705 int r=current.regmap[hr];
8708 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8709 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
8711 //printf("dump %d/r%d\n",hr,r);
8712 current.regmap[hr]=-1;
8713 if(get_reg(current.regmap,r|64)>=0)
8714 current.regmap[get_reg(current.regmap,r|64)]=-1;
8722 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8724 current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8725 current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8726 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8735 current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
8736 current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8737 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8738 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8739 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8742 } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
8746 ds=0; // Skip delay slot, already allocated as part of branch
8747 // ...but we need to alloc it in case something jumps here
8749 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
8750 current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
8752 current.u=branch_unneeded_reg[i-1];
8753 current.uu=branch_unneeded_reg_upper[i-1];
8755 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8756 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8757 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8760 struct regstat temp;
8761 memcpy(&temp,¤t,sizeof(current));
8762 temp.wasdirty=temp.dirty;
8763 temp.was32=temp.is32;
8764 // TODO: Take into account unconditional branches, as below
8765 delayslot_alloc(&temp,i);
8766 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
8767 regs[i].wasdirty=temp.wasdirty;
8768 regs[i].was32=temp.was32;
8769 regs[i].dirty=temp.dirty;
8770 regs[i].is32=temp.is32;
8774 // Create entry (branch target) regmap
8775 for(hr=0;hr<HOST_REGS;hr++)
8777 int r=temp.regmap[hr];
8779 if(r!=regmap_pre[i][hr]) {
8780 regs[i].regmap_entry[hr]=-1;
8785 if((current.u>>r)&1) {
8786 regs[i].regmap_entry[hr]=-1;
8787 regs[i].regmap[hr]=-1;
8788 //Don't clear regs in the delay slot as the branch might need them
8789 //current.regmap[hr]=-1;
8791 regs[i].regmap_entry[hr]=r;
8794 if((current.uu>>(r&63))&1) {
8795 regs[i].regmap_entry[hr]=-1;
8796 regs[i].regmap[hr]=-1;
8797 //Don't clear regs in the delay slot as the branch might need them
8798 //current.regmap[hr]=-1;
8800 regs[i].regmap_entry[hr]=r;
8804 // First instruction expects CCREG to be allocated
8805 if(i==0&&hr==HOST_CCREG)
8806 regs[i].regmap_entry[hr]=CCREG;
8808 regs[i].regmap_entry[hr]=-1;
8812 else { // Not delay slot
8815 //current.isconst=0; // DEBUG
8816 //current.wasconst=0; // DEBUG
8817 //regs[i].wasconst=0; // DEBUG
8818 clear_const(¤t,rt1[i]);
8819 alloc_cc(¤t,i);
8820 dirty_reg(¤t,CCREG);
8822 alloc_reg(¤t,i,31);
8823 dirty_reg(¤t,31);
8824 assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8825 assert(rt1[i+1]!=rt1[i]);
8827 alloc_reg(¤t,i,PTEMP);
8829 //current.is32|=1LL<<rt1[i];
8832 delayslot_alloc(¤t,i+1);
8833 //current.isconst=0; // DEBUG
8835 //printf("i=%d, isconst=%x\n",i,current.isconst);
8838 //current.isconst=0;
8839 //current.wasconst=0;
8840 //regs[i].wasconst=0;
8841 clear_const(¤t,rs1[i]);
8842 clear_const(¤t,rt1[i]);
8843 alloc_cc(¤t,i);
8844 dirty_reg(¤t,CCREG);
8845 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
8846 alloc_reg(¤t,i,rs1[i]);
8848 alloc_reg(¤t,i,rt1[i]);
8849 dirty_reg(¤t,rt1[i]);
8850 assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
8851 assert(rt1[i+1]!=rt1[i]);
8853 alloc_reg(¤t,i,PTEMP);
8857 if(rs1[i]==31) { // JALR
8858 alloc_reg(¤t,i,RHASH);
8859 #ifndef HOST_IMM_ADDR32
8860 alloc_reg(¤t,i,RHTBL);
8864 delayslot_alloc(¤t,i+1);
8866 // The delay slot overwrites our source register,
8867 // allocate a temporary register to hold the old value.
8871 delayslot_alloc(¤t,i+1);
8873 alloc_reg(¤t,i,RTEMP);
8875 //current.isconst=0; // DEBUG
8880 //current.isconst=0;
8881 //current.wasconst=0;
8882 //regs[i].wasconst=0;
8883 clear_const(¤t,rs1[i]);
8884 clear_const(¤t,rs2[i]);
8885 if((opcode[i]&0x3E)==4) // BEQ/BNE
8887 alloc_cc(¤t,i);
8888 dirty_reg(¤t,CCREG);
8889 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
8890 if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
8891 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8893 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
8894 if(rs2[i]) alloc_reg64(¤t,i,rs2[i]);
8896 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
8897 (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
8898 // The delay slot overwrites one of our conditions.
8899 // Allocate the branch condition registers instead.
8903 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
8904 if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
8905 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8907 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
8908 if(rs2[i]) alloc_reg64(¤t,i,rs2[i]);
8914 delayslot_alloc(¤t,i+1);
8918 if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
8920 alloc_cc(¤t,i);
8921 dirty_reg(¤t,CCREG);
8922 alloc_reg(¤t,i,rs1[i]);
8923 if(!(current.is32>>rs1[i]&1))
8925 alloc_reg64(¤t,i,rs1[i]);
8927 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
8928 // The delay slot overwrites one of our conditions.
8929 // Allocate the branch condition registers instead.
8933 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
8934 if(!((current.is32>>rs1[i])&1))
8936 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
8942 delayslot_alloc(¤t,i+1);
8946 // Don't alloc the delay slot yet because we might not execute it
8947 if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
8952 alloc_cc(¤t,i);
8953 dirty_reg(¤t,CCREG);
8954 alloc_reg(¤t,i,rs1[i]);
8955 alloc_reg(¤t,i,rs2[i]);
8956 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8958 alloc_reg64(¤t,i,rs1[i]);
8959 alloc_reg64(¤t,i,rs2[i]);
8963 if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
8968 alloc_cc(¤t,i);
8969 dirty_reg(¤t,CCREG);
8970 alloc_reg(¤t,i,rs1[i]);
8971 if(!(current.is32>>rs1[i]&1))
8973 alloc_reg64(¤t,i,rs1[i]);
8977 //current.isconst=0;
8980 //current.isconst=0;
8981 //current.wasconst=0;
8982 //regs[i].wasconst=0;
8983 clear_const(¤t,rs1[i]);
8984 clear_const(¤t,rt1[i]);
8985 //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
8986 if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
8988 alloc_cc(¤t,i);
8989 dirty_reg(¤t,CCREG);
8990 alloc_reg(¤t,i,rs1[i]);
8991 if(!(current.is32>>rs1[i]&1))
8993 alloc_reg64(¤t,i,rs1[i]);
8995 if (rt1[i]==31) { // BLTZAL/BGEZAL
8996 alloc_reg(¤t,i,31);
8997 dirty_reg(¤t,31);
8998 //#ifdef REG_PREFETCH
8999 //alloc_reg(¤t,i,PTEMP);
9001 //current.is32|=1LL<<rt1[i];
9003 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) // The delay slot overwrites the branch condition.
9004 ||(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))) { // DS touches $ra
9005 // Allocate the branch condition registers instead.
9009 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9010 if(!((current.is32>>rs1[i])&1))
9012 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9018 delayslot_alloc(¤t,i+1);
9022 // Don't alloc the delay slot yet because we might not execute it
9023 if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
9028 alloc_cc(¤t,i);
9029 dirty_reg(¤t,CCREG);
9030 alloc_reg(¤t,i,rs1[i]);
9031 if(!(current.is32>>rs1[i]&1))
9033 alloc_reg64(¤t,i,rs1[i]);
9037 //current.isconst=0;
9043 if(likely[i]==0) // BC1F/BC1T
9045 // TODO: Theoretically we can run out of registers here on x86.
9046 // The delay slot can allocate up to six, and we need to check
9047 // CSREG before executing the delay slot. Possibly we can drop
9048 // the cycle count and then reload it after checking that the
9049 // FPU is in a usable state, or don't do out-of-order execution.
9050 alloc_cc(¤t,i);
9051 dirty_reg(¤t,CCREG);
9052 alloc_reg(¤t,i,FSREG);
9053 alloc_reg(¤t,i,CSREG);
9054 if(itype[i+1]==FCOMP) {
9055 // The delay slot overwrites the branch condition.
9056 // Allocate the branch condition registers instead.
9057 alloc_cc(¤t,i);
9058 dirty_reg(¤t,CCREG);
9059 alloc_reg(¤t,i,CSREG);
9060 alloc_reg(¤t,i,FSREG);
9064 delayslot_alloc(¤t,i+1);
9065 alloc_reg(¤t,i+1,CSREG);
9069 // Don't alloc the delay slot yet because we might not execute it
9070 if(likely[i]) // BC1FL/BC1TL
9072 alloc_cc(¤t,i);
9073 dirty_reg(¤t,CCREG);
9074 alloc_reg(¤t,i,CSREG);
9075 alloc_reg(¤t,i,FSREG);
9081 imm16_alloc(¤t,i);
9085 load_alloc(¤t,i);
9089 store_alloc(¤t,i);
9092 alu_alloc(¤t,i);
9095 shift_alloc(¤t,i);
9098 multdiv_alloc(¤t,i);
9101 shiftimm_alloc(¤t,i);
9104 mov_alloc(¤t,i);
9107 cop0_alloc(¤t,i);
9111 cop1_alloc(¤t,i);
9114 c1ls_alloc(¤t,i);
9117 c2ls_alloc(¤t,i);
9120 c2op_alloc(¤t,i);
9123 fconv_alloc(¤t,i);
9126 float_alloc(¤t,i);
9129 fcomp_alloc(¤t,i);
9134 syscall_alloc(¤t,i);
9137 pagespan_alloc(¤t,i);
9141 // Drop the upper half of registers that have become 32-bit
9142 current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
9143 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9144 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9145 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9148 current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
9149 current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9150 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9151 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9155 // Create entry (branch target) regmap
9156 for(hr=0;hr<HOST_REGS;hr++)
9159 r=current.regmap[hr];
9161 if(r!=regmap_pre[i][hr]) {
9162 // TODO: delay slot (?)
9163 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9164 if(or<0||(r&63)>=TEMPREG){
9165 regs[i].regmap_entry[hr]=-1;
9169 // Just move it to a different register
9170 regs[i].regmap_entry[hr]=r;
9171 // If it was dirty before, it's still dirty
9172 if((regs[i].wasdirty>>or)&1) dirty_reg(¤t,r&63);
9179 regs[i].regmap_entry[hr]=0;
9183 if((current.u>>r)&1) {
9184 regs[i].regmap_entry[hr]=-1;
9185 //regs[i].regmap[hr]=-1;
9186 current.regmap[hr]=-1;
9188 regs[i].regmap_entry[hr]=r;
9191 if((current.uu>>(r&63))&1) {
9192 regs[i].regmap_entry[hr]=-1;
9193 //regs[i].regmap[hr]=-1;
9194 current.regmap[hr]=-1;
9196 regs[i].regmap_entry[hr]=r;
9200 // Branches expect CCREG to be allocated at the target
9201 if(regmap_pre[i][hr]==CCREG)
9202 regs[i].regmap_entry[hr]=CCREG;
9204 regs[i].regmap_entry[hr]=-1;
9207 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9209 /* Branch post-alloc */
9212 current.was32=current.is32;
9213 current.wasdirty=current.dirty;
9214 switch(itype[i-1]) {
9216 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9217 branch_regs[i-1].isconst=0;
9218 branch_regs[i-1].wasconst=0;
9219 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9220 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9221 alloc_cc(&branch_regs[i-1],i-1);
9222 dirty_reg(&branch_regs[i-1],CCREG);
9223 if(rt1[i-1]==31) { // JAL
9224 alloc_reg(&branch_regs[i-1],i-1,31);
9225 dirty_reg(&branch_regs[i-1],31);
9226 branch_regs[i-1].is32|=1LL<<31;
9228 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9229 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9232 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9233 branch_regs[i-1].isconst=0;
9234 branch_regs[i-1].wasconst=0;
9235 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9236 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9237 alloc_cc(&branch_regs[i-1],i-1);
9238 dirty_reg(&branch_regs[i-1],CCREG);
9239 alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
9240 if(rt1[i-1]!=0) { // JALR
9241 alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9242 dirty_reg(&branch_regs[i-1],rt1[i-1]);
9243 branch_regs[i-1].is32|=1LL<<rt1[i-1];
9246 if(rs1[i-1]==31) { // JALR
9247 alloc_reg(&branch_regs[i-1],i-1,RHASH);
9248 #ifndef HOST_IMM_ADDR32
9249 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9253 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9254 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9257 if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9259 alloc_cc(¤t,i-1);
9260 dirty_reg(¤t,CCREG);
9261 if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9262 (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9263 // The delay slot overwrote one of our conditions
9264 // Delay slot goes after the test (in order)
9265 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9266 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9267 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9270 delayslot_alloc(¤t,i);
9275 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9276 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9277 // Alloc the branch condition registers
9278 if(rs1[i-1]) alloc_reg(¤t,i-1,rs1[i-1]);
9279 if(rs2[i-1]) alloc_reg(¤t,i-1,rs2[i-1]);
9280 if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9282 if(rs1[i-1]) alloc_reg64(¤t,i-1,rs1[i-1]);
9283 if(rs2[i-1]) alloc_reg64(¤t,i-1,rs2[i-1]);
9286 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9287 branch_regs[i-1].isconst=0;
9288 branch_regs[i-1].wasconst=0;
9289 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9290 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9293 if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9295 alloc_cc(¤t,i-1);
9296 dirty_reg(¤t,CCREG);
9297 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9298 // The delay slot overwrote the branch condition
9299 // Delay slot goes after the test (in order)
9300 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9301 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9302 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9305 delayslot_alloc(¤t,i);
9310 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9311 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9312 // Alloc the branch condition register
9313 alloc_reg(¤t,i-1,rs1[i-1]);
9314 if(!(current.is32>>rs1[i-1]&1))
9316 alloc_reg64(¤t,i-1,rs1[i-1]);
9319 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9320 branch_regs[i-1].isconst=0;
9321 branch_regs[i-1].wasconst=0;
9322 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9323 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9326 // Alloc the delay slot in case the branch is taken
9327 if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9329 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9330 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9331 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9332 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9333 alloc_cc(&branch_regs[i-1],i);
9334 dirty_reg(&branch_regs[i-1],CCREG);
9335 delayslot_alloc(&branch_regs[i-1],i);
9336 branch_regs[i-1].isconst=0;
9337 alloc_reg(¤t,i,CCREG); // Not taken path
9338 dirty_reg(¤t,CCREG);
9339 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9342 if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9344 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9345 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9346 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9347 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9348 alloc_cc(&branch_regs[i-1],i);
9349 dirty_reg(&branch_regs[i-1],CCREG);
9350 delayslot_alloc(&branch_regs[i-1],i);
9351 branch_regs[i-1].isconst=0;
9352 alloc_reg(¤t,i,CCREG); // Not taken path
9353 dirty_reg(¤t,CCREG);
9354 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9358 //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9359 if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9361 alloc_cc(¤t,i-1);
9362 dirty_reg(¤t,CCREG);
9363 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9364 // The delay slot overwrote the branch condition
9365 // Delay slot goes after the test (in order)
9366 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9367 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9368 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9371 delayslot_alloc(¤t,i);
9376 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9377 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9378 // Alloc the branch condition register
9379 alloc_reg(¤t,i-1,rs1[i-1]);
9380 if(!(current.is32>>rs1[i-1]&1))
9382 alloc_reg64(¤t,i-1,rs1[i-1]);
9385 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9386 branch_regs[i-1].isconst=0;
9387 branch_regs[i-1].wasconst=0;
9388 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9389 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9392 // Alloc the delay slot in case the branch is taken
9393 if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9395 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9396 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9397 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9398 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9399 alloc_cc(&branch_regs[i-1],i);
9400 dirty_reg(&branch_regs[i-1],CCREG);
9401 delayslot_alloc(&branch_regs[i-1],i);
9402 branch_regs[i-1].isconst=0;
9403 alloc_reg(¤t,i,CCREG); // Not taken path
9404 dirty_reg(¤t,CCREG);
9405 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9407 // FIXME: BLTZAL/BGEZAL
9408 if(opcode2[i-1]&0x10) { // BxxZAL
9409 alloc_reg(&branch_regs[i-1],i-1,31);
9410 dirty_reg(&branch_regs[i-1],31);
9411 branch_regs[i-1].is32|=1LL<<31;
9415 if(likely[i-1]==0) // BC1F/BC1T
9417 alloc_cc(¤t,i-1);
9418 dirty_reg(¤t,CCREG);
9419 if(itype[i]==FCOMP) {
9420 // The delay slot overwrote the branch condition
9421 // Delay slot goes after the test (in order)
9422 delayslot_alloc(¤t,i);
9427 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9428 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9429 // Alloc the branch condition register
9430 alloc_reg(¤t,i-1,FSREG);
9432 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9433 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9437 // Alloc the delay slot in case the branch is taken
9438 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9439 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9440 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9441 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9442 alloc_cc(&branch_regs[i-1],i);
9443 dirty_reg(&branch_regs[i-1],CCREG);
9444 delayslot_alloc(&branch_regs[i-1],i);
9445 branch_regs[i-1].isconst=0;
9446 alloc_reg(¤t,i,CCREG); // Not taken path
9447 dirty_reg(¤t,CCREG);
9448 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9453 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9455 if(rt1[i-1]==31) // JAL/JALR
9457 // Subroutine call will return here, don't alloc any registers
9460 clear_all_regs(current.regmap);
9461 alloc_reg(¤t,i,CCREG);
9462 dirty_reg(¤t,CCREG);
9466 // Internal branch will jump here, match registers to caller
9467 current.is32=0x3FFFFFFFFLL;
9469 clear_all_regs(current.regmap);
9470 alloc_reg(¤t,i,CCREG);
9471 dirty_reg(¤t,CCREG);
9474 if(ba[j]==start+i*4+4) {
9475 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9476 current.is32=branch_regs[j].is32;
9477 current.dirty=branch_regs[j].dirty;
9482 if(ba[j]==start+i*4+4) {
9483 for(hr=0;hr<HOST_REGS;hr++) {
9484 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9485 current.regmap[hr]=-1;
9487 current.is32&=branch_regs[j].is32;
9488 current.dirty&=branch_regs[j].dirty;
9497 // Count cycles in between branches
9499 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
9504 else if(/*itype[i]==LOAD||*/itype[i]==STORE||itype[i]==C1LS) // load causes weird timing issues
9506 cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
9508 else if(itype[i]==C2LS)
9518 flush_dirty_uppers(¤t);
9520 regs[i].is32=current.is32;
9521 regs[i].dirty=current.dirty;
9522 regs[i].isconst=current.isconst;
9523 memcpy(constmap[i],current.constmap,sizeof(current.constmap));
9525 for(hr=0;hr<HOST_REGS;hr++) {
9526 if(hr!=EXCLUDE_REG&®s[i].regmap[hr]>=0) {
9527 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9528 regs[i].wasconst&=~(1<<hr);
9532 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9535 /* Pass 4 - Cull unused host registers */
9539 for (i=slen-1;i>=0;i--)
9542 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9544 if(ba[i]<start || ba[i]>=(start+slen*4))
9546 // Branch out of this block, don't need anything
9552 // Need whatever matches the target
9554 int t=(ba[i]-start)>>2;
9555 for(hr=0;hr<HOST_REGS;hr++)
9557 if(regs[i].regmap_entry[hr]>=0) {
9558 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9562 // Conditional branch may need registers for following instructions
9563 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9566 nr|=needed_reg[i+2];
9567 for(hr=0;hr<HOST_REGS;hr++)
9569 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9570 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9574 // Don't need stuff which is overwritten
9575 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9576 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9577 // Merge in delay slot
9578 for(hr=0;hr<HOST_REGS;hr++)
9581 // These are overwritten unless the branch is "likely"
9582 // and the delay slot is nullified if not taken
9583 if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9584 if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9586 if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9587 if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9588 if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9589 if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9590 if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9591 if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9592 if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9593 if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9594 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9595 if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9596 if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9598 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9599 if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9600 if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9602 if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
9603 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9604 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9608 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
9610 // SYSCALL instruction (software interrupt)
9613 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9615 // ERET instruction (return from interrupt)
9621 for(hr=0;hr<HOST_REGS;hr++) {
9622 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9623 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9624 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9625 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9629 for(hr=0;hr<HOST_REGS;hr++)
9631 // Overwritten registers are not needed
9632 if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9633 if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9634 if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9635 // Source registers are needed
9636 if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9637 if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9638 if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9639 if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9640 if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9641 if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9642 if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9643 if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9644 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9645 if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9646 if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9648 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
9649 if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9650 if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9652 if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
9653 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9654 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9656 // Don't store a register immediately after writing it,
9657 // may prevent dual-issue.
9658 // But do so if this is a branch target, otherwise we
9659 // might have to load the register before the branch.
9660 if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
9661 if((regmap_pre[i][hr]>0&®map_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
9662 (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
9663 if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9664 if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9666 if((regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
9667 (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
9668 if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9669 if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9673 // Cycle count is needed at branches. Assume it is needed at the target too.
9674 if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
9675 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9676 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9681 // Deallocate unneeded registers
9682 for(hr=0;hr<HOST_REGS;hr++)
9685 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
9686 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9687 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9688 (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
9690 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9693 regs[i].regmap[hr]=-1;
9694 regs[i].isconst&=~(1<<hr);
9695 if(i<slen-2) regmap_pre[i+2][hr]=-1;
9699 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9701 int d1=0,d2=0,map=0,temp=0;
9702 if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
9708 if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
9709 itype[i+1]==STORE || itype[i+1]==STORELR ||
9710 itype[i+1]==C1LS || itype[i+1]==C2LS)
9713 if(itype[i+1]==STORE || itype[i+1]==STORELR ||
9714 (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
9717 if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
9718 itype[i+1]==C1LS || itype[i+1]==C2LS)
9720 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9721 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9722 (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
9723 (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
9724 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9725 regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
9726 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
9727 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
9728 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
9729 regs[i].regmap[hr]!=map )
9731 regs[i].regmap[hr]=-1;
9732 regs[i].isconst&=~(1<<hr);
9733 if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
9734 (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
9735 (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
9736 (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
9737 (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
9738 branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
9739 (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
9740 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
9741 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
9742 branch_regs[i].regmap[hr]!=map)
9744 branch_regs[i].regmap[hr]=-1;
9745 branch_regs[i].regmap_entry[hr]=-1;
9746 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9748 if(!likely[i]&&i<slen-2) {
9749 regmap_pre[i+2][hr]=-1;
9760 int d1=0,d2=0,map=-1,temp=-1;
9761 if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
9767 if(itype[i]==LOAD || itype[i]==LOADLR ||
9768 itype[i]==STORE || itype[i]==STORELR ||
9769 itype[i]==C1LS || itype[i]==C2LS)
9771 } else if(itype[i]==STORE || itype[i]==STORELR ||
9772 (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
9775 if(itype[i]==LOADLR || itype[i]==STORELR ||
9776 itype[i]==C1LS || itype[i]==C2LS)
9778 if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9779 (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
9780 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9781 regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
9782 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
9783 (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
9785 if(i<slen-1&&!is_ds[i]) {
9786 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
9787 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
9788 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
9790 printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
9791 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
9793 regmap_pre[i+1][hr]=-1;
9794 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
9796 regs[i].regmap[hr]=-1;
9797 regs[i].isconst&=~(1<<hr);
9805 /* Pass 5 - Pre-allocate registers */
9807 // If a register is allocated during a loop, try to allocate it for the
9808 // entire loop, if possible. This avoids loading/storing registers
9809 // inside of the loop.
9811 signed char f_regmap[HOST_REGS];
9812 clear_all_regs(f_regmap);
9813 for(i=0;i<slen-1;i++)
9815 if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9817 if(ba[i]>=start && ba[i]<(start+i*4))
9818 if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
9819 ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
9820 ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
9821 ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
9822 ||itype[i+1]==FCOMP||itype[i+1]==FCONV
9823 ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
9825 int t=(ba[i]-start)>>2;
9826 if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
9827 if(t<2||(itype[t-2]!=UJUMP)) // call/ret assumes no registers allocated
9828 for(hr=0;hr<HOST_REGS;hr++)
9830 if(regs[i].regmap[hr]>64) {
9831 if(!((regs[i].dirty>>hr)&1))
9832 f_regmap[hr]=regs[i].regmap[hr];
9833 else f_regmap[hr]=-1;
9835 else if(regs[i].regmap[hr]>=0) {
9836 if(f_regmap[hr]!=regs[i].regmap[hr]) {
9837 // dealloc old register
9839 for(n=0;n<HOST_REGS;n++)
9841 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
9843 // and alloc new one
9844 f_regmap[hr]=regs[i].regmap[hr];
9847 if(branch_regs[i].regmap[hr]>64) {
9848 if(!((branch_regs[i].dirty>>hr)&1))
9849 f_regmap[hr]=branch_regs[i].regmap[hr];
9850 else f_regmap[hr]=-1;
9852 else if(branch_regs[i].regmap[hr]>=0) {
9853 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
9854 // dealloc old register
9856 for(n=0;n<HOST_REGS;n++)
9858 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
9860 // and alloc new one
9861 f_regmap[hr]=branch_regs[i].regmap[hr];
9865 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
9866 f_regmap[hr]=branch_regs[i].regmap[hr];
9868 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
9869 f_regmap[hr]=branch_regs[i].regmap[hr];
9871 // Avoid dirty->clean transition
9872 #ifdef DESTRUCTIVE_WRITEBACK
9873 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
9875 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
9876 // case above, however it's always a good idea. We can't hoist the
9877 // load if the register was already allocated, so there's no point
9878 // wasting time analyzing most of these cases. It only "succeeds"
9879 // when the mapping was different and the load can be replaced with
9880 // a mov, which is of negligible benefit. So such cases are
9882 if(f_regmap[hr]>0) {
9883 if(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0) {
9887 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9888 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
9889 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
9891 // NB This can exclude the case where the upper-half
9892 // register is lower numbered than the lower-half
9893 // register. Not sure if it's worth fixing...
9894 if(get_reg(regs[j].regmap,r&63)<0) break;
9895 if(get_reg(regs[j].regmap_entry,r&63)<0) break;
9896 if(regs[j].is32&(1LL<<(r&63))) break;
9898 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
9899 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9901 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
9902 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
9904 if(get_reg(regs[i].regmap,r&63)<0) break;
9905 if(get_reg(branch_regs[i].regmap,r&63)<0) break;
9908 while(k>1&®s[k-1].regmap[hr]==-1) {
9909 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
9910 //printf("no free regs for store %x\n",start+(k-1)*4);
9913 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
9914 //printf("no-match due to different register\n");
9917 if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
9918 //printf("no-match due to branch\n");
9921 // call/ret fast path assumes no registers allocated
9922 if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)) {
9926 // NB This can exclude the case where the upper-half
9927 // register is lower numbered than the lower-half
9928 // register. Not sure if it's worth fixing...
9929 if(get_reg(regs[k-1].regmap,r&63)<0) break;
9930 if(regs[k-1].is32&(1LL<<(r&63))) break;
9935 if((regs[k].is32&(1LL<<f_regmap[hr]))!=
9936 (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
9937 //printf("bad match after branch\n");
9941 if(regs[k-1].regmap[hr]==f_regmap[hr]&®map_pre[k][hr]==f_regmap[hr]) {
9942 //printf("Extend r%d, %x ->\n",hr,start+k*4);
9944 regs[k].regmap_entry[hr]=f_regmap[hr];
9945 regs[k].regmap[hr]=f_regmap[hr];
9946 regmap_pre[k+1][hr]=f_regmap[hr];
9947 regs[k].wasdirty&=~(1<<hr);
9948 regs[k].dirty&=~(1<<hr);
9949 regs[k].wasdirty|=(1<<hr)®s[k-1].dirty;
9950 regs[k].dirty|=(1<<hr)®s[k].wasdirty;
9951 regs[k].wasconst&=~(1<<hr);
9952 regs[k].isconst&=~(1<<hr);
9957 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
9960 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
9961 if(regs[i-1].regmap[hr]==f_regmap[hr]&®map_pre[i][hr]==f_regmap[hr]) {
9962 //printf("OK fill %x (r%d)\n",start+i*4,hr);
9963 regs[i].regmap_entry[hr]=f_regmap[hr];
9964 regs[i].regmap[hr]=f_regmap[hr];
9965 regs[i].wasdirty&=~(1<<hr);
9966 regs[i].dirty&=~(1<<hr);
9967 regs[i].wasdirty|=(1<<hr)®s[i-1].dirty;
9968 regs[i].dirty|=(1<<hr)®s[i-1].dirty;
9969 regs[i].wasconst&=~(1<<hr);
9970 regs[i].isconst&=~(1<<hr);
9971 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
9972 branch_regs[i].wasdirty&=~(1<<hr);
9973 branch_regs[i].wasdirty|=(1<<hr)®s[i].dirty;
9974 branch_regs[i].regmap[hr]=f_regmap[hr];
9975 branch_regs[i].dirty&=~(1<<hr);
9976 branch_regs[i].dirty|=(1<<hr)®s[i].dirty;
9977 branch_regs[i].wasconst&=~(1<<hr);
9978 branch_regs[i].isconst&=~(1<<hr);
9979 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
9980 regmap_pre[i+2][hr]=f_regmap[hr];
9981 regs[i+2].wasdirty&=~(1<<hr);
9982 regs[i+2].wasdirty|=(1<<hr)®s[i].dirty;
9983 assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
9984 (regs[i+2].was32&(1LL<<f_regmap[hr])));
9989 // Alloc register clean at beginning of loop,
9990 // but may dirty it in pass 6
9991 regs[k].regmap_entry[hr]=f_regmap[hr];
9992 regs[k].regmap[hr]=f_regmap[hr];
9993 regs[k].dirty&=~(1<<hr);
9994 regs[k].wasconst&=~(1<<hr);
9995 regs[k].isconst&=~(1<<hr);
9996 if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) {
9997 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
9998 branch_regs[k].regmap[hr]=f_regmap[hr];
9999 branch_regs[k].dirty&=~(1<<hr);
10000 branch_regs[k].wasconst&=~(1<<hr);
10001 branch_regs[k].isconst&=~(1<<hr);
10002 if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
10003 regmap_pre[k+2][hr]=f_regmap[hr];
10004 regs[k+2].wasdirty&=~(1<<hr);
10005 assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))==
10006 (regs[k+2].was32&(1LL<<f_regmap[hr])));
10011 regmap_pre[k+1][hr]=f_regmap[hr];
10012 regs[k+1].wasdirty&=~(1<<hr);
10015 if(regs[j].regmap[hr]==f_regmap[hr])
10016 regs[j].regmap_entry[hr]=f_regmap[hr];
10020 if(regs[j].regmap[hr]>=0)
10022 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
10023 //printf("no-match due to different register\n");
10026 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
10027 //printf("32/64 mismatch %x %d\n",start+j*4,hr);
10030 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10032 // Stop on unconditional branch
10035 if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
10038 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
10041 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
10044 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
10045 //printf("no-match due to different register (branch)\n");
10049 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10050 //printf("No free regs for store %x\n",start+j*4);
10053 if(f_regmap[hr]>=64) {
10054 if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
10059 if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
10071 for(hr=0;hr<HOST_REGS;hr++)
10073 if(hr!=EXCLUDE_REG) {
10074 if(regs[i].regmap[hr]>64) {
10075 if(!((regs[i].dirty>>hr)&1))
10076 f_regmap[hr]=regs[i].regmap[hr];
10078 else if(regs[i].regmap[hr]>=0) {
10079 if(f_regmap[hr]!=regs[i].regmap[hr]) {
10080 // dealloc old register
10082 for(n=0;n<HOST_REGS;n++)
10084 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10086 // and alloc new one
10087 f_regmap[hr]=regs[i].regmap[hr];
10090 else if(regs[i].regmap[hr]<0) count++;
10093 // Try to restore cycle count at branch targets
10095 for(j=i;j<slen-1;j++) {
10096 if(regs[j].regmap[HOST_CCREG]!=-1) break;
10097 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10098 //printf("no free regs for store %x\n",start+j*4);
10102 if(regs[j].regmap[HOST_CCREG]==CCREG) {
10104 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
10106 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10107 regs[k].regmap[HOST_CCREG]=CCREG;
10108 regmap_pre[k+1][HOST_CCREG]=CCREG;
10109 regs[k+1].wasdirty|=1<<HOST_CCREG;
10110 regs[k].dirty|=1<<HOST_CCREG;
10111 regs[k].wasconst&=~(1<<HOST_CCREG);
10112 regs[k].isconst&=~(1<<HOST_CCREG);
10115 regs[j].regmap_entry[HOST_CCREG]=CCREG;
10117 // Work backwards from the branch target
10118 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
10120 //printf("Extend backwards\n");
10123 while(regs[k-1].regmap[HOST_CCREG]==-1) {
10124 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10125 //printf("no free regs for store %x\n",start+(k-1)*4);
10130 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
10131 //printf("Extend CC, %x ->\n",start+k*4);
10133 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10134 regs[k].regmap[HOST_CCREG]=CCREG;
10135 regmap_pre[k+1][HOST_CCREG]=CCREG;
10136 regs[k+1].wasdirty|=1<<HOST_CCREG;
10137 regs[k].dirty|=1<<HOST_CCREG;
10138 regs[k].wasconst&=~(1<<HOST_CCREG);
10139 regs[k].isconst&=~(1<<HOST_CCREG);
10144 //printf("Fail Extend CC, %x ->\n",start+k*4);
10148 if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
10149 itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
10150 itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
10151 itype[i]!=FCONV&&itype[i]!=FCOMP)
10153 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
10158 // This allocates registers (if possible) one instruction prior
10159 // to use, which can avoid a load-use penalty on certain CPUs.
10160 for(i=0;i<slen-1;i++)
10162 if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10166 if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
10167 ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
10170 if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10172 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10174 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10175 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10176 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10177 regs[i].isconst&=~(1<<hr);
10178 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10179 constmap[i][hr]=constmap[i+1][hr];
10180 regs[i+1].wasdirty&=~(1<<hr);
10181 regs[i].dirty&=~(1<<hr);
10186 if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10188 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10190 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10191 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10192 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10193 regs[i].isconst&=~(1<<hr);
10194 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10195 constmap[i][hr]=constmap[i+1][hr];
10196 regs[i+1].wasdirty&=~(1<<hr);
10197 regs[i].dirty&=~(1<<hr);
10201 if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10202 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10204 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10206 regs[i].regmap[hr]=rs1[i+1];
10207 regmap_pre[i+1][hr]=rs1[i+1];
10208 regs[i+1].regmap_entry[hr]=rs1[i+1];
10209 regs[i].isconst&=~(1<<hr);
10210 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10211 constmap[i][hr]=constmap[i+1][hr];
10212 regs[i+1].wasdirty&=~(1<<hr);
10213 regs[i].dirty&=~(1<<hr);
10217 if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10218 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10220 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10222 regs[i].regmap[hr]=rs1[i+1];
10223 regmap_pre[i+1][hr]=rs1[i+1];
10224 regs[i+1].regmap_entry[hr]=rs1[i+1];
10225 regs[i].isconst&=~(1<<hr);
10226 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10227 constmap[i][hr]=constmap[i+1][hr];
10228 regs[i+1].wasdirty&=~(1<<hr);
10229 regs[i].dirty&=~(1<<hr);
10233 #ifndef HOST_IMM_ADDR32
10234 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
10235 hr=get_reg(regs[i+1].regmap,TLREG);
10237 int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10238 if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10240 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10242 regs[i].regmap[hr]=MGEN1+((i+1)&1);
10243 regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10244 regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10245 regs[i].isconst&=~(1<<hr);
10246 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10247 constmap[i][hr]=constmap[i+1][hr];
10248 regs[i+1].wasdirty&=~(1<<hr);
10249 regs[i].dirty&=~(1<<hr);
10251 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10253 // move it to another register
10254 regs[i+1].regmap[hr]=-1;
10255 regmap_pre[i+2][hr]=-1;
10256 regs[i+1].regmap[nr]=TLREG;
10257 regmap_pre[i+2][nr]=TLREG;
10258 regs[i].regmap[nr]=MGEN1+((i+1)&1);
10259 regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10260 regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10261 regs[i].isconst&=~(1<<nr);
10262 regs[i+1].isconst&=~(1<<nr);
10263 regs[i].dirty&=~(1<<nr);
10264 regs[i+1].wasdirty&=~(1<<nr);
10265 regs[i+1].dirty&=~(1<<nr);
10266 regs[i+2].wasdirty&=~(1<<nr);
10272 if(itype[i+1]==STORE||itype[i+1]==STORELR
10273 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
10274 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10275 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10276 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10277 else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10279 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10281 regs[i].regmap[hr]=rs1[i+1];
10282 regmap_pre[i+1][hr]=rs1[i+1];
10283 regs[i+1].regmap_entry[hr]=rs1[i+1];
10284 regs[i].isconst&=~(1<<hr);
10285 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10286 constmap[i][hr]=constmap[i+1][hr];
10287 regs[i+1].wasdirty&=~(1<<hr);
10288 regs[i].dirty&=~(1<<hr);
10292 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
10293 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10295 hr=get_reg(regs[i+1].regmap,FTEMP);
10297 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10299 regs[i].regmap[hr]=rs1[i+1];
10300 regmap_pre[i+1][hr]=rs1[i+1];
10301 regs[i+1].regmap_entry[hr]=rs1[i+1];
10302 regs[i].isconst&=~(1<<hr);
10303 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10304 constmap[i][hr]=constmap[i+1][hr];
10305 regs[i+1].wasdirty&=~(1<<hr);
10306 regs[i].dirty&=~(1<<hr);
10308 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10310 // move it to another register
10311 regs[i+1].regmap[hr]=-1;
10312 regmap_pre[i+2][hr]=-1;
10313 regs[i+1].regmap[nr]=FTEMP;
10314 regmap_pre[i+2][nr]=FTEMP;
10315 regs[i].regmap[nr]=rs1[i+1];
10316 regmap_pre[i+1][nr]=rs1[i+1];
10317 regs[i+1].regmap_entry[nr]=rs1[i+1];
10318 regs[i].isconst&=~(1<<nr);
10319 regs[i+1].isconst&=~(1<<nr);
10320 regs[i].dirty&=~(1<<nr);
10321 regs[i+1].wasdirty&=~(1<<nr);
10322 regs[i+1].dirty&=~(1<<nr);
10323 regs[i+2].wasdirty&=~(1<<nr);
10327 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
10328 if(itype[i+1]==LOAD)
10329 hr=get_reg(regs[i+1].regmap,rt1[i+1]);
10330 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
10331 hr=get_reg(regs[i+1].regmap,FTEMP);
10332 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
10333 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10334 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10336 if(hr>=0&®s[i].regmap[hr]<0) {
10337 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10338 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10339 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10340 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10341 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10342 regs[i].isconst&=~(1<<hr);
10343 regs[i+1].wasdirty&=~(1<<hr);
10344 regs[i].dirty&=~(1<<hr);
10353 /* Pass 6 - Optimize clean/dirty state */
10354 clean_registers(0,slen-1,1);
10356 /* Pass 7 - Identify 32-bit registers */
10362 for (i=slen-1;i>=0;i--)
10365 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10367 if(ba[i]<start || ba[i]>=(start+slen*4))
10369 // Branch out of this block, don't need anything
10375 // Need whatever matches the target
10376 // (and doesn't get overwritten by the delay slot instruction)
10378 int t=(ba[i]-start)>>2;
10379 if(ba[i]>start+i*4) {
10381 if(!(requires_32bit[t]&~regs[i].was32))
10382 r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10385 //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10386 // r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10387 if(!(pr32[t]&~regs[i].was32))
10388 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10391 // Conditional branch may need registers for following instructions
10392 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10395 r32|=requires_32bit[i+2];
10396 r32&=regs[i].was32;
10397 // Mark this address as a branch target since it may be called
10398 // upon return from interrupt
10402 // Merge in delay slot
10404 // These are overwritten unless the branch is "likely"
10405 // and the delay slot is nullified if not taken
10406 r32&=~(1LL<<rt1[i+1]);
10407 r32&=~(1LL<<rt2[i+1]);
10409 // Assume these are needed (delay slot)
10412 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10416 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10418 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10420 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10422 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10424 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10427 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
10429 // SYSCALL instruction (software interrupt)
10432 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10434 // ERET instruction (return from interrupt)
10438 r32&=~(1LL<<rt1[i]);
10439 r32&=~(1LL<<rt2[i]);
10442 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10446 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10448 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
10450 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
10452 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
10454 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
10456 requires_32bit[i]=r32;
10458 // Dirty registers which are 32-bit, require 32-bit input
10459 // as they will be written as 32-bit values
10460 for(hr=0;hr<HOST_REGS;hr++)
10462 if(regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64) {
10463 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
10464 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
10465 requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
10469 //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
10473 if(itype[slen-1]==SPAN) {
10474 bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
10477 /* Debug/disassembly */
10478 if((void*)assem_debug==(void*)printf)
10479 for(i=0;i<slen;i++)
10483 for(r=1;r<=CCREG;r++) {
10484 if((unneeded_reg[i]>>r)&1) {
10485 if(r==HIREG) printf(" HI");
10486 else if(r==LOREG) printf(" LO");
10487 else printf(" r%d",r);
10492 for(r=1;r<=CCREG;r++) {
10493 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
10494 if(r==HIREG) printf(" HI");
10495 else if(r==LOREG) printf(" LO");
10496 else printf(" r%d",r);
10500 for(r=0;r<=CCREG;r++) {
10501 //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10502 if((regs[i].was32>>r)&1) {
10503 if(r==CCREG) printf(" CC");
10504 else if(r==HIREG) printf(" HI");
10505 else if(r==LOREG) printf(" LO");
10506 else printf(" r%d",r);
10511 #if defined(__i386__) || defined(__x86_64__)
10512 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
10515 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
10518 if(needed_reg[i]&1) printf("eax ");
10519 if((needed_reg[i]>>1)&1) printf("ecx ");
10520 if((needed_reg[i]>>2)&1) printf("edx ");
10521 if((needed_reg[i]>>3)&1) printf("ebx ");
10522 if((needed_reg[i]>>5)&1) printf("ebp ");
10523 if((needed_reg[i]>>6)&1) printf("esi ");
10524 if((needed_reg[i]>>7)&1) printf("edi ");
10526 for(r=0;r<=CCREG;r++) {
10527 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10528 if((requires_32bit[i]>>r)&1) {
10529 if(r==CCREG) printf(" CC");
10530 else if(r==HIREG) printf(" HI");
10531 else if(r==LOREG) printf(" LO");
10532 else printf(" r%d",r);
10537 for(r=0;r<=CCREG;r++) {
10538 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10539 if((pr32[i]>>r)&1) {
10540 if(r==CCREG) printf(" CC");
10541 else if(r==HIREG) printf(" HI");
10542 else if(r==LOREG) printf(" LO");
10543 else printf(" r%d",r);
10546 if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
10548 #if defined(__i386__) || defined(__x86_64__)
10549 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
10551 if(regs[i].wasdirty&1) printf("eax ");
10552 if((regs[i].wasdirty>>1)&1) printf("ecx ");
10553 if((regs[i].wasdirty>>2)&1) printf("edx ");
10554 if((regs[i].wasdirty>>3)&1) printf("ebx ");
10555 if((regs[i].wasdirty>>5)&1) printf("ebp ");
10556 if((regs[i].wasdirty>>6)&1) printf("esi ");
10557 if((regs[i].wasdirty>>7)&1) printf("edi ");
10560 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
10562 if(regs[i].wasdirty&1) printf("r0 ");
10563 if((regs[i].wasdirty>>1)&1) printf("r1 ");
10564 if((regs[i].wasdirty>>2)&1) printf("r2 ");
10565 if((regs[i].wasdirty>>3)&1) printf("r3 ");
10566 if((regs[i].wasdirty>>4)&1) printf("r4 ");
10567 if((regs[i].wasdirty>>5)&1) printf("r5 ");
10568 if((regs[i].wasdirty>>6)&1) printf("r6 ");
10569 if((regs[i].wasdirty>>7)&1) printf("r7 ");
10570 if((regs[i].wasdirty>>8)&1) printf("r8 ");
10571 if((regs[i].wasdirty>>9)&1) printf("r9 ");
10572 if((regs[i].wasdirty>>10)&1) printf("r10 ");
10573 if((regs[i].wasdirty>>12)&1) printf("r12 ");
10576 disassemble_inst(i);
10577 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
10578 #if defined(__i386__) || defined(__x86_64__)
10579 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
10580 if(regs[i].dirty&1) printf("eax ");
10581 if((regs[i].dirty>>1)&1) printf("ecx ");
10582 if((regs[i].dirty>>2)&1) printf("edx ");
10583 if((regs[i].dirty>>3)&1) printf("ebx ");
10584 if((regs[i].dirty>>5)&1) printf("ebp ");
10585 if((regs[i].dirty>>6)&1) printf("esi ");
10586 if((regs[i].dirty>>7)&1) printf("edi ");
10589 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
10590 if(regs[i].dirty&1) printf("r0 ");
10591 if((regs[i].dirty>>1)&1) printf("r1 ");
10592 if((regs[i].dirty>>2)&1) printf("r2 ");
10593 if((regs[i].dirty>>3)&1) printf("r3 ");
10594 if((regs[i].dirty>>4)&1) printf("r4 ");
10595 if((regs[i].dirty>>5)&1) printf("r5 ");
10596 if((regs[i].dirty>>6)&1) printf("r6 ");
10597 if((regs[i].dirty>>7)&1) printf("r7 ");
10598 if((regs[i].dirty>>8)&1) printf("r8 ");
10599 if((regs[i].dirty>>9)&1) printf("r9 ");
10600 if((regs[i].dirty>>10)&1) printf("r10 ");
10601 if((regs[i].dirty>>12)&1) printf("r12 ");
10604 if(regs[i].isconst) {
10605 printf("constants: ");
10606 #if defined(__i386__) || defined(__x86_64__)
10607 if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
10608 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
10609 if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
10610 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
10611 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
10612 if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
10613 if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
10616 if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
10617 if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
10618 if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
10619 if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
10620 if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
10621 if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
10622 if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
10623 if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
10624 if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
10625 if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
10626 if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
10627 if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
10633 for(r=0;r<=CCREG;r++) {
10634 if((regs[i].is32>>r)&1) {
10635 if(r==CCREG) printf(" CC");
10636 else if(r==HIREG) printf(" HI");
10637 else if(r==LOREG) printf(" LO");
10638 else printf(" r%d",r);
10644 for(r=0;r<=CCREG;r++) {
10645 if((p32[i]>>r)&1) {
10646 if(r==CCREG) printf(" CC");
10647 else if(r==HIREG) printf(" HI");
10648 else if(r==LOREG) printf(" LO");
10649 else printf(" r%d",r);
10652 if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
10653 else printf("\n");*/
10654 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10655 #if defined(__i386__) || defined(__x86_64__)
10656 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
10657 if(branch_regs[i].dirty&1) printf("eax ");
10658 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
10659 if((branch_regs[i].dirty>>2)&1) printf("edx ");
10660 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
10661 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
10662 if((branch_regs[i].dirty>>6)&1) printf("esi ");
10663 if((branch_regs[i].dirty>>7)&1) printf("edi ");
10666 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
10667 if(branch_regs[i].dirty&1) printf("r0 ");
10668 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
10669 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
10670 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
10671 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
10672 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
10673 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
10674 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
10675 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
10676 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
10677 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
10678 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
10682 for(r=0;r<=CCREG;r++) {
10683 if((branch_regs[i].is32>>r)&1) {
10684 if(r==CCREG) printf(" CC");
10685 else if(r==HIREG) printf(" HI");
10686 else if(r==LOREG) printf(" LO");
10687 else printf(" r%d",r);
10695 /* Pass 8 - Assembly */
10696 linkcount=0;stubcount=0;
10697 ds=0;is_delayslot=0;
10699 uint64_t is32_pre=0;
10701 u_int beginning=(u_int)out;
10702 if((u_int)addr&1) {
10706 u_int instr_addr0_override=0;
10709 if (start == 0x80030000) {
10710 // nasty hack for fastbios thing
10711 instr_addr0_override=(u_int)out;
10712 emit_movimm(start,0);
10713 emit_readword((int)&pcaddr,1);
10714 emit_writeword(0,(int)&pcaddr);
10716 emit_jne((int)new_dyna_leave);
10719 for(i=0;i<slen;i++)
10721 //if(ds) printf("ds: ");
10722 if((void*)assem_debug==(void*)printf) disassemble_inst(i);
10724 ds=0; // Skip delay slot
10725 if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
10728 #ifndef DESTRUCTIVE_WRITEBACK
10729 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10731 wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
10732 unneeded_reg[i],unneeded_reg_upper[i]);
10733 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
10734 unneeded_reg[i],unneeded_reg_upper[i]);
10736 is32_pre=regs[i].is32;
10737 dirty_pre=regs[i].dirty;
10740 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10742 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
10743 unneeded_reg[i],unneeded_reg_upper[i]);
10744 loop_preload(regmap_pre[i],regs[i].regmap_entry);
10746 // branch target entry point
10747 instr_addr[i]=(u_int)out;
10748 assem_debug("<->\n");
10750 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&®s[i].regmap[HOST_CCREG]!=CCREG)
10751 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
10752 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
10753 address_generation(i,®s[i],regs[i].regmap_entry);
10754 load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
10755 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10757 // Load the delay slot registers if necessary
10758 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10759 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10760 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10761 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
10762 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
10763 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10767 // Preload registers for following instruction
10768 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10769 if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
10770 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10771 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10772 if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
10773 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
10775 // TODO: if(is_ooo(i)) address_generation(i+1);
10776 if(itype[i]==CJUMP||itype[i]==FJUMP)
10777 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
10778 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
10779 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10780 if(bt[i]) cop1_usable=0;
10784 alu_assemble(i,®s[i]);break;
10786 imm16_assemble(i,®s[i]);break;
10788 shift_assemble(i,®s[i]);break;
10790 shiftimm_assemble(i,®s[i]);break;
10792 load_assemble(i,®s[i]);break;
10794 loadlr_assemble(i,®s[i]);break;
10796 store_assemble(i,®s[i]);break;
10798 storelr_assemble(i,®s[i]);break;
10800 cop0_assemble(i,®s[i]);break;
10802 cop1_assemble(i,®s[i]);break;
10804 c1ls_assemble(i,®s[i]);break;
10806 cop2_assemble(i,®s[i]);break;
10808 c2ls_assemble(i,®s[i]);break;
10810 c2op_assemble(i,®s[i]);break;
10812 fconv_assemble(i,®s[i]);break;
10814 float_assemble(i,®s[i]);break;
10816 fcomp_assemble(i,®s[i]);break;
10818 multdiv_assemble(i,®s[i]);break;
10820 mov_assemble(i,®s[i]);break;
10822 syscall_assemble(i,®s[i]);break;
10824 hlecall_assemble(i,®s[i]);break;
10826 intcall_assemble(i,®s[i]);break;
10828 ujump_assemble(i,®s[i]);ds=1;break;
10830 rjump_assemble(i,®s[i]);ds=1;break;
10832 cjump_assemble(i,®s[i]);ds=1;break;
10834 sjump_assemble(i,®s[i]);ds=1;break;
10836 fjump_assemble(i,®s[i]);ds=1;break;
10838 pagespan_assemble(i,®s[i]);break;
10840 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10841 literal_pool(1024);
10843 literal_pool_jumpover(256);
10846 //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
10847 // If the block did not end with an unconditional branch,
10848 // add a jump to the next instruction.
10850 if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
10851 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10853 if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
10854 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10855 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10856 emit_loadreg(CCREG,HOST_CCREG);
10857 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10859 else if(!likely[i-2])
10861 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
10862 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
10866 store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
10867 assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
10869 add_to_linker((int)out,start+i*4,0);
10876 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10877 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10878 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10879 emit_loadreg(CCREG,HOST_CCREG);
10880 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10881 add_to_linker((int)out,start+i*4,0);
10885 // TODO: delay slot stubs?
10887 for(i=0;i<stubcount;i++)
10889 switch(stubs[i][0])
10897 do_readstub(i);break;
10902 do_writestub(i);break;
10904 do_ccstub(i);break;
10906 do_invstub(i);break;
10908 do_cop1stub(i);break;
10910 do_unalignedwritestub(i);break;
10914 if (instr_addr0_override)
10915 instr_addr[0] = instr_addr0_override;
10917 /* Pass 9 - Linker */
10918 for(i=0;i<linkcount;i++)
10920 assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
10922 if(!link_addr[i][2])
10925 void *addr=check_addr(link_addr[i][1]);
10926 emit_extjump(link_addr[i][0],link_addr[i][1]);
10928 set_jump_target(link_addr[i][0],(int)addr);
10929 add_link(link_addr[i][1],stub);
10931 else set_jump_target(link_addr[i][0],(int)stub);
10936 int target=(link_addr[i][1]-start)>>2;
10937 assert(target>=0&&target<slen);
10938 assert(instr_addr[target]);
10939 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10940 //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
10942 set_jump_target(link_addr[i][0],instr_addr[target]);
10946 // External Branch Targets (jump_in)
10947 if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
10948 for(i=0;i<slen;i++)
10952 if(instr_addr[i]) // TODO - delay slots (=null)
10954 u_int vaddr=start+i*4;
10955 u_int page=get_page(vaddr);
10956 u_int vpage=get_vpage(vaddr);
10958 //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
10960 if(!requires_32bit[i])
10965 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
10966 assem_debug("jump_in: %x\n",start+i*4);
10967 ll_add(jump_dirty+vpage,vaddr,(void *)out);
10968 int entry_point=do_dirty_stub(i);
10969 ll_add(jump_in+page,vaddr,(void *)entry_point);
10970 // If there was an existing entry in the hash table,
10971 // replace it with the new address.
10972 // Don't add new entries. We'll insert the
10973 // ones that actually get used in check_addr().
10974 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
10975 if(ht_bin[0]==vaddr) {
10976 ht_bin[1]=entry_point;
10978 if(ht_bin[2]==vaddr) {
10979 ht_bin[3]=entry_point;
10984 u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
10985 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
10986 assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
10987 //int entry_point=(int)out;
10988 ////assem_debug("entry_point: %x\n",entry_point);
10989 //load_regs_entry(i);
10990 //if(entry_point==(int)out)
10991 // entry_point=instr_addr[i];
10993 // emit_jmp(instr_addr[i]);
10994 //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
10995 ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
10996 int entry_point=do_dirty_stub(i);
10997 ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11002 // Write out the literal pool if necessary
11004 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11006 if(((u_int)out)&7) emit_addnop(13);
11008 assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
11009 //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
11010 memcpy(copy,source,slen*4);
11014 __clear_cache((void *)beginning,out);
11017 // If we're within 256K of the end of the buffer,
11018 // start over from the beginning. (Is 256K enough?)
11019 if((int)out>BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
11021 // Trap writes to any of the pages we compiled
11022 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
11024 #ifndef DISABLE_TLB
11025 memory_map[i]|=0x40000000;
11026 if((signed int)start>=(signed int)0xC0000000) {
11028 j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
11030 memory_map[j]|=0x40000000;
11031 //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
11036 /* Pass 10 - Free memory by expiring oldest blocks */
11038 int end=((((int)out-BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
11039 while(expirep!=end)
11041 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
11042 int base=BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
11043 inv_debug("EXP: Phase %d\n",expirep);
11044 switch((expirep>>11)&3)
11047 // Clear jump_in and jump_dirty
11048 ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
11049 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
11050 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
11051 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
11055 ll_kill_pointers(jump_out[expirep&2047],base,shift);
11056 ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
11059 // Clear hash table
11060 for(i=0;i<32;i++) {
11061 int *ht_bin=hash_table[((expirep&2047)<<5)+i];
11062 if((ht_bin[3]>>shift)==(base>>shift) ||
11063 ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11064 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
11065 ht_bin[2]=ht_bin[3]=-1;
11067 if((ht_bin[1]>>shift)==(base>>shift) ||
11068 ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11069 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
11070 ht_bin[0]=ht_bin[2];
11071 ht_bin[1]=ht_bin[3];
11072 ht_bin[2]=ht_bin[3]=-1;
11079 if((expirep&2047)==0)
11082 ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
11083 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
11086 expirep=(expirep+1)&65535;
11091 // vim:shiftwidth=2:expandtab