libpcsxcore/new_dynarec/new_dynarec.c

   1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
   2  *   Mupen64plus - new_dynarec.c                                           *
   3  *   Copyright (C) 2009-2011 Ari64                                         *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.          *
  19  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
  20
  21 #include <stdlib.h>
  22 #include <stdint.h> //include for uint64_t
  23 #include <assert.h>
  24 #include <errno.h>
  25 #include <sys/mman.h>
  26 #ifdef __MACH__
  27 #include <libkern/OSCacheControl.h>
  28 #endif
  29 #ifdef _3DS
  30 #include <3ds_utils.h>
  31 #endif
  32 #ifdef VITA
  33 #include <psp2/kernel/sysmem.h>
  34 static int sceBlock;
  35 #endif
  36
  37 #include "new_dynarec_config.h"
  38 #include "../psxhle.h"
  39 #include "../psxinterpreter.h"
  40 #include "../gte.h"
  41 #include "emu_if.h" // emulator interface
  42
  43 #define noinline __attribute__((noinline,noclone))
  44 #ifndef ARRAY_SIZE
  45 #define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
  46 #endif
  47 #ifndef min
  48 #define min(a, b) ((b) < (a) ? (b) : (a))
  49 #endif
  50 #ifndef max
  51 #define max(a, b) ((b) > (a) ? (b) : (a))
  52 #endif
  53
  54 //#define DISASM
  55 //#define ASSEM_PRINT
  56
  57 #ifdef ASSEM_PRINT
  58 #define assem_debug printf
  59 #else
  60 #define assem_debug(...)
  61 #endif
  62 //#define inv_debug printf
  63 #define inv_debug(...)
  64
  65 #ifdef __i386__
  66 #include "assem_x86.h"
  67 #endif
  68 #ifdef __x86_64__
  69 #include "assem_x64.h"
  70 #endif
  71 #ifdef __arm__
  72 #include "assem_arm.h"
  73 #endif
  74 #ifdef __aarch64__
  75 #include "assem_arm64.h"
  76 #endif
  77
  78 #define RAM_SIZE 0x200000
  79 #define MAXBLOCK 4096
  80 #define MAX_OUTPUT_BLOCK_SIZE 262144
  81
  82 struct ndrc_mem
  83 {
  84   u_char translation_cache[1 << TARGET_SIZE_2];
  85   struct
  86   {
  87     struct tramp_insns ops[2048 / sizeof(struct tramp_insns)];
  88     const void *f[2048 / sizeof(void *)];
  89   } tramp;
  90 };
  91
  92 #ifdef BASE_ADDR_DYNAMIC
  93 static struct ndrc_mem *ndrc;
  94 #else
  95 static struct ndrc_mem ndrc_ __attribute__((aligned(4096)));
  96 static struct ndrc_mem *ndrc = &ndrc_;
  97 #endif
  98
  99 // stubs
 100 enum stub_type {
 101   CC_STUB = 1,
 102   FP_STUB = 2,
 103   LOADB_STUB = 3,
 104   LOADH_STUB = 4,
 105   LOADW_STUB = 5,
 106   LOADD_STUB = 6,
 107   LOADBU_STUB = 7,
 108   LOADHU_STUB = 8,
 109   STOREB_STUB = 9,
 110   STOREH_STUB = 10,
 111   STOREW_STUB = 11,
 112   STORED_STUB = 12,
 113   STORELR_STUB = 13,
 114   INVCODE_STUB = 14,
 115 };
 116
 117 struct regstat
 118 {
 119   signed char regmap_entry[HOST_REGS];
 120   signed char regmap[HOST_REGS];
 121   uint64_t wasdirty;
 122   uint64_t dirty;
 123   uint64_t u;
 124   u_int wasconst;
 125   u_int isconst;
 126   u_int loadedconst;             // host regs that have constants loaded
 127   u_int waswritten;              // MIPS regs that were used as store base before
 128 };
 129
 130 // note: asm depends on this layout
 131 struct ll_entry
 132 {
 133   u_int vaddr;
 134   u_int reg_sv_flags;
 135   void *addr;
 136   struct ll_entry *next;
 137 };
 138
 139 struct ht_entry
 140 {
 141   u_int vaddr[2];
 142   void *tcaddr[2];
 143 };
 144
 145 struct code_stub
 146 {
 147   enum stub_type type;
 148   void *addr;
 149   void *retaddr;
 150   u_int a;
 151   uintptr_t b;
 152   uintptr_t c;
 153   u_int d;
 154   u_int e;
 155 };
 156
 157 struct link_entry
 158 {
 159   void *addr;
 160   u_int target;
 161   u_int ext;
 162 };
 163
 164 static struct decoded_insn
 165 {
 166   u_char itype;
 167   u_char opcode;
 168   u_char opcode2;
 169   u_char rs1;
 170   u_char rs2;
 171   u_char rt1;
 172   u_char rt2;
 173   u_char lt1;
 174   u_char bt:1;
 175   u_char ooo:1;
 176   u_char is_ds:1;
 177   u_char is_jump:1;
 178   u_char is_ujump:1;
 179 } dops[MAXBLOCK];
 180
 181   // used by asm:
 182   u_char *out;
 183   struct ht_entry hash_table[65536]  __attribute__((aligned(16)));
 184   struct ll_entry *jump_in[4096] __attribute__((aligned(16)));
 185   struct ll_entry *jump_dirty[4096];
 186
 187   static struct ll_entry *jump_out[4096];
 188   static u_int start;
 189   static u_int *source;
 190   static char insn[MAXBLOCK][10];
 191   static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
 192   static uint64_t gte_rt[MAXBLOCK];
 193   static uint64_t gte_unneeded[MAXBLOCK];
 194   static u_int smrv[32]; // speculated MIPS register values
 195   static u_int smrv_strong; // mask or regs that are likely to have correct values
 196   static u_int smrv_weak; // same, but somewhat less likely
 197   static u_int smrv_strong_next; // same, but after current insn executes
 198   static u_int smrv_weak_next;
 199   static int imm[MAXBLOCK];
 200   static u_int ba[MAXBLOCK];
 201   static uint64_t unneeded_reg[MAXBLOCK];
 202   static uint64_t branch_unneeded_reg[MAXBLOCK];
 203   static signed char regmap_pre[MAXBLOCK][HOST_REGS]; // pre-instruction i?
 204   // contains 'real' consts at [i] insn, but may differ from what's actually
 205   // loaded in host reg as 'final' value is always loaded, see get_final_value()
 206   static uint32_t current_constmap[HOST_REGS];
 207   static uint32_t constmap[MAXBLOCK][HOST_REGS];
 208   static struct regstat regs[MAXBLOCK];
 209   static struct regstat branch_regs[MAXBLOCK];
 210   static signed char minimum_free_regs[MAXBLOCK];
 211   static u_int needed_reg[MAXBLOCK];
 212   static u_int wont_dirty[MAXBLOCK];
 213   static u_int will_dirty[MAXBLOCK];
 214   static int ccadj[MAXBLOCK];
 215   static int slen;
 216   static void *instr_addr[MAXBLOCK];
 217   static struct link_entry link_addr[MAXBLOCK];
 218   static int linkcount;
 219   static struct code_stub stubs[MAXBLOCK*3];
 220   static int stubcount;
 221   static u_int literals[1024][2];
 222   static int literalcount;
 223   static int is_delayslot;
 224   static char shadow[1048576]  __attribute__((aligned(16)));
 225   static void *copy;
 226   static int expirep;
 227   static u_int stop_after_jal;
 228   static u_int f1_hack; // 0 - off, ~0 - capture address, else addr
 229 #ifndef RAM_FIXED
 230   static uintptr_t ram_offset;
 231 #else
 232   static const uintptr_t ram_offset=0;
 233 #endif
 234
 235   int new_dynarec_hacks;
 236   int new_dynarec_hacks_pergame;
 237   int new_dynarec_hacks_old;
 238   int new_dynarec_did_compile;
 239
 240   #define HACK_ENABLED(x) ((new_dynarec_hacks | new_dynarec_hacks_pergame) & (x))
 241
 242   extern int cycle_count; // ... until end of the timeslice, counts -N -> 0
 243   extern int last_count;  // last absolute target, often = next_interupt
 244   extern int pcaddr;
 245   extern int pending_exception;
 246   extern int branch_target;
 247   extern uintptr_t mini_ht[32][2];
 248   extern u_char restore_candidate[512];
 249
 250   /* registers that may be allocated */
 251   /* 1-31 gpr */
 252 #define LOREG 32 // lo
 253 #define HIREG 33 // hi
 254 //#define FSREG 34 // FPU status (FCSR)
 255 #define CSREG 35 // Coprocessor status
 256 #define CCREG 36 // Cycle count
 257 #define INVCP 37 // Pointer to invalid_code
 258 //#define MMREG 38 // Pointer to memory_map
 259 //#define ROREG 39 // ram offset (if rdram!=0x80000000)
 260 #define TEMPREG 40
 261 #define FTEMP 40 // FPU temporary register
 262 #define PTEMP 41 // Prefetch temporary register
 263 //#define TLREG 42 // TLB mapping offset
 264 #define RHASH 43 // Return address hash
 265 #define RHTBL 44 // Return address hash table address
 266 #define RTEMP 45 // JR/JALR address register
 267 #define MAXREG 45
 268 #define AGEN1 46 // Address generation temporary register
 269 //#define AGEN2 47 // Address generation temporary register
 270 //#define MGEN1 48 // Maptable address generation temporary register
 271 //#define MGEN2 49 // Maptable address generation temporary register
 272 #define BTREG 50 // Branch target temporary register
 273
 274   /* instruction types */
 275 #define NOP 0     // No operation
 276 #define LOAD 1    // Load
 277 #define STORE 2   // Store
 278 #define LOADLR 3  // Unaligned load
 279 #define STORELR 4 // Unaligned store
 280 #define MOV 5     // Move
 281 #define ALU 6     // Arithmetic/logic
 282 #define MULTDIV 7 // Multiply/divide
 283 #define SHIFT 8   // Shift by register
 284 #define SHIFTIMM 9// Shift by immediate
 285 #define IMM16 10  // 16-bit immediate
 286 #define RJUMP 11  // Unconditional jump to register
 287 #define UJUMP 12  // Unconditional jump
 288 #define CJUMP 13  // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
 289 #define SJUMP 14  // Conditional branch (regimm format)
 290 #define COP0 15   // Coprocessor 0
 291 #define COP1 16   // Coprocessor 1
 292 #define C1LS 17   // Coprocessor 1 load/store
 293 //#define FJUMP 18  // Conditional branch (floating point)
 294 //#define FLOAT 19  // Floating point unit
 295 //#define FCONV 20  // Convert integer to float
 296 //#define FCOMP 21  // Floating point compare (sets FSREG)
 297 #define SYSCALL 22// SYSCALL
 298 #define OTHER 23  // Other
 299 #define SPAN 24   // Branch/delay slot spans 2 pages
 300 #define NI 25     // Not implemented
 301 #define HLECALL 26// PCSX fake opcodes for HLE
 302 #define COP2 27   // Coprocessor 2 move
 303 #define C2LS 28   // Coprocessor 2 load/store
 304 #define C2OP 29   // Coprocessor 2 operation
 305 #define INTCALL 30// Call interpreter to handle rare corner cases
 306
 307   /* branch codes */
 308 #define TAKEN 1
 309 #define NOTTAKEN 2
 310 #define NULLDS 3
 311
 312 #define DJT_1 (void *)1l // no function, just a label in assem_debug log
 313 #define DJT_2 (void *)2l
 314
 315 // asm linkage
 316 int new_recompile_block(u_int addr);
 317 void *get_addr_ht(u_int vaddr);
 318 void invalidate_block(u_int block);
 319 void invalidate_addr(u_int addr);
 320 void remove_hash(int vaddr);
 321 void dyna_linker();
 322 void dyna_linker_ds();
 323 void verify_code();
 324 void verify_code_ds();
 325 void cc_interrupt();
 326 void fp_exception();
 327 void fp_exception_ds();
 328 void jump_to_new_pc();
 329 void call_gteStall();
 330 void new_dyna_leave();
 331
 332 // Needed by assembler
 333 static void wb_register(signed char r,signed char regmap[],uint64_t dirty);
 334 static void wb_dirtys(signed char i_regmap[],uint64_t i_dirty);
 335 static void wb_needed_dirtys(signed char i_regmap[],uint64_t i_dirty,int addr);
 336 static void load_all_regs(signed char i_regmap[]);
 337 static void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
 338 static void load_regs_entry(int t);
 339 static void load_all_consts(signed char regmap[],u_int dirty,int i);
 340 static u_int get_host_reglist(const signed char *regmap);
 341
 342 static int verify_dirty(const u_int *ptr);
 343 static int get_final_value(int hr, int i, int *value);
 344 static void add_stub(enum stub_type type, void *addr, void *retaddr,
 345   u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e);
 346 static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
 347   int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist);
 348 static void add_to_linker(void *addr, u_int target, int ext);
 349 static void *emit_fastpath_cmp_jump(int i,int addr,int *addr_reg_override);
 350 static void *get_direct_memhandler(void *table, u_int addr,
 351   enum stub_type type, uintptr_t *addr_host);
 352 static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist);
 353 static void pass_args(int a0, int a1);
 354 static void emit_far_jump(const void *f);
 355 static void emit_far_call(const void *f);
 356
 357 static void mprotect_w_x(void *start, void *end, int is_x)
 358 {
 359 #ifdef NO_WRITE_EXEC
 360   #if defined(VITA)
 361   // *Open* enables write on all memory that was
 362   // allocated by sceKernelAllocMemBlockForVM()?
 363   if (is_x)
 364     sceKernelCloseVMDomain();
 365   else
 366     sceKernelOpenVMDomain();
 367   #else
 368   u_long mstart = (u_long)start & ~4095ul;
 369   u_long mend = (u_long)end;
 370   if (mprotect((void *)mstart, mend - mstart,
 371                PROT_READ | (is_x ? PROT_EXEC : PROT_WRITE)) != 0)
 372     SysPrintf("mprotect(%c) failed: %s\n", is_x ? 'x' : 'w', strerror(errno));
 373   #endif
 374 #endif
 375 }
 376
 377 static void start_tcache_write(void *start, void *end)
 378 {
 379   mprotect_w_x(start, end, 0);
 380 }
 381
 382 static void end_tcache_write(void *start, void *end)
 383 {
 384 #if defined(__arm__) || defined(__aarch64__)
 385   size_t len = (char *)end - (char *)start;
 386   #if   defined(__BLACKBERRY_QNX__)
 387   msync(start, len, MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE);
 388   #elif defined(__MACH__)
 389   sys_cache_control(kCacheFunctionPrepareForExecution, start, len);
 390   #elif defined(VITA)
 391   sceKernelSyncVMDomain(sceBlock, start, len);
 392   #elif defined(_3DS)
 393   ctr_flush_invalidate_cache();
 394   #elif defined(__aarch64__)
 395   // as of 2021, __clear_cache() is still broken on arm64
 396   // so here is a custom one :(
 397   clear_cache_arm64(start, end);
 398   #else
 399   __clear_cache(start, end);
 400   #endif
 401   (void)len;
 402 #endif
 403
 404   mprotect_w_x(start, end, 1);
 405 }
 406
 407 static void *start_block(void)
 408 {
 409   u_char *end = out + MAX_OUTPUT_BLOCK_SIZE;
 410   if (end > ndrc->translation_cache + sizeof(ndrc->translation_cache))
 411     end = ndrc->translation_cache + sizeof(ndrc->translation_cache);
 412   start_tcache_write(out, end);
 413   return out;
 414 }
 415
 416 static void end_block(void *start)
 417 {
 418   end_tcache_write(start, out);
 419 }
 420
 421 // also takes care of w^x mappings when patching code
 422 static u_int needs_clear_cache[1<<(TARGET_SIZE_2-17)];
 423
 424 static void mark_clear_cache(void *target)
 425 {
 426   uintptr_t offset = (u_char *)target - ndrc->translation_cache;
 427   u_int mask = 1u << ((offset >> 12) & 31);
 428   if (!(needs_clear_cache[offset >> 17] & mask)) {
 429     char *start = (char *)((uintptr_t)target & ~4095l);
 430     start_tcache_write(start, start + 4095);
 431     needs_clear_cache[offset >> 17] |= mask;
 432   }
 433 }
 434
 435 // Clearing the cache is rather slow on ARM Linux, so mark the areas
 436 // that need to be cleared, and then only clear these areas once.
 437 static void do_clear_cache(void)
 438 {
 439   int i, j;
 440   for (i = 0; i < (1<<(TARGET_SIZE_2-17)); i++)
 441   {
 442     u_int bitmap = needs_clear_cache[i];
 443     if (!bitmap)
 444       continue;
 445     for (j = 0; j < 32; j++)
 446     {
 447       u_char *start, *end;
 448       if (!(bitmap & (1<<j)))
 449         continue;
 450
 451       start = ndrc->translation_cache + i*131072 + j*4096;
 452       end = start + 4095;
 453       for (j++; j < 32; j++) {
 454         if (!(bitmap & (1<<j)))
 455           break;
 456         end += 4096;
 457       }
 458       end_tcache_write(start, end);
 459     }
 460     needs_clear_cache[i] = 0;
 461   }
 462 }
 463
 464 //#define DEBUG_CYCLE_COUNT 1
 465
 466 #define NO_CYCLE_PENALTY_THR 12
 467
 468 int cycle_multiplier; // 100 for 1.0
 469 int cycle_multiplier_override;
 470 int cycle_multiplier_old;
 471
 472 static int CLOCK_ADJUST(int x)
 473 {
 474   int m = cycle_multiplier_override
 475         ? cycle_multiplier_override : cycle_multiplier;
 476   int s=(x>>31)|1;
 477   return (x * m + s * 50) / 100;
 478 }
 479
 480 static int ds_writes_rjump_rs(int i)
 481 {
 482   return dops[i].rs1 != 0 && (dops[i].rs1 == dops[i+1].rt1 || dops[i].rs1 == dops[i+1].rt2);
 483 }
 484
 485 static u_int get_page(u_int vaddr)
 486 {
 487   u_int page=vaddr&~0xe0000000;
 488   if (page < 0x1000000)
 489     page &= ~0x0e00000; // RAM mirrors
 490   page>>=12;
 491   if(page>2048) page=2048+(page&2047);
 492   return page;
 493 }
 494
 495 // no virtual mem in PCSX
 496 static u_int get_vpage(u_int vaddr)
 497 {
 498   return get_page(vaddr);
 499 }
 500
 501 static struct ht_entry *hash_table_get(u_int vaddr)
 502 {
 503   return &hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 504 }
 505
 506 static void hash_table_add(struct ht_entry *ht_bin, u_int vaddr, void *tcaddr)
 507 {
 508   ht_bin->vaddr[1] = ht_bin->vaddr[0];
 509   ht_bin->tcaddr[1] = ht_bin->tcaddr[0];
 510   ht_bin->vaddr[0] = vaddr;
 511   ht_bin->tcaddr[0] = tcaddr;
 512 }
 513
 514 // some messy ari64's code, seems to rely on unsigned 32bit overflow
 515 static int doesnt_expire_soon(void *tcaddr)
 516 {
 517   u_int diff = (u_int)((u_char *)tcaddr - out) << (32-TARGET_SIZE_2);
 518   return diff > (u_int)(0x60000000 + (MAX_OUTPUT_BLOCK_SIZE << (32-TARGET_SIZE_2)));
 519 }
 520
 521 // Get address from virtual address
 522 // This is called from the recompiled JR/JALR instructions
 523 void noinline *get_addr(u_int vaddr)
 524 {
 525   u_int page=get_page(vaddr);
 526   u_int vpage=get_vpage(vaddr);
 527   struct ll_entry *head;
 528   //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
 529   head=jump_in[page];
 530   while(head!=NULL) {
 531     if(head->vaddr==vaddr) {
 532   //printf("TRACE: count=%d next=%d (get_addr match %x: %p)\n",Count,next_interupt,vaddr,head->addr);
 533       hash_table_add(hash_table_get(vaddr), vaddr, head->addr);
 534       return head->addr;
 535     }
 536     head=head->next;
 537   }
 538   head=jump_dirty[vpage];
 539   while(head!=NULL) {
 540     if(head->vaddr==vaddr) {
 541       //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %p)\n",Count,next_interupt,vaddr,head->addr);
 542       // Don't restore blocks which are about to expire from the cache
 543       if (doesnt_expire_soon(head->addr))
 544       if (verify_dirty(head->addr)) {
 545         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
 546         invalid_code[vaddr>>12]=0;
 547         inv_code_start=inv_code_end=~0;
 548         if(vpage<2048) {
 549           restore_candidate[vpage>>3]|=1<<(vpage&7);
 550         }
 551         else restore_candidate[page>>3]|=1<<(page&7);
 552         struct ht_entry *ht_bin = hash_table_get(vaddr);
 553         if (ht_bin->vaddr[0] == vaddr)
 554           ht_bin->tcaddr[0] = head->addr; // Replace existing entry
 555         else
 556           hash_table_add(ht_bin, vaddr, head->addr);
 557
 558         return head->addr;
 559       }
 560     }
 561     head=head->next;
 562   }
 563   //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
 564   int r=new_recompile_block(vaddr);
 565   if(r==0) return get_addr(vaddr);
 566   // Execute in unmapped page, generate pagefault execption
 567   Status|=2;
 568   Cause=(vaddr<<31)|0x8;
 569   EPC=(vaddr&1)?vaddr-5:vaddr;
 570   BadVAddr=(vaddr&~1);
 571   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
 572   EntryHi=BadVAddr&0xFFFFE000;
 573   return get_addr_ht(0x80000000);
 574 }
 575 // Look up address in hash table first
 576 void *get_addr_ht(u_int vaddr)
 577 {
 578   //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
 579   const struct ht_entry *ht_bin = hash_table_get(vaddr);
 580   if (ht_bin->vaddr[0] == vaddr) return ht_bin->tcaddr[0];
 581   if (ht_bin->vaddr[1] == vaddr) return ht_bin->tcaddr[1];
 582   return get_addr(vaddr);
 583 }
 584
 585 void clear_all_regs(signed char regmap[])
 586 {
 587   int hr;
 588   for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
 589 }
 590
 591 static signed char get_reg(const signed char regmap[],int r)
 592 {
 593   int hr;
 594   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
 595   return -1;
 596 }
 597
 598 // Find a register that is available for two consecutive cycles
 599 static signed char get_reg2(signed char regmap1[], const signed char regmap2[], int r)
 600 {
 601   int hr;
 602   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
 603   return -1;
 604 }
 605
 606 int count_free_regs(signed char regmap[])
 607 {
 608   int count=0;
 609   int hr;
 610   for(hr=0;hr<HOST_REGS;hr++)
 611   {
 612     if(hr!=EXCLUDE_REG) {
 613       if(regmap[hr]<0) count++;
 614     }
 615   }
 616   return count;
 617 }
 618
 619 void dirty_reg(struct regstat *cur,signed char reg)
 620 {
 621   int hr;
 622   if(!reg) return;
 623   for (hr=0;hr<HOST_REGS;hr++) {
 624     if((cur->regmap[hr]&63)==reg) {
 625       cur->dirty|=1<<hr;
 626     }
 627   }
 628 }
 629
 630 static void set_const(struct regstat *cur, signed char reg, uint32_t value)
 631 {
 632   int hr;
 633   if(!reg) return;
 634   for (hr=0;hr<HOST_REGS;hr++) {
 635     if(cur->regmap[hr]==reg) {
 636       cur->isconst|=1<<hr;
 637       current_constmap[hr]=value;
 638     }
 639   }
 640 }
 641
 642 static void clear_const(struct regstat *cur, signed char reg)
 643 {
 644   int hr;
 645   if(!reg) return;
 646   for (hr=0;hr<HOST_REGS;hr++) {
 647     if((cur->regmap[hr]&63)==reg) {
 648       cur->isconst&=~(1<<hr);
 649     }
 650   }
 651 }
 652
 653 static int is_const(struct regstat *cur, signed char reg)
 654 {
 655   int hr;
 656   if(reg<0) return 0;
 657   if(!reg) return 1;
 658   for (hr=0;hr<HOST_REGS;hr++) {
 659     if((cur->regmap[hr]&63)==reg) {
 660       return (cur->isconst>>hr)&1;
 661     }
 662   }
 663   return 0;
 664 }
 665
 666 static uint32_t get_const(struct regstat *cur, signed char reg)
 667 {
 668   int hr;
 669   if(!reg) return 0;
 670   for (hr=0;hr<HOST_REGS;hr++) {
 671     if(cur->regmap[hr]==reg) {
 672       return current_constmap[hr];
 673     }
 674   }
 675   SysPrintf("Unknown constant in r%d\n",reg);
 676   abort();
 677 }
 678
 679 // Least soon needed registers
 680 // Look at the next ten instructions and see which registers
 681 // will be used.  Try not to reallocate these.
 682 void lsn(u_char hsn[], int i, int *preferred_reg)
 683 {
 684   int j;
 685   int b=-1;
 686   for(j=0;j<9;j++)
 687   {
 688     if(i+j>=slen) {
 689       j=slen-i-1;
 690       break;
 691     }
 692     if (dops[i+j].is_ujump)
 693     {
 694       // Don't go past an unconditonal jump
 695       j++;
 696       break;
 697     }
 698   }
 699   for(;j>=0;j--)
 700   {
 701     if(dops[i+j].rs1) hsn[dops[i+j].rs1]=j;
 702     if(dops[i+j].rs2) hsn[dops[i+j].rs2]=j;
 703     if(dops[i+j].rt1) hsn[dops[i+j].rt1]=j;
 704     if(dops[i+j].rt2) hsn[dops[i+j].rt2]=j;
 705     if(dops[i+j].itype==STORE || dops[i+j].itype==STORELR) {
 706       // Stores can allocate zero
 707       hsn[dops[i+j].rs1]=j;
 708       hsn[dops[i+j].rs2]=j;
 709     }
 710     // On some architectures stores need invc_ptr
 711     #if defined(HOST_IMM8)
 712     if(dops[i+j].itype==STORE || dops[i+j].itype==STORELR || (dops[i+j].opcode&0x3b)==0x39 || (dops[i+j].opcode&0x3b)==0x3a) {
 713       hsn[INVCP]=j;
 714     }
 715     #endif
 716     if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
 717     {
 718       hsn[CCREG]=j;
 719       b=j;
 720     }
 721   }
 722   if(b>=0)
 723   {
 724     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 725     {
 726       // Follow first branch
 727       int t=(ba[i+b]-start)>>2;
 728       j=7-b;if(t+j>=slen) j=slen-t-1;
 729       for(;j>=0;j--)
 730       {
 731         if(dops[t+j].rs1) if(hsn[dops[t+j].rs1]>j+b+2) hsn[dops[t+j].rs1]=j+b+2;
 732         if(dops[t+j].rs2) if(hsn[dops[t+j].rs2]>j+b+2) hsn[dops[t+j].rs2]=j+b+2;
 733         //if(dops[t+j].rt1) if(hsn[dops[t+j].rt1]>j+b+2) hsn[dops[t+j].rt1]=j+b+2;
 734         //if(dops[t+j].rt2) if(hsn[dops[t+j].rt2]>j+b+2) hsn[dops[t+j].rt2]=j+b+2;
 735       }
 736     }
 737     // TODO: preferred register based on backward branch
 738   }
 739   // Delay slot should preferably not overwrite branch conditions or cycle count
 740   if (i > 0 && dops[i-1].is_jump) {
 741     if(dops[i-1].rs1) if(hsn[dops[i-1].rs1]>1) hsn[dops[i-1].rs1]=1;
 742     if(dops[i-1].rs2) if(hsn[dops[i-1].rs2]>1) hsn[dops[i-1].rs2]=1;
 743     hsn[CCREG]=1;
 744     // ...or hash tables
 745     hsn[RHASH]=1;
 746     hsn[RHTBL]=1;
 747   }
 748   // Coprocessor load/store needs FTEMP, even if not declared
 749   if(dops[i].itype==C1LS||dops[i].itype==C2LS) {
 750     hsn[FTEMP]=0;
 751   }
 752   // Load L/R also uses FTEMP as a temporary register
 753   if(dops[i].itype==LOADLR) {
 754     hsn[FTEMP]=0;
 755   }
 756   // Also SWL/SWR/SDL/SDR
 757   if(dops[i].opcode==0x2a||dops[i].opcode==0x2e||dops[i].opcode==0x2c||dops[i].opcode==0x2d) {
 758     hsn[FTEMP]=0;
 759   }
 760   // Don't remove the miniht registers
 761   if(dops[i].itype==UJUMP||dops[i].itype==RJUMP)
 762   {
 763     hsn[RHASH]=0;
 764     hsn[RHTBL]=0;
 765   }
 766 }
 767
 768 // We only want to allocate registers if we're going to use them again soon
 769 int needed_again(int r, int i)
 770 {
 771   int j;
 772   int b=-1;
 773   int rn=10;
 774
 775   if (i > 0 && dops[i-1].is_ujump)
 776   {
 777     if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
 778       return 0; // Don't need any registers if exiting the block
 779   }
 780   for(j=0;j<9;j++)
 781   {
 782     if(i+j>=slen) {
 783       j=slen-i-1;
 784       break;
 785     }
 786     if (dops[i+j].is_ujump)
 787     {
 788       // Don't go past an unconditonal jump
 789       j++;
 790       break;
 791     }
 792     if(dops[i+j].itype==SYSCALL||dops[i+j].itype==HLECALL||dops[i+j].itype==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
 793     {
 794       break;
 795     }
 796   }
 797   for(;j>=1;j--)
 798   {
 799     if(dops[i+j].rs1==r) rn=j;
 800     if(dops[i+j].rs2==r) rn=j;
 801     if((unneeded_reg[i+j]>>r)&1) rn=10;
 802     if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
 803     {
 804       b=j;
 805     }
 806   }
 807   if(rn<10) return 1;
 808   (void)b;
 809   return 0;
 810 }
 811
 812 // Try to match register allocations at the end of a loop with those
 813 // at the beginning
 814 int loop_reg(int i, int r, int hr)
 815 {
 816   int j,k;
 817   for(j=0;j<9;j++)
 818   {
 819     if(i+j>=slen) {
 820       j=slen-i-1;
 821       break;
 822     }
 823     if (dops[i+j].is_ujump)
 824     {
 825       // Don't go past an unconditonal jump
 826       j++;
 827       break;
 828     }
 829   }
 830   k=0;
 831   if(i>0){
 832     if(dops[i-1].itype==UJUMP||dops[i-1].itype==CJUMP||dops[i-1].itype==SJUMP)
 833       k--;
 834   }
 835   for(;k<j;k++)
 836   {
 837     assert(r < 64);
 838     if((unneeded_reg[i+k]>>r)&1) return hr;
 839     if(i+k>=0&&(dops[i+k].itype==UJUMP||dops[i+k].itype==CJUMP||dops[i+k].itype==SJUMP))
 840     {
 841       if(ba[i+k]>=start && ba[i+k]<(start+i*4))
 842       {
 843         int t=(ba[i+k]-start)>>2;
 844         int reg=get_reg(regs[t].regmap_entry,r);
 845         if(reg>=0) return reg;
 846         //reg=get_reg(regs[t+1].regmap_entry,r);
 847         //if(reg>=0) return reg;
 848       }
 849     }
 850   }
 851   return hr;
 852 }
 853
 854
 855 // Allocate every register, preserving source/target regs
 856 void alloc_all(struct regstat *cur,int i)
 857 {
 858   int hr;
 859
 860   for(hr=0;hr<HOST_REGS;hr++) {
 861     if(hr!=EXCLUDE_REG) {
 862       if(((cur->regmap[hr]&63)!=dops[i].rs1)&&((cur->regmap[hr]&63)!=dops[i].rs2)&&
 863          ((cur->regmap[hr]&63)!=dops[i].rt1)&&((cur->regmap[hr]&63)!=dops[i].rt2))
 864       {
 865         cur->regmap[hr]=-1;
 866         cur->dirty&=~(1<<hr);
 867       }
 868       // Don't need zeros
 869       if((cur->regmap[hr]&63)==0)
 870       {
 871         cur->regmap[hr]=-1;
 872         cur->dirty&=~(1<<hr);
 873       }
 874     }
 875   }
 876 }
 877
 878 #ifndef NDEBUG
 879 static int host_tempreg_in_use;
 880
 881 static void host_tempreg_acquire(void)
 882 {
 883   assert(!host_tempreg_in_use);
 884   host_tempreg_in_use = 1;
 885 }
 886
 887 static void host_tempreg_release(void)
 888 {
 889   host_tempreg_in_use = 0;
 890 }
 891 #else
 892 static void host_tempreg_acquire(void) {}
 893 static void host_tempreg_release(void) {}
 894 #endif
 895
 896 #ifdef ASSEM_PRINT
 897 extern void gen_interupt();
 898 extern void do_insn_cmp();
 899 #define FUNCNAME(f) { f, " " #f }
 900 static const struct {
 901   void *addr;
 902   const char *name;
 903 } function_names[] = {
 904   FUNCNAME(cc_interrupt),
 905   FUNCNAME(gen_interupt),
 906   FUNCNAME(get_addr_ht),
 907   FUNCNAME(get_addr),
 908   FUNCNAME(jump_handler_read8),
 909   FUNCNAME(jump_handler_read16),
 910   FUNCNAME(jump_handler_read32),
 911   FUNCNAME(jump_handler_write8),
 912   FUNCNAME(jump_handler_write16),
 913   FUNCNAME(jump_handler_write32),
 914   FUNCNAME(invalidate_addr),
 915   FUNCNAME(jump_to_new_pc),
 916   FUNCNAME(call_gteStall),
 917   FUNCNAME(new_dyna_leave),
 918   FUNCNAME(pcsx_mtc0),
 919   FUNCNAME(pcsx_mtc0_ds),
 920 #ifdef DRC_DBG
 921   FUNCNAME(do_insn_cmp),
 922 #endif
 923 #ifdef __arm__
 924   FUNCNAME(verify_code),
 925 #endif
 926 };
 927
 928 static const char *func_name(const void *a)
 929 {
 930   int i;
 931   for (i = 0; i < sizeof(function_names)/sizeof(function_names[0]); i++)
 932     if (function_names[i].addr == a)
 933       return function_names[i].name;
 934   return "";
 935 }
 936 #else
 937 #define func_name(x) ""
 938 #endif
 939
 940 #ifdef __i386__
 941 #include "assem_x86.c"
 942 #endif
 943 #ifdef __x86_64__
 944 #include "assem_x64.c"
 945 #endif
 946 #ifdef __arm__
 947 #include "assem_arm.c"
 948 #endif
 949 #ifdef __aarch64__
 950 #include "assem_arm64.c"
 951 #endif
 952
 953 static void *get_trampoline(const void *f)
 954 {
 955   size_t i;
 956
 957   for (i = 0; i < ARRAY_SIZE(ndrc->tramp.f); i++) {
 958     if (ndrc->tramp.f[i] == f || ndrc->tramp.f[i] == NULL)
 959       break;
 960   }
 961   if (i == ARRAY_SIZE(ndrc->tramp.f)) {
 962     SysPrintf("trampoline table is full, last func %p\n", f);
 963     abort();
 964   }
 965   if (ndrc->tramp.f[i] == NULL) {
 966     start_tcache_write(&ndrc->tramp.f[i], &ndrc->tramp.f[i + 1]);
 967     ndrc->tramp.f[i] = f;
 968     end_tcache_write(&ndrc->tramp.f[i], &ndrc->tramp.f[i + 1]);
 969   }
 970   return &ndrc->tramp.ops[i];
 971 }
 972
 973 static void emit_far_jump(const void *f)
 974 {
 975   if (can_jump_or_call(f)) {
 976     emit_jmp(f);
 977     return;
 978   }
 979
 980   f = get_trampoline(f);
 981   emit_jmp(f);
 982 }
 983
 984 static void emit_far_call(const void *f)
 985 {
 986   if (can_jump_or_call(f)) {
 987     emit_call(f);
 988     return;
 989   }
 990
 991   f = get_trampoline(f);
 992   emit_call(f);
 993 }
 994
 995 // Add virtual address mapping to linked list
 996 void ll_add(struct ll_entry **head,int vaddr,void *addr)
 997 {
 998   struct ll_entry *new_entry;
 999   new_entry=malloc(sizeof(struct ll_entry));
1000   assert(new_entry!=NULL);
1001   new_entry->vaddr=vaddr;
1002   new_entry->reg_sv_flags=0;
1003   new_entry->addr=addr;
1004   new_entry->next=*head;
1005   *head=new_entry;
1006 }
1007
1008 void ll_add_flags(struct ll_entry **head,int vaddr,u_int reg_sv_flags,void *addr)
1009 {
1010   ll_add(head,vaddr,addr);
1011   (*head)->reg_sv_flags=reg_sv_flags;
1012 }
1013
1014 // Check if an address is already compiled
1015 // but don't return addresses which are about to expire from the cache
1016 void *check_addr(u_int vaddr)
1017 {
1018   struct ht_entry *ht_bin = hash_table_get(vaddr);
1019   size_t i;
1020   for (i = 0; i < ARRAY_SIZE(ht_bin->vaddr); i++) {
1021     if (ht_bin->vaddr[i] == vaddr)
1022       if (doesnt_expire_soon((u_char *)ht_bin->tcaddr[i] - MAX_OUTPUT_BLOCK_SIZE))
1023         if (isclean(ht_bin->tcaddr[i]))
1024           return ht_bin->tcaddr[i];
1025   }
1026   u_int page=get_page(vaddr);
1027   struct ll_entry *head;
1028   head=jump_in[page];
1029   while (head != NULL) {
1030     if (head->vaddr == vaddr) {
1031       if (doesnt_expire_soon(head->addr)) {
1032         // Update existing entry with current address
1033         if (ht_bin->vaddr[0] == vaddr) {
1034           ht_bin->tcaddr[0] = head->addr;
1035           return head->addr;
1036         }
1037         if (ht_bin->vaddr[1] == vaddr) {
1038           ht_bin->tcaddr[1] = head->addr;
1039           return head->addr;
1040         }
1041         // Insert into hash table with low priority.
1042         // Don't evict existing entries, as they are probably
1043         // addresses that are being accessed frequently.
1044         if (ht_bin->vaddr[0] == -1) {
1045           ht_bin->vaddr[0] = vaddr;
1046           ht_bin->tcaddr[0] = head->addr;
1047         }
1048         else if (ht_bin->vaddr[1] == -1) {
1049           ht_bin->vaddr[1] = vaddr;
1050           ht_bin->tcaddr[1] = head->addr;
1051         }
1052         return head->addr;
1053       }
1054     }
1055     head=head->next;
1056   }
1057   return 0;
1058 }
1059
1060 void remove_hash(int vaddr)
1061 {
1062   //printf("remove hash: %x\n",vaddr);
1063   struct ht_entry *ht_bin = hash_table_get(vaddr);
1064   if (ht_bin->vaddr[1] == vaddr) {
1065     ht_bin->vaddr[1] = -1;
1066     ht_bin->tcaddr[1] = NULL;
1067   }
1068   if (ht_bin->vaddr[0] == vaddr) {
1069     ht_bin->vaddr[0] = ht_bin->vaddr[1];
1070     ht_bin->tcaddr[0] = ht_bin->tcaddr[1];
1071     ht_bin->vaddr[1] = -1;
1072     ht_bin->tcaddr[1] = NULL;
1073   }
1074 }
1075
1076 static void ll_remove_matching_addrs(struct ll_entry **head,
1077   uintptr_t base_offs_s, int shift)
1078 {
1079   struct ll_entry *next;
1080   while(*head) {
1081     uintptr_t o1 = (u_char *)(*head)->addr - ndrc->translation_cache;
1082     uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
1083     if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s)
1084     {
1085       inv_debug("EXP: Remove pointer to %p (%x)\n",(*head)->addr,(*head)->vaddr);
1086       remove_hash((*head)->vaddr);
1087       next=(*head)->next;
1088       free(*head);
1089       *head=next;
1090     }
1091     else
1092     {
1093       head=&((*head)->next);
1094     }
1095   }
1096 }
1097
1098 // Remove all entries from linked list
1099 void ll_clear(struct ll_entry **head)
1100 {
1101   struct ll_entry *cur;
1102   struct ll_entry *next;
1103   if((cur=*head)) {
1104     *head=0;
1105     while(cur) {
1106       next=cur->next;
1107       free(cur);
1108       cur=next;
1109     }
1110   }
1111 }
1112
1113 // Dereference the pointers and remove if it matches
1114 static void ll_kill_pointers(struct ll_entry *head,
1115   uintptr_t base_offs_s, int shift)
1116 {
1117   while(head) {
1118     u_char *ptr = get_pointer(head->addr);
1119     uintptr_t o1 = ptr - ndrc->translation_cache;
1120     uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
1121     inv_debug("EXP: Lookup pointer to %p at %p (%x)\n",ptr,head->addr,head->vaddr);
1122     if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s)
1123     {
1124       inv_debug("EXP: Kill pointer at %p (%x)\n",head->addr,head->vaddr);
1125       void *host_addr=find_extjump_insn(head->addr);
1126       mark_clear_cache(host_addr);
1127       set_jump_target(host_addr, head->addr);
1128     }
1129     head=head->next;
1130   }
1131 }
1132
1133 // This is called when we write to a compiled block (see do_invstub)
1134 static void invalidate_page(u_int page)
1135 {
1136   struct ll_entry *head;
1137   struct ll_entry *next;
1138   head=jump_in[page];
1139   jump_in[page]=0;
1140   while(head!=NULL) {
1141     inv_debug("INVALIDATE: %x\n",head->vaddr);
1142     remove_hash(head->vaddr);
1143     next=head->next;
1144     free(head);
1145     head=next;
1146   }
1147   head=jump_out[page];
1148   jump_out[page]=0;
1149   while(head!=NULL) {
1150     inv_debug("INVALIDATE: kill pointer to %x (%p)\n",head->vaddr,head->addr);
1151     void *host_addr=find_extjump_insn(head->addr);
1152     mark_clear_cache(host_addr);
1153     set_jump_target(host_addr, head->addr); // point back to dyna_linker
1154     next=head->next;
1155     free(head);
1156     head=next;
1157   }
1158 }
1159
1160 static void invalidate_block_range(u_int block, u_int first, u_int last)
1161 {
1162   u_int page=get_page(block<<12);
1163   //printf("first=%d last=%d\n",first,last);
1164   invalidate_page(page);
1165   assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1166   assert(last<page+5);
1167   // Invalidate the adjacent pages if a block crosses a 4K boundary
1168   while(first<page) {
1169     invalidate_page(first);
1170     first++;
1171   }
1172   for(first=page+1;first<last;first++) {
1173     invalidate_page(first);
1174   }
1175   do_clear_cache();
1176
1177   // Don't trap writes
1178   invalid_code[block]=1;
1179
1180   #ifdef USE_MINI_HT
1181   memset(mini_ht,-1,sizeof(mini_ht));
1182   #endif
1183 }
1184
1185 void invalidate_block(u_int block)
1186 {
1187   u_int page=get_page(block<<12);
1188   u_int vpage=get_vpage(block<<12);
1189   inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1190   //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1191   u_int first,last;
1192   first=last=page;
1193   struct ll_entry *head;
1194   head=jump_dirty[vpage];
1195   //printf("page=%d vpage=%d\n",page,vpage);
1196   while(head!=NULL) {
1197     if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1198       u_char *start, *end;
1199       get_bounds(head->addr, &start, &end);
1200       //printf("start: %p end: %p\n", start, end);
1201       if (page < 2048 && start >= rdram && end < rdram+RAM_SIZE) {
1202         if (((start-rdram)>>12) <= page && ((end-1-rdram)>>12) >= page) {
1203           if ((((start-rdram)>>12)&2047) < first) first = ((start-rdram)>>12)&2047;
1204           if ((((end-1-rdram)>>12)&2047) > last)  last = ((end-1-rdram)>>12)&2047;
1205         }
1206       }
1207     }
1208     head=head->next;
1209   }
1210   invalidate_block_range(block,first,last);
1211 }
1212
1213 void invalidate_addr(u_int addr)
1214 {
1215   //static int rhits;
1216   // this check is done by the caller
1217   //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
1218   u_int page=get_vpage(addr);
1219   if(page<2048) { // RAM
1220     struct ll_entry *head;
1221     u_int addr_min=~0, addr_max=0;
1222     u_int mask=RAM_SIZE-1;
1223     u_int addr_main=0x80000000|(addr&mask);
1224     int pg1;
1225     inv_code_start=addr_main&~0xfff;
1226     inv_code_end=addr_main|0xfff;
1227     pg1=page;
1228     if (pg1>0) {
1229       // must check previous page too because of spans..
1230       pg1--;
1231       inv_code_start-=0x1000;
1232     }
1233     for(;pg1<=page;pg1++) {
1234       for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
1235         u_char *start_h, *end_h;
1236         u_int start, end;
1237         get_bounds(head->addr, &start_h, &end_h);
1238         start = (uintptr_t)start_h - ram_offset;
1239         end = (uintptr_t)end_h - ram_offset;
1240         if(start<=addr_main&&addr_main<end) {
1241           if(start<addr_min) addr_min=start;
1242           if(end>addr_max) addr_max=end;
1243         }
1244         else if(addr_main<start) {
1245           if(start<inv_code_end)
1246             inv_code_end=start-1;
1247         }
1248         else {
1249           if(end>inv_code_start)
1250             inv_code_start=end;
1251         }
1252       }
1253     }
1254     if (addr_min!=~0) {
1255       inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1256       inv_code_start=inv_code_end=~0;
1257       invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1258       return;
1259     }
1260     else {
1261       inv_code_start=(addr&~mask)|(inv_code_start&mask);
1262       inv_code_end=(addr&~mask)|(inv_code_end&mask);
1263       inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);
1264       return;
1265     }
1266   }
1267   invalidate_block(addr>>12);
1268 }
1269
1270 // This is called when loading a save state.
1271 // Anything could have changed, so invalidate everything.
1272 void invalidate_all_pages(void)
1273 {
1274   u_int page;
1275   for(page=0;page<4096;page++)
1276     invalidate_page(page);
1277   for(page=0;page<1048576;page++)
1278     if(!invalid_code[page]) {
1279       restore_candidate[(page&2047)>>3]|=1<<(page&7);
1280       restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1281     }
1282   #ifdef USE_MINI_HT
1283   memset(mini_ht,-1,sizeof(mini_ht));
1284   #endif
1285   do_clear_cache();
1286 }
1287
1288 static void do_invstub(int n)
1289 {
1290   literal_pool(20);
1291   u_int reglist=stubs[n].a;
1292   set_jump_target(stubs[n].addr, out);
1293   save_regs(reglist);
1294   if(stubs[n].b!=0) emit_mov(stubs[n].b,0);
1295   emit_far_call(invalidate_addr);
1296   restore_regs(reglist);
1297   emit_jmp(stubs[n].retaddr); // return address
1298 }
1299
1300 // Add an entry to jump_out after making a link
1301 // src should point to code by emit_extjump2()
1302 void add_jump_out(u_int vaddr,void *src)
1303 {
1304   u_int page=get_page(vaddr);
1305   inv_debug("add_jump_out: %p -> %x (%d)\n",src,vaddr,page);
1306   check_extjump2(src);
1307   ll_add(jump_out+page,vaddr,src);
1308   //inv_debug("add_jump_out:  to %p\n",get_pointer(src));
1309 }
1310
1311 // If a code block was found to be unmodified (bit was set in
1312 // restore_candidate) and it remains unmodified (bit is clear
1313 // in invalid_code) then move the entries for that 4K page from
1314 // the dirty list to the clean list.
1315 void clean_blocks(u_int page)
1316 {
1317   struct ll_entry *head;
1318   inv_debug("INV: clean_blocks page=%d\n",page);
1319   head=jump_dirty[page];
1320   while(head!=NULL) {
1321     if(!invalid_code[head->vaddr>>12]) {
1322       // Don't restore blocks which are about to expire from the cache
1323       if (doesnt_expire_soon(head->addr)) {
1324         if(verify_dirty(head->addr)) {
1325           u_char *start, *end;
1326           //printf("Possibly Restore %x (%p)\n",head->vaddr, head->addr);
1327           u_int i;
1328           u_int inv=0;
1329           get_bounds(head->addr, &start, &end);
1330           if (start - rdram < RAM_SIZE) {
1331             for (i = (start-rdram+0x80000000)>>12; i <= (end-1-rdram+0x80000000)>>12; i++) {
1332               inv|=invalid_code[i];
1333             }
1334           }
1335           else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1336             inv=1;
1337           }
1338           if(!inv) {
1339             void *clean_addr = get_clean_addr(head->addr);
1340             if (doesnt_expire_soon(clean_addr)) {
1341               u_int ppage=page;
1342               inv_debug("INV: Restored %x (%p/%p)\n",head->vaddr, head->addr, clean_addr);
1343               //printf("page=%x, addr=%x\n",page,head->vaddr);
1344               //assert(head->vaddr>>12==(page|0x80000));
1345               ll_add_flags(jump_in+ppage,head->vaddr,head->reg_sv_flags,clean_addr);
1346               struct ht_entry *ht_bin = hash_table_get(head->vaddr);
1347               if (ht_bin->vaddr[0] == head->vaddr)
1348                 ht_bin->tcaddr[0] = clean_addr; // Replace existing entry
1349               if (ht_bin->vaddr[1] == head->vaddr)
1350                 ht_bin->tcaddr[1] = clean_addr; // Replace existing entry
1351             }
1352           }
1353         }
1354       }
1355     }
1356     head=head->next;
1357   }
1358 }
1359
1360 /* Register allocation */
1361
1362 // Note: registers are allocated clean (unmodified state)
1363 // if you intend to modify the register, you must call dirty_reg().
1364 static void alloc_reg(struct regstat *cur,int i,signed char reg)
1365 {
1366   int r,hr;
1367   int preferred_reg = (reg&7);
1368   if(reg==CCREG) preferred_reg=HOST_CCREG;
1369   if(reg==PTEMP||reg==FTEMP) preferred_reg=12;
1370
1371   // Don't allocate unused registers
1372   if((cur->u>>reg)&1) return;
1373
1374   // see if it's already allocated
1375   for(hr=0;hr<HOST_REGS;hr++)
1376   {
1377     if(cur->regmap[hr]==reg) return;
1378   }
1379
1380   // Keep the same mapping if the register was already allocated in a loop
1381   preferred_reg = loop_reg(i,reg,preferred_reg);
1382
1383   // Try to allocate the preferred register
1384   if(cur->regmap[preferred_reg]==-1) {
1385     cur->regmap[preferred_reg]=reg;
1386     cur->dirty&=~(1<<preferred_reg);
1387     cur->isconst&=~(1<<preferred_reg);
1388     return;
1389   }
1390   r=cur->regmap[preferred_reg];
1391   assert(r < 64);
1392   if((cur->u>>r)&1) {
1393     cur->regmap[preferred_reg]=reg;
1394     cur->dirty&=~(1<<preferred_reg);
1395     cur->isconst&=~(1<<preferred_reg);
1396     return;
1397   }
1398
1399   // Clear any unneeded registers
1400   // We try to keep the mapping consistent, if possible, because it
1401   // makes branches easier (especially loops).  So we try to allocate
1402   // first (see above) before removing old mappings.  If this is not
1403   // possible then go ahead and clear out the registers that are no
1404   // longer needed.
1405   for(hr=0;hr<HOST_REGS;hr++)
1406   {
1407     r=cur->regmap[hr];
1408     if(r>=0) {
1409       assert(r < 64);
1410       if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
1411     }
1412   }
1413   // Try to allocate any available register, but prefer
1414   // registers that have not been used recently.
1415   if(i>0) {
1416     for(hr=0;hr<HOST_REGS;hr++) {
1417       if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
1418         if(regs[i-1].regmap[hr]!=dops[i-1].rs1&&regs[i-1].regmap[hr]!=dops[i-1].rs2&&regs[i-1].regmap[hr]!=dops[i-1].rt1&&regs[i-1].regmap[hr]!=dops[i-1].rt2) {
1419           cur->regmap[hr]=reg;
1420           cur->dirty&=~(1<<hr);
1421           cur->isconst&=~(1<<hr);
1422           return;
1423         }
1424       }
1425     }
1426   }
1427   // Try to allocate any available register
1428   for(hr=0;hr<HOST_REGS;hr++) {
1429     if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
1430       cur->regmap[hr]=reg;
1431       cur->dirty&=~(1<<hr);
1432       cur->isconst&=~(1<<hr);
1433       return;
1434     }
1435   }
1436
1437   // Ok, now we have to evict someone
1438   // Pick a register we hopefully won't need soon
1439   u_char hsn[MAXREG+1];
1440   memset(hsn,10,sizeof(hsn));
1441   int j;
1442   lsn(hsn,i,&preferred_reg);
1443   //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
1444   //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
1445   if(i>0) {
1446     // Don't evict the cycle count at entry points, otherwise the entry
1447     // stub will have to write it.
1448     if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2;
1449     if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2;
1450     for(j=10;j>=3;j--)
1451     {
1452       // Alloc preferred register if available
1453       if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
1454         for(hr=0;hr<HOST_REGS;hr++) {
1455           // Evict both parts of a 64-bit register
1456           if((cur->regmap[hr]&63)==r) {
1457             cur->regmap[hr]=-1;
1458             cur->dirty&=~(1<<hr);
1459             cur->isconst&=~(1<<hr);
1460           }
1461         }
1462         cur->regmap[preferred_reg]=reg;
1463         return;
1464       }
1465       for(r=1;r<=MAXREG;r++)
1466       {
1467         if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) {
1468           for(hr=0;hr<HOST_REGS;hr++) {
1469             if(hr!=HOST_CCREG||j<hsn[CCREG]) {
1470               if(cur->regmap[hr]==r) {
1471                 cur->regmap[hr]=reg;
1472                 cur->dirty&=~(1<<hr);
1473                 cur->isconst&=~(1<<hr);
1474                 return;
1475               }
1476             }
1477           }
1478         }
1479       }
1480     }
1481   }
1482   for(j=10;j>=0;j--)
1483   {
1484     for(r=1;r<=MAXREG;r++)
1485     {
1486       if(hsn[r]==j) {
1487         for(hr=0;hr<HOST_REGS;hr++) {
1488           if(cur->regmap[hr]==r) {
1489             cur->regmap[hr]=reg;
1490             cur->dirty&=~(1<<hr);
1491             cur->isconst&=~(1<<hr);
1492             return;
1493           }
1494         }
1495       }
1496     }
1497   }
1498   SysPrintf("This shouldn't happen (alloc_reg)");abort();
1499 }
1500
1501 // Allocate a temporary register.  This is done without regard to
1502 // dirty status or whether the register we request is on the unneeded list
1503 // Note: This will only allocate one register, even if called multiple times
1504 static void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
1505 {
1506   int r,hr;
1507   int preferred_reg = -1;
1508
1509   // see if it's already allocated
1510   for(hr=0;hr<HOST_REGS;hr++)
1511   {
1512     if(hr!=EXCLUDE_REG&&cur->regmap[hr]==reg) return;
1513   }
1514
1515   // Try to allocate any available register
1516   for(hr=HOST_REGS-1;hr>=0;hr--) {
1517     if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
1518       cur->regmap[hr]=reg;
1519       cur->dirty&=~(1<<hr);
1520       cur->isconst&=~(1<<hr);
1521       return;
1522     }
1523   }
1524
1525   // Find an unneeded register
1526   for(hr=HOST_REGS-1;hr>=0;hr--)
1527   {
1528     r=cur->regmap[hr];
1529     if(r>=0) {
1530       assert(r < 64);
1531       if((cur->u>>r)&1) {
1532         if(i==0||((unneeded_reg[i-1]>>r)&1)) {
1533           cur->regmap[hr]=reg;
1534           cur->dirty&=~(1<<hr);
1535           cur->isconst&=~(1<<hr);
1536           return;
1537         }
1538       }
1539     }
1540   }
1541
1542   // Ok, now we have to evict someone
1543   // Pick a register we hopefully won't need soon
1544   // TODO: we might want to follow unconditional jumps here
1545   // TODO: get rid of dupe code and make this into a function
1546   u_char hsn[MAXREG+1];
1547   memset(hsn,10,sizeof(hsn));
1548   int j;
1549   lsn(hsn,i,&preferred_reg);
1550   //printf("hsn: %d %d %d %d %d %d %d\n",hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
1551   if(i>0) {
1552     // Don't evict the cycle count at entry points, otherwise the entry
1553     // stub will have to write it.
1554     if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2;
1555     if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2;
1556     for(j=10;j>=3;j--)
1557     {
1558       for(r=1;r<=MAXREG;r++)
1559       {
1560         if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) {
1561           for(hr=0;hr<HOST_REGS;hr++) {
1562             if(hr!=HOST_CCREG||hsn[CCREG]>2) {
1563               if(cur->regmap[hr]==r) {
1564                 cur->regmap[hr]=reg;
1565                 cur->dirty&=~(1<<hr);
1566                 cur->isconst&=~(1<<hr);
1567                 return;
1568               }
1569             }
1570           }
1571         }
1572       }
1573     }
1574   }
1575   for(j=10;j>=0;j--)
1576   {
1577     for(r=1;r<=MAXREG;r++)
1578     {
1579       if(hsn[r]==j) {
1580         for(hr=0;hr<HOST_REGS;hr++) {
1581           if(cur->regmap[hr]==r) {
1582             cur->regmap[hr]=reg;
1583             cur->dirty&=~(1<<hr);
1584             cur->isconst&=~(1<<hr);
1585             return;
1586           }
1587         }
1588       }
1589     }
1590   }
1591   SysPrintf("This shouldn't happen");abort();
1592 }
1593
1594 static void mov_alloc(struct regstat *current,int i)
1595 {
1596   if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) {
1597     // logically this is needed but just won't work, no idea why
1598     //alloc_cc(current,i); // for stalls
1599     //dirty_reg(current,CCREG);
1600   }
1601
1602   // Note: Don't need to actually alloc the source registers
1603   //alloc_reg(current,i,dops[i].rs1);
1604   alloc_reg(current,i,dops[i].rt1);
1605
1606   clear_const(current,dops[i].rs1);
1607   clear_const(current,dops[i].rt1);
1608   dirty_reg(current,dops[i].rt1);
1609 }
1610
1611 static void shiftimm_alloc(struct regstat *current,int i)
1612 {
1613   if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
1614   {
1615     if(dops[i].rt1) {
1616       if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1617       else dops[i].lt1=dops[i].rs1;
1618       alloc_reg(current,i,dops[i].rt1);
1619       dirty_reg(current,dops[i].rt1);
1620       if(is_const(current,dops[i].rs1)) {
1621         int v=get_const(current,dops[i].rs1);
1622         if(dops[i].opcode2==0x00) set_const(current,dops[i].rt1,v<<imm[i]);
1623         if(dops[i].opcode2==0x02) set_const(current,dops[i].rt1,(u_int)v>>imm[i]);
1624         if(dops[i].opcode2==0x03) set_const(current,dops[i].rt1,v>>imm[i]);
1625       }
1626       else clear_const(current,dops[i].rt1);
1627     }
1628   }
1629   else
1630   {
1631     clear_const(current,dops[i].rs1);
1632     clear_const(current,dops[i].rt1);
1633   }
1634
1635   if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
1636   {
1637     assert(0);
1638   }
1639   if(dops[i].opcode2==0x3c) // DSLL32
1640   {
1641     assert(0);
1642   }
1643   if(dops[i].opcode2==0x3e) // DSRL32
1644   {
1645     assert(0);
1646   }
1647   if(dops[i].opcode2==0x3f) // DSRA32
1648   {
1649     assert(0);
1650   }
1651 }
1652
1653 static void shift_alloc(struct regstat *current,int i)
1654 {
1655   if(dops[i].rt1) {
1656     if(dops[i].opcode2<=0x07) // SLLV/SRLV/SRAV
1657     {
1658       if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
1659       if(dops[i].rs2) alloc_reg(current,i,dops[i].rs2);
1660       alloc_reg(current,i,dops[i].rt1);
1661       if(dops[i].rt1==dops[i].rs2) {
1662         alloc_reg_temp(current,i,-1);
1663         minimum_free_regs[i]=1;
1664       }
1665     } else { // DSLLV/DSRLV/DSRAV
1666       assert(0);
1667     }
1668     clear_const(current,dops[i].rs1);
1669     clear_const(current,dops[i].rs2);
1670     clear_const(current,dops[i].rt1);
1671     dirty_reg(current,dops[i].rt1);
1672   }
1673 }
1674
1675 static void alu_alloc(struct regstat *current,int i)
1676 {
1677   if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
1678     if(dops[i].rt1) {
1679       if(dops[i].rs1&&dops[i].rs2) {
1680         alloc_reg(current,i,dops[i].rs1);
1681         alloc_reg(current,i,dops[i].rs2);
1682       }
1683       else {
1684         if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1685         if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
1686       }
1687       alloc_reg(current,i,dops[i].rt1);
1688     }
1689   }
1690   if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
1691     if(dops[i].rt1) {
1692       alloc_reg(current,i,dops[i].rs1);
1693       alloc_reg(current,i,dops[i].rs2);
1694       alloc_reg(current,i,dops[i].rt1);
1695     }
1696   }
1697   if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
1698     if(dops[i].rt1) {
1699       if(dops[i].rs1&&dops[i].rs2) {
1700         alloc_reg(current,i,dops[i].rs1);
1701         alloc_reg(current,i,dops[i].rs2);
1702       }
1703       else
1704       {
1705         if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1706         if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
1707       }
1708       alloc_reg(current,i,dops[i].rt1);
1709     }
1710   }
1711   if(dops[i].opcode2>=0x2c&&dops[i].opcode2<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1712     assert(0);
1713   }
1714   clear_const(current,dops[i].rs1);
1715   clear_const(current,dops[i].rs2);
1716   clear_const(current,dops[i].rt1);
1717   dirty_reg(current,dops[i].rt1);
1718 }
1719
1720 static void imm16_alloc(struct regstat *current,int i)
1721 {
1722   if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1723   else dops[i].lt1=dops[i].rs1;
1724   if(dops[i].rt1) alloc_reg(current,i,dops[i].rt1);
1725   if(dops[i].opcode==0x18||dops[i].opcode==0x19) { // DADDI/DADDIU
1726     assert(0);
1727   }
1728   else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
1729     clear_const(current,dops[i].rs1);
1730     clear_const(current,dops[i].rt1);
1731   }
1732   else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
1733     if(is_const(current,dops[i].rs1)) {
1734       int v=get_const(current,dops[i].rs1);
1735       if(dops[i].opcode==0x0c) set_const(current,dops[i].rt1,v&imm[i]);
1736       if(dops[i].opcode==0x0d) set_const(current,dops[i].rt1,v|imm[i]);
1737       if(dops[i].opcode==0x0e) set_const(current,dops[i].rt1,v^imm[i]);
1738     }
1739     else clear_const(current,dops[i].rt1);
1740   }
1741   else if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
1742     if(is_const(current,dops[i].rs1)) {
1743       int v=get_const(current,dops[i].rs1);
1744       set_const(current,dops[i].rt1,v+imm[i]);
1745     }
1746     else clear_const(current,dops[i].rt1);
1747   }
1748   else {
1749     set_const(current,dops[i].rt1,imm[i]<<16); // LUI
1750   }
1751   dirty_reg(current,dops[i].rt1);
1752 }
1753
1754 static void load_alloc(struct regstat *current,int i)
1755 {
1756   clear_const(current,dops[i].rt1);
1757   //if(dops[i].rs1!=dops[i].rt1&&needed_again(dops[i].rs1,i)) clear_const(current,dops[i].rs1); // Does this help or hurt?
1758   if(!dops[i].rs1) current->u&=~1LL; // Allow allocating r0 if it's the source register
1759   if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1760   if(dops[i].rt1&&!((current->u>>dops[i].rt1)&1)) {
1761     alloc_reg(current,i,dops[i].rt1);
1762     assert(get_reg(current->regmap,dops[i].rt1)>=0);
1763     if(dops[i].opcode==0x27||dops[i].opcode==0x37) // LWU/LD
1764     {
1765       assert(0);
1766     }
1767     else if(dops[i].opcode==0x1A||dops[i].opcode==0x1B) // LDL/LDR
1768     {
1769       assert(0);
1770     }
1771     dirty_reg(current,dops[i].rt1);
1772     // LWL/LWR need a temporary register for the old value
1773     if(dops[i].opcode==0x22||dops[i].opcode==0x26)
1774     {
1775       alloc_reg(current,i,FTEMP);
1776       alloc_reg_temp(current,i,-1);
1777       minimum_free_regs[i]=1;
1778     }
1779   }
1780   else
1781   {
1782     // Load to r0 or unneeded register (dummy load)
1783     // but we still need a register to calculate the address
1784     if(dops[i].opcode==0x22||dops[i].opcode==0x26)
1785     {
1786       alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1787     }
1788     alloc_reg_temp(current,i,-1);
1789     minimum_free_regs[i]=1;
1790     if(dops[i].opcode==0x1A||dops[i].opcode==0x1B) // LDL/LDR
1791     {
1792       assert(0);
1793     }
1794   }
1795 }
1796
1797 void store_alloc(struct regstat *current,int i)
1798 {
1799   clear_const(current,dops[i].rs2);
1800   if(!(dops[i].rs2)) current->u&=~1LL; // Allow allocating r0 if necessary
1801   if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1802   alloc_reg(current,i,dops[i].rs2);
1803   if(dops[i].opcode==0x2c||dops[i].opcode==0x2d||dops[i].opcode==0x3f) { // 64-bit SDL/SDR/SD
1804     assert(0);
1805   }
1806   #if defined(HOST_IMM8)
1807   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1808   else alloc_reg(current,i,INVCP);
1809   #endif
1810   if(dops[i].opcode==0x2a||dops[i].opcode==0x2e||dops[i].opcode==0x2c||dops[i].opcode==0x2d) { // SWL/SWL/SDL/SDR
1811     alloc_reg(current,i,FTEMP);
1812   }
1813   // We need a temporary register for address generation
1814   alloc_reg_temp(current,i,-1);
1815   minimum_free_regs[i]=1;
1816 }
1817
1818 void c1ls_alloc(struct regstat *current,int i)
1819 {
1820   //clear_const(current,dops[i].rs1); // FIXME
1821   clear_const(current,dops[i].rt1);
1822   if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1823   alloc_reg(current,i,CSREG); // Status
1824   alloc_reg(current,i,FTEMP);
1825   if(dops[i].opcode==0x35||dops[i].opcode==0x3d) { // 64-bit LDC1/SDC1
1826     assert(0);
1827   }
1828   #if defined(HOST_IMM8)
1829   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1830   else if((dops[i].opcode&0x3b)==0x39) // SWC1/SDC1
1831     alloc_reg(current,i,INVCP);
1832   #endif
1833   // We need a temporary register for address generation
1834   alloc_reg_temp(current,i,-1);
1835 }
1836
1837 void c2ls_alloc(struct regstat *current,int i)
1838 {
1839   clear_const(current,dops[i].rt1);
1840   if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1841   alloc_reg(current,i,FTEMP);
1842   #if defined(HOST_IMM8)
1843   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1844   if((dops[i].opcode&0x3b)==0x3a) // SWC2/SDC2
1845     alloc_reg(current,i,INVCP);
1846   #endif
1847   // We need a temporary register for address generation
1848   alloc_reg_temp(current,i,-1);
1849   minimum_free_regs[i]=1;
1850 }
1851
1852 #ifndef multdiv_alloc
1853 void multdiv_alloc(struct regstat *current,int i)
1854 {
1855   //  case 0x18: MULT
1856   //  case 0x19: MULTU
1857   //  case 0x1A: DIV
1858   //  case 0x1B: DIVU
1859   //  case 0x1C: DMULT
1860   //  case 0x1D: DMULTU
1861   //  case 0x1E: DDIV
1862   //  case 0x1F: DDIVU
1863   clear_const(current,dops[i].rs1);
1864   clear_const(current,dops[i].rs2);
1865   alloc_cc(current,i); // for stalls
1866   if(dops[i].rs1&&dops[i].rs2)
1867   {
1868     if((dops[i].opcode2&4)==0) // 32-bit
1869     {
1870       current->u&=~(1LL<<HIREG);
1871       current->u&=~(1LL<<LOREG);
1872       alloc_reg(current,i,HIREG);
1873       alloc_reg(current,i,LOREG);
1874       alloc_reg(current,i,dops[i].rs1);
1875       alloc_reg(current,i,dops[i].rs2);
1876       dirty_reg(current,HIREG);
1877       dirty_reg(current,LOREG);
1878     }
1879     else // 64-bit
1880     {
1881       assert(0);
1882     }
1883   }
1884   else
1885   {
1886     // Multiply by zero is zero.
1887     // MIPS does not have a divide by zero exception.
1888     // The result is undefined, we return zero.
1889     alloc_reg(current,i,HIREG);
1890     alloc_reg(current,i,LOREG);
1891     dirty_reg(current,HIREG);
1892     dirty_reg(current,LOREG);
1893   }
1894 }
1895 #endif
1896
1897 void cop0_alloc(struct regstat *current,int i)
1898 {
1899   if(dops[i].opcode2==0) // MFC0
1900   {
1901     if(dops[i].rt1) {
1902       clear_const(current,dops[i].rt1);
1903       alloc_all(current,i);
1904       alloc_reg(current,i,dops[i].rt1);
1905       dirty_reg(current,dops[i].rt1);
1906     }
1907   }
1908   else if(dops[i].opcode2==4) // MTC0
1909   {
1910     if(dops[i].rs1){
1911       clear_const(current,dops[i].rs1);
1912       alloc_reg(current,i,dops[i].rs1);
1913       alloc_all(current,i);
1914     }
1915     else {
1916       alloc_all(current,i); // FIXME: Keep r0
1917       current->u&=~1LL;
1918       alloc_reg(current,i,0);
1919     }
1920   }
1921   else
1922   {
1923     // TLBR/TLBWI/TLBWR/TLBP/ERET
1924     assert(dops[i].opcode2==0x10);
1925     alloc_all(current,i);
1926   }
1927   minimum_free_regs[i]=HOST_REGS;
1928 }
1929
1930 static void cop2_alloc(struct regstat *current,int i)
1931 {
1932   if (dops[i].opcode2 < 3) // MFC2/CFC2
1933   {
1934     alloc_cc(current,i); // for stalls
1935     dirty_reg(current,CCREG);
1936     if(dops[i].rt1){
1937       clear_const(current,dops[i].rt1);
1938       alloc_reg(current,i,dops[i].rt1);
1939       dirty_reg(current,dops[i].rt1);
1940     }
1941   }
1942   else if (dops[i].opcode2 > 3) // MTC2/CTC2
1943   {
1944     if(dops[i].rs1){
1945       clear_const(current,dops[i].rs1);
1946       alloc_reg(current,i,dops[i].rs1);
1947     }
1948     else {
1949       current->u&=~1LL;
1950       alloc_reg(current,i,0);
1951     }
1952   }
1953   alloc_reg_temp(current,i,-1);
1954   minimum_free_regs[i]=1;
1955 }
1956
1957 void c2op_alloc(struct regstat *current,int i)
1958 {
1959   alloc_cc(current,i); // for stalls
1960   dirty_reg(current,CCREG);
1961   alloc_reg_temp(current,i,-1);
1962 }
1963
1964 void syscall_alloc(struct regstat *current,int i)
1965 {
1966   alloc_cc(current,i);
1967   dirty_reg(current,CCREG);
1968   alloc_all(current,i);
1969   minimum_free_regs[i]=HOST_REGS;
1970   current->isconst=0;
1971 }
1972
1973 void delayslot_alloc(struct regstat *current,int i)
1974 {
1975   switch(dops[i].itype) {
1976     case UJUMP:
1977     case CJUMP:
1978     case SJUMP:
1979     case RJUMP:
1980     case SYSCALL:
1981     case HLECALL:
1982     case SPAN:
1983       assem_debug("jump in the delay slot.  this shouldn't happen.\n");//abort();
1984       SysPrintf("Disabled speculative precompilation\n");
1985       stop_after_jal=1;
1986       break;
1987     case IMM16:
1988       imm16_alloc(current,i);
1989       break;
1990     case LOAD:
1991     case LOADLR:
1992       load_alloc(current,i);
1993       break;
1994     case STORE:
1995     case STORELR:
1996       store_alloc(current,i);
1997       break;
1998     case ALU:
1999       alu_alloc(current,i);
2000       break;
2001     case SHIFT:
2002       shift_alloc(current,i);
2003       break;
2004     case MULTDIV:
2005       multdiv_alloc(current,i);
2006       break;
2007     case SHIFTIMM:
2008       shiftimm_alloc(current,i);
2009       break;
2010     case MOV:
2011       mov_alloc(current,i);
2012       break;
2013     case COP0:
2014       cop0_alloc(current,i);
2015       break;
2016     case COP1:
2017       break;
2018     case COP2:
2019       cop2_alloc(current,i);
2020       break;
2021     case C1LS:
2022       c1ls_alloc(current,i);
2023       break;
2024     case C2LS:
2025       c2ls_alloc(current,i);
2026       break;
2027     case C2OP:
2028       c2op_alloc(current,i);
2029       break;
2030   }
2031 }
2032
2033 // Special case where a branch and delay slot span two pages in virtual memory
2034 static void pagespan_alloc(struct regstat *current,int i)
2035 {
2036   current->isconst=0;
2037   current->wasconst=0;
2038   regs[i].wasconst=0;
2039   minimum_free_regs[i]=HOST_REGS;
2040   alloc_all(current,i);
2041   alloc_cc(current,i);
2042   dirty_reg(current,CCREG);
2043   if(dops[i].opcode==3) // JAL
2044   {
2045     alloc_reg(current,i,31);
2046     dirty_reg(current,31);
2047   }
2048   if(dops[i].opcode==0&&(dops[i].opcode2&0x3E)==8) // JR/JALR
2049   {
2050     alloc_reg(current,i,dops[i].rs1);
2051     if (dops[i].rt1!=0) {
2052       alloc_reg(current,i,dops[i].rt1);
2053       dirty_reg(current,dops[i].rt1);
2054     }
2055   }
2056   if((dops[i].opcode&0x2E)==4) // BEQ/BNE/BEQL/BNEL
2057   {
2058     if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
2059     if(dops[i].rs2) alloc_reg(current,i,dops[i].rs2);
2060   }
2061   else
2062   if((dops[i].opcode&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
2063   {
2064     if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
2065   }
2066   //else ...
2067 }
2068
2069 static void add_stub(enum stub_type type, void *addr, void *retaddr,
2070   u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e)
2071 {
2072   assert(stubcount < ARRAY_SIZE(stubs));
2073   stubs[stubcount].type = type;
2074   stubs[stubcount].addr = addr;
2075   stubs[stubcount].retaddr = retaddr;
2076   stubs[stubcount].a = a;
2077   stubs[stubcount].b = b;
2078   stubs[stubcount].c = c;
2079   stubs[stubcount].d = d;
2080   stubs[stubcount].e = e;
2081   stubcount++;
2082 }
2083
2084 static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
2085   int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist)
2086 {
2087   add_stub(type, addr, retaddr, i, addr_reg, (uintptr_t)i_regs, ccadj, reglist);
2088 }
2089
2090 // Write out a single register
2091 static void wb_register(signed char r,signed char regmap[],uint64_t dirty)
2092 {
2093   int hr;
2094   for(hr=0;hr<HOST_REGS;hr++) {
2095     if(hr!=EXCLUDE_REG) {
2096       if((regmap[hr]&63)==r) {
2097         if((dirty>>hr)&1) {
2098           assert(regmap[hr]<64);
2099           emit_storereg(r,hr);
2100         }
2101       }
2102     }
2103   }
2104 }
2105
2106 static void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t u)
2107 {
2108   //if(dirty_pre==dirty) return;
2109   int hr,reg;
2110   for(hr=0;hr<HOST_REGS;hr++) {
2111     if(hr!=EXCLUDE_REG) {
2112       reg=pre[hr];
2113       if(((~u)>>(reg&63))&1) {
2114         if(reg>0) {
2115           if(((dirty_pre&~dirty)>>hr)&1) {
2116             if(reg>0&&reg<34) {
2117               emit_storereg(reg,hr);
2118             }
2119             else if(reg>=64) {
2120               assert(0);
2121             }
2122           }
2123         }
2124       }
2125     }
2126   }
2127 }
2128
2129 // trashes r2
2130 static void pass_args(int a0, int a1)
2131 {
2132   if(a0==1&&a1==0) {
2133     // must swap
2134     emit_mov(a0,2); emit_mov(a1,1); emit_mov(2,0);
2135   }
2136   else if(a0!=0&&a1==0) {
2137     emit_mov(a1,1);
2138     if (a0>=0) emit_mov(a0,0);
2139   }
2140   else {
2141     if(a0>=0&&a0!=0) emit_mov(a0,0);
2142     if(a1>=0&&a1!=1) emit_mov(a1,1);
2143   }
2144 }
2145
2146 static void alu_assemble(int i,struct regstat *i_regs)
2147 {
2148   if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
2149     if(dops[i].rt1) {
2150       signed char s1,s2,t;
2151       t=get_reg(i_regs->regmap,dops[i].rt1);
2152       if(t>=0) {
2153         s1=get_reg(i_regs->regmap,dops[i].rs1);
2154         s2=get_reg(i_regs->regmap,dops[i].rs2);
2155         if(dops[i].rs1&&dops[i].rs2) {
2156           assert(s1>=0);
2157           assert(s2>=0);
2158           if(dops[i].opcode2&2) emit_sub(s1,s2,t);
2159           else emit_add(s1,s2,t);
2160         }
2161         else if(dops[i].rs1) {
2162           if(s1>=0) emit_mov(s1,t);
2163           else emit_loadreg(dops[i].rs1,t);
2164         }
2165         else if(dops[i].rs2) {
2166           if(s2>=0) {
2167             if(dops[i].opcode2&2) emit_neg(s2,t);
2168             else emit_mov(s2,t);
2169           }
2170           else {
2171             emit_loadreg(dops[i].rs2,t);
2172             if(dops[i].opcode2&2) emit_neg(t,t);
2173           }
2174         }
2175         else emit_zeroreg(t);
2176       }
2177     }
2178   }
2179   if(dops[i].opcode2>=0x2c&&dops[i].opcode2<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2180     assert(0);
2181   }
2182   if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
2183     if(dops[i].rt1) {
2184       signed char s1l,s2l,t;
2185       {
2186         t=get_reg(i_regs->regmap,dops[i].rt1);
2187         //assert(t>=0);
2188         if(t>=0) {
2189           s1l=get_reg(i_regs->regmap,dops[i].rs1);
2190           s2l=get_reg(i_regs->regmap,dops[i].rs2);
2191           if(dops[i].rs2==0) // rx<r0
2192           {
2193             if(dops[i].opcode2==0x2a&&dops[i].rs1!=0) { // SLT
2194               assert(s1l>=0);
2195               emit_shrimm(s1l,31,t);
2196             }
2197             else // SLTU (unsigned can not be less than zero, 0<0)
2198               emit_zeroreg(t);
2199           }
2200           else if(dops[i].rs1==0) // r0<rx
2201           {
2202             assert(s2l>=0);
2203             if(dops[i].opcode2==0x2a) // SLT
2204               emit_set_gz32(s2l,t);
2205             else // SLTU (set if not zero)
2206               emit_set_nz32(s2l,t);
2207           }
2208           else{
2209             assert(s1l>=0);assert(s2l>=0);
2210             if(dops[i].opcode2==0x2a) // SLT
2211               emit_set_if_less32(s1l,s2l,t);
2212             else // SLTU
2213               emit_set_if_carry32(s1l,s2l,t);
2214           }
2215         }
2216       }
2217     }
2218   }
2219   if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
2220     if(dops[i].rt1) {
2221       signed char s1l,s2l,tl;
2222       tl=get_reg(i_regs->regmap,dops[i].rt1);
2223       {
2224         if(tl>=0) {
2225           s1l=get_reg(i_regs->regmap,dops[i].rs1);
2226           s2l=get_reg(i_regs->regmap,dops[i].rs2);
2227           if(dops[i].rs1&&dops[i].rs2) {
2228             assert(s1l>=0);
2229             assert(s2l>=0);
2230             if(dops[i].opcode2==0x24) { // AND
2231               emit_and(s1l,s2l,tl);
2232             } else
2233             if(dops[i].opcode2==0x25) { // OR
2234               emit_or(s1l,s2l,tl);
2235             } else
2236             if(dops[i].opcode2==0x26) { // XOR
2237               emit_xor(s1l,s2l,tl);
2238             } else
2239             if(dops[i].opcode2==0x27) { // NOR
2240               emit_or(s1l,s2l,tl);
2241               emit_not(tl,tl);
2242             }
2243           }
2244           else
2245           {
2246             if(dops[i].opcode2==0x24) { // AND
2247               emit_zeroreg(tl);
2248             } else
2249             if(dops[i].opcode2==0x25||dops[i].opcode2==0x26) { // OR/XOR
2250               if(dops[i].rs1){
2251                 if(s1l>=0) emit_mov(s1l,tl);
2252                 else emit_loadreg(dops[i].rs1,tl); // CHECK: regmap_entry?
2253               }
2254               else
2255               if(dops[i].rs2){
2256                 if(s2l>=0) emit_mov(s2l,tl);
2257                 else emit_loadreg(dops[i].rs2,tl); // CHECK: regmap_entry?
2258               }
2259               else emit_zeroreg(tl);
2260             } else
2261             if(dops[i].opcode2==0x27) { // NOR
2262               if(dops[i].rs1){
2263                 if(s1l>=0) emit_not(s1l,tl);
2264                 else {
2265                   emit_loadreg(dops[i].rs1,tl);
2266                   emit_not(tl,tl);
2267                 }
2268               }
2269               else
2270               if(dops[i].rs2){
2271                 if(s2l>=0) emit_not(s2l,tl);
2272                 else {
2273                   emit_loadreg(dops[i].rs2,tl);
2274                   emit_not(tl,tl);
2275                 }
2276               }
2277               else emit_movimm(-1,tl);
2278             }
2279           }
2280         }
2281       }
2282     }
2283   }
2284 }
2285
2286 void imm16_assemble(int i,struct regstat *i_regs)
2287 {
2288   if (dops[i].opcode==0x0f) { // LUI
2289     if(dops[i].rt1) {
2290       signed char t;
2291       t=get_reg(i_regs->regmap,dops[i].rt1);
2292       //assert(t>=0);
2293       if(t>=0) {
2294         if(!((i_regs->isconst>>t)&1))
2295           emit_movimm(imm[i]<<16,t);
2296       }
2297     }
2298   }
2299   if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
2300     if(dops[i].rt1) {
2301       signed char s,t;
2302       t=get_reg(i_regs->regmap,dops[i].rt1);
2303       s=get_reg(i_regs->regmap,dops[i].rs1);
2304       if(dops[i].rs1) {
2305         //assert(t>=0);
2306         //assert(s>=0);
2307         if(t>=0) {
2308           if(!((i_regs->isconst>>t)&1)) {
2309             if(s<0) {
2310               if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2311               emit_addimm(t,imm[i],t);
2312             }else{
2313               if(!((i_regs->wasconst>>s)&1))
2314                 emit_addimm(s,imm[i],t);
2315               else
2316                 emit_movimm(constmap[i][s]+imm[i],t);
2317             }
2318           }
2319         }
2320       } else {
2321         if(t>=0) {
2322           if(!((i_regs->isconst>>t)&1))
2323             emit_movimm(imm[i],t);
2324         }
2325       }
2326     }
2327   }
2328   if(dops[i].opcode==0x18||dops[i].opcode==0x19) { // DADDI/DADDIU
2329     if(dops[i].rt1) {
2330       signed char sl,tl;
2331       tl=get_reg(i_regs->regmap,dops[i].rt1);
2332       sl=get_reg(i_regs->regmap,dops[i].rs1);
2333       if(tl>=0) {
2334         if(dops[i].rs1) {
2335           assert(sl>=0);
2336           emit_addimm(sl,imm[i],tl);
2337         } else {
2338           emit_movimm(imm[i],tl);
2339         }
2340       }
2341     }
2342   }
2343   else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
2344     if(dops[i].rt1) {
2345       //assert(dops[i].rs1!=0); // r0 might be valid, but it's probably a bug
2346       signed char sl,t;
2347       t=get_reg(i_regs->regmap,dops[i].rt1);
2348       sl=get_reg(i_regs->regmap,dops[i].rs1);
2349       //assert(t>=0);
2350       if(t>=0) {
2351         if(dops[i].rs1>0) {
2352             if(dops[i].opcode==0x0a) { // SLTI
2353               if(sl<0) {
2354                 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2355                 emit_slti32(t,imm[i],t);
2356               }else{
2357                 emit_slti32(sl,imm[i],t);
2358               }
2359             }
2360             else { // SLTIU
2361               if(sl<0) {
2362                 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2363                 emit_sltiu32(t,imm[i],t);
2364               }else{
2365                 emit_sltiu32(sl,imm[i],t);
2366               }
2367             }
2368         }else{
2369           // SLTI(U) with r0 is just stupid,
2370           // nonetheless examples can be found
2371           if(dops[i].opcode==0x0a) // SLTI
2372             if(0<imm[i]) emit_movimm(1,t);
2373             else emit_zeroreg(t);
2374           else // SLTIU
2375           {
2376             if(imm[i]) emit_movimm(1,t);
2377             else emit_zeroreg(t);
2378           }
2379         }
2380       }
2381     }
2382   }
2383   else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
2384     if(dops[i].rt1) {
2385       signed char sl,tl;
2386       tl=get_reg(i_regs->regmap,dops[i].rt1);
2387       sl=get_reg(i_regs->regmap,dops[i].rs1);
2388       if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2389         if(dops[i].opcode==0x0c) //ANDI
2390         {
2391           if(dops[i].rs1) {
2392             if(sl<0) {
2393               if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
2394               emit_andimm(tl,imm[i],tl);
2395             }else{
2396               if(!((i_regs->wasconst>>sl)&1))
2397                 emit_andimm(sl,imm[i],tl);
2398               else
2399                 emit_movimm(constmap[i][sl]&imm[i],tl);
2400             }
2401           }
2402           else
2403             emit_zeroreg(tl);
2404         }
2405         else
2406         {
2407           if(dops[i].rs1) {
2408             if(sl<0) {
2409               if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
2410             }
2411             if(dops[i].opcode==0x0d) { // ORI
2412               if(sl<0) {
2413                 emit_orimm(tl,imm[i],tl);
2414               }else{
2415                 if(!((i_regs->wasconst>>sl)&1))
2416                   emit_orimm(sl,imm[i],tl);
2417                 else
2418                   emit_movimm(constmap[i][sl]|imm[i],tl);
2419               }
2420             }
2421             if(dops[i].opcode==0x0e) { // XORI
2422               if(sl<0) {
2423                 emit_xorimm(tl,imm[i],tl);
2424               }else{
2425                 if(!((i_regs->wasconst>>sl)&1))
2426                   emit_xorimm(sl,imm[i],tl);
2427                 else
2428                   emit_movimm(constmap[i][sl]^imm[i],tl);
2429               }
2430             }
2431           }
2432           else {
2433             emit_movimm(imm[i],tl);
2434           }
2435         }
2436       }
2437     }
2438   }
2439 }
2440
2441 void shiftimm_assemble(int i,struct regstat *i_regs)
2442 {
2443   if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
2444   {
2445     if(dops[i].rt1) {
2446       signed char s,t;
2447       t=get_reg(i_regs->regmap,dops[i].rt1);
2448       s=get_reg(i_regs->regmap,dops[i].rs1);
2449       //assert(t>=0);
2450       if(t>=0&&!((i_regs->isconst>>t)&1)){
2451         if(dops[i].rs1==0)
2452         {
2453           emit_zeroreg(t);
2454         }
2455         else
2456         {
2457           if(s<0&&i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2458           if(imm[i]) {
2459             if(dops[i].opcode2==0) // SLL
2460             {
2461               emit_shlimm(s<0?t:s,imm[i],t);
2462             }
2463             if(dops[i].opcode2==2) // SRL
2464             {
2465               emit_shrimm(s<0?t:s,imm[i],t);
2466             }
2467             if(dops[i].opcode2==3) // SRA
2468             {
2469               emit_sarimm(s<0?t:s,imm[i],t);
2470             }
2471           }else{
2472             // Shift by zero
2473             if(s>=0 && s!=t) emit_mov(s,t);
2474           }
2475         }
2476       }
2477       //emit_storereg(dops[i].rt1,t); //DEBUG
2478     }
2479   }
2480   if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
2481   {
2482     assert(0);
2483   }
2484   if(dops[i].opcode2==0x3c) // DSLL32
2485   {
2486     assert(0);
2487   }
2488   if(dops[i].opcode2==0x3e) // DSRL32
2489   {
2490     assert(0);
2491   }
2492   if(dops[i].opcode2==0x3f) // DSRA32
2493   {
2494     assert(0);
2495   }
2496 }
2497
2498 #ifndef shift_assemble
2499 static void shift_assemble(int i,struct regstat *i_regs)
2500 {
2501   signed char s,t,shift;
2502   if (dops[i].rt1 == 0)
2503     return;
2504   assert(dops[i].opcode2<=0x07); // SLLV/SRLV/SRAV
2505   t = get_reg(i_regs->regmap, dops[i].rt1);
2506   s = get_reg(i_regs->regmap, dops[i].rs1);
2507   shift = get_reg(i_regs->regmap, dops[i].rs2);
2508   if (t < 0)
2509     return;
2510
2511   if(dops[i].rs1==0)
2512     emit_zeroreg(t);
2513   else if(dops[i].rs2==0) {
2514     assert(s>=0);
2515     if(s!=t) emit_mov(s,t);
2516   }
2517   else {
2518     host_tempreg_acquire();
2519     emit_andimm(shift,31,HOST_TEMPREG);
2520     switch(dops[i].opcode2) {
2521     case 4: // SLLV
2522       emit_shl(s,HOST_TEMPREG,t);
2523       break;
2524     case 6: // SRLV
2525       emit_shr(s,HOST_TEMPREG,t);
2526       break;
2527     case 7: // SRAV
2528       emit_sar(s,HOST_TEMPREG,t);
2529       break;
2530     default:
2531       assert(0);
2532     }
2533     host_tempreg_release();
2534   }
2535 }
2536
2537 #endif
2538
2539 enum {
2540   MTYPE_8000 = 0,
2541   MTYPE_8020,
2542   MTYPE_0000,
2543   MTYPE_A000,
2544   MTYPE_1F80,
2545 };
2546
2547 static int get_ptr_mem_type(u_int a)
2548 {
2549   if(a < 0x00200000) {
2550     if(a<0x1000&&((start>>20)==0xbfc||(start>>24)==0xa0))
2551       // return wrong, must use memhandler for BIOS self-test to pass
2552       // 007 does similar stuff from a00 mirror, weird stuff
2553       return MTYPE_8000;
2554     return MTYPE_0000;
2555   }
2556   if(0x1f800000 <= a && a < 0x1f801000)
2557     return MTYPE_1F80;
2558   if(0x80200000 <= a && a < 0x80800000)
2559     return MTYPE_8020;
2560   if(0xa0000000 <= a && a < 0xa0200000)
2561     return MTYPE_A000;
2562   return MTYPE_8000;
2563 }
2564
2565 static void *emit_fastpath_cmp_jump(int i,int addr,int *addr_reg_override)
2566 {
2567   void *jaddr = NULL;
2568   int type=0;
2569   int mr=dops[i].rs1;
2570   if(((smrv_strong|smrv_weak)>>mr)&1) {
2571     type=get_ptr_mem_type(smrv[mr]);
2572     //printf("set %08x @%08x r%d %d\n", smrv[mr], start+i*4, mr, type);
2573   }
2574   else {
2575     // use the mirror we are running on
2576     type=get_ptr_mem_type(start);
2577     //printf("set nospec   @%08x r%d %d\n", start+i*4, mr, type);
2578   }
2579
2580   if(type==MTYPE_8020) { // RAM 80200000+ mirror
2581     host_tempreg_acquire();
2582     emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
2583     addr=*addr_reg_override=HOST_TEMPREG;
2584     type=0;
2585   }
2586   else if(type==MTYPE_0000) { // RAM 0 mirror
2587     host_tempreg_acquire();
2588     emit_orimm(addr,0x80000000,HOST_TEMPREG);
2589     addr=*addr_reg_override=HOST_TEMPREG;
2590     type=0;
2591   }
2592   else if(type==MTYPE_A000) { // RAM A mirror
2593     host_tempreg_acquire();
2594     emit_andimm(addr,~0x20000000,HOST_TEMPREG);
2595     addr=*addr_reg_override=HOST_TEMPREG;
2596     type=0;
2597   }
2598   else if(type==MTYPE_1F80) { // scratchpad
2599     if (psxH == (void *)0x1f800000) {
2600       host_tempreg_acquire();
2601       emit_xorimm(addr,0x1f800000,HOST_TEMPREG);
2602       emit_cmpimm(HOST_TEMPREG,0x1000);
2603       host_tempreg_release();
2604       jaddr=out;
2605       emit_jc(0);
2606     }
2607     else {
2608       // do the usual RAM check, jump will go to the right handler
2609       type=0;
2610     }
2611   }
2612
2613   if(type==0)
2614   {
2615     emit_cmpimm(addr,RAM_SIZE);
2616     jaddr=out;
2617     #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2618     // Hint to branch predictor that the branch is unlikely to be taken
2619     if(dops[i].rs1>=28)
2620       emit_jno_unlikely(0);
2621     else
2622     #endif
2623       emit_jno(0);
2624     if(ram_offset!=0) {
2625       host_tempreg_acquire();
2626       emit_addimm(addr,ram_offset,HOST_TEMPREG);
2627       addr=*addr_reg_override=HOST_TEMPREG;
2628     }
2629   }
2630
2631   return jaddr;
2632 }
2633
2634 // return memhandler, or get directly accessable address and return 0
2635 static void *get_direct_memhandler(void *table, u_int addr,
2636   enum stub_type type, uintptr_t *addr_host)
2637 {
2638   uintptr_t l1, l2 = 0;
2639   l1 = ((uintptr_t *)table)[addr>>12];
2640   if ((l1 & (1ul << (sizeof(l1)*8-1))) == 0) {
2641     uintptr_t v = l1 << 1;
2642     *addr_host = v + addr;
2643     return NULL;
2644   }
2645   else {
2646     l1 <<= 1;
2647     if (type == LOADB_STUB || type == LOADBU_STUB || type == STOREB_STUB)
2648       l2 = ((uintptr_t *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)];
2649     else if (type == LOADH_STUB || type == LOADHU_STUB || type == STOREH_STUB)
2650       l2=((uintptr_t *)l1)[0x1000/4 + (addr&0xfff)/2];
2651     else
2652       l2=((uintptr_t *)l1)[(addr&0xfff)/4];
2653     if ((l2 & (1<<31)) == 0) {
2654       uintptr_t v = l2 << 1;
2655       *addr_host = v + (addr&0xfff);
2656       return NULL;
2657     }
2658     return (void *)(l2 << 1);
2659   }
2660 }
2661
2662 static u_int get_host_reglist(const signed char *regmap)
2663 {
2664   u_int reglist = 0, hr;
2665   for (hr = 0; hr < HOST_REGS; hr++) {
2666     if (hr != EXCLUDE_REG && regmap[hr] >= 0)
2667       reglist |= 1 << hr;
2668   }
2669   return reglist;
2670 }
2671
2672 static u_int reglist_exclude(u_int reglist, int r1, int r2)
2673 {
2674   if (r1 >= 0)
2675     reglist &= ~(1u << r1);
2676   if (r2 >= 0)
2677     reglist &= ~(1u << r2);
2678   return reglist;
2679 }
2680
2681 // find a temp caller-saved register not in reglist (so assumed to be free)
2682 static int reglist_find_free(u_int reglist)
2683 {
2684   u_int free_regs = ~reglist & CALLER_SAVE_REGS;
2685   if (free_regs == 0)
2686     return -1;
2687   return __builtin_ctz(free_regs);
2688 }
2689
2690 static void load_assemble(int i, const struct regstat *i_regs)
2691 {
2692   int s,tl,addr;
2693   int offset;
2694   void *jaddr=0;
2695   int memtarget=0,c=0;
2696   int fastio_reg_override=-1;
2697   u_int reglist=get_host_reglist(i_regs->regmap);
2698   tl=get_reg(i_regs->regmap,dops[i].rt1);
2699   s=get_reg(i_regs->regmap,dops[i].rs1);
2700   offset=imm[i];
2701   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2702   if(s>=0) {
2703     c=(i_regs->wasconst>>s)&1;
2704     if (c) {
2705       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2706     }
2707   }
2708   //printf("load_assemble: c=%d\n",c);
2709   //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
2710   // FIXME: Even if the load is a NOP, we should check for pagefaults...
2711   if((tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80))
2712     ||dops[i].rt1==0) {
2713       // could be FIFO, must perform the read
2714       // ||dummy read
2715       assem_debug("(forced read)\n");
2716       tl=get_reg(i_regs->regmap,-1);
2717       assert(tl>=0);
2718   }
2719   if(offset||s<0||c) addr=tl;
2720   else addr=s;
2721   //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2722  if(tl>=0) {
2723   //printf("load_assemble: c=%d\n",c);
2724   //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
2725   assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2726   reglist&=~(1<<tl);
2727   if(!c) {
2728     #ifdef R29_HACK
2729     // Strmnnrmn's speed hack
2730     if(dops[i].rs1!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2731     #endif
2732     {
2733       jaddr=emit_fastpath_cmp_jump(i,addr,&fastio_reg_override);
2734     }
2735   }
2736   else if(ram_offset&&memtarget) {
2737     host_tempreg_acquire();
2738     emit_addimm(addr,ram_offset,HOST_TEMPREG);
2739     fastio_reg_override=HOST_TEMPREG;
2740   }
2741   int dummy=(dops[i].rt1==0)||(tl!=get_reg(i_regs->regmap,dops[i].rt1)); // ignore loads to r0 and unneeded reg
2742   if (dops[i].opcode==0x20) { // LB
2743     if(!c||memtarget) {
2744       if(!dummy) {
2745         {
2746           int x=0,a=tl;
2747           if(!c) a=addr;
2748           if(fastio_reg_override>=0) a=fastio_reg_override;
2749
2750           emit_movsbl_indexed(x,a,tl);
2751         }
2752       }
2753       if(jaddr)
2754         add_stub_r(LOADB_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist);
2755     }
2756     else
2757       inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj[i],reglist);
2758   }
2759   if (dops[i].opcode==0x21) { // LH
2760     if(!c||memtarget) {
2761       if(!dummy) {
2762         int x=0,a=tl;
2763         if(!c) a=addr;
2764         if(fastio_reg_override>=0) a=fastio_reg_override;
2765         emit_movswl_indexed(x,a,tl);
2766       }
2767       if(jaddr)
2768         add_stub_r(LOADH_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist);
2769     }
2770     else
2771       inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj[i],reglist);
2772   }
2773   if (dops[i].opcode==0x23) { // LW
2774     if(!c||memtarget) {
2775       if(!dummy) {
2776         int a=addr;
2777         if(fastio_reg_override>=0) a=fastio_reg_override;
2778         emit_readword_indexed(0,a,tl);
2779       }
2780       if(jaddr)
2781         add_stub_r(LOADW_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist);
2782     }
2783     else
2784       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj[i],reglist);
2785   }
2786   if (dops[i].opcode==0x24) { // LBU
2787     if(!c||memtarget) {
2788       if(!dummy) {
2789         int x=0,a=tl;
2790         if(!c) a=addr;
2791         if(fastio_reg_override>=0) a=fastio_reg_override;
2792
2793         emit_movzbl_indexed(x,a,tl);
2794       }
2795       if(jaddr)
2796         add_stub_r(LOADBU_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist);
2797     }
2798     else
2799       inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj[i],reglist);
2800   }
2801   if (dops[i].opcode==0x25) { // LHU
2802     if(!c||memtarget) {
2803       if(!dummy) {
2804         int x=0,a=tl;
2805         if(!c) a=addr;
2806         if(fastio_reg_override>=0) a=fastio_reg_override;
2807         emit_movzwl_indexed(x,a,tl);
2808       }
2809       if(jaddr)
2810         add_stub_r(LOADHU_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist);
2811     }
2812     else
2813       inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj[i],reglist);
2814   }
2815   if (dops[i].opcode==0x27) { // LWU
2816     assert(0);
2817   }
2818   if (dops[i].opcode==0x37) { // LD
2819     assert(0);
2820   }
2821  }
2822  if (fastio_reg_override == HOST_TEMPREG)
2823    host_tempreg_release();
2824 }
2825
2826 #ifndef loadlr_assemble
2827 static void loadlr_assemble(int i, const struct regstat *i_regs)
2828 {
2829   int s,tl,temp,temp2,addr;
2830   int offset;
2831   void *jaddr=0;
2832   int memtarget=0,c=0;
2833   int fastio_reg_override=-1;
2834   u_int reglist=get_host_reglist(i_regs->regmap);
2835   tl=get_reg(i_regs->regmap,dops[i].rt1);
2836   s=get_reg(i_regs->regmap,dops[i].rs1);
2837   temp=get_reg(i_regs->regmap,-1);
2838   temp2=get_reg(i_regs->regmap,FTEMP);
2839   addr=get_reg(i_regs->regmap,AGEN1+(i&1));
2840   assert(addr<0);
2841   offset=imm[i];
2842   reglist|=1<<temp;
2843   if(offset||s<0||c) addr=temp2;
2844   else addr=s;
2845   if(s>=0) {
2846     c=(i_regs->wasconst>>s)&1;
2847     if(c) {
2848       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2849     }
2850   }
2851   if(!c) {
2852     emit_shlimm(addr,3,temp);
2853     if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
2854       emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR
2855     }else{
2856       emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR
2857     }
2858     jaddr=emit_fastpath_cmp_jump(i,temp2,&fastio_reg_override);
2859   }
2860   else {
2861     if(ram_offset&&memtarget) {
2862       host_tempreg_acquire();
2863       emit_addimm(temp2,ram_offset,HOST_TEMPREG);
2864       fastio_reg_override=HOST_TEMPREG;
2865     }
2866     if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
2867       emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
2868     }else{
2869       emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
2870     }
2871   }
2872   if (dops[i].opcode==0x22||dops[i].opcode==0x26) { // LWL/LWR
2873     if(!c||memtarget) {
2874       int a=temp2;
2875       if(fastio_reg_override>=0) a=fastio_reg_override;
2876       emit_readword_indexed(0,a,temp2);
2877       if(fastio_reg_override==HOST_TEMPREG) host_tempreg_release();
2878       if(jaddr) add_stub_r(LOADW_STUB,jaddr,out,i,temp2,i_regs,ccadj[i],reglist);
2879     }
2880     else
2881       inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj[i],reglist);
2882     if(dops[i].rt1) {
2883       assert(tl>=0);
2884       emit_andimm(temp,24,temp);
2885       if (dops[i].opcode==0x22) // LWL
2886         emit_xorimm(temp,24,temp);
2887       host_tempreg_acquire();
2888       emit_movimm(-1,HOST_TEMPREG);
2889       if (dops[i].opcode==0x26) {
2890         emit_shr(temp2,temp,temp2);
2891         emit_bic_lsr(tl,HOST_TEMPREG,temp,tl);
2892       }else{
2893         emit_shl(temp2,temp,temp2);
2894         emit_bic_lsl(tl,HOST_TEMPREG,temp,tl);
2895       }
2896       host_tempreg_release();
2897       emit_or(temp2,tl,tl);
2898     }
2899     //emit_storereg(dops[i].rt1,tl); // DEBUG
2900   }
2901   if (dops[i].opcode==0x1A||dops[i].opcode==0x1B) { // LDL/LDR
2902     assert(0);
2903   }
2904 }
2905 #endif
2906
2907 void store_assemble(int i, const struct regstat *i_regs)
2908 {
2909   int s,tl;
2910   int addr,temp;
2911   int offset;
2912   void *jaddr=0;
2913   enum stub_type type;
2914   int memtarget=0,c=0;
2915   int agr=AGEN1+(i&1);
2916   int fastio_reg_override=-1;
2917   u_int reglist=get_host_reglist(i_regs->regmap);
2918   tl=get_reg(i_regs->regmap,dops[i].rs2);
2919   s=get_reg(i_regs->regmap,dops[i].rs1);
2920   temp=get_reg(i_regs->regmap,agr);
2921   if(temp<0) temp=get_reg(i_regs->regmap,-1);
2922   offset=imm[i];
2923   if(s>=0) {
2924     c=(i_regs->wasconst>>s)&1;
2925     if(c) {
2926       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2927     }
2928   }
2929   assert(tl>=0);
2930   assert(temp>=0);
2931   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2932   if(offset||s<0||c) addr=temp;
2933   else addr=s;
2934   if(!c) {
2935     jaddr=emit_fastpath_cmp_jump(i,addr,&fastio_reg_override);
2936   }
2937   else if(ram_offset&&memtarget) {
2938     host_tempreg_acquire();
2939     emit_addimm(addr,ram_offset,HOST_TEMPREG);
2940     fastio_reg_override=HOST_TEMPREG;
2941   }
2942
2943   if (dops[i].opcode==0x28) { // SB
2944     if(!c||memtarget) {
2945       int x=0,a=temp;
2946       if(!c) a=addr;
2947       if(fastio_reg_override>=0) a=fastio_reg_override;
2948       emit_writebyte_indexed(tl,x,a);
2949     }
2950     type=STOREB_STUB;
2951   }
2952   if (dops[i].opcode==0x29) { // SH
2953     if(!c||memtarget) {
2954       int x=0,a=temp;
2955       if(!c) a=addr;
2956       if(fastio_reg_override>=0) a=fastio_reg_override;
2957       emit_writehword_indexed(tl,x,a);
2958     }
2959     type=STOREH_STUB;
2960   }
2961   if (dops[i].opcode==0x2B) { // SW
2962     if(!c||memtarget) {
2963       int a=addr;
2964       if(fastio_reg_override>=0) a=fastio_reg_override;
2965       emit_writeword_indexed(tl,0,a);
2966     }
2967     type=STOREW_STUB;
2968   }
2969   if (dops[i].opcode==0x3F) { // SD
2970     assert(0);
2971     type=STORED_STUB;
2972   }
2973   if(fastio_reg_override==HOST_TEMPREG)
2974     host_tempreg_release();
2975   if(jaddr) {
2976     // PCSX store handlers don't check invcode again
2977     reglist|=1<<addr;
2978     add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj[i],reglist);
2979     jaddr=0;
2980   }
2981   if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
2982     if(!c||memtarget) {
2983       #ifdef DESTRUCTIVE_SHIFT
2984       // The x86 shift operation is 'destructive'; it overwrites the
2985       // source register, so we need to make a copy first and use that.
2986       addr=temp;
2987       #endif
2988       #if defined(HOST_IMM8)
2989       int ir=get_reg(i_regs->regmap,INVCP);
2990       assert(ir>=0);
2991       emit_cmpmem_indexedsr12_reg(ir,addr,1);
2992       #else
2993       emit_cmpmem_indexedsr12_imm(invalid_code,addr,1);
2994       #endif
2995       #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
2996       emit_callne(invalidate_addr_reg[addr]);
2997       #else
2998       void *jaddr2 = out;
2999       emit_jne(0);
3000       add_stub(INVCODE_STUB,jaddr2,out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3001       #endif
3002     }
3003   }
3004   u_int addr_val=constmap[i][s]+offset;
3005   if(jaddr) {
3006     add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj[i],reglist);
3007   } else if(c&&!memtarget) {
3008     inline_writestub(type,i,addr_val,i_regs->regmap,dops[i].rs2,ccadj[i],reglist);
3009   }
3010   // basic current block modification detection..
3011   // not looking back as that should be in mips cache already
3012   // (see Spyro2 title->attract mode)
3013   if(c&&start+i*4<addr_val&&addr_val<start+slen*4) {
3014     SysPrintf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4);
3015     assert(i_regs->regmap==regs[i].regmap); // not delay slot
3016     if(i_regs->regmap==regs[i].regmap) {
3017       load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
3018       wb_dirtys(regs[i].regmap_entry,regs[i].wasdirty);
3019       emit_movimm(start+i*4+4,0);
3020       emit_writeword(0,&pcaddr);
3021       emit_addimm(HOST_CCREG,2,HOST_CCREG);
3022       emit_far_call(get_addr_ht);
3023       emit_jmpreg(0);
3024     }
3025   }
3026 }
3027
3028 static void storelr_assemble(int i, const struct regstat *i_regs)
3029 {
3030   int s,tl;
3031   int temp;
3032   int offset;
3033   void *jaddr=0;
3034   void *case1, *case2, *case3;
3035   void *done0, *done1, *done2;
3036   int memtarget=0,c=0;
3037   int agr=AGEN1+(i&1);
3038   u_int reglist=get_host_reglist(i_regs->regmap);
3039   tl=get_reg(i_regs->regmap,dops[i].rs2);
3040   s=get_reg(i_regs->regmap,dops[i].rs1);
3041   temp=get_reg(i_regs->regmap,agr);
3042   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3043   offset=imm[i];
3044   if(s>=0) {
3045     c=(i_regs->isconst>>s)&1;
3046     if(c) {
3047       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3048     }
3049   }
3050   assert(tl>=0);
3051   assert(temp>=0);
3052   if(!c) {
3053     emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3054     if(!offset&&s!=temp) emit_mov(s,temp);
3055     jaddr=out;
3056     emit_jno(0);
3057   }
3058   else
3059   {
3060     if(!memtarget||!dops[i].rs1) {
3061       jaddr=out;
3062       emit_jmp(0);
3063     }
3064   }
3065   if(ram_offset)
3066     emit_addimm_no_flags(ram_offset,temp);
3067
3068   if (dops[i].opcode==0x2C||dops[i].opcode==0x2D) { // SDL/SDR
3069     assert(0);
3070   }
3071
3072   emit_xorimm(temp,3,temp);
3073   emit_testimm(temp,2);
3074   case2=out;
3075   emit_jne(0);
3076   emit_testimm(temp,1);
3077   case1=out;
3078   emit_jne(0);
3079   // 0
3080   if (dops[i].opcode==0x2A) { // SWL
3081     emit_writeword_indexed(tl,0,temp);
3082   }
3083   else if (dops[i].opcode==0x2E) { // SWR
3084     emit_writebyte_indexed(tl,3,temp);
3085   }
3086   else
3087     assert(0);
3088   done0=out;
3089   emit_jmp(0);
3090   // 1
3091   set_jump_target(case1, out);
3092   if (dops[i].opcode==0x2A) { // SWL
3093     // Write 3 msb into three least significant bytes
3094     if(dops[i].rs2) emit_rorimm(tl,8,tl);
3095     emit_writehword_indexed(tl,-1,temp);
3096     if(dops[i].rs2) emit_rorimm(tl,16,tl);
3097     emit_writebyte_indexed(tl,1,temp);
3098     if(dops[i].rs2) emit_rorimm(tl,8,tl);
3099   }
3100   else if (dops[i].opcode==0x2E) { // SWR
3101     // Write two lsb into two most significant bytes
3102     emit_writehword_indexed(tl,1,temp);
3103   }
3104   done1=out;
3105   emit_jmp(0);
3106   // 2
3107   set_jump_target(case2, out);
3108   emit_testimm(temp,1);
3109   case3=out;
3110   emit_jne(0);
3111   if (dops[i].opcode==0x2A) { // SWL
3112     // Write two msb into two least significant bytes
3113     if(dops[i].rs2) emit_rorimm(tl,16,tl);
3114     emit_writehword_indexed(tl,-2,temp);
3115     if(dops[i].rs2) emit_rorimm(tl,16,tl);
3116   }
3117   else if (dops[i].opcode==0x2E) { // SWR
3118     // Write 3 lsb into three most significant bytes
3119     emit_writebyte_indexed(tl,-1,temp);
3120     if(dops[i].rs2) emit_rorimm(tl,8,tl);
3121     emit_writehword_indexed(tl,0,temp);
3122     if(dops[i].rs2) emit_rorimm(tl,24,tl);
3123   }
3124   done2=out;
3125   emit_jmp(0);
3126   // 3
3127   set_jump_target(case3, out);
3128   if (dops[i].opcode==0x2A) { // SWL
3129     // Write msb into least significant byte
3130     if(dops[i].rs2) emit_rorimm(tl,24,tl);
3131     emit_writebyte_indexed(tl,-3,temp);
3132     if(dops[i].rs2) emit_rorimm(tl,8,tl);
3133   }
3134   else if (dops[i].opcode==0x2E) { // SWR
3135     // Write entire word
3136     emit_writeword_indexed(tl,-3,temp);
3137   }
3138   set_jump_target(done0, out);
3139   set_jump_target(done1, out);
3140   set_jump_target(done2, out);
3141   if(!c||!memtarget)
3142     add_stub_r(STORELR_STUB,jaddr,out,i,temp,i_regs,ccadj[i],reglist);
3143   if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
3144     emit_addimm_no_flags(-ram_offset,temp);
3145     #if defined(HOST_IMM8)
3146     int ir=get_reg(i_regs->regmap,INVCP);
3147     assert(ir>=0);
3148     emit_cmpmem_indexedsr12_reg(ir,temp,1);
3149     #else
3150     emit_cmpmem_indexedsr12_imm(invalid_code,temp,1);
3151     #endif
3152     #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3153     emit_callne(invalidate_addr_reg[temp]);
3154     #else
3155     void *jaddr2 = out;
3156     emit_jne(0);
3157     add_stub(INVCODE_STUB,jaddr2,out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3158     #endif
3159   }
3160 }
3161
3162 static void cop0_assemble(int i,struct regstat *i_regs)
3163 {
3164   if(dops[i].opcode2==0) // MFC0
3165   {
3166     signed char t=get_reg(i_regs->regmap,dops[i].rt1);
3167     u_int copr=(source[i]>>11)&0x1f;
3168     //assert(t>=0); // Why does this happen?  OOT is weird
3169     if(t>=0&&dops[i].rt1!=0) {
3170       emit_readword(&reg_cop0[copr],t);
3171     }
3172   }
3173   else if(dops[i].opcode2==4) // MTC0
3174   {
3175     signed char s=get_reg(i_regs->regmap,dops[i].rs1);
3176     char copr=(source[i]>>11)&0x1f;
3177     assert(s>=0);
3178     wb_register(dops[i].rs1,i_regs->regmap,i_regs->dirty);
3179     if(copr==9||copr==11||copr==12||copr==13) {
3180       emit_readword(&last_count,HOST_TEMPREG);
3181       emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
3182       emit_add(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
3183       emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
3184       emit_writeword(HOST_CCREG,&Count);
3185     }
3186     // What a mess.  The status register (12) can enable interrupts,
3187     // so needs a special case to handle a pending interrupt.
3188     // The interrupt must be taken immediately, because a subsequent
3189     // instruction might disable interrupts again.
3190     if(copr==12||copr==13) {
3191       if (is_delayslot) {
3192         // burn cycles to cause cc_interrupt, which will
3193         // reschedule next_interupt. Relies on CCREG from above.
3194         assem_debug("MTC0 DS %d\n", copr);
3195         emit_writeword(HOST_CCREG,&last_count);
3196         emit_movimm(0,HOST_CCREG);
3197         emit_storereg(CCREG,HOST_CCREG);
3198         emit_loadreg(dops[i].rs1,1);
3199         emit_movimm(copr,0);
3200         emit_far_call(pcsx_mtc0_ds);
3201         emit_loadreg(dops[i].rs1,s);
3202         return;
3203       }
3204       emit_movimm(start+i*4+4,HOST_TEMPREG);
3205       emit_writeword(HOST_TEMPREG,&pcaddr);
3206       emit_movimm(0,HOST_TEMPREG);
3207       emit_writeword(HOST_TEMPREG,&pending_exception);
3208     }
3209     if(s==HOST_CCREG)
3210       emit_loadreg(dops[i].rs1,1);
3211     else if(s!=1)
3212       emit_mov(s,1);
3213     emit_movimm(copr,0);
3214     emit_far_call(pcsx_mtc0);
3215     if(copr==9||copr==11||copr==12||copr==13) {
3216       emit_readword(&Count,HOST_CCREG);
3217       emit_readword(&next_interupt,HOST_TEMPREG);
3218       emit_addimm(HOST_CCREG,-CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
3219       emit_sub(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
3220       emit_writeword(HOST_TEMPREG,&last_count);
3221       emit_storereg(CCREG,HOST_CCREG);
3222     }
3223     if(copr==12||copr==13) {
3224       assert(!is_delayslot);
3225       emit_readword(&pending_exception,14);
3226       emit_test(14,14);
3227       void *jaddr = out;
3228       emit_jeq(0);
3229       emit_readword(&pcaddr, 0);
3230       emit_addimm(HOST_CCREG,2,HOST_CCREG);
3231       emit_far_call(get_addr_ht);
3232       emit_jmpreg(0);
3233       set_jump_target(jaddr, out);
3234     }
3235     emit_loadreg(dops[i].rs1,s);
3236   }
3237   else
3238   {
3239     assert(dops[i].opcode2==0x10);
3240     //if((source[i]&0x3f)==0x10) // RFE
3241     {
3242       emit_readword(&Status,0);
3243       emit_andimm(0,0x3c,1);
3244       emit_andimm(0,~0xf,0);
3245       emit_orrshr_imm(1,2,0);
3246       emit_writeword(0,&Status);
3247     }
3248   }
3249 }
3250
3251 static void cop1_unusable(int i,struct regstat *i_regs)
3252 {
3253   // XXX: should just just do the exception instead
3254   //if(!cop1_usable)
3255   {
3256     void *jaddr=out;
3257     emit_jmp(0);
3258     add_stub_r(FP_STUB,jaddr,out,i,0,i_regs,is_delayslot,0);
3259   }
3260 }
3261
3262 static void cop1_assemble(int i,struct regstat *i_regs)
3263 {
3264   cop1_unusable(i, i_regs);
3265 }
3266
3267 static void c1ls_assemble(int i,struct regstat *i_regs)
3268 {
3269   cop1_unusable(i, i_regs);
3270 }
3271
3272 // FP_STUB
3273 static void do_cop1stub(int n)
3274 {
3275   literal_pool(256);
3276   assem_debug("do_cop1stub %x\n",start+stubs[n].a*4);
3277   set_jump_target(stubs[n].addr, out);
3278   int i=stubs[n].a;
3279 //  int rs=stubs[n].b;
3280   struct regstat *i_regs=(struct regstat *)stubs[n].c;
3281   int ds=stubs[n].d;
3282   if(!ds) {
3283     load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
3284     //if(i_regs!=&regs[i]) printf("oops: regs[i]=%x i_regs=%x",(int)&regs[i],(int)i_regs);
3285   }
3286   //else {printf("fp exception in delay slot\n");}
3287   wb_dirtys(i_regs->regmap_entry,i_regs->wasdirty);
3288   if(regs[i].regmap_entry[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
3289   emit_movimm(start+(i-ds)*4,EAX); // Get PC
3290   emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // CHECK: is this right?  There should probably be an extra cycle...
3291   emit_far_jump(ds?fp_exception_ds:fp_exception);
3292 }
3293
3294 static int cop2_is_stalling_op(int i, int *cycles)
3295 {
3296   if (dops[i].opcode == 0x3a) { // SWC2
3297     *cycles = 0;
3298     return 1;
3299   }
3300   if (dops[i].itype == COP2 && (dops[i].opcode2 == 0 || dops[i].opcode2 == 2)) { // MFC2/CFC2
3301     *cycles = 0;
3302     return 1;
3303   }
3304   if (dops[i].itype == C2OP) {
3305     *cycles = gte_cycletab[source[i] & 0x3f];
3306     return 1;
3307   }
3308   // ... what about MTC2/CTC2/LWC2?
3309   return 0;
3310 }
3311
3312 #if 0
3313 static void log_gte_stall(int stall, u_int cycle)
3314 {
3315   if ((u_int)stall <= 44)
3316     printf("x    stall %2d %u\n", stall, cycle + last_count);
3317 }
3318
3319 static void emit_log_gte_stall(int i, int stall, u_int reglist)
3320 {
3321   save_regs(reglist);
3322   if (stall > 0)
3323     emit_movimm(stall, 0);
3324   else
3325     emit_mov(HOST_TEMPREG, 0);
3326   emit_addimm(HOST_CCREG, CLOCK_ADJUST(ccadj[i]), 1);
3327   emit_far_call(log_gte_stall);
3328   restore_regs(reglist);
3329 }
3330 #endif
3331
3332 static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist)
3333 {
3334   int j = i, other_gte_op_cycles = -1, stall = -MAXBLOCK, cycles_passed;
3335   int rtmp = reglist_find_free(reglist);
3336
3337   if (HACK_ENABLED(NDHACK_NO_STALLS))
3338     return;
3339   if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3340     // happens occasionally... cc evicted? Don't bother then
3341     //printf("no cc %08x\n", start + i*4);
3342     return;
3343   }
3344   if (!dops[i].bt) {
3345     for (j = i - 1; j >= 0; j--) {
3346       //if (dops[j].is_ds) break;
3347       if (cop2_is_stalling_op(j, &other_gte_op_cycles) || dops[j].bt)
3348         break;
3349     }
3350     j = max(j, 0);
3351   }
3352   cycles_passed = CLOCK_ADJUST(ccadj[i] - ccadj[j]);
3353   if (other_gte_op_cycles >= 0)
3354     stall = other_gte_op_cycles - cycles_passed;
3355   else if (cycles_passed >= 44)
3356     stall = 0; // can't stall
3357   if (stall == -MAXBLOCK && rtmp >= 0) {
3358     // unknown stall, do the expensive runtime check
3359     assem_debug("; cop2_do_stall_check\n");
3360 #if 0 // too slow
3361     save_regs(reglist);
3362     emit_movimm(gte_cycletab[op], 0);
3363     emit_addimm(HOST_CCREG, CLOCK_ADJUST(ccadj[i]), 1);
3364     emit_far_call(call_gteStall);
3365     restore_regs(reglist);
3366 #else
3367     host_tempreg_acquire();
3368     emit_readword(&psxRegs.gteBusyCycle, rtmp);
3369     emit_addimm(rtmp, -CLOCK_ADJUST(ccadj[i]), rtmp);
3370     emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3371     emit_cmpimm(HOST_TEMPREG, 44);
3372     emit_cmovb_reg(rtmp, HOST_CCREG);
3373     //emit_log_gte_stall(i, 0, reglist);
3374     host_tempreg_release();
3375 #endif
3376   }
3377   else if (stall > 0) {
3378     //emit_log_gte_stall(i, stall, reglist);
3379     emit_addimm(HOST_CCREG, stall, HOST_CCREG);
3380   }
3381
3382   // save gteBusyCycle, if needed
3383   if (gte_cycletab[op] == 0)
3384     return;
3385   other_gte_op_cycles = -1;
3386   for (j = i + 1; j < slen; j++) {
3387     if (cop2_is_stalling_op(j, &other_gte_op_cycles))
3388       break;
3389     if (dops[j].is_jump) {
3390       // check ds
3391       if (j + 1 < slen && cop2_is_stalling_op(j + 1, &other_gte_op_cycles))
3392         j++;
3393       break;
3394     }
3395   }
3396   if (other_gte_op_cycles >= 0)
3397     // will handle stall when assembling that op
3398     return;
3399   cycles_passed = CLOCK_ADJUST(ccadj[min(j, slen -1)] - ccadj[i]);
3400   if (cycles_passed >= 44)
3401     return;
3402   assem_debug("; save gteBusyCycle\n");
3403   host_tempreg_acquire();
3404 #if 0
3405   emit_readword(&last_count, HOST_TEMPREG);
3406   emit_add(HOST_TEMPREG, HOST_CCREG, HOST_TEMPREG);
3407   emit_addimm(HOST_TEMPREG, CLOCK_ADJUST(ccadj[i]), HOST_TEMPREG);
3408   emit_addimm(HOST_TEMPREG, gte_cycletab[op]), HOST_TEMPREG);
3409   emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3410 #else
3411   emit_addimm(HOST_CCREG, CLOCK_ADJUST(ccadj[i]) + gte_cycletab[op], HOST_TEMPREG);
3412   emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3413 #endif
3414   host_tempreg_release();
3415 }
3416
3417 static int is_mflohi(int i)
3418 {
3419   return (dops[i].itype == MOV && (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG));
3420 }
3421
3422 static int check_multdiv(int i, int *cycles)
3423 {
3424   if (dops[i].itype != MULTDIV)
3425     return 0;
3426   if (dops[i].opcode2 == 0x18 || dops[i].opcode2 == 0x19) // MULT(U)
3427     *cycles = 11; // approx from 7 11 14
3428   else
3429     *cycles = 37;
3430   return 1;
3431 }
3432
3433 static void multdiv_prepare_stall(int i, const struct regstat *i_regs)
3434 {
3435   int j, found = 0, c = 0;
3436   if (HACK_ENABLED(NDHACK_NO_STALLS))
3437     return;
3438   if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3439     // happens occasionally... cc evicted? Don't bother then
3440     return;
3441   }
3442   for (j = i + 1; j < slen; j++) {
3443     if (dops[j].bt)
3444       break;
3445     if ((found = is_mflohi(j)))
3446       break;
3447     if (dops[j].is_jump) {
3448       // check ds
3449       if (j + 1 < slen && (found = is_mflohi(j + 1)))
3450         j++;
3451       break;
3452     }
3453   }
3454   if (found)
3455     // handle all in multdiv_do_stall()
3456     return;
3457   check_multdiv(i, &c);
3458   assert(c > 0);
3459   assem_debug("; muldiv prepare stall %d\n", c);
3460   host_tempreg_acquire();
3461   emit_addimm(HOST_CCREG, CLOCK_ADJUST(ccadj[i]) + c, HOST_TEMPREG);
3462   emit_writeword(HOST_TEMPREG, &psxRegs.muldivBusyCycle);
3463   host_tempreg_release();
3464 }
3465
3466 static void multdiv_do_stall(int i, const struct regstat *i_regs)
3467 {
3468   int j, known_cycles = 0;
3469   u_int reglist = get_host_reglist(i_regs->regmap);
3470   int rtmp = get_reg(i_regs->regmap, -1);
3471   if (rtmp < 0)
3472     rtmp = reglist_find_free(reglist);
3473   if (HACK_ENABLED(NDHACK_NO_STALLS))
3474     return;
3475   if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG || rtmp < 0) {
3476     // happens occasionally... cc evicted? Don't bother then
3477     //printf("no cc/rtmp %08x\n", start + i*4);
3478     return;
3479   }
3480   if (!dops[i].bt) {
3481     for (j = i - 1; j >= 0; j--) {
3482       if (dops[j].is_ds) break;
3483       if (check_multdiv(j, &known_cycles) || dops[j].bt)
3484         break;
3485       if (is_mflohi(j))
3486         // already handled by this op
3487         return;
3488     }
3489     j = max(j, 0);
3490   }
3491   if (known_cycles > 0) {
3492     known_cycles -= CLOCK_ADJUST(ccadj[i] - ccadj[j]);
3493     assem_debug("; muldiv stall resolved %d\n", known_cycles);
3494     if (known_cycles > 0)
3495       emit_addimm(HOST_CCREG, known_cycles, HOST_CCREG);
3496     return;
3497   }
3498   assem_debug("; muldiv stall unresolved\n");
3499   host_tempreg_acquire();
3500   emit_readword(&psxRegs.muldivBusyCycle, rtmp);
3501   emit_addimm(rtmp, -CLOCK_ADJUST(ccadj[i]), rtmp);
3502   emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3503   emit_cmpimm(HOST_TEMPREG, 37);
3504   emit_cmovb_reg(rtmp, HOST_CCREG);
3505   //emit_log_gte_stall(i, 0, reglist);
3506   host_tempreg_release();
3507 }
3508
3509 static void cop2_get_dreg(u_int copr,signed char tl,signed char temp)
3510 {
3511   switch (copr) {
3512     case 1:
3513     case 3:
3514     case 5:
3515     case 8:
3516     case 9:
3517     case 10:
3518     case 11:
3519       emit_readword(&reg_cop2d[copr],tl);
3520       emit_signextend16(tl,tl);
3521       emit_writeword(tl,&reg_cop2d[copr]); // hmh
3522       break;
3523     case 7:
3524     case 16:
3525     case 17:
3526     case 18:
3527     case 19:
3528       emit_readword(&reg_cop2d[copr],tl);
3529       emit_andimm(tl,0xffff,tl);
3530       emit_writeword(tl,&reg_cop2d[copr]);
3531       break;
3532     case 15:
3533       emit_readword(&reg_cop2d[14],tl); // SXY2
3534       emit_writeword(tl,&reg_cop2d[copr]);
3535       break;
3536     case 28:
3537     case 29:
3538       c2op_mfc2_29_assemble(tl,temp);
3539       break;
3540     default:
3541       emit_readword(&reg_cop2d[copr],tl);
3542       break;
3543   }
3544 }
3545
3546 static void cop2_put_dreg(u_int copr,signed char sl,signed char temp)
3547 {
3548   switch (copr) {
3549     case 15:
3550       emit_readword(&reg_cop2d[13],temp);  // SXY1
3551       emit_writeword(sl,&reg_cop2d[copr]);
3552       emit_writeword(temp,&reg_cop2d[12]); // SXY0
3553       emit_readword(&reg_cop2d[14],temp);  // SXY2
3554       emit_writeword(sl,&reg_cop2d[14]);
3555       emit_writeword(temp,&reg_cop2d[13]); // SXY1
3556       break;
3557     case 28:
3558       emit_andimm(sl,0x001f,temp);
3559       emit_shlimm(temp,7,temp);
3560       emit_writeword(temp,&reg_cop2d[9]);
3561       emit_andimm(sl,0x03e0,temp);
3562       emit_shlimm(temp,2,temp);
3563       emit_writeword(temp,&reg_cop2d[10]);
3564       emit_andimm(sl,0x7c00,temp);
3565       emit_shrimm(temp,3,temp);
3566       emit_writeword(temp,&reg_cop2d[11]);
3567       emit_writeword(sl,&reg_cop2d[28]);
3568       break;
3569     case 30:
3570       emit_xorsar_imm(sl,sl,31,temp);
3571 #if defined(HAVE_ARMV5) || defined(__aarch64__)
3572       emit_clz(temp,temp);
3573 #else
3574       emit_movs(temp,HOST_TEMPREG);
3575       emit_movimm(0,temp);
3576       emit_jeq((int)out+4*4);
3577       emit_addpl_imm(temp,1,temp);
3578       emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG);
3579       emit_jns((int)out-2*4);
3580 #endif
3581       emit_writeword(sl,&reg_cop2d[30]);
3582       emit_writeword(temp,&reg_cop2d[31]);
3583       break;
3584     case 31:
3585       break;
3586     default:
3587       emit_writeword(sl,&reg_cop2d[copr]);
3588       break;
3589   }
3590 }
3591
3592 static void c2ls_assemble(int i, const struct regstat *i_regs)
3593 {
3594   int s,tl;
3595   int ar;
3596   int offset;
3597   int memtarget=0,c=0;
3598   void *jaddr2=NULL;
3599   enum stub_type type;
3600   int agr=AGEN1+(i&1);
3601   int fastio_reg_override=-1;
3602   u_int reglist=get_host_reglist(i_regs->regmap);
3603   u_int copr=(source[i]>>16)&0x1f;
3604   s=get_reg(i_regs->regmap,dops[i].rs1);
3605   tl=get_reg(i_regs->regmap,FTEMP);
3606   offset=imm[i];
3607   assert(dops[i].rs1>0);
3608   assert(tl>=0);
3609
3610   if(i_regs->regmap[HOST_CCREG]==CCREG)
3611     reglist&=~(1<<HOST_CCREG);
3612
3613   // get the address
3614   if (dops[i].opcode==0x3a) { // SWC2
3615     ar=get_reg(i_regs->regmap,agr);
3616     if(ar<0) ar=get_reg(i_regs->regmap,-1);
3617     reglist|=1<<ar;
3618   } else { // LWC2
3619     ar=tl;
3620   }
3621   if(s>=0) c=(i_regs->wasconst>>s)&1;
3622   memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3623   if (!offset&&!c&&s>=0) ar=s;
3624   assert(ar>=0);
3625
3626   cop2_do_stall_check(0, i, i_regs, reglist);
3627
3628   if (dops[i].opcode==0x3a) { // SWC2
3629     cop2_get_dreg(copr,tl,-1);
3630     type=STOREW_STUB;
3631   }
3632   else
3633     type=LOADW_STUB;
3634
3635   if(c&&!memtarget) {
3636     jaddr2=out;
3637     emit_jmp(0); // inline_readstub/inline_writestub?
3638   }
3639   else {
3640     if(!c) {
3641       jaddr2=emit_fastpath_cmp_jump(i,ar,&fastio_reg_override);
3642     }
3643     else if(ram_offset&&memtarget) {
3644       host_tempreg_acquire();
3645       emit_addimm(ar,ram_offset,HOST_TEMPREG);
3646       fastio_reg_override=HOST_TEMPREG;
3647     }
3648     if (dops[i].opcode==0x32) { // LWC2
3649       int a=ar;
3650       if(fastio_reg_override>=0) a=fastio_reg_override;
3651       emit_readword_indexed(0,a,tl);
3652     }
3653     if (dops[i].opcode==0x3a) { // SWC2
3654       #ifdef DESTRUCTIVE_SHIFT
3655       if(!offset&&!c&&s>=0) emit_mov(s,ar);
3656       #endif
3657       int a=ar;
3658       if(fastio_reg_override>=0) a=fastio_reg_override;
3659       emit_writeword_indexed(tl,0,a);
3660     }
3661   }
3662   if(fastio_reg_override==HOST_TEMPREG)
3663     host_tempreg_release();
3664   if(jaddr2)
3665     add_stub_r(type,jaddr2,out,i,ar,i_regs,ccadj[i],reglist);
3666   if(dops[i].opcode==0x3a) // SWC2
3667   if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
3668 #if defined(HOST_IMM8)
3669     int ir=get_reg(i_regs->regmap,INVCP);
3670     assert(ir>=0);
3671     emit_cmpmem_indexedsr12_reg(ir,ar,1);
3672 #else
3673     emit_cmpmem_indexedsr12_imm(invalid_code,ar,1);
3674 #endif
3675     #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3676     emit_callne(invalidate_addr_reg[ar]);
3677     #else
3678     void *jaddr3 = out;
3679     emit_jne(0);
3680     add_stub(INVCODE_STUB,jaddr3,out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3681     #endif
3682   }
3683   if (dops[i].opcode==0x32) { // LWC2
3684     host_tempreg_acquire();
3685     cop2_put_dreg(copr,tl,HOST_TEMPREG);
3686     host_tempreg_release();
3687   }
3688 }
3689
3690 static void cop2_assemble(int i, const struct regstat *i_regs)
3691 {
3692   u_int copr = (source[i]>>11) & 0x1f;
3693   signed char temp = get_reg(i_regs->regmap, -1);
3694
3695   if (!HACK_ENABLED(NDHACK_NO_STALLS)) {
3696     u_int reglist = reglist_exclude(get_host_reglist(i_regs->regmap), temp, -1);
3697     if (dops[i].opcode2 == 0 || dops[i].opcode2 == 2) { // MFC2/CFC2
3698       signed char tl = get_reg(i_regs->regmap, dops[i].rt1);
3699       reglist = reglist_exclude(reglist, tl, -1);
3700     }
3701     cop2_do_stall_check(0, i, i_regs, reglist);
3702   }
3703   if (dops[i].opcode2==0) { // MFC2
3704     signed char tl=get_reg(i_regs->regmap,dops[i].rt1);
3705     if(tl>=0&&dops[i].rt1!=0)
3706       cop2_get_dreg(copr,tl,temp);
3707   }
3708   else if (dops[i].opcode2==4) { // MTC2
3709     signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
3710     cop2_put_dreg(copr,sl,temp);
3711   }
3712   else if (dops[i].opcode2==2) // CFC2
3713   {
3714     signed char tl=get_reg(i_regs->regmap,dops[i].rt1);
3715     if(tl>=0&&dops[i].rt1!=0)
3716       emit_readword(&reg_cop2c[copr],tl);
3717   }
3718   else if (dops[i].opcode2==6) // CTC2
3719   {
3720     signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
3721     switch(copr) {
3722       case 4:
3723       case 12:
3724       case 20:
3725       case 26:
3726       case 27:
3727       case 29:
3728       case 30:
3729         emit_signextend16(sl,temp);
3730         break;
3731       case 31:
3732         c2op_ctc2_31_assemble(sl,temp);
3733         break;
3734       default:
3735         temp=sl;
3736         break;
3737     }
3738     emit_writeword(temp,&reg_cop2c[copr]);
3739     assert(sl>=0);
3740   }
3741 }
3742
3743 static void do_unalignedwritestub(int n)
3744 {
3745   assem_debug("do_unalignedwritestub %x\n",start+stubs[n].a*4);
3746   literal_pool(256);
3747   set_jump_target(stubs[n].addr, out);
3748
3749   int i=stubs[n].a;
3750   struct regstat *i_regs=(struct regstat *)stubs[n].c;
3751   int addr=stubs[n].b;
3752   u_int reglist=stubs[n].e;
3753   signed char *i_regmap=i_regs->regmap;
3754   int temp2=get_reg(i_regmap,FTEMP);
3755   int rt;
3756   rt=get_reg(i_regmap,dops[i].rs2);
3757   assert(rt>=0);
3758   assert(addr>=0);
3759   assert(dops[i].opcode==0x2a||dops[i].opcode==0x2e); // SWL/SWR only implemented
3760   reglist|=(1<<addr);
3761   reglist&=~(1<<temp2);
3762
3763   // don't bother with it and call write handler
3764   save_regs(reglist);
3765   pass_args(addr,rt);
3766   int cc=get_reg(i_regmap,CCREG);
3767   if(cc<0)
3768     emit_loadreg(CCREG,2);
3769   emit_addimm(cc<0?2:cc,CLOCK_ADJUST((int)stubs[n].d+1),2);
3770   emit_far_call((dops[i].opcode==0x2a?jump_handle_swl:jump_handle_swr));
3771   emit_addimm(0,-CLOCK_ADJUST((int)stubs[n].d+1),cc<0?2:cc);
3772   if(cc<0)
3773     emit_storereg(CCREG,2);
3774   restore_regs(reglist);
3775   emit_jmp(stubs[n].retaddr); // return address
3776 }
3777
3778 #ifndef multdiv_assemble
3779 void multdiv_assemble(int i,struct regstat *i_regs)
3780 {
3781   printf("Need multdiv_assemble for this architecture.\n");
3782   abort();
3783 }
3784 #endif
3785
3786 static void mov_assemble(int i,struct regstat *i_regs)
3787 {
3788   //if(dops[i].opcode2==0x10||dops[i].opcode2==0x12) { // MFHI/MFLO
3789   //if(dops[i].opcode2==0x11||dops[i].opcode2==0x13) { // MTHI/MTLO
3790   if(dops[i].rt1) {
3791     signed char sl,tl;
3792     tl=get_reg(i_regs->regmap,dops[i].rt1);
3793     //assert(tl>=0);
3794     if(tl>=0) {
3795       sl=get_reg(i_regs->regmap,dops[i].rs1);
3796       if(sl>=0) emit_mov(sl,tl);
3797       else emit_loadreg(dops[i].rs1,tl);
3798     }
3799   }
3800   if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) // MFHI/MFLO
3801     multdiv_do_stall(i, i_regs);
3802 }
3803
3804 // call interpreter, exception handler, things that change pc/regs/cycles ...
3805 static void call_c_cpu_handler(int i, const struct regstat *i_regs, u_int pc, void *func)
3806 {
3807   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3808   assert(ccreg==HOST_CCREG);
3809   assert(!is_delayslot);
3810   (void)ccreg;
3811
3812   emit_movimm(pc,3); // Get PC
3813   emit_readword(&last_count,2);
3814   emit_writeword(3,&psxRegs.pc);
3815   emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // XXX
3816   emit_add(2,HOST_CCREG,2);
3817   emit_writeword(2,&psxRegs.cycle);
3818   emit_far_call(func);
3819   emit_far_jump(jump_to_new_pc);
3820 }
3821
3822 static void syscall_assemble(int i,struct regstat *i_regs)
3823 {
3824   emit_movimm(0x20,0); // cause code
3825   emit_movimm(0,1);    // not in delay slot
3826   call_c_cpu_handler(i,i_regs,start+i*4,psxException);
3827 }
3828
3829 static void hlecall_assemble(int i,struct regstat *i_regs)
3830 {
3831   void *hlefunc = psxNULL;
3832   uint32_t hleCode = source[i] & 0x03ffffff;
3833   if (hleCode < ARRAY_SIZE(psxHLEt))
3834     hlefunc = psxHLEt[hleCode];
3835
3836   call_c_cpu_handler(i,i_regs,start+i*4+4,hlefunc);
3837 }
3838
3839 static void intcall_assemble(int i,struct regstat *i_regs)
3840 {
3841   call_c_cpu_handler(i,i_regs,start+i*4,execI);
3842 }
3843
3844 static void speculate_mov(int rs,int rt)
3845 {
3846   if(rt!=0) {
3847     smrv_strong_next|=1<<rt;
3848     smrv[rt]=smrv[rs];
3849   }
3850 }
3851
3852 static void speculate_mov_weak(int rs,int rt)
3853 {
3854   if(rt!=0) {
3855     smrv_weak_next|=1<<rt;
3856     smrv[rt]=smrv[rs];
3857   }
3858 }
3859
3860 static void speculate_register_values(int i)
3861 {
3862   if(i==0) {
3863     memcpy(smrv,psxRegs.GPR.r,sizeof(smrv));
3864     // gp,sp are likely to stay the same throughout the block
3865     smrv_strong_next=(1<<28)|(1<<29)|(1<<30);
3866     smrv_weak_next=~smrv_strong_next;
3867     //printf(" llr %08x\n", smrv[4]);
3868   }
3869   smrv_strong=smrv_strong_next;
3870   smrv_weak=smrv_weak_next;
3871   switch(dops[i].itype) {
3872     case ALU:
3873       if     ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
3874       else if((smrv_strong>>dops[i].rs2)&1) speculate_mov(dops[i].rs2,dops[i].rt1);
3875       else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
3876       else if((smrv_weak>>dops[i].rs2)&1) speculate_mov_weak(dops[i].rs2,dops[i].rt1);
3877       else {
3878         smrv_strong_next&=~(1<<dops[i].rt1);
3879         smrv_weak_next&=~(1<<dops[i].rt1);
3880       }
3881       break;
3882     case SHIFTIMM:
3883       smrv_strong_next&=~(1<<dops[i].rt1);
3884       smrv_weak_next&=~(1<<dops[i].rt1);
3885       // fallthrough
3886     case IMM16:
3887       if(dops[i].rt1&&is_const(&regs[i],dops[i].rt1)) {
3888         int value,hr=get_reg(regs[i].regmap,dops[i].rt1);
3889         if(hr>=0) {
3890           if(get_final_value(hr,i,&value))
3891                smrv[dops[i].rt1]=value;
3892           else smrv[dops[i].rt1]=constmap[i][hr];
3893           smrv_strong_next|=1<<dops[i].rt1;
3894         }
3895       }
3896       else {
3897         if     ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
3898         else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
3899       }
3900       break;
3901     case LOAD:
3902       if(start<0x2000&&(dops[i].rt1==26||(smrv[dops[i].rt1]>>24)==0xa0)) {
3903         // special case for BIOS
3904         smrv[dops[i].rt1]=0xa0000000;
3905         smrv_strong_next|=1<<dops[i].rt1;
3906         break;
3907       }
3908       // fallthrough
3909     case SHIFT:
3910     case LOADLR:
3911     case MOV:
3912       smrv_strong_next&=~(1<<dops[i].rt1);
3913       smrv_weak_next&=~(1<<dops[i].rt1);
3914       break;
3915     case COP0:
3916     case COP2:
3917       if(dops[i].opcode2==0||dops[i].opcode2==2) { // MFC/CFC
3918         smrv_strong_next&=~(1<<dops[i].rt1);
3919         smrv_weak_next&=~(1<<dops[i].rt1);
3920       }
3921       break;
3922     case C2LS:
3923       if (dops[i].opcode==0x32) { // LWC2
3924         smrv_strong_next&=~(1<<dops[i].rt1);
3925         smrv_weak_next&=~(1<<dops[i].rt1);
3926       }
3927       break;
3928   }
3929 #if 0
3930   int r=4;
3931   printf("x %08x %08x %d %d c %08x %08x\n",smrv[r],start+i*4,
3932     ((smrv_strong>>r)&1),(smrv_weak>>r)&1,regs[i].isconst,regs[i].wasconst);
3933 #endif
3934 }
3935
3936 static void ds_assemble(int i,struct regstat *i_regs)
3937 {
3938   speculate_register_values(i);
3939   is_delayslot=1;
3940   switch(dops[i].itype) {
3941     case ALU:
3942       alu_assemble(i,i_regs);break;
3943     case IMM16:
3944       imm16_assemble(i,i_regs);break;
3945     case SHIFT:
3946       shift_assemble(i,i_regs);break;
3947     case SHIFTIMM:
3948       shiftimm_assemble(i,i_regs);break;
3949     case LOAD:
3950       load_assemble(i,i_regs);break;
3951     case LOADLR:
3952       loadlr_assemble(i,i_regs);break;
3953     case STORE:
3954       store_assemble(i,i_regs);break;
3955     case STORELR:
3956       storelr_assemble(i,i_regs);break;
3957     case COP0:
3958       cop0_assemble(i,i_regs);break;
3959     case COP1:
3960       cop1_assemble(i,i_regs);break;
3961     case C1LS:
3962       c1ls_assemble(i,i_regs);break;
3963     case COP2:
3964       cop2_assemble(i,i_regs);break;
3965     case C2LS:
3966       c2ls_assemble(i,i_regs);break;
3967     case C2OP:
3968       c2op_assemble(i,i_regs);break;
3969     case MULTDIV:
3970       multdiv_assemble(i,i_regs);
3971       multdiv_prepare_stall(i,i_regs);
3972       break;
3973     case MOV:
3974       mov_assemble(i,i_regs);break;
3975     case SYSCALL:
3976     case HLECALL:
3977     case INTCALL:
3978     case SPAN:
3979     case UJUMP:
3980     case RJUMP:
3981     case CJUMP:
3982     case SJUMP:
3983       SysPrintf("Jump in the delay slot.  This is probably a bug.\n");
3984   }
3985   is_delayslot=0;
3986 }
3987
3988 // Is the branch target a valid internal jump?
3989 static int internal_branch(int addr)
3990 {
3991   if(addr&1) return 0; // Indirect (register) jump
3992   if(addr>=start && addr<start+slen*4-4)
3993   {
3994     return 1;
3995   }
3996   return 0;
3997 }
3998
3999 static void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t u)
4000 {
4001   int hr;
4002   for(hr=0;hr<HOST_REGS;hr++) {
4003     if(hr!=EXCLUDE_REG) {
4004       if(pre[hr]!=entry[hr]) {
4005         if(pre[hr]>=0) {
4006           if((dirty>>hr)&1) {
4007             if(get_reg(entry,pre[hr])<0) {
4008               assert(pre[hr]<64);
4009               if(!((u>>pre[hr])&1))
4010                 emit_storereg(pre[hr],hr);
4011             }
4012           }
4013         }
4014       }
4015     }
4016   }
4017   // Move from one register to another (no writeback)
4018   for(hr=0;hr<HOST_REGS;hr++) {
4019     if(hr!=EXCLUDE_REG) {
4020       if(pre[hr]!=entry[hr]) {
4021         if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
4022           int nr;
4023           if((nr=get_reg(entry,pre[hr]))>=0) {
4024             emit_mov(hr,nr);
4025           }
4026         }
4027       }
4028     }
4029   }
4030 }
4031
4032 // Load the specified registers
4033 // This only loads the registers given as arguments because
4034 // we don't want to load things that will be overwritten
4035 static void load_regs(signed char entry[],signed char regmap[],int rs1,int rs2)
4036 {
4037   int hr;
4038   // Load 32-bit regs
4039   for(hr=0;hr<HOST_REGS;hr++) {
4040     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4041       if(entry[hr]!=regmap[hr]) {
4042         if(regmap[hr]==rs1||regmap[hr]==rs2)
4043         {
4044           if(regmap[hr]==0) {
4045             emit_zeroreg(hr);
4046           }
4047           else
4048           {
4049             emit_loadreg(regmap[hr],hr);
4050           }
4051         }
4052       }
4053     }
4054   }
4055 }
4056
4057 // Load registers prior to the start of a loop
4058 // so that they are not loaded within the loop
4059 static void loop_preload(signed char pre[],signed char entry[])
4060 {
4061   int hr;
4062   for(hr=0;hr<HOST_REGS;hr++) {
4063     if(hr!=EXCLUDE_REG) {
4064       if(pre[hr]!=entry[hr]) {
4065         if(entry[hr]>=0) {
4066           if(get_reg(pre,entry[hr])<0) {
4067             assem_debug("loop preload:\n");
4068             //printf("loop preload: %d\n",hr);
4069             if(entry[hr]==0) {
4070               emit_zeroreg(hr);
4071             }
4072             else if(entry[hr]<TEMPREG)
4073             {
4074               emit_loadreg(entry[hr],hr);
4075             }
4076             else if(entry[hr]-64<TEMPREG)
4077             {
4078               emit_loadreg(entry[hr],hr);
4079             }
4080           }
4081         }
4082       }
4083     }
4084   }
4085 }
4086
4087 // Generate address for load/store instruction
4088 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
4089 void address_generation(int i,struct regstat *i_regs,signed char entry[])
4090 {
4091   if(dops[i].itype==LOAD||dops[i].itype==LOADLR||dops[i].itype==STORE||dops[i].itype==STORELR||dops[i].itype==C1LS||dops[i].itype==C2LS) {
4092     int ra=-1;
4093     int agr=AGEN1+(i&1);
4094     if(dops[i].itype==LOAD) {
4095       ra=get_reg(i_regs->regmap,dops[i].rt1);
4096       if(ra<0) ra=get_reg(i_regs->regmap,-1);
4097       assert(ra>=0);
4098     }
4099     if(dops[i].itype==LOADLR) {
4100       ra=get_reg(i_regs->regmap,FTEMP);
4101     }
4102     if(dops[i].itype==STORE||dops[i].itype==STORELR) {
4103       ra=get_reg(i_regs->regmap,agr);
4104       if(ra<0) ra=get_reg(i_regs->regmap,-1);
4105     }
4106     if(dops[i].itype==C1LS||dops[i].itype==C2LS) {
4107       if ((dops[i].opcode&0x3b)==0x31||(dops[i].opcode&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
4108         ra=get_reg(i_regs->regmap,FTEMP);
4109       else { // SWC1/SDC1/SWC2/SDC2
4110         ra=get_reg(i_regs->regmap,agr);
4111         if(ra<0) ra=get_reg(i_regs->regmap,-1);
4112       }
4113     }
4114     int rs=get_reg(i_regs->regmap,dops[i].rs1);
4115     if(ra>=0) {
4116       int offset=imm[i];
4117       int c=(i_regs->wasconst>>rs)&1;
4118       if(dops[i].rs1==0) {
4119         // Using r0 as a base address
4120         if(!entry||entry[ra]!=agr) {
4121           if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
4122             emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4123           }else if (dops[i].opcode==0x1a||dops[i].opcode==0x1b) {
4124             emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4125           }else{
4126             emit_movimm(offset,ra);
4127           }
4128         } // else did it in the previous cycle
4129       }
4130       else if(rs<0) {
4131         if(!entry||entry[ra]!=dops[i].rs1)
4132           emit_loadreg(dops[i].rs1,ra);
4133         //if(!entry||entry[ra]!=dops[i].rs1)
4134         //  printf("poor load scheduling!\n");
4135       }
4136       else if(c) {
4137         if(dops[i].rs1!=dops[i].rt1||dops[i].itype!=LOAD) {
4138           if(!entry||entry[ra]!=agr) {
4139             if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
4140               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4141             }else if (dops[i].opcode==0x1a||dops[i].opcode==0x1b) {
4142               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4143             }else{
4144               emit_movimm(constmap[i][rs]+offset,ra);
4145               regs[i].loadedconst|=1<<ra;
4146             }
4147           } // else did it in the previous cycle
4148         } // else load_consts already did it
4149       }
4150       if(offset&&!c&&dops[i].rs1) {
4151         if(rs>=0) {
4152           emit_addimm(rs,offset,ra);
4153         }else{
4154           emit_addimm(ra,offset,ra);
4155         }
4156       }
4157     }
4158   }
4159   // Preload constants for next instruction
4160   if(dops[i+1].itype==LOAD||dops[i+1].itype==LOADLR||dops[i+1].itype==STORE||dops[i+1].itype==STORELR||dops[i+1].itype==C1LS||dops[i+1].itype==C2LS) {
4161     int agr,ra;
4162     // Actual address
4163     agr=AGEN1+((i+1)&1);
4164     ra=get_reg(i_regs->regmap,agr);
4165     if(ra>=0) {
4166       int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
4167       int offset=imm[i+1];
4168       int c=(regs[i+1].wasconst>>rs)&1;
4169       if(c&&(dops[i+1].rs1!=dops[i+1].rt1||dops[i+1].itype!=LOAD)) {
4170         if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
4171           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4172         }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
4173           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4174         }else{
4175           emit_movimm(constmap[i+1][rs]+offset,ra);
4176           regs[i+1].loadedconst|=1<<ra;
4177         }
4178       }
4179       else if(dops[i+1].rs1==0) {
4180         // Using r0 as a base address
4181         if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
4182           emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4183         }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
4184           emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4185         }else{
4186           emit_movimm(offset,ra);
4187         }
4188       }
4189     }
4190   }
4191 }
4192
4193 static int get_final_value(int hr, int i, int *value)
4194 {
4195   int reg=regs[i].regmap[hr];
4196   while(i<slen-1) {
4197     if(regs[i+1].regmap[hr]!=reg) break;
4198     if(!((regs[i+1].isconst>>hr)&1)) break;
4199     if(dops[i+1].bt) break;
4200     i++;
4201   }
4202   if(i<slen-1) {
4203     if (dops[i].is_jump) {
4204       *value=constmap[i][hr];
4205       return 1;
4206     }
4207     if(!dops[i+1].bt) {
4208       if (dops[i+1].is_jump) {
4209         // Load in delay slot, out-of-order execution
4210         if(dops[i+2].itype==LOAD&&dops[i+2].rs1==reg&&dops[i+2].rt1==reg&&((regs[i+1].wasconst>>hr)&1))
4211         {
4212           // Precompute load address
4213           *value=constmap[i][hr]+imm[i+2];
4214           return 1;
4215         }
4216       }
4217       if(dops[i+1].itype==LOAD&&dops[i+1].rs1==reg&&dops[i+1].rt1==reg)
4218       {
4219         // Precompute load address
4220         *value=constmap[i][hr]+imm[i+1];
4221         //printf("c=%x imm=%lx\n",(long)constmap[i][hr],imm[i+1]);
4222         return 1;
4223       }
4224     }
4225   }
4226   *value=constmap[i][hr];
4227   //printf("c=%lx\n",(long)constmap[i][hr]);
4228   if(i==slen-1) return 1;
4229   assert(reg < 64);
4230   return !((unneeded_reg[i+1]>>reg)&1);
4231 }
4232
4233 // Load registers with known constants
4234 static void load_consts(signed char pre[],signed char regmap[],int i)
4235 {
4236   int hr,hr2;
4237   // propagate loaded constant flags
4238   if(i==0||dops[i].bt)
4239     regs[i].loadedconst=0;
4240   else {
4241     for(hr=0;hr<HOST_REGS;hr++) {
4242       if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((regs[i-1].isconst>>hr)&1)&&pre[hr]==regmap[hr]
4243          &&regmap[hr]==regs[i-1].regmap[hr]&&((regs[i-1].loadedconst>>hr)&1))
4244       {
4245         regs[i].loadedconst|=1<<hr;
4246       }
4247     }
4248   }
4249   // Load 32-bit regs
4250   for(hr=0;hr<HOST_REGS;hr++) {
4251     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4252       //if(entry[hr]!=regmap[hr]) {
4253       if(!((regs[i].loadedconst>>hr)&1)) {
4254         assert(regmap[hr]<64);
4255         if(((regs[i].isconst>>hr)&1)&&regmap[hr]>0) {
4256           int value,similar=0;
4257           if(get_final_value(hr,i,&value)) {
4258             // see if some other register has similar value
4259             for(hr2=0;hr2<HOST_REGS;hr2++) {
4260               if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
4261                 if(is_similar_value(value,constmap[i][hr2])) {
4262                   similar=1;
4263                   break;
4264                 }
4265               }
4266             }
4267             if(similar) {
4268               int value2;
4269               if(get_final_value(hr2,i,&value2)) // is this needed?
4270                 emit_movimm_from(value2,hr2,value,hr);
4271               else
4272                 emit_movimm(value,hr);
4273             }
4274             else if(value==0) {
4275               emit_zeroreg(hr);
4276             }
4277             else {
4278               emit_movimm(value,hr);
4279             }
4280           }
4281           regs[i].loadedconst|=1<<hr;
4282         }
4283       }
4284     }
4285   }
4286 }
4287
4288 void load_all_consts(signed char regmap[], u_int dirty, int i)
4289 {
4290   int hr;
4291   // Load 32-bit regs
4292   for(hr=0;hr<HOST_REGS;hr++) {
4293     if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4294       assert(regmap[hr] < 64);
4295       if(((regs[i].isconst>>hr)&1)&&regmap[hr]>0) {
4296         int value=constmap[i][hr];
4297         if(value==0) {
4298           emit_zeroreg(hr);
4299         }
4300         else {
4301           emit_movimm(value,hr);
4302         }
4303       }
4304     }
4305   }
4306 }
4307
4308 // Write out all dirty registers (except cycle count)
4309 static void wb_dirtys(signed char i_regmap[],uint64_t i_dirty)
4310 {
4311   int hr;
4312   for(hr=0;hr<HOST_REGS;hr++) {
4313     if(hr!=EXCLUDE_REG) {
4314       if(i_regmap[hr]>0) {
4315         if(i_regmap[hr]!=CCREG) {
4316           if((i_dirty>>hr)&1) {
4317             assert(i_regmap[hr]<64);
4318             emit_storereg(i_regmap[hr],hr);
4319           }
4320         }
4321       }
4322     }
4323   }
4324 }
4325
4326 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4327 // This writes the registers not written by store_regs_bt
4328 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_dirty,int addr)
4329 {
4330   int hr;
4331   int t=(addr-start)>>2;
4332   for(hr=0;hr<HOST_REGS;hr++) {
4333     if(hr!=EXCLUDE_REG) {
4334       if(i_regmap[hr]>0) {
4335         if(i_regmap[hr]!=CCREG) {
4336           if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1)) {
4337             if((i_dirty>>hr)&1) {
4338               assert(i_regmap[hr]<64);
4339               emit_storereg(i_regmap[hr],hr);
4340             }
4341           }
4342         }
4343       }
4344     }
4345   }
4346 }
4347
4348 // Load all registers (except cycle count)
4349 void load_all_regs(signed char i_regmap[])
4350 {
4351   int hr;
4352   for(hr=0;hr<HOST_REGS;hr++) {
4353     if(hr!=EXCLUDE_REG) {
4354       if(i_regmap[hr]==0) {
4355         emit_zeroreg(hr);
4356       }
4357       else
4358       if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4359       {
4360         emit_loadreg(i_regmap[hr],hr);
4361       }
4362     }
4363   }
4364 }
4365
4366 // Load all current registers also needed by next instruction
4367 void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4368 {
4369   int hr;
4370   for(hr=0;hr<HOST_REGS;hr++) {
4371     if(hr!=EXCLUDE_REG) {
4372       if(get_reg(next_regmap,i_regmap[hr])>=0) {
4373         if(i_regmap[hr]==0) {
4374           emit_zeroreg(hr);
4375         }
4376         else
4377         if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4378         {
4379           emit_loadreg(i_regmap[hr],hr);
4380         }
4381       }
4382     }
4383   }
4384 }
4385
4386 // Load all regs, storing cycle count if necessary
4387 void load_regs_entry(int t)
4388 {
4389   int hr;
4390   if(dops[t].is_ds) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
4391   else if(ccadj[t]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST(ccadj[t]),HOST_CCREG);
4392   if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4393     emit_storereg(CCREG,HOST_CCREG);
4394   }
4395   // Load 32-bit regs
4396   for(hr=0;hr<HOST_REGS;hr++) {
4397     if(regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
4398       if(regs[t].regmap_entry[hr]==0) {
4399         emit_zeroreg(hr);
4400       }
4401       else if(regs[t].regmap_entry[hr]!=CCREG)
4402       {
4403         emit_loadreg(regs[t].regmap_entry[hr],hr);
4404       }
4405     }
4406   }
4407 }
4408
4409 // Store dirty registers prior to branch
4410 void store_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
4411 {
4412   if(internal_branch(addr))
4413   {
4414     int t=(addr-start)>>2;
4415     int hr;
4416     for(hr=0;hr<HOST_REGS;hr++) {
4417       if(hr!=EXCLUDE_REG) {
4418         if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4419           if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1)) {
4420             if((i_dirty>>hr)&1) {
4421               assert(i_regmap[hr]<64);
4422               if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4423                 emit_storereg(i_regmap[hr],hr);
4424             }
4425           }
4426         }
4427       }
4428     }
4429   }
4430   else
4431   {
4432     // Branch out of this block, write out all dirty regs
4433     wb_dirtys(i_regmap,i_dirty);
4434   }
4435 }
4436
4437 // Load all needed registers for branch target
4438 static void load_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
4439 {
4440   //if(addr>=start && addr<(start+slen*4))
4441   if(internal_branch(addr))
4442   {
4443     int t=(addr-start)>>2;
4444     int hr;
4445     // Store the cycle count before loading something else
4446     if(i_regmap[HOST_CCREG]!=CCREG) {
4447       assert(i_regmap[HOST_CCREG]==-1);
4448     }
4449     if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4450       emit_storereg(CCREG,HOST_CCREG);
4451     }
4452     // Load 32-bit regs
4453     for(hr=0;hr<HOST_REGS;hr++) {
4454       if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
4455         if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4456           if(regs[t].regmap_entry[hr]==0) {
4457             emit_zeroreg(hr);
4458           }
4459           else if(regs[t].regmap_entry[hr]!=CCREG)
4460           {
4461             emit_loadreg(regs[t].regmap_entry[hr],hr);
4462           }
4463         }
4464       }
4465     }
4466   }
4467 }
4468
4469 static int match_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
4470 {
4471   if(addr>=start && addr<start+slen*4-4)
4472   {
4473     int t=(addr-start)>>2;
4474     int hr;
4475     if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4476     for(hr=0;hr<HOST_REGS;hr++)
4477     {
4478       if(hr!=EXCLUDE_REG)
4479       {
4480         if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4481         {
4482           if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
4483           {
4484             return 0;
4485           }
4486           else
4487           if((i_dirty>>hr)&1)
4488           {
4489             if(i_regmap[hr]<TEMPREG)
4490             {
4491               if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4492                 return 0;
4493             }
4494             else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
4495             {
4496               assert(0);
4497             }
4498           }
4499         }
4500         else // Same register but is it 32-bit or dirty?
4501         if(i_regmap[hr]>=0)
4502         {
4503           if(!((regs[t].dirty>>hr)&1))
4504           {
4505             if((i_dirty>>hr)&1)
4506             {
4507               if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4508               {
4509                 //printf("%x: dirty no match\n",addr);
4510                 return 0;
4511               }
4512             }
4513           }
4514         }
4515       }
4516     }
4517     // Delay slots are not valid branch targets
4518     //if(t>0&&(dops[t-1].is_jump) return 0;
4519     // Delay slots require additional processing, so do not match
4520     if(dops[t].is_ds) return 0;
4521   }
4522   else
4523   {
4524     int hr;
4525     for(hr=0;hr<HOST_REGS;hr++)
4526     {
4527       if(hr!=EXCLUDE_REG)
4528       {
4529         if(i_regmap[hr]>=0)
4530         {
4531           if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4532           {
4533             if((i_dirty>>hr)&1)
4534             {
4535               return 0;
4536             }
4537           }
4538         }
4539       }
4540     }
4541   }
4542   return 1;
4543 }
4544
4545 #ifdef DRC_DBG
4546 static void drc_dbg_emit_do_cmp(int i)
4547 {
4548   extern void do_insn_cmp();
4549   //extern int cycle;
4550   u_int hr, reglist = get_host_reglist(regs[i].regmap);
4551
4552   assem_debug("//do_insn_cmp %08x\n", start+i*4);
4553   save_regs(reglist);
4554   // write out changed consts to match the interpreter
4555   if (i > 0 && !dops[i].bt) {
4556     for (hr = 0; hr < HOST_REGS; hr++) {
4557       int reg = regs[i-1].regmap[hr];
4558       if (hr == EXCLUDE_REG || reg < 0)
4559         continue;
4560       if (!((regs[i-1].isconst >> hr) & 1))
4561         continue;
4562       if (i > 1 && reg == regs[i-2].regmap[hr] && constmap[i-1][hr] == constmap[i-2][hr])
4563         continue;
4564       emit_movimm(constmap[i-1][hr],0);
4565       emit_storereg(reg, 0);
4566     }
4567   }
4568   emit_movimm(start+i*4,0);
4569   emit_writeword(0,&pcaddr);
4570   emit_far_call(do_insn_cmp);
4571   //emit_readword(&cycle,0);
4572   //emit_addimm(0,2,0);
4573   //emit_writeword(0,&cycle);
4574   (void)get_reg2;
4575   restore_regs(reglist);
4576   assem_debug("\\\\do_insn_cmp\n");
4577 }
4578 #else
4579 #define drc_dbg_emit_do_cmp(x)
4580 #endif
4581
4582 // Used when a branch jumps into the delay slot of another branch
4583 static void ds_assemble_entry(int i)
4584 {
4585   int t=(ba[i]-start)>>2;
4586   if (!instr_addr[t])
4587     instr_addr[t] = out;
4588   assem_debug("Assemble delay slot at %x\n",ba[i]);
4589   assem_debug("<->\n");
4590   drc_dbg_emit_do_cmp(t);
4591   if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
4592     wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty);
4593   load_regs(regs[t].regmap_entry,regs[t].regmap,dops[t].rs1,dops[t].rs2);
4594   address_generation(t,&regs[t],regs[t].regmap_entry);
4595   if(dops[t].itype==STORE||dops[t].itype==STORELR||(dops[t].opcode&0x3b)==0x39||(dops[t].opcode&0x3b)==0x3a)
4596     load_regs(regs[t].regmap_entry,regs[t].regmap,INVCP,INVCP);
4597   is_delayslot=0;
4598   switch(dops[t].itype) {
4599     case ALU:
4600       alu_assemble(t,&regs[t]);break;
4601     case IMM16:
4602       imm16_assemble(t,&regs[t]);break;
4603     case SHIFT:
4604       shift_assemble(t,&regs[t]);break;
4605     case SHIFTIMM:
4606       shiftimm_assemble(t,&regs[t]);break;
4607     case LOAD:
4608       load_assemble(t,&regs[t]);break;
4609     case LOADLR:
4610       loadlr_assemble(t,&regs[t]);break;
4611     case STORE:
4612       store_assemble(t,&regs[t]);break;
4613     case STORELR:
4614       storelr_assemble(t,&regs[t]);break;
4615     case COP0:
4616       cop0_assemble(t,&regs[t]);break;
4617     case COP1:
4618       cop1_assemble(t,&regs[t]);break;
4619     case C1LS:
4620       c1ls_assemble(t,&regs[t]);break;
4621     case COP2:
4622       cop2_assemble(t,&regs[t]);break;
4623     case C2LS:
4624       c2ls_assemble(t,&regs[t]);break;
4625     case C2OP:
4626       c2op_assemble(t,&regs[t]);break;
4627     case MULTDIV:
4628       multdiv_assemble(t,&regs[t]);
4629       multdiv_prepare_stall(i,&regs[t]);
4630       break;
4631     case MOV:
4632       mov_assemble(t,&regs[t]);break;
4633     case SYSCALL:
4634     case HLECALL:
4635     case INTCALL:
4636     case SPAN:
4637     case UJUMP:
4638     case RJUMP:
4639     case CJUMP:
4640     case SJUMP:
4641       SysPrintf("Jump in the delay slot.  This is probably a bug.\n");
4642   }
4643   store_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4);
4644   load_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4);
4645   if(internal_branch(ba[i]+4))
4646     assem_debug("branch: internal\n");
4647   else
4648     assem_debug("branch: external\n");
4649   assert(internal_branch(ba[i]+4));
4650   add_to_linker(out,ba[i]+4,internal_branch(ba[i]+4));
4651   emit_jmp(0);
4652 }
4653
4654 static void emit_extjump(void *addr, u_int target)
4655 {
4656   emit_extjump2(addr, target, dyna_linker);
4657 }
4658
4659 static void emit_extjump_ds(void *addr, u_int target)
4660 {
4661   emit_extjump2(addr, target, dyna_linker_ds);
4662 }
4663
4664 // Load 2 immediates optimizing for small code size
4665 static void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
4666 {
4667   emit_movimm(imm1,rt1);
4668   emit_movimm_from(imm1,rt1,imm2,rt2);
4669 }
4670
4671 void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4672 {
4673   int count;
4674   void *jaddr;
4675   void *idle=NULL;
4676   int t=0;
4677   if(dops[i].itype==RJUMP)
4678   {
4679     *adj=0;
4680   }
4681   //if(ba[i]>=start && ba[i]<(start+slen*4))
4682   if(internal_branch(ba[i]))
4683   {
4684     t=(ba[i]-start)>>2;
4685     if(dops[t].is_ds) *adj=-1; // Branch into delay slot adds an extra cycle
4686     else *adj=ccadj[t];
4687   }
4688   else
4689   {
4690     *adj=0;
4691   }
4692   count=ccadj[i];
4693   if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4694     // Idle loop
4695     if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4696     idle=out;
4697     //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4698     emit_andimm(HOST_CCREG,3,HOST_CCREG);
4699     jaddr=out;
4700     emit_jmp(0);
4701   }
4702   else if(*adj==0||invert) {
4703     int cycles=CLOCK_ADJUST(count+2);
4704     // faster loop HACK
4705 #if 0
4706     if (t&&*adj) {
4707       int rel=t-i;
4708       if(-NO_CYCLE_PENALTY_THR<rel&&rel<0)
4709         cycles=CLOCK_ADJUST(*adj)+count+2-*adj;
4710     }
4711 #endif
4712     emit_addimm_and_set_flags(cycles,HOST_CCREG);
4713     jaddr=out;
4714     emit_jns(0);
4715   }
4716   else
4717   {
4718     emit_cmpimm(HOST_CCREG,-CLOCK_ADJUST(count+2));
4719     jaddr=out;
4720     emit_jns(0);
4721   }
4722   add_stub(CC_STUB,jaddr,idle?idle:out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4723 }
4724
4725 static void do_ccstub(int n)
4726 {
4727   literal_pool(256);
4728   assem_debug("do_ccstub %x\n",start+(u_int)stubs[n].b*4);
4729   set_jump_target(stubs[n].addr, out);
4730   int i=stubs[n].b;
4731   if(stubs[n].d==NULLDS) {
4732     // Delay slot instruction is nullified ("likely" branch)
4733     wb_dirtys(regs[i].regmap,regs[i].dirty);
4734   }
4735   else if(stubs[n].d!=TAKEN) {
4736     wb_dirtys(branch_regs[i].regmap,branch_regs[i].dirty);
4737   }
4738   else {
4739     if(internal_branch(ba[i]))
4740       wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
4741   }
4742   if(stubs[n].c!=-1)
4743   {
4744     // Save PC as return address
4745     emit_movimm(stubs[n].c,EAX);
4746     emit_writeword(EAX,&pcaddr);
4747   }
4748   else
4749   {
4750     // Return address depends on which way the branch goes
4751     if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
4752     {
4753       int s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
4754       int s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
4755       if(dops[i].rs1==0)
4756       {
4757         s1l=s2l;
4758         s2l=-1;
4759       }
4760       else if(dops[i].rs2==0)
4761       {
4762         s2l=-1;
4763       }
4764       assert(s1l>=0);
4765       #ifdef DESTRUCTIVE_WRITEBACK
4766       if(dops[i].rs1) {
4767         if((branch_regs[i].dirty>>s1l)&&1)
4768           emit_loadreg(dops[i].rs1,s1l);
4769       }
4770       else {
4771         if((branch_regs[i].dirty>>s1l)&1)
4772           emit_loadreg(dops[i].rs2,s1l);
4773       }
4774       if(s2l>=0)
4775         if((branch_regs[i].dirty>>s2l)&1)
4776           emit_loadreg(dops[i].rs2,s2l);
4777       #endif
4778       int hr=0;
4779       int addr=-1,alt=-1,ntaddr=-1;
4780       while(hr<HOST_REGS)
4781       {
4782         if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4783            (branch_regs[i].regmap[hr]&63)!=dops[i].rs1 &&
4784            (branch_regs[i].regmap[hr]&63)!=dops[i].rs2 )
4785         {
4786           addr=hr++;break;
4787         }
4788         hr++;
4789       }
4790       while(hr<HOST_REGS)
4791       {
4792         if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4793            (branch_regs[i].regmap[hr]&63)!=dops[i].rs1 &&
4794            (branch_regs[i].regmap[hr]&63)!=dops[i].rs2 )
4795         {
4796           alt=hr++;break;
4797         }
4798         hr++;
4799       }
4800       if((dops[i].opcode&0x2E)==6) // BLEZ/BGTZ needs another register
4801       {
4802         while(hr<HOST_REGS)
4803         {
4804           if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4805              (branch_regs[i].regmap[hr]&63)!=dops[i].rs1 &&
4806              (branch_regs[i].regmap[hr]&63)!=dops[i].rs2 )
4807           {
4808             ntaddr=hr;break;
4809           }
4810           hr++;
4811         }
4812         assert(hr<HOST_REGS);
4813       }
4814       if((dops[i].opcode&0x2f)==4) // BEQ
4815       {
4816         #ifdef HAVE_CMOV_IMM
4817         if(s2l>=0) emit_cmp(s1l,s2l);
4818         else emit_test(s1l,s1l);
4819         emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
4820         #else
4821         emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4822         if(s2l>=0) emit_cmp(s1l,s2l);
4823         else emit_test(s1l,s1l);
4824         emit_cmovne_reg(alt,addr);
4825         #endif
4826       }
4827       if((dops[i].opcode&0x2f)==5) // BNE
4828       {
4829         #ifdef HAVE_CMOV_IMM
4830         if(s2l>=0) emit_cmp(s1l,s2l);
4831         else emit_test(s1l,s1l);
4832         emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
4833         #else
4834         emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
4835         if(s2l>=0) emit_cmp(s1l,s2l);
4836         else emit_test(s1l,s1l);
4837         emit_cmovne_reg(alt,addr);
4838         #endif
4839       }
4840       if((dops[i].opcode&0x2f)==6) // BLEZ
4841       {
4842         //emit_movimm(ba[i],alt);
4843         //emit_movimm(start+i*4+8,addr);
4844         emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4845         emit_cmpimm(s1l,1);
4846         emit_cmovl_reg(alt,addr);
4847       }
4848       if((dops[i].opcode&0x2f)==7) // BGTZ
4849       {
4850         //emit_movimm(ba[i],addr);
4851         //emit_movimm(start+i*4+8,ntaddr);
4852         emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
4853         emit_cmpimm(s1l,1);
4854         emit_cmovl_reg(ntaddr,addr);
4855       }
4856       if((dops[i].opcode==1)&&(dops[i].opcode2&0x2D)==0) // BLTZ
4857       {
4858         //emit_movimm(ba[i],alt);
4859         //emit_movimm(start+i*4+8,addr);
4860         emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4861         emit_test(s1l,s1l);
4862         emit_cmovs_reg(alt,addr);
4863       }
4864       if((dops[i].opcode==1)&&(dops[i].opcode2&0x2D)==1) // BGEZ
4865       {
4866         //emit_movimm(ba[i],addr);
4867         //emit_movimm(start+i*4+8,alt);
4868         emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4869         emit_test(s1l,s1l);
4870         emit_cmovs_reg(alt,addr);
4871       }
4872       if(dops[i].opcode==0x11 && dops[i].opcode2==0x08 ) {
4873         if(source[i]&0x10000) // BC1T
4874         {
4875           //emit_movimm(ba[i],alt);
4876           //emit_movimm(start+i*4+8,addr);
4877           emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4878           emit_testimm(s1l,0x800000);
4879           emit_cmovne_reg(alt,addr);
4880         }
4881         else // BC1F
4882         {
4883           //emit_movimm(ba[i],addr);
4884           //emit_movimm(start+i*4+8,alt);
4885           emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4886           emit_testimm(s1l,0x800000);
4887           emit_cmovne_reg(alt,addr);
4888         }
4889       }
4890       emit_writeword(addr,&pcaddr);
4891     }
4892     else
4893     if(dops[i].itype==RJUMP)
4894     {
4895       int r=get_reg(branch_regs[i].regmap,dops[i].rs1);
4896       if (ds_writes_rjump_rs(i)) {
4897         r=get_reg(branch_regs[i].regmap,RTEMP);
4898       }
4899       emit_writeword(r,&pcaddr);
4900     }
4901     else {SysPrintf("Unknown branch type in do_ccstub\n");abort();}
4902   }
4903   // Update cycle count
4904   assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
4905   if(stubs[n].a) emit_addimm(HOST_CCREG,CLOCK_ADJUST((signed int)stubs[n].a),HOST_CCREG);
4906   emit_far_call(cc_interrupt);
4907   if(stubs[n].a) emit_addimm(HOST_CCREG,-CLOCK_ADJUST((signed int)stubs[n].a),HOST_CCREG);
4908   if(stubs[n].d==TAKEN) {
4909     if(internal_branch(ba[i]))
4910       load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
4911     else if(dops[i].itype==RJUMP) {
4912       if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
4913         emit_readword(&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
4914       else
4915         emit_loadreg(dops[i].rs1,get_reg(branch_regs[i].regmap,dops[i].rs1));
4916     }
4917   }else if(stubs[n].d==NOTTAKEN) {
4918     if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
4919     else load_all_regs(branch_regs[i].regmap);
4920   }else if(stubs[n].d==NULLDS) {
4921     // Delay slot instruction is nullified ("likely" branch)
4922     if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
4923     else load_all_regs(regs[i].regmap);
4924   }else{
4925     load_all_regs(branch_regs[i].regmap);
4926   }
4927   if (stubs[n].retaddr)
4928     emit_jmp(stubs[n].retaddr);
4929   else
4930     do_jump_vaddr(stubs[n].e);
4931 }
4932
4933 static void add_to_linker(void *addr, u_int target, int ext)
4934 {
4935   assert(linkcount < ARRAY_SIZE(link_addr));
4936   link_addr[linkcount].addr = addr;
4937   link_addr[linkcount].target = target;
4938   link_addr[linkcount].ext = ext;
4939   linkcount++;
4940 }
4941
4942 static void ujump_assemble_write_ra(int i)
4943 {
4944   int rt;
4945   unsigned int return_address;
4946   rt=get_reg(branch_regs[i].regmap,31);
4947   assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
4948   //assert(rt>=0);
4949   return_address=start+i*4+8;
4950   if(rt>=0) {
4951     #ifdef USE_MINI_HT
4952     if(internal_branch(return_address)&&dops[i+1].rt1!=31) {
4953       int temp=-1; // note: must be ds-safe
4954       #ifdef HOST_TEMPREG
4955       temp=HOST_TEMPREG;
4956       #endif
4957       if(temp>=0) do_miniht_insert(return_address,rt,temp);
4958       else emit_movimm(return_address,rt);
4959     }
4960     else
4961     #endif
4962     {
4963       #ifdef REG_PREFETCH
4964       if(temp>=0)
4965       {
4966         if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
4967       }
4968       #endif
4969       emit_movimm(return_address,rt); // PC into link register
4970       #ifdef IMM_PREFETCH
4971       emit_prefetch(hash_table_get(return_address));
4972       #endif
4973     }
4974   }
4975 }
4976
4977 static void ujump_assemble(int i,struct regstat *i_regs)
4978 {
4979   int ra_done=0;
4980   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
4981   address_generation(i+1,i_regs,regs[i].regmap_entry);
4982   #ifdef REG_PREFETCH
4983   int temp=get_reg(branch_regs[i].regmap,PTEMP);
4984   if(dops[i].rt1==31&&temp>=0)
4985   {
4986     signed char *i_regmap=i_regs->regmap;
4987     int return_address=start+i*4+8;
4988     if(get_reg(branch_regs[i].regmap,31)>0)
4989     if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
4990   }
4991   #endif
4992   if(dops[i].rt1==31&&(dops[i].rt1==dops[i+1].rs1||dops[i].rt1==dops[i+1].rs2)) {
4993     ujump_assemble_write_ra(i); // writeback ra for DS
4994     ra_done=1;
4995   }
4996   ds_assemble(i+1,i_regs);
4997   uint64_t bc_unneeded=branch_regs[i].u;
4998   bc_unneeded|=1|(1LL<<dops[i].rt1);
4999   wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5000   load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
5001   if(!ra_done&&dops[i].rt1==31)
5002     ujump_assemble_write_ra(i);
5003   int cc,adj;
5004   cc=get_reg(branch_regs[i].regmap,CCREG);
5005   assert(cc==HOST_CCREG);
5006   store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5007   #ifdef REG_PREFETCH
5008   if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
5009   #endif
5010   do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5011   if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5012   load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5013   if(internal_branch(ba[i]))
5014     assem_debug("branch: internal\n");
5015   else
5016     assem_debug("branch: external\n");
5017   if (internal_branch(ba[i]) && dops[(ba[i]-start)>>2].is_ds) {
5018     ds_assemble_entry(i);
5019   }
5020   else {
5021     add_to_linker(out,ba[i],internal_branch(ba[i]));
5022     emit_jmp(0);
5023   }
5024 }
5025
5026 static void rjump_assemble_write_ra(int i)
5027 {
5028   int rt,return_address;
5029   assert(dops[i+1].rt1!=dops[i].rt1);
5030   assert(dops[i+1].rt2!=dops[i].rt1);
5031   rt=get_reg(branch_regs[i].regmap,dops[i].rt1);
5032   assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5033   assert(rt>=0);
5034   return_address=start+i*4+8;
5035   #ifdef REG_PREFETCH
5036   if(temp>=0)
5037   {
5038     if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5039   }
5040   #endif
5041   emit_movimm(return_address,rt); // PC into link register
5042   #ifdef IMM_PREFETCH
5043   emit_prefetch(hash_table_get(return_address));
5044   #endif
5045 }
5046
5047 static void rjump_assemble(int i,struct regstat *i_regs)
5048 {
5049   int temp;
5050   int rs,cc;
5051   int ra_done=0;
5052   rs=get_reg(branch_regs[i].regmap,dops[i].rs1);
5053   assert(rs>=0);
5054   if (ds_writes_rjump_rs(i)) {
5055     // Delay slot abuse, make a copy of the branch address register
5056     temp=get_reg(branch_regs[i].regmap,RTEMP);
5057     assert(temp>=0);
5058     assert(regs[i].regmap[temp]==RTEMP);
5059     emit_mov(rs,temp);
5060     rs=temp;
5061   }
5062   address_generation(i+1,i_regs,regs[i].regmap_entry);
5063   #ifdef REG_PREFETCH
5064   if(dops[i].rt1==31)
5065   {
5066     if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5067       signed char *i_regmap=i_regs->regmap;
5068       int return_address=start+i*4+8;
5069       if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5070     }
5071   }
5072   #endif
5073   #ifdef USE_MINI_HT
5074   if(dops[i].rs1==31) {
5075     int rh=get_reg(regs[i].regmap,RHASH);
5076     if(rh>=0) do_preload_rhash(rh);
5077   }
5078   #endif
5079   if(dops[i].rt1!=0&&(dops[i].rt1==dops[i+1].rs1||dops[i].rt1==dops[i+1].rs2)) {
5080     rjump_assemble_write_ra(i);
5081     ra_done=1;
5082   }
5083   ds_assemble(i+1,i_regs);
5084   uint64_t bc_unneeded=branch_regs[i].u;
5085   bc_unneeded|=1|(1LL<<dops[i].rt1);
5086   bc_unneeded&=~(1LL<<dops[i].rs1);
5087   wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5088   load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,CCREG);
5089   if(!ra_done&&dops[i].rt1!=0)
5090     rjump_assemble_write_ra(i);
5091   cc=get_reg(branch_regs[i].regmap,CCREG);
5092   assert(cc==HOST_CCREG);
5093   (void)cc;
5094   #ifdef USE_MINI_HT
5095   int rh=get_reg(branch_regs[i].regmap,RHASH);
5096   int ht=get_reg(branch_regs[i].regmap,RHTBL);
5097   if(dops[i].rs1==31) {
5098     if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5099     do_preload_rhtbl(ht);
5100     do_rhash(rs,rh);
5101   }
5102   #endif
5103   store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
5104   #ifdef DESTRUCTIVE_WRITEBACK
5105   if((branch_regs[i].dirty>>rs)&1) {
5106     if(dops[i].rs1!=dops[i+1].rt1&&dops[i].rs1!=dops[i+1].rt2) {
5107       emit_loadreg(dops[i].rs1,rs);
5108     }
5109   }
5110   #endif
5111   #ifdef REG_PREFETCH
5112   if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
5113   #endif
5114   #ifdef USE_MINI_HT
5115   if(dops[i].rs1==31) {
5116     do_miniht_load(ht,rh);
5117   }
5118   #endif
5119   //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5120   //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5121   //assert(adj==0);
5122   emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5123   add_stub(CC_STUB,out,NULL,0,i,-1,TAKEN,rs);
5124   if(dops[i+1].itype==COP0&&(source[i+1]&0x3f)==0x10)
5125     // special case for RFE
5126     emit_jmp(0);
5127   else
5128     emit_jns(0);
5129   //load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
5130   #ifdef USE_MINI_HT
5131   if(dops[i].rs1==31) {
5132     do_miniht_jump(rs,rh,ht);
5133   }
5134   else
5135   #endif
5136   {
5137     do_jump_vaddr(rs);
5138   }
5139   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5140   if(dops[i].rt1!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5141   #endif
5142 }
5143
5144 static void cjump_assemble(int i,struct regstat *i_regs)
5145 {
5146   signed char *i_regmap=i_regs->regmap;
5147   int cc;
5148   int match;
5149   match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5150   assem_debug("match=%d\n",match);
5151   int s1l,s2l;
5152   int unconditional=0,nop=0;
5153   int invert=0;
5154   int internal=internal_branch(ba[i]);
5155   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5156   if(!match) invert=1;
5157   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5158   if(i>(ba[i]-start)>>2) invert=1;
5159   #endif
5160   #ifdef __aarch64__
5161   invert=1; // because of near cond. branches
5162   #endif
5163
5164   if(dops[i].ooo) {
5165     s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5166     s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
5167   }
5168   else {
5169     s1l=get_reg(i_regmap,dops[i].rs1);
5170     s2l=get_reg(i_regmap,dops[i].rs2);
5171   }
5172   if(dops[i].rs1==0&&dops[i].rs2==0)
5173   {
5174     if(dops[i].opcode&1) nop=1;
5175     else unconditional=1;
5176     //assert(dops[i].opcode!=5);
5177     //assert(dops[i].opcode!=7);
5178     //assert(dops[i].opcode!=0x15);
5179     //assert(dops[i].opcode!=0x17);
5180   }
5181   else if(dops[i].rs1==0)
5182   {
5183     s1l=s2l;
5184     s2l=-1;
5185   }
5186   else if(dops[i].rs2==0)
5187   {
5188     s2l=-1;
5189   }
5190
5191   if(dops[i].ooo) {
5192     // Out of order execution (delay slot first)
5193     //printf("OOOE\n");
5194     address_generation(i+1,i_regs,regs[i].regmap_entry);
5195     ds_assemble(i+1,i_regs);
5196     int adj;
5197     uint64_t bc_unneeded=branch_regs[i].u;
5198     bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
5199     bc_unneeded|=1;
5200     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5201     load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs2);
5202     load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
5203     cc=get_reg(branch_regs[i].regmap,CCREG);
5204     assert(cc==HOST_CCREG);
5205     if(unconditional)
5206       store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5207     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5208     //assem_debug("cycle count (adj)\n");
5209     if(unconditional) {
5210       do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5211       if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5212         if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5213         load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5214         if(internal)
5215           assem_debug("branch: internal\n");
5216         else
5217           assem_debug("branch: external\n");
5218         if (internal && dops[(ba[i]-start)>>2].is_ds) {
5219           ds_assemble_entry(i);
5220         }
5221         else {
5222           add_to_linker(out,ba[i],internal);
5223           emit_jmp(0);
5224         }
5225         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5226         if(((u_int)out)&7) emit_addnop(0);
5227         #endif
5228       }
5229     }
5230     else if(nop) {
5231       emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5232       void *jaddr=out;
5233       emit_jns(0);
5234       add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5235     }
5236     else {
5237       void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
5238       do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5239       if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5240
5241       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5242       assert(s1l>=0);
5243       if(dops[i].opcode==4) // BEQ
5244       {
5245         if(s2l>=0) emit_cmp(s1l,s2l);
5246         else emit_test(s1l,s1l);
5247         if(invert){
5248           nottaken=out;
5249           emit_jne(DJT_1);
5250         }else{
5251           add_to_linker(out,ba[i],internal);
5252           emit_jeq(0);
5253         }
5254       }
5255       if(dops[i].opcode==5) // BNE
5256       {
5257         if(s2l>=0) emit_cmp(s1l,s2l);
5258         else emit_test(s1l,s1l);
5259         if(invert){
5260           nottaken=out;
5261           emit_jeq(DJT_1);
5262         }else{
5263           add_to_linker(out,ba[i],internal);
5264           emit_jne(0);
5265         }
5266       }
5267       if(dops[i].opcode==6) // BLEZ
5268       {
5269         emit_cmpimm(s1l,1);
5270         if(invert){
5271           nottaken=out;
5272           emit_jge(DJT_1);
5273         }else{
5274           add_to_linker(out,ba[i],internal);
5275           emit_jl(0);
5276         }
5277       }
5278       if(dops[i].opcode==7) // BGTZ
5279       {
5280         emit_cmpimm(s1l,1);
5281         if(invert){
5282           nottaken=out;
5283           emit_jl(DJT_1);
5284         }else{
5285           add_to_linker(out,ba[i],internal);
5286           emit_jge(0);
5287         }
5288       }
5289       if(invert) {
5290         if(taken) set_jump_target(taken, out);
5291         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5292         if (match && (!internal || !dops[(ba[i]-start)>>2].is_ds)) {
5293           if(adj) {
5294             emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5295             add_to_linker(out,ba[i],internal);
5296           }else{
5297             emit_addnop(13);
5298             add_to_linker(out,ba[i],internal*2);
5299           }
5300           emit_jmp(0);
5301         }else
5302         #endif
5303         {
5304           if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5305           store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5306           load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5307           if(internal)
5308             assem_debug("branch: internal\n");
5309           else
5310             assem_debug("branch: external\n");
5311           if (internal && dops[(ba[i] - start) >> 2].is_ds) {
5312             ds_assemble_entry(i);
5313           }
5314           else {
5315             add_to_linker(out,ba[i],internal);
5316             emit_jmp(0);
5317           }
5318         }
5319         set_jump_target(nottaken, out);
5320       }
5321
5322       if(nottaken1) set_jump_target(nottaken1, out);
5323       if(adj) {
5324         if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
5325       }
5326     } // (!unconditional)
5327   } // if(ooo)
5328   else
5329   {
5330     // In-order execution (branch first)
5331     void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
5332     if(!unconditional&&!nop) {
5333       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5334       assert(s1l>=0);
5335       if((dops[i].opcode&0x2f)==4) // BEQ
5336       {
5337         if(s2l>=0) emit_cmp(s1l,s2l);
5338         else emit_test(s1l,s1l);
5339         nottaken=out;
5340         emit_jne(DJT_2);
5341       }
5342       if((dops[i].opcode&0x2f)==5) // BNE
5343       {
5344         if(s2l>=0) emit_cmp(s1l,s2l);
5345         else emit_test(s1l,s1l);
5346         nottaken=out;
5347         emit_jeq(DJT_2);
5348       }
5349       if((dops[i].opcode&0x2f)==6) // BLEZ
5350       {
5351         emit_cmpimm(s1l,1);
5352         nottaken=out;
5353         emit_jge(DJT_2);
5354       }
5355       if((dops[i].opcode&0x2f)==7) // BGTZ
5356       {
5357         emit_cmpimm(s1l,1);
5358         nottaken=out;
5359         emit_jl(DJT_2);
5360       }
5361     } // if(!unconditional)
5362     int adj;
5363     uint64_t ds_unneeded=branch_regs[i].u;
5364     ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
5365     ds_unneeded|=1;
5366     // branch taken
5367     if(!nop) {
5368       if(taken) set_jump_target(taken, out);
5369       assem_debug("1:\n");
5370       wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5371       // load regs
5372       load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5373       address_generation(i+1,&branch_regs[i],0);
5374       load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
5375       ds_assemble(i+1,&branch_regs[i]);
5376       cc=get_reg(branch_regs[i].regmap,CCREG);
5377       if(cc==-1) {
5378         emit_loadreg(CCREG,cc=HOST_CCREG);
5379         // CHECK: Is the following instruction (fall thru) allocated ok?
5380       }
5381       assert(cc==HOST_CCREG);
5382       store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5383       do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5384       assem_debug("cycle count (adj)\n");
5385       if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5386       load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5387       if(internal)
5388         assem_debug("branch: internal\n");
5389       else
5390         assem_debug("branch: external\n");
5391       if (internal && dops[(ba[i] - start) >> 2].is_ds) {
5392         ds_assemble_entry(i);
5393       }
5394       else {
5395         add_to_linker(out,ba[i],internal);
5396         emit_jmp(0);
5397       }
5398     }
5399     // branch not taken
5400     if(!unconditional) {
5401       if(nottaken1) set_jump_target(nottaken1, out);
5402       set_jump_target(nottaken, out);
5403       assem_debug("2:\n");
5404       wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5405       load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5406       address_generation(i+1,&branch_regs[i],0);
5407       load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
5408       ds_assemble(i+1,&branch_regs[i]);
5409       cc=get_reg(branch_regs[i].regmap,CCREG);
5410       if (cc == -1) {
5411         // Cycle count isn't in a register, temporarily load it then write it out
5412         emit_loadreg(CCREG,HOST_CCREG);
5413         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5414         void *jaddr=out;
5415         emit_jns(0);
5416         add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5417         emit_storereg(CCREG,HOST_CCREG);
5418       }
5419       else{
5420         cc=get_reg(i_regmap,CCREG);
5421         assert(cc==HOST_CCREG);
5422         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5423         void *jaddr=out;
5424         emit_jns(0);
5425         add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5426       }
5427     }
5428   }
5429 }
5430
5431 static void sjump_assemble(int i,struct regstat *i_regs)
5432 {
5433   signed char *i_regmap=i_regs->regmap;
5434   int cc;
5435   int match;
5436   match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5437   assem_debug("smatch=%d\n",match);
5438   int s1l;
5439   int unconditional=0,nevertaken=0;
5440   int invert=0;
5441   int internal=internal_branch(ba[i]);
5442   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5443   if(!match) invert=1;
5444   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5445   if(i>(ba[i]-start)>>2) invert=1;
5446   #endif
5447   #ifdef __aarch64__
5448   invert=1; // because of near cond. branches
5449   #endif
5450
5451   //if(dops[i].opcode2>=0x10) return; // FIXME (BxxZAL)
5452   //assert(dops[i].opcode2<0x10||dops[i].rs1==0); // FIXME (BxxZAL)
5453
5454   if(dops[i].ooo) {
5455     s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5456   }
5457   else {
5458     s1l=get_reg(i_regmap,dops[i].rs1);
5459   }
5460   if(dops[i].rs1==0)
5461   {
5462     if(dops[i].opcode2&1) unconditional=1;
5463     else nevertaken=1;
5464     // These are never taken (r0 is never less than zero)
5465     //assert(dops[i].opcode2!=0);
5466     //assert(dops[i].opcode2!=2);
5467     //assert(dops[i].opcode2!=0x10);
5468     //assert(dops[i].opcode2!=0x12);
5469   }
5470
5471   if(dops[i].ooo) {
5472     // Out of order execution (delay slot first)
5473     //printf("OOOE\n");
5474     address_generation(i+1,i_regs,regs[i].regmap_entry);
5475     ds_assemble(i+1,i_regs);
5476     int adj;
5477     uint64_t bc_unneeded=branch_regs[i].u;
5478     bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
5479     bc_unneeded|=1;
5480     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5481     load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs1);
5482     load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
5483     if(dops[i].rt1==31) {
5484       int rt,return_address;
5485       rt=get_reg(branch_regs[i].regmap,31);
5486       assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5487       if(rt>=0) {
5488         // Save the PC even if the branch is not taken
5489         return_address=start+i*4+8;
5490         emit_movimm(return_address,rt); // PC into link register
5491         #ifdef IMM_PREFETCH
5492         if(!nevertaken) emit_prefetch(hash_table_get(return_address));
5493         #endif
5494       }
5495     }
5496     cc=get_reg(branch_regs[i].regmap,CCREG);
5497     assert(cc==HOST_CCREG);
5498     if(unconditional)
5499       store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5500     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5501     assem_debug("cycle count (adj)\n");
5502     if(unconditional) {
5503       do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5504       if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5505         if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5506         load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5507         if(internal)
5508           assem_debug("branch: internal\n");
5509         else
5510           assem_debug("branch: external\n");
5511         if (internal && dops[(ba[i] - start) >> 2].is_ds) {
5512           ds_assemble_entry(i);
5513         }
5514         else {
5515           add_to_linker(out,ba[i],internal);
5516           emit_jmp(0);
5517         }
5518         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5519         if(((u_int)out)&7) emit_addnop(0);
5520         #endif
5521       }
5522     }
5523     else if(nevertaken) {
5524       emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5525       void *jaddr=out;
5526       emit_jns(0);
5527       add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5528     }
5529     else {
5530       void *nottaken = NULL;
5531       do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5532       if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5533       {
5534         assert(s1l>=0);
5535         if((dops[i].opcode2&0xf)==0) // BLTZ/BLTZAL
5536         {
5537           emit_test(s1l,s1l);
5538           if(invert){
5539             nottaken=out;
5540             emit_jns(DJT_1);
5541           }else{
5542             add_to_linker(out,ba[i],internal);
5543             emit_js(0);
5544           }
5545         }
5546         if((dops[i].opcode2&0xf)==1) // BGEZ/BLTZAL
5547         {
5548           emit_test(s1l,s1l);
5549           if(invert){
5550             nottaken=out;
5551             emit_js(DJT_1);
5552           }else{
5553             add_to_linker(out,ba[i],internal);
5554             emit_jns(0);
5555           }
5556         }
5557       }
5558
5559       if(invert) {
5560         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5561         if (match && (!internal || !dops[(ba[i] - start) >> 2].is_ds)) {
5562           if(adj) {
5563             emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5564             add_to_linker(out,ba[i],internal);
5565           }else{
5566             emit_addnop(13);
5567             add_to_linker(out,ba[i],internal*2);
5568           }
5569           emit_jmp(0);
5570         }else
5571         #endif
5572         {
5573           if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5574           store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5575           load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5576           if(internal)
5577             assem_debug("branch: internal\n");
5578           else
5579             assem_debug("branch: external\n");
5580           if (internal && dops[(ba[i] - start) >> 2].is_ds) {
5581             ds_assemble_entry(i);
5582           }
5583           else {
5584             add_to_linker(out,ba[i],internal);
5585             emit_jmp(0);
5586           }
5587         }
5588         set_jump_target(nottaken, out);
5589       }
5590
5591       if(adj) {
5592         if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
5593       }
5594     } // (!unconditional)
5595   } // if(ooo)
5596   else
5597   {
5598     // In-order execution (branch first)
5599     //printf("IOE\n");
5600     void *nottaken = NULL;
5601     if(dops[i].rt1==31) {
5602       int rt,return_address;
5603       rt=get_reg(branch_regs[i].regmap,31);
5604       if(rt>=0) {
5605         // Save the PC even if the branch is not taken
5606         return_address=start+i*4+8;
5607         emit_movimm(return_address,rt); // PC into link register
5608         #ifdef IMM_PREFETCH
5609         emit_prefetch(hash_table_get(return_address));
5610         #endif
5611       }
5612     }
5613     if(!unconditional) {
5614       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5615         assert(s1l>=0);
5616         if((dops[i].opcode2&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
5617         {
5618           emit_test(s1l,s1l);
5619           nottaken=out;
5620           emit_jns(DJT_1);
5621         }
5622         if((dops[i].opcode2&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
5623         {
5624           emit_test(s1l,s1l);
5625           nottaken=out;
5626           emit_js(DJT_1);
5627         }
5628     } // if(!unconditional)
5629     int adj;
5630     uint64_t ds_unneeded=branch_regs[i].u;
5631     ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
5632     ds_unneeded|=1;
5633     // branch taken
5634     if(!nevertaken) {
5635       //assem_debug("1:\n");
5636       wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5637       // load regs
5638       load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5639       address_generation(i+1,&branch_regs[i],0);
5640       load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
5641       ds_assemble(i+1,&branch_regs[i]);
5642       cc=get_reg(branch_regs[i].regmap,CCREG);
5643       if(cc==-1) {
5644         emit_loadreg(CCREG,cc=HOST_CCREG);
5645         // CHECK: Is the following instruction (fall thru) allocated ok?
5646       }
5647       assert(cc==HOST_CCREG);
5648       store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5649       do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5650       assem_debug("cycle count (adj)\n");
5651       if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5652       load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5653       if(internal)
5654         assem_debug("branch: internal\n");
5655       else
5656         assem_debug("branch: external\n");
5657       if (internal && dops[(ba[i] - start) >> 2].is_ds) {
5658         ds_assemble_entry(i);
5659       }
5660       else {
5661         add_to_linker(out,ba[i],internal);
5662         emit_jmp(0);
5663       }
5664     }
5665     // branch not taken
5666     if(!unconditional) {
5667       set_jump_target(nottaken, out);
5668       assem_debug("1:\n");
5669       wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5670       load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5671       address_generation(i+1,&branch_regs[i],0);
5672       load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
5673       ds_assemble(i+1,&branch_regs[i]);
5674       cc=get_reg(branch_regs[i].regmap,CCREG);
5675       if (cc == -1) {
5676         // Cycle count isn't in a register, temporarily load it then write it out
5677         emit_loadreg(CCREG,HOST_CCREG);
5678         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5679         void *jaddr=out;
5680         emit_jns(0);
5681         add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5682         emit_storereg(CCREG,HOST_CCREG);
5683       }
5684       else{
5685         cc=get_reg(i_regmap,CCREG);
5686         assert(cc==HOST_CCREG);
5687         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5688         void *jaddr=out;
5689         emit_jns(0);
5690         add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5691       }
5692     }
5693   }
5694 }
5695
5696 static void pagespan_assemble(int i,struct regstat *i_regs)
5697 {
5698   int s1l=get_reg(i_regs->regmap,dops[i].rs1);
5699   int s2l=get_reg(i_regs->regmap,dops[i].rs2);
5700   void *taken = NULL;
5701   void *nottaken = NULL;
5702   int unconditional=0;
5703   if(dops[i].rs1==0)
5704   {
5705     s1l=s2l;
5706     s2l=-1;
5707   }
5708   else if(dops[i].rs2==0)
5709   {
5710     s2l=-1;
5711   }
5712   int hr=0;
5713   int addr=-1,alt=-1,ntaddr=-1;
5714   if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
5715   else {
5716     while(hr<HOST_REGS)
5717     {
5718       if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5719          (i_regs->regmap[hr]&63)!=dops[i].rs1 &&
5720          (i_regs->regmap[hr]&63)!=dops[i].rs2 )
5721       {
5722         addr=hr++;break;
5723       }
5724       hr++;
5725     }
5726   }
5727   while(hr<HOST_REGS)
5728   {
5729     if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
5730        (i_regs->regmap[hr]&63)!=dops[i].rs1 &&
5731        (i_regs->regmap[hr]&63)!=dops[i].rs2 )
5732     {
5733       alt=hr++;break;
5734     }
5735     hr++;
5736   }
5737   if((dops[i].opcode&0x2E)==6) // BLEZ/BGTZ needs another register
5738   {
5739     while(hr<HOST_REGS)
5740     {
5741       if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
5742          (i_regs->regmap[hr]&63)!=dops[i].rs1 &&
5743          (i_regs->regmap[hr]&63)!=dops[i].rs2 )
5744       {
5745         ntaddr=hr;break;
5746       }
5747       hr++;
5748     }
5749   }
5750   assert(hr<HOST_REGS);
5751   if((dops[i].opcode&0x2e)==4||dops[i].opcode==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
5752     load_regs(regs[i].regmap_entry,regs[i].regmap,CCREG,CCREG);
5753   }
5754   emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5755   if(dops[i].opcode==2) // J
5756   {
5757     unconditional=1;
5758   }
5759   if(dops[i].opcode==3) // JAL
5760   {
5761     // TODO: mini_ht
5762     int rt=get_reg(i_regs->regmap,31);
5763     emit_movimm(start+i*4+8,rt);
5764     unconditional=1;
5765   }
5766   if(dops[i].opcode==0&&(dops[i].opcode2&0x3E)==8) // JR/JALR
5767   {
5768     emit_mov(s1l,addr);
5769     if(dops[i].opcode2==9) // JALR
5770     {
5771       int rt=get_reg(i_regs->regmap,dops[i].rt1);
5772       emit_movimm(start+i*4+8,rt);
5773     }
5774   }
5775   if((dops[i].opcode&0x3f)==4) // BEQ
5776   {
5777     if(dops[i].rs1==dops[i].rs2)
5778     {
5779       unconditional=1;
5780     }
5781     else
5782     #ifdef HAVE_CMOV_IMM
5783     if(1) {
5784       if(s2l>=0) emit_cmp(s1l,s2l);
5785       else emit_test(s1l,s1l);
5786       emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5787     }
5788     else
5789     #endif
5790     {
5791       assert(s1l>=0);
5792       emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5793       if(s2l>=0) emit_cmp(s1l,s2l);
5794       else emit_test(s1l,s1l);
5795       emit_cmovne_reg(alt,addr);
5796     }
5797   }
5798   if((dops[i].opcode&0x3f)==5) // BNE
5799   {
5800     #ifdef HAVE_CMOV_IMM
5801     if(s2l>=0) emit_cmp(s1l,s2l);
5802     else emit_test(s1l,s1l);
5803     emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5804     #else
5805     assert(s1l>=0);
5806     emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5807     if(s2l>=0) emit_cmp(s1l,s2l);
5808     else emit_test(s1l,s1l);
5809     emit_cmovne_reg(alt,addr);
5810     #endif
5811   }
5812   if((dops[i].opcode&0x3f)==0x14) // BEQL
5813   {
5814     if(s2l>=0) emit_cmp(s1l,s2l);
5815     else emit_test(s1l,s1l);
5816     if(nottaken) set_jump_target(nottaken, out);
5817     nottaken=out;
5818     emit_jne(0);
5819   }
5820   if((dops[i].opcode&0x3f)==0x15) // BNEL
5821   {
5822     if(s2l>=0) emit_cmp(s1l,s2l);
5823     else emit_test(s1l,s1l);
5824     nottaken=out;
5825     emit_jeq(0);
5826     if(taken) set_jump_target(taken, out);
5827   }
5828   if((dops[i].opcode&0x3f)==6) // BLEZ
5829   {
5830     emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5831     emit_cmpimm(s1l,1);
5832     emit_cmovl_reg(alt,addr);
5833   }
5834   if((dops[i].opcode&0x3f)==7) // BGTZ
5835   {
5836     emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5837     emit_cmpimm(s1l,1);
5838     emit_cmovl_reg(ntaddr,addr);
5839   }
5840   if((dops[i].opcode&0x3f)==0x16) // BLEZL
5841   {
5842     assert((dops[i].opcode&0x3f)!=0x16);
5843   }
5844   if((dops[i].opcode&0x3f)==0x17) // BGTZL
5845   {
5846     assert((dops[i].opcode&0x3f)!=0x17);
5847   }
5848   assert(dops[i].opcode!=1); // BLTZ/BGEZ
5849
5850   //FIXME: Check CSREG
5851   if(dops[i].opcode==0x11 && dops[i].opcode2==0x08 ) {
5852     if((source[i]&0x30000)==0) // BC1F
5853     {
5854       emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5855       emit_testimm(s1l,0x800000);
5856       emit_cmovne_reg(alt,addr);
5857     }
5858     if((source[i]&0x30000)==0x10000) // BC1T
5859     {
5860       emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5861       emit_testimm(s1l,0x800000);
5862       emit_cmovne_reg(alt,addr);
5863     }
5864     if((source[i]&0x30000)==0x20000) // BC1FL
5865     {
5866       emit_testimm(s1l,0x800000);
5867       nottaken=out;
5868       emit_jne(0);
5869     }
5870     if((source[i]&0x30000)==0x30000) // BC1TL
5871     {
5872       emit_testimm(s1l,0x800000);
5873       nottaken=out;
5874       emit_jeq(0);
5875     }
5876   }
5877
5878   assert(i_regs->regmap[HOST_CCREG]==CCREG);
5879   wb_dirtys(regs[i].regmap,regs[i].dirty);
5880   if(unconditional)
5881   {
5882     emit_movimm(ba[i],HOST_BTREG);
5883   }
5884   else if(addr!=HOST_BTREG)
5885   {
5886     emit_mov(addr,HOST_BTREG);
5887   }
5888   void *branch_addr=out;
5889   emit_jmp(0);
5890   int target_addr=start+i*4+5;
5891   void *stub=out;
5892   void *compiled_target_addr=check_addr(target_addr);
5893   emit_extjump_ds(branch_addr, target_addr);
5894   if(compiled_target_addr) {
5895     set_jump_target(branch_addr, compiled_target_addr);
5896     add_jump_out(target_addr,stub);
5897   }
5898   else set_jump_target(branch_addr, stub);
5899 }
5900
5901 // Assemble the delay slot for the above
5902 static void pagespan_ds()
5903 {
5904   assem_debug("initial delay slot:\n");
5905   u_int vaddr=start+1;
5906   u_int page=get_page(vaddr);
5907   u_int vpage=get_vpage(vaddr);
5908   ll_add(jump_dirty+vpage,vaddr,(void *)out);
5909   do_dirty_stub_ds(slen*4);
5910   ll_add(jump_in+page,vaddr,(void *)out);
5911   assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
5912   if(regs[0].regmap[HOST_CCREG]!=CCREG)
5913     wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty);
5914   if(regs[0].regmap[HOST_BTREG]!=BTREG)
5915     emit_writeword(HOST_BTREG,&branch_target);
5916   load_regs(regs[0].regmap_entry,regs[0].regmap,dops[0].rs1,dops[0].rs2);
5917   address_generation(0,&regs[0],regs[0].regmap_entry);
5918   if(dops[0].itype==STORE||dops[0].itype==STORELR||(dops[0].opcode&0x3b)==0x39||(dops[0].opcode&0x3b)==0x3a)
5919     load_regs(regs[0].regmap_entry,regs[0].regmap,INVCP,INVCP);
5920   is_delayslot=0;
5921   switch(dops[0].itype) {
5922     case ALU:
5923       alu_assemble(0,&regs[0]);break;
5924     case IMM16:
5925       imm16_assemble(0,&regs[0]);break;
5926     case SHIFT:
5927       shift_assemble(0,&regs[0]);break;
5928     case SHIFTIMM:
5929       shiftimm_assemble(0,&regs[0]);break;
5930     case LOAD:
5931       load_assemble(0,&regs[0]);break;
5932     case LOADLR:
5933       loadlr_assemble(0,&regs[0]);break;
5934     case STORE:
5935       store_assemble(0,&regs[0]);break;
5936     case STORELR:
5937       storelr_assemble(0,&regs[0]);break;
5938     case COP0:
5939       cop0_assemble(0,&regs[0]);break;
5940     case COP1:
5941       cop1_assemble(0,&regs[0]);break;
5942     case C1LS:
5943       c1ls_assemble(0,&regs[0]);break;
5944     case COP2:
5945       cop2_assemble(0,&regs[0]);break;
5946     case C2LS:
5947       c2ls_assemble(0,&regs[0]);break;
5948     case C2OP:
5949       c2op_assemble(0,&regs[0]);break;
5950     case MULTDIV:
5951       multdiv_assemble(0,&regs[0]);
5952       multdiv_prepare_stall(0,&regs[0]);
5953       break;
5954     case MOV:
5955       mov_assemble(0,&regs[0]);break;
5956     case SYSCALL:
5957     case HLECALL:
5958     case INTCALL:
5959     case SPAN:
5960     case UJUMP:
5961     case RJUMP:
5962     case CJUMP:
5963     case SJUMP:
5964       SysPrintf("Jump in the delay slot.  This is probably a bug.\n");
5965   }
5966   int btaddr=get_reg(regs[0].regmap,BTREG);
5967   if(btaddr<0) {
5968     btaddr=get_reg(regs[0].regmap,-1);
5969     emit_readword(&branch_target,btaddr);
5970   }
5971   assert(btaddr!=HOST_CCREG);
5972   if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
5973 #ifdef HOST_IMM8
5974   host_tempreg_acquire();
5975   emit_movimm(start+4,HOST_TEMPREG);
5976   emit_cmp(btaddr,HOST_TEMPREG);
5977   host_tempreg_release();
5978 #else
5979   emit_cmpimm(btaddr,start+4);
5980 #endif
5981   void *branch = out;
5982   emit_jeq(0);
5983   store_regs_bt(regs[0].regmap,regs[0].dirty,-1);
5984   do_jump_vaddr(btaddr);
5985   set_jump_target(branch, out);
5986   store_regs_bt(regs[0].regmap,regs[0].dirty,start+4);
5987   load_regs_bt(regs[0].regmap,regs[0].dirty,start+4);
5988 }
5989
5990 // Basic liveness analysis for MIPS registers
5991 void unneeded_registers(int istart,int iend,int r)
5992 {
5993   int i;
5994   uint64_t u,gte_u,b,gte_b;
5995   uint64_t temp_u,temp_gte_u=0;
5996   uint64_t gte_u_unknown=0;
5997   if (HACK_ENABLED(NDHACK_GTE_UNNEEDED))
5998     gte_u_unknown=~0ll;
5999   if(iend==slen-1) {
6000     u=1;
6001     gte_u=gte_u_unknown;
6002   }else{
6003     //u=unneeded_reg[iend+1];
6004     u=1;
6005     gte_u=gte_unneeded[iend+1];
6006   }
6007
6008   for (i=iend;i>=istart;i--)
6009   {
6010     //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6011     if(dops[i].is_jump)
6012     {
6013       // If subroutine call, flag return address as a possible branch target
6014       if(dops[i].rt1==31 && i<slen-2) dops[i+2].bt=1;
6015
6016       if(ba[i]<start || ba[i]>=(start+slen*4))
6017       {
6018         // Branch out of this block, flush all regs
6019         u=1;
6020         gte_u=gte_u_unknown;
6021         branch_unneeded_reg[i]=u;
6022         // Merge in delay slot
6023         u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6024         u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
6025         u|=1;
6026         gte_u|=gte_rt[i+1];
6027         gte_u&=~gte_rs[i+1];
6028       }
6029       else
6030       {
6031         // Internal branch, flag target
6032         dops[(ba[i]-start)>>2].bt=1;
6033         if(ba[i]<=start+i*4) {
6034           // Backward branch
6035           if(dops[i].is_ujump)
6036           {
6037             // Unconditional branch
6038             temp_u=1;
6039             temp_gte_u=0;
6040           } else {
6041             // Conditional branch (not taken case)
6042             temp_u=unneeded_reg[i+2];
6043             temp_gte_u&=gte_unneeded[i+2];
6044           }
6045           // Merge in delay slot
6046           temp_u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6047           temp_u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
6048           temp_u|=1;
6049           temp_gte_u|=gte_rt[i+1];
6050           temp_gte_u&=~gte_rs[i+1];
6051           temp_u|=(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2);
6052           temp_u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
6053           temp_u|=1;
6054           temp_gte_u|=gte_rt[i];
6055           temp_gte_u&=~gte_rs[i];
6056           unneeded_reg[i]=temp_u;
6057           gte_unneeded[i]=temp_gte_u;
6058           // Only go three levels deep.  This recursion can take an
6059           // excessive amount of time if there are a lot of nested loops.
6060           if(r<2) {
6061             unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6062           }else{
6063             unneeded_reg[(ba[i]-start)>>2]=1;
6064             gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown;
6065           }
6066         } /*else*/ if(1) {
6067           if (dops[i].is_ujump)
6068           {
6069             // Unconditional branch
6070             u=unneeded_reg[(ba[i]-start)>>2];
6071             gte_u=gte_unneeded[(ba[i]-start)>>2];
6072             branch_unneeded_reg[i]=u;
6073             // Merge in delay slot
6074             u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6075             u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
6076             u|=1;
6077             gte_u|=gte_rt[i+1];
6078             gte_u&=~gte_rs[i+1];
6079           } else {
6080             // Conditional branch
6081             b=unneeded_reg[(ba[i]-start)>>2];
6082             gte_b=gte_unneeded[(ba[i]-start)>>2];
6083             branch_unneeded_reg[i]=b;
6084             // Branch delay slot
6085             b|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6086             b&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
6087             b|=1;
6088             gte_b|=gte_rt[i+1];
6089             gte_b&=~gte_rs[i+1];
6090             u&=b;
6091             gte_u&=gte_b;
6092             if(i<slen-1) {
6093               branch_unneeded_reg[i]&=unneeded_reg[i+2];
6094             } else {
6095               branch_unneeded_reg[i]=1;
6096             }
6097           }
6098         }
6099       }
6100     }
6101     else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
6102     {
6103       // SYSCALL instruction (software interrupt)
6104       u=1;
6105     }
6106     else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
6107     {
6108       // ERET instruction (return from interrupt)
6109       u=1;
6110     }
6111     //u=1; // DEBUG
6112     // Written registers are unneeded
6113     u|=1LL<<dops[i].rt1;
6114     u|=1LL<<dops[i].rt2;
6115     gte_u|=gte_rt[i];
6116     // Accessed registers are needed
6117     u&=~(1LL<<dops[i].rs1);
6118     u&=~(1LL<<dops[i].rs2);
6119     gte_u&=~gte_rs[i];
6120     if(gte_rs[i]&&dops[i].rt1&&(unneeded_reg[i+1]&(1ll<<dops[i].rt1)))
6121       gte_u|=gte_rs[i]&gte_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded
6122     // Source-target dependencies
6123     // R0 is always unneeded
6124     u|=1;
6125     // Save it
6126     unneeded_reg[i]=u;
6127     gte_unneeded[i]=gte_u;
6128     /*
6129     printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6130     printf("U:");
6131     int r;
6132     for(r=1;r<=CCREG;r++) {
6133       if((unneeded_reg[i]>>r)&1) {
6134         if(r==HIREG) printf(" HI");
6135         else if(r==LOREG) printf(" LO");
6136         else printf(" r%d",r);
6137       }
6138     }
6139     printf("\n");
6140     */
6141   }
6142 }
6143
6144 // Write back dirty registers as soon as we will no longer modify them,
6145 // so that we don't end up with lots of writes at the branches.
6146 void clean_registers(int istart,int iend,int wr)
6147 {
6148   int i;
6149   int r;
6150   u_int will_dirty_i,will_dirty_next,temp_will_dirty;
6151   u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
6152   if(iend==slen-1) {
6153     will_dirty_i=will_dirty_next=0;
6154     wont_dirty_i=wont_dirty_next=0;
6155   }else{
6156     will_dirty_i=will_dirty_next=will_dirty[iend+1];
6157     wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
6158   }
6159   for (i=iend;i>=istart;i--)
6160   {
6161     if(dops[i].is_jump)
6162     {
6163       if(ba[i]<start || ba[i]>=(start+slen*4))
6164       {
6165         // Branch out of this block, flush all regs
6166         if (dops[i].is_ujump)
6167         {
6168           // Unconditional branch
6169           will_dirty_i=0;
6170           wont_dirty_i=0;
6171           // Merge in delay slot (will dirty)
6172           for(r=0;r<HOST_REGS;r++) {
6173             if(r!=EXCLUDE_REG) {
6174               if((branch_regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6175               if((branch_regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6176               if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6177               if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
6178               if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6179               if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6180               if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6181               if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6182               if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6183               if((regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6184               if((regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
6185               if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6186               if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6187               if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6188             }
6189           }
6190         }
6191         else
6192         {
6193           // Conditional branch
6194           will_dirty_i=0;
6195           wont_dirty_i=wont_dirty_next;
6196           // Merge in delay slot (will dirty)
6197           for(r=0;r<HOST_REGS;r++) {
6198             if(r!=EXCLUDE_REG) {
6199               if (1) { // !dops[i].likely) {
6200                 // Might not dirty if likely branch is not taken
6201                 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6202                 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6203                 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6204                 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
6205                 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6206                 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
6207                 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6208                 //if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6209                 //if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6210                 if((regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6211                 if((regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
6212                 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6213                 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6214                 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6215               }
6216             }
6217           }
6218         }
6219         // Merge in delay slot (wont dirty)
6220         for(r=0;r<HOST_REGS;r++) {
6221           if(r!=EXCLUDE_REG) {
6222             if((regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6223             if((regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
6224             if((regs[i].regmap[r]&63)==dops[i+1].rt1) wont_dirty_i|=1<<r;
6225             if((regs[i].regmap[r]&63)==dops[i+1].rt2) wont_dirty_i|=1<<r;
6226             if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6227             if((branch_regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6228             if((branch_regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
6229             if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) wont_dirty_i|=1<<r;
6230             if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) wont_dirty_i|=1<<r;
6231             if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6232           }
6233         }
6234         if(wr) {
6235           #ifndef DESTRUCTIVE_WRITEBACK
6236           branch_regs[i].dirty&=wont_dirty_i;
6237           #endif
6238           branch_regs[i].dirty|=will_dirty_i;
6239         }
6240       }
6241       else
6242       {
6243         // Internal branch
6244         if(ba[i]<=start+i*4) {
6245           // Backward branch
6246           if (dops[i].is_ujump)
6247           {
6248             // Unconditional branch
6249             temp_will_dirty=0;
6250             temp_wont_dirty=0;
6251             // Merge in delay slot (will dirty)
6252             for(r=0;r<HOST_REGS;r++) {
6253               if(r!=EXCLUDE_REG) {
6254                 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) temp_will_dirty|=1<<r;
6255                 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) temp_will_dirty|=1<<r;
6256                 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) temp_will_dirty|=1<<r;
6257                 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) temp_will_dirty|=1<<r;
6258                 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6259                 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6260                 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6261                 if((regs[i].regmap[r]&63)==dops[i].rt1) temp_will_dirty|=1<<r;
6262                 if((regs[i].regmap[r]&63)==dops[i].rt2) temp_will_dirty|=1<<r;
6263                 if((regs[i].regmap[r]&63)==dops[i+1].rt1) temp_will_dirty|=1<<r;
6264                 if((regs[i].regmap[r]&63)==dops[i+1].rt2) temp_will_dirty|=1<<r;
6265                 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6266                 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6267                 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6268               }
6269             }
6270           } else {
6271             // Conditional branch (not taken case)
6272             temp_will_dirty=will_dirty_next;
6273             temp_wont_dirty=wont_dirty_next;
6274             // Merge in delay slot (will dirty)
6275             for(r=0;r<HOST_REGS;r++) {
6276               if(r!=EXCLUDE_REG) {
6277                 if (1) { // !dops[i].likely) {
6278                   // Will not dirty if likely branch is not taken
6279                   if((branch_regs[i].regmap[r]&63)==dops[i].rt1) temp_will_dirty|=1<<r;
6280                   if((branch_regs[i].regmap[r]&63)==dops[i].rt2) temp_will_dirty|=1<<r;
6281                   if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) temp_will_dirty|=1<<r;
6282                   if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) temp_will_dirty|=1<<r;
6283                   if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6284                   if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
6285                   if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6286                   //if((regs[i].regmap[r]&63)==dops[i].rt1) temp_will_dirty|=1<<r;
6287                   //if((regs[i].regmap[r]&63)==dops[i].rt2) temp_will_dirty|=1<<r;
6288                   if((regs[i].regmap[r]&63)==dops[i+1].rt1) temp_will_dirty|=1<<r;
6289                   if((regs[i].regmap[r]&63)==dops[i+1].rt2) temp_will_dirty|=1<<r;
6290                   if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6291                   if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6292                   if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6293                 }
6294               }
6295             }
6296           }
6297           // Merge in delay slot (wont dirty)
6298           for(r=0;r<HOST_REGS;r++) {
6299             if(r!=EXCLUDE_REG) {
6300               if((regs[i].regmap[r]&63)==dops[i].rt1) temp_wont_dirty|=1<<r;
6301               if((regs[i].regmap[r]&63)==dops[i].rt2) temp_wont_dirty|=1<<r;
6302               if((regs[i].regmap[r]&63)==dops[i+1].rt1) temp_wont_dirty|=1<<r;
6303               if((regs[i].regmap[r]&63)==dops[i+1].rt2) temp_wont_dirty|=1<<r;
6304               if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
6305               if((branch_regs[i].regmap[r]&63)==dops[i].rt1) temp_wont_dirty|=1<<r;
6306               if((branch_regs[i].regmap[r]&63)==dops[i].rt2) temp_wont_dirty|=1<<r;
6307               if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) temp_wont_dirty|=1<<r;
6308               if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) temp_wont_dirty|=1<<r;
6309               if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
6310             }
6311           }
6312           // Deal with changed mappings
6313           if(i<iend) {
6314             for(r=0;r<HOST_REGS;r++) {
6315               if(r!=EXCLUDE_REG) {
6316                 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
6317                   temp_will_dirty&=~(1<<r);
6318                   temp_wont_dirty&=~(1<<r);
6319                   if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
6320                     temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6321                     temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6322                   } else {
6323                     temp_will_dirty|=1<<r;
6324                     temp_wont_dirty|=1<<r;
6325                   }
6326                 }
6327               }
6328             }
6329           }
6330           if(wr) {
6331             will_dirty[i]=temp_will_dirty;
6332             wont_dirty[i]=temp_wont_dirty;
6333             clean_registers((ba[i]-start)>>2,i-1,0);
6334           }else{
6335             // Limit recursion.  It can take an excessive amount
6336             // of time if there are a lot of nested loops.
6337             will_dirty[(ba[i]-start)>>2]=0;
6338             wont_dirty[(ba[i]-start)>>2]=-1;
6339           }
6340         }
6341         /*else*/ if(1)
6342         {
6343           if (dops[i].is_ujump)
6344           {
6345             // Unconditional branch
6346             will_dirty_i=0;
6347             wont_dirty_i=0;
6348           //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
6349             for(r=0;r<HOST_REGS;r++) {
6350               if(r!=EXCLUDE_REG) {
6351                 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
6352                   will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
6353                   wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
6354                 }
6355                 if(branch_regs[i].regmap[r]>=0) {
6356                   will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
6357                   wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
6358                 }
6359               }
6360             }
6361           //}
6362             // Merge in delay slot
6363             for(r=0;r<HOST_REGS;r++) {
6364               if(r!=EXCLUDE_REG) {
6365                 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6366                 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6367                 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6368                 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
6369                 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6370                 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6371                 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6372                 if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6373                 if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6374                 if((regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6375                 if((regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
6376                 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6377                 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6378                 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6379               }
6380             }
6381           } else {
6382             // Conditional branch
6383             will_dirty_i=will_dirty_next;
6384             wont_dirty_i=wont_dirty_next;
6385           //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
6386             for(r=0;r<HOST_REGS;r++) {
6387               if(r!=EXCLUDE_REG) {
6388                 signed char target_reg=branch_regs[i].regmap[r];
6389                 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
6390                   will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
6391                   wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
6392                 }
6393                 else if(target_reg>=0) {
6394                   will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
6395                   wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
6396                 }
6397               }
6398             }
6399           //}
6400             // Merge in delay slot
6401             for(r=0;r<HOST_REGS;r++) {
6402               if(r!=EXCLUDE_REG) {
6403                 if (1) { // !dops[i].likely) {
6404                   // Might not dirty if likely branch is not taken
6405                   if((branch_regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6406                   if((branch_regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6407                   if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6408                   if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
6409                   if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6410                   if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6411                   if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6412                   //if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6413                   //if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6414                   if((regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6415                   if((regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
6416                   if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6417                   if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6418                   if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6419                 }
6420               }
6421             }
6422           }
6423           // Merge in delay slot (won't dirty)
6424           for(r=0;r<HOST_REGS;r++) {
6425             if(r!=EXCLUDE_REG) {
6426               if((regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6427               if((regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
6428               if((regs[i].regmap[r]&63)==dops[i+1].rt1) wont_dirty_i|=1<<r;
6429               if((regs[i].regmap[r]&63)==dops[i+1].rt2) wont_dirty_i|=1<<r;
6430               if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6431               if((branch_regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6432               if((branch_regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
6433               if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) wont_dirty_i|=1<<r;
6434               if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) wont_dirty_i|=1<<r;
6435               if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6436             }
6437           }
6438           if(wr) {
6439             #ifndef DESTRUCTIVE_WRITEBACK
6440             branch_regs[i].dirty&=wont_dirty_i;
6441             #endif
6442             branch_regs[i].dirty|=will_dirty_i;
6443           }
6444         }
6445       }
6446     }
6447     else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
6448     {
6449       // SYSCALL instruction (software interrupt)
6450       will_dirty_i=0;
6451       wont_dirty_i=0;
6452     }
6453     else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
6454     {
6455       // ERET instruction (return from interrupt)
6456       will_dirty_i=0;
6457       wont_dirty_i=0;
6458     }
6459     will_dirty_next=will_dirty_i;
6460     wont_dirty_next=wont_dirty_i;
6461     for(r=0;r<HOST_REGS;r++) {
6462       if(r!=EXCLUDE_REG) {
6463         if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6464         if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6465         if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6466         if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6467         if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6468         if((regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6469         if((regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
6470         if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6471         if(i>istart) {
6472           if (!dops[i].is_jump)
6473           {
6474             // Don't store a register immediately after writing it,
6475             // may prevent dual-issue.
6476             if((regs[i].regmap[r]&63)==dops[i-1].rt1) wont_dirty_i|=1<<r;
6477             if((regs[i].regmap[r]&63)==dops[i-1].rt2) wont_dirty_i|=1<<r;
6478           }
6479         }
6480       }
6481     }
6482     // Save it
6483     will_dirty[i]=will_dirty_i;
6484     wont_dirty[i]=wont_dirty_i;
6485     // Mark registers that won't be dirtied as not dirty
6486     if(wr) {
6487         regs[i].dirty|=will_dirty_i;
6488         #ifndef DESTRUCTIVE_WRITEBACK
6489         regs[i].dirty&=wont_dirty_i;
6490         if(dops[i].is_jump)
6491         {
6492           if (i < iend-1 && !dops[i].is_ujump) {
6493             for(r=0;r<HOST_REGS;r++) {
6494               if(r!=EXCLUDE_REG) {
6495                 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
6496                   regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
6497                 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
6498               }
6499             }
6500           }
6501         }
6502         else
6503         {
6504           if(i<iend) {
6505             for(r=0;r<HOST_REGS;r++) {
6506               if(r!=EXCLUDE_REG) {
6507                 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
6508                   regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
6509                 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
6510               }
6511             }
6512           }
6513         }
6514         #endif
6515       //}
6516     }
6517     // Deal with changed mappings
6518     temp_will_dirty=will_dirty_i;
6519     temp_wont_dirty=wont_dirty_i;
6520     for(r=0;r<HOST_REGS;r++) {
6521       if(r!=EXCLUDE_REG) {
6522         int nr;
6523         if(regs[i].regmap[r]==regmap_pre[i][r]) {
6524           if(wr) {
6525             #ifndef DESTRUCTIVE_WRITEBACK
6526             regs[i].wasdirty&=wont_dirty_i|~(1<<r);
6527             #endif
6528             regs[i].wasdirty|=will_dirty_i&(1<<r);
6529           }
6530         }
6531         else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
6532           // Register moved to a different register
6533           will_dirty_i&=~(1<<r);
6534           wont_dirty_i&=~(1<<r);
6535           will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
6536           wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
6537           if(wr) {
6538             #ifndef DESTRUCTIVE_WRITEBACK
6539             regs[i].wasdirty&=wont_dirty_i|~(1<<r);
6540             #endif
6541             regs[i].wasdirty|=will_dirty_i&(1<<r);
6542           }
6543         }
6544         else {
6545           will_dirty_i&=~(1<<r);
6546           wont_dirty_i&=~(1<<r);
6547           if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
6548             will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6549             wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6550           } else {
6551             wont_dirty_i|=1<<r;
6552             /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);assert(!((will_dirty>>r)&1));*/
6553           }
6554         }
6555       }
6556     }
6557   }
6558 }
6559
6560 #ifdef DISASM
6561   /* disassembly */
6562 void disassemble_inst(int i)
6563 {
6564     if (dops[i].bt) printf("*"); else printf(" ");
6565     switch(dops[i].itype) {
6566       case UJUMP:
6567         printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
6568       case CJUMP:
6569         printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2,i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
6570       case SJUMP:
6571         printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
6572       case RJUMP:
6573         if (dops[i].opcode==0x9&&dops[i].rt1!=31)
6574           printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1);
6575         else
6576           printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
6577         break;
6578       case SPAN:
6579         printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2,ba[i]);break;
6580       case IMM16:
6581         if(dops[i].opcode==0xf) //LUI
6582           printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],dops[i].rt1,imm[i]&0xffff);
6583         else
6584           printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
6585         break;
6586       case LOAD:
6587       case LOADLR:
6588         printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
6589         break;
6590       case STORE:
6591       case STORELR:
6592         printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rs2,dops[i].rs1,imm[i]);
6593         break;
6594       case ALU:
6595       case SHIFT:
6596         printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,dops[i].rs2);
6597         break;
6598       case MULTDIV:
6599         printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2);
6600         break;
6601       case SHIFTIMM:
6602         printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
6603         break;
6604       case MOV:
6605         if((dops[i].opcode2&0x1d)==0x10)
6606           printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rt1);
6607         else if((dops[i].opcode2&0x1d)==0x11)
6608           printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
6609         else
6610           printf (" %x: %s\n",start+i*4,insn[i]);
6611         break;
6612       case COP0:
6613         if(dops[i].opcode2==0)
6614           printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC0
6615         else if(dops[i].opcode2==4)
6616           printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC0
6617         else printf (" %x: %s\n",start+i*4,insn[i]);
6618         break;
6619       case COP1:
6620         if(dops[i].opcode2<3)
6621           printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC1
6622         else if(dops[i].opcode2>3)
6623           printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC1
6624         else printf (" %x: %s\n",start+i*4,insn[i]);
6625         break;
6626       case COP2:
6627         if(dops[i].opcode2<3)
6628           printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC2
6629         else if(dops[i].opcode2>3)
6630           printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC2
6631         else printf (" %x: %s\n",start+i*4,insn[i]);
6632         break;
6633       case C1LS:
6634         printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,imm[i]);
6635         break;
6636       case C2LS:
6637         printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,imm[i]);
6638         break;
6639       case INTCALL:
6640         printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
6641         break;
6642       default:
6643         //printf (" %s %8x\n",insn[i],source[i]);
6644         printf (" %x: %s\n",start+i*4,insn[i]);
6645     }
6646 }
6647 #else
6648 static void disassemble_inst(int i) {}
6649 #endif // DISASM
6650
6651 #define DRC_TEST_VAL 0x74657374
6652
6653 static void new_dynarec_test(void)
6654 {
6655   int (*testfunc)(void);
6656   void *beginning;
6657   int ret[2];
6658   size_t i;
6659
6660   // check structure linkage
6661   if ((u_char *)rcnts - (u_char *)&psxRegs != sizeof(psxRegs))
6662   {
6663     SysPrintf("linkage_arm* miscompilation/breakage detected.\n");
6664   }
6665
6666   SysPrintf("testing if we can run recompiled code...\n");
6667   ((volatile u_int *)out)[0]++; // make cache dirty
6668
6669   for (i = 0; i < ARRAY_SIZE(ret); i++) {
6670     out = ndrc->translation_cache;
6671     beginning = start_block();
6672     emit_movimm(DRC_TEST_VAL + i, 0); // test
6673     emit_ret();
6674     literal_pool(0);
6675     end_block(beginning);
6676     testfunc = beginning;
6677     ret[i] = testfunc();
6678   }
6679
6680   if (ret[0] == DRC_TEST_VAL && ret[1] == DRC_TEST_VAL + 1)
6681     SysPrintf("test passed.\n");
6682   else
6683     SysPrintf("test failed, will likely crash soon (r=%08x %08x)\n", ret[0], ret[1]);
6684   out = ndrc->translation_cache;
6685 }
6686
6687 // clear the state completely, instead of just marking
6688 // things invalid like invalidate_all_pages() does
6689 void new_dynarec_clear_full(void)
6690 {
6691   int n;
6692   out = ndrc->translation_cache;
6693   memset(invalid_code,1,sizeof(invalid_code));
6694   memset(hash_table,0xff,sizeof(hash_table));
6695   memset(mini_ht,-1,sizeof(mini_ht));
6696   memset(restore_candidate,0,sizeof(restore_candidate));
6697   memset(shadow,0,sizeof(shadow));
6698   copy=shadow;
6699   expirep=16384; // Expiry pointer, +2 blocks
6700   pending_exception=0;
6701   literalcount=0;
6702   stop_after_jal=0;
6703   inv_code_start=inv_code_end=~0;
6704   f1_hack=0;
6705   // TLB
6706   for(n=0;n<4096;n++) ll_clear(jump_in+n);
6707   for(n=0;n<4096;n++) ll_clear(jump_out+n);
6708   for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
6709
6710   cycle_multiplier_old = cycle_multiplier;
6711   new_dynarec_hacks_old = new_dynarec_hacks;
6712 }
6713
6714 void new_dynarec_init(void)
6715 {
6716   SysPrintf("Init new dynarec\n");
6717
6718 #ifdef BASE_ADDR_DYNAMIC
6719   #ifdef VITA
6720   sceBlock = sceKernelAllocMemBlockForVM("code", 1 << TARGET_SIZE_2);
6721   if (sceBlock < 0)
6722     SysPrintf("sceKernelAllocMemBlockForVM failed\n");
6723   int ret = sceKernelGetMemBlockBase(sceBlock, (void **)&ndrc);
6724   if (ret < 0)
6725     SysPrintf("sceKernelGetMemBlockBase failed\n");
6726   #else
6727   uintptr_t desired_addr = 0;
6728   #ifdef __ELF__
6729   extern char _end;
6730   desired_addr = ((uintptr_t)&_end + 0xffffff) & ~0xffffffl;
6731   #endif
6732   ndrc = mmap((void *)desired_addr, sizeof(*ndrc),
6733             PROT_READ | PROT_WRITE | PROT_EXEC,
6734             MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
6735   if (ndrc == MAP_FAILED) {
6736     SysPrintf("mmap() failed: %s\n", strerror(errno));
6737     abort();
6738   }
6739   #endif
6740 #else
6741   #ifndef NO_WRITE_EXEC
6742   // not all systems allow execute in data segment by default
6743   if (mprotect(ndrc, sizeof(ndrc->translation_cache) + sizeof(ndrc->tramp.ops),
6744                PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
6745     SysPrintf("mprotect() failed: %s\n", strerror(errno));
6746   #endif
6747 #endif
6748   out = ndrc->translation_cache;
6749   cycle_multiplier=200;
6750   new_dynarec_clear_full();
6751 #ifdef HOST_IMM8
6752   // Copy this into local area so we don't have to put it in every literal pool
6753   invc_ptr=invalid_code;
6754 #endif
6755   arch_init();
6756   new_dynarec_test();
6757 #ifndef RAM_FIXED
6758   ram_offset=(uintptr_t)rdram-0x80000000;
6759 #endif
6760   if (ram_offset!=0)
6761     SysPrintf("warning: RAM is not directly mapped, performance will suffer\n");
6762 }
6763
6764 void new_dynarec_cleanup(void)
6765 {
6766   int n;
6767 #ifdef BASE_ADDR_DYNAMIC
6768   #ifdef VITA
6769   sceKernelFreeMemBlock(sceBlock);
6770   sceBlock = -1;
6771   #else
6772   if (munmap(ndrc, sizeof(*ndrc)) < 0)
6773     SysPrintf("munmap() failed\n");
6774   #endif
6775 #endif
6776   for(n=0;n<4096;n++) ll_clear(jump_in+n);
6777   for(n=0;n<4096;n++) ll_clear(jump_out+n);
6778   for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
6779   #ifdef ROM_COPY
6780   if (munmap (ROM_COPY, 67108864) < 0) {SysPrintf("munmap() failed\n");}
6781   #endif
6782 }
6783
6784 static u_int *get_source_start(u_int addr, u_int *limit)
6785 {
6786   if (!HACK_ENABLED(NDHACK_OVERRIDE_CYCLE_M))
6787     cycle_multiplier_override = 0;
6788
6789   if (addr < 0x00200000 ||
6790     (0xa0000000 <= addr && addr < 0xa0200000))
6791   {
6792     // used for BIOS calls mostly?
6793     *limit = (addr&0xa0000000)|0x00200000;
6794     return (u_int *)(rdram + (addr&0x1fffff));
6795   }
6796   else if (!Config.HLE && (
6797     /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
6798     (0xbfc00000 <= addr && addr < 0xbfc80000)))
6799   {
6800     // BIOS. The multiplier should be much higher as it's uncached 8bit mem,
6801     // but timings in PCSX are too tied to the interpreter's BIAS
6802     if (!HACK_ENABLED(NDHACK_OVERRIDE_CYCLE_M))
6803       cycle_multiplier_override = 200;
6804
6805     *limit = (addr & 0xfff00000) | 0x80000;
6806     return (u_int *)((u_char *)psxR + (addr&0x7ffff));
6807   }
6808   else if (addr >= 0x80000000 && addr < 0x80000000+RAM_SIZE) {
6809     *limit = (addr & 0x80600000) + 0x00200000;
6810     return (u_int *)(rdram + (addr&0x1fffff));
6811   }
6812   return NULL;
6813 }
6814
6815 static u_int scan_for_ret(u_int addr)
6816 {
6817   u_int limit = 0;
6818   u_int *mem;
6819
6820   mem = get_source_start(addr, &limit);
6821   if (mem == NULL)
6822     return addr;
6823
6824   if (limit > addr + 0x1000)
6825     limit = addr + 0x1000;
6826   for (; addr < limit; addr += 4, mem++) {
6827     if (*mem == 0x03e00008) // jr $ra
6828       return addr + 8;
6829   }
6830   return addr;
6831 }
6832
6833 struct savestate_block {
6834   uint32_t addr;
6835   uint32_t regflags;
6836 };
6837
6838 static int addr_cmp(const void *p1_, const void *p2_)
6839 {
6840   const struct savestate_block *p1 = p1_, *p2 = p2_;
6841   return p1->addr - p2->addr;
6842 }
6843
6844 int new_dynarec_save_blocks(void *save, int size)
6845 {
6846   struct savestate_block *blocks = save;
6847   int maxcount = size / sizeof(blocks[0]);
6848   struct savestate_block tmp_blocks[1024];
6849   struct ll_entry *head;
6850   int p, s, d, o, bcnt;
6851   u_int addr;
6852
6853   o = 0;
6854   for (p = 0; p < ARRAY_SIZE(jump_in); p++) {
6855     bcnt = 0;
6856     for (head = jump_in[p]; head != NULL; head = head->next) {
6857       tmp_blocks[bcnt].addr = head->vaddr;
6858       tmp_blocks[bcnt].regflags = head->reg_sv_flags;
6859       bcnt++;
6860     }
6861     if (bcnt < 1)
6862       continue;
6863     qsort(tmp_blocks, bcnt, sizeof(tmp_blocks[0]), addr_cmp);
6864
6865     addr = tmp_blocks[0].addr;
6866     for (s = d = 0; s < bcnt; s++) {
6867       if (tmp_blocks[s].addr < addr)
6868         continue;
6869       if (d == 0 || tmp_blocks[d-1].addr != tmp_blocks[s].addr)
6870         tmp_blocks[d++] = tmp_blocks[s];
6871       addr = scan_for_ret(tmp_blocks[s].addr);
6872     }
6873
6874     if (o + d > maxcount)
6875       d = maxcount - o;
6876     memcpy(&blocks[o], tmp_blocks, d * sizeof(blocks[0]));
6877     o += d;
6878   }
6879
6880   return o * sizeof(blocks[0]);
6881 }
6882
6883 void new_dynarec_load_blocks(const void *save, int size)
6884 {
6885   const struct savestate_block *blocks = save;
6886   int count = size / sizeof(blocks[0]);
6887   u_int regs_save[32];
6888   uint32_t f;
6889   int i, b;
6890
6891   get_addr(psxRegs.pc);
6892
6893   // change GPRs for speculation to at least partially work..
6894   memcpy(regs_save, &psxRegs.GPR, sizeof(regs_save));
6895   for (i = 1; i < 32; i++)
6896     psxRegs.GPR.r[i] = 0x80000000;
6897
6898   for (b = 0; b < count; b++) {
6899     for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) {
6900       if (f & 1)
6901         psxRegs.GPR.r[i] = 0x1f800000;
6902     }
6903
6904     get_addr(blocks[b].addr);
6905
6906     for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) {
6907       if (f & 1)
6908         psxRegs.GPR.r[i] = 0x80000000;
6909     }
6910   }
6911
6912   memcpy(&psxRegs.GPR, regs_save, sizeof(regs_save));
6913 }
6914
6915 int new_recompile_block(u_int addr)
6916 {
6917   u_int pagelimit = 0;
6918   u_int state_rflags = 0;
6919   int i;
6920
6921   assem_debug("NOTCOMPILED: addr = %x -> %p\n", addr, out);
6922   //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
6923   //if(debug)
6924   //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
6925
6926   // this is just for speculation
6927   for (i = 1; i < 32; i++) {
6928     if ((psxRegs.GPR.r[i] & 0xffff0000) == 0x1f800000)
6929       state_rflags |= 1 << i;
6930   }
6931
6932   start = (u_int)addr&~3;
6933   //assert(((u_int)addr&1)==0); // start-in-delay-slot flag
6934   new_dynarec_did_compile=1;
6935   if (Config.HLE && start == 0x80001000) // hlecall
6936   {
6937     // XXX: is this enough? Maybe check hleSoftCall?
6938     void *beginning=start_block();
6939     u_int page=get_page(start);
6940
6941     invalid_code[start>>12]=0;
6942     emit_movimm(start,0);
6943     emit_writeword(0,&pcaddr);
6944     emit_far_jump(new_dyna_leave);
6945     literal_pool(0);
6946     end_block(beginning);
6947     ll_add_flags(jump_in+page,start,state_rflags,(void *)beginning);
6948     return 0;
6949   }
6950   else if (f1_hack == ~0u || (f1_hack != 0 && start == f1_hack)) {
6951     void *beginning = start_block();
6952     u_int page = get_page(start);
6953     emit_readword(&psxRegs.GPR.n.sp, 0);
6954     emit_readptr(&mem_rtab, 1);
6955     emit_shrimm(0, 12, 2);
6956     emit_readptr_dualindexedx_ptrlen(1, 2, 1);
6957     emit_addimm(0, 0x18, 0);
6958     emit_adds_ptr(1, 1, 1);
6959     emit_ldr_dualindexed(1, 0, 0);
6960     emit_writeword(0, &psxRegs.GPR.r[26]); // lw k0, 0x18(sp)
6961     emit_far_call(get_addr_ht);
6962     emit_jmpreg(0); // jr k0
6963     literal_pool(0);
6964     end_block(beginning);
6965
6966     ll_add_flags(jump_in + page, start, state_rflags, beginning);
6967     SysPrintf("F1 hack to   %08x\n", start);
6968     f1_hack = start;
6969     return 0;
6970   }
6971
6972   source = get_source_start(start, &pagelimit);
6973   if (source == NULL) {
6974     SysPrintf("Compile at bogus memory address: %08x\n", addr);
6975     abort();
6976   }
6977
6978   /* Pass 1: disassemble */
6979   /* Pass 2: register dependencies, branch targets */
6980   /* Pass 3: register allocation */
6981   /* Pass 4: branch dependencies */
6982   /* Pass 5: pre-alloc */
6983   /* Pass 6: optimize clean/dirty state */
6984   /* Pass 7: flag 32-bit registers */
6985   /* Pass 8: assembly */
6986   /* Pass 9: linker */
6987   /* Pass 10: garbage collection / free memory */
6988
6989   int j;
6990   int done=0;
6991   unsigned int type,op,op2;
6992
6993   //printf("addr = %x source = %x %x\n", addr,source,source[0]);
6994
6995   /* Pass 1 disassembly */
6996
6997   for(i=0;!done;i++) {
6998     dops[i].bt=0;
6999     dops[i].ooo=0;
7000     op2=0;
7001     minimum_free_regs[i]=0;
7002     dops[i].opcode=op=source[i]>>26;
7003     switch(op)
7004     {
7005       case 0x00: strcpy(insn[i],"special"); type=NI;
7006         op2=source[i]&0x3f;
7007         switch(op2)
7008         {
7009           case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
7010           case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
7011           case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
7012           case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
7013           case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
7014           case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
7015           case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
7016           case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
7017           case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
7018           case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
7019           case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
7020           case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
7021           case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
7022           case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
7023           case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
7024           case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
7025           case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
7026           case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
7027           case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
7028           case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
7029           case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
7030           case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
7031           case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
7032           case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
7033           case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
7034           case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
7035           case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
7036           case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
7037           case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
7038           case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
7039           case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
7040           case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
7041           case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
7042           case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
7043           case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
7044 #if 0
7045           case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
7046           case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
7047           case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
7048           case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
7049           case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
7050           case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
7051           case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
7052           case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
7053           case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
7054           case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
7055           case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
7056           case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
7057           case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
7058           case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
7059           case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
7060           case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
7061           case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
7062 #endif
7063         }
7064         break;
7065       case 0x01: strcpy(insn[i],"regimm"); type=NI;
7066         op2=(source[i]>>16)&0x1f;
7067         switch(op2)
7068         {
7069           case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
7070           case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
7071           //case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
7072           //case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
7073           //case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
7074           //case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
7075           //case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
7076           //case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
7077           //case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
7078           //case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
7079           case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
7080           case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
7081           //case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
7082           //case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
7083         }
7084         break;
7085       case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
7086       case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
7087       case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
7088       case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
7089       case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
7090       case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
7091       case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
7092       case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
7093       case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
7094       case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
7095       case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
7096       case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
7097       case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
7098       case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
7099       case 0x10: strcpy(insn[i],"cop0"); type=NI;
7100         op2=(source[i]>>21)&0x1f;
7101         switch(op2)
7102         {
7103           case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
7104           case 0x02: strcpy(insn[i],"CFC0"); type=COP0; break;
7105           case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
7106           case 0x06: strcpy(insn[i],"CTC0"); type=COP0; break;
7107           case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
7108         }
7109         break;
7110       case 0x11: strcpy(insn[i],"cop1"); type=COP1;
7111         op2=(source[i]>>21)&0x1f;
7112         break;
7113 #if 0
7114       case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
7115       case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
7116       case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
7117       case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
7118       case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
7119       case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
7120       case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
7121       case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
7122 #endif
7123       case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
7124       case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
7125       case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
7126       case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
7127       case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
7128       case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
7129       case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
7130 #if 0
7131       case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
7132 #endif
7133       case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
7134       case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
7135       case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
7136       case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
7137 #if 0
7138       case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
7139       case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
7140 #endif
7141       case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
7142       case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
7143       case 0x30: strcpy(insn[i],"LL"); type=NI; break;
7144       case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
7145 #if 0
7146       case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
7147       case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
7148       case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
7149 #endif
7150       case 0x38: strcpy(insn[i],"SC"); type=NI; break;
7151       case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
7152 #if 0
7153       case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
7154       case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
7155       case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
7156 #endif
7157       case 0x12: strcpy(insn[i],"COP2"); type=NI;
7158         op2=(source[i]>>21)&0x1f;
7159         //if (op2 & 0x10)
7160         if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
7161           if (gte_handlers[source[i]&0x3f]!=NULL) {
7162             if (gte_regnames[source[i]&0x3f]!=NULL)
7163               strcpy(insn[i],gte_regnames[source[i]&0x3f]);
7164             else
7165               snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
7166             type=C2OP;
7167           }
7168         }
7169         else switch(op2)
7170         {
7171           case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
7172           case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
7173           case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
7174           case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
7175         }
7176         break;
7177       case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
7178       case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
7179       case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
7180       default: strcpy(insn[i],"???"); type=NI;
7181         SysPrintf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
7182         break;
7183     }
7184     dops[i].itype=type;
7185     dops[i].opcode2=op2;
7186     /* Get registers/immediates */
7187     dops[i].lt1=0;
7188     gte_rs[i]=gte_rt[i]=0;
7189     switch(type) {
7190       case LOAD:
7191         dops[i].rs1=(source[i]>>21)&0x1f;
7192         dops[i].rs2=0;
7193         dops[i].rt1=(source[i]>>16)&0x1f;
7194         dops[i].rt2=0;
7195         imm[i]=(short)source[i];
7196         break;
7197       case STORE:
7198       case STORELR:
7199         dops[i].rs1=(source[i]>>21)&0x1f;
7200         dops[i].rs2=(source[i]>>16)&0x1f;
7201         dops[i].rt1=0;
7202         dops[i].rt2=0;
7203         imm[i]=(short)source[i];
7204         break;
7205       case LOADLR:
7206         // LWL/LWR only load part of the register,
7207         // therefore the target register must be treated as a source too
7208         dops[i].rs1=(source[i]>>21)&0x1f;
7209         dops[i].rs2=(source[i]>>16)&0x1f;
7210         dops[i].rt1=(source[i]>>16)&0x1f;
7211         dops[i].rt2=0;
7212         imm[i]=(short)source[i];
7213         break;
7214       case IMM16:
7215         if (op==0x0f) dops[i].rs1=0; // LUI instruction has no source register
7216         else dops[i].rs1=(source[i]>>21)&0x1f;
7217         dops[i].rs2=0;
7218         dops[i].rt1=(source[i]>>16)&0x1f;
7219         dops[i].rt2=0;
7220         if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
7221           imm[i]=(unsigned short)source[i];
7222         }else{
7223           imm[i]=(short)source[i];
7224         }
7225         break;
7226       case UJUMP:
7227         dops[i].rs1=0;
7228         dops[i].rs2=0;
7229         dops[i].rt1=0;
7230         dops[i].rt2=0;
7231         // The JAL instruction writes to r31.
7232         if (op&1) {
7233           dops[i].rt1=31;
7234         }
7235         dops[i].rs2=CCREG;
7236         break;
7237       case RJUMP:
7238         dops[i].rs1=(source[i]>>21)&0x1f;
7239         dops[i].rs2=0;
7240         dops[i].rt1=0;
7241         dops[i].rt2=0;
7242         // The JALR instruction writes to rd.
7243         if (op2&1) {
7244           dops[i].rt1=(source[i]>>11)&0x1f;
7245         }
7246         dops[i].rs2=CCREG;
7247         break;
7248       case CJUMP:
7249         dops[i].rs1=(source[i]>>21)&0x1f;
7250         dops[i].rs2=(source[i]>>16)&0x1f;
7251         dops[i].rt1=0;
7252         dops[i].rt2=0;
7253         if(op&2) { // BGTZ/BLEZ
7254           dops[i].rs2=0;
7255         }
7256         break;
7257       case SJUMP:
7258         dops[i].rs1=(source[i]>>21)&0x1f;
7259         dops[i].rs2=CCREG;
7260         dops[i].rt1=0;
7261         dops[i].rt2=0;
7262         if(op2&0x10) { // BxxAL
7263           dops[i].rt1=31;
7264           // NOTE: If the branch is not taken, r31 is still overwritten
7265         }
7266         break;
7267       case ALU:
7268         dops[i].rs1=(source[i]>>21)&0x1f; // source
7269         dops[i].rs2=(source[i]>>16)&0x1f; // subtract amount
7270         dops[i].rt1=(source[i]>>11)&0x1f; // destination
7271         dops[i].rt2=0;
7272         break;
7273       case MULTDIV:
7274         dops[i].rs1=(source[i]>>21)&0x1f; // source
7275         dops[i].rs2=(source[i]>>16)&0x1f; // divisor
7276         dops[i].rt1=HIREG;
7277         dops[i].rt2=LOREG;
7278         break;
7279       case MOV:
7280         dops[i].rs1=0;
7281         dops[i].rs2=0;
7282         dops[i].rt1=0;
7283         dops[i].rt2=0;
7284         if(op2==0x10) dops[i].rs1=HIREG; // MFHI
7285         if(op2==0x11) dops[i].rt1=HIREG; // MTHI
7286         if(op2==0x12) dops[i].rs1=LOREG; // MFLO
7287         if(op2==0x13) dops[i].rt1=LOREG; // MTLO
7288         if((op2&0x1d)==0x10) dops[i].rt1=(source[i]>>11)&0x1f; // MFxx
7289         if((op2&0x1d)==0x11) dops[i].rs1=(source[i]>>21)&0x1f; // MTxx
7290         break;
7291       case SHIFT:
7292         dops[i].rs1=(source[i]>>16)&0x1f; // target of shift
7293         dops[i].rs2=(source[i]>>21)&0x1f; // shift amount
7294         dops[i].rt1=(source[i]>>11)&0x1f; // destination
7295         dops[i].rt2=0;
7296         break;
7297       case SHIFTIMM:
7298         dops[i].rs1=(source[i]>>16)&0x1f;
7299         dops[i].rs2=0;
7300         dops[i].rt1=(source[i]>>11)&0x1f;
7301         dops[i].rt2=0;
7302         imm[i]=(source[i]>>6)&0x1f;
7303         // DSxx32 instructions
7304         if(op2>=0x3c) imm[i]|=0x20;
7305         break;
7306       case COP0:
7307         dops[i].rs1=0;
7308         dops[i].rs2=0;
7309         dops[i].rt1=0;
7310         dops[i].rt2=0;
7311         if(op2==0||op2==2) dops[i].rt1=(source[i]>>16)&0x1F; // MFC0/CFC0
7312         if(op2==4||op2==6) dops[i].rs1=(source[i]>>16)&0x1F; // MTC0/CTC0
7313         if(op2==4&&((source[i]>>11)&0x1f)==12) dops[i].rt2=CSREG; // Status
7314         if(op2==16) if((source[i]&0x3f)==0x18) dops[i].rs2=CCREG; // ERET
7315         break;
7316       case COP1:
7317         dops[i].rs1=0;
7318         dops[i].rs2=0;
7319         dops[i].rt1=0;
7320         dops[i].rt2=0;
7321         if(op2<3) dops[i].rt1=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
7322         if(op2>3) dops[i].rs1=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
7323         dops[i].rs2=CSREG;
7324         break;
7325       case COP2:
7326         dops[i].rs1=0;
7327         dops[i].rs2=0;
7328         dops[i].rt1=0;
7329         dops[i].rt2=0;
7330         if(op2<3) dops[i].rt1=(source[i]>>16)&0x1F; // MFC2/CFC2
7331         if(op2>3) dops[i].rs1=(source[i]>>16)&0x1F; // MTC2/CTC2
7332         dops[i].rs2=CSREG;
7333         int gr=(source[i]>>11)&0x1F;
7334         switch(op2)
7335         {
7336           case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
7337           case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
7338           case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2
7339           case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
7340         }
7341         break;
7342       case C1LS:
7343         dops[i].rs1=(source[i]>>21)&0x1F;
7344         dops[i].rs2=CSREG;
7345         dops[i].rt1=0;
7346         dops[i].rt2=0;
7347         imm[i]=(short)source[i];
7348         break;
7349       case C2LS:
7350         dops[i].rs1=(source[i]>>21)&0x1F;
7351         dops[i].rs2=0;
7352         dops[i].rt1=0;
7353         dops[i].rt2=0;
7354         imm[i]=(short)source[i];
7355         if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
7356         else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
7357         break;
7358       case C2OP:
7359         dops[i].rs1=0;
7360         dops[i].rs2=0;
7361         dops[i].rt1=0;
7362         dops[i].rt2=0;
7363         gte_rs[i]=gte_reg_reads[source[i]&0x3f];
7364         gte_rt[i]=gte_reg_writes[source[i]&0x3f];
7365         gte_rt[i]|=1ll<<63; // every op changes flags
7366         if((source[i]&0x3f)==GTE_MVMVA) {
7367           int v = (source[i] >> 15) & 3;
7368           gte_rs[i]&=~0xe3fll;
7369           if(v==3) gte_rs[i]|=0xe00ll;
7370           else gte_rs[i]|=3ll<<(v*2);
7371         }
7372         break;
7373       case SYSCALL:
7374       case HLECALL:
7375       case INTCALL:
7376         dops[i].rs1=CCREG;
7377         dops[i].rs2=0;
7378         dops[i].rt1=0;
7379         dops[i].rt2=0;
7380         break;
7381       default:
7382         dops[i].rs1=0;
7383         dops[i].rs2=0;
7384         dops[i].rt1=0;
7385         dops[i].rt2=0;
7386     }
7387     /* Calculate branch target addresses */
7388     if(type==UJUMP)
7389       ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
7390     else if(type==CJUMP&&dops[i].rs1==dops[i].rs2&&(op&1))
7391       ba[i]=start+i*4+8; // Ignore never taken branch
7392     else if(type==SJUMP&&dops[i].rs1==0&&!(op2&1))
7393       ba[i]=start+i*4+8; // Ignore never taken branch
7394     else if(type==CJUMP||type==SJUMP)
7395       ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
7396     else ba[i]=-1;
7397
7398     /* simplify always (not)taken branches */
7399     if (type == CJUMP && dops[i].rs1 == dops[i].rs2) {
7400       dops[i].rs1 = dops[i].rs2 = 0;
7401       if (!(op & 1)) {
7402         dops[i].itype = type = UJUMP;
7403         dops[i].rs2 = CCREG;
7404       }
7405     }
7406     else if (type == SJUMP && dops[i].rs1 == 0 && (op2 & 1))
7407       dops[i].itype = type = UJUMP;
7408
7409     dops[i].is_jump = (dops[i].itype == RJUMP || dops[i].itype == UJUMP || dops[i].itype == CJUMP || dops[i].itype == SJUMP);
7410     dops[i].is_ujump = (dops[i].itype == RJUMP || dops[i].itype == UJUMP); // || (source[i] >> 16) == 0x1000 // beq r0,r0
7411
7412     /* messy cases to just pass over to the interpreter */
7413     if (i > 0 && dops[i-1].is_jump) {
7414       int do_in_intrp=0;
7415       // branch in delay slot?
7416       if (dops[i].is_jump) {
7417         // don't handle first branch and call interpreter if it's hit
7418         SysPrintf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
7419         do_in_intrp=1;
7420       }
7421       // basic load delay detection
7422       else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&dops[i].rt1!=0) {
7423         int t=(ba[i-1]-start)/4;
7424         if(0 <= t && t < i &&(dops[i].rt1==dops[t].rs1||dops[i].rt1==dops[t].rs2)&&dops[t].itype!=CJUMP&&dops[t].itype!=SJUMP) {
7425           // jump target wants DS result - potential load delay effect
7426           SysPrintf("load delay @%08x (%08x)\n", addr + i*4, addr);
7427           do_in_intrp=1;
7428           dops[t+1].bt=1; // expected return from interpreter
7429         }
7430         else if(i>=2&&dops[i-2].rt1==2&&dops[i].rt1==2&&dops[i].rs1!=2&&dops[i].rs2!=2&&dops[i-1].rs1!=2&&dops[i-1].rs2!=2&&
7431               !(i>=3&&dops[i-3].is_jump)) {
7432           // v0 overwrite like this is a sign of trouble, bail out
7433           SysPrintf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
7434           do_in_intrp=1;
7435         }
7436       }
7437       if(do_in_intrp) {
7438         dops[i-1].rs1=CCREG;
7439         dops[i-1].rs2=dops[i-1].rt1=dops[i-1].rt2=0;
7440         ba[i-1]=-1;
7441         dops[i-1].itype=INTCALL;
7442         done=2;
7443         i--; // don't compile the DS
7444       }
7445     }
7446
7447     /* Is this the end of the block? */
7448     if (i > 0 && dops[i-1].is_ujump) {
7449       if(dops[i-1].rt1==0) { // Continue past subroutine call (JAL)
7450         done=2;
7451       }
7452       else {
7453         if(stop_after_jal) done=1;
7454         // Stop on BREAK
7455         if((source[i+1]&0xfc00003f)==0x0d) done=1;
7456       }
7457       // Don't recompile stuff that's already compiled
7458       if(check_addr(start+i*4+4)) done=1;
7459       // Don't get too close to the limit
7460       if(i>MAXBLOCK/2) done=1;
7461     }
7462     if(dops[i].itype==SYSCALL&&stop_after_jal) done=1;
7463     if(dops[i].itype==HLECALL||dops[i].itype==INTCALL) done=2;
7464     if(done==2) {
7465       // Does the block continue due to a branch?
7466       for(j=i-1;j>=0;j--)
7467       {
7468         if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
7469         if(ba[j]==start+i*4+4) done=j=0;
7470         if(ba[j]==start+i*4+8) done=j=0;
7471       }
7472     }
7473     //assert(i<MAXBLOCK-1);
7474     if(start+i*4==pagelimit-4) done=1;
7475     assert(start+i*4<pagelimit);
7476     if (i==MAXBLOCK-1) done=1;
7477     // Stop if we're compiling junk
7478     if(dops[i].itype==NI&&dops[i].opcode==0x11) {
7479       done=stop_after_jal=1;
7480       SysPrintf("Disabled speculative precompilation\n");
7481     }
7482   }
7483   slen=i;
7484   if (dops[i-1].is_jump) {
7485     if(start+i*4==pagelimit) {
7486       dops[i-1].itype=SPAN;
7487     }
7488   }
7489   assert(slen>0);
7490
7491   /* spacial hack(s) */
7492   if (i > 10 && source[i-1] == 0 && source[i-2] == 0x03e00008
7493       && source[i-4] == 0x8fbf0018 && source[i-6] == 0x00c0f809
7494       && dops[i-7].itype == STORE)
7495   {
7496     i = i-8;
7497     if (dops[i].itype == IMM16)
7498       i--;
7499     // swl r2, 15(r6); swr r2, 12(r6); sw r6, *; jalr r6
7500     if (dops[i].itype == STORELR && dops[i].rs1 == 6
7501       && dops[i-1].itype == STORELR && dops[i-1].rs1 == 6)
7502     {
7503       SysPrintf("F1 hack from %08x\n", start);
7504       f1_hack = ~0u;
7505     }
7506   }
7507
7508   /* Pass 2 - Register dependencies and branch targets */
7509
7510   unneeded_registers(0,slen-1,0);
7511
7512   /* Pass 3 - Register allocation */
7513
7514   struct regstat current; // Current register allocations/status
7515   current.dirty=0;
7516   current.u=unneeded_reg[0];
7517   clear_all_regs(current.regmap);
7518   alloc_reg(&current,0,CCREG);
7519   dirty_reg(&current,CCREG);
7520   current.isconst=0;
7521   current.wasconst=0;
7522   current.waswritten=0;
7523   int ds=0;
7524   int cc=0;
7525   int hr=-1;
7526
7527   if((u_int)addr&1) {
7528     // First instruction is delay slot
7529     cc=-1;
7530     dops[1].bt=1;
7531     ds=1;
7532     unneeded_reg[0]=1;
7533     current.regmap[HOST_BTREG]=BTREG;
7534   }
7535
7536   for(i=0;i<slen;i++)
7537   {
7538     if(dops[i].bt)
7539     {
7540       int hr;
7541       for(hr=0;hr<HOST_REGS;hr++)
7542       {
7543         // Is this really necessary?
7544         if(current.regmap[hr]==0) current.regmap[hr]=-1;
7545       }
7546       current.isconst=0;
7547       current.waswritten=0;
7548     }
7549
7550     memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
7551     regs[i].wasconst=current.isconst;
7552     regs[i].wasdirty=current.dirty;
7553     regs[i].loadedconst=0;
7554     if (!dops[i].is_jump) {
7555       if(i+1<slen) {
7556         current.u=unneeded_reg[i+1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7557         current.u|=1;
7558       } else {
7559         current.u=1;
7560       }
7561     } else {
7562       if(i+1<slen) {
7563         current.u=branch_unneeded_reg[i]&~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7564         current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7565         current.u|=1;
7566       } else { SysPrintf("oops, branch at end of block with no delay slot\n");abort(); }
7567     }
7568     dops[i].is_ds=ds;
7569     if(ds) {
7570       ds=0; // Skip delay slot, already allocated as part of branch
7571       // ...but we need to alloc it in case something jumps here
7572       if(i+1<slen) {
7573         current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
7574       }else{
7575         current.u=branch_unneeded_reg[i-1];
7576       }
7577       current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7578       current.u|=1;
7579       struct regstat temp;
7580       memcpy(&temp,&current,sizeof(current));
7581       temp.wasdirty=temp.dirty;
7582       // TODO: Take into account unconditional branches, as below
7583       delayslot_alloc(&temp,i);
7584       memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
7585       regs[i].wasdirty=temp.wasdirty;
7586       regs[i].dirty=temp.dirty;
7587       regs[i].isconst=0;
7588       regs[i].wasconst=0;
7589       current.isconst=0;
7590       // Create entry (branch target) regmap
7591       for(hr=0;hr<HOST_REGS;hr++)
7592       {
7593         int r=temp.regmap[hr];
7594         if(r>=0) {
7595           if(r!=regmap_pre[i][hr]) {
7596             regs[i].regmap_entry[hr]=-1;
7597           }
7598           else
7599           {
7600               assert(r < 64);
7601               if((current.u>>r)&1) {
7602                 regs[i].regmap_entry[hr]=-1;
7603                 regs[i].regmap[hr]=-1;
7604                 //Don't clear regs in the delay slot as the branch might need them
7605                 //current.regmap[hr]=-1;
7606               }else
7607                 regs[i].regmap_entry[hr]=r;
7608           }
7609         } else {
7610           // First instruction expects CCREG to be allocated
7611           if(i==0&&hr==HOST_CCREG)
7612             regs[i].regmap_entry[hr]=CCREG;
7613           else
7614             regs[i].regmap_entry[hr]=-1;
7615         }
7616       }
7617     }
7618     else { // Not delay slot
7619       switch(dops[i].itype) {
7620         case UJUMP:
7621           //current.isconst=0; // DEBUG
7622           //current.wasconst=0; // DEBUG
7623           //regs[i].wasconst=0; // DEBUG
7624           clear_const(&current,dops[i].rt1);
7625           alloc_cc(&current,i);
7626           dirty_reg(&current,CCREG);
7627           if (dops[i].rt1==31) {
7628             alloc_reg(&current,i,31);
7629             dirty_reg(&current,31);
7630             //assert(dops[i+1].rs1!=31&&dops[i+1].rs2!=31);
7631             //assert(dops[i+1].rt1!=dops[i].rt1);
7632             #ifdef REG_PREFETCH
7633             alloc_reg(&current,i,PTEMP);
7634             #endif
7635           }
7636           dops[i].ooo=1;
7637           delayslot_alloc(&current,i+1);
7638           //current.isconst=0; // DEBUG
7639           ds=1;
7640           //printf("i=%d, isconst=%x\n",i,current.isconst);
7641           break;
7642         case RJUMP:
7643           //current.isconst=0;
7644           //current.wasconst=0;
7645           //regs[i].wasconst=0;
7646           clear_const(&current,dops[i].rs1);
7647           clear_const(&current,dops[i].rt1);
7648           alloc_cc(&current,i);
7649           dirty_reg(&current,CCREG);
7650           if (!ds_writes_rjump_rs(i)) {
7651             alloc_reg(&current,i,dops[i].rs1);
7652             if (dops[i].rt1!=0) {
7653               alloc_reg(&current,i,dops[i].rt1);
7654               dirty_reg(&current,dops[i].rt1);
7655               assert(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt1);
7656               assert(dops[i+1].rt1!=dops[i].rt1);
7657               #ifdef REG_PREFETCH
7658               alloc_reg(&current,i,PTEMP);
7659               #endif
7660             }
7661             #ifdef USE_MINI_HT
7662             if(dops[i].rs1==31) { // JALR
7663               alloc_reg(&current,i,RHASH);
7664               alloc_reg(&current,i,RHTBL);
7665             }
7666             #endif
7667             delayslot_alloc(&current,i+1);
7668           } else {
7669             // The delay slot overwrites our source register,
7670             // allocate a temporary register to hold the old value.
7671             current.isconst=0;
7672             current.wasconst=0;
7673             regs[i].wasconst=0;
7674             delayslot_alloc(&current,i+1);
7675             current.isconst=0;
7676             alloc_reg(&current,i,RTEMP);
7677           }
7678           //current.isconst=0; // DEBUG
7679           dops[i].ooo=1;
7680           ds=1;
7681           break;
7682         case CJUMP:
7683           //current.isconst=0;
7684           //current.wasconst=0;
7685           //regs[i].wasconst=0;
7686           clear_const(&current,dops[i].rs1);
7687           clear_const(&current,dops[i].rs2);
7688           if((dops[i].opcode&0x3E)==4) // BEQ/BNE
7689           {
7690             alloc_cc(&current,i);
7691             dirty_reg(&current,CCREG);
7692             if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
7693             if(dops[i].rs2) alloc_reg(&current,i,dops[i].rs2);
7694             if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2))||
7695                (dops[i].rs2&&(dops[i].rs2==dops[i+1].rt1||dops[i].rs2==dops[i+1].rt2))) {
7696               // The delay slot overwrites one of our conditions.
7697               // Allocate the branch condition registers instead.
7698               current.isconst=0;
7699               current.wasconst=0;
7700               regs[i].wasconst=0;
7701               if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
7702               if(dops[i].rs2) alloc_reg(&current,i,dops[i].rs2);
7703             }
7704             else
7705             {
7706               dops[i].ooo=1;
7707               delayslot_alloc(&current,i+1);
7708             }
7709           }
7710           else
7711           if((dops[i].opcode&0x3E)==6) // BLEZ/BGTZ
7712           {
7713             alloc_cc(&current,i);
7714             dirty_reg(&current,CCREG);
7715             alloc_reg(&current,i,dops[i].rs1);
7716             if(dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) {
7717               // The delay slot overwrites one of our conditions.
7718               // Allocate the branch condition registers instead.
7719               current.isconst=0;
7720               current.wasconst=0;
7721               regs[i].wasconst=0;
7722               if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
7723             }
7724             else
7725             {
7726               dops[i].ooo=1;
7727               delayslot_alloc(&current,i+1);
7728             }
7729           }
7730           else
7731           // Don't alloc the delay slot yet because we might not execute it
7732           if((dops[i].opcode&0x3E)==0x14) // BEQL/BNEL
7733           {
7734             current.isconst=0;
7735             current.wasconst=0;
7736             regs[i].wasconst=0;
7737             alloc_cc(&current,i);
7738             dirty_reg(&current,CCREG);
7739             alloc_reg(&current,i,dops[i].rs1);
7740             alloc_reg(&current,i,dops[i].rs2);
7741           }
7742           else
7743           if((dops[i].opcode&0x3E)==0x16) // BLEZL/BGTZL
7744           {
7745             current.isconst=0;
7746             current.wasconst=0;
7747             regs[i].wasconst=0;
7748             alloc_cc(&current,i);
7749             dirty_reg(&current,CCREG);
7750             alloc_reg(&current,i,dops[i].rs1);
7751           }
7752           ds=1;
7753           //current.isconst=0;
7754           break;
7755         case SJUMP:
7756           //current.isconst=0;
7757           //current.wasconst=0;
7758           //regs[i].wasconst=0;
7759           clear_const(&current,dops[i].rs1);
7760           clear_const(&current,dops[i].rt1);
7761           //if((dops[i].opcode2&0x1E)==0x0) // BLTZ/BGEZ
7762           if((dops[i].opcode2&0x0E)==0x0) // BLTZ/BGEZ
7763           {
7764             alloc_cc(&current,i);
7765             dirty_reg(&current,CCREG);
7766             alloc_reg(&current,i,dops[i].rs1);
7767             if (dops[i].rt1==31) { // BLTZAL/BGEZAL
7768               alloc_reg(&current,i,31);
7769               dirty_reg(&current,31);
7770               //#ifdef REG_PREFETCH
7771               //alloc_reg(&current,i,PTEMP);
7772               //#endif
7773             }
7774             if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) // The delay slot overwrites the branch condition.
7775                ||(dops[i].rt1==31&&(dops[i+1].rs1==31||dops[i+1].rs2==31||dops[i+1].rt1==31||dops[i+1].rt2==31))) { // DS touches $ra
7776               // Allocate the branch condition registers instead.
7777               current.isconst=0;
7778               current.wasconst=0;
7779               regs[i].wasconst=0;
7780               if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
7781             }
7782             else
7783             {
7784               dops[i].ooo=1;
7785               delayslot_alloc(&current,i+1);
7786             }
7787           }
7788           else
7789           // Don't alloc the delay slot yet because we might not execute it
7790           if((dops[i].opcode2&0x1E)==0x2) // BLTZL/BGEZL
7791           {
7792             current.isconst=0;
7793             current.wasconst=0;
7794             regs[i].wasconst=0;
7795             alloc_cc(&current,i);
7796             dirty_reg(&current,CCREG);
7797             alloc_reg(&current,i,dops[i].rs1);
7798           }
7799           ds=1;
7800           //current.isconst=0;
7801           break;
7802         case IMM16:
7803           imm16_alloc(&current,i);
7804           break;
7805         case LOAD:
7806         case LOADLR:
7807           load_alloc(&current,i);
7808           break;
7809         case STORE:
7810         case STORELR:
7811           store_alloc(&current,i);
7812           break;
7813         case ALU:
7814           alu_alloc(&current,i);
7815           break;
7816         case SHIFT:
7817           shift_alloc(&current,i);
7818           break;
7819         case MULTDIV:
7820           multdiv_alloc(&current,i);
7821           break;
7822         case SHIFTIMM:
7823           shiftimm_alloc(&current,i);
7824           break;
7825         case MOV:
7826           mov_alloc(&current,i);
7827           break;
7828         case COP0:
7829           cop0_alloc(&current,i);
7830           break;
7831         case COP1:
7832           break;
7833         case COP2:
7834           cop2_alloc(&current,i);
7835           break;
7836         case C1LS:
7837           c1ls_alloc(&current,i);
7838           break;
7839         case C2LS:
7840           c2ls_alloc(&current,i);
7841           break;
7842         case C2OP:
7843           c2op_alloc(&current,i);
7844           break;
7845         case SYSCALL:
7846         case HLECALL:
7847         case INTCALL:
7848           syscall_alloc(&current,i);
7849           break;
7850         case SPAN:
7851           pagespan_alloc(&current,i);
7852           break;
7853       }
7854
7855       // Create entry (branch target) regmap
7856       for(hr=0;hr<HOST_REGS;hr++)
7857       {
7858         int r,or;
7859         r=current.regmap[hr];
7860         if(r>=0) {
7861           if(r!=regmap_pre[i][hr]) {
7862             // TODO: delay slot (?)
7863             or=get_reg(regmap_pre[i],r); // Get old mapping for this register
7864             if(or<0||(r&63)>=TEMPREG){
7865               regs[i].regmap_entry[hr]=-1;
7866             }
7867             else
7868             {
7869               // Just move it to a different register
7870               regs[i].regmap_entry[hr]=r;
7871               // If it was dirty before, it's still dirty
7872               if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r&63);
7873             }
7874           }
7875           else
7876           {
7877             // Unneeded
7878             if(r==0){
7879               regs[i].regmap_entry[hr]=0;
7880             }
7881             else
7882             {
7883               assert(r<64);
7884               if((current.u>>r)&1) {
7885                 regs[i].regmap_entry[hr]=-1;
7886                 //regs[i].regmap[hr]=-1;
7887                 current.regmap[hr]=-1;
7888               }else
7889                 regs[i].regmap_entry[hr]=r;
7890             }
7891           }
7892         } else {
7893           // Branches expect CCREG to be allocated at the target
7894           if(regmap_pre[i][hr]==CCREG)
7895             regs[i].regmap_entry[hr]=CCREG;
7896           else
7897             regs[i].regmap_entry[hr]=-1;
7898         }
7899       }
7900       memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
7901     }
7902
7903     if(i>0&&(dops[i-1].itype==STORE||dops[i-1].itype==STORELR||(dops[i-1].itype==C2LS&&dops[i-1].opcode==0x3a))&&(u_int)imm[i-1]<0x800)
7904       current.waswritten|=1<<dops[i-1].rs1;
7905     current.waswritten&=~(1<<dops[i].rt1);
7906     current.waswritten&=~(1<<dops[i].rt2);
7907     if((dops[i].itype==STORE||dops[i].itype==STORELR||(dops[i].itype==C2LS&&dops[i].opcode==0x3a))&&(u_int)imm[i]>=0x800)
7908       current.waswritten&=~(1<<dops[i].rs1);
7909
7910     /* Branch post-alloc */
7911     if(i>0)
7912     {
7913       current.wasdirty=current.dirty;
7914       switch(dops[i-1].itype) {
7915         case UJUMP:
7916           memcpy(&branch_regs[i-1],&current,sizeof(current));
7917           branch_regs[i-1].isconst=0;
7918           branch_regs[i-1].wasconst=0;
7919           branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
7920           alloc_cc(&branch_regs[i-1],i-1);
7921           dirty_reg(&branch_regs[i-1],CCREG);
7922           if(dops[i-1].rt1==31) { // JAL
7923             alloc_reg(&branch_regs[i-1],i-1,31);
7924             dirty_reg(&branch_regs[i-1],31);
7925           }
7926           memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
7927           memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
7928           break;
7929         case RJUMP:
7930           memcpy(&branch_regs[i-1],&current,sizeof(current));
7931           branch_regs[i-1].isconst=0;
7932           branch_regs[i-1].wasconst=0;
7933           branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
7934           alloc_cc(&branch_regs[i-1],i-1);
7935           dirty_reg(&branch_regs[i-1],CCREG);
7936           alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rs1);
7937           if(dops[i-1].rt1!=0) { // JALR
7938             alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rt1);
7939             dirty_reg(&branch_regs[i-1],dops[i-1].rt1);
7940           }
7941           #ifdef USE_MINI_HT
7942           if(dops[i-1].rs1==31) { // JALR
7943             alloc_reg(&branch_regs[i-1],i-1,RHASH);
7944             alloc_reg(&branch_regs[i-1],i-1,RHTBL);
7945           }
7946           #endif
7947           memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
7948           memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
7949           break;
7950         case CJUMP:
7951           if((dops[i-1].opcode&0x3E)==4) // BEQ/BNE
7952           {
7953             alloc_cc(&current,i-1);
7954             dirty_reg(&current,CCREG);
7955             if((dops[i-1].rs1&&(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2))||
7956                (dops[i-1].rs2&&(dops[i-1].rs2==dops[i].rt1||dops[i-1].rs2==dops[i].rt2))) {
7957               // The delay slot overwrote one of our conditions
7958               // Delay slot goes after the test (in order)
7959               current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7960               current.u|=1;
7961               delayslot_alloc(&current,i);
7962               current.isconst=0;
7963             }
7964             else
7965             {
7966               current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
7967               // Alloc the branch condition registers
7968               if(dops[i-1].rs1) alloc_reg(&current,i-1,dops[i-1].rs1);
7969               if(dops[i-1].rs2) alloc_reg(&current,i-1,dops[i-1].rs2);
7970             }
7971             memcpy(&branch_regs[i-1],&current,sizeof(current));
7972             branch_regs[i-1].isconst=0;
7973             branch_regs[i-1].wasconst=0;
7974             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
7975             memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
7976           }
7977           else
7978           if((dops[i-1].opcode&0x3E)==6) // BLEZ/BGTZ
7979           {
7980             alloc_cc(&current,i-1);
7981             dirty_reg(&current,CCREG);
7982             if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
7983               // The delay slot overwrote the branch condition
7984               // Delay slot goes after the test (in order)
7985               current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7986               current.u|=1;
7987               delayslot_alloc(&current,i);
7988               current.isconst=0;
7989             }
7990             else
7991             {
7992               current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
7993               // Alloc the branch condition register
7994               alloc_reg(&current,i-1,dops[i-1].rs1);
7995             }
7996             memcpy(&branch_regs[i-1],&current,sizeof(current));
7997             branch_regs[i-1].isconst=0;
7998             branch_regs[i-1].wasconst=0;
7999             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
8000             memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
8001           }
8002           else
8003           // Alloc the delay slot in case the branch is taken
8004           if((dops[i-1].opcode&0x3E)==0x14) // BEQL/BNEL
8005           {
8006             memcpy(&branch_regs[i-1],&current,sizeof(current));
8007             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
8008             alloc_cc(&branch_regs[i-1],i);
8009             dirty_reg(&branch_regs[i-1],CCREG);
8010             delayslot_alloc(&branch_regs[i-1],i);
8011             branch_regs[i-1].isconst=0;
8012             alloc_reg(&current,i,CCREG); // Not taken path
8013             dirty_reg(&current,CCREG);
8014             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8015           }
8016           else
8017           if((dops[i-1].opcode&0x3E)==0x16) // BLEZL/BGTZL
8018           {
8019             memcpy(&branch_regs[i-1],&current,sizeof(current));
8020             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
8021             alloc_cc(&branch_regs[i-1],i);
8022             dirty_reg(&branch_regs[i-1],CCREG);
8023             delayslot_alloc(&branch_regs[i-1],i);
8024             branch_regs[i-1].isconst=0;
8025             alloc_reg(&current,i,CCREG); // Not taken path
8026             dirty_reg(&current,CCREG);
8027             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8028           }
8029           break;
8030         case SJUMP:
8031           //if((dops[i-1].opcode2&0x1E)==0) // BLTZ/BGEZ
8032           if((dops[i-1].opcode2&0x0E)==0) // BLTZ/BGEZ
8033           {
8034             alloc_cc(&current,i-1);
8035             dirty_reg(&current,CCREG);
8036             if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
8037               // The delay slot overwrote the branch condition
8038               // Delay slot goes after the test (in order)
8039               current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
8040               current.u|=1;
8041               delayslot_alloc(&current,i);
8042               current.isconst=0;
8043             }
8044             else
8045             {
8046               current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
8047               // Alloc the branch condition register
8048               alloc_reg(&current,i-1,dops[i-1].rs1);
8049             }
8050             memcpy(&branch_regs[i-1],&current,sizeof(current));
8051             branch_regs[i-1].isconst=0;
8052             branch_regs[i-1].wasconst=0;
8053             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
8054             memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
8055           }
8056           else
8057           // Alloc the delay slot in case the branch is taken
8058           if((dops[i-1].opcode2&0x1E)==2) // BLTZL/BGEZL
8059           {
8060             memcpy(&branch_regs[i-1],&current,sizeof(current));
8061             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
8062             alloc_cc(&branch_regs[i-1],i);
8063             dirty_reg(&branch_regs[i-1],CCREG);
8064             delayslot_alloc(&branch_regs[i-1],i);
8065             branch_regs[i-1].isconst=0;
8066             alloc_reg(&current,i,CCREG); // Not taken path
8067             dirty_reg(&current,CCREG);
8068             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8069           }
8070           // FIXME: BLTZAL/BGEZAL
8071           if(dops[i-1].opcode2&0x10) { // BxxZAL
8072             alloc_reg(&branch_regs[i-1],i-1,31);
8073             dirty_reg(&branch_regs[i-1],31);
8074           }
8075           break;
8076       }
8077
8078       if (dops[i-1].is_ujump)
8079       {
8080         if(dops[i-1].rt1==31) // JAL/JALR
8081         {
8082           // Subroutine call will return here, don't alloc any registers
8083           current.dirty=0;
8084           clear_all_regs(current.regmap);
8085           alloc_reg(&current,i,CCREG);
8086           dirty_reg(&current,CCREG);
8087         }
8088         else if(i+1<slen)
8089         {
8090           // Internal branch will jump here, match registers to caller
8091           current.dirty=0;
8092           clear_all_regs(current.regmap);
8093           alloc_reg(&current,i,CCREG);
8094           dirty_reg(&current,CCREG);
8095           for(j=i-1;j>=0;j--)
8096           {
8097             if(ba[j]==start+i*4+4) {
8098               memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
8099               current.dirty=branch_regs[j].dirty;
8100               break;
8101             }
8102           }
8103           while(j>=0) {
8104             if(ba[j]==start+i*4+4) {
8105               for(hr=0;hr<HOST_REGS;hr++) {
8106                 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
8107                   current.regmap[hr]=-1;
8108                 }
8109                 current.dirty&=branch_regs[j].dirty;
8110               }
8111             }
8112             j--;
8113           }
8114         }
8115       }
8116     }
8117
8118     // Count cycles in between branches
8119     ccadj[i]=cc;
8120     if (i > 0 && (dops[i-1].is_jump || dops[i].itype == SYSCALL || dops[i].itype == HLECALL))
8121     {
8122       cc=0;
8123     }
8124 #if !defined(DRC_DBG)
8125     else if(dops[i].itype==C2OP&&gte_cycletab[source[i]&0x3f]>2)
8126     {
8127       // this should really be removed since the real stalls have been implemented,
8128       // but doing so causes sizeable perf regression against the older version
8129       u_int gtec = gte_cycletab[source[i] & 0x3f];
8130       cc += HACK_ENABLED(NDHACK_NO_STALLS) ? gtec/2 : 2;
8131     }
8132     else if(i>1&&dops[i].itype==STORE&&dops[i-1].itype==STORE&&dops[i-2].itype==STORE&&!dops[i].bt)
8133     {
8134       cc+=4;
8135     }
8136     else if(dops[i].itype==C2LS)
8137     {
8138       // same as with C2OP
8139       cc += HACK_ENABLED(NDHACK_NO_STALLS) ? 4 : 2;
8140     }
8141 #endif
8142     else
8143     {
8144       cc++;
8145     }
8146
8147     if(!dops[i].is_ds) {
8148       regs[i].dirty=current.dirty;
8149       regs[i].isconst=current.isconst;
8150       memcpy(constmap[i],current_constmap,sizeof(constmap[i]));
8151     }
8152     for(hr=0;hr<HOST_REGS;hr++) {
8153       if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
8154         if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
8155           regs[i].wasconst&=~(1<<hr);
8156         }
8157       }
8158     }
8159     if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
8160     regs[i].waswritten=current.waswritten;
8161   }
8162
8163   /* Pass 4 - Cull unused host registers */
8164
8165   uint64_t nr=0;
8166
8167   for (i=slen-1;i>=0;i--)
8168   {
8169     int hr;
8170     if(dops[i].is_jump)
8171     {
8172       if(ba[i]<start || ba[i]>=(start+slen*4))
8173       {
8174         // Branch out of this block, don't need anything
8175         nr=0;
8176       }
8177       else
8178       {
8179         // Internal branch
8180         // Need whatever matches the target
8181         nr=0;
8182         int t=(ba[i]-start)>>2;
8183         for(hr=0;hr<HOST_REGS;hr++)
8184         {
8185           if(regs[i].regmap_entry[hr]>=0) {
8186             if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
8187           }
8188         }
8189       }
8190       // Conditional branch may need registers for following instructions
8191       if (!dops[i].is_ujump)
8192       {
8193         if(i<slen-2) {
8194           nr|=needed_reg[i+2];
8195           for(hr=0;hr<HOST_REGS;hr++)
8196           {
8197             if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
8198             //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
8199           }
8200         }
8201       }
8202       // Don't need stuff which is overwritten
8203       //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
8204       //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
8205       // Merge in delay slot
8206       for(hr=0;hr<HOST_REGS;hr++)
8207       {
8208         if(dops[i+1].rt1&&dops[i+1].rt1==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8209         if(dops[i+1].rt2&&dops[i+1].rt2==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8210         if(dops[i+1].rs1==regmap_pre[i][hr]) nr|=1<<hr;
8211         if(dops[i+1].rs2==regmap_pre[i][hr]) nr|=1<<hr;
8212         if(dops[i+1].rs1==regs[i].regmap_entry[hr]) nr|=1<<hr;
8213         if(dops[i+1].rs2==regs[i].regmap_entry[hr]) nr|=1<<hr;
8214         if(dops[i+1].itype==STORE || dops[i+1].itype==STORELR || (dops[i+1].opcode&0x3b)==0x39 || (dops[i+1].opcode&0x3b)==0x3a) {
8215           if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
8216           if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
8217         }
8218       }
8219     }
8220     else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
8221     {
8222       // SYSCALL instruction (software interrupt)
8223       nr=0;
8224     }
8225     else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
8226     {
8227       // ERET instruction (return from interrupt)
8228       nr=0;
8229     }
8230     else // Non-branch
8231     {
8232       if(i<slen-1) {
8233         for(hr=0;hr<HOST_REGS;hr++) {
8234           if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
8235           if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
8236           if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
8237           if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
8238         }
8239       }
8240     }
8241     for(hr=0;hr<HOST_REGS;hr++)
8242     {
8243       // Overwritten registers are not needed
8244       if(dops[i].rt1&&dops[i].rt1==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8245       if(dops[i].rt2&&dops[i].rt2==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8246       if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8247       // Source registers are needed
8248       if(dops[i].rs1==regmap_pre[i][hr]) nr|=1<<hr;
8249       if(dops[i].rs2==regmap_pre[i][hr]) nr|=1<<hr;
8250       if(dops[i].rs1==regs[i].regmap_entry[hr]) nr|=1<<hr;
8251       if(dops[i].rs2==regs[i].regmap_entry[hr]) nr|=1<<hr;
8252       if(dops[i].itype==STORE || dops[i].itype==STORELR || (dops[i].opcode&0x3b)==0x39 || (dops[i].opcode&0x3b)==0x3a) {
8253         if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
8254         if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
8255       }
8256       // Don't store a register immediately after writing it,
8257       // may prevent dual-issue.
8258       // But do so if this is a branch target, otherwise we
8259       // might have to load the register before the branch.
8260       if(i>0&&!dops[i].bt&&((regs[i].wasdirty>>hr)&1)) {
8261         if((regmap_pre[i][hr]>0&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1))) {
8262           if(dops[i-1].rt1==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8263           if(dops[i-1].rt2==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8264         }
8265         if((regs[i].regmap_entry[hr]>0&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1))) {
8266           if(dops[i-1].rt1==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8267           if(dops[i-1].rt2==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8268         }
8269       }
8270     }
8271     // Cycle count is needed at branches.  Assume it is needed at the target too.
8272     if(i==0||dops[i].bt||dops[i].itype==CJUMP||dops[i].itype==SPAN) {
8273       if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
8274       if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
8275     }
8276     // Save it
8277     needed_reg[i]=nr;
8278
8279     // Deallocate unneeded registers
8280     for(hr=0;hr<HOST_REGS;hr++)
8281     {
8282       if(!((nr>>hr)&1)) {
8283         if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
8284         if(dops[i].is_jump)
8285         {
8286           int map=0,temp=0;
8287           if(dops[i+1].itype==STORE || dops[i+1].itype==STORELR ||
8288              (dops[i+1].opcode&0x3b)==0x39 || (dops[i+1].opcode&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
8289             map=INVCP;
8290           }
8291           if(dops[i+1].itype==LOADLR || dops[i+1].itype==STORELR ||
8292              dops[i+1].itype==C1LS || dops[i+1].itype==C2LS)
8293             temp=FTEMP;
8294           if((regs[i].regmap[hr]&63)!=dops[i].rs1 && (regs[i].regmap[hr]&63)!=dops[i].rs2 &&
8295              (regs[i].regmap[hr]&63)!=dops[i].rt1 && (regs[i].regmap[hr]&63)!=dops[i].rt2 &&
8296              (regs[i].regmap[hr]&63)!=dops[i+1].rt1 && (regs[i].regmap[hr]&63)!=dops[i+1].rt2 &&
8297              regs[i].regmap[hr]!=dops[i+1].rs1 && regs[i].regmap[hr]!=dops[i+1].rs2 &&
8298              (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
8299              regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
8300              regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
8301              regs[i].regmap[hr]!=map )
8302           {
8303             regs[i].regmap[hr]=-1;
8304             regs[i].isconst&=~(1<<hr);
8305             if((branch_regs[i].regmap[hr]&63)!=dops[i].rs1 && (branch_regs[i].regmap[hr]&63)!=dops[i].rs2 &&
8306                (branch_regs[i].regmap[hr]&63)!=dops[i].rt1 && (branch_regs[i].regmap[hr]&63)!=dops[i].rt2 &&
8307                (branch_regs[i].regmap[hr]&63)!=dops[i+1].rt1 && (branch_regs[i].regmap[hr]&63)!=dops[i+1].rt2 &&
8308                branch_regs[i].regmap[hr]!=dops[i+1].rs1 && branch_regs[i].regmap[hr]!=dops[i+1].rs2 &&
8309                (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
8310                branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
8311                branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
8312                branch_regs[i].regmap[hr]!=map)
8313             {
8314               branch_regs[i].regmap[hr]=-1;
8315               branch_regs[i].regmap_entry[hr]=-1;
8316               if (!dops[i].is_ujump)
8317               {
8318                 if (i < slen-2) {
8319                   regmap_pre[i+2][hr]=-1;
8320                   regs[i+2].wasconst&=~(1<<hr);
8321                 }
8322               }
8323             }
8324           }
8325         }
8326         else
8327         {
8328           // Non-branch
8329           if(i>0)
8330           {
8331             int map=-1,temp=-1;
8332             if(dops[i].itype==STORE || dops[i].itype==STORELR ||
8333                       (dops[i].opcode&0x3b)==0x39 || (dops[i].opcode&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
8334               map=INVCP;
8335             }
8336             if(dops[i].itype==LOADLR || dops[i].itype==STORELR ||
8337                dops[i].itype==C1LS || dops[i].itype==C2LS)
8338               temp=FTEMP;
8339             if((regs[i].regmap[hr]&63)!=dops[i].rt1 && (regs[i].regmap[hr]&63)!=dops[i].rt2 &&
8340                regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 &&
8341                (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
8342                (dops[i].itype!=SPAN||regs[i].regmap[hr]!=CCREG))
8343             {
8344               if(i<slen-1&&!dops[i].is_ds) {
8345                 assert(regs[i].regmap[hr]<64);
8346                 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]>0)
8347                 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
8348                 {
8349                   SysPrintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
8350                   assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
8351                 }
8352                 regmap_pre[i+1][hr]=-1;
8353                 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
8354                 regs[i+1].wasconst&=~(1<<hr);
8355               }
8356               regs[i].regmap[hr]=-1;
8357               regs[i].isconst&=~(1<<hr);
8358             }
8359           }
8360         }
8361       } // if needed
8362     } // for hr
8363   }
8364
8365   /* Pass 5 - Pre-allocate registers */
8366
8367   // If a register is allocated during a loop, try to allocate it for the
8368   // entire loop, if possible.  This avoids loading/storing registers
8369   // inside of the loop.
8370
8371   signed char f_regmap[HOST_REGS];
8372   clear_all_regs(f_regmap);
8373   for(i=0;i<slen-1;i++)
8374   {
8375     if(dops[i].itype==UJUMP||dops[i].itype==CJUMP||dops[i].itype==SJUMP)
8376     {
8377       if(ba[i]>=start && ba[i]<(start+i*4))
8378       if(dops[i+1].itype==NOP||dops[i+1].itype==MOV||dops[i+1].itype==ALU
8379       ||dops[i+1].itype==SHIFTIMM||dops[i+1].itype==IMM16||dops[i+1].itype==LOAD
8380       ||dops[i+1].itype==STORE||dops[i+1].itype==STORELR||dops[i+1].itype==C1LS
8381       ||dops[i+1].itype==SHIFT||dops[i+1].itype==COP1
8382       ||dops[i+1].itype==COP2||dops[i+1].itype==C2LS||dops[i+1].itype==C2OP)
8383       {
8384         int t=(ba[i]-start)>>2;
8385         if(t > 0 && !dops[t-1].is_jump) // loop_preload can't handle jumps into delay slots
8386         if(t<2||(dops[t-2].itype!=UJUMP&&dops[t-2].itype!=RJUMP)||dops[t-2].rt1!=31) // call/ret assumes no registers allocated
8387         for(hr=0;hr<HOST_REGS;hr++)
8388         {
8389           if(regs[i].regmap[hr]>=0) {
8390             if(f_regmap[hr]!=regs[i].regmap[hr]) {
8391               // dealloc old register
8392               int n;
8393               for(n=0;n<HOST_REGS;n++)
8394               {
8395                 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8396               }
8397               // and alloc new one
8398               f_regmap[hr]=regs[i].regmap[hr];
8399             }
8400           }
8401           if(branch_regs[i].regmap[hr]>=0) {
8402             if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
8403               // dealloc old register
8404               int n;
8405               for(n=0;n<HOST_REGS;n++)
8406               {
8407                 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
8408               }
8409               // and alloc new one
8410               f_regmap[hr]=branch_regs[i].regmap[hr];
8411             }
8412           }
8413           if(dops[i].ooo) {
8414             if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
8415               f_regmap[hr]=branch_regs[i].regmap[hr];
8416           }else{
8417             if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
8418               f_regmap[hr]=branch_regs[i].regmap[hr];
8419           }
8420           // Avoid dirty->clean transition
8421           #ifdef DESTRUCTIVE_WRITEBACK
8422           if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
8423           #endif
8424           // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
8425           // case above, however it's always a good idea.  We can't hoist the
8426           // load if the register was already allocated, so there's no point
8427           // wasting time analyzing most of these cases.  It only "succeeds"
8428           // when the mapping was different and the load can be replaced with
8429           // a mov, which is of negligible benefit.  So such cases are
8430           // skipped below.
8431           if(f_regmap[hr]>0) {
8432             if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
8433               int r=f_regmap[hr];
8434               for(j=t;j<=i;j++)
8435               {
8436                 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
8437                 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
8438                 assert(r < 64);
8439                 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
8440                   //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
8441                   int k;
8442                   if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
8443                     if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
8444                     if(r>63) {
8445                       if(get_reg(regs[i].regmap,r&63)<0) break;
8446                       if(get_reg(branch_regs[i].regmap,r&63)<0) break;
8447                     }
8448                     k=i;
8449                     while(k>1&&regs[k-1].regmap[hr]==-1) {
8450                       if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
8451                         //printf("no free regs for store %x\n",start+(k-1)*4);
8452                         break;
8453                       }
8454                       if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
8455                         //printf("no-match due to different register\n");
8456                         break;
8457                       }
8458                       if (dops[k-2].is_jump) {
8459                         //printf("no-match due to branch\n");
8460                         break;
8461                       }
8462                       // call/ret fast path assumes no registers allocated
8463                       if(k>2&&(dops[k-3].itype==UJUMP||dops[k-3].itype==RJUMP)&&dops[k-3].rt1==31) {
8464                         break;
8465                       }
8466                       assert(r < 64);
8467                       k--;
8468                     }
8469                     if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
8470                       //printf("Extend r%d, %x ->\n",hr,start+k*4);
8471                       while(k<i) {
8472                         regs[k].regmap_entry[hr]=f_regmap[hr];
8473                         regs[k].regmap[hr]=f_regmap[hr];
8474                         regmap_pre[k+1][hr]=f_regmap[hr];
8475                         regs[k].wasdirty&=~(1<<hr);
8476                         regs[k].dirty&=~(1<<hr);
8477                         regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
8478                         regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
8479                         regs[k].wasconst&=~(1<<hr);
8480                         regs[k].isconst&=~(1<<hr);
8481                         k++;
8482                       }
8483                     }
8484                     else {
8485                       //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
8486                       break;
8487                     }
8488                     assert(regs[i-1].regmap[hr]==f_regmap[hr]);
8489                     if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
8490                       //printf("OK fill %x (r%d)\n",start+i*4,hr);
8491                       regs[i].regmap_entry[hr]=f_regmap[hr];
8492                       regs[i].regmap[hr]=f_regmap[hr];
8493                       regs[i].wasdirty&=~(1<<hr);
8494                       regs[i].dirty&=~(1<<hr);
8495                       regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
8496                       regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
8497                       regs[i].wasconst&=~(1<<hr);
8498                       regs[i].isconst&=~(1<<hr);
8499                       branch_regs[i].regmap_entry[hr]=f_regmap[hr];
8500                       branch_regs[i].wasdirty&=~(1<<hr);
8501                       branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
8502                       branch_regs[i].regmap[hr]=f_regmap[hr];
8503                       branch_regs[i].dirty&=~(1<<hr);
8504                       branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
8505                       branch_regs[i].wasconst&=~(1<<hr);
8506                       branch_regs[i].isconst&=~(1<<hr);
8507                       if (!dops[i].is_ujump) {
8508                         regmap_pre[i+2][hr]=f_regmap[hr];
8509                         regs[i+2].wasdirty&=~(1<<hr);
8510                         regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
8511                       }
8512                     }
8513                   }
8514                   for(k=t;k<j;k++) {
8515                     // Alloc register clean at beginning of loop,
8516                     // but may dirty it in pass 6
8517                     regs[k].regmap_entry[hr]=f_regmap[hr];
8518                     regs[k].regmap[hr]=f_regmap[hr];
8519                     regs[k].dirty&=~(1<<hr);
8520                     regs[k].wasconst&=~(1<<hr);
8521                     regs[k].isconst&=~(1<<hr);
8522                     if (dops[k].is_jump) {
8523                       branch_regs[k].regmap_entry[hr]=f_regmap[hr];
8524                       branch_regs[k].regmap[hr]=f_regmap[hr];
8525                       branch_regs[k].dirty&=~(1<<hr);
8526                       branch_regs[k].wasconst&=~(1<<hr);
8527                       branch_regs[k].isconst&=~(1<<hr);
8528                       if (!dops[k].is_ujump) {
8529                         regmap_pre[k+2][hr]=f_regmap[hr];
8530                         regs[k+2].wasdirty&=~(1<<hr);
8531                       }
8532                     }
8533                     else
8534                     {
8535                       regmap_pre[k+1][hr]=f_regmap[hr];
8536                       regs[k+1].wasdirty&=~(1<<hr);
8537                     }
8538                   }
8539                   if(regs[j].regmap[hr]==f_regmap[hr])
8540                     regs[j].regmap_entry[hr]=f_regmap[hr];
8541                   break;
8542                 }
8543                 if(j==i) break;
8544                 if(regs[j].regmap[hr]>=0)
8545                   break;
8546                 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
8547                   //printf("no-match due to different register\n");
8548                   break;
8549                 }
8550                 if (dops[j].is_ujump)
8551                 {
8552                   // Stop on unconditional branch
8553                   break;
8554                 }
8555                 if(dops[j].itype==CJUMP||dops[j].itype==SJUMP)
8556                 {
8557                   if(dops[j].ooo) {
8558                     if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
8559                       break;
8560                   }else{
8561                     if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
8562                       break;
8563                   }
8564                   if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
8565                     //printf("no-match due to different register (branch)\n");
8566                     break;
8567                   }
8568                 }
8569                 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
8570                   //printf("No free regs for store %x\n",start+j*4);
8571                   break;
8572                 }
8573                 assert(f_regmap[hr]<64);
8574               }
8575             }
8576           }
8577         }
8578       }
8579     }else{
8580       // Non branch or undetermined branch target
8581       for(hr=0;hr<HOST_REGS;hr++)
8582       {
8583         if(hr!=EXCLUDE_REG) {
8584           if(regs[i].regmap[hr]>=0) {
8585             if(f_regmap[hr]!=regs[i].regmap[hr]) {
8586               // dealloc old register
8587               int n;
8588               for(n=0;n<HOST_REGS;n++)
8589               {
8590                 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8591               }
8592               // and alloc new one
8593               f_regmap[hr]=regs[i].regmap[hr];
8594             }
8595           }
8596         }
8597       }
8598       // Try to restore cycle count at branch targets
8599       if(dops[i].bt) {
8600         for(j=i;j<slen-1;j++) {
8601           if(regs[j].regmap[HOST_CCREG]!=-1) break;
8602           if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
8603             //printf("no free regs for store %x\n",start+j*4);
8604             break;
8605           }
8606         }
8607         if(regs[j].regmap[HOST_CCREG]==CCREG) {
8608           int k=i;
8609           //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
8610           while(k<j) {
8611             regs[k].regmap_entry[HOST_CCREG]=CCREG;
8612             regs[k].regmap[HOST_CCREG]=CCREG;
8613             regmap_pre[k+1][HOST_CCREG]=CCREG;
8614             regs[k+1].wasdirty|=1<<HOST_CCREG;
8615             regs[k].dirty|=1<<HOST_CCREG;
8616             regs[k].wasconst&=~(1<<HOST_CCREG);
8617             regs[k].isconst&=~(1<<HOST_CCREG);
8618             k++;
8619           }
8620           regs[j].regmap_entry[HOST_CCREG]=CCREG;
8621         }
8622         // Work backwards from the branch target
8623         if(j>i&&f_regmap[HOST_CCREG]==CCREG)
8624         {
8625           //printf("Extend backwards\n");
8626           int k;
8627           k=i;
8628           while(regs[k-1].regmap[HOST_CCREG]==-1) {
8629             if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
8630               //printf("no free regs for store %x\n",start+(k-1)*4);
8631               break;
8632             }
8633             k--;
8634           }
8635           if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
8636             //printf("Extend CC, %x ->\n",start+k*4);
8637             while(k<=i) {
8638               regs[k].regmap_entry[HOST_CCREG]=CCREG;
8639               regs[k].regmap[HOST_CCREG]=CCREG;
8640               regmap_pre[k+1][HOST_CCREG]=CCREG;
8641               regs[k+1].wasdirty|=1<<HOST_CCREG;
8642               regs[k].dirty|=1<<HOST_CCREG;
8643               regs[k].wasconst&=~(1<<HOST_CCREG);
8644               regs[k].isconst&=~(1<<HOST_CCREG);
8645               k++;
8646             }
8647           }
8648           else {
8649             //printf("Fail Extend CC, %x ->\n",start+k*4);
8650           }
8651         }
8652       }
8653       if(dops[i].itype!=STORE&&dops[i].itype!=STORELR&&dops[i].itype!=C1LS&&dops[i].itype!=SHIFT&&
8654          dops[i].itype!=NOP&&dops[i].itype!=MOV&&dops[i].itype!=ALU&&dops[i].itype!=SHIFTIMM&&
8655          dops[i].itype!=IMM16&&dops[i].itype!=LOAD&&dops[i].itype!=COP1)
8656       {
8657         memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
8658       }
8659     }
8660   }
8661
8662   // This allocates registers (if possible) one instruction prior
8663   // to use, which can avoid a load-use penalty on certain CPUs.
8664   for(i=0;i<slen-1;i++)
8665   {
8666     if (!i || !dops[i-1].is_jump)
8667     {
8668       if(!dops[i+1].bt)
8669       {
8670         if(dops[i].itype==ALU||dops[i].itype==MOV||dops[i].itype==LOAD||dops[i].itype==SHIFTIMM||dops[i].itype==IMM16
8671            ||((dops[i].itype==COP1||dops[i].itype==COP2)&&dops[i].opcode2<3))
8672         {
8673           if(dops[i+1].rs1) {
8674             if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs1))>=0)
8675             {
8676               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8677               {
8678                 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8679                 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8680                 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8681                 regs[i].isconst&=~(1<<hr);
8682                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8683                 constmap[i][hr]=constmap[i+1][hr];
8684                 regs[i+1].wasdirty&=~(1<<hr);
8685                 regs[i].dirty&=~(1<<hr);
8686               }
8687             }
8688           }
8689           if(dops[i+1].rs2) {
8690             if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs2))>=0)
8691             {
8692               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8693               {
8694                 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8695                 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8696                 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8697                 regs[i].isconst&=~(1<<hr);
8698                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8699                 constmap[i][hr]=constmap[i+1][hr];
8700                 regs[i+1].wasdirty&=~(1<<hr);
8701                 regs[i].dirty&=~(1<<hr);
8702               }
8703             }
8704           }
8705           // Preload target address for load instruction (non-constant)
8706           if(dops[i+1].itype==LOAD&&dops[i+1].rs1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8707             if((hr=get_reg(regs[i+1].regmap,dops[i+1].rt1))>=0)
8708             {
8709               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8710               {
8711                 regs[i].regmap[hr]=dops[i+1].rs1;
8712                 regmap_pre[i+1][hr]=dops[i+1].rs1;
8713                 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8714                 regs[i].isconst&=~(1<<hr);
8715                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8716                 constmap[i][hr]=constmap[i+1][hr];
8717                 regs[i+1].wasdirty&=~(1<<hr);
8718                 regs[i].dirty&=~(1<<hr);
8719               }
8720             }
8721           }
8722           // Load source into target register
8723           if(dops[i+1].lt1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8724             if((hr=get_reg(regs[i+1].regmap,dops[i+1].rt1))>=0)
8725             {
8726               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8727               {
8728                 regs[i].regmap[hr]=dops[i+1].rs1;
8729                 regmap_pre[i+1][hr]=dops[i+1].rs1;
8730                 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8731                 regs[i].isconst&=~(1<<hr);
8732                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8733                 constmap[i][hr]=constmap[i+1][hr];
8734                 regs[i+1].wasdirty&=~(1<<hr);
8735                 regs[i].dirty&=~(1<<hr);
8736               }
8737             }
8738           }
8739           // Address for store instruction (non-constant)
8740           if(dops[i+1].itype==STORE||dops[i+1].itype==STORELR
8741              ||(dops[i+1].opcode&0x3b)==0x39||(dops[i+1].opcode&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
8742             if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8743               hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
8744               if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
8745               else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
8746               assert(hr>=0);
8747               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8748               {
8749                 regs[i].regmap[hr]=dops[i+1].rs1;
8750                 regmap_pre[i+1][hr]=dops[i+1].rs1;
8751                 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8752                 regs[i].isconst&=~(1<<hr);
8753                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8754                 constmap[i][hr]=constmap[i+1][hr];
8755                 regs[i+1].wasdirty&=~(1<<hr);
8756                 regs[i].dirty&=~(1<<hr);
8757               }
8758             }
8759           }
8760           if(dops[i+1].itype==LOADLR||(dops[i+1].opcode&0x3b)==0x31||(dops[i+1].opcode&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
8761             if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8762               int nr;
8763               hr=get_reg(regs[i+1].regmap,FTEMP);
8764               assert(hr>=0);
8765               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8766               {
8767                 regs[i].regmap[hr]=dops[i+1].rs1;
8768                 regmap_pre[i+1][hr]=dops[i+1].rs1;
8769                 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8770                 regs[i].isconst&=~(1<<hr);
8771                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8772                 constmap[i][hr]=constmap[i+1][hr];
8773                 regs[i+1].wasdirty&=~(1<<hr);
8774                 regs[i].dirty&=~(1<<hr);
8775               }
8776               else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
8777               {
8778                 // move it to another register
8779                 regs[i+1].regmap[hr]=-1;
8780                 regmap_pre[i+2][hr]=-1;
8781                 regs[i+1].regmap[nr]=FTEMP;
8782                 regmap_pre[i+2][nr]=FTEMP;
8783                 regs[i].regmap[nr]=dops[i+1].rs1;
8784                 regmap_pre[i+1][nr]=dops[i+1].rs1;
8785                 regs[i+1].regmap_entry[nr]=dops[i+1].rs1;
8786                 regs[i].isconst&=~(1<<nr);
8787                 regs[i+1].isconst&=~(1<<nr);
8788                 regs[i].dirty&=~(1<<nr);
8789                 regs[i+1].wasdirty&=~(1<<nr);
8790                 regs[i+1].dirty&=~(1<<nr);
8791                 regs[i+2].wasdirty&=~(1<<nr);
8792               }
8793             }
8794           }
8795           if(dops[i+1].itype==LOAD||dops[i+1].itype==LOADLR||dops[i+1].itype==STORE||dops[i+1].itype==STORELR/*||dops[i+1].itype==C1LS||||dops[i+1].itype==C2LS*/) {
8796             if(dops[i+1].itype==LOAD)
8797               hr=get_reg(regs[i+1].regmap,dops[i+1].rt1);
8798             if(dops[i+1].itype==LOADLR||(dops[i+1].opcode&0x3b)==0x31||(dops[i+1].opcode&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
8799               hr=get_reg(regs[i+1].regmap,FTEMP);
8800             if(dops[i+1].itype==STORE||dops[i+1].itype==STORELR||(dops[i+1].opcode&0x3b)==0x39||(dops[i+1].opcode&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
8801               hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
8802               if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
8803             }
8804             if(hr>=0&&regs[i].regmap[hr]<0) {
8805               int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
8806               if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
8807                 regs[i].regmap[hr]=AGEN1+((i+1)&1);
8808                 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
8809                 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
8810                 regs[i].isconst&=~(1<<hr);
8811                 regs[i+1].wasdirty&=~(1<<hr);
8812                 regs[i].dirty&=~(1<<hr);
8813               }
8814             }
8815           }
8816         }
8817       }
8818     }
8819   }
8820
8821   /* Pass 6 - Optimize clean/dirty state */
8822   clean_registers(0,slen-1,1);
8823
8824   /* Pass 7 - Identify 32-bit registers */
8825   for (i=slen-1;i>=0;i--)
8826   {
8827     if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
8828     {
8829       // Conditional branch
8830       if((source[i]>>16)!=0x1000&&i<slen-2) {
8831         // Mark this address as a branch target since it may be called
8832         // upon return from interrupt
8833         dops[i+2].bt=1;
8834       }
8835     }
8836   }
8837
8838   if(dops[slen-1].itype==SPAN) {
8839     dops[slen-1].bt=1; // Mark as a branch target so instruction can restart after exception
8840   }
8841
8842 #ifdef DISASM
8843   /* Debug/disassembly */
8844   for(i=0;i<slen;i++)
8845   {
8846     printf("U:");
8847     int r;
8848     for(r=1;r<=CCREG;r++) {
8849       if((unneeded_reg[i]>>r)&1) {
8850         if(r==HIREG) printf(" HI");
8851         else if(r==LOREG) printf(" LO");
8852         else printf(" r%d",r);
8853       }
8854     }
8855     printf("\n");
8856     #if defined(__i386__) || defined(__x86_64__)
8857     printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
8858     #endif
8859     #ifdef __arm__
8860     printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
8861     #endif
8862     #if defined(__i386__) || defined(__x86_64__)
8863     printf("needs: ");
8864     if(needed_reg[i]&1) printf("eax ");
8865     if((needed_reg[i]>>1)&1) printf("ecx ");
8866     if((needed_reg[i]>>2)&1) printf("edx ");
8867     if((needed_reg[i]>>3)&1) printf("ebx ");
8868     if((needed_reg[i]>>5)&1) printf("ebp ");
8869     if((needed_reg[i]>>6)&1) printf("esi ");
8870     if((needed_reg[i]>>7)&1) printf("edi ");
8871     printf("\n");
8872     printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
8873     printf("dirty: ");
8874     if(regs[i].wasdirty&1) printf("eax ");
8875     if((regs[i].wasdirty>>1)&1) printf("ecx ");
8876     if((regs[i].wasdirty>>2)&1) printf("edx ");
8877     if((regs[i].wasdirty>>3)&1) printf("ebx ");
8878     if((regs[i].wasdirty>>5)&1) printf("ebp ");
8879     if((regs[i].wasdirty>>6)&1) printf("esi ");
8880     if((regs[i].wasdirty>>7)&1) printf("edi ");
8881     #endif
8882     #ifdef __arm__
8883     printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
8884     printf("dirty: ");
8885     if(regs[i].wasdirty&1) printf("r0 ");
8886     if((regs[i].wasdirty>>1)&1) printf("r1 ");
8887     if((regs[i].wasdirty>>2)&1) printf("r2 ");
8888     if((regs[i].wasdirty>>3)&1) printf("r3 ");
8889     if((regs[i].wasdirty>>4)&1) printf("r4 ");
8890     if((regs[i].wasdirty>>5)&1) printf("r5 ");
8891     if((regs[i].wasdirty>>6)&1) printf("r6 ");
8892     if((regs[i].wasdirty>>7)&1) printf("r7 ");
8893     if((regs[i].wasdirty>>8)&1) printf("r8 ");
8894     if((regs[i].wasdirty>>9)&1) printf("r9 ");
8895     if((regs[i].wasdirty>>10)&1) printf("r10 ");
8896     if((regs[i].wasdirty>>12)&1) printf("r12 ");
8897     #endif
8898     printf("\n");
8899     disassemble_inst(i);
8900     //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
8901     #if defined(__i386__) || defined(__x86_64__)
8902     printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
8903     if(regs[i].dirty&1) printf("eax ");
8904     if((regs[i].dirty>>1)&1) printf("ecx ");
8905     if((regs[i].dirty>>2)&1) printf("edx ");
8906     if((regs[i].dirty>>3)&1) printf("ebx ");
8907     if((regs[i].dirty>>5)&1) printf("ebp ");
8908     if((regs[i].dirty>>6)&1) printf("esi ");
8909     if((regs[i].dirty>>7)&1) printf("edi ");
8910     #endif
8911     #ifdef __arm__
8912     printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
8913     if(regs[i].dirty&1) printf("r0 ");
8914     if((regs[i].dirty>>1)&1) printf("r1 ");
8915     if((regs[i].dirty>>2)&1) printf("r2 ");
8916     if((regs[i].dirty>>3)&1) printf("r3 ");
8917     if((regs[i].dirty>>4)&1) printf("r4 ");
8918     if((regs[i].dirty>>5)&1) printf("r5 ");
8919     if((regs[i].dirty>>6)&1) printf("r6 ");
8920     if((regs[i].dirty>>7)&1) printf("r7 ");
8921     if((regs[i].dirty>>8)&1) printf("r8 ");
8922     if((regs[i].dirty>>9)&1) printf("r9 ");
8923     if((regs[i].dirty>>10)&1) printf("r10 ");
8924     if((regs[i].dirty>>12)&1) printf("r12 ");
8925     #endif
8926     printf("\n");
8927     if(regs[i].isconst) {
8928       printf("constants: ");
8929       #if defined(__i386__) || defined(__x86_64__)
8930       if(regs[i].isconst&1) printf("eax=%x ",(u_int)constmap[i][0]);
8931       if((regs[i].isconst>>1)&1) printf("ecx=%x ",(u_int)constmap[i][1]);
8932       if((regs[i].isconst>>2)&1) printf("edx=%x ",(u_int)constmap[i][2]);
8933       if((regs[i].isconst>>3)&1) printf("ebx=%x ",(u_int)constmap[i][3]);
8934       if((regs[i].isconst>>5)&1) printf("ebp=%x ",(u_int)constmap[i][5]);
8935       if((regs[i].isconst>>6)&1) printf("esi=%x ",(u_int)constmap[i][6]);
8936       if((regs[i].isconst>>7)&1) printf("edi=%x ",(u_int)constmap[i][7]);
8937       #endif
8938       #if defined(__arm__) || defined(__aarch64__)
8939       int r;
8940       for (r = 0; r < ARRAY_SIZE(constmap[i]); r++)
8941         if ((regs[i].isconst >> r) & 1)
8942           printf(" r%d=%x", r, (u_int)constmap[i][r]);
8943       #endif
8944       printf("\n");
8945     }
8946     if(dops[i].is_jump) {
8947       #if defined(__i386__) || defined(__x86_64__)
8948       printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
8949       if(branch_regs[i].dirty&1) printf("eax ");
8950       if((branch_regs[i].dirty>>1)&1) printf("ecx ");
8951       if((branch_regs[i].dirty>>2)&1) printf("edx ");
8952       if((branch_regs[i].dirty>>3)&1) printf("ebx ");
8953       if((branch_regs[i].dirty>>5)&1) printf("ebp ");
8954       if((branch_regs[i].dirty>>6)&1) printf("esi ");
8955       if((branch_regs[i].dirty>>7)&1) printf("edi ");
8956       #endif
8957       #ifdef __arm__
8958       printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
8959       if(branch_regs[i].dirty&1) printf("r0 ");
8960       if((branch_regs[i].dirty>>1)&1) printf("r1 ");
8961       if((branch_regs[i].dirty>>2)&1) printf("r2 ");
8962       if((branch_regs[i].dirty>>3)&1) printf("r3 ");
8963       if((branch_regs[i].dirty>>4)&1) printf("r4 ");
8964       if((branch_regs[i].dirty>>5)&1) printf("r5 ");
8965       if((branch_regs[i].dirty>>6)&1) printf("r6 ");
8966       if((branch_regs[i].dirty>>7)&1) printf("r7 ");
8967       if((branch_regs[i].dirty>>8)&1) printf("r8 ");
8968       if((branch_regs[i].dirty>>9)&1) printf("r9 ");
8969       if((branch_regs[i].dirty>>10)&1) printf("r10 ");
8970       if((branch_regs[i].dirty>>12)&1) printf("r12 ");
8971       #endif
8972     }
8973   }
8974 #endif // DISASM
8975
8976   /* Pass 8 - Assembly */
8977   linkcount=0;stubcount=0;
8978   ds=0;is_delayslot=0;
8979   u_int dirty_pre=0;
8980   void *beginning=start_block();
8981   if((u_int)addr&1) {
8982     ds=1;
8983     pagespan_ds();
8984   }
8985   void *instr_addr0_override = NULL;
8986
8987   if (start == 0x80030000) {
8988     // nasty hack for the fastbios thing
8989     // override block entry to this code
8990     instr_addr0_override = out;
8991     emit_movimm(start,0);
8992     // abuse io address var as a flag that we
8993     // have already returned here once
8994     emit_readword(&address,1);
8995     emit_writeword(0,&pcaddr);
8996     emit_writeword(0,&address);
8997     emit_cmp(0,1);
8998     #ifdef __aarch64__
8999     emit_jeq(out + 4*2);
9000     emit_far_jump(new_dyna_leave);
9001     #else
9002     emit_jne(new_dyna_leave);
9003     #endif
9004   }
9005   for(i=0;i<slen;i++)
9006   {
9007     //if(ds) printf("ds: ");
9008     disassemble_inst(i);
9009     if(ds) {
9010       ds=0; // Skip delay slot
9011       if(dops[i].bt) assem_debug("OOPS - branch into delay slot\n");
9012       instr_addr[i] = NULL;
9013     } else {
9014       speculate_register_values(i);
9015       #ifndef DESTRUCTIVE_WRITEBACK
9016       if (i < 2 || !dops[i-2].is_ujump)
9017       {
9018         wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,unneeded_reg[i]);
9019       }
9020       if((dops[i].itype==CJUMP||dops[i].itype==SJUMP)) {
9021         dirty_pre=branch_regs[i].dirty;
9022       }else{
9023         dirty_pre=regs[i].dirty;
9024       }
9025       #endif
9026       // write back
9027       if (i < 2 || !dops[i-2].is_ujump)
9028       {
9029         wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,unneeded_reg[i]);
9030         loop_preload(regmap_pre[i],regs[i].regmap_entry);
9031       }
9032       // branch target entry point
9033       instr_addr[i] = out;
9034       assem_debug("<->\n");
9035       drc_dbg_emit_do_cmp(i);
9036
9037       // load regs
9038       if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
9039         wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty);
9040       load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i].rs1,dops[i].rs2);
9041       address_generation(i,&regs[i],regs[i].regmap_entry);
9042       load_consts(regmap_pre[i],regs[i].regmap,i);
9043       if(dops[i].is_jump)
9044       {
9045         // Load the delay slot registers if necessary
9046         if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2&&(dops[i+1].rs1!=dops[i].rt1||dops[i].rt1==0))
9047           load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9048         if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2&&(dops[i+1].rs2!=dops[i].rt1||dops[i].rt1==0))
9049           load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
9050         if(dops[i+1].itype==STORE||dops[i+1].itype==STORELR||(dops[i+1].opcode&0x3b)==0x39||(dops[i+1].opcode&0x3b)==0x3a)
9051           load_regs(regs[i].regmap_entry,regs[i].regmap,INVCP,INVCP);
9052       }
9053       else if(i+1<slen)
9054       {
9055         // Preload registers for following instruction
9056         if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2)
9057           if(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs1!=dops[i].rt2)
9058             load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9059         if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2)
9060           if(dops[i+1].rs2!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt2)
9061             load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
9062       }
9063       // TODO: if(is_ooo(i)) address_generation(i+1);
9064       if(dops[i].itype==CJUMP)
9065         load_regs(regs[i].regmap_entry,regs[i].regmap,CCREG,CCREG);
9066       if(dops[i].itype==STORE||dops[i].itype==STORELR||(dops[i].opcode&0x3b)==0x39||(dops[i].opcode&0x3b)==0x3a)
9067         load_regs(regs[i].regmap_entry,regs[i].regmap,INVCP,INVCP);
9068       // assemble
9069       switch(dops[i].itype) {
9070         case ALU:
9071           alu_assemble(i,&regs[i]);break;
9072         case IMM16:
9073           imm16_assemble(i,&regs[i]);break;
9074         case SHIFT:
9075           shift_assemble(i,&regs[i]);break;
9076         case SHIFTIMM:
9077           shiftimm_assemble(i,&regs[i]);break;
9078         case LOAD:
9079           load_assemble(i,&regs[i]);break;
9080         case LOADLR:
9081           loadlr_assemble(i,&regs[i]);break;
9082         case STORE:
9083           store_assemble(i,&regs[i]);break;
9084         case STORELR:
9085           storelr_assemble(i,&regs[i]);break;
9086         case COP0:
9087           cop0_assemble(i,&regs[i]);break;
9088         case COP1:
9089           cop1_assemble(i,&regs[i]);break;
9090         case C1LS:
9091           c1ls_assemble(i,&regs[i]);break;
9092         case COP2:
9093           cop2_assemble(i,&regs[i]);break;
9094         case C2LS:
9095           c2ls_assemble(i,&regs[i]);break;
9096         case C2OP:
9097           c2op_assemble(i,&regs[i]);break;
9098         case MULTDIV:
9099           multdiv_assemble(i,&regs[i]);
9100           multdiv_prepare_stall(i,&regs[i]);
9101           break;
9102         case MOV:
9103           mov_assemble(i,&regs[i]);break;
9104         case SYSCALL:
9105           syscall_assemble(i,&regs[i]);break;
9106         case HLECALL:
9107           hlecall_assemble(i,&regs[i]);break;
9108         case INTCALL:
9109           intcall_assemble(i,&regs[i]);break;
9110         case UJUMP:
9111           ujump_assemble(i,&regs[i]);ds=1;break;
9112         case RJUMP:
9113           rjump_assemble(i,&regs[i]);ds=1;break;
9114         case CJUMP:
9115           cjump_assemble(i,&regs[i]);ds=1;break;
9116         case SJUMP:
9117           sjump_assemble(i,&regs[i]);ds=1;break;
9118         case SPAN:
9119           pagespan_assemble(i,&regs[i]);break;
9120       }
9121       if (dops[i].is_ujump)
9122         literal_pool(1024);
9123       else
9124         literal_pool_jumpover(256);
9125     }
9126   }
9127
9128   assert(slen > 0);
9129   if (slen > 0 && dops[slen-1].itype == INTCALL) {
9130     // no ending needed for this block since INTCALL never returns
9131   }
9132   // If the block did not end with an unconditional branch,
9133   // add a jump to the next instruction.
9134   else if (i > 1) {
9135     if (!dops[i-2].is_ujump && dops[i-1].itype != SPAN) {
9136       assert(!dops[i-1].is_jump);
9137       assert(i==slen);
9138       if(dops[i-2].itype!=CJUMP&&dops[i-2].itype!=SJUMP) {
9139         store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
9140         if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9141           emit_loadreg(CCREG,HOST_CCREG);
9142         emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
9143       }
9144       else
9145       {
9146         store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].dirty,start+i*4);
9147         assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
9148       }
9149       add_to_linker(out,start+i*4,0);
9150       emit_jmp(0);
9151     }
9152   }
9153   else
9154   {
9155     assert(i>0);
9156     assert(!dops[i-1].is_jump);
9157     store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
9158     if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9159       emit_loadreg(CCREG,HOST_CCREG);
9160     emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
9161     add_to_linker(out,start+i*4,0);
9162     emit_jmp(0);
9163   }
9164
9165   // TODO: delay slot stubs?
9166   // Stubs
9167   for(i=0;i<stubcount;i++)
9168   {
9169     switch(stubs[i].type)
9170     {
9171       case LOADB_STUB:
9172       case LOADH_STUB:
9173       case LOADW_STUB:
9174       case LOADD_STUB:
9175       case LOADBU_STUB:
9176       case LOADHU_STUB:
9177         do_readstub(i);break;
9178       case STOREB_STUB:
9179       case STOREH_STUB:
9180       case STOREW_STUB:
9181       case STORED_STUB:
9182         do_writestub(i);break;
9183       case CC_STUB:
9184         do_ccstub(i);break;
9185       case INVCODE_STUB:
9186         do_invstub(i);break;
9187       case FP_STUB:
9188         do_cop1stub(i);break;
9189       case STORELR_STUB:
9190         do_unalignedwritestub(i);break;
9191     }
9192   }
9193
9194   if (instr_addr0_override)
9195     instr_addr[0] = instr_addr0_override;
9196
9197   /* Pass 9 - Linker */
9198   for(i=0;i<linkcount;i++)
9199   {
9200     assem_debug("%p -> %8x\n",link_addr[i].addr,link_addr[i].target);
9201     literal_pool(64);
9202     if (!link_addr[i].ext)
9203     {
9204       void *stub = out;
9205       void *addr = check_addr(link_addr[i].target);
9206       emit_extjump(link_addr[i].addr, link_addr[i].target);
9207       if (addr) {
9208         set_jump_target(link_addr[i].addr, addr);
9209         add_jump_out(link_addr[i].target,stub);
9210       }
9211       else
9212         set_jump_target(link_addr[i].addr, stub);
9213     }
9214     else
9215     {
9216       // Internal branch
9217       int target=(link_addr[i].target-start)>>2;
9218       assert(target>=0&&target<slen);
9219       assert(instr_addr[target]);
9220       //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
9221       //set_jump_target_fillslot(link_addr[i].addr,instr_addr[target],link_addr[i].ext>>1);
9222       //#else
9223       set_jump_target(link_addr[i].addr, instr_addr[target]);
9224       //#endif
9225     }
9226   }
9227
9228   u_int source_len = slen*4;
9229   if (dops[slen-1].itype == INTCALL && source_len > 4)
9230     // no need to treat the last instruction as compiled
9231     // as interpreter fully handles it
9232     source_len -= 4;
9233
9234   if ((u_char *)copy + source_len > (u_char *)shadow + sizeof(shadow))
9235     copy = shadow;
9236
9237   // External Branch Targets (jump_in)
9238   for(i=0;i<slen;i++)
9239   {
9240     if(dops[i].bt||i==0)
9241     {
9242       if(instr_addr[i]) // TODO - delay slots (=null)
9243       {
9244         u_int vaddr=start+i*4;
9245         u_int page=get_page(vaddr);
9246         u_int vpage=get_vpage(vaddr);
9247         literal_pool(256);
9248         {
9249           assem_debug("%p (%d) <- %8x\n",instr_addr[i],i,start+i*4);
9250           assem_debug("jump_in: %x\n",start+i*4);
9251           ll_add(jump_dirty+vpage,vaddr,out);
9252           void *entry_point = do_dirty_stub(i, source_len);
9253           ll_add_flags(jump_in+page,vaddr,state_rflags,entry_point);
9254           // If there was an existing entry in the hash table,
9255           // replace it with the new address.
9256           // Don't add new entries.  We'll insert the
9257           // ones that actually get used in check_addr().
9258           struct ht_entry *ht_bin = hash_table_get(vaddr);
9259           if (ht_bin->vaddr[0] == vaddr)
9260             ht_bin->tcaddr[0] = entry_point;
9261           if (ht_bin->vaddr[1] == vaddr)
9262             ht_bin->tcaddr[1] = entry_point;
9263         }
9264       }
9265     }
9266   }
9267   // Write out the literal pool if necessary
9268   literal_pool(0);
9269   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
9270   // Align code
9271   if(((u_int)out)&7) emit_addnop(13);
9272   #endif
9273   assert(out - (u_char *)beginning < MAX_OUTPUT_BLOCK_SIZE);
9274   //printf("shadow buffer: %p-%p\n",copy,(u_char *)copy+slen*4);
9275   memcpy(copy, source, source_len);
9276   copy += source_len;
9277
9278   end_block(beginning);
9279
9280   // If we're within 256K of the end of the buffer,
9281   // start over from the beginning. (Is 256K enough?)
9282   if (out > ndrc->translation_cache + sizeof(ndrc->translation_cache) - MAX_OUTPUT_BLOCK_SIZE)
9283     out = ndrc->translation_cache;
9284
9285   // Trap writes to any of the pages we compiled
9286   for(i=start>>12;i<=(start+slen*4)>>12;i++) {
9287     invalid_code[i]=0;
9288   }
9289   inv_code_start=inv_code_end=~0;
9290
9291   // for PCSX we need to mark all mirrors too
9292   if(get_page(start)<(RAM_SIZE>>12))
9293     for(i=start>>12;i<=(start+slen*4)>>12;i++)
9294       invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]=
9295       invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]=
9296       invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0;
9297
9298   /* Pass 10 - Free memory by expiring oldest blocks */
9299
9300   int end=(((out-ndrc->translation_cache)>>(TARGET_SIZE_2-16))+16384)&65535;
9301   while(expirep!=end)
9302   {
9303     int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
9304     uintptr_t base_offs = ((uintptr_t)(expirep >> 13) << shift); // Base offset of this block
9305     uintptr_t base_offs_s = base_offs >> shift;
9306     inv_debug("EXP: Phase %d\n",expirep);
9307     switch((expirep>>11)&3)
9308     {
9309       case 0:
9310         // Clear jump_in and jump_dirty
9311         ll_remove_matching_addrs(jump_in+(expirep&2047),base_offs_s,shift);
9312         ll_remove_matching_addrs(jump_dirty+(expirep&2047),base_offs_s,shift);
9313         ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base_offs_s,shift);
9314         ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base_offs_s,shift);
9315         break;
9316       case 1:
9317         // Clear pointers
9318         ll_kill_pointers(jump_out[expirep&2047],base_offs_s,shift);
9319         ll_kill_pointers(jump_out[(expirep&2047)+2048],base_offs_s,shift);
9320         break;
9321       case 2:
9322         // Clear hash table
9323         for(i=0;i<32;i++) {
9324           struct ht_entry *ht_bin = &hash_table[((expirep&2047)<<5)+i];
9325           uintptr_t o1 = (u_char *)ht_bin->tcaddr[1] - ndrc->translation_cache;
9326           uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
9327           if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s) {
9328             inv_debug("EXP: Remove hash %x -> %p\n",ht_bin->vaddr[1],ht_bin->tcaddr[1]);
9329             ht_bin->vaddr[1] = -1;
9330             ht_bin->tcaddr[1] = NULL;
9331           }
9332           o1 = (u_char *)ht_bin->tcaddr[0] - ndrc->translation_cache;
9333           o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
9334           if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s) {
9335             inv_debug("EXP: Remove hash %x -> %p\n",ht_bin->vaddr[0],ht_bin->tcaddr[0]);
9336             ht_bin->vaddr[0] = ht_bin->vaddr[1];
9337             ht_bin->tcaddr[0] = ht_bin->tcaddr[1];
9338             ht_bin->vaddr[1] = -1;
9339             ht_bin->tcaddr[1] = NULL;
9340           }
9341         }
9342         break;
9343       case 3:
9344         // Clear jump_out
9345         if((expirep&2047)==0)
9346           do_clear_cache();
9347         ll_remove_matching_addrs(jump_out+(expirep&2047),base_offs_s,shift);
9348         ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base_offs_s,shift);
9349         break;
9350     }
9351     expirep=(expirep+1)&65535;
9352   }
9353   return 0;
9354 }
9355
9356 // vim:shiftwidth=2:expandtab