1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2011 Ari64 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include <stdint.h> //include for uint64_t
26 #include "emu_if.h" //emulator interface
29 //#define assem_debug printf
30 //#define inv_debug printf
31 #define assem_debug(...)
32 #define inv_debug(...)
35 #include "assem_x86.h"
38 #include "assem_x64.h"
41 #include "assem_arm.h"
45 #define MAX_OUTPUT_BLOCK_SIZE 262144
46 #define CLOCK_DIVIDER 2
50 signed char regmap_entry[HOST_REGS];
51 signed char regmap[HOST_REGS];
60 uint64_t constmap[HOST_REGS];
68 struct ll_entry *next;
74 char insn[MAXBLOCK][10];
75 u_char itype[MAXBLOCK];
76 u_char opcode[MAXBLOCK];
77 u_char opcode2[MAXBLOCK];
85 u_char dep1[MAXBLOCK];
86 u_char dep2[MAXBLOCK];
88 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
89 static uint64_t gte_rt[MAXBLOCK];
90 static uint64_t gte_unneeded[MAXBLOCK];
91 static int gte_reads_flags; // gte flag read encountered
94 char likely[MAXBLOCK];
97 uint64_t unneeded_reg[MAXBLOCK];
98 uint64_t unneeded_reg_upper[MAXBLOCK];
99 uint64_t branch_unneeded_reg[MAXBLOCK];
100 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
101 uint64_t p32[MAXBLOCK];
102 uint64_t pr32[MAXBLOCK];
103 signed char regmap_pre[MAXBLOCK][HOST_REGS];
104 signed char regmap[MAXBLOCK][HOST_REGS];
105 signed char regmap_entry[MAXBLOCK][HOST_REGS];
106 uint64_t constmap[MAXBLOCK][HOST_REGS];
107 struct regstat regs[MAXBLOCK];
108 struct regstat branch_regs[MAXBLOCK];
109 signed char minimum_free_regs[MAXBLOCK];
110 u_int needed_reg[MAXBLOCK];
111 uint64_t requires_32bit[MAXBLOCK];
112 u_int wont_dirty[MAXBLOCK];
113 u_int will_dirty[MAXBLOCK];
116 u_int instr_addr[MAXBLOCK];
117 u_int link_addr[MAXBLOCK][3];
119 u_int stubs[MAXBLOCK*3][8];
121 u_int literals[1024][2];
126 struct ll_entry *jump_in[4096];
127 struct ll_entry *jump_out[4096];
128 struct ll_entry *jump_dirty[4096];
129 u_int hash_table[65536][4] __attribute__((aligned(16)));
130 char shadow[1048576] __attribute__((aligned(16)));
136 static const u_int using_tlb=0;
138 static u_int sp_in_mirror;
139 u_int stop_after_jal;
140 extern u_char restore_candidate[512];
141 extern int cycle_count;
143 /* registers that may be allocated */
145 #define HIREG 32 // hi
146 #define LOREG 33 // lo
147 #define FSREG 34 // FPU status (FCSR)
148 #define CSREG 35 // Coprocessor status
149 #define CCREG 36 // Cycle count
150 #define INVCP 37 // Pointer to invalid_code
151 #define MMREG 38 // Pointer to memory_map
152 #define ROREG 39 // ram offset (if rdram!=0x80000000)
154 #define FTEMP 40 // FPU temporary register
155 #define PTEMP 41 // Prefetch temporary register
156 #define TLREG 42 // TLB mapping offset
157 #define RHASH 43 // Return address hash
158 #define RHTBL 44 // Return address hash table address
159 #define RTEMP 45 // JR/JALR address register
161 #define AGEN1 46 // Address generation temporary register
162 #define AGEN2 47 // Address generation temporary register
163 #define MGEN1 48 // Maptable address generation temporary register
164 #define MGEN2 49 // Maptable address generation temporary register
165 #define BTREG 50 // Branch target temporary register
167 /* instruction types */
168 #define NOP 0 // No operation
169 #define LOAD 1 // Load
170 #define STORE 2 // Store
171 #define LOADLR 3 // Unaligned load
172 #define STORELR 4 // Unaligned store
173 #define MOV 5 // Move
174 #define ALU 6 // Arithmetic/logic
175 #define MULTDIV 7 // Multiply/divide
176 #define SHIFT 8 // Shift by register
177 #define SHIFTIMM 9// Shift by immediate
178 #define IMM16 10 // 16-bit immediate
179 #define RJUMP 11 // Unconditional jump to register
180 #define UJUMP 12 // Unconditional jump
181 #define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
182 #define SJUMP 14 // Conditional branch (regimm format)
183 #define COP0 15 // Coprocessor 0
184 #define COP1 16 // Coprocessor 1
185 #define C1LS 17 // Coprocessor 1 load/store
186 #define FJUMP 18 // Conditional branch (floating point)
187 #define FLOAT 19 // Floating point unit
188 #define FCONV 20 // Convert integer to float
189 #define FCOMP 21 // Floating point compare (sets FSREG)
190 #define SYSCALL 22// SYSCALL
191 #define OTHER 23 // Other
192 #define SPAN 24 // Branch/delay slot spans 2 pages
193 #define NI 25 // Not implemented
194 #define HLECALL 26// PCSX fake opcodes for HLE
195 #define COP2 27 // Coprocessor 2 move
196 #define C2LS 28 // Coprocessor 2 load/store
197 #define C2OP 29 // Coprocessor 2 operation
198 #define INTCALL 30// Call interpreter to handle rare corner cases
207 #define LOADBU_STUB 7
208 #define LOADHU_STUB 8
209 #define STOREB_STUB 9
210 #define STOREH_STUB 10
211 #define STOREW_STUB 11
212 #define STORED_STUB 12
213 #define STORELR_STUB 13
214 #define INVCODE_STUB 14
222 int new_recompile_block(int addr);
223 void *get_addr_ht(u_int vaddr);
224 void invalidate_block(u_int block);
225 void invalidate_addr(u_int addr);
226 void remove_hash(int vaddr);
229 void dyna_linker_ds();
231 void verify_code_vm();
232 void verify_code_ds();
235 void fp_exception_ds();
237 void jump_syscall_hle();
241 void new_dyna_leave();
246 void read_nomem_new();
247 void read_nomemb_new();
248 void read_nomemh_new();
249 void read_nomemd_new();
250 void write_nomem_new();
251 void write_nomemb_new();
252 void write_nomemh_new();
253 void write_nomemd_new();
254 void write_rdram_new();
255 void write_rdramb_new();
256 void write_rdramh_new();
257 void write_rdramd_new();
258 extern u_int memory_map[1048576];
260 // Needed by assembler
261 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
262 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
263 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
264 void load_all_regs(signed char i_regmap[]);
265 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
266 void load_regs_entry(int t);
267 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
271 //#define DEBUG_CYCLE_COUNT 1
273 static void tlb_hacks()
277 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
281 switch (ROM_HEADER->Country_code&0xFF)
293 // Unknown country code
297 u_int rom_addr=(u_int)rom;
299 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
300 // in the lower 4G of memory to use this hack. Copy it if necessary.
301 if((void *)rom>(void *)0xffffffff) {
302 munmap(ROM_COPY, 67108864);
303 if(mmap(ROM_COPY, 12582912,
304 PROT_READ | PROT_WRITE,
305 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
306 -1, 0) <= 0) {printf("mmap() failed\n");}
307 memcpy(ROM_COPY,rom,12582912);
308 rom_addr=(u_int)ROM_COPY;
312 for(n=0x7F000;n<0x80000;n++) {
313 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
320 static u_int get_page(u_int vaddr)
323 u_int page=(vaddr^0x80000000)>>12;
325 u_int page=vaddr&~0xe0000000;
326 if (page < 0x1000000)
327 page &= ~0x0e00000; // RAM mirrors
331 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
333 if(page>2048) page=2048+(page&2047);
337 static u_int get_vpage(u_int vaddr)
339 u_int vpage=(vaddr^0x80000000)>>12;
341 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
343 if(vpage>2048) vpage=2048+(vpage&2047);
347 // Get address from virtual address
348 // This is called from the recompiled JR/JALR instructions
349 void *get_addr(u_int vaddr)
351 u_int page=get_page(vaddr);
352 u_int vpage=get_vpage(vaddr);
353 struct ll_entry *head;
354 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
357 if(head->vaddr==vaddr&&head->reg32==0) {
358 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
359 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
362 ht_bin[1]=(int)head->addr;
368 head=jump_dirty[vpage];
370 if(head->vaddr==vaddr&&head->reg32==0) {
371 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
372 // Don't restore blocks which are about to expire from the cache
373 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
374 if(verify_dirty(head->addr)) {
375 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
376 invalid_code[vaddr>>12]=0;
377 inv_code_start=inv_code_end=~0;
378 memory_map[vaddr>>12]|=0x40000000;
381 if(tlb_LUT_r[vaddr>>12]) {
382 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
383 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
386 restore_candidate[vpage>>3]|=1<<(vpage&7);
388 else restore_candidate[page>>3]|=1<<(page&7);
389 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
390 if(ht_bin[0]==vaddr) {
391 ht_bin[1]=(int)head->addr; // Replace existing entry
397 ht_bin[1]=(int)head->addr;
405 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
406 int r=new_recompile_block(vaddr);
407 if(r==0) return get_addr(vaddr);
408 // Execute in unmapped page, generate pagefault execption
410 Cause=(vaddr<<31)|0x8;
411 EPC=(vaddr&1)?vaddr-5:vaddr;
413 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
414 EntryHi=BadVAddr&0xFFFFE000;
415 return get_addr_ht(0x80000000);
417 // Look up address in hash table first
418 void *get_addr_ht(u_int vaddr)
420 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
421 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
422 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
423 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
424 return get_addr(vaddr);
427 void *get_addr_32(u_int vaddr,u_int flags)
430 return get_addr(vaddr);
432 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
433 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
434 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
435 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
436 u_int page=get_page(vaddr);
437 u_int vpage=get_vpage(vaddr);
438 struct ll_entry *head;
441 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
442 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
444 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
446 ht_bin[1]=(int)head->addr;
448 }else if(ht_bin[2]==-1) {
449 ht_bin[3]=(int)head->addr;
452 //ht_bin[3]=ht_bin[1];
453 //ht_bin[2]=ht_bin[0];
454 //ht_bin[1]=(int)head->addr;
461 head=jump_dirty[vpage];
463 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
464 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
465 // Don't restore blocks which are about to expire from the cache
466 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
467 if(verify_dirty(head->addr)) {
468 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
469 invalid_code[vaddr>>12]=0;
470 inv_code_start=inv_code_end=~0;
471 memory_map[vaddr>>12]|=0x40000000;
474 if(tlb_LUT_r[vaddr>>12]) {
475 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
476 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
479 restore_candidate[vpage>>3]|=1<<(vpage&7);
481 else restore_candidate[page>>3]|=1<<(page&7);
483 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
485 ht_bin[1]=(int)head->addr;
487 }else if(ht_bin[2]==-1) {
488 ht_bin[3]=(int)head->addr;
491 //ht_bin[3]=ht_bin[1];
492 //ht_bin[2]=ht_bin[0];
493 //ht_bin[1]=(int)head->addr;
501 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
502 int r=new_recompile_block(vaddr);
503 if(r==0) return get_addr(vaddr);
504 // Execute in unmapped page, generate pagefault execption
506 Cause=(vaddr<<31)|0x8;
507 EPC=(vaddr&1)?vaddr-5:vaddr;
509 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
510 EntryHi=BadVAddr&0xFFFFE000;
511 return get_addr_ht(0x80000000);
515 void clear_all_regs(signed char regmap[])
518 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
521 signed char get_reg(signed char regmap[],int r)
524 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map[hr]==r) return hr;
528 // Find a register that is available for two consecutive cycles
529 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
532 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr;
536 int count_free_regs(signed char regmap[])
540 for(hr=0;hr<HOST_REGS;hr++)
542 if(hr!=EXCLUDE_REG) {
543 if(regmap[hr]<0) count++;
549 void dirty_reg(struct regstat *cur,signed char reg)
553 for (hr=0;hr<HOST_REGS;hr++) {
554 if((cur->regmap[hr]&63)==reg) {
560 // If we dirty the lower half of a 64 bit register which is now being
561 // sign-extended, we need to dump the upper half.
562 // Note: Do this only after completion of the instruction, because
563 // some instructions may need to read the full 64-bit value even if
564 // overwriting it (eg SLTI, DSRA32).
565 static void flush_dirty_uppers(struct regstat *cur)
568 for (hr=0;hr<HOST_REGS;hr++) {
569 if((cur->dirty>>hr)&1) {
572 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
577 void set_const(struct regstat *cur,signed char reg,uint64_t value)
581 for (hr=0;hr<HOST_REGS;hr++) {
582 if(cur->regmap[hr]==reg) {
584 cur->constmap[hr]=value;
586 else if((cur->regmap[hr]^64)==reg) {
588 cur->constmap[hr]=value>>32;
593 void clear_const(struct regstat *cur,signed char reg)
597 for (hr=0;hr<HOST_REGS;hr++) {
598 if((cur->regmap[hr]&63)==reg) {
599 cur->isconst&=~(1<<hr);
604 int is_const(struct regstat *cur,signed char reg)
609 for (hr=0;hr<HOST_REGS;hr++) {
610 if((cur->regmap[hr]&63)==reg) {
611 return (cur->isconst>>hr)&1;
616 uint64_t get_const(struct regstat *cur,signed char reg)
620 for (hr=0;hr<HOST_REGS;hr++) {
621 if(cur->regmap[hr]==reg) {
622 return cur->constmap[hr];
625 printf("Unknown constant in r%d\n",reg);
629 // Least soon needed registers
630 // Look at the next ten instructions and see which registers
631 // will be used. Try not to reallocate these.
632 void lsn(u_char hsn[], int i, int *preferred_reg)
642 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
644 // Don't go past an unconditonal jump
651 if(rs1[i+j]) hsn[rs1[i+j]]=j;
652 if(rs2[i+j]) hsn[rs2[i+j]]=j;
653 if(rt1[i+j]) hsn[rt1[i+j]]=j;
654 if(rt2[i+j]) hsn[rt2[i+j]]=j;
655 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
656 // Stores can allocate zero
660 // On some architectures stores need invc_ptr
661 #if defined(HOST_IMM8)
662 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
666 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
674 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
676 // Follow first branch
677 int t=(ba[i+b]-start)>>2;
678 j=7-b;if(t+j>=slen) j=slen-t-1;
681 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
682 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
683 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
684 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
687 // TODO: preferred register based on backward branch
689 // Delay slot should preferably not overwrite branch conditions or cycle count
690 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
691 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
692 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
698 // Coprocessor load/store needs FTEMP, even if not declared
699 if(itype[i]==C1LS||itype[i]==C2LS) {
702 // Load L/R also uses FTEMP as a temporary register
703 if(itype[i]==LOADLR) {
706 // Also SWL/SWR/SDL/SDR
707 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
710 // Don't remove the TLB registers either
711 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
714 // Don't remove the miniht registers
715 if(itype[i]==UJUMP||itype[i]==RJUMP)
722 // We only want to allocate registers if we're going to use them again soon
723 int needed_again(int r, int i)
729 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
731 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
732 return 0; // Don't need any registers if exiting the block
740 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
742 // Don't go past an unconditonal jump
746 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
753 if(rs1[i+j]==r) rn=j;
754 if(rs2[i+j]==r) rn=j;
755 if((unneeded_reg[i+j]>>r)&1) rn=10;
756 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
764 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
766 // Follow first branch
768 int t=(ba[i+b]-start)>>2;
769 j=7-b;if(t+j>=slen) j=slen-t-1;
772 if(!((unneeded_reg[t+j]>>r)&1)) {
773 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
774 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
784 // Try to match register allocations at the end of a loop with those
786 int loop_reg(int i, int r, int hr)
795 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
797 // Don't go past an unconditonal jump
804 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
809 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
810 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
811 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
813 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
815 int t=(ba[i+k]-start)>>2;
816 int reg=get_reg(regs[t].regmap_entry,r);
817 if(reg>=0) return reg;
818 //reg=get_reg(regs[t+1].regmap_entry,r);
819 //if(reg>=0) return reg;
827 // Allocate every register, preserving source/target regs
828 void alloc_all(struct regstat *cur,int i)
832 for(hr=0;hr<HOST_REGS;hr++) {
833 if(hr!=EXCLUDE_REG) {
834 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
835 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
838 cur->dirty&=~(1<<hr);
841 if((cur->regmap[hr]&63)==0)
844 cur->dirty&=~(1<<hr);
851 void div64(int64_t dividend,int64_t divisor)
855 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
856 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
858 void divu64(uint64_t dividend,uint64_t divisor)
862 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
863 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
866 void mult64(uint64_t m1,uint64_t m2)
868 unsigned long long int op1, op2, op3, op4;
869 unsigned long long int result1, result2, result3, result4;
870 unsigned long long int temp1, temp2, temp3, temp4;
886 op1 = op2 & 0xFFFFFFFF;
887 op2 = (op2 >> 32) & 0xFFFFFFFF;
888 op3 = op4 & 0xFFFFFFFF;
889 op4 = (op4 >> 32) & 0xFFFFFFFF;
892 temp2 = (temp1 >> 32) + op1 * op4;
894 temp4 = (temp3 >> 32) + op2 * op4;
896 result1 = temp1 & 0xFFFFFFFF;
897 result2 = temp2 + (temp3 & 0xFFFFFFFF);
898 result3 = (result2 >> 32) + temp4;
899 result4 = (result3 >> 32);
901 lo = result1 | (result2 << 32);
902 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
911 void multu64(uint64_t m1,uint64_t m2)
913 unsigned long long int op1, op2, op3, op4;
914 unsigned long long int result1, result2, result3, result4;
915 unsigned long long int temp1, temp2, temp3, temp4;
917 op1 = m1 & 0xFFFFFFFF;
918 op2 = (m1 >> 32) & 0xFFFFFFFF;
919 op3 = m2 & 0xFFFFFFFF;
920 op4 = (m2 >> 32) & 0xFFFFFFFF;
923 temp2 = (temp1 >> 32) + op1 * op4;
925 temp4 = (temp3 >> 32) + op2 * op4;
927 result1 = temp1 & 0xFFFFFFFF;
928 result2 = temp2 + (temp3 & 0xFFFFFFFF);
929 result3 = (result2 >> 32) + temp4;
930 result4 = (result3 >> 32);
932 lo = result1 | (result2 << 32);
933 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
935 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
936 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
939 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
947 else original=loaded;
950 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
953 original>>=64-(bits^56);
954 original<<=64-(bits^56);
958 else original=loaded;
964 #include "assem_x86.c"
967 #include "assem_x64.c"
970 #include "assem_arm.c"
973 // Add virtual address mapping to linked list
974 void ll_add(struct ll_entry **head,int vaddr,void *addr)
976 struct ll_entry *new_entry;
977 new_entry=malloc(sizeof(struct ll_entry));
978 assert(new_entry!=NULL);
979 new_entry->vaddr=vaddr;
981 new_entry->addr=addr;
982 new_entry->next=*head;
986 // Add virtual address mapping for 32-bit compiled block
987 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
989 ll_add(head,vaddr,addr);
991 (*head)->reg32=reg32;
995 // Check if an address is already compiled
996 // but don't return addresses which are about to expire from the cache
997 void *check_addr(u_int vaddr)
999 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
1000 if(ht_bin[0]==vaddr) {
1001 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1002 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
1004 if(ht_bin[2]==vaddr) {
1005 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1006 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1008 u_int page=get_page(vaddr);
1009 struct ll_entry *head;
1012 if(head->vaddr==vaddr&&head->reg32==0) {
1013 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1014 // Update existing entry with current address
1015 if(ht_bin[0]==vaddr) {
1016 ht_bin[1]=(int)head->addr;
1019 if(ht_bin[2]==vaddr) {
1020 ht_bin[3]=(int)head->addr;
1023 // Insert into hash table with low priority.
1024 // Don't evict existing entries, as they are probably
1025 // addresses that are being accessed frequently.
1027 ht_bin[1]=(int)head->addr;
1029 }else if(ht_bin[2]==-1) {
1030 ht_bin[3]=(int)head->addr;
1041 void remove_hash(int vaddr)
1043 //printf("remove hash: %x\n",vaddr);
1044 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1045 if(ht_bin[2]==vaddr) {
1046 ht_bin[2]=ht_bin[3]=-1;
1048 if(ht_bin[0]==vaddr) {
1049 ht_bin[0]=ht_bin[2];
1050 ht_bin[1]=ht_bin[3];
1051 ht_bin[2]=ht_bin[3]=-1;
1055 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1057 struct ll_entry *next;
1059 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1060 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1062 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1063 remove_hash((*head)->vaddr);
1070 head=&((*head)->next);
1075 // Remove all entries from linked list
1076 void ll_clear(struct ll_entry **head)
1078 struct ll_entry *cur;
1079 struct ll_entry *next;
1090 // Dereference the pointers and remove if it matches
1091 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1094 int ptr=get_pointer(head->addr);
1095 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1096 if(((ptr>>shift)==(addr>>shift)) ||
1097 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1099 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1100 u_int host_addr=(u_int)kill_pointer(head->addr);
1102 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1109 // This is called when we write to a compiled block (see do_invstub)
1110 void invalidate_page(u_int page)
1112 struct ll_entry *head;
1113 struct ll_entry *next;
1117 inv_debug("INVALIDATE: %x\n",head->vaddr);
1118 remove_hash(head->vaddr);
1123 head=jump_out[page];
1126 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1127 u_int host_addr=(u_int)kill_pointer(head->addr);
1129 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1137 static void invalidate_block_range(u_int block, u_int first, u_int last)
1139 u_int page=get_page(block<<12);
1140 //printf("first=%d last=%d\n",first,last);
1141 invalidate_page(page);
1142 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1143 assert(last<page+5);
1144 // Invalidate the adjacent pages if a block crosses a 4K boundary
1146 invalidate_page(first);
1149 for(first=page+1;first<last;first++) {
1150 invalidate_page(first);
1156 // Don't trap writes
1157 invalid_code[block]=1;
1159 // If there is a valid TLB entry for this page, remove write protect
1160 if(tlb_LUT_w[block]) {
1161 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1162 // CHECK: Is this right?
1163 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1164 u_int real_block=tlb_LUT_w[block]>>12;
1165 invalid_code[real_block]=1;
1166 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1168 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1172 memset(mini_ht,-1,sizeof(mini_ht));
1176 void invalidate_block(u_int block)
1178 u_int page=get_page(block<<12);
1179 u_int vpage=get_vpage(block<<12);
1180 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1181 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1184 struct ll_entry *head;
1185 head=jump_dirty[vpage];
1186 //printf("page=%d vpage=%d\n",page,vpage);
1189 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1190 get_bounds((int)head->addr,&start,&end);
1191 //printf("start: %x end: %x\n",start,end);
1192 if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
1193 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1194 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1195 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1199 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1200 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1201 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1202 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1209 invalidate_block_range(block,first,last);
1212 void invalidate_addr(u_int addr)
1216 // this check is done by the caller
1217 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
1218 u_int page=get_page(addr);
1219 if(page<2048) { // RAM
1220 struct ll_entry *head;
1221 u_int addr_min=~0, addr_max=0;
1222 int mask=RAM_SIZE-1;
1224 inv_code_start=addr&~0xfff;
1225 inv_code_end=addr|0xfff;
1228 // must check previous page too because of spans..
1230 inv_code_start-=0x1000;
1232 for(;pg1<=page;pg1++) {
1233 for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
1235 get_bounds((int)head->addr,&start,&end);
1236 if((start&mask)<=(addr&mask)&&(addr&mask)<(end&mask)) {
1237 if(start<addr_min) addr_min=start;
1238 if(end>addr_max) addr_max=end;
1240 else if(addr<start) {
1241 if(start<inv_code_end)
1242 inv_code_end=start-1;
1245 if(end>inv_code_start)
1251 inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1252 inv_code_start=inv_code_end=~0;
1253 invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1257 inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);//rhits);
1260 if(page!=0) // FIXME: don't know what's up with page 0 (Klonoa)
1264 invalidate_block(addr>>12);
1267 // This is called when loading a save state.
1268 // Anything could have changed, so invalidate everything.
1269 void invalidate_all_pages()
1272 for(page=0;page<4096;page++)
1273 invalidate_page(page);
1274 for(page=0;page<1048576;page++)
1275 if(!invalid_code[page]) {
1276 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1277 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1280 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1283 memset(mini_ht,-1,sizeof(mini_ht));
1287 for(page=0;page<0x100000;page++) {
1288 if(tlb_LUT_r[page]) {
1289 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1290 if(!tlb_LUT_w[page]||!invalid_code[page])
1291 memory_map[page]|=0x40000000; // Write protect
1293 else memory_map[page]=-1;
1294 if(page==0x80000) page=0xC0000;
1300 // Add an entry to jump_out after making a link
1301 void add_link(u_int vaddr,void *src)
1303 u_int page=get_page(vaddr);
1304 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1305 int *ptr=(int *)(src+4);
1306 assert((*ptr&0x0fff0000)==0x059f0000);
1307 ll_add(jump_out+page,vaddr,src);
1308 //int ptr=get_pointer(src);
1309 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1312 // If a code block was found to be unmodified (bit was set in
1313 // restore_candidate) and it remains unmodified (bit is clear
1314 // in invalid_code) then move the entries for that 4K page from
1315 // the dirty list to the clean list.
1316 void clean_blocks(u_int page)
1318 struct ll_entry *head;
1319 inv_debug("INV: clean_blocks page=%d\n",page);
1320 head=jump_dirty[page];
1322 if(!invalid_code[head->vaddr>>12]) {
1323 // Don't restore blocks which are about to expire from the cache
1324 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1326 if(verify_dirty((int)head->addr)) {
1327 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1330 get_bounds((int)head->addr,&start,&end);
1331 if(start-(u_int)rdram<RAM_SIZE) {
1332 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1333 inv|=invalid_code[i];
1336 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1337 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1338 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1339 if(addr<start||addr>=end) inv=1;
1341 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1345 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1346 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1349 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1351 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1352 //printf("page=%x, addr=%x\n",page,head->vaddr);
1353 //assert(head->vaddr>>12==(page|0x80000));
1354 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1355 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1357 if(ht_bin[0]==head->vaddr) {
1358 ht_bin[1]=(int)clean_addr; // Replace existing entry
1360 if(ht_bin[2]==head->vaddr) {
1361 ht_bin[3]=(int)clean_addr; // Replace existing entry
1374 void mov_alloc(struct regstat *current,int i)
1376 // Note: Don't need to actually alloc the source registers
1377 if((~current->is32>>rs1[i])&1) {
1378 //alloc_reg64(current,i,rs1[i]);
1379 alloc_reg64(current,i,rt1[i]);
1380 current->is32&=~(1LL<<rt1[i]);
1382 //alloc_reg(current,i,rs1[i]);
1383 alloc_reg(current,i,rt1[i]);
1384 current->is32|=(1LL<<rt1[i]);
1386 clear_const(current,rs1[i]);
1387 clear_const(current,rt1[i]);
1388 dirty_reg(current,rt1[i]);
1391 void shiftimm_alloc(struct regstat *current,int i)
1393 clear_const(current,rs1[i]);
1394 clear_const(current,rt1[i]);
1395 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1398 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1400 alloc_reg(current,i,rt1[i]);
1401 current->is32|=1LL<<rt1[i];
1402 dirty_reg(current,rt1[i]);
1405 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1408 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1409 alloc_reg64(current,i,rt1[i]);
1410 current->is32&=~(1LL<<rt1[i]);
1411 dirty_reg(current,rt1[i]);
1414 if(opcode2[i]==0x3c) // DSLL32
1417 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1418 alloc_reg64(current,i,rt1[i]);
1419 current->is32&=~(1LL<<rt1[i]);
1420 dirty_reg(current,rt1[i]);
1423 if(opcode2[i]==0x3e) // DSRL32
1426 alloc_reg64(current,i,rs1[i]);
1428 alloc_reg64(current,i,rt1[i]);
1429 current->is32&=~(1LL<<rt1[i]);
1431 alloc_reg(current,i,rt1[i]);
1432 current->is32|=1LL<<rt1[i];
1434 dirty_reg(current,rt1[i]);
1437 if(opcode2[i]==0x3f) // DSRA32
1440 alloc_reg64(current,i,rs1[i]);
1441 alloc_reg(current,i,rt1[i]);
1442 current->is32|=1LL<<rt1[i];
1443 dirty_reg(current,rt1[i]);
1448 void shift_alloc(struct regstat *current,int i)
1451 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1453 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1454 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1455 alloc_reg(current,i,rt1[i]);
1456 if(rt1[i]==rs2[i]) {
1457 alloc_reg_temp(current,i,-1);
1458 minimum_free_regs[i]=1;
1460 current->is32|=1LL<<rt1[i];
1461 } else { // DSLLV/DSRLV/DSRAV
1462 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1463 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1464 alloc_reg64(current,i,rt1[i]);
1465 current->is32&=~(1LL<<rt1[i]);
1466 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1468 alloc_reg_temp(current,i,-1);
1469 minimum_free_regs[i]=1;
1472 clear_const(current,rs1[i]);
1473 clear_const(current,rs2[i]);
1474 clear_const(current,rt1[i]);
1475 dirty_reg(current,rt1[i]);
1479 void alu_alloc(struct regstat *current,int i)
1481 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1483 if(rs1[i]&&rs2[i]) {
1484 alloc_reg(current,i,rs1[i]);
1485 alloc_reg(current,i,rs2[i]);
1488 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1489 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1491 alloc_reg(current,i,rt1[i]);
1493 current->is32|=1LL<<rt1[i];
1495 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1497 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1499 alloc_reg64(current,i,rs1[i]);
1500 alloc_reg64(current,i,rs2[i]);
1501 alloc_reg(current,i,rt1[i]);
1503 alloc_reg(current,i,rs1[i]);
1504 alloc_reg(current,i,rs2[i]);
1505 alloc_reg(current,i,rt1[i]);
1508 current->is32|=1LL<<rt1[i];
1510 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1512 if(rs1[i]&&rs2[i]) {
1513 alloc_reg(current,i,rs1[i]);
1514 alloc_reg(current,i,rs2[i]);
1518 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1519 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1521 alloc_reg(current,i,rt1[i]);
1522 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1524 if(!((current->uu>>rt1[i])&1)) {
1525 alloc_reg64(current,i,rt1[i]);
1527 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1528 if(rs1[i]&&rs2[i]) {
1529 alloc_reg64(current,i,rs1[i]);
1530 alloc_reg64(current,i,rs2[i]);
1534 // Is is really worth it to keep 64-bit values in registers?
1536 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1537 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1541 current->is32&=~(1LL<<rt1[i]);
1543 current->is32|=1LL<<rt1[i];
1547 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1549 if(rs1[i]&&rs2[i]) {
1550 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1551 alloc_reg64(current,i,rs1[i]);
1552 alloc_reg64(current,i,rs2[i]);
1553 alloc_reg64(current,i,rt1[i]);
1555 alloc_reg(current,i,rs1[i]);
1556 alloc_reg(current,i,rs2[i]);
1557 alloc_reg(current,i,rt1[i]);
1561 alloc_reg(current,i,rt1[i]);
1562 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1563 // DADD used as move, or zeroing
1564 // If we have a 64-bit source, then make the target 64 bits too
1565 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1566 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1567 alloc_reg64(current,i,rt1[i]);
1568 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1569 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1570 alloc_reg64(current,i,rt1[i]);
1572 if(opcode2[i]>=0x2e&&rs2[i]) {
1573 // DSUB used as negation - 64-bit result
1574 // If we have a 32-bit register, extend it to 64 bits
1575 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1576 alloc_reg64(current,i,rt1[i]);
1580 if(rs1[i]&&rs2[i]) {
1581 current->is32&=~(1LL<<rt1[i]);
1583 current->is32&=~(1LL<<rt1[i]);
1584 if((current->is32>>rs1[i])&1)
1585 current->is32|=1LL<<rt1[i];
1587 current->is32&=~(1LL<<rt1[i]);
1588 if((current->is32>>rs2[i])&1)
1589 current->is32|=1LL<<rt1[i];
1591 current->is32|=1LL<<rt1[i];
1595 clear_const(current,rs1[i]);
1596 clear_const(current,rs2[i]);
1597 clear_const(current,rt1[i]);
1598 dirty_reg(current,rt1[i]);
1601 void imm16_alloc(struct regstat *current,int i)
1603 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1605 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1606 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1607 current->is32&=~(1LL<<rt1[i]);
1608 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1609 // TODO: Could preserve the 32-bit flag if the immediate is zero
1610 alloc_reg64(current,i,rt1[i]);
1611 alloc_reg64(current,i,rs1[i]);
1613 clear_const(current,rs1[i]);
1614 clear_const(current,rt1[i]);
1616 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1617 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1618 current->is32|=1LL<<rt1[i];
1619 clear_const(current,rs1[i]);
1620 clear_const(current,rt1[i]);
1622 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1623 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1624 if(rs1[i]!=rt1[i]) {
1625 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1626 alloc_reg64(current,i,rt1[i]);
1627 current->is32&=~(1LL<<rt1[i]);
1630 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1631 if(is_const(current,rs1[i])) {
1632 int v=get_const(current,rs1[i]);
1633 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1634 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1635 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1637 else clear_const(current,rt1[i]);
1639 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1640 if(is_const(current,rs1[i])) {
1641 int v=get_const(current,rs1[i]);
1642 set_const(current,rt1[i],v+imm[i]);
1644 else clear_const(current,rt1[i]);
1645 current->is32|=1LL<<rt1[i];
1648 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1649 current->is32|=1LL<<rt1[i];
1651 dirty_reg(current,rt1[i]);
1654 void load_alloc(struct regstat *current,int i)
1656 clear_const(current,rt1[i]);
1657 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1658 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1659 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1660 if(rt1[i]&&!((current->u>>rt1[i])&1)) {
1661 alloc_reg(current,i,rt1[i]);
1662 assert(get_reg(current->regmap,rt1[i])>=0);
1663 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1665 current->is32&=~(1LL<<rt1[i]);
1666 alloc_reg64(current,i,rt1[i]);
1668 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1670 current->is32&=~(1LL<<rt1[i]);
1671 alloc_reg64(current,i,rt1[i]);
1672 alloc_all(current,i);
1673 alloc_reg64(current,i,FTEMP);
1674 minimum_free_regs[i]=HOST_REGS;
1676 else current->is32|=1LL<<rt1[i];
1677 dirty_reg(current,rt1[i]);
1678 // If using TLB, need a register for pointer to the mapping table
1679 if(using_tlb) alloc_reg(current,i,TLREG);
1680 // LWL/LWR need a temporary register for the old value
1681 if(opcode[i]==0x22||opcode[i]==0x26)
1683 alloc_reg(current,i,FTEMP);
1684 alloc_reg_temp(current,i,-1);
1685 minimum_free_regs[i]=1;
1690 // Load to r0 or unneeded register (dummy load)
1691 // but we still need a register to calculate the address
1692 if(opcode[i]==0x22||opcode[i]==0x26)
1694 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1696 // If using TLB, need a register for pointer to the mapping table
1697 if(using_tlb) alloc_reg(current,i,TLREG);
1698 alloc_reg_temp(current,i,-1);
1699 minimum_free_regs[i]=1;
1700 if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1702 alloc_all(current,i);
1703 alloc_reg64(current,i,FTEMP);
1704 minimum_free_regs[i]=HOST_REGS;
1709 void store_alloc(struct regstat *current,int i)
1711 clear_const(current,rs2[i]);
1712 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1713 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1714 alloc_reg(current,i,rs2[i]);
1715 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1716 alloc_reg64(current,i,rs2[i]);
1717 if(rs2[i]) alloc_reg(current,i,FTEMP);
1719 // If using TLB, need a register for pointer to the mapping table
1720 if(using_tlb) alloc_reg(current,i,TLREG);
1721 #if defined(HOST_IMM8)
1722 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1723 else alloc_reg(current,i,INVCP);
1725 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1726 alloc_reg(current,i,FTEMP);
1728 // We need a temporary register for address generation
1729 alloc_reg_temp(current,i,-1);
1730 minimum_free_regs[i]=1;
1733 void c1ls_alloc(struct regstat *current,int i)
1735 //clear_const(current,rs1[i]); // FIXME
1736 clear_const(current,rt1[i]);
1737 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1738 alloc_reg(current,i,CSREG); // Status
1739 alloc_reg(current,i,FTEMP);
1740 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1741 alloc_reg64(current,i,FTEMP);
1743 // If using TLB, need a register for pointer to the mapping table
1744 if(using_tlb) alloc_reg(current,i,TLREG);
1745 #if defined(HOST_IMM8)
1746 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1747 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1748 alloc_reg(current,i,INVCP);
1750 // We need a temporary register for address generation
1751 alloc_reg_temp(current,i,-1);
1754 void c2ls_alloc(struct regstat *current,int i)
1756 clear_const(current,rt1[i]);
1757 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1758 alloc_reg(current,i,FTEMP);
1759 // If using TLB, need a register for pointer to the mapping table
1760 if(using_tlb) alloc_reg(current,i,TLREG);
1761 #if defined(HOST_IMM8)
1762 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1763 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1764 alloc_reg(current,i,INVCP);
1766 // We need a temporary register for address generation
1767 alloc_reg_temp(current,i,-1);
1768 minimum_free_regs[i]=1;
1771 #ifndef multdiv_alloc
1772 void multdiv_alloc(struct regstat *current,int i)
1779 // case 0x1D: DMULTU
1782 clear_const(current,rs1[i]);
1783 clear_const(current,rs2[i]);
1786 if((opcode2[i]&4)==0) // 32-bit
1788 current->u&=~(1LL<<HIREG);
1789 current->u&=~(1LL<<LOREG);
1790 alloc_reg(current,i,HIREG);
1791 alloc_reg(current,i,LOREG);
1792 alloc_reg(current,i,rs1[i]);
1793 alloc_reg(current,i,rs2[i]);
1794 current->is32|=1LL<<HIREG;
1795 current->is32|=1LL<<LOREG;
1796 dirty_reg(current,HIREG);
1797 dirty_reg(current,LOREG);
1801 current->u&=~(1LL<<HIREG);
1802 current->u&=~(1LL<<LOREG);
1803 current->uu&=~(1LL<<HIREG);
1804 current->uu&=~(1LL<<LOREG);
1805 alloc_reg64(current,i,HIREG);
1806 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1807 alloc_reg64(current,i,rs1[i]);
1808 alloc_reg64(current,i,rs2[i]);
1809 alloc_all(current,i);
1810 current->is32&=~(1LL<<HIREG);
1811 current->is32&=~(1LL<<LOREG);
1812 dirty_reg(current,HIREG);
1813 dirty_reg(current,LOREG);
1814 minimum_free_regs[i]=HOST_REGS;
1819 // Multiply by zero is zero.
1820 // MIPS does not have a divide by zero exception.
1821 // The result is undefined, we return zero.
1822 alloc_reg(current,i,HIREG);
1823 alloc_reg(current,i,LOREG);
1824 current->is32|=1LL<<HIREG;
1825 current->is32|=1LL<<LOREG;
1826 dirty_reg(current,HIREG);
1827 dirty_reg(current,LOREG);
1832 void cop0_alloc(struct regstat *current,int i)
1834 if(opcode2[i]==0) // MFC0
1837 clear_const(current,rt1[i]);
1838 alloc_all(current,i);
1839 alloc_reg(current,i,rt1[i]);
1840 current->is32|=1LL<<rt1[i];
1841 dirty_reg(current,rt1[i]);
1844 else if(opcode2[i]==4) // MTC0
1847 clear_const(current,rs1[i]);
1848 alloc_reg(current,i,rs1[i]);
1849 alloc_all(current,i);
1852 alloc_all(current,i); // FIXME: Keep r0
1854 alloc_reg(current,i,0);
1859 // TLBR/TLBWI/TLBWR/TLBP/ERET
1860 assert(opcode2[i]==0x10);
1861 alloc_all(current,i);
1863 minimum_free_regs[i]=HOST_REGS;
1866 void cop1_alloc(struct regstat *current,int i)
1868 alloc_reg(current,i,CSREG); // Load status
1869 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1872 clear_const(current,rt1[i]);
1874 alloc_reg64(current,i,rt1[i]); // DMFC1
1875 current->is32&=~(1LL<<rt1[i]);
1877 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1878 current->is32|=1LL<<rt1[i];
1880 dirty_reg(current,rt1[i]);
1882 alloc_reg_temp(current,i,-1);
1884 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1887 clear_const(current,rs1[i]);
1889 alloc_reg64(current,i,rs1[i]); // DMTC1
1891 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1892 alloc_reg_temp(current,i,-1);
1896 alloc_reg(current,i,0);
1897 alloc_reg_temp(current,i,-1);
1900 minimum_free_regs[i]=1;
1902 void fconv_alloc(struct regstat *current,int i)
1904 alloc_reg(current,i,CSREG); // Load status
1905 alloc_reg_temp(current,i,-1);
1906 minimum_free_regs[i]=1;
1908 void float_alloc(struct regstat *current,int i)
1910 alloc_reg(current,i,CSREG); // Load status
1911 alloc_reg_temp(current,i,-1);
1912 minimum_free_regs[i]=1;
1914 void c2op_alloc(struct regstat *current,int i)
1916 alloc_reg_temp(current,i,-1);
1918 void fcomp_alloc(struct regstat *current,int i)
1920 alloc_reg(current,i,CSREG); // Load status
1921 alloc_reg(current,i,FSREG); // Load flags
1922 dirty_reg(current,FSREG); // Flag will be modified
1923 alloc_reg_temp(current,i,-1);
1924 minimum_free_regs[i]=1;
1927 void syscall_alloc(struct regstat *current,int i)
1929 alloc_cc(current,i);
1930 dirty_reg(current,CCREG);
1931 alloc_all(current,i);
1932 minimum_free_regs[i]=HOST_REGS;
1936 void delayslot_alloc(struct regstat *current,int i)
1947 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1948 printf("Disabled speculative precompilation\n");
1952 imm16_alloc(current,i);
1956 load_alloc(current,i);
1960 store_alloc(current,i);
1963 alu_alloc(current,i);
1966 shift_alloc(current,i);
1969 multdiv_alloc(current,i);
1972 shiftimm_alloc(current,i);
1975 mov_alloc(current,i);
1978 cop0_alloc(current,i);
1982 cop1_alloc(current,i);
1985 c1ls_alloc(current,i);
1988 c2ls_alloc(current,i);
1991 fconv_alloc(current,i);
1994 float_alloc(current,i);
1997 fcomp_alloc(current,i);
2000 c2op_alloc(current,i);
2005 // Special case where a branch and delay slot span two pages in virtual memory
2006 static void pagespan_alloc(struct regstat *current,int i)
2009 current->wasconst=0;
2011 minimum_free_regs[i]=HOST_REGS;
2012 alloc_all(current,i);
2013 alloc_cc(current,i);
2014 dirty_reg(current,CCREG);
2015 if(opcode[i]==3) // JAL
2017 alloc_reg(current,i,31);
2018 dirty_reg(current,31);
2020 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
2022 alloc_reg(current,i,rs1[i]);
2024 alloc_reg(current,i,rt1[i]);
2025 dirty_reg(current,rt1[i]);
2028 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
2030 if(rs1[i]) alloc_reg(current,i,rs1[i]);
2031 if(rs2[i]) alloc_reg(current,i,rs2[i]);
2032 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
2034 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2035 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
2039 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
2041 if(rs1[i]) alloc_reg(current,i,rs1[i]);
2042 if(!((current->is32>>rs1[i])&1))
2044 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2048 if(opcode[i]==0x11) // BC1
2050 alloc_reg(current,i,FSREG);
2051 alloc_reg(current,i,CSREG);
2056 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
2058 stubs[stubcount][0]=type;
2059 stubs[stubcount][1]=addr;
2060 stubs[stubcount][2]=retaddr;
2061 stubs[stubcount][3]=a;
2062 stubs[stubcount][4]=b;
2063 stubs[stubcount][5]=c;
2064 stubs[stubcount][6]=d;
2065 stubs[stubcount][7]=e;
2069 // Write out a single register
2070 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2073 for(hr=0;hr<HOST_REGS;hr++) {
2074 if(hr!=EXCLUDE_REG) {
2075 if((regmap[hr]&63)==r) {
2078 emit_storereg(r,hr);
2080 if((is32>>regmap[hr])&1) {
2081 emit_sarimm(hr,31,hr);
2082 emit_storereg(r|64,hr);
2086 emit_storereg(r|64,hr);
2096 //if(!tracedebug) return 0;
2099 for(i=0;i<2097152;i++) {
2100 unsigned int temp=sum;
2103 sum^=((u_int *)rdram)[i];
2112 sum^=((u_int *)reg)[i];
2120 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2122 #ifndef DISABLE_COP1
2125 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2135 void memdebug(int i)
2137 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2138 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2141 //if(Count>=-2084597794) {
2142 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2144 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2145 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2146 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2149 printf("TRACE: %x\n",(&i)[-1]);
2153 printf("TRACE: %x \n",(&j)[10]);
2154 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2158 //printf("TRACE: %x\n",(&i)[-1]);
2161 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2163 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2166 void alu_assemble(int i,struct regstat *i_regs)
2168 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2170 signed char s1,s2,t;
2171 t=get_reg(i_regs->regmap,rt1[i]);
2173 s1=get_reg(i_regs->regmap,rs1[i]);
2174 s2=get_reg(i_regs->regmap,rs2[i]);
2175 if(rs1[i]&&rs2[i]) {
2178 if(opcode2[i]&2) emit_sub(s1,s2,t);
2179 else emit_add(s1,s2,t);
2182 if(s1>=0) emit_mov(s1,t);
2183 else emit_loadreg(rs1[i],t);
2187 if(opcode2[i]&2) emit_neg(s2,t);
2188 else emit_mov(s2,t);
2191 emit_loadreg(rs2[i],t);
2192 if(opcode2[i]&2) emit_neg(t,t);
2195 else emit_zeroreg(t);
2199 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2201 signed char s1l,s2l,s1h,s2h,tl,th;
2202 tl=get_reg(i_regs->regmap,rt1[i]);
2203 th=get_reg(i_regs->regmap,rt1[i]|64);
2205 s1l=get_reg(i_regs->regmap,rs1[i]);
2206 s2l=get_reg(i_regs->regmap,rs2[i]);
2207 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2208 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2209 if(rs1[i]&&rs2[i]) {
2212 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2213 else emit_adds(s1l,s2l,tl);
2215 #ifdef INVERTED_CARRY
2216 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2218 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2220 else emit_add(s1h,s2h,th);
2224 if(s1l>=0) emit_mov(s1l,tl);
2225 else emit_loadreg(rs1[i],tl);
2227 if(s1h>=0) emit_mov(s1h,th);
2228 else emit_loadreg(rs1[i]|64,th);
2233 if(opcode2[i]&2) emit_negs(s2l,tl);
2234 else emit_mov(s2l,tl);
2237 emit_loadreg(rs2[i],tl);
2238 if(opcode2[i]&2) emit_negs(tl,tl);
2241 #ifdef INVERTED_CARRY
2242 if(s2h>=0) emit_mov(s2h,th);
2243 else emit_loadreg(rs2[i]|64,th);
2245 emit_adcimm(-1,th); // x86 has inverted carry flag
2250 if(s2h>=0) emit_rscimm(s2h,0,th);
2252 emit_loadreg(rs2[i]|64,th);
2253 emit_rscimm(th,0,th);
2256 if(s2h>=0) emit_mov(s2h,th);
2257 else emit_loadreg(rs2[i]|64,th);
2264 if(th>=0) emit_zeroreg(th);
2269 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2271 signed char s1l,s1h,s2l,s2h,t;
2272 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2274 t=get_reg(i_regs->regmap,rt1[i]);
2277 s1l=get_reg(i_regs->regmap,rs1[i]);
2278 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2279 s2l=get_reg(i_regs->regmap,rs2[i]);
2280 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2281 if(rs2[i]==0) // rx<r0
2284 if(opcode2[i]==0x2a) // SLT
2285 emit_shrimm(s1h,31,t);
2286 else // SLTU (unsigned can not be less than zero)
2289 else if(rs1[i]==0) // r0<rx
2292 if(opcode2[i]==0x2a) // SLT
2293 emit_set_gz64_32(s2h,s2l,t);
2294 else // SLTU (set if not zero)
2295 emit_set_nz64_32(s2h,s2l,t);
2298 assert(s1l>=0);assert(s1h>=0);
2299 assert(s2l>=0);assert(s2h>=0);
2300 if(opcode2[i]==0x2a) // SLT
2301 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2303 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2307 t=get_reg(i_regs->regmap,rt1[i]);
2310 s1l=get_reg(i_regs->regmap,rs1[i]);
2311 s2l=get_reg(i_regs->regmap,rs2[i]);
2312 if(rs2[i]==0) // rx<r0
2315 if(opcode2[i]==0x2a) // SLT
2316 emit_shrimm(s1l,31,t);
2317 else // SLTU (unsigned can not be less than zero)
2320 else if(rs1[i]==0) // r0<rx
2323 if(opcode2[i]==0x2a) // SLT
2324 emit_set_gz32(s2l,t);
2325 else // SLTU (set if not zero)
2326 emit_set_nz32(s2l,t);
2329 assert(s1l>=0);assert(s2l>=0);
2330 if(opcode2[i]==0x2a) // SLT
2331 emit_set_if_less32(s1l,s2l,t);
2333 emit_set_if_carry32(s1l,s2l,t);
2339 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2341 signed char s1l,s1h,s2l,s2h,th,tl;
2342 tl=get_reg(i_regs->regmap,rt1[i]);
2343 th=get_reg(i_regs->regmap,rt1[i]|64);
2344 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2348 s1l=get_reg(i_regs->regmap,rs1[i]);
2349 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2350 s2l=get_reg(i_regs->regmap,rs2[i]);
2351 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2352 if(rs1[i]&&rs2[i]) {
2353 assert(s1l>=0);assert(s1h>=0);
2354 assert(s2l>=0);assert(s2h>=0);
2355 if(opcode2[i]==0x24) { // AND
2356 emit_and(s1l,s2l,tl);
2357 emit_and(s1h,s2h,th);
2359 if(opcode2[i]==0x25) { // OR
2360 emit_or(s1l,s2l,tl);
2361 emit_or(s1h,s2h,th);
2363 if(opcode2[i]==0x26) { // XOR
2364 emit_xor(s1l,s2l,tl);
2365 emit_xor(s1h,s2h,th);
2367 if(opcode2[i]==0x27) { // NOR
2368 emit_or(s1l,s2l,tl);
2369 emit_or(s1h,s2h,th);
2376 if(opcode2[i]==0x24) { // AND
2380 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2382 if(s1l>=0) emit_mov(s1l,tl);
2383 else emit_loadreg(rs1[i],tl);
2384 if(s1h>=0) emit_mov(s1h,th);
2385 else emit_loadreg(rs1[i]|64,th);
2389 if(s2l>=0) emit_mov(s2l,tl);
2390 else emit_loadreg(rs2[i],tl);
2391 if(s2h>=0) emit_mov(s2h,th);
2392 else emit_loadreg(rs2[i]|64,th);
2399 if(opcode2[i]==0x27) { // NOR
2401 if(s1l>=0) emit_not(s1l,tl);
2403 emit_loadreg(rs1[i],tl);
2406 if(s1h>=0) emit_not(s1h,th);
2408 emit_loadreg(rs1[i]|64,th);
2414 if(s2l>=0) emit_not(s2l,tl);
2416 emit_loadreg(rs2[i],tl);
2419 if(s2h>=0) emit_not(s2h,th);
2421 emit_loadreg(rs2[i]|64,th);
2437 s1l=get_reg(i_regs->regmap,rs1[i]);
2438 s2l=get_reg(i_regs->regmap,rs2[i]);
2439 if(rs1[i]&&rs2[i]) {
2442 if(opcode2[i]==0x24) { // AND
2443 emit_and(s1l,s2l,tl);
2445 if(opcode2[i]==0x25) { // OR
2446 emit_or(s1l,s2l,tl);
2448 if(opcode2[i]==0x26) { // XOR
2449 emit_xor(s1l,s2l,tl);
2451 if(opcode2[i]==0x27) { // NOR
2452 emit_or(s1l,s2l,tl);
2458 if(opcode2[i]==0x24) { // AND
2461 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2463 if(s1l>=0) emit_mov(s1l,tl);
2464 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2468 if(s2l>=0) emit_mov(s2l,tl);
2469 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2471 else emit_zeroreg(tl);
2473 if(opcode2[i]==0x27) { // NOR
2475 if(s1l>=0) emit_not(s1l,tl);
2477 emit_loadreg(rs1[i],tl);
2483 if(s2l>=0) emit_not(s2l,tl);
2485 emit_loadreg(rs2[i],tl);
2489 else emit_movimm(-1,tl);
2498 void imm16_assemble(int i,struct regstat *i_regs)
2500 if (opcode[i]==0x0f) { // LUI
2503 t=get_reg(i_regs->regmap,rt1[i]);
2506 if(!((i_regs->isconst>>t)&1))
2507 emit_movimm(imm[i]<<16,t);
2511 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2514 t=get_reg(i_regs->regmap,rt1[i]);
2515 s=get_reg(i_regs->regmap,rs1[i]);
2520 if(!((i_regs->isconst>>t)&1)) {
2522 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2523 emit_addimm(t,imm[i],t);
2525 if(!((i_regs->wasconst>>s)&1))
2526 emit_addimm(s,imm[i],t);
2528 emit_movimm(constmap[i][s]+imm[i],t);
2534 if(!((i_regs->isconst>>t)&1))
2535 emit_movimm(imm[i],t);
2540 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2542 signed char sh,sl,th,tl;
2543 th=get_reg(i_regs->regmap,rt1[i]|64);
2544 tl=get_reg(i_regs->regmap,rt1[i]);
2545 sh=get_reg(i_regs->regmap,rs1[i]|64);
2546 sl=get_reg(i_regs->regmap,rs1[i]);
2552 emit_addimm64_32(sh,sl,imm[i],th,tl);
2555 emit_addimm(sl,imm[i],tl);
2558 emit_movimm(imm[i],tl);
2559 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2564 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2566 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2567 signed char sh,sl,t;
2568 t=get_reg(i_regs->regmap,rt1[i]);
2569 sh=get_reg(i_regs->regmap,rs1[i]|64);
2570 sl=get_reg(i_regs->regmap,rs1[i]);
2574 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2575 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2576 if(opcode[i]==0x0a) { // SLTI
2578 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2579 emit_slti32(t,imm[i],t);
2581 emit_slti32(sl,imm[i],t);
2586 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2587 emit_sltiu32(t,imm[i],t);
2589 emit_sltiu32(sl,imm[i],t);
2594 if(opcode[i]==0x0a) // SLTI
2595 emit_slti64_32(sh,sl,imm[i],t);
2597 emit_sltiu64_32(sh,sl,imm[i],t);
2600 // SLTI(U) with r0 is just stupid,
2601 // nonetheless examples can be found
2602 if(opcode[i]==0x0a) // SLTI
2603 if(0<imm[i]) emit_movimm(1,t);
2604 else emit_zeroreg(t);
2607 if(imm[i]) emit_movimm(1,t);
2608 else emit_zeroreg(t);
2614 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2616 signed char sh,sl,th,tl;
2617 th=get_reg(i_regs->regmap,rt1[i]|64);
2618 tl=get_reg(i_regs->regmap,rt1[i]);
2619 sh=get_reg(i_regs->regmap,rs1[i]|64);
2620 sl=get_reg(i_regs->regmap,rs1[i]);
2621 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2622 if(opcode[i]==0x0c) //ANDI
2626 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2627 emit_andimm(tl,imm[i],tl);
2629 if(!((i_regs->wasconst>>sl)&1))
2630 emit_andimm(sl,imm[i],tl);
2632 emit_movimm(constmap[i][sl]&imm[i],tl);
2637 if(th>=0) emit_zeroreg(th);
2643 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2647 emit_loadreg(rs1[i]|64,th);
2652 if(opcode[i]==0x0d) //ORI
2654 emit_orimm(tl,imm[i],tl);
2656 if(!((i_regs->wasconst>>sl)&1))
2657 emit_orimm(sl,imm[i],tl);
2659 emit_movimm(constmap[i][sl]|imm[i],tl);
2661 if(opcode[i]==0x0e) //XORI
2663 emit_xorimm(tl,imm[i],tl);
2665 if(!((i_regs->wasconst>>sl)&1))
2666 emit_xorimm(sl,imm[i],tl);
2668 emit_movimm(constmap[i][sl]^imm[i],tl);
2672 emit_movimm(imm[i],tl);
2673 if(th>=0) emit_zeroreg(th);
2681 void shiftimm_assemble(int i,struct regstat *i_regs)
2683 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2687 t=get_reg(i_regs->regmap,rt1[i]);
2688 s=get_reg(i_regs->regmap,rs1[i]);
2697 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2699 if(opcode2[i]==0) // SLL
2701 emit_shlimm(s<0?t:s,imm[i],t);
2703 if(opcode2[i]==2) // SRL
2705 emit_shrimm(s<0?t:s,imm[i],t);
2707 if(opcode2[i]==3) // SRA
2709 emit_sarimm(s<0?t:s,imm[i],t);
2713 if(s>=0 && s!=t) emit_mov(s,t);
2717 //emit_storereg(rt1[i],t); //DEBUG
2720 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2723 signed char sh,sl,th,tl;
2724 th=get_reg(i_regs->regmap,rt1[i]|64);
2725 tl=get_reg(i_regs->regmap,rt1[i]);
2726 sh=get_reg(i_regs->regmap,rs1[i]|64);
2727 sl=get_reg(i_regs->regmap,rs1[i]);
2732 if(th>=0) emit_zeroreg(th);
2739 if(opcode2[i]==0x38) // DSLL
2741 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2742 emit_shlimm(sl,imm[i],tl);
2744 if(opcode2[i]==0x3a) // DSRL
2746 emit_shrdimm(sl,sh,imm[i],tl);
2747 if(th>=0) emit_shrimm(sh,imm[i],th);
2749 if(opcode2[i]==0x3b) // DSRA
2751 emit_shrdimm(sl,sh,imm[i],tl);
2752 if(th>=0) emit_sarimm(sh,imm[i],th);
2756 if(sl!=tl) emit_mov(sl,tl);
2757 if(th>=0&&sh!=th) emit_mov(sh,th);
2763 if(opcode2[i]==0x3c) // DSLL32
2766 signed char sl,tl,th;
2767 tl=get_reg(i_regs->regmap,rt1[i]);
2768 th=get_reg(i_regs->regmap,rt1[i]|64);
2769 sl=get_reg(i_regs->regmap,rs1[i]);
2778 emit_shlimm(th,imm[i]&31,th);
2783 if(opcode2[i]==0x3e) // DSRL32
2786 signed char sh,tl,th;
2787 tl=get_reg(i_regs->regmap,rt1[i]);
2788 th=get_reg(i_regs->regmap,rt1[i]|64);
2789 sh=get_reg(i_regs->regmap,rs1[i]|64);
2793 if(th>=0) emit_zeroreg(th);
2796 emit_shrimm(tl,imm[i]&31,tl);
2801 if(opcode2[i]==0x3f) // DSRA32
2805 tl=get_reg(i_regs->regmap,rt1[i]);
2806 sh=get_reg(i_regs->regmap,rs1[i]|64);
2812 emit_sarimm(tl,imm[i]&31,tl);
2819 #ifndef shift_assemble
2820 void shift_assemble(int i,struct regstat *i_regs)
2822 printf("Need shift_assemble for this architecture.\n");
2827 void load_assemble(int i,struct regstat *i_regs)
2829 int s,th,tl,addr,map=-1;
2832 int memtarget=0,c=0;
2833 int fastload_reg_override=0;
2835 th=get_reg(i_regs->regmap,rt1[i]|64);
2836 tl=get_reg(i_regs->regmap,rt1[i]);
2837 s=get_reg(i_regs->regmap,rs1[i]);
2839 for(hr=0;hr<HOST_REGS;hr++) {
2840 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2842 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2844 c=(i_regs->wasconst>>s)&1;
2846 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2847 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2850 //printf("load_assemble: c=%d\n",c);
2851 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2852 // FIXME: Even if the load is a NOP, we should check for pagefaults...
2854 if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2856 // could be FIFO, must perform the read
2858 assem_debug("(forced read)\n");
2859 tl=get_reg(i_regs->regmap,-1);
2863 if(offset||s<0||c) addr=tl;
2865 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2867 //printf("load_assemble: c=%d\n",c);
2868 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2869 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2871 if(th>=0) reglist&=~(1<<th);
2875 map=get_reg(i_regs->regmap,ROREG);
2876 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2878 //#define R29_HACK 1
2880 // Strmnnrmn's speed hack
2881 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2885 if(sp_in_mirror&&rs1[i]==29) {
2886 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
2887 emit_cmpimm(HOST_TEMPREG,RAM_SIZE);
2888 fastload_reg_override=HOST_TEMPREG;
2892 emit_cmpimm(addr,RAM_SIZE);
2894 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2895 // Hint to branch predictor that the branch is unlikely to be taken
2897 emit_jno_unlikely(0);
2905 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2906 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2907 map=get_reg(i_regs->regmap,TLREG);
2910 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2911 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2913 int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2914 if (opcode[i]==0x20) { // LB
2917 #ifdef HOST_IMM_ADDR32
2919 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2923 //emit_xorimm(addr,3,tl);
2924 //gen_tlb_addr_r(tl,map);
2925 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2927 #ifdef BIG_ENDIAN_MIPS
2928 if(!c) emit_xorimm(addr,3,tl);
2929 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2933 if(fastload_reg_override) a=fastload_reg_override;
2935 emit_movsbl_indexed_tlb(x,a,map,tl);
2939 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2942 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2944 if (opcode[i]==0x21) { // LH
2947 #ifdef HOST_IMM_ADDR32
2949 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2954 #ifdef BIG_ENDIAN_MIPS
2955 if(!c) emit_xorimm(addr,2,tl);
2956 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2960 if(fastload_reg_override) a=fastload_reg_override;
2962 //emit_movswl_indexed_tlb(x,tl,map,tl);
2965 gen_tlb_addr_r(a,map);
2966 emit_movswl_indexed(x,a,tl);
2969 emit_movswl_indexed(x,a,tl);
2971 emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2977 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2980 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2982 if (opcode[i]==0x23) { // LW
2986 if(fastload_reg_override) a=fastload_reg_override;
2987 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2988 #ifdef HOST_IMM_ADDR32
2990 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2993 emit_readword_indexed_tlb(0,a,map,tl);
2996 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2999 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3001 if (opcode[i]==0x24) { // LBU
3004 #ifdef HOST_IMM_ADDR32
3006 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
3010 //emit_xorimm(addr,3,tl);
3011 //gen_tlb_addr_r(tl,map);
3012 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
3014 #ifdef BIG_ENDIAN_MIPS
3015 if(!c) emit_xorimm(addr,3,tl);
3016 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3020 if(fastload_reg_override) a=fastload_reg_override;
3022 emit_movzbl_indexed_tlb(x,a,map,tl);
3026 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3029 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3031 if (opcode[i]==0x25) { // LHU
3034 #ifdef HOST_IMM_ADDR32
3036 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
3041 #ifdef BIG_ENDIAN_MIPS
3042 if(!c) emit_xorimm(addr,2,tl);
3043 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3047 if(fastload_reg_override) a=fastload_reg_override;
3049 //emit_movzwl_indexed_tlb(x,tl,map,tl);
3052 gen_tlb_addr_r(a,map);
3053 emit_movzwl_indexed(x,a,tl);
3056 emit_movzwl_indexed(x,a,tl);
3058 emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
3064 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3067 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3069 if (opcode[i]==0x27) { // LWU
3074 if(fastload_reg_override) a=fastload_reg_override;
3075 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3076 #ifdef HOST_IMM_ADDR32
3078 emit_readword_tlb(constmap[i][s]+offset,map,tl);
3081 emit_readword_indexed_tlb(0,a,map,tl);
3084 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3087 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3091 if (opcode[i]==0x37) { // LD
3095 if(fastload_reg_override) a=fastload_reg_override;
3096 //gen_tlb_addr_r(tl,map);
3097 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3098 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3099 #ifdef HOST_IMM_ADDR32
3101 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3104 emit_readdword_indexed_tlb(0,a,map,th,tl);
3107 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3110 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3113 //emit_storereg(rt1[i],tl); // DEBUG
3114 //if(opcode[i]==0x23)
3115 //if(opcode[i]==0x24)
3116 //if(opcode[i]==0x23||opcode[i]==0x24)
3117 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3121 emit_readword((int)&last_count,ECX);
3123 if(get_reg(i_regs->regmap,CCREG)<0)
3124 emit_loadreg(CCREG,HOST_CCREG);
3125 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3126 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3127 emit_writeword(HOST_CCREG,(int)&Count);
3130 if(get_reg(i_regs->regmap,CCREG)<0)
3131 emit_loadreg(CCREG,0);
3133 emit_mov(HOST_CCREG,0);
3135 emit_addimm(0,2*ccadj[i],0);
3136 emit_writeword(0,(int)&Count);
3138 emit_call((int)memdebug);
3140 restore_regs(0x100f);
3144 #ifndef loadlr_assemble
3145 void loadlr_assemble(int i,struct regstat *i_regs)
3147 printf("Need loadlr_assemble for this architecture.\n");
3152 void store_assemble(int i,struct regstat *i_regs)
3157 int jaddr=0,jaddr2,type;
3158 int memtarget=0,c=0;
3159 int agr=AGEN1+(i&1);
3160 int faststore_reg_override=0;
3162 th=get_reg(i_regs->regmap,rs2[i]|64);
3163 tl=get_reg(i_regs->regmap,rs2[i]);
3164 s=get_reg(i_regs->regmap,rs1[i]);
3165 temp=get_reg(i_regs->regmap,agr);
3166 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3169 c=(i_regs->wasconst>>s)&1;
3171 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3172 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3177 for(hr=0;hr<HOST_REGS;hr++) {
3178 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3180 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3181 if(offset||s<0||c) addr=temp;
3186 if(sp_in_mirror&&rs1[i]==29) {
3187 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
3188 emit_cmpimm(HOST_TEMPREG,RAM_SIZE);
3189 faststore_reg_override=HOST_TEMPREG;
3194 // Strmnnrmn's speed hack
3195 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3197 emit_cmpimm(addr,RAM_SIZE);
3198 #ifdef DESTRUCTIVE_SHIFT
3199 if(s==addr) emit_mov(s,temp);
3203 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3207 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3208 // Hint to branch predictor that the branch is unlikely to be taken
3210 emit_jno_unlikely(0);
3218 if (opcode[i]==0x28) x=3; // SB
3219 if (opcode[i]==0x29) x=2; // SH
3220 map=get_reg(i_regs->regmap,TLREG);
3223 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3224 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3227 if (opcode[i]==0x28) { // SB
3230 #ifdef BIG_ENDIAN_MIPS
3231 if(!c) emit_xorimm(addr,3,temp);
3232 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3236 if(faststore_reg_override) a=faststore_reg_override;
3237 //gen_tlb_addr_w(temp,map);
3238 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3239 emit_writebyte_indexed_tlb(tl,x,a,map,a);
3243 if (opcode[i]==0x29) { // SH
3246 #ifdef BIG_ENDIAN_MIPS
3247 if(!c) emit_xorimm(addr,2,temp);
3248 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3252 if(faststore_reg_override) a=faststore_reg_override;
3254 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3257 gen_tlb_addr_w(a,map);
3258 emit_writehword_indexed(tl,x,a);
3260 emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
3264 if (opcode[i]==0x2B) { // SW
3267 if(faststore_reg_override) a=faststore_reg_override;
3268 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3269 emit_writeword_indexed_tlb(tl,0,a,map,temp);
3273 if (opcode[i]==0x3F) { // SD
3276 if(faststore_reg_override) a=faststore_reg_override;
3279 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3280 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3281 emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
3284 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3285 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3286 emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
3293 // PCSX store handlers don't check invcode again
3295 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3301 #ifdef DESTRUCTIVE_SHIFT
3302 // The x86 shift operation is 'destructive'; it overwrites the
3303 // source register, so we need to make a copy first and use that.
3306 #if defined(HOST_IMM8)
3307 int ir=get_reg(i_regs->regmap,INVCP);
3309 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3311 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3313 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3314 emit_callne(invalidate_addr_reg[addr]);
3318 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3323 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3324 } else if(c&&!memtarget) {
3325 inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3327 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3328 //if(opcode[i]==0x2B || opcode[i]==0x28)
3329 //if(opcode[i]==0x2B || opcode[i]==0x29)
3330 //if(opcode[i]==0x2B)
3331 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3339 emit_readword((int)&last_count,ECX);
3341 if(get_reg(i_regs->regmap,CCREG)<0)
3342 emit_loadreg(CCREG,HOST_CCREG);
3343 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3344 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3345 emit_writeword(HOST_CCREG,(int)&Count);
3348 if(get_reg(i_regs->regmap,CCREG)<0)
3349 emit_loadreg(CCREG,0);
3351 emit_mov(HOST_CCREG,0);
3353 emit_addimm(0,2*ccadj[i],0);
3354 emit_writeword(0,(int)&Count);
3356 emit_call((int)memdebug);
3361 restore_regs(0x100f);
3366 void storelr_assemble(int i,struct regstat *i_regs)
3373 int case1,case2,case3;
3374 int done0,done1,done2;
3375 int memtarget=0,c=0;
3376 int agr=AGEN1+(i&1);
3378 th=get_reg(i_regs->regmap,rs2[i]|64);
3379 tl=get_reg(i_regs->regmap,rs2[i]);
3380 s=get_reg(i_regs->regmap,rs1[i]);
3381 temp=get_reg(i_regs->regmap,agr);
3382 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3385 c=(i_regs->isconst>>s)&1;
3387 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3388 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3392 for(hr=0;hr<HOST_REGS;hr++) {
3393 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3398 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3399 if(!offset&&s!=temp) emit_mov(s,temp);
3405 if(!memtarget||!rs1[i]) {
3411 int map=get_reg(i_regs->regmap,ROREG);
3412 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3413 gen_tlb_addr_w(temp,map);
3415 if((u_int)rdram!=0x80000000)
3416 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3419 int map=get_reg(i_regs->regmap,TLREG);
3422 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3423 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3424 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3425 if(!jaddr&&!memtarget) {
3429 gen_tlb_addr_w(temp,map);
3432 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3433 temp2=get_reg(i_regs->regmap,FTEMP);
3434 if(!rs2[i]) temp2=th=tl;
3437 #ifndef BIG_ENDIAN_MIPS
3438 emit_xorimm(temp,3,temp);
3440 emit_testimm(temp,2);
3443 emit_testimm(temp,1);
3447 if (opcode[i]==0x2A) { // SWL
3448 emit_writeword_indexed(tl,0,temp);
3450 if (opcode[i]==0x2E) { // SWR
3451 emit_writebyte_indexed(tl,3,temp);
3453 if (opcode[i]==0x2C) { // SDL
3454 emit_writeword_indexed(th,0,temp);
3455 if(rs2[i]) emit_mov(tl,temp2);
3457 if (opcode[i]==0x2D) { // SDR
3458 emit_writebyte_indexed(tl,3,temp);
3459 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3464 set_jump_target(case1,(int)out);
3465 if (opcode[i]==0x2A) { // SWL
3466 // Write 3 msb into three least significant bytes
3467 if(rs2[i]) emit_rorimm(tl,8,tl);
3468 emit_writehword_indexed(tl,-1,temp);
3469 if(rs2[i]) emit_rorimm(tl,16,tl);
3470 emit_writebyte_indexed(tl,1,temp);
3471 if(rs2[i]) emit_rorimm(tl,8,tl);
3473 if (opcode[i]==0x2E) { // SWR
3474 // Write two lsb into two most significant bytes
3475 emit_writehword_indexed(tl,1,temp);
3477 if (opcode[i]==0x2C) { // SDL
3478 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3479 // Write 3 msb into three least significant bytes
3480 if(rs2[i]) emit_rorimm(th,8,th);
3481 emit_writehword_indexed(th,-1,temp);
3482 if(rs2[i]) emit_rorimm(th,16,th);
3483 emit_writebyte_indexed(th,1,temp);
3484 if(rs2[i]) emit_rorimm(th,8,th);
3486 if (opcode[i]==0x2D) { // SDR
3487 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3488 // Write two lsb into two most significant bytes
3489 emit_writehword_indexed(tl,1,temp);
3494 set_jump_target(case2,(int)out);
3495 emit_testimm(temp,1);
3498 if (opcode[i]==0x2A) { // SWL
3499 // Write two msb into two least significant bytes
3500 if(rs2[i]) emit_rorimm(tl,16,tl);
3501 emit_writehword_indexed(tl,-2,temp);
3502 if(rs2[i]) emit_rorimm(tl,16,tl);
3504 if (opcode[i]==0x2E) { // SWR
3505 // Write 3 lsb into three most significant bytes
3506 emit_writebyte_indexed(tl,-1,temp);
3507 if(rs2[i]) emit_rorimm(tl,8,tl);
3508 emit_writehword_indexed(tl,0,temp);
3509 if(rs2[i]) emit_rorimm(tl,24,tl);
3511 if (opcode[i]==0x2C) { // SDL
3512 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3513 // Write two msb into two least significant bytes
3514 if(rs2[i]) emit_rorimm(th,16,th);
3515 emit_writehword_indexed(th,-2,temp);
3516 if(rs2[i]) emit_rorimm(th,16,th);
3518 if (opcode[i]==0x2D) { // SDR
3519 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3520 // Write 3 lsb into three most significant bytes
3521 emit_writebyte_indexed(tl,-1,temp);
3522 if(rs2[i]) emit_rorimm(tl,8,tl);
3523 emit_writehword_indexed(tl,0,temp);
3524 if(rs2[i]) emit_rorimm(tl,24,tl);
3529 set_jump_target(case3,(int)out);
3530 if (opcode[i]==0x2A) { // SWL
3531 // Write msb into least significant byte
3532 if(rs2[i]) emit_rorimm(tl,24,tl);
3533 emit_writebyte_indexed(tl,-3,temp);
3534 if(rs2[i]) emit_rorimm(tl,8,tl);
3536 if (opcode[i]==0x2E) { // SWR
3537 // Write entire word
3538 emit_writeword_indexed(tl,-3,temp);
3540 if (opcode[i]==0x2C) { // SDL
3541 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3542 // Write msb into least significant byte
3543 if(rs2[i]) emit_rorimm(th,24,th);
3544 emit_writebyte_indexed(th,-3,temp);
3545 if(rs2[i]) emit_rorimm(th,8,th);
3547 if (opcode[i]==0x2D) { // SDR
3548 if(rs2[i]) emit_mov(th,temp2);
3549 // Write entire word
3550 emit_writeword_indexed(tl,-3,temp);
3552 set_jump_target(done0,(int)out);
3553 set_jump_target(done1,(int)out);
3554 set_jump_target(done2,(int)out);
3555 if (opcode[i]==0x2C) { // SDL
3556 emit_testimm(temp,4);
3559 emit_andimm(temp,~3,temp);
3560 emit_writeword_indexed(temp2,4,temp);
3561 set_jump_target(done0,(int)out);
3563 if (opcode[i]==0x2D) { // SDR
3564 emit_testimm(temp,4);
3567 emit_andimm(temp,~3,temp);
3568 emit_writeword_indexed(temp2,-4,temp);
3569 set_jump_target(done0,(int)out);
3572 add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
3575 int map=get_reg(i_regs->regmap,ROREG);
3576 if(map<0) map=HOST_TEMPREG;
3577 gen_orig_addr_w(temp,map);
3579 emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3581 #if defined(HOST_IMM8)
3582 int ir=get_reg(i_regs->regmap,INVCP);
3584 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3586 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3588 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3589 emit_callne(invalidate_addr_reg[temp]);
3593 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3598 //save_regs(0x100f);
3599 emit_readword((int)&last_count,ECX);
3600 if(get_reg(i_regs->regmap,CCREG)<0)
3601 emit_loadreg(CCREG,HOST_CCREG);
3602 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3603 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3604 emit_writeword(HOST_CCREG,(int)&Count);
3605 emit_call((int)memdebug);
3607 //restore_regs(0x100f);
3611 void c1ls_assemble(int i,struct regstat *i_regs)
3613 #ifndef DISABLE_COP1
3619 int jaddr,jaddr2=0,jaddr3,type;
3620 int agr=AGEN1+(i&1);
3622 th=get_reg(i_regs->regmap,FTEMP|64);
3623 tl=get_reg(i_regs->regmap,FTEMP);
3624 s=get_reg(i_regs->regmap,rs1[i]);
3625 temp=get_reg(i_regs->regmap,agr);
3626 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3631 for(hr=0;hr<HOST_REGS;hr++) {
3632 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3634 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3635 if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3637 // Loads use a temporary register which we need to save
3640 if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3644 //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3645 //else c=(i_regs->wasconst>>s)&1;
3646 if(s>=0) c=(i_regs->wasconst>>s)&1;
3647 // Check cop1 unusable
3649 signed char rs=get_reg(i_regs->regmap,CSREG);
3651 emit_testimm(rs,0x20000000);
3654 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3657 if (opcode[i]==0x39) { // SWC1 (get float address)
3658 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],tl);
3660 if (opcode[i]==0x3D) { // SDC1 (get double address)
3661 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],tl);
3663 // Generate address + offset
3666 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3670 map=get_reg(i_regs->regmap,TLREG);
3673 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3674 map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3676 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3677 map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3680 if (opcode[i]==0x39) { // SWC1 (read float)
3681 emit_readword_indexed(0,tl,tl);
3683 if (opcode[i]==0x3D) { // SDC1 (read double)
3684 emit_readword_indexed(4,tl,th);
3685 emit_readword_indexed(0,tl,tl);
3687 if (opcode[i]==0x31) { // LWC1 (get target address)
3688 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],temp);
3690 if (opcode[i]==0x35) { // LDC1 (get target address)
3691 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],temp);
3698 else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
3700 emit_jmp(0); // inline_readstub/inline_writestub? Very rare case
3702 #ifdef DESTRUCTIVE_SHIFT
3703 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3704 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3708 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3709 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3711 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3712 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3715 if (opcode[i]==0x31) { // LWC1
3716 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3717 //gen_tlb_addr_r(ar,map);
3718 //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3719 #ifdef HOST_IMM_ADDR32
3720 if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3723 emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3726 if (opcode[i]==0x35) { // LDC1
3728 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3729 //gen_tlb_addr_r(ar,map);
3730 //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3731 //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3732 #ifdef HOST_IMM_ADDR32
3733 if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3736 emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3739 if (opcode[i]==0x39) { // SWC1
3740 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3741 emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3744 if (opcode[i]==0x3D) { // SDC1
3746 //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3747 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3748 emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3752 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3753 #ifndef DESTRUCTIVE_SHIFT
3754 temp=offset||c||s<0?ar:s;
3756 #if defined(HOST_IMM8)
3757 int ir=get_reg(i_regs->regmap,INVCP);
3759 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3761 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3763 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3764 emit_callne(invalidate_addr_reg[temp]);
3768 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3772 if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3773 if (opcode[i]==0x31) { // LWC1 (write float)
3774 emit_writeword_indexed(tl,0,temp);
3776 if (opcode[i]==0x35) { // LDC1 (write double)
3777 emit_writeword_indexed(th,4,temp);
3778 emit_writeword_indexed(tl,0,temp);
3780 //if(opcode[i]==0x39)
3781 /*if(opcode[i]==0x39||opcode[i]==0x31)
3784 emit_readword((int)&last_count,ECX);
3785 if(get_reg(i_regs->regmap,CCREG)<0)
3786 emit_loadreg(CCREG,HOST_CCREG);
3787 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3788 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3789 emit_writeword(HOST_CCREG,(int)&Count);
3790 emit_call((int)memdebug);
3794 cop1_unusable(i, i_regs);
3798 void c2ls_assemble(int i,struct regstat *i_regs)
3803 int memtarget=0,c=0;
3804 int jaddr2=0,jaddr3,type;
3805 int agr=AGEN1+(i&1);
3807 u_int copr=(source[i]>>16)&0x1f;
3808 s=get_reg(i_regs->regmap,rs1[i]);
3809 tl=get_reg(i_regs->regmap,FTEMP);
3815 for(hr=0;hr<HOST_REGS;hr++) {
3816 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3818 if(i_regs->regmap[HOST_CCREG]==CCREG)
3819 reglist&=~(1<<HOST_CCREG);
3822 if (opcode[i]==0x3a) { // SWC2
3823 ar=get_reg(i_regs->regmap,agr);
3824 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3829 if(s>=0) c=(i_regs->wasconst>>s)&1;
3830 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3831 if (!offset&&!c&&s>=0) ar=s;
3834 if (opcode[i]==0x3a) { // SWC2
3835 cop2_get_dreg(copr,tl,HOST_TEMPREG);
3843 emit_jmp(0); // inline_readstub/inline_writestub?
3847 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3851 if (opcode[i]==0x32) { // LWC2
3852 #ifdef HOST_IMM_ADDR32
3853 if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3856 emit_readword_indexed(0,ar,tl);
3858 if (opcode[i]==0x3a) { // SWC2
3859 #ifdef DESTRUCTIVE_SHIFT
3860 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3862 emit_writeword_indexed(tl,0,ar);
3866 add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3867 if (opcode[i]==0x3a) { // SWC2
3868 #if defined(HOST_IMM8)
3869 int ir=get_reg(i_regs->regmap,INVCP);
3871 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3873 emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3875 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3876 emit_callne(invalidate_addr_reg[ar]);
3880 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3883 if (opcode[i]==0x32) { // LWC2
3884 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3888 #ifndef multdiv_assemble
3889 void multdiv_assemble(int i,struct regstat *i_regs)
3891 printf("Need multdiv_assemble for this architecture.\n");
3896 void mov_assemble(int i,struct regstat *i_regs)
3898 //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3899 //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3901 signed char sh,sl,th,tl;
3902 th=get_reg(i_regs->regmap,rt1[i]|64);
3903 tl=get_reg(i_regs->regmap,rt1[i]);
3906 sh=get_reg(i_regs->regmap,rs1[i]|64);
3907 sl=get_reg(i_regs->regmap,rs1[i]);
3908 if(sl>=0) emit_mov(sl,tl);
3909 else emit_loadreg(rs1[i],tl);
3911 if(sh>=0) emit_mov(sh,th);
3912 else emit_loadreg(rs1[i]|64,th);
3918 #ifndef fconv_assemble
3919 void fconv_assemble(int i,struct regstat *i_regs)
3921 printf("Need fconv_assemble for this architecture.\n");
3927 void float_assemble(int i,struct regstat *i_regs)
3929 printf("Need float_assemble for this architecture.\n");
3934 void syscall_assemble(int i,struct regstat *i_regs)
3936 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3937 assert(ccreg==HOST_CCREG);
3938 assert(!is_delayslot);
3939 emit_movimm(start+i*4,EAX); // Get PC
3940 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
3941 emit_jmp((int)jump_syscall_hle); // XXX
3944 void hlecall_assemble(int i,struct regstat *i_regs)
3946 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3947 assert(ccreg==HOST_CCREG);
3948 assert(!is_delayslot);
3949 emit_movimm(start+i*4+4,0); // Get PC
3950 emit_movimm((int)psxHLEt[source[i]&7],1);
3951 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // XXX
3952 emit_jmp((int)jump_hlecall);
3955 void intcall_assemble(int i,struct regstat *i_regs)
3957 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3958 assert(ccreg==HOST_CCREG);
3959 assert(!is_delayslot);
3960 emit_movimm(start+i*4,0); // Get PC
3961 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3962 emit_jmp((int)jump_intcall);
3965 void ds_assemble(int i,struct regstat *i_regs)
3970 alu_assemble(i,i_regs);break;
3972 imm16_assemble(i,i_regs);break;
3974 shift_assemble(i,i_regs);break;
3976 shiftimm_assemble(i,i_regs);break;
3978 load_assemble(i,i_regs);break;
3980 loadlr_assemble(i,i_regs);break;
3982 store_assemble(i,i_regs);break;
3984 storelr_assemble(i,i_regs);break;
3986 cop0_assemble(i,i_regs);break;
3988 cop1_assemble(i,i_regs);break;
3990 c1ls_assemble(i,i_regs);break;
3992 cop2_assemble(i,i_regs);break;
3994 c2ls_assemble(i,i_regs);break;
3996 c2op_assemble(i,i_regs);break;
3998 fconv_assemble(i,i_regs);break;
4000 float_assemble(i,i_regs);break;
4002 fcomp_assemble(i,i_regs);break;
4004 multdiv_assemble(i,i_regs);break;
4006 mov_assemble(i,i_regs);break;
4016 printf("Jump in the delay slot. This is probably a bug.\n");
4021 // Is the branch target a valid internal jump?
4022 int internal_branch(uint64_t i_is32,int addr)
4024 if(addr&1) return 0; // Indirect (register) jump
4025 if(addr>=start && addr<start+slen*4-4)
4027 int t=(addr-start)>>2;
4028 // Delay slots are not valid branch targets
4029 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4030 // 64 -> 32 bit transition requires a recompile
4031 /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
4033 if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
4034 else printf("optimizable: yes\n");
4036 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4038 if(requires_32bit[t]&~i_is32) return 0;
4046 #ifndef wb_invalidate
4047 void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
4048 uint64_t u,uint64_t uu)
4051 for(hr=0;hr<HOST_REGS;hr++) {
4052 if(hr!=EXCLUDE_REG) {
4053 if(pre[hr]!=entry[hr]) {
4056 if(get_reg(entry,pre[hr])<0) {
4058 if(!((u>>pre[hr])&1)) {
4059 emit_storereg(pre[hr],hr);
4060 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
4061 emit_sarimm(hr,31,hr);
4062 emit_storereg(pre[hr]|64,hr);
4066 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
4067 emit_storereg(pre[hr],hr);
4076 // Move from one register to another (no writeback)
4077 for(hr=0;hr<HOST_REGS;hr++) {
4078 if(hr!=EXCLUDE_REG) {
4079 if(pre[hr]!=entry[hr]) {
4080 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
4082 if((nr=get_reg(entry,pre[hr]))>=0) {
4092 // Load the specified registers
4093 // This only loads the registers given as arguments because
4094 // we don't want to load things that will be overwritten
4095 void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
4099 for(hr=0;hr<HOST_REGS;hr++) {
4100 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4101 if(entry[hr]!=regmap[hr]) {
4102 if(regmap[hr]==rs1||regmap[hr]==rs2)
4109 emit_loadreg(regmap[hr],hr);
4116 for(hr=0;hr<HOST_REGS;hr++) {
4117 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4118 if(entry[hr]!=regmap[hr]) {
4119 if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
4121 assert(regmap[hr]!=64);
4122 if((is32>>(regmap[hr]&63))&1) {
4123 int lr=get_reg(regmap,regmap[hr]-64);
4125 emit_sarimm(lr,31,hr);
4127 emit_loadreg(regmap[hr],hr);
4131 emit_loadreg(regmap[hr],hr);
4139 // Load registers prior to the start of a loop
4140 // so that they are not loaded within the loop
4141 static void loop_preload(signed char pre[],signed char entry[])
4144 for(hr=0;hr<HOST_REGS;hr++) {
4145 if(hr!=EXCLUDE_REG) {
4146 if(pre[hr]!=entry[hr]) {
4148 if(get_reg(pre,entry[hr])<0) {
4149 assem_debug("loop preload:\n");
4150 //printf("loop preload: %d\n",hr);
4154 else if(entry[hr]<TEMPREG)
4156 emit_loadreg(entry[hr],hr);
4158 else if(entry[hr]-64<TEMPREG)
4160 emit_loadreg(entry[hr],hr);
4169 // Generate address for load/store instruction
4170 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
4171 void address_generation(int i,struct regstat *i_regs,signed char entry[])
4173 if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
4175 int agr=AGEN1+(i&1);
4176 int mgr=MGEN1+(i&1);
4177 if(itype[i]==LOAD) {
4178 ra=get_reg(i_regs->regmap,rt1[i]);
4179 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4182 if(itype[i]==LOADLR) {
4183 ra=get_reg(i_regs->regmap,FTEMP);
4185 if(itype[i]==STORE||itype[i]==STORELR) {
4186 ra=get_reg(i_regs->regmap,agr);
4187 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4189 if(itype[i]==C1LS||itype[i]==C2LS) {
4190 if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
4191 ra=get_reg(i_regs->regmap,FTEMP);
4192 else { // SWC1/SDC1/SWC2/SDC2
4193 ra=get_reg(i_regs->regmap,agr);
4194 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4197 int rs=get_reg(i_regs->regmap,rs1[i]);
4198 int rm=get_reg(i_regs->regmap,TLREG);
4201 int c=(i_regs->wasconst>>rs)&1;
4203 // Using r0 as a base address
4205 if(!entry||entry[rm]!=mgr) {
4206 generate_map_const(offset,rm);
4207 } // else did it in the previous cycle
4209 if(!entry||entry[ra]!=agr) {
4210 if (opcode[i]==0x22||opcode[i]==0x26) {
4211 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4212 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4213 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4215 emit_movimm(offset,ra);
4217 } // else did it in the previous cycle
4220 if(!entry||entry[ra]!=rs1[i])
4221 emit_loadreg(rs1[i],ra);
4222 //if(!entry||entry[ra]!=rs1[i])
4223 // printf("poor load scheduling!\n");
4227 if(!entry||entry[rm]!=mgr) {
4228 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
4229 // Stores to memory go thru the mapper to detect self-modifying
4230 // code, loads don't.
4231 if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
4232 (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
4233 generate_map_const(constmap[i][rs]+offset,rm);
4235 if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
4236 generate_map_const(constmap[i][rs]+offset,rm);
4240 if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
4241 if(!entry||entry[ra]!=agr) {
4242 if (opcode[i]==0x22||opcode[i]==0x26) {
4243 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4244 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4245 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4247 #ifdef HOST_IMM_ADDR32
4248 if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4249 (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4251 emit_movimm(constmap[i][rs]+offset,ra);
4253 } // else did it in the previous cycle
4254 } // else load_consts already did it
4256 if(offset&&!c&&rs1[i]) {
4258 emit_addimm(rs,offset,ra);
4260 emit_addimm(ra,offset,ra);
4265 // Preload constants for next instruction
4266 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
4268 #ifndef HOST_IMM_ADDR32
4270 agr=MGEN1+((i+1)&1);
4271 ra=get_reg(i_regs->regmap,agr);
4273 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4274 int offset=imm[i+1];
4275 int c=(regs[i+1].wasconst>>rs)&1;
4277 if(itype[i+1]==STORE||itype[i+1]==STORELR
4278 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
4279 // Stores to memory go thru the mapper to detect self-modifying
4280 // code, loads don't.
4281 if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4282 (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
4283 generate_map_const(constmap[i+1][rs]+offset,ra);
4285 if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4286 generate_map_const(constmap[i+1][rs]+offset,ra);
4289 /*else if(rs1[i]==0) {
4290 generate_map_const(offset,ra);
4295 agr=AGEN1+((i+1)&1);
4296 ra=get_reg(i_regs->regmap,agr);
4298 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4299 int offset=imm[i+1];
4300 int c=(regs[i+1].wasconst>>rs)&1;
4301 if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4302 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4303 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4304 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4305 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4307 #ifdef HOST_IMM_ADDR32
4308 if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4309 (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4311 emit_movimm(constmap[i+1][rs]+offset,ra);
4314 else if(rs1[i+1]==0) {
4315 // Using r0 as a base address
4316 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4317 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4318 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4319 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4321 emit_movimm(offset,ra);
4328 int get_final_value(int hr, int i, int *value)
4330 int reg=regs[i].regmap[hr];
4332 if(regs[i+1].regmap[hr]!=reg) break;
4333 if(!((regs[i+1].isconst>>hr)&1)) break;
4338 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4339 *value=constmap[i][hr];
4343 if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4344 // Load in delay slot, out-of-order execution
4345 if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4347 #ifdef HOST_IMM_ADDR32
4348 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4350 // Precompute load address
4351 *value=constmap[i][hr]+imm[i+2];
4355 if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4357 #ifdef HOST_IMM_ADDR32
4358 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4360 // Precompute load address
4361 *value=constmap[i][hr]+imm[i+1];
4362 //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4367 *value=constmap[i][hr];
4368 //printf("c=%x\n",(int)constmap[i][hr]);
4369 if(i==slen-1) return 1;
4371 return !((unneeded_reg[i+1]>>reg)&1);
4373 return !((unneeded_reg_upper[i+1]>>reg)&1);
4377 // Load registers with known constants
4378 void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4382 for(hr=0;hr<HOST_REGS;hr++) {
4383 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4384 //if(entry[hr]!=regmap[hr]) {
4385 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4386 if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) {
4388 if(get_final_value(hr,i,&value)) {
4393 emit_movimm(value,hr);
4401 for(hr=0;hr<HOST_REGS;hr++) {
4402 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4403 //if(entry[hr]!=regmap[hr]) {
4404 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4405 if(((regs[i].isconst>>hr)&1)&®map[hr]>64) {
4406 if((is32>>(regmap[hr]&63))&1) {
4407 int lr=get_reg(regmap,regmap[hr]-64);
4409 emit_sarimm(lr,31,hr);
4414 if(get_final_value(hr,i,&value)) {
4419 emit_movimm(value,hr);
4428 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4432 for(hr=0;hr<HOST_REGS;hr++) {
4433 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4434 if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) {
4435 int value=constmap[i][hr];
4440 emit_movimm(value,hr);
4446 for(hr=0;hr<HOST_REGS;hr++) {
4447 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4448 if(((regs[i].isconst>>hr)&1)&®map[hr]>64) {
4449 if((is32>>(regmap[hr]&63))&1) {
4450 int lr=get_reg(regmap,regmap[hr]-64);
4452 emit_sarimm(lr,31,hr);
4456 int value=constmap[i][hr];
4461 emit_movimm(value,hr);
4469 // Write out all dirty registers (except cycle count)
4470 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4473 for(hr=0;hr<HOST_REGS;hr++) {
4474 if(hr!=EXCLUDE_REG) {
4475 if(i_regmap[hr]>0) {
4476 if(i_regmap[hr]!=CCREG) {
4477 if((i_dirty>>hr)&1) {
4478 if(i_regmap[hr]<64) {
4479 emit_storereg(i_regmap[hr],hr);
4481 if( ((i_is32>>i_regmap[hr])&1) ) {
4482 #ifdef DESTRUCTIVE_WRITEBACK
4483 emit_sarimm(hr,31,hr);
4484 emit_storereg(i_regmap[hr]|64,hr);
4486 emit_sarimm(hr,31,HOST_TEMPREG);
4487 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4492 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4493 emit_storereg(i_regmap[hr],hr);
4502 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4503 // This writes the registers not written by store_regs_bt
4504 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4507 int t=(addr-start)>>2;
4508 for(hr=0;hr<HOST_REGS;hr++) {
4509 if(hr!=EXCLUDE_REG) {
4510 if(i_regmap[hr]>0) {
4511 if(i_regmap[hr]!=CCREG) {
4512 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4513 if((i_dirty>>hr)&1) {
4514 if(i_regmap[hr]<64) {
4515 emit_storereg(i_regmap[hr],hr);
4517 if( ((i_is32>>i_regmap[hr])&1) ) {
4518 #ifdef DESTRUCTIVE_WRITEBACK
4519 emit_sarimm(hr,31,hr);
4520 emit_storereg(i_regmap[hr]|64,hr);
4522 emit_sarimm(hr,31,HOST_TEMPREG);
4523 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4528 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4529 emit_storereg(i_regmap[hr],hr);
4540 // Load all registers (except cycle count)
4541 void load_all_regs(signed char i_regmap[])
4544 for(hr=0;hr<HOST_REGS;hr++) {
4545 if(hr!=EXCLUDE_REG) {
4546 if(i_regmap[hr]==0) {
4550 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4552 emit_loadreg(i_regmap[hr],hr);
4558 // Load all current registers also needed by next instruction
4559 void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4562 for(hr=0;hr<HOST_REGS;hr++) {
4563 if(hr!=EXCLUDE_REG) {
4564 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4565 if(i_regmap[hr]==0) {
4569 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4571 emit_loadreg(i_regmap[hr],hr);
4578 // Load all regs, storing cycle count if necessary
4579 void load_regs_entry(int t)
4582 if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER,HOST_CCREG);
4583 else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t]*CLOCK_DIVIDER,HOST_CCREG);
4584 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4585 emit_storereg(CCREG,HOST_CCREG);
4588 for(hr=0;hr<HOST_REGS;hr++) {
4589 if(regs[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4590 if(regs[t].regmap_entry[hr]==0) {
4593 else if(regs[t].regmap_entry[hr]!=CCREG)
4595 emit_loadreg(regs[t].regmap_entry[hr],hr);
4600 for(hr=0;hr<HOST_REGS;hr++) {
4601 if(regs[t].regmap_entry[hr]>=64&®s[t].regmap_entry[hr]<TEMPREG+64) {
4602 assert(regs[t].regmap_entry[hr]!=64);
4603 if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4604 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4606 emit_loadreg(regs[t].regmap_entry[hr],hr);
4610 emit_sarimm(lr,31,hr);
4615 emit_loadreg(regs[t].regmap_entry[hr],hr);
4621 // Store dirty registers prior to branch
4622 void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4624 if(internal_branch(i_is32,addr))
4626 int t=(addr-start)>>2;
4628 for(hr=0;hr<HOST_REGS;hr++) {
4629 if(hr!=EXCLUDE_REG) {
4630 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4631 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4632 if((i_dirty>>hr)&1) {
4633 if(i_regmap[hr]<64) {
4634 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4635 emit_storereg(i_regmap[hr],hr);
4636 if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4637 #ifdef DESTRUCTIVE_WRITEBACK
4638 emit_sarimm(hr,31,hr);
4639 emit_storereg(i_regmap[hr]|64,hr);
4641 emit_sarimm(hr,31,HOST_TEMPREG);
4642 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4647 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4648 emit_storereg(i_regmap[hr],hr);
4659 // Branch out of this block, write out all dirty regs
4660 wb_dirtys(i_regmap,i_is32,i_dirty);
4664 // Load all needed registers for branch target
4665 void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4667 //if(addr>=start && addr<(start+slen*4))
4668 if(internal_branch(i_is32,addr))
4670 int t=(addr-start)>>2;
4672 // Store the cycle count before loading something else
4673 if(i_regmap[HOST_CCREG]!=CCREG) {
4674 assert(i_regmap[HOST_CCREG]==-1);
4676 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4677 emit_storereg(CCREG,HOST_CCREG);
4680 for(hr=0;hr<HOST_REGS;hr++) {
4681 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4682 #ifdef DESTRUCTIVE_WRITEBACK
4683 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4685 if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4687 if(regs[t].regmap_entry[hr]==0) {
4690 else if(regs[t].regmap_entry[hr]!=CCREG)
4692 emit_loadreg(regs[t].regmap_entry[hr],hr);
4698 for(hr=0;hr<HOST_REGS;hr++) {
4699 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=64&®s[t].regmap_entry[hr]<TEMPREG+64) {
4700 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4701 assert(regs[t].regmap_entry[hr]!=64);
4702 if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4703 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4705 emit_loadreg(regs[t].regmap_entry[hr],hr);
4709 emit_sarimm(lr,31,hr);
4714 emit_loadreg(regs[t].regmap_entry[hr],hr);
4717 else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4718 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4720 emit_sarimm(lr,31,hr);
4727 int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4729 if(addr>=start && addr<start+slen*4-4)
4731 int t=(addr-start)>>2;
4733 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4734 for(hr=0;hr<HOST_REGS;hr++)
4738 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4740 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
4747 if(i_regmap[hr]<TEMPREG)
4749 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4752 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
4754 if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4759 else // Same register but is it 32-bit or dirty?
4762 if(!((regs[t].dirty>>hr)&1))
4766 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4768 //printf("%x: dirty no match\n",addr);
4773 if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4775 //printf("%x: is32 no match\n",addr);
4781 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4783 if(requires_32bit[t]&~i_is32) return 0;
4785 // Delay slots are not valid branch targets
4786 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4787 // Delay slots require additional processing, so do not match
4788 if(is_ds[t]) return 0;
4793 for(hr=0;hr<HOST_REGS;hr++)
4799 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4813 // Used when a branch jumps into the delay slot of another branch
4814 void ds_assemble_entry(int i)
4816 int t=(ba[i]-start)>>2;
4817 if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4818 assem_debug("Assemble delay slot at %x\n",ba[i]);
4819 assem_debug("<->\n");
4820 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&®s[t].regmap[HOST_CCREG]!=CCREG)
4821 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4822 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4823 address_generation(t,®s[t],regs[t].regmap_entry);
4824 if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
4825 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4830 alu_assemble(t,®s[t]);break;
4832 imm16_assemble(t,®s[t]);break;
4834 shift_assemble(t,®s[t]);break;
4836 shiftimm_assemble(t,®s[t]);break;
4838 load_assemble(t,®s[t]);break;
4840 loadlr_assemble(t,®s[t]);break;
4842 store_assemble(t,®s[t]);break;
4844 storelr_assemble(t,®s[t]);break;
4846 cop0_assemble(t,®s[t]);break;
4848 cop1_assemble(t,®s[t]);break;
4850 c1ls_assemble(t,®s[t]);break;
4852 cop2_assemble(t,®s[t]);break;
4854 c2ls_assemble(t,®s[t]);break;
4856 c2op_assemble(t,®s[t]);break;
4858 fconv_assemble(t,®s[t]);break;
4860 float_assemble(t,®s[t]);break;
4862 fcomp_assemble(t,®s[t]);break;
4864 multdiv_assemble(t,®s[t]);break;
4866 mov_assemble(t,®s[t]);break;
4876 printf("Jump in the delay slot. This is probably a bug.\n");
4878 store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4879 load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4880 if(internal_branch(regs[t].is32,ba[i]+4))
4881 assem_debug("branch: internal\n");
4883 assem_debug("branch: external\n");
4884 assert(internal_branch(regs[t].is32,ba[i]+4));
4885 add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4889 void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4898 //if(ba[i]>=start && ba[i]<(start+slen*4))
4899 if(internal_branch(branch_regs[i].is32,ba[i]))
4901 int t=(ba[i]-start)>>2;
4902 if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4910 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4912 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4914 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4915 emit_andimm(HOST_CCREG,3,HOST_CCREG);
4919 else if(*adj==0||invert) {
4920 emit_addimm_and_set_flags(CLOCK_DIVIDER*(count+2),HOST_CCREG);
4926 emit_cmpimm(HOST_CCREG,-CLOCK_DIVIDER*(count+2));
4930 add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4933 void do_ccstub(int n)
4936 assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
4937 set_jump_target(stubs[n][1],(int)out);
4939 if(stubs[n][6]==NULLDS) {
4940 // Delay slot instruction is nullified ("likely" branch)
4941 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4943 else if(stubs[n][6]!=TAKEN) {
4944 wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4947 if(internal_branch(branch_regs[i].is32,ba[i]))
4948 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4952 // Save PC as return address
4953 emit_movimm(stubs[n][5],EAX);
4954 emit_writeword(EAX,(int)&pcaddr);
4958 // Return address depends on which way the branch goes
4959 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
4961 int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4962 int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4963 int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4964 int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4974 if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
4978 #ifdef DESTRUCTIVE_WRITEBACK
4980 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
4981 emit_loadreg(rs1[i],s1l);
4984 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
4985 emit_loadreg(rs2[i],s1l);
4988 if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
4989 emit_loadreg(rs2[i],s2l);
4992 int addr=-1,alt=-1,ntaddr=-1;
4995 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4996 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4997 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5005 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5006 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5007 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5013 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
5017 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5018 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5019 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5025 assert(hr<HOST_REGS);
5027 if((opcode[i]&0x2f)==4) // BEQ
5029 #ifdef HAVE_CMOV_IMM
5031 if(s2l>=0) emit_cmp(s1l,s2l);
5032 else emit_test(s1l,s1l);
5033 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5038 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5040 if(s2h>=0) emit_cmp(s1h,s2h);
5041 else emit_test(s1h,s1h);
5042 emit_cmovne_reg(alt,addr);
5044 if(s2l>=0) emit_cmp(s1l,s2l);
5045 else emit_test(s1l,s1l);
5046 emit_cmovne_reg(alt,addr);
5049 if((opcode[i]&0x2f)==5) // BNE
5051 #ifdef HAVE_CMOV_IMM
5053 if(s2l>=0) emit_cmp(s1l,s2l);
5054 else emit_test(s1l,s1l);
5055 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5060 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5062 if(s2h>=0) emit_cmp(s1h,s2h);
5063 else emit_test(s1h,s1h);
5064 emit_cmovne_reg(alt,addr);
5066 if(s2l>=0) emit_cmp(s1l,s2l);
5067 else emit_test(s1l,s1l);
5068 emit_cmovne_reg(alt,addr);
5071 if((opcode[i]&0x2f)==6) // BLEZ
5073 //emit_movimm(ba[i],alt);
5074 //emit_movimm(start+i*4+8,addr);
5075 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5077 if(s1h>=0) emit_mov(addr,ntaddr);
5078 emit_cmovl_reg(alt,addr);
5081 emit_cmovne_reg(ntaddr,addr);
5082 emit_cmovs_reg(alt,addr);
5085 if((opcode[i]&0x2f)==7) // BGTZ
5087 //emit_movimm(ba[i],addr);
5088 //emit_movimm(start+i*4+8,ntaddr);
5089 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5091 if(s1h>=0) emit_mov(addr,alt);
5092 emit_cmovl_reg(ntaddr,addr);
5095 emit_cmovne_reg(alt,addr);
5096 emit_cmovs_reg(ntaddr,addr);
5099 if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
5101 //emit_movimm(ba[i],alt);
5102 //emit_movimm(start+i*4+8,addr);
5103 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5104 if(s1h>=0) emit_test(s1h,s1h);
5105 else emit_test(s1l,s1l);
5106 emit_cmovs_reg(alt,addr);
5108 if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
5110 //emit_movimm(ba[i],addr);
5111 //emit_movimm(start+i*4+8,alt);
5112 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5113 if(s1h>=0) emit_test(s1h,s1h);
5114 else emit_test(s1l,s1l);
5115 emit_cmovs_reg(alt,addr);
5117 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
5118 if(source[i]&0x10000) // BC1T
5120 //emit_movimm(ba[i],alt);
5121 //emit_movimm(start+i*4+8,addr);
5122 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5123 emit_testimm(s1l,0x800000);
5124 emit_cmovne_reg(alt,addr);
5128 //emit_movimm(ba[i],addr);
5129 //emit_movimm(start+i*4+8,alt);
5130 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5131 emit_testimm(s1l,0x800000);
5132 emit_cmovne_reg(alt,addr);
5135 emit_writeword(addr,(int)&pcaddr);
5140 int r=get_reg(branch_regs[i].regmap,rs1[i]);
5141 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5142 r=get_reg(branch_regs[i].regmap,RTEMP);
5144 emit_writeword(r,(int)&pcaddr);
5146 else {printf("Unknown branch type in do_ccstub\n");exit(1);}
5148 // Update cycle count
5149 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5150 if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
5151 emit_call((int)cc_interrupt);
5152 if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
5153 if(stubs[n][6]==TAKEN) {
5154 if(internal_branch(branch_regs[i].is32,ba[i]))
5155 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
5156 else if(itype[i]==RJUMP) {
5157 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5158 emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5160 emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
5162 }else if(stubs[n][6]==NOTTAKEN) {
5163 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5164 else load_all_regs(branch_regs[i].regmap);
5165 }else if(stubs[n][6]==NULLDS) {
5166 // Delay slot instruction is nullified ("likely" branch)
5167 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5168 else load_all_regs(regs[i].regmap);
5170 load_all_regs(branch_regs[i].regmap);
5172 emit_jmp(stubs[n][2]); // return address
5174 /* This works but uses a lot of memory...
5175 emit_readword((int)&last_count,ECX);
5176 emit_add(HOST_CCREG,ECX,EAX);
5177 emit_writeword(EAX,(int)&Count);
5178 emit_call((int)gen_interupt);
5179 emit_readword((int)&Count,HOST_CCREG);
5180 emit_readword((int)&next_interupt,EAX);
5181 emit_readword((int)&pending_exception,EBX);
5182 emit_writeword(EAX,(int)&last_count);
5183 emit_sub(HOST_CCREG,EAX,HOST_CCREG);
5185 int jne_instr=(int)out;
5187 if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
5188 load_all_regs(branch_regs[i].regmap);
5189 emit_jmp(stubs[n][2]); // return address
5190 set_jump_target(jne_instr,(int)out);
5191 emit_readword((int)&pcaddr,EAX);
5192 // Call get_addr_ht instead of doing the hash table here.
5193 // This code is executed infrequently and takes up a lot of space
5194 // so smaller is better.
5195 emit_storereg(CCREG,HOST_CCREG);
5197 emit_call((int)get_addr_ht);
5198 emit_loadreg(CCREG,HOST_CCREG);
5199 emit_addimm(ESP,4,ESP);
5203 add_to_linker(int addr,int target,int ext)
5205 link_addr[linkcount][0]=addr;
5206 link_addr[linkcount][1]=target;
5207 link_addr[linkcount][2]=ext;
5211 static void ujump_assemble_write_ra(int i)
5214 unsigned int return_address;
5215 rt=get_reg(branch_regs[i].regmap,31);
5216 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5218 return_address=start+i*4+8;
5221 if(internal_branch(branch_regs[i].is32,return_address)&&rt1[i+1]!=31) {
5222 int temp=-1; // note: must be ds-safe
5226 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5227 else emit_movimm(return_address,rt);
5235 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5238 emit_movimm(return_address,rt); // PC into link register
5240 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5246 void ujump_assemble(int i,struct regstat *i_regs)
5248 signed char *i_regmap=i_regs->regmap;
5250 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5251 address_generation(i+1,i_regs,regs[i].regmap_entry);
5253 int temp=get_reg(branch_regs[i].regmap,PTEMP);
5254 if(rt1[i]==31&&temp>=0)
5256 int return_address=start+i*4+8;
5257 if(get_reg(branch_regs[i].regmap,31)>0)
5258 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5261 if(rt1[i]==31&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5262 ujump_assemble_write_ra(i); // writeback ra for DS
5265 ds_assemble(i+1,i_regs);
5266 uint64_t bc_unneeded=branch_regs[i].u;
5267 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5268 bc_unneeded|=1|(1LL<<rt1[i]);
5269 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5270 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5271 bc_unneeded,bc_unneeded_upper);
5272 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5273 if(!ra_done&&rt1[i]==31)
5274 ujump_assemble_write_ra(i);
5276 cc=get_reg(branch_regs[i].regmap,CCREG);
5277 assert(cc==HOST_CCREG);
5278 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5280 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5282 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5283 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5284 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5285 if(internal_branch(branch_regs[i].is32,ba[i]))
5286 assem_debug("branch: internal\n");
5288 assem_debug("branch: external\n");
5289 if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5290 ds_assemble_entry(i);
5293 add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5298 static void rjump_assemble_write_ra(int i)
5300 int rt,return_address;
5301 assert(rt1[i+1]!=rt1[i]);
5302 assert(rt2[i+1]!=rt1[i]);
5303 rt=get_reg(branch_regs[i].regmap,rt1[i]);
5304 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5306 return_address=start+i*4+8;
5310 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5313 emit_movimm(return_address,rt); // PC into link register
5315 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5319 void rjump_assemble(int i,struct regstat *i_regs)
5321 signed char *i_regmap=i_regs->regmap;
5325 rs=get_reg(branch_regs[i].regmap,rs1[i]);
5327 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5328 // Delay slot abuse, make a copy of the branch address register
5329 temp=get_reg(branch_regs[i].regmap,RTEMP);
5331 assert(regs[i].regmap[temp]==RTEMP);
5335 address_generation(i+1,i_regs,regs[i].regmap_entry);
5339 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5340 int return_address=start+i*4+8;
5341 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5347 int rh=get_reg(regs[i].regmap,RHASH);
5348 if(rh>=0) do_preload_rhash(rh);
5351 if(rt1[i]!=0&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5352 rjump_assemble_write_ra(i);
5355 ds_assemble(i+1,i_regs);
5356 uint64_t bc_unneeded=branch_regs[i].u;
5357 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5358 bc_unneeded|=1|(1LL<<rt1[i]);
5359 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5360 bc_unneeded&=~(1LL<<rs1[i]);
5361 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5362 bc_unneeded,bc_unneeded_upper);
5363 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5364 if(!ra_done&&rt1[i]!=0)
5365 rjump_assemble_write_ra(i);
5366 cc=get_reg(branch_regs[i].regmap,CCREG);
5367 assert(cc==HOST_CCREG);
5369 int rh=get_reg(branch_regs[i].regmap,RHASH);
5370 int ht=get_reg(branch_regs[i].regmap,RHTBL);
5372 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5373 do_preload_rhtbl(ht);
5377 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5378 #ifdef DESTRUCTIVE_WRITEBACK
5379 if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5380 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5381 emit_loadreg(rs1[i],rs);
5386 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5390 do_miniht_load(ht,rh);
5393 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5394 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5396 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5397 add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5399 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5402 do_miniht_jump(rs,rh,ht);
5407 //if(rs!=EAX) emit_mov(rs,EAX);
5408 //emit_jmp((int)jump_vaddr_eax);
5409 emit_jmp(jump_vaddr_reg[rs]);
5414 emit_shrimm(rs,16,rs);
5415 emit_xor(temp,rs,rs);
5416 emit_movzwl_reg(rs,rs);
5417 emit_shlimm(rs,4,rs);
5418 emit_cmpmem_indexed((int)hash_table,rs,temp);
5419 emit_jne((int)out+14);
5420 emit_readword_indexed((int)hash_table+4,rs,rs);
5422 emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5423 emit_addimm_no_flags(8,rs);
5424 emit_jeq((int)out-17);
5425 // No hit on hash table, call compiler
5428 #ifdef DEBUG_CYCLE_COUNT
5429 emit_readword((int)&last_count,ECX);
5430 emit_add(HOST_CCREG,ECX,HOST_CCREG);
5431 emit_readword((int)&next_interupt,ECX);
5432 emit_writeword(HOST_CCREG,(int)&Count);
5433 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5434 emit_writeword(ECX,(int)&last_count);
5437 emit_storereg(CCREG,HOST_CCREG);
5438 emit_call((int)get_addr);
5439 emit_loadreg(CCREG,HOST_CCREG);
5440 emit_addimm(ESP,4,ESP);
5442 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5443 if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5447 void cjump_assemble(int i,struct regstat *i_regs)
5449 signed char *i_regmap=i_regs->regmap;
5452 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5453 assem_debug("match=%d\n",match);
5454 int s1h,s1l,s2h,s2l;
5455 int prev_cop1_usable=cop1_usable;
5456 int unconditional=0,nop=0;
5459 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5460 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5461 if(!match) invert=1;
5462 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5463 if(i>(ba[i]-start)>>2) invert=1;
5467 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5468 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5469 s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5470 s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5473 s1l=get_reg(i_regmap,rs1[i]);
5474 s1h=get_reg(i_regmap,rs1[i]|64);
5475 s2l=get_reg(i_regmap,rs2[i]);
5476 s2h=get_reg(i_regmap,rs2[i]|64);
5478 if(rs1[i]==0&&rs2[i]==0)
5480 if(opcode[i]&1) nop=1;
5481 else unconditional=1;
5482 //assert(opcode[i]!=5);
5483 //assert(opcode[i]!=7);
5484 //assert(opcode[i]!=0x15);
5485 //assert(opcode[i]!=0x17);
5491 only32=(regs[i].was32>>rs2[i])&1;
5496 only32=(regs[i].was32>>rs1[i])&1;
5499 only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5503 // Out of order execution (delay slot first)
5505 address_generation(i+1,i_regs,regs[i].regmap_entry);
5506 ds_assemble(i+1,i_regs);
5508 uint64_t bc_unneeded=branch_regs[i].u;
5509 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5510 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5511 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5513 bc_unneeded_upper|=1;
5514 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5515 bc_unneeded,bc_unneeded_upper);
5516 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5517 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5518 cc=get_reg(branch_regs[i].regmap,CCREG);
5519 assert(cc==HOST_CCREG);
5521 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5522 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5523 //assem_debug("cycle count (adj)\n");
5525 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5526 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5527 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5528 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5530 assem_debug("branch: internal\n");
5532 assem_debug("branch: external\n");
5533 if(internal&&is_ds[(ba[i]-start)>>2]) {
5534 ds_assemble_entry(i);
5537 add_to_linker((int)out,ba[i],internal);
5540 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5541 if(((u_int)out)&7) emit_addnop(0);
5546 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5549 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5552 int taken=0,nottaken=0,nottaken1=0;
5553 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5554 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5558 if(opcode[i]==4) // BEQ
5560 if(s2h>=0) emit_cmp(s1h,s2h);
5561 else emit_test(s1h,s1h);
5565 if(opcode[i]==5) // BNE
5567 if(s2h>=0) emit_cmp(s1h,s2h);
5568 else emit_test(s1h,s1h);
5569 if(invert) taken=(int)out;
5570 else add_to_linker((int)out,ba[i],internal);
5573 if(opcode[i]==6) // BLEZ
5576 if(invert) taken=(int)out;
5577 else add_to_linker((int)out,ba[i],internal);
5582 if(opcode[i]==7) // BGTZ
5587 if(invert) taken=(int)out;
5588 else add_to_linker((int)out,ba[i],internal);
5593 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5595 if(opcode[i]==4) // BEQ
5597 if(s2l>=0) emit_cmp(s1l,s2l);
5598 else emit_test(s1l,s1l);
5603 add_to_linker((int)out,ba[i],internal);
5607 if(opcode[i]==5) // BNE
5609 if(s2l>=0) emit_cmp(s1l,s2l);
5610 else emit_test(s1l,s1l);
5615 add_to_linker((int)out,ba[i],internal);
5619 if(opcode[i]==6) // BLEZ
5626 add_to_linker((int)out,ba[i],internal);
5630 if(opcode[i]==7) // BGTZ
5637 add_to_linker((int)out,ba[i],internal);
5642 if(taken) set_jump_target(taken,(int)out);
5643 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5644 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5646 emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5647 add_to_linker((int)out,ba[i],internal);
5650 add_to_linker((int)out,ba[i],internal*2);
5656 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5657 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5658 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5660 assem_debug("branch: internal\n");
5662 assem_debug("branch: external\n");
5663 if(internal&&is_ds[(ba[i]-start)>>2]) {
5664 ds_assemble_entry(i);
5667 add_to_linker((int)out,ba[i],internal);
5671 set_jump_target(nottaken,(int)out);
5674 if(nottaken1) set_jump_target(nottaken1,(int)out);
5676 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5678 } // (!unconditional)
5682 // In-order execution (branch first)
5683 //if(likely[i]) printf("IOL\n");
5686 int taken=0,nottaken=0,nottaken1=0;
5687 if(!unconditional&&!nop) {
5691 if((opcode[i]&0x2f)==4) // BEQ
5693 if(s2h>=0) emit_cmp(s1h,s2h);
5694 else emit_test(s1h,s1h);
5698 if((opcode[i]&0x2f)==5) // BNE
5700 if(s2h>=0) emit_cmp(s1h,s2h);
5701 else emit_test(s1h,s1h);
5705 if((opcode[i]&0x2f)==6) // BLEZ
5713 if((opcode[i]&0x2f)==7) // BGTZ
5723 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5725 if((opcode[i]&0x2f)==4) // BEQ
5727 if(s2l>=0) emit_cmp(s1l,s2l);
5728 else emit_test(s1l,s1l);
5732 if((opcode[i]&0x2f)==5) // BNE
5734 if(s2l>=0) emit_cmp(s1l,s2l);
5735 else emit_test(s1l,s1l);
5739 if((opcode[i]&0x2f)==6) // BLEZ
5745 if((opcode[i]&0x2f)==7) // BGTZ
5751 } // if(!unconditional)
5753 uint64_t ds_unneeded=branch_regs[i].u;
5754 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5755 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5756 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5757 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5759 ds_unneeded_upper|=1;
5762 if(taken) set_jump_target(taken,(int)out);
5763 assem_debug("1:\n");
5764 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5765 ds_unneeded,ds_unneeded_upper);
5767 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5768 address_generation(i+1,&branch_regs[i],0);
5769 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5770 ds_assemble(i+1,&branch_regs[i]);
5771 cc=get_reg(branch_regs[i].regmap,CCREG);
5773 emit_loadreg(CCREG,cc=HOST_CCREG);
5774 // CHECK: Is the following instruction (fall thru) allocated ok?
5776 assert(cc==HOST_CCREG);
5777 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5778 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5779 assem_debug("cycle count (adj)\n");
5780 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5781 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5783 assem_debug("branch: internal\n");
5785 assem_debug("branch: external\n");
5786 if(internal&&is_ds[(ba[i]-start)>>2]) {
5787 ds_assemble_entry(i);
5790 add_to_linker((int)out,ba[i],internal);
5795 cop1_usable=prev_cop1_usable;
5796 if(!unconditional) {
5797 if(nottaken1) set_jump_target(nottaken1,(int)out);
5798 set_jump_target(nottaken,(int)out);
5799 assem_debug("2:\n");
5801 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5802 ds_unneeded,ds_unneeded_upper);
5803 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5804 address_generation(i+1,&branch_regs[i],0);
5805 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5806 ds_assemble(i+1,&branch_regs[i]);
5808 cc=get_reg(branch_regs[i].regmap,CCREG);
5809 if(cc==-1&&!likely[i]) {
5810 // Cycle count isn't in a register, temporarily load it then write it out
5811 emit_loadreg(CCREG,HOST_CCREG);
5812 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5815 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5816 emit_storereg(CCREG,HOST_CCREG);
5819 cc=get_reg(i_regmap,CCREG);
5820 assert(cc==HOST_CCREG);
5821 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5824 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5830 void sjump_assemble(int i,struct regstat *i_regs)
5832 signed char *i_regmap=i_regs->regmap;
5835 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5836 assem_debug("smatch=%d\n",match);
5838 int prev_cop1_usable=cop1_usable;
5839 int unconditional=0,nevertaken=0;
5842 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5843 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5844 if(!match) invert=1;
5845 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5846 if(i>(ba[i]-start)>>2) invert=1;
5849 //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
5850 //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
5853 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5854 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5857 s1l=get_reg(i_regmap,rs1[i]);
5858 s1h=get_reg(i_regmap,rs1[i]|64);
5862 if(opcode2[i]&1) unconditional=1;
5864 // These are never taken (r0 is never less than zero)
5865 //assert(opcode2[i]!=0);
5866 //assert(opcode2[i]!=2);
5867 //assert(opcode2[i]!=0x10);
5868 //assert(opcode2[i]!=0x12);
5871 only32=(regs[i].was32>>rs1[i])&1;
5875 // Out of order execution (delay slot first)
5877 address_generation(i+1,i_regs,regs[i].regmap_entry);
5878 ds_assemble(i+1,i_regs);
5880 uint64_t bc_unneeded=branch_regs[i].u;
5881 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5882 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5883 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5885 bc_unneeded_upper|=1;
5886 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5887 bc_unneeded,bc_unneeded_upper);
5888 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5889 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5891 int rt,return_address;
5892 rt=get_reg(branch_regs[i].regmap,31);
5893 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5895 // Save the PC even if the branch is not taken
5896 return_address=start+i*4+8;
5897 emit_movimm(return_address,rt); // PC into link register
5899 if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5903 cc=get_reg(branch_regs[i].regmap,CCREG);
5904 assert(cc==HOST_CCREG);
5906 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5907 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5908 assem_debug("cycle count (adj)\n");
5910 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5911 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5912 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5913 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5915 assem_debug("branch: internal\n");
5917 assem_debug("branch: external\n");
5918 if(internal&&is_ds[(ba[i]-start)>>2]) {
5919 ds_assemble_entry(i);
5922 add_to_linker((int)out,ba[i],internal);
5925 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5926 if(((u_int)out)&7) emit_addnop(0);
5930 else if(nevertaken) {
5931 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5934 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5938 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5939 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5943 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5950 add_to_linker((int)out,ba[i],internal);
5954 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5961 add_to_linker((int)out,ba[i],internal);
5969 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5976 add_to_linker((int)out,ba[i],internal);
5980 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5987 add_to_linker((int)out,ba[i],internal);
5994 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5995 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5997 emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5998 add_to_linker((int)out,ba[i],internal);
6001 add_to_linker((int)out,ba[i],internal*2);
6007 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
6008 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6009 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6011 assem_debug("branch: internal\n");
6013 assem_debug("branch: external\n");
6014 if(internal&&is_ds[(ba[i]-start)>>2]) {
6015 ds_assemble_entry(i);
6018 add_to_linker((int)out,ba[i],internal);
6022 set_jump_target(nottaken,(int)out);
6026 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
6028 } // (!unconditional)
6032 // In-order execution (branch first)
6036 int rt,return_address;
6037 rt=get_reg(branch_regs[i].regmap,31);
6039 // Save the PC even if the branch is not taken
6040 return_address=start+i*4+8;
6041 emit_movimm(return_address,rt); // PC into link register
6043 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
6047 if(!unconditional) {
6048 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6052 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
6058 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
6068 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
6074 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
6081 } // if(!unconditional)
6083 uint64_t ds_unneeded=branch_regs[i].u;
6084 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6085 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6086 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6087 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6089 ds_unneeded_upper|=1;
6092 //assem_debug("1:\n");
6093 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6094 ds_unneeded,ds_unneeded_upper);
6096 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6097 address_generation(i+1,&branch_regs[i],0);
6098 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6099 ds_assemble(i+1,&branch_regs[i]);
6100 cc=get_reg(branch_regs[i].regmap,CCREG);
6102 emit_loadreg(CCREG,cc=HOST_CCREG);
6103 // CHECK: Is the following instruction (fall thru) allocated ok?
6105 assert(cc==HOST_CCREG);
6106 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6107 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6108 assem_debug("cycle count (adj)\n");
6109 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6110 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6112 assem_debug("branch: internal\n");
6114 assem_debug("branch: external\n");
6115 if(internal&&is_ds[(ba[i]-start)>>2]) {
6116 ds_assemble_entry(i);
6119 add_to_linker((int)out,ba[i],internal);
6124 cop1_usable=prev_cop1_usable;
6125 if(!unconditional) {
6126 set_jump_target(nottaken,(int)out);
6127 assem_debug("1:\n");
6129 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6130 ds_unneeded,ds_unneeded_upper);
6131 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6132 address_generation(i+1,&branch_regs[i],0);
6133 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6134 ds_assemble(i+1,&branch_regs[i]);
6136 cc=get_reg(branch_regs[i].regmap,CCREG);
6137 if(cc==-1&&!likely[i]) {
6138 // Cycle count isn't in a register, temporarily load it then write it out
6139 emit_loadreg(CCREG,HOST_CCREG);
6140 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6143 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6144 emit_storereg(CCREG,HOST_CCREG);
6147 cc=get_reg(i_regmap,CCREG);
6148 assert(cc==HOST_CCREG);
6149 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6152 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6158 void fjump_assemble(int i,struct regstat *i_regs)
6160 signed char *i_regmap=i_regs->regmap;
6163 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6164 assem_debug("fmatch=%d\n",match);
6168 int internal=internal_branch(branch_regs[i].is32,ba[i]);
6169 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
6170 if(!match) invert=1;
6171 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6172 if(i>(ba[i]-start)>>2) invert=1;
6176 fs=get_reg(branch_regs[i].regmap,FSREG);
6177 address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
6180 fs=get_reg(i_regmap,FSREG);
6183 // Check cop1 unusable
6185 cs=get_reg(i_regmap,CSREG);
6187 emit_testimm(cs,0x20000000);
6190 add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
6195 // Out of order execution (delay slot first)
6197 ds_assemble(i+1,i_regs);
6199 uint64_t bc_unneeded=branch_regs[i].u;
6200 uint64_t bc_unneeded_upper=branch_regs[i].uu;
6201 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6202 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
6204 bc_unneeded_upper|=1;
6205 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6206 bc_unneeded,bc_unneeded_upper);
6207 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
6208 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6209 cc=get_reg(branch_regs[i].regmap,CCREG);
6210 assert(cc==HOST_CCREG);
6211 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6212 assem_debug("cycle count (adj)\n");
6215 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6218 emit_testimm(fs,0x800000);
6219 if(source[i]&0x10000) // BC1T
6225 add_to_linker((int)out,ba[i],internal);
6234 add_to_linker((int)out,ba[i],internal);
6242 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
6243 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6244 else if(match) emit_addnop(13);
6246 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6247 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6249 assem_debug("branch: internal\n");
6251 assem_debug("branch: external\n");
6252 if(internal&&is_ds[(ba[i]-start)>>2]) {
6253 ds_assemble_entry(i);
6256 add_to_linker((int)out,ba[i],internal);
6259 set_jump_target(nottaken,(int)out);
6263 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
6265 } // (!unconditional)
6269 // In-order execution (branch first)
6273 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6276 emit_testimm(fs,0x800000);
6277 if(source[i]&0x10000) // BC1T
6288 } // if(!unconditional)
6290 uint64_t ds_unneeded=branch_regs[i].u;
6291 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6292 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6293 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6294 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6296 ds_unneeded_upper|=1;
6298 //assem_debug("1:\n");
6299 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6300 ds_unneeded,ds_unneeded_upper);
6302 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6303 address_generation(i+1,&branch_regs[i],0);
6304 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6305 ds_assemble(i+1,&branch_regs[i]);
6306 cc=get_reg(branch_regs[i].regmap,CCREG);
6308 emit_loadreg(CCREG,cc=HOST_CCREG);
6309 // CHECK: Is the following instruction (fall thru) allocated ok?
6311 assert(cc==HOST_CCREG);
6312 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6313 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6314 assem_debug("cycle count (adj)\n");
6315 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6316 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6318 assem_debug("branch: internal\n");
6320 assem_debug("branch: external\n");
6321 if(internal&&is_ds[(ba[i]-start)>>2]) {
6322 ds_assemble_entry(i);
6325 add_to_linker((int)out,ba[i],internal);
6330 if(1) { // <- FIXME (don't need this)
6331 set_jump_target(nottaken,(int)out);
6332 assem_debug("1:\n");
6334 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6335 ds_unneeded,ds_unneeded_upper);
6336 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6337 address_generation(i+1,&branch_regs[i],0);
6338 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6339 ds_assemble(i+1,&branch_regs[i]);
6341 cc=get_reg(branch_regs[i].regmap,CCREG);
6342 if(cc==-1&&!likely[i]) {
6343 // Cycle count isn't in a register, temporarily load it then write it out
6344 emit_loadreg(CCREG,HOST_CCREG);
6345 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6348 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6349 emit_storereg(CCREG,HOST_CCREG);
6352 cc=get_reg(i_regmap,CCREG);
6353 assert(cc==HOST_CCREG);
6354 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6357 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6363 static void pagespan_assemble(int i,struct regstat *i_regs)
6365 int s1l=get_reg(i_regs->regmap,rs1[i]);
6366 int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6367 int s2l=get_reg(i_regs->regmap,rs2[i]);
6368 int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6369 void *nt_branch=NULL;
6372 int unconditional=0;
6382 if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6386 int addr,alt,ntaddr;
6387 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6391 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6392 (i_regs->regmap[hr]&63)!=rs1[i] &&
6393 (i_regs->regmap[hr]&63)!=rs2[i] )
6402 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6403 (i_regs->regmap[hr]&63)!=rs1[i] &&
6404 (i_regs->regmap[hr]&63)!=rs2[i] )
6410 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6414 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6415 (i_regs->regmap[hr]&63)!=rs1[i] &&
6416 (i_regs->regmap[hr]&63)!=rs2[i] )
6423 assert(hr<HOST_REGS);
6424 if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6425 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6427 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6428 if(opcode[i]==2) // J
6432 if(opcode[i]==3) // JAL
6435 int rt=get_reg(i_regs->regmap,31);
6436 emit_movimm(start+i*4+8,rt);
6439 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6442 if(opcode2[i]==9) // JALR
6444 int rt=get_reg(i_regs->regmap,rt1[i]);
6445 emit_movimm(start+i*4+8,rt);
6448 if((opcode[i]&0x3f)==4) // BEQ
6455 #ifdef HAVE_CMOV_IMM
6457 if(s2l>=0) emit_cmp(s1l,s2l);
6458 else emit_test(s1l,s1l);
6459 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6465 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6467 if(s2h>=0) emit_cmp(s1h,s2h);
6468 else emit_test(s1h,s1h);
6469 emit_cmovne_reg(alt,addr);
6471 if(s2l>=0) emit_cmp(s1l,s2l);
6472 else emit_test(s1l,s1l);
6473 emit_cmovne_reg(alt,addr);
6476 if((opcode[i]&0x3f)==5) // BNE
6478 #ifdef HAVE_CMOV_IMM
6480 if(s2l>=0) emit_cmp(s1l,s2l);
6481 else emit_test(s1l,s1l);
6482 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6488 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6490 if(s2h>=0) emit_cmp(s1h,s2h);
6491 else emit_test(s1h,s1h);
6492 emit_cmovne_reg(alt,addr);
6494 if(s2l>=0) emit_cmp(s1l,s2l);
6495 else emit_test(s1l,s1l);
6496 emit_cmovne_reg(alt,addr);
6499 if((opcode[i]&0x3f)==0x14) // BEQL
6502 if(s2h>=0) emit_cmp(s1h,s2h);
6503 else emit_test(s1h,s1h);
6507 if(s2l>=0) emit_cmp(s1l,s2l);
6508 else emit_test(s1l,s1l);
6509 if(nottaken) set_jump_target(nottaken,(int)out);
6513 if((opcode[i]&0x3f)==0x15) // BNEL
6516 if(s2h>=0) emit_cmp(s1h,s2h);
6517 else emit_test(s1h,s1h);
6521 if(s2l>=0) emit_cmp(s1l,s2l);
6522 else emit_test(s1l,s1l);
6525 if(taken) set_jump_target(taken,(int)out);
6527 if((opcode[i]&0x3f)==6) // BLEZ
6529 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6531 if(s1h>=0) emit_mov(addr,ntaddr);
6532 emit_cmovl_reg(alt,addr);
6535 emit_cmovne_reg(ntaddr,addr);
6536 emit_cmovs_reg(alt,addr);
6539 if((opcode[i]&0x3f)==7) // BGTZ
6541 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6543 if(s1h>=0) emit_mov(addr,alt);
6544 emit_cmovl_reg(ntaddr,addr);
6547 emit_cmovne_reg(alt,addr);
6548 emit_cmovs_reg(ntaddr,addr);
6551 if((opcode[i]&0x3f)==0x16) // BLEZL
6553 assert((opcode[i]&0x3f)!=0x16);
6555 if((opcode[i]&0x3f)==0x17) // BGTZL
6557 assert((opcode[i]&0x3f)!=0x17);
6559 assert(opcode[i]!=1); // BLTZ/BGEZ
6561 //FIXME: Check CSREG
6562 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6563 if((source[i]&0x30000)==0) // BC1F
6565 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6566 emit_testimm(s1l,0x800000);
6567 emit_cmovne_reg(alt,addr);
6569 if((source[i]&0x30000)==0x10000) // BC1T
6571 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6572 emit_testimm(s1l,0x800000);
6573 emit_cmovne_reg(alt,addr);
6575 if((source[i]&0x30000)==0x20000) // BC1FL
6577 emit_testimm(s1l,0x800000);
6581 if((source[i]&0x30000)==0x30000) // BC1TL
6583 emit_testimm(s1l,0x800000);
6589 assert(i_regs->regmap[HOST_CCREG]==CCREG);
6590 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6591 if(likely[i]||unconditional)
6593 emit_movimm(ba[i],HOST_BTREG);
6595 else if(addr!=HOST_BTREG)
6597 emit_mov(addr,HOST_BTREG);
6599 void *branch_addr=out;
6601 int target_addr=start+i*4+5;
6603 void *compiled_target_addr=check_addr(target_addr);
6604 emit_extjump_ds((int)branch_addr,target_addr);
6605 if(compiled_target_addr) {
6606 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6607 add_link(target_addr,stub);
6609 else set_jump_target((int)branch_addr,(int)stub);
6612 set_jump_target((int)nottaken,(int)out);
6613 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6614 void *branch_addr=out;
6616 int target_addr=start+i*4+8;
6618 void *compiled_target_addr=check_addr(target_addr);
6619 emit_extjump_ds((int)branch_addr,target_addr);
6620 if(compiled_target_addr) {
6621 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6622 add_link(target_addr,stub);
6624 else set_jump_target((int)branch_addr,(int)stub);
6628 // Assemble the delay slot for the above
6629 static void pagespan_ds()
6631 assem_debug("initial delay slot:\n");
6632 u_int vaddr=start+1;
6633 u_int page=get_page(vaddr);
6634 u_int vpage=get_vpage(vaddr);
6635 ll_add(jump_dirty+vpage,vaddr,(void *)out);
6637 ll_add(jump_in+page,vaddr,(void *)out);
6638 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6639 if(regs[0].regmap[HOST_CCREG]!=CCREG)
6640 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6641 if(regs[0].regmap[HOST_BTREG]!=BTREG)
6642 emit_writeword(HOST_BTREG,(int)&branch_target);
6643 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6644 address_generation(0,®s[0],regs[0].regmap_entry);
6645 if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
6646 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6651 alu_assemble(0,®s[0]);break;
6653 imm16_assemble(0,®s[0]);break;
6655 shift_assemble(0,®s[0]);break;
6657 shiftimm_assemble(0,®s[0]);break;
6659 load_assemble(0,®s[0]);break;
6661 loadlr_assemble(0,®s[0]);break;
6663 store_assemble(0,®s[0]);break;
6665 storelr_assemble(0,®s[0]);break;
6667 cop0_assemble(0,®s[0]);break;
6669 cop1_assemble(0,®s[0]);break;
6671 c1ls_assemble(0,®s[0]);break;
6673 cop2_assemble(0,®s[0]);break;
6675 c2ls_assemble(0,®s[0]);break;
6677 c2op_assemble(0,®s[0]);break;
6679 fconv_assemble(0,®s[0]);break;
6681 float_assemble(0,®s[0]);break;
6683 fcomp_assemble(0,®s[0]);break;
6685 multdiv_assemble(0,®s[0]);break;
6687 mov_assemble(0,®s[0]);break;
6697 printf("Jump in the delay slot. This is probably a bug.\n");
6699 int btaddr=get_reg(regs[0].regmap,BTREG);
6701 btaddr=get_reg(regs[0].regmap,-1);
6702 emit_readword((int)&branch_target,btaddr);
6704 assert(btaddr!=HOST_CCREG);
6705 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6707 emit_movimm(start+4,HOST_TEMPREG);
6708 emit_cmp(btaddr,HOST_TEMPREG);
6710 emit_cmpimm(btaddr,start+4);
6712 int branch=(int)out;
6714 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6715 emit_jmp(jump_vaddr_reg[btaddr]);
6716 set_jump_target(branch,(int)out);
6717 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6718 load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6721 // Basic liveness analysis for MIPS registers
6722 void unneeded_registers(int istart,int iend,int r)
6725 uint64_t u,uu,gte_u,b,bu,gte_bu;
6726 uint64_t temp_u,temp_uu,temp_gte_u;
6731 u=unneeded_reg[iend+1];
6732 uu=unneeded_reg_upper[iend+1];
6737 for (i=iend;i>=istart;i--)
6739 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6740 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6742 // If subroutine call, flag return address as a possible branch target
6743 if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6745 if(ba[i]<start || ba[i]>=(start+slen*4))
6747 // Branch out of this block, flush all regs
6752 if(itype[i]==UJUMP&&rt1[i]==31)
6754 uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6756 if(itype[i]==RJUMP&&rs1[i]==31)
6758 uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6760 if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
6761 if(itype[i]==UJUMP&&rt1[i]==31)
6763 //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6764 uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6766 if(itype[i]==RJUMP&&rs1[i]==31)
6768 //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6769 uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6772 branch_unneeded_reg[i]=u;
6773 branch_unneeded_reg_upper[i]=uu;
6774 // Merge in delay slot
6775 tdep=(~uu>>rt1[i+1])&1;
6776 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6777 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6778 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6779 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6780 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6783 gte_u&=~gte_rs[i+1];
6784 // If branch is "likely" (and conditional)
6785 // then we skip the delay slot on the fall-thru path
6788 u&=unneeded_reg[i+2];
6789 uu&=unneeded_reg_upper[i+2];
6790 gte_u&=gte_unneeded[i+2];
6802 // Internal branch, flag target
6803 bt[(ba[i]-start)>>2]=1;
6804 if(ba[i]<=start+i*4) {
6806 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6808 // Unconditional branch
6812 // Conditional branch (not taken case)
6813 temp_u=unneeded_reg[i+2];
6814 temp_uu=unneeded_reg_upper[i+2];
6815 temp_gte_u&=gte_unneeded[i+2];
6817 // Merge in delay slot
6818 tdep=(~temp_uu>>rt1[i+1])&1;
6819 temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6820 temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6821 temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6822 temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6823 temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6824 temp_u|=1;temp_uu|=1;
6825 temp_gte_u|=gte_rt[i+1];
6826 temp_gte_u&=~gte_rs[i+1];
6827 // If branch is "likely" (and conditional)
6828 // then we skip the delay slot on the fall-thru path
6831 temp_u&=unneeded_reg[i+2];
6832 temp_uu&=unneeded_reg_upper[i+2];
6833 temp_gte_u&=gte_unneeded[i+2];
6842 tdep=(~temp_uu>>rt1[i])&1;
6843 temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6844 temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6845 temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6846 temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6847 temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6848 temp_u|=1;temp_uu|=1;
6849 temp_gte_u|=gte_rt[i];
6850 temp_gte_u&=~gte_rs[i];
6851 unneeded_reg[i]=temp_u;
6852 unneeded_reg_upper[i]=temp_uu;
6853 gte_unneeded[i]=temp_gte_u;
6854 // Only go three levels deep. This recursion can take an
6855 // excessive amount of time if there are a lot of nested loops.
6857 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6859 unneeded_reg[(ba[i]-start)>>2]=1;
6860 unneeded_reg_upper[(ba[i]-start)>>2]=1;
6861 gte_unneeded[(ba[i]-start)>>2]=0;
6864 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6866 // Unconditional branch
6867 u=unneeded_reg[(ba[i]-start)>>2];
6868 uu=unneeded_reg_upper[(ba[i]-start)>>2];
6869 gte_u=gte_unneeded[(ba[i]-start)>>2];
6870 branch_unneeded_reg[i]=u;
6871 branch_unneeded_reg_upper[i]=uu;
6874 //branch_unneeded_reg[i]=u;
6875 //branch_unneeded_reg_upper[i]=uu;
6876 // Merge in delay slot
6877 tdep=(~uu>>rt1[i+1])&1;
6878 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6879 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6880 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6881 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6882 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6885 gte_u&=~gte_rs[i+1];
6887 // Conditional branch
6888 b=unneeded_reg[(ba[i]-start)>>2];
6889 bu=unneeded_reg_upper[(ba[i]-start)>>2];
6890 gte_bu=gte_unneeded[(ba[i]-start)>>2];
6891 branch_unneeded_reg[i]=b;
6892 branch_unneeded_reg_upper[i]=bu;
6895 //branch_unneeded_reg[i]=b;
6896 //branch_unneeded_reg_upper[i]=bu;
6897 // Branch delay slot
6898 tdep=(~uu>>rt1[i+1])&1;
6899 b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6900 bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6901 b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6902 bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6903 bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6905 gte_bu|=gte_rt[i+1];
6906 gte_bu&=~gte_rs[i+1];
6907 // If branch is "likely" then we skip the
6908 // delay slot on the fall-thru path
6914 u&=unneeded_reg[i+2];
6915 uu&=unneeded_reg_upper[i+2];
6916 gte_u&=gte_unneeded[i+2];
6928 branch_unneeded_reg[i]&=unneeded_reg[i+2];
6929 branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6930 //branch_unneeded_reg[i]=1;
6931 //branch_unneeded_reg_upper[i]=1;
6933 branch_unneeded_reg[i]=1;
6934 branch_unneeded_reg_upper[i]=1;
6940 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
6942 // SYSCALL instruction (software interrupt)
6946 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6948 // ERET instruction (return from interrupt)
6953 tdep=(~uu>>rt1[i])&1;
6954 // Written registers are unneeded
6960 // Accessed registers are needed
6966 // Source-target dependencies
6967 uu&=~(tdep<<dep1[i]);
6968 uu&=~(tdep<<dep2[i]);
6969 // R0 is always unneeded
6973 unneeded_reg_upper[i]=uu;
6974 gte_unneeded[i]=gte_u;
6976 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6979 for(r=1;r<=CCREG;r++) {
6980 if((unneeded_reg[i]>>r)&1) {
6981 if(r==HIREG) printf(" HI");
6982 else if(r==LOREG) printf(" LO");
6983 else printf(" r%d",r);
6987 for(r=1;r<=CCREG;r++) {
6988 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
6989 if(r==HIREG) printf(" HI");
6990 else if(r==LOREG) printf(" LO");
6991 else printf(" r%d",r);
6997 for (i=iend;i>=istart;i--)
6999 unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
7004 // Identify registers which are likely to contain 32-bit values
7005 // This is used to predict whether any branches will jump to a
7006 // location with 64-bit values in registers.
7007 static void provisional_32bit()
7011 uint64_t lastbranch=1;
7016 if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
7017 if(i>1) is32=lastbranch;
7023 if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
7025 if(i>2) is32=lastbranch;
7029 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
7031 if(rs1[i-2]==0||rs2[i-2]==0)
7034 is32|=1LL<<rs1[i-2];
7037 is32|=1LL<<rs2[i-2];
7042 // If something jumps here with 64-bit values
7043 // then promote those registers to 64 bits
7046 uint64_t temp_is32=is32;
7049 if(ba[j]==start+i*4)
7050 //temp_is32&=branch_regs[j].is32;
7055 if(ba[j]==start+i*4)
7066 if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
7067 // Branches don't write registers, consider the delay slot instead.
7078 if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
7079 opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
7088 if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
7089 if(op==0x22) is32|=1LL<<rt; // LWL
7092 if (op==0x08||op==0x09|| // ADDI/ADDIU
7093 op==0x0a||op==0x0b|| // SLTI/SLTIU
7099 if(op==0x18||op==0x19) { // DADDI/DADDIU
7102 // is32|=((is32>>s1)&1LL)<<rt;
7104 if(op==0x0d||op==0x0e) { // ORI/XORI
7105 uint64_t sr=((is32>>s1)&1LL);
7121 if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
7124 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
7127 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
7128 uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
7132 else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
7137 uint64_t sr=((is32>>s1)&1LL);
7142 uint64_t sr=((is32>>s2)&1LL);
7150 else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
7155 uint64_t sr=((is32>>s1)&1LL);
7165 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
7166 is32&=~((1LL<<HIREG)|(1LL<<LOREG));
7169 is32|=(1LL<<HIREG)|(1LL<<LOREG);
7174 uint64_t sr=((is32>>s1)&1LL);
7180 if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
7181 else is32|=1LL<<rt; // SLLV/SRLV/SRAV
7185 // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
7186 if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
7189 if(op2==0) is32|=1LL<<rt; // MFC0
7193 if(op2==0) is32|=1LL<<rt; // MFC1
7194 if(op2==1) is32&=~(1LL<<rt); // DMFC1
7195 if(op2==2) is32|=1LL<<rt; // CFC1
7217 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
7219 if(rt1[i-1]==31) // JAL/JALR
7221 // Subroutine call will return here, don't alloc any registers
7226 // Internal branch will jump here, match registers to caller
7234 // Identify registers which may be assumed to contain 32-bit values
7235 // and where optimizations will rely on this.
7236 // This is used to determine whether backward branches can safely
7237 // jump to a location with 64-bit values in registers.
7238 static void provisional_r32()
7243 for (i=slen-1;i>=0;i--)
7246 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7248 if(ba[i]<start || ba[i]>=(start+slen*4))
7250 // Branch out of this block, don't need anything
7256 // Need whatever matches the target
7257 // (and doesn't get overwritten by the delay slot instruction)
7259 int t=(ba[i]-start)>>2;
7260 if(ba[i]>start+i*4) {
7262 //if(!(requires_32bit[t]&~regs[i].was32))
7263 // r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7264 if(!(pr32[t]&~regs[i].was32))
7265 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7268 if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
7269 r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7272 // Conditional branch may need registers for following instructions
7273 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7276 //r32|=requires_32bit[i+2];
7279 // Mark this address as a branch target since it may be called
7280 // upon return from interrupt
7284 // Merge in delay slot
7286 // These are overwritten unless the branch is "likely"
7287 // and the delay slot is nullified if not taken
7288 r32&=~(1LL<<rt1[i+1]);
7289 r32&=~(1LL<<rt2[i+1]);
7291 // Assume these are needed (delay slot)
7294 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7298 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7300 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7302 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7304 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7306 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7309 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7311 // SYSCALL instruction (software interrupt)
7314 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7316 // ERET instruction (return from interrupt)
7320 r32&=~(1LL<<rt1[i]);
7321 r32&=~(1LL<<rt2[i]);
7324 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7328 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7330 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7332 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7334 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7336 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7338 //requires_32bit[i]=r32;
7341 // Dirty registers which are 32-bit, require 32-bit input
7342 // as they will be written as 32-bit values
7343 for(hr=0;hr<HOST_REGS;hr++)
7345 if(regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64) {
7346 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7347 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7348 pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7349 //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7356 // Write back dirty registers as soon as we will no longer modify them,
7357 // so that we don't end up with lots of writes at the branches.
7358 void clean_registers(int istart,int iend,int wr)
7362 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7363 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7365 will_dirty_i=will_dirty_next=0;
7366 wont_dirty_i=wont_dirty_next=0;
7368 will_dirty_i=will_dirty_next=will_dirty[iend+1];
7369 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7371 for (i=iend;i>=istart;i--)
7373 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7375 if(ba[i]<start || ba[i]>=(start+slen*4))
7377 // Branch out of this block, flush all regs
7378 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7380 // Unconditional branch
7383 // Merge in delay slot (will dirty)
7384 for(r=0;r<HOST_REGS;r++) {
7385 if(r!=EXCLUDE_REG) {
7386 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7387 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7388 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7389 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7390 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7391 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7392 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7393 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7394 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7395 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7396 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7397 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7398 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7399 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7405 // Conditional branch
7407 wont_dirty_i=wont_dirty_next;
7408 // Merge in delay slot (will dirty)
7409 for(r=0;r<HOST_REGS;r++) {
7410 if(r!=EXCLUDE_REG) {
7412 // Might not dirty if likely branch is not taken
7413 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7414 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7415 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7416 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7417 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7418 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7419 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7420 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7421 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7422 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7423 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7424 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7425 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7426 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7431 // Merge in delay slot (wont dirty)
7432 for(r=0;r<HOST_REGS;r++) {
7433 if(r!=EXCLUDE_REG) {
7434 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7435 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7436 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7437 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7438 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7439 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7440 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7441 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7442 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7443 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7447 #ifndef DESTRUCTIVE_WRITEBACK
7448 branch_regs[i].dirty&=wont_dirty_i;
7450 branch_regs[i].dirty|=will_dirty_i;
7456 if(ba[i]<=start+i*4) {
7458 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7460 // Unconditional branch
7463 // Merge in delay slot (will dirty)
7464 for(r=0;r<HOST_REGS;r++) {
7465 if(r!=EXCLUDE_REG) {
7466 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7467 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7468 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7469 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7470 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7471 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7472 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7473 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7474 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7475 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7476 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7477 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7478 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7479 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7483 // Conditional branch (not taken case)
7484 temp_will_dirty=will_dirty_next;
7485 temp_wont_dirty=wont_dirty_next;
7486 // Merge in delay slot (will dirty)
7487 for(r=0;r<HOST_REGS;r++) {
7488 if(r!=EXCLUDE_REG) {
7490 // Will not dirty if likely branch is not taken
7491 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7492 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7493 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7494 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7495 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7496 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7497 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7498 //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7499 //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7500 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7501 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7502 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7503 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7504 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7509 // Merge in delay slot (wont dirty)
7510 for(r=0;r<HOST_REGS;r++) {
7511 if(r!=EXCLUDE_REG) {
7512 if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7513 if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7514 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7515 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7516 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7517 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7518 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7519 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7520 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7521 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7524 // Deal with changed mappings
7526 for(r=0;r<HOST_REGS;r++) {
7527 if(r!=EXCLUDE_REG) {
7528 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7529 temp_will_dirty&=~(1<<r);
7530 temp_wont_dirty&=~(1<<r);
7531 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7532 temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7533 temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7535 temp_will_dirty|=1<<r;
7536 temp_wont_dirty|=1<<r;
7543 will_dirty[i]=temp_will_dirty;
7544 wont_dirty[i]=temp_wont_dirty;
7545 clean_registers((ba[i]-start)>>2,i-1,0);
7547 // Limit recursion. It can take an excessive amount
7548 // of time if there are a lot of nested loops.
7549 will_dirty[(ba[i]-start)>>2]=0;
7550 wont_dirty[(ba[i]-start)>>2]=-1;
7555 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7557 // Unconditional branch
7560 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7561 for(r=0;r<HOST_REGS;r++) {
7562 if(r!=EXCLUDE_REG) {
7563 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7564 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7565 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7567 if(branch_regs[i].regmap[r]>=0) {
7568 will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7569 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7574 // Merge in delay slot
7575 for(r=0;r<HOST_REGS;r++) {
7576 if(r!=EXCLUDE_REG) {
7577 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7578 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7579 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7580 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7581 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7582 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7583 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7584 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7585 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7586 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7587 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7588 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7589 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7590 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7594 // Conditional branch
7595 will_dirty_i=will_dirty_next;
7596 wont_dirty_i=wont_dirty_next;
7597 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7598 for(r=0;r<HOST_REGS;r++) {
7599 if(r!=EXCLUDE_REG) {
7600 signed char target_reg=branch_regs[i].regmap[r];
7601 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7602 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7603 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7605 else if(target_reg>=0) {
7606 will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7607 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7609 // Treat delay slot as part of branch too
7610 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7611 will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7612 wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7616 will_dirty[i+1]&=~(1<<r);
7621 // Merge in delay slot
7622 for(r=0;r<HOST_REGS;r++) {
7623 if(r!=EXCLUDE_REG) {
7625 // Might not dirty if likely branch is not taken
7626 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7627 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7628 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7629 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7630 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7631 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7632 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7633 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7634 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7635 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7636 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7637 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7638 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7639 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7644 // Merge in delay slot (won't dirty)
7645 for(r=0;r<HOST_REGS;r++) {
7646 if(r!=EXCLUDE_REG) {
7647 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7648 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7649 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7650 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7651 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7652 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7653 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7654 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7655 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7656 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7660 #ifndef DESTRUCTIVE_WRITEBACK
7661 branch_regs[i].dirty&=wont_dirty_i;
7663 branch_regs[i].dirty|=will_dirty_i;
7668 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7670 // SYSCALL instruction (software interrupt)
7674 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7676 // ERET instruction (return from interrupt)
7680 will_dirty_next=will_dirty_i;
7681 wont_dirty_next=wont_dirty_i;
7682 for(r=0;r<HOST_REGS;r++) {
7683 if(r!=EXCLUDE_REG) {
7684 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7685 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7686 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7687 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7688 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7689 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7690 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7691 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7693 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7695 // Don't store a register immediately after writing it,
7696 // may prevent dual-issue.
7697 if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7698 if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7704 will_dirty[i]=will_dirty_i;
7705 wont_dirty[i]=wont_dirty_i;
7706 // Mark registers that won't be dirtied as not dirty
7708 /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7709 for(r=0;r<HOST_REGS;r++) {
7710 if((will_dirty_i>>r)&1) {
7716 //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7717 regs[i].dirty|=will_dirty_i;
7718 #ifndef DESTRUCTIVE_WRITEBACK
7719 regs[i].dirty&=wont_dirty_i;
7720 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7722 if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7723 for(r=0;r<HOST_REGS;r++) {
7724 if(r!=EXCLUDE_REG) {
7725 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7726 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7727 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7735 for(r=0;r<HOST_REGS;r++) {
7736 if(r!=EXCLUDE_REG) {
7737 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7738 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7739 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7747 // Deal with changed mappings
7748 temp_will_dirty=will_dirty_i;
7749 temp_wont_dirty=wont_dirty_i;
7750 for(r=0;r<HOST_REGS;r++) {
7751 if(r!=EXCLUDE_REG) {
7753 if(regs[i].regmap[r]==regmap_pre[i][r]) {
7755 #ifndef DESTRUCTIVE_WRITEBACK
7756 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7758 regs[i].wasdirty|=will_dirty_i&(1<<r);
7761 else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7762 // Register moved to a different register
7763 will_dirty_i&=~(1<<r);
7764 wont_dirty_i&=~(1<<r);
7765 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7766 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7768 #ifndef DESTRUCTIVE_WRITEBACK
7769 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7771 regs[i].wasdirty|=will_dirty_i&(1<<r);
7775 will_dirty_i&=~(1<<r);
7776 wont_dirty_i&=~(1<<r);
7777 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7778 will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7779 wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7782 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7792 void disassemble_inst(int i)
7794 if (bt[i]) printf("*"); else printf(" ");
7797 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7799 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7801 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7803 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7805 if (opcode[i]==0x9&&rt1[i]!=31)
7806 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7808 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7811 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7813 if(opcode[i]==0xf) //LUI
7814 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7816 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7820 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7824 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7828 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7831 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7834 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7837 if((opcode2[i]&0x1d)==0x10)
7838 printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7839 else if((opcode2[i]&0x1d)==0x11)
7840 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7842 printf (" %x: %s\n",start+i*4,insn[i]);
7846 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7847 else if(opcode2[i]==4)
7848 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7849 else printf (" %x: %s\n",start+i*4,insn[i]);
7853 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7854 else if(opcode2[i]>3)
7855 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7856 else printf (" %x: %s\n",start+i*4,insn[i]);
7860 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7861 else if(opcode2[i]>3)
7862 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7863 else printf (" %x: %s\n",start+i*4,insn[i]);
7866 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7869 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7872 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
7875 //printf (" %s %8x\n",insn[i],source[i]);
7876 printf (" %x: %s\n",start+i*4,insn[i]);
7880 static void disassemble_inst(int i) {}
7883 // clear the state completely, instead of just marking
7884 // things invalid like invalidate_all_pages() does
7885 void new_dynarec_clear_full()
7888 out=(u_char *)BASE_ADDR;
7889 memset(invalid_code,1,sizeof(invalid_code));
7890 memset(hash_table,0xff,sizeof(hash_table));
7891 memset(mini_ht,-1,sizeof(mini_ht));
7892 memset(restore_candidate,0,sizeof(restore_candidate));
7893 memset(shadow,0,sizeof(shadow));
7895 expirep=16384; // Expiry pointer, +2 blocks
7896 pending_exception=0;
7899 inv_code_start=inv_code_end=~0;
7906 for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7908 for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7909 memory_map[n]=((u_int)rdram-0x80000000)>>2;
7910 for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7912 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7913 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7914 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7917 void new_dynarec_init()
7919 printf("Init new dynarec\n");
7920 out=(u_char *)BASE_ADDR;
7921 if (mmap (out, 1<<TARGET_SIZE_2,
7922 PROT_READ | PROT_WRITE | PROT_EXEC,
7923 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
7924 -1, 0) <= 0) {printf("mmap() failed\n");}
7926 rdword=&readmem_dword;
7927 fake_pc.f.r.rs=&readmem_dword;
7928 fake_pc.f.r.rt=&readmem_dword;
7929 fake_pc.f.r.rd=&readmem_dword;
7932 new_dynarec_clear_full();
7934 // Copy this into local area so we don't have to put it in every literal pool
7935 invc_ptr=invalid_code;
7938 for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
7939 writemem[n] = write_nomem_new;
7940 writememb[n] = write_nomemb_new;
7941 writememh[n] = write_nomemh_new;
7943 writememd[n] = write_nomemd_new;
7945 readmem[n] = read_nomem_new;
7946 readmemb[n] = read_nomemb_new;
7947 readmemh[n] = read_nomemh_new;
7949 readmemd[n] = read_nomemd_new;
7952 for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
7953 writemem[n] = write_rdram_new;
7954 writememb[n] = write_rdramb_new;
7955 writememh[n] = write_rdramh_new;
7957 writememd[n] = write_rdramd_new;
7960 for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
7961 writemem[n] = write_nomem_new;
7962 writememb[n] = write_nomemb_new;
7963 writememh[n] = write_nomemh_new;
7965 writememd[n] = write_nomemd_new;
7967 readmem[n] = read_nomem_new;
7968 readmemb[n] = read_nomemb_new;
7969 readmemh[n] = read_nomemh_new;
7971 readmemd[n] = read_nomemd_new;
7979 void new_dynarec_cleanup()
7982 if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
7983 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7984 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7985 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7987 if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
7991 int new_recompile_block(int addr)
7994 if(addr==0x800cd050) {
7996 for(block=0x80000;block<0x80800;block++) invalidate_block(block);
7998 for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
8001 //if(Count==365117028) tracedebug=1;
8002 assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
8003 //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
8004 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
8006 //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
8007 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
8008 /*if(Count>=312978186) {
8012 start = (u_int)addr&~3;
8013 //assert(((u_int)addr&1)==0);
8015 if(!sp_in_mirror&&(signed int)(psxRegs.GPR.n.sp&0xffe00000)>0x80200000&&
8016 0x10000<=psxRegs.GPR.n.sp&&(psxRegs.GPR.n.sp&~0xe0e00000)<RAM_SIZE) {
8017 printf("SP hack enabled (%08x), @%08x\n", psxRegs.GPR.n.sp, psxRegs.pc);
8020 if (Config.HLE && start == 0x80001000) // hlecall
8022 // XXX: is this enough? Maybe check hleSoftCall?
8023 u_int beginning=(u_int)out;
8024 u_int page=get_page(start);
8025 invalid_code[start>>12]=0;
8026 emit_movimm(start,0);
8027 emit_writeword(0,(int)&pcaddr);
8028 emit_jmp((int)new_dyna_leave);
8031 __clear_cache((void *)beginning,out);
8033 ll_add(jump_in+page,start,(void *)beginning);
8036 else if ((u_int)addr < 0x00200000 ||
8037 (0xa0000000 <= addr && addr < 0xa0200000)) {
8038 // used for BIOS calls mostly?
8039 source = (u_int *)((u_int)rdram+(start&0x1fffff));
8040 pagelimit = (addr&0xa0000000)|0x00200000;
8042 else if (!Config.HLE && (
8043 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
8044 (0xbfc00000 <= addr && addr < 0xbfc80000))) {
8046 source = (u_int *)((u_int)psxR+(start&0x7ffff));
8047 pagelimit = (addr&0xfff00000)|0x80000;
8052 if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
8053 source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
8054 pagelimit = 0xa4001000;
8058 if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
8059 source = (u_int *)((u_int)rdram+start-0x80000000);
8060 pagelimit = 0x80000000+RAM_SIZE;
8063 else if ((signed int)addr >= (signed int)0xC0000000) {
8064 //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
8065 //if(tlb_LUT_r[start>>12])
8066 //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
8067 if((signed int)memory_map[start>>12]>=0) {
8068 source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
8069 pagelimit=(start+4096)&0xFFFFF000;
8070 int map=memory_map[start>>12];
8073 //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
8074 if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
8076 assem_debug("pagelimit=%x\n",pagelimit);
8077 assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
8080 assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
8081 //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
8082 return -1; // Caller will invoke exception handler
8084 //printf("source= %x\n",(int)source);
8088 printf("Compile at bogus memory address: %x \n", (int)addr);
8092 /* Pass 1: disassemble */
8093 /* Pass 2: register dependencies, branch targets */
8094 /* Pass 3: register allocation */
8095 /* Pass 4: branch dependencies */
8096 /* Pass 5: pre-alloc */
8097 /* Pass 6: optimize clean/dirty state */
8098 /* Pass 7: flag 32-bit registers */
8099 /* Pass 8: assembly */
8100 /* Pass 9: linker */
8101 /* Pass 10: garbage collection / free memory */
8105 unsigned int type,op,op2;
8107 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
8109 /* Pass 1 disassembly */
8111 for(i=0;!done;i++) {
8112 bt[i]=0;likely[i]=0;ooo[i]=0;op2=0;
8113 minimum_free_regs[i]=0;
8114 opcode[i]=op=source[i]>>26;
8117 case 0x00: strcpy(insn[i],"special"); type=NI;
8121 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
8122 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
8123 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
8124 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
8125 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
8126 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
8127 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
8128 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
8129 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
8130 case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
8131 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
8132 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
8133 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
8134 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
8135 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
8136 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
8137 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
8138 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
8139 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
8140 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
8141 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
8142 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
8143 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
8144 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
8145 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
8146 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
8147 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
8148 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
8149 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
8150 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
8151 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
8152 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
8153 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
8154 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
8155 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
8157 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
8158 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
8159 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
8160 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
8161 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
8162 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
8163 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
8164 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
8165 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
8166 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
8167 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
8168 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
8169 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
8170 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
8171 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
8172 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
8173 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
8177 case 0x01: strcpy(insn[i],"regimm"); type=NI;
8178 op2=(source[i]>>16)&0x1f;
8181 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
8182 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
8183 case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
8184 case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
8185 case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
8186 case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
8187 case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
8188 case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
8189 case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
8190 case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
8191 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
8192 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
8193 case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
8194 case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
8197 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
8198 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
8199 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
8200 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
8201 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
8202 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
8203 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
8204 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
8205 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
8206 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
8207 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
8208 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
8209 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
8210 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
8211 case 0x10: strcpy(insn[i],"cop0"); type=NI;
8212 op2=(source[i]>>21)&0x1f;
8215 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
8216 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
8217 case 0x10: strcpy(insn[i],"tlb"); type=NI;
8218 switch(source[i]&0x3f)
8220 case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
8221 case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
8222 case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
8223 case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
8225 case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
8227 case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
8232 case 0x11: strcpy(insn[i],"cop1"); type=NI;
8233 op2=(source[i]>>21)&0x1f;
8236 case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
8237 case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
8238 case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
8239 case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
8240 case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
8241 case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
8242 case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
8243 switch((source[i]>>16)&0x3)
8245 case 0x00: strcpy(insn[i],"BC1F"); break;
8246 case 0x01: strcpy(insn[i],"BC1T"); break;
8247 case 0x02: strcpy(insn[i],"BC1FL"); break;
8248 case 0x03: strcpy(insn[i],"BC1TL"); break;
8251 case 0x10: strcpy(insn[i],"C1.S"); type=NI;
8252 switch(source[i]&0x3f)
8254 case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
8255 case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
8256 case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
8257 case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
8258 case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
8259 case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
8260 case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
8261 case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
8262 case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
8263 case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
8264 case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
8265 case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
8266 case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
8267 case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
8268 case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
8269 case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
8270 case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
8271 case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
8272 case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
8273 case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
8274 case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
8275 case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
8276 case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
8277 case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
8278 case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
8279 case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
8280 case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
8281 case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
8282 case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
8283 case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
8284 case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
8285 case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
8286 case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
8287 case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
8288 case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
8291 case 0x11: strcpy(insn[i],"C1.D"); type=NI;
8292 switch(source[i]&0x3f)
8294 case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
8295 case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
8296 case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
8297 case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
8298 case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
8299 case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
8300 case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
8301 case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
8302 case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
8303 case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
8304 case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
8305 case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
8306 case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
8307 case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
8308 case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
8309 case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
8310 case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
8311 case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
8312 case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
8313 case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
8314 case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
8315 case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
8316 case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
8317 case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
8318 case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
8319 case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
8320 case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
8321 case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
8322 case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
8323 case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
8324 case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8325 case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8326 case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8327 case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8328 case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8331 case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8332 switch(source[i]&0x3f)
8334 case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8335 case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8338 case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8339 switch(source[i]&0x3f)
8341 case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8342 case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8348 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8349 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8350 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8351 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8352 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8353 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8354 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8355 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
8357 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8358 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8359 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8360 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8361 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8362 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8363 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
8365 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
8367 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8368 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8369 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8370 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
8372 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8373 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
8375 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8376 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8377 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8378 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
8380 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8381 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8382 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
8384 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8385 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
8387 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8388 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8389 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
8392 case 0x12: strcpy(insn[i],"COP2"); type=NI;
8393 op2=(source[i]>>21)&0x1f;
8395 if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
8396 if (gte_handlers[source[i]&0x3f]!=NULL) {
8397 if (gte_regnames[source[i]&0x3f]!=NULL)
8398 strcpy(insn[i],gte_regnames[source[i]&0x3f]);
8400 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8406 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8407 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8408 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8409 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
8412 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8413 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8414 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8416 default: strcpy(insn[i],"???"); type=NI;
8417 printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
8422 /* Get registers/immediates */
8428 gte_rs[i]=gte_rt[i]=0;
8431 rs1[i]=(source[i]>>21)&0x1f;
8433 rt1[i]=(source[i]>>16)&0x1f;
8435 imm[i]=(short)source[i];
8439 rs1[i]=(source[i]>>21)&0x1f;
8440 rs2[i]=(source[i]>>16)&0x1f;
8443 imm[i]=(short)source[i];
8444 if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8447 // LWL/LWR only load part of the register,
8448 // therefore the target register must be treated as a source too
8449 rs1[i]=(source[i]>>21)&0x1f;
8450 rs2[i]=(source[i]>>16)&0x1f;
8451 rt1[i]=(source[i]>>16)&0x1f;
8453 imm[i]=(short)source[i];
8454 if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8455 if(op==0x26) dep1[i]=rt1[i]; // LWR
8458 if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8459 else rs1[i]=(source[i]>>21)&0x1f;
8461 rt1[i]=(source[i]>>16)&0x1f;
8463 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8464 imm[i]=(unsigned short)source[i];
8466 imm[i]=(short)source[i];
8468 if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8469 if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8470 if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8477 // The JAL instruction writes to r31.
8484 rs1[i]=(source[i]>>21)&0x1f;
8488 // The JALR instruction writes to rd.
8490 rt1[i]=(source[i]>>11)&0x1f;
8495 rs1[i]=(source[i]>>21)&0x1f;
8496 rs2[i]=(source[i]>>16)&0x1f;
8499 if(op&2) { // BGTZ/BLEZ
8507 rs1[i]=(source[i]>>21)&0x1f;
8512 if(op2&0x10) { // BxxAL
8514 // NOTE: If the branch is not taken, r31 is still overwritten
8516 likely[i]=(op2&2)>>1;
8523 likely[i]=((source[i])>>17)&1;
8526 rs1[i]=(source[i]>>21)&0x1f; // source
8527 rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8528 rt1[i]=(source[i]>>11)&0x1f; // destination
8530 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8531 us1[i]=rs1[i];us2[i]=rs2[i];
8533 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8534 dep1[i]=rs1[i];dep2[i]=rs2[i];
8536 else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8537 dep1[i]=rs1[i];dep2[i]=rs2[i];
8541 rs1[i]=(source[i]>>21)&0x1f; // source
8542 rs2[i]=(source[i]>>16)&0x1f; // divisor
8545 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8546 us1[i]=rs1[i];us2[i]=rs2[i];
8554 if(op2==0x10) rs1[i]=HIREG; // MFHI
8555 if(op2==0x11) rt1[i]=HIREG; // MTHI
8556 if(op2==0x12) rs1[i]=LOREG; // MFLO
8557 if(op2==0x13) rt1[i]=LOREG; // MTLO
8558 if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8559 if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8563 rs1[i]=(source[i]>>16)&0x1f; // target of shift
8564 rs2[i]=(source[i]>>21)&0x1f; // shift amount
8565 rt1[i]=(source[i]>>11)&0x1f; // destination
8567 // DSLLV/DSRLV/DSRAV are 64-bit
8568 if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8571 rs1[i]=(source[i]>>16)&0x1f;
8573 rt1[i]=(source[i]>>11)&0x1f;
8575 imm[i]=(source[i]>>6)&0x1f;
8576 // DSxx32 instructions
8577 if(op2>=0x3c) imm[i]|=0x20;
8578 // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8579 if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8586 if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8587 if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8588 if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8589 if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8596 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8597 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8598 if(op2==5) us1[i]=rs1[i]; // DMTC1
8606 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC2/CFC2
8607 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC2/CTC2
8609 int gr=(source[i]>>11)&0x1F;
8612 case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
8613 case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
8614 case 0x02: gte_rs[i]=1ll<<(gr+32); // CFC2
8615 if(gr==31&&!gte_reads_flags) {
8616 assem_debug("gte flag read encountered @%08x\n",addr + i*4);
8620 case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
8624 rs1[i]=(source[i]>>21)&0x1F;
8628 imm[i]=(short)source[i];
8631 rs1[i]=(source[i]>>21)&0x1F;
8635 imm[i]=(short)source[i];
8636 if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
8637 else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
8644 gte_rt[i]=1ll<<63; // every op changes flags
8645 // TODO: other regs?
8674 /* Calculate branch target addresses */
8676 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8677 else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8678 ba[i]=start+i*4+8; // Ignore never taken branch
8679 else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8680 ba[i]=start+i*4+8; // Ignore never taken branch
8681 else if(type==CJUMP||type==SJUMP||type==FJUMP)
8682 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8685 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
8687 // branch in delay slot?
8688 if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
8689 // don't handle first branch and call interpreter if it's hit
8690 printf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
8693 // basic load delay detection
8694 else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&rt1[i]!=0) {
8695 int t=(ba[i-1]-start)/4;
8696 if(0 <= t && t < i &&(rt1[i]==rs1[t]||rt1[i]==rs2[t])&&itype[t]!=CJUMP&&itype[t]!=SJUMP) {
8697 // jump target wants DS result - potential load delay effect
8698 printf("load delay @%08x (%08x)\n", addr + i*4, addr);
8700 bt[t+1]=1; // expected return from interpreter
8702 else if(i>=2&&rt1[i-2]==2&&rt1[i]==2&&rs1[i]!=2&&rs2[i]!=2&&rs1[i-1]!=2&&rs2[i-1]!=2&&
8703 !(i>=3&&(itype[i-3]==RJUMP||itype[i-3]==UJUMP||itype[i-3]==CJUMP||itype[i-3]==SJUMP))) {
8704 // v0 overwrite like this is a sign of trouble, bail out
8705 printf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
8711 rs2[i-1]=rt1[i-1]=rt2[i-1]=0;
8715 i--; // don't compile the DS
8719 /* Is this the end of the block? */
8720 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
8721 if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
8725 if(stop_after_jal) done=1;
8727 if((source[i+1]&0xfc00003f)==0x0d) done=1;
8729 // Don't recompile stuff that's already compiled
8730 if(check_addr(start+i*4+4)) done=1;
8731 // Don't get too close to the limit
8732 if(i>MAXBLOCK/2) done=1;
8734 if(itype[i]==SYSCALL&&stop_after_jal) done=1;
8735 if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
8737 // Does the block continue due to a branch?
8740 if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
8741 if(ba[j]==start+i*4+4) done=j=0;
8742 if(ba[j]==start+i*4+8) done=j=0;
8745 //assert(i<MAXBLOCK-1);
8746 if(start+i*4==pagelimit-4) done=1;
8747 assert(start+i*4<pagelimit);
8748 if (i==MAXBLOCK-1) done=1;
8749 // Stop if we're compiling junk
8750 if(itype[i]==NI&&opcode[i]==0x11) {
8751 done=stop_after_jal=1;
8752 printf("Disabled speculative precompilation\n");
8756 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8757 if(start+i*4==pagelimit) {
8763 /* Pass 2 - Register dependencies and branch targets */
8765 unneeded_registers(0,slen-1,0);
8767 /* Pass 3 - Register allocation */
8769 struct regstat current; // Current register allocations/status
8772 current.u=unneeded_reg[0];
8773 current.uu=unneeded_reg_upper[0];
8774 clear_all_regs(current.regmap);
8775 alloc_reg(¤t,0,CCREG);
8776 dirty_reg(¤t,CCREG);
8784 provisional_32bit();
8787 // First instruction is delay slot
8792 unneeded_reg_upper[0]=1;
8793 current.regmap[HOST_BTREG]=BTREG;
8801 for(hr=0;hr<HOST_REGS;hr++)
8803 // Is this really necessary?
8804 if(current.regmap[hr]==0) current.regmap[hr]=-1;
8810 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8812 if(rs1[i-2]==0||rs2[i-2]==0)
8815 current.is32|=1LL<<rs1[i-2];
8816 int hr=get_reg(current.regmap,rs1[i-2]|64);
8817 if(hr>=0) current.regmap[hr]=-1;
8820 current.is32|=1LL<<rs2[i-2];
8821 int hr=get_reg(current.regmap,rs2[i-2]|64);
8822 if(hr>=0) current.regmap[hr]=-1;
8828 // If something jumps here with 64-bit values
8829 // then promote those registers to 64 bits
8832 uint64_t temp_is32=current.is32;
8835 if(ba[j]==start+i*4)
8836 temp_is32&=branch_regs[j].is32;
8840 if(ba[j]==start+i*4)
8844 if(temp_is32!=current.is32) {
8845 //printf("dumping 32-bit regs (%x)\n",start+i*4);
8846 #ifndef DESTRUCTIVE_WRITEBACK
8849 for(hr=0;hr<HOST_REGS;hr++)
8851 int r=current.regmap[hr];
8854 if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8856 //printf("restore %d\n",r);
8860 current.is32=temp_is32;
8867 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8868 regs[i].wasconst=current.isconst;
8869 regs[i].was32=current.is32;
8870 regs[i].wasdirty=current.dirty;
8871 #if defined(DESTRUCTIVE_WRITEBACK) && !defined(FORCE32)
8872 // To change a dirty register from 32 to 64 bits, we must write
8873 // it out during the previous cycle (for branches, 2 cycles)
8874 if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8876 uint64_t temp_is32=current.is32;
8879 if(ba[j]==start+i*4+4)
8880 temp_is32&=branch_regs[j].is32;
8884 if(ba[j]==start+i*4+4)
8888 if(temp_is32!=current.is32) {
8889 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8890 for(hr=0;hr<HOST_REGS;hr++)
8892 int r=current.regmap[hr];
8895 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8896 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
8898 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
8900 //printf("dump %d/r%d\n",hr,r);
8901 current.regmap[hr]=-1;
8902 if(get_reg(current.regmap,r|64)>=0)
8903 current.regmap[get_reg(current.regmap,r|64)]=-1;
8911 else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
8913 uint64_t temp_is32=current.is32;
8916 if(ba[j]==start+i*4+8)
8917 temp_is32&=branch_regs[j].is32;
8921 if(ba[j]==start+i*4+8)
8925 if(temp_is32!=current.is32) {
8926 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8927 for(hr=0;hr<HOST_REGS;hr++)
8929 int r=current.regmap[hr];
8932 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8933 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
8935 //printf("dump %d/r%d\n",hr,r);
8936 current.regmap[hr]=-1;
8937 if(get_reg(current.regmap,r|64)>=0)
8938 current.regmap[get_reg(current.regmap,r|64)]=-1;
8946 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8948 current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8949 current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8950 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8959 current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
8960 current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8961 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8962 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8963 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8966 } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
8970 ds=0; // Skip delay slot, already allocated as part of branch
8971 // ...but we need to alloc it in case something jumps here
8973 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
8974 current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
8976 current.u=branch_unneeded_reg[i-1];
8977 current.uu=branch_unneeded_reg_upper[i-1];
8979 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8980 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8981 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8984 struct regstat temp;
8985 memcpy(&temp,¤t,sizeof(current));
8986 temp.wasdirty=temp.dirty;
8987 temp.was32=temp.is32;
8988 // TODO: Take into account unconditional branches, as below
8989 delayslot_alloc(&temp,i);
8990 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
8991 regs[i].wasdirty=temp.wasdirty;
8992 regs[i].was32=temp.was32;
8993 regs[i].dirty=temp.dirty;
8994 regs[i].is32=temp.is32;
8998 // Create entry (branch target) regmap
8999 for(hr=0;hr<HOST_REGS;hr++)
9001 int r=temp.regmap[hr];
9003 if(r!=regmap_pre[i][hr]) {
9004 regs[i].regmap_entry[hr]=-1;
9009 if((current.u>>r)&1) {
9010 regs[i].regmap_entry[hr]=-1;
9011 regs[i].regmap[hr]=-1;
9012 //Don't clear regs in the delay slot as the branch might need them
9013 //current.regmap[hr]=-1;
9015 regs[i].regmap_entry[hr]=r;
9018 if((current.uu>>(r&63))&1) {
9019 regs[i].regmap_entry[hr]=-1;
9020 regs[i].regmap[hr]=-1;
9021 //Don't clear regs in the delay slot as the branch might need them
9022 //current.regmap[hr]=-1;
9024 regs[i].regmap_entry[hr]=r;
9028 // First instruction expects CCREG to be allocated
9029 if(i==0&&hr==HOST_CCREG)
9030 regs[i].regmap_entry[hr]=CCREG;
9032 regs[i].regmap_entry[hr]=-1;
9036 else { // Not delay slot
9039 //current.isconst=0; // DEBUG
9040 //current.wasconst=0; // DEBUG
9041 //regs[i].wasconst=0; // DEBUG
9042 clear_const(¤t,rt1[i]);
9043 alloc_cc(¤t,i);
9044 dirty_reg(¤t,CCREG);
9046 alloc_reg(¤t,i,31);
9047 dirty_reg(¤t,31);
9048 //assert(rs1[i+1]!=31&&rs2[i+1]!=31);
9049 //assert(rt1[i+1]!=rt1[i]);
9051 alloc_reg(¤t,i,PTEMP);
9053 //current.is32|=1LL<<rt1[i];
9056 delayslot_alloc(¤t,i+1);
9057 //current.isconst=0; // DEBUG
9059 //printf("i=%d, isconst=%x\n",i,current.isconst);
9062 //current.isconst=0;
9063 //current.wasconst=0;
9064 //regs[i].wasconst=0;
9065 clear_const(¤t,rs1[i]);
9066 clear_const(¤t,rt1[i]);
9067 alloc_cc(¤t,i);
9068 dirty_reg(¤t,CCREG);
9069 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
9070 alloc_reg(¤t,i,rs1[i]);
9072 alloc_reg(¤t,i,rt1[i]);
9073 dirty_reg(¤t,rt1[i]);
9074 assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
9075 assert(rt1[i+1]!=rt1[i]);
9077 alloc_reg(¤t,i,PTEMP);
9081 if(rs1[i]==31) { // JALR
9082 alloc_reg(¤t,i,RHASH);
9083 #ifndef HOST_IMM_ADDR32
9084 alloc_reg(¤t,i,RHTBL);
9088 delayslot_alloc(¤t,i+1);
9090 // The delay slot overwrites our source register,
9091 // allocate a temporary register to hold the old value.
9095 delayslot_alloc(¤t,i+1);
9097 alloc_reg(¤t,i,RTEMP);
9099 //current.isconst=0; // DEBUG
9104 //current.isconst=0;
9105 //current.wasconst=0;
9106 //regs[i].wasconst=0;
9107 clear_const(¤t,rs1[i]);
9108 clear_const(¤t,rs2[i]);
9109 if((opcode[i]&0x3E)==4) // BEQ/BNE
9111 alloc_cc(¤t,i);
9112 dirty_reg(¤t,CCREG);
9113 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9114 if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
9115 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9117 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9118 if(rs2[i]) alloc_reg64(¤t,i,rs2[i]);
9120 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
9121 (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
9122 // The delay slot overwrites one of our conditions.
9123 // Allocate the branch condition registers instead.
9127 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9128 if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
9129 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9131 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9132 if(rs2[i]) alloc_reg64(¤t,i,rs2[i]);
9138 delayslot_alloc(¤t,i+1);
9142 if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
9144 alloc_cc(¤t,i);
9145 dirty_reg(¤t,CCREG);
9146 alloc_reg(¤t,i,rs1[i]);
9147 if(!(current.is32>>rs1[i]&1))
9149 alloc_reg64(¤t,i,rs1[i]);
9151 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
9152 // The delay slot overwrites one of our conditions.
9153 // Allocate the branch condition registers instead.
9157 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9158 if(!((current.is32>>rs1[i])&1))
9160 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9166 delayslot_alloc(¤t,i+1);
9170 // Don't alloc the delay slot yet because we might not execute it
9171 if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
9176 alloc_cc(¤t,i);
9177 dirty_reg(¤t,CCREG);
9178 alloc_reg(¤t,i,rs1[i]);
9179 alloc_reg(¤t,i,rs2[i]);
9180 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9182 alloc_reg64(¤t,i,rs1[i]);
9183 alloc_reg64(¤t,i,rs2[i]);
9187 if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
9192 alloc_cc(¤t,i);
9193 dirty_reg(¤t,CCREG);
9194 alloc_reg(¤t,i,rs1[i]);
9195 if(!(current.is32>>rs1[i]&1))
9197 alloc_reg64(¤t,i,rs1[i]);
9201 //current.isconst=0;
9204 //current.isconst=0;
9205 //current.wasconst=0;
9206 //regs[i].wasconst=0;
9207 clear_const(¤t,rs1[i]);
9208 clear_const(¤t,rt1[i]);
9209 //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
9210 if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
9212 alloc_cc(¤t,i);
9213 dirty_reg(¤t,CCREG);
9214 alloc_reg(¤t,i,rs1[i]);
9215 if(!(current.is32>>rs1[i]&1))
9217 alloc_reg64(¤t,i,rs1[i]);
9219 if (rt1[i]==31) { // BLTZAL/BGEZAL
9220 alloc_reg(¤t,i,31);
9221 dirty_reg(¤t,31);
9222 //#ifdef REG_PREFETCH
9223 //alloc_reg(¤t,i,PTEMP);
9225 //current.is32|=1LL<<rt1[i];
9227 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) // The delay slot overwrites the branch condition.
9228 ||(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))) { // DS touches $ra
9229 // Allocate the branch condition registers instead.
9233 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9234 if(!((current.is32>>rs1[i])&1))
9236 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9242 delayslot_alloc(¤t,i+1);
9246 // Don't alloc the delay slot yet because we might not execute it
9247 if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
9252 alloc_cc(¤t,i);
9253 dirty_reg(¤t,CCREG);
9254 alloc_reg(¤t,i,rs1[i]);
9255 if(!(current.is32>>rs1[i]&1))
9257 alloc_reg64(¤t,i,rs1[i]);
9261 //current.isconst=0;
9267 if(likely[i]==0) // BC1F/BC1T
9269 // TODO: Theoretically we can run out of registers here on x86.
9270 // The delay slot can allocate up to six, and we need to check
9271 // CSREG before executing the delay slot. Possibly we can drop
9272 // the cycle count and then reload it after checking that the
9273 // FPU is in a usable state, or don't do out-of-order execution.
9274 alloc_cc(¤t,i);
9275 dirty_reg(¤t,CCREG);
9276 alloc_reg(¤t,i,FSREG);
9277 alloc_reg(¤t,i,CSREG);
9278 if(itype[i+1]==FCOMP) {
9279 // The delay slot overwrites the branch condition.
9280 // Allocate the branch condition registers instead.
9281 alloc_cc(¤t,i);
9282 dirty_reg(¤t,CCREG);
9283 alloc_reg(¤t,i,CSREG);
9284 alloc_reg(¤t,i,FSREG);
9288 delayslot_alloc(¤t,i+1);
9289 alloc_reg(¤t,i+1,CSREG);
9293 // Don't alloc the delay slot yet because we might not execute it
9294 if(likely[i]) // BC1FL/BC1TL
9296 alloc_cc(¤t,i);
9297 dirty_reg(¤t,CCREG);
9298 alloc_reg(¤t,i,CSREG);
9299 alloc_reg(¤t,i,FSREG);
9305 imm16_alloc(¤t,i);
9309 load_alloc(¤t,i);
9313 store_alloc(¤t,i);
9316 alu_alloc(¤t,i);
9319 shift_alloc(¤t,i);
9322 multdiv_alloc(¤t,i);
9325 shiftimm_alloc(¤t,i);
9328 mov_alloc(¤t,i);
9331 cop0_alloc(¤t,i);
9335 cop1_alloc(¤t,i);
9338 c1ls_alloc(¤t,i);
9341 c2ls_alloc(¤t,i);
9344 c2op_alloc(¤t,i);
9347 fconv_alloc(¤t,i);
9350 float_alloc(¤t,i);
9353 fcomp_alloc(¤t,i);
9358 syscall_alloc(¤t,i);
9361 pagespan_alloc(¤t,i);
9365 // Drop the upper half of registers that have become 32-bit
9366 current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
9367 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9368 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9369 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9372 current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
9373 current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9374 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9375 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9379 // Create entry (branch target) regmap
9380 for(hr=0;hr<HOST_REGS;hr++)
9383 r=current.regmap[hr];
9385 if(r!=regmap_pre[i][hr]) {
9386 // TODO: delay slot (?)
9387 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9388 if(or<0||(r&63)>=TEMPREG){
9389 regs[i].regmap_entry[hr]=-1;
9393 // Just move it to a different register
9394 regs[i].regmap_entry[hr]=r;
9395 // If it was dirty before, it's still dirty
9396 if((regs[i].wasdirty>>or)&1) dirty_reg(¤t,r&63);
9403 regs[i].regmap_entry[hr]=0;
9407 if((current.u>>r)&1) {
9408 regs[i].regmap_entry[hr]=-1;
9409 //regs[i].regmap[hr]=-1;
9410 current.regmap[hr]=-1;
9412 regs[i].regmap_entry[hr]=r;
9415 if((current.uu>>(r&63))&1) {
9416 regs[i].regmap_entry[hr]=-1;
9417 //regs[i].regmap[hr]=-1;
9418 current.regmap[hr]=-1;
9420 regs[i].regmap_entry[hr]=r;
9424 // Branches expect CCREG to be allocated at the target
9425 if(regmap_pre[i][hr]==CCREG)
9426 regs[i].regmap_entry[hr]=CCREG;
9428 regs[i].regmap_entry[hr]=-1;
9431 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9433 /* Branch post-alloc */
9436 current.was32=current.is32;
9437 current.wasdirty=current.dirty;
9438 switch(itype[i-1]) {
9440 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9441 branch_regs[i-1].isconst=0;
9442 branch_regs[i-1].wasconst=0;
9443 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9444 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9445 alloc_cc(&branch_regs[i-1],i-1);
9446 dirty_reg(&branch_regs[i-1],CCREG);
9447 if(rt1[i-1]==31) { // JAL
9448 alloc_reg(&branch_regs[i-1],i-1,31);
9449 dirty_reg(&branch_regs[i-1],31);
9450 branch_regs[i-1].is32|=1LL<<31;
9452 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9453 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9456 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9457 branch_regs[i-1].isconst=0;
9458 branch_regs[i-1].wasconst=0;
9459 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9460 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9461 alloc_cc(&branch_regs[i-1],i-1);
9462 dirty_reg(&branch_regs[i-1],CCREG);
9463 alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
9464 if(rt1[i-1]!=0) { // JALR
9465 alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9466 dirty_reg(&branch_regs[i-1],rt1[i-1]);
9467 branch_regs[i-1].is32|=1LL<<rt1[i-1];
9470 if(rs1[i-1]==31) { // JALR
9471 alloc_reg(&branch_regs[i-1],i-1,RHASH);
9472 #ifndef HOST_IMM_ADDR32
9473 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9477 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9478 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9481 if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9483 alloc_cc(¤t,i-1);
9484 dirty_reg(¤t,CCREG);
9485 if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9486 (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9487 // The delay slot overwrote one of our conditions
9488 // Delay slot goes after the test (in order)
9489 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9490 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9491 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9494 delayslot_alloc(¤t,i);
9499 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9500 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9501 // Alloc the branch condition registers
9502 if(rs1[i-1]) alloc_reg(¤t,i-1,rs1[i-1]);
9503 if(rs2[i-1]) alloc_reg(¤t,i-1,rs2[i-1]);
9504 if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9506 if(rs1[i-1]) alloc_reg64(¤t,i-1,rs1[i-1]);
9507 if(rs2[i-1]) alloc_reg64(¤t,i-1,rs2[i-1]);
9510 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9511 branch_regs[i-1].isconst=0;
9512 branch_regs[i-1].wasconst=0;
9513 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9514 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9517 if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9519 alloc_cc(¤t,i-1);
9520 dirty_reg(¤t,CCREG);
9521 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9522 // The delay slot overwrote the branch condition
9523 // Delay slot goes after the test (in order)
9524 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9525 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9526 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9529 delayslot_alloc(¤t,i);
9534 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9535 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9536 // Alloc the branch condition register
9537 alloc_reg(¤t,i-1,rs1[i-1]);
9538 if(!(current.is32>>rs1[i-1]&1))
9540 alloc_reg64(¤t,i-1,rs1[i-1]);
9543 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9544 branch_regs[i-1].isconst=0;
9545 branch_regs[i-1].wasconst=0;
9546 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9547 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9550 // Alloc the delay slot in case the branch is taken
9551 if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9553 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9554 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9555 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9556 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9557 alloc_cc(&branch_regs[i-1],i);
9558 dirty_reg(&branch_regs[i-1],CCREG);
9559 delayslot_alloc(&branch_regs[i-1],i);
9560 branch_regs[i-1].isconst=0;
9561 alloc_reg(¤t,i,CCREG); // Not taken path
9562 dirty_reg(¤t,CCREG);
9563 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9566 if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9568 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9569 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9570 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9571 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9572 alloc_cc(&branch_regs[i-1],i);
9573 dirty_reg(&branch_regs[i-1],CCREG);
9574 delayslot_alloc(&branch_regs[i-1],i);
9575 branch_regs[i-1].isconst=0;
9576 alloc_reg(¤t,i,CCREG); // Not taken path
9577 dirty_reg(¤t,CCREG);
9578 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9582 //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9583 if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9585 alloc_cc(¤t,i-1);
9586 dirty_reg(¤t,CCREG);
9587 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9588 // The delay slot overwrote the branch condition
9589 // Delay slot goes after the test (in order)
9590 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9591 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9592 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9595 delayslot_alloc(¤t,i);
9600 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9601 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9602 // Alloc the branch condition register
9603 alloc_reg(¤t,i-1,rs1[i-1]);
9604 if(!(current.is32>>rs1[i-1]&1))
9606 alloc_reg64(¤t,i-1,rs1[i-1]);
9609 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9610 branch_regs[i-1].isconst=0;
9611 branch_regs[i-1].wasconst=0;
9612 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9613 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9616 // Alloc the delay slot in case the branch is taken
9617 if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9619 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9620 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9621 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9622 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9623 alloc_cc(&branch_regs[i-1],i);
9624 dirty_reg(&branch_regs[i-1],CCREG);
9625 delayslot_alloc(&branch_regs[i-1],i);
9626 branch_regs[i-1].isconst=0;
9627 alloc_reg(¤t,i,CCREG); // Not taken path
9628 dirty_reg(¤t,CCREG);
9629 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9631 // FIXME: BLTZAL/BGEZAL
9632 if(opcode2[i-1]&0x10) { // BxxZAL
9633 alloc_reg(&branch_regs[i-1],i-1,31);
9634 dirty_reg(&branch_regs[i-1],31);
9635 branch_regs[i-1].is32|=1LL<<31;
9639 if(likely[i-1]==0) // BC1F/BC1T
9641 alloc_cc(¤t,i-1);
9642 dirty_reg(¤t,CCREG);
9643 if(itype[i]==FCOMP) {
9644 // The delay slot overwrote the branch condition
9645 // Delay slot goes after the test (in order)
9646 delayslot_alloc(¤t,i);
9651 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9652 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9653 // Alloc the branch condition register
9654 alloc_reg(¤t,i-1,FSREG);
9656 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9657 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9661 // Alloc the delay slot in case the branch is taken
9662 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9663 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9664 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9665 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9666 alloc_cc(&branch_regs[i-1],i);
9667 dirty_reg(&branch_regs[i-1],CCREG);
9668 delayslot_alloc(&branch_regs[i-1],i);
9669 branch_regs[i-1].isconst=0;
9670 alloc_reg(¤t,i,CCREG); // Not taken path
9671 dirty_reg(¤t,CCREG);
9672 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9677 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9679 if(rt1[i-1]==31) // JAL/JALR
9681 // Subroutine call will return here, don't alloc any registers
9684 clear_all_regs(current.regmap);
9685 alloc_reg(¤t,i,CCREG);
9686 dirty_reg(¤t,CCREG);
9690 // Internal branch will jump here, match registers to caller
9691 current.is32=0x3FFFFFFFFLL;
9693 clear_all_regs(current.regmap);
9694 alloc_reg(¤t,i,CCREG);
9695 dirty_reg(¤t,CCREG);
9698 if(ba[j]==start+i*4+4) {
9699 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9700 current.is32=branch_regs[j].is32;
9701 current.dirty=branch_regs[j].dirty;
9706 if(ba[j]==start+i*4+4) {
9707 for(hr=0;hr<HOST_REGS;hr++) {
9708 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9709 current.regmap[hr]=-1;
9711 current.is32&=branch_regs[j].is32;
9712 current.dirty&=branch_regs[j].dirty;
9721 // Count cycles in between branches
9723 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
9728 else if(/*itype[i]==LOAD||*/itype[i]==STORE||itype[i]==C1LS) // load causes weird timing issues
9730 cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
9732 else if(itype[i]==C2LS)
9742 flush_dirty_uppers(¤t);
9744 regs[i].is32=current.is32;
9745 regs[i].dirty=current.dirty;
9746 regs[i].isconst=current.isconst;
9747 memcpy(constmap[i],current.constmap,sizeof(current.constmap));
9749 for(hr=0;hr<HOST_REGS;hr++) {
9750 if(hr!=EXCLUDE_REG&®s[i].regmap[hr]>=0) {
9751 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9752 regs[i].wasconst&=~(1<<hr);
9756 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9759 /* Pass 4 - Cull unused host registers */
9763 for (i=slen-1;i>=0;i--)
9766 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9768 if(ba[i]<start || ba[i]>=(start+slen*4))
9770 // Branch out of this block, don't need anything
9776 // Need whatever matches the target
9778 int t=(ba[i]-start)>>2;
9779 for(hr=0;hr<HOST_REGS;hr++)
9781 if(regs[i].regmap_entry[hr]>=0) {
9782 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9786 // Conditional branch may need registers for following instructions
9787 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9790 nr|=needed_reg[i+2];
9791 for(hr=0;hr<HOST_REGS;hr++)
9793 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9794 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9798 // Don't need stuff which is overwritten
9799 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9800 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9801 // Merge in delay slot
9802 for(hr=0;hr<HOST_REGS;hr++)
9805 // These are overwritten unless the branch is "likely"
9806 // and the delay slot is nullified if not taken
9807 if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9808 if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9810 if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9811 if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9812 if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9813 if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9814 if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9815 if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9816 if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9817 if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9818 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9819 if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9820 if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9822 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9823 if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9824 if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9826 if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
9827 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9828 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9832 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
9834 // SYSCALL instruction (software interrupt)
9837 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9839 // ERET instruction (return from interrupt)
9845 for(hr=0;hr<HOST_REGS;hr++) {
9846 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9847 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9848 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9849 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9853 for(hr=0;hr<HOST_REGS;hr++)
9855 // Overwritten registers are not needed
9856 if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9857 if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9858 if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9859 // Source registers are needed
9860 if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9861 if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9862 if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9863 if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9864 if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9865 if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9866 if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9867 if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9868 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9869 if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9870 if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9872 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
9873 if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9874 if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9876 if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
9877 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9878 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9880 // Don't store a register immediately after writing it,
9881 // may prevent dual-issue.
9882 // But do so if this is a branch target, otherwise we
9883 // might have to load the register before the branch.
9884 if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
9885 if((regmap_pre[i][hr]>0&®map_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
9886 (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
9887 if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9888 if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9890 if((regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
9891 (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
9892 if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9893 if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9897 // Cycle count is needed at branches. Assume it is needed at the target too.
9898 if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
9899 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9900 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9905 // Deallocate unneeded registers
9906 for(hr=0;hr<HOST_REGS;hr++)
9909 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
9910 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9911 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9912 (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
9914 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9917 regs[i].regmap[hr]=-1;
9918 regs[i].isconst&=~(1<<hr);
9920 regmap_pre[i+2][hr]=-1;
9921 regs[i+2].wasconst&=~(1<<hr);
9926 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9928 int d1=0,d2=0,map=0,temp=0;
9929 if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
9935 if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
9936 itype[i+1]==STORE || itype[i+1]==STORELR ||
9937 itype[i+1]==C1LS || itype[i+1]==C2LS)
9940 if(itype[i+1]==STORE || itype[i+1]==STORELR ||
9941 (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
9944 if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
9945 itype[i+1]==C1LS || itype[i+1]==C2LS)
9947 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9948 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9949 (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
9950 (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
9951 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9952 regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
9953 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
9954 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
9955 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
9956 regs[i].regmap[hr]!=map )
9958 regs[i].regmap[hr]=-1;
9959 regs[i].isconst&=~(1<<hr);
9960 if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
9961 (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
9962 (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
9963 (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
9964 (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
9965 branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
9966 (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
9967 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
9968 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
9969 branch_regs[i].regmap[hr]!=map)
9971 branch_regs[i].regmap[hr]=-1;
9972 branch_regs[i].regmap_entry[hr]=-1;
9973 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9975 if(!likely[i]&&i<slen-2) {
9976 regmap_pre[i+2][hr]=-1;
9977 regs[i+2].wasconst&=~(1<<hr);
9988 int d1=0,d2=0,map=-1,temp=-1;
9989 if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
9995 if(itype[i]==LOAD || itype[i]==LOADLR ||
9996 itype[i]==STORE || itype[i]==STORELR ||
9997 itype[i]==C1LS || itype[i]==C2LS)
9999 } else if(itype[i]==STORE || itype[i]==STORELR ||
10000 (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
10003 if(itype[i]==LOADLR || itype[i]==STORELR ||
10004 itype[i]==C1LS || itype[i]==C2LS)
10006 if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
10007 (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
10008 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
10009 regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
10010 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
10011 (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
10013 if(i<slen-1&&!is_ds[i]) {
10014 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
10015 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
10016 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
10018 printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
10019 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
10021 regmap_pre[i+1][hr]=-1;
10022 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
10023 regs[i+1].wasconst&=~(1<<hr);
10025 regs[i].regmap[hr]=-1;
10026 regs[i].isconst&=~(1<<hr);
10034 /* Pass 5 - Pre-allocate registers */
10036 // If a register is allocated during a loop, try to allocate it for the
10037 // entire loop, if possible. This avoids loading/storing registers
10038 // inside of the loop.
10040 signed char f_regmap[HOST_REGS];
10041 clear_all_regs(f_regmap);
10042 for(i=0;i<slen-1;i++)
10044 if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10046 if(ba[i]>=start && ba[i]<(start+i*4))
10047 if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
10048 ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
10049 ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
10050 ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
10051 ||itype[i+1]==FCOMP||itype[i+1]==FCONV
10052 ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
10054 int t=(ba[i]-start)>>2;
10055 if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
10056 if(t<2||(itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||rt1[t-2]!=31) // call/ret assumes no registers allocated
10057 for(hr=0;hr<HOST_REGS;hr++)
10059 if(regs[i].regmap[hr]>64) {
10060 if(!((regs[i].dirty>>hr)&1))
10061 f_regmap[hr]=regs[i].regmap[hr];
10062 else f_regmap[hr]=-1;
10064 else if(regs[i].regmap[hr]>=0) {
10065 if(f_regmap[hr]!=regs[i].regmap[hr]) {
10066 // dealloc old register
10068 for(n=0;n<HOST_REGS;n++)
10070 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10072 // and alloc new one
10073 f_regmap[hr]=regs[i].regmap[hr];
10076 if(branch_regs[i].regmap[hr]>64) {
10077 if(!((branch_regs[i].dirty>>hr)&1))
10078 f_regmap[hr]=branch_regs[i].regmap[hr];
10079 else f_regmap[hr]=-1;
10081 else if(branch_regs[i].regmap[hr]>=0) {
10082 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
10083 // dealloc old register
10085 for(n=0;n<HOST_REGS;n++)
10087 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
10089 // and alloc new one
10090 f_regmap[hr]=branch_regs[i].regmap[hr];
10094 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
10095 f_regmap[hr]=branch_regs[i].regmap[hr];
10097 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
10098 f_regmap[hr]=branch_regs[i].regmap[hr];
10100 // Avoid dirty->clean transition
10101 #ifdef DESTRUCTIVE_WRITEBACK
10102 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
10104 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
10105 // case above, however it's always a good idea. We can't hoist the
10106 // load if the register was already allocated, so there's no point
10107 // wasting time analyzing most of these cases. It only "succeeds"
10108 // when the mapping was different and the load can be replaced with
10109 // a mov, which is of negligible benefit. So such cases are
10111 if(f_regmap[hr]>0) {
10112 if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
10113 int r=f_regmap[hr];
10116 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10117 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
10118 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
10120 // NB This can exclude the case where the upper-half
10121 // register is lower numbered than the lower-half
10122 // register. Not sure if it's worth fixing...
10123 if(get_reg(regs[j].regmap,r&63)<0) break;
10124 if(get_reg(regs[j].regmap_entry,r&63)<0) break;
10125 if(regs[j].is32&(1LL<<(r&63))) break;
10127 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
10128 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10130 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
10131 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
10133 if(get_reg(regs[i].regmap,r&63)<0) break;
10134 if(get_reg(branch_regs[i].regmap,r&63)<0) break;
10137 while(k>1&®s[k-1].regmap[hr]==-1) {
10138 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10139 //printf("no free regs for store %x\n",start+(k-1)*4);
10142 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
10143 //printf("no-match due to different register\n");
10146 if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
10147 //printf("no-match due to branch\n");
10150 // call/ret fast path assumes no registers allocated
10151 if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)&&rt1[k-3]==31) {
10155 // NB This can exclude the case where the upper-half
10156 // register is lower numbered than the lower-half
10157 // register. Not sure if it's worth fixing...
10158 if(get_reg(regs[k-1].regmap,r&63)<0) break;
10159 if(regs[k-1].is32&(1LL<<(r&63))) break;
10164 if((regs[k].is32&(1LL<<f_regmap[hr]))!=
10165 (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
10166 //printf("bad match after branch\n");
10170 if(regs[k-1].regmap[hr]==f_regmap[hr]&®map_pre[k][hr]==f_regmap[hr]) {
10171 //printf("Extend r%d, %x ->\n",hr,start+k*4);
10173 regs[k].regmap_entry[hr]=f_regmap[hr];
10174 regs[k].regmap[hr]=f_regmap[hr];
10175 regmap_pre[k+1][hr]=f_regmap[hr];
10176 regs[k].wasdirty&=~(1<<hr);
10177 regs[k].dirty&=~(1<<hr);
10178 regs[k].wasdirty|=(1<<hr)®s[k-1].dirty;
10179 regs[k].dirty|=(1<<hr)®s[k].wasdirty;
10180 regs[k].wasconst&=~(1<<hr);
10181 regs[k].isconst&=~(1<<hr);
10186 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
10189 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
10190 if(regs[i-1].regmap[hr]==f_regmap[hr]&®map_pre[i][hr]==f_regmap[hr]) {
10191 //printf("OK fill %x (r%d)\n",start+i*4,hr);
10192 regs[i].regmap_entry[hr]=f_regmap[hr];
10193 regs[i].regmap[hr]=f_regmap[hr];
10194 regs[i].wasdirty&=~(1<<hr);
10195 regs[i].dirty&=~(1<<hr);
10196 regs[i].wasdirty|=(1<<hr)®s[i-1].dirty;
10197 regs[i].dirty|=(1<<hr)®s[i-1].dirty;
10198 regs[i].wasconst&=~(1<<hr);
10199 regs[i].isconst&=~(1<<hr);
10200 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
10201 branch_regs[i].wasdirty&=~(1<<hr);
10202 branch_regs[i].wasdirty|=(1<<hr)®s[i].dirty;
10203 branch_regs[i].regmap[hr]=f_regmap[hr];
10204 branch_regs[i].dirty&=~(1<<hr);
10205 branch_regs[i].dirty|=(1<<hr)®s[i].dirty;
10206 branch_regs[i].wasconst&=~(1<<hr);
10207 branch_regs[i].isconst&=~(1<<hr);
10208 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
10209 regmap_pre[i+2][hr]=f_regmap[hr];
10210 regs[i+2].wasdirty&=~(1<<hr);
10211 regs[i+2].wasdirty|=(1<<hr)®s[i].dirty;
10212 assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
10213 (regs[i+2].was32&(1LL<<f_regmap[hr])));
10218 // Alloc register clean at beginning of loop,
10219 // but may dirty it in pass 6
10220 regs[k].regmap_entry[hr]=f_regmap[hr];
10221 regs[k].regmap[hr]=f_regmap[hr];
10222 regs[k].dirty&=~(1<<hr);
10223 regs[k].wasconst&=~(1<<hr);
10224 regs[k].isconst&=~(1<<hr);
10225 if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) {
10226 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
10227 branch_regs[k].regmap[hr]=f_regmap[hr];
10228 branch_regs[k].dirty&=~(1<<hr);
10229 branch_regs[k].wasconst&=~(1<<hr);
10230 branch_regs[k].isconst&=~(1<<hr);
10231 if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
10232 regmap_pre[k+2][hr]=f_regmap[hr];
10233 regs[k+2].wasdirty&=~(1<<hr);
10234 assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))==
10235 (regs[k+2].was32&(1LL<<f_regmap[hr])));
10240 regmap_pre[k+1][hr]=f_regmap[hr];
10241 regs[k+1].wasdirty&=~(1<<hr);
10244 if(regs[j].regmap[hr]==f_regmap[hr])
10245 regs[j].regmap_entry[hr]=f_regmap[hr];
10249 if(regs[j].regmap[hr]>=0)
10251 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
10252 //printf("no-match due to different register\n");
10255 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
10256 //printf("32/64 mismatch %x %d\n",start+j*4,hr);
10259 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10261 // Stop on unconditional branch
10264 if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
10267 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
10270 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
10273 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
10274 //printf("no-match due to different register (branch)\n");
10278 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10279 //printf("No free regs for store %x\n",start+j*4);
10282 if(f_regmap[hr]>=64) {
10283 if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
10288 if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
10299 // Non branch or undetermined branch target
10300 for(hr=0;hr<HOST_REGS;hr++)
10302 if(hr!=EXCLUDE_REG) {
10303 if(regs[i].regmap[hr]>64) {
10304 if(!((regs[i].dirty>>hr)&1))
10305 f_regmap[hr]=regs[i].regmap[hr];
10307 else if(regs[i].regmap[hr]>=0) {
10308 if(f_regmap[hr]!=regs[i].regmap[hr]) {
10309 // dealloc old register
10311 for(n=0;n<HOST_REGS;n++)
10313 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10315 // and alloc new one
10316 f_regmap[hr]=regs[i].regmap[hr];
10321 // Try to restore cycle count at branch targets
10323 for(j=i;j<slen-1;j++) {
10324 if(regs[j].regmap[HOST_CCREG]!=-1) break;
10325 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10326 //printf("no free regs for store %x\n",start+j*4);
10330 if(regs[j].regmap[HOST_CCREG]==CCREG) {
10332 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
10334 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10335 regs[k].regmap[HOST_CCREG]=CCREG;
10336 regmap_pre[k+1][HOST_CCREG]=CCREG;
10337 regs[k+1].wasdirty|=1<<HOST_CCREG;
10338 regs[k].dirty|=1<<HOST_CCREG;
10339 regs[k].wasconst&=~(1<<HOST_CCREG);
10340 regs[k].isconst&=~(1<<HOST_CCREG);
10343 regs[j].regmap_entry[HOST_CCREG]=CCREG;
10345 // Work backwards from the branch target
10346 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
10348 //printf("Extend backwards\n");
10351 while(regs[k-1].regmap[HOST_CCREG]==-1) {
10352 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10353 //printf("no free regs for store %x\n",start+(k-1)*4);
10358 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
10359 //printf("Extend CC, %x ->\n",start+k*4);
10361 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10362 regs[k].regmap[HOST_CCREG]=CCREG;
10363 regmap_pre[k+1][HOST_CCREG]=CCREG;
10364 regs[k+1].wasdirty|=1<<HOST_CCREG;
10365 regs[k].dirty|=1<<HOST_CCREG;
10366 regs[k].wasconst&=~(1<<HOST_CCREG);
10367 regs[k].isconst&=~(1<<HOST_CCREG);
10372 //printf("Fail Extend CC, %x ->\n",start+k*4);
10376 if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
10377 itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
10378 itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
10379 itype[i]!=FCONV&&itype[i]!=FCOMP)
10381 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
10386 // Cache memory offset or tlb map pointer if a register is available
10387 #ifndef HOST_IMM_ADDR32
10392 int earliest_available[HOST_REGS];
10393 int loop_start[HOST_REGS];
10394 int score[HOST_REGS];
10395 int end[HOST_REGS];
10396 int reg=using_tlb?MMREG:ROREG;
10399 for(hr=0;hr<HOST_REGS;hr++) {
10400 score[hr]=0;earliest_available[hr]=0;
10401 loop_start[hr]=MAXBLOCK;
10403 for(i=0;i<slen-1;i++)
10405 // Can't do anything if no registers are available
10406 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i]) {
10407 for(hr=0;hr<HOST_REGS;hr++) {
10408 score[hr]=0;earliest_available[hr]=i+1;
10409 loop_start[hr]=MAXBLOCK;
10412 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10414 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) {
10415 for(hr=0;hr<HOST_REGS;hr++) {
10416 score[hr]=0;earliest_available[hr]=i+1;
10417 loop_start[hr]=MAXBLOCK;
10421 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) {
10422 for(hr=0;hr<HOST_REGS;hr++) {
10423 score[hr]=0;earliest_available[hr]=i+1;
10424 loop_start[hr]=MAXBLOCK;
10429 // Mark unavailable registers
10430 for(hr=0;hr<HOST_REGS;hr++) {
10431 if(regs[i].regmap[hr]>=0) {
10432 score[hr]=0;earliest_available[hr]=i+1;
10433 loop_start[hr]=MAXBLOCK;
10435 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10436 if(branch_regs[i].regmap[hr]>=0) {
10437 score[hr]=0;earliest_available[hr]=i+2;
10438 loop_start[hr]=MAXBLOCK;
10442 // No register allocations after unconditional jumps
10443 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10445 for(hr=0;hr<HOST_REGS;hr++) {
10446 score[hr]=0;earliest_available[hr]=i+2;
10447 loop_start[hr]=MAXBLOCK;
10449 i++; // Skip delay slot too
10450 //printf("skip delay slot: %x\n",start+i*4);
10454 if(itype[i]==LOAD||itype[i]==LOADLR||
10455 itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) {
10456 for(hr=0;hr<HOST_REGS;hr++) {
10457 if(hr!=EXCLUDE_REG) {
10459 for(j=i;j<slen-1;j++) {
10460 if(regs[j].regmap[hr]>=0) break;
10461 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10462 if(branch_regs[j].regmap[hr]>=0) break;
10464 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) break;
10466 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) break;
10469 else if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) break;
10470 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10471 int t=(ba[j]-start)>>2;
10472 if(t<j&&t>=earliest_available[hr]) {
10473 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) { // call/ret assumes no registers allocated
10474 // Score a point for hoisting loop invariant
10475 if(t<loop_start[hr]) loop_start[hr]=t;
10476 //printf("set loop_start: i=%x j=%x (%x)\n",start+i*4,start+j*4,start+t*4);
10482 if(regs[t].regmap[hr]==reg) {
10483 // Score a point if the branch target matches this register
10488 if(itype[j+1]==LOAD||itype[j+1]==LOADLR||
10489 itype[j+1]==STORE||itype[j+1]==STORELR||itype[j+1]==C1LS) {
10494 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10496 // Stop on unconditional branch
10500 if(itype[j]==LOAD||itype[j]==LOADLR||
10501 itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS) {
10508 // Find highest score and allocate that register
10510 for(hr=0;hr<HOST_REGS;hr++) {
10511 if(hr!=EXCLUDE_REG) {
10512 if(score[hr]>score[maxscore]) {
10514 //printf("highest score: %d %d (%x->%x)\n",score[hr],hr,start+i*4,start+end[hr]*4);
10518 if(score[maxscore]>1)
10520 if(i<loop_start[maxscore]) loop_start[maxscore]=i;
10521 for(j=loop_start[maxscore];j<slen&&j<=end[maxscore];j++) {
10522 //if(regs[j].regmap[maxscore]>=0) {printf("oops: %x %x was %d=%d\n",loop_start[maxscore]*4+start,j*4+start,maxscore,regs[j].regmap[maxscore]);}
10523 assert(regs[j].regmap[maxscore]<0);
10524 if(j>loop_start[maxscore]) regs[j].regmap_entry[maxscore]=reg;
10525 regs[j].regmap[maxscore]=reg;
10526 regs[j].dirty&=~(1<<maxscore);
10527 regs[j].wasconst&=~(1<<maxscore);
10528 regs[j].isconst&=~(1<<maxscore);
10529 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10530 branch_regs[j].regmap[maxscore]=reg;
10531 branch_regs[j].wasdirty&=~(1<<maxscore);
10532 branch_regs[j].dirty&=~(1<<maxscore);
10533 branch_regs[j].wasconst&=~(1<<maxscore);
10534 branch_regs[j].isconst&=~(1<<maxscore);
10535 if(itype[j]!=RJUMP&&itype[j]!=UJUMP&&(source[j]>>16)!=0x1000) {
10536 regmap_pre[j+2][maxscore]=reg;
10537 regs[j+2].wasdirty&=~(1<<maxscore);
10539 // loop optimization (loop_preload)
10540 int t=(ba[j]-start)>>2;
10541 if(t==loop_start[maxscore]) {
10542 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) // call/ret assumes no registers allocated
10543 regs[t].regmap_entry[maxscore]=reg;
10548 if(j<1||(itype[j-1]!=RJUMP&&itype[j-1]!=UJUMP&&itype[j-1]!=CJUMP&&itype[j-1]!=SJUMP&&itype[j-1]!=FJUMP)) {
10549 regmap_pre[j+1][maxscore]=reg;
10550 regs[j+1].wasdirty&=~(1<<maxscore);
10555 if(itype[j-1]==RJUMP||itype[j-1]==UJUMP||itype[j-1]==CJUMP||itype[j-1]==SJUMP||itype[j-1]==FJUMP) i++; // skip delay slot
10556 for(hr=0;hr<HOST_REGS;hr++) {
10557 score[hr]=0;earliest_available[hr]=i+i;
10558 loop_start[hr]=MAXBLOCK;
10566 // This allocates registers (if possible) one instruction prior
10567 // to use, which can avoid a load-use penalty on certain CPUs.
10568 for(i=0;i<slen-1;i++)
10570 if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10574 if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
10575 ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
10578 if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10580 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10582 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10583 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10584 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10585 regs[i].isconst&=~(1<<hr);
10586 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10587 constmap[i][hr]=constmap[i+1][hr];
10588 regs[i+1].wasdirty&=~(1<<hr);
10589 regs[i].dirty&=~(1<<hr);
10594 if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10596 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10598 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10599 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10600 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10601 regs[i].isconst&=~(1<<hr);
10602 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10603 constmap[i][hr]=constmap[i+1][hr];
10604 regs[i+1].wasdirty&=~(1<<hr);
10605 regs[i].dirty&=~(1<<hr);
10609 // Preload target address for load instruction (non-constant)
10610 if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10611 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10613 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10615 regs[i].regmap[hr]=rs1[i+1];
10616 regmap_pre[i+1][hr]=rs1[i+1];
10617 regs[i+1].regmap_entry[hr]=rs1[i+1];
10618 regs[i].isconst&=~(1<<hr);
10619 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10620 constmap[i][hr]=constmap[i+1][hr];
10621 regs[i+1].wasdirty&=~(1<<hr);
10622 regs[i].dirty&=~(1<<hr);
10626 // Load source into target register
10627 if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10628 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10630 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10632 regs[i].regmap[hr]=rs1[i+1];
10633 regmap_pre[i+1][hr]=rs1[i+1];
10634 regs[i+1].regmap_entry[hr]=rs1[i+1];
10635 regs[i].isconst&=~(1<<hr);
10636 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10637 constmap[i][hr]=constmap[i+1][hr];
10638 regs[i+1].wasdirty&=~(1<<hr);
10639 regs[i].dirty&=~(1<<hr);
10643 // Preload map address
10644 #ifndef HOST_IMM_ADDR32
10645 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
10646 hr=get_reg(regs[i+1].regmap,TLREG);
10648 int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10649 if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10651 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10653 regs[i].regmap[hr]=MGEN1+((i+1)&1);
10654 regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10655 regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10656 regs[i].isconst&=~(1<<hr);
10657 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10658 constmap[i][hr]=constmap[i+1][hr];
10659 regs[i+1].wasdirty&=~(1<<hr);
10660 regs[i].dirty&=~(1<<hr);
10662 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10664 // move it to another register
10665 regs[i+1].regmap[hr]=-1;
10666 regmap_pre[i+2][hr]=-1;
10667 regs[i+1].regmap[nr]=TLREG;
10668 regmap_pre[i+2][nr]=TLREG;
10669 regs[i].regmap[nr]=MGEN1+((i+1)&1);
10670 regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10671 regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10672 regs[i].isconst&=~(1<<nr);
10673 regs[i+1].isconst&=~(1<<nr);
10674 regs[i].dirty&=~(1<<nr);
10675 regs[i+1].wasdirty&=~(1<<nr);
10676 regs[i+1].dirty&=~(1<<nr);
10677 regs[i+2].wasdirty&=~(1<<nr);
10683 // Address for store instruction (non-constant)
10684 if(itype[i+1]==STORE||itype[i+1]==STORELR
10685 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
10686 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10687 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10688 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10689 else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10691 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10693 regs[i].regmap[hr]=rs1[i+1];
10694 regmap_pre[i+1][hr]=rs1[i+1];
10695 regs[i+1].regmap_entry[hr]=rs1[i+1];
10696 regs[i].isconst&=~(1<<hr);
10697 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10698 constmap[i][hr]=constmap[i+1][hr];
10699 regs[i+1].wasdirty&=~(1<<hr);
10700 regs[i].dirty&=~(1<<hr);
10704 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
10705 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10707 hr=get_reg(regs[i+1].regmap,FTEMP);
10709 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10711 regs[i].regmap[hr]=rs1[i+1];
10712 regmap_pre[i+1][hr]=rs1[i+1];
10713 regs[i+1].regmap_entry[hr]=rs1[i+1];
10714 regs[i].isconst&=~(1<<hr);
10715 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10716 constmap[i][hr]=constmap[i+1][hr];
10717 regs[i+1].wasdirty&=~(1<<hr);
10718 regs[i].dirty&=~(1<<hr);
10720 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10722 // move it to another register
10723 regs[i+1].regmap[hr]=-1;
10724 regmap_pre[i+2][hr]=-1;
10725 regs[i+1].regmap[nr]=FTEMP;
10726 regmap_pre[i+2][nr]=FTEMP;
10727 regs[i].regmap[nr]=rs1[i+1];
10728 regmap_pre[i+1][nr]=rs1[i+1];
10729 regs[i+1].regmap_entry[nr]=rs1[i+1];
10730 regs[i].isconst&=~(1<<nr);
10731 regs[i+1].isconst&=~(1<<nr);
10732 regs[i].dirty&=~(1<<nr);
10733 regs[i+1].wasdirty&=~(1<<nr);
10734 regs[i+1].dirty&=~(1<<nr);
10735 regs[i+2].wasdirty&=~(1<<nr);
10739 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
10740 if(itype[i+1]==LOAD)
10741 hr=get_reg(regs[i+1].regmap,rt1[i+1]);
10742 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
10743 hr=get_reg(regs[i+1].regmap,FTEMP);
10744 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
10745 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10746 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10748 if(hr>=0&®s[i].regmap[hr]<0) {
10749 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10750 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10751 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10752 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10753 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10754 regs[i].isconst&=~(1<<hr);
10755 regs[i+1].wasdirty&=~(1<<hr);
10756 regs[i].dirty&=~(1<<hr);
10765 /* Pass 6 - Optimize clean/dirty state */
10766 clean_registers(0,slen-1,1);
10768 /* Pass 7 - Identify 32-bit registers */
10774 for (i=slen-1;i>=0;i--)
10777 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10779 if(ba[i]<start || ba[i]>=(start+slen*4))
10781 // Branch out of this block, don't need anything
10787 // Need whatever matches the target
10788 // (and doesn't get overwritten by the delay slot instruction)
10790 int t=(ba[i]-start)>>2;
10791 if(ba[i]>start+i*4) {
10793 if(!(requires_32bit[t]&~regs[i].was32))
10794 r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10797 //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10798 // r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10799 if(!(pr32[t]&~regs[i].was32))
10800 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10803 // Conditional branch may need registers for following instructions
10804 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10807 r32|=requires_32bit[i+2];
10808 r32&=regs[i].was32;
10809 // Mark this address as a branch target since it may be called
10810 // upon return from interrupt
10814 // Merge in delay slot
10816 // These are overwritten unless the branch is "likely"
10817 // and the delay slot is nullified if not taken
10818 r32&=~(1LL<<rt1[i+1]);
10819 r32&=~(1LL<<rt2[i+1]);
10821 // Assume these are needed (delay slot)
10824 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10828 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10830 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10832 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10834 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10836 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10839 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
10841 // SYSCALL instruction (software interrupt)
10844 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10846 // ERET instruction (return from interrupt)
10850 r32&=~(1LL<<rt1[i]);
10851 r32&=~(1LL<<rt2[i]);
10854 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10858 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10860 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
10862 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
10864 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
10866 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
10868 requires_32bit[i]=r32;
10870 // Dirty registers which are 32-bit, require 32-bit input
10871 // as they will be written as 32-bit values
10872 for(hr=0;hr<HOST_REGS;hr++)
10874 if(regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64) {
10875 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
10876 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
10877 requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
10881 //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
10884 for (i=slen-1;i>=0;i--)
10886 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10888 // Conditional branch
10889 if((source[i]>>16)!=0x1000&&i<slen-2) {
10890 // Mark this address as a branch target since it may be called
10891 // upon return from interrupt
10898 if(itype[slen-1]==SPAN) {
10899 bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
10903 /* Debug/disassembly */
10904 for(i=0;i<slen;i++)
10908 for(r=1;r<=CCREG;r++) {
10909 if((unneeded_reg[i]>>r)&1) {
10910 if(r==HIREG) printf(" HI");
10911 else if(r==LOREG) printf(" LO");
10912 else printf(" r%d",r);
10917 for(r=1;r<=CCREG;r++) {
10918 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
10919 if(r==HIREG) printf(" HI");
10920 else if(r==LOREG) printf(" LO");
10921 else printf(" r%d",r);
10925 for(r=0;r<=CCREG;r++) {
10926 //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10927 if((regs[i].was32>>r)&1) {
10928 if(r==CCREG) printf(" CC");
10929 else if(r==HIREG) printf(" HI");
10930 else if(r==LOREG) printf(" LO");
10931 else printf(" r%d",r);
10936 #if defined(__i386__) || defined(__x86_64__)
10937 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
10940 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
10943 if(needed_reg[i]&1) printf("eax ");
10944 if((needed_reg[i]>>1)&1) printf("ecx ");
10945 if((needed_reg[i]>>2)&1) printf("edx ");
10946 if((needed_reg[i]>>3)&1) printf("ebx ");
10947 if((needed_reg[i]>>5)&1) printf("ebp ");
10948 if((needed_reg[i]>>6)&1) printf("esi ");
10949 if((needed_reg[i]>>7)&1) printf("edi ");
10951 for(r=0;r<=CCREG;r++) {
10952 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10953 if((requires_32bit[i]>>r)&1) {
10954 if(r==CCREG) printf(" CC");
10955 else if(r==HIREG) printf(" HI");
10956 else if(r==LOREG) printf(" LO");
10957 else printf(" r%d",r);
10962 for(r=0;r<=CCREG;r++) {
10963 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10964 if((pr32[i]>>r)&1) {
10965 if(r==CCREG) printf(" CC");
10966 else if(r==HIREG) printf(" HI");
10967 else if(r==LOREG) printf(" LO");
10968 else printf(" r%d",r);
10971 if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
10973 #if defined(__i386__) || defined(__x86_64__)
10974 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
10976 if(regs[i].wasdirty&1) printf("eax ");
10977 if((regs[i].wasdirty>>1)&1) printf("ecx ");
10978 if((regs[i].wasdirty>>2)&1) printf("edx ");
10979 if((regs[i].wasdirty>>3)&1) printf("ebx ");
10980 if((regs[i].wasdirty>>5)&1) printf("ebp ");
10981 if((regs[i].wasdirty>>6)&1) printf("esi ");
10982 if((regs[i].wasdirty>>7)&1) printf("edi ");
10985 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
10987 if(regs[i].wasdirty&1) printf("r0 ");
10988 if((regs[i].wasdirty>>1)&1) printf("r1 ");
10989 if((regs[i].wasdirty>>2)&1) printf("r2 ");
10990 if((regs[i].wasdirty>>3)&1) printf("r3 ");
10991 if((regs[i].wasdirty>>4)&1) printf("r4 ");
10992 if((regs[i].wasdirty>>5)&1) printf("r5 ");
10993 if((regs[i].wasdirty>>6)&1) printf("r6 ");
10994 if((regs[i].wasdirty>>7)&1) printf("r7 ");
10995 if((regs[i].wasdirty>>8)&1) printf("r8 ");
10996 if((regs[i].wasdirty>>9)&1) printf("r9 ");
10997 if((regs[i].wasdirty>>10)&1) printf("r10 ");
10998 if((regs[i].wasdirty>>12)&1) printf("r12 ");
11001 disassemble_inst(i);
11002 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
11003 #if defined(__i386__) || defined(__x86_64__)
11004 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
11005 if(regs[i].dirty&1) printf("eax ");
11006 if((regs[i].dirty>>1)&1) printf("ecx ");
11007 if((regs[i].dirty>>2)&1) printf("edx ");
11008 if((regs[i].dirty>>3)&1) printf("ebx ");
11009 if((regs[i].dirty>>5)&1) printf("ebp ");
11010 if((regs[i].dirty>>6)&1) printf("esi ");
11011 if((regs[i].dirty>>7)&1) printf("edi ");
11014 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
11015 if(regs[i].dirty&1) printf("r0 ");
11016 if((regs[i].dirty>>1)&1) printf("r1 ");
11017 if((regs[i].dirty>>2)&1) printf("r2 ");
11018 if((regs[i].dirty>>3)&1) printf("r3 ");
11019 if((regs[i].dirty>>4)&1) printf("r4 ");
11020 if((regs[i].dirty>>5)&1) printf("r5 ");
11021 if((regs[i].dirty>>6)&1) printf("r6 ");
11022 if((regs[i].dirty>>7)&1) printf("r7 ");
11023 if((regs[i].dirty>>8)&1) printf("r8 ");
11024 if((regs[i].dirty>>9)&1) printf("r9 ");
11025 if((regs[i].dirty>>10)&1) printf("r10 ");
11026 if((regs[i].dirty>>12)&1) printf("r12 ");
11029 if(regs[i].isconst) {
11030 printf("constants: ");
11031 #if defined(__i386__) || defined(__x86_64__)
11032 if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
11033 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
11034 if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
11035 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
11036 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
11037 if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
11038 if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
11041 if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
11042 if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
11043 if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
11044 if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
11045 if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
11046 if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
11047 if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
11048 if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
11049 if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
11050 if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
11051 if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
11052 if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
11058 for(r=0;r<=CCREG;r++) {
11059 if((regs[i].is32>>r)&1) {
11060 if(r==CCREG) printf(" CC");
11061 else if(r==HIREG) printf(" HI");
11062 else if(r==LOREG) printf(" LO");
11063 else printf(" r%d",r);
11069 for(r=0;r<=CCREG;r++) {
11070 if((p32[i]>>r)&1) {
11071 if(r==CCREG) printf(" CC");
11072 else if(r==HIREG) printf(" HI");
11073 else if(r==LOREG) printf(" LO");
11074 else printf(" r%d",r);
11077 if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
11078 else printf("\n");*/
11079 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
11080 #if defined(__i386__) || defined(__x86_64__)
11081 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
11082 if(branch_regs[i].dirty&1) printf("eax ");
11083 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
11084 if((branch_regs[i].dirty>>2)&1) printf("edx ");
11085 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
11086 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
11087 if((branch_regs[i].dirty>>6)&1) printf("esi ");
11088 if((branch_regs[i].dirty>>7)&1) printf("edi ");
11091 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
11092 if(branch_regs[i].dirty&1) printf("r0 ");
11093 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
11094 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
11095 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
11096 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
11097 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
11098 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
11099 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
11100 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
11101 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
11102 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
11103 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
11107 for(r=0;r<=CCREG;r++) {
11108 if((branch_regs[i].is32>>r)&1) {
11109 if(r==CCREG) printf(" CC");
11110 else if(r==HIREG) printf(" HI");
11111 else if(r==LOREG) printf(" LO");
11112 else printf(" r%d",r);
11121 /* Pass 8 - Assembly */
11122 linkcount=0;stubcount=0;
11123 ds=0;is_delayslot=0;
11125 uint64_t is32_pre=0;
11127 u_int beginning=(u_int)out;
11128 if((u_int)addr&1) {
11132 u_int instr_addr0_override=0;
11135 if (start == 0x80030000) {
11136 // nasty hack for fastbios thing
11137 // override block entry to this code
11138 instr_addr0_override=(u_int)out;
11139 emit_movimm(start,0);
11140 // abuse io address var as a flag that we
11141 // have already returned here once
11142 emit_readword((int)&address,1);
11143 emit_writeword(0,(int)&pcaddr);
11144 emit_writeword(0,(int)&address);
11146 emit_jne((int)new_dyna_leave);
11149 for(i=0;i<slen;i++)
11151 //if(ds) printf("ds: ");
11152 disassemble_inst(i);
11154 ds=0; // Skip delay slot
11155 if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
11158 #ifndef DESTRUCTIVE_WRITEBACK
11159 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11161 wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
11162 unneeded_reg[i],unneeded_reg_upper[i]);
11163 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
11164 unneeded_reg[i],unneeded_reg_upper[i]);
11166 if((itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)&&!likely[i]) {
11167 is32_pre=branch_regs[i].is32;
11168 dirty_pre=branch_regs[i].dirty;
11170 is32_pre=regs[i].is32;
11171 dirty_pre=regs[i].dirty;
11175 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11177 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
11178 unneeded_reg[i],unneeded_reg_upper[i]);
11179 loop_preload(regmap_pre[i],regs[i].regmap_entry);
11181 // branch target entry point
11182 instr_addr[i]=(u_int)out;
11183 assem_debug("<->\n");
11185 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&®s[i].regmap[HOST_CCREG]!=CCREG)
11186 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
11187 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
11188 address_generation(i,®s[i],regs[i].regmap_entry);
11189 load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
11190 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
11192 // Load the delay slot registers if necessary
11193 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i]&&(rs1[i+1]!=rt1[i]||rt1[i]==0))
11194 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11195 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i]&&(rs2[i+1]!=rt1[i]||rt1[i]==0))
11196 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11197 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
11198 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11202 // Preload registers for following instruction
11203 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
11204 if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
11205 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11206 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
11207 if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
11208 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11210 // TODO: if(is_ooo(i)) address_generation(i+1);
11211 if(itype[i]==CJUMP||itype[i]==FJUMP)
11212 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
11213 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
11214 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11215 if(bt[i]) cop1_usable=0;
11219 alu_assemble(i,®s[i]);break;
11221 imm16_assemble(i,®s[i]);break;
11223 shift_assemble(i,®s[i]);break;
11225 shiftimm_assemble(i,®s[i]);break;
11227 load_assemble(i,®s[i]);break;
11229 loadlr_assemble(i,®s[i]);break;
11231 store_assemble(i,®s[i]);break;
11233 storelr_assemble(i,®s[i]);break;
11235 cop0_assemble(i,®s[i]);break;
11237 cop1_assemble(i,®s[i]);break;
11239 c1ls_assemble(i,®s[i]);break;
11241 cop2_assemble(i,®s[i]);break;
11243 c2ls_assemble(i,®s[i]);break;
11245 c2op_assemble(i,®s[i]);break;
11247 fconv_assemble(i,®s[i]);break;
11249 float_assemble(i,®s[i]);break;
11251 fcomp_assemble(i,®s[i]);break;
11253 multdiv_assemble(i,®s[i]);break;
11255 mov_assemble(i,®s[i]);break;
11257 syscall_assemble(i,®s[i]);break;
11259 hlecall_assemble(i,®s[i]);break;
11261 intcall_assemble(i,®s[i]);break;
11263 ujump_assemble(i,®s[i]);ds=1;break;
11265 rjump_assemble(i,®s[i]);ds=1;break;
11267 cjump_assemble(i,®s[i]);ds=1;break;
11269 sjump_assemble(i,®s[i]);ds=1;break;
11271 fjump_assemble(i,®s[i]);ds=1;break;
11273 pagespan_assemble(i,®s[i]);break;
11275 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
11276 literal_pool(1024);
11278 literal_pool_jumpover(256);
11281 //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
11282 // If the block did not end with an unconditional branch,
11283 // add a jump to the next instruction.
11285 if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
11286 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11288 if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
11289 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11290 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11291 emit_loadreg(CCREG,HOST_CCREG);
11292 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
11294 else if(!likely[i-2])
11296 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
11297 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
11301 store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
11302 assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
11304 add_to_linker((int)out,start+i*4,0);
11311 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11312 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11313 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11314 emit_loadreg(CCREG,HOST_CCREG);
11315 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
11316 add_to_linker((int)out,start+i*4,0);
11320 // TODO: delay slot stubs?
11322 for(i=0;i<stubcount;i++)
11324 switch(stubs[i][0])
11332 do_readstub(i);break;
11337 do_writestub(i);break;
11339 do_ccstub(i);break;
11341 do_invstub(i);break;
11343 do_cop1stub(i);break;
11345 do_unalignedwritestub(i);break;
11349 if (instr_addr0_override)
11350 instr_addr[0] = instr_addr0_override;
11352 /* Pass 9 - Linker */
11353 for(i=0;i<linkcount;i++)
11355 assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
11357 if(!link_addr[i][2])
11360 void *addr=check_addr(link_addr[i][1]);
11361 emit_extjump(link_addr[i][0],link_addr[i][1]);
11363 set_jump_target(link_addr[i][0],(int)addr);
11364 add_link(link_addr[i][1],stub);
11366 else set_jump_target(link_addr[i][0],(int)stub);
11371 int target=(link_addr[i][1]-start)>>2;
11372 assert(target>=0&&target<slen);
11373 assert(instr_addr[target]);
11374 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11375 //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
11377 set_jump_target(link_addr[i][0],instr_addr[target]);
11381 // External Branch Targets (jump_in)
11382 if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
11383 for(i=0;i<slen;i++)
11387 if(instr_addr[i]) // TODO - delay slots (=null)
11389 u_int vaddr=start+i*4;
11390 u_int page=get_page(vaddr);
11391 u_int vpage=get_vpage(vaddr);
11393 //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
11395 if(!requires_32bit[i])
11400 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11401 assem_debug("jump_in: %x\n",start+i*4);
11402 ll_add(jump_dirty+vpage,vaddr,(void *)out);
11403 int entry_point=do_dirty_stub(i);
11404 ll_add(jump_in+page,vaddr,(void *)entry_point);
11405 // If there was an existing entry in the hash table,
11406 // replace it with the new address.
11407 // Don't add new entries. We'll insert the
11408 // ones that actually get used in check_addr().
11409 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
11410 if(ht_bin[0]==vaddr) {
11411 ht_bin[1]=entry_point;
11413 if(ht_bin[2]==vaddr) {
11414 ht_bin[3]=entry_point;
11419 u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
11420 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11421 assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
11422 //int entry_point=(int)out;
11423 ////assem_debug("entry_point: %x\n",entry_point);
11424 //load_regs_entry(i);
11425 //if(entry_point==(int)out)
11426 // entry_point=instr_addr[i];
11428 // emit_jmp(instr_addr[i]);
11429 //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11430 ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
11431 int entry_point=do_dirty_stub(i);
11432 ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11437 // Write out the literal pool if necessary
11439 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11441 if(((u_int)out)&7) emit_addnop(13);
11443 assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
11444 //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
11445 memcpy(copy,source,slen*4);
11449 __clear_cache((void *)beginning,out);
11452 // If we're within 256K of the end of the buffer,
11453 // start over from the beginning. (Is 256K enough?)
11454 if((int)out>BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
11456 // Trap writes to any of the pages we compiled
11457 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
11459 #ifndef DISABLE_TLB
11460 memory_map[i]|=0x40000000;
11461 if((signed int)start>=(signed int)0xC0000000) {
11463 j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
11465 memory_map[j]|=0x40000000;
11466 //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
11470 inv_code_start=inv_code_end=~0;
11472 // for PCSX we need to mark all mirrors too
11473 if(get_page(start)<(RAM_SIZE>>12))
11474 for(i=start>>12;i<=(start+slen*4)>>12;i++)
11475 invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]=
11476 invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]=
11477 invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0;
11480 /* Pass 10 - Free memory by expiring oldest blocks */
11482 int end=((((int)out-BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
11483 while(expirep!=end)
11485 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
11486 int base=BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
11487 inv_debug("EXP: Phase %d\n",expirep);
11488 switch((expirep>>11)&3)
11491 // Clear jump_in and jump_dirty
11492 ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
11493 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
11494 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
11495 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
11499 ll_kill_pointers(jump_out[expirep&2047],base,shift);
11500 ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
11503 // Clear hash table
11504 for(i=0;i<32;i++) {
11505 int *ht_bin=hash_table[((expirep&2047)<<5)+i];
11506 if((ht_bin[3]>>shift)==(base>>shift) ||
11507 ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11508 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
11509 ht_bin[2]=ht_bin[3]=-1;
11511 if((ht_bin[1]>>shift)==(base>>shift) ||
11512 ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11513 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
11514 ht_bin[0]=ht_bin[2];
11515 ht_bin[1]=ht_bin[3];
11516 ht_bin[2]=ht_bin[3]=-1;
11523 if((expirep&2047)==0)
11526 ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
11527 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
11530 expirep=(expirep+1)&65535;
11535 // vim:shiftwidth=2:expandtab