libpcsxcore/new_dynarec/new_dynarec.c

   1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
   2  *   Mupen64plus - new_dynarec.c                                           *
   3  *   Copyright (C) 2009-2010 Ari64                                         *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.          *
  19  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
  20
  21 #include <stdlib.h>
  22 #include <stdint.h> //include for uint64_t
  23 #include <assert.h>
  24
  25 #include "emu_if.h" //emulator interface
  26
  27 #include <sys/mman.h>
  28
  29 #ifdef __i386__
  30 #include "assem_x86.h"
  31 #endif
  32 #ifdef __x86_64__
  33 #include "assem_x64.h"
  34 #endif
  35 #ifdef __arm__
  36 #include "assem_arm.h"
  37 #endif
  38
  39 #define MAXBLOCK 4096
  40 #define MAX_OUTPUT_BLOCK_SIZE 262144
  41 #define CLOCK_DIVIDER 2
  42
  43 struct regstat
  44 {
  45   signed char regmap_entry[HOST_REGS];
  46   signed char regmap[HOST_REGS];
  47   uint64_t was32;
  48   uint64_t is32;
  49   uint64_t wasdirty;
  50   uint64_t dirty;
  51   uint64_t u;
  52   uint64_t uu;
  53   u_int wasconst;
  54   u_int isconst;
  55   uint64_t constmap[HOST_REGS];
  56 };
  57
  58 struct ll_entry
  59 {
  60   u_int vaddr;
  61   u_int reg32;
  62   void *addr;
  63   struct ll_entry *next;
  64 };
  65
  66   u_int start;
  67   u_int *source;
  68   u_int pagelimit;
  69   char insn[MAXBLOCK][10];
  70   u_char itype[MAXBLOCK];
  71   u_char opcode[MAXBLOCK];
  72   u_char opcode2[MAXBLOCK];
  73   u_char bt[MAXBLOCK];
  74   u_char rs1[MAXBLOCK];
  75   u_char rs2[MAXBLOCK];
  76   u_char rt1[MAXBLOCK];
  77   u_char rt2[MAXBLOCK];
  78   u_char us1[MAXBLOCK];
  79   u_char us2[MAXBLOCK];
  80   u_char dep1[MAXBLOCK];
  81   u_char dep2[MAXBLOCK];
  82   u_char lt1[MAXBLOCK];
  83   int imm[MAXBLOCK];
  84   u_int ba[MAXBLOCK];
  85   char likely[MAXBLOCK];
  86   char is_ds[MAXBLOCK];
  87   char ooo[MAXBLOCK];
  88   uint64_t unneeded_reg[MAXBLOCK];
  89   uint64_t unneeded_reg_upper[MAXBLOCK];
  90   uint64_t branch_unneeded_reg[MAXBLOCK];
  91   uint64_t branch_unneeded_reg_upper[MAXBLOCK];
  92   uint64_t p32[MAXBLOCK];
  93   uint64_t pr32[MAXBLOCK];
  94   signed char regmap_pre[MAXBLOCK][HOST_REGS];
  95   signed char regmap[MAXBLOCK][HOST_REGS];
  96   signed char regmap_entry[MAXBLOCK][HOST_REGS];
  97   uint64_t constmap[MAXBLOCK][HOST_REGS];
  98   struct regstat regs[MAXBLOCK];
  99   struct regstat branch_regs[MAXBLOCK];
 100   signed char minimum_free_regs[MAXBLOCK];
 101   u_int needed_reg[MAXBLOCK];
 102   uint64_t requires_32bit[MAXBLOCK];
 103   u_int wont_dirty[MAXBLOCK];
 104   u_int will_dirty[MAXBLOCK];
 105   int ccadj[MAXBLOCK];
 106   int slen;
 107   u_int instr_addr[MAXBLOCK];
 108   u_int link_addr[MAXBLOCK][3];
 109   int linkcount;
 110   u_int stubs[MAXBLOCK*3][8];
 111   int stubcount;
 112   u_int literals[1024][2];
 113   int literalcount;
 114   int is_delayslot;
 115   int cop1_usable;
 116   u_char *out;
 117   struct ll_entry *jump_in[4096];
 118   struct ll_entry *jump_out[4096];
 119   struct ll_entry *jump_dirty[4096];
 120   u_int hash_table[65536][4]  __attribute__((aligned(16)));
 121   char shadow[1048576]  __attribute__((aligned(16)));
 122   void *copy;
 123   int expirep;
 124 #ifndef PCSX
 125   u_int using_tlb;
 126 #else
 127   static const u_int using_tlb=0;
 128 #endif
 129   u_int stop_after_jal;
 130   extern u_char restore_candidate[512];
 131   extern int cycle_count;
 132
 133   /* registers that may be allocated */
 134   /* 1-31 gpr */
 135 #define HIREG 32 // hi
 136 #define LOREG 33 // lo
 137 #define FSREG 34 // FPU status (FCSR)
 138 #define CSREG 35 // Coprocessor status
 139 #define CCREG 36 // Cycle count
 140 #define INVCP 37 // Pointer to invalid_code
 141 #define MMREG 38 // Pointer to memory_map
 142 #define ROREG 39 // ram offset (if rdram!=0x80000000)
 143 #define TEMPREG 40
 144 #define FTEMP 40 // FPU temporary register
 145 #define PTEMP 41 // Prefetch temporary register
 146 #define TLREG 42 // TLB mapping offset
 147 #define RHASH 43 // Return address hash
 148 #define RHTBL 44 // Return address hash table address
 149 #define RTEMP 45 // JR/JALR address register
 150 #define MAXREG 45
 151 #define AGEN1 46 // Address generation temporary register
 152 #define AGEN2 47 // Address generation temporary register
 153 #define MGEN1 48 // Maptable address generation temporary register
 154 #define MGEN2 49 // Maptable address generation temporary register
 155 #define BTREG 50 // Branch target temporary register
 156
 157   /* instruction types */
 158 #define NOP 0     // No operation
 159 #define LOAD 1    // Load
 160 #define STORE 2   // Store
 161 #define LOADLR 3  // Unaligned load
 162 #define STORELR 4 // Unaligned store
 163 #define MOV 5     // Move
 164 #define ALU 6     // Arithmetic/logic
 165 #define MULTDIV 7 // Multiply/divide
 166 #define SHIFT 8   // Shift by register
 167 #define SHIFTIMM 9// Shift by immediate
 168 #define IMM16 10  // 16-bit immediate
 169 #define RJUMP 11  // Unconditional jump to register
 170 #define UJUMP 12  // Unconditional jump
 171 #define CJUMP 13  // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
 172 #define SJUMP 14  // Conditional branch (regimm format)
 173 #define COP0 15   // Coprocessor 0
 174 #define COP1 16   // Coprocessor 1
 175 #define C1LS 17   // Coprocessor 1 load/store
 176 #define FJUMP 18  // Conditional branch (floating point)
 177 #define FLOAT 19  // Floating point unit
 178 #define FCONV 20  // Convert integer to float
 179 #define FCOMP 21  // Floating point compare (sets FSREG)
 180 #define SYSCALL 22// SYSCALL
 181 #define OTHER 23  // Other
 182 #define SPAN 24   // Branch/delay slot spans 2 pages
 183 #define NI 25     // Not implemented
 184 #define HLECALL 26// PCSX fake opcodes for HLE
 185 #define COP2 27   // Coprocessor 2 move
 186 #define C2LS 28   // Coprocessor 2 load/store
 187 #define C2OP 29   // Coprocessor 2 operation
 188 #define INTCALL 30// Call interpreter to handle rare corner cases
 189
 190   /* stubs */
 191 #define CC_STUB 1
 192 #define FP_STUB 2
 193 #define LOADB_STUB 3
 194 #define LOADH_STUB 4
 195 #define LOADW_STUB 5
 196 #define LOADD_STUB 6
 197 #define LOADBU_STUB 7
 198 #define LOADHU_STUB 8
 199 #define STOREB_STUB 9
 200 #define STOREH_STUB 10
 201 #define STOREW_STUB 11
 202 #define STORED_STUB 12
 203 #define STORELR_STUB 13
 204 #define INVCODE_STUB 14
 205
 206   /* branch codes */
 207 #define TAKEN 1
 208 #define NOTTAKEN 2
 209 #define NULLDS 3
 210
 211 // asm linkage
 212 int new_recompile_block(int addr);
 213 void *get_addr_ht(u_int vaddr);
 214 void invalidate_block(u_int block);
 215 void invalidate_addr(u_int addr);
 216 void remove_hash(int vaddr);
 217 void jump_vaddr();
 218 void dyna_linker();
 219 void dyna_linker_ds();
 220 void verify_code();
 221 void verify_code_vm();
 222 void verify_code_ds();
 223 void cc_interrupt();
 224 void fp_exception();
 225 void fp_exception_ds();
 226 void jump_syscall();
 227 void jump_syscall_hle();
 228 void jump_eret();
 229 void jump_hlecall();
 230 void jump_intcall();
 231 void new_dyna_leave();
 232
 233 // TLB
 234 void TLBWI_new();
 235 void TLBWR_new();
 236 void read_nomem_new();
 237 void read_nomemb_new();
 238 void read_nomemh_new();
 239 void read_nomemd_new();
 240 void write_nomem_new();
 241 void write_nomemb_new();
 242 void write_nomemh_new();
 243 void write_nomemd_new();
 244 void write_rdram_new();
 245 void write_rdramb_new();
 246 void write_rdramh_new();
 247 void write_rdramd_new();
 248 extern u_int memory_map[1048576];
 249
 250 // Needed by assembler
 251 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
 252 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
 253 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
 254 void load_all_regs(signed char i_regmap[]);
 255 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
 256 void load_regs_entry(int t);
 257 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
 258
 259 int tracedebug=0;
 260
 261 //#define DEBUG_CYCLE_COUNT 1
 262
 263 void nullf() {}
 264 //#define assem_debug printf
 265 //#define inv_debug printf
 266 #define assem_debug nullf
 267 #define inv_debug nullf
 268
 269 static void tlb_hacks()
 270 {
 271 #ifndef DISABLE_TLB
 272   // Goldeneye hack
 273   if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
 274   {
 275     u_int addr;
 276     int n;
 277     switch (ROM_HEADER->Country_code&0xFF)
 278     {
 279       case 0x45: // U
 280         addr=0x34b30;
 281         break;
 282       case 0x4A: // J
 283         addr=0x34b70;
 284         break;
 285       case 0x50: // E
 286         addr=0x329f0;
 287         break;
 288       default:
 289         // Unknown country code
 290         addr=0;
 291         break;
 292     }
 293     u_int rom_addr=(u_int)rom;
 294     #ifdef ROM_COPY
 295     // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
 296     // in the lower 4G of memory to use this hack.  Copy it if necessary.
 297     if((void *)rom>(void *)0xffffffff) {
 298       munmap(ROM_COPY, 67108864);
 299       if(mmap(ROM_COPY, 12582912,
 300               PROT_READ | PROT_WRITE,
 301               MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
 302               -1, 0) <= 0) {printf("mmap() failed\n");}
 303       memcpy(ROM_COPY,rom,12582912);
 304       rom_addr=(u_int)ROM_COPY;
 305     }
 306     #endif
 307     if(addr) {
 308       for(n=0x7F000;n<0x80000;n++) {
 309         memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
 310       }
 311     }
 312   }
 313 #endif
 314 }
 315
 316 static u_int get_page(u_int vaddr)
 317 {
 318 #ifndef PCSX
 319   u_int page=(vaddr^0x80000000)>>12;
 320 #else
 321   u_int page=vaddr&~0xe0000000;
 322   if (page < 0x1000000)
 323     page &= ~0x0e00000; // RAM mirrors
 324   page>>=12;
 325 #endif
 326 #ifndef DISABLE_TLB
 327   if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
 328 #endif
 329   if(page>2048) page=2048+(page&2047);
 330   return page;
 331 }
 332
 333 static u_int get_vpage(u_int vaddr)
 334 {
 335   u_int vpage=(vaddr^0x80000000)>>12;
 336 #ifndef DISABLE_TLB
 337   if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
 338 #endif
 339   if(vpage>2048) vpage=2048+(vpage&2047);
 340   return vpage;
 341 }
 342
 343 // Get address from virtual address
 344 // This is called from the recompiled JR/JALR instructions
 345 void *get_addr(u_int vaddr)
 346 {
 347   u_int page=get_page(vaddr);
 348   u_int vpage=get_vpage(vaddr);
 349   struct ll_entry *head;
 350   //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
 351   head=jump_in[page];
 352   while(head!=NULL) {
 353     if(head->vaddr==vaddr&&head->reg32==0) {
 354   //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 355       int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 356       ht_bin[3]=ht_bin[1];
 357       ht_bin[2]=ht_bin[0];
 358       ht_bin[1]=(int)head->addr;
 359       ht_bin[0]=vaddr;
 360       return head->addr;
 361     }
 362     head=head->next;
 363   }
 364   head=jump_dirty[vpage];
 365   while(head!=NULL) {
 366     if(head->vaddr==vaddr&&head->reg32==0) {
 367       //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 368       // Don't restore blocks which are about to expire from the cache
 369       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 370       if(verify_dirty(head->addr)) {
 371         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
 372         invalid_code[vaddr>>12]=0;
 373         memory_map[vaddr>>12]|=0x40000000;
 374         if(vpage<2048) {
 375 #ifndef DISABLE_TLB
 376           if(tlb_LUT_r[vaddr>>12]) {
 377             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
 378             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
 379           }
 380 #endif
 381           restore_candidate[vpage>>3]|=1<<(vpage&7);
 382         }
 383         else restore_candidate[page>>3]|=1<<(page&7);
 384         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 385         if(ht_bin[0]==vaddr) {
 386           ht_bin[1]=(int)head->addr; // Replace existing entry
 387         }
 388         else
 389         {
 390           ht_bin[3]=ht_bin[1];
 391           ht_bin[2]=ht_bin[0];
 392           ht_bin[1]=(int)head->addr;
 393           ht_bin[0]=vaddr;
 394         }
 395         return head->addr;
 396       }
 397     }
 398     head=head->next;
 399   }
 400   //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
 401   int r=new_recompile_block(vaddr);
 402   if(r==0) return get_addr(vaddr);
 403   // Execute in unmapped page, generate pagefault execption
 404   Status|=2;
 405   Cause=(vaddr<<31)|0x8;
 406   EPC=(vaddr&1)?vaddr-5:vaddr;
 407   BadVAddr=(vaddr&~1);
 408   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
 409   EntryHi=BadVAddr&0xFFFFE000;
 410   return get_addr_ht(0x80000000);
 411 }
 412 // Look up address in hash table first
 413 void *get_addr_ht(u_int vaddr)
 414 {
 415   //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
 416   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 417   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
 418   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
 419   return get_addr(vaddr);
 420 }
 421
 422 void *get_addr_32(u_int vaddr,u_int flags)
 423 {
 424 #ifdef FORCE32
 425   return get_addr(vaddr);
 426 #else
 427   //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
 428   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 429   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
 430   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
 431   u_int page=get_page(vaddr);
 432   u_int vpage=get_vpage(vaddr);
 433   struct ll_entry *head;
 434   head=jump_in[page];
 435   while(head!=NULL) {
 436     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
 437       //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 438       if(head->reg32==0) {
 439         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 440         if(ht_bin[0]==-1) {
 441           ht_bin[1]=(int)head->addr;
 442           ht_bin[0]=vaddr;
 443         }else if(ht_bin[2]==-1) {
 444           ht_bin[3]=(int)head->addr;
 445           ht_bin[2]=vaddr;
 446         }
 447         //ht_bin[3]=ht_bin[1];
 448         //ht_bin[2]=ht_bin[0];
 449         //ht_bin[1]=(int)head->addr;
 450         //ht_bin[0]=vaddr;
 451       }
 452       return head->addr;
 453     }
 454     head=head->next;
 455   }
 456   head=jump_dirty[vpage];
 457   while(head!=NULL) {
 458     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
 459       //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 460       // Don't restore blocks which are about to expire from the cache
 461       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 462       if(verify_dirty(head->addr)) {
 463         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
 464         invalid_code[vaddr>>12]=0;
 465         memory_map[vaddr>>12]|=0x40000000;
 466         if(vpage<2048) {
 467 #ifndef DISABLE_TLB
 468           if(tlb_LUT_r[vaddr>>12]) {
 469             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
 470             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
 471           }
 472 #endif
 473           restore_candidate[vpage>>3]|=1<<(vpage&7);
 474         }
 475         else restore_candidate[page>>3]|=1<<(page&7);
 476         if(head->reg32==0) {
 477           int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 478           if(ht_bin[0]==-1) {
 479             ht_bin[1]=(int)head->addr;
 480             ht_bin[0]=vaddr;
 481           }else if(ht_bin[2]==-1) {
 482             ht_bin[3]=(int)head->addr;
 483             ht_bin[2]=vaddr;
 484           }
 485           //ht_bin[3]=ht_bin[1];
 486           //ht_bin[2]=ht_bin[0];
 487           //ht_bin[1]=(int)head->addr;
 488           //ht_bin[0]=vaddr;
 489         }
 490         return head->addr;
 491       }
 492     }
 493     head=head->next;
 494   }
 495   //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
 496   int r=new_recompile_block(vaddr);
 497   if(r==0) return get_addr(vaddr);
 498   // Execute in unmapped page, generate pagefault execption
 499   Status|=2;
 500   Cause=(vaddr<<31)|0x8;
 501   EPC=(vaddr&1)?vaddr-5:vaddr;
 502   BadVAddr=(vaddr&~1);
 503   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
 504   EntryHi=BadVAddr&0xFFFFE000;
 505   return get_addr_ht(0x80000000);
 506 #endif
 507 }
 508
 509 void clear_all_regs(signed char regmap[])
 510 {
 511   int hr;
 512   for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
 513 }
 514
 515 signed char get_reg(signed char regmap[],int r)
 516 {
 517   int hr;
 518   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
 519   return -1;
 520 }
 521
 522 // Find a register that is available for two consecutive cycles
 523 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
 524 {
 525   int hr;
 526   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
 527   return -1;
 528 }
 529
 530 int count_free_regs(signed char regmap[])
 531 {
 532   int count=0;
 533   int hr;
 534   for(hr=0;hr<HOST_REGS;hr++)
 535   {
 536     if(hr!=EXCLUDE_REG) {
 537       if(regmap[hr]<0) count++;
 538     }
 539   }
 540   return count;
 541 }
 542
 543 void dirty_reg(struct regstat *cur,signed char reg)
 544 {
 545   int hr;
 546   if(!reg) return;
 547   for (hr=0;hr<HOST_REGS;hr++) {
 548     if((cur->regmap[hr]&63)==reg) {
 549       cur->dirty|=1<<hr;
 550     }
 551   }
 552 }
 553
 554 // If we dirty the lower half of a 64 bit register which is now being
 555 // sign-extended, we need to dump the upper half.
 556 // Note: Do this only after completion of the instruction, because
 557 // some instructions may need to read the full 64-bit value even if
 558 // overwriting it (eg SLTI, DSRA32).
 559 static void flush_dirty_uppers(struct regstat *cur)
 560 {
 561   int hr,reg;
 562   for (hr=0;hr<HOST_REGS;hr++) {
 563     if((cur->dirty>>hr)&1) {
 564       reg=cur->regmap[hr];
 565       if(reg>=64)
 566         if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
 567     }
 568   }
 569 }
 570
 571 void set_const(struct regstat *cur,signed char reg,uint64_t value)
 572 {
 573   int hr;
 574   if(!reg) return;
 575   for (hr=0;hr<HOST_REGS;hr++) {
 576     if(cur->regmap[hr]==reg) {
 577       cur->isconst|=1<<hr;
 578       cur->constmap[hr]=value;
 579     }
 580     else if((cur->regmap[hr]^64)==reg) {
 581       cur->isconst|=1<<hr;
 582       cur->constmap[hr]=value>>32;
 583     }
 584   }
 585 }
 586
 587 void clear_const(struct regstat *cur,signed char reg)
 588 {
 589   int hr;
 590   if(!reg) return;
 591   for (hr=0;hr<HOST_REGS;hr++) {
 592     if((cur->regmap[hr]&63)==reg) {
 593       cur->isconst&=~(1<<hr);
 594     }
 595   }
 596 }
 597
 598 int is_const(struct regstat *cur,signed char reg)
 599 {
 600   int hr;
 601   if(!reg) return 1;
 602   for (hr=0;hr<HOST_REGS;hr++) {
 603     if((cur->regmap[hr]&63)==reg) {
 604       return (cur->isconst>>hr)&1;
 605     }
 606   }
 607   return 0;
 608 }
 609 uint64_t get_const(struct regstat *cur,signed char reg)
 610 {
 611   int hr;
 612   if(!reg) return 0;
 613   for (hr=0;hr<HOST_REGS;hr++) {
 614     if(cur->regmap[hr]==reg) {
 615       return cur->constmap[hr];
 616     }
 617   }
 618   printf("Unknown constant in r%d\n",reg);
 619   exit(1);
 620 }
 621
 622 // Least soon needed registers
 623 // Look at the next ten instructions and see which registers
 624 // will be used.  Try not to reallocate these.
 625 void lsn(u_char hsn[], int i, int *preferred_reg)
 626 {
 627   int j;
 628   int b=-1;
 629   for(j=0;j<9;j++)
 630   {
 631     if(i+j>=slen) {
 632       j=slen-i-1;
 633       break;
 634     }
 635     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 636     {
 637       // Don't go past an unconditonal jump
 638       j++;
 639       break;
 640     }
 641   }
 642   for(;j>=0;j--)
 643   {
 644     if(rs1[i+j]) hsn[rs1[i+j]]=j;
 645     if(rs2[i+j]) hsn[rs2[i+j]]=j;
 646     if(rt1[i+j]) hsn[rt1[i+j]]=j;
 647     if(rt2[i+j]) hsn[rt2[i+j]]=j;
 648     if(itype[i+j]==STORE || itype[i+j]==STORELR) {
 649       // Stores can allocate zero
 650       hsn[rs1[i+j]]=j;
 651       hsn[rs2[i+j]]=j;
 652     }
 653     // On some architectures stores need invc_ptr
 654     #if defined(HOST_IMM8)
 655     if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
 656       hsn[INVCP]=j;
 657     }
 658     #endif
 659     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 660     {
 661       hsn[CCREG]=j;
 662       b=j;
 663     }
 664   }
 665   if(b>=0)
 666   {
 667     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 668     {
 669       // Follow first branch
 670       int t=(ba[i+b]-start)>>2;
 671       j=7-b;if(t+j>=slen) j=slen-t-1;
 672       for(;j>=0;j--)
 673       {
 674         if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
 675         if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
 676         //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
 677         //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
 678       }
 679     }
 680     // TODO: preferred register based on backward branch
 681   }
 682   // Delay slot should preferably not overwrite branch conditions or cycle count
 683   if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
 684     if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
 685     if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
 686     hsn[CCREG]=1;
 687     // ...or hash tables
 688     hsn[RHASH]=1;
 689     hsn[RHTBL]=1;
 690   }
 691   // Coprocessor load/store needs FTEMP, even if not declared
 692   if(itype[i]==C1LS||itype[i]==C2LS) {
 693     hsn[FTEMP]=0;
 694   }
 695   // Load L/R also uses FTEMP as a temporary register
 696   if(itype[i]==LOADLR) {
 697     hsn[FTEMP]=0;
 698   }
 699   // Also SWL/SWR/SDL/SDR
 700   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
 701     hsn[FTEMP]=0;
 702   }
 703   // Don't remove the TLB registers either
 704   if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
 705     hsn[TLREG]=0;
 706   }
 707   // Don't remove the miniht registers
 708   if(itype[i]==UJUMP||itype[i]==RJUMP)
 709   {
 710     hsn[RHASH]=0;
 711     hsn[RHTBL]=0;
 712   }
 713 }
 714
 715 // We only want to allocate registers if we're going to use them again soon
 716 int needed_again(int r, int i)
 717 {
 718   int j;
 719   int b=-1;
 720   int rn=10;
 721   int hr;
 722   u_char hsn[MAXREG+1];
 723   int preferred_reg;
 724
 725   memset(hsn,10,sizeof(hsn));
 726   lsn(hsn,i,&preferred_reg);
 727
 728   if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
 729   {
 730     if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
 731       return 0; // Don't need any registers if exiting the block
 732   }
 733   for(j=0;j<9;j++)
 734   {
 735     if(i+j>=slen) {
 736       j=slen-i-1;
 737       break;
 738     }
 739     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 740     {
 741       // Don't go past an unconditonal jump
 742       j++;
 743       break;
 744     }
 745     if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
 746     {
 747       break;
 748     }
 749   }
 750   for(;j>=1;j--)
 751   {
 752     if(rs1[i+j]==r) rn=j;
 753     if(rs2[i+j]==r) rn=j;
 754     if((unneeded_reg[i+j]>>r)&1) rn=10;
 755     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 756     {
 757       b=j;
 758     }
 759   }
 760   /*
 761   if(b>=0)
 762   {
 763     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 764     {
 765       // Follow first branch
 766       int o=rn;
 767       int t=(ba[i+b]-start)>>2;
 768       j=7-b;if(t+j>=slen) j=slen-t-1;
 769       for(;j>=0;j--)
 770       {
 771         if(!((unneeded_reg[t+j]>>r)&1)) {
 772           if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 773           if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 774         }
 775         else rn=o;
 776       }
 777     }
 778   }*/
 779   for(hr=0;hr<HOST_REGS;hr++) {
 780     if(hr!=EXCLUDE_REG) {
 781       if(rn<hsn[hr]) return 1;
 782     }
 783   }
 784   return 0;
 785 }
 786
 787 // Try to match register allocations at the end of a loop with those
 788 // at the beginning
 789 int loop_reg(int i, int r, int hr)
 790 {
 791   int j,k;
 792   for(j=0;j<9;j++)
 793   {
 794     if(i+j>=slen) {
 795       j=slen-i-1;
 796       break;
 797     }
 798     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 799     {
 800       // Don't go past an unconditonal jump
 801       j++;
 802       break;
 803     }
 804   }
 805   k=0;
 806   if(i>0){
 807     if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
 808       k--;
 809   }
 810   for(;k<j;k++)
 811   {
 812     if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
 813     if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
 814     if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
 815     {
 816       if(ba[i+k]>=start && ba[i+k]<(start+i*4))
 817       {
 818         int t=(ba[i+k]-start)>>2;
 819         int reg=get_reg(regs[t].regmap_entry,r);
 820         if(reg>=0) return reg;
 821         //reg=get_reg(regs[t+1].regmap_entry,r);
 822         //if(reg>=0) return reg;
 823       }
 824     }
 825   }
 826   return hr;
 827 }
 828
 829
 830 // Allocate every register, preserving source/target regs
 831 void alloc_all(struct regstat *cur,int i)
 832 {
 833   int hr;
 834
 835   for(hr=0;hr<HOST_REGS;hr++) {
 836     if(hr!=EXCLUDE_REG) {
 837       if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
 838          ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
 839       {
 840         cur->regmap[hr]=-1;
 841         cur->dirty&=~(1<<hr);
 842       }
 843       // Don't need zeros
 844       if((cur->regmap[hr]&63)==0)
 845       {
 846         cur->regmap[hr]=-1;
 847         cur->dirty&=~(1<<hr);
 848       }
 849     }
 850   }
 851 }
 852
 853
 854 void div64(int64_t dividend,int64_t divisor)
 855 {
 856   lo=dividend/divisor;
 857   hi=dividend%divisor;
 858   //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
 859   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 860 }
 861 void divu64(uint64_t dividend,uint64_t divisor)
 862 {
 863   lo=dividend/divisor;
 864   hi=dividend%divisor;
 865   //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 866   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 867 }
 868
 869 void mult64(uint64_t m1,uint64_t m2)
 870 {
 871    unsigned long long int op1, op2, op3, op4;
 872    unsigned long long int result1, result2, result3, result4;
 873    unsigned long long int temp1, temp2, temp3, temp4;
 874    int sign = 0;
 875
 876    if (m1 < 0)
 877      {
 878     op2 = -m1;
 879     sign = 1 - sign;
 880      }
 881    else op2 = m1;
 882    if (m2 < 0)
 883      {
 884     op4 = -m2;
 885     sign = 1 - sign;
 886      }
 887    else op4 = m2;
 888
 889    op1 = op2 & 0xFFFFFFFF;
 890    op2 = (op2 >> 32) & 0xFFFFFFFF;
 891    op3 = op4 & 0xFFFFFFFF;
 892    op4 = (op4 >> 32) & 0xFFFFFFFF;
 893
 894    temp1 = op1 * op3;
 895    temp2 = (temp1 >> 32) + op1 * op4;
 896    temp3 = op2 * op3;
 897    temp4 = (temp3 >> 32) + op2 * op4;
 898
 899    result1 = temp1 & 0xFFFFFFFF;
 900    result2 = temp2 + (temp3 & 0xFFFFFFFF);
 901    result3 = (result2 >> 32) + temp4;
 902    result4 = (result3 >> 32);
 903
 904    lo = result1 | (result2 << 32);
 905    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
 906    if (sign)
 907      {
 908     hi = ~hi;
 909     if (!lo) hi++;
 910     else lo = ~lo + 1;
 911      }
 912 }
 913
 914 void multu64(uint64_t m1,uint64_t m2)
 915 {
 916    unsigned long long int op1, op2, op3, op4;
 917    unsigned long long int result1, result2, result3, result4;
 918    unsigned long long int temp1, temp2, temp3, temp4;
 919
 920    op1 = m1 & 0xFFFFFFFF;
 921    op2 = (m1 >> 32) & 0xFFFFFFFF;
 922    op3 = m2 & 0xFFFFFFFF;
 923    op4 = (m2 >> 32) & 0xFFFFFFFF;
 924
 925    temp1 = op1 * op3;
 926    temp2 = (temp1 >> 32) + op1 * op4;
 927    temp3 = op2 * op3;
 928    temp4 = (temp3 >> 32) + op2 * op4;
 929
 930    result1 = temp1 & 0xFFFFFFFF;
 931    result2 = temp2 + (temp3 & 0xFFFFFFFF);
 932    result3 = (result2 >> 32) + temp4;
 933    result4 = (result3 >> 32);
 934
 935    lo = result1 | (result2 << 32);
 936    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
 937
 938   //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 939   //                                      ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 940 }
 941
 942 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
 943 {
 944   if(bits) {
 945     original<<=64-bits;
 946     original>>=64-bits;
 947     loaded<<=bits;
 948     original|=loaded;
 949   }
 950   else original=loaded;
 951   return original;
 952 }
 953 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
 954 {
 955   if(bits^56) {
 956     original>>=64-(bits^56);
 957     original<<=64-(bits^56);
 958     loaded>>=bits^56;
 959     original|=loaded;
 960   }
 961   else original=loaded;
 962   return original;
 963 }
 964
 965 #ifdef __i386__
 966 #include "assem_x86.c"
 967 #endif
 968 #ifdef __x86_64__
 969 #include "assem_x64.c"
 970 #endif
 971 #ifdef __arm__
 972 #include "assem_arm.c"
 973 #endif
 974
 975 // Add virtual address mapping to linked list
 976 void ll_add(struct ll_entry **head,int vaddr,void *addr)
 977 {
 978   struct ll_entry *new_entry;
 979   new_entry=malloc(sizeof(struct ll_entry));
 980   assert(new_entry!=NULL);
 981   new_entry->vaddr=vaddr;
 982   new_entry->reg32=0;
 983   new_entry->addr=addr;
 984   new_entry->next=*head;
 985   *head=new_entry;
 986 }
 987
 988 // Add virtual address mapping for 32-bit compiled block
 989 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
 990 {
 991   ll_add(head,vaddr,addr);
 992 #ifndef FORCE32
 993   (*head)->reg32=reg32;
 994 #endif
 995 }
 996
 997 // Check if an address is already compiled
 998 // but don't return addresses which are about to expire from the cache
 999 void *check_addr(u_int vaddr)
1000 {
1001   u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
1002   if(ht_bin[0]==vaddr) {
1003     if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1004       if(isclean(ht_bin[1])) return (void *)ht_bin[1];
1005   }
1006   if(ht_bin[2]==vaddr) {
1007     if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1008       if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1009   }
1010   u_int page=get_page(vaddr);
1011   struct ll_entry *head;
1012   head=jump_in[page];
1013   while(head!=NULL) {
1014     if(head->vaddr==vaddr&&head->reg32==0) {
1015       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1016         // Update existing entry with current address
1017         if(ht_bin[0]==vaddr) {
1018           ht_bin[1]=(int)head->addr;
1019           return head->addr;
1020         }
1021         if(ht_bin[2]==vaddr) {
1022           ht_bin[3]=(int)head->addr;
1023           return head->addr;
1024         }
1025         // Insert into hash table with low priority.
1026         // Don't evict existing entries, as they are probably
1027         // addresses that are being accessed frequently.
1028         if(ht_bin[0]==-1) {
1029           ht_bin[1]=(int)head->addr;
1030           ht_bin[0]=vaddr;
1031         }else if(ht_bin[2]==-1) {
1032           ht_bin[3]=(int)head->addr;
1033           ht_bin[2]=vaddr;
1034         }
1035         return head->addr;
1036       }
1037     }
1038     head=head->next;
1039   }
1040   return 0;
1041 }
1042
1043 void remove_hash(int vaddr)
1044 {
1045   //printf("remove hash: %x\n",vaddr);
1046   int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1047   if(ht_bin[2]==vaddr) {
1048     ht_bin[2]=ht_bin[3]=-1;
1049   }
1050   if(ht_bin[0]==vaddr) {
1051     ht_bin[0]=ht_bin[2];
1052     ht_bin[1]=ht_bin[3];
1053     ht_bin[2]=ht_bin[3]=-1;
1054   }
1055 }
1056
1057 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1058 {
1059   struct ll_entry *next;
1060   while(*head) {
1061     if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1062        ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1063     {
1064       inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1065       remove_hash((*head)->vaddr);
1066       next=(*head)->next;
1067       free(*head);
1068       *head=next;
1069     }
1070     else
1071     {
1072       head=&((*head)->next);
1073     }
1074   }
1075 }
1076
1077 // Remove all entries from linked list
1078 void ll_clear(struct ll_entry **head)
1079 {
1080   struct ll_entry *cur;
1081   struct ll_entry *next;
1082   if(cur=*head) {
1083     *head=0;
1084     while(cur) {
1085       next=cur->next;
1086       free(cur);
1087       cur=next;
1088     }
1089   }
1090 }
1091
1092 // Dereference the pointers and remove if it matches
1093 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1094 {
1095   while(head) {
1096     int ptr=get_pointer(head->addr);
1097     inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1098     if(((ptr>>shift)==(addr>>shift)) ||
1099        (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1100     {
1101       inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1102       u_int host_addr=(u_int)kill_pointer(head->addr);
1103       #ifdef __arm__
1104         needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1105       #endif
1106     }
1107     head=head->next;
1108   }
1109 }
1110
1111 // This is called when we write to a compiled block (see do_invstub)
1112 void invalidate_page(u_int page)
1113 {
1114   struct ll_entry *head;
1115   struct ll_entry *next;
1116   head=jump_in[page];
1117   jump_in[page]=0;
1118   while(head!=NULL) {
1119     inv_debug("INVALIDATE: %x\n",head->vaddr);
1120     remove_hash(head->vaddr);
1121     next=head->next;
1122     free(head);
1123     head=next;
1124   }
1125   head=jump_out[page];
1126   jump_out[page]=0;
1127   while(head!=NULL) {
1128     inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1129     u_int host_addr=(u_int)kill_pointer(head->addr);
1130     #ifdef __arm__
1131       needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1132     #endif
1133     next=head->next;
1134     free(head);
1135     head=next;
1136   }
1137 }
1138 void invalidate_block(u_int block)
1139 {
1140   u_int page=get_page(block<<12);
1141   u_int vpage=get_vpage(block<<12);
1142   inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1143   //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1144   u_int first,last;
1145   first=last=page;
1146   struct ll_entry *head;
1147   head=jump_dirty[vpage];
1148   //printf("page=%d vpage=%d\n",page,vpage);
1149   while(head!=NULL) {
1150     u_int start,end;
1151     if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1152       get_bounds((int)head->addr,&start,&end);
1153       //printf("start: %x end: %x\n",start,end);
1154       if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
1155         if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1156           if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1157           if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1158         }
1159       }
1160 #ifndef DISABLE_TLB
1161       if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1162         if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1163           if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1164           if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1165         }
1166       }
1167 #endif
1168     }
1169     head=head->next;
1170   }
1171   //printf("first=%d last=%d\n",first,last);
1172   invalidate_page(page);
1173   assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1174   assert(last<page+5);
1175   // Invalidate the adjacent pages if a block crosses a 4K boundary
1176   while(first<page) {
1177     invalidate_page(first);
1178     first++;
1179   }
1180   for(first=page+1;first<last;first++) {
1181     invalidate_page(first);
1182   }
1183   #ifdef __arm__
1184     do_clear_cache();
1185   #endif
1186
1187   // Don't trap writes
1188   invalid_code[block]=1;
1189 #ifdef PCSX
1190   invalid_code[((u_int)0x80000000>>12)|page]=1;
1191 #endif
1192 #ifndef DISABLE_TLB
1193   // If there is a valid TLB entry for this page, remove write protect
1194   if(tlb_LUT_w[block]) {
1195     assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1196     // CHECK: Is this right?
1197     memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1198     u_int real_block=tlb_LUT_w[block]>>12;
1199     invalid_code[real_block]=1;
1200     if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1201   }
1202   else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1203 #endif
1204
1205   #ifdef USE_MINI_HT
1206   memset(mini_ht,-1,sizeof(mini_ht));
1207   #endif
1208 }
1209 void invalidate_addr(u_int addr)
1210 {
1211   invalidate_block(addr>>12);
1212 }
1213 // This is called when loading a save state.
1214 // Anything could have changed, so invalidate everything.
1215 void invalidate_all_pages()
1216 {
1217   u_int page,n;
1218   for(page=0;page<4096;page++)
1219     invalidate_page(page);
1220   for(page=0;page<1048576;page++)
1221     if(!invalid_code[page]) {
1222       restore_candidate[(page&2047)>>3]|=1<<(page&7);
1223       restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1224     }
1225   #ifdef __arm__
1226   __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1227   #endif
1228   #ifdef USE_MINI_HT
1229   memset(mini_ht,-1,sizeof(mini_ht));
1230   #endif
1231   #ifndef DISABLE_TLB
1232   // TLB
1233   for(page=0;page<0x100000;page++) {
1234     if(tlb_LUT_r[page]) {
1235       memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1236       if(!tlb_LUT_w[page]||!invalid_code[page])
1237         memory_map[page]|=0x40000000; // Write protect
1238     }
1239     else memory_map[page]=-1;
1240     if(page==0x80000) page=0xC0000;
1241   }
1242   tlb_hacks();
1243   #endif
1244 }
1245
1246 // Add an entry to jump_out after making a link
1247 void add_link(u_int vaddr,void *src)
1248 {
1249   u_int page=get_page(vaddr);
1250   inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1251   ll_add(jump_out+page,vaddr,src);
1252   //int ptr=get_pointer(src);
1253   //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1254 }
1255
1256 // If a code block was found to be unmodified (bit was set in
1257 // restore_candidate) and it remains unmodified (bit is clear
1258 // in invalid_code) then move the entries for that 4K page from
1259 // the dirty list to the clean list.
1260 void clean_blocks(u_int page)
1261 {
1262   struct ll_entry *head;
1263   inv_debug("INV: clean_blocks page=%d\n",page);
1264   head=jump_dirty[page];
1265   while(head!=NULL) {
1266     if(!invalid_code[head->vaddr>>12]) {
1267       // Don't restore blocks which are about to expire from the cache
1268       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1269         u_int start,end;
1270         if(verify_dirty((int)head->addr)) {
1271           //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1272           u_int i;
1273           u_int inv=0;
1274           get_bounds((int)head->addr,&start,&end);
1275           if(start-(u_int)rdram<RAM_SIZE) {
1276             for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1277               inv|=invalid_code[i];
1278             }
1279           }
1280           if((signed int)head->vaddr>=(signed int)0xC0000000) {
1281             u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1282             //printf("addr=%x start=%x end=%x\n",addr,start,end);
1283             if(addr<start||addr>=end) inv=1;
1284           }
1285           else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1286             inv=1;
1287           }
1288           if(!inv) {
1289             void * clean_addr=(void *)get_clean_addr((int)head->addr);
1290             if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1291               u_int ppage=page;
1292 #ifndef DISABLE_TLB
1293               if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1294 #endif
1295               inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1296               //printf("page=%x, addr=%x\n",page,head->vaddr);
1297               //assert(head->vaddr>>12==(page|0x80000));
1298               ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1299               int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1300               if(!head->reg32) {
1301                 if(ht_bin[0]==head->vaddr) {
1302                   ht_bin[1]=(int)clean_addr; // Replace existing entry
1303                 }
1304                 if(ht_bin[2]==head->vaddr) {
1305                   ht_bin[3]=(int)clean_addr; // Replace existing entry
1306                 }
1307               }
1308             }
1309           }
1310         }
1311       }
1312     }
1313     head=head->next;
1314   }
1315 }
1316
1317
1318 void mov_alloc(struct regstat *current,int i)
1319 {
1320   // Note: Don't need to actually alloc the source registers
1321   if((~current->is32>>rs1[i])&1) {
1322     //alloc_reg64(current,i,rs1[i]);
1323     alloc_reg64(current,i,rt1[i]);
1324     current->is32&=~(1LL<<rt1[i]);
1325   } else {
1326     //alloc_reg(current,i,rs1[i]);
1327     alloc_reg(current,i,rt1[i]);
1328     current->is32|=(1LL<<rt1[i]);
1329   }
1330   clear_const(current,rs1[i]);
1331   clear_const(current,rt1[i]);
1332   dirty_reg(current,rt1[i]);
1333 }
1334
1335 void shiftimm_alloc(struct regstat *current,int i)
1336 {
1337   clear_const(current,rs1[i]);
1338   clear_const(current,rt1[i]);
1339   if(opcode2[i]<=0x3) // SLL/SRL/SRA
1340   {
1341     if(rt1[i]) {
1342       if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1343       else lt1[i]=rs1[i];
1344       alloc_reg(current,i,rt1[i]);
1345       current->is32|=1LL<<rt1[i];
1346       dirty_reg(current,rt1[i]);
1347     }
1348   }
1349   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1350   {
1351     if(rt1[i]) {
1352       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1353       alloc_reg64(current,i,rt1[i]);
1354       current->is32&=~(1LL<<rt1[i]);
1355       dirty_reg(current,rt1[i]);
1356     }
1357   }
1358   if(opcode2[i]==0x3c) // DSLL32
1359   {
1360     if(rt1[i]) {
1361       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1362       alloc_reg64(current,i,rt1[i]);
1363       current->is32&=~(1LL<<rt1[i]);
1364       dirty_reg(current,rt1[i]);
1365     }
1366   }
1367   if(opcode2[i]==0x3e) // DSRL32
1368   {
1369     if(rt1[i]) {
1370       alloc_reg64(current,i,rs1[i]);
1371       if(imm[i]==32) {
1372         alloc_reg64(current,i,rt1[i]);
1373         current->is32&=~(1LL<<rt1[i]);
1374       } else {
1375         alloc_reg(current,i,rt1[i]);
1376         current->is32|=1LL<<rt1[i];
1377       }
1378       dirty_reg(current,rt1[i]);
1379     }
1380   }
1381   if(opcode2[i]==0x3f) // DSRA32
1382   {
1383     if(rt1[i]) {
1384       alloc_reg64(current,i,rs1[i]);
1385       alloc_reg(current,i,rt1[i]);
1386       current->is32|=1LL<<rt1[i];
1387       dirty_reg(current,rt1[i]);
1388     }
1389   }
1390 }
1391
1392 void shift_alloc(struct regstat *current,int i)
1393 {
1394   if(rt1[i]) {
1395     if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1396     {
1397       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1398       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1399       alloc_reg(current,i,rt1[i]);
1400       if(rt1[i]==rs2[i]) {
1401         alloc_reg_temp(current,i,-1);
1402         minimum_free_regs[i]=1;
1403       }
1404       current->is32|=1LL<<rt1[i];
1405     } else { // DSLLV/DSRLV/DSRAV
1406       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1407       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1408       alloc_reg64(current,i,rt1[i]);
1409       current->is32&=~(1LL<<rt1[i]);
1410       if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1411       {
1412         alloc_reg_temp(current,i,-1);
1413         minimum_free_regs[i]=1;
1414       }
1415     }
1416     clear_const(current,rs1[i]);
1417     clear_const(current,rs2[i]);
1418     clear_const(current,rt1[i]);
1419     dirty_reg(current,rt1[i]);
1420   }
1421 }
1422
1423 void alu_alloc(struct regstat *current,int i)
1424 {
1425   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1426     if(rt1[i]) {
1427       if(rs1[i]&&rs2[i]) {
1428         alloc_reg(current,i,rs1[i]);
1429         alloc_reg(current,i,rs2[i]);
1430       }
1431       else {
1432         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1433         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1434       }
1435       alloc_reg(current,i,rt1[i]);
1436     }
1437     current->is32|=1LL<<rt1[i];
1438   }
1439   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1440     if(rt1[i]) {
1441       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1442       {
1443         alloc_reg64(current,i,rs1[i]);
1444         alloc_reg64(current,i,rs2[i]);
1445         alloc_reg(current,i,rt1[i]);
1446       } else {
1447         alloc_reg(current,i,rs1[i]);
1448         alloc_reg(current,i,rs2[i]);
1449         alloc_reg(current,i,rt1[i]);
1450       }
1451     }
1452     current->is32|=1LL<<rt1[i];
1453   }
1454   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1455     if(rt1[i]) {
1456       if(rs1[i]&&rs2[i]) {
1457         alloc_reg(current,i,rs1[i]);
1458         alloc_reg(current,i,rs2[i]);
1459       }
1460       else
1461       {
1462         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1463         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1464       }
1465       alloc_reg(current,i,rt1[i]);
1466       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1467       {
1468         if(!((current->uu>>rt1[i])&1)) {
1469           alloc_reg64(current,i,rt1[i]);
1470         }
1471         if(get_reg(current->regmap,rt1[i]|64)>=0) {
1472           if(rs1[i]&&rs2[i]) {
1473             alloc_reg64(current,i,rs1[i]);
1474             alloc_reg64(current,i,rs2[i]);
1475           }
1476           else
1477           {
1478             // Is is really worth it to keep 64-bit values in registers?
1479             #ifdef NATIVE_64BIT
1480             if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1481             if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1482             #endif
1483           }
1484         }
1485         current->is32&=~(1LL<<rt1[i]);
1486       } else {
1487         current->is32|=1LL<<rt1[i];
1488       }
1489     }
1490   }
1491   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1492     if(rt1[i]) {
1493       if(rs1[i]&&rs2[i]) {
1494         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1495           alloc_reg64(current,i,rs1[i]);
1496           alloc_reg64(current,i,rs2[i]);
1497           alloc_reg64(current,i,rt1[i]);
1498         } else {
1499           alloc_reg(current,i,rs1[i]);
1500           alloc_reg(current,i,rs2[i]);
1501           alloc_reg(current,i,rt1[i]);
1502         }
1503       }
1504       else {
1505         alloc_reg(current,i,rt1[i]);
1506         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1507           // DADD used as move, or zeroing
1508           // If we have a 64-bit source, then make the target 64 bits too
1509           if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1510             if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1511             alloc_reg64(current,i,rt1[i]);
1512           } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1513             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1514             alloc_reg64(current,i,rt1[i]);
1515           }
1516           if(opcode2[i]>=0x2e&&rs2[i]) {
1517             // DSUB used as negation - 64-bit result
1518             // If we have a 32-bit register, extend it to 64 bits
1519             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1520             alloc_reg64(current,i,rt1[i]);
1521           }
1522         }
1523       }
1524       if(rs1[i]&&rs2[i]) {
1525         current->is32&=~(1LL<<rt1[i]);
1526       } else if(rs1[i]) {
1527         current->is32&=~(1LL<<rt1[i]);
1528         if((current->is32>>rs1[i])&1)
1529           current->is32|=1LL<<rt1[i];
1530       } else if(rs2[i]) {
1531         current->is32&=~(1LL<<rt1[i]);
1532         if((current->is32>>rs2[i])&1)
1533           current->is32|=1LL<<rt1[i];
1534       } else {
1535         current->is32|=1LL<<rt1[i];
1536       }
1537     }
1538   }
1539   clear_const(current,rs1[i]);
1540   clear_const(current,rs2[i]);
1541   clear_const(current,rt1[i]);
1542   dirty_reg(current,rt1[i]);
1543 }
1544
1545 void imm16_alloc(struct regstat *current,int i)
1546 {
1547   if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1548   else lt1[i]=rs1[i];
1549   if(rt1[i]) alloc_reg(current,i,rt1[i]);
1550   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1551     current->is32&=~(1LL<<rt1[i]);
1552     if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1553       // TODO: Could preserve the 32-bit flag if the immediate is zero
1554       alloc_reg64(current,i,rt1[i]);
1555       alloc_reg64(current,i,rs1[i]);
1556     }
1557     clear_const(current,rs1[i]);
1558     clear_const(current,rt1[i]);
1559   }
1560   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1561     if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1562     current->is32|=1LL<<rt1[i];
1563     clear_const(current,rs1[i]);
1564     clear_const(current,rt1[i]);
1565   }
1566   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1567     if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1568       if(rs1[i]!=rt1[i]) {
1569         if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1570         alloc_reg64(current,i,rt1[i]);
1571         current->is32&=~(1LL<<rt1[i]);
1572       }
1573     }
1574     else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1575     if(is_const(current,rs1[i])) {
1576       int v=get_const(current,rs1[i]);
1577       if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1578       if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1579       if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1580     }
1581     else clear_const(current,rt1[i]);
1582   }
1583   else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1584     if(is_const(current,rs1[i])) {
1585       int v=get_const(current,rs1[i]);
1586       set_const(current,rt1[i],v+imm[i]);
1587     }
1588     else clear_const(current,rt1[i]);
1589     current->is32|=1LL<<rt1[i];
1590   }
1591   else {
1592     set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1593     current->is32|=1LL<<rt1[i];
1594   }
1595   dirty_reg(current,rt1[i]);
1596 }
1597
1598 void load_alloc(struct regstat *current,int i)
1599 {
1600   clear_const(current,rt1[i]);
1601   //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1602   if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1603   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1604   if(rt1[i]) {
1605     alloc_reg(current,i,rt1[i]);
1606     if(get_reg(current->regmap,rt1[i])<0) {
1607       // dummy load, but we still need a register to calculate the address
1608       alloc_reg_temp(current,i,-1);
1609       minimum_free_regs[i]=1;
1610     }
1611     if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1612     {
1613       current->is32&=~(1LL<<rt1[i]);
1614       alloc_reg64(current,i,rt1[i]);
1615     }
1616     else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1617     {
1618       current->is32&=~(1LL<<rt1[i]);
1619       alloc_reg64(current,i,rt1[i]);
1620       alloc_all(current,i);
1621       alloc_reg64(current,i,FTEMP);
1622       minimum_free_regs[i]=HOST_REGS;
1623     }
1624     else current->is32|=1LL<<rt1[i];
1625     dirty_reg(current,rt1[i]);
1626     // If using TLB, need a register for pointer to the mapping table
1627     if(using_tlb) alloc_reg(current,i,TLREG);
1628     // LWL/LWR need a temporary register for the old value
1629     if(opcode[i]==0x22||opcode[i]==0x26)
1630     {
1631       alloc_reg(current,i,FTEMP);
1632       alloc_reg_temp(current,i,-1);
1633       minimum_free_regs[i]=1;
1634     }
1635   }
1636   else
1637   {
1638     // Load to r0 (dummy load)
1639     // but we still need a register to calculate the address
1640     if(opcode[i]==0x22||opcode[i]==0x26)
1641     {
1642       alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1643     }
1644     alloc_reg_temp(current,i,-1);
1645     minimum_free_regs[i]=1;
1646     if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1647     {
1648       alloc_all(current,i);
1649       alloc_reg64(current,i,FTEMP);
1650       minimum_free_regs[i]=HOST_REGS;
1651     }
1652   }
1653 }
1654
1655 void store_alloc(struct regstat *current,int i)
1656 {
1657   clear_const(current,rs2[i]);
1658   if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1659   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1660   alloc_reg(current,i,rs2[i]);
1661   if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1662     alloc_reg64(current,i,rs2[i]);
1663     if(rs2[i]) alloc_reg(current,i,FTEMP);
1664   }
1665   // If using TLB, need a register for pointer to the mapping table
1666   if(using_tlb) alloc_reg(current,i,TLREG);
1667   #if defined(HOST_IMM8)
1668   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1669   else alloc_reg(current,i,INVCP);
1670   #endif
1671   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1672     alloc_reg(current,i,FTEMP);
1673   }
1674   // We need a temporary register for address generation
1675   alloc_reg_temp(current,i,-1);
1676   minimum_free_regs[i]=1;
1677 }
1678
1679 void c1ls_alloc(struct regstat *current,int i)
1680 {
1681   //clear_const(current,rs1[i]); // FIXME
1682   clear_const(current,rt1[i]);
1683   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1684   alloc_reg(current,i,CSREG); // Status
1685   alloc_reg(current,i,FTEMP);
1686   if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1687     alloc_reg64(current,i,FTEMP);
1688   }
1689   // If using TLB, need a register for pointer to the mapping table
1690   if(using_tlb) alloc_reg(current,i,TLREG);
1691   #if defined(HOST_IMM8)
1692   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1693   else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1694     alloc_reg(current,i,INVCP);
1695   #endif
1696   // We need a temporary register for address generation
1697   alloc_reg_temp(current,i,-1);
1698 }
1699
1700 void c2ls_alloc(struct regstat *current,int i)
1701 {
1702   clear_const(current,rt1[i]);
1703   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1704   alloc_reg(current,i,FTEMP);
1705   // If using TLB, need a register for pointer to the mapping table
1706   if(using_tlb) alloc_reg(current,i,TLREG);
1707   #if defined(HOST_IMM8)
1708   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1709   else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1710     alloc_reg(current,i,INVCP);
1711   #endif
1712   // We need a temporary register for address generation
1713   alloc_reg_temp(current,i,-1);
1714   minimum_free_regs[i]=1;
1715 }
1716
1717 #ifndef multdiv_alloc
1718 void multdiv_alloc(struct regstat *current,int i)
1719 {
1720   //  case 0x18: MULT
1721   //  case 0x19: MULTU
1722   //  case 0x1A: DIV
1723   //  case 0x1B: DIVU
1724   //  case 0x1C: DMULT
1725   //  case 0x1D: DMULTU
1726   //  case 0x1E: DDIV
1727   //  case 0x1F: DDIVU
1728   clear_const(current,rs1[i]);
1729   clear_const(current,rs2[i]);
1730   if(rs1[i]&&rs2[i])
1731   {
1732     if((opcode2[i]&4)==0) // 32-bit
1733     {
1734       current->u&=~(1LL<<HIREG);
1735       current->u&=~(1LL<<LOREG);
1736       alloc_reg(current,i,HIREG);
1737       alloc_reg(current,i,LOREG);
1738       alloc_reg(current,i,rs1[i]);
1739       alloc_reg(current,i,rs2[i]);
1740       current->is32|=1LL<<HIREG;
1741       current->is32|=1LL<<LOREG;
1742       dirty_reg(current,HIREG);
1743       dirty_reg(current,LOREG);
1744     }
1745     else // 64-bit
1746     {
1747       current->u&=~(1LL<<HIREG);
1748       current->u&=~(1LL<<LOREG);
1749       current->uu&=~(1LL<<HIREG);
1750       current->uu&=~(1LL<<LOREG);
1751       alloc_reg64(current,i,HIREG);
1752       //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1753       alloc_reg64(current,i,rs1[i]);
1754       alloc_reg64(current,i,rs2[i]);
1755       alloc_all(current,i);
1756       current->is32&=~(1LL<<HIREG);
1757       current->is32&=~(1LL<<LOREG);
1758       dirty_reg(current,HIREG);
1759       dirty_reg(current,LOREG);
1760       minimum_free_regs[i]=HOST_REGS;
1761     }
1762   }
1763   else
1764   {
1765     // Multiply by zero is zero.
1766     // MIPS does not have a divide by zero exception.
1767     // The result is undefined, we return zero.
1768     alloc_reg(current,i,HIREG);
1769     alloc_reg(current,i,LOREG);
1770     current->is32|=1LL<<HIREG;
1771     current->is32|=1LL<<LOREG;
1772     dirty_reg(current,HIREG);
1773     dirty_reg(current,LOREG);
1774   }
1775 }
1776 #endif
1777
1778 void cop0_alloc(struct regstat *current,int i)
1779 {
1780   if(opcode2[i]==0) // MFC0
1781   {
1782     if(rt1[i]) {
1783       clear_const(current,rt1[i]);
1784       alloc_all(current,i);
1785       alloc_reg(current,i,rt1[i]);
1786       current->is32|=1LL<<rt1[i];
1787       dirty_reg(current,rt1[i]);
1788     }
1789   }
1790   else if(opcode2[i]==4) // MTC0
1791   {
1792     if(rs1[i]){
1793       clear_const(current,rs1[i]);
1794       alloc_reg(current,i,rs1[i]);
1795       alloc_all(current,i);
1796     }
1797     else {
1798       alloc_all(current,i); // FIXME: Keep r0
1799       current->u&=~1LL;
1800       alloc_reg(current,i,0);
1801     }
1802   }
1803   else
1804   {
1805     // TLBR/TLBWI/TLBWR/TLBP/ERET
1806     assert(opcode2[i]==0x10);
1807     alloc_all(current,i);
1808   }
1809   minimum_free_regs[i]=HOST_REGS;
1810 }
1811
1812 void cop1_alloc(struct regstat *current,int i)
1813 {
1814   alloc_reg(current,i,CSREG); // Load status
1815   if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1816   {
1817     if(rt1[i]){
1818       clear_const(current,rt1[i]);
1819       if(opcode2[i]==1) {
1820         alloc_reg64(current,i,rt1[i]); // DMFC1
1821         current->is32&=~(1LL<<rt1[i]);
1822       }else{
1823         alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1824         current->is32|=1LL<<rt1[i];
1825       }
1826       dirty_reg(current,rt1[i]);
1827     }
1828     alloc_reg_temp(current,i,-1);
1829   }
1830   else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1831   {
1832     if(rs1[i]){
1833       clear_const(current,rs1[i]);
1834       if(opcode2[i]==5)
1835         alloc_reg64(current,i,rs1[i]); // DMTC1
1836       else
1837         alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1838       alloc_reg_temp(current,i,-1);
1839     }
1840     else {
1841       current->u&=~1LL;
1842       alloc_reg(current,i,0);
1843       alloc_reg_temp(current,i,-1);
1844     }
1845   }
1846   minimum_free_regs[i]=1;
1847 }
1848 void fconv_alloc(struct regstat *current,int i)
1849 {
1850   alloc_reg(current,i,CSREG); // Load status
1851   alloc_reg_temp(current,i,-1);
1852   minimum_free_regs[i]=1;
1853 }
1854 void float_alloc(struct regstat *current,int i)
1855 {
1856   alloc_reg(current,i,CSREG); // Load status
1857   alloc_reg_temp(current,i,-1);
1858   minimum_free_regs[i]=1;
1859 }
1860 void c2op_alloc(struct regstat *current,int i)
1861 {
1862   alloc_reg_temp(current,i,-1);
1863 }
1864 void fcomp_alloc(struct regstat *current,int i)
1865 {
1866   alloc_reg(current,i,CSREG); // Load status
1867   alloc_reg(current,i,FSREG); // Load flags
1868   dirty_reg(current,FSREG); // Flag will be modified
1869   alloc_reg_temp(current,i,-1);
1870   minimum_free_regs[i]=1;
1871 }
1872
1873 void syscall_alloc(struct regstat *current,int i)
1874 {
1875   alloc_cc(current,i);
1876   dirty_reg(current,CCREG);
1877   alloc_all(current,i);
1878   minimum_free_regs[i]=HOST_REGS;
1879   current->isconst=0;
1880 }
1881
1882 void delayslot_alloc(struct regstat *current,int i)
1883 {
1884   switch(itype[i]) {
1885     case UJUMP:
1886     case CJUMP:
1887     case SJUMP:
1888     case RJUMP:
1889     case FJUMP:
1890     case SYSCALL:
1891     case HLECALL:
1892     case SPAN:
1893       assem_debug("jump in the delay slot.  this shouldn't happen.\n");//exit(1);
1894       printf("Disabled speculative precompilation\n");
1895       stop_after_jal=1;
1896       break;
1897     case IMM16:
1898       imm16_alloc(current,i);
1899       break;
1900     case LOAD:
1901     case LOADLR:
1902       load_alloc(current,i);
1903       break;
1904     case STORE:
1905     case STORELR:
1906       store_alloc(current,i);
1907       break;
1908     case ALU:
1909       alu_alloc(current,i);
1910       break;
1911     case SHIFT:
1912       shift_alloc(current,i);
1913       break;
1914     case MULTDIV:
1915       multdiv_alloc(current,i);
1916       break;
1917     case SHIFTIMM:
1918       shiftimm_alloc(current,i);
1919       break;
1920     case MOV:
1921       mov_alloc(current,i);
1922       break;
1923     case COP0:
1924       cop0_alloc(current,i);
1925       break;
1926     case COP1:
1927     case COP2:
1928       cop1_alloc(current,i);
1929       break;
1930     case C1LS:
1931       c1ls_alloc(current,i);
1932       break;
1933     case C2LS:
1934       c2ls_alloc(current,i);
1935       break;
1936     case FCONV:
1937       fconv_alloc(current,i);
1938       break;
1939     case FLOAT:
1940       float_alloc(current,i);
1941       break;
1942     case FCOMP:
1943       fcomp_alloc(current,i);
1944       break;
1945     case C2OP:
1946       c2op_alloc(current,i);
1947       break;
1948   }
1949 }
1950
1951 // Special case where a branch and delay slot span two pages in virtual memory
1952 static void pagespan_alloc(struct regstat *current,int i)
1953 {
1954   current->isconst=0;
1955   current->wasconst=0;
1956   regs[i].wasconst=0;
1957   minimum_free_regs[i]=HOST_REGS;
1958   alloc_all(current,i);
1959   alloc_cc(current,i);
1960   dirty_reg(current,CCREG);
1961   if(opcode[i]==3) // JAL
1962   {
1963     alloc_reg(current,i,31);
1964     dirty_reg(current,31);
1965   }
1966   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1967   {
1968     alloc_reg(current,i,rs1[i]);
1969     if (rt1[i]!=0) {
1970       alloc_reg(current,i,rt1[i]);
1971       dirty_reg(current,rt1[i]);
1972     }
1973   }
1974   if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1975   {
1976     if(rs1[i]) alloc_reg(current,i,rs1[i]);
1977     if(rs2[i]) alloc_reg(current,i,rs2[i]);
1978     if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1979     {
1980       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1981       if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1982     }
1983   }
1984   else
1985   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1986   {
1987     if(rs1[i]) alloc_reg(current,i,rs1[i]);
1988     if(!((current->is32>>rs1[i])&1))
1989     {
1990       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1991     }
1992   }
1993   else
1994   if(opcode[i]==0x11) // BC1
1995   {
1996     alloc_reg(current,i,FSREG);
1997     alloc_reg(current,i,CSREG);
1998   }
1999   //else ...
2000 }
2001
2002 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
2003 {
2004   stubs[stubcount][0]=type;
2005   stubs[stubcount][1]=addr;
2006   stubs[stubcount][2]=retaddr;
2007   stubs[stubcount][3]=a;
2008   stubs[stubcount][4]=b;
2009   stubs[stubcount][5]=c;
2010   stubs[stubcount][6]=d;
2011   stubs[stubcount][7]=e;
2012   stubcount++;
2013 }
2014
2015 // Write out a single register
2016 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2017 {
2018   int hr;
2019   for(hr=0;hr<HOST_REGS;hr++) {
2020     if(hr!=EXCLUDE_REG) {
2021       if((regmap[hr]&63)==r) {
2022         if((dirty>>hr)&1) {
2023           if(regmap[hr]<64) {
2024             emit_storereg(r,hr);
2025 #ifndef FORCE32
2026             if((is32>>regmap[hr])&1) {
2027               emit_sarimm(hr,31,hr);
2028               emit_storereg(r|64,hr);
2029             }
2030 #endif
2031           }else{
2032             emit_storereg(r|64,hr);
2033           }
2034         }
2035       }
2036     }
2037   }
2038 }
2039
2040 int mchecksum()
2041 {
2042   //if(!tracedebug) return 0;
2043   int i;
2044   int sum=0;
2045   for(i=0;i<2097152;i++) {
2046     unsigned int temp=sum;
2047     sum<<=1;
2048     sum|=(~temp)>>31;
2049     sum^=((u_int *)rdram)[i];
2050   }
2051   return sum;
2052 }
2053 int rchecksum()
2054 {
2055   int i;
2056   int sum=0;
2057   for(i=0;i<64;i++)
2058     sum^=((u_int *)reg)[i];
2059   return sum;
2060 }
2061 void rlist()
2062 {
2063   int i;
2064   printf("TRACE: ");
2065   for(i=0;i<32;i++)
2066     printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2067   printf("\n");
2068 #ifndef DISABLE_COP1
2069   printf("TRACE: ");
2070   for(i=0;i<32;i++)
2071     printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2072   printf("\n");
2073 #endif
2074 }
2075
2076 void enabletrace()
2077 {
2078   tracedebug=1;
2079 }
2080
2081 void memdebug(int i)
2082 {
2083   //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2084   //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2085   //rlist();
2086   //if(tracedebug) {
2087   //if(Count>=-2084597794) {
2088   if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2089   //if(0) {
2090     printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2091     //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2092     //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2093     rlist();
2094     #ifdef __i386__
2095     printf("TRACE: %x\n",(&i)[-1]);
2096     #endif
2097     #ifdef __arm__
2098     int j;
2099     printf("TRACE: %x \n",(&j)[10]);
2100     printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2101     #endif
2102     //fflush(stdout);
2103   }
2104   //printf("TRACE: %x\n",(&i)[-1]);
2105 }
2106
2107 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2108 {
2109   printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2110 }
2111
2112 void alu_assemble(int i,struct regstat *i_regs)
2113 {
2114   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2115     if(rt1[i]) {
2116       signed char s1,s2,t;
2117       t=get_reg(i_regs->regmap,rt1[i]);
2118       if(t>=0) {
2119         s1=get_reg(i_regs->regmap,rs1[i]);
2120         s2=get_reg(i_regs->regmap,rs2[i]);
2121         if(rs1[i]&&rs2[i]) {
2122           assert(s1>=0);
2123           assert(s2>=0);
2124           if(opcode2[i]&2) emit_sub(s1,s2,t);
2125           else emit_add(s1,s2,t);
2126         }
2127         else if(rs1[i]) {
2128           if(s1>=0) emit_mov(s1,t);
2129           else emit_loadreg(rs1[i],t);
2130         }
2131         else if(rs2[i]) {
2132           if(s2>=0) {
2133             if(opcode2[i]&2) emit_neg(s2,t);
2134             else emit_mov(s2,t);
2135           }
2136           else {
2137             emit_loadreg(rs2[i],t);
2138             if(opcode2[i]&2) emit_neg(t,t);
2139           }
2140         }
2141         else emit_zeroreg(t);
2142       }
2143     }
2144   }
2145   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2146     if(rt1[i]) {
2147       signed char s1l,s2l,s1h,s2h,tl,th;
2148       tl=get_reg(i_regs->regmap,rt1[i]);
2149       th=get_reg(i_regs->regmap,rt1[i]|64);
2150       if(tl>=0) {
2151         s1l=get_reg(i_regs->regmap,rs1[i]);
2152         s2l=get_reg(i_regs->regmap,rs2[i]);
2153         s1h=get_reg(i_regs->regmap,rs1[i]|64);
2154         s2h=get_reg(i_regs->regmap,rs2[i]|64);
2155         if(rs1[i]&&rs2[i]) {
2156           assert(s1l>=0);
2157           assert(s2l>=0);
2158           if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2159           else emit_adds(s1l,s2l,tl);
2160           if(th>=0) {
2161             #ifdef INVERTED_CARRY
2162             if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2163             #else
2164             if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2165             #endif
2166             else emit_add(s1h,s2h,th);
2167           }
2168         }
2169         else if(rs1[i]) {
2170           if(s1l>=0) emit_mov(s1l,tl);
2171           else emit_loadreg(rs1[i],tl);
2172           if(th>=0) {
2173             if(s1h>=0) emit_mov(s1h,th);
2174             else emit_loadreg(rs1[i]|64,th);
2175           }
2176         }
2177         else if(rs2[i]) {
2178           if(s2l>=0) {
2179             if(opcode2[i]&2) emit_negs(s2l,tl);
2180             else emit_mov(s2l,tl);
2181           }
2182           else {
2183             emit_loadreg(rs2[i],tl);
2184             if(opcode2[i]&2) emit_negs(tl,tl);
2185           }
2186           if(th>=0) {
2187             #ifdef INVERTED_CARRY
2188             if(s2h>=0) emit_mov(s2h,th);
2189             else emit_loadreg(rs2[i]|64,th);
2190             if(opcode2[i]&2) {
2191               emit_adcimm(-1,th); // x86 has inverted carry flag
2192               emit_not(th,th);
2193             }
2194             #else
2195             if(opcode2[i]&2) {
2196               if(s2h>=0) emit_rscimm(s2h,0,th);
2197               else {
2198                 emit_loadreg(rs2[i]|64,th);
2199                 emit_rscimm(th,0,th);
2200               }
2201             }else{
2202               if(s2h>=0) emit_mov(s2h,th);
2203               else emit_loadreg(rs2[i]|64,th);
2204             }
2205             #endif
2206           }
2207         }
2208         else {
2209           emit_zeroreg(tl);
2210           if(th>=0) emit_zeroreg(th);
2211         }
2212       }
2213     }
2214   }
2215   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2216     if(rt1[i]) {
2217       signed char s1l,s1h,s2l,s2h,t;
2218       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2219       {
2220         t=get_reg(i_regs->regmap,rt1[i]);
2221         //assert(t>=0);
2222         if(t>=0) {
2223           s1l=get_reg(i_regs->regmap,rs1[i]);
2224           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2225           s2l=get_reg(i_regs->regmap,rs2[i]);
2226           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2227           if(rs2[i]==0) // rx<r0
2228           {
2229             assert(s1h>=0);
2230             if(opcode2[i]==0x2a) // SLT
2231               emit_shrimm(s1h,31,t);
2232             else // SLTU (unsigned can not be less than zero)
2233               emit_zeroreg(t);
2234           }
2235           else if(rs1[i]==0) // r0<rx
2236           {
2237             assert(s2h>=0);
2238             if(opcode2[i]==0x2a) // SLT
2239               emit_set_gz64_32(s2h,s2l,t);
2240             else // SLTU (set if not zero)
2241               emit_set_nz64_32(s2h,s2l,t);
2242           }
2243           else {
2244             assert(s1l>=0);assert(s1h>=0);
2245             assert(s2l>=0);assert(s2h>=0);
2246             if(opcode2[i]==0x2a) // SLT
2247               emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2248             else // SLTU
2249               emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2250           }
2251         }
2252       } else {
2253         t=get_reg(i_regs->regmap,rt1[i]);
2254         //assert(t>=0);
2255         if(t>=0) {
2256           s1l=get_reg(i_regs->regmap,rs1[i]);
2257           s2l=get_reg(i_regs->regmap,rs2[i]);
2258           if(rs2[i]==0) // rx<r0
2259           {
2260             assert(s1l>=0);
2261             if(opcode2[i]==0x2a) // SLT
2262               emit_shrimm(s1l,31,t);
2263             else // SLTU (unsigned can not be less than zero)
2264               emit_zeroreg(t);
2265           }
2266           else if(rs1[i]==0) // r0<rx
2267           {
2268             assert(s2l>=0);
2269             if(opcode2[i]==0x2a) // SLT
2270               emit_set_gz32(s2l,t);
2271             else // SLTU (set if not zero)
2272               emit_set_nz32(s2l,t);
2273           }
2274           else{
2275             assert(s1l>=0);assert(s2l>=0);
2276             if(opcode2[i]==0x2a) // SLT
2277               emit_set_if_less32(s1l,s2l,t);
2278             else // SLTU
2279               emit_set_if_carry32(s1l,s2l,t);
2280           }
2281         }
2282       }
2283     }
2284   }
2285   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2286     if(rt1[i]) {
2287       signed char s1l,s1h,s2l,s2h,th,tl;
2288       tl=get_reg(i_regs->regmap,rt1[i]);
2289       th=get_reg(i_regs->regmap,rt1[i]|64);
2290       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2291       {
2292         assert(tl>=0);
2293         if(tl>=0) {
2294           s1l=get_reg(i_regs->regmap,rs1[i]);
2295           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2296           s2l=get_reg(i_regs->regmap,rs2[i]);
2297           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2298           if(rs1[i]&&rs2[i]) {
2299             assert(s1l>=0);assert(s1h>=0);
2300             assert(s2l>=0);assert(s2h>=0);
2301             if(opcode2[i]==0x24) { // AND
2302               emit_and(s1l,s2l,tl);
2303               emit_and(s1h,s2h,th);
2304             } else
2305             if(opcode2[i]==0x25) { // OR
2306               emit_or(s1l,s2l,tl);
2307               emit_or(s1h,s2h,th);
2308             } else
2309             if(opcode2[i]==0x26) { // XOR
2310               emit_xor(s1l,s2l,tl);
2311               emit_xor(s1h,s2h,th);
2312             } else
2313             if(opcode2[i]==0x27) { // NOR
2314               emit_or(s1l,s2l,tl);
2315               emit_or(s1h,s2h,th);
2316               emit_not(tl,tl);
2317               emit_not(th,th);
2318             }
2319           }
2320           else
2321           {
2322             if(opcode2[i]==0x24) { // AND
2323               emit_zeroreg(tl);
2324               emit_zeroreg(th);
2325             } else
2326             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2327               if(rs1[i]){
2328                 if(s1l>=0) emit_mov(s1l,tl);
2329                 else emit_loadreg(rs1[i],tl);
2330                 if(s1h>=0) emit_mov(s1h,th);
2331                 else emit_loadreg(rs1[i]|64,th);
2332               }
2333               else
2334               if(rs2[i]){
2335                 if(s2l>=0) emit_mov(s2l,tl);
2336                 else emit_loadreg(rs2[i],tl);
2337                 if(s2h>=0) emit_mov(s2h,th);
2338                 else emit_loadreg(rs2[i]|64,th);
2339               }
2340               else{
2341                 emit_zeroreg(tl);
2342                 emit_zeroreg(th);
2343               }
2344             } else
2345             if(opcode2[i]==0x27) { // NOR
2346               if(rs1[i]){
2347                 if(s1l>=0) emit_not(s1l,tl);
2348                 else{
2349                   emit_loadreg(rs1[i],tl);
2350                   emit_not(tl,tl);
2351                 }
2352                 if(s1h>=0) emit_not(s1h,th);
2353                 else{
2354                   emit_loadreg(rs1[i]|64,th);
2355                   emit_not(th,th);
2356                 }
2357               }
2358               else
2359               if(rs2[i]){
2360                 if(s2l>=0) emit_not(s2l,tl);
2361                 else{
2362                   emit_loadreg(rs2[i],tl);
2363                   emit_not(tl,tl);
2364                 }
2365                 if(s2h>=0) emit_not(s2h,th);
2366                 else{
2367                   emit_loadreg(rs2[i]|64,th);
2368                   emit_not(th,th);
2369                 }
2370               }
2371               else {
2372                 emit_movimm(-1,tl);
2373                 emit_movimm(-1,th);
2374               }
2375             }
2376           }
2377         }
2378       }
2379       else
2380       {
2381         // 32 bit
2382         if(tl>=0) {
2383           s1l=get_reg(i_regs->regmap,rs1[i]);
2384           s2l=get_reg(i_regs->regmap,rs2[i]);
2385           if(rs1[i]&&rs2[i]) {
2386             assert(s1l>=0);
2387             assert(s2l>=0);
2388             if(opcode2[i]==0x24) { // AND
2389               emit_and(s1l,s2l,tl);
2390             } else
2391             if(opcode2[i]==0x25) { // OR
2392               emit_or(s1l,s2l,tl);
2393             } else
2394             if(opcode2[i]==0x26) { // XOR
2395               emit_xor(s1l,s2l,tl);
2396             } else
2397             if(opcode2[i]==0x27) { // NOR
2398               emit_or(s1l,s2l,tl);
2399               emit_not(tl,tl);
2400             }
2401           }
2402           else
2403           {
2404             if(opcode2[i]==0x24) { // AND
2405               emit_zeroreg(tl);
2406             } else
2407             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2408               if(rs1[i]){
2409                 if(s1l>=0) emit_mov(s1l,tl);
2410                 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2411               }
2412               else
2413               if(rs2[i]){
2414                 if(s2l>=0) emit_mov(s2l,tl);
2415                 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2416               }
2417               else emit_zeroreg(tl);
2418             } else
2419             if(opcode2[i]==0x27) { // NOR
2420               if(rs1[i]){
2421                 if(s1l>=0) emit_not(s1l,tl);
2422                 else {
2423                   emit_loadreg(rs1[i],tl);
2424                   emit_not(tl,tl);
2425                 }
2426               }
2427               else
2428               if(rs2[i]){
2429                 if(s2l>=0) emit_not(s2l,tl);
2430                 else {
2431                   emit_loadreg(rs2[i],tl);
2432                   emit_not(tl,tl);
2433                 }
2434               }
2435               else emit_movimm(-1,tl);
2436             }
2437           }
2438         }
2439       }
2440     }
2441   }
2442 }
2443
2444 void imm16_assemble(int i,struct regstat *i_regs)
2445 {
2446   if (opcode[i]==0x0f) { // LUI
2447     if(rt1[i]) {
2448       signed char t;
2449       t=get_reg(i_regs->regmap,rt1[i]);
2450       //assert(t>=0);
2451       if(t>=0) {
2452         if(!((i_regs->isconst>>t)&1))
2453           emit_movimm(imm[i]<<16,t);
2454       }
2455     }
2456   }
2457   if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2458     if(rt1[i]) {
2459       signed char s,t;
2460       t=get_reg(i_regs->regmap,rt1[i]);
2461       s=get_reg(i_regs->regmap,rs1[i]);
2462       if(rs1[i]) {
2463         //assert(t>=0);
2464         //assert(s>=0);
2465         if(t>=0) {
2466           if(!((i_regs->isconst>>t)&1)) {
2467             if(s<0) {
2468               if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2469               emit_addimm(t,imm[i],t);
2470             }else{
2471               if(!((i_regs->wasconst>>s)&1))
2472                 emit_addimm(s,imm[i],t);
2473               else
2474                 emit_movimm(constmap[i][s]+imm[i],t);
2475             }
2476           }
2477         }
2478       } else {
2479         if(t>=0) {
2480           if(!((i_regs->isconst>>t)&1))
2481             emit_movimm(imm[i],t);
2482         }
2483       }
2484     }
2485   }
2486   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2487     if(rt1[i]) {
2488       signed char sh,sl,th,tl;
2489       th=get_reg(i_regs->regmap,rt1[i]|64);
2490       tl=get_reg(i_regs->regmap,rt1[i]);
2491       sh=get_reg(i_regs->regmap,rs1[i]|64);
2492       sl=get_reg(i_regs->regmap,rs1[i]);
2493       if(tl>=0) {
2494         if(rs1[i]) {
2495           assert(sh>=0);
2496           assert(sl>=0);
2497           if(th>=0) {
2498             emit_addimm64_32(sh,sl,imm[i],th,tl);
2499           }
2500           else {
2501             emit_addimm(sl,imm[i],tl);
2502           }
2503         } else {
2504           emit_movimm(imm[i],tl);
2505           if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2506         }
2507       }
2508     }
2509   }
2510   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2511     if(rt1[i]) {
2512       //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2513       signed char sh,sl,t;
2514       t=get_reg(i_regs->regmap,rt1[i]);
2515       sh=get_reg(i_regs->regmap,rs1[i]|64);
2516       sl=get_reg(i_regs->regmap,rs1[i]);
2517       //assert(t>=0);
2518       if(t>=0) {
2519         if(rs1[i]>0) {
2520           if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2521           if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2522             if(opcode[i]==0x0a) { // SLTI
2523               if(sl<0) {
2524                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2525                 emit_slti32(t,imm[i],t);
2526               }else{
2527                 emit_slti32(sl,imm[i],t);
2528               }
2529             }
2530             else { // SLTIU
2531               if(sl<0) {
2532                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2533                 emit_sltiu32(t,imm[i],t);
2534               }else{
2535                 emit_sltiu32(sl,imm[i],t);
2536               }
2537             }
2538           }else{ // 64-bit
2539             assert(sl>=0);
2540             if(opcode[i]==0x0a) // SLTI
2541               emit_slti64_32(sh,sl,imm[i],t);
2542             else // SLTIU
2543               emit_sltiu64_32(sh,sl,imm[i],t);
2544           }
2545         }else{
2546           // SLTI(U) with r0 is just stupid,
2547           // nonetheless examples can be found
2548           if(opcode[i]==0x0a) // SLTI
2549             if(0<imm[i]) emit_movimm(1,t);
2550             else emit_zeroreg(t);
2551           else // SLTIU
2552           {
2553             if(imm[i]) emit_movimm(1,t);
2554             else emit_zeroreg(t);
2555           }
2556         }
2557       }
2558     }
2559   }
2560   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2561     if(rt1[i]) {
2562       signed char sh,sl,th,tl;
2563       th=get_reg(i_regs->regmap,rt1[i]|64);
2564       tl=get_reg(i_regs->regmap,rt1[i]);
2565       sh=get_reg(i_regs->regmap,rs1[i]|64);
2566       sl=get_reg(i_regs->regmap,rs1[i]);
2567       if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2568         if(opcode[i]==0x0c) //ANDI
2569         {
2570           if(rs1[i]) {
2571             if(sl<0) {
2572               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2573               emit_andimm(tl,imm[i],tl);
2574             }else{
2575               if(!((i_regs->wasconst>>sl)&1))
2576                 emit_andimm(sl,imm[i],tl);
2577               else
2578                 emit_movimm(constmap[i][sl]&imm[i],tl);
2579             }
2580           }
2581           else
2582             emit_zeroreg(tl);
2583           if(th>=0) emit_zeroreg(th);
2584         }
2585         else
2586         {
2587           if(rs1[i]) {
2588             if(sl<0) {
2589               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2590             }
2591             if(th>=0) {
2592               if(sh<0) {
2593                 emit_loadreg(rs1[i]|64,th);
2594               }else{
2595                 emit_mov(sh,th);
2596               }
2597             }
2598             if(opcode[i]==0x0d) //ORI
2599             if(sl<0) {
2600               emit_orimm(tl,imm[i],tl);
2601             }else{
2602               if(!((i_regs->wasconst>>sl)&1))
2603                 emit_orimm(sl,imm[i],tl);
2604               else
2605                 emit_movimm(constmap[i][sl]|imm[i],tl);
2606             }
2607             if(opcode[i]==0x0e) //XORI
2608             if(sl<0) {
2609               emit_xorimm(tl,imm[i],tl);
2610             }else{
2611               if(!((i_regs->wasconst>>sl)&1))
2612                 emit_xorimm(sl,imm[i],tl);
2613               else
2614                 emit_movimm(constmap[i][sl]^imm[i],tl);
2615             }
2616           }
2617           else {
2618             emit_movimm(imm[i],tl);
2619             if(th>=0) emit_zeroreg(th);
2620           }
2621         }
2622       }
2623     }
2624   }
2625 }
2626
2627 void shiftimm_assemble(int i,struct regstat *i_regs)
2628 {
2629   if(opcode2[i]<=0x3) // SLL/SRL/SRA
2630   {
2631     if(rt1[i]) {
2632       signed char s,t;
2633       t=get_reg(i_regs->regmap,rt1[i]);
2634       s=get_reg(i_regs->regmap,rs1[i]);
2635       //assert(t>=0);
2636       if(t>=0){
2637         if(rs1[i]==0)
2638         {
2639           emit_zeroreg(t);
2640         }
2641         else
2642         {
2643           if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2644           if(imm[i]) {
2645             if(opcode2[i]==0) // SLL
2646             {
2647               emit_shlimm(s<0?t:s,imm[i],t);
2648             }
2649             if(opcode2[i]==2) // SRL
2650             {
2651               emit_shrimm(s<0?t:s,imm[i],t);
2652             }
2653             if(opcode2[i]==3) // SRA
2654             {
2655               emit_sarimm(s<0?t:s,imm[i],t);
2656             }
2657           }else{
2658             // Shift by zero
2659             if(s>=0 && s!=t) emit_mov(s,t);
2660           }
2661         }
2662       }
2663       //emit_storereg(rt1[i],t); //DEBUG
2664     }
2665   }
2666   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2667   {
2668     if(rt1[i]) {
2669       signed char sh,sl,th,tl;
2670       th=get_reg(i_regs->regmap,rt1[i]|64);
2671       tl=get_reg(i_regs->regmap,rt1[i]);
2672       sh=get_reg(i_regs->regmap,rs1[i]|64);
2673       sl=get_reg(i_regs->regmap,rs1[i]);
2674       if(tl>=0) {
2675         if(rs1[i]==0)
2676         {
2677           emit_zeroreg(tl);
2678           if(th>=0) emit_zeroreg(th);
2679         }
2680         else
2681         {
2682           assert(sl>=0);
2683           assert(sh>=0);
2684           if(imm[i]) {
2685             if(opcode2[i]==0x38) // DSLL
2686             {
2687               if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2688               emit_shlimm(sl,imm[i],tl);
2689             }
2690             if(opcode2[i]==0x3a) // DSRL
2691             {
2692               emit_shrdimm(sl,sh,imm[i],tl);
2693               if(th>=0) emit_shrimm(sh,imm[i],th);
2694             }
2695             if(opcode2[i]==0x3b) // DSRA
2696             {
2697               emit_shrdimm(sl,sh,imm[i],tl);
2698               if(th>=0) emit_sarimm(sh,imm[i],th);
2699             }
2700           }else{
2701             // Shift by zero
2702             if(sl!=tl) emit_mov(sl,tl);
2703             if(th>=0&&sh!=th) emit_mov(sh,th);
2704           }
2705         }
2706       }
2707     }
2708   }
2709   if(opcode2[i]==0x3c) // DSLL32
2710   {
2711     if(rt1[i]) {
2712       signed char sl,tl,th;
2713       tl=get_reg(i_regs->regmap,rt1[i]);
2714       th=get_reg(i_regs->regmap,rt1[i]|64);
2715       sl=get_reg(i_regs->regmap,rs1[i]);
2716       if(th>=0||tl>=0){
2717         assert(tl>=0);
2718         assert(th>=0);
2719         assert(sl>=0);
2720         emit_mov(sl,th);
2721         emit_zeroreg(tl);
2722         if(imm[i]>32)
2723         {
2724           emit_shlimm(th,imm[i]&31,th);
2725         }
2726       }
2727     }
2728   }
2729   if(opcode2[i]==0x3e) // DSRL32
2730   {
2731     if(rt1[i]) {
2732       signed char sh,tl,th;
2733       tl=get_reg(i_regs->regmap,rt1[i]);
2734       th=get_reg(i_regs->regmap,rt1[i]|64);
2735       sh=get_reg(i_regs->regmap,rs1[i]|64);
2736       if(tl>=0){
2737         assert(sh>=0);
2738         emit_mov(sh,tl);
2739         if(th>=0) emit_zeroreg(th);
2740         if(imm[i]>32)
2741         {
2742           emit_shrimm(tl,imm[i]&31,tl);
2743         }
2744       }
2745     }
2746   }
2747   if(opcode2[i]==0x3f) // DSRA32
2748   {
2749     if(rt1[i]) {
2750       signed char sh,tl;
2751       tl=get_reg(i_regs->regmap,rt1[i]);
2752       sh=get_reg(i_regs->regmap,rs1[i]|64);
2753       if(tl>=0){
2754         assert(sh>=0);
2755         emit_mov(sh,tl);
2756         if(imm[i]>32)
2757         {
2758           emit_sarimm(tl,imm[i]&31,tl);
2759         }
2760       }
2761     }
2762   }
2763 }
2764
2765 #ifndef shift_assemble
2766 void shift_assemble(int i,struct regstat *i_regs)
2767 {
2768   printf("Need shift_assemble for this architecture.\n");
2769   exit(1);
2770 }
2771 #endif
2772
2773 void load_assemble(int i,struct regstat *i_regs)
2774 {
2775   int s,th,tl,addr,map=-1;
2776   int offset;
2777   int jaddr=0;
2778   int memtarget=0,c=0;
2779   u_int hr,reglist=0;
2780   th=get_reg(i_regs->regmap,rt1[i]|64);
2781   tl=get_reg(i_regs->regmap,rt1[i]);
2782   s=get_reg(i_regs->regmap,rs1[i]);
2783   offset=imm[i];
2784   for(hr=0;hr<HOST_REGS;hr++) {
2785     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2786   }
2787   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2788   if(s>=0) {
2789     c=(i_regs->wasconst>>s)&1;
2790     if (c) {
2791       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2792       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2793     }
2794   }
2795   //printf("load_assemble: c=%d\n",c);
2796   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2797   // FIXME: Even if the load is a NOP, we should check for pagefaults...
2798 #ifdef PCSX
2799   if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2800     ||rt1[i]==0) {
2801       // could be FIFO, must perform the read
2802       // ||dummy read
2803       assem_debug("(forced read)\n");
2804       tl=get_reg(i_regs->regmap,-1);
2805       assert(tl>=0);
2806   }
2807 #endif
2808   if(offset||s<0||c) addr=tl;
2809   else addr=s;
2810   //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2811  if(tl>=0) {
2812   //printf("load_assemble: c=%d\n",c);
2813   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2814   assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2815   reglist&=~(1<<tl);
2816   if(th>=0) reglist&=~(1<<th);
2817   if(!using_tlb) {
2818     if(!c) {
2819       #ifdef RAM_OFFSET
2820       map=get_reg(i_regs->regmap,ROREG);
2821       if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2822       #endif
2823 //#define R29_HACK 1
2824       #ifdef R29_HACK
2825       // Strmnnrmn's speed hack
2826       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2827       #endif
2828       {
2829         emit_cmpimm(addr,RAM_SIZE);
2830         jaddr=(int)out;
2831         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2832         // Hint to branch predictor that the branch is unlikely to be taken
2833         if(rs1[i]>=28)
2834           emit_jno_unlikely(0);
2835         else
2836         #endif
2837         emit_jno(0);
2838       }
2839     }
2840   }else{ // using tlb
2841     int x=0;
2842     if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2843     if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2844     map=get_reg(i_regs->regmap,TLREG);
2845     assert(map>=0);
2846     map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2847     do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2848   }
2849   int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2850   if (opcode[i]==0x20) { // LB
2851     if(!c||memtarget) {
2852       if(!dummy) {
2853         #ifdef HOST_IMM_ADDR32
2854         if(c)
2855           emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2856         else
2857         #endif
2858         {
2859           //emit_xorimm(addr,3,tl);
2860           //gen_tlb_addr_r(tl,map);
2861           //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2862           int x=0,a=tl;
2863 #ifdef BIG_ENDIAN_MIPS
2864           if(!c) emit_xorimm(addr,3,tl);
2865           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2866 #else
2867           if(!c) a=addr;
2868 #endif
2869           emit_movsbl_indexed_tlb(x,a,map,tl);
2870         }
2871       }
2872       if(jaddr)
2873         add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2874     }
2875     else
2876       inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2877   }
2878   if (opcode[i]==0x21) { // LH
2879     if(!c||memtarget) {
2880       if(!dummy) {
2881         #ifdef HOST_IMM_ADDR32
2882         if(c)
2883           emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2884         else
2885         #endif
2886         {
2887           int x=0,a=tl;
2888 #ifdef BIG_ENDIAN_MIPS
2889           if(!c) emit_xorimm(addr,2,tl);
2890           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2891 #else
2892           if(!c) a=addr;
2893 #endif
2894           //#ifdef
2895           //emit_movswl_indexed_tlb(x,tl,map,tl);
2896           //else
2897           if(map>=0) {
2898             gen_tlb_addr_r(a,map);
2899             emit_movswl_indexed(x,a,tl);
2900           }else{
2901             #ifdef RAM_OFFSET
2902             emit_movswl_indexed(x,a,tl);
2903             #else
2904             emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2905             #endif
2906           }
2907         }
2908       }
2909       if(jaddr)
2910         add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2911     }
2912     else
2913       inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2914   }
2915   if (opcode[i]==0x23) { // LW
2916     if(!c||memtarget) {
2917       if(!dummy) {
2918         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2919         #ifdef HOST_IMM_ADDR32
2920         if(c)
2921           emit_readword_tlb(constmap[i][s]+offset,map,tl);
2922         else
2923         #endif
2924         emit_readword_indexed_tlb(0,addr,map,tl);
2925       }
2926       if(jaddr)
2927         add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2928     }
2929     else
2930       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2931   }
2932   if (opcode[i]==0x24) { // LBU
2933     if(!c||memtarget) {
2934       if(!dummy) {
2935         #ifdef HOST_IMM_ADDR32
2936         if(c)
2937           emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2938         else
2939         #endif
2940         {
2941           //emit_xorimm(addr,3,tl);
2942           //gen_tlb_addr_r(tl,map);
2943           //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
2944           int x=0,a=tl;
2945 #ifdef BIG_ENDIAN_MIPS
2946           if(!c) emit_xorimm(addr,3,tl);
2947           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2948 #else
2949           if(!c) a=addr;
2950 #endif
2951           emit_movzbl_indexed_tlb(x,a,map,tl);
2952         }
2953       }
2954       if(jaddr)
2955         add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2956     }
2957     else
2958       inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2959   }
2960   if (opcode[i]==0x25) { // LHU
2961     if(!c||memtarget) {
2962       if(!dummy) {
2963         #ifdef HOST_IMM_ADDR32
2964         if(c)
2965           emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2966         else
2967         #endif
2968         {
2969           int x=0,a=tl;
2970 #ifdef BIG_ENDIAN_MIPS
2971           if(!c) emit_xorimm(addr,2,tl);
2972           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2973 #else
2974           if(!c) a=addr;
2975 #endif
2976           //#ifdef
2977           //emit_movzwl_indexed_tlb(x,tl,map,tl);
2978           //#else
2979           if(map>=0) {
2980             gen_tlb_addr_r(a,map);
2981             emit_movzwl_indexed(x,a,tl);
2982           }else{
2983             #ifdef RAM_OFFSET
2984             emit_movzwl_indexed(x,a,tl);
2985             #else
2986             emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
2987             #endif
2988           }
2989         }
2990       }
2991       if(jaddr)
2992         add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2993     }
2994     else
2995       inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2996   }
2997   if (opcode[i]==0x27) { // LWU
2998     assert(th>=0);
2999     if(!c||memtarget) {
3000       if(!dummy) {
3001         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3002         #ifdef HOST_IMM_ADDR32
3003         if(c)
3004           emit_readword_tlb(constmap[i][s]+offset,map,tl);
3005         else
3006         #endif
3007         emit_readword_indexed_tlb(0,addr,map,tl);
3008       }
3009       if(jaddr)
3010         add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3011     }
3012     else {
3013       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3014     }
3015     emit_zeroreg(th);
3016   }
3017   if (opcode[i]==0x37) { // LD
3018     if(!c||memtarget) {
3019       if(!dummy) {
3020         //gen_tlb_addr_r(tl,map);
3021         //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3022         //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3023         #ifdef HOST_IMM_ADDR32
3024         if(c)
3025           emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3026         else
3027         #endif
3028         emit_readdword_indexed_tlb(0,addr,map,th,tl);
3029       }
3030       if(jaddr)
3031         add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3032     }
3033     else
3034       inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3035   }
3036  }
3037   //emit_storereg(rt1[i],tl); // DEBUG
3038   //if(opcode[i]==0x23)
3039   //if(opcode[i]==0x24)
3040   //if(opcode[i]==0x23||opcode[i]==0x24)
3041   /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3042   {
3043     //emit_pusha();
3044     save_regs(0x100f);
3045         emit_readword((int)&last_count,ECX);
3046         #ifdef __i386__
3047         if(get_reg(i_regs->regmap,CCREG)<0)
3048           emit_loadreg(CCREG,HOST_CCREG);
3049         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3050         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3051         emit_writeword(HOST_CCREG,(int)&Count);
3052         #endif
3053         #ifdef __arm__
3054         if(get_reg(i_regs->regmap,CCREG)<0)
3055           emit_loadreg(CCREG,0);
3056         else
3057           emit_mov(HOST_CCREG,0);
3058         emit_add(0,ECX,0);
3059         emit_addimm(0,2*ccadj[i],0);
3060         emit_writeword(0,(int)&Count);
3061         #endif
3062     emit_call((int)memdebug);
3063     //emit_popa();
3064     restore_regs(0x100f);
3065   }/**/
3066 }
3067
3068 #ifndef loadlr_assemble
3069 void loadlr_assemble(int i,struct regstat *i_regs)
3070 {
3071   printf("Need loadlr_assemble for this architecture.\n");
3072   exit(1);
3073 }
3074 #endif
3075
3076 void store_assemble(int i,struct regstat *i_regs)
3077 {
3078   int s,th,tl,map=-1;
3079   int addr,temp;
3080   int offset;
3081   int jaddr=0,jaddr2,type;
3082   int memtarget=0,c=0;
3083   int agr=AGEN1+(i&1);
3084   u_int hr,reglist=0;
3085   th=get_reg(i_regs->regmap,rs2[i]|64);
3086   tl=get_reg(i_regs->regmap,rs2[i]);
3087   s=get_reg(i_regs->regmap,rs1[i]);
3088   temp=get_reg(i_regs->regmap,agr);
3089   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3090   offset=imm[i];
3091   if(s>=0) {
3092     c=(i_regs->wasconst>>s)&1;
3093     if(c) {
3094       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3095       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3096     }
3097   }
3098   assert(tl>=0);
3099   assert(temp>=0);
3100   for(hr=0;hr<HOST_REGS;hr++) {
3101     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3102   }
3103   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3104   if(offset||s<0||c) addr=temp;
3105   else addr=s;
3106   if(!using_tlb) {
3107     if(!c) {
3108       #ifdef R29_HACK
3109       // Strmnnrmn's speed hack
3110       memtarget=1;
3111       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3112       #endif
3113       emit_cmpimm(addr,RAM_SIZE);
3114       #ifdef DESTRUCTIVE_SHIFT
3115       if(s==addr) emit_mov(s,temp);
3116       #endif
3117       #ifdef R29_HACK
3118       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3119       #endif
3120       {
3121         jaddr=(int)out;
3122         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3123         // Hint to branch predictor that the branch is unlikely to be taken
3124         if(rs1[i]>=28)
3125           emit_jno_unlikely(0);
3126         else
3127         #endif
3128         emit_jno(0);
3129       }
3130     }
3131   }else{ // using tlb
3132     int x=0;
3133     if (opcode[i]==0x28) x=3; // SB
3134     if (opcode[i]==0x29) x=2; // SH
3135     map=get_reg(i_regs->regmap,TLREG);
3136     assert(map>=0);
3137     map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3138     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3139   }
3140
3141   if (opcode[i]==0x28) { // SB
3142     if(!c||memtarget) {
3143       int x=0,a=temp;
3144 #ifdef BIG_ENDIAN_MIPS
3145       if(!c) emit_xorimm(addr,3,temp);
3146       else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3147 #else
3148       if(!c) a=addr;
3149 #endif
3150       //gen_tlb_addr_w(temp,map);
3151       //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3152       emit_writebyte_indexed_tlb(tl,x,a,map,a);
3153     }
3154     type=STOREB_STUB;
3155   }
3156   if (opcode[i]==0x29) { // SH
3157     if(!c||memtarget) {
3158       int x=0,a=temp;
3159 #ifdef BIG_ENDIAN_MIPS
3160       if(!c) emit_xorimm(addr,2,temp);
3161       else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3162 #else
3163       if(!c) a=addr;
3164 #endif
3165       //#ifdef
3166       //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3167       //#else
3168       if(map>=0) {
3169         gen_tlb_addr_w(a,map);
3170         emit_writehword_indexed(tl,x,a);
3171       }else
3172         emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
3173     }
3174     type=STOREH_STUB;
3175   }
3176   if (opcode[i]==0x2B) { // SW
3177     if(!c||memtarget)
3178       //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3179       emit_writeword_indexed_tlb(tl,0,addr,map,temp);
3180     type=STOREW_STUB;
3181   }
3182   if (opcode[i]==0x3F) { // SD
3183     if(!c||memtarget) {
3184       if(rs2[i]) {
3185         assert(th>=0);
3186         //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3187         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3188         emit_writedword_indexed_tlb(th,tl,0,addr,map,temp);
3189       }else{
3190         // Store zero
3191         //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3192         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3193         emit_writedword_indexed_tlb(tl,tl,0,addr,map,temp);
3194       }
3195     }
3196     type=STORED_STUB;
3197   }
3198   if(!using_tlb) {
3199     if(!c||memtarget) {
3200       #ifdef DESTRUCTIVE_SHIFT
3201       // The x86 shift operation is 'destructive'; it overwrites the
3202       // source register, so we need to make a copy first and use that.
3203       addr=temp;
3204       #endif
3205       #if defined(HOST_IMM8)
3206       int ir=get_reg(i_regs->regmap,INVCP);
3207       assert(ir>=0);
3208       emit_cmpmem_indexedsr12_reg(ir,addr,1);
3209       #else
3210       emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3211       #endif
3212       #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3213       emit_callne(invalidate_addr_reg[addr]);
3214       #else
3215       jaddr2=(int)out;
3216       emit_jne(0);
3217       add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3218       #endif
3219     }
3220   }
3221   if(jaddr) {
3222     add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3223   } else if(c&&!memtarget) {
3224     inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3225   }
3226   //if(opcode[i]==0x2B || opcode[i]==0x3F)
3227   //if(opcode[i]==0x2B || opcode[i]==0x28)
3228   //if(opcode[i]==0x2B || opcode[i]==0x29)
3229   //if(opcode[i]==0x2B)
3230   /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3231   {
3232     //emit_pusha();
3233     save_regs(0x100f);
3234         emit_readword((int)&last_count,ECX);
3235         #ifdef __i386__
3236         if(get_reg(i_regs->regmap,CCREG)<0)
3237           emit_loadreg(CCREG,HOST_CCREG);
3238         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3239         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3240         emit_writeword(HOST_CCREG,(int)&Count);
3241         #endif
3242         #ifdef __arm__
3243         if(get_reg(i_regs->regmap,CCREG)<0)
3244           emit_loadreg(CCREG,0);
3245         else
3246           emit_mov(HOST_CCREG,0);
3247         emit_add(0,ECX,0);
3248         emit_addimm(0,2*ccadj[i],0);
3249         emit_writeword(0,(int)&Count);
3250         #endif
3251     emit_call((int)memdebug);
3252     //emit_popa();
3253     restore_regs(0x100f);
3254   }/**/
3255 }
3256
3257 void storelr_assemble(int i,struct regstat *i_regs)
3258 {
3259   int s,th,tl;
3260   int temp;
3261   int temp2;
3262   int offset;
3263   int jaddr=0,jaddr2;
3264   int case1,case2,case3;
3265   int done0,done1,done2;
3266   int memtarget=0,c=0;
3267   int agr=AGEN1+(i&1);
3268   u_int hr,reglist=0;
3269   th=get_reg(i_regs->regmap,rs2[i]|64);
3270   tl=get_reg(i_regs->regmap,rs2[i]);
3271   s=get_reg(i_regs->regmap,rs1[i]);
3272   temp=get_reg(i_regs->regmap,agr);
3273   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3274   offset=imm[i];
3275   if(s>=0) {
3276     c=(i_regs->isconst>>s)&1;
3277     if(c) {
3278       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3279       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3280     }
3281   }
3282   assert(tl>=0);
3283   for(hr=0;hr<HOST_REGS;hr++) {
3284     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3285   }
3286   assert(temp>=0);
3287   if(!using_tlb) {
3288     if(!c) {
3289       emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3290       if(!offset&&s!=temp) emit_mov(s,temp);
3291       jaddr=(int)out;
3292       emit_jno(0);
3293     }
3294     else
3295     {
3296       if(!memtarget||!rs1[i]) {
3297         jaddr=(int)out;
3298         emit_jmp(0);
3299       }
3300     }
3301     #ifdef RAM_OFFSET
3302     int map=get_reg(i_regs->regmap,ROREG);
3303     if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3304     gen_tlb_addr_w(temp,map);
3305     #else
3306     if((u_int)rdram!=0x80000000)
3307       emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3308     #endif
3309   }else{ // using tlb
3310     int map=get_reg(i_regs->regmap,TLREG);
3311     assert(map>=0);
3312     map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3313     if(!c&&!offset&&s>=0) emit_mov(s,temp);
3314     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3315     if(!jaddr&&!memtarget) {
3316       jaddr=(int)out;
3317       emit_jmp(0);
3318     }
3319     gen_tlb_addr_w(temp,map);
3320   }
3321
3322   if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3323     temp2=get_reg(i_regs->regmap,FTEMP);
3324     if(!rs2[i]) temp2=th=tl;
3325   }
3326
3327 #ifndef BIG_ENDIAN_MIPS
3328     emit_xorimm(temp,3,temp);
3329 #endif
3330   emit_testimm(temp,2);
3331   case2=(int)out;
3332   emit_jne(0);
3333   emit_testimm(temp,1);
3334   case1=(int)out;
3335   emit_jne(0);
3336   // 0
3337   if (opcode[i]==0x2A) { // SWL
3338     emit_writeword_indexed(tl,0,temp);
3339   }
3340   if (opcode[i]==0x2E) { // SWR
3341     emit_writebyte_indexed(tl,3,temp);
3342   }
3343   if (opcode[i]==0x2C) { // SDL
3344     emit_writeword_indexed(th,0,temp);
3345     if(rs2[i]) emit_mov(tl,temp2);
3346   }
3347   if (opcode[i]==0x2D) { // SDR
3348     emit_writebyte_indexed(tl,3,temp);
3349     if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3350   }
3351   done0=(int)out;
3352   emit_jmp(0);
3353   // 1
3354   set_jump_target(case1,(int)out);
3355   if (opcode[i]==0x2A) { // SWL
3356     // Write 3 msb into three least significant bytes
3357     if(rs2[i]) emit_rorimm(tl,8,tl);
3358     emit_writehword_indexed(tl,-1,temp);
3359     if(rs2[i]) emit_rorimm(tl,16,tl);
3360     emit_writebyte_indexed(tl,1,temp);
3361     if(rs2[i]) emit_rorimm(tl,8,tl);
3362   }
3363   if (opcode[i]==0x2E) { // SWR
3364     // Write two lsb into two most significant bytes
3365     emit_writehword_indexed(tl,1,temp);
3366   }
3367   if (opcode[i]==0x2C) { // SDL
3368     if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3369     // Write 3 msb into three least significant bytes
3370     if(rs2[i]) emit_rorimm(th,8,th);
3371     emit_writehword_indexed(th,-1,temp);
3372     if(rs2[i]) emit_rorimm(th,16,th);
3373     emit_writebyte_indexed(th,1,temp);
3374     if(rs2[i]) emit_rorimm(th,8,th);
3375   }
3376   if (opcode[i]==0x2D) { // SDR
3377     if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3378     // Write two lsb into two most significant bytes
3379     emit_writehword_indexed(tl,1,temp);
3380   }
3381   done1=(int)out;
3382   emit_jmp(0);
3383   // 2
3384   set_jump_target(case2,(int)out);
3385   emit_testimm(temp,1);
3386   case3=(int)out;
3387   emit_jne(0);
3388   if (opcode[i]==0x2A) { // SWL
3389     // Write two msb into two least significant bytes
3390     if(rs2[i]) emit_rorimm(tl,16,tl);
3391     emit_writehword_indexed(tl,-2,temp);
3392     if(rs2[i]) emit_rorimm(tl,16,tl);
3393   }
3394   if (opcode[i]==0x2E) { // SWR
3395     // Write 3 lsb into three most significant bytes
3396     emit_writebyte_indexed(tl,-1,temp);
3397     if(rs2[i]) emit_rorimm(tl,8,tl);
3398     emit_writehword_indexed(tl,0,temp);
3399     if(rs2[i]) emit_rorimm(tl,24,tl);
3400   }
3401   if (opcode[i]==0x2C) { // SDL
3402     if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3403     // Write two msb into two least significant bytes
3404     if(rs2[i]) emit_rorimm(th,16,th);
3405     emit_writehword_indexed(th,-2,temp);
3406     if(rs2[i]) emit_rorimm(th,16,th);
3407   }
3408   if (opcode[i]==0x2D) { // SDR
3409     if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3410     // Write 3 lsb into three most significant bytes
3411     emit_writebyte_indexed(tl,-1,temp);
3412     if(rs2[i]) emit_rorimm(tl,8,tl);
3413     emit_writehword_indexed(tl,0,temp);
3414     if(rs2[i]) emit_rorimm(tl,24,tl);
3415   }
3416   done2=(int)out;
3417   emit_jmp(0);
3418   // 3
3419   set_jump_target(case3,(int)out);
3420   if (opcode[i]==0x2A) { // SWL
3421     // Write msb into least significant byte
3422     if(rs2[i]) emit_rorimm(tl,24,tl);
3423     emit_writebyte_indexed(tl,-3,temp);
3424     if(rs2[i]) emit_rorimm(tl,8,tl);
3425   }
3426   if (opcode[i]==0x2E) { // SWR
3427     // Write entire word
3428     emit_writeword_indexed(tl,-3,temp);
3429   }
3430   if (opcode[i]==0x2C) { // SDL
3431     if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3432     // Write msb into least significant byte
3433     if(rs2[i]) emit_rorimm(th,24,th);
3434     emit_writebyte_indexed(th,-3,temp);
3435     if(rs2[i]) emit_rorimm(th,8,th);
3436   }
3437   if (opcode[i]==0x2D) { // SDR
3438     if(rs2[i]) emit_mov(th,temp2);
3439     // Write entire word
3440     emit_writeword_indexed(tl,-3,temp);
3441   }
3442   set_jump_target(done0,(int)out);
3443   set_jump_target(done1,(int)out);
3444   set_jump_target(done2,(int)out);
3445   if (opcode[i]==0x2C) { // SDL
3446     emit_testimm(temp,4);
3447     done0=(int)out;
3448     emit_jne(0);
3449     emit_andimm(temp,~3,temp);
3450     emit_writeword_indexed(temp2,4,temp);
3451     set_jump_target(done0,(int)out);
3452   }
3453   if (opcode[i]==0x2D) { // SDR
3454     emit_testimm(temp,4);
3455     done0=(int)out;
3456     emit_jeq(0);
3457     emit_andimm(temp,~3,temp);
3458     emit_writeword_indexed(temp2,-4,temp);
3459     set_jump_target(done0,(int)out);
3460   }
3461   if(!c||!memtarget)
3462     add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
3463   if(!using_tlb) {
3464     #ifdef RAM_OFFSET
3465     int map=get_reg(i_regs->regmap,ROREG);
3466     if(map<0) map=HOST_TEMPREG;
3467     gen_orig_addr_w(temp,map);
3468     #else
3469     emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3470     #endif
3471     #if defined(HOST_IMM8)
3472     int ir=get_reg(i_regs->regmap,INVCP);
3473     assert(ir>=0);
3474     emit_cmpmem_indexedsr12_reg(ir,temp,1);
3475     #else
3476     emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3477     #endif
3478     #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3479     emit_callne(invalidate_addr_reg[temp]);
3480     #else
3481     jaddr2=(int)out;
3482     emit_jne(0);
3483     add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3484     #endif
3485   }
3486   /*
3487     emit_pusha();
3488     //save_regs(0x100f);
3489         emit_readword((int)&last_count,ECX);
3490         if(get_reg(i_regs->regmap,CCREG)<0)
3491           emit_loadreg(CCREG,HOST_CCREG);
3492         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3493         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3494         emit_writeword(HOST_CCREG,(int)&Count);
3495     emit_call((int)memdebug);
3496     emit_popa();
3497     //restore_regs(0x100f);
3498   /**/
3499 }
3500
3501 void c1ls_assemble(int i,struct regstat *i_regs)
3502 {
3503 #ifndef DISABLE_COP1
3504   int s,th,tl;
3505   int temp,ar;
3506   int map=-1;
3507   int offset;
3508   int c=0;
3509   int jaddr,jaddr2=0,jaddr3,type;
3510   int agr=AGEN1+(i&1);
3511   u_int hr,reglist=0;
3512   th=get_reg(i_regs->regmap,FTEMP|64);
3513   tl=get_reg(i_regs->regmap,FTEMP);
3514   s=get_reg(i_regs->regmap,rs1[i]);
3515   temp=get_reg(i_regs->regmap,agr);
3516   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3517   offset=imm[i];
3518   assert(tl>=0);
3519   assert(rs1[i]>0);
3520   assert(temp>=0);
3521   for(hr=0;hr<HOST_REGS;hr++) {
3522     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3523   }
3524   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3525   if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3526   {
3527     // Loads use a temporary register which we need to save
3528     reglist|=1<<temp;
3529   }
3530   if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3531     ar=temp;
3532   else // LWC1/LDC1
3533     ar=tl;
3534   //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3535   //else c=(i_regs->wasconst>>s)&1;
3536   if(s>=0) c=(i_regs->wasconst>>s)&1;
3537   // Check cop1 unusable
3538   if(!cop1_usable) {
3539     signed char rs=get_reg(i_regs->regmap,CSREG);
3540     assert(rs>=0);
3541     emit_testimm(rs,0x20000000);
3542     jaddr=(int)out;
3543     emit_jeq(0);
3544     add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3545     cop1_usable=1;
3546   }
3547   if (opcode[i]==0x39) { // SWC1 (get float address)
3548     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],tl);
3549   }
3550   if (opcode[i]==0x3D) { // SDC1 (get double address)
3551     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],tl);
3552   }
3553   // Generate address + offset
3554   if(!using_tlb) {
3555     if(!c)
3556       emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3557   }
3558   else
3559   {
3560     map=get_reg(i_regs->regmap,TLREG);
3561     assert(map>=0);
3562     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3563       map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3564     }
3565     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3566       map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3567     }
3568   }
3569   if (opcode[i]==0x39) { // SWC1 (read float)
3570     emit_readword_indexed(0,tl,tl);
3571   }
3572   if (opcode[i]==0x3D) { // SDC1 (read double)
3573     emit_readword_indexed(4,tl,th);
3574     emit_readword_indexed(0,tl,tl);
3575   }
3576   if (opcode[i]==0x31) { // LWC1 (get target address)
3577     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],temp);
3578   }
3579   if (opcode[i]==0x35) { // LDC1 (get target address)
3580     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],temp);
3581   }
3582   if(!using_tlb) {
3583     if(!c) {
3584       jaddr2=(int)out;
3585       emit_jno(0);
3586     }
3587     else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
3588       jaddr2=(int)out;
3589       emit_jmp(0); // inline_readstub/inline_writestub?  Very rare case
3590     }
3591     #ifdef DESTRUCTIVE_SHIFT
3592     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3593       if(!offset&&!c&&s>=0) emit_mov(s,ar);
3594     }
3595     #endif
3596   }else{
3597     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3598       do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3599     }
3600     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3601       do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3602     }
3603   }
3604   if (opcode[i]==0x31) { // LWC1
3605     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3606     //gen_tlb_addr_r(ar,map);
3607     //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3608     #ifdef HOST_IMM_ADDR32
3609     if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3610     else
3611     #endif
3612     emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3613     type=LOADW_STUB;
3614   }
3615   if (opcode[i]==0x35) { // LDC1
3616     assert(th>=0);
3617     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3618     //gen_tlb_addr_r(ar,map);
3619     //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3620     //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3621     #ifdef HOST_IMM_ADDR32
3622     if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3623     else
3624     #endif
3625     emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3626     type=LOADD_STUB;
3627   }
3628   if (opcode[i]==0x39) { // SWC1
3629     //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3630     emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3631     type=STOREW_STUB;
3632   }
3633   if (opcode[i]==0x3D) { // SDC1
3634     assert(th>=0);
3635     //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3636     //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3637     emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3638     type=STORED_STUB;
3639   }
3640   if(!using_tlb) {
3641     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3642       #ifndef DESTRUCTIVE_SHIFT
3643       temp=offset||c||s<0?ar:s;
3644       #endif
3645       #if defined(HOST_IMM8)
3646       int ir=get_reg(i_regs->regmap,INVCP);
3647       assert(ir>=0);
3648       emit_cmpmem_indexedsr12_reg(ir,temp,1);
3649       #else
3650       emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3651       #endif
3652       #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3653       emit_callne(invalidate_addr_reg[temp]);
3654       #else
3655       jaddr3=(int)out;
3656       emit_jne(0);
3657       add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3658       #endif
3659     }
3660   }
3661   if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3662   if (opcode[i]==0x31) { // LWC1 (write float)
3663     emit_writeword_indexed(tl,0,temp);
3664   }
3665   if (opcode[i]==0x35) { // LDC1 (write double)
3666     emit_writeword_indexed(th,4,temp);
3667     emit_writeword_indexed(tl,0,temp);
3668   }
3669   //if(opcode[i]==0x39)
3670   /*if(opcode[i]==0x39||opcode[i]==0x31)
3671   {
3672     emit_pusha();
3673         emit_readword((int)&last_count,ECX);
3674         if(get_reg(i_regs->regmap,CCREG)<0)
3675           emit_loadreg(CCREG,HOST_CCREG);
3676         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3677         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3678         emit_writeword(HOST_CCREG,(int)&Count);
3679     emit_call((int)memdebug);
3680     emit_popa();
3681   }/**/
3682 #else
3683   cop1_unusable(i, i_regs);
3684 #endif
3685 }
3686
3687 void c2ls_assemble(int i,struct regstat *i_regs)
3688 {
3689   int s,tl;
3690   int ar;
3691   int offset;
3692   int memtarget=0,c=0;
3693   int jaddr,jaddr2=0,jaddr3,type;
3694   int agr=AGEN1+(i&1);
3695   u_int hr,reglist=0;
3696   u_int copr=(source[i]>>16)&0x1f;
3697   s=get_reg(i_regs->regmap,rs1[i]);
3698   tl=get_reg(i_regs->regmap,FTEMP);
3699   offset=imm[i];
3700   assert(rs1[i]>0);
3701   assert(tl>=0);
3702   assert(!using_tlb);
3703
3704   for(hr=0;hr<HOST_REGS;hr++) {
3705     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3706   }
3707   if(i_regs->regmap[HOST_CCREG]==CCREG)
3708     reglist&=~(1<<HOST_CCREG);
3709
3710   // get the address
3711   if (opcode[i]==0x3a) { // SWC2
3712     ar=get_reg(i_regs->regmap,agr);
3713     if(ar<0) ar=get_reg(i_regs->regmap,-1);
3714     reglist|=1<<ar;
3715   } else { // LWC2
3716     ar=tl;
3717   }
3718   if(s>=0) c=(i_regs->wasconst>>s)&1;
3719   memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3720   if (!offset&&!c&&s>=0) ar=s;
3721   assert(ar>=0);
3722
3723   if (opcode[i]==0x3a) { // SWC2
3724     cop2_get_dreg(copr,tl,HOST_TEMPREG);
3725     type=STOREW_STUB;
3726   }
3727   else
3728     type=LOADW_STUB;
3729
3730   if(c&&!memtarget) {
3731     jaddr2=(int)out;
3732     emit_jmp(0); // inline_readstub/inline_writestub?
3733   }
3734   else {
3735     if(!c) {
3736       emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3737       jaddr2=(int)out;
3738       emit_jno(0);
3739     }
3740     if (opcode[i]==0x32) { // LWC2
3741       #ifdef HOST_IMM_ADDR32
3742       if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3743       else
3744       #endif
3745       emit_readword_indexed(0,ar,tl);
3746     }
3747     if (opcode[i]==0x3a) { // SWC2
3748       #ifdef DESTRUCTIVE_SHIFT
3749       if(!offset&&!c&&s>=0) emit_mov(s,ar);
3750       #endif
3751       emit_writeword_indexed(tl,0,ar);
3752     }
3753   }
3754   if(jaddr2)
3755     add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3756   if (opcode[i]==0x3a) { // SWC2
3757 #if defined(HOST_IMM8)
3758     int ir=get_reg(i_regs->regmap,INVCP);
3759     assert(ir>=0);
3760     emit_cmpmem_indexedsr12_reg(ir,ar,1);
3761 #else
3762     emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3763 #endif
3764     #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3765     emit_callne(invalidate_addr_reg[ar]);
3766     #else
3767     jaddr3=(int)out;
3768     emit_jne(0);
3769     add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3770     #endif
3771   }
3772   if (opcode[i]==0x32) { // LWC2
3773     cop2_put_dreg(copr,tl,HOST_TEMPREG);
3774   }
3775 }
3776
3777 #ifndef multdiv_assemble
3778 void multdiv_assemble(int i,struct regstat *i_regs)
3779 {
3780   printf("Need multdiv_assemble for this architecture.\n");
3781   exit(1);
3782 }
3783 #endif
3784
3785 void mov_assemble(int i,struct regstat *i_regs)
3786 {
3787   //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3788   //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3789   if(rt1[i]) {
3790     signed char sh,sl,th,tl;
3791     th=get_reg(i_regs->regmap,rt1[i]|64);
3792     tl=get_reg(i_regs->regmap,rt1[i]);
3793     //assert(tl>=0);
3794     if(tl>=0) {
3795       sh=get_reg(i_regs->regmap,rs1[i]|64);
3796       sl=get_reg(i_regs->regmap,rs1[i]);
3797       if(sl>=0) emit_mov(sl,tl);
3798       else emit_loadreg(rs1[i],tl);
3799       if(th>=0) {
3800         if(sh>=0) emit_mov(sh,th);
3801         else emit_loadreg(rs1[i]|64,th);
3802       }
3803     }
3804   }
3805 }
3806
3807 #ifndef fconv_assemble
3808 void fconv_assemble(int i,struct regstat *i_regs)
3809 {
3810   printf("Need fconv_assemble for this architecture.\n");
3811   exit(1);
3812 }
3813 #endif
3814
3815 #if 0
3816 void float_assemble(int i,struct regstat *i_regs)
3817 {
3818   printf("Need float_assemble for this architecture.\n");
3819   exit(1);
3820 }
3821 #endif
3822
3823 void syscall_assemble(int i,struct regstat *i_regs)
3824 {
3825   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3826   assert(ccreg==HOST_CCREG);
3827   assert(!is_delayslot);
3828   emit_movimm(start+i*4,EAX); // Get PC
3829   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right?  There should probably be an extra cycle...
3830   emit_jmp((int)jump_syscall_hle); // XXX
3831 }
3832
3833 void hlecall_assemble(int i,struct regstat *i_regs)
3834 {
3835   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3836   assert(ccreg==HOST_CCREG);
3837   assert(!is_delayslot);
3838   emit_movimm(start+i*4+4,0); // Get PC
3839   emit_movimm((int)psxHLEt[source[i]&7],1);
3840   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // XXX
3841   emit_jmp((int)jump_hlecall);
3842 }
3843
3844 void intcall_assemble(int i,struct regstat *i_regs)
3845 {
3846   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3847   assert(ccreg==HOST_CCREG);
3848   assert(!is_delayslot);
3849   emit_movimm(start+i*4,0); // Get PC
3850   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3851   emit_jmp((int)jump_intcall);
3852 }
3853
3854 void ds_assemble(int i,struct regstat *i_regs)
3855 {
3856   is_delayslot=1;
3857   switch(itype[i]) {
3858     case ALU:
3859       alu_assemble(i,i_regs);break;
3860     case IMM16:
3861       imm16_assemble(i,i_regs);break;
3862     case SHIFT:
3863       shift_assemble(i,i_regs);break;
3864     case SHIFTIMM:
3865       shiftimm_assemble(i,i_regs);break;
3866     case LOAD:
3867       load_assemble(i,i_regs);break;
3868     case LOADLR:
3869       loadlr_assemble(i,i_regs);break;
3870     case STORE:
3871       store_assemble(i,i_regs);break;
3872     case STORELR:
3873       storelr_assemble(i,i_regs);break;
3874     case COP0:
3875       cop0_assemble(i,i_regs);break;
3876     case COP1:
3877       cop1_assemble(i,i_regs);break;
3878     case C1LS:
3879       c1ls_assemble(i,i_regs);break;
3880     case COP2:
3881       cop2_assemble(i,i_regs);break;
3882     case C2LS:
3883       c2ls_assemble(i,i_regs);break;
3884     case C2OP:
3885       c2op_assemble(i,i_regs);break;
3886     case FCONV:
3887       fconv_assemble(i,i_regs);break;
3888     case FLOAT:
3889       float_assemble(i,i_regs);break;
3890     case FCOMP:
3891       fcomp_assemble(i,i_regs);break;
3892     case MULTDIV:
3893       multdiv_assemble(i,i_regs);break;
3894     case MOV:
3895       mov_assemble(i,i_regs);break;
3896     case SYSCALL:
3897     case HLECALL:
3898     case INTCALL:
3899     case SPAN:
3900     case UJUMP:
3901     case RJUMP:
3902     case CJUMP:
3903     case SJUMP:
3904     case FJUMP:
3905       printf("Jump in the delay slot.  This is probably a bug.\n");
3906   }
3907   is_delayslot=0;
3908 }
3909
3910 // Is the branch target a valid internal jump?
3911 int internal_branch(uint64_t i_is32,int addr)
3912 {
3913   if(addr&1) return 0; // Indirect (register) jump
3914   if(addr>=start && addr<start+slen*4-4)
3915   {
3916     int t=(addr-start)>>2;
3917     // Delay slots are not valid branch targets
3918     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
3919     // 64 -> 32 bit transition requires a recompile
3920     /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
3921     {
3922       if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
3923       else printf("optimizable: yes\n");
3924     }*/
3925     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
3926 #ifndef FORCE32
3927     if(requires_32bit[t]&~i_is32) return 0;
3928     else
3929 #endif
3930       return 1;
3931   }
3932   return 0;
3933 }
3934
3935 #ifndef wb_invalidate
3936 void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
3937   uint64_t u,uint64_t uu)
3938 {
3939   int hr;
3940   for(hr=0;hr<HOST_REGS;hr++) {
3941     if(hr!=EXCLUDE_REG) {
3942       if(pre[hr]!=entry[hr]) {
3943         if(pre[hr]>=0) {
3944           if((dirty>>hr)&1) {
3945             if(get_reg(entry,pre[hr])<0) {
3946               if(pre[hr]<64) {
3947                 if(!((u>>pre[hr])&1)) {
3948                   emit_storereg(pre[hr],hr);
3949                   if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
3950                     emit_sarimm(hr,31,hr);
3951                     emit_storereg(pre[hr]|64,hr);
3952                   }
3953                 }
3954               }else{
3955                 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
3956                   emit_storereg(pre[hr],hr);
3957                 }
3958               }
3959             }
3960           }
3961         }
3962       }
3963     }
3964   }
3965   // Move from one register to another (no writeback)
3966   for(hr=0;hr<HOST_REGS;hr++) {
3967     if(hr!=EXCLUDE_REG) {
3968       if(pre[hr]!=entry[hr]) {
3969         if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
3970           int nr;
3971           if((nr=get_reg(entry,pre[hr]))>=0) {
3972             emit_mov(hr,nr);
3973           }
3974         }
3975       }
3976     }
3977   }
3978 }
3979 #endif
3980
3981 // Load the specified registers
3982 // This only loads the registers given as arguments because
3983 // we don't want to load things that will be overwritten
3984 void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
3985 {
3986   int hr;
3987   // Load 32-bit regs
3988   for(hr=0;hr<HOST_REGS;hr++) {
3989     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
3990       if(entry[hr]!=regmap[hr]) {
3991         if(regmap[hr]==rs1||regmap[hr]==rs2)
3992         {
3993           if(regmap[hr]==0) {
3994             emit_zeroreg(hr);
3995           }
3996           else
3997           {
3998             emit_loadreg(regmap[hr],hr);
3999           }
4000         }
4001       }
4002     }
4003   }
4004   //Load 64-bit regs
4005   for(hr=0;hr<HOST_REGS;hr++) {
4006     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4007       if(entry[hr]!=regmap[hr]) {
4008         if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
4009         {
4010           assert(regmap[hr]!=64);
4011           if((is32>>(regmap[hr]&63))&1) {
4012             int lr=get_reg(regmap,regmap[hr]-64);
4013             if(lr>=0)
4014               emit_sarimm(lr,31,hr);
4015             else
4016               emit_loadreg(regmap[hr],hr);
4017           }
4018           else
4019           {
4020             emit_loadreg(regmap[hr],hr);
4021           }
4022         }
4023       }
4024     }
4025   }
4026 }
4027
4028 // Load registers prior to the start of a loop
4029 // so that they are not loaded within the loop
4030 static void loop_preload(signed char pre[],signed char entry[])
4031 {
4032   int hr;
4033   for(hr=0;hr<HOST_REGS;hr++) {
4034     if(hr!=EXCLUDE_REG) {
4035       if(pre[hr]!=entry[hr]) {
4036         if(entry[hr]>=0) {
4037           if(get_reg(pre,entry[hr])<0) {
4038             assem_debug("loop preload:\n");
4039             //printf("loop preload: %d\n",hr);
4040             if(entry[hr]==0) {
4041               emit_zeroreg(hr);
4042             }
4043             else if(entry[hr]<TEMPREG)
4044             {
4045               emit_loadreg(entry[hr],hr);
4046             }
4047             else if(entry[hr]-64<TEMPREG)
4048             {
4049               emit_loadreg(entry[hr],hr);
4050             }
4051           }
4052         }
4053       }
4054     }
4055   }
4056 }
4057
4058 // Generate address for load/store instruction
4059 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
4060 void address_generation(int i,struct regstat *i_regs,signed char entry[])
4061 {
4062   if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
4063     int ra;
4064     int agr=AGEN1+(i&1);
4065     int mgr=MGEN1+(i&1);
4066     if(itype[i]==LOAD) {
4067       ra=get_reg(i_regs->regmap,rt1[i]);
4068       if(ra<0) ra=get_reg(i_regs->regmap,-1);
4069       assert(ra>=0);
4070     }
4071     if(itype[i]==LOADLR) {
4072       ra=get_reg(i_regs->regmap,FTEMP);
4073     }
4074     if(itype[i]==STORE||itype[i]==STORELR) {
4075       ra=get_reg(i_regs->regmap,agr);
4076       if(ra<0) ra=get_reg(i_regs->regmap,-1);
4077     }
4078     if(itype[i]==C1LS||itype[i]==C2LS) {
4079       if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
4080         ra=get_reg(i_regs->regmap,FTEMP);
4081       else { // SWC1/SDC1/SWC2/SDC2
4082         ra=get_reg(i_regs->regmap,agr);
4083         if(ra<0) ra=get_reg(i_regs->regmap,-1);
4084       }
4085     }
4086     int rs=get_reg(i_regs->regmap,rs1[i]);
4087     int rm=get_reg(i_regs->regmap,TLREG);
4088     if(ra>=0) {
4089       int offset=imm[i];
4090       int c=(i_regs->wasconst>>rs)&1;
4091       if(rs1[i]==0) {
4092         // Using r0 as a base address
4093         /*if(rm>=0) {
4094           if(!entry||entry[rm]!=mgr) {
4095             generate_map_const(offset,rm);
4096           } // else did it in the previous cycle
4097         }*/
4098         if(!entry||entry[ra]!=agr) {
4099           if (opcode[i]==0x22||opcode[i]==0x26) {
4100             emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4101           }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4102             emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4103           }else{
4104             emit_movimm(offset,ra);
4105           }
4106         } // else did it in the previous cycle
4107       }
4108       else if(rs<0) {
4109         if(!entry||entry[ra]!=rs1[i])
4110           emit_loadreg(rs1[i],ra);
4111         //if(!entry||entry[ra]!=rs1[i])
4112         //  printf("poor load scheduling!\n");
4113       }
4114       else if(c) {
4115         if(rm>=0) {
4116           if(!entry||entry[rm]!=mgr) {
4117             if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
4118               // Stores to memory go thru the mapper to detect self-modifying
4119               // code, loads don't.
4120               if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
4121                  (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
4122                 generate_map_const(constmap[i][rs]+offset,rm);
4123             }else{
4124               if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
4125                 generate_map_const(constmap[i][rs]+offset,rm);
4126             }
4127           }
4128         }
4129         if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
4130           if(!entry||entry[ra]!=agr) {
4131             if (opcode[i]==0x22||opcode[i]==0x26) {
4132               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4133             }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4134               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4135             }else{
4136               #ifdef HOST_IMM_ADDR32
4137               if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4138                  (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4139               #endif
4140               emit_movimm(constmap[i][rs]+offset,ra);
4141             }
4142           } // else did it in the previous cycle
4143         } // else load_consts already did it
4144       }
4145       if(offset&&!c&&rs1[i]) {
4146         if(rs>=0) {
4147           emit_addimm(rs,offset,ra);
4148         }else{
4149           emit_addimm(ra,offset,ra);
4150         }
4151       }
4152     }
4153   }
4154   // Preload constants for next instruction
4155   if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
4156     int agr,ra;
4157     #ifndef HOST_IMM_ADDR32
4158     // Mapper entry
4159     agr=MGEN1+((i+1)&1);
4160     ra=get_reg(i_regs->regmap,agr);
4161     if(ra>=0) {
4162       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4163       int offset=imm[i+1];
4164       int c=(regs[i+1].wasconst>>rs)&1;
4165       if(c) {
4166         if(itype[i+1]==STORE||itype[i+1]==STORELR
4167            ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
4168           // Stores to memory go thru the mapper to detect self-modifying
4169           // code, loads don't.
4170           if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4171              (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
4172             generate_map_const(constmap[i+1][rs]+offset,ra);
4173         }else{
4174           if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4175             generate_map_const(constmap[i+1][rs]+offset,ra);
4176         }
4177       }
4178       /*else if(rs1[i]==0) {
4179         generate_map_const(offset,ra);
4180       }*/
4181     }
4182     #endif
4183     // Actual address
4184     agr=AGEN1+((i+1)&1);
4185     ra=get_reg(i_regs->regmap,agr);
4186     if(ra>=0) {
4187       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4188       int offset=imm[i+1];
4189       int c=(regs[i+1].wasconst>>rs)&1;
4190       if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4191         if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4192           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4193         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4194           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4195         }else{
4196           #ifdef HOST_IMM_ADDR32
4197           if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4198              (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4199           #endif
4200           emit_movimm(constmap[i+1][rs]+offset,ra);
4201         }
4202       }
4203       else if(rs1[i+1]==0) {
4204         // Using r0 as a base address
4205         if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4206           emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4207         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4208           emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4209         }else{
4210           emit_movimm(offset,ra);
4211         }
4212       }
4213     }
4214   }
4215 }
4216
4217 int get_final_value(int hr, int i, int *value)
4218 {
4219   int reg=regs[i].regmap[hr];
4220   while(i<slen-1) {
4221     if(regs[i+1].regmap[hr]!=reg) break;
4222     if(!((regs[i+1].isconst>>hr)&1)) break;
4223     if(bt[i+1]) break;
4224     i++;
4225   }
4226   if(i<slen-1) {
4227     if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4228       *value=constmap[i][hr];
4229       return 1;
4230     }
4231     if(!bt[i+1]) {
4232       if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4233         // Load in delay slot, out-of-order execution
4234         if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4235         {
4236           #ifdef HOST_IMM_ADDR32
4237           if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4238           #endif
4239           // Precompute load address
4240           *value=constmap[i][hr]+imm[i+2];
4241           return 1;
4242         }
4243       }
4244       if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4245       {
4246         #ifdef HOST_IMM_ADDR32
4247         if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4248         #endif
4249         // Precompute load address
4250         *value=constmap[i][hr]+imm[i+1];
4251         //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4252         return 1;
4253       }
4254     }
4255   }
4256   *value=constmap[i][hr];
4257   //printf("c=%x\n",(int)constmap[i][hr]);
4258   if(i==slen-1) return 1;
4259   if(reg<64) {
4260     return !((unneeded_reg[i+1]>>reg)&1);
4261   }else{
4262     return !((unneeded_reg_upper[i+1]>>reg)&1);
4263   }
4264 }
4265
4266 // Load registers with known constants
4267 void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4268 {
4269   int hr;
4270   // Load 32-bit regs
4271   for(hr=0;hr<HOST_REGS;hr++) {
4272     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4273       //if(entry[hr]!=regmap[hr]) {
4274       if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4275         if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4276           int value;
4277           if(get_final_value(hr,i,&value)) {
4278             if(value==0) {
4279               emit_zeroreg(hr);
4280             }
4281             else {
4282               emit_movimm(value,hr);
4283             }
4284           }
4285         }
4286       }
4287     }
4288   }
4289   // Load 64-bit regs
4290   for(hr=0;hr<HOST_REGS;hr++) {
4291     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4292       //if(entry[hr]!=regmap[hr]) {
4293       if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4294         if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4295           if((is32>>(regmap[hr]&63))&1) {
4296             int lr=get_reg(regmap,regmap[hr]-64);
4297             assert(lr>=0);
4298             emit_sarimm(lr,31,hr);
4299           }
4300           else
4301           {
4302             int value;
4303             if(get_final_value(hr,i,&value)) {
4304               if(value==0) {
4305                 emit_zeroreg(hr);
4306               }
4307               else {
4308                 emit_movimm(value,hr);
4309               }
4310             }
4311           }
4312         }
4313       }
4314     }
4315   }
4316 }
4317 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4318 {
4319   int hr;
4320   // Load 32-bit regs
4321   for(hr=0;hr<HOST_REGS;hr++) {
4322     if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4323       if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4324         int value=constmap[i][hr];
4325         if(value==0) {
4326           emit_zeroreg(hr);
4327         }
4328         else {
4329           emit_movimm(value,hr);
4330         }
4331       }
4332     }
4333   }
4334   // Load 64-bit regs
4335   for(hr=0;hr<HOST_REGS;hr++) {
4336     if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4337       if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4338         if((is32>>(regmap[hr]&63))&1) {
4339           int lr=get_reg(regmap,regmap[hr]-64);
4340           assert(lr>=0);
4341           emit_sarimm(lr,31,hr);
4342         }
4343         else
4344         {
4345           int value=constmap[i][hr];
4346           if(value==0) {
4347             emit_zeroreg(hr);
4348           }
4349           else {
4350             emit_movimm(value,hr);
4351           }
4352         }
4353       }
4354     }
4355   }
4356 }
4357
4358 // Write out all dirty registers (except cycle count)
4359 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4360 {
4361   int hr;
4362   for(hr=0;hr<HOST_REGS;hr++) {
4363     if(hr!=EXCLUDE_REG) {
4364       if(i_regmap[hr]>0) {
4365         if(i_regmap[hr]!=CCREG) {
4366           if((i_dirty>>hr)&1) {
4367             if(i_regmap[hr]<64) {
4368               emit_storereg(i_regmap[hr],hr);
4369 #ifndef FORCE32
4370               if( ((i_is32>>i_regmap[hr])&1) ) {
4371                 #ifdef DESTRUCTIVE_WRITEBACK
4372                 emit_sarimm(hr,31,hr);
4373                 emit_storereg(i_regmap[hr]|64,hr);
4374                 #else
4375                 emit_sarimm(hr,31,HOST_TEMPREG);
4376                 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4377                 #endif
4378               }
4379 #endif
4380             }else{
4381               if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4382                 emit_storereg(i_regmap[hr],hr);
4383               }
4384             }
4385           }
4386         }
4387       }
4388     }
4389   }
4390 }
4391 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4392 // This writes the registers not written by store_regs_bt
4393 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4394 {
4395   int hr;
4396   int t=(addr-start)>>2;
4397   for(hr=0;hr<HOST_REGS;hr++) {
4398     if(hr!=EXCLUDE_REG) {
4399       if(i_regmap[hr]>0) {
4400         if(i_regmap[hr]!=CCREG) {
4401           if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4402             if((i_dirty>>hr)&1) {
4403               if(i_regmap[hr]<64) {
4404                 emit_storereg(i_regmap[hr],hr);
4405 #ifndef FORCE32
4406                 if( ((i_is32>>i_regmap[hr])&1) ) {
4407                   #ifdef DESTRUCTIVE_WRITEBACK
4408                   emit_sarimm(hr,31,hr);
4409                   emit_storereg(i_regmap[hr]|64,hr);
4410                   #else
4411                   emit_sarimm(hr,31,HOST_TEMPREG);
4412                   emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4413                   #endif
4414                 }
4415 #endif
4416               }else{
4417                 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4418                   emit_storereg(i_regmap[hr],hr);
4419                 }
4420               }
4421             }
4422           }
4423         }
4424       }
4425     }
4426   }
4427 }
4428
4429 // Load all registers (except cycle count)
4430 void load_all_regs(signed char i_regmap[])
4431 {
4432   int hr;
4433   for(hr=0;hr<HOST_REGS;hr++) {
4434     if(hr!=EXCLUDE_REG) {
4435       if(i_regmap[hr]==0) {
4436         emit_zeroreg(hr);
4437       }
4438       else
4439       if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG)
4440       {
4441         emit_loadreg(i_regmap[hr],hr);
4442       }
4443     }
4444   }
4445 }
4446
4447 // Load all current registers also needed by next instruction
4448 void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4449 {
4450   int hr;
4451   for(hr=0;hr<HOST_REGS;hr++) {
4452     if(hr!=EXCLUDE_REG) {
4453       if(get_reg(next_regmap,i_regmap[hr])>=0) {
4454         if(i_regmap[hr]==0) {
4455           emit_zeroreg(hr);
4456         }
4457         else
4458         if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG)
4459         {
4460           emit_loadreg(i_regmap[hr],hr);
4461         }
4462       }
4463     }
4464   }
4465 }
4466
4467 // Load all regs, storing cycle count if necessary
4468 void load_regs_entry(int t)
4469 {
4470   int hr;
4471   if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER,HOST_CCREG);
4472   else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t]*CLOCK_DIVIDER,HOST_CCREG);
4473   if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4474     emit_storereg(CCREG,HOST_CCREG);
4475   }
4476   // Load 32-bit regs
4477   for(hr=0;hr<HOST_REGS;hr++) {
4478     if(regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<64) {
4479       if(regs[t].regmap_entry[hr]==0) {
4480         emit_zeroreg(hr);
4481       }
4482       else if(regs[t].regmap_entry[hr]!=CCREG)
4483       {
4484         emit_loadreg(regs[t].regmap_entry[hr],hr);
4485       }
4486     }
4487   }
4488   // Load 64-bit regs
4489   for(hr=0;hr<HOST_REGS;hr++) {
4490     if(regs[t].regmap_entry[hr]>=64) {
4491       assert(regs[t].regmap_entry[hr]!=64);
4492       if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4493         int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4494         if(lr<0) {
4495           emit_loadreg(regs[t].regmap_entry[hr],hr);
4496         }
4497         else
4498         {
4499           emit_sarimm(lr,31,hr);
4500         }
4501       }
4502       else
4503       {
4504         emit_loadreg(regs[t].regmap_entry[hr],hr);
4505       }
4506     }
4507   }
4508 }
4509
4510 // Store dirty registers prior to branch
4511 void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4512 {
4513   if(internal_branch(i_is32,addr))
4514   {
4515     int t=(addr-start)>>2;
4516     int hr;
4517     for(hr=0;hr<HOST_REGS;hr++) {
4518       if(hr!=EXCLUDE_REG) {
4519         if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4520           if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4521             if((i_dirty>>hr)&1) {
4522               if(i_regmap[hr]<64) {
4523                 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4524                   emit_storereg(i_regmap[hr],hr);
4525                   if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4526                     #ifdef DESTRUCTIVE_WRITEBACK
4527                     emit_sarimm(hr,31,hr);
4528                     emit_storereg(i_regmap[hr]|64,hr);
4529                     #else
4530                     emit_sarimm(hr,31,HOST_TEMPREG);
4531                     emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4532                     #endif
4533                   }
4534                 }
4535               }else{
4536                 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4537                   emit_storereg(i_regmap[hr],hr);
4538                 }
4539               }
4540             }
4541           }
4542         }
4543       }
4544     }
4545   }
4546   else
4547   {
4548     // Branch out of this block, write out all dirty regs
4549     wb_dirtys(i_regmap,i_is32,i_dirty);
4550   }
4551 }
4552
4553 // Load all needed registers for branch target
4554 void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4555 {
4556   //if(addr>=start && addr<(start+slen*4))
4557   if(internal_branch(i_is32,addr))
4558   {
4559     int t=(addr-start)>>2;
4560     int hr;
4561     // Store the cycle count before loading something else
4562     if(i_regmap[HOST_CCREG]!=CCREG) {
4563       assert(i_regmap[HOST_CCREG]==-1);
4564     }
4565     if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4566       emit_storereg(CCREG,HOST_CCREG);
4567     }
4568     // Load 32-bit regs
4569     for(hr=0;hr<HOST_REGS;hr++) {
4570       if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<64) {
4571         #ifdef DESTRUCTIVE_WRITEBACK
4572         if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4573         #else
4574         if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4575         #endif
4576           if(regs[t].regmap_entry[hr]==0) {
4577             emit_zeroreg(hr);
4578           }
4579           else if(regs[t].regmap_entry[hr]!=CCREG)
4580           {
4581             emit_loadreg(regs[t].regmap_entry[hr],hr);
4582           }
4583         }
4584       }
4585     }
4586     //Load 64-bit regs
4587     for(hr=0;hr<HOST_REGS;hr++) {
4588       if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=64) {
4589         if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4590           assert(regs[t].regmap_entry[hr]!=64);
4591           if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4592             int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4593             if(lr<0) {
4594               emit_loadreg(regs[t].regmap_entry[hr],hr);
4595             }
4596             else
4597             {
4598               emit_sarimm(lr,31,hr);
4599             }
4600           }
4601           else
4602           {
4603             emit_loadreg(regs[t].regmap_entry[hr],hr);
4604           }
4605         }
4606         else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4607           int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4608           assert(lr>=0);
4609           emit_sarimm(lr,31,hr);
4610         }
4611       }
4612     }
4613   }
4614 }
4615
4616 int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4617 {
4618   if(addr>=start && addr<start+slen*4-4)
4619   {
4620     int t=(addr-start)>>2;
4621     int hr;
4622     if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4623     for(hr=0;hr<HOST_REGS;hr++)
4624     {
4625       if(hr!=EXCLUDE_REG)
4626       {
4627         if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4628         {
4629           if(regs[t].regmap_entry[hr]!=-1)
4630           {
4631             return 0;
4632           }
4633           else
4634           if((i_dirty>>hr)&1)
4635           {
4636             if(i_regmap[hr]<64)
4637             {
4638               if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4639                 return 0;
4640             }
4641             else
4642             {
4643               if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4644                 return 0;
4645             }
4646           }
4647         }
4648         else // Same register but is it 32-bit or dirty?
4649         if(i_regmap[hr]>=0)
4650         {
4651           if(!((regs[t].dirty>>hr)&1))
4652           {
4653             if((i_dirty>>hr)&1)
4654             {
4655               if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4656               {
4657                 //printf("%x: dirty no match\n",addr);
4658                 return 0;
4659               }
4660             }
4661           }
4662           if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4663           {
4664             //printf("%x: is32 no match\n",addr);
4665             return 0;
4666           }
4667         }
4668       }
4669     }
4670     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4671 #ifndef FORCE32
4672     if(requires_32bit[t]&~i_is32) return 0;
4673 #endif
4674     // Delay slots are not valid branch targets
4675     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4676     // Delay slots require additional processing, so do not match
4677     if(is_ds[t]) return 0;
4678   }
4679   else
4680   {
4681     int hr;
4682     for(hr=0;hr<HOST_REGS;hr++)
4683     {
4684       if(hr!=EXCLUDE_REG)
4685       {
4686         if(i_regmap[hr]>=0)
4687         {
4688           if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4689           {
4690             if((i_dirty>>hr)&1)
4691             {
4692               return 0;
4693             }
4694           }
4695         }
4696       }
4697     }
4698   }
4699   return 1;
4700 }
4701
4702 // Used when a branch jumps into the delay slot of another branch
4703 void ds_assemble_entry(int i)
4704 {
4705   int t=(ba[i]-start)>>2;
4706   if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4707   assem_debug("Assemble delay slot at %x\n",ba[i]);
4708   assem_debug("<->\n");
4709   if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
4710     wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4711   load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4712   address_generation(t,&regs[t],regs[t].regmap_entry);
4713   if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
4714     load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4715   cop1_usable=0;
4716   is_delayslot=0;
4717   switch(itype[t]) {
4718     case ALU:
4719       alu_assemble(t,&regs[t]);break;
4720     case IMM16:
4721       imm16_assemble(t,&regs[t]);break;
4722     case SHIFT:
4723       shift_assemble(t,&regs[t]);break;
4724     case SHIFTIMM:
4725       shiftimm_assemble(t,&regs[t]);break;
4726     case LOAD:
4727       load_assemble(t,&regs[t]);break;
4728     case LOADLR:
4729       loadlr_assemble(t,&regs[t]);break;
4730     case STORE:
4731       store_assemble(t,&regs[t]);break;
4732     case STORELR:
4733       storelr_assemble(t,&regs[t]);break;
4734     case COP0:
4735       cop0_assemble(t,&regs[t]);break;
4736     case COP1:
4737       cop1_assemble(t,&regs[t]);break;
4738     case C1LS:
4739       c1ls_assemble(t,&regs[t]);break;
4740     case COP2:
4741       cop2_assemble(t,&regs[t]);break;
4742     case C2LS:
4743       c2ls_assemble(t,&regs[t]);break;
4744     case C2OP:
4745       c2op_assemble(t,&regs[t]);break;
4746     case FCONV:
4747       fconv_assemble(t,&regs[t]);break;
4748     case FLOAT:
4749       float_assemble(t,&regs[t]);break;
4750     case FCOMP:
4751       fcomp_assemble(t,&regs[t]);break;
4752     case MULTDIV:
4753       multdiv_assemble(t,&regs[t]);break;
4754     case MOV:
4755       mov_assemble(t,&regs[t]);break;
4756     case SYSCALL:
4757     case HLECALL:
4758     case INTCALL:
4759     case SPAN:
4760     case UJUMP:
4761     case RJUMP:
4762     case CJUMP:
4763     case SJUMP:
4764     case FJUMP:
4765       printf("Jump in the delay slot.  This is probably a bug.\n");
4766   }
4767   store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4768   load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4769   if(internal_branch(regs[t].is32,ba[i]+4))
4770     assem_debug("branch: internal\n");
4771   else
4772     assem_debug("branch: external\n");
4773   assert(internal_branch(regs[t].is32,ba[i]+4));
4774   add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4775   emit_jmp(0);
4776 }
4777
4778 void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4779 {
4780   int count;
4781   int jaddr;
4782   int idle=0;
4783   if(itype[i]==RJUMP)
4784   {
4785     *adj=0;
4786   }
4787   //if(ba[i]>=start && ba[i]<(start+slen*4))
4788   if(internal_branch(branch_regs[i].is32,ba[i]))
4789   {
4790     int t=(ba[i]-start)>>2;
4791     if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4792     else *adj=ccadj[t];
4793   }
4794   else
4795   {
4796     *adj=0;
4797   }
4798   count=ccadj[i];
4799   if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4800     // Idle loop
4801     if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4802     idle=(int)out;
4803     //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4804     emit_andimm(HOST_CCREG,3,HOST_CCREG);
4805     jaddr=(int)out;
4806     emit_jmp(0);
4807   }
4808   else if(*adj==0||invert) {
4809     emit_addimm_and_set_flags(CLOCK_DIVIDER*(count+2),HOST_CCREG);
4810     jaddr=(int)out;
4811     emit_jns(0);
4812   }
4813   else
4814   {
4815     emit_cmpimm(HOST_CCREG,-2*(count+2));
4816     jaddr=(int)out;
4817     emit_jns(0);
4818   }
4819   add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4820 }
4821
4822 void do_ccstub(int n)
4823 {
4824   literal_pool(256);
4825   assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
4826   set_jump_target(stubs[n][1],(int)out);
4827   int i=stubs[n][4];
4828   if(stubs[n][6]==NULLDS) {
4829     // Delay slot instruction is nullified ("likely" branch)
4830     wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4831   }
4832   else if(stubs[n][6]!=TAKEN) {
4833     wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4834   }
4835   else {
4836     if(internal_branch(branch_regs[i].is32,ba[i]))
4837       wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4838   }
4839   if(stubs[n][5]!=-1)
4840   {
4841     // Save PC as return address
4842     emit_movimm(stubs[n][5],EAX);
4843     emit_writeword(EAX,(int)&pcaddr);
4844   }
4845   else
4846   {
4847     // Return address depends on which way the branch goes
4848     if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
4849     {
4850       int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4851       int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4852       int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4853       int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4854       if(rs1[i]==0)
4855       {
4856         s1l=s2l;s1h=s2h;
4857         s2l=s2h=-1;
4858       }
4859       else if(rs2[i]==0)
4860       {
4861         s2l=s2h=-1;
4862       }
4863       if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
4864         s1h=s2h=-1;
4865       }
4866       assert(s1l>=0);
4867       #ifdef DESTRUCTIVE_WRITEBACK
4868       if(rs1[i]) {
4869         if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
4870           emit_loadreg(rs1[i],s1l);
4871       }
4872       else {
4873         if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
4874           emit_loadreg(rs2[i],s1l);
4875       }
4876       if(s2l>=0)
4877         if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
4878           emit_loadreg(rs2[i],s2l);
4879       #endif
4880       int hr=0;
4881       int addr,alt,ntaddr;
4882       while(hr<HOST_REGS)
4883       {
4884         if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4885            (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4886            (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4887         {
4888           addr=hr++;break;
4889         }
4890         hr++;
4891       }
4892       while(hr<HOST_REGS)
4893       {
4894         if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4895            (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4896            (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4897         {
4898           alt=hr++;break;
4899         }
4900         hr++;
4901       }
4902       if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
4903       {
4904         while(hr<HOST_REGS)
4905         {
4906           if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4907              (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4908              (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4909           {
4910             ntaddr=hr;break;
4911           }
4912           hr++;
4913         }
4914         assert(hr<HOST_REGS);
4915       }
4916       if((opcode[i]&0x2f)==4) // BEQ
4917       {
4918         #ifdef HAVE_CMOV_IMM
4919         if(s1h<0) {
4920           if(s2l>=0) emit_cmp(s1l,s2l);
4921           else emit_test(s1l,s1l);
4922           emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
4923         }
4924         else
4925         #endif
4926         {
4927           emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4928           if(s1h>=0) {
4929             if(s2h>=0) emit_cmp(s1h,s2h);
4930             else emit_test(s1h,s1h);
4931             emit_cmovne_reg(alt,addr);
4932           }
4933           if(s2l>=0) emit_cmp(s1l,s2l);
4934           else emit_test(s1l,s1l);
4935           emit_cmovne_reg(alt,addr);
4936         }
4937       }
4938       if((opcode[i]&0x2f)==5) // BNE
4939       {
4940         #ifdef HAVE_CMOV_IMM
4941         if(s1h<0) {
4942           if(s2l>=0) emit_cmp(s1l,s2l);
4943           else emit_test(s1l,s1l);
4944           emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
4945         }
4946         else
4947         #endif
4948         {
4949           emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
4950           if(s1h>=0) {
4951             if(s2h>=0) emit_cmp(s1h,s2h);
4952             else emit_test(s1h,s1h);
4953             emit_cmovne_reg(alt,addr);
4954           }
4955           if(s2l>=0) emit_cmp(s1l,s2l);
4956           else emit_test(s1l,s1l);
4957           emit_cmovne_reg(alt,addr);
4958         }
4959       }
4960       if((opcode[i]&0x2f)==6) // BLEZ
4961       {
4962         //emit_movimm(ba[i],alt);
4963         //emit_movimm(start+i*4+8,addr);
4964         emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4965         emit_cmpimm(s1l,1);
4966         if(s1h>=0) emit_mov(addr,ntaddr);
4967         emit_cmovl_reg(alt,addr);
4968         if(s1h>=0) {
4969           emit_test(s1h,s1h);
4970           emit_cmovne_reg(ntaddr,addr);
4971           emit_cmovs_reg(alt,addr);
4972         }
4973       }
4974       if((opcode[i]&0x2f)==7) // BGTZ
4975       {
4976         //emit_movimm(ba[i],addr);
4977         //emit_movimm(start+i*4+8,ntaddr);
4978         emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
4979         emit_cmpimm(s1l,1);
4980         if(s1h>=0) emit_mov(addr,alt);
4981         emit_cmovl_reg(ntaddr,addr);
4982         if(s1h>=0) {
4983           emit_test(s1h,s1h);
4984           emit_cmovne_reg(alt,addr);
4985           emit_cmovs_reg(ntaddr,addr);
4986         }
4987       }
4988       if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
4989       {
4990         //emit_movimm(ba[i],alt);
4991         //emit_movimm(start+i*4+8,addr);
4992         emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4993         if(s1h>=0) emit_test(s1h,s1h);
4994         else emit_test(s1l,s1l);
4995         emit_cmovs_reg(alt,addr);
4996       }
4997       if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
4998       {
4999         //emit_movimm(ba[i],addr);
5000         //emit_movimm(start+i*4+8,alt);
5001         emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5002         if(s1h>=0) emit_test(s1h,s1h);
5003         else emit_test(s1l,s1l);
5004         emit_cmovs_reg(alt,addr);
5005       }
5006       if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
5007         if(source[i]&0x10000) // BC1T
5008         {
5009           //emit_movimm(ba[i],alt);
5010           //emit_movimm(start+i*4+8,addr);
5011           emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5012           emit_testimm(s1l,0x800000);
5013           emit_cmovne_reg(alt,addr);
5014         }
5015         else // BC1F
5016         {
5017           //emit_movimm(ba[i],addr);
5018           //emit_movimm(start+i*4+8,alt);
5019           emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5020           emit_testimm(s1l,0x800000);
5021           emit_cmovne_reg(alt,addr);
5022         }
5023       }
5024       emit_writeword(addr,(int)&pcaddr);
5025     }
5026     else
5027     if(itype[i]==RJUMP)
5028     {
5029       int r=get_reg(branch_regs[i].regmap,rs1[i]);
5030       if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5031         r=get_reg(branch_regs[i].regmap,RTEMP);
5032       }
5033       emit_writeword(r,(int)&pcaddr);
5034     }
5035     else {printf("Unknown branch type in do_ccstub\n");exit(1);}
5036   }
5037   // Update cycle count
5038   assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5039   if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
5040   emit_call((int)cc_interrupt);
5041   if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
5042   if(stubs[n][6]==TAKEN) {
5043     if(internal_branch(branch_regs[i].is32,ba[i]))
5044       load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
5045     else if(itype[i]==RJUMP) {
5046       if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5047         emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5048       else
5049         emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
5050     }
5051   }else if(stubs[n][6]==NOTTAKEN) {
5052     if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5053     else load_all_regs(branch_regs[i].regmap);
5054   }else if(stubs[n][6]==NULLDS) {
5055     // Delay slot instruction is nullified ("likely" branch)
5056     if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5057     else load_all_regs(regs[i].regmap);
5058   }else{
5059     load_all_regs(branch_regs[i].regmap);
5060   }
5061   emit_jmp(stubs[n][2]); // return address
5062
5063   /* This works but uses a lot of memory...
5064   emit_readword((int)&last_count,ECX);
5065   emit_add(HOST_CCREG,ECX,EAX);
5066   emit_writeword(EAX,(int)&Count);
5067   emit_call((int)gen_interupt);
5068   emit_readword((int)&Count,HOST_CCREG);
5069   emit_readword((int)&next_interupt,EAX);
5070   emit_readword((int)&pending_exception,EBX);
5071   emit_writeword(EAX,(int)&last_count);
5072   emit_sub(HOST_CCREG,EAX,HOST_CCREG);
5073   emit_test(EBX,EBX);
5074   int jne_instr=(int)out;
5075   emit_jne(0);
5076   if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
5077   load_all_regs(branch_regs[i].regmap);
5078   emit_jmp(stubs[n][2]); // return address
5079   set_jump_target(jne_instr,(int)out);
5080   emit_readword((int)&pcaddr,EAX);
5081   // Call get_addr_ht instead of doing the hash table here.
5082   // This code is executed infrequently and takes up a lot of space
5083   // so smaller is better.
5084   emit_storereg(CCREG,HOST_CCREG);
5085   emit_pushreg(EAX);
5086   emit_call((int)get_addr_ht);
5087   emit_loadreg(CCREG,HOST_CCREG);
5088   emit_addimm(ESP,4,ESP);
5089   emit_jmpreg(EAX);*/
5090 }
5091
5092 add_to_linker(int addr,int target,int ext)
5093 {
5094   link_addr[linkcount][0]=addr;
5095   link_addr[linkcount][1]=target;
5096   link_addr[linkcount][2]=ext;
5097   linkcount++;
5098 }
5099
5100 void ujump_assemble(int i,struct regstat *i_regs)
5101 {
5102   signed char *i_regmap=i_regs->regmap;
5103   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5104   address_generation(i+1,i_regs,regs[i].regmap_entry);
5105   #ifdef REG_PREFETCH
5106   int temp=get_reg(branch_regs[i].regmap,PTEMP);
5107   if(rt1[i]==31&&temp>=0)
5108   {
5109     int return_address=start+i*4+8;
5110     if(get_reg(branch_regs[i].regmap,31)>0)
5111     if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5112   }
5113   #endif
5114   if(rt1[i]==31) {
5115     int rt;
5116     unsigned int return_address;
5117     rt=get_reg(branch_regs[i].regmap,31);
5118     assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5119     //assert(rt>=0);
5120     return_address=start+i*4+8;
5121     if(rt>=0) {
5122       #ifdef USE_MINI_HT
5123       if(internal_branch(branch_regs[i].is32,return_address)&&rt1[i+1]!=31) {
5124         int temp=-1; // note: must be ds-safe
5125         #ifdef HOST_TEMPREG
5126         temp=HOST_TEMPREG;
5127         #endif
5128         if(temp>=0) do_miniht_insert(return_address,rt,temp);
5129         else emit_movimm(return_address,rt);
5130       }
5131       else
5132       #endif
5133       {
5134         #ifdef REG_PREFETCH
5135         if(temp>=0)
5136         {
5137           if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5138         }
5139         #endif
5140         emit_movimm(return_address,rt); // PC into link register
5141         #ifdef IMM_PREFETCH
5142         emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5143         #endif
5144       }
5145     }
5146   }
5147   ds_assemble(i+1,i_regs);
5148   uint64_t bc_unneeded=branch_regs[i].u;
5149   uint64_t bc_unneeded_upper=branch_regs[i].uu;
5150   bc_unneeded|=1|(1LL<<rt1[i]);
5151   bc_unneeded_upper|=1|(1LL<<rt1[i]);
5152   wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5153                 bc_unneeded,bc_unneeded_upper);
5154   load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5155   int cc,adj;
5156   cc=get_reg(branch_regs[i].regmap,CCREG);
5157   assert(cc==HOST_CCREG);
5158   store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5159   #ifdef REG_PREFETCH
5160   if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5161   #endif
5162   do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5163   if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5164   load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5165   if(internal_branch(branch_regs[i].is32,ba[i]))
5166     assem_debug("branch: internal\n");
5167   else
5168     assem_debug("branch: external\n");
5169   if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5170     ds_assemble_entry(i);
5171   }
5172   else {
5173     add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5174     emit_jmp(0);
5175   }
5176 }
5177
5178 void rjump_assemble(int i,struct regstat *i_regs)
5179 {
5180   signed char *i_regmap=i_regs->regmap;
5181   int temp;
5182   int rs,cc,adj;
5183   rs=get_reg(branch_regs[i].regmap,rs1[i]);
5184   assert(rs>=0);
5185   if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5186     // Delay slot abuse, make a copy of the branch address register
5187     temp=get_reg(branch_regs[i].regmap,RTEMP);
5188     assert(temp>=0);
5189     assert(regs[i].regmap[temp]==RTEMP);
5190     emit_mov(rs,temp);
5191     rs=temp;
5192   }
5193   address_generation(i+1,i_regs,regs[i].regmap_entry);
5194   #ifdef REG_PREFETCH
5195   if(rt1[i]==31)
5196   {
5197     if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5198       int return_address=start+i*4+8;
5199       if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5200     }
5201   }
5202   #endif
5203   #ifdef USE_MINI_HT
5204   if(rs1[i]==31) {
5205     int rh=get_reg(regs[i].regmap,RHASH);
5206     if(rh>=0) do_preload_rhash(rh);
5207   }
5208   #endif
5209   ds_assemble(i+1,i_regs);
5210   uint64_t bc_unneeded=branch_regs[i].u;
5211   uint64_t bc_unneeded_upper=branch_regs[i].uu;
5212   bc_unneeded|=1|(1LL<<rt1[i]);
5213   bc_unneeded_upper|=1|(1LL<<rt1[i]);
5214   bc_unneeded&=~(1LL<<rs1[i]);
5215   wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5216                 bc_unneeded,bc_unneeded_upper);
5217   load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5218   if(rt1[i]!=0) {
5219     int rt,return_address;
5220     assert(rt1[i+1]!=rt1[i]);
5221     assert(rt2[i+1]!=rt1[i]);
5222     rt=get_reg(branch_regs[i].regmap,rt1[i]);
5223     assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5224     assert(rt>=0);
5225     return_address=start+i*4+8;
5226     #ifdef REG_PREFETCH
5227     if(temp>=0)
5228     {
5229       if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5230     }
5231     #endif
5232     emit_movimm(return_address,rt); // PC into link register
5233     #ifdef IMM_PREFETCH
5234     emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5235     #endif
5236   }
5237   cc=get_reg(branch_regs[i].regmap,CCREG);
5238   assert(cc==HOST_CCREG);
5239   #ifdef USE_MINI_HT
5240   int rh=get_reg(branch_regs[i].regmap,RHASH);
5241   int ht=get_reg(branch_regs[i].regmap,RHTBL);
5242   if(rs1[i]==31) {
5243     if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5244     do_preload_rhtbl(ht);
5245     do_rhash(rs,rh);
5246   }
5247   #endif
5248   store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5249   #ifdef DESTRUCTIVE_WRITEBACK
5250   if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5251     if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5252       emit_loadreg(rs1[i],rs);
5253     }
5254   }
5255   #endif
5256   #ifdef REG_PREFETCH
5257   if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5258   #endif
5259   #ifdef USE_MINI_HT
5260   if(rs1[i]==31) {
5261     do_miniht_load(ht,rh);
5262   }
5263   #endif
5264   //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5265   //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5266   //assert(adj==0);
5267   emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5268   add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5269   emit_jns(0);
5270   //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5271   #ifdef USE_MINI_HT
5272   if(rs1[i]==31) {
5273     do_miniht_jump(rs,rh,ht);
5274   }
5275   else
5276   #endif
5277   {
5278     //if(rs!=EAX) emit_mov(rs,EAX);
5279     //emit_jmp((int)jump_vaddr_eax);
5280     emit_jmp(jump_vaddr_reg[rs]);
5281   }
5282   /* Check hash table
5283   temp=!rs;
5284   emit_mov(rs,temp);
5285   emit_shrimm(rs,16,rs);
5286   emit_xor(temp,rs,rs);
5287   emit_movzwl_reg(rs,rs);
5288   emit_shlimm(rs,4,rs);
5289   emit_cmpmem_indexed((int)hash_table,rs,temp);
5290   emit_jne((int)out+14);
5291   emit_readword_indexed((int)hash_table+4,rs,rs);
5292   emit_jmpreg(rs);
5293   emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5294   emit_addimm_no_flags(8,rs);
5295   emit_jeq((int)out-17);
5296   // No hit on hash table, call compiler
5297   emit_pushreg(temp);
5298 //DEBUG >
5299 #ifdef DEBUG_CYCLE_COUNT
5300   emit_readword((int)&last_count,ECX);
5301   emit_add(HOST_CCREG,ECX,HOST_CCREG);
5302   emit_readword((int)&next_interupt,ECX);
5303   emit_writeword(HOST_CCREG,(int)&Count);
5304   emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5305   emit_writeword(ECX,(int)&last_count);
5306 #endif
5307 //DEBUG <
5308   emit_storereg(CCREG,HOST_CCREG);
5309   emit_call((int)get_addr);
5310   emit_loadreg(CCREG,HOST_CCREG);
5311   emit_addimm(ESP,4,ESP);
5312   emit_jmpreg(EAX);*/
5313   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5314   if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5315   #endif
5316 }
5317
5318 void cjump_assemble(int i,struct regstat *i_regs)
5319 {
5320   signed char *i_regmap=i_regs->regmap;
5321   int cc;
5322   int match;
5323   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5324   assem_debug("match=%d\n",match);
5325   int s1h,s1l,s2h,s2l;
5326   int prev_cop1_usable=cop1_usable;
5327   int unconditional=0,nop=0;
5328   int only32=0;
5329   int invert=0;
5330   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5331   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5332   if(!match) invert=1;
5333   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5334   if(i>(ba[i]-start)>>2) invert=1;
5335   #endif
5336
5337   if(ooo[i]) {
5338     s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5339     s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5340     s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5341     s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5342   }
5343   else {
5344     s1l=get_reg(i_regmap,rs1[i]);
5345     s1h=get_reg(i_regmap,rs1[i]|64);
5346     s2l=get_reg(i_regmap,rs2[i]);
5347     s2h=get_reg(i_regmap,rs2[i]|64);
5348   }
5349   if(rs1[i]==0&&rs2[i]==0)
5350   {
5351     if(opcode[i]&1) nop=1;
5352     else unconditional=1;
5353     //assert(opcode[i]!=5);
5354     //assert(opcode[i]!=7);
5355     //assert(opcode[i]!=0x15);
5356     //assert(opcode[i]!=0x17);
5357   }
5358   else if(rs1[i]==0)
5359   {
5360     s1l=s2l;s1h=s2h;
5361     s2l=s2h=-1;
5362     only32=(regs[i].was32>>rs2[i])&1;
5363   }
5364   else if(rs2[i]==0)
5365   {
5366     s2l=s2h=-1;
5367     only32=(regs[i].was32>>rs1[i])&1;
5368   }
5369   else {
5370     only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5371   }
5372
5373   if(ooo[i]) {
5374     // Out of order execution (delay slot first)
5375     //printf("OOOE\n");
5376     address_generation(i+1,i_regs,regs[i].regmap_entry);
5377     ds_assemble(i+1,i_regs);
5378     int adj;
5379     uint64_t bc_unneeded=branch_regs[i].u;
5380     uint64_t bc_unneeded_upper=branch_regs[i].uu;
5381     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5382     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5383     bc_unneeded|=1;
5384     bc_unneeded_upper|=1;
5385     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5386                   bc_unneeded,bc_unneeded_upper);
5387     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5388     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5389     cc=get_reg(branch_regs[i].regmap,CCREG);
5390     assert(cc==HOST_CCREG);
5391     if(unconditional)
5392       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5393     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5394     //assem_debug("cycle count (adj)\n");
5395     if(unconditional) {
5396       do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5397       if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5398         if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5399         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5400         if(internal)
5401           assem_debug("branch: internal\n");
5402         else
5403           assem_debug("branch: external\n");
5404         if(internal&&is_ds[(ba[i]-start)>>2]) {
5405           ds_assemble_entry(i);
5406         }
5407         else {
5408           add_to_linker((int)out,ba[i],internal);
5409           emit_jmp(0);
5410         }
5411         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5412         if(((u_int)out)&7) emit_addnop(0);
5413         #endif
5414       }
5415     }
5416     else if(nop) {
5417       emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5418       int jaddr=(int)out;
5419       emit_jns(0);
5420       add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5421     }
5422     else {
5423       int taken=0,nottaken=0,nottaken1=0;
5424       do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5425       if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5426       if(!only32)
5427       {
5428         assert(s1h>=0);
5429         if(opcode[i]==4) // BEQ
5430         {
5431           if(s2h>=0) emit_cmp(s1h,s2h);
5432           else emit_test(s1h,s1h);
5433           nottaken1=(int)out;
5434           emit_jne(1);
5435         }
5436         if(opcode[i]==5) // BNE
5437         {
5438           if(s2h>=0) emit_cmp(s1h,s2h);
5439           else emit_test(s1h,s1h);
5440           if(invert) taken=(int)out;
5441           else add_to_linker((int)out,ba[i],internal);
5442           emit_jne(0);
5443         }
5444         if(opcode[i]==6) // BLEZ
5445         {
5446           emit_test(s1h,s1h);
5447           if(invert) taken=(int)out;
5448           else add_to_linker((int)out,ba[i],internal);
5449           emit_js(0);
5450           nottaken1=(int)out;
5451           emit_jne(1);
5452         }
5453         if(opcode[i]==7) // BGTZ
5454         {
5455           emit_test(s1h,s1h);
5456           nottaken1=(int)out;
5457           emit_js(1);
5458           if(invert) taken=(int)out;
5459           else add_to_linker((int)out,ba[i],internal);
5460           emit_jne(0);
5461         }
5462       } // if(!only32)
5463
5464       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5465       assert(s1l>=0);
5466       if(opcode[i]==4) // BEQ
5467       {
5468         if(s2l>=0) emit_cmp(s1l,s2l);
5469         else emit_test(s1l,s1l);
5470         if(invert){
5471           nottaken=(int)out;
5472           emit_jne(1);
5473         }else{
5474           add_to_linker((int)out,ba[i],internal);
5475           emit_jeq(0);
5476         }
5477       }
5478       if(opcode[i]==5) // BNE
5479       {
5480         if(s2l>=0) emit_cmp(s1l,s2l);
5481         else emit_test(s1l,s1l);
5482         if(invert){
5483           nottaken=(int)out;
5484           emit_jeq(1);
5485         }else{
5486           add_to_linker((int)out,ba[i],internal);
5487           emit_jne(0);
5488         }
5489       }
5490       if(opcode[i]==6) // BLEZ
5491       {
5492         emit_cmpimm(s1l,1);
5493         if(invert){
5494           nottaken=(int)out;
5495           emit_jge(1);
5496         }else{
5497           add_to_linker((int)out,ba[i],internal);
5498           emit_jl(0);
5499         }
5500       }
5501       if(opcode[i]==7) // BGTZ
5502       {
5503         emit_cmpimm(s1l,1);
5504         if(invert){
5505           nottaken=(int)out;
5506           emit_jl(1);
5507         }else{
5508           add_to_linker((int)out,ba[i],internal);
5509           emit_jge(0);
5510         }
5511       }
5512       if(invert) {
5513         if(taken) set_jump_target(taken,(int)out);
5514         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5515         if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5516           if(adj) {
5517             emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5518             add_to_linker((int)out,ba[i],internal);
5519           }else{
5520             emit_addnop(13);
5521             add_to_linker((int)out,ba[i],internal*2);
5522           }
5523           emit_jmp(0);
5524         }else
5525         #endif
5526         {
5527           if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5528           store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5529           load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5530           if(internal)
5531             assem_debug("branch: internal\n");
5532           else
5533             assem_debug("branch: external\n");
5534           if(internal&&is_ds[(ba[i]-start)>>2]) {
5535             ds_assemble_entry(i);
5536           }
5537           else {
5538             add_to_linker((int)out,ba[i],internal);
5539             emit_jmp(0);
5540           }
5541         }
5542         set_jump_target(nottaken,(int)out);
5543       }
5544
5545       if(nottaken1) set_jump_target(nottaken1,(int)out);
5546       if(adj) {
5547         if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5548       }
5549     } // (!unconditional)
5550   } // if(ooo)
5551   else
5552   {
5553     // In-order execution (branch first)
5554     //if(likely[i]) printf("IOL\n");
5555     //else
5556     //printf("IOE\n");
5557     int taken=0,nottaken=0,nottaken1=0;
5558     if(!unconditional&&!nop) {
5559       if(!only32)
5560       {
5561         assert(s1h>=0);
5562         if((opcode[i]&0x2f)==4) // BEQ
5563         {
5564           if(s2h>=0) emit_cmp(s1h,s2h);
5565           else emit_test(s1h,s1h);
5566           nottaken1=(int)out;
5567           emit_jne(2);
5568         }
5569         if((opcode[i]&0x2f)==5) // BNE
5570         {
5571           if(s2h>=0) emit_cmp(s1h,s2h);
5572           else emit_test(s1h,s1h);
5573           taken=(int)out;
5574           emit_jne(1);
5575         }
5576         if((opcode[i]&0x2f)==6) // BLEZ
5577         {
5578           emit_test(s1h,s1h);
5579           taken=(int)out;
5580           emit_js(1);
5581           nottaken1=(int)out;
5582           emit_jne(2);
5583         }
5584         if((opcode[i]&0x2f)==7) // BGTZ
5585         {
5586           emit_test(s1h,s1h);
5587           nottaken1=(int)out;
5588           emit_js(2);
5589           taken=(int)out;
5590           emit_jne(1);
5591         }
5592       } // if(!only32)
5593
5594       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5595       assert(s1l>=0);
5596       if((opcode[i]&0x2f)==4) // BEQ
5597       {
5598         if(s2l>=0) emit_cmp(s1l,s2l);
5599         else emit_test(s1l,s1l);
5600         nottaken=(int)out;
5601         emit_jne(2);
5602       }
5603       if((opcode[i]&0x2f)==5) // BNE
5604       {
5605         if(s2l>=0) emit_cmp(s1l,s2l);
5606         else emit_test(s1l,s1l);
5607         nottaken=(int)out;
5608         emit_jeq(2);
5609       }
5610       if((opcode[i]&0x2f)==6) // BLEZ
5611       {
5612         emit_cmpimm(s1l,1);
5613         nottaken=(int)out;
5614         emit_jge(2);
5615       }
5616       if((opcode[i]&0x2f)==7) // BGTZ
5617       {
5618         emit_cmpimm(s1l,1);
5619         nottaken=(int)out;
5620         emit_jl(2);
5621       }
5622     } // if(!unconditional)
5623     int adj;
5624     uint64_t ds_unneeded=branch_regs[i].u;
5625     uint64_t ds_unneeded_upper=branch_regs[i].uu;
5626     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5627     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5628     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5629     ds_unneeded|=1;
5630     ds_unneeded_upper|=1;
5631     // branch taken
5632     if(!nop) {
5633       if(taken) set_jump_target(taken,(int)out);
5634       assem_debug("1:\n");
5635       wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5636                     ds_unneeded,ds_unneeded_upper);
5637       // load regs
5638       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5639       address_generation(i+1,&branch_regs[i],0);
5640       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5641       ds_assemble(i+1,&branch_regs[i]);
5642       cc=get_reg(branch_regs[i].regmap,CCREG);
5643       if(cc==-1) {
5644         emit_loadreg(CCREG,cc=HOST_CCREG);
5645         // CHECK: Is the following instruction (fall thru) allocated ok?
5646       }
5647       assert(cc==HOST_CCREG);
5648       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5649       do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5650       assem_debug("cycle count (adj)\n");
5651       if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5652       load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5653       if(internal)
5654         assem_debug("branch: internal\n");
5655       else
5656         assem_debug("branch: external\n");
5657       if(internal&&is_ds[(ba[i]-start)>>2]) {
5658         ds_assemble_entry(i);
5659       }
5660       else {
5661         add_to_linker((int)out,ba[i],internal);
5662         emit_jmp(0);
5663       }
5664     }
5665     // branch not taken
5666     cop1_usable=prev_cop1_usable;
5667     if(!unconditional) {
5668       if(nottaken1) set_jump_target(nottaken1,(int)out);
5669       set_jump_target(nottaken,(int)out);
5670       assem_debug("2:\n");
5671       if(!likely[i]) {
5672         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5673                       ds_unneeded,ds_unneeded_upper);
5674         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5675         address_generation(i+1,&branch_regs[i],0);
5676         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5677         ds_assemble(i+1,&branch_regs[i]);
5678       }
5679       cc=get_reg(branch_regs[i].regmap,CCREG);
5680       if(cc==-1&&!likely[i]) {
5681         // Cycle count isn't in a register, temporarily load it then write it out
5682         emit_loadreg(CCREG,HOST_CCREG);
5683         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5684         int jaddr=(int)out;
5685         emit_jns(0);
5686         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5687         emit_storereg(CCREG,HOST_CCREG);
5688       }
5689       else{
5690         cc=get_reg(i_regmap,CCREG);
5691         assert(cc==HOST_CCREG);
5692         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5693         int jaddr=(int)out;
5694         emit_jns(0);
5695         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5696       }
5697     }
5698   }
5699 }
5700
5701 void sjump_assemble(int i,struct regstat *i_regs)
5702 {
5703   signed char *i_regmap=i_regs->regmap;
5704   int cc;
5705   int match;
5706   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5707   assem_debug("smatch=%d\n",match);
5708   int s1h,s1l;
5709   int prev_cop1_usable=cop1_usable;
5710   int unconditional=0,nevertaken=0;
5711   int only32=0;
5712   int invert=0;
5713   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5714   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5715   if(!match) invert=1;
5716   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5717   if(i>(ba[i]-start)>>2) invert=1;
5718   #endif
5719
5720   //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
5721   //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
5722
5723   if(ooo[i]) {
5724     s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5725     s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5726   }
5727   else {
5728     s1l=get_reg(i_regmap,rs1[i]);
5729     s1h=get_reg(i_regmap,rs1[i]|64);
5730   }
5731   if(rs1[i]==0)
5732   {
5733     if(opcode2[i]&1) unconditional=1;
5734     else nevertaken=1;
5735     // These are never taken (r0 is never less than zero)
5736     //assert(opcode2[i]!=0);
5737     //assert(opcode2[i]!=2);
5738     //assert(opcode2[i]!=0x10);
5739     //assert(opcode2[i]!=0x12);
5740   }
5741   else {
5742     only32=(regs[i].was32>>rs1[i])&1;
5743   }
5744
5745   if(ooo[i]) {
5746     // Out of order execution (delay slot first)
5747     //printf("OOOE\n");
5748     address_generation(i+1,i_regs,regs[i].regmap_entry);
5749     ds_assemble(i+1,i_regs);
5750     int adj;
5751     uint64_t bc_unneeded=branch_regs[i].u;
5752     uint64_t bc_unneeded_upper=branch_regs[i].uu;
5753     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5754     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5755     bc_unneeded|=1;
5756     bc_unneeded_upper|=1;
5757     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5758                   bc_unneeded,bc_unneeded_upper);
5759     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5760     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5761     if(rt1[i]==31) {
5762       int rt,return_address;
5763       rt=get_reg(branch_regs[i].regmap,31);
5764       assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5765       if(rt>=0) {
5766         // Save the PC even if the branch is not taken
5767         return_address=start+i*4+8;
5768         emit_movimm(return_address,rt); // PC into link register
5769         #ifdef IMM_PREFETCH
5770         if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5771         #endif
5772       }
5773     }
5774     cc=get_reg(branch_regs[i].regmap,CCREG);
5775     assert(cc==HOST_CCREG);
5776     if(unconditional)
5777       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5778     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5779     assem_debug("cycle count (adj)\n");
5780     if(unconditional) {
5781       do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5782       if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5783         if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5784         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5785         if(internal)
5786           assem_debug("branch: internal\n");
5787         else
5788           assem_debug("branch: external\n");
5789         if(internal&&is_ds[(ba[i]-start)>>2]) {
5790           ds_assemble_entry(i);
5791         }
5792         else {
5793           add_to_linker((int)out,ba[i],internal);
5794           emit_jmp(0);
5795         }
5796         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5797         if(((u_int)out)&7) emit_addnop(0);
5798         #endif
5799       }
5800     }
5801     else if(nevertaken) {
5802       emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5803       int jaddr=(int)out;
5804       emit_jns(0);
5805       add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5806     }
5807     else {
5808       int nottaken=0;
5809       do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5810       if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5811       if(!only32)
5812       {
5813         assert(s1h>=0);
5814         if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5815         {
5816           emit_test(s1h,s1h);
5817           if(invert){
5818             nottaken=(int)out;
5819             emit_jns(1);
5820           }else{
5821             add_to_linker((int)out,ba[i],internal);
5822             emit_js(0);
5823           }
5824         }
5825         if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5826         {
5827           emit_test(s1h,s1h);
5828           if(invert){
5829             nottaken=(int)out;
5830             emit_js(1);
5831           }else{
5832             add_to_linker((int)out,ba[i],internal);
5833             emit_jns(0);
5834           }
5835         }
5836       } // if(!only32)
5837       else
5838       {
5839         assert(s1l>=0);
5840         if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5841         {
5842           emit_test(s1l,s1l);
5843           if(invert){
5844             nottaken=(int)out;
5845             emit_jns(1);
5846           }else{
5847             add_to_linker((int)out,ba[i],internal);
5848             emit_js(0);
5849           }
5850         }
5851         if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5852         {
5853           emit_test(s1l,s1l);
5854           if(invert){
5855             nottaken=(int)out;
5856             emit_js(1);
5857           }else{
5858             add_to_linker((int)out,ba[i],internal);
5859             emit_jns(0);
5860           }
5861         }
5862       } // if(!only32)
5863
5864       if(invert) {
5865         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5866         if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5867           if(adj) {
5868             emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5869             add_to_linker((int)out,ba[i],internal);
5870           }else{
5871             emit_addnop(13);
5872             add_to_linker((int)out,ba[i],internal*2);
5873           }
5874           emit_jmp(0);
5875         }else
5876         #endif
5877         {
5878           if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5879           store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5880           load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5881           if(internal)
5882             assem_debug("branch: internal\n");
5883           else
5884             assem_debug("branch: external\n");
5885           if(internal&&is_ds[(ba[i]-start)>>2]) {
5886             ds_assemble_entry(i);
5887           }
5888           else {
5889             add_to_linker((int)out,ba[i],internal);
5890             emit_jmp(0);
5891           }
5892         }
5893         set_jump_target(nottaken,(int)out);
5894       }
5895
5896       if(adj) {
5897         if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5898       }
5899     } // (!unconditional)
5900   } // if(ooo)
5901   else
5902   {
5903     // In-order execution (branch first)
5904     //printf("IOE\n");
5905     int nottaken=0;
5906     if(rt1[i]==31) {
5907       int rt,return_address;
5908       rt=get_reg(branch_regs[i].regmap,31);
5909       if(rt>=0) {
5910         // Save the PC even if the branch is not taken
5911         return_address=start+i*4+8;
5912         emit_movimm(return_address,rt); // PC into link register
5913         #ifdef IMM_PREFETCH
5914         emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5915         #endif
5916       }
5917     }
5918     if(!unconditional) {
5919       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5920       if(!only32)
5921       {
5922         assert(s1h>=0);
5923         if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
5924         {
5925           emit_test(s1h,s1h);
5926           nottaken=(int)out;
5927           emit_jns(1);
5928         }
5929         if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
5930         {
5931           emit_test(s1h,s1h);
5932           nottaken=(int)out;
5933           emit_js(1);
5934         }
5935       } // if(!only32)
5936       else
5937       {
5938         assert(s1l>=0);
5939         if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
5940         {
5941           emit_test(s1l,s1l);
5942           nottaken=(int)out;
5943           emit_jns(1);
5944         }
5945         if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
5946         {
5947           emit_test(s1l,s1l);
5948           nottaken=(int)out;
5949           emit_js(1);
5950         }
5951       }
5952     } // if(!unconditional)
5953     int adj;
5954     uint64_t ds_unneeded=branch_regs[i].u;
5955     uint64_t ds_unneeded_upper=branch_regs[i].uu;
5956     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5957     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5958     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5959     ds_unneeded|=1;
5960     ds_unneeded_upper|=1;
5961     // branch taken
5962     if(!nevertaken) {
5963       //assem_debug("1:\n");
5964       wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5965                     ds_unneeded,ds_unneeded_upper);
5966       // load regs
5967       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5968       address_generation(i+1,&branch_regs[i],0);
5969       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5970       ds_assemble(i+1,&branch_regs[i]);
5971       cc=get_reg(branch_regs[i].regmap,CCREG);
5972       if(cc==-1) {
5973         emit_loadreg(CCREG,cc=HOST_CCREG);
5974         // CHECK: Is the following instruction (fall thru) allocated ok?
5975       }
5976       assert(cc==HOST_CCREG);
5977       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5978       do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5979       assem_debug("cycle count (adj)\n");
5980       if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5981       load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5982       if(internal)
5983         assem_debug("branch: internal\n");
5984       else
5985         assem_debug("branch: external\n");
5986       if(internal&&is_ds[(ba[i]-start)>>2]) {
5987         ds_assemble_entry(i);
5988       }
5989       else {
5990         add_to_linker((int)out,ba[i],internal);
5991         emit_jmp(0);
5992       }
5993     }
5994     // branch not taken
5995     cop1_usable=prev_cop1_usable;
5996     if(!unconditional) {
5997       set_jump_target(nottaken,(int)out);
5998       assem_debug("1:\n");
5999       if(!likely[i]) {
6000         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6001                       ds_unneeded,ds_unneeded_upper);
6002         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6003         address_generation(i+1,&branch_regs[i],0);
6004         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6005         ds_assemble(i+1,&branch_regs[i]);
6006       }
6007       cc=get_reg(branch_regs[i].regmap,CCREG);
6008       if(cc==-1&&!likely[i]) {
6009         // Cycle count isn't in a register, temporarily load it then write it out
6010         emit_loadreg(CCREG,HOST_CCREG);
6011         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6012         int jaddr=(int)out;
6013         emit_jns(0);
6014         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6015         emit_storereg(CCREG,HOST_CCREG);
6016       }
6017       else{
6018         cc=get_reg(i_regmap,CCREG);
6019         assert(cc==HOST_CCREG);
6020         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6021         int jaddr=(int)out;
6022         emit_jns(0);
6023         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6024       }
6025     }
6026   }
6027 }
6028
6029 void fjump_assemble(int i,struct regstat *i_regs)
6030 {
6031   signed char *i_regmap=i_regs->regmap;
6032   int cc;
6033   int match;
6034   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6035   assem_debug("fmatch=%d\n",match);
6036   int fs,cs;
6037   int eaddr;
6038   int invert=0;
6039   int internal=internal_branch(branch_regs[i].is32,ba[i]);
6040   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
6041   if(!match) invert=1;
6042   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6043   if(i>(ba[i]-start)>>2) invert=1;
6044   #endif
6045
6046   if(ooo[i]) {
6047     fs=get_reg(branch_regs[i].regmap,FSREG);
6048     address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
6049   }
6050   else {
6051     fs=get_reg(i_regmap,FSREG);
6052   }
6053
6054   // Check cop1 unusable
6055   if(!cop1_usable) {
6056     cs=get_reg(i_regmap,CSREG);
6057     assert(cs>=0);
6058     emit_testimm(cs,0x20000000);
6059     eaddr=(int)out;
6060     emit_jeq(0);
6061     add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
6062     cop1_usable=1;
6063   }
6064
6065   if(ooo[i]) {
6066     // Out of order execution (delay slot first)
6067     //printf("OOOE\n");
6068     ds_assemble(i+1,i_regs);
6069     int adj;
6070     uint64_t bc_unneeded=branch_regs[i].u;
6071     uint64_t bc_unneeded_upper=branch_regs[i].uu;
6072     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6073     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
6074     bc_unneeded|=1;
6075     bc_unneeded_upper|=1;
6076     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6077                   bc_unneeded,bc_unneeded_upper);
6078     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
6079     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6080     cc=get_reg(branch_regs[i].regmap,CCREG);
6081     assert(cc==HOST_CCREG);
6082     do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6083     assem_debug("cycle count (adj)\n");
6084     if(1) {
6085       int nottaken=0;
6086       if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6087       if(1) {
6088         assert(fs>=0);
6089         emit_testimm(fs,0x800000);
6090         if(source[i]&0x10000) // BC1T
6091         {
6092           if(invert){
6093             nottaken=(int)out;
6094             emit_jeq(1);
6095           }else{
6096             add_to_linker((int)out,ba[i],internal);
6097             emit_jne(0);
6098           }
6099         }
6100         else // BC1F
6101           if(invert){
6102             nottaken=(int)out;
6103             emit_jne(1);
6104           }else{
6105             add_to_linker((int)out,ba[i],internal);
6106             emit_jeq(0);
6107           }
6108         {
6109         }
6110       } // if(!only32)
6111
6112       if(invert) {
6113         if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
6114         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6115         else if(match) emit_addnop(13);
6116         #endif
6117         store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6118         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6119         if(internal)
6120           assem_debug("branch: internal\n");
6121         else
6122           assem_debug("branch: external\n");
6123         if(internal&&is_ds[(ba[i]-start)>>2]) {
6124           ds_assemble_entry(i);
6125         }
6126         else {
6127           add_to_linker((int)out,ba[i],internal);
6128           emit_jmp(0);
6129         }
6130         set_jump_target(nottaken,(int)out);
6131       }
6132
6133       if(adj) {
6134         if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
6135       }
6136     } // (!unconditional)
6137   } // if(ooo)
6138   else
6139   {
6140     // In-order execution (branch first)
6141     //printf("IOE\n");
6142     int nottaken=0;
6143     if(1) {
6144       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6145       if(1) {
6146         assert(fs>=0);
6147         emit_testimm(fs,0x800000);
6148         if(source[i]&0x10000) // BC1T
6149         {
6150           nottaken=(int)out;
6151           emit_jeq(1);
6152         }
6153         else // BC1F
6154         {
6155           nottaken=(int)out;
6156           emit_jne(1);
6157         }
6158       }
6159     } // if(!unconditional)
6160     int adj;
6161     uint64_t ds_unneeded=branch_regs[i].u;
6162     uint64_t ds_unneeded_upper=branch_regs[i].uu;
6163     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6164     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6165     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6166     ds_unneeded|=1;
6167     ds_unneeded_upper|=1;
6168     // branch taken
6169     //assem_debug("1:\n");
6170     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6171                   ds_unneeded,ds_unneeded_upper);
6172     // load regs
6173     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6174     address_generation(i+1,&branch_regs[i],0);
6175     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6176     ds_assemble(i+1,&branch_regs[i]);
6177     cc=get_reg(branch_regs[i].regmap,CCREG);
6178     if(cc==-1) {
6179       emit_loadreg(CCREG,cc=HOST_CCREG);
6180       // CHECK: Is the following instruction (fall thru) allocated ok?
6181     }
6182     assert(cc==HOST_CCREG);
6183     store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6184     do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6185     assem_debug("cycle count (adj)\n");
6186     if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6187     load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6188     if(internal)
6189       assem_debug("branch: internal\n");
6190     else
6191       assem_debug("branch: external\n");
6192     if(internal&&is_ds[(ba[i]-start)>>2]) {
6193       ds_assemble_entry(i);
6194     }
6195     else {
6196       add_to_linker((int)out,ba[i],internal);
6197       emit_jmp(0);
6198     }
6199
6200     // branch not taken
6201     if(1) { // <- FIXME (don't need this)
6202       set_jump_target(nottaken,(int)out);
6203       assem_debug("1:\n");
6204       if(!likely[i]) {
6205         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6206                       ds_unneeded,ds_unneeded_upper);
6207         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6208         address_generation(i+1,&branch_regs[i],0);
6209         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6210         ds_assemble(i+1,&branch_regs[i]);
6211       }
6212       cc=get_reg(branch_regs[i].regmap,CCREG);
6213       if(cc==-1&&!likely[i]) {
6214         // Cycle count isn't in a register, temporarily load it then write it out
6215         emit_loadreg(CCREG,HOST_CCREG);
6216         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6217         int jaddr=(int)out;
6218         emit_jns(0);
6219         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6220         emit_storereg(CCREG,HOST_CCREG);
6221       }
6222       else{
6223         cc=get_reg(i_regmap,CCREG);
6224         assert(cc==HOST_CCREG);
6225         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6226         int jaddr=(int)out;
6227         emit_jns(0);
6228         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6229       }
6230     }
6231   }
6232 }
6233
6234 static void pagespan_assemble(int i,struct regstat *i_regs)
6235 {
6236   int s1l=get_reg(i_regs->regmap,rs1[i]);
6237   int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6238   int s2l=get_reg(i_regs->regmap,rs2[i]);
6239   int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6240   void *nt_branch=NULL;
6241   int taken=0;
6242   int nottaken=0;
6243   int unconditional=0;
6244   if(rs1[i]==0)
6245   {
6246     s1l=s2l;s1h=s2h;
6247     s2l=s2h=-1;
6248   }
6249   else if(rs2[i]==0)
6250   {
6251     s2l=s2h=-1;
6252   }
6253   if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6254     s1h=s2h=-1;
6255   }
6256   int hr=0;
6257   int addr,alt,ntaddr;
6258   if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6259   else {
6260     while(hr<HOST_REGS)
6261     {
6262       if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6263          (i_regs->regmap[hr]&63)!=rs1[i] &&
6264          (i_regs->regmap[hr]&63)!=rs2[i] )
6265       {
6266         addr=hr++;break;
6267       }
6268       hr++;
6269     }
6270   }
6271   while(hr<HOST_REGS)
6272   {
6273     if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6274        (i_regs->regmap[hr]&63)!=rs1[i] &&
6275        (i_regs->regmap[hr]&63)!=rs2[i] )
6276     {
6277       alt=hr++;break;
6278     }
6279     hr++;
6280   }
6281   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6282   {
6283     while(hr<HOST_REGS)
6284     {
6285       if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6286          (i_regs->regmap[hr]&63)!=rs1[i] &&
6287          (i_regs->regmap[hr]&63)!=rs2[i] )
6288       {
6289         ntaddr=hr;break;
6290       }
6291       hr++;
6292     }
6293   }
6294   assert(hr<HOST_REGS);
6295   if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6296     load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6297   }
6298   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6299   if(opcode[i]==2) // J
6300   {
6301     unconditional=1;
6302   }
6303   if(opcode[i]==3) // JAL
6304   {
6305     // TODO: mini_ht
6306     int rt=get_reg(i_regs->regmap,31);
6307     emit_movimm(start+i*4+8,rt);
6308     unconditional=1;
6309   }
6310   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6311   {
6312     emit_mov(s1l,addr);
6313     if(opcode2[i]==9) // JALR
6314     {
6315       int rt=get_reg(i_regs->regmap,rt1[i]);
6316       emit_movimm(start+i*4+8,rt);
6317     }
6318   }
6319   if((opcode[i]&0x3f)==4) // BEQ
6320   {
6321     if(rs1[i]==rs2[i])
6322     {
6323       unconditional=1;
6324     }
6325     else
6326     #ifdef HAVE_CMOV_IMM
6327     if(s1h<0) {
6328       if(s2l>=0) emit_cmp(s1l,s2l);
6329       else emit_test(s1l,s1l);
6330       emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6331     }
6332     else
6333     #endif
6334     {
6335       assert(s1l>=0);
6336       emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6337       if(s1h>=0) {
6338         if(s2h>=0) emit_cmp(s1h,s2h);
6339         else emit_test(s1h,s1h);
6340         emit_cmovne_reg(alt,addr);
6341       }
6342       if(s2l>=0) emit_cmp(s1l,s2l);
6343       else emit_test(s1l,s1l);
6344       emit_cmovne_reg(alt,addr);
6345     }
6346   }
6347   if((opcode[i]&0x3f)==5) // BNE
6348   {
6349     #ifdef HAVE_CMOV_IMM
6350     if(s1h<0) {
6351       if(s2l>=0) emit_cmp(s1l,s2l);
6352       else emit_test(s1l,s1l);
6353       emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6354     }
6355     else
6356     #endif
6357     {
6358       assert(s1l>=0);
6359       emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6360       if(s1h>=0) {
6361         if(s2h>=0) emit_cmp(s1h,s2h);
6362         else emit_test(s1h,s1h);
6363         emit_cmovne_reg(alt,addr);
6364       }
6365       if(s2l>=0) emit_cmp(s1l,s2l);
6366       else emit_test(s1l,s1l);
6367       emit_cmovne_reg(alt,addr);
6368     }
6369   }
6370   if((opcode[i]&0x3f)==0x14) // BEQL
6371   {
6372     if(s1h>=0) {
6373       if(s2h>=0) emit_cmp(s1h,s2h);
6374       else emit_test(s1h,s1h);
6375       nottaken=(int)out;
6376       emit_jne(0);
6377     }
6378     if(s2l>=0) emit_cmp(s1l,s2l);
6379     else emit_test(s1l,s1l);
6380     if(nottaken) set_jump_target(nottaken,(int)out);
6381     nottaken=(int)out;
6382     emit_jne(0);
6383   }
6384   if((opcode[i]&0x3f)==0x15) // BNEL
6385   {
6386     if(s1h>=0) {
6387       if(s2h>=0) emit_cmp(s1h,s2h);
6388       else emit_test(s1h,s1h);
6389       taken=(int)out;
6390       emit_jne(0);
6391     }
6392     if(s2l>=0) emit_cmp(s1l,s2l);
6393     else emit_test(s1l,s1l);
6394     nottaken=(int)out;
6395     emit_jeq(0);
6396     if(taken) set_jump_target(taken,(int)out);
6397   }
6398   if((opcode[i]&0x3f)==6) // BLEZ
6399   {
6400     emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6401     emit_cmpimm(s1l,1);
6402     if(s1h>=0) emit_mov(addr,ntaddr);
6403     emit_cmovl_reg(alt,addr);
6404     if(s1h>=0) {
6405       emit_test(s1h,s1h);
6406       emit_cmovne_reg(ntaddr,addr);
6407       emit_cmovs_reg(alt,addr);
6408     }
6409   }
6410   if((opcode[i]&0x3f)==7) // BGTZ
6411   {
6412     emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6413     emit_cmpimm(s1l,1);
6414     if(s1h>=0) emit_mov(addr,alt);
6415     emit_cmovl_reg(ntaddr,addr);
6416     if(s1h>=0) {
6417       emit_test(s1h,s1h);
6418       emit_cmovne_reg(alt,addr);
6419       emit_cmovs_reg(ntaddr,addr);
6420     }
6421   }
6422   if((opcode[i]&0x3f)==0x16) // BLEZL
6423   {
6424     assert((opcode[i]&0x3f)!=0x16);
6425   }
6426   if((opcode[i]&0x3f)==0x17) // BGTZL
6427   {
6428     assert((opcode[i]&0x3f)!=0x17);
6429   }
6430   assert(opcode[i]!=1); // BLTZ/BGEZ
6431
6432   //FIXME: Check CSREG
6433   if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6434     if((source[i]&0x30000)==0) // BC1F
6435     {
6436       emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6437       emit_testimm(s1l,0x800000);
6438       emit_cmovne_reg(alt,addr);
6439     }
6440     if((source[i]&0x30000)==0x10000) // BC1T
6441     {
6442       emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6443       emit_testimm(s1l,0x800000);
6444       emit_cmovne_reg(alt,addr);
6445     }
6446     if((source[i]&0x30000)==0x20000) // BC1FL
6447     {
6448       emit_testimm(s1l,0x800000);
6449       nottaken=(int)out;
6450       emit_jne(0);
6451     }
6452     if((source[i]&0x30000)==0x30000) // BC1TL
6453     {
6454       emit_testimm(s1l,0x800000);
6455       nottaken=(int)out;
6456       emit_jeq(0);
6457     }
6458   }
6459
6460   assert(i_regs->regmap[HOST_CCREG]==CCREG);
6461   wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6462   if(likely[i]||unconditional)
6463   {
6464     emit_movimm(ba[i],HOST_BTREG);
6465   }
6466   else if(addr!=HOST_BTREG)
6467   {
6468     emit_mov(addr,HOST_BTREG);
6469   }
6470   void *branch_addr=out;
6471   emit_jmp(0);
6472   int target_addr=start+i*4+5;
6473   void *stub=out;
6474   void *compiled_target_addr=check_addr(target_addr);
6475   emit_extjump_ds((int)branch_addr,target_addr);
6476   if(compiled_target_addr) {
6477     set_jump_target((int)branch_addr,(int)compiled_target_addr);
6478     add_link(target_addr,stub);
6479   }
6480   else set_jump_target((int)branch_addr,(int)stub);
6481   if(likely[i]) {
6482     // Not-taken path
6483     set_jump_target((int)nottaken,(int)out);
6484     wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6485     void *branch_addr=out;
6486     emit_jmp(0);
6487     int target_addr=start+i*4+8;
6488     void *stub=out;
6489     void *compiled_target_addr=check_addr(target_addr);
6490     emit_extjump_ds((int)branch_addr,target_addr);
6491     if(compiled_target_addr) {
6492       set_jump_target((int)branch_addr,(int)compiled_target_addr);
6493       add_link(target_addr,stub);
6494     }
6495     else set_jump_target((int)branch_addr,(int)stub);
6496   }
6497 }
6498
6499 // Assemble the delay slot for the above
6500 static void pagespan_ds()
6501 {
6502   assem_debug("initial delay slot:\n");
6503   u_int vaddr=start+1;
6504   u_int page=get_page(vaddr);
6505   u_int vpage=get_vpage(vaddr);
6506   ll_add(jump_dirty+vpage,vaddr,(void *)out);
6507   do_dirty_stub_ds();
6508   ll_add(jump_in+page,vaddr,(void *)out);
6509   assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6510   if(regs[0].regmap[HOST_CCREG]!=CCREG)
6511     wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6512   if(regs[0].regmap[HOST_BTREG]!=BTREG)
6513     emit_writeword(HOST_BTREG,(int)&branch_target);
6514   load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6515   address_generation(0,&regs[0],regs[0].regmap_entry);
6516   if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
6517     load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6518   cop1_usable=0;
6519   is_delayslot=0;
6520   switch(itype[0]) {
6521     case ALU:
6522       alu_assemble(0,&regs[0]);break;
6523     case IMM16:
6524       imm16_assemble(0,&regs[0]);break;
6525     case SHIFT:
6526       shift_assemble(0,&regs[0]);break;
6527     case SHIFTIMM:
6528       shiftimm_assemble(0,&regs[0]);break;
6529     case LOAD:
6530       load_assemble(0,&regs[0]);break;
6531     case LOADLR:
6532       loadlr_assemble(0,&regs[0]);break;
6533     case STORE:
6534       store_assemble(0,&regs[0]);break;
6535     case STORELR:
6536       storelr_assemble(0,&regs[0]);break;
6537     case COP0:
6538       cop0_assemble(0,&regs[0]);break;
6539     case COP1:
6540       cop1_assemble(0,&regs[0]);break;
6541     case C1LS:
6542       c1ls_assemble(0,&regs[0]);break;
6543     case COP2:
6544       cop2_assemble(0,&regs[0]);break;
6545     case C2LS:
6546       c2ls_assemble(0,&regs[0]);break;
6547     case C2OP:
6548       c2op_assemble(0,&regs[0]);break;
6549     case FCONV:
6550       fconv_assemble(0,&regs[0]);break;
6551     case FLOAT:
6552       float_assemble(0,&regs[0]);break;
6553     case FCOMP:
6554       fcomp_assemble(0,&regs[0]);break;
6555     case MULTDIV:
6556       multdiv_assemble(0,&regs[0]);break;
6557     case MOV:
6558       mov_assemble(0,&regs[0]);break;
6559     case SYSCALL:
6560     case HLECALL:
6561     case INTCALL:
6562     case SPAN:
6563     case UJUMP:
6564     case RJUMP:
6565     case CJUMP:
6566     case SJUMP:
6567     case FJUMP:
6568       printf("Jump in the delay slot.  This is probably a bug.\n");
6569   }
6570   int btaddr=get_reg(regs[0].regmap,BTREG);
6571   if(btaddr<0) {
6572     btaddr=get_reg(regs[0].regmap,-1);
6573     emit_readword((int)&branch_target,btaddr);
6574   }
6575   assert(btaddr!=HOST_CCREG);
6576   if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6577 #ifdef HOST_IMM8
6578   emit_movimm(start+4,HOST_TEMPREG);
6579   emit_cmp(btaddr,HOST_TEMPREG);
6580 #else
6581   emit_cmpimm(btaddr,start+4);
6582 #endif
6583   int branch=(int)out;
6584   emit_jeq(0);
6585   store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6586   emit_jmp(jump_vaddr_reg[btaddr]);
6587   set_jump_target(branch,(int)out);
6588   store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6589   load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6590 }
6591
6592 // Basic liveness analysis for MIPS registers
6593 void unneeded_registers(int istart,int iend,int r)
6594 {
6595   int i;
6596   uint64_t u,uu,b,bu;
6597   uint64_t temp_u,temp_uu;
6598   uint64_t tdep;
6599   if(iend==slen-1) {
6600     u=1;uu=1;
6601   }else{
6602     u=unneeded_reg[iend+1];
6603     uu=unneeded_reg_upper[iend+1];
6604     u=1;uu=1;
6605   }
6606   for (i=iend;i>=istart;i--)
6607   {
6608     //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6609     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6610     {
6611       // If subroutine call, flag return address as a possible branch target
6612       if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6613
6614       if(ba[i]<start || ba[i]>=(start+slen*4))
6615       {
6616         // Branch out of this block, flush all regs
6617         u=1;
6618         uu=1;
6619         /* Hexagon hack
6620         if(itype[i]==UJUMP&&rt1[i]==31)
6621         {
6622           uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6623         }
6624         if(itype[i]==RJUMP&&rs1[i]==31)
6625         {
6626           uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6627         }
6628         if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
6629           if(itype[i]==UJUMP&&rt1[i]==31)
6630           {
6631             //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6632             uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6633           }
6634           if(itype[i]==RJUMP&&rs1[i]==31)
6635           {
6636             //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6637             uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6638           }
6639         }*/
6640         branch_unneeded_reg[i]=u;
6641         branch_unneeded_reg_upper[i]=uu;
6642         // Merge in delay slot
6643         tdep=(~uu>>rt1[i+1])&1;
6644         u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6645         uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6646         u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6647         uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6648         uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6649         u|=1;uu|=1;
6650         // If branch is "likely" (and conditional)
6651         // then we skip the delay slot on the fall-thru path
6652         if(likely[i]) {
6653           if(i<slen-1) {
6654             u&=unneeded_reg[i+2];
6655             uu&=unneeded_reg_upper[i+2];
6656           }
6657           else
6658           {
6659             u=1;
6660             uu=1;
6661           }
6662         }
6663       }
6664       else
6665       {
6666         // Internal branch, flag target
6667         bt[(ba[i]-start)>>2]=1;
6668         if(ba[i]<=start+i*4) {
6669           // Backward branch
6670           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6671           {
6672             // Unconditional branch
6673             temp_u=1;temp_uu=1;
6674           } else {
6675             // Conditional branch (not taken case)
6676             temp_u=unneeded_reg[i+2];
6677             temp_uu=unneeded_reg_upper[i+2];
6678           }
6679           // Merge in delay slot
6680           tdep=(~temp_uu>>rt1[i+1])&1;
6681           temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6682           temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6683           temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6684           temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6685           temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6686           temp_u|=1;temp_uu|=1;
6687           // If branch is "likely" (and conditional)
6688           // then we skip the delay slot on the fall-thru path
6689           if(likely[i]) {
6690             if(i<slen-1) {
6691               temp_u&=unneeded_reg[i+2];
6692               temp_uu&=unneeded_reg_upper[i+2];
6693             }
6694             else
6695             {
6696               temp_u=1;
6697               temp_uu=1;
6698             }
6699           }
6700           tdep=(~temp_uu>>rt1[i])&1;
6701           temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6702           temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6703           temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6704           temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6705           temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6706           temp_u|=1;temp_uu|=1;
6707           unneeded_reg[i]=temp_u;
6708           unneeded_reg_upper[i]=temp_uu;
6709           // Only go three levels deep.  This recursion can take an
6710           // excessive amount of time if there are a lot of nested loops.
6711           if(r<2) {
6712             unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6713           }else{
6714             unneeded_reg[(ba[i]-start)>>2]=1;
6715             unneeded_reg_upper[(ba[i]-start)>>2]=1;
6716           }
6717         } /*else*/ if(1) {
6718           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6719           {
6720             // Unconditional branch
6721             u=unneeded_reg[(ba[i]-start)>>2];
6722             uu=unneeded_reg_upper[(ba[i]-start)>>2];
6723             branch_unneeded_reg[i]=u;
6724             branch_unneeded_reg_upper[i]=uu;
6725         //u=1;
6726         //uu=1;
6727         //branch_unneeded_reg[i]=u;
6728         //branch_unneeded_reg_upper[i]=uu;
6729             // Merge in delay slot
6730             tdep=(~uu>>rt1[i+1])&1;
6731             u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6732             uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6733             u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6734             uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6735             uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6736             u|=1;uu|=1;
6737           } else {
6738             // Conditional branch
6739             b=unneeded_reg[(ba[i]-start)>>2];
6740             bu=unneeded_reg_upper[(ba[i]-start)>>2];
6741             branch_unneeded_reg[i]=b;
6742             branch_unneeded_reg_upper[i]=bu;
6743         //b=1;
6744         //bu=1;
6745         //branch_unneeded_reg[i]=b;
6746         //branch_unneeded_reg_upper[i]=bu;
6747             // Branch delay slot
6748             tdep=(~uu>>rt1[i+1])&1;
6749             b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6750             bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6751             b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6752             bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6753             bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6754             b|=1;bu|=1;
6755             // If branch is "likely" then we skip the
6756             // delay slot on the fall-thru path
6757             if(likely[i]) {
6758               u=b;
6759               uu=bu;
6760               if(i<slen-1) {
6761                 u&=unneeded_reg[i+2];
6762                 uu&=unneeded_reg_upper[i+2];
6763         //u=1;
6764         //uu=1;
6765               }
6766             } else {
6767               u&=b;
6768               uu&=bu;
6769         //u=1;
6770         //uu=1;
6771             }
6772             if(i<slen-1) {
6773               branch_unneeded_reg[i]&=unneeded_reg[i+2];
6774               branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6775         //branch_unneeded_reg[i]=1;
6776         //branch_unneeded_reg_upper[i]=1;
6777             } else {
6778               branch_unneeded_reg[i]=1;
6779               branch_unneeded_reg_upper[i]=1;
6780             }
6781           }
6782         }
6783       }
6784     }
6785     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
6786     {
6787       // SYSCALL instruction (software interrupt)
6788       u=1;
6789       uu=1;
6790     }
6791     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6792     {
6793       // ERET instruction (return from interrupt)
6794       u=1;
6795       uu=1;
6796     }
6797     //u=uu=1; // DEBUG
6798     tdep=(~uu>>rt1[i])&1;
6799     // Written registers are unneeded
6800     u|=1LL<<rt1[i];
6801     u|=1LL<<rt2[i];
6802     uu|=1LL<<rt1[i];
6803     uu|=1LL<<rt2[i];
6804     // Accessed registers are needed
6805     u&=~(1LL<<rs1[i]);
6806     u&=~(1LL<<rs2[i]);
6807     uu&=~(1LL<<us1[i]);
6808     uu&=~(1LL<<us2[i]);
6809     // Source-target dependencies
6810     uu&=~(tdep<<dep1[i]);
6811     uu&=~(tdep<<dep2[i]);
6812     // R0 is always unneeded
6813     u|=1;uu|=1;
6814     // Save it
6815     unneeded_reg[i]=u;
6816     unneeded_reg_upper[i]=uu;
6817     /*
6818     printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6819     printf("U:");
6820     int r;
6821     for(r=1;r<=CCREG;r++) {
6822       if((unneeded_reg[i]>>r)&1) {
6823         if(r==HIREG) printf(" HI");
6824         else if(r==LOREG) printf(" LO");
6825         else printf(" r%d",r);
6826       }
6827     }
6828     printf(" UU:");
6829     for(r=1;r<=CCREG;r++) {
6830       if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
6831         if(r==HIREG) printf(" HI");
6832         else if(r==LOREG) printf(" LO");
6833         else printf(" r%d",r);
6834       }
6835     }
6836     printf("\n");*/
6837   }
6838 #ifdef FORCE32
6839   for (i=iend;i>=istart;i--)
6840   {
6841     unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
6842   }
6843 #endif
6844 }
6845
6846 // Identify registers which are likely to contain 32-bit values
6847 // This is used to predict whether any branches will jump to a
6848 // location with 64-bit values in registers.
6849 static void provisional_32bit()
6850 {
6851   int i,j;
6852   uint64_t is32=1;
6853   uint64_t lastbranch=1;
6854
6855   for(i=0;i<slen;i++)
6856   {
6857     if(i>0) {
6858       if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
6859         if(i>1) is32=lastbranch;
6860         else is32=1;
6861       }
6862     }
6863     if(i>1)
6864     {
6865       if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
6866         if(likely[i-2]) {
6867           if(i>2) is32=lastbranch;
6868           else is32=1;
6869         }
6870       }
6871       if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
6872       {
6873         if(rs1[i-2]==0||rs2[i-2]==0)
6874         {
6875           if(rs1[i-2]) {
6876             is32|=1LL<<rs1[i-2];
6877           }
6878           if(rs2[i-2]) {
6879             is32|=1LL<<rs2[i-2];
6880           }
6881         }
6882       }
6883     }
6884     // If something jumps here with 64-bit values
6885     // then promote those registers to 64 bits
6886     if(bt[i])
6887     {
6888       uint64_t temp_is32=is32;
6889       for(j=i-1;j>=0;j--)
6890       {
6891         if(ba[j]==start+i*4)
6892           //temp_is32&=branch_regs[j].is32;
6893           temp_is32&=p32[j];
6894       }
6895       for(j=i;j<slen;j++)
6896       {
6897         if(ba[j]==start+i*4)
6898           temp_is32=1;
6899       }
6900       is32=temp_is32;
6901     }
6902     int type=itype[i];
6903     int op=opcode[i];
6904     int op2=opcode2[i];
6905     int rt=rt1[i];
6906     int s1=rs1[i];
6907     int s2=rs2[i];
6908     if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
6909       // Branches don't write registers, consider the delay slot instead.
6910       type=itype[i+1];
6911       op=opcode[i+1];
6912       op2=opcode2[i+1];
6913       rt=rt1[i+1];
6914       s1=rs1[i+1];
6915       s2=rs2[i+1];
6916       lastbranch=is32;
6917     }
6918     switch(type) {
6919       case LOAD:
6920         if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
6921            opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
6922           is32&=~(1LL<<rt);
6923         else
6924           is32|=1LL<<rt;
6925         break;
6926       case STORE:
6927       case STORELR:
6928         break;
6929       case LOADLR:
6930         if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
6931         if(op==0x22) is32|=1LL<<rt; // LWL
6932         break;
6933       case IMM16:
6934         if (op==0x08||op==0x09|| // ADDI/ADDIU
6935             op==0x0a||op==0x0b|| // SLTI/SLTIU
6936             op==0x0c|| // ANDI
6937             op==0x0f)  // LUI
6938         {
6939           is32|=1LL<<rt;
6940         }
6941         if(op==0x18||op==0x19) { // DADDI/DADDIU
6942           is32&=~(1LL<<rt);
6943           //if(imm[i]==0)
6944           //  is32|=((is32>>s1)&1LL)<<rt;
6945         }
6946         if(op==0x0d||op==0x0e) { // ORI/XORI
6947           uint64_t sr=((is32>>s1)&1LL);
6948           is32&=~(1LL<<rt);
6949           is32|=sr<<rt;
6950         }
6951         break;
6952       case UJUMP:
6953         break;
6954       case RJUMP:
6955         break;
6956       case CJUMP:
6957         break;
6958       case SJUMP:
6959         break;
6960       case FJUMP:
6961         break;
6962       case ALU:
6963         if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
6964           is32|=1LL<<rt;
6965         }
6966         if(op2==0x2a||op2==0x2b) { // SLT/SLTU
6967           is32|=1LL<<rt;
6968         }
6969         else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
6970           uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
6971           is32&=~(1LL<<rt);
6972           is32|=sr<<rt;
6973         }
6974         else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
6975           if(s1==0&&s2==0) {
6976             is32|=1LL<<rt;
6977           }
6978           else if(s2==0) {
6979             uint64_t sr=((is32>>s1)&1LL);
6980             is32&=~(1LL<<rt);
6981             is32|=sr<<rt;
6982           }
6983           else if(s1==0) {
6984             uint64_t sr=((is32>>s2)&1LL);
6985             is32&=~(1LL<<rt);
6986             is32|=sr<<rt;
6987           }
6988           else {
6989             is32&=~(1LL<<rt);
6990           }
6991         }
6992         else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
6993           if(s1==0&&s2==0) {
6994             is32|=1LL<<rt;
6995           }
6996           else if(s2==0) {
6997             uint64_t sr=((is32>>s1)&1LL);
6998             is32&=~(1LL<<rt);
6999             is32|=sr<<rt;
7000           }
7001           else {
7002             is32&=~(1LL<<rt);
7003           }
7004         }
7005         break;
7006       case MULTDIV:
7007         if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
7008           is32&=~((1LL<<HIREG)|(1LL<<LOREG));
7009         }
7010         else {
7011           is32|=(1LL<<HIREG)|(1LL<<LOREG);
7012         }
7013         break;
7014       case MOV:
7015         {
7016           uint64_t sr=((is32>>s1)&1LL);
7017           is32&=~(1LL<<rt);
7018           is32|=sr<<rt;
7019         }
7020         break;
7021       case SHIFT:
7022         if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
7023         else is32|=1LL<<rt; // SLLV/SRLV/SRAV
7024         break;
7025       case SHIFTIMM:
7026         is32|=1LL<<rt;
7027         // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
7028         if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
7029         break;
7030       case COP0:
7031         if(op2==0) is32|=1LL<<rt; // MFC0
7032         break;
7033       case COP1:
7034       case COP2:
7035         if(op2==0) is32|=1LL<<rt; // MFC1
7036         if(op2==1) is32&=~(1LL<<rt); // DMFC1
7037         if(op2==2) is32|=1LL<<rt; // CFC1
7038         break;
7039       case C1LS:
7040       case C2LS:
7041         break;
7042       case FLOAT:
7043       case FCONV:
7044         break;
7045       case FCOMP:
7046         break;
7047       case C2OP:
7048       case SYSCALL:
7049       case HLECALL:
7050         break;
7051       default:
7052         break;
7053     }
7054     is32|=1;
7055     p32[i]=is32;
7056
7057     if(i>0)
7058     {
7059       if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
7060       {
7061         if(rt1[i-1]==31) // JAL/JALR
7062         {
7063           // Subroutine call will return here, don't alloc any registers
7064           is32=1;
7065         }
7066         else if(i+1<slen)
7067         {
7068           // Internal branch will jump here, match registers to caller
7069           is32=0x3FFFFFFFFLL;
7070         }
7071       }
7072     }
7073   }
7074 }
7075
7076 // Identify registers which may be assumed to contain 32-bit values
7077 // and where optimizations will rely on this.
7078 // This is used to determine whether backward branches can safely
7079 // jump to a location with 64-bit values in registers.
7080 static void provisional_r32()
7081 {
7082   u_int r32=0;
7083   int i;
7084
7085   for (i=slen-1;i>=0;i--)
7086   {
7087     int hr;
7088     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7089     {
7090       if(ba[i]<start || ba[i]>=(start+slen*4))
7091       {
7092         // Branch out of this block, don't need anything
7093         r32=0;
7094       }
7095       else
7096       {
7097         // Internal branch
7098         // Need whatever matches the target
7099         // (and doesn't get overwritten by the delay slot instruction)
7100         r32=0;
7101         int t=(ba[i]-start)>>2;
7102         if(ba[i]>start+i*4) {
7103           // Forward branch
7104           //if(!(requires_32bit[t]&~regs[i].was32))
7105           //  r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7106           if(!(pr32[t]&~regs[i].was32))
7107             r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7108         }else{
7109           // Backward branch
7110           if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
7111             r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7112         }
7113       }
7114       // Conditional branch may need registers for following instructions
7115       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7116       {
7117         if(i<slen-2) {
7118           //r32|=requires_32bit[i+2];
7119           r32|=pr32[i+2];
7120           r32&=regs[i].was32;
7121           // Mark this address as a branch target since it may be called
7122           // upon return from interrupt
7123           //bt[i+2]=1;
7124         }
7125       }
7126       // Merge in delay slot
7127       if(!likely[i]) {
7128         // These are overwritten unless the branch is "likely"
7129         // and the delay slot is nullified if not taken
7130         r32&=~(1LL<<rt1[i+1]);
7131         r32&=~(1LL<<rt2[i+1]);
7132       }
7133       // Assume these are needed (delay slot)
7134       if(us1[i+1]>0)
7135       {
7136         if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7137       }
7138       if(us2[i+1]>0)
7139       {
7140         if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7141       }
7142       if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7143       {
7144         if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7145       }
7146       if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7147       {
7148         if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7149       }
7150     }
7151     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7152     {
7153       // SYSCALL instruction (software interrupt)
7154       r32=0;
7155     }
7156     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7157     {
7158       // ERET instruction (return from interrupt)
7159       r32=0;
7160     }
7161     // Check 32 bits
7162     r32&=~(1LL<<rt1[i]);
7163     r32&=~(1LL<<rt2[i]);
7164     if(us1[i]>0)
7165     {
7166       if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7167     }
7168     if(us2[i]>0)
7169     {
7170       if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7171     }
7172     if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7173     {
7174       if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7175     }
7176     if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7177     {
7178       if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7179     }
7180     //requires_32bit[i]=r32;
7181     pr32[i]=r32;
7182
7183     // Dirty registers which are 32-bit, require 32-bit input
7184     // as they will be written as 32-bit values
7185     for(hr=0;hr<HOST_REGS;hr++)
7186     {
7187       if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
7188         if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7189           if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7190           pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7191           //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7192         }
7193       }
7194     }
7195   }
7196 }
7197
7198 // Write back dirty registers as soon as we will no longer modify them,
7199 // so that we don't end up with lots of writes at the branches.
7200 void clean_registers(int istart,int iend,int wr)
7201 {
7202   int i;
7203   int r;
7204   u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7205   u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7206   if(iend==slen-1) {
7207     will_dirty_i=will_dirty_next=0;
7208     wont_dirty_i=wont_dirty_next=0;
7209   }else{
7210     will_dirty_i=will_dirty_next=will_dirty[iend+1];
7211     wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7212   }
7213   for (i=iend;i>=istart;i--)
7214   {
7215     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7216     {
7217       if(ba[i]<start || ba[i]>=(start+slen*4))
7218       {
7219         // Branch out of this block, flush all regs
7220         if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7221         {
7222           // Unconditional branch
7223           will_dirty_i=0;
7224           wont_dirty_i=0;
7225           // Merge in delay slot (will dirty)
7226           for(r=0;r<HOST_REGS;r++) {
7227             if(r!=EXCLUDE_REG) {
7228               if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7229               if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7230               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7231               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7232               if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7233               if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7234               if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7235               if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7236               if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7237               if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7238               if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7239               if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7240               if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7241               if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7242             }
7243           }
7244         }
7245         else
7246         {
7247           // Conditional branch
7248           will_dirty_i=0;
7249           wont_dirty_i=wont_dirty_next;
7250           // Merge in delay slot (will dirty)
7251           for(r=0;r<HOST_REGS;r++) {
7252             if(r!=EXCLUDE_REG) {
7253               if(!likely[i]) {
7254                 // Might not dirty if likely branch is not taken
7255                 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7256                 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7257                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7258                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7259                 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7260                 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7261                 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7262                 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7263                 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7264                 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7265                 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7266                 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7267                 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7268                 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7269               }
7270             }
7271           }
7272         }
7273         // Merge in delay slot (wont dirty)
7274         for(r=0;r<HOST_REGS;r++) {
7275           if(r!=EXCLUDE_REG) {
7276             if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7277             if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7278             if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7279             if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7280             if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7281             if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7282             if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7283             if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7284             if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7285             if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7286           }
7287         }
7288         if(wr) {
7289           #ifndef DESTRUCTIVE_WRITEBACK
7290           branch_regs[i].dirty&=wont_dirty_i;
7291           #endif
7292           branch_regs[i].dirty|=will_dirty_i;
7293         }
7294       }
7295       else
7296       {
7297         // Internal branch
7298         if(ba[i]<=start+i*4) {
7299           // Backward branch
7300           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7301           {
7302             // Unconditional branch
7303             temp_will_dirty=0;
7304             temp_wont_dirty=0;
7305             // Merge in delay slot (will dirty)
7306             for(r=0;r<HOST_REGS;r++) {
7307               if(r!=EXCLUDE_REG) {
7308                 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7309                 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7310                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7311                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7312                 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7313                 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7314                 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7315                 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7316                 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7317                 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7318                 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7319                 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7320                 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7321                 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7322               }
7323             }
7324           } else {
7325             // Conditional branch (not taken case)
7326             temp_will_dirty=will_dirty_next;
7327             temp_wont_dirty=wont_dirty_next;
7328             // Merge in delay slot (will dirty)
7329             for(r=0;r<HOST_REGS;r++) {
7330               if(r!=EXCLUDE_REG) {
7331                 if(!likely[i]) {
7332                   // Will not dirty if likely branch is not taken
7333                   if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7334                   if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7335                   if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7336                   if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7337                   if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7338                   if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7339                   if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7340                   //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7341                   //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7342                   if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7343                   if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7344                   if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7345                   if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7346                   if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7347                 }
7348               }
7349             }
7350           }
7351           // Merge in delay slot (wont dirty)
7352           for(r=0;r<HOST_REGS;r++) {
7353             if(r!=EXCLUDE_REG) {
7354               if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7355               if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7356               if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7357               if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7358               if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7359               if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7360               if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7361               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7362               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7363               if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7364             }
7365           }
7366           // Deal with changed mappings
7367           if(i<iend) {
7368             for(r=0;r<HOST_REGS;r++) {
7369               if(r!=EXCLUDE_REG) {
7370                 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7371                   temp_will_dirty&=~(1<<r);
7372                   temp_wont_dirty&=~(1<<r);
7373                   if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7374                     temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7375                     temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7376                   } else {
7377                     temp_will_dirty|=1<<r;
7378                     temp_wont_dirty|=1<<r;
7379                   }
7380                 }
7381               }
7382             }
7383           }
7384           if(wr) {
7385             will_dirty[i]=temp_will_dirty;
7386             wont_dirty[i]=temp_wont_dirty;
7387             clean_registers((ba[i]-start)>>2,i-1,0);
7388           }else{
7389             // Limit recursion.  It can take an excessive amount
7390             // of time if there are a lot of nested loops.
7391             will_dirty[(ba[i]-start)>>2]=0;
7392             wont_dirty[(ba[i]-start)>>2]=-1;
7393           }
7394         }
7395         /*else*/ if(1)
7396         {
7397           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7398           {
7399             // Unconditional branch
7400             will_dirty_i=0;
7401             wont_dirty_i=0;
7402           //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7403             for(r=0;r<HOST_REGS;r++) {
7404               if(r!=EXCLUDE_REG) {
7405                 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7406                   will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7407                   wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7408                 }
7409               }
7410             }
7411           //}
7412             // Merge in delay slot
7413             for(r=0;r<HOST_REGS;r++) {
7414               if(r!=EXCLUDE_REG) {
7415                 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7416                 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7417                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7418                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7419                 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7420                 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7421                 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7422                 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7423                 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7424                 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7425                 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7426                 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7427                 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7428                 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7429               }
7430             }
7431           } else {
7432             // Conditional branch
7433             will_dirty_i=will_dirty_next;
7434             wont_dirty_i=wont_dirty_next;
7435           //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7436             for(r=0;r<HOST_REGS;r++) {
7437               if(r!=EXCLUDE_REG) {
7438                 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7439                   will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7440                   wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7441                 }
7442                 else
7443                 {
7444                   will_dirty_i&=~(1<<r);
7445                 }
7446                 // Treat delay slot as part of branch too
7447                 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7448                   will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7449                   wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7450                 }
7451                 else
7452                 {
7453                   will_dirty[i+1]&=~(1<<r);
7454                 }*/
7455               }
7456             }
7457           //}
7458             // Merge in delay slot
7459             for(r=0;r<HOST_REGS;r++) {
7460               if(r!=EXCLUDE_REG) {
7461                 if(!likely[i]) {
7462                   // Might not dirty if likely branch is not taken
7463                   if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7464                   if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7465                   if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7466                   if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7467                   if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7468                   if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7469                   if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7470                   //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7471                   //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7472                   if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7473                   if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7474                   if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7475                   if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7476                   if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7477                 }
7478               }
7479             }
7480           }
7481           // Merge in delay slot
7482           for(r=0;r<HOST_REGS;r++) {
7483             if(r!=EXCLUDE_REG) {
7484               if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7485               if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7486               if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7487               if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7488               if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7489               if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7490               if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7491               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7492               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7493               if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7494             }
7495           }
7496           if(wr) {
7497             #ifndef DESTRUCTIVE_WRITEBACK
7498             branch_regs[i].dirty&=wont_dirty_i;
7499             #endif
7500             branch_regs[i].dirty|=will_dirty_i;
7501           }
7502         }
7503       }
7504     }
7505     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7506     {
7507       // SYSCALL instruction (software interrupt)
7508       will_dirty_i=0;
7509       wont_dirty_i=0;
7510     }
7511     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7512     {
7513       // ERET instruction (return from interrupt)
7514       will_dirty_i=0;
7515       wont_dirty_i=0;
7516     }
7517     will_dirty_next=will_dirty_i;
7518     wont_dirty_next=wont_dirty_i;
7519     for(r=0;r<HOST_REGS;r++) {
7520       if(r!=EXCLUDE_REG) {
7521         if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7522         if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7523         if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7524         if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7525         if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7526         if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7527         if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7528         if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7529         if(i>istart) {
7530           if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7531           {
7532             // Don't store a register immediately after writing it,
7533             // may prevent dual-issue.
7534             if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7535             if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7536           }
7537         }
7538       }
7539     }
7540     // Save it
7541     will_dirty[i]=will_dirty_i;
7542     wont_dirty[i]=wont_dirty_i;
7543     // Mark registers that won't be dirtied as not dirty
7544     if(wr) {
7545       /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7546       for(r=0;r<HOST_REGS;r++) {
7547         if((will_dirty_i>>r)&1) {
7548           printf(" r%d",r);
7549         }
7550       }
7551       printf("\n");*/
7552
7553       //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7554         regs[i].dirty|=will_dirty_i;
7555         #ifndef DESTRUCTIVE_WRITEBACK
7556         regs[i].dirty&=wont_dirty_i;
7557         if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7558         {
7559           if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7560             for(r=0;r<HOST_REGS;r++) {
7561               if(r!=EXCLUDE_REG) {
7562                 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7563                   regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7564                 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7565               }
7566             }
7567           }
7568         }
7569         else
7570         {
7571           if(i<iend) {
7572             for(r=0;r<HOST_REGS;r++) {
7573               if(r!=EXCLUDE_REG) {
7574                 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7575                   regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7576                 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7577               }
7578             }
7579           }
7580         }
7581         #endif
7582       //}
7583     }
7584     // Deal with changed mappings
7585     temp_will_dirty=will_dirty_i;
7586     temp_wont_dirty=wont_dirty_i;
7587     for(r=0;r<HOST_REGS;r++) {
7588       if(r!=EXCLUDE_REG) {
7589         int nr;
7590         if(regs[i].regmap[r]==regmap_pre[i][r]) {
7591           if(wr) {
7592             #ifndef DESTRUCTIVE_WRITEBACK
7593             regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7594             #endif
7595             regs[i].wasdirty|=will_dirty_i&(1<<r);
7596           }
7597         }
7598         else if((nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7599           // Register moved to a different register
7600           will_dirty_i&=~(1<<r);
7601           wont_dirty_i&=~(1<<r);
7602           will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7603           wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7604           if(wr) {
7605             #ifndef DESTRUCTIVE_WRITEBACK
7606             regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7607             #endif
7608             regs[i].wasdirty|=will_dirty_i&(1<<r);
7609           }
7610         }
7611         else {
7612           will_dirty_i&=~(1<<r);
7613           wont_dirty_i&=~(1<<r);
7614           if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7615             will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7616             wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7617           } else {
7618             wont_dirty_i|=1<<r;
7619             /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7620           }
7621         }
7622       }
7623     }
7624   }
7625 }
7626
7627   /* disassembly */
7628 void disassemble_inst(int i)
7629 {
7630     if (bt[i]) printf("*"); else printf(" ");
7631     switch(itype[i]) {
7632       case UJUMP:
7633         printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7634       case CJUMP:
7635         printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7636       case SJUMP:
7637         printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7638       case FJUMP:
7639         printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7640       case RJUMP:
7641         if (opcode[i]==0x9&&rt1[i]!=31)
7642           printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7643         else
7644           printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7645         break;
7646       case SPAN:
7647         printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7648       case IMM16:
7649         if(opcode[i]==0xf) //LUI
7650           printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7651         else
7652           printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7653         break;
7654       case LOAD:
7655       case LOADLR:
7656         printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7657         break;
7658       case STORE:
7659       case STORELR:
7660         printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7661         break;
7662       case ALU:
7663       case SHIFT:
7664         printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7665         break;
7666       case MULTDIV:
7667         printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7668         break;
7669       case SHIFTIMM:
7670         printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7671         break;
7672       case MOV:
7673         if((opcode2[i]&0x1d)==0x10)
7674           printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7675         else if((opcode2[i]&0x1d)==0x11)
7676           printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7677         else
7678           printf (" %x: %s\n",start+i*4,insn[i]);
7679         break;
7680       case COP0:
7681         if(opcode2[i]==0)
7682           printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7683         else if(opcode2[i]==4)
7684           printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7685         else printf (" %x: %s\n",start+i*4,insn[i]);
7686         break;
7687       case COP1:
7688         if(opcode2[i]<3)
7689           printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7690         else if(opcode2[i]>3)
7691           printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7692         else printf (" %x: %s\n",start+i*4,insn[i]);
7693         break;
7694       case COP2:
7695         if(opcode2[i]<3)
7696           printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7697         else if(opcode2[i]>3)
7698           printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7699         else printf (" %x: %s\n",start+i*4,insn[i]);
7700         break;
7701       case C1LS:
7702         printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7703         break;
7704       case C2LS:
7705         printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7706         break;
7707       case INTCALL:
7708         printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
7709         break;
7710       default:
7711         //printf (" %s %8x\n",insn[i],source[i]);
7712         printf (" %x: %s\n",start+i*4,insn[i]);
7713     }
7714 }
7715
7716 // clear the state completely, instead of just marking
7717 // things invalid like invalidate_all_pages() does
7718 void new_dynarec_clear_full()
7719 {
7720   int n;
7721   for(n=0x80000;n<0x80800;n++)
7722     invalid_code[n]=1;
7723   for(n=0;n<65536;n++)
7724     hash_table[n][0]=hash_table[n][2]=-1;
7725   memset(mini_ht,-1,sizeof(mini_ht));
7726   memset(restore_candidate,0,sizeof(restore_candidate));
7727   memset(shadow,0,sizeof(shadow));
7728   copy=shadow;
7729   expirep=16384; // Expiry pointer, +2 blocks
7730   pending_exception=0;
7731   literalcount=0;
7732   stop_after_jal=0;
7733   // TLB
7734 #ifndef DISABLE_TLB
7735   using_tlb=0;
7736 #endif
7737   for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7738     memory_map[n]=-1;
7739   for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7740     memory_map[n]=((u_int)rdram-0x80000000)>>2;
7741   for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7742     memory_map[n]=-1;
7743   for(n=0;n<4096;n++) ll_clear(jump_in+n);
7744   for(n=0;n<4096;n++) ll_clear(jump_out+n);
7745   for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7746 }
7747
7748 void new_dynarec_init()
7749 {
7750   printf("Init new dynarec\n");
7751   out=(u_char *)BASE_ADDR;
7752   if (mmap (out, 1<<TARGET_SIZE_2,
7753             PROT_READ | PROT_WRITE | PROT_EXEC,
7754             MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
7755             -1, 0) <= 0) {printf("mmap() failed\n");}
7756 #ifdef MUPEN64
7757   rdword=&readmem_dword;
7758   fake_pc.f.r.rs=&readmem_dword;
7759   fake_pc.f.r.rt=&readmem_dword;
7760   fake_pc.f.r.rd=&readmem_dword;
7761 #endif
7762   int n;
7763   new_dynarec_clear_full();
7764 #ifdef HOST_IMM8
7765   // Copy this into local area so we don't have to put it in every literal pool
7766   invc_ptr=invalid_code;
7767 #endif
7768 #ifdef MUPEN64
7769   for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
7770     writemem[n] = write_nomem_new;
7771     writememb[n] = write_nomemb_new;
7772     writememh[n] = write_nomemh_new;
7773 #ifndef FORCE32
7774     writememd[n] = write_nomemd_new;
7775 #endif
7776     readmem[n] = read_nomem_new;
7777     readmemb[n] = read_nomemb_new;
7778     readmemh[n] = read_nomemh_new;
7779 #ifndef FORCE32
7780     readmemd[n] = read_nomemd_new;
7781 #endif
7782   }
7783   for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
7784     writemem[n] = write_rdram_new;
7785     writememb[n] = write_rdramb_new;
7786     writememh[n] = write_rdramh_new;
7787 #ifndef FORCE32
7788     writememd[n] = write_rdramd_new;
7789 #endif
7790   }
7791   for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
7792     writemem[n] = write_nomem_new;
7793     writememb[n] = write_nomemb_new;
7794     writememh[n] = write_nomemh_new;
7795 #ifndef FORCE32
7796     writememd[n] = write_nomemd_new;
7797 #endif
7798     readmem[n] = read_nomem_new;
7799     readmemb[n] = read_nomemb_new;
7800     readmemh[n] = read_nomemh_new;
7801 #ifndef FORCE32
7802     readmemd[n] = read_nomemd_new;
7803 #endif
7804   }
7805 #endif
7806   tlb_hacks();
7807   arch_init();
7808 }
7809
7810 void new_dynarec_cleanup()
7811 {
7812   int n;
7813   if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
7814   for(n=0;n<4096;n++) ll_clear(jump_in+n);
7815   for(n=0;n<4096;n++) ll_clear(jump_out+n);
7816   for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7817   #ifdef ROM_COPY
7818   if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
7819   #endif
7820 }
7821
7822 int new_recompile_block(int addr)
7823 {
7824 /*
7825   if(addr==0x800cd050) {
7826     int block;
7827     for(block=0x80000;block<0x80800;block++) invalidate_block(block);
7828     int n;
7829     for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
7830   }
7831 */
7832   //if(Count==365117028) tracedebug=1;
7833   assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7834   //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7835   //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
7836   //if(debug)
7837   //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
7838   //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
7839   /*if(Count>=312978186) {
7840     rlist();
7841   }*/
7842   //rlist();
7843   start = (u_int)addr&~3;
7844   //assert(((u_int)addr&1)==0);
7845 #ifdef PCSX
7846   if (Config.HLE && start == 0x80001000) // hlecall
7847   {
7848     // XXX: is this enough? Maybe check hleSoftCall?
7849     u_int beginning=(u_int)out;
7850     u_int page=get_page(start);
7851     invalid_code[start>>12]=0;
7852     emit_movimm(start,0);
7853     emit_writeword(0,(int)&pcaddr);
7854     emit_jmp((int)new_dyna_leave);
7855 #ifdef __arm__
7856     __clear_cache((void *)beginning,out);
7857 #endif
7858     ll_add(jump_in+page,start,(void *)beginning);
7859     return 0;
7860   }
7861   else if ((u_int)addr < 0x00200000 ||
7862     (0xa0000000 <= addr && addr < 0xa0200000)) {
7863     // used for BIOS calls mostly?
7864     source = (u_int *)((u_int)rdram+(start&0x1fffff));
7865     pagelimit = (addr&0xa0000000)|0x00200000;
7866   }
7867   else if (!Config.HLE && (
7868 /*    (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
7869     (0xbfc00000 <= addr && addr < 0xbfc80000))) {
7870     // BIOS
7871     source = (u_int *)((u_int)psxR+(start&0x7ffff));
7872     pagelimit = (addr&0xfff00000)|0x80000;
7873   }
7874   else
7875 #endif
7876 #ifdef MUPEN64
7877   if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
7878     source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
7879     pagelimit = 0xa4001000;
7880   }
7881   else
7882 #endif
7883   if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
7884     source = (u_int *)((u_int)rdram+start-0x80000000);
7885     pagelimit = 0x80000000+RAM_SIZE;
7886   }
7887 #ifndef DISABLE_TLB
7888   else if ((signed int)addr >= (signed int)0xC0000000) {
7889     //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
7890     //if(tlb_LUT_r[start>>12])
7891       //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
7892     if((signed int)memory_map[start>>12]>=0) {
7893       source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
7894       pagelimit=(start+4096)&0xFFFFF000;
7895       int map=memory_map[start>>12];
7896       int i;
7897       for(i=0;i<5;i++) {
7898         //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
7899         if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
7900       }
7901       assem_debug("pagelimit=%x\n",pagelimit);
7902       assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
7903     }
7904     else {
7905       assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
7906       //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
7907       return -1; // Caller will invoke exception handler
7908     }
7909     //printf("source= %x\n",(int)source);
7910   }
7911 #endif
7912   else {
7913     printf("Compile at bogus memory address: %x \n", (int)addr);
7914     exit(1);
7915   }
7916
7917   /* Pass 1: disassemble */
7918   /* Pass 2: register dependencies, branch targets */
7919   /* Pass 3: register allocation */
7920   /* Pass 4: branch dependencies */
7921   /* Pass 5: pre-alloc */
7922   /* Pass 6: optimize clean/dirty state */
7923   /* Pass 7: flag 32-bit registers */
7924   /* Pass 8: assembly */
7925   /* Pass 9: linker */
7926   /* Pass 10: garbage collection / free memory */
7927
7928   int i,j;
7929   int done=0;
7930   unsigned int type,op,op2;
7931
7932   //printf("addr = %x source = %x %x\n", addr,source,source[0]);
7933
7934   /* Pass 1 disassembly */
7935
7936   for(i=0;!done;i++) {
7937     bt[i]=0;likely[i]=0;ooo[i]=0;op2=0;
7938     minimum_free_regs[i]=0;
7939     opcode[i]=op=source[i]>>26;
7940     switch(op)
7941     {
7942       case 0x00: strcpy(insn[i],"special"); type=NI;
7943         op2=source[i]&0x3f;
7944         switch(op2)
7945         {
7946           case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
7947           case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
7948           case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
7949           case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
7950           case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
7951           case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
7952           case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
7953           case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
7954           case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
7955           case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
7956           case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
7957           case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
7958           case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
7959           case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
7960           case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
7961           case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
7962           case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
7963           case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
7964           case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
7965           case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
7966           case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
7967           case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
7968           case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
7969           case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
7970           case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
7971           case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
7972           case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
7973           case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
7974           case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
7975           case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
7976           case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
7977           case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
7978           case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
7979           case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
7980           case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
7981           case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
7982           case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
7983           case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
7984           case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
7985           case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
7986           case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
7987           case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
7988           case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
7989           case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
7990           case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
7991           case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
7992           case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
7993           case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
7994           case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
7995           case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
7996           case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
7997           case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
7998         }
7999         break;
8000       case 0x01: strcpy(insn[i],"regimm"); type=NI;
8001         op2=(source[i]>>16)&0x1f;
8002         switch(op2)
8003         {
8004           case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
8005           case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
8006           case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
8007           case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
8008           case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
8009           case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
8010           case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
8011           case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
8012           case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
8013           case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
8014           case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
8015           case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
8016           case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
8017           case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
8018         }
8019         break;
8020       case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
8021       case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
8022       case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
8023       case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
8024       case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
8025       case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
8026       case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
8027       case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
8028       case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
8029       case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
8030       case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
8031       case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
8032       case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
8033       case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
8034       case 0x10: strcpy(insn[i],"cop0"); type=NI;
8035         op2=(source[i]>>21)&0x1f;
8036         switch(op2)
8037         {
8038           case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
8039           case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
8040           case 0x10: strcpy(insn[i],"tlb"); type=NI;
8041           switch(source[i]&0x3f)
8042           {
8043             case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
8044             case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
8045             case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
8046             case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
8047 #ifdef PCSX
8048             case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
8049 #else
8050             case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
8051 #endif
8052           }
8053         }
8054         break;
8055       case 0x11: strcpy(insn[i],"cop1"); type=NI;
8056         op2=(source[i]>>21)&0x1f;
8057         switch(op2)
8058         {
8059           case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
8060           case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
8061           case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
8062           case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
8063           case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
8064           case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
8065           case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
8066           switch((source[i]>>16)&0x3)
8067           {
8068             case 0x00: strcpy(insn[i],"BC1F"); break;
8069             case 0x01: strcpy(insn[i],"BC1T"); break;
8070             case 0x02: strcpy(insn[i],"BC1FL"); break;
8071             case 0x03: strcpy(insn[i],"BC1TL"); break;
8072           }
8073           break;
8074           case 0x10: strcpy(insn[i],"C1.S"); type=NI;
8075           switch(source[i]&0x3f)
8076           {
8077             case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
8078             case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
8079             case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
8080             case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
8081             case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
8082             case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
8083             case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
8084             case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
8085             case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
8086             case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
8087             case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
8088             case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
8089             case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
8090             case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
8091             case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
8092             case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
8093             case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
8094             case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
8095             case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
8096             case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
8097             case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
8098             case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
8099             case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
8100             case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
8101             case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
8102             case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
8103             case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
8104             case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
8105             case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
8106             case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
8107             case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
8108             case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
8109             case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
8110             case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
8111             case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
8112           }
8113           break;
8114           case 0x11: strcpy(insn[i],"C1.D"); type=NI;
8115           switch(source[i]&0x3f)
8116           {
8117             case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
8118             case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
8119             case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
8120             case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
8121             case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
8122             case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
8123             case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
8124             case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
8125             case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
8126             case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
8127             case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
8128             case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
8129             case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
8130             case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
8131             case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
8132             case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
8133             case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
8134             case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
8135             case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
8136             case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
8137             case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
8138             case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
8139             case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
8140             case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
8141             case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
8142             case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
8143             case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
8144             case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
8145             case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
8146             case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
8147             case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8148             case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8149             case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8150             case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8151             case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8152           }
8153           break;
8154           case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8155           switch(source[i]&0x3f)
8156           {
8157             case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8158             case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8159           }
8160           break;
8161           case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8162           switch(source[i]&0x3f)
8163           {
8164             case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8165             case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8166           }
8167           break;
8168         }
8169         break;
8170 #ifndef FORCE32
8171       case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8172       case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8173       case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8174       case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8175       case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8176       case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8177       case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8178       case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
8179 #endif
8180       case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8181       case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8182       case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8183       case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8184       case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8185       case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8186       case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
8187       case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
8188       case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8189       case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8190       case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8191       case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
8192 #ifndef FORCE32
8193       case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8194       case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
8195 #endif
8196       case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8197       case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8198       case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8199       case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
8200 #ifndef FORCE32
8201       case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8202       case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8203       case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
8204 #endif
8205       case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8206       case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
8207 #ifndef FORCE32
8208       case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8209       case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8210       case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
8211 #endif
8212 #ifdef PCSX
8213       case 0x12: strcpy(insn[i],"COP2"); type=NI;
8214         // note: COP MIPS-1 encoding differs from MIPS32
8215         op2=(source[i]>>21)&0x1f;
8216         if (source[i]&0x3f) {
8217           if (gte_handlers[source[i]&0x3f]!=NULL) {
8218             snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8219             type=C2OP;
8220           }
8221         }
8222         else switch(op2)
8223         {
8224           case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8225           case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8226           case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8227           case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
8228         }
8229         break;
8230       case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8231       case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8232       case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8233 #endif
8234       default: strcpy(insn[i],"???"); type=NI;
8235         printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
8236         break;
8237     }
8238     itype[i]=type;
8239     opcode2[i]=op2;
8240     /* Get registers/immediates */
8241     lt1[i]=0;
8242     us1[i]=0;
8243     us2[i]=0;
8244     dep1[i]=0;
8245     dep2[i]=0;
8246     switch(type) {
8247       case LOAD:
8248         rs1[i]=(source[i]>>21)&0x1f;
8249         rs2[i]=0;
8250         rt1[i]=(source[i]>>16)&0x1f;
8251         rt2[i]=0;
8252         imm[i]=(short)source[i];
8253         break;
8254       case STORE:
8255       case STORELR:
8256         rs1[i]=(source[i]>>21)&0x1f;
8257         rs2[i]=(source[i]>>16)&0x1f;
8258         rt1[i]=0;
8259         rt2[i]=0;
8260         imm[i]=(short)source[i];
8261         if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8262         break;
8263       case LOADLR:
8264         // LWL/LWR only load part of the register,
8265         // therefore the target register must be treated as a source too
8266         rs1[i]=(source[i]>>21)&0x1f;
8267         rs2[i]=(source[i]>>16)&0x1f;
8268         rt1[i]=(source[i]>>16)&0x1f;
8269         rt2[i]=0;
8270         imm[i]=(short)source[i];
8271         if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8272         if(op==0x26) dep1[i]=rt1[i]; // LWR
8273         break;
8274       case IMM16:
8275         if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8276         else rs1[i]=(source[i]>>21)&0x1f;
8277         rs2[i]=0;
8278         rt1[i]=(source[i]>>16)&0x1f;
8279         rt2[i]=0;
8280         if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8281           imm[i]=(unsigned short)source[i];
8282         }else{
8283           imm[i]=(short)source[i];
8284         }
8285         if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8286         if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8287         if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8288         break;
8289       case UJUMP:
8290         rs1[i]=0;
8291         rs2[i]=0;
8292         rt1[i]=0;
8293         rt2[i]=0;
8294         // The JAL instruction writes to r31.
8295         if (op&1) {
8296           rt1[i]=31;
8297         }
8298         rs2[i]=CCREG;
8299         break;
8300       case RJUMP:
8301         rs1[i]=(source[i]>>21)&0x1f;
8302         rs2[i]=0;
8303         rt1[i]=0;
8304         rt2[i]=0;
8305         // The JALR instruction writes to rd.
8306         if (op2&1) {
8307           rt1[i]=(source[i]>>11)&0x1f;
8308         }
8309         rs2[i]=CCREG;
8310         break;
8311       case CJUMP:
8312         rs1[i]=(source[i]>>21)&0x1f;
8313         rs2[i]=(source[i]>>16)&0x1f;
8314         rt1[i]=0;
8315         rt2[i]=0;
8316         if(op&2) { // BGTZ/BLEZ
8317           rs2[i]=0;
8318         }
8319         us1[i]=rs1[i];
8320         us2[i]=rs2[i];
8321         likely[i]=op>>4;
8322         break;
8323       case SJUMP:
8324         rs1[i]=(source[i]>>21)&0x1f;
8325         rs2[i]=CCREG;
8326         rt1[i]=0;
8327         rt2[i]=0;
8328         us1[i]=rs1[i];
8329         if(op2&0x10) { // BxxAL
8330           rt1[i]=31;
8331           // NOTE: If the branch is not taken, r31 is still overwritten
8332         }
8333         likely[i]=(op2&2)>>1;
8334         break;
8335       case FJUMP:
8336         rs1[i]=FSREG;
8337         rs2[i]=CSREG;
8338         rt1[i]=0;
8339         rt2[i]=0;
8340         likely[i]=((source[i])>>17)&1;
8341         break;
8342       case ALU:
8343         rs1[i]=(source[i]>>21)&0x1f; // source
8344         rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8345         rt1[i]=(source[i]>>11)&0x1f; // destination
8346         rt2[i]=0;
8347         if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8348           us1[i]=rs1[i];us2[i]=rs2[i];
8349         }
8350         else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8351           dep1[i]=rs1[i];dep2[i]=rs2[i];
8352         }
8353         else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8354           dep1[i]=rs1[i];dep2[i]=rs2[i];
8355         }
8356         break;
8357       case MULTDIV:
8358         rs1[i]=(source[i]>>21)&0x1f; // source
8359         rs2[i]=(source[i]>>16)&0x1f; // divisor
8360         rt1[i]=HIREG;
8361         rt2[i]=LOREG;
8362         if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8363           us1[i]=rs1[i];us2[i]=rs2[i];
8364         }
8365         break;
8366       case MOV:
8367         rs1[i]=0;
8368         rs2[i]=0;
8369         rt1[i]=0;
8370         rt2[i]=0;
8371         if(op2==0x10) rs1[i]=HIREG; // MFHI
8372         if(op2==0x11) rt1[i]=HIREG; // MTHI
8373         if(op2==0x12) rs1[i]=LOREG; // MFLO
8374         if(op2==0x13) rt1[i]=LOREG; // MTLO
8375         if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8376         if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8377         dep1[i]=rs1[i];
8378         break;
8379       case SHIFT:
8380         rs1[i]=(source[i]>>16)&0x1f; // target of shift
8381         rs2[i]=(source[i]>>21)&0x1f; // shift amount
8382         rt1[i]=(source[i]>>11)&0x1f; // destination
8383         rt2[i]=0;
8384         // DSLLV/DSRLV/DSRAV are 64-bit
8385         if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8386         break;
8387       case SHIFTIMM:
8388         rs1[i]=(source[i]>>16)&0x1f;
8389         rs2[i]=0;
8390         rt1[i]=(source[i]>>11)&0x1f;
8391         rt2[i]=0;
8392         imm[i]=(source[i]>>6)&0x1f;
8393         // DSxx32 instructions
8394         if(op2>=0x3c) imm[i]|=0x20;
8395         // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8396         if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8397         break;
8398       case COP0:
8399         rs1[i]=0;
8400         rs2[i]=0;
8401         rt1[i]=0;
8402         rt2[i]=0;
8403         if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8404         if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8405         if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8406         if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8407         break;
8408       case COP1:
8409       case COP2:
8410         rs1[i]=0;
8411         rs2[i]=0;
8412         rt1[i]=0;
8413         rt2[i]=0;
8414         if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8415         if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8416         if(op2==5) us1[i]=rs1[i]; // DMTC1
8417         rs2[i]=CSREG;
8418         break;
8419       case C1LS:
8420         rs1[i]=(source[i]>>21)&0x1F;
8421         rs2[i]=CSREG;
8422         rt1[i]=0;
8423         rt2[i]=0;
8424         imm[i]=(short)source[i];
8425         break;
8426       case C2LS:
8427         rs1[i]=(source[i]>>21)&0x1F;
8428         rs2[i]=0;
8429         rt1[i]=0;
8430         rt2[i]=0;
8431         imm[i]=(short)source[i];
8432         break;
8433       case FLOAT:
8434       case FCONV:
8435         rs1[i]=0;
8436         rs2[i]=CSREG;
8437         rt1[i]=0;
8438         rt2[i]=0;
8439         break;
8440       case FCOMP:
8441         rs1[i]=FSREG;
8442         rs2[i]=CSREG;
8443         rt1[i]=FSREG;
8444         rt2[i]=0;
8445         break;
8446       case SYSCALL:
8447       case HLECALL:
8448       case INTCALL:
8449         rs1[i]=CCREG;
8450         rs2[i]=0;
8451         rt1[i]=0;
8452         rt2[i]=0;
8453         break;
8454       default:
8455         rs1[i]=0;
8456         rs2[i]=0;
8457         rt1[i]=0;
8458         rt2[i]=0;
8459     }
8460     /* Calculate branch target addresses */
8461     if(type==UJUMP)
8462       ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8463     else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8464       ba[i]=start+i*4+8; // Ignore never taken branch
8465     else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8466       ba[i]=start+i*4+8; // Ignore never taken branch
8467     else if(type==CJUMP||type==SJUMP||type==FJUMP)
8468       ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8469     else ba[i]=-1;
8470 #ifdef PCSX
8471     if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
8472       int do_in_intrp=0;
8473       // branch in delay slot?
8474       if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
8475         // don't handle first branch and call interpreter if it's hit
8476         printf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
8477         do_in_intrp=1;
8478       }
8479       // basic load delay detection
8480       else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&rt1[i]!=0) {
8481         int t=(ba[i-1]-start)/4;
8482         if(0 <= t && t < i &&(rt1[i]==rs1[t]||rt1[i]==rs2[t])&&itype[t]!=CJUMP&&itype[t]!=SJUMP) {
8483           // jump target wants DS result - potential load delay effect
8484           printf("load delay @%08x (%08x)\n", addr + i*4, addr);
8485           do_in_intrp=1;
8486           bt[t+1]=1; // expected return from interpreter
8487         }
8488         else if(i>=2&&rt1[i-2]==2&&rt1[i]==2&&rs1[i]!=2&&rs2[i]!=2&&rs1[i-1]!=2&&rs2[i-1]!=2&&
8489               !(i>=3&&(itype[i-3]==RJUMP||itype[i-3]==UJUMP||itype[i-3]==CJUMP||itype[i-3]==SJUMP))) {
8490           // v0 overwrite like this is a sign of trouble, bail out
8491           printf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
8492           do_in_intrp=1;
8493         }
8494       }
8495       if(do_in_intrp) {
8496         rs1[i-1]=CCREG;
8497         rs2[i-1]=rt1[i-1]=rt2[i-1]=0;
8498         ba[i-1]=-1;
8499         itype[i-1]=INTCALL;
8500         done=2;
8501         i--; // don't compile the DS
8502       }
8503     }
8504 #endif
8505     /* Is this the end of the block? */
8506     if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
8507       if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
8508         done=2;
8509       }
8510       else {
8511         if(stop_after_jal) done=1;
8512         // Stop on BREAK
8513         if((source[i+1]&0xfc00003f)==0x0d) done=1;
8514       }
8515       // Don't recompile stuff that's already compiled
8516       if(check_addr(start+i*4+4)) done=1;
8517       // Don't get too close to the limit
8518       if(i>MAXBLOCK/2) done=1;
8519     }
8520     if(itype[i]==SYSCALL&&stop_after_jal) done=1;
8521     if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
8522     if(done==2) {
8523       // Does the block continue due to a branch?
8524       for(j=i-1;j>=0;j--)
8525       {
8526         if(ba[j]==start+i*4+4) done=j=0;
8527         if(ba[j]==start+i*4+8) done=j=0;
8528       }
8529     }
8530     //assert(i<MAXBLOCK-1);
8531     if(start+i*4==pagelimit-4) done=1;
8532     assert(start+i*4<pagelimit);
8533     if (i==MAXBLOCK-1) done=1;
8534     // Stop if we're compiling junk
8535     if(itype[i]==NI&&opcode[i]==0x11) {
8536       done=stop_after_jal=1;
8537       printf("Disabled speculative precompilation\n");
8538     }
8539   }
8540   slen=i;
8541   if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8542     if(start+i*4==pagelimit) {
8543       itype[i-1]=SPAN;
8544     }
8545   }
8546   assert(slen>0);
8547
8548   /* Pass 2 - Register dependencies and branch targets */
8549
8550   unneeded_registers(0,slen-1,0);
8551
8552   /* Pass 3 - Register allocation */
8553
8554   struct regstat current; // Current register allocations/status
8555   current.is32=1;
8556   current.dirty=0;
8557   current.u=unneeded_reg[0];
8558   current.uu=unneeded_reg_upper[0];
8559   clear_all_regs(current.regmap);
8560   alloc_reg(&current,0,CCREG);
8561   dirty_reg(&current,CCREG);
8562   current.isconst=0;
8563   current.wasconst=0;
8564   int ds=0;
8565   int cc=0;
8566   int hr;
8567
8568 #ifndef FORCE32
8569   provisional_32bit();
8570 #endif
8571   if((u_int)addr&1) {
8572     // First instruction is delay slot
8573     cc=-1;
8574     bt[1]=1;
8575     ds=1;
8576     unneeded_reg[0]=1;
8577     unneeded_reg_upper[0]=1;
8578     current.regmap[HOST_BTREG]=BTREG;
8579   }
8580
8581   for(i=0;i<slen;i++)
8582   {
8583     if(bt[i])
8584     {
8585       int hr;
8586       for(hr=0;hr<HOST_REGS;hr++)
8587       {
8588         // Is this really necessary?
8589         if(current.regmap[hr]==0) current.regmap[hr]=-1;
8590       }
8591       current.isconst=0;
8592     }
8593     if(i>1)
8594     {
8595       if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8596       {
8597         if(rs1[i-2]==0||rs2[i-2]==0)
8598         {
8599           if(rs1[i-2]) {
8600             current.is32|=1LL<<rs1[i-2];
8601             int hr=get_reg(current.regmap,rs1[i-2]|64);
8602             if(hr>=0) current.regmap[hr]=-1;
8603           }
8604           if(rs2[i-2]) {
8605             current.is32|=1LL<<rs2[i-2];
8606             int hr=get_reg(current.regmap,rs2[i-2]|64);
8607             if(hr>=0) current.regmap[hr]=-1;
8608           }
8609         }
8610       }
8611     }
8612 #ifndef FORCE32
8613     // If something jumps here with 64-bit values
8614     // then promote those registers to 64 bits
8615     if(bt[i])
8616     {
8617       uint64_t temp_is32=current.is32;
8618       for(j=i-1;j>=0;j--)
8619       {
8620         if(ba[j]==start+i*4)
8621           temp_is32&=branch_regs[j].is32;
8622       }
8623       for(j=i;j<slen;j++)
8624       {
8625         if(ba[j]==start+i*4)
8626           //temp_is32=1;
8627           temp_is32&=p32[j];
8628       }
8629       if(temp_is32!=current.is32) {
8630         //printf("dumping 32-bit regs (%x)\n",start+i*4);
8631         #ifdef DESTRUCTIVE_WRITEBACK
8632         for(hr=0;hr<HOST_REGS;hr++)
8633         {
8634           int r=current.regmap[hr];
8635           if(r>0&&r<64)
8636           {
8637             if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8638               temp_is32|=1LL<<r;
8639               //printf("restore %d\n",r);
8640             }
8641           }
8642         }
8643         #endif
8644         current.is32=temp_is32;
8645       }
8646     }
8647 #else
8648     current.is32=-1LL;
8649 #endif
8650
8651     memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8652     regs[i].wasconst=current.isconst;
8653     regs[i].was32=current.is32;
8654     regs[i].wasdirty=current.dirty;
8655     #if defined(DESTRUCTIVE_WRITEBACK) && !defined(FORCE32)
8656     // To change a dirty register from 32 to 64 bits, we must write
8657     // it out during the previous cycle (for branches, 2 cycles)
8658     if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8659     {
8660       uint64_t temp_is32=current.is32;
8661       for(j=i-1;j>=0;j--)
8662       {
8663         if(ba[j]==start+i*4+4)
8664           temp_is32&=branch_regs[j].is32;
8665       }
8666       for(j=i;j<slen;j++)
8667       {
8668         if(ba[j]==start+i*4+4)
8669           //temp_is32=1;
8670           temp_is32&=p32[j];
8671       }
8672       if(temp_is32!=current.is32) {
8673         //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8674         for(hr=0;hr<HOST_REGS;hr++)
8675         {
8676           int r=current.regmap[hr];
8677           if(r>0)
8678           {
8679             if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8680               if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
8681               {
8682                 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
8683                 {
8684                   //printf("dump %d/r%d\n",hr,r);
8685                   current.regmap[hr]=-1;
8686                   if(get_reg(current.regmap,r|64)>=0)
8687                     current.regmap[get_reg(current.regmap,r|64)]=-1;
8688                 }
8689               }
8690             }
8691           }
8692         }
8693       }
8694     }
8695     else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
8696     {
8697       uint64_t temp_is32=current.is32;
8698       for(j=i-1;j>=0;j--)
8699       {
8700         if(ba[j]==start+i*4+8)
8701           temp_is32&=branch_regs[j].is32;
8702       }
8703       for(j=i;j<slen;j++)
8704       {
8705         if(ba[j]==start+i*4+8)
8706           //temp_is32=1;
8707           temp_is32&=p32[j];
8708       }
8709       if(temp_is32!=current.is32) {
8710         //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8711         for(hr=0;hr<HOST_REGS;hr++)
8712         {
8713           int r=current.regmap[hr];
8714           if(r>0)
8715           {
8716             if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8717               if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
8718               {
8719                 //printf("dump %d/r%d\n",hr,r);
8720                 current.regmap[hr]=-1;
8721                 if(get_reg(current.regmap,r|64)>=0)
8722                   current.regmap[get_reg(current.regmap,r|64)]=-1;
8723               }
8724             }
8725           }
8726         }
8727       }
8728     }
8729     #endif
8730     if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8731       if(i+1<slen) {
8732         current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8733         current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8734         if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8735         current.u|=1;
8736         current.uu|=1;
8737       } else {
8738         current.u=1;
8739         current.uu=1;
8740       }
8741     } else {
8742       if(i+1<slen) {
8743         current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
8744         current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8745         if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8746         current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8747         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8748         current.u|=1;
8749         current.uu|=1;
8750       } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
8751     }
8752     is_ds[i]=ds;
8753     if(ds) {
8754       ds=0; // Skip delay slot, already allocated as part of branch
8755       // ...but we need to alloc it in case something jumps here
8756       if(i+1<slen) {
8757         current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
8758         current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
8759       }else{
8760         current.u=branch_unneeded_reg[i-1];
8761         current.uu=branch_unneeded_reg_upper[i-1];
8762       }
8763       current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8764       current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8765       if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8766       current.u|=1;
8767       current.uu|=1;
8768       struct regstat temp;
8769       memcpy(&temp,&current,sizeof(current));
8770       temp.wasdirty=temp.dirty;
8771       temp.was32=temp.is32;
8772       // TODO: Take into account unconditional branches, as below
8773       delayslot_alloc(&temp,i);
8774       memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
8775       regs[i].wasdirty=temp.wasdirty;
8776       regs[i].was32=temp.was32;
8777       regs[i].dirty=temp.dirty;
8778       regs[i].is32=temp.is32;
8779       regs[i].isconst=0;
8780       regs[i].wasconst=0;
8781       current.isconst=0;
8782       // Create entry (branch target) regmap
8783       for(hr=0;hr<HOST_REGS;hr++)
8784       {
8785         int r=temp.regmap[hr];
8786         if(r>=0) {
8787           if(r!=regmap_pre[i][hr]) {
8788             regs[i].regmap_entry[hr]=-1;
8789           }
8790           else
8791           {
8792             if(r<64){
8793               if((current.u>>r)&1) {
8794                 regs[i].regmap_entry[hr]=-1;
8795                 regs[i].regmap[hr]=-1;
8796                 //Don't clear regs in the delay slot as the branch might need them
8797                 //current.regmap[hr]=-1;
8798               }else
8799                 regs[i].regmap_entry[hr]=r;
8800             }
8801             else {
8802               if((current.uu>>(r&63))&1) {
8803                 regs[i].regmap_entry[hr]=-1;
8804                 regs[i].regmap[hr]=-1;
8805                 //Don't clear regs in the delay slot as the branch might need them
8806                 //current.regmap[hr]=-1;
8807               }else
8808                 regs[i].regmap_entry[hr]=r;
8809             }
8810           }
8811         } else {
8812           // First instruction expects CCREG to be allocated
8813           if(i==0&&hr==HOST_CCREG)
8814             regs[i].regmap_entry[hr]=CCREG;
8815           else
8816             regs[i].regmap_entry[hr]=-1;
8817         }
8818       }
8819     }
8820     else { // Not delay slot
8821       switch(itype[i]) {
8822         case UJUMP:
8823           //current.isconst=0; // DEBUG
8824           //current.wasconst=0; // DEBUG
8825           //regs[i].wasconst=0; // DEBUG
8826           clear_const(&current,rt1[i]);
8827           alloc_cc(&current,i);
8828           dirty_reg(&current,CCREG);
8829           if (rt1[i]==31) {
8830             alloc_reg(&current,i,31);
8831             dirty_reg(&current,31);
8832             //assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8833             //assert(rt1[i+1]!=rt1[i]);
8834             #ifdef REG_PREFETCH
8835             alloc_reg(&current,i,PTEMP);
8836             #endif
8837             //current.is32|=1LL<<rt1[i];
8838           }
8839           ooo[i]=1;
8840           delayslot_alloc(&current,i+1);
8841           //current.isconst=0; // DEBUG
8842           ds=1;
8843           //printf("i=%d, isconst=%x\n",i,current.isconst);
8844           break;
8845         case RJUMP:
8846           //current.isconst=0;
8847           //current.wasconst=0;
8848           //regs[i].wasconst=0;
8849           clear_const(&current,rs1[i]);
8850           clear_const(&current,rt1[i]);
8851           alloc_cc(&current,i);
8852           dirty_reg(&current,CCREG);
8853           if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
8854             alloc_reg(&current,i,rs1[i]);
8855             if (rt1[i]!=0) {
8856               alloc_reg(&current,i,rt1[i]);
8857               dirty_reg(&current,rt1[i]);
8858               assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
8859               assert(rt1[i+1]!=rt1[i]);
8860               #ifdef REG_PREFETCH
8861               alloc_reg(&current,i,PTEMP);
8862               #endif
8863             }
8864             #ifdef USE_MINI_HT
8865             if(rs1[i]==31) { // JALR
8866               alloc_reg(&current,i,RHASH);
8867               #ifndef HOST_IMM_ADDR32
8868               alloc_reg(&current,i,RHTBL);
8869               #endif
8870             }
8871             #endif
8872             delayslot_alloc(&current,i+1);
8873           } else {
8874             // The delay slot overwrites our source register,
8875             // allocate a temporary register to hold the old value.
8876             current.isconst=0;
8877             current.wasconst=0;
8878             regs[i].wasconst=0;
8879             delayslot_alloc(&current,i+1);
8880             current.isconst=0;
8881             alloc_reg(&current,i,RTEMP);
8882           }
8883           //current.isconst=0; // DEBUG
8884           ooo[i]=1;
8885           ds=1;
8886           break;
8887         case CJUMP:
8888           //current.isconst=0;
8889           //current.wasconst=0;
8890           //regs[i].wasconst=0;
8891           clear_const(&current,rs1[i]);
8892           clear_const(&current,rs2[i]);
8893           if((opcode[i]&0x3E)==4) // BEQ/BNE
8894           {
8895             alloc_cc(&current,i);
8896             dirty_reg(&current,CCREG);
8897             if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8898             if(rs2[i]) alloc_reg(&current,i,rs2[i]);
8899             if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8900             {
8901               if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8902               if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
8903             }
8904             if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
8905                (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
8906               // The delay slot overwrites one of our conditions.
8907               // Allocate the branch condition registers instead.
8908               current.isconst=0;
8909               current.wasconst=0;
8910               regs[i].wasconst=0;
8911               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8912               if(rs2[i]) alloc_reg(&current,i,rs2[i]);
8913               if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8914               {
8915                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8916                 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
8917               }
8918             }
8919             else
8920             {
8921               ooo[i]=1;
8922               delayslot_alloc(&current,i+1);
8923             }
8924           }
8925           else
8926           if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
8927           {
8928             alloc_cc(&current,i);
8929             dirty_reg(&current,CCREG);
8930             alloc_reg(&current,i,rs1[i]);
8931             if(!(current.is32>>rs1[i]&1))
8932             {
8933               alloc_reg64(&current,i,rs1[i]);
8934             }
8935             if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
8936               // The delay slot overwrites one of our conditions.
8937               // Allocate the branch condition registers instead.
8938               current.isconst=0;
8939               current.wasconst=0;
8940               regs[i].wasconst=0;
8941               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8942               if(!((current.is32>>rs1[i])&1))
8943               {
8944                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8945               }
8946             }
8947             else
8948             {
8949               ooo[i]=1;
8950               delayslot_alloc(&current,i+1);
8951             }
8952           }
8953           else
8954           // Don't alloc the delay slot yet because we might not execute it
8955           if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
8956           {
8957             current.isconst=0;
8958             current.wasconst=0;
8959             regs[i].wasconst=0;
8960             alloc_cc(&current,i);
8961             dirty_reg(&current,CCREG);
8962             alloc_reg(&current,i,rs1[i]);
8963             alloc_reg(&current,i,rs2[i]);
8964             if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8965             {
8966               alloc_reg64(&current,i,rs1[i]);
8967               alloc_reg64(&current,i,rs2[i]);
8968             }
8969           }
8970           else
8971           if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
8972           {
8973             current.isconst=0;
8974             current.wasconst=0;
8975             regs[i].wasconst=0;
8976             alloc_cc(&current,i);
8977             dirty_reg(&current,CCREG);
8978             alloc_reg(&current,i,rs1[i]);
8979             if(!(current.is32>>rs1[i]&1))
8980             {
8981               alloc_reg64(&current,i,rs1[i]);
8982             }
8983           }
8984           ds=1;
8985           //current.isconst=0;
8986           break;
8987         case SJUMP:
8988           //current.isconst=0;
8989           //current.wasconst=0;
8990           //regs[i].wasconst=0;
8991           clear_const(&current,rs1[i]);
8992           clear_const(&current,rt1[i]);
8993           //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
8994           if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
8995           {
8996             alloc_cc(&current,i);
8997             dirty_reg(&current,CCREG);
8998             alloc_reg(&current,i,rs1[i]);
8999             if(!(current.is32>>rs1[i]&1))
9000             {
9001               alloc_reg64(&current,i,rs1[i]);
9002             }
9003             if (rt1[i]==31) { // BLTZAL/BGEZAL
9004               alloc_reg(&current,i,31);
9005               dirty_reg(&current,31);
9006               //#ifdef REG_PREFETCH
9007               //alloc_reg(&current,i,PTEMP);
9008               //#endif
9009               //current.is32|=1LL<<rt1[i];
9010             }
9011             if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) // The delay slot overwrites the branch condition.
9012                ||(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))) { // DS touches $ra
9013               // Allocate the branch condition registers instead.
9014               current.isconst=0;
9015               current.wasconst=0;
9016               regs[i].wasconst=0;
9017               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9018               if(!((current.is32>>rs1[i])&1))
9019               {
9020                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9021               }
9022             }
9023             else
9024             {
9025               ooo[i]=1;
9026               delayslot_alloc(&current,i+1);
9027             }
9028           }
9029           else
9030           // Don't alloc the delay slot yet because we might not execute it
9031           if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
9032           {
9033             current.isconst=0;
9034             current.wasconst=0;
9035             regs[i].wasconst=0;
9036             alloc_cc(&current,i);
9037             dirty_reg(&current,CCREG);
9038             alloc_reg(&current,i,rs1[i]);
9039             if(!(current.is32>>rs1[i]&1))
9040             {
9041               alloc_reg64(&current,i,rs1[i]);
9042             }
9043           }
9044           ds=1;
9045           //current.isconst=0;
9046           break;
9047         case FJUMP:
9048           current.isconst=0;
9049           current.wasconst=0;
9050           regs[i].wasconst=0;
9051           if(likely[i]==0) // BC1F/BC1T
9052           {
9053             // TODO: Theoretically we can run out of registers here on x86.
9054             // The delay slot can allocate up to six, and we need to check
9055             // CSREG before executing the delay slot.  Possibly we can drop
9056             // the cycle count and then reload it after checking that the
9057             // FPU is in a usable state, or don't do out-of-order execution.
9058             alloc_cc(&current,i);
9059             dirty_reg(&current,CCREG);
9060             alloc_reg(&current,i,FSREG);
9061             alloc_reg(&current,i,CSREG);
9062             if(itype[i+1]==FCOMP) {
9063               // The delay slot overwrites the branch condition.
9064               // Allocate the branch condition registers instead.
9065               alloc_cc(&current,i);
9066               dirty_reg(&current,CCREG);
9067               alloc_reg(&current,i,CSREG);
9068               alloc_reg(&current,i,FSREG);
9069             }
9070             else {
9071               ooo[i]=1;
9072               delayslot_alloc(&current,i+1);
9073               alloc_reg(&current,i+1,CSREG);
9074             }
9075           }
9076           else
9077           // Don't alloc the delay slot yet because we might not execute it
9078           if(likely[i]) // BC1FL/BC1TL
9079           {
9080             alloc_cc(&current,i);
9081             dirty_reg(&current,CCREG);
9082             alloc_reg(&current,i,CSREG);
9083             alloc_reg(&current,i,FSREG);
9084           }
9085           ds=1;
9086           current.isconst=0;
9087           break;
9088         case IMM16:
9089           imm16_alloc(&current,i);
9090           break;
9091         case LOAD:
9092         case LOADLR:
9093           load_alloc(&current,i);
9094           break;
9095         case STORE:
9096         case STORELR:
9097           store_alloc(&current,i);
9098           break;
9099         case ALU:
9100           alu_alloc(&current,i);
9101           break;
9102         case SHIFT:
9103           shift_alloc(&current,i);
9104           break;
9105         case MULTDIV:
9106           multdiv_alloc(&current,i);
9107           break;
9108         case SHIFTIMM:
9109           shiftimm_alloc(&current,i);
9110           break;
9111         case MOV:
9112           mov_alloc(&current,i);
9113           break;
9114         case COP0:
9115           cop0_alloc(&current,i);
9116           break;
9117         case COP1:
9118         case COP2:
9119           cop1_alloc(&current,i);
9120           break;
9121         case C1LS:
9122           c1ls_alloc(&current,i);
9123           break;
9124         case C2LS:
9125           c2ls_alloc(&current,i);
9126           break;
9127         case C2OP:
9128           c2op_alloc(&current,i);
9129           break;
9130         case FCONV:
9131           fconv_alloc(&current,i);
9132           break;
9133         case FLOAT:
9134           float_alloc(&current,i);
9135           break;
9136         case FCOMP:
9137           fcomp_alloc(&current,i);
9138           break;
9139         case SYSCALL:
9140         case HLECALL:
9141         case INTCALL:
9142           syscall_alloc(&current,i);
9143           break;
9144         case SPAN:
9145           pagespan_alloc(&current,i);
9146           break;
9147       }
9148
9149       // Drop the upper half of registers that have become 32-bit
9150       current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
9151       if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9152         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9153         if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9154         current.uu|=1;
9155       } else {
9156         current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
9157         current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9158         if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9159         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9160         current.uu|=1;
9161       }
9162
9163       // Create entry (branch target) regmap
9164       for(hr=0;hr<HOST_REGS;hr++)
9165       {
9166         int r,or,er;
9167         r=current.regmap[hr];
9168         if(r>=0) {
9169           if(r!=regmap_pre[i][hr]) {
9170             // TODO: delay slot (?)
9171             or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9172             if(or<0||(r&63)>=TEMPREG){
9173               regs[i].regmap_entry[hr]=-1;
9174             }
9175             else
9176             {
9177               // Just move it to a different register
9178               regs[i].regmap_entry[hr]=r;
9179               // If it was dirty before, it's still dirty
9180               if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r&63);
9181             }
9182           }
9183           else
9184           {
9185             // Unneeded
9186             if(r==0){
9187               regs[i].regmap_entry[hr]=0;
9188             }
9189             else
9190             if(r<64){
9191               if((current.u>>r)&1) {
9192                 regs[i].regmap_entry[hr]=-1;
9193                 //regs[i].regmap[hr]=-1;
9194                 current.regmap[hr]=-1;
9195               }else
9196                 regs[i].regmap_entry[hr]=r;
9197             }
9198             else {
9199               if((current.uu>>(r&63))&1) {
9200                 regs[i].regmap_entry[hr]=-1;
9201                 //regs[i].regmap[hr]=-1;
9202                 current.regmap[hr]=-1;
9203               }else
9204                 regs[i].regmap_entry[hr]=r;
9205             }
9206           }
9207         } else {
9208           // Branches expect CCREG to be allocated at the target
9209           if(regmap_pre[i][hr]==CCREG)
9210             regs[i].regmap_entry[hr]=CCREG;
9211           else
9212             regs[i].regmap_entry[hr]=-1;
9213         }
9214       }
9215       memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9216     }
9217     /* Branch post-alloc */
9218     if(i>0)
9219     {
9220       current.was32=current.is32;
9221       current.wasdirty=current.dirty;
9222       switch(itype[i-1]) {
9223         case UJUMP:
9224           memcpy(&branch_regs[i-1],&current,sizeof(current));
9225           branch_regs[i-1].isconst=0;
9226           branch_regs[i-1].wasconst=0;
9227           branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9228           branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9229           alloc_cc(&branch_regs[i-1],i-1);
9230           dirty_reg(&branch_regs[i-1],CCREG);
9231           if(rt1[i-1]==31) { // JAL
9232             alloc_reg(&branch_regs[i-1],i-1,31);
9233             dirty_reg(&branch_regs[i-1],31);
9234             branch_regs[i-1].is32|=1LL<<31;
9235           }
9236           memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9237           memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9238           break;
9239         case RJUMP:
9240           memcpy(&branch_regs[i-1],&current,sizeof(current));
9241           branch_regs[i-1].isconst=0;
9242           branch_regs[i-1].wasconst=0;
9243           branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9244           branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9245           alloc_cc(&branch_regs[i-1],i-1);
9246           dirty_reg(&branch_regs[i-1],CCREG);
9247           alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
9248           if(rt1[i-1]!=0) { // JALR
9249             alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9250             dirty_reg(&branch_regs[i-1],rt1[i-1]);
9251             branch_regs[i-1].is32|=1LL<<rt1[i-1];
9252           }
9253           #ifdef USE_MINI_HT
9254           if(rs1[i-1]==31) { // JALR
9255             alloc_reg(&branch_regs[i-1],i-1,RHASH);
9256             #ifndef HOST_IMM_ADDR32
9257             alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9258             #endif
9259           }
9260           #endif
9261           memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9262           memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9263           break;
9264         case CJUMP:
9265           if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9266           {
9267             alloc_cc(&current,i-1);
9268             dirty_reg(&current,CCREG);
9269             if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9270                (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9271               // The delay slot overwrote one of our conditions
9272               // Delay slot goes after the test (in order)
9273               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9274               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9275               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9276               current.u|=1;
9277               current.uu|=1;
9278               delayslot_alloc(&current,i);
9279               current.isconst=0;
9280             }
9281             else
9282             {
9283               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9284               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9285               // Alloc the branch condition registers
9286               if(rs1[i-1]) alloc_reg(&current,i-1,rs1[i-1]);
9287               if(rs2[i-1]) alloc_reg(&current,i-1,rs2[i-1]);
9288               if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9289               {
9290                 if(rs1[i-1]) alloc_reg64(&current,i-1,rs1[i-1]);
9291                 if(rs2[i-1]) alloc_reg64(&current,i-1,rs2[i-1]);
9292               }
9293             }
9294             memcpy(&branch_regs[i-1],&current,sizeof(current));
9295             branch_regs[i-1].isconst=0;
9296             branch_regs[i-1].wasconst=0;
9297             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9298             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9299           }
9300           else
9301           if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9302           {
9303             alloc_cc(&current,i-1);
9304             dirty_reg(&current,CCREG);
9305             if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9306               // The delay slot overwrote the branch condition
9307               // Delay slot goes after the test (in order)
9308               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9309               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9310               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9311               current.u|=1;
9312               current.uu|=1;
9313               delayslot_alloc(&current,i);
9314               current.isconst=0;
9315             }
9316             else
9317             {
9318               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9319               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9320               // Alloc the branch condition register
9321               alloc_reg(&current,i-1,rs1[i-1]);
9322               if(!(current.is32>>rs1[i-1]&1))
9323               {
9324                 alloc_reg64(&current,i-1,rs1[i-1]);
9325               }
9326             }
9327             memcpy(&branch_regs[i-1],&current,sizeof(current));
9328             branch_regs[i-1].isconst=0;
9329             branch_regs[i-1].wasconst=0;
9330             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9331             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9332           }
9333           else
9334           // Alloc the delay slot in case the branch is taken
9335           if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9336           {
9337             memcpy(&branch_regs[i-1],&current,sizeof(current));
9338             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9339             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9340             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9341             alloc_cc(&branch_regs[i-1],i);
9342             dirty_reg(&branch_regs[i-1],CCREG);
9343             delayslot_alloc(&branch_regs[i-1],i);
9344             branch_regs[i-1].isconst=0;
9345             alloc_reg(&current,i,CCREG); // Not taken path
9346             dirty_reg(&current,CCREG);
9347             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9348           }
9349           else
9350           if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9351           {
9352             memcpy(&branch_regs[i-1],&current,sizeof(current));
9353             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9354             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9355             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9356             alloc_cc(&branch_regs[i-1],i);
9357             dirty_reg(&branch_regs[i-1],CCREG);
9358             delayslot_alloc(&branch_regs[i-1],i);
9359             branch_regs[i-1].isconst=0;
9360             alloc_reg(&current,i,CCREG); // Not taken path
9361             dirty_reg(&current,CCREG);
9362             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9363           }
9364           break;
9365         case SJUMP:
9366           //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9367           if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9368           {
9369             alloc_cc(&current,i-1);
9370             dirty_reg(&current,CCREG);
9371             if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9372               // The delay slot overwrote the branch condition
9373               // Delay slot goes after the test (in order)
9374               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9375               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9376               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9377               current.u|=1;
9378               current.uu|=1;
9379               delayslot_alloc(&current,i);
9380               current.isconst=0;
9381             }
9382             else
9383             {
9384               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9385               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9386               // Alloc the branch condition register
9387               alloc_reg(&current,i-1,rs1[i-1]);
9388               if(!(current.is32>>rs1[i-1]&1))
9389               {
9390                 alloc_reg64(&current,i-1,rs1[i-1]);
9391               }
9392             }
9393             memcpy(&branch_regs[i-1],&current,sizeof(current));
9394             branch_regs[i-1].isconst=0;
9395             branch_regs[i-1].wasconst=0;
9396             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9397             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9398           }
9399           else
9400           // Alloc the delay slot in case the branch is taken
9401           if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9402           {
9403             memcpy(&branch_regs[i-1],&current,sizeof(current));
9404             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9405             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9406             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9407             alloc_cc(&branch_regs[i-1],i);
9408             dirty_reg(&branch_regs[i-1],CCREG);
9409             delayslot_alloc(&branch_regs[i-1],i);
9410             branch_regs[i-1].isconst=0;
9411             alloc_reg(&current,i,CCREG); // Not taken path
9412             dirty_reg(&current,CCREG);
9413             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9414           }
9415           // FIXME: BLTZAL/BGEZAL
9416           if(opcode2[i-1]&0x10) { // BxxZAL
9417             alloc_reg(&branch_regs[i-1],i-1,31);
9418             dirty_reg(&branch_regs[i-1],31);
9419             branch_regs[i-1].is32|=1LL<<31;
9420           }
9421           break;
9422         case FJUMP:
9423           if(likely[i-1]==0) // BC1F/BC1T
9424           {
9425             alloc_cc(&current,i-1);
9426             dirty_reg(&current,CCREG);
9427             if(itype[i]==FCOMP) {
9428               // The delay slot overwrote the branch condition
9429               // Delay slot goes after the test (in order)
9430               delayslot_alloc(&current,i);
9431               current.isconst=0;
9432             }
9433             else
9434             {
9435               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9436               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9437               // Alloc the branch condition register
9438               alloc_reg(&current,i-1,FSREG);
9439             }
9440             memcpy(&branch_regs[i-1],&current,sizeof(current));
9441             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9442           }
9443           else // BC1FL/BC1TL
9444           {
9445             // Alloc the delay slot in case the branch is taken
9446             memcpy(&branch_regs[i-1],&current,sizeof(current));
9447             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9448             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9449             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9450             alloc_cc(&branch_regs[i-1],i);
9451             dirty_reg(&branch_regs[i-1],CCREG);
9452             delayslot_alloc(&branch_regs[i-1],i);
9453             branch_regs[i-1].isconst=0;
9454             alloc_reg(&current,i,CCREG); // Not taken path
9455             dirty_reg(&current,CCREG);
9456             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9457           }
9458           break;
9459       }
9460
9461       if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9462       {
9463         if(rt1[i-1]==31) // JAL/JALR
9464         {
9465           // Subroutine call will return here, don't alloc any registers
9466           current.is32=1;
9467           current.dirty=0;
9468           clear_all_regs(current.regmap);
9469           alloc_reg(&current,i,CCREG);
9470           dirty_reg(&current,CCREG);
9471         }
9472         else if(i+1<slen)
9473         {
9474           // Internal branch will jump here, match registers to caller
9475           current.is32=0x3FFFFFFFFLL;
9476           current.dirty=0;
9477           clear_all_regs(current.regmap);
9478           alloc_reg(&current,i,CCREG);
9479           dirty_reg(&current,CCREG);
9480           for(j=i-1;j>=0;j--)
9481           {
9482             if(ba[j]==start+i*4+4) {
9483               memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9484               current.is32=branch_regs[j].is32;
9485               current.dirty=branch_regs[j].dirty;
9486               break;
9487             }
9488           }
9489           while(j>=0) {
9490             if(ba[j]==start+i*4+4) {
9491               for(hr=0;hr<HOST_REGS;hr++) {
9492                 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9493                   current.regmap[hr]=-1;
9494                 }
9495                 current.is32&=branch_regs[j].is32;
9496                 current.dirty&=branch_regs[j].dirty;
9497               }
9498             }
9499             j--;
9500           }
9501         }
9502       }
9503     }
9504
9505     // Count cycles in between branches
9506     ccadj[i]=cc;
9507     if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
9508     {
9509       cc=0;
9510     }
9511 #ifdef PCSX
9512     else if(/*itype[i]==LOAD||*/itype[i]==STORE||itype[i]==C1LS) // load causes weird timing issues
9513     {
9514       cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
9515     }
9516     else if(itype[i]==C2LS)
9517     {
9518       cc+=4;
9519     }
9520 #endif
9521     else
9522     {
9523       cc++;
9524     }
9525
9526     flush_dirty_uppers(&current);
9527     if(!is_ds[i]) {
9528       regs[i].is32=current.is32;
9529       regs[i].dirty=current.dirty;
9530       regs[i].isconst=current.isconst;
9531       memcpy(constmap[i],current.constmap,sizeof(current.constmap));
9532     }
9533     for(hr=0;hr<HOST_REGS;hr++) {
9534       if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
9535         if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9536           regs[i].wasconst&=~(1<<hr);
9537         }
9538       }
9539     }
9540     if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9541   }
9542
9543   /* Pass 4 - Cull unused host registers */
9544
9545   uint64_t nr=0;
9546
9547   for (i=slen-1;i>=0;i--)
9548   {
9549     int hr;
9550     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9551     {
9552       if(ba[i]<start || ba[i]>=(start+slen*4))
9553       {
9554         // Branch out of this block, don't need anything
9555         nr=0;
9556       }
9557       else
9558       {
9559         // Internal branch
9560         // Need whatever matches the target
9561         nr=0;
9562         int t=(ba[i]-start)>>2;
9563         for(hr=0;hr<HOST_REGS;hr++)
9564         {
9565           if(regs[i].regmap_entry[hr]>=0) {
9566             if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9567           }
9568         }
9569       }
9570       // Conditional branch may need registers for following instructions
9571       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9572       {
9573         if(i<slen-2) {
9574           nr|=needed_reg[i+2];
9575           for(hr=0;hr<HOST_REGS;hr++)
9576           {
9577             if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9578             //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9579           }
9580         }
9581       }
9582       // Don't need stuff which is overwritten
9583       if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9584       if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9585       // Merge in delay slot
9586       for(hr=0;hr<HOST_REGS;hr++)
9587       {
9588         if(!likely[i]) {
9589           // These are overwritten unless the branch is "likely"
9590           // and the delay slot is nullified if not taken
9591           if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9592           if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9593         }
9594         if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9595         if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9596         if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9597         if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9598         if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9599         if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9600         if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9601         if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9602         if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9603           if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9604           if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9605         }
9606         if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9607           if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9608           if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9609         }
9610         if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
9611           if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9612           if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9613         }
9614       }
9615     }
9616     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
9617     {
9618       // SYSCALL instruction (software interrupt)
9619       nr=0;
9620     }
9621     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9622     {
9623       // ERET instruction (return from interrupt)
9624       nr=0;
9625     }
9626     else // Non-branch
9627     {
9628       if(i<slen-1) {
9629         for(hr=0;hr<HOST_REGS;hr++) {
9630           if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9631           if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9632           if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9633           if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9634         }
9635       }
9636     }
9637     for(hr=0;hr<HOST_REGS;hr++)
9638     {
9639       // Overwritten registers are not needed
9640       if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9641       if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9642       if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9643       // Source registers are needed
9644       if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9645       if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9646       if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9647       if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9648       if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9649       if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9650       if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9651       if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9652       if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9653         if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9654         if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9655       }
9656       if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
9657         if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9658         if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9659       }
9660       if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
9661         if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9662         if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9663       }
9664       // Don't store a register immediately after writing it,
9665       // may prevent dual-issue.
9666       // But do so if this is a branch target, otherwise we
9667       // might have to load the register before the branch.
9668       if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
9669         if((regmap_pre[i][hr]>0&&regmap_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
9670            (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
9671           if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9672           if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9673         }
9674         if((regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
9675            (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
9676           if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9677           if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9678         }
9679       }
9680     }
9681     // Cycle count is needed at branches.  Assume it is needed at the target too.
9682     if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
9683       if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9684       if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9685     }
9686     // Save it
9687     needed_reg[i]=nr;
9688
9689     // Deallocate unneeded registers
9690     for(hr=0;hr<HOST_REGS;hr++)
9691     {
9692       if(!((nr>>hr)&1)) {
9693         if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
9694         if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9695            (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9696            (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
9697         {
9698           if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9699           {
9700             if(likely[i]) {
9701               regs[i].regmap[hr]=-1;
9702               regs[i].isconst&=~(1<<hr);
9703               if(i<slen-2) regmap_pre[i+2][hr]=-1;
9704             }
9705           }
9706         }
9707         if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9708         {
9709           int d1=0,d2=0,map=0,temp=0;
9710           if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
9711           {
9712             d1=dep1[i+1];
9713             d2=dep2[i+1];
9714           }
9715           if(using_tlb) {
9716             if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
9717                itype[i+1]==STORE || itype[i+1]==STORELR ||
9718                itype[i+1]==C1LS || itype[i+1]==C2LS)
9719             map=TLREG;
9720           } else
9721           if(itype[i+1]==STORE || itype[i+1]==STORELR ||
9722              (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
9723             map=INVCP;
9724           }
9725           if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
9726              itype[i+1]==C1LS || itype[i+1]==C2LS)
9727             temp=FTEMP;
9728           if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9729              (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9730              (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
9731              (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
9732              (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9733              regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
9734              (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
9735              regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
9736              regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
9737              regs[i].regmap[hr]!=map )
9738           {
9739             regs[i].regmap[hr]=-1;
9740             regs[i].isconst&=~(1<<hr);
9741             if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
9742                (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
9743                (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
9744                (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
9745                (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
9746                branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
9747                (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
9748                branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
9749                branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
9750                branch_regs[i].regmap[hr]!=map)
9751             {
9752               branch_regs[i].regmap[hr]=-1;
9753               branch_regs[i].regmap_entry[hr]=-1;
9754               if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9755               {
9756                 if(!likely[i]&&i<slen-2) {
9757                   regmap_pre[i+2][hr]=-1;
9758                 }
9759               }
9760             }
9761           }
9762         }
9763         else
9764         {
9765           // Non-branch
9766           if(i>0)
9767           {
9768             int d1=0,d2=0,map=-1,temp=-1;
9769             if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
9770             {
9771               d1=dep1[i];
9772               d2=dep2[i];
9773             }
9774             if(using_tlb) {
9775               if(itype[i]==LOAD || itype[i]==LOADLR ||
9776                  itype[i]==STORE || itype[i]==STORELR ||
9777                  itype[i]==C1LS || itype[i]==C2LS)
9778               map=TLREG;
9779             } else if(itype[i]==STORE || itype[i]==STORELR ||
9780                       (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
9781               map=INVCP;
9782             }
9783             if(itype[i]==LOADLR || itype[i]==STORELR ||
9784                itype[i]==C1LS || itype[i]==C2LS)
9785               temp=FTEMP;
9786             if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9787                (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
9788                (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9789                regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
9790                (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
9791                (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
9792             {
9793               if(i<slen-1&&!is_ds[i]) {
9794                 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
9795                 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
9796                 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
9797                 {
9798                   printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
9799                   assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
9800                 }
9801                 regmap_pre[i+1][hr]=-1;
9802                 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
9803               }
9804               regs[i].regmap[hr]=-1;
9805               regs[i].isconst&=~(1<<hr);
9806             }
9807           }
9808         }
9809       }
9810     }
9811   }
9812
9813   /* Pass 5 - Pre-allocate registers */
9814
9815   // If a register is allocated during a loop, try to allocate it for the
9816   // entire loop, if possible.  This avoids loading/storing registers
9817   // inside of the loop.
9818
9819   signed char f_regmap[HOST_REGS];
9820   clear_all_regs(f_regmap);
9821   for(i=0;i<slen-1;i++)
9822   {
9823     if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9824     {
9825       if(ba[i]>=start && ba[i]<(start+i*4))
9826       if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
9827       ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
9828       ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
9829       ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
9830       ||itype[i+1]==FCOMP||itype[i+1]==FCONV
9831       ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
9832       {
9833         int t=(ba[i]-start)>>2;
9834         if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
9835         if(t<2||(itype[t-2]!=UJUMP)) // call/ret assumes no registers allocated
9836         for(hr=0;hr<HOST_REGS;hr++)
9837         {
9838           if(regs[i].regmap[hr]>64) {
9839             if(!((regs[i].dirty>>hr)&1))
9840               f_regmap[hr]=regs[i].regmap[hr];
9841             else f_regmap[hr]=-1;
9842           }
9843           else if(regs[i].regmap[hr]>=0) {
9844             if(f_regmap[hr]!=regs[i].regmap[hr]) {
9845               // dealloc old register
9846               int n;
9847               for(n=0;n<HOST_REGS;n++)
9848               {
9849                 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
9850               }
9851               // and alloc new one
9852               f_regmap[hr]=regs[i].regmap[hr];
9853             }
9854           }
9855           if(branch_regs[i].regmap[hr]>64) {
9856             if(!((branch_regs[i].dirty>>hr)&1))
9857               f_regmap[hr]=branch_regs[i].regmap[hr];
9858             else f_regmap[hr]=-1;
9859           }
9860           else if(branch_regs[i].regmap[hr]>=0) {
9861             if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
9862               // dealloc old register
9863               int n;
9864               for(n=0;n<HOST_REGS;n++)
9865               {
9866                 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
9867               }
9868               // and alloc new one
9869               f_regmap[hr]=branch_regs[i].regmap[hr];
9870             }
9871           }
9872           if(ooo[i]) {
9873             if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
9874               f_regmap[hr]=branch_regs[i].regmap[hr];
9875           }else{
9876             if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
9877               f_regmap[hr]=branch_regs[i].regmap[hr];
9878           }
9879           // Avoid dirty->clean transition
9880           #ifdef DESTRUCTIVE_WRITEBACK
9881           if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
9882           #endif
9883           // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
9884           // case above, however it's always a good idea.  We can't hoist the
9885           // load if the register was already allocated, so there's no point
9886           // wasting time analyzing most of these cases.  It only "succeeds"
9887           // when the mapping was different and the load can be replaced with
9888           // a mov, which is of negligible benefit.  So such cases are
9889           // skipped below.
9890           if(f_regmap[hr]>0) {
9891             if(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0) {
9892               int r=f_regmap[hr];
9893               for(j=t;j<=i;j++)
9894               {
9895                 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9896                 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
9897                 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
9898                 if(r>63) {
9899                   // NB This can exclude the case where the upper-half
9900                   // register is lower numbered than the lower-half
9901                   // register.  Not sure if it's worth fixing...
9902                   if(get_reg(regs[j].regmap,r&63)<0) break;
9903                   if(get_reg(regs[j].regmap_entry,r&63)<0) break;
9904                   if(regs[j].is32&(1LL<<(r&63))) break;
9905                 }
9906                 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
9907                   //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9908                   int k;
9909                   if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
9910                     if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
9911                     if(r>63) {
9912                       if(get_reg(regs[i].regmap,r&63)<0) break;
9913                       if(get_reg(branch_regs[i].regmap,r&63)<0) break;
9914                     }
9915                     k=i;
9916                     while(k>1&&regs[k-1].regmap[hr]==-1) {
9917                       if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
9918                         //printf("no free regs for store %x\n",start+(k-1)*4);
9919                         break;
9920                       }
9921                       if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
9922                         //printf("no-match due to different register\n");
9923                         break;
9924                       }
9925                       if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
9926                         //printf("no-match due to branch\n");
9927                         break;
9928                       }
9929                       // call/ret fast path assumes no registers allocated
9930                       if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)) {
9931                         break;
9932                       }
9933                       if(r>63) {
9934                         // NB This can exclude the case where the upper-half
9935                         // register is lower numbered than the lower-half
9936                         // register.  Not sure if it's worth fixing...
9937                         if(get_reg(regs[k-1].regmap,r&63)<0) break;
9938                         if(regs[k-1].is32&(1LL<<(r&63))) break;
9939                       }
9940                       k--;
9941                     }
9942                     if(i<slen-1) {
9943                       if((regs[k].is32&(1LL<<f_regmap[hr]))!=
9944                         (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
9945                         //printf("bad match after branch\n");
9946                         break;
9947                       }
9948                     }
9949                     if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
9950                       //printf("Extend r%d, %x ->\n",hr,start+k*4);
9951                       while(k<i) {
9952                         regs[k].regmap_entry[hr]=f_regmap[hr];
9953                         regs[k].regmap[hr]=f_regmap[hr];
9954                         regmap_pre[k+1][hr]=f_regmap[hr];
9955                         regs[k].wasdirty&=~(1<<hr);
9956                         regs[k].dirty&=~(1<<hr);
9957                         regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
9958                         regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
9959                         regs[k].wasconst&=~(1<<hr);
9960                         regs[k].isconst&=~(1<<hr);
9961                         k++;
9962                       }
9963                     }
9964                     else {
9965                       //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
9966                       break;
9967                     }
9968                     assert(regs[i-1].regmap[hr]==f_regmap[hr]);
9969                     if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
9970                       //printf("OK fill %x (r%d)\n",start+i*4,hr);
9971                       regs[i].regmap_entry[hr]=f_regmap[hr];
9972                       regs[i].regmap[hr]=f_regmap[hr];
9973                       regs[i].wasdirty&=~(1<<hr);
9974                       regs[i].dirty&=~(1<<hr);
9975                       regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
9976                       regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
9977                       regs[i].wasconst&=~(1<<hr);
9978                       regs[i].isconst&=~(1<<hr);
9979                       branch_regs[i].regmap_entry[hr]=f_regmap[hr];
9980                       branch_regs[i].wasdirty&=~(1<<hr);
9981                       branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
9982                       branch_regs[i].regmap[hr]=f_regmap[hr];
9983                       branch_regs[i].dirty&=~(1<<hr);
9984                       branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
9985                       branch_regs[i].wasconst&=~(1<<hr);
9986                       branch_regs[i].isconst&=~(1<<hr);
9987                       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
9988                         regmap_pre[i+2][hr]=f_regmap[hr];
9989                         regs[i+2].wasdirty&=~(1<<hr);
9990                         regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
9991                         assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
9992                           (regs[i+2].was32&(1LL<<f_regmap[hr])));
9993                       }
9994                     }
9995                   }
9996                   for(k=t;k<j;k++) {
9997                     // Alloc register clean at beginning of loop,
9998                     // but may dirty it in pass 6
9999                     regs[k].regmap_entry[hr]=f_regmap[hr];
10000                     regs[k].regmap[hr]=f_regmap[hr];
10001                     regs[k].dirty&=~(1<<hr);
10002                     regs[k].wasconst&=~(1<<hr);
10003                     regs[k].isconst&=~(1<<hr);
10004                     if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) {
10005                       branch_regs[k].regmap_entry[hr]=f_regmap[hr];
10006                       branch_regs[k].regmap[hr]=f_regmap[hr];
10007                       branch_regs[k].dirty&=~(1<<hr);
10008                       branch_regs[k].wasconst&=~(1<<hr);
10009                       branch_regs[k].isconst&=~(1<<hr);
10010                       if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
10011                         regmap_pre[k+2][hr]=f_regmap[hr];
10012                         regs[k+2].wasdirty&=~(1<<hr);
10013                         assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))==
10014                           (regs[k+2].was32&(1LL<<f_regmap[hr])));
10015                       }
10016                     }
10017                     else
10018                     {
10019                       regmap_pre[k+1][hr]=f_regmap[hr];
10020                       regs[k+1].wasdirty&=~(1<<hr);
10021                     }
10022                   }
10023                   if(regs[j].regmap[hr]==f_regmap[hr])
10024                     regs[j].regmap_entry[hr]=f_regmap[hr];
10025                   break;
10026                 }
10027                 if(j==i) break;
10028                 if(regs[j].regmap[hr]>=0)
10029                   break;
10030                 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
10031                   //printf("no-match due to different register\n");
10032                   break;
10033                 }
10034                 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
10035                   //printf("32/64 mismatch %x %d\n",start+j*4,hr);
10036                   break;
10037                 }
10038                 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10039                 {
10040                   // Stop on unconditional branch
10041                   break;
10042                 }
10043                 if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
10044                 {
10045                   if(ooo[j]) {
10046                     if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
10047                       break;
10048                   }else{
10049                     if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
10050                       break;
10051                   }
10052                   if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
10053                     //printf("no-match due to different register (branch)\n");
10054                     break;
10055                   }
10056                 }
10057                 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10058                   //printf("No free regs for store %x\n",start+j*4);
10059                   break;
10060                 }
10061                 if(f_regmap[hr]>=64) {
10062                   if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
10063                     break;
10064                   }
10065                   else
10066                   {
10067                     if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
10068                       break;
10069                     }
10070                   }
10071                 }
10072               }
10073             }
10074           }
10075         }
10076       }
10077     }else{
10078       int count=0;
10079       for(hr=0;hr<HOST_REGS;hr++)
10080       {
10081         if(hr!=EXCLUDE_REG) {
10082           if(regs[i].regmap[hr]>64) {
10083             if(!((regs[i].dirty>>hr)&1))
10084               f_regmap[hr]=regs[i].regmap[hr];
10085           }
10086           else if(regs[i].regmap[hr]>=0) {
10087             if(f_regmap[hr]!=regs[i].regmap[hr]) {
10088               // dealloc old register
10089               int n;
10090               for(n=0;n<HOST_REGS;n++)
10091               {
10092                 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10093               }
10094               // and alloc new one
10095               f_regmap[hr]=regs[i].regmap[hr];
10096             }
10097           }
10098           else if(regs[i].regmap[hr]<0) count++;
10099         }
10100       }
10101       // Try to restore cycle count at branch targets
10102       if(bt[i]) {
10103         for(j=i;j<slen-1;j++) {
10104           if(regs[j].regmap[HOST_CCREG]!=-1) break;
10105           if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10106             //printf("no free regs for store %x\n",start+j*4);
10107             break;
10108           }
10109         }
10110         if(regs[j].regmap[HOST_CCREG]==CCREG) {
10111           int k=i;
10112           //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
10113           while(k<j) {
10114             regs[k].regmap_entry[HOST_CCREG]=CCREG;
10115             regs[k].regmap[HOST_CCREG]=CCREG;
10116             regmap_pre[k+1][HOST_CCREG]=CCREG;
10117             regs[k+1].wasdirty|=1<<HOST_CCREG;
10118             regs[k].dirty|=1<<HOST_CCREG;
10119             regs[k].wasconst&=~(1<<HOST_CCREG);
10120             regs[k].isconst&=~(1<<HOST_CCREG);
10121             k++;
10122           }
10123           regs[j].regmap_entry[HOST_CCREG]=CCREG;
10124         }
10125         // Work backwards from the branch target
10126         if(j>i&&f_regmap[HOST_CCREG]==CCREG)
10127         {
10128           //printf("Extend backwards\n");
10129           int k;
10130           k=i;
10131           while(regs[k-1].regmap[HOST_CCREG]==-1) {
10132             if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10133               //printf("no free regs for store %x\n",start+(k-1)*4);
10134               break;
10135             }
10136             k--;
10137           }
10138           if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
10139             //printf("Extend CC, %x ->\n",start+k*4);
10140             while(k<=i) {
10141               regs[k].regmap_entry[HOST_CCREG]=CCREG;
10142               regs[k].regmap[HOST_CCREG]=CCREG;
10143               regmap_pre[k+1][HOST_CCREG]=CCREG;
10144               regs[k+1].wasdirty|=1<<HOST_CCREG;
10145               regs[k].dirty|=1<<HOST_CCREG;
10146               regs[k].wasconst&=~(1<<HOST_CCREG);
10147               regs[k].isconst&=~(1<<HOST_CCREG);
10148               k++;
10149             }
10150           }
10151           else {
10152             //printf("Fail Extend CC, %x ->\n",start+k*4);
10153           }
10154         }
10155       }
10156       if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
10157          itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
10158          itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
10159          itype[i]!=FCONV&&itype[i]!=FCOMP)
10160       {
10161         memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
10162       }
10163     }
10164   }
10165
10166   // This allocates registers (if possible) one instruction prior
10167   // to use, which can avoid a load-use penalty on certain CPUs.
10168   for(i=0;i<slen-1;i++)
10169   {
10170     if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10171     {
10172       if(!bt[i+1])
10173       {
10174         if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
10175            ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
10176         {
10177           if(rs1[i+1]) {
10178             if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10179             {
10180               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10181               {
10182                 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10183                 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10184                 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10185                 regs[i].isconst&=~(1<<hr);
10186                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10187                 constmap[i][hr]=constmap[i+1][hr];
10188                 regs[i+1].wasdirty&=~(1<<hr);
10189                 regs[i].dirty&=~(1<<hr);
10190               }
10191             }
10192           }
10193           if(rs2[i+1]) {
10194             if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10195             {
10196               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10197               {
10198                 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10199                 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10200                 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10201                 regs[i].isconst&=~(1<<hr);
10202                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10203                 constmap[i][hr]=constmap[i+1][hr];
10204                 regs[i+1].wasdirty&=~(1<<hr);
10205                 regs[i].dirty&=~(1<<hr);
10206               }
10207             }
10208           }
10209           if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10210             if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10211             {
10212               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10213               {
10214                 regs[i].regmap[hr]=rs1[i+1];
10215                 regmap_pre[i+1][hr]=rs1[i+1];
10216                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10217                 regs[i].isconst&=~(1<<hr);
10218                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10219                 constmap[i][hr]=constmap[i+1][hr];
10220                 regs[i+1].wasdirty&=~(1<<hr);
10221                 regs[i].dirty&=~(1<<hr);
10222               }
10223             }
10224           }
10225           if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10226             if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10227             {
10228               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10229               {
10230                 regs[i].regmap[hr]=rs1[i+1];
10231                 regmap_pre[i+1][hr]=rs1[i+1];
10232                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10233                 regs[i].isconst&=~(1<<hr);
10234                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10235                 constmap[i][hr]=constmap[i+1][hr];
10236                 regs[i+1].wasdirty&=~(1<<hr);
10237                 regs[i].dirty&=~(1<<hr);
10238               }
10239             }
10240           }
10241           #ifndef HOST_IMM_ADDR32
10242           if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
10243             hr=get_reg(regs[i+1].regmap,TLREG);
10244             if(hr>=0) {
10245               int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10246               if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10247                 int nr;
10248                 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10249                 {
10250                   regs[i].regmap[hr]=MGEN1+((i+1)&1);
10251                   regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10252                   regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10253                   regs[i].isconst&=~(1<<hr);
10254                   regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10255                   constmap[i][hr]=constmap[i+1][hr];
10256                   regs[i+1].wasdirty&=~(1<<hr);
10257                   regs[i].dirty&=~(1<<hr);
10258                 }
10259                 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10260                 {
10261                   // move it to another register
10262                   regs[i+1].regmap[hr]=-1;
10263                   regmap_pre[i+2][hr]=-1;
10264                   regs[i+1].regmap[nr]=TLREG;
10265                   regmap_pre[i+2][nr]=TLREG;
10266                   regs[i].regmap[nr]=MGEN1+((i+1)&1);
10267                   regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10268                   regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10269                   regs[i].isconst&=~(1<<nr);
10270                   regs[i+1].isconst&=~(1<<nr);
10271                   regs[i].dirty&=~(1<<nr);
10272                   regs[i+1].wasdirty&=~(1<<nr);
10273                   regs[i+1].dirty&=~(1<<nr);
10274                   regs[i+2].wasdirty&=~(1<<nr);
10275                 }
10276               }
10277             }
10278           }
10279           #endif
10280           if(itype[i+1]==STORE||itype[i+1]==STORELR
10281              ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
10282             if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10283               hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10284               if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10285               else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10286               assert(hr>=0);
10287               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10288               {
10289                 regs[i].regmap[hr]=rs1[i+1];
10290                 regmap_pre[i+1][hr]=rs1[i+1];
10291                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10292                 regs[i].isconst&=~(1<<hr);
10293                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10294                 constmap[i][hr]=constmap[i+1][hr];
10295                 regs[i+1].wasdirty&=~(1<<hr);
10296                 regs[i].dirty&=~(1<<hr);
10297               }
10298             }
10299           }
10300           if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
10301             if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10302               int nr;
10303               hr=get_reg(regs[i+1].regmap,FTEMP);
10304               assert(hr>=0);
10305               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10306               {
10307                 regs[i].regmap[hr]=rs1[i+1];
10308                 regmap_pre[i+1][hr]=rs1[i+1];
10309                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10310                 regs[i].isconst&=~(1<<hr);
10311                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10312                 constmap[i][hr]=constmap[i+1][hr];
10313                 regs[i+1].wasdirty&=~(1<<hr);
10314                 regs[i].dirty&=~(1<<hr);
10315               }
10316               else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10317               {
10318                 // move it to another register
10319                 regs[i+1].regmap[hr]=-1;
10320                 regmap_pre[i+2][hr]=-1;
10321                 regs[i+1].regmap[nr]=FTEMP;
10322                 regmap_pre[i+2][nr]=FTEMP;
10323                 regs[i].regmap[nr]=rs1[i+1];
10324                 regmap_pre[i+1][nr]=rs1[i+1];
10325                 regs[i+1].regmap_entry[nr]=rs1[i+1];
10326                 regs[i].isconst&=~(1<<nr);
10327                 regs[i+1].isconst&=~(1<<nr);
10328                 regs[i].dirty&=~(1<<nr);
10329                 regs[i+1].wasdirty&=~(1<<nr);
10330                 regs[i+1].dirty&=~(1<<nr);
10331                 regs[i+2].wasdirty&=~(1<<nr);
10332               }
10333             }
10334           }
10335           if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
10336             if(itype[i+1]==LOAD)
10337               hr=get_reg(regs[i+1].regmap,rt1[i+1]);
10338             if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
10339               hr=get_reg(regs[i+1].regmap,FTEMP);
10340             if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
10341               hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10342               if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10343             }
10344             if(hr>=0&&regs[i].regmap[hr]<0) {
10345               int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10346               if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10347                 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10348                 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10349                 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10350                 regs[i].isconst&=~(1<<hr);
10351                 regs[i+1].wasdirty&=~(1<<hr);
10352                 regs[i].dirty&=~(1<<hr);
10353               }
10354             }
10355           }
10356         }
10357       }
10358     }
10359   }
10360
10361   /* Pass 6 - Optimize clean/dirty state */
10362   clean_registers(0,slen-1,1);
10363
10364   /* Pass 7 - Identify 32-bit registers */
10365 #ifndef FORCE32
10366   provisional_r32();
10367
10368   u_int r32=0;
10369
10370   for (i=slen-1;i>=0;i--)
10371   {
10372     int hr;
10373     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10374     {
10375       if(ba[i]<start || ba[i]>=(start+slen*4))
10376       {
10377         // Branch out of this block, don't need anything
10378         r32=0;
10379       }
10380       else
10381       {
10382         // Internal branch
10383         // Need whatever matches the target
10384         // (and doesn't get overwritten by the delay slot instruction)
10385         r32=0;
10386         int t=(ba[i]-start)>>2;
10387         if(ba[i]>start+i*4) {
10388           // Forward branch
10389           if(!(requires_32bit[t]&~regs[i].was32))
10390             r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10391         }else{
10392           // Backward branch
10393           //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10394           //  r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10395           if(!(pr32[t]&~regs[i].was32))
10396             r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10397         }
10398       }
10399       // Conditional branch may need registers for following instructions
10400       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10401       {
10402         if(i<slen-2) {
10403           r32|=requires_32bit[i+2];
10404           r32&=regs[i].was32;
10405           // Mark this address as a branch target since it may be called
10406           // upon return from interrupt
10407           bt[i+2]=1;
10408         }
10409       }
10410       // Merge in delay slot
10411       if(!likely[i]) {
10412         // These are overwritten unless the branch is "likely"
10413         // and the delay slot is nullified if not taken
10414         r32&=~(1LL<<rt1[i+1]);
10415         r32&=~(1LL<<rt2[i+1]);
10416       }
10417       // Assume these are needed (delay slot)
10418       if(us1[i+1]>0)
10419       {
10420         if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10421       }
10422       if(us2[i+1]>0)
10423       {
10424         if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10425       }
10426       if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10427       {
10428         if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10429       }
10430       if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10431       {
10432         if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10433       }
10434     }
10435     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
10436     {
10437       // SYSCALL instruction (software interrupt)
10438       r32=0;
10439     }
10440     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10441     {
10442       // ERET instruction (return from interrupt)
10443       r32=0;
10444     }
10445     // Check 32 bits
10446     r32&=~(1LL<<rt1[i]);
10447     r32&=~(1LL<<rt2[i]);
10448     if(us1[i]>0)
10449     {
10450       if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10451     }
10452     if(us2[i]>0)
10453     {
10454       if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10455     }
10456     if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
10457     {
10458       if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
10459     }
10460     if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
10461     {
10462       if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
10463     }
10464     requires_32bit[i]=r32;
10465
10466     // Dirty registers which are 32-bit, require 32-bit input
10467     // as they will be written as 32-bit values
10468     for(hr=0;hr<HOST_REGS;hr++)
10469     {
10470       if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
10471         if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
10472           if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
10473           requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
10474         }
10475       }
10476     }
10477     //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
10478   }
10479 #endif
10480
10481   if(itype[slen-1]==SPAN) {
10482     bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
10483   }
10484
10485   /* Debug/disassembly */
10486   if((void*)assem_debug==(void*)printf)
10487   for(i=0;i<slen;i++)
10488   {
10489     printf("U:");
10490     int r;
10491     for(r=1;r<=CCREG;r++) {
10492       if((unneeded_reg[i]>>r)&1) {
10493         if(r==HIREG) printf(" HI");
10494         else if(r==LOREG) printf(" LO");
10495         else printf(" r%d",r);
10496       }
10497     }
10498 #ifndef FORCE32
10499     printf(" UU:");
10500     for(r=1;r<=CCREG;r++) {
10501       if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
10502         if(r==HIREG) printf(" HI");
10503         else if(r==LOREG) printf(" LO");
10504         else printf(" r%d",r);
10505       }
10506     }
10507     printf(" 32:");
10508     for(r=0;r<=CCREG;r++) {
10509       //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10510       if((regs[i].was32>>r)&1) {
10511         if(r==CCREG) printf(" CC");
10512         else if(r==HIREG) printf(" HI");
10513         else if(r==LOREG) printf(" LO");
10514         else printf(" r%d",r);
10515       }
10516     }
10517 #endif
10518     printf("\n");
10519     #if defined(__i386__) || defined(__x86_64__)
10520     printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
10521     #endif
10522     #ifdef __arm__
10523     printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
10524     #endif
10525     printf("needs: ");
10526     if(needed_reg[i]&1) printf("eax ");
10527     if((needed_reg[i]>>1)&1) printf("ecx ");
10528     if((needed_reg[i]>>2)&1) printf("edx ");
10529     if((needed_reg[i]>>3)&1) printf("ebx ");
10530     if((needed_reg[i]>>5)&1) printf("ebp ");
10531     if((needed_reg[i]>>6)&1) printf("esi ");
10532     if((needed_reg[i]>>7)&1) printf("edi ");
10533     printf("r:");
10534     for(r=0;r<=CCREG;r++) {
10535       //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10536       if((requires_32bit[i]>>r)&1) {
10537         if(r==CCREG) printf(" CC");
10538         else if(r==HIREG) printf(" HI");
10539         else if(r==LOREG) printf(" LO");
10540         else printf(" r%d",r);
10541       }
10542     }
10543     printf("\n");
10544     /*printf("pr:");
10545     for(r=0;r<=CCREG;r++) {
10546       //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10547       if((pr32[i]>>r)&1) {
10548         if(r==CCREG) printf(" CC");
10549         else if(r==HIREG) printf(" HI");
10550         else if(r==LOREG) printf(" LO");
10551         else printf(" r%d",r);
10552       }
10553     }
10554     if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
10555     printf("\n");*/
10556     #if defined(__i386__) || defined(__x86_64__)
10557     printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
10558     printf("dirty: ");
10559     if(regs[i].wasdirty&1) printf("eax ");
10560     if((regs[i].wasdirty>>1)&1) printf("ecx ");
10561     if((regs[i].wasdirty>>2)&1) printf("edx ");
10562     if((regs[i].wasdirty>>3)&1) printf("ebx ");
10563     if((regs[i].wasdirty>>5)&1) printf("ebp ");
10564     if((regs[i].wasdirty>>6)&1) printf("esi ");
10565     if((regs[i].wasdirty>>7)&1) printf("edi ");
10566     #endif
10567     #ifdef __arm__
10568     printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
10569     printf("dirty: ");
10570     if(regs[i].wasdirty&1) printf("r0 ");
10571     if((regs[i].wasdirty>>1)&1) printf("r1 ");
10572     if((regs[i].wasdirty>>2)&1) printf("r2 ");
10573     if((regs[i].wasdirty>>3)&1) printf("r3 ");
10574     if((regs[i].wasdirty>>4)&1) printf("r4 ");
10575     if((regs[i].wasdirty>>5)&1) printf("r5 ");
10576     if((regs[i].wasdirty>>6)&1) printf("r6 ");
10577     if((regs[i].wasdirty>>7)&1) printf("r7 ");
10578     if((regs[i].wasdirty>>8)&1) printf("r8 ");
10579     if((regs[i].wasdirty>>9)&1) printf("r9 ");
10580     if((regs[i].wasdirty>>10)&1) printf("r10 ");
10581     if((regs[i].wasdirty>>12)&1) printf("r12 ");
10582     #endif
10583     printf("\n");
10584     disassemble_inst(i);
10585     //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
10586     #if defined(__i386__) || defined(__x86_64__)
10587     printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
10588     if(regs[i].dirty&1) printf("eax ");
10589     if((regs[i].dirty>>1)&1) printf("ecx ");
10590     if((regs[i].dirty>>2)&1) printf("edx ");
10591     if((regs[i].dirty>>3)&1) printf("ebx ");
10592     if((regs[i].dirty>>5)&1) printf("ebp ");
10593     if((regs[i].dirty>>6)&1) printf("esi ");
10594     if((regs[i].dirty>>7)&1) printf("edi ");
10595     #endif
10596     #ifdef __arm__
10597     printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
10598     if(regs[i].dirty&1) printf("r0 ");
10599     if((regs[i].dirty>>1)&1) printf("r1 ");
10600     if((regs[i].dirty>>2)&1) printf("r2 ");
10601     if((regs[i].dirty>>3)&1) printf("r3 ");
10602     if((regs[i].dirty>>4)&1) printf("r4 ");
10603     if((regs[i].dirty>>5)&1) printf("r5 ");
10604     if((regs[i].dirty>>6)&1) printf("r6 ");
10605     if((regs[i].dirty>>7)&1) printf("r7 ");
10606     if((regs[i].dirty>>8)&1) printf("r8 ");
10607     if((regs[i].dirty>>9)&1) printf("r9 ");
10608     if((regs[i].dirty>>10)&1) printf("r10 ");
10609     if((regs[i].dirty>>12)&1) printf("r12 ");
10610     #endif
10611     printf("\n");
10612     if(regs[i].isconst) {
10613       printf("constants: ");
10614       #if defined(__i386__) || defined(__x86_64__)
10615       if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
10616       if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
10617       if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
10618       if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
10619       if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
10620       if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
10621       if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
10622       #endif
10623       #ifdef __arm__
10624       if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
10625       if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
10626       if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
10627       if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
10628       if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
10629       if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
10630       if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
10631       if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
10632       if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
10633       if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
10634       if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
10635       if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
10636       #endif
10637       printf("\n");
10638     }
10639 #ifndef FORCE32
10640     printf(" 32:");
10641     for(r=0;r<=CCREG;r++) {
10642       if((regs[i].is32>>r)&1) {
10643         if(r==CCREG) printf(" CC");
10644         else if(r==HIREG) printf(" HI");
10645         else if(r==LOREG) printf(" LO");
10646         else printf(" r%d",r);
10647       }
10648     }
10649     printf("\n");
10650 #endif
10651     /*printf(" p32:");
10652     for(r=0;r<=CCREG;r++) {
10653       if((p32[i]>>r)&1) {
10654         if(r==CCREG) printf(" CC");
10655         else if(r==HIREG) printf(" HI");
10656         else if(r==LOREG) printf(" LO");
10657         else printf(" r%d",r);
10658       }
10659     }
10660     if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
10661     else printf("\n");*/
10662     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10663       #if defined(__i386__) || defined(__x86_64__)
10664       printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
10665       if(branch_regs[i].dirty&1) printf("eax ");
10666       if((branch_regs[i].dirty>>1)&1) printf("ecx ");
10667       if((branch_regs[i].dirty>>2)&1) printf("edx ");
10668       if((branch_regs[i].dirty>>3)&1) printf("ebx ");
10669       if((branch_regs[i].dirty>>5)&1) printf("ebp ");
10670       if((branch_regs[i].dirty>>6)&1) printf("esi ");
10671       if((branch_regs[i].dirty>>7)&1) printf("edi ");
10672       #endif
10673       #ifdef __arm__
10674       printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
10675       if(branch_regs[i].dirty&1) printf("r0 ");
10676       if((branch_regs[i].dirty>>1)&1) printf("r1 ");
10677       if((branch_regs[i].dirty>>2)&1) printf("r2 ");
10678       if((branch_regs[i].dirty>>3)&1) printf("r3 ");
10679       if((branch_regs[i].dirty>>4)&1) printf("r4 ");
10680       if((branch_regs[i].dirty>>5)&1) printf("r5 ");
10681       if((branch_regs[i].dirty>>6)&1) printf("r6 ");
10682       if((branch_regs[i].dirty>>7)&1) printf("r7 ");
10683       if((branch_regs[i].dirty>>8)&1) printf("r8 ");
10684       if((branch_regs[i].dirty>>9)&1) printf("r9 ");
10685       if((branch_regs[i].dirty>>10)&1) printf("r10 ");
10686       if((branch_regs[i].dirty>>12)&1) printf("r12 ");
10687       #endif
10688 #ifndef FORCE32
10689       printf(" 32:");
10690       for(r=0;r<=CCREG;r++) {
10691         if((branch_regs[i].is32>>r)&1) {
10692           if(r==CCREG) printf(" CC");
10693           else if(r==HIREG) printf(" HI");
10694           else if(r==LOREG) printf(" LO");
10695           else printf(" r%d",r);
10696         }
10697       }
10698       printf("\n");
10699 #endif
10700     }
10701   }
10702
10703   /* Pass 8 - Assembly */
10704   linkcount=0;stubcount=0;
10705   ds=0;is_delayslot=0;
10706   cop1_usable=0;
10707   uint64_t is32_pre=0;
10708   u_int dirty_pre=0;
10709   u_int beginning=(u_int)out;
10710   if((u_int)addr&1) {
10711     ds=1;
10712     pagespan_ds();
10713   }
10714   u_int instr_addr0_override=0;
10715
10716 #ifdef PCSX
10717   if (start == 0x80030000) {
10718     // nasty hack for fastbios thing
10719     instr_addr0_override=(u_int)out;
10720     emit_movimm(start,0);
10721     emit_readword((int)&pcaddr,1);
10722     emit_writeword(0,(int)&pcaddr);
10723     emit_cmp(0,1);
10724     emit_jne((int)new_dyna_leave);
10725   }
10726 #endif
10727   for(i=0;i<slen;i++)
10728   {
10729     //if(ds) printf("ds: ");
10730     if((void*)assem_debug==(void*)printf) disassemble_inst(i);
10731     if(ds) {
10732       ds=0; // Skip delay slot
10733       if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
10734       instr_addr[i]=0;
10735     } else {
10736       #ifndef DESTRUCTIVE_WRITEBACK
10737       if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10738       {
10739         wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
10740               unneeded_reg[i],unneeded_reg_upper[i]);
10741         wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
10742               unneeded_reg[i],unneeded_reg_upper[i]);
10743       }
10744       is32_pre=regs[i].is32;
10745       dirty_pre=regs[i].dirty;
10746       #endif
10747       // write back
10748       if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10749       {
10750         wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
10751                       unneeded_reg[i],unneeded_reg_upper[i]);
10752         loop_preload(regmap_pre[i],regs[i].regmap_entry);
10753       }
10754       // branch target entry point
10755       instr_addr[i]=(u_int)out;
10756       assem_debug("<->\n");
10757       // load regs
10758       if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
10759         wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
10760       load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
10761       address_generation(i,&regs[i],regs[i].regmap_entry);
10762       load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
10763       if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10764       {
10765         // Load the delay slot registers if necessary
10766         if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i]&&(rs1[i+1]!=rt1[i]||rt1[i]==0))
10767           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10768         if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i]&&(rs2[i+1]!=rt1[i]||rt1[i]==0))
10769           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
10770         if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
10771           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10772       }
10773       else if(i+1<slen)
10774       {
10775         // Preload registers for following instruction
10776         if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10777           if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
10778             load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10779         if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10780           if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
10781             load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
10782       }
10783       // TODO: if(is_ooo(i)) address_generation(i+1);
10784       if(itype[i]==CJUMP||itype[i]==FJUMP)
10785         load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
10786       if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
10787         load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10788       if(bt[i]) cop1_usable=0;
10789       // assemble
10790       switch(itype[i]) {
10791         case ALU:
10792           alu_assemble(i,&regs[i]);break;
10793         case IMM16:
10794           imm16_assemble(i,&regs[i]);break;
10795         case SHIFT:
10796           shift_assemble(i,&regs[i]);break;
10797         case SHIFTIMM:
10798           shiftimm_assemble(i,&regs[i]);break;
10799         case LOAD:
10800           load_assemble(i,&regs[i]);break;
10801         case LOADLR:
10802           loadlr_assemble(i,&regs[i]);break;
10803         case STORE:
10804           store_assemble(i,&regs[i]);break;
10805         case STORELR:
10806           storelr_assemble(i,&regs[i]);break;
10807         case COP0:
10808           cop0_assemble(i,&regs[i]);break;
10809         case COP1:
10810           cop1_assemble(i,&regs[i]);break;
10811         case C1LS:
10812           c1ls_assemble(i,&regs[i]);break;
10813         case COP2:
10814           cop2_assemble(i,&regs[i]);break;
10815         case C2LS:
10816           c2ls_assemble(i,&regs[i]);break;
10817         case C2OP:
10818           c2op_assemble(i,&regs[i]);break;
10819         case FCONV:
10820           fconv_assemble(i,&regs[i]);break;
10821         case FLOAT:
10822           float_assemble(i,&regs[i]);break;
10823         case FCOMP:
10824           fcomp_assemble(i,&regs[i]);break;
10825         case MULTDIV:
10826           multdiv_assemble(i,&regs[i]);break;
10827         case MOV:
10828           mov_assemble(i,&regs[i]);break;
10829         case SYSCALL:
10830           syscall_assemble(i,&regs[i]);break;
10831         case HLECALL:
10832           hlecall_assemble(i,&regs[i]);break;
10833         case INTCALL:
10834           intcall_assemble(i,&regs[i]);break;
10835         case UJUMP:
10836           ujump_assemble(i,&regs[i]);ds=1;break;
10837         case RJUMP:
10838           rjump_assemble(i,&regs[i]);ds=1;break;
10839         case CJUMP:
10840           cjump_assemble(i,&regs[i]);ds=1;break;
10841         case SJUMP:
10842           sjump_assemble(i,&regs[i]);ds=1;break;
10843         case FJUMP:
10844           fjump_assemble(i,&regs[i]);ds=1;break;
10845         case SPAN:
10846           pagespan_assemble(i,&regs[i]);break;
10847       }
10848       if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10849         literal_pool(1024);
10850       else
10851         literal_pool_jumpover(256);
10852     }
10853   }
10854   //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
10855   // If the block did not end with an unconditional branch,
10856   // add a jump to the next instruction.
10857   if(i>1) {
10858     if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
10859       assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10860       assert(i==slen);
10861       if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
10862         store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10863         if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10864           emit_loadreg(CCREG,HOST_CCREG);
10865         emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10866       }
10867       else if(!likely[i-2])
10868       {
10869         store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
10870         assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
10871       }
10872       else
10873       {
10874         store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
10875         assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
10876       }
10877       add_to_linker((int)out,start+i*4,0);
10878       emit_jmp(0);
10879     }
10880   }
10881   else
10882   {
10883     assert(i>0);
10884     assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10885     store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10886     if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10887       emit_loadreg(CCREG,HOST_CCREG);
10888     emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10889     add_to_linker((int)out,start+i*4,0);
10890     emit_jmp(0);
10891   }
10892
10893   // TODO: delay slot stubs?
10894   // Stubs
10895   for(i=0;i<stubcount;i++)
10896   {
10897     switch(stubs[i][0])
10898     {
10899       case LOADB_STUB:
10900       case LOADH_STUB:
10901       case LOADW_STUB:
10902       case LOADD_STUB:
10903       case LOADBU_STUB:
10904       case LOADHU_STUB:
10905         do_readstub(i);break;
10906       case STOREB_STUB:
10907       case STOREH_STUB:
10908       case STOREW_STUB:
10909       case STORED_STUB:
10910         do_writestub(i);break;
10911       case CC_STUB:
10912         do_ccstub(i);break;
10913       case INVCODE_STUB:
10914         do_invstub(i);break;
10915       case FP_STUB:
10916         do_cop1stub(i);break;
10917       case STORELR_STUB:
10918         do_unalignedwritestub(i);break;
10919     }
10920   }
10921
10922   if (instr_addr0_override)
10923     instr_addr[0] = instr_addr0_override;
10924
10925   /* Pass 9 - Linker */
10926   for(i=0;i<linkcount;i++)
10927   {
10928     assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
10929     literal_pool(64);
10930     if(!link_addr[i][2])
10931     {
10932       void *stub=out;
10933       void *addr=check_addr(link_addr[i][1]);
10934       emit_extjump(link_addr[i][0],link_addr[i][1]);
10935       if(addr) {
10936         set_jump_target(link_addr[i][0],(int)addr);
10937         add_link(link_addr[i][1],stub);
10938       }
10939       else set_jump_target(link_addr[i][0],(int)stub);
10940     }
10941     else
10942     {
10943       // Internal branch
10944       int target=(link_addr[i][1]-start)>>2;
10945       assert(target>=0&&target<slen);
10946       assert(instr_addr[target]);
10947       //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10948       //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
10949       //#else
10950       set_jump_target(link_addr[i][0],instr_addr[target]);
10951       //#endif
10952     }
10953   }
10954   // External Branch Targets (jump_in)
10955   if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
10956   for(i=0;i<slen;i++)
10957   {
10958     if(bt[i]||i==0)
10959     {
10960       if(instr_addr[i]) // TODO - delay slots (=null)
10961       {
10962         u_int vaddr=start+i*4;
10963         u_int page=get_page(vaddr);
10964         u_int vpage=get_vpage(vaddr);
10965         literal_pool(256);
10966         //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
10967 #ifndef FORCE32
10968         if(!requires_32bit[i])
10969 #else
10970         if(1)
10971 #endif
10972         {
10973           assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
10974           assem_debug("jump_in: %x\n",start+i*4);
10975           ll_add(jump_dirty+vpage,vaddr,(void *)out);
10976           int entry_point=do_dirty_stub(i);
10977           ll_add(jump_in+page,vaddr,(void *)entry_point);
10978           // If there was an existing entry in the hash table,
10979           // replace it with the new address.
10980           // Don't add new entries.  We'll insert the
10981           // ones that actually get used in check_addr().
10982           int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
10983           if(ht_bin[0]==vaddr) {
10984             ht_bin[1]=entry_point;
10985           }
10986           if(ht_bin[2]==vaddr) {
10987             ht_bin[3]=entry_point;
10988           }
10989         }
10990         else
10991         {
10992           u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
10993           assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
10994           assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
10995           //int entry_point=(int)out;
10996           ////assem_debug("entry_point: %x\n",entry_point);
10997           //load_regs_entry(i);
10998           //if(entry_point==(int)out)
10999           //  entry_point=instr_addr[i];
11000           //else
11001           //  emit_jmp(instr_addr[i]);
11002           //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11003           ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
11004           int entry_point=do_dirty_stub(i);
11005           ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11006         }
11007       }
11008     }
11009   }
11010   // Write out the literal pool if necessary
11011   literal_pool(0);
11012   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11013   // Align code
11014   if(((u_int)out)&7) emit_addnop(13);
11015   #endif
11016   assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
11017   //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
11018   memcpy(copy,source,slen*4);
11019   copy+=slen*4;
11020
11021   #ifdef __arm__
11022   __clear_cache((void *)beginning,out);
11023   #endif
11024
11025   // If we're within 256K of the end of the buffer,
11026   // start over from the beginning. (Is 256K enough?)
11027   if((int)out>BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
11028
11029   // Trap writes to any of the pages we compiled
11030   for(i=start>>12;i<=(start+slen*4)>>12;i++) {
11031     invalid_code[i]=0;
11032 #ifndef DISABLE_TLB
11033     memory_map[i]|=0x40000000;
11034     if((signed int)start>=(signed int)0xC0000000) {
11035       assert(using_tlb);
11036       j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
11037       invalid_code[j]=0;
11038       memory_map[j]|=0x40000000;
11039       //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
11040     }
11041 #endif
11042   }
11043 #ifdef PCSX
11044   // PCSX maps all RAM mirror invalid_code tests to 0x80000000..0x80000000+RAM_SIZE
11045   if(get_page(start)<(RAM_SIZE>>12))
11046     for(i=start>>12;i<=(start+slen*4)>>12;i++)
11047       invalid_code[((u_int)0x80000000>>12)|i]=0;
11048 #endif
11049
11050   /* Pass 10 - Free memory by expiring oldest blocks */
11051
11052   int end=((((int)out-BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
11053   while(expirep!=end)
11054   {
11055     int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
11056     int base=BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
11057     inv_debug("EXP: Phase %d\n",expirep);
11058     switch((expirep>>11)&3)
11059     {
11060       case 0:
11061         // Clear jump_in and jump_dirty
11062         ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
11063         ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
11064         ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
11065         ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
11066         break;
11067       case 1:
11068         // Clear pointers
11069         ll_kill_pointers(jump_out[expirep&2047],base,shift);
11070         ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
11071         break;
11072       case 2:
11073         // Clear hash table
11074         for(i=0;i<32;i++) {
11075           int *ht_bin=hash_table[((expirep&2047)<<5)+i];
11076           if((ht_bin[3]>>shift)==(base>>shift) ||
11077              ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11078             inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
11079             ht_bin[2]=ht_bin[3]=-1;
11080           }
11081           if((ht_bin[1]>>shift)==(base>>shift) ||
11082              ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11083             inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
11084             ht_bin[0]=ht_bin[2];
11085             ht_bin[1]=ht_bin[3];
11086             ht_bin[2]=ht_bin[3]=-1;
11087           }
11088         }
11089         break;
11090       case 3:
11091         // Clear jump_out
11092         #ifdef __arm__
11093         if((expirep&2047)==0)
11094           do_clear_cache();
11095         #endif
11096         ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
11097         ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
11098         break;
11099     }
11100     expirep=(expirep+1)&65535;
11101   }
11102   return 0;
11103 }
11104
11105 // vim:shiftwidth=2:expandtab