1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2010 Ari64 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include <stdint.h> //include for uint64_t
25 #include "emu_if.h" //emulator interface
30 #include "assem_x86.h"
33 #include "assem_x64.h"
36 #include "assem_arm.h"
40 #define MAX_OUTPUT_BLOCK_SIZE 262144
41 #define CLOCK_DIVIDER 2
45 signed char regmap_entry[HOST_REGS];
46 signed char regmap[HOST_REGS];
55 uint64_t constmap[HOST_REGS];
63 struct ll_entry *next;
69 char insn[MAXBLOCK][10];
70 u_char itype[MAXBLOCK];
71 u_char opcode[MAXBLOCK];
72 u_char opcode2[MAXBLOCK];
80 u_char dep1[MAXBLOCK];
81 u_char dep2[MAXBLOCK];
85 char likely[MAXBLOCK];
88 uint64_t unneeded_reg[MAXBLOCK];
89 uint64_t unneeded_reg_upper[MAXBLOCK];
90 uint64_t branch_unneeded_reg[MAXBLOCK];
91 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
92 uint64_t p32[MAXBLOCK];
93 uint64_t pr32[MAXBLOCK];
94 signed char regmap_pre[MAXBLOCK][HOST_REGS];
95 signed char regmap[MAXBLOCK][HOST_REGS];
96 signed char regmap_entry[MAXBLOCK][HOST_REGS];
97 uint64_t constmap[MAXBLOCK][HOST_REGS];
98 struct regstat regs[MAXBLOCK];
99 struct regstat branch_regs[MAXBLOCK];
100 signed char minimum_free_regs[MAXBLOCK];
101 u_int needed_reg[MAXBLOCK];
102 uint64_t requires_32bit[MAXBLOCK];
103 u_int wont_dirty[MAXBLOCK];
104 u_int will_dirty[MAXBLOCK];
107 u_int instr_addr[MAXBLOCK];
108 u_int link_addr[MAXBLOCK][3];
110 u_int stubs[MAXBLOCK*3][8];
112 u_int literals[1024][2];
117 struct ll_entry *jump_in[4096];
118 struct ll_entry *jump_out[4096];
119 struct ll_entry *jump_dirty[4096];
120 u_int hash_table[65536][4] __attribute__((aligned(16)));
121 char shadow[1048576] __attribute__((aligned(16)));
125 u_int stop_after_jal;
126 extern u_char restore_candidate[512];
127 extern int cycle_count;
129 /* registers that may be allocated */
131 #define HIREG 32 // hi
132 #define LOREG 33 // lo
133 #define FSREG 34 // FPU status (FCSR)
134 #define CSREG 35 // Coprocessor status
135 #define CCREG 36 // Cycle count
136 #define INVCP 37 // Pointer to invalid_code
137 #define MMREG 38 // Pointer to memory_map
138 #define ROREG 39 // ram offset (if rdram!=0x80000000)
140 #define FTEMP 40 // FPU temporary register
141 #define PTEMP 41 // Prefetch temporary register
142 #define TLREG 42 // TLB mapping offset
143 #define RHASH 43 // Return address hash
144 #define RHTBL 44 // Return address hash table address
145 #define RTEMP 45 // JR/JALR address register
147 #define AGEN1 46 // Address generation temporary register
148 #define AGEN2 47 // Address generation temporary register
149 #define MGEN1 48 // Maptable address generation temporary register
150 #define MGEN2 49 // Maptable address generation temporary register
151 #define BTREG 50 // Branch target temporary register
153 /* instruction types */
154 #define NOP 0 // No operation
155 #define LOAD 1 // Load
156 #define STORE 2 // Store
157 #define LOADLR 3 // Unaligned load
158 #define STORELR 4 // Unaligned store
159 #define MOV 5 // Move
160 #define ALU 6 // Arithmetic/logic
161 #define MULTDIV 7 // Multiply/divide
162 #define SHIFT 8 // Shift by register
163 #define SHIFTIMM 9// Shift by immediate
164 #define IMM16 10 // 16-bit immediate
165 #define RJUMP 11 // Unconditional jump to register
166 #define UJUMP 12 // Unconditional jump
167 #define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
168 #define SJUMP 14 // Conditional branch (regimm format)
169 #define COP0 15 // Coprocessor 0
170 #define COP1 16 // Coprocessor 1
171 #define C1LS 17 // Coprocessor 1 load/store
172 #define FJUMP 18 // Conditional branch (floating point)
173 #define FLOAT 19 // Floating point unit
174 #define FCONV 20 // Convert integer to float
175 #define FCOMP 21 // Floating point compare (sets FSREG)
176 #define SYSCALL 22// SYSCALL
177 #define OTHER 23 // Other
178 #define SPAN 24 // Branch/delay slot spans 2 pages
179 #define NI 25 // Not implemented
180 #define HLECALL 26// PCSX fake opcodes for HLE
181 #define COP2 27 // Coprocessor 2 move
182 #define C2LS 28 // Coprocessor 2 load/store
183 #define C2OP 29 // Coprocessor 2 operation
184 #define INTCALL 30// Call interpreter to handle rare corner cases
193 #define LOADBU_STUB 7
194 #define LOADHU_STUB 8
195 #define STOREB_STUB 9
196 #define STOREH_STUB 10
197 #define STOREW_STUB 11
198 #define STORED_STUB 12
199 #define STORELR_STUB 13
200 #define INVCODE_STUB 14
208 int new_recompile_block(int addr);
209 void *get_addr_ht(u_int vaddr);
210 void invalidate_block(u_int block);
211 void invalidate_addr(u_int addr);
212 void remove_hash(int vaddr);
215 void dyna_linker_ds();
217 void verify_code_vm();
218 void verify_code_ds();
221 void fp_exception_ds();
223 void jump_syscall_hle();
227 void new_dyna_leave();
232 void read_nomem_new();
233 void read_nomemb_new();
234 void read_nomemh_new();
235 void read_nomemd_new();
236 void write_nomem_new();
237 void write_nomemb_new();
238 void write_nomemh_new();
239 void write_nomemd_new();
240 void write_rdram_new();
241 void write_rdramb_new();
242 void write_rdramh_new();
243 void write_rdramd_new();
244 extern u_int memory_map[1048576];
246 // Needed by assembler
247 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
248 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
249 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
250 void load_all_regs(signed char i_regmap[]);
251 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
252 void load_regs_entry(int t);
253 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
257 //#define DEBUG_CYCLE_COUNT 1
260 //#define assem_debug printf
261 //#define inv_debug printf
262 #define assem_debug nullf
263 #define inv_debug nullf
265 static void tlb_hacks()
269 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
273 switch (ROM_HEADER->Country_code&0xFF)
285 // Unknown country code
289 u_int rom_addr=(u_int)rom;
291 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
292 // in the lower 4G of memory to use this hack. Copy it if necessary.
293 if((void *)rom>(void *)0xffffffff) {
294 munmap(ROM_COPY, 67108864);
295 if(mmap(ROM_COPY, 12582912,
296 PROT_READ | PROT_WRITE,
297 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
298 -1, 0) <= 0) {printf("mmap() failed\n");}
299 memcpy(ROM_COPY,rom,12582912);
300 rom_addr=(u_int)ROM_COPY;
304 for(n=0x7F000;n<0x80000;n++) {
305 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
312 static u_int get_page(u_int vaddr)
315 u_int page=(vaddr^0x80000000)>>12;
317 u_int page=vaddr&~0xe0000000;
318 if (page < 0x1000000)
319 page &= ~0x0e00000; // RAM mirrors
323 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
325 if(page>2048) page=2048+(page&2047);
329 static u_int get_vpage(u_int vaddr)
331 u_int vpage=(vaddr^0x80000000)>>12;
333 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
335 if(vpage>2048) vpage=2048+(vpage&2047);
339 // Get address from virtual address
340 // This is called from the recompiled JR/JALR instructions
341 void *get_addr(u_int vaddr)
343 u_int page=get_page(vaddr);
344 u_int vpage=get_vpage(vaddr);
345 struct ll_entry *head;
346 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
349 if(head->vaddr==vaddr&&head->reg32==0) {
350 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
351 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
354 ht_bin[1]=(int)head->addr;
360 head=jump_dirty[vpage];
362 if(head->vaddr==vaddr&&head->reg32==0) {
363 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
364 // Don't restore blocks which are about to expire from the cache
365 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
366 if(verify_dirty(head->addr)) {
367 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
368 invalid_code[vaddr>>12]=0;
369 memory_map[vaddr>>12]|=0x40000000;
372 if(tlb_LUT_r[vaddr>>12]) {
373 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
374 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
377 restore_candidate[vpage>>3]|=1<<(vpage&7);
379 else restore_candidate[page>>3]|=1<<(page&7);
380 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
381 if(ht_bin[0]==vaddr) {
382 ht_bin[1]=(int)head->addr; // Replace existing entry
388 ht_bin[1]=(int)head->addr;
396 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
397 int r=new_recompile_block(vaddr);
398 if(r==0) return get_addr(vaddr);
399 // Execute in unmapped page, generate pagefault execption
401 Cause=(vaddr<<31)|0x8;
402 EPC=(vaddr&1)?vaddr-5:vaddr;
404 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
405 EntryHi=BadVAddr&0xFFFFE000;
406 return get_addr_ht(0x80000000);
408 // Look up address in hash table first
409 void *get_addr_ht(u_int vaddr)
411 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
412 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
413 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
414 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
415 return get_addr(vaddr);
418 void *get_addr_32(u_int vaddr,u_int flags)
421 return get_addr(vaddr);
423 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
424 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
425 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
426 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
427 u_int page=get_page(vaddr);
428 u_int vpage=get_vpage(vaddr);
429 struct ll_entry *head;
432 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
433 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
435 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
437 ht_bin[1]=(int)head->addr;
439 }else if(ht_bin[2]==-1) {
440 ht_bin[3]=(int)head->addr;
443 //ht_bin[3]=ht_bin[1];
444 //ht_bin[2]=ht_bin[0];
445 //ht_bin[1]=(int)head->addr;
452 head=jump_dirty[vpage];
454 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
455 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
456 // Don't restore blocks which are about to expire from the cache
457 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
458 if(verify_dirty(head->addr)) {
459 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
460 invalid_code[vaddr>>12]=0;
461 memory_map[vaddr>>12]|=0x40000000;
464 if(tlb_LUT_r[vaddr>>12]) {
465 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
466 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
469 restore_candidate[vpage>>3]|=1<<(vpage&7);
471 else restore_candidate[page>>3]|=1<<(page&7);
473 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
475 ht_bin[1]=(int)head->addr;
477 }else if(ht_bin[2]==-1) {
478 ht_bin[3]=(int)head->addr;
481 //ht_bin[3]=ht_bin[1];
482 //ht_bin[2]=ht_bin[0];
483 //ht_bin[1]=(int)head->addr;
491 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
492 int r=new_recompile_block(vaddr);
493 if(r==0) return get_addr(vaddr);
494 // Execute in unmapped page, generate pagefault execption
496 Cause=(vaddr<<31)|0x8;
497 EPC=(vaddr&1)?vaddr-5:vaddr;
499 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
500 EntryHi=BadVAddr&0xFFFFE000;
501 return get_addr_ht(0x80000000);
505 void clear_all_regs(signed char regmap[])
508 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
511 signed char get_reg(signed char regmap[],int r)
514 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map[hr]==r) return hr;
518 // Find a register that is available for two consecutive cycles
519 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
522 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr;
526 int count_free_regs(signed char regmap[])
530 for(hr=0;hr<HOST_REGS;hr++)
532 if(hr!=EXCLUDE_REG) {
533 if(regmap[hr]<0) count++;
539 void dirty_reg(struct regstat *cur,signed char reg)
543 for (hr=0;hr<HOST_REGS;hr++) {
544 if((cur->regmap[hr]&63)==reg) {
550 // If we dirty the lower half of a 64 bit register which is now being
551 // sign-extended, we need to dump the upper half.
552 // Note: Do this only after completion of the instruction, because
553 // some instructions may need to read the full 64-bit value even if
554 // overwriting it (eg SLTI, DSRA32).
555 static void flush_dirty_uppers(struct regstat *cur)
558 for (hr=0;hr<HOST_REGS;hr++) {
559 if((cur->dirty>>hr)&1) {
562 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
567 void set_const(struct regstat *cur,signed char reg,uint64_t value)
571 for (hr=0;hr<HOST_REGS;hr++) {
572 if(cur->regmap[hr]==reg) {
574 cur->constmap[hr]=value;
576 else if((cur->regmap[hr]^64)==reg) {
578 cur->constmap[hr]=value>>32;
583 void clear_const(struct regstat *cur,signed char reg)
587 for (hr=0;hr<HOST_REGS;hr++) {
588 if((cur->regmap[hr]&63)==reg) {
589 cur->isconst&=~(1<<hr);
594 int is_const(struct regstat *cur,signed char reg)
598 for (hr=0;hr<HOST_REGS;hr++) {
599 if((cur->regmap[hr]&63)==reg) {
600 return (cur->isconst>>hr)&1;
605 uint64_t get_const(struct regstat *cur,signed char reg)
609 for (hr=0;hr<HOST_REGS;hr++) {
610 if(cur->regmap[hr]==reg) {
611 return cur->constmap[hr];
614 printf("Unknown constant in r%d\n",reg);
618 // Least soon needed registers
619 // Look at the next ten instructions and see which registers
620 // will be used. Try not to reallocate these.
621 void lsn(u_char hsn[], int i, int *preferred_reg)
631 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
633 // Don't go past an unconditonal jump
640 if(rs1[i+j]) hsn[rs1[i+j]]=j;
641 if(rs2[i+j]) hsn[rs2[i+j]]=j;
642 if(rt1[i+j]) hsn[rt1[i+j]]=j;
643 if(rt2[i+j]) hsn[rt2[i+j]]=j;
644 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
645 // Stores can allocate zero
649 // On some architectures stores need invc_ptr
650 #if defined(HOST_IMM8)
651 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
655 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
663 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
665 // Follow first branch
666 int t=(ba[i+b]-start)>>2;
667 j=7-b;if(t+j>=slen) j=slen-t-1;
670 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
671 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
672 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
673 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
676 // TODO: preferred register based on backward branch
678 // Delay slot should preferably not overwrite branch conditions or cycle count
679 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
680 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
681 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
687 // Coprocessor load/store needs FTEMP, even if not declared
688 if(itype[i]==C1LS||itype[i]==C2LS) {
691 // Load L/R also uses FTEMP as a temporary register
692 if(itype[i]==LOADLR) {
695 // Also SWL/SWR/SDL/SDR
696 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
699 // Don't remove the TLB registers either
700 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
703 // Don't remove the miniht registers
704 if(itype[i]==UJUMP||itype[i]==RJUMP)
711 // We only want to allocate registers if we're going to use them again soon
712 int needed_again(int r, int i)
718 u_char hsn[MAXREG+1];
721 memset(hsn,10,sizeof(hsn));
722 lsn(hsn,i,&preferred_reg);
724 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
726 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
727 return 0; // Don't need any registers if exiting the block
735 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
737 // Don't go past an unconditonal jump
741 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
748 if(rs1[i+j]==r) rn=j;
749 if(rs2[i+j]==r) rn=j;
750 if((unneeded_reg[i+j]>>r)&1) rn=10;
751 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
759 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
761 // Follow first branch
763 int t=(ba[i+b]-start)>>2;
764 j=7-b;if(t+j>=slen) j=slen-t-1;
767 if(!((unneeded_reg[t+j]>>r)&1)) {
768 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
769 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
775 for(hr=0;hr<HOST_REGS;hr++) {
776 if(hr!=EXCLUDE_REG) {
777 if(rn<hsn[hr]) return 1;
783 // Try to match register allocations at the end of a loop with those
785 int loop_reg(int i, int r, int hr)
794 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
796 // Don't go past an unconditonal jump
803 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
808 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
809 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
810 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
812 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
814 int t=(ba[i+k]-start)>>2;
815 int reg=get_reg(regs[t].regmap_entry,r);
816 if(reg>=0) return reg;
817 //reg=get_reg(regs[t+1].regmap_entry,r);
818 //if(reg>=0) return reg;
826 // Allocate every register, preserving source/target regs
827 void alloc_all(struct regstat *cur,int i)
831 for(hr=0;hr<HOST_REGS;hr++) {
832 if(hr!=EXCLUDE_REG) {
833 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
834 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
837 cur->dirty&=~(1<<hr);
840 if((cur->regmap[hr]&63)==0)
843 cur->dirty&=~(1<<hr);
850 void div64(int64_t dividend,int64_t divisor)
854 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
855 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
857 void divu64(uint64_t dividend,uint64_t divisor)
861 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
862 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
865 void mult64(uint64_t m1,uint64_t m2)
867 unsigned long long int op1, op2, op3, op4;
868 unsigned long long int result1, result2, result3, result4;
869 unsigned long long int temp1, temp2, temp3, temp4;
885 op1 = op2 & 0xFFFFFFFF;
886 op2 = (op2 >> 32) & 0xFFFFFFFF;
887 op3 = op4 & 0xFFFFFFFF;
888 op4 = (op4 >> 32) & 0xFFFFFFFF;
891 temp2 = (temp1 >> 32) + op1 * op4;
893 temp4 = (temp3 >> 32) + op2 * op4;
895 result1 = temp1 & 0xFFFFFFFF;
896 result2 = temp2 + (temp3 & 0xFFFFFFFF);
897 result3 = (result2 >> 32) + temp4;
898 result4 = (result3 >> 32);
900 lo = result1 | (result2 << 32);
901 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
910 void multu64(uint64_t m1,uint64_t m2)
912 unsigned long long int op1, op2, op3, op4;
913 unsigned long long int result1, result2, result3, result4;
914 unsigned long long int temp1, temp2, temp3, temp4;
916 op1 = m1 & 0xFFFFFFFF;
917 op2 = (m1 >> 32) & 0xFFFFFFFF;
918 op3 = m2 & 0xFFFFFFFF;
919 op4 = (m2 >> 32) & 0xFFFFFFFF;
922 temp2 = (temp1 >> 32) + op1 * op4;
924 temp4 = (temp3 >> 32) + op2 * op4;
926 result1 = temp1 & 0xFFFFFFFF;
927 result2 = temp2 + (temp3 & 0xFFFFFFFF);
928 result3 = (result2 >> 32) + temp4;
929 result4 = (result3 >> 32);
931 lo = result1 | (result2 << 32);
932 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
934 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
935 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
938 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
946 else original=loaded;
949 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
952 original>>=64-(bits^56);
953 original<<=64-(bits^56);
957 else original=loaded;
962 #include "assem_x86.c"
965 #include "assem_x64.c"
968 #include "assem_arm.c"
971 // Add virtual address mapping to linked list
972 void ll_add(struct ll_entry **head,int vaddr,void *addr)
974 struct ll_entry *new_entry;
975 new_entry=malloc(sizeof(struct ll_entry));
976 assert(new_entry!=NULL);
977 new_entry->vaddr=vaddr;
979 new_entry->addr=addr;
980 new_entry->next=*head;
984 // Add virtual address mapping for 32-bit compiled block
985 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
987 ll_add(head,vaddr,addr);
989 (*head)->reg32=reg32;
993 // Check if an address is already compiled
994 // but don't return addresses which are about to expire from the cache
995 void *check_addr(u_int vaddr)
997 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
998 if(ht_bin[0]==vaddr) {
999 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1000 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
1002 if(ht_bin[2]==vaddr) {
1003 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1004 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1006 u_int page=get_page(vaddr);
1007 struct ll_entry *head;
1010 if(head->vaddr==vaddr&&head->reg32==0) {
1011 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1012 // Update existing entry with current address
1013 if(ht_bin[0]==vaddr) {
1014 ht_bin[1]=(int)head->addr;
1017 if(ht_bin[2]==vaddr) {
1018 ht_bin[3]=(int)head->addr;
1021 // Insert into hash table with low priority.
1022 // Don't evict existing entries, as they are probably
1023 // addresses that are being accessed frequently.
1025 ht_bin[1]=(int)head->addr;
1027 }else if(ht_bin[2]==-1) {
1028 ht_bin[3]=(int)head->addr;
1039 void remove_hash(int vaddr)
1041 //printf("remove hash: %x\n",vaddr);
1042 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1043 if(ht_bin[2]==vaddr) {
1044 ht_bin[2]=ht_bin[3]=-1;
1046 if(ht_bin[0]==vaddr) {
1047 ht_bin[0]=ht_bin[2];
1048 ht_bin[1]=ht_bin[3];
1049 ht_bin[2]=ht_bin[3]=-1;
1053 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1055 struct ll_entry *next;
1057 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1058 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1060 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1061 remove_hash((*head)->vaddr);
1068 head=&((*head)->next);
1073 // Remove all entries from linked list
1074 void ll_clear(struct ll_entry **head)
1076 struct ll_entry *cur;
1077 struct ll_entry *next;
1088 // Dereference the pointers and remove if it matches
1089 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1092 int ptr=get_pointer(head->addr);
1093 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1094 if(((ptr>>shift)==(addr>>shift)) ||
1095 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1097 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1098 u_int host_addr=(u_int)kill_pointer(head->addr);
1100 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1107 // This is called when we write to a compiled block (see do_invstub)
1108 void invalidate_page(u_int page)
1110 struct ll_entry *head;
1111 struct ll_entry *next;
1115 inv_debug("INVALIDATE: %x\n",head->vaddr);
1116 remove_hash(head->vaddr);
1121 head=jump_out[page];
1124 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1125 u_int host_addr=(u_int)kill_pointer(head->addr);
1127 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1134 void invalidate_block(u_int block)
1136 u_int page=get_page(block<<12);
1137 u_int vpage=get_vpage(block<<12);
1138 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1139 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1142 struct ll_entry *head;
1143 head=jump_dirty[vpage];
1144 //printf("page=%d vpage=%d\n",page,vpage);
1147 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1148 get_bounds((int)head->addr,&start,&end);
1149 //printf("start: %x end: %x\n",start,end);
1150 if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
1151 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1152 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1153 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1157 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1158 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1159 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1160 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1167 //printf("first=%d last=%d\n",first,last);
1168 invalidate_page(page);
1169 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1170 assert(last<page+5);
1171 // Invalidate the adjacent pages if a block crosses a 4K boundary
1173 invalidate_page(first);
1176 for(first=page+1;first<last;first++) {
1177 invalidate_page(first);
1183 // Don't trap writes
1184 invalid_code[block]=1;
1186 // If there is a valid TLB entry for this page, remove write protect
1187 if(tlb_LUT_w[block]) {
1188 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1189 // CHECK: Is this right?
1190 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1191 u_int real_block=tlb_LUT_w[block]>>12;
1192 invalid_code[real_block]=1;
1193 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1195 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1199 memset(mini_ht,-1,sizeof(mini_ht));
1202 void invalidate_addr(u_int addr)
1204 invalidate_block(addr>>12);
1206 // This is called when loading a save state.
1207 // Anything could have changed, so invalidate everything.
1208 void invalidate_all_pages()
1211 for(page=0;page<4096;page++)
1212 invalidate_page(page);
1213 for(page=0;page<1048576;page++)
1214 if(!invalid_code[page]) {
1215 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1216 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1219 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1222 memset(mini_ht,-1,sizeof(mini_ht));
1226 for(page=0;page<0x100000;page++) {
1227 if(tlb_LUT_r[page]) {
1228 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1229 if(!tlb_LUT_w[page]||!invalid_code[page])
1230 memory_map[page]|=0x40000000; // Write protect
1232 else memory_map[page]=-1;
1233 if(page==0x80000) page=0xC0000;
1239 // Add an entry to jump_out after making a link
1240 void add_link(u_int vaddr,void *src)
1242 u_int page=get_page(vaddr);
1243 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1244 ll_add(jump_out+page,vaddr,src);
1245 //int ptr=get_pointer(src);
1246 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1249 // If a code block was found to be unmodified (bit was set in
1250 // restore_candidate) and it remains unmodified (bit is clear
1251 // in invalid_code) then move the entries for that 4K page from
1252 // the dirty list to the clean list.
1253 void clean_blocks(u_int page)
1255 struct ll_entry *head;
1256 inv_debug("INV: clean_blocks page=%d\n",page);
1257 head=jump_dirty[page];
1259 if(!invalid_code[head->vaddr>>12]) {
1260 // Don't restore blocks which are about to expire from the cache
1261 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1263 if(verify_dirty((int)head->addr)) {
1264 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1267 get_bounds((int)head->addr,&start,&end);
1268 if(start-(u_int)rdram<RAM_SIZE) {
1269 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1270 inv|=invalid_code[i];
1273 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1274 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1275 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1276 if(addr<start||addr>=end) inv=1;
1278 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1282 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1283 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1286 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1288 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1289 //printf("page=%x, addr=%x\n",page,head->vaddr);
1290 //assert(head->vaddr>>12==(page|0x80000));
1291 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1292 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1294 if(ht_bin[0]==head->vaddr) {
1295 ht_bin[1]=(int)clean_addr; // Replace existing entry
1297 if(ht_bin[2]==head->vaddr) {
1298 ht_bin[3]=(int)clean_addr; // Replace existing entry
1311 void mov_alloc(struct regstat *current,int i)
1313 // Note: Don't need to actually alloc the source registers
1314 if((~current->is32>>rs1[i])&1) {
1315 //alloc_reg64(current,i,rs1[i]);
1316 alloc_reg64(current,i,rt1[i]);
1317 current->is32&=~(1LL<<rt1[i]);
1319 //alloc_reg(current,i,rs1[i]);
1320 alloc_reg(current,i,rt1[i]);
1321 current->is32|=(1LL<<rt1[i]);
1323 clear_const(current,rs1[i]);
1324 clear_const(current,rt1[i]);
1325 dirty_reg(current,rt1[i]);
1328 void shiftimm_alloc(struct regstat *current,int i)
1330 clear_const(current,rs1[i]);
1331 clear_const(current,rt1[i]);
1332 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1335 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1337 alloc_reg(current,i,rt1[i]);
1338 current->is32|=1LL<<rt1[i];
1339 dirty_reg(current,rt1[i]);
1342 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1345 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1346 alloc_reg64(current,i,rt1[i]);
1347 current->is32&=~(1LL<<rt1[i]);
1348 dirty_reg(current,rt1[i]);
1351 if(opcode2[i]==0x3c) // DSLL32
1354 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1355 alloc_reg64(current,i,rt1[i]);
1356 current->is32&=~(1LL<<rt1[i]);
1357 dirty_reg(current,rt1[i]);
1360 if(opcode2[i]==0x3e) // DSRL32
1363 alloc_reg64(current,i,rs1[i]);
1365 alloc_reg64(current,i,rt1[i]);
1366 current->is32&=~(1LL<<rt1[i]);
1368 alloc_reg(current,i,rt1[i]);
1369 current->is32|=1LL<<rt1[i];
1371 dirty_reg(current,rt1[i]);
1374 if(opcode2[i]==0x3f) // DSRA32
1377 alloc_reg64(current,i,rs1[i]);
1378 alloc_reg(current,i,rt1[i]);
1379 current->is32|=1LL<<rt1[i];
1380 dirty_reg(current,rt1[i]);
1385 void shift_alloc(struct regstat *current,int i)
1388 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1390 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1391 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1392 alloc_reg(current,i,rt1[i]);
1393 if(rt1[i]==rs2[i]) {
1394 alloc_reg_temp(current,i,-1);
1395 minimum_free_regs[i]=1;
1397 current->is32|=1LL<<rt1[i];
1398 } else { // DSLLV/DSRLV/DSRAV
1399 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1400 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1401 alloc_reg64(current,i,rt1[i]);
1402 current->is32&=~(1LL<<rt1[i]);
1403 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1405 alloc_reg_temp(current,i,-1);
1406 minimum_free_regs[i]=1;
1409 clear_const(current,rs1[i]);
1410 clear_const(current,rs2[i]);
1411 clear_const(current,rt1[i]);
1412 dirty_reg(current,rt1[i]);
1416 void alu_alloc(struct regstat *current,int i)
1418 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1420 if(rs1[i]&&rs2[i]) {
1421 alloc_reg(current,i,rs1[i]);
1422 alloc_reg(current,i,rs2[i]);
1425 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1426 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1428 alloc_reg(current,i,rt1[i]);
1430 current->is32|=1LL<<rt1[i];
1432 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1434 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1436 alloc_reg64(current,i,rs1[i]);
1437 alloc_reg64(current,i,rs2[i]);
1438 alloc_reg(current,i,rt1[i]);
1440 alloc_reg(current,i,rs1[i]);
1441 alloc_reg(current,i,rs2[i]);
1442 alloc_reg(current,i,rt1[i]);
1445 current->is32|=1LL<<rt1[i];
1447 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1449 if(rs1[i]&&rs2[i]) {
1450 alloc_reg(current,i,rs1[i]);
1451 alloc_reg(current,i,rs2[i]);
1455 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1456 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1458 alloc_reg(current,i,rt1[i]);
1459 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1461 if(!((current->uu>>rt1[i])&1)) {
1462 alloc_reg64(current,i,rt1[i]);
1464 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1465 if(rs1[i]&&rs2[i]) {
1466 alloc_reg64(current,i,rs1[i]);
1467 alloc_reg64(current,i,rs2[i]);
1471 // Is is really worth it to keep 64-bit values in registers?
1473 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1474 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1478 current->is32&=~(1LL<<rt1[i]);
1480 current->is32|=1LL<<rt1[i];
1484 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1486 if(rs1[i]&&rs2[i]) {
1487 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1488 alloc_reg64(current,i,rs1[i]);
1489 alloc_reg64(current,i,rs2[i]);
1490 alloc_reg64(current,i,rt1[i]);
1492 alloc_reg(current,i,rs1[i]);
1493 alloc_reg(current,i,rs2[i]);
1494 alloc_reg(current,i,rt1[i]);
1498 alloc_reg(current,i,rt1[i]);
1499 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1500 // DADD used as move, or zeroing
1501 // If we have a 64-bit source, then make the target 64 bits too
1502 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1503 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1504 alloc_reg64(current,i,rt1[i]);
1505 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1506 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1507 alloc_reg64(current,i,rt1[i]);
1509 if(opcode2[i]>=0x2e&&rs2[i]) {
1510 // DSUB used as negation - 64-bit result
1511 // If we have a 32-bit register, extend it to 64 bits
1512 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1513 alloc_reg64(current,i,rt1[i]);
1517 if(rs1[i]&&rs2[i]) {
1518 current->is32&=~(1LL<<rt1[i]);
1520 current->is32&=~(1LL<<rt1[i]);
1521 if((current->is32>>rs1[i])&1)
1522 current->is32|=1LL<<rt1[i];
1524 current->is32&=~(1LL<<rt1[i]);
1525 if((current->is32>>rs2[i])&1)
1526 current->is32|=1LL<<rt1[i];
1528 current->is32|=1LL<<rt1[i];
1532 clear_const(current,rs1[i]);
1533 clear_const(current,rs2[i]);
1534 clear_const(current,rt1[i]);
1535 dirty_reg(current,rt1[i]);
1538 void imm16_alloc(struct regstat *current,int i)
1540 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1542 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1543 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1544 current->is32&=~(1LL<<rt1[i]);
1545 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1546 // TODO: Could preserve the 32-bit flag if the immediate is zero
1547 alloc_reg64(current,i,rt1[i]);
1548 alloc_reg64(current,i,rs1[i]);
1550 clear_const(current,rs1[i]);
1551 clear_const(current,rt1[i]);
1553 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1554 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1555 current->is32|=1LL<<rt1[i];
1556 clear_const(current,rs1[i]);
1557 clear_const(current,rt1[i]);
1559 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1560 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1561 if(rs1[i]!=rt1[i]) {
1562 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1563 alloc_reg64(current,i,rt1[i]);
1564 current->is32&=~(1LL<<rt1[i]);
1567 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1568 if(is_const(current,rs1[i])) {
1569 int v=get_const(current,rs1[i]);
1570 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1571 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1572 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1574 else clear_const(current,rt1[i]);
1576 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1577 if(is_const(current,rs1[i])) {
1578 int v=get_const(current,rs1[i]);
1579 set_const(current,rt1[i],v+imm[i]);
1581 else clear_const(current,rt1[i]);
1582 current->is32|=1LL<<rt1[i];
1585 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1586 current->is32|=1LL<<rt1[i];
1588 dirty_reg(current,rt1[i]);
1591 void load_alloc(struct regstat *current,int i)
1593 clear_const(current,rt1[i]);
1594 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1595 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1596 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1598 alloc_reg(current,i,rt1[i]);
1599 if(get_reg(current->regmap,rt1[i])<0) {
1600 // dummy load, but we still need a register to calculate the address
1601 alloc_reg_temp(current,i,-1);
1602 minimum_free_regs[i]=1;
1604 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1606 current->is32&=~(1LL<<rt1[i]);
1607 alloc_reg64(current,i,rt1[i]);
1609 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1611 current->is32&=~(1LL<<rt1[i]);
1612 alloc_reg64(current,i,rt1[i]);
1613 alloc_all(current,i);
1614 alloc_reg64(current,i,FTEMP);
1615 minimum_free_regs[i]=HOST_REGS;
1617 else current->is32|=1LL<<rt1[i];
1618 dirty_reg(current,rt1[i]);
1619 // If using TLB, need a register for pointer to the mapping table
1620 if(using_tlb) alloc_reg(current,i,TLREG);
1621 // LWL/LWR need a temporary register for the old value
1622 if(opcode[i]==0x22||opcode[i]==0x26)
1624 alloc_reg(current,i,FTEMP);
1625 alloc_reg_temp(current,i,-1);
1626 minimum_free_regs[i]=1;
1631 // Load to r0 (dummy load)
1632 // but we still need a register to calculate the address
1633 if(opcode[i]==0x22||opcode[i]==0x26)
1635 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1637 alloc_reg_temp(current,i,-1);
1638 minimum_free_regs[i]=1;
1639 if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1641 alloc_all(current,i);
1642 alloc_reg64(current,i,FTEMP);
1643 minimum_free_regs[i]=HOST_REGS;
1648 void store_alloc(struct regstat *current,int i)
1650 clear_const(current,rs2[i]);
1651 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1652 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1653 alloc_reg(current,i,rs2[i]);
1654 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1655 alloc_reg64(current,i,rs2[i]);
1656 if(rs2[i]) alloc_reg(current,i,FTEMP);
1658 // If using TLB, need a register for pointer to the mapping table
1659 if(using_tlb) alloc_reg(current,i,TLREG);
1660 #if defined(HOST_IMM8)
1661 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1662 else alloc_reg(current,i,INVCP);
1664 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1665 alloc_reg(current,i,FTEMP);
1667 // We need a temporary register for address generation
1668 alloc_reg_temp(current,i,-1);
1669 minimum_free_regs[i]=1;
1672 void c1ls_alloc(struct regstat *current,int i)
1674 //clear_const(current,rs1[i]); // FIXME
1675 clear_const(current,rt1[i]);
1676 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1677 alloc_reg(current,i,CSREG); // Status
1678 alloc_reg(current,i,FTEMP);
1679 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1680 alloc_reg64(current,i,FTEMP);
1682 // If using TLB, need a register for pointer to the mapping table
1683 if(using_tlb) alloc_reg(current,i,TLREG);
1684 #if defined(HOST_IMM8)
1685 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1686 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1687 alloc_reg(current,i,INVCP);
1689 // We need a temporary register for address generation
1690 alloc_reg_temp(current,i,-1);
1693 void c2ls_alloc(struct regstat *current,int i)
1695 clear_const(current,rt1[i]);
1696 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1697 alloc_reg(current,i,FTEMP);
1698 // If using TLB, need a register for pointer to the mapping table
1699 if(using_tlb) alloc_reg(current,i,TLREG);
1700 #if defined(HOST_IMM8)
1701 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1702 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1703 alloc_reg(current,i,INVCP);
1705 // We need a temporary register for address generation
1706 alloc_reg_temp(current,i,-1);
1707 minimum_free_regs[i]=1;
1710 #ifndef multdiv_alloc
1711 void multdiv_alloc(struct regstat *current,int i)
1718 // case 0x1D: DMULTU
1721 clear_const(current,rs1[i]);
1722 clear_const(current,rs2[i]);
1725 if((opcode2[i]&4)==0) // 32-bit
1727 current->u&=~(1LL<<HIREG);
1728 current->u&=~(1LL<<LOREG);
1729 alloc_reg(current,i,HIREG);
1730 alloc_reg(current,i,LOREG);
1731 alloc_reg(current,i,rs1[i]);
1732 alloc_reg(current,i,rs2[i]);
1733 current->is32|=1LL<<HIREG;
1734 current->is32|=1LL<<LOREG;
1735 dirty_reg(current,HIREG);
1736 dirty_reg(current,LOREG);
1740 current->u&=~(1LL<<HIREG);
1741 current->u&=~(1LL<<LOREG);
1742 current->uu&=~(1LL<<HIREG);
1743 current->uu&=~(1LL<<LOREG);
1744 alloc_reg64(current,i,HIREG);
1745 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1746 alloc_reg64(current,i,rs1[i]);
1747 alloc_reg64(current,i,rs2[i]);
1748 alloc_all(current,i);
1749 current->is32&=~(1LL<<HIREG);
1750 current->is32&=~(1LL<<LOREG);
1751 dirty_reg(current,HIREG);
1752 dirty_reg(current,LOREG);
1753 minimum_free_regs[i]=HOST_REGS;
1758 // Multiply by zero is zero.
1759 // MIPS does not have a divide by zero exception.
1760 // The result is undefined, we return zero.
1761 alloc_reg(current,i,HIREG);
1762 alloc_reg(current,i,LOREG);
1763 current->is32|=1LL<<HIREG;
1764 current->is32|=1LL<<LOREG;
1765 dirty_reg(current,HIREG);
1766 dirty_reg(current,LOREG);
1771 void cop0_alloc(struct regstat *current,int i)
1773 if(opcode2[i]==0) // MFC0
1776 clear_const(current,rt1[i]);
1777 alloc_all(current,i);
1778 alloc_reg(current,i,rt1[i]);
1779 current->is32|=1LL<<rt1[i];
1780 dirty_reg(current,rt1[i]);
1783 else if(opcode2[i]==4) // MTC0
1786 clear_const(current,rs1[i]);
1787 alloc_reg(current,i,rs1[i]);
1788 alloc_all(current,i);
1791 alloc_all(current,i); // FIXME: Keep r0
1793 alloc_reg(current,i,0);
1798 // TLBR/TLBWI/TLBWR/TLBP/ERET
1799 assert(opcode2[i]==0x10);
1800 alloc_all(current,i);
1802 minimum_free_regs[i]=HOST_REGS;
1805 void cop1_alloc(struct regstat *current,int i)
1807 alloc_reg(current,i,CSREG); // Load status
1808 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1811 clear_const(current,rt1[i]);
1813 alloc_reg64(current,i,rt1[i]); // DMFC1
1814 current->is32&=~(1LL<<rt1[i]);
1816 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1817 current->is32|=1LL<<rt1[i];
1819 dirty_reg(current,rt1[i]);
1821 alloc_reg_temp(current,i,-1);
1823 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1826 clear_const(current,rs1[i]);
1828 alloc_reg64(current,i,rs1[i]); // DMTC1
1830 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1831 alloc_reg_temp(current,i,-1);
1835 alloc_reg(current,i,0);
1836 alloc_reg_temp(current,i,-1);
1839 minimum_free_regs[i]=1;
1841 void fconv_alloc(struct regstat *current,int i)
1843 alloc_reg(current,i,CSREG); // Load status
1844 alloc_reg_temp(current,i,-1);
1845 minimum_free_regs[i]=1;
1847 void float_alloc(struct regstat *current,int i)
1849 alloc_reg(current,i,CSREG); // Load status
1850 alloc_reg_temp(current,i,-1);
1851 minimum_free_regs[i]=1;
1853 void c2op_alloc(struct regstat *current,int i)
1855 alloc_reg_temp(current,i,-1);
1857 void fcomp_alloc(struct regstat *current,int i)
1859 alloc_reg(current,i,CSREG); // Load status
1860 alloc_reg(current,i,FSREG); // Load flags
1861 dirty_reg(current,FSREG); // Flag will be modified
1862 alloc_reg_temp(current,i,-1);
1863 minimum_free_regs[i]=1;
1866 void syscall_alloc(struct regstat *current,int i)
1868 alloc_cc(current,i);
1869 dirty_reg(current,CCREG);
1870 alloc_all(current,i);
1871 minimum_free_regs[i]=HOST_REGS;
1875 void delayslot_alloc(struct regstat *current,int i)
1886 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1887 printf("Disabled speculative precompilation\n");
1891 imm16_alloc(current,i);
1895 load_alloc(current,i);
1899 store_alloc(current,i);
1902 alu_alloc(current,i);
1905 shift_alloc(current,i);
1908 multdiv_alloc(current,i);
1911 shiftimm_alloc(current,i);
1914 mov_alloc(current,i);
1917 cop0_alloc(current,i);
1921 cop1_alloc(current,i);
1924 c1ls_alloc(current,i);
1927 c2ls_alloc(current,i);
1930 fconv_alloc(current,i);
1933 float_alloc(current,i);
1936 fcomp_alloc(current,i);
1939 c2op_alloc(current,i);
1944 // Special case where a branch and delay slot span two pages in virtual memory
1945 static void pagespan_alloc(struct regstat *current,int i)
1948 current->wasconst=0;
1950 minimum_free_regs[i]=HOST_REGS;
1951 alloc_all(current,i);
1952 alloc_cc(current,i);
1953 dirty_reg(current,CCREG);
1954 if(opcode[i]==3) // JAL
1956 alloc_reg(current,i,31);
1957 dirty_reg(current,31);
1959 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1961 alloc_reg(current,i,rs1[i]);
1963 alloc_reg(current,i,rt1[i]);
1964 dirty_reg(current,rt1[i]);
1967 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1969 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1970 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1971 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1973 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1974 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1978 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1980 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1981 if(!((current->is32>>rs1[i])&1))
1983 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1987 if(opcode[i]==0x11) // BC1
1989 alloc_reg(current,i,FSREG);
1990 alloc_reg(current,i,CSREG);
1995 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
1997 stubs[stubcount][0]=type;
1998 stubs[stubcount][1]=addr;
1999 stubs[stubcount][2]=retaddr;
2000 stubs[stubcount][3]=a;
2001 stubs[stubcount][4]=b;
2002 stubs[stubcount][5]=c;
2003 stubs[stubcount][6]=d;
2004 stubs[stubcount][7]=e;
2008 // Write out a single register
2009 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2012 for(hr=0;hr<HOST_REGS;hr++) {
2013 if(hr!=EXCLUDE_REG) {
2014 if((regmap[hr]&63)==r) {
2017 emit_storereg(r,hr);
2019 if((is32>>regmap[hr])&1) {
2020 emit_sarimm(hr,31,hr);
2021 emit_storereg(r|64,hr);
2025 emit_storereg(r|64,hr);
2035 //if(!tracedebug) return 0;
2038 for(i=0;i<2097152;i++) {
2039 unsigned int temp=sum;
2042 sum^=((u_int *)rdram)[i];
2051 sum^=((u_int *)reg)[i];
2059 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2061 #ifndef DISABLE_COP1
2064 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2074 void memdebug(int i)
2076 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2077 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2080 //if(Count>=-2084597794) {
2081 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2083 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2084 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2085 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2088 printf("TRACE: %x\n",(&i)[-1]);
2092 printf("TRACE: %x \n",(&j)[10]);
2093 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2097 //printf("TRACE: %x\n",(&i)[-1]);
2100 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2102 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2105 void alu_assemble(int i,struct regstat *i_regs)
2107 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2109 signed char s1,s2,t;
2110 t=get_reg(i_regs->regmap,rt1[i]);
2112 s1=get_reg(i_regs->regmap,rs1[i]);
2113 s2=get_reg(i_regs->regmap,rs2[i]);
2114 if(rs1[i]&&rs2[i]) {
2117 if(opcode2[i]&2) emit_sub(s1,s2,t);
2118 else emit_add(s1,s2,t);
2121 if(s1>=0) emit_mov(s1,t);
2122 else emit_loadreg(rs1[i],t);
2126 if(opcode2[i]&2) emit_neg(s2,t);
2127 else emit_mov(s2,t);
2130 emit_loadreg(rs2[i],t);
2131 if(opcode2[i]&2) emit_neg(t,t);
2134 else emit_zeroreg(t);
2138 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2140 signed char s1l,s2l,s1h,s2h,tl,th;
2141 tl=get_reg(i_regs->regmap,rt1[i]);
2142 th=get_reg(i_regs->regmap,rt1[i]|64);
2144 s1l=get_reg(i_regs->regmap,rs1[i]);
2145 s2l=get_reg(i_regs->regmap,rs2[i]);
2146 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2147 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2148 if(rs1[i]&&rs2[i]) {
2151 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2152 else emit_adds(s1l,s2l,tl);
2154 #ifdef INVERTED_CARRY
2155 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2157 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2159 else emit_add(s1h,s2h,th);
2163 if(s1l>=0) emit_mov(s1l,tl);
2164 else emit_loadreg(rs1[i],tl);
2166 if(s1h>=0) emit_mov(s1h,th);
2167 else emit_loadreg(rs1[i]|64,th);
2172 if(opcode2[i]&2) emit_negs(s2l,tl);
2173 else emit_mov(s2l,tl);
2176 emit_loadreg(rs2[i],tl);
2177 if(opcode2[i]&2) emit_negs(tl,tl);
2180 #ifdef INVERTED_CARRY
2181 if(s2h>=0) emit_mov(s2h,th);
2182 else emit_loadreg(rs2[i]|64,th);
2184 emit_adcimm(-1,th); // x86 has inverted carry flag
2189 if(s2h>=0) emit_rscimm(s2h,0,th);
2191 emit_loadreg(rs2[i]|64,th);
2192 emit_rscimm(th,0,th);
2195 if(s2h>=0) emit_mov(s2h,th);
2196 else emit_loadreg(rs2[i]|64,th);
2203 if(th>=0) emit_zeroreg(th);
2208 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2210 signed char s1l,s1h,s2l,s2h,t;
2211 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2213 t=get_reg(i_regs->regmap,rt1[i]);
2216 s1l=get_reg(i_regs->regmap,rs1[i]);
2217 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2218 s2l=get_reg(i_regs->regmap,rs2[i]);
2219 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2220 if(rs2[i]==0) // rx<r0
2223 if(opcode2[i]==0x2a) // SLT
2224 emit_shrimm(s1h,31,t);
2225 else // SLTU (unsigned can not be less than zero)
2228 else if(rs1[i]==0) // r0<rx
2231 if(opcode2[i]==0x2a) // SLT
2232 emit_set_gz64_32(s2h,s2l,t);
2233 else // SLTU (set if not zero)
2234 emit_set_nz64_32(s2h,s2l,t);
2237 assert(s1l>=0);assert(s1h>=0);
2238 assert(s2l>=0);assert(s2h>=0);
2239 if(opcode2[i]==0x2a) // SLT
2240 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2242 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2246 t=get_reg(i_regs->regmap,rt1[i]);
2249 s1l=get_reg(i_regs->regmap,rs1[i]);
2250 s2l=get_reg(i_regs->regmap,rs2[i]);
2251 if(rs2[i]==0) // rx<r0
2254 if(opcode2[i]==0x2a) // SLT
2255 emit_shrimm(s1l,31,t);
2256 else // SLTU (unsigned can not be less than zero)
2259 else if(rs1[i]==0) // r0<rx
2262 if(opcode2[i]==0x2a) // SLT
2263 emit_set_gz32(s2l,t);
2264 else // SLTU (set if not zero)
2265 emit_set_nz32(s2l,t);
2268 assert(s1l>=0);assert(s2l>=0);
2269 if(opcode2[i]==0x2a) // SLT
2270 emit_set_if_less32(s1l,s2l,t);
2272 emit_set_if_carry32(s1l,s2l,t);
2278 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2280 signed char s1l,s1h,s2l,s2h,th,tl;
2281 tl=get_reg(i_regs->regmap,rt1[i]);
2282 th=get_reg(i_regs->regmap,rt1[i]|64);
2283 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2287 s1l=get_reg(i_regs->regmap,rs1[i]);
2288 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2289 s2l=get_reg(i_regs->regmap,rs2[i]);
2290 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2291 if(rs1[i]&&rs2[i]) {
2292 assert(s1l>=0);assert(s1h>=0);
2293 assert(s2l>=0);assert(s2h>=0);
2294 if(opcode2[i]==0x24) { // AND
2295 emit_and(s1l,s2l,tl);
2296 emit_and(s1h,s2h,th);
2298 if(opcode2[i]==0x25) { // OR
2299 emit_or(s1l,s2l,tl);
2300 emit_or(s1h,s2h,th);
2302 if(opcode2[i]==0x26) { // XOR
2303 emit_xor(s1l,s2l,tl);
2304 emit_xor(s1h,s2h,th);
2306 if(opcode2[i]==0x27) { // NOR
2307 emit_or(s1l,s2l,tl);
2308 emit_or(s1h,s2h,th);
2315 if(opcode2[i]==0x24) { // AND
2319 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2321 if(s1l>=0) emit_mov(s1l,tl);
2322 else emit_loadreg(rs1[i],tl);
2323 if(s1h>=0) emit_mov(s1h,th);
2324 else emit_loadreg(rs1[i]|64,th);
2328 if(s2l>=0) emit_mov(s2l,tl);
2329 else emit_loadreg(rs2[i],tl);
2330 if(s2h>=0) emit_mov(s2h,th);
2331 else emit_loadreg(rs2[i]|64,th);
2338 if(opcode2[i]==0x27) { // NOR
2340 if(s1l>=0) emit_not(s1l,tl);
2342 emit_loadreg(rs1[i],tl);
2345 if(s1h>=0) emit_not(s1h,th);
2347 emit_loadreg(rs1[i]|64,th);
2353 if(s2l>=0) emit_not(s2l,tl);
2355 emit_loadreg(rs2[i],tl);
2358 if(s2h>=0) emit_not(s2h,th);
2360 emit_loadreg(rs2[i]|64,th);
2376 s1l=get_reg(i_regs->regmap,rs1[i]);
2377 s2l=get_reg(i_regs->regmap,rs2[i]);
2378 if(rs1[i]&&rs2[i]) {
2381 if(opcode2[i]==0x24) { // AND
2382 emit_and(s1l,s2l,tl);
2384 if(opcode2[i]==0x25) { // OR
2385 emit_or(s1l,s2l,tl);
2387 if(opcode2[i]==0x26) { // XOR
2388 emit_xor(s1l,s2l,tl);
2390 if(opcode2[i]==0x27) { // NOR
2391 emit_or(s1l,s2l,tl);
2397 if(opcode2[i]==0x24) { // AND
2400 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2402 if(s1l>=0) emit_mov(s1l,tl);
2403 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2407 if(s2l>=0) emit_mov(s2l,tl);
2408 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2410 else emit_zeroreg(tl);
2412 if(opcode2[i]==0x27) { // NOR
2414 if(s1l>=0) emit_not(s1l,tl);
2416 emit_loadreg(rs1[i],tl);
2422 if(s2l>=0) emit_not(s2l,tl);
2424 emit_loadreg(rs2[i],tl);
2428 else emit_movimm(-1,tl);
2437 void imm16_assemble(int i,struct regstat *i_regs)
2439 if (opcode[i]==0x0f) { // LUI
2442 t=get_reg(i_regs->regmap,rt1[i]);
2445 if(!((i_regs->isconst>>t)&1))
2446 emit_movimm(imm[i]<<16,t);
2450 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2453 t=get_reg(i_regs->regmap,rt1[i]);
2454 s=get_reg(i_regs->regmap,rs1[i]);
2459 if(!((i_regs->isconst>>t)&1)) {
2461 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2462 emit_addimm(t,imm[i],t);
2464 if(!((i_regs->wasconst>>s)&1))
2465 emit_addimm(s,imm[i],t);
2467 emit_movimm(constmap[i][s]+imm[i],t);
2473 if(!((i_regs->isconst>>t)&1))
2474 emit_movimm(imm[i],t);
2479 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2481 signed char sh,sl,th,tl;
2482 th=get_reg(i_regs->regmap,rt1[i]|64);
2483 tl=get_reg(i_regs->regmap,rt1[i]);
2484 sh=get_reg(i_regs->regmap,rs1[i]|64);
2485 sl=get_reg(i_regs->regmap,rs1[i]);
2491 emit_addimm64_32(sh,sl,imm[i],th,tl);
2494 emit_addimm(sl,imm[i],tl);
2497 emit_movimm(imm[i],tl);
2498 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2503 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2505 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2506 signed char sh,sl,t;
2507 t=get_reg(i_regs->regmap,rt1[i]);
2508 sh=get_reg(i_regs->regmap,rs1[i]|64);
2509 sl=get_reg(i_regs->regmap,rs1[i]);
2513 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2514 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2515 if(opcode[i]==0x0a) { // SLTI
2517 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2518 emit_slti32(t,imm[i],t);
2520 emit_slti32(sl,imm[i],t);
2525 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2526 emit_sltiu32(t,imm[i],t);
2528 emit_sltiu32(sl,imm[i],t);
2533 if(opcode[i]==0x0a) // SLTI
2534 emit_slti64_32(sh,sl,imm[i],t);
2536 emit_sltiu64_32(sh,sl,imm[i],t);
2539 // SLTI(U) with r0 is just stupid,
2540 // nonetheless examples can be found
2541 if(opcode[i]==0x0a) // SLTI
2542 if(0<imm[i]) emit_movimm(1,t);
2543 else emit_zeroreg(t);
2546 if(imm[i]) emit_movimm(1,t);
2547 else emit_zeroreg(t);
2553 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2555 signed char sh,sl,th,tl;
2556 th=get_reg(i_regs->regmap,rt1[i]|64);
2557 tl=get_reg(i_regs->regmap,rt1[i]);
2558 sh=get_reg(i_regs->regmap,rs1[i]|64);
2559 sl=get_reg(i_regs->regmap,rs1[i]);
2560 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2561 if(opcode[i]==0x0c) //ANDI
2565 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2566 emit_andimm(tl,imm[i],tl);
2568 if(!((i_regs->wasconst>>sl)&1))
2569 emit_andimm(sl,imm[i],tl);
2571 emit_movimm(constmap[i][sl]&imm[i],tl);
2576 if(th>=0) emit_zeroreg(th);
2582 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2586 emit_loadreg(rs1[i]|64,th);
2591 if(opcode[i]==0x0d) //ORI
2593 emit_orimm(tl,imm[i],tl);
2595 if(!((i_regs->wasconst>>sl)&1))
2596 emit_orimm(sl,imm[i],tl);
2598 emit_movimm(constmap[i][sl]|imm[i],tl);
2600 if(opcode[i]==0x0e) //XORI
2602 emit_xorimm(tl,imm[i],tl);
2604 if(!((i_regs->wasconst>>sl)&1))
2605 emit_xorimm(sl,imm[i],tl);
2607 emit_movimm(constmap[i][sl]^imm[i],tl);
2611 emit_movimm(imm[i],tl);
2612 if(th>=0) emit_zeroreg(th);
2620 void shiftimm_assemble(int i,struct regstat *i_regs)
2622 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2626 t=get_reg(i_regs->regmap,rt1[i]);
2627 s=get_reg(i_regs->regmap,rs1[i]);
2636 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2638 if(opcode2[i]==0) // SLL
2640 emit_shlimm(s<0?t:s,imm[i],t);
2642 if(opcode2[i]==2) // SRL
2644 emit_shrimm(s<0?t:s,imm[i],t);
2646 if(opcode2[i]==3) // SRA
2648 emit_sarimm(s<0?t:s,imm[i],t);
2652 if(s>=0 && s!=t) emit_mov(s,t);
2656 //emit_storereg(rt1[i],t); //DEBUG
2659 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2662 signed char sh,sl,th,tl;
2663 th=get_reg(i_regs->regmap,rt1[i]|64);
2664 tl=get_reg(i_regs->regmap,rt1[i]);
2665 sh=get_reg(i_regs->regmap,rs1[i]|64);
2666 sl=get_reg(i_regs->regmap,rs1[i]);
2671 if(th>=0) emit_zeroreg(th);
2678 if(opcode2[i]==0x38) // DSLL
2680 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2681 emit_shlimm(sl,imm[i],tl);
2683 if(opcode2[i]==0x3a) // DSRL
2685 emit_shrdimm(sl,sh,imm[i],tl);
2686 if(th>=0) emit_shrimm(sh,imm[i],th);
2688 if(opcode2[i]==0x3b) // DSRA
2690 emit_shrdimm(sl,sh,imm[i],tl);
2691 if(th>=0) emit_sarimm(sh,imm[i],th);
2695 if(sl!=tl) emit_mov(sl,tl);
2696 if(th>=0&&sh!=th) emit_mov(sh,th);
2702 if(opcode2[i]==0x3c) // DSLL32
2705 signed char sl,tl,th;
2706 tl=get_reg(i_regs->regmap,rt1[i]);
2707 th=get_reg(i_regs->regmap,rt1[i]|64);
2708 sl=get_reg(i_regs->regmap,rs1[i]);
2717 emit_shlimm(th,imm[i]&31,th);
2722 if(opcode2[i]==0x3e) // DSRL32
2725 signed char sh,tl,th;
2726 tl=get_reg(i_regs->regmap,rt1[i]);
2727 th=get_reg(i_regs->regmap,rt1[i]|64);
2728 sh=get_reg(i_regs->regmap,rs1[i]|64);
2732 if(th>=0) emit_zeroreg(th);
2735 emit_shrimm(tl,imm[i]&31,tl);
2740 if(opcode2[i]==0x3f) // DSRA32
2744 tl=get_reg(i_regs->regmap,rt1[i]);
2745 sh=get_reg(i_regs->regmap,rs1[i]|64);
2751 emit_sarimm(tl,imm[i]&31,tl);
2758 #ifndef shift_assemble
2759 void shift_assemble(int i,struct regstat *i_regs)
2761 printf("Need shift_assemble for this architecture.\n");
2766 void load_assemble(int i,struct regstat *i_regs)
2768 int s,th,tl,addr,map=-1;
2771 int memtarget=0,c=0;
2773 th=get_reg(i_regs->regmap,rt1[i]|64);
2774 tl=get_reg(i_regs->regmap,rt1[i]);
2775 s=get_reg(i_regs->regmap,rs1[i]);
2777 for(hr=0;hr<HOST_REGS;hr++) {
2778 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2780 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2782 c=(i_regs->wasconst>>s)&1;
2783 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2784 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2786 //printf("load_assemble: c=%d\n",c);
2787 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2788 // FIXME: Even if the load is a NOP, we should check for pagefaults...
2790 if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2792 // could be FIFO, must perform the read
2794 assem_debug("(forced read)\n");
2795 tl=get_reg(i_regs->regmap,-1);
2799 if(offset||s<0||c) addr=tl;
2801 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2803 //printf("load_assemble: c=%d\n",c);
2804 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2805 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2807 if(th>=0) reglist&=~(1<<th);
2811 map=get_reg(i_regs->regmap,ROREG);
2812 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2814 //#define R29_HACK 1
2816 // Strmnnrmn's speed hack
2817 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2820 emit_cmpimm(addr,RAM_SIZE);
2822 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2823 // Hint to branch predictor that the branch is unlikely to be taken
2825 emit_jno_unlikely(0);
2833 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2834 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2835 map=get_reg(i_regs->regmap,TLREG);
2837 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2838 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2840 int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2841 if (opcode[i]==0x20) { // LB
2844 #ifdef HOST_IMM_ADDR32
2846 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2850 //emit_xorimm(addr,3,tl);
2851 //gen_tlb_addr_r(tl,map);
2852 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2854 #ifdef BIG_ENDIAN_MIPS
2855 if(!c) emit_xorimm(addr,3,tl);
2856 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2860 emit_movsbl_indexed_tlb(x,a,map,tl);
2864 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2867 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2869 if (opcode[i]==0x21) { // LH
2872 #ifdef HOST_IMM_ADDR32
2874 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2879 #ifdef BIG_ENDIAN_MIPS
2880 if(!c) emit_xorimm(addr,2,tl);
2881 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2886 //emit_movswl_indexed_tlb(x,tl,map,tl);
2889 gen_tlb_addr_r(a,map);
2890 emit_movswl_indexed(x,a,tl);
2893 emit_movswl_indexed(x,a,tl);
2895 emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2901 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2904 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2906 if (opcode[i]==0x23) { // LW
2909 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2910 #ifdef HOST_IMM_ADDR32
2912 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2915 emit_readword_indexed_tlb(0,addr,map,tl);
2918 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2921 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2923 if (opcode[i]==0x24) { // LBU
2926 #ifdef HOST_IMM_ADDR32
2928 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2932 //emit_xorimm(addr,3,tl);
2933 //gen_tlb_addr_r(tl,map);
2934 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
2936 #ifdef BIG_ENDIAN_MIPS
2937 if(!c) emit_xorimm(addr,3,tl);
2938 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2942 emit_movzbl_indexed_tlb(x,a,map,tl);
2946 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2949 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2951 if (opcode[i]==0x25) { // LHU
2954 #ifdef HOST_IMM_ADDR32
2956 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2961 #ifdef BIG_ENDIAN_MIPS
2962 if(!c) emit_xorimm(addr,2,tl);
2963 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2968 //emit_movzwl_indexed_tlb(x,tl,map,tl);
2971 gen_tlb_addr_r(a,map);
2972 emit_movzwl_indexed(x,a,tl);
2975 emit_movzwl_indexed(x,a,tl);
2977 emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
2983 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2986 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2988 if (opcode[i]==0x27) { // LWU
2992 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2993 #ifdef HOST_IMM_ADDR32
2995 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2998 emit_readword_indexed_tlb(0,addr,map,tl);
3001 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3004 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3008 if (opcode[i]==0x37) { // LD
3011 //gen_tlb_addr_r(tl,map);
3012 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3013 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3014 #ifdef HOST_IMM_ADDR32
3016 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3019 emit_readdword_indexed_tlb(0,addr,map,th,tl);
3022 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3025 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3028 //emit_storereg(rt1[i],tl); // DEBUG
3029 //if(opcode[i]==0x23)
3030 //if(opcode[i]==0x24)
3031 //if(opcode[i]==0x23||opcode[i]==0x24)
3032 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3036 emit_readword((int)&last_count,ECX);
3038 if(get_reg(i_regs->regmap,CCREG)<0)
3039 emit_loadreg(CCREG,HOST_CCREG);
3040 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3041 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3042 emit_writeword(HOST_CCREG,(int)&Count);
3045 if(get_reg(i_regs->regmap,CCREG)<0)
3046 emit_loadreg(CCREG,0);
3048 emit_mov(HOST_CCREG,0);
3050 emit_addimm(0,2*ccadj[i],0);
3051 emit_writeword(0,(int)&Count);
3053 emit_call((int)memdebug);
3055 restore_regs(0x100f);
3059 #ifndef loadlr_assemble
3060 void loadlr_assemble(int i,struct regstat *i_regs)
3062 printf("Need loadlr_assemble for this architecture.\n");
3067 void store_assemble(int i,struct regstat *i_regs)
3072 int jaddr=0,jaddr2,type;
3073 int memtarget=0,c=0;
3074 int agr=AGEN1+(i&1);
3076 th=get_reg(i_regs->regmap,rs2[i]|64);
3077 tl=get_reg(i_regs->regmap,rs2[i]);
3078 s=get_reg(i_regs->regmap,rs1[i]);
3079 temp=get_reg(i_regs->regmap,agr);
3080 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3083 c=(i_regs->wasconst>>s)&1;
3084 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3085 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3089 for(hr=0;hr<HOST_REGS;hr++) {
3090 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3092 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3093 if(offset||s<0||c) addr=temp;
3098 // Strmnnrmn's speed hack
3100 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3102 emit_cmpimm(addr,RAM_SIZE);
3103 #ifdef DESTRUCTIVE_SHIFT
3104 if(s==addr) emit_mov(s,temp);
3107 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3111 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3112 // Hint to branch predictor that the branch is unlikely to be taken
3114 emit_jno_unlikely(0);
3122 if (opcode[i]==0x28) x=3; // SB
3123 if (opcode[i]==0x29) x=2; // SH
3124 map=get_reg(i_regs->regmap,TLREG);
3126 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3127 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3130 if (opcode[i]==0x28) { // SB
3133 #ifdef BIG_ENDIAN_MIPS
3134 if(!c) emit_xorimm(addr,3,temp);
3135 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3139 //gen_tlb_addr_w(temp,map);
3140 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3141 emit_writebyte_indexed_tlb(tl,x,a,map,a);
3145 if (opcode[i]==0x29) { // SH
3148 #ifdef BIG_ENDIAN_MIPS
3149 if(!c) emit_xorimm(addr,2,temp);
3150 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3155 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3158 gen_tlb_addr_w(a,map);
3159 emit_writehword_indexed(tl,x,a);
3161 emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
3165 if (opcode[i]==0x2B) { // SW
3167 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3168 emit_writeword_indexed_tlb(tl,0,addr,map,temp);
3171 if (opcode[i]==0x3F) { // SD
3175 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3176 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3177 emit_writedword_indexed_tlb(th,tl,0,addr,map,temp);
3180 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3181 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3182 emit_writedword_indexed_tlb(tl,tl,0,addr,map,temp);
3189 #ifdef DESTRUCTIVE_SHIFT
3190 // The x86 shift operation is 'destructive'; it overwrites the
3191 // source register, so we need to make a copy first and use that.
3194 #if defined(HOST_IMM8)
3195 int ir=get_reg(i_regs->regmap,INVCP);
3197 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3199 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3201 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3202 emit_callne(invalidate_addr_reg[addr]);
3206 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3211 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3212 } else if(c&&!memtarget) {
3213 inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3215 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3216 //if(opcode[i]==0x2B || opcode[i]==0x28)
3217 //if(opcode[i]==0x2B || opcode[i]==0x29)
3218 //if(opcode[i]==0x2B)
3219 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3223 emit_readword((int)&last_count,ECX);
3225 if(get_reg(i_regs->regmap,CCREG)<0)
3226 emit_loadreg(CCREG,HOST_CCREG);
3227 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3228 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3229 emit_writeword(HOST_CCREG,(int)&Count);
3232 if(get_reg(i_regs->regmap,CCREG)<0)
3233 emit_loadreg(CCREG,0);
3235 emit_mov(HOST_CCREG,0);
3237 emit_addimm(0,2*ccadj[i],0);
3238 emit_writeword(0,(int)&Count);
3240 emit_call((int)memdebug);
3242 restore_regs(0x100f);
3246 void storelr_assemble(int i,struct regstat *i_regs)
3253 int case1,case2,case3;
3254 int done0,done1,done2;
3256 int agr=AGEN1+(i&1);
3258 th=get_reg(i_regs->regmap,rs2[i]|64);
3259 tl=get_reg(i_regs->regmap,rs2[i]);
3260 s=get_reg(i_regs->regmap,rs1[i]);
3261 temp=get_reg(i_regs->regmap,agr);
3262 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3265 c=(i_regs->isconst>>s)&1;
3266 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3267 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3270 for(hr=0;hr<HOST_REGS;hr++) {
3271 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3276 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3277 if(!offset&&s!=temp) emit_mov(s,temp);
3283 if(!memtarget||!rs1[i]) {
3289 int map=get_reg(i_regs->regmap,ROREG);
3290 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3291 gen_tlb_addr_w(temp,map);
3293 if((u_int)rdram!=0x80000000)
3294 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3297 int map=get_reg(i_regs->regmap,TLREG);
3299 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3300 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3301 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3302 if(!jaddr&&!memtarget) {
3306 gen_tlb_addr_w(temp,map);
3309 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3310 temp2=get_reg(i_regs->regmap,FTEMP);
3311 if(!rs2[i]) temp2=th=tl;
3314 #ifndef BIG_ENDIAN_MIPS
3315 emit_xorimm(temp,3,temp);
3317 emit_testimm(temp,2);
3320 emit_testimm(temp,1);
3324 if (opcode[i]==0x2A) { // SWL
3325 emit_writeword_indexed(tl,0,temp);
3327 if (opcode[i]==0x2E) { // SWR
3328 emit_writebyte_indexed(tl,3,temp);
3330 if (opcode[i]==0x2C) { // SDL
3331 emit_writeword_indexed(th,0,temp);
3332 if(rs2[i]) emit_mov(tl,temp2);
3334 if (opcode[i]==0x2D) { // SDR
3335 emit_writebyte_indexed(tl,3,temp);
3336 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3341 set_jump_target(case1,(int)out);
3342 if (opcode[i]==0x2A) { // SWL
3343 // Write 3 msb into three least significant bytes
3344 if(rs2[i]) emit_rorimm(tl,8,tl);
3345 emit_writehword_indexed(tl,-1,temp);
3346 if(rs2[i]) emit_rorimm(tl,16,tl);
3347 emit_writebyte_indexed(tl,1,temp);
3348 if(rs2[i]) emit_rorimm(tl,8,tl);
3350 if (opcode[i]==0x2E) { // SWR
3351 // Write two lsb into two most significant bytes
3352 emit_writehword_indexed(tl,1,temp);
3354 if (opcode[i]==0x2C) { // SDL
3355 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3356 // Write 3 msb into three least significant bytes
3357 if(rs2[i]) emit_rorimm(th,8,th);
3358 emit_writehword_indexed(th,-1,temp);
3359 if(rs2[i]) emit_rorimm(th,16,th);
3360 emit_writebyte_indexed(th,1,temp);
3361 if(rs2[i]) emit_rorimm(th,8,th);
3363 if (opcode[i]==0x2D) { // SDR
3364 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3365 // Write two lsb into two most significant bytes
3366 emit_writehword_indexed(tl,1,temp);
3371 set_jump_target(case2,(int)out);
3372 emit_testimm(temp,1);
3375 if (opcode[i]==0x2A) { // SWL
3376 // Write two msb into two least significant bytes
3377 if(rs2[i]) emit_rorimm(tl,16,tl);
3378 emit_writehword_indexed(tl,-2,temp);
3379 if(rs2[i]) emit_rorimm(tl,16,tl);
3381 if (opcode[i]==0x2E) { // SWR
3382 // Write 3 lsb into three most significant bytes
3383 emit_writebyte_indexed(tl,-1,temp);
3384 if(rs2[i]) emit_rorimm(tl,8,tl);
3385 emit_writehword_indexed(tl,0,temp);
3386 if(rs2[i]) emit_rorimm(tl,24,tl);
3388 if (opcode[i]==0x2C) { // SDL
3389 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3390 // Write two msb into two least significant bytes
3391 if(rs2[i]) emit_rorimm(th,16,th);
3392 emit_writehword_indexed(th,-2,temp);
3393 if(rs2[i]) emit_rorimm(th,16,th);
3395 if (opcode[i]==0x2D) { // SDR
3396 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3397 // Write 3 lsb into three most significant bytes
3398 emit_writebyte_indexed(tl,-1,temp);
3399 if(rs2[i]) emit_rorimm(tl,8,tl);
3400 emit_writehword_indexed(tl,0,temp);
3401 if(rs2[i]) emit_rorimm(tl,24,tl);
3406 set_jump_target(case3,(int)out);
3407 if (opcode[i]==0x2A) { // SWL
3408 // Write msb into least significant byte
3409 if(rs2[i]) emit_rorimm(tl,24,tl);
3410 emit_writebyte_indexed(tl,-3,temp);
3411 if(rs2[i]) emit_rorimm(tl,8,tl);
3413 if (opcode[i]==0x2E) { // SWR
3414 // Write entire word
3415 emit_writeword_indexed(tl,-3,temp);
3417 if (opcode[i]==0x2C) { // SDL
3418 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3419 // Write msb into least significant byte
3420 if(rs2[i]) emit_rorimm(th,24,th);
3421 emit_writebyte_indexed(th,-3,temp);
3422 if(rs2[i]) emit_rorimm(th,8,th);
3424 if (opcode[i]==0x2D) { // SDR
3425 if(rs2[i]) emit_mov(th,temp2);
3426 // Write entire word
3427 emit_writeword_indexed(tl,-3,temp);
3429 set_jump_target(done0,(int)out);
3430 set_jump_target(done1,(int)out);
3431 set_jump_target(done2,(int)out);
3432 if (opcode[i]==0x2C) { // SDL
3433 emit_testimm(temp,4);
3436 emit_andimm(temp,~3,temp);
3437 emit_writeword_indexed(temp2,4,temp);
3438 set_jump_target(done0,(int)out);
3440 if (opcode[i]==0x2D) { // SDR
3441 emit_testimm(temp,4);
3444 emit_andimm(temp,~3,temp);
3445 emit_writeword_indexed(temp2,-4,temp);
3446 set_jump_target(done0,(int)out);
3449 add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
3452 int map=get_reg(i_regs->regmap,ROREG);
3453 if(map<0) map=HOST_TEMPREG;
3454 gen_orig_addr_w(temp,map);
3456 emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3458 #if defined(HOST_IMM8)
3459 int ir=get_reg(i_regs->regmap,INVCP);
3461 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3463 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3465 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3466 emit_callne(invalidate_addr_reg[temp]);
3470 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3475 //save_regs(0x100f);
3476 emit_readword((int)&last_count,ECX);
3477 if(get_reg(i_regs->regmap,CCREG)<0)
3478 emit_loadreg(CCREG,HOST_CCREG);
3479 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3480 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3481 emit_writeword(HOST_CCREG,(int)&Count);
3482 emit_call((int)memdebug);
3484 //restore_regs(0x100f);
3488 void c1ls_assemble(int i,struct regstat *i_regs)
3490 #ifndef DISABLE_COP1
3496 int jaddr,jaddr2=0,jaddr3,type;
3497 int agr=AGEN1+(i&1);
3499 th=get_reg(i_regs->regmap,FTEMP|64);
3500 tl=get_reg(i_regs->regmap,FTEMP);
3501 s=get_reg(i_regs->regmap,rs1[i]);
3502 temp=get_reg(i_regs->regmap,agr);
3503 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3508 for(hr=0;hr<HOST_REGS;hr++) {
3509 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3511 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3512 if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3514 // Loads use a temporary register which we need to save
3517 if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3521 //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3522 //else c=(i_regs->wasconst>>s)&1;
3523 if(s>=0) c=(i_regs->wasconst>>s)&1;
3524 // Check cop1 unusable
3526 signed char rs=get_reg(i_regs->regmap,CSREG);
3528 emit_testimm(rs,0x20000000);
3531 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3534 if (opcode[i]==0x39) { // SWC1 (get float address)
3535 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],tl);
3537 if (opcode[i]==0x3D) { // SDC1 (get double address)
3538 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],tl);
3540 // Generate address + offset
3543 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3547 map=get_reg(i_regs->regmap,TLREG);
3549 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3550 map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3552 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3553 map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3556 if (opcode[i]==0x39) { // SWC1 (read float)
3557 emit_readword_indexed(0,tl,tl);
3559 if (opcode[i]==0x3D) { // SDC1 (read double)
3560 emit_readword_indexed(4,tl,th);
3561 emit_readword_indexed(0,tl,tl);
3563 if (opcode[i]==0x31) { // LWC1 (get target address)
3564 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],temp);
3566 if (opcode[i]==0x35) { // LDC1 (get target address)
3567 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],temp);
3574 else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
3576 emit_jmp(0); // inline_readstub/inline_writestub? Very rare case
3578 #ifdef DESTRUCTIVE_SHIFT
3579 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3580 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3584 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3585 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3587 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3588 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3591 if (opcode[i]==0x31) { // LWC1
3592 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3593 //gen_tlb_addr_r(ar,map);
3594 //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3595 #ifdef HOST_IMM_ADDR32
3596 if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3599 emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3602 if (opcode[i]==0x35) { // LDC1
3604 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3605 //gen_tlb_addr_r(ar,map);
3606 //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3607 //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3608 #ifdef HOST_IMM_ADDR32
3609 if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3612 emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3615 if (opcode[i]==0x39) { // SWC1
3616 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3617 emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3620 if (opcode[i]==0x3D) { // SDC1
3622 //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3623 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3624 emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3628 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3629 #ifndef DESTRUCTIVE_SHIFT
3630 temp=offset||c||s<0?ar:s;
3632 #if defined(HOST_IMM8)
3633 int ir=get_reg(i_regs->regmap,INVCP);
3635 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3637 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3639 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3640 emit_callne(invalidate_addr_reg[temp]);
3644 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3648 if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3649 if (opcode[i]==0x31) { // LWC1 (write float)
3650 emit_writeword_indexed(tl,0,temp);
3652 if (opcode[i]==0x35) { // LDC1 (write double)
3653 emit_writeword_indexed(th,4,temp);
3654 emit_writeword_indexed(tl,0,temp);
3656 //if(opcode[i]==0x39)
3657 /*if(opcode[i]==0x39||opcode[i]==0x31)
3660 emit_readword((int)&last_count,ECX);
3661 if(get_reg(i_regs->regmap,CCREG)<0)
3662 emit_loadreg(CCREG,HOST_CCREG);
3663 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3664 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3665 emit_writeword(HOST_CCREG,(int)&Count);
3666 emit_call((int)memdebug);
3670 cop1_unusable(i, i_regs);
3674 void c2ls_assemble(int i,struct regstat *i_regs)
3679 int memtarget=0,c=0;
3680 int jaddr,jaddr2=0,jaddr3,type;
3681 int agr=AGEN1+(i&1);
3683 u_int copr=(source[i]>>16)&0x1f;
3684 s=get_reg(i_regs->regmap,rs1[i]);
3685 tl=get_reg(i_regs->regmap,FTEMP);
3691 for(hr=0;hr<HOST_REGS;hr++) {
3692 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3694 if(i_regs->regmap[HOST_CCREG]==CCREG)
3695 reglist&=~(1<<HOST_CCREG);
3698 if (opcode[i]==0x3a) { // SWC2
3699 ar=get_reg(i_regs->regmap,agr);
3700 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3705 if(s>=0) c=(i_regs->wasconst>>s)&1;
3706 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3707 if (!offset&&!c&&s>=0) ar=s;
3710 if (opcode[i]==0x3a) { // SWC2
3711 cop2_get_dreg(copr,tl,HOST_TEMPREG);
3719 emit_jmp(0); // inline_readstub/inline_writestub?
3723 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3727 if (opcode[i]==0x32) { // LWC2
3728 #ifdef HOST_IMM_ADDR32
3729 if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3732 emit_readword_indexed(0,ar,tl);
3734 if (opcode[i]==0x3a) { // SWC2
3735 #ifdef DESTRUCTIVE_SHIFT
3736 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3738 emit_writeword_indexed(tl,0,ar);
3742 add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3743 if (opcode[i]==0x3a) { // SWC2
3744 #if defined(HOST_IMM8)
3745 int ir=get_reg(i_regs->regmap,INVCP);
3747 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3749 emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3751 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3752 emit_callne(invalidate_addr_reg[ar]);
3756 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3759 if (opcode[i]==0x32) { // LWC2
3760 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3764 #ifndef multdiv_assemble
3765 void multdiv_assemble(int i,struct regstat *i_regs)
3767 printf("Need multdiv_assemble for this architecture.\n");
3772 void mov_assemble(int i,struct regstat *i_regs)
3774 //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3775 //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3777 signed char sh,sl,th,tl;
3778 th=get_reg(i_regs->regmap,rt1[i]|64);
3779 tl=get_reg(i_regs->regmap,rt1[i]);
3782 sh=get_reg(i_regs->regmap,rs1[i]|64);
3783 sl=get_reg(i_regs->regmap,rs1[i]);
3784 if(sl>=0) emit_mov(sl,tl);
3785 else emit_loadreg(rs1[i],tl);
3787 if(sh>=0) emit_mov(sh,th);
3788 else emit_loadreg(rs1[i]|64,th);
3794 #ifndef fconv_assemble
3795 void fconv_assemble(int i,struct regstat *i_regs)
3797 printf("Need fconv_assemble for this architecture.\n");
3803 void float_assemble(int i,struct regstat *i_regs)
3805 printf("Need float_assemble for this architecture.\n");
3810 void syscall_assemble(int i,struct regstat *i_regs)
3812 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3813 assert(ccreg==HOST_CCREG);
3814 assert(!is_delayslot);
3815 emit_movimm(start+i*4,EAX); // Get PC
3816 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
3817 emit_jmp((int)jump_syscall_hle); // XXX
3820 void hlecall_assemble(int i,struct regstat *i_regs)
3822 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3823 assert(ccreg==HOST_CCREG);
3824 assert(!is_delayslot);
3825 emit_movimm(start+i*4+4,0); // Get PC
3826 emit_movimm((int)psxHLEt[source[i]&7],1);
3827 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // XXX
3828 emit_jmp((int)jump_hlecall);
3831 void intcall_assemble(int i,struct regstat *i_regs)
3833 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3834 assert(ccreg==HOST_CCREG);
3835 assert(!is_delayslot);
3836 emit_movimm(start+i*4,0); // Get PC
3837 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3838 emit_jmp((int)jump_intcall);
3841 void ds_assemble(int i,struct regstat *i_regs)
3846 alu_assemble(i,i_regs);break;
3848 imm16_assemble(i,i_regs);break;
3850 shift_assemble(i,i_regs);break;
3852 shiftimm_assemble(i,i_regs);break;
3854 load_assemble(i,i_regs);break;
3856 loadlr_assemble(i,i_regs);break;
3858 store_assemble(i,i_regs);break;
3860 storelr_assemble(i,i_regs);break;
3862 cop0_assemble(i,i_regs);break;
3864 cop1_assemble(i,i_regs);break;
3866 c1ls_assemble(i,i_regs);break;
3868 cop2_assemble(i,i_regs);break;
3870 c2ls_assemble(i,i_regs);break;
3872 c2op_assemble(i,i_regs);break;
3874 fconv_assemble(i,i_regs);break;
3876 float_assemble(i,i_regs);break;
3878 fcomp_assemble(i,i_regs);break;
3880 multdiv_assemble(i,i_regs);break;
3882 mov_assemble(i,i_regs);break;
3892 printf("Jump in the delay slot. This is probably a bug.\n");
3897 // Is the branch target a valid internal jump?
3898 int internal_branch(uint64_t i_is32,int addr)
3900 if(addr&1) return 0; // Indirect (register) jump
3901 if(addr>=start && addr<start+slen*4-4)
3903 int t=(addr-start)>>2;
3904 // Delay slots are not valid branch targets
3905 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
3906 // 64 -> 32 bit transition requires a recompile
3907 /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
3909 if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
3910 else printf("optimizable: yes\n");
3912 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
3914 if(requires_32bit[t]&~i_is32) return 0;
3922 #ifndef wb_invalidate
3923 void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
3924 uint64_t u,uint64_t uu)
3927 for(hr=0;hr<HOST_REGS;hr++) {
3928 if(hr!=EXCLUDE_REG) {
3929 if(pre[hr]!=entry[hr]) {
3932 if(get_reg(entry,pre[hr])<0) {
3934 if(!((u>>pre[hr])&1)) {
3935 emit_storereg(pre[hr],hr);
3936 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
3937 emit_sarimm(hr,31,hr);
3938 emit_storereg(pre[hr]|64,hr);
3942 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
3943 emit_storereg(pre[hr],hr);
3952 // Move from one register to another (no writeback)
3953 for(hr=0;hr<HOST_REGS;hr++) {
3954 if(hr!=EXCLUDE_REG) {
3955 if(pre[hr]!=entry[hr]) {
3956 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
3958 if((nr=get_reg(entry,pre[hr]))>=0) {
3968 // Load the specified registers
3969 // This only loads the registers given as arguments because
3970 // we don't want to load things that will be overwritten
3971 void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
3975 for(hr=0;hr<HOST_REGS;hr++) {
3976 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
3977 if(entry[hr]!=regmap[hr]) {
3978 if(regmap[hr]==rs1||regmap[hr]==rs2)
3985 emit_loadreg(regmap[hr],hr);
3992 for(hr=0;hr<HOST_REGS;hr++) {
3993 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
3994 if(entry[hr]!=regmap[hr]) {
3995 if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
3997 assert(regmap[hr]!=64);
3998 if((is32>>(regmap[hr]&63))&1) {
3999 int lr=get_reg(regmap,regmap[hr]-64);
4001 emit_sarimm(lr,31,hr);
4003 emit_loadreg(regmap[hr],hr);
4007 emit_loadreg(regmap[hr],hr);
4015 // Load registers prior to the start of a loop
4016 // so that they are not loaded within the loop
4017 static void loop_preload(signed char pre[],signed char entry[])
4020 for(hr=0;hr<HOST_REGS;hr++) {
4021 if(hr!=EXCLUDE_REG) {
4022 if(pre[hr]!=entry[hr]) {
4024 if(get_reg(pre,entry[hr])<0) {
4025 assem_debug("loop preload:\n");
4026 //printf("loop preload: %d\n",hr);
4030 else if(entry[hr]<TEMPREG)
4032 emit_loadreg(entry[hr],hr);
4034 else if(entry[hr]-64<TEMPREG)
4036 emit_loadreg(entry[hr],hr);
4045 // Generate address for load/store instruction
4046 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
4047 void address_generation(int i,struct regstat *i_regs,signed char entry[])
4049 if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
4051 int agr=AGEN1+(i&1);
4052 int mgr=MGEN1+(i&1);
4053 if(itype[i]==LOAD) {
4054 ra=get_reg(i_regs->regmap,rt1[i]);
4055 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4058 if(itype[i]==LOADLR) {
4059 ra=get_reg(i_regs->regmap,FTEMP);
4061 if(itype[i]==STORE||itype[i]==STORELR) {
4062 ra=get_reg(i_regs->regmap,agr);
4063 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4065 if(itype[i]==C1LS||itype[i]==C2LS) {
4066 if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
4067 ra=get_reg(i_regs->regmap,FTEMP);
4068 else { // SWC1/SDC1/SWC2/SDC2
4069 ra=get_reg(i_regs->regmap,agr);
4070 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4073 int rs=get_reg(i_regs->regmap,rs1[i]);
4074 int rm=get_reg(i_regs->regmap,TLREG);
4077 int c=(i_regs->wasconst>>rs)&1;
4079 // Using r0 as a base address
4081 if(!entry||entry[rm]!=mgr) {
4082 generate_map_const(offset,rm);
4083 } // else did it in the previous cycle
4085 if(!entry||entry[ra]!=agr) {
4086 if (opcode[i]==0x22||opcode[i]==0x26) {
4087 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4088 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4089 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4091 emit_movimm(offset,ra);
4093 } // else did it in the previous cycle
4096 if(!entry||entry[ra]!=rs1[i])
4097 emit_loadreg(rs1[i],ra);
4098 //if(!entry||entry[ra]!=rs1[i])
4099 // printf("poor load scheduling!\n");
4103 if(!entry||entry[rm]!=mgr) {
4104 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
4105 // Stores to memory go thru the mapper to detect self-modifying
4106 // code, loads don't.
4107 if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
4108 (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
4109 generate_map_const(constmap[i][rs]+offset,rm);
4111 if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
4112 generate_map_const(constmap[i][rs]+offset,rm);
4116 if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
4117 if(!entry||entry[ra]!=agr) {
4118 if (opcode[i]==0x22||opcode[i]==0x26) {
4119 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4120 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4121 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4123 #ifdef HOST_IMM_ADDR32
4124 if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4125 (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4127 emit_movimm(constmap[i][rs]+offset,ra);
4129 } // else did it in the previous cycle
4130 } // else load_consts already did it
4132 if(offset&&!c&&rs1[i]) {
4134 emit_addimm(rs,offset,ra);
4136 emit_addimm(ra,offset,ra);
4141 // Preload constants for next instruction
4142 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
4144 #ifndef HOST_IMM_ADDR32
4146 agr=MGEN1+((i+1)&1);
4147 ra=get_reg(i_regs->regmap,agr);
4149 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4150 int offset=imm[i+1];
4151 int c=(regs[i+1].wasconst>>rs)&1;
4153 if(itype[i+1]==STORE||itype[i+1]==STORELR
4154 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
4155 // Stores to memory go thru the mapper to detect self-modifying
4156 // code, loads don't.
4157 if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4158 (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
4159 generate_map_const(constmap[i+1][rs]+offset,ra);
4161 if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4162 generate_map_const(constmap[i+1][rs]+offset,ra);
4165 /*else if(rs1[i]==0) {
4166 generate_map_const(offset,ra);
4171 agr=AGEN1+((i+1)&1);
4172 ra=get_reg(i_regs->regmap,agr);
4174 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4175 int offset=imm[i+1];
4176 int c=(regs[i+1].wasconst>>rs)&1;
4177 if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4178 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4179 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4180 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4181 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4183 #ifdef HOST_IMM_ADDR32
4184 if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4185 (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4187 emit_movimm(constmap[i+1][rs]+offset,ra);
4190 else if(rs1[i+1]==0) {
4191 // Using r0 as a base address
4192 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4193 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4194 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4195 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4197 emit_movimm(offset,ra);
4204 int get_final_value(int hr, int i, int *value)
4206 int reg=regs[i].regmap[hr];
4208 if(regs[i+1].regmap[hr]!=reg) break;
4209 if(!((regs[i+1].isconst>>hr)&1)) break;
4214 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4215 *value=constmap[i][hr];
4219 if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4220 // Load in delay slot, out-of-order execution
4221 if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4223 #ifdef HOST_IMM_ADDR32
4224 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4226 // Precompute load address
4227 *value=constmap[i][hr]+imm[i+2];
4231 if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4233 #ifdef HOST_IMM_ADDR32
4234 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4236 // Precompute load address
4237 *value=constmap[i][hr]+imm[i+1];
4238 //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4243 *value=constmap[i][hr];
4244 //printf("c=%x\n",(int)constmap[i][hr]);
4245 if(i==slen-1) return 1;
4247 return !((unneeded_reg[i+1]>>reg)&1);
4249 return !((unneeded_reg_upper[i+1]>>reg)&1);
4253 // Load registers with known constants
4254 void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4258 for(hr=0;hr<HOST_REGS;hr++) {
4259 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4260 //if(entry[hr]!=regmap[hr]) {
4261 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4262 if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) {
4264 if(get_final_value(hr,i,&value)) {
4269 emit_movimm(value,hr);
4277 for(hr=0;hr<HOST_REGS;hr++) {
4278 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4279 //if(entry[hr]!=regmap[hr]) {
4280 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4281 if(((regs[i].isconst>>hr)&1)&®map[hr]>64) {
4282 if((is32>>(regmap[hr]&63))&1) {
4283 int lr=get_reg(regmap,regmap[hr]-64);
4285 emit_sarimm(lr,31,hr);
4290 if(get_final_value(hr,i,&value)) {
4295 emit_movimm(value,hr);
4304 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4308 for(hr=0;hr<HOST_REGS;hr++) {
4309 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4310 if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) {
4311 int value=constmap[i][hr];
4316 emit_movimm(value,hr);
4322 for(hr=0;hr<HOST_REGS;hr++) {
4323 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4324 if(((regs[i].isconst>>hr)&1)&®map[hr]>64) {
4325 if((is32>>(regmap[hr]&63))&1) {
4326 int lr=get_reg(regmap,regmap[hr]-64);
4328 emit_sarimm(lr,31,hr);
4332 int value=constmap[i][hr];
4337 emit_movimm(value,hr);
4345 // Write out all dirty registers (except cycle count)
4346 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4349 for(hr=0;hr<HOST_REGS;hr++) {
4350 if(hr!=EXCLUDE_REG) {
4351 if(i_regmap[hr]>0) {
4352 if(i_regmap[hr]!=CCREG) {
4353 if((i_dirty>>hr)&1) {
4354 if(i_regmap[hr]<64) {
4355 emit_storereg(i_regmap[hr],hr);
4357 if( ((i_is32>>i_regmap[hr])&1) ) {
4358 #ifdef DESTRUCTIVE_WRITEBACK
4359 emit_sarimm(hr,31,hr);
4360 emit_storereg(i_regmap[hr]|64,hr);
4362 emit_sarimm(hr,31,HOST_TEMPREG);
4363 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4368 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4369 emit_storereg(i_regmap[hr],hr);
4378 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4379 // This writes the registers not written by store_regs_bt
4380 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4383 int t=(addr-start)>>2;
4384 for(hr=0;hr<HOST_REGS;hr++) {
4385 if(hr!=EXCLUDE_REG) {
4386 if(i_regmap[hr]>0) {
4387 if(i_regmap[hr]!=CCREG) {
4388 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4389 if((i_dirty>>hr)&1) {
4390 if(i_regmap[hr]<64) {
4391 emit_storereg(i_regmap[hr],hr);
4393 if( ((i_is32>>i_regmap[hr])&1) ) {
4394 #ifdef DESTRUCTIVE_WRITEBACK
4395 emit_sarimm(hr,31,hr);
4396 emit_storereg(i_regmap[hr]|64,hr);
4398 emit_sarimm(hr,31,HOST_TEMPREG);
4399 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4404 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4405 emit_storereg(i_regmap[hr],hr);
4416 // Load all registers (except cycle count)
4417 void load_all_regs(signed char i_regmap[])
4420 for(hr=0;hr<HOST_REGS;hr++) {
4421 if(hr!=EXCLUDE_REG) {
4422 if(i_regmap[hr]==0) {
4426 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG)
4428 emit_loadreg(i_regmap[hr],hr);
4434 // Load all current registers also needed by next instruction
4435 void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4438 for(hr=0;hr<HOST_REGS;hr++) {
4439 if(hr!=EXCLUDE_REG) {
4440 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4441 if(i_regmap[hr]==0) {
4445 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG)
4447 emit_loadreg(i_regmap[hr],hr);
4454 // Load all regs, storing cycle count if necessary
4455 void load_regs_entry(int t)
4458 if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER,HOST_CCREG);
4459 else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t]*CLOCK_DIVIDER,HOST_CCREG);
4460 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4461 emit_storereg(CCREG,HOST_CCREG);
4464 for(hr=0;hr<HOST_REGS;hr++) {
4465 if(regs[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<64) {
4466 if(regs[t].regmap_entry[hr]==0) {
4469 else if(regs[t].regmap_entry[hr]!=CCREG)
4471 emit_loadreg(regs[t].regmap_entry[hr],hr);
4476 for(hr=0;hr<HOST_REGS;hr++) {
4477 if(regs[t].regmap_entry[hr]>=64) {
4478 assert(regs[t].regmap_entry[hr]!=64);
4479 if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4480 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4482 emit_loadreg(regs[t].regmap_entry[hr],hr);
4486 emit_sarimm(lr,31,hr);
4491 emit_loadreg(regs[t].regmap_entry[hr],hr);
4497 // Store dirty registers prior to branch
4498 void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4500 if(internal_branch(i_is32,addr))
4502 int t=(addr-start)>>2;
4504 for(hr=0;hr<HOST_REGS;hr++) {
4505 if(hr!=EXCLUDE_REG) {
4506 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4507 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4508 if((i_dirty>>hr)&1) {
4509 if(i_regmap[hr]<64) {
4510 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4511 emit_storereg(i_regmap[hr],hr);
4512 if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4513 #ifdef DESTRUCTIVE_WRITEBACK
4514 emit_sarimm(hr,31,hr);
4515 emit_storereg(i_regmap[hr]|64,hr);
4517 emit_sarimm(hr,31,HOST_TEMPREG);
4518 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4523 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4524 emit_storereg(i_regmap[hr],hr);
4535 // Branch out of this block, write out all dirty regs
4536 wb_dirtys(i_regmap,i_is32,i_dirty);
4540 // Load all needed registers for branch target
4541 void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4543 //if(addr>=start && addr<(start+slen*4))
4544 if(internal_branch(i_is32,addr))
4546 int t=(addr-start)>>2;
4548 // Store the cycle count before loading something else
4549 if(i_regmap[HOST_CCREG]!=CCREG) {
4550 assert(i_regmap[HOST_CCREG]==-1);
4552 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4553 emit_storereg(CCREG,HOST_CCREG);
4556 for(hr=0;hr<HOST_REGS;hr++) {
4557 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<64) {
4558 #ifdef DESTRUCTIVE_WRITEBACK
4559 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4561 if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4563 if(regs[t].regmap_entry[hr]==0) {
4566 else if(regs[t].regmap_entry[hr]!=CCREG)
4568 emit_loadreg(regs[t].regmap_entry[hr],hr);
4574 for(hr=0;hr<HOST_REGS;hr++) {
4575 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=64) {
4576 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4577 assert(regs[t].regmap_entry[hr]!=64);
4578 if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4579 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4581 emit_loadreg(regs[t].regmap_entry[hr],hr);
4585 emit_sarimm(lr,31,hr);
4590 emit_loadreg(regs[t].regmap_entry[hr],hr);
4593 else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4594 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4596 emit_sarimm(lr,31,hr);
4603 int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4605 if(addr>=start && addr<start+slen*4-4)
4607 int t=(addr-start)>>2;
4609 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4610 for(hr=0;hr<HOST_REGS;hr++)
4614 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4616 if(regs[t].regmap_entry[hr]!=-1)
4625 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4630 if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4635 else // Same register but is it 32-bit or dirty?
4638 if(!((regs[t].dirty>>hr)&1))
4642 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4644 //printf("%x: dirty no match\n",addr);
4649 if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4651 //printf("%x: is32 no match\n",addr);
4657 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4659 if(requires_32bit[t]&~i_is32) return 0;
4661 // Delay slots are not valid branch targets
4662 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4663 // Delay slots require additional processing, so do not match
4664 if(is_ds[t]) return 0;
4669 for(hr=0;hr<HOST_REGS;hr++)
4675 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4689 // Used when a branch jumps into the delay slot of another branch
4690 void ds_assemble_entry(int i)
4692 int t=(ba[i]-start)>>2;
4693 if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4694 assem_debug("Assemble delay slot at %x\n",ba[i]);
4695 assem_debug("<->\n");
4696 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&®s[t].regmap[HOST_CCREG]!=CCREG)
4697 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4698 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4699 address_generation(t,®s[t],regs[t].regmap_entry);
4700 if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
4701 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4706 alu_assemble(t,®s[t]);break;
4708 imm16_assemble(t,®s[t]);break;
4710 shift_assemble(t,®s[t]);break;
4712 shiftimm_assemble(t,®s[t]);break;
4714 load_assemble(t,®s[t]);break;
4716 loadlr_assemble(t,®s[t]);break;
4718 store_assemble(t,®s[t]);break;
4720 storelr_assemble(t,®s[t]);break;
4722 cop0_assemble(t,®s[t]);break;
4724 cop1_assemble(t,®s[t]);break;
4726 c1ls_assemble(t,®s[t]);break;
4728 cop2_assemble(t,®s[t]);break;
4730 c2ls_assemble(t,®s[t]);break;
4732 c2op_assemble(t,®s[t]);break;
4734 fconv_assemble(t,®s[t]);break;
4736 float_assemble(t,®s[t]);break;
4738 fcomp_assemble(t,®s[t]);break;
4740 multdiv_assemble(t,®s[t]);break;
4742 mov_assemble(t,®s[t]);break;
4752 printf("Jump in the delay slot. This is probably a bug.\n");
4754 store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4755 load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4756 if(internal_branch(regs[t].is32,ba[i]+4))
4757 assem_debug("branch: internal\n");
4759 assem_debug("branch: external\n");
4760 assert(internal_branch(regs[t].is32,ba[i]+4));
4761 add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4765 void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4774 //if(ba[i]>=start && ba[i]<(start+slen*4))
4775 if(internal_branch(branch_regs[i].is32,ba[i]))
4777 int t=(ba[i]-start)>>2;
4778 if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4786 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4788 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4790 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4791 emit_andimm(HOST_CCREG,3,HOST_CCREG);
4795 else if(*adj==0||invert) {
4796 emit_addimm_and_set_flags(CLOCK_DIVIDER*(count+2),HOST_CCREG);
4802 emit_cmpimm(HOST_CCREG,-2*(count+2));
4806 add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4809 void do_ccstub(int n)
4812 assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
4813 set_jump_target(stubs[n][1],(int)out);
4815 if(stubs[n][6]==NULLDS) {
4816 // Delay slot instruction is nullified ("likely" branch)
4817 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4819 else if(stubs[n][6]!=TAKEN) {
4820 wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4823 if(internal_branch(branch_regs[i].is32,ba[i]))
4824 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4828 // Save PC as return address
4829 emit_movimm(stubs[n][5],EAX);
4830 emit_writeword(EAX,(int)&pcaddr);
4834 // Return address depends on which way the branch goes
4835 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
4837 int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4838 int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4839 int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4840 int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4850 if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
4854 #ifdef DESTRUCTIVE_WRITEBACK
4856 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
4857 emit_loadreg(rs1[i],s1l);
4860 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
4861 emit_loadreg(rs2[i],s1l);
4864 if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
4865 emit_loadreg(rs2[i],s2l);
4868 int addr,alt,ntaddr;
4871 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4872 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4873 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4881 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4882 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4883 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4889 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
4893 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4894 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4895 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4901 assert(hr<HOST_REGS);
4903 if((opcode[i]&0x2f)==4) // BEQ
4905 #ifdef HAVE_CMOV_IMM
4907 if(s2l>=0) emit_cmp(s1l,s2l);
4908 else emit_test(s1l,s1l);
4909 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
4914 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4916 if(s2h>=0) emit_cmp(s1h,s2h);
4917 else emit_test(s1h,s1h);
4918 emit_cmovne_reg(alt,addr);
4920 if(s2l>=0) emit_cmp(s1l,s2l);
4921 else emit_test(s1l,s1l);
4922 emit_cmovne_reg(alt,addr);
4925 if((opcode[i]&0x2f)==5) // BNE
4927 #ifdef HAVE_CMOV_IMM
4929 if(s2l>=0) emit_cmp(s1l,s2l);
4930 else emit_test(s1l,s1l);
4931 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
4936 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
4938 if(s2h>=0) emit_cmp(s1h,s2h);
4939 else emit_test(s1h,s1h);
4940 emit_cmovne_reg(alt,addr);
4942 if(s2l>=0) emit_cmp(s1l,s2l);
4943 else emit_test(s1l,s1l);
4944 emit_cmovne_reg(alt,addr);
4947 if((opcode[i]&0x2f)==6) // BLEZ
4949 //emit_movimm(ba[i],alt);
4950 //emit_movimm(start+i*4+8,addr);
4951 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4953 if(s1h>=0) emit_mov(addr,ntaddr);
4954 emit_cmovl_reg(alt,addr);
4957 emit_cmovne_reg(ntaddr,addr);
4958 emit_cmovs_reg(alt,addr);
4961 if((opcode[i]&0x2f)==7) // BGTZ
4963 //emit_movimm(ba[i],addr);
4964 //emit_movimm(start+i*4+8,ntaddr);
4965 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
4967 if(s1h>=0) emit_mov(addr,alt);
4968 emit_cmovl_reg(ntaddr,addr);
4971 emit_cmovne_reg(alt,addr);
4972 emit_cmovs_reg(ntaddr,addr);
4975 if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
4977 //emit_movimm(ba[i],alt);
4978 //emit_movimm(start+i*4+8,addr);
4979 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4980 if(s1h>=0) emit_test(s1h,s1h);
4981 else emit_test(s1l,s1l);
4982 emit_cmovs_reg(alt,addr);
4984 if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
4986 //emit_movimm(ba[i],addr);
4987 //emit_movimm(start+i*4+8,alt);
4988 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4989 if(s1h>=0) emit_test(s1h,s1h);
4990 else emit_test(s1l,s1l);
4991 emit_cmovs_reg(alt,addr);
4993 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
4994 if(source[i]&0x10000) // BC1T
4996 //emit_movimm(ba[i],alt);
4997 //emit_movimm(start+i*4+8,addr);
4998 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4999 emit_testimm(s1l,0x800000);
5000 emit_cmovne_reg(alt,addr);
5004 //emit_movimm(ba[i],addr);
5005 //emit_movimm(start+i*4+8,alt);
5006 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5007 emit_testimm(s1l,0x800000);
5008 emit_cmovne_reg(alt,addr);
5011 emit_writeword(addr,(int)&pcaddr);
5016 int r=get_reg(branch_regs[i].regmap,rs1[i]);
5017 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5018 r=get_reg(branch_regs[i].regmap,RTEMP);
5020 emit_writeword(r,(int)&pcaddr);
5022 else {printf("Unknown branch type in do_ccstub\n");exit(1);}
5024 // Update cycle count
5025 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5026 if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
5027 emit_call((int)cc_interrupt);
5028 if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
5029 if(stubs[n][6]==TAKEN) {
5030 if(internal_branch(branch_regs[i].is32,ba[i]))
5031 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
5032 else if(itype[i]==RJUMP) {
5033 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5034 emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5036 emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
5038 }else if(stubs[n][6]==NOTTAKEN) {
5039 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5040 else load_all_regs(branch_regs[i].regmap);
5041 }else if(stubs[n][6]==NULLDS) {
5042 // Delay slot instruction is nullified ("likely" branch)
5043 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5044 else load_all_regs(regs[i].regmap);
5046 load_all_regs(branch_regs[i].regmap);
5048 emit_jmp(stubs[n][2]); // return address
5050 /* This works but uses a lot of memory...
5051 emit_readword((int)&last_count,ECX);
5052 emit_add(HOST_CCREG,ECX,EAX);
5053 emit_writeword(EAX,(int)&Count);
5054 emit_call((int)gen_interupt);
5055 emit_readword((int)&Count,HOST_CCREG);
5056 emit_readword((int)&next_interupt,EAX);
5057 emit_readword((int)&pending_exception,EBX);
5058 emit_writeword(EAX,(int)&last_count);
5059 emit_sub(HOST_CCREG,EAX,HOST_CCREG);
5061 int jne_instr=(int)out;
5063 if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
5064 load_all_regs(branch_regs[i].regmap);
5065 emit_jmp(stubs[n][2]); // return address
5066 set_jump_target(jne_instr,(int)out);
5067 emit_readword((int)&pcaddr,EAX);
5068 // Call get_addr_ht instead of doing the hash table here.
5069 // This code is executed infrequently and takes up a lot of space
5070 // so smaller is better.
5071 emit_storereg(CCREG,HOST_CCREG);
5073 emit_call((int)get_addr_ht);
5074 emit_loadreg(CCREG,HOST_CCREG);
5075 emit_addimm(ESP,4,ESP);
5079 add_to_linker(int addr,int target,int ext)
5081 link_addr[linkcount][0]=addr;
5082 link_addr[linkcount][1]=target;
5083 link_addr[linkcount][2]=ext;
5087 void ujump_assemble(int i,struct regstat *i_regs)
5089 signed char *i_regmap=i_regs->regmap;
5090 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5091 address_generation(i+1,i_regs,regs[i].regmap_entry);
5093 int temp=get_reg(branch_regs[i].regmap,PTEMP);
5094 if(rt1[i]==31&&temp>=0)
5096 int return_address=start+i*4+8;
5097 if(get_reg(branch_regs[i].regmap,31)>0)
5098 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5101 ds_assemble(i+1,i_regs);
5102 uint64_t bc_unneeded=branch_regs[i].u;
5103 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5104 bc_unneeded|=1|(1LL<<rt1[i]);
5105 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5106 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5107 bc_unneeded,bc_unneeded_upper);
5108 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5111 unsigned int return_address;
5112 assert(rt1[i+1]!=31);
5113 assert(rt2[i+1]!=31);
5114 rt=get_reg(branch_regs[i].regmap,31);
5115 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5117 return_address=start+i*4+8;
5120 if(internal_branch(branch_regs[i].is32,return_address)) {
5122 if(temp==EXCLUDE_REG||temp>=HOST_REGS||
5123 branch_regs[i].regmap[temp]>=0)
5125 temp=get_reg(branch_regs[i].regmap,-1);
5128 if(temp<0) temp=HOST_TEMPREG;
5130 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5131 else emit_movimm(return_address,rt);
5139 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5142 emit_movimm(return_address,rt); // PC into link register
5144 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5150 cc=get_reg(branch_regs[i].regmap,CCREG);
5151 assert(cc==HOST_CCREG);
5152 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5154 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5156 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5157 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5158 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5159 if(internal_branch(branch_regs[i].is32,ba[i]))
5160 assem_debug("branch: internal\n");
5162 assem_debug("branch: external\n");
5163 if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5164 ds_assemble_entry(i);
5167 add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5172 void rjump_assemble(int i,struct regstat *i_regs)
5174 signed char *i_regmap=i_regs->regmap;
5177 rs=get_reg(branch_regs[i].regmap,rs1[i]);
5179 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5180 // Delay slot abuse, make a copy of the branch address register
5181 temp=get_reg(branch_regs[i].regmap,RTEMP);
5183 assert(regs[i].regmap[temp]==RTEMP);
5187 address_generation(i+1,i_regs,regs[i].regmap_entry);
5191 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5192 int return_address=start+i*4+8;
5193 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5199 int rh=get_reg(regs[i].regmap,RHASH);
5200 if(rh>=0) do_preload_rhash(rh);
5203 ds_assemble(i+1,i_regs);
5204 uint64_t bc_unneeded=branch_regs[i].u;
5205 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5206 bc_unneeded|=1|(1LL<<rt1[i]);
5207 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5208 bc_unneeded&=~(1LL<<rs1[i]);
5209 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5210 bc_unneeded,bc_unneeded_upper);
5211 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5213 int rt,return_address;
5214 assert(rt1[i+1]!=rt1[i]);
5215 assert(rt2[i+1]!=rt1[i]);
5216 rt=get_reg(branch_regs[i].regmap,rt1[i]);
5217 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5219 return_address=start+i*4+8;
5223 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5226 emit_movimm(return_address,rt); // PC into link register
5228 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5231 cc=get_reg(branch_regs[i].regmap,CCREG);
5232 assert(cc==HOST_CCREG);
5234 int rh=get_reg(branch_regs[i].regmap,RHASH);
5235 int ht=get_reg(branch_regs[i].regmap,RHTBL);
5237 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5238 do_preload_rhtbl(ht);
5242 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5243 #ifdef DESTRUCTIVE_WRITEBACK
5244 if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5245 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5246 emit_loadreg(rs1[i],rs);
5251 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5255 do_miniht_load(ht,rh);
5258 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5259 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5261 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5262 add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5264 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5267 do_miniht_jump(rs,rh,ht);
5272 //if(rs!=EAX) emit_mov(rs,EAX);
5273 //emit_jmp((int)jump_vaddr_eax);
5274 emit_jmp(jump_vaddr_reg[rs]);
5279 emit_shrimm(rs,16,rs);
5280 emit_xor(temp,rs,rs);
5281 emit_movzwl_reg(rs,rs);
5282 emit_shlimm(rs,4,rs);
5283 emit_cmpmem_indexed((int)hash_table,rs,temp);
5284 emit_jne((int)out+14);
5285 emit_readword_indexed((int)hash_table+4,rs,rs);
5287 emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5288 emit_addimm_no_flags(8,rs);
5289 emit_jeq((int)out-17);
5290 // No hit on hash table, call compiler
5293 #ifdef DEBUG_CYCLE_COUNT
5294 emit_readword((int)&last_count,ECX);
5295 emit_add(HOST_CCREG,ECX,HOST_CCREG);
5296 emit_readword((int)&next_interupt,ECX);
5297 emit_writeword(HOST_CCREG,(int)&Count);
5298 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5299 emit_writeword(ECX,(int)&last_count);
5302 emit_storereg(CCREG,HOST_CCREG);
5303 emit_call((int)get_addr);
5304 emit_loadreg(CCREG,HOST_CCREG);
5305 emit_addimm(ESP,4,ESP);
5307 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5308 if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5312 void cjump_assemble(int i,struct regstat *i_regs)
5314 signed char *i_regmap=i_regs->regmap;
5317 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5318 assem_debug("match=%d\n",match);
5319 int s1h,s1l,s2h,s2l;
5320 int prev_cop1_usable=cop1_usable;
5321 int unconditional=0,nop=0;
5324 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5325 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5326 if(!match) invert=1;
5327 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5328 if(i>(ba[i]-start)>>2) invert=1;
5332 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5333 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5334 s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5335 s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5338 s1l=get_reg(i_regmap,rs1[i]);
5339 s1h=get_reg(i_regmap,rs1[i]|64);
5340 s2l=get_reg(i_regmap,rs2[i]);
5341 s2h=get_reg(i_regmap,rs2[i]|64);
5343 if(rs1[i]==0&&rs2[i]==0)
5345 if(opcode[i]&1) nop=1;
5346 else unconditional=1;
5347 //assert(opcode[i]!=5);
5348 //assert(opcode[i]!=7);
5349 //assert(opcode[i]!=0x15);
5350 //assert(opcode[i]!=0x17);
5356 only32=(regs[i].was32>>rs2[i])&1;
5361 only32=(regs[i].was32>>rs1[i])&1;
5364 only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5368 // Out of order execution (delay slot first)
5370 address_generation(i+1,i_regs,regs[i].regmap_entry);
5371 ds_assemble(i+1,i_regs);
5373 uint64_t bc_unneeded=branch_regs[i].u;
5374 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5375 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5376 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5378 bc_unneeded_upper|=1;
5379 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5380 bc_unneeded,bc_unneeded_upper);
5381 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5382 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5383 cc=get_reg(branch_regs[i].regmap,CCREG);
5384 assert(cc==HOST_CCREG);
5386 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5387 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5388 //assem_debug("cycle count (adj)\n");
5390 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5391 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5392 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5393 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5395 assem_debug("branch: internal\n");
5397 assem_debug("branch: external\n");
5398 if(internal&&is_ds[(ba[i]-start)>>2]) {
5399 ds_assemble_entry(i);
5402 add_to_linker((int)out,ba[i],internal);
5405 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5406 if(((u_int)out)&7) emit_addnop(0);
5411 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5414 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5417 int taken=0,nottaken=0,nottaken1=0;
5418 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5419 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5423 if(opcode[i]==4) // BEQ
5425 if(s2h>=0) emit_cmp(s1h,s2h);
5426 else emit_test(s1h,s1h);
5430 if(opcode[i]==5) // BNE
5432 if(s2h>=0) emit_cmp(s1h,s2h);
5433 else emit_test(s1h,s1h);
5434 if(invert) taken=(int)out;
5435 else add_to_linker((int)out,ba[i],internal);
5438 if(opcode[i]==6) // BLEZ
5441 if(invert) taken=(int)out;
5442 else add_to_linker((int)out,ba[i],internal);
5447 if(opcode[i]==7) // BGTZ
5452 if(invert) taken=(int)out;
5453 else add_to_linker((int)out,ba[i],internal);
5458 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5460 if(opcode[i]==4) // BEQ
5462 if(s2l>=0) emit_cmp(s1l,s2l);
5463 else emit_test(s1l,s1l);
5468 add_to_linker((int)out,ba[i],internal);
5472 if(opcode[i]==5) // BNE
5474 if(s2l>=0) emit_cmp(s1l,s2l);
5475 else emit_test(s1l,s1l);
5480 add_to_linker((int)out,ba[i],internal);
5484 if(opcode[i]==6) // BLEZ
5491 add_to_linker((int)out,ba[i],internal);
5495 if(opcode[i]==7) // BGTZ
5502 add_to_linker((int)out,ba[i],internal);
5507 if(taken) set_jump_target(taken,(int)out);
5508 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5509 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5511 emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5512 add_to_linker((int)out,ba[i],internal);
5515 add_to_linker((int)out,ba[i],internal*2);
5521 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5522 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5523 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5525 assem_debug("branch: internal\n");
5527 assem_debug("branch: external\n");
5528 if(internal&&is_ds[(ba[i]-start)>>2]) {
5529 ds_assemble_entry(i);
5532 add_to_linker((int)out,ba[i],internal);
5536 set_jump_target(nottaken,(int)out);
5539 if(nottaken1) set_jump_target(nottaken1,(int)out);
5541 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5543 } // (!unconditional)
5547 // In-order execution (branch first)
5548 //if(likely[i]) printf("IOL\n");
5551 int taken=0,nottaken=0,nottaken1=0;
5552 if(!unconditional&&!nop) {
5556 if((opcode[i]&0x2f)==4) // BEQ
5558 if(s2h>=0) emit_cmp(s1h,s2h);
5559 else emit_test(s1h,s1h);
5563 if((opcode[i]&0x2f)==5) // BNE
5565 if(s2h>=0) emit_cmp(s1h,s2h);
5566 else emit_test(s1h,s1h);
5570 if((opcode[i]&0x2f)==6) // BLEZ
5578 if((opcode[i]&0x2f)==7) // BGTZ
5588 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5590 if((opcode[i]&0x2f)==4) // BEQ
5592 if(s2l>=0) emit_cmp(s1l,s2l);
5593 else emit_test(s1l,s1l);
5597 if((opcode[i]&0x2f)==5) // BNE
5599 if(s2l>=0) emit_cmp(s1l,s2l);
5600 else emit_test(s1l,s1l);
5604 if((opcode[i]&0x2f)==6) // BLEZ
5610 if((opcode[i]&0x2f)==7) // BGTZ
5616 } // if(!unconditional)
5618 uint64_t ds_unneeded=branch_regs[i].u;
5619 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5620 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5621 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5622 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5624 ds_unneeded_upper|=1;
5627 if(taken) set_jump_target(taken,(int)out);
5628 assem_debug("1:\n");
5629 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5630 ds_unneeded,ds_unneeded_upper);
5632 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5633 address_generation(i+1,&branch_regs[i],0);
5634 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5635 ds_assemble(i+1,&branch_regs[i]);
5636 cc=get_reg(branch_regs[i].regmap,CCREG);
5638 emit_loadreg(CCREG,cc=HOST_CCREG);
5639 // CHECK: Is the following instruction (fall thru) allocated ok?
5641 assert(cc==HOST_CCREG);
5642 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5643 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5644 assem_debug("cycle count (adj)\n");
5645 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5646 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5648 assem_debug("branch: internal\n");
5650 assem_debug("branch: external\n");
5651 if(internal&&is_ds[(ba[i]-start)>>2]) {
5652 ds_assemble_entry(i);
5655 add_to_linker((int)out,ba[i],internal);
5660 cop1_usable=prev_cop1_usable;
5661 if(!unconditional) {
5662 if(nottaken1) set_jump_target(nottaken1,(int)out);
5663 set_jump_target(nottaken,(int)out);
5664 assem_debug("2:\n");
5666 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5667 ds_unneeded,ds_unneeded_upper);
5668 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5669 address_generation(i+1,&branch_regs[i],0);
5670 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5671 ds_assemble(i+1,&branch_regs[i]);
5673 cc=get_reg(branch_regs[i].regmap,CCREG);
5674 if(cc==-1&&!likely[i]) {
5675 // Cycle count isn't in a register, temporarily load it then write it out
5676 emit_loadreg(CCREG,HOST_CCREG);
5677 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5680 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5681 emit_storereg(CCREG,HOST_CCREG);
5684 cc=get_reg(i_regmap,CCREG);
5685 assert(cc==HOST_CCREG);
5686 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5689 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5695 void sjump_assemble(int i,struct regstat *i_regs)
5697 signed char *i_regmap=i_regs->regmap;
5700 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5701 assem_debug("smatch=%d\n",match);
5703 int prev_cop1_usable=cop1_usable;
5704 int unconditional=0,nevertaken=0;
5707 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5708 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5709 if(!match) invert=1;
5710 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5711 if(i>(ba[i]-start)>>2) invert=1;
5714 //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
5715 //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
5718 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5719 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5722 s1l=get_reg(i_regmap,rs1[i]);
5723 s1h=get_reg(i_regmap,rs1[i]|64);
5727 if(opcode2[i]&1) unconditional=1;
5729 // These are never taken (r0 is never less than zero)
5730 //assert(opcode2[i]!=0);
5731 //assert(opcode2[i]!=2);
5732 //assert(opcode2[i]!=0x10);
5733 //assert(opcode2[i]!=0x12);
5736 only32=(regs[i].was32>>rs1[i])&1;
5740 // Out of order execution (delay slot first)
5742 address_generation(i+1,i_regs,regs[i].regmap_entry);
5743 ds_assemble(i+1,i_regs);
5745 uint64_t bc_unneeded=branch_regs[i].u;
5746 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5747 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5748 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5750 bc_unneeded_upper|=1;
5751 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5752 bc_unneeded,bc_unneeded_upper);
5753 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5754 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5756 int rt,return_address;
5757 rt=get_reg(branch_regs[i].regmap,31);
5758 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5760 // Save the PC even if the branch is not taken
5761 return_address=start+i*4+8;
5762 emit_movimm(return_address,rt); // PC into link register
5764 if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5768 cc=get_reg(branch_regs[i].regmap,CCREG);
5769 assert(cc==HOST_CCREG);
5771 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5772 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5773 assem_debug("cycle count (adj)\n");
5775 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5776 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5777 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5778 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5780 assem_debug("branch: internal\n");
5782 assem_debug("branch: external\n");
5783 if(internal&&is_ds[(ba[i]-start)>>2]) {
5784 ds_assemble_entry(i);
5787 add_to_linker((int)out,ba[i],internal);
5790 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5791 if(((u_int)out)&7) emit_addnop(0);
5795 else if(nevertaken) {
5796 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5799 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5803 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5804 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5808 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5815 add_to_linker((int)out,ba[i],internal);
5819 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5826 add_to_linker((int)out,ba[i],internal);
5834 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5841 add_to_linker((int)out,ba[i],internal);
5845 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5852 add_to_linker((int)out,ba[i],internal);
5859 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5860 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5862 emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5863 add_to_linker((int)out,ba[i],internal);
5866 add_to_linker((int)out,ba[i],internal*2);
5872 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5873 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5874 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5876 assem_debug("branch: internal\n");
5878 assem_debug("branch: external\n");
5879 if(internal&&is_ds[(ba[i]-start)>>2]) {
5880 ds_assemble_entry(i);
5883 add_to_linker((int)out,ba[i],internal);
5887 set_jump_target(nottaken,(int)out);
5891 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5893 } // (!unconditional)
5897 // In-order execution (branch first)
5901 int rt,return_address;
5902 rt=get_reg(branch_regs[i].regmap,31);
5904 // Save the PC even if the branch is not taken
5905 return_address=start+i*4+8;
5906 emit_movimm(return_address,rt); // PC into link register
5908 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5912 if(!unconditional) {
5913 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5917 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
5923 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
5933 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
5939 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
5946 } // if(!unconditional)
5948 uint64_t ds_unneeded=branch_regs[i].u;
5949 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5950 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5951 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5952 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5954 ds_unneeded_upper|=1;
5957 //assem_debug("1:\n");
5958 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5959 ds_unneeded,ds_unneeded_upper);
5961 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5962 address_generation(i+1,&branch_regs[i],0);
5963 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5964 ds_assemble(i+1,&branch_regs[i]);
5965 cc=get_reg(branch_regs[i].regmap,CCREG);
5967 emit_loadreg(CCREG,cc=HOST_CCREG);
5968 // CHECK: Is the following instruction (fall thru) allocated ok?
5970 assert(cc==HOST_CCREG);
5971 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5972 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5973 assem_debug("cycle count (adj)\n");
5974 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5975 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5977 assem_debug("branch: internal\n");
5979 assem_debug("branch: external\n");
5980 if(internal&&is_ds[(ba[i]-start)>>2]) {
5981 ds_assemble_entry(i);
5984 add_to_linker((int)out,ba[i],internal);
5989 cop1_usable=prev_cop1_usable;
5990 if(!unconditional) {
5991 set_jump_target(nottaken,(int)out);
5992 assem_debug("1:\n");
5994 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5995 ds_unneeded,ds_unneeded_upper);
5996 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5997 address_generation(i+1,&branch_regs[i],0);
5998 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5999 ds_assemble(i+1,&branch_regs[i]);
6001 cc=get_reg(branch_regs[i].regmap,CCREG);
6002 if(cc==-1&&!likely[i]) {
6003 // Cycle count isn't in a register, temporarily load it then write it out
6004 emit_loadreg(CCREG,HOST_CCREG);
6005 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6008 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6009 emit_storereg(CCREG,HOST_CCREG);
6012 cc=get_reg(i_regmap,CCREG);
6013 assert(cc==HOST_CCREG);
6014 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6017 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6023 void fjump_assemble(int i,struct regstat *i_regs)
6025 signed char *i_regmap=i_regs->regmap;
6028 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6029 assem_debug("fmatch=%d\n",match);
6033 int internal=internal_branch(branch_regs[i].is32,ba[i]);
6034 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
6035 if(!match) invert=1;
6036 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6037 if(i>(ba[i]-start)>>2) invert=1;
6041 fs=get_reg(branch_regs[i].regmap,FSREG);
6042 address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
6045 fs=get_reg(i_regmap,FSREG);
6048 // Check cop1 unusable
6050 cs=get_reg(i_regmap,CSREG);
6052 emit_testimm(cs,0x20000000);
6055 add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
6060 // Out of order execution (delay slot first)
6062 ds_assemble(i+1,i_regs);
6064 uint64_t bc_unneeded=branch_regs[i].u;
6065 uint64_t bc_unneeded_upper=branch_regs[i].uu;
6066 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6067 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
6069 bc_unneeded_upper|=1;
6070 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6071 bc_unneeded,bc_unneeded_upper);
6072 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
6073 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6074 cc=get_reg(branch_regs[i].regmap,CCREG);
6075 assert(cc==HOST_CCREG);
6076 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6077 assem_debug("cycle count (adj)\n");
6080 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6083 emit_testimm(fs,0x800000);
6084 if(source[i]&0x10000) // BC1T
6090 add_to_linker((int)out,ba[i],internal);
6099 add_to_linker((int)out,ba[i],internal);
6107 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
6108 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6109 else if(match) emit_addnop(13);
6111 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6112 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6114 assem_debug("branch: internal\n");
6116 assem_debug("branch: external\n");
6117 if(internal&&is_ds[(ba[i]-start)>>2]) {
6118 ds_assemble_entry(i);
6121 add_to_linker((int)out,ba[i],internal);
6124 set_jump_target(nottaken,(int)out);
6128 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
6130 } // (!unconditional)
6134 // In-order execution (branch first)
6138 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6141 emit_testimm(fs,0x800000);
6142 if(source[i]&0x10000) // BC1T
6153 } // if(!unconditional)
6155 uint64_t ds_unneeded=branch_regs[i].u;
6156 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6157 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6158 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6159 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6161 ds_unneeded_upper|=1;
6163 //assem_debug("1:\n");
6164 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6165 ds_unneeded,ds_unneeded_upper);
6167 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6168 address_generation(i+1,&branch_regs[i],0);
6169 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6170 ds_assemble(i+1,&branch_regs[i]);
6171 cc=get_reg(branch_regs[i].regmap,CCREG);
6173 emit_loadreg(CCREG,cc=HOST_CCREG);
6174 // CHECK: Is the following instruction (fall thru) allocated ok?
6176 assert(cc==HOST_CCREG);
6177 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6178 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6179 assem_debug("cycle count (adj)\n");
6180 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6181 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6183 assem_debug("branch: internal\n");
6185 assem_debug("branch: external\n");
6186 if(internal&&is_ds[(ba[i]-start)>>2]) {
6187 ds_assemble_entry(i);
6190 add_to_linker((int)out,ba[i],internal);
6195 if(1) { // <- FIXME (don't need this)
6196 set_jump_target(nottaken,(int)out);
6197 assem_debug("1:\n");
6199 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6200 ds_unneeded,ds_unneeded_upper);
6201 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6202 address_generation(i+1,&branch_regs[i],0);
6203 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6204 ds_assemble(i+1,&branch_regs[i]);
6206 cc=get_reg(branch_regs[i].regmap,CCREG);
6207 if(cc==-1&&!likely[i]) {
6208 // Cycle count isn't in a register, temporarily load it then write it out
6209 emit_loadreg(CCREG,HOST_CCREG);
6210 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6213 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6214 emit_storereg(CCREG,HOST_CCREG);
6217 cc=get_reg(i_regmap,CCREG);
6218 assert(cc==HOST_CCREG);
6219 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6222 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6228 static void pagespan_assemble(int i,struct regstat *i_regs)
6230 int s1l=get_reg(i_regs->regmap,rs1[i]);
6231 int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6232 int s2l=get_reg(i_regs->regmap,rs2[i]);
6233 int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6234 void *nt_branch=NULL;
6237 int unconditional=0;
6247 if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6251 int addr,alt,ntaddr;
6252 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6256 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6257 (i_regs->regmap[hr]&63)!=rs1[i] &&
6258 (i_regs->regmap[hr]&63)!=rs2[i] )
6267 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6268 (i_regs->regmap[hr]&63)!=rs1[i] &&
6269 (i_regs->regmap[hr]&63)!=rs2[i] )
6275 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6279 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6280 (i_regs->regmap[hr]&63)!=rs1[i] &&
6281 (i_regs->regmap[hr]&63)!=rs2[i] )
6288 assert(hr<HOST_REGS);
6289 if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6290 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6292 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6293 if(opcode[i]==2) // J
6297 if(opcode[i]==3) // JAL
6300 int rt=get_reg(i_regs->regmap,31);
6301 emit_movimm(start+i*4+8,rt);
6304 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6307 if(opcode2[i]==9) // JALR
6309 int rt=get_reg(i_regs->regmap,rt1[i]);
6310 emit_movimm(start+i*4+8,rt);
6313 if((opcode[i]&0x3f)==4) // BEQ
6320 #ifdef HAVE_CMOV_IMM
6322 if(s2l>=0) emit_cmp(s1l,s2l);
6323 else emit_test(s1l,s1l);
6324 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6330 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6332 if(s2h>=0) emit_cmp(s1h,s2h);
6333 else emit_test(s1h,s1h);
6334 emit_cmovne_reg(alt,addr);
6336 if(s2l>=0) emit_cmp(s1l,s2l);
6337 else emit_test(s1l,s1l);
6338 emit_cmovne_reg(alt,addr);
6341 if((opcode[i]&0x3f)==5) // BNE
6343 #ifdef HAVE_CMOV_IMM
6345 if(s2l>=0) emit_cmp(s1l,s2l);
6346 else emit_test(s1l,s1l);
6347 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6353 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6355 if(s2h>=0) emit_cmp(s1h,s2h);
6356 else emit_test(s1h,s1h);
6357 emit_cmovne_reg(alt,addr);
6359 if(s2l>=0) emit_cmp(s1l,s2l);
6360 else emit_test(s1l,s1l);
6361 emit_cmovne_reg(alt,addr);
6364 if((opcode[i]&0x3f)==0x14) // BEQL
6367 if(s2h>=0) emit_cmp(s1h,s2h);
6368 else emit_test(s1h,s1h);
6372 if(s2l>=0) emit_cmp(s1l,s2l);
6373 else emit_test(s1l,s1l);
6374 if(nottaken) set_jump_target(nottaken,(int)out);
6378 if((opcode[i]&0x3f)==0x15) // BNEL
6381 if(s2h>=0) emit_cmp(s1h,s2h);
6382 else emit_test(s1h,s1h);
6386 if(s2l>=0) emit_cmp(s1l,s2l);
6387 else emit_test(s1l,s1l);
6390 if(taken) set_jump_target(taken,(int)out);
6392 if((opcode[i]&0x3f)==6) // BLEZ
6394 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6396 if(s1h>=0) emit_mov(addr,ntaddr);
6397 emit_cmovl_reg(alt,addr);
6400 emit_cmovne_reg(ntaddr,addr);
6401 emit_cmovs_reg(alt,addr);
6404 if((opcode[i]&0x3f)==7) // BGTZ
6406 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6408 if(s1h>=0) emit_mov(addr,alt);
6409 emit_cmovl_reg(ntaddr,addr);
6412 emit_cmovne_reg(alt,addr);
6413 emit_cmovs_reg(ntaddr,addr);
6416 if((opcode[i]&0x3f)==0x16) // BLEZL
6418 assert((opcode[i]&0x3f)!=0x16);
6420 if((opcode[i]&0x3f)==0x17) // BGTZL
6422 assert((opcode[i]&0x3f)!=0x17);
6424 assert(opcode[i]!=1); // BLTZ/BGEZ
6426 //FIXME: Check CSREG
6427 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6428 if((source[i]&0x30000)==0) // BC1F
6430 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6431 emit_testimm(s1l,0x800000);
6432 emit_cmovne_reg(alt,addr);
6434 if((source[i]&0x30000)==0x10000) // BC1T
6436 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6437 emit_testimm(s1l,0x800000);
6438 emit_cmovne_reg(alt,addr);
6440 if((source[i]&0x30000)==0x20000) // BC1FL
6442 emit_testimm(s1l,0x800000);
6446 if((source[i]&0x30000)==0x30000) // BC1TL
6448 emit_testimm(s1l,0x800000);
6454 assert(i_regs->regmap[HOST_CCREG]==CCREG);
6455 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6456 if(likely[i]||unconditional)
6458 emit_movimm(ba[i],HOST_BTREG);
6460 else if(addr!=HOST_BTREG)
6462 emit_mov(addr,HOST_BTREG);
6464 void *branch_addr=out;
6466 int target_addr=start+i*4+5;
6468 void *compiled_target_addr=check_addr(target_addr);
6469 emit_extjump_ds((int)branch_addr,target_addr);
6470 if(compiled_target_addr) {
6471 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6472 add_link(target_addr,stub);
6474 else set_jump_target((int)branch_addr,(int)stub);
6477 set_jump_target((int)nottaken,(int)out);
6478 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6479 void *branch_addr=out;
6481 int target_addr=start+i*4+8;
6483 void *compiled_target_addr=check_addr(target_addr);
6484 emit_extjump_ds((int)branch_addr,target_addr);
6485 if(compiled_target_addr) {
6486 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6487 add_link(target_addr,stub);
6489 else set_jump_target((int)branch_addr,(int)stub);
6493 // Assemble the delay slot for the above
6494 static void pagespan_ds()
6496 assem_debug("initial delay slot:\n");
6497 u_int vaddr=start+1;
6498 u_int page=get_page(vaddr);
6499 u_int vpage=get_vpage(vaddr);
6500 ll_add(jump_dirty+vpage,vaddr,(void *)out);
6502 ll_add(jump_in+page,vaddr,(void *)out);
6503 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6504 if(regs[0].regmap[HOST_CCREG]!=CCREG)
6505 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6506 if(regs[0].regmap[HOST_BTREG]!=BTREG)
6507 emit_writeword(HOST_BTREG,(int)&branch_target);
6508 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6509 address_generation(0,®s[0],regs[0].regmap_entry);
6510 if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
6511 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6516 alu_assemble(0,®s[0]);break;
6518 imm16_assemble(0,®s[0]);break;
6520 shift_assemble(0,®s[0]);break;
6522 shiftimm_assemble(0,®s[0]);break;
6524 load_assemble(0,®s[0]);break;
6526 loadlr_assemble(0,®s[0]);break;
6528 store_assemble(0,®s[0]);break;
6530 storelr_assemble(0,®s[0]);break;
6532 cop0_assemble(0,®s[0]);break;
6534 cop1_assemble(0,®s[0]);break;
6536 c1ls_assemble(0,®s[0]);break;
6538 cop2_assemble(0,®s[0]);break;
6540 c2ls_assemble(0,®s[0]);break;
6542 c2op_assemble(0,®s[0]);break;
6544 fconv_assemble(0,®s[0]);break;
6546 float_assemble(0,®s[0]);break;
6548 fcomp_assemble(0,®s[0]);break;
6550 multdiv_assemble(0,®s[0]);break;
6552 mov_assemble(0,®s[0]);break;
6562 printf("Jump in the delay slot. This is probably a bug.\n");
6564 int btaddr=get_reg(regs[0].regmap,BTREG);
6566 btaddr=get_reg(regs[0].regmap,-1);
6567 emit_readword((int)&branch_target,btaddr);
6569 assert(btaddr!=HOST_CCREG);
6570 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6572 emit_movimm(start+4,HOST_TEMPREG);
6573 emit_cmp(btaddr,HOST_TEMPREG);
6575 emit_cmpimm(btaddr,start+4);
6577 int branch=(int)out;
6579 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6580 emit_jmp(jump_vaddr_reg[btaddr]);
6581 set_jump_target(branch,(int)out);
6582 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6583 load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6586 // Basic liveness analysis for MIPS registers
6587 void unneeded_registers(int istart,int iend,int r)
6591 uint64_t temp_u,temp_uu;
6596 u=unneeded_reg[iend+1];
6597 uu=unneeded_reg_upper[iend+1];
6600 for (i=iend;i>=istart;i--)
6602 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6603 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6605 // If subroutine call, flag return address as a possible branch target
6606 if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6608 if(ba[i]<start || ba[i]>=(start+slen*4))
6610 // Branch out of this block, flush all regs
6614 if(itype[i]==UJUMP&&rt1[i]==31)
6616 uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6618 if(itype[i]==RJUMP&&rs1[i]==31)
6620 uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6622 if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
6623 if(itype[i]==UJUMP&&rt1[i]==31)
6625 //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6626 uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6628 if(itype[i]==RJUMP&&rs1[i]==31)
6630 //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6631 uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6634 branch_unneeded_reg[i]=u;
6635 branch_unneeded_reg_upper[i]=uu;
6636 // Merge in delay slot
6637 tdep=(~uu>>rt1[i+1])&1;
6638 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6639 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6640 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6641 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6642 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6644 // If branch is "likely" (and conditional)
6645 // then we skip the delay slot on the fall-thru path
6648 u&=unneeded_reg[i+2];
6649 uu&=unneeded_reg_upper[i+2];
6660 // Internal branch, flag target
6661 bt[(ba[i]-start)>>2]=1;
6662 if(ba[i]<=start+i*4) {
6664 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6666 // Unconditional branch
6669 // Conditional branch (not taken case)
6670 temp_u=unneeded_reg[i+2];
6671 temp_uu=unneeded_reg_upper[i+2];
6673 // Merge in delay slot
6674 tdep=(~temp_uu>>rt1[i+1])&1;
6675 temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6676 temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6677 temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6678 temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6679 temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6680 temp_u|=1;temp_uu|=1;
6681 // If branch is "likely" (and conditional)
6682 // then we skip the delay slot on the fall-thru path
6685 temp_u&=unneeded_reg[i+2];
6686 temp_uu&=unneeded_reg_upper[i+2];
6694 tdep=(~temp_uu>>rt1[i])&1;
6695 temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6696 temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6697 temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6698 temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6699 temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6700 temp_u|=1;temp_uu|=1;
6701 unneeded_reg[i]=temp_u;
6702 unneeded_reg_upper[i]=temp_uu;
6703 // Only go three levels deep. This recursion can take an
6704 // excessive amount of time if there are a lot of nested loops.
6706 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6708 unneeded_reg[(ba[i]-start)>>2]=1;
6709 unneeded_reg_upper[(ba[i]-start)>>2]=1;
6712 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6714 // Unconditional branch
6715 u=unneeded_reg[(ba[i]-start)>>2];
6716 uu=unneeded_reg_upper[(ba[i]-start)>>2];
6717 branch_unneeded_reg[i]=u;
6718 branch_unneeded_reg_upper[i]=uu;
6721 //branch_unneeded_reg[i]=u;
6722 //branch_unneeded_reg_upper[i]=uu;
6723 // Merge in delay slot
6724 tdep=(~uu>>rt1[i+1])&1;
6725 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6726 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6727 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6728 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6729 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6732 // Conditional branch
6733 b=unneeded_reg[(ba[i]-start)>>2];
6734 bu=unneeded_reg_upper[(ba[i]-start)>>2];
6735 branch_unneeded_reg[i]=b;
6736 branch_unneeded_reg_upper[i]=bu;
6739 //branch_unneeded_reg[i]=b;
6740 //branch_unneeded_reg_upper[i]=bu;
6741 // Branch delay slot
6742 tdep=(~uu>>rt1[i+1])&1;
6743 b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6744 bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6745 b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6746 bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6747 bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6749 // If branch is "likely" then we skip the
6750 // delay slot on the fall-thru path
6755 u&=unneeded_reg[i+2];
6756 uu&=unneeded_reg_upper[i+2];
6767 branch_unneeded_reg[i]&=unneeded_reg[i+2];
6768 branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6769 //branch_unneeded_reg[i]=1;
6770 //branch_unneeded_reg_upper[i]=1;
6772 branch_unneeded_reg[i]=1;
6773 branch_unneeded_reg_upper[i]=1;
6779 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
6781 // SYSCALL instruction (software interrupt)
6785 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6787 // ERET instruction (return from interrupt)
6792 tdep=(~uu>>rt1[i])&1;
6793 // Written registers are unneeded
6798 // Accessed registers are needed
6803 // Source-target dependencies
6804 uu&=~(tdep<<dep1[i]);
6805 uu&=~(tdep<<dep2[i]);
6806 // R0 is always unneeded
6810 unneeded_reg_upper[i]=uu;
6812 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6815 for(r=1;r<=CCREG;r++) {
6816 if((unneeded_reg[i]>>r)&1) {
6817 if(r==HIREG) printf(" HI");
6818 else if(r==LOREG) printf(" LO");
6819 else printf(" r%d",r);
6823 for(r=1;r<=CCREG;r++) {
6824 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
6825 if(r==HIREG) printf(" HI");
6826 else if(r==LOREG) printf(" LO");
6827 else printf(" r%d",r);
6833 for (i=iend;i>=istart;i--)
6835 unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
6840 // Identify registers which are likely to contain 32-bit values
6841 // This is used to predict whether any branches will jump to a
6842 // location with 64-bit values in registers.
6843 static void provisional_32bit()
6847 uint64_t lastbranch=1;
6852 if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
6853 if(i>1) is32=lastbranch;
6859 if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
6861 if(i>2) is32=lastbranch;
6865 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
6867 if(rs1[i-2]==0||rs2[i-2]==0)
6870 is32|=1LL<<rs1[i-2];
6873 is32|=1LL<<rs2[i-2];
6878 // If something jumps here with 64-bit values
6879 // then promote those registers to 64 bits
6882 uint64_t temp_is32=is32;
6885 if(ba[j]==start+i*4)
6886 //temp_is32&=branch_regs[j].is32;
6891 if(ba[j]==start+i*4)
6902 if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
6903 // Branches don't write registers, consider the delay slot instead.
6914 if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
6915 opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
6924 if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
6925 if(op==0x22) is32|=1LL<<rt; // LWL
6928 if (op==0x08||op==0x09|| // ADDI/ADDIU
6929 op==0x0a||op==0x0b|| // SLTI/SLTIU
6935 if(op==0x18||op==0x19) { // DADDI/DADDIU
6938 // is32|=((is32>>s1)&1LL)<<rt;
6940 if(op==0x0d||op==0x0e) { // ORI/XORI
6941 uint64_t sr=((is32>>s1)&1LL);
6957 if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
6960 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
6963 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
6964 uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
6968 else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
6973 uint64_t sr=((is32>>s1)&1LL);
6978 uint64_t sr=((is32>>s2)&1LL);
6986 else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
6991 uint64_t sr=((is32>>s1)&1LL);
7001 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
7002 is32&=~((1LL<<HIREG)|(1LL<<LOREG));
7005 is32|=(1LL<<HIREG)|(1LL<<LOREG);
7010 uint64_t sr=((is32>>s1)&1LL);
7016 if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
7017 else is32|=1LL<<rt; // SLLV/SRLV/SRAV
7021 // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
7022 if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
7025 if(op2==0) is32|=1LL<<rt; // MFC0
7029 if(op2==0) is32|=1LL<<rt; // MFC1
7030 if(op2==1) is32&=~(1LL<<rt); // DMFC1
7031 if(op2==2) is32|=1LL<<rt; // CFC1
7053 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
7055 if(rt1[i-1]==31) // JAL/JALR
7057 // Subroutine call will return here, don't alloc any registers
7062 // Internal branch will jump here, match registers to caller
7070 // Identify registers which may be assumed to contain 32-bit values
7071 // and where optimizations will rely on this.
7072 // This is used to determine whether backward branches can safely
7073 // jump to a location with 64-bit values in registers.
7074 static void provisional_r32()
7079 for (i=slen-1;i>=0;i--)
7082 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7084 if(ba[i]<start || ba[i]>=(start+slen*4))
7086 // Branch out of this block, don't need anything
7092 // Need whatever matches the target
7093 // (and doesn't get overwritten by the delay slot instruction)
7095 int t=(ba[i]-start)>>2;
7096 if(ba[i]>start+i*4) {
7098 //if(!(requires_32bit[t]&~regs[i].was32))
7099 // r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7100 if(!(pr32[t]&~regs[i].was32))
7101 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7104 if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
7105 r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7108 // Conditional branch may need registers for following instructions
7109 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7112 //r32|=requires_32bit[i+2];
7115 // Mark this address as a branch target since it may be called
7116 // upon return from interrupt
7120 // Merge in delay slot
7122 // These are overwritten unless the branch is "likely"
7123 // and the delay slot is nullified if not taken
7124 r32&=~(1LL<<rt1[i+1]);
7125 r32&=~(1LL<<rt2[i+1]);
7127 // Assume these are needed (delay slot)
7130 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7134 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7136 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7138 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7140 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7142 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7145 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7147 // SYSCALL instruction (software interrupt)
7150 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7152 // ERET instruction (return from interrupt)
7156 r32&=~(1LL<<rt1[i]);
7157 r32&=~(1LL<<rt2[i]);
7160 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7164 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7166 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7168 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7170 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7172 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7174 //requires_32bit[i]=r32;
7177 // Dirty registers which are 32-bit, require 32-bit input
7178 // as they will be written as 32-bit values
7179 for(hr=0;hr<HOST_REGS;hr++)
7181 if(regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64) {
7182 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7183 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7184 pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7185 //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7192 // Write back dirty registers as soon as we will no longer modify them,
7193 // so that we don't end up with lots of writes at the branches.
7194 void clean_registers(int istart,int iend,int wr)
7198 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7199 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7201 will_dirty_i=will_dirty_next=0;
7202 wont_dirty_i=wont_dirty_next=0;
7204 will_dirty_i=will_dirty_next=will_dirty[iend+1];
7205 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7207 for (i=iend;i>=istart;i--)
7209 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7211 if(ba[i]<start || ba[i]>=(start+slen*4))
7213 // Branch out of this block, flush all regs
7214 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7216 // Unconditional branch
7219 // Merge in delay slot (will dirty)
7220 for(r=0;r<HOST_REGS;r++) {
7221 if(r!=EXCLUDE_REG) {
7222 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7223 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7224 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7225 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7226 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7227 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7228 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7229 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7230 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7231 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7232 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7233 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7234 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7235 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7241 // Conditional branch
7243 wont_dirty_i=wont_dirty_next;
7244 // Merge in delay slot (will dirty)
7245 for(r=0;r<HOST_REGS;r++) {
7246 if(r!=EXCLUDE_REG) {
7248 // Might not dirty if likely branch is not taken
7249 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7250 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7251 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7252 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7253 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7254 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7255 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7256 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7257 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7258 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7259 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7260 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7261 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7262 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7267 // Merge in delay slot (wont dirty)
7268 for(r=0;r<HOST_REGS;r++) {
7269 if(r!=EXCLUDE_REG) {
7270 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7271 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7272 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7273 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7274 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7275 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7276 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7277 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7278 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7279 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7283 #ifndef DESTRUCTIVE_WRITEBACK
7284 branch_regs[i].dirty&=wont_dirty_i;
7286 branch_regs[i].dirty|=will_dirty_i;
7292 if(ba[i]<=start+i*4) {
7294 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7296 // Unconditional branch
7299 // Merge in delay slot (will dirty)
7300 for(r=0;r<HOST_REGS;r++) {
7301 if(r!=EXCLUDE_REG) {
7302 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7303 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7304 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7305 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7306 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7307 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7308 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7309 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7310 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7311 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7312 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7313 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7314 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7315 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7319 // Conditional branch (not taken case)
7320 temp_will_dirty=will_dirty_next;
7321 temp_wont_dirty=wont_dirty_next;
7322 // Merge in delay slot (will dirty)
7323 for(r=0;r<HOST_REGS;r++) {
7324 if(r!=EXCLUDE_REG) {
7326 // Will not dirty if likely branch is not taken
7327 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7328 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7329 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7330 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7331 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7332 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7333 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7334 //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7335 //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7336 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7337 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7338 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7339 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7340 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7345 // Merge in delay slot (wont dirty)
7346 for(r=0;r<HOST_REGS;r++) {
7347 if(r!=EXCLUDE_REG) {
7348 if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7349 if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7350 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7351 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7352 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7353 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7354 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7355 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7356 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7357 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7360 // Deal with changed mappings
7362 for(r=0;r<HOST_REGS;r++) {
7363 if(r!=EXCLUDE_REG) {
7364 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7365 temp_will_dirty&=~(1<<r);
7366 temp_wont_dirty&=~(1<<r);
7367 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7368 temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7369 temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7371 temp_will_dirty|=1<<r;
7372 temp_wont_dirty|=1<<r;
7379 will_dirty[i]=temp_will_dirty;
7380 wont_dirty[i]=temp_wont_dirty;
7381 clean_registers((ba[i]-start)>>2,i-1,0);
7383 // Limit recursion. It can take an excessive amount
7384 // of time if there are a lot of nested loops.
7385 will_dirty[(ba[i]-start)>>2]=0;
7386 wont_dirty[(ba[i]-start)>>2]=-1;
7391 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7393 // Unconditional branch
7396 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7397 for(r=0;r<HOST_REGS;r++) {
7398 if(r!=EXCLUDE_REG) {
7399 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7400 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7401 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7406 // Merge in delay slot
7407 for(r=0;r<HOST_REGS;r++) {
7408 if(r!=EXCLUDE_REG) {
7409 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7410 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7411 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7412 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7413 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7414 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7415 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7416 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7417 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7418 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7419 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7420 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7421 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7422 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7426 // Conditional branch
7427 will_dirty_i=will_dirty_next;
7428 wont_dirty_i=wont_dirty_next;
7429 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7430 for(r=0;r<HOST_REGS;r++) {
7431 if(r!=EXCLUDE_REG) {
7432 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7433 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7434 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7438 will_dirty_i&=~(1<<r);
7440 // Treat delay slot as part of branch too
7441 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7442 will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7443 wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7447 will_dirty[i+1]&=~(1<<r);
7452 // Merge in delay slot
7453 for(r=0;r<HOST_REGS;r++) {
7454 if(r!=EXCLUDE_REG) {
7456 // Might not dirty if likely branch is not taken
7457 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7458 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7459 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7460 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7461 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7462 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7463 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7464 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7465 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7466 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7467 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7468 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7469 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7470 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7475 // Merge in delay slot
7476 for(r=0;r<HOST_REGS;r++) {
7477 if(r!=EXCLUDE_REG) {
7478 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7479 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7480 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7481 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7482 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7483 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7484 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7485 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7486 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7487 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7491 #ifndef DESTRUCTIVE_WRITEBACK
7492 branch_regs[i].dirty&=wont_dirty_i;
7494 branch_regs[i].dirty|=will_dirty_i;
7499 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7501 // SYSCALL instruction (software interrupt)
7505 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7507 // ERET instruction (return from interrupt)
7511 will_dirty_next=will_dirty_i;
7512 wont_dirty_next=wont_dirty_i;
7513 for(r=0;r<HOST_REGS;r++) {
7514 if(r!=EXCLUDE_REG) {
7515 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7516 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7517 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7518 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7519 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7520 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7521 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7522 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7524 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7526 // Don't store a register immediately after writing it,
7527 // may prevent dual-issue.
7528 if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7529 if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7535 will_dirty[i]=will_dirty_i;
7536 wont_dirty[i]=wont_dirty_i;
7537 // Mark registers that won't be dirtied as not dirty
7539 /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7540 for(r=0;r<HOST_REGS;r++) {
7541 if((will_dirty_i>>r)&1) {
7547 //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7548 regs[i].dirty|=will_dirty_i;
7549 #ifndef DESTRUCTIVE_WRITEBACK
7550 regs[i].dirty&=wont_dirty_i;
7551 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7553 if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7554 for(r=0;r<HOST_REGS;r++) {
7555 if(r!=EXCLUDE_REG) {
7556 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7557 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7558 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7566 for(r=0;r<HOST_REGS;r++) {
7567 if(r!=EXCLUDE_REG) {
7568 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7569 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7570 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7578 // Deal with changed mappings
7579 temp_will_dirty=will_dirty_i;
7580 temp_wont_dirty=wont_dirty_i;
7581 for(r=0;r<HOST_REGS;r++) {
7582 if(r!=EXCLUDE_REG) {
7584 if(regs[i].regmap[r]==regmap_pre[i][r]) {
7586 #ifndef DESTRUCTIVE_WRITEBACK
7587 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7589 regs[i].wasdirty|=will_dirty_i&(1<<r);
7592 else if((nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7593 // Register moved to a different register
7594 will_dirty_i&=~(1<<r);
7595 wont_dirty_i&=~(1<<r);
7596 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7597 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7599 #ifndef DESTRUCTIVE_WRITEBACK
7600 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7602 regs[i].wasdirty|=will_dirty_i&(1<<r);
7606 will_dirty_i&=~(1<<r);
7607 wont_dirty_i&=~(1<<r);
7608 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7609 will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7610 wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7613 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7622 void disassemble_inst(int i)
7624 if (bt[i]) printf("*"); else printf(" ");
7627 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7629 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7631 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7633 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7635 if (opcode[i]==0x9&&rt1[i]!=31)
7636 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7638 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7641 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7643 if(opcode[i]==0xf) //LUI
7644 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7646 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7650 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7654 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7658 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7661 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7664 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7667 if((opcode2[i]&0x1d)==0x10)
7668 printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7669 else if((opcode2[i]&0x1d)==0x11)
7670 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7672 printf (" %x: %s\n",start+i*4,insn[i]);
7676 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7677 else if(opcode2[i]==4)
7678 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7679 else printf (" %x: %s\n",start+i*4,insn[i]);
7683 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7684 else if(opcode2[i]>3)
7685 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7686 else printf (" %x: %s\n",start+i*4,insn[i]);
7690 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7691 else if(opcode2[i]>3)
7692 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7693 else printf (" %x: %s\n",start+i*4,insn[i]);
7696 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7699 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7702 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
7705 //printf (" %s %8x\n",insn[i],source[i]);
7706 printf (" %x: %s\n",start+i*4,insn[i]);
7710 // clear the state completely, instead of just marking
7711 // things invalid like invalidate_all_pages() does
7712 void new_dynarec_clear_full()
7715 for(n=0x80000;n<0x80800;n++)
7717 for(n=0;n<65536;n++)
7718 hash_table[n][0]=hash_table[n][2]=-1;
7719 memset(mini_ht,-1,sizeof(mini_ht));
7720 memset(restore_candidate,0,sizeof(restore_candidate));
7721 memset(shadow,0,sizeof(shadow));
7723 expirep=16384; // Expiry pointer, +2 blocks
7724 pending_exception=0;
7729 for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7731 for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7732 memory_map[n]=((u_int)rdram-0x80000000)>>2;
7733 for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7735 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7736 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7737 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7740 void new_dynarec_init()
7742 printf("Init new dynarec\n");
7743 out=(u_char *)BASE_ADDR;
7744 if (mmap (out, 1<<TARGET_SIZE_2,
7745 PROT_READ | PROT_WRITE | PROT_EXEC,
7746 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
7747 -1, 0) <= 0) {printf("mmap() failed\n");}
7749 rdword=&readmem_dword;
7750 fake_pc.f.r.rs=&readmem_dword;
7751 fake_pc.f.r.rt=&readmem_dword;
7752 fake_pc.f.r.rd=&readmem_dword;
7755 new_dynarec_clear_full();
7757 // Copy this into local area so we don't have to put it in every literal pool
7758 invc_ptr=invalid_code;
7761 for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
7762 writemem[n] = write_nomem_new;
7763 writememb[n] = write_nomemb_new;
7764 writememh[n] = write_nomemh_new;
7766 writememd[n] = write_nomemd_new;
7768 readmem[n] = read_nomem_new;
7769 readmemb[n] = read_nomemb_new;
7770 readmemh[n] = read_nomemh_new;
7772 readmemd[n] = read_nomemd_new;
7775 for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
7776 writemem[n] = write_rdram_new;
7777 writememb[n] = write_rdramb_new;
7778 writememh[n] = write_rdramh_new;
7780 writememd[n] = write_rdramd_new;
7783 for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
7784 writemem[n] = write_nomem_new;
7785 writememb[n] = write_nomemb_new;
7786 writememh[n] = write_nomemh_new;
7788 writememd[n] = write_nomemd_new;
7790 readmem[n] = read_nomem_new;
7791 readmemb[n] = read_nomemb_new;
7792 readmemh[n] = read_nomemh_new;
7794 readmemd[n] = read_nomemd_new;
7802 void new_dynarec_cleanup()
7805 if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
7806 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7807 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7808 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7810 if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
7814 int new_recompile_block(int addr)
7817 if(addr==0x800cd050) {
7819 for(block=0x80000;block<0x80800;block++) invalidate_block(block);
7821 for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
7824 //if(Count==365117028) tracedebug=1;
7825 assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7826 //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7827 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
7829 //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
7830 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
7831 /*if(Count>=312978186) {
7835 start = (u_int)addr&~3;
7836 //assert(((u_int)addr&1)==0);
7838 if (Config.HLE && start == 0x80001000) // hlecall
7840 // XXX: is this enough? Maybe check hleSoftCall?
7841 u_int beginning=(u_int)out;
7842 u_int page=get_page(start);
7843 invalid_code[start>>12]=0;
7844 emit_movimm(start,0);
7845 emit_writeword(0,(int)&pcaddr);
7846 emit_jmp((int)new_dyna_leave);
7848 __clear_cache((void *)beginning,out);
7850 ll_add(jump_in+page,start,(void *)beginning);
7853 else if ((u_int)addr < 0x00200000 ||
7854 (0xa0000000 <= addr && addr < 0xa0200000)) {
7855 // used for BIOS calls mostly?
7856 source = (u_int *)((u_int)rdram+(start&0x1fffff));
7857 pagelimit = (addr&0xa0000000)|0x00200000;
7859 else if (!Config.HLE && (
7860 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
7861 (0xbfc00000 <= addr && addr < 0xbfc80000))) {
7863 source = (u_int *)((u_int)psxR+(start&0x7ffff));
7864 pagelimit = (addr&0xfff00000)|0x80000;
7869 if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
7870 source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
7871 pagelimit = 0xa4001000;
7875 if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
7876 source = (u_int *)((u_int)rdram+start-0x80000000);
7877 pagelimit = 0x80000000+RAM_SIZE;
7880 else if ((signed int)addr >= (signed int)0xC0000000) {
7881 //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
7882 //if(tlb_LUT_r[start>>12])
7883 //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
7884 if((signed int)memory_map[start>>12]>=0) {
7885 source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
7886 pagelimit=(start+4096)&0xFFFFF000;
7887 int map=memory_map[start>>12];
7890 //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
7891 if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
7893 assem_debug("pagelimit=%x\n",pagelimit);
7894 assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
7897 assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
7898 //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
7899 return -1; // Caller will invoke exception handler
7901 //printf("source= %x\n",(int)source);
7905 printf("Compile at bogus memory address: %x \n", (int)addr);
7909 /* Pass 1: disassemble */
7910 /* Pass 2: register dependencies, branch targets */
7911 /* Pass 3: register allocation */
7912 /* Pass 4: branch dependencies */
7913 /* Pass 5: pre-alloc */
7914 /* Pass 6: optimize clean/dirty state */
7915 /* Pass 7: flag 32-bit registers */
7916 /* Pass 8: assembly */
7917 /* Pass 9: linker */
7918 /* Pass 10: garbage collection / free memory */
7922 unsigned int type,op,op2;
7924 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
7926 /* Pass 1 disassembly */
7928 for(i=0;!done;i++) {
7929 bt[i]=0;likely[i]=0;ooo[i]=0;op2=0;
7930 minimum_free_regs[i]=0;
7931 opcode[i]=op=source[i]>>26;
7934 case 0x00: strcpy(insn[i],"special"); type=NI;
7938 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
7939 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
7940 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
7941 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
7942 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
7943 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
7944 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
7945 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
7946 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
7947 case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
7948 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
7949 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
7950 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
7951 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
7952 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
7953 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
7954 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
7955 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
7956 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
7957 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
7958 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
7959 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
7960 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
7961 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
7962 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
7963 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
7964 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
7965 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
7966 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
7967 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
7968 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
7969 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
7970 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
7971 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
7972 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
7973 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
7974 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
7975 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
7976 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
7977 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
7978 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
7979 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
7980 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
7981 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
7982 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
7983 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
7984 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
7985 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
7986 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
7987 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
7988 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
7989 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
7992 case 0x01: strcpy(insn[i],"regimm"); type=NI;
7993 op2=(source[i]>>16)&0x1f;
7996 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
7997 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
7998 case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
7999 case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
8000 case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
8001 case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
8002 case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
8003 case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
8004 case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
8005 case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
8006 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
8007 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
8008 case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
8009 case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
8012 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
8013 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
8014 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
8015 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
8016 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
8017 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
8018 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
8019 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
8020 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
8021 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
8022 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
8023 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
8024 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
8025 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
8026 case 0x10: strcpy(insn[i],"cop0"); type=NI;
8027 op2=(source[i]>>21)&0x1f;
8030 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
8031 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
8032 case 0x10: strcpy(insn[i],"tlb"); type=NI;
8033 switch(source[i]&0x3f)
8035 case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
8036 case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
8037 case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
8038 case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
8040 case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
8042 case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
8047 case 0x11: strcpy(insn[i],"cop1"); type=NI;
8048 op2=(source[i]>>21)&0x1f;
8051 case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
8052 case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
8053 case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
8054 case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
8055 case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
8056 case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
8057 case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
8058 switch((source[i]>>16)&0x3)
8060 case 0x00: strcpy(insn[i],"BC1F"); break;
8061 case 0x01: strcpy(insn[i],"BC1T"); break;
8062 case 0x02: strcpy(insn[i],"BC1FL"); break;
8063 case 0x03: strcpy(insn[i],"BC1TL"); break;
8066 case 0x10: strcpy(insn[i],"C1.S"); type=NI;
8067 switch(source[i]&0x3f)
8069 case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
8070 case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
8071 case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
8072 case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
8073 case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
8074 case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
8075 case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
8076 case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
8077 case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
8078 case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
8079 case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
8080 case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
8081 case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
8082 case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
8083 case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
8084 case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
8085 case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
8086 case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
8087 case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
8088 case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
8089 case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
8090 case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
8091 case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
8092 case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
8093 case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
8094 case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
8095 case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
8096 case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
8097 case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
8098 case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
8099 case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
8100 case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
8101 case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
8102 case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
8103 case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
8106 case 0x11: strcpy(insn[i],"C1.D"); type=NI;
8107 switch(source[i]&0x3f)
8109 case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
8110 case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
8111 case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
8112 case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
8113 case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
8114 case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
8115 case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
8116 case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
8117 case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
8118 case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
8119 case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
8120 case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
8121 case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
8122 case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
8123 case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
8124 case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
8125 case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
8126 case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
8127 case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
8128 case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
8129 case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
8130 case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
8131 case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
8132 case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
8133 case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
8134 case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
8135 case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
8136 case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
8137 case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
8138 case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
8139 case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8140 case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8141 case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8142 case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8143 case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8146 case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8147 switch(source[i]&0x3f)
8149 case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8150 case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8153 case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8154 switch(source[i]&0x3f)
8156 case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8157 case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8163 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8164 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8165 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8166 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8167 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8168 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8169 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8170 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
8172 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8173 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8174 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8175 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8176 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8177 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8178 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
8179 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
8180 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8181 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8182 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8183 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
8185 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8186 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
8188 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8189 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8190 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8191 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
8193 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8194 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8195 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
8197 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8198 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
8200 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8201 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8202 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
8205 case 0x12: strcpy(insn[i],"COP2"); type=NI;
8206 // note: COP MIPS-1 encoding differs from MIPS32
8207 op2=(source[i]>>21)&0x1f;
8208 if (source[i]&0x3f) {
8209 if (gte_handlers[source[i]&0x3f]!=NULL) {
8210 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8216 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8217 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8218 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8219 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
8222 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8223 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8224 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8226 default: strcpy(insn[i],"???"); type=NI;
8227 printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
8231 /* detect branch in delay slot early */
8232 if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
8233 opcode[i+1]=source[i+1]>>26;
8234 opcode2[i+1]=source[i+1]&0x3f;
8235 if((0<opcode[i+1]&&opcode[i+1]<8)||(opcode[i+1]==0&&(opcode2[i+1]==8||opcode2[i+1]==9))) {
8236 printf("branch in delay slot @%08x (%08x)\n", addr + i*4+4, addr);
8237 // don't handle first branch and call interpreter if it's hit
8244 /* Get registers/immediates */
8252 rs1[i]=(source[i]>>21)&0x1f;
8254 rt1[i]=(source[i]>>16)&0x1f;
8256 imm[i]=(short)source[i];
8260 rs1[i]=(source[i]>>21)&0x1f;
8261 rs2[i]=(source[i]>>16)&0x1f;
8264 imm[i]=(short)source[i];
8265 if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8268 // LWL/LWR only load part of the register,
8269 // therefore the target register must be treated as a source too
8270 rs1[i]=(source[i]>>21)&0x1f;
8271 rs2[i]=(source[i]>>16)&0x1f;
8272 rt1[i]=(source[i]>>16)&0x1f;
8274 imm[i]=(short)source[i];
8275 if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8276 if(op==0x26) dep1[i]=rt1[i]; // LWR
8279 if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8280 else rs1[i]=(source[i]>>21)&0x1f;
8282 rt1[i]=(source[i]>>16)&0x1f;
8284 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8285 imm[i]=(unsigned short)source[i];
8287 imm[i]=(short)source[i];
8289 if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8290 if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8291 if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8298 // The JAL instruction writes to r31.
8305 rs1[i]=(source[i]>>21)&0x1f;
8309 // The JALR instruction writes to rd.
8311 rt1[i]=(source[i]>>11)&0x1f;
8316 rs1[i]=(source[i]>>21)&0x1f;
8317 rs2[i]=(source[i]>>16)&0x1f;
8320 if(op&2) { // BGTZ/BLEZ
8328 rs1[i]=(source[i]>>21)&0x1f;
8333 if(op2&0x10) { // BxxAL
8335 // NOTE: If the branch is not taken, r31 is still overwritten
8337 likely[i]=(op2&2)>>1;
8344 likely[i]=((source[i])>>17)&1;
8347 rs1[i]=(source[i]>>21)&0x1f; // source
8348 rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8349 rt1[i]=(source[i]>>11)&0x1f; // destination
8351 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8352 us1[i]=rs1[i];us2[i]=rs2[i];
8354 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8355 dep1[i]=rs1[i];dep2[i]=rs2[i];
8357 else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8358 dep1[i]=rs1[i];dep2[i]=rs2[i];
8362 rs1[i]=(source[i]>>21)&0x1f; // source
8363 rs2[i]=(source[i]>>16)&0x1f; // divisor
8366 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8367 us1[i]=rs1[i];us2[i]=rs2[i];
8375 if(op2==0x10) rs1[i]=HIREG; // MFHI
8376 if(op2==0x11) rt1[i]=HIREG; // MTHI
8377 if(op2==0x12) rs1[i]=LOREG; // MFLO
8378 if(op2==0x13) rt1[i]=LOREG; // MTLO
8379 if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8380 if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8384 rs1[i]=(source[i]>>16)&0x1f; // target of shift
8385 rs2[i]=(source[i]>>21)&0x1f; // shift amount
8386 rt1[i]=(source[i]>>11)&0x1f; // destination
8388 // DSLLV/DSRLV/DSRAV are 64-bit
8389 if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8392 rs1[i]=(source[i]>>16)&0x1f;
8394 rt1[i]=(source[i]>>11)&0x1f;
8396 imm[i]=(source[i]>>6)&0x1f;
8397 // DSxx32 instructions
8398 if(op2>=0x3c) imm[i]|=0x20;
8399 // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8400 if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8407 if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8408 if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8409 if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8410 if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8418 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8419 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8420 if(op2==5) us1[i]=rs1[i]; // DMTC1
8424 rs1[i]=(source[i]>>21)&0x1F;
8428 imm[i]=(short)source[i];
8431 rs1[i]=(source[i]>>21)&0x1F;
8435 imm[i]=(short)source[i];
8464 /* Calculate branch target addresses */
8466 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8467 else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8468 ba[i]=start+i*4+8; // Ignore never taken branch
8469 else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8470 ba[i]=start+i*4+8; // Ignore never taken branch
8471 else if(type==CJUMP||type==SJUMP||type==FJUMP)
8472 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8474 /* Is this the end of the block? */
8475 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
8477 // check for link register access in delay slot
8479 if(rt1_!=0&&(rs1[i]==rt1_||rs2[i]==rt1_||rt1[i]==rt1_||rt2[i]==rt1_)) {
8480 printf("link access in delay slot @%08x (%08x)\n", addr + i*4, addr);
8487 if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
8491 if(stop_after_jal) done=1;
8493 if((source[i+1]&0xfc00003f)==0x0d) done=1;
8495 // Don't recompile stuff that's already compiled
8496 if(check_addr(start+i*4+4)) done=1;
8497 // Don't get too close to the limit
8498 if(i>MAXBLOCK/2) done=1;
8500 if(itype[i]==SYSCALL&&stop_after_jal) done=1;
8501 if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
8503 // Does the block continue due to a branch?
8506 if(ba[j]==start+i*4+4) done=j=0;
8507 if(ba[j]==start+i*4+8) done=j=0;
8510 //assert(i<MAXBLOCK-1);
8511 if(start+i*4==pagelimit-4) done=1;
8512 assert(start+i*4<pagelimit);
8513 if (i==MAXBLOCK-1) done=1;
8514 // Stop if we're compiling junk
8515 if(itype[i]==NI&&opcode[i]==0x11) {
8516 done=stop_after_jal=1;
8517 printf("Disabled speculative precompilation\n");
8521 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8522 if(start+i*4==pagelimit) {
8528 /* Pass 2 - Register dependencies and branch targets */
8530 unneeded_registers(0,slen-1,0);
8532 /* Pass 3 - Register allocation */
8534 struct regstat current; // Current register allocations/status
8537 current.u=unneeded_reg[0];
8538 current.uu=unneeded_reg_upper[0];
8539 clear_all_regs(current.regmap);
8540 alloc_reg(¤t,0,CCREG);
8541 dirty_reg(¤t,CCREG);
8549 provisional_32bit();
8552 // First instruction is delay slot
8557 unneeded_reg_upper[0]=1;
8558 current.regmap[HOST_BTREG]=BTREG;
8566 for(hr=0;hr<HOST_REGS;hr++)
8568 // Is this really necessary?
8569 if(current.regmap[hr]==0) current.regmap[hr]=-1;
8575 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8577 if(rs1[i-2]==0||rs2[i-2]==0)
8580 current.is32|=1LL<<rs1[i-2];
8581 int hr=get_reg(current.regmap,rs1[i-2]|64);
8582 if(hr>=0) current.regmap[hr]=-1;
8585 current.is32|=1LL<<rs2[i-2];
8586 int hr=get_reg(current.regmap,rs2[i-2]|64);
8587 if(hr>=0) current.regmap[hr]=-1;
8593 // If something jumps here with 64-bit values
8594 // then promote those registers to 64 bits
8597 uint64_t temp_is32=current.is32;
8600 if(ba[j]==start+i*4)
8601 temp_is32&=branch_regs[j].is32;
8605 if(ba[j]==start+i*4)
8609 if(temp_is32!=current.is32) {
8610 //printf("dumping 32-bit regs (%x)\n",start+i*4);
8611 #ifdef DESTRUCTIVE_WRITEBACK
8612 for(hr=0;hr<HOST_REGS;hr++)
8614 int r=current.regmap[hr];
8617 if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8619 //printf("restore %d\n",r);
8624 current.is32=temp_is32;
8631 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8632 regs[i].wasconst=current.isconst;
8633 regs[i].was32=current.is32;
8634 regs[i].wasdirty=current.dirty;
8635 #if defined(DESTRUCTIVE_WRITEBACK) && !defined(FORCE32)
8636 // To change a dirty register from 32 to 64 bits, we must write
8637 // it out during the previous cycle (for branches, 2 cycles)
8638 if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8640 uint64_t temp_is32=current.is32;
8643 if(ba[j]==start+i*4+4)
8644 temp_is32&=branch_regs[j].is32;
8648 if(ba[j]==start+i*4+4)
8652 if(temp_is32!=current.is32) {
8653 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8654 for(hr=0;hr<HOST_REGS;hr++)
8656 int r=current.regmap[hr];
8659 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8660 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
8662 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
8664 //printf("dump %d/r%d\n",hr,r);
8665 current.regmap[hr]=-1;
8666 if(get_reg(current.regmap,r|64)>=0)
8667 current.regmap[get_reg(current.regmap,r|64)]=-1;
8675 else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
8677 uint64_t temp_is32=current.is32;
8680 if(ba[j]==start+i*4+8)
8681 temp_is32&=branch_regs[j].is32;
8685 if(ba[j]==start+i*4+8)
8689 if(temp_is32!=current.is32) {
8690 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8691 for(hr=0;hr<HOST_REGS;hr++)
8693 int r=current.regmap[hr];
8696 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8697 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
8699 //printf("dump %d/r%d\n",hr,r);
8700 current.regmap[hr]=-1;
8701 if(get_reg(current.regmap,r|64)>=0)
8702 current.regmap[get_reg(current.regmap,r|64)]=-1;
8710 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8712 current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8713 current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8714 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8723 current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
8724 current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8725 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8726 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8727 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8730 } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
8734 ds=0; // Skip delay slot, already allocated as part of branch
8735 // ...but we need to alloc it in case something jumps here
8737 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
8738 current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
8740 current.u=branch_unneeded_reg[i-1];
8741 current.uu=branch_unneeded_reg_upper[i-1];
8743 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8744 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8745 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8748 struct regstat temp;
8749 memcpy(&temp,¤t,sizeof(current));
8750 temp.wasdirty=temp.dirty;
8751 temp.was32=temp.is32;
8752 // TODO: Take into account unconditional branches, as below
8753 delayslot_alloc(&temp,i);
8754 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
8755 regs[i].wasdirty=temp.wasdirty;
8756 regs[i].was32=temp.was32;
8757 regs[i].dirty=temp.dirty;
8758 regs[i].is32=temp.is32;
8762 // Create entry (branch target) regmap
8763 for(hr=0;hr<HOST_REGS;hr++)
8765 int r=temp.regmap[hr];
8767 if(r!=regmap_pre[i][hr]) {
8768 regs[i].regmap_entry[hr]=-1;
8773 if((current.u>>r)&1) {
8774 regs[i].regmap_entry[hr]=-1;
8775 regs[i].regmap[hr]=-1;
8776 //Don't clear regs in the delay slot as the branch might need them
8777 //current.regmap[hr]=-1;
8779 regs[i].regmap_entry[hr]=r;
8782 if((current.uu>>(r&63))&1) {
8783 regs[i].regmap_entry[hr]=-1;
8784 regs[i].regmap[hr]=-1;
8785 //Don't clear regs in the delay slot as the branch might need them
8786 //current.regmap[hr]=-1;
8788 regs[i].regmap_entry[hr]=r;
8792 // First instruction expects CCREG to be allocated
8793 if(i==0&&hr==HOST_CCREG)
8794 regs[i].regmap_entry[hr]=CCREG;
8796 regs[i].regmap_entry[hr]=-1;
8800 else { // Not delay slot
8803 //current.isconst=0; // DEBUG
8804 //current.wasconst=0; // DEBUG
8805 //regs[i].wasconst=0; // DEBUG
8806 clear_const(¤t,rt1[i]);
8807 alloc_cc(¤t,i);
8808 dirty_reg(¤t,CCREG);
8810 alloc_reg(¤t,i,31);
8811 dirty_reg(¤t,31);
8812 assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8813 assert(rt1[i+1]!=rt1[i]);
8815 alloc_reg(¤t,i,PTEMP);
8817 //current.is32|=1LL<<rt1[i];
8820 delayslot_alloc(¤t,i+1);
8821 //current.isconst=0; // DEBUG
8823 //printf("i=%d, isconst=%x\n",i,current.isconst);
8826 //current.isconst=0;
8827 //current.wasconst=0;
8828 //regs[i].wasconst=0;
8829 clear_const(¤t,rs1[i]);
8830 clear_const(¤t,rt1[i]);
8831 alloc_cc(¤t,i);
8832 dirty_reg(¤t,CCREG);
8833 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
8834 alloc_reg(¤t,i,rs1[i]);
8836 alloc_reg(¤t,i,rt1[i]);
8837 dirty_reg(¤t,rt1[i]);
8838 assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
8839 assert(rt1[i+1]!=rt1[i]);
8841 alloc_reg(¤t,i,PTEMP);
8845 if(rs1[i]==31) { // JALR
8846 alloc_reg(¤t,i,RHASH);
8847 #ifndef HOST_IMM_ADDR32
8848 alloc_reg(¤t,i,RHTBL);
8852 delayslot_alloc(¤t,i+1);
8854 // The delay slot overwrites our source register,
8855 // allocate a temporary register to hold the old value.
8859 delayslot_alloc(¤t,i+1);
8861 alloc_reg(¤t,i,RTEMP);
8863 //current.isconst=0; // DEBUG
8868 //current.isconst=0;
8869 //current.wasconst=0;
8870 //regs[i].wasconst=0;
8871 clear_const(¤t,rs1[i]);
8872 clear_const(¤t,rs2[i]);
8873 if((opcode[i]&0x3E)==4) // BEQ/BNE
8875 alloc_cc(¤t,i);
8876 dirty_reg(¤t,CCREG);
8877 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
8878 if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
8879 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8881 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
8882 if(rs2[i]) alloc_reg64(¤t,i,rs2[i]);
8884 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
8885 (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
8886 // The delay slot overwrites one of our conditions.
8887 // Allocate the branch condition registers instead.
8891 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
8892 if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
8893 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8895 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
8896 if(rs2[i]) alloc_reg64(¤t,i,rs2[i]);
8902 delayslot_alloc(¤t,i+1);
8906 if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
8908 alloc_cc(¤t,i);
8909 dirty_reg(¤t,CCREG);
8910 alloc_reg(¤t,i,rs1[i]);
8911 if(!(current.is32>>rs1[i]&1))
8913 alloc_reg64(¤t,i,rs1[i]);
8915 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
8916 // The delay slot overwrites one of our conditions.
8917 // Allocate the branch condition registers instead.
8921 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
8922 if(!((current.is32>>rs1[i])&1))
8924 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
8930 delayslot_alloc(¤t,i+1);
8934 // Don't alloc the delay slot yet because we might not execute it
8935 if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
8940 alloc_cc(¤t,i);
8941 dirty_reg(¤t,CCREG);
8942 alloc_reg(¤t,i,rs1[i]);
8943 alloc_reg(¤t,i,rs2[i]);
8944 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8946 alloc_reg64(¤t,i,rs1[i]);
8947 alloc_reg64(¤t,i,rs2[i]);
8951 if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
8956 alloc_cc(¤t,i);
8957 dirty_reg(¤t,CCREG);
8958 alloc_reg(¤t,i,rs1[i]);
8959 if(!(current.is32>>rs1[i]&1))
8961 alloc_reg64(¤t,i,rs1[i]);
8965 //current.isconst=0;
8968 //current.isconst=0;
8969 //current.wasconst=0;
8970 //regs[i].wasconst=0;
8971 clear_const(¤t,rs1[i]);
8972 clear_const(¤t,rt1[i]);
8973 //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
8974 if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
8976 alloc_cc(¤t,i);
8977 dirty_reg(¤t,CCREG);
8978 alloc_reg(¤t,i,rs1[i]);
8979 if(!(current.is32>>rs1[i]&1))
8981 alloc_reg64(¤t,i,rs1[i]);
8983 if (rt1[i]==31) { // BLTZAL/BGEZAL
8984 alloc_reg(¤t,i,31);
8985 dirty_reg(¤t,31);
8986 //#ifdef REG_PREFETCH
8987 //alloc_reg(¤t,i,PTEMP);
8989 //current.is32|=1LL<<rt1[i];
8991 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) // The delay slot overwrites the branch condition.
8992 ||(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))) { // DS touches $ra
8993 // Allocate the branch condition registers instead.
8997 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
8998 if(!((current.is32>>rs1[i])&1))
9000 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9006 delayslot_alloc(¤t,i+1);
9010 // Don't alloc the delay slot yet because we might not execute it
9011 if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
9016 alloc_cc(¤t,i);
9017 dirty_reg(¤t,CCREG);
9018 alloc_reg(¤t,i,rs1[i]);
9019 if(!(current.is32>>rs1[i]&1))
9021 alloc_reg64(¤t,i,rs1[i]);
9025 //current.isconst=0;
9031 if(likely[i]==0) // BC1F/BC1T
9033 // TODO: Theoretically we can run out of registers here on x86.
9034 // The delay slot can allocate up to six, and we need to check
9035 // CSREG before executing the delay slot. Possibly we can drop
9036 // the cycle count and then reload it after checking that the
9037 // FPU is in a usable state, or don't do out-of-order execution.
9038 alloc_cc(¤t,i);
9039 dirty_reg(¤t,CCREG);
9040 alloc_reg(¤t,i,FSREG);
9041 alloc_reg(¤t,i,CSREG);
9042 if(itype[i+1]==FCOMP) {
9043 // The delay slot overwrites the branch condition.
9044 // Allocate the branch condition registers instead.
9045 alloc_cc(¤t,i);
9046 dirty_reg(¤t,CCREG);
9047 alloc_reg(¤t,i,CSREG);
9048 alloc_reg(¤t,i,FSREG);
9052 delayslot_alloc(¤t,i+1);
9053 alloc_reg(¤t,i+1,CSREG);
9057 // Don't alloc the delay slot yet because we might not execute it
9058 if(likely[i]) // BC1FL/BC1TL
9060 alloc_cc(¤t,i);
9061 dirty_reg(¤t,CCREG);
9062 alloc_reg(¤t,i,CSREG);
9063 alloc_reg(¤t,i,FSREG);
9069 imm16_alloc(¤t,i);
9073 load_alloc(¤t,i);
9077 store_alloc(¤t,i);
9080 alu_alloc(¤t,i);
9083 shift_alloc(¤t,i);
9086 multdiv_alloc(¤t,i);
9089 shiftimm_alloc(¤t,i);
9092 mov_alloc(¤t,i);
9095 cop0_alloc(¤t,i);
9099 cop1_alloc(¤t,i);
9102 c1ls_alloc(¤t,i);
9105 c2ls_alloc(¤t,i);
9108 c2op_alloc(¤t,i);
9111 fconv_alloc(¤t,i);
9114 float_alloc(¤t,i);
9117 fcomp_alloc(¤t,i);
9122 syscall_alloc(¤t,i);
9125 pagespan_alloc(¤t,i);
9129 // Drop the upper half of registers that have become 32-bit
9130 current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
9131 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9132 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9133 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9136 current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
9137 current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9138 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9139 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9143 // Create entry (branch target) regmap
9144 for(hr=0;hr<HOST_REGS;hr++)
9147 r=current.regmap[hr];
9149 if(r!=regmap_pre[i][hr]) {
9150 // TODO: delay slot (?)
9151 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9152 if(or<0||(r&63)>=TEMPREG){
9153 regs[i].regmap_entry[hr]=-1;
9157 // Just move it to a different register
9158 regs[i].regmap_entry[hr]=r;
9159 // If it was dirty before, it's still dirty
9160 if((regs[i].wasdirty>>or)&1) dirty_reg(¤t,r&63);
9167 regs[i].regmap_entry[hr]=0;
9171 if((current.u>>r)&1) {
9172 regs[i].regmap_entry[hr]=-1;
9173 //regs[i].regmap[hr]=-1;
9174 current.regmap[hr]=-1;
9176 regs[i].regmap_entry[hr]=r;
9179 if((current.uu>>(r&63))&1) {
9180 regs[i].regmap_entry[hr]=-1;
9181 //regs[i].regmap[hr]=-1;
9182 current.regmap[hr]=-1;
9184 regs[i].regmap_entry[hr]=r;
9188 // Branches expect CCREG to be allocated at the target
9189 if(regmap_pre[i][hr]==CCREG)
9190 regs[i].regmap_entry[hr]=CCREG;
9192 regs[i].regmap_entry[hr]=-1;
9195 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9197 /* Branch post-alloc */
9200 current.was32=current.is32;
9201 current.wasdirty=current.dirty;
9202 switch(itype[i-1]) {
9204 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9205 branch_regs[i-1].isconst=0;
9206 branch_regs[i-1].wasconst=0;
9207 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9208 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9209 alloc_cc(&branch_regs[i-1],i-1);
9210 dirty_reg(&branch_regs[i-1],CCREG);
9211 if(rt1[i-1]==31) { // JAL
9212 alloc_reg(&branch_regs[i-1],i-1,31);
9213 dirty_reg(&branch_regs[i-1],31);
9214 branch_regs[i-1].is32|=1LL<<31;
9216 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9217 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9220 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9221 branch_regs[i-1].isconst=0;
9222 branch_regs[i-1].wasconst=0;
9223 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9224 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9225 alloc_cc(&branch_regs[i-1],i-1);
9226 dirty_reg(&branch_regs[i-1],CCREG);
9227 alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
9228 if(rt1[i-1]!=0) { // JALR
9229 alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9230 dirty_reg(&branch_regs[i-1],rt1[i-1]);
9231 branch_regs[i-1].is32|=1LL<<rt1[i-1];
9234 if(rs1[i-1]==31) { // JALR
9235 alloc_reg(&branch_regs[i-1],i-1,RHASH);
9236 #ifndef HOST_IMM_ADDR32
9237 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9241 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9242 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9245 if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9247 alloc_cc(¤t,i-1);
9248 dirty_reg(¤t,CCREG);
9249 if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9250 (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9251 // The delay slot overwrote one of our conditions
9252 // Delay slot goes after the test (in order)
9253 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9254 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9255 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9258 delayslot_alloc(¤t,i);
9263 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9264 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9265 // Alloc the branch condition registers
9266 if(rs1[i-1]) alloc_reg(¤t,i-1,rs1[i-1]);
9267 if(rs2[i-1]) alloc_reg(¤t,i-1,rs2[i-1]);
9268 if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9270 if(rs1[i-1]) alloc_reg64(¤t,i-1,rs1[i-1]);
9271 if(rs2[i-1]) alloc_reg64(¤t,i-1,rs2[i-1]);
9274 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9275 branch_regs[i-1].isconst=0;
9276 branch_regs[i-1].wasconst=0;
9277 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9278 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9281 if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9283 alloc_cc(¤t,i-1);
9284 dirty_reg(¤t,CCREG);
9285 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9286 // The delay slot overwrote the branch condition
9287 // Delay slot goes after the test (in order)
9288 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9289 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9290 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9293 delayslot_alloc(¤t,i);
9298 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9299 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9300 // Alloc the branch condition register
9301 alloc_reg(¤t,i-1,rs1[i-1]);
9302 if(!(current.is32>>rs1[i-1]&1))
9304 alloc_reg64(¤t,i-1,rs1[i-1]);
9307 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9308 branch_regs[i-1].isconst=0;
9309 branch_regs[i-1].wasconst=0;
9310 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9311 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9314 // Alloc the delay slot in case the branch is taken
9315 if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9317 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9318 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9319 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9320 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9321 alloc_cc(&branch_regs[i-1],i);
9322 dirty_reg(&branch_regs[i-1],CCREG);
9323 delayslot_alloc(&branch_regs[i-1],i);
9324 branch_regs[i-1].isconst=0;
9325 alloc_reg(¤t,i,CCREG); // Not taken path
9326 dirty_reg(¤t,CCREG);
9327 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9330 if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9332 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9333 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9334 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9335 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9336 alloc_cc(&branch_regs[i-1],i);
9337 dirty_reg(&branch_regs[i-1],CCREG);
9338 delayslot_alloc(&branch_regs[i-1],i);
9339 branch_regs[i-1].isconst=0;
9340 alloc_reg(¤t,i,CCREG); // Not taken path
9341 dirty_reg(¤t,CCREG);
9342 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9346 //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9347 if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9349 alloc_cc(¤t,i-1);
9350 dirty_reg(¤t,CCREG);
9351 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9352 // The delay slot overwrote the branch condition
9353 // Delay slot goes after the test (in order)
9354 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9355 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9356 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9359 delayslot_alloc(¤t,i);
9364 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9365 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9366 // Alloc the branch condition register
9367 alloc_reg(¤t,i-1,rs1[i-1]);
9368 if(!(current.is32>>rs1[i-1]&1))
9370 alloc_reg64(¤t,i-1,rs1[i-1]);
9373 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9374 branch_regs[i-1].isconst=0;
9375 branch_regs[i-1].wasconst=0;
9376 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9377 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9380 // Alloc the delay slot in case the branch is taken
9381 if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9383 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9384 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9385 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9386 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9387 alloc_cc(&branch_regs[i-1],i);
9388 dirty_reg(&branch_regs[i-1],CCREG);
9389 delayslot_alloc(&branch_regs[i-1],i);
9390 branch_regs[i-1].isconst=0;
9391 alloc_reg(¤t,i,CCREG); // Not taken path
9392 dirty_reg(¤t,CCREG);
9393 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9395 // FIXME: BLTZAL/BGEZAL
9396 if(opcode2[i-1]&0x10) { // BxxZAL
9397 alloc_reg(&branch_regs[i-1],i-1,31);
9398 dirty_reg(&branch_regs[i-1],31);
9399 branch_regs[i-1].is32|=1LL<<31;
9403 if(likely[i-1]==0) // BC1F/BC1T
9405 alloc_cc(¤t,i-1);
9406 dirty_reg(¤t,CCREG);
9407 if(itype[i]==FCOMP) {
9408 // The delay slot overwrote the branch condition
9409 // Delay slot goes after the test (in order)
9410 delayslot_alloc(¤t,i);
9415 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9416 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9417 // Alloc the branch condition register
9418 alloc_reg(¤t,i-1,FSREG);
9420 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9421 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9425 // Alloc the delay slot in case the branch is taken
9426 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9427 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9428 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9429 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9430 alloc_cc(&branch_regs[i-1],i);
9431 dirty_reg(&branch_regs[i-1],CCREG);
9432 delayslot_alloc(&branch_regs[i-1],i);
9433 branch_regs[i-1].isconst=0;
9434 alloc_reg(¤t,i,CCREG); // Not taken path
9435 dirty_reg(¤t,CCREG);
9436 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9441 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9443 if(rt1[i-1]==31) // JAL/JALR
9445 // Subroutine call will return here, don't alloc any registers
9448 clear_all_regs(current.regmap);
9449 alloc_reg(¤t,i,CCREG);
9450 dirty_reg(¤t,CCREG);
9454 // Internal branch will jump here, match registers to caller
9455 current.is32=0x3FFFFFFFFLL;
9457 clear_all_regs(current.regmap);
9458 alloc_reg(¤t,i,CCREG);
9459 dirty_reg(¤t,CCREG);
9462 if(ba[j]==start+i*4+4) {
9463 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9464 current.is32=branch_regs[j].is32;
9465 current.dirty=branch_regs[j].dirty;
9470 if(ba[j]==start+i*4+4) {
9471 for(hr=0;hr<HOST_REGS;hr++) {
9472 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9473 current.regmap[hr]=-1;
9475 current.is32&=branch_regs[j].is32;
9476 current.dirty&=branch_regs[j].dirty;
9485 // Count cycles in between branches
9487 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
9492 else if(/*itype[i]==LOAD||*/itype[i]==STORE||itype[i]==C1LS) // load causes weird timing issues
9494 cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
9496 else if(itype[i]==C2LS)
9506 flush_dirty_uppers(¤t);
9508 regs[i].is32=current.is32;
9509 regs[i].dirty=current.dirty;
9510 regs[i].isconst=current.isconst;
9511 memcpy(constmap[i],current.constmap,sizeof(current.constmap));
9513 for(hr=0;hr<HOST_REGS;hr++) {
9514 if(hr!=EXCLUDE_REG&®s[i].regmap[hr]>=0) {
9515 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9516 regs[i].wasconst&=~(1<<hr);
9520 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9523 /* Pass 4 - Cull unused host registers */
9527 for (i=slen-1;i>=0;i--)
9530 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9532 if(ba[i]<start || ba[i]>=(start+slen*4))
9534 // Branch out of this block, don't need anything
9540 // Need whatever matches the target
9542 int t=(ba[i]-start)>>2;
9543 for(hr=0;hr<HOST_REGS;hr++)
9545 if(regs[i].regmap_entry[hr]>=0) {
9546 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9550 // Conditional branch may need registers for following instructions
9551 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9554 nr|=needed_reg[i+2];
9555 for(hr=0;hr<HOST_REGS;hr++)
9557 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9558 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9562 // Don't need stuff which is overwritten
9563 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9564 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9565 // Merge in delay slot
9566 for(hr=0;hr<HOST_REGS;hr++)
9569 // These are overwritten unless the branch is "likely"
9570 // and the delay slot is nullified if not taken
9571 if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9572 if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9574 if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9575 if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9576 if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9577 if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9578 if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9579 if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9580 if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9581 if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9582 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9583 if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9584 if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9586 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9587 if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9588 if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9590 if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
9591 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9592 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9596 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
9598 // SYSCALL instruction (software interrupt)
9601 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9603 // ERET instruction (return from interrupt)
9609 for(hr=0;hr<HOST_REGS;hr++) {
9610 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9611 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9612 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9613 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9617 for(hr=0;hr<HOST_REGS;hr++)
9619 // Overwritten registers are not needed
9620 if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9621 if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9622 if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9623 // Source registers are needed
9624 if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9625 if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9626 if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9627 if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9628 if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9629 if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9630 if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9631 if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9632 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9633 if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9634 if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9636 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
9637 if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9638 if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9640 if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
9641 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9642 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9644 // Don't store a register immediately after writing it,
9645 // may prevent dual-issue.
9646 // But do so if this is a branch target, otherwise we
9647 // might have to load the register before the branch.
9648 if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
9649 if((regmap_pre[i][hr]>0&®map_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
9650 (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
9651 if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9652 if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9654 if((regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
9655 (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
9656 if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9657 if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9661 // Cycle count is needed at branches. Assume it is needed at the target too.
9662 if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
9663 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9664 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9669 // Deallocate unneeded registers
9670 for(hr=0;hr<HOST_REGS;hr++)
9673 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
9674 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9675 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9676 (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
9678 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9681 regs[i].regmap[hr]=-1;
9682 regs[i].isconst&=~(1<<hr);
9683 if(i<slen-2) regmap_pre[i+2][hr]=-1;
9687 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9689 int d1=0,d2=0,map=0,temp=0;
9690 if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
9696 if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
9697 itype[i+1]==STORE || itype[i+1]==STORELR ||
9698 itype[i+1]==C1LS || itype[i+1]==C2LS)
9701 if(itype[i+1]==STORE || itype[i+1]==STORELR ||
9702 (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
9705 if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
9706 itype[i+1]==C1LS || itype[i+1]==C2LS)
9708 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9709 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9710 (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
9711 (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
9712 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9713 regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
9714 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
9715 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
9716 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
9717 regs[i].regmap[hr]!=map )
9719 regs[i].regmap[hr]=-1;
9720 regs[i].isconst&=~(1<<hr);
9721 if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
9722 (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
9723 (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
9724 (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
9725 (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
9726 branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
9727 (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
9728 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
9729 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
9730 branch_regs[i].regmap[hr]!=map)
9732 branch_regs[i].regmap[hr]=-1;
9733 branch_regs[i].regmap_entry[hr]=-1;
9734 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9736 if(!likely[i]&&i<slen-2) {
9737 regmap_pre[i+2][hr]=-1;
9748 int d1=0,d2=0,map=-1,temp=-1;
9749 if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
9755 if(itype[i]==LOAD || itype[i]==LOADLR ||
9756 itype[i]==STORE || itype[i]==STORELR ||
9757 itype[i]==C1LS || itype[i]==C2LS)
9759 } else if(itype[i]==STORE || itype[i]==STORELR ||
9760 (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
9763 if(itype[i]==LOADLR || itype[i]==STORELR ||
9764 itype[i]==C1LS || itype[i]==C2LS)
9766 if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9767 (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
9768 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9769 regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
9770 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
9771 (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
9773 if(i<slen-1&&!is_ds[i]) {
9774 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
9775 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
9776 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
9778 printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
9779 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
9781 regmap_pre[i+1][hr]=-1;
9782 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
9784 regs[i].regmap[hr]=-1;
9785 regs[i].isconst&=~(1<<hr);
9793 /* Pass 5 - Pre-allocate registers */
9795 // If a register is allocated during a loop, try to allocate it for the
9796 // entire loop, if possible. This avoids loading/storing registers
9797 // inside of the loop.
9799 signed char f_regmap[HOST_REGS];
9800 clear_all_regs(f_regmap);
9801 for(i=0;i<slen-1;i++)
9803 if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9805 if(ba[i]>=start && ba[i]<(start+i*4))
9806 if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
9807 ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
9808 ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
9809 ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
9810 ||itype[i+1]==FCOMP||itype[i+1]==FCONV
9811 ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
9813 int t=(ba[i]-start)>>2;
9814 if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
9815 if(t<2||(itype[t-2]!=UJUMP)) // call/ret assumes no registers allocated
9816 for(hr=0;hr<HOST_REGS;hr++)
9818 if(regs[i].regmap[hr]>64) {
9819 if(!((regs[i].dirty>>hr)&1))
9820 f_regmap[hr]=regs[i].regmap[hr];
9821 else f_regmap[hr]=-1;
9823 else if(regs[i].regmap[hr]>=0) {
9824 if(f_regmap[hr]!=regs[i].regmap[hr]) {
9825 // dealloc old register
9827 for(n=0;n<HOST_REGS;n++)
9829 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
9831 // and alloc new one
9832 f_regmap[hr]=regs[i].regmap[hr];
9835 if(branch_regs[i].regmap[hr]>64) {
9836 if(!((branch_regs[i].dirty>>hr)&1))
9837 f_regmap[hr]=branch_regs[i].regmap[hr];
9838 else f_regmap[hr]=-1;
9840 else if(branch_regs[i].regmap[hr]>=0) {
9841 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
9842 // dealloc old register
9844 for(n=0;n<HOST_REGS;n++)
9846 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
9848 // and alloc new one
9849 f_regmap[hr]=branch_regs[i].regmap[hr];
9853 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
9854 f_regmap[hr]=branch_regs[i].regmap[hr];
9856 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
9857 f_regmap[hr]=branch_regs[i].regmap[hr];
9859 // Avoid dirty->clean transition
9860 #ifdef DESTRUCTIVE_WRITEBACK
9861 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
9863 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
9864 // case above, however it's always a good idea. We can't hoist the
9865 // load if the register was already allocated, so there's no point
9866 // wasting time analyzing most of these cases. It only "succeeds"
9867 // when the mapping was different and the load can be replaced with
9868 // a mov, which is of negligible benefit. So such cases are
9870 if(f_regmap[hr]>0) {
9871 if(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0) {
9875 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9876 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
9877 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
9879 // NB This can exclude the case where the upper-half
9880 // register is lower numbered than the lower-half
9881 // register. Not sure if it's worth fixing...
9882 if(get_reg(regs[j].regmap,r&63)<0) break;
9883 if(get_reg(regs[j].regmap_entry,r&63)<0) break;
9884 if(regs[j].is32&(1LL<<(r&63))) break;
9886 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
9887 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9889 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
9890 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
9892 if(get_reg(regs[i].regmap,r&63)<0) break;
9893 if(get_reg(branch_regs[i].regmap,r&63)<0) break;
9896 while(k>1&®s[k-1].regmap[hr]==-1) {
9897 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
9898 //printf("no free regs for store %x\n",start+(k-1)*4);
9901 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
9902 //printf("no-match due to different register\n");
9905 if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
9906 //printf("no-match due to branch\n");
9909 // call/ret fast path assumes no registers allocated
9910 if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)) {
9914 // NB This can exclude the case where the upper-half
9915 // register is lower numbered than the lower-half
9916 // register. Not sure if it's worth fixing...
9917 if(get_reg(regs[k-1].regmap,r&63)<0) break;
9918 if(regs[k-1].is32&(1LL<<(r&63))) break;
9923 if((regs[k].is32&(1LL<<f_regmap[hr]))!=
9924 (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
9925 //printf("bad match after branch\n");
9929 if(regs[k-1].regmap[hr]==f_regmap[hr]&®map_pre[k][hr]==f_regmap[hr]) {
9930 //printf("Extend r%d, %x ->\n",hr,start+k*4);
9932 regs[k].regmap_entry[hr]=f_regmap[hr];
9933 regs[k].regmap[hr]=f_regmap[hr];
9934 regmap_pre[k+1][hr]=f_regmap[hr];
9935 regs[k].wasdirty&=~(1<<hr);
9936 regs[k].dirty&=~(1<<hr);
9937 regs[k].wasdirty|=(1<<hr)®s[k-1].dirty;
9938 regs[k].dirty|=(1<<hr)®s[k].wasdirty;
9939 regs[k].wasconst&=~(1<<hr);
9940 regs[k].isconst&=~(1<<hr);
9945 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
9948 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
9949 if(regs[i-1].regmap[hr]==f_regmap[hr]&®map_pre[i][hr]==f_regmap[hr]) {
9950 //printf("OK fill %x (r%d)\n",start+i*4,hr);
9951 regs[i].regmap_entry[hr]=f_regmap[hr];
9952 regs[i].regmap[hr]=f_regmap[hr];
9953 regs[i].wasdirty&=~(1<<hr);
9954 regs[i].dirty&=~(1<<hr);
9955 regs[i].wasdirty|=(1<<hr)®s[i-1].dirty;
9956 regs[i].dirty|=(1<<hr)®s[i-1].dirty;
9957 regs[i].wasconst&=~(1<<hr);
9958 regs[i].isconst&=~(1<<hr);
9959 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
9960 branch_regs[i].wasdirty&=~(1<<hr);
9961 branch_regs[i].wasdirty|=(1<<hr)®s[i].dirty;
9962 branch_regs[i].regmap[hr]=f_regmap[hr];
9963 branch_regs[i].dirty&=~(1<<hr);
9964 branch_regs[i].dirty|=(1<<hr)®s[i].dirty;
9965 branch_regs[i].wasconst&=~(1<<hr);
9966 branch_regs[i].isconst&=~(1<<hr);
9967 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
9968 regmap_pre[i+2][hr]=f_regmap[hr];
9969 regs[i+2].wasdirty&=~(1<<hr);
9970 regs[i+2].wasdirty|=(1<<hr)®s[i].dirty;
9971 assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
9972 (regs[i+2].was32&(1LL<<f_regmap[hr])));
9977 // Alloc register clean at beginning of loop,
9978 // but may dirty it in pass 6
9979 regs[k].regmap_entry[hr]=f_regmap[hr];
9980 regs[k].regmap[hr]=f_regmap[hr];
9981 regs[k].dirty&=~(1<<hr);
9982 regs[k].wasconst&=~(1<<hr);
9983 regs[k].isconst&=~(1<<hr);
9984 if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) {
9985 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
9986 branch_regs[k].regmap[hr]=f_regmap[hr];
9987 branch_regs[k].dirty&=~(1<<hr);
9988 branch_regs[k].wasconst&=~(1<<hr);
9989 branch_regs[k].isconst&=~(1<<hr);
9990 if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
9991 regmap_pre[k+2][hr]=f_regmap[hr];
9992 regs[k+2].wasdirty&=~(1<<hr);
9993 assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))==
9994 (regs[k+2].was32&(1LL<<f_regmap[hr])));
9999 regmap_pre[k+1][hr]=f_regmap[hr];
10000 regs[k+1].wasdirty&=~(1<<hr);
10003 if(regs[j].regmap[hr]==f_regmap[hr])
10004 regs[j].regmap_entry[hr]=f_regmap[hr];
10008 if(regs[j].regmap[hr]>=0)
10010 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
10011 //printf("no-match due to different register\n");
10014 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
10015 //printf("32/64 mismatch %x %d\n",start+j*4,hr);
10018 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10020 // Stop on unconditional branch
10023 if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
10026 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
10029 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
10032 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
10033 //printf("no-match due to different register (branch)\n");
10037 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10038 //printf("No free regs for store %x\n",start+j*4);
10041 if(f_regmap[hr]>=64) {
10042 if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
10047 if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
10059 for(hr=0;hr<HOST_REGS;hr++)
10061 if(hr!=EXCLUDE_REG) {
10062 if(regs[i].regmap[hr]>64) {
10063 if(!((regs[i].dirty>>hr)&1))
10064 f_regmap[hr]=regs[i].regmap[hr];
10066 else if(regs[i].regmap[hr]>=0) {
10067 if(f_regmap[hr]!=regs[i].regmap[hr]) {
10068 // dealloc old register
10070 for(n=0;n<HOST_REGS;n++)
10072 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10074 // and alloc new one
10075 f_regmap[hr]=regs[i].regmap[hr];
10078 else if(regs[i].regmap[hr]<0) count++;
10081 // Try to restore cycle count at branch targets
10083 for(j=i;j<slen-1;j++) {
10084 if(regs[j].regmap[HOST_CCREG]!=-1) break;
10085 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10086 //printf("no free regs for store %x\n",start+j*4);
10090 if(regs[j].regmap[HOST_CCREG]==CCREG) {
10092 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
10094 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10095 regs[k].regmap[HOST_CCREG]=CCREG;
10096 regmap_pre[k+1][HOST_CCREG]=CCREG;
10097 regs[k+1].wasdirty|=1<<HOST_CCREG;
10098 regs[k].dirty|=1<<HOST_CCREG;
10099 regs[k].wasconst&=~(1<<HOST_CCREG);
10100 regs[k].isconst&=~(1<<HOST_CCREG);
10103 regs[j].regmap_entry[HOST_CCREG]=CCREG;
10105 // Work backwards from the branch target
10106 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
10108 //printf("Extend backwards\n");
10111 while(regs[k-1].regmap[HOST_CCREG]==-1) {
10112 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10113 //printf("no free regs for store %x\n",start+(k-1)*4);
10118 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
10119 //printf("Extend CC, %x ->\n",start+k*4);
10121 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10122 regs[k].regmap[HOST_CCREG]=CCREG;
10123 regmap_pre[k+1][HOST_CCREG]=CCREG;
10124 regs[k+1].wasdirty|=1<<HOST_CCREG;
10125 regs[k].dirty|=1<<HOST_CCREG;
10126 regs[k].wasconst&=~(1<<HOST_CCREG);
10127 regs[k].isconst&=~(1<<HOST_CCREG);
10132 //printf("Fail Extend CC, %x ->\n",start+k*4);
10136 if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
10137 itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
10138 itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
10139 itype[i]!=FCONV&&itype[i]!=FCOMP)
10141 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
10146 // This allocates registers (if possible) one instruction prior
10147 // to use, which can avoid a load-use penalty on certain CPUs.
10148 for(i=0;i<slen-1;i++)
10150 if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10154 if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
10155 ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
10158 if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10160 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10162 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10163 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10164 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10165 regs[i].isconst&=~(1<<hr);
10166 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10167 constmap[i][hr]=constmap[i+1][hr];
10168 regs[i+1].wasdirty&=~(1<<hr);
10169 regs[i].dirty&=~(1<<hr);
10174 if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10176 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10178 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10179 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10180 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10181 regs[i].isconst&=~(1<<hr);
10182 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10183 constmap[i][hr]=constmap[i+1][hr];
10184 regs[i+1].wasdirty&=~(1<<hr);
10185 regs[i].dirty&=~(1<<hr);
10189 if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10190 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10192 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10194 regs[i].regmap[hr]=rs1[i+1];
10195 regmap_pre[i+1][hr]=rs1[i+1];
10196 regs[i+1].regmap_entry[hr]=rs1[i+1];
10197 regs[i].isconst&=~(1<<hr);
10198 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10199 constmap[i][hr]=constmap[i+1][hr];
10200 regs[i+1].wasdirty&=~(1<<hr);
10201 regs[i].dirty&=~(1<<hr);
10205 if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10206 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10208 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10210 regs[i].regmap[hr]=rs1[i+1];
10211 regmap_pre[i+1][hr]=rs1[i+1];
10212 regs[i+1].regmap_entry[hr]=rs1[i+1];
10213 regs[i].isconst&=~(1<<hr);
10214 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10215 constmap[i][hr]=constmap[i+1][hr];
10216 regs[i+1].wasdirty&=~(1<<hr);
10217 regs[i].dirty&=~(1<<hr);
10221 #ifndef HOST_IMM_ADDR32
10222 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
10223 hr=get_reg(regs[i+1].regmap,TLREG);
10225 int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10226 if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10228 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10230 regs[i].regmap[hr]=MGEN1+((i+1)&1);
10231 regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10232 regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10233 regs[i].isconst&=~(1<<hr);
10234 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10235 constmap[i][hr]=constmap[i+1][hr];
10236 regs[i+1].wasdirty&=~(1<<hr);
10237 regs[i].dirty&=~(1<<hr);
10239 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10241 // move it to another register
10242 regs[i+1].regmap[hr]=-1;
10243 regmap_pre[i+2][hr]=-1;
10244 regs[i+1].regmap[nr]=TLREG;
10245 regmap_pre[i+2][nr]=TLREG;
10246 regs[i].regmap[nr]=MGEN1+((i+1)&1);
10247 regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10248 regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10249 regs[i].isconst&=~(1<<nr);
10250 regs[i+1].isconst&=~(1<<nr);
10251 regs[i].dirty&=~(1<<nr);
10252 regs[i+1].wasdirty&=~(1<<nr);
10253 regs[i+1].dirty&=~(1<<nr);
10254 regs[i+2].wasdirty&=~(1<<nr);
10260 if(itype[i+1]==STORE||itype[i+1]==STORELR
10261 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
10262 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10263 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10264 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10265 else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10267 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10269 regs[i].regmap[hr]=rs1[i+1];
10270 regmap_pre[i+1][hr]=rs1[i+1];
10271 regs[i+1].regmap_entry[hr]=rs1[i+1];
10272 regs[i].isconst&=~(1<<hr);
10273 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10274 constmap[i][hr]=constmap[i+1][hr];
10275 regs[i+1].wasdirty&=~(1<<hr);
10276 regs[i].dirty&=~(1<<hr);
10280 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
10281 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10283 hr=get_reg(regs[i+1].regmap,FTEMP);
10285 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10287 regs[i].regmap[hr]=rs1[i+1];
10288 regmap_pre[i+1][hr]=rs1[i+1];
10289 regs[i+1].regmap_entry[hr]=rs1[i+1];
10290 regs[i].isconst&=~(1<<hr);
10291 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10292 constmap[i][hr]=constmap[i+1][hr];
10293 regs[i+1].wasdirty&=~(1<<hr);
10294 regs[i].dirty&=~(1<<hr);
10296 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10298 // move it to another register
10299 regs[i+1].regmap[hr]=-1;
10300 regmap_pre[i+2][hr]=-1;
10301 regs[i+1].regmap[nr]=FTEMP;
10302 regmap_pre[i+2][nr]=FTEMP;
10303 regs[i].regmap[nr]=rs1[i+1];
10304 regmap_pre[i+1][nr]=rs1[i+1];
10305 regs[i+1].regmap_entry[nr]=rs1[i+1];
10306 regs[i].isconst&=~(1<<nr);
10307 regs[i+1].isconst&=~(1<<nr);
10308 regs[i].dirty&=~(1<<nr);
10309 regs[i+1].wasdirty&=~(1<<nr);
10310 regs[i+1].dirty&=~(1<<nr);
10311 regs[i+2].wasdirty&=~(1<<nr);
10315 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
10316 if(itype[i+1]==LOAD)
10317 hr=get_reg(regs[i+1].regmap,rt1[i+1]);
10318 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
10319 hr=get_reg(regs[i+1].regmap,FTEMP);
10320 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
10321 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10322 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10324 if(hr>=0&®s[i].regmap[hr]<0) {
10325 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10326 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10327 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10328 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10329 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10330 regs[i].isconst&=~(1<<hr);
10331 regs[i+1].wasdirty&=~(1<<hr);
10332 regs[i].dirty&=~(1<<hr);
10341 /* Pass 6 - Optimize clean/dirty state */
10342 clean_registers(0,slen-1,1);
10344 /* Pass 7 - Identify 32-bit registers */
10350 for (i=slen-1;i>=0;i--)
10353 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10355 if(ba[i]<start || ba[i]>=(start+slen*4))
10357 // Branch out of this block, don't need anything
10363 // Need whatever matches the target
10364 // (and doesn't get overwritten by the delay slot instruction)
10366 int t=(ba[i]-start)>>2;
10367 if(ba[i]>start+i*4) {
10369 if(!(requires_32bit[t]&~regs[i].was32))
10370 r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10373 //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10374 // r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10375 if(!(pr32[t]&~regs[i].was32))
10376 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10379 // Conditional branch may need registers for following instructions
10380 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10383 r32|=requires_32bit[i+2];
10384 r32&=regs[i].was32;
10385 // Mark this address as a branch target since it may be called
10386 // upon return from interrupt
10390 // Merge in delay slot
10392 // These are overwritten unless the branch is "likely"
10393 // and the delay slot is nullified if not taken
10394 r32&=~(1LL<<rt1[i+1]);
10395 r32&=~(1LL<<rt2[i+1]);
10397 // Assume these are needed (delay slot)
10400 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10404 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10406 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10408 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10410 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10412 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10415 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
10417 // SYSCALL instruction (software interrupt)
10420 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10422 // ERET instruction (return from interrupt)
10426 r32&=~(1LL<<rt1[i]);
10427 r32&=~(1LL<<rt2[i]);
10430 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10434 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10436 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
10438 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
10440 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
10442 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
10444 requires_32bit[i]=r32;
10446 // Dirty registers which are 32-bit, require 32-bit input
10447 // as they will be written as 32-bit values
10448 for(hr=0;hr<HOST_REGS;hr++)
10450 if(regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64) {
10451 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
10452 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
10453 requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
10457 //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
10461 if(itype[slen-1]==SPAN) {
10462 bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
10465 /* Debug/disassembly */
10466 if((void*)assem_debug==(void*)printf)
10467 for(i=0;i<slen;i++)
10471 for(r=1;r<=CCREG;r++) {
10472 if((unneeded_reg[i]>>r)&1) {
10473 if(r==HIREG) printf(" HI");
10474 else if(r==LOREG) printf(" LO");
10475 else printf(" r%d",r);
10480 for(r=1;r<=CCREG;r++) {
10481 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
10482 if(r==HIREG) printf(" HI");
10483 else if(r==LOREG) printf(" LO");
10484 else printf(" r%d",r);
10488 for(r=0;r<=CCREG;r++) {
10489 //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10490 if((regs[i].was32>>r)&1) {
10491 if(r==CCREG) printf(" CC");
10492 else if(r==HIREG) printf(" HI");
10493 else if(r==LOREG) printf(" LO");
10494 else printf(" r%d",r);
10499 #if defined(__i386__) || defined(__x86_64__)
10500 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
10503 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
10506 if(needed_reg[i]&1) printf("eax ");
10507 if((needed_reg[i]>>1)&1) printf("ecx ");
10508 if((needed_reg[i]>>2)&1) printf("edx ");
10509 if((needed_reg[i]>>3)&1) printf("ebx ");
10510 if((needed_reg[i]>>5)&1) printf("ebp ");
10511 if((needed_reg[i]>>6)&1) printf("esi ");
10512 if((needed_reg[i]>>7)&1) printf("edi ");
10514 for(r=0;r<=CCREG;r++) {
10515 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10516 if((requires_32bit[i]>>r)&1) {
10517 if(r==CCREG) printf(" CC");
10518 else if(r==HIREG) printf(" HI");
10519 else if(r==LOREG) printf(" LO");
10520 else printf(" r%d",r);
10525 for(r=0;r<=CCREG;r++) {
10526 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10527 if((pr32[i]>>r)&1) {
10528 if(r==CCREG) printf(" CC");
10529 else if(r==HIREG) printf(" HI");
10530 else if(r==LOREG) printf(" LO");
10531 else printf(" r%d",r);
10534 if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
10536 #if defined(__i386__) || defined(__x86_64__)
10537 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
10539 if(regs[i].wasdirty&1) printf("eax ");
10540 if((regs[i].wasdirty>>1)&1) printf("ecx ");
10541 if((regs[i].wasdirty>>2)&1) printf("edx ");
10542 if((regs[i].wasdirty>>3)&1) printf("ebx ");
10543 if((regs[i].wasdirty>>5)&1) printf("ebp ");
10544 if((regs[i].wasdirty>>6)&1) printf("esi ");
10545 if((regs[i].wasdirty>>7)&1) printf("edi ");
10548 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
10550 if(regs[i].wasdirty&1) printf("r0 ");
10551 if((regs[i].wasdirty>>1)&1) printf("r1 ");
10552 if((regs[i].wasdirty>>2)&1) printf("r2 ");
10553 if((regs[i].wasdirty>>3)&1) printf("r3 ");
10554 if((regs[i].wasdirty>>4)&1) printf("r4 ");
10555 if((regs[i].wasdirty>>5)&1) printf("r5 ");
10556 if((regs[i].wasdirty>>6)&1) printf("r6 ");
10557 if((regs[i].wasdirty>>7)&1) printf("r7 ");
10558 if((regs[i].wasdirty>>8)&1) printf("r8 ");
10559 if((regs[i].wasdirty>>9)&1) printf("r9 ");
10560 if((regs[i].wasdirty>>10)&1) printf("r10 ");
10561 if((regs[i].wasdirty>>12)&1) printf("r12 ");
10564 disassemble_inst(i);
10565 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
10566 #if defined(__i386__) || defined(__x86_64__)
10567 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
10568 if(regs[i].dirty&1) printf("eax ");
10569 if((regs[i].dirty>>1)&1) printf("ecx ");
10570 if((regs[i].dirty>>2)&1) printf("edx ");
10571 if((regs[i].dirty>>3)&1) printf("ebx ");
10572 if((regs[i].dirty>>5)&1) printf("ebp ");
10573 if((regs[i].dirty>>6)&1) printf("esi ");
10574 if((regs[i].dirty>>7)&1) printf("edi ");
10577 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
10578 if(regs[i].dirty&1) printf("r0 ");
10579 if((regs[i].dirty>>1)&1) printf("r1 ");
10580 if((regs[i].dirty>>2)&1) printf("r2 ");
10581 if((regs[i].dirty>>3)&1) printf("r3 ");
10582 if((regs[i].dirty>>4)&1) printf("r4 ");
10583 if((regs[i].dirty>>5)&1) printf("r5 ");
10584 if((regs[i].dirty>>6)&1) printf("r6 ");
10585 if((regs[i].dirty>>7)&1) printf("r7 ");
10586 if((regs[i].dirty>>8)&1) printf("r8 ");
10587 if((regs[i].dirty>>9)&1) printf("r9 ");
10588 if((regs[i].dirty>>10)&1) printf("r10 ");
10589 if((regs[i].dirty>>12)&1) printf("r12 ");
10592 if(regs[i].isconst) {
10593 printf("constants: ");
10594 #if defined(__i386__) || defined(__x86_64__)
10595 if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
10596 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
10597 if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
10598 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
10599 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
10600 if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
10601 if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
10604 if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
10605 if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
10606 if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
10607 if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
10608 if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
10609 if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
10610 if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
10611 if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
10612 if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
10613 if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
10614 if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
10615 if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
10621 for(r=0;r<=CCREG;r++) {
10622 if((regs[i].is32>>r)&1) {
10623 if(r==CCREG) printf(" CC");
10624 else if(r==HIREG) printf(" HI");
10625 else if(r==LOREG) printf(" LO");
10626 else printf(" r%d",r);
10632 for(r=0;r<=CCREG;r++) {
10633 if((p32[i]>>r)&1) {
10634 if(r==CCREG) printf(" CC");
10635 else if(r==HIREG) printf(" HI");
10636 else if(r==LOREG) printf(" LO");
10637 else printf(" r%d",r);
10640 if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
10641 else printf("\n");*/
10642 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10643 #if defined(__i386__) || defined(__x86_64__)
10644 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
10645 if(branch_regs[i].dirty&1) printf("eax ");
10646 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
10647 if((branch_regs[i].dirty>>2)&1) printf("edx ");
10648 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
10649 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
10650 if((branch_regs[i].dirty>>6)&1) printf("esi ");
10651 if((branch_regs[i].dirty>>7)&1) printf("edi ");
10654 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
10655 if(branch_regs[i].dirty&1) printf("r0 ");
10656 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
10657 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
10658 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
10659 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
10660 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
10661 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
10662 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
10663 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
10664 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
10665 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
10666 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
10670 for(r=0;r<=CCREG;r++) {
10671 if((branch_regs[i].is32>>r)&1) {
10672 if(r==CCREG) printf(" CC");
10673 else if(r==HIREG) printf(" HI");
10674 else if(r==LOREG) printf(" LO");
10675 else printf(" r%d",r);
10683 /* Pass 8 - Assembly */
10684 linkcount=0;stubcount=0;
10685 ds=0;is_delayslot=0;
10687 uint64_t is32_pre=0;
10689 u_int beginning=(u_int)out;
10690 if((u_int)addr&1) {
10694 u_int instr_addr0_override=0;
10697 if (start == 0x80030000) {
10698 // nasty hack for fastbios thing
10699 instr_addr0_override=(u_int)out;
10700 emit_movimm(start,0);
10701 emit_readword((int)&pcaddr,1);
10702 emit_writeword(0,(int)&pcaddr);
10704 emit_jne((int)new_dyna_leave);
10707 for(i=0;i<slen;i++)
10709 //if(ds) printf("ds: ");
10710 if((void*)assem_debug==(void*)printf) disassemble_inst(i);
10712 ds=0; // Skip delay slot
10713 if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
10716 #ifndef DESTRUCTIVE_WRITEBACK
10717 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10719 wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
10720 unneeded_reg[i],unneeded_reg_upper[i]);
10721 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
10722 unneeded_reg[i],unneeded_reg_upper[i]);
10724 is32_pre=regs[i].is32;
10725 dirty_pre=regs[i].dirty;
10728 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10730 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
10731 unneeded_reg[i],unneeded_reg_upper[i]);
10732 loop_preload(regmap_pre[i],regs[i].regmap_entry);
10734 // branch target entry point
10735 instr_addr[i]=(u_int)out;
10736 assem_debug("<->\n");
10738 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&®s[i].regmap[HOST_CCREG]!=CCREG)
10739 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
10740 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
10741 address_generation(i,®s[i],regs[i].regmap_entry);
10742 load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
10743 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10745 // Load the delay slot registers if necessary
10746 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10747 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10748 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10749 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
10750 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
10751 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10755 // Preload registers for following instruction
10756 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10757 if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
10758 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10759 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10760 if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
10761 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
10763 // TODO: if(is_ooo(i)) address_generation(i+1);
10764 if(itype[i]==CJUMP||itype[i]==FJUMP)
10765 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
10766 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
10767 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10768 if(bt[i]) cop1_usable=0;
10772 alu_assemble(i,®s[i]);break;
10774 imm16_assemble(i,®s[i]);break;
10776 shift_assemble(i,®s[i]);break;
10778 shiftimm_assemble(i,®s[i]);break;
10780 load_assemble(i,®s[i]);break;
10782 loadlr_assemble(i,®s[i]);break;
10784 store_assemble(i,®s[i]);break;
10786 storelr_assemble(i,®s[i]);break;
10788 cop0_assemble(i,®s[i]);break;
10790 cop1_assemble(i,®s[i]);break;
10792 c1ls_assemble(i,®s[i]);break;
10794 cop2_assemble(i,®s[i]);break;
10796 c2ls_assemble(i,®s[i]);break;
10798 c2op_assemble(i,®s[i]);break;
10800 fconv_assemble(i,®s[i]);break;
10802 float_assemble(i,®s[i]);break;
10804 fcomp_assemble(i,®s[i]);break;
10806 multdiv_assemble(i,®s[i]);break;
10808 mov_assemble(i,®s[i]);break;
10810 syscall_assemble(i,®s[i]);break;
10812 hlecall_assemble(i,®s[i]);break;
10814 intcall_assemble(i,®s[i]);break;
10816 ujump_assemble(i,®s[i]);ds=1;break;
10818 rjump_assemble(i,®s[i]);ds=1;break;
10820 cjump_assemble(i,®s[i]);ds=1;break;
10822 sjump_assemble(i,®s[i]);ds=1;break;
10824 fjump_assemble(i,®s[i]);ds=1;break;
10826 pagespan_assemble(i,®s[i]);break;
10828 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10829 literal_pool(1024);
10831 literal_pool_jumpover(256);
10834 //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
10835 // If the block did not end with an unconditional branch,
10836 // add a jump to the next instruction.
10838 if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
10839 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10841 if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
10842 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10843 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10844 emit_loadreg(CCREG,HOST_CCREG);
10845 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10847 else if(!likely[i-2])
10849 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
10850 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
10854 store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
10855 assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
10857 add_to_linker((int)out,start+i*4,0);
10864 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10865 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10866 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10867 emit_loadreg(CCREG,HOST_CCREG);
10868 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10869 add_to_linker((int)out,start+i*4,0);
10873 // TODO: delay slot stubs?
10875 for(i=0;i<stubcount;i++)
10877 switch(stubs[i][0])
10885 do_readstub(i);break;
10890 do_writestub(i);break;
10892 do_ccstub(i);break;
10894 do_invstub(i);break;
10896 do_cop1stub(i);break;
10898 do_unalignedwritestub(i);break;
10902 if (instr_addr0_override)
10903 instr_addr[0] = instr_addr0_override;
10905 /* Pass 9 - Linker */
10906 for(i=0;i<linkcount;i++)
10908 assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
10910 if(!link_addr[i][2])
10913 void *addr=check_addr(link_addr[i][1]);
10914 emit_extjump(link_addr[i][0],link_addr[i][1]);
10916 set_jump_target(link_addr[i][0],(int)addr);
10917 add_link(link_addr[i][1],stub);
10919 else set_jump_target(link_addr[i][0],(int)stub);
10924 int target=(link_addr[i][1]-start)>>2;
10925 assert(target>=0&&target<slen);
10926 assert(instr_addr[target]);
10927 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10928 //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
10930 set_jump_target(link_addr[i][0],instr_addr[target]);
10934 // External Branch Targets (jump_in)
10935 if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
10936 for(i=0;i<slen;i++)
10940 if(instr_addr[i]) // TODO - delay slots (=null)
10942 u_int vaddr=start+i*4;
10943 u_int page=get_page(vaddr);
10944 u_int vpage=get_vpage(vaddr);
10946 //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
10948 if(!requires_32bit[i])
10953 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
10954 assem_debug("jump_in: %x\n",start+i*4);
10955 ll_add(jump_dirty+vpage,vaddr,(void *)out);
10956 int entry_point=do_dirty_stub(i);
10957 ll_add(jump_in+page,vaddr,(void *)entry_point);
10958 // If there was an existing entry in the hash table,
10959 // replace it with the new address.
10960 // Don't add new entries. We'll insert the
10961 // ones that actually get used in check_addr().
10962 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
10963 if(ht_bin[0]==vaddr) {
10964 ht_bin[1]=entry_point;
10966 if(ht_bin[2]==vaddr) {
10967 ht_bin[3]=entry_point;
10972 u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
10973 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
10974 assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
10975 //int entry_point=(int)out;
10976 ////assem_debug("entry_point: %x\n",entry_point);
10977 //load_regs_entry(i);
10978 //if(entry_point==(int)out)
10979 // entry_point=instr_addr[i];
10981 // emit_jmp(instr_addr[i]);
10982 //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
10983 ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
10984 int entry_point=do_dirty_stub(i);
10985 ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
10990 // Write out the literal pool if necessary
10992 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10994 if(((u_int)out)&7) emit_addnop(13);
10996 assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
10997 //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
10998 memcpy(copy,source,slen*4);
11002 __clear_cache((void *)beginning,out);
11005 // If we're within 256K of the end of the buffer,
11006 // start over from the beginning. (Is 256K enough?)
11007 if((int)out>BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
11009 // Trap writes to any of the pages we compiled
11010 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
11012 #ifndef DISABLE_TLB
11013 memory_map[i]|=0x40000000;
11014 if((signed int)start>=(signed int)0xC0000000) {
11016 j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
11018 memory_map[j]|=0x40000000;
11019 //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
11024 /* Pass 10 - Free memory by expiring oldest blocks */
11026 int end=((((int)out-BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
11027 while(expirep!=end)
11029 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
11030 int base=BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
11031 inv_debug("EXP: Phase %d\n",expirep);
11032 switch((expirep>>11)&3)
11035 // Clear jump_in and jump_dirty
11036 ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
11037 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
11038 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
11039 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
11043 ll_kill_pointers(jump_out[expirep&2047],base,shift);
11044 ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
11047 // Clear hash table
11048 for(i=0;i<32;i++) {
11049 int *ht_bin=hash_table[((expirep&2047)<<5)+i];
11050 if((ht_bin[3]>>shift)==(base>>shift) ||
11051 ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11052 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
11053 ht_bin[2]=ht_bin[3]=-1;
11055 if((ht_bin[1]>>shift)==(base>>shift) ||
11056 ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11057 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
11058 ht_bin[0]=ht_bin[2];
11059 ht_bin[1]=ht_bin[3];
11060 ht_bin[2]=ht_bin[3]=-1;
11067 if((expirep&2047)==0)
11070 ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
11071 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
11074 expirep=(expirep+1)&65535;
11079 // vim:shiftwidth=2:expandtab