libpcsxcore/new_dynarec/new_dynarec.c

   1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
   2  *   Mupen64plus - new_dynarec.c                                           *
   3  *   Copyright (C) 2009-2010 Ari64                                         *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.          *
  19  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
  20
  21 #include <stdlib.h>
  22 #include <stdint.h> //include for uint64_t
  23 #include <assert.h>
  24
  25 #include "emu_if.h" //emulator interface
  26
  27 #include <sys/mman.h>
  28
  29 #ifdef __i386__
  30 #include "assem_x86.h"
  31 #endif
  32 #ifdef __x86_64__
  33 #include "assem_x64.h"
  34 #endif
  35 #ifdef __arm__
  36 #include "assem_arm.h"
  37 #endif
  38
  39 #define MAXBLOCK 4096
  40 #define MAX_OUTPUT_BLOCK_SIZE 262144
  41 #define CLOCK_DIVIDER 2
  42
  43 struct regstat
  44 {
  45   signed char regmap_entry[HOST_REGS];
  46   signed char regmap[HOST_REGS];
  47   uint64_t was32;
  48   uint64_t is32;
  49   uint64_t wasdirty;
  50   uint64_t dirty;
  51   uint64_t u;
  52   uint64_t uu;
  53   u_int wasconst;
  54   u_int isconst;
  55   uint64_t constmap[HOST_REGS];
  56 };
  57
  58 struct ll_entry
  59 {
  60   u_int vaddr;
  61   u_int reg32;
  62   void *addr;
  63   struct ll_entry *next;
  64 };
  65
  66   u_int start;
  67   u_int *source;
  68   u_int pagelimit;
  69   char insn[MAXBLOCK][10];
  70   u_char itype[MAXBLOCK];
  71   u_char opcode[MAXBLOCK];
  72   u_char opcode2[MAXBLOCK];
  73   u_char bt[MAXBLOCK];
  74   u_char rs1[MAXBLOCK];
  75   u_char rs2[MAXBLOCK];
  76   u_char rt1[MAXBLOCK];
  77   u_char rt2[MAXBLOCK];
  78   u_char us1[MAXBLOCK];
  79   u_char us2[MAXBLOCK];
  80   u_char dep1[MAXBLOCK];
  81   u_char dep2[MAXBLOCK];
  82   u_char lt1[MAXBLOCK];
  83   int imm[MAXBLOCK];
  84   u_int ba[MAXBLOCK];
  85   char likely[MAXBLOCK];
  86   char is_ds[MAXBLOCK];
  87   uint64_t unneeded_reg[MAXBLOCK];
  88   uint64_t unneeded_reg_upper[MAXBLOCK];
  89   uint64_t branch_unneeded_reg[MAXBLOCK];
  90   uint64_t branch_unneeded_reg_upper[MAXBLOCK];
  91   uint64_t p32[MAXBLOCK];
  92   uint64_t pr32[MAXBLOCK];
  93   signed char regmap_pre[MAXBLOCK][HOST_REGS];
  94   signed char regmap[MAXBLOCK][HOST_REGS];
  95   signed char regmap_entry[MAXBLOCK][HOST_REGS];
  96   uint64_t constmap[MAXBLOCK][HOST_REGS];
  97   uint64_t known_value[HOST_REGS];
  98   u_int known_reg;
  99   struct regstat regs[MAXBLOCK];
 100   struct regstat branch_regs[MAXBLOCK];
 101   u_int needed_reg[MAXBLOCK];
 102   uint64_t requires_32bit[MAXBLOCK];
 103   u_int wont_dirty[MAXBLOCK];
 104   u_int will_dirty[MAXBLOCK];
 105   int ccadj[MAXBLOCK];
 106   int slen;
 107   u_int instr_addr[MAXBLOCK];
 108   u_int link_addr[MAXBLOCK][3];
 109   int linkcount;
 110   u_int stubs[MAXBLOCK*3][8];
 111   int stubcount;
 112   u_int literals[1024][2];
 113   int literalcount;
 114   int is_delayslot;
 115   int cop1_usable;
 116   u_char *out;
 117   struct ll_entry *jump_in[4096];
 118   struct ll_entry *jump_out[4096];
 119   struct ll_entry *jump_dirty[4096];
 120   u_int hash_table[65536][4]  __attribute__((aligned(16)));
 121   char shadow[1048576]  __attribute__((aligned(16)));
 122   void *copy;
 123   int expirep;
 124   u_int using_tlb;
 125   u_int stop_after_jal;
 126   extern u_char restore_candidate[512];
 127   extern int cycle_count;
 128
 129   /* registers that may be allocated */
 130   /* 1-31 gpr */
 131 #define HIREG 32 // hi
 132 #define LOREG 33 // lo
 133 #define FSREG 34 // FPU status (FCSR)
 134 #define CSREG 35 // Coprocessor status
 135 #define CCREG 36 // Cycle count
 136 #define INVCP 37 // Pointer to invalid_code
 137 #define TEMPREG 38
 138 #define FTEMP 38 // FPU/LDL/LDR temporary register
 139 #define PTEMP 39 // Prefetch temporary register
 140 #define TLREG 40 // TLB mapping offset
 141 #define RHASH 41 // Return address hash
 142 #define RHTBL 42 // Return address hash table address
 143 #define RTEMP 43 // JR/JALR address register
 144 #define MAXREG 43
 145 #define AGEN1 44 // Address generation temporary register
 146 #define AGEN2 45 // Address generation temporary register
 147 #define MGEN1 46 // Maptable address generation temporary register
 148 #define MGEN2 47 // Maptable address generation temporary register
 149 #define BTREG 48 // Branch target temporary register
 150
 151   /* instruction types */
 152 #define NOP 0     // No operation
 153 #define LOAD 1    // Load
 154 #define STORE 2   // Store
 155 #define LOADLR 3  // Unaligned load
 156 #define STORELR 4 // Unaligned store
 157 #define MOV 5     // Move
 158 #define ALU 6     // Arithmetic/logic
 159 #define MULTDIV 7 // Multiply/divide
 160 #define SHIFT 8   // Shift by register
 161 #define SHIFTIMM 9// Shift by immediate
 162 #define IMM16 10  // 16-bit immediate
 163 #define RJUMP 11  // Unconditional jump to register
 164 #define UJUMP 12  // Unconditional jump
 165 #define CJUMP 13  // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
 166 #define SJUMP 14  // Conditional branch (regimm format)
 167 #define COP0 15   // Coprocessor 0
 168 #define COP1 16   // Coprocessor 1
 169 #define C1LS 17   // Coprocessor 1 load/store
 170 #define FJUMP 18  // Conditional branch (floating point)
 171 #define FLOAT 19  // Floating point unit
 172 #define FCONV 20  // Convert integer to float
 173 #define FCOMP 21  // Floating point compare (sets FSREG)
 174 #define SYSCALL 22// SYSCALL
 175 #define OTHER 23  // Other
 176 #define SPAN 24   // Branch/delay slot spans 2 pages
 177 #define NI 25     // Not implemented
 178 #define HLECALL 26// PCSX fake opcodes for HLE
 179 #define COP2 27   // Coprocessor 2 move
 180 #define C2LS 28   // Coprocessor 2 load/store
 181 #define C2OP 29   // Coprocessor 2 operation
 182 #define INTCALL 30// Call interpreter to handle rare corner cases
 183
 184   /* stubs */
 185 #define CC_STUB 1
 186 #define FP_STUB 2
 187 #define LOADB_STUB 3
 188 #define LOADH_STUB 4
 189 #define LOADW_STUB 5
 190 #define LOADD_STUB 6
 191 #define LOADBU_STUB 7
 192 #define LOADHU_STUB 8
 193 #define STOREB_STUB 9
 194 #define STOREH_STUB 10
 195 #define STOREW_STUB 11
 196 #define STORED_STUB 12
 197 #define STORELR_STUB 13
 198 #define INVCODE_STUB 14
 199
 200   /* branch codes */
 201 #define TAKEN 1
 202 #define NOTTAKEN 2
 203 #define NULLDS 3
 204
 205 // asm linkage
 206 int new_recompile_block(int addr);
 207 void *get_addr_ht(u_int vaddr);
 208 void invalidate_block(u_int block);
 209 void invalidate_addr(u_int addr);
 210 void remove_hash(int vaddr);
 211 void jump_vaddr();
 212 void dyna_linker();
 213 void dyna_linker_ds();
 214 void verify_code();
 215 void verify_code_vm();
 216 void verify_code_ds();
 217 void cc_interrupt();
 218 void fp_exception();
 219 void fp_exception_ds();
 220 void jump_syscall();
 221 void jump_syscall_hle();
 222 void jump_eret();
 223 void jump_hlecall();
 224 void jump_intcall();
 225 void new_dyna_leave();
 226
 227 // TLB
 228 void TLBWI_new();
 229 void TLBWR_new();
 230 void read_nomem_new();
 231 void read_nomemb_new();
 232 void read_nomemh_new();
 233 void read_nomemd_new();
 234 void write_nomem_new();
 235 void write_nomemb_new();
 236 void write_nomemh_new();
 237 void write_nomemd_new();
 238 void write_rdram_new();
 239 void write_rdramb_new();
 240 void write_rdramh_new();
 241 void write_rdramd_new();
 242 extern u_int memory_map[1048576];
 243
 244 // Needed by assembler
 245 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
 246 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
 247 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
 248 void load_all_regs(signed char i_regmap[]);
 249 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
 250 void load_regs_entry(int t);
 251 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
 252
 253 int tracedebug=0;
 254
 255 //#define DEBUG_CYCLE_COUNT 1
 256
 257 void nullf() {}
 258 //#define assem_debug printf
 259 //#define inv_debug printf
 260 #define assem_debug nullf
 261 #define inv_debug nullf
 262
 263 static void tlb_hacks()
 264 {
 265 #ifndef DISABLE_TLB
 266   // Goldeneye hack
 267   if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
 268   {
 269     u_int addr;
 270     int n;
 271     switch (ROM_HEADER->Country_code&0xFF)
 272     {
 273       case 0x45: // U
 274         addr=0x34b30;
 275         break;
 276       case 0x4A: // J
 277         addr=0x34b70;
 278         break;
 279       case 0x50: // E
 280         addr=0x329f0;
 281         break;
 282       default:
 283         // Unknown country code
 284         addr=0;
 285         break;
 286     }
 287     u_int rom_addr=(u_int)rom;
 288     #ifdef ROM_COPY
 289     // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
 290     // in the lower 4G of memory to use this hack.  Copy it if necessary.
 291     if((void *)rom>(void *)0xffffffff) {
 292       munmap(ROM_COPY, 67108864);
 293       if(mmap(ROM_COPY, 12582912,
 294               PROT_READ | PROT_WRITE,
 295               MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
 296               -1, 0) <= 0) {printf("mmap() failed\n");}
 297       memcpy(ROM_COPY,rom,12582912);
 298       rom_addr=(u_int)ROM_COPY;
 299     }
 300     #endif
 301     if(addr) {
 302       for(n=0x7F000;n<0x80000;n++) {
 303         memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
 304       }
 305     }
 306   }
 307 #endif
 308 }
 309
 310 static u_int get_page(u_int vaddr)
 311 {
 312 #ifndef PCSX
 313   u_int page=(vaddr^0x80000000)>>12;
 314 #else
 315   u_int page=vaddr&~0xe0000000;
 316   if (page < 0x1000000)
 317     page &= ~0x0e00000; // RAM mirrors
 318   page>>=12;
 319 #endif
 320 #ifndef DISABLE_TLB
 321   if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
 322 #endif
 323   if(page>2048) page=2048+(page&2047);
 324   return page;
 325 }
 326
 327 static u_int get_vpage(u_int vaddr)
 328 {
 329   u_int vpage=(vaddr^0x80000000)>>12;
 330 #ifndef DISABLE_TLB
 331   if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
 332 #endif
 333   if(vpage>2048) vpage=2048+(vpage&2047);
 334   return vpage;
 335 }
 336
 337 // Get address from virtual address
 338 // This is called from the recompiled JR/JALR instructions
 339 void *get_addr(u_int vaddr)
 340 {
 341   u_int page=get_page(vaddr);
 342   u_int vpage=get_vpage(vaddr);
 343   struct ll_entry *head;
 344   //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
 345   head=jump_in[page];
 346   while(head!=NULL) {
 347     if(head->vaddr==vaddr&&head->reg32==0) {
 348   //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 349       int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 350       ht_bin[3]=ht_bin[1];
 351       ht_bin[2]=ht_bin[0];
 352       ht_bin[1]=(int)head->addr;
 353       ht_bin[0]=vaddr;
 354       return head->addr;
 355     }
 356     head=head->next;
 357   }
 358   head=jump_dirty[vpage];
 359   while(head!=NULL) {
 360     if(head->vaddr==vaddr&&head->reg32==0) {
 361       //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 362       // Don't restore blocks which are about to expire from the cache
 363       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 364       if(verify_dirty(head->addr)) {
 365         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
 366         invalid_code[vaddr>>12]=0;
 367         memory_map[vaddr>>12]|=0x40000000;
 368         if(vpage<2048) {
 369 #ifndef DISABLE_TLB
 370           if(tlb_LUT_r[vaddr>>12]) {
 371             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
 372             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
 373           }
 374 #endif
 375           restore_candidate[vpage>>3]|=1<<(vpage&7);
 376         }
 377         else restore_candidate[page>>3]|=1<<(page&7);
 378         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 379         if(ht_bin[0]==vaddr) {
 380           ht_bin[1]=(int)head->addr; // Replace existing entry
 381         }
 382         else
 383         {
 384           ht_bin[3]=ht_bin[1];
 385           ht_bin[2]=ht_bin[0];
 386           ht_bin[1]=(int)head->addr;
 387           ht_bin[0]=vaddr;
 388         }
 389         return head->addr;
 390       }
 391     }
 392     head=head->next;
 393   }
 394   //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
 395   int r=new_recompile_block(vaddr);
 396   if(r==0) return get_addr(vaddr);
 397   // Execute in unmapped page, generate pagefault execption
 398   Status|=2;
 399   Cause=(vaddr<<31)|0x8;
 400   EPC=(vaddr&1)?vaddr-5:vaddr;
 401   BadVAddr=(vaddr&~1);
 402   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
 403   EntryHi=BadVAddr&0xFFFFE000;
 404   return get_addr_ht(0x80000000);
 405 }
 406 // Look up address in hash table first
 407 void *get_addr_ht(u_int vaddr)
 408 {
 409   //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
 410   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 411   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
 412   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
 413   return get_addr(vaddr);
 414 }
 415
 416 void *get_addr_32(u_int vaddr,u_int flags)
 417 {
 418 #ifdef FORCE32
 419   return get_addr(vaddr);
 420 #else
 421   //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
 422   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 423   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
 424   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
 425   u_int page=get_page(vaddr);
 426   u_int vpage=get_vpage(vaddr);
 427   struct ll_entry *head;
 428   head=jump_in[page];
 429   while(head!=NULL) {
 430     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
 431       //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 432       if(head->reg32==0) {
 433         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 434         if(ht_bin[0]==-1) {
 435           ht_bin[1]=(int)head->addr;
 436           ht_bin[0]=vaddr;
 437         }else if(ht_bin[2]==-1) {
 438           ht_bin[3]=(int)head->addr;
 439           ht_bin[2]=vaddr;
 440         }
 441         //ht_bin[3]=ht_bin[1];
 442         //ht_bin[2]=ht_bin[0];
 443         //ht_bin[1]=(int)head->addr;
 444         //ht_bin[0]=vaddr;
 445       }
 446       return head->addr;
 447     }
 448     head=head->next;
 449   }
 450   head=jump_dirty[vpage];
 451   while(head!=NULL) {
 452     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
 453       //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 454       // Don't restore blocks which are about to expire from the cache
 455       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 456       if(verify_dirty(head->addr)) {
 457         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
 458         invalid_code[vaddr>>12]=0;
 459         memory_map[vaddr>>12]|=0x40000000;
 460         if(vpage<2048) {
 461 #ifndef DISABLE_TLB
 462           if(tlb_LUT_r[vaddr>>12]) {
 463             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
 464             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
 465           }
 466 #endif
 467           restore_candidate[vpage>>3]|=1<<(vpage&7);
 468         }
 469         else restore_candidate[page>>3]|=1<<(page&7);
 470         if(head->reg32==0) {
 471           int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 472           if(ht_bin[0]==-1) {
 473             ht_bin[1]=(int)head->addr;
 474             ht_bin[0]=vaddr;
 475           }else if(ht_bin[2]==-1) {
 476             ht_bin[3]=(int)head->addr;
 477             ht_bin[2]=vaddr;
 478           }
 479           //ht_bin[3]=ht_bin[1];
 480           //ht_bin[2]=ht_bin[0];
 481           //ht_bin[1]=(int)head->addr;
 482           //ht_bin[0]=vaddr;
 483         }
 484         return head->addr;
 485       }
 486     }
 487     head=head->next;
 488   }
 489   //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
 490   int r=new_recompile_block(vaddr);
 491   if(r==0) return get_addr(vaddr);
 492   // Execute in unmapped page, generate pagefault execption
 493   Status|=2;
 494   Cause=(vaddr<<31)|0x8;
 495   EPC=(vaddr&1)?vaddr-5:vaddr;
 496   BadVAddr=(vaddr&~1);
 497   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
 498   EntryHi=BadVAddr&0xFFFFE000;
 499   return get_addr_ht(0x80000000);
 500 #endif
 501 }
 502
 503 void clear_all_regs(signed char regmap[])
 504 {
 505   int hr;
 506   for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
 507 }
 508
 509 signed char get_reg(signed char regmap[],int r)
 510 {
 511   int hr;
 512   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
 513   return -1;
 514 }
 515
 516 // Find a register that is available for two consecutive cycles
 517 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
 518 {
 519   int hr;
 520   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
 521   return -1;
 522 }
 523
 524 int count_free_regs(signed char regmap[])
 525 {
 526   int count=0;
 527   int hr;
 528   for(hr=0;hr<HOST_REGS;hr++)
 529   {
 530     if(hr!=EXCLUDE_REG) {
 531       if(regmap[hr]<0) count++;
 532     }
 533   }
 534   return count;
 535 }
 536
 537 void dirty_reg(struct regstat *cur,signed char reg)
 538 {
 539   int hr;
 540   if(!reg) return;
 541   for (hr=0;hr<HOST_REGS;hr++) {
 542     if((cur->regmap[hr]&63)==reg) {
 543       cur->dirty|=1<<hr;
 544     }
 545   }
 546 }
 547
 548 // If we dirty the lower half of a 64 bit register which is now being
 549 // sign-extended, we need to dump the upper half.
 550 // Note: Do this only after completion of the instruction, because
 551 // some instructions may need to read the full 64-bit value even if
 552 // overwriting it (eg SLTI, DSRA32).
 553 static void flush_dirty_uppers(struct regstat *cur)
 554 {
 555   int hr,reg;
 556   for (hr=0;hr<HOST_REGS;hr++) {
 557     if((cur->dirty>>hr)&1) {
 558       reg=cur->regmap[hr];
 559       if(reg>=64)
 560         if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
 561     }
 562   }
 563 }
 564
 565 void set_const(struct regstat *cur,signed char reg,uint64_t value)
 566 {
 567   int hr;
 568   if(!reg) return;
 569   for (hr=0;hr<HOST_REGS;hr++) {
 570     if(cur->regmap[hr]==reg) {
 571       cur->isconst|=1<<hr;
 572       cur->constmap[hr]=value;
 573     }
 574     else if((cur->regmap[hr]^64)==reg) {
 575       cur->isconst|=1<<hr;
 576       cur->constmap[hr]=value>>32;
 577     }
 578   }
 579 }
 580
 581 void clear_const(struct regstat *cur,signed char reg)
 582 {
 583   int hr;
 584   if(!reg) return;
 585   for (hr=0;hr<HOST_REGS;hr++) {
 586     if((cur->regmap[hr]&63)==reg) {
 587       cur->isconst&=~(1<<hr);
 588     }
 589   }
 590 }
 591
 592 int is_const(struct regstat *cur,signed char reg)
 593 {
 594   int hr;
 595   if(!reg) return 1;
 596   for (hr=0;hr<HOST_REGS;hr++) {
 597     if((cur->regmap[hr]&63)==reg) {
 598       return (cur->isconst>>hr)&1;
 599     }
 600   }
 601   return 0;
 602 }
 603 uint64_t get_const(struct regstat *cur,signed char reg)
 604 {
 605   int hr;
 606   if(!reg) return 0;
 607   for (hr=0;hr<HOST_REGS;hr++) {
 608     if(cur->regmap[hr]==reg) {
 609       return cur->constmap[hr];
 610     }
 611   }
 612   printf("Unknown constant in r%d\n",reg);
 613   exit(1);
 614 }
 615
 616 // Least soon needed registers
 617 // Look at the next ten instructions and see which registers
 618 // will be used.  Try not to reallocate these.
 619 void lsn(u_char hsn[], int i, int *preferred_reg)
 620 {
 621   int j;
 622   int b=-1;
 623   for(j=0;j<9;j++)
 624   {
 625     if(i+j>=slen) {
 626       j=slen-i-1;
 627       break;
 628     }
 629     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 630     {
 631       // Don't go past an unconditonal jump
 632       j++;
 633       break;
 634     }
 635   }
 636   for(;j>=0;j--)
 637   {
 638     if(rs1[i+j]) hsn[rs1[i+j]]=j;
 639     if(rs2[i+j]) hsn[rs2[i+j]]=j;
 640     if(rt1[i+j]) hsn[rt1[i+j]]=j;
 641     if(rt2[i+j]) hsn[rt2[i+j]]=j;
 642     if(itype[i+j]==STORE || itype[i+j]==STORELR) {
 643       // Stores can allocate zero
 644       hsn[rs1[i+j]]=j;
 645       hsn[rs2[i+j]]=j;
 646     }
 647     // On some architectures stores need invc_ptr
 648     #if defined(HOST_IMM8)
 649     if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
 650       hsn[INVCP]=j;
 651     }
 652     #endif
 653     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 654     {
 655       hsn[CCREG]=j;
 656       b=j;
 657     }
 658   }
 659   if(b>=0)
 660   {
 661     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 662     {
 663       // Follow first branch
 664       int t=(ba[i+b]-start)>>2;
 665       j=7-b;if(t+j>=slen) j=slen-t-1;
 666       for(;j>=0;j--)
 667       {
 668         if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
 669         if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
 670         //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
 671         //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
 672       }
 673     }
 674     // TODO: preferred register based on backward branch
 675   }
 676   // Delay slot should preferably not overwrite branch conditions or cycle count
 677   if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
 678     if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
 679     if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
 680     hsn[CCREG]=1;
 681     // ...or hash tables
 682     hsn[RHASH]=1;
 683     hsn[RHTBL]=1;
 684   }
 685   // Coprocessor load/store needs FTEMP, even if not declared
 686   if(itype[i]==C1LS||itype[i]==C2LS) {
 687     hsn[FTEMP]=0;
 688   }
 689   // Load L/R also uses FTEMP as a temporary register
 690   if(itype[i]==LOADLR) {
 691     hsn[FTEMP]=0;
 692   }
 693   // Also SWL/SWR/SDL/SDR
 694   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
 695     hsn[FTEMP]=0;
 696   }
 697   // Don't remove the TLB registers either
 698   if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
 699     hsn[TLREG]=0;
 700   }
 701   // Don't remove the miniht registers
 702   if(itype[i]==UJUMP||itype[i]==RJUMP)
 703   {
 704     hsn[RHASH]=0;
 705     hsn[RHTBL]=0;
 706   }
 707 }
 708
 709 // We only want to allocate registers if we're going to use them again soon
 710 int needed_again(int r, int i)
 711 {
 712   int j;
 713   int b=-1;
 714   int rn=10;
 715   int hr;
 716   u_char hsn[MAXREG+1];
 717   int preferred_reg;
 718
 719   memset(hsn,10,sizeof(hsn));
 720   lsn(hsn,i,&preferred_reg);
 721
 722   if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
 723   {
 724     if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
 725       return 0; // Don't need any registers if exiting the block
 726   }
 727   for(j=0;j<9;j++)
 728   {
 729     if(i+j>=slen) {
 730       j=slen-i-1;
 731       break;
 732     }
 733     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 734     {
 735       // Don't go past an unconditonal jump
 736       j++;
 737       break;
 738     }
 739     if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
 740     {
 741       break;
 742     }
 743   }
 744   for(;j>=1;j--)
 745   {
 746     if(rs1[i+j]==r) rn=j;
 747     if(rs2[i+j]==r) rn=j;
 748     if((unneeded_reg[i+j]>>r)&1) rn=10;
 749     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 750     {
 751       b=j;
 752     }
 753   }
 754   /*
 755   if(b>=0)
 756   {
 757     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 758     {
 759       // Follow first branch
 760       int o=rn;
 761       int t=(ba[i+b]-start)>>2;
 762       j=7-b;if(t+j>=slen) j=slen-t-1;
 763       for(;j>=0;j--)
 764       {
 765         if(!((unneeded_reg[t+j]>>r)&1)) {
 766           if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 767           if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 768         }
 769         else rn=o;
 770       }
 771     }
 772   }*/
 773   for(hr=0;hr<HOST_REGS;hr++) {
 774     if(hr!=EXCLUDE_REG) {
 775       if(rn<hsn[hr]) return 1;
 776     }
 777   }
 778   return 0;
 779 }
 780
 781 // Try to match register allocations at the end of a loop with those
 782 // at the beginning
 783 int loop_reg(int i, int r, int hr)
 784 {
 785   int j,k;
 786   for(j=0;j<9;j++)
 787   {
 788     if(i+j>=slen) {
 789       j=slen-i-1;
 790       break;
 791     }
 792     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 793     {
 794       // Don't go past an unconditonal jump
 795       j++;
 796       break;
 797     }
 798   }
 799   k=0;
 800   if(i>0){
 801     if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
 802       k--;
 803   }
 804   for(;k<j;k++)
 805   {
 806     if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
 807     if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
 808     if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
 809     {
 810       if(ba[i+k]>=start && ba[i+k]<(start+i*4))
 811       {
 812         int t=(ba[i+k]-start)>>2;
 813         int reg=get_reg(regs[t].regmap_entry,r);
 814         if(reg>=0) return reg;
 815         //reg=get_reg(regs[t+1].regmap_entry,r);
 816         //if(reg>=0) return reg;
 817       }
 818     }
 819   }
 820   return hr;
 821 }
 822
 823
 824 // Allocate every register, preserving source/target regs
 825 void alloc_all(struct regstat *cur,int i)
 826 {
 827   int hr;
 828
 829   for(hr=0;hr<HOST_REGS;hr++) {
 830     if(hr!=EXCLUDE_REG) {
 831       if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
 832          ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
 833       {
 834         cur->regmap[hr]=-1;
 835         cur->dirty&=~(1<<hr);
 836       }
 837       // Don't need zeros
 838       if((cur->regmap[hr]&63)==0)
 839       {
 840         cur->regmap[hr]=-1;
 841         cur->dirty&=~(1<<hr);
 842       }
 843     }
 844   }
 845 }
 846
 847
 848 void div64(int64_t dividend,int64_t divisor)
 849 {
 850   lo=dividend/divisor;
 851   hi=dividend%divisor;
 852   //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
 853   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 854 }
 855 void divu64(uint64_t dividend,uint64_t divisor)
 856 {
 857   lo=dividend/divisor;
 858   hi=dividend%divisor;
 859   //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 860   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 861 }
 862
 863 void mult64(uint64_t m1,uint64_t m2)
 864 {
 865    unsigned long long int op1, op2, op3, op4;
 866    unsigned long long int result1, result2, result3, result4;
 867    unsigned long long int temp1, temp2, temp3, temp4;
 868    int sign = 0;
 869
 870    if (m1 < 0)
 871      {
 872     op2 = -m1;
 873     sign = 1 - sign;
 874      }
 875    else op2 = m1;
 876    if (m2 < 0)
 877      {
 878     op4 = -m2;
 879     sign = 1 - sign;
 880      }
 881    else op4 = m2;
 882
 883    op1 = op2 & 0xFFFFFFFF;
 884    op2 = (op2 >> 32) & 0xFFFFFFFF;
 885    op3 = op4 & 0xFFFFFFFF;
 886    op4 = (op4 >> 32) & 0xFFFFFFFF;
 887
 888    temp1 = op1 * op3;
 889    temp2 = (temp1 >> 32) + op1 * op4;
 890    temp3 = op2 * op3;
 891    temp4 = (temp3 >> 32) + op2 * op4;
 892
 893    result1 = temp1 & 0xFFFFFFFF;
 894    result2 = temp2 + (temp3 & 0xFFFFFFFF);
 895    result3 = (result2 >> 32) + temp4;
 896    result4 = (result3 >> 32);
 897
 898    lo = result1 | (result2 << 32);
 899    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
 900    if (sign)
 901      {
 902     hi = ~hi;
 903     if (!lo) hi++;
 904     else lo = ~lo + 1;
 905      }
 906 }
 907
 908 void multu64(uint64_t m1,uint64_t m2)
 909 {
 910    unsigned long long int op1, op2, op3, op4;
 911    unsigned long long int result1, result2, result3, result4;
 912    unsigned long long int temp1, temp2, temp3, temp4;
 913
 914    op1 = m1 & 0xFFFFFFFF;
 915    op2 = (m1 >> 32) & 0xFFFFFFFF;
 916    op3 = m2 & 0xFFFFFFFF;
 917    op4 = (m2 >> 32) & 0xFFFFFFFF;
 918
 919    temp1 = op1 * op3;
 920    temp2 = (temp1 >> 32) + op1 * op4;
 921    temp3 = op2 * op3;
 922    temp4 = (temp3 >> 32) + op2 * op4;
 923
 924    result1 = temp1 & 0xFFFFFFFF;
 925    result2 = temp2 + (temp3 & 0xFFFFFFFF);
 926    result3 = (result2 >> 32) + temp4;
 927    result4 = (result3 >> 32);
 928
 929    lo = result1 | (result2 << 32);
 930    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
 931
 932   //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 933   //                                      ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 934 }
 935
 936 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
 937 {
 938   if(bits) {
 939     original<<=64-bits;
 940     original>>=64-bits;
 941     loaded<<=bits;
 942     original|=loaded;
 943   }
 944   else original=loaded;
 945   return original;
 946 }
 947 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
 948 {
 949   if(bits^56) {
 950     original>>=64-(bits^56);
 951     original<<=64-(bits^56);
 952     loaded>>=bits^56;
 953     original|=loaded;
 954   }
 955   else original=loaded;
 956   return original;
 957 }
 958
 959 #ifdef __i386__
 960 #include "assem_x86.c"
 961 #endif
 962 #ifdef __x86_64__
 963 #include "assem_x64.c"
 964 #endif
 965 #ifdef __arm__
 966 #include "assem_arm.c"
 967 #endif
 968
 969 // Add virtual address mapping to linked list
 970 void ll_add(struct ll_entry **head,int vaddr,void *addr)
 971 {
 972   struct ll_entry *new_entry;
 973   new_entry=malloc(sizeof(struct ll_entry));
 974   assert(new_entry!=NULL);
 975   new_entry->vaddr=vaddr;
 976   new_entry->reg32=0;
 977   new_entry->addr=addr;
 978   new_entry->next=*head;
 979   *head=new_entry;
 980 }
 981
 982 // Add virtual address mapping for 32-bit compiled block
 983 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
 984 {
 985   ll_add(head,vaddr,addr);
 986 #ifndef FORCE32
 987   (*head)->reg32=reg32;
 988 #endif
 989 }
 990
 991 // Check if an address is already compiled
 992 // but don't return addresses which are about to expire from the cache
 993 void *check_addr(u_int vaddr)
 994 {
 995   u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 996   if(ht_bin[0]==vaddr) {
 997     if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 998       if(isclean(ht_bin[1])) return (void *)ht_bin[1];
 999   }
1000   if(ht_bin[2]==vaddr) {
1001     if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1002       if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1003   }
1004   u_int page=get_page(vaddr);
1005   struct ll_entry *head;
1006   head=jump_in[page];
1007   while(head!=NULL) {
1008     if(head->vaddr==vaddr&&head->reg32==0) {
1009       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1010         // Update existing entry with current address
1011         if(ht_bin[0]==vaddr) {
1012           ht_bin[1]=(int)head->addr;
1013           return head->addr;
1014         }
1015         if(ht_bin[2]==vaddr) {
1016           ht_bin[3]=(int)head->addr;
1017           return head->addr;
1018         }
1019         // Insert into hash table with low priority.
1020         // Don't evict existing entries, as they are probably
1021         // addresses that are being accessed frequently.
1022         if(ht_bin[0]==-1) {
1023           ht_bin[1]=(int)head->addr;
1024           ht_bin[0]=vaddr;
1025         }else if(ht_bin[2]==-1) {
1026           ht_bin[3]=(int)head->addr;
1027           ht_bin[2]=vaddr;
1028         }
1029         return head->addr;
1030       }
1031     }
1032     head=head->next;
1033   }
1034   return 0;
1035 }
1036
1037 void remove_hash(int vaddr)
1038 {
1039   //printf("remove hash: %x\n",vaddr);
1040   int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1041   if(ht_bin[2]==vaddr) {
1042     ht_bin[2]=ht_bin[3]=-1;
1043   }
1044   if(ht_bin[0]==vaddr) {
1045     ht_bin[0]=ht_bin[2];
1046     ht_bin[1]=ht_bin[3];
1047     ht_bin[2]=ht_bin[3]=-1;
1048   }
1049 }
1050
1051 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1052 {
1053   struct ll_entry *next;
1054   while(*head) {
1055     if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1056        ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1057     {
1058       inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1059       remove_hash((*head)->vaddr);
1060       next=(*head)->next;
1061       free(*head);
1062       *head=next;
1063     }
1064     else
1065     {
1066       head=&((*head)->next);
1067     }
1068   }
1069 }
1070
1071 // Remove all entries from linked list
1072 void ll_clear(struct ll_entry **head)
1073 {
1074   struct ll_entry *cur;
1075   struct ll_entry *next;
1076   if(cur=*head) {
1077     *head=0;
1078     while(cur) {
1079       next=cur->next;
1080       free(cur);
1081       cur=next;
1082     }
1083   }
1084 }
1085
1086 // Dereference the pointers and remove if it matches
1087 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1088 {
1089   u_int old_host_addr=0;
1090   while(head) {
1091     int ptr=get_pointer(head->addr);
1092     inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1093     if(((ptr>>shift)==(addr>>shift)) ||
1094        (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1095     {
1096       inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1097       u_int host_addr=(u_int)kill_pointer(head->addr);
1098
1099       if((host_addr>>12)!=(old_host_addr>>12)) {
1100         #ifdef __arm__
1101         __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1102         #endif
1103         old_host_addr=host_addr;
1104       }
1105     }
1106     head=head->next;
1107   }
1108   #ifdef __arm__
1109   if (old_host_addr)
1110     __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1111   #endif
1112 }
1113
1114 // This is called when we write to a compiled block (see do_invstub)
1115 void invalidate_page(u_int page)
1116 {
1117   struct ll_entry *head;
1118   struct ll_entry *next;
1119   u_int old_host_addr=0;
1120   head=jump_in[page];
1121   jump_in[page]=0;
1122   while(head!=NULL) {
1123     inv_debug("INVALIDATE: %x\n",head->vaddr);
1124     remove_hash(head->vaddr);
1125     next=head->next;
1126     free(head);
1127     head=next;
1128   }
1129   head=jump_out[page];
1130   jump_out[page]=0;
1131   while(head!=NULL) {
1132     inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1133     u_int host_addr=(u_int)kill_pointer(head->addr);
1134
1135     if((host_addr>>12)!=(old_host_addr>>12)) {
1136       #ifdef __arm__
1137       __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1138       #endif
1139       old_host_addr=host_addr;
1140     }
1141     next=head->next;
1142     free(head);
1143     head=next;
1144   }
1145   #ifdef __arm__
1146   if (old_host_addr)
1147     __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1148   #endif
1149 }
1150 void invalidate_block(u_int block)
1151 {
1152   u_int page=get_page(block<<12);
1153   u_int vpage=get_vpage(block<<12);
1154   inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1155   //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1156   u_int first,last;
1157   first=last=page;
1158   struct ll_entry *head;
1159   head=jump_dirty[vpage];
1160   //printf("page=%d vpage=%d\n",page,vpage);
1161   while(head!=NULL) {
1162     u_int start,end;
1163     if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1164       get_bounds((int)head->addr,&start,&end);
1165       //printf("start: %x end: %x\n",start,end);
1166       if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
1167         if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1168           if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1169           if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1170         }
1171       }
1172 #ifndef DISABLE_TLB
1173       if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1174         if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1175           if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1176           if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1177         }
1178       }
1179 #endif
1180     }
1181     head=head->next;
1182   }
1183   //printf("first=%d last=%d\n",first,last);
1184   invalidate_page(page);
1185   assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1186   assert(last<page+5);
1187   // Invalidate the adjacent pages if a block crosses a 4K boundary
1188   while(first<page) {
1189     invalidate_page(first);
1190     first++;
1191   }
1192   for(first=page+1;first<last;first++) {
1193     invalidate_page(first);
1194   }
1195
1196   // Don't trap writes
1197   invalid_code[block]=1;
1198 #ifndef DISABLE_TLB
1199   // If there is a valid TLB entry for this page, remove write protect
1200   if(tlb_LUT_w[block]) {
1201     assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1202     // CHECK: Is this right?
1203     memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1204     u_int real_block=tlb_LUT_w[block]>>12;
1205     invalid_code[real_block]=1;
1206     if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1207   }
1208   else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1209 #endif
1210
1211   #ifdef USE_MINI_HT
1212   memset(mini_ht,-1,sizeof(mini_ht));
1213   #endif
1214 }
1215 void invalidate_addr(u_int addr)
1216 {
1217   invalidate_block(addr>>12);
1218 }
1219 void invalidate_all_pages()
1220 {
1221   u_int page,n;
1222   for(page=0;page<4096;page++)
1223     invalidate_page(page);
1224   for(page=0;page<1048576;page++)
1225     if(!invalid_code[page]) {
1226       restore_candidate[(page&2047)>>3]|=1<<(page&7);
1227       restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1228     }
1229   #ifdef __arm__
1230   __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1231   #endif
1232   #ifdef USE_MINI_HT
1233   memset(mini_ht,-1,sizeof(mini_ht));
1234   #endif
1235   #ifndef DISABLE_TLB
1236   // TLB
1237   for(page=0;page<0x100000;page++) {
1238     if(tlb_LUT_r[page]) {
1239       memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1240       if(!tlb_LUT_w[page]||!invalid_code[page])
1241         memory_map[page]|=0x40000000; // Write protect
1242     }
1243     else memory_map[page]=-1;
1244     if(page==0x80000) page=0xC0000;
1245   }
1246   tlb_hacks();
1247   #endif
1248 }
1249
1250 // Add an entry to jump_out after making a link
1251 void add_link(u_int vaddr,void *src)
1252 {
1253   u_int page=get_page(vaddr);
1254   inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1255   ll_add(jump_out+page,vaddr,src);
1256   //int ptr=get_pointer(src);
1257   //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1258 }
1259
1260 // If a code block was found to be unmodified (bit was set in
1261 // restore_candidate) and it remains unmodified (bit is clear
1262 // in invalid_code) then move the entries for that 4K page from
1263 // the dirty list to the clean list.
1264 void clean_blocks(u_int page)
1265 {
1266   struct ll_entry *head;
1267   inv_debug("INV: clean_blocks page=%d\n",page);
1268   head=jump_dirty[page];
1269   while(head!=NULL) {
1270     if(!invalid_code[head->vaddr>>12]) {
1271       // Don't restore blocks which are about to expire from the cache
1272       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1273         u_int start,end;
1274         if(verify_dirty((int)head->addr)) {
1275           //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1276           u_int i;
1277           u_int inv=0;
1278           get_bounds((int)head->addr,&start,&end);
1279           if(start-(u_int)rdram<RAM_SIZE) {
1280             for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1281               inv|=invalid_code[i];
1282             }
1283           }
1284           if((signed int)head->vaddr>=(signed int)0xC0000000) {
1285             u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1286             //printf("addr=%x start=%x end=%x\n",addr,start,end);
1287             if(addr<start||addr>=end) inv=1;
1288           }
1289           else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1290             inv=1;
1291           }
1292           if(!inv) {
1293             void * clean_addr=(void *)get_clean_addr((int)head->addr);
1294             if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1295               u_int ppage=page;
1296 #ifndef DISABLE_TLB
1297               if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1298 #endif
1299               inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1300               //printf("page=%x, addr=%x\n",page,head->vaddr);
1301               //assert(head->vaddr>>12==(page|0x80000));
1302               ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1303               int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1304               if(!head->reg32) {
1305                 if(ht_bin[0]==head->vaddr) {
1306                   ht_bin[1]=(int)clean_addr; // Replace existing entry
1307                 }
1308                 if(ht_bin[2]==head->vaddr) {
1309                   ht_bin[3]=(int)clean_addr; // Replace existing entry
1310                 }
1311               }
1312             }
1313           }
1314         }
1315       }
1316     }
1317     head=head->next;
1318   }
1319 }
1320
1321
1322 void mov_alloc(struct regstat *current,int i)
1323 {
1324   // Note: Don't need to actually alloc the source registers
1325   if((~current->is32>>rs1[i])&1) {
1326     //alloc_reg64(current,i,rs1[i]);
1327     alloc_reg64(current,i,rt1[i]);
1328     current->is32&=~(1LL<<rt1[i]);
1329   } else {
1330     //alloc_reg(current,i,rs1[i]);
1331     alloc_reg(current,i,rt1[i]);
1332     current->is32|=(1LL<<rt1[i]);
1333   }
1334   clear_const(current,rs1[i]);
1335   clear_const(current,rt1[i]);
1336   dirty_reg(current,rt1[i]);
1337 }
1338
1339 void shiftimm_alloc(struct regstat *current,int i)
1340 {
1341   clear_const(current,rs1[i]);
1342   clear_const(current,rt1[i]);
1343   if(opcode2[i]<=0x3) // SLL/SRL/SRA
1344   {
1345     if(rt1[i]) {
1346       if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1347       else lt1[i]=rs1[i];
1348       alloc_reg(current,i,rt1[i]);
1349       current->is32|=1LL<<rt1[i];
1350       dirty_reg(current,rt1[i]);
1351     }
1352   }
1353   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1354   {
1355     if(rt1[i]) {
1356       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1357       alloc_reg64(current,i,rt1[i]);
1358       current->is32&=~(1LL<<rt1[i]);
1359       dirty_reg(current,rt1[i]);
1360     }
1361   }
1362   if(opcode2[i]==0x3c) // DSLL32
1363   {
1364     if(rt1[i]) {
1365       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1366       alloc_reg64(current,i,rt1[i]);
1367       current->is32&=~(1LL<<rt1[i]);
1368       dirty_reg(current,rt1[i]);
1369     }
1370   }
1371   if(opcode2[i]==0x3e) // DSRL32
1372   {
1373     if(rt1[i]) {
1374       alloc_reg64(current,i,rs1[i]);
1375       if(imm[i]==32) {
1376         alloc_reg64(current,i,rt1[i]);
1377         current->is32&=~(1LL<<rt1[i]);
1378       } else {
1379         alloc_reg(current,i,rt1[i]);
1380         current->is32|=1LL<<rt1[i];
1381       }
1382       dirty_reg(current,rt1[i]);
1383     }
1384   }
1385   if(opcode2[i]==0x3f) // DSRA32
1386   {
1387     if(rt1[i]) {
1388       alloc_reg64(current,i,rs1[i]);
1389       alloc_reg(current,i,rt1[i]);
1390       current->is32|=1LL<<rt1[i];
1391       dirty_reg(current,rt1[i]);
1392     }
1393   }
1394 }
1395
1396 void shift_alloc(struct regstat *current,int i)
1397 {
1398   if(rt1[i]) {
1399     if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1400     {
1401       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1402       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1403       alloc_reg(current,i,rt1[i]);
1404       if(rt1[i]==rs2[i]) alloc_reg_temp(current,i,-1);
1405       current->is32|=1LL<<rt1[i];
1406     } else { // DSLLV/DSRLV/DSRAV
1407       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1408       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1409       alloc_reg64(current,i,rt1[i]);
1410       current->is32&=~(1LL<<rt1[i]);
1411       if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1412         alloc_reg_temp(current,i,-1);
1413     }
1414     clear_const(current,rs1[i]);
1415     clear_const(current,rs2[i]);
1416     clear_const(current,rt1[i]);
1417     dirty_reg(current,rt1[i]);
1418   }
1419 }
1420
1421 void alu_alloc(struct regstat *current,int i)
1422 {
1423   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1424     if(rt1[i]) {
1425       if(rs1[i]&&rs2[i]) {
1426         alloc_reg(current,i,rs1[i]);
1427         alloc_reg(current,i,rs2[i]);
1428       }
1429       else {
1430         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1431         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1432       }
1433       alloc_reg(current,i,rt1[i]);
1434     }
1435     current->is32|=1LL<<rt1[i];
1436   }
1437   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1438     if(rt1[i]) {
1439       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1440       {
1441         alloc_reg64(current,i,rs1[i]);
1442         alloc_reg64(current,i,rs2[i]);
1443         alloc_reg(current,i,rt1[i]);
1444       } else {
1445         alloc_reg(current,i,rs1[i]);
1446         alloc_reg(current,i,rs2[i]);
1447         alloc_reg(current,i,rt1[i]);
1448       }
1449     }
1450     current->is32|=1LL<<rt1[i];
1451   }
1452   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1453     if(rt1[i]) {
1454       if(rs1[i]&&rs2[i]) {
1455         alloc_reg(current,i,rs1[i]);
1456         alloc_reg(current,i,rs2[i]);
1457       }
1458       else
1459       {
1460         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1461         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1462       }
1463       alloc_reg(current,i,rt1[i]);
1464       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1465       {
1466         if(!((current->uu>>rt1[i])&1)) {
1467           alloc_reg64(current,i,rt1[i]);
1468         }
1469         if(get_reg(current->regmap,rt1[i]|64)>=0) {
1470           if(rs1[i]&&rs2[i]) {
1471             alloc_reg64(current,i,rs1[i]);
1472             alloc_reg64(current,i,rs2[i]);
1473           }
1474           else
1475           {
1476             // Is is really worth it to keep 64-bit values in registers?
1477             #ifdef NATIVE_64BIT
1478             if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1479             if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1480             #endif
1481           }
1482         }
1483         current->is32&=~(1LL<<rt1[i]);
1484       } else {
1485         current->is32|=1LL<<rt1[i];
1486       }
1487     }
1488   }
1489   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1490     if(rt1[i]) {
1491       if(rs1[i]&&rs2[i]) {
1492         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1493           alloc_reg64(current,i,rs1[i]);
1494           alloc_reg64(current,i,rs2[i]);
1495           alloc_reg64(current,i,rt1[i]);
1496         } else {
1497           alloc_reg(current,i,rs1[i]);
1498           alloc_reg(current,i,rs2[i]);
1499           alloc_reg(current,i,rt1[i]);
1500         }
1501       }
1502       else {
1503         alloc_reg(current,i,rt1[i]);
1504         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1505           // DADD used as move, or zeroing
1506           // If we have a 64-bit source, then make the target 64 bits too
1507           if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1508             if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1509             alloc_reg64(current,i,rt1[i]);
1510           } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1511             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1512             alloc_reg64(current,i,rt1[i]);
1513           }
1514           if(opcode2[i]>=0x2e&&rs2[i]) {
1515             // DSUB used as negation - 64-bit result
1516             // If we have a 32-bit register, extend it to 64 bits
1517             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1518             alloc_reg64(current,i,rt1[i]);
1519           }
1520         }
1521       }
1522       if(rs1[i]&&rs2[i]) {
1523         current->is32&=~(1LL<<rt1[i]);
1524       } else if(rs1[i]) {
1525         current->is32&=~(1LL<<rt1[i]);
1526         if((current->is32>>rs1[i])&1)
1527           current->is32|=1LL<<rt1[i];
1528       } else if(rs2[i]) {
1529         current->is32&=~(1LL<<rt1[i]);
1530         if((current->is32>>rs2[i])&1)
1531           current->is32|=1LL<<rt1[i];
1532       } else {
1533         current->is32|=1LL<<rt1[i];
1534       }
1535     }
1536   }
1537   clear_const(current,rs1[i]);
1538   clear_const(current,rs2[i]);
1539   clear_const(current,rt1[i]);
1540   dirty_reg(current,rt1[i]);
1541 }
1542
1543 void imm16_alloc(struct regstat *current,int i)
1544 {
1545   if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1546   else lt1[i]=rs1[i];
1547   if(rt1[i]) alloc_reg(current,i,rt1[i]);
1548   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1549     current->is32&=~(1LL<<rt1[i]);
1550     if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1551       // TODO: Could preserve the 32-bit flag if the immediate is zero
1552       alloc_reg64(current,i,rt1[i]);
1553       alloc_reg64(current,i,rs1[i]);
1554     }
1555     clear_const(current,rs1[i]);
1556     clear_const(current,rt1[i]);
1557   }
1558   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1559     if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1560     current->is32|=1LL<<rt1[i];
1561     clear_const(current,rs1[i]);
1562     clear_const(current,rt1[i]);
1563   }
1564   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1565     if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1566       if(rs1[i]!=rt1[i]) {
1567         if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1568         alloc_reg64(current,i,rt1[i]);
1569         current->is32&=~(1LL<<rt1[i]);
1570       }
1571     }
1572     else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1573     if(is_const(current,rs1[i])) {
1574       int v=get_const(current,rs1[i]);
1575       if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1576       if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1577       if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1578     }
1579     else clear_const(current,rt1[i]);
1580   }
1581   else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1582     if(is_const(current,rs1[i])) {
1583       int v=get_const(current,rs1[i]);
1584       set_const(current,rt1[i],v+imm[i]);
1585     }
1586     else clear_const(current,rt1[i]);
1587     current->is32|=1LL<<rt1[i];
1588   }
1589   else {
1590     set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1591     current->is32|=1LL<<rt1[i];
1592   }
1593   dirty_reg(current,rt1[i]);
1594 }
1595
1596 void load_alloc(struct regstat *current,int i)
1597 {
1598   clear_const(current,rt1[i]);
1599   //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1600   if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1601   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1602   if(rt1[i]) {
1603     alloc_reg(current,i,rt1[i]);
1604     if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1605     {
1606       current->is32&=~(1LL<<rt1[i]);
1607       alloc_reg64(current,i,rt1[i]);
1608     }
1609     else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1610     {
1611       current->is32&=~(1LL<<rt1[i]);
1612       alloc_reg64(current,i,rt1[i]);
1613       alloc_all(current,i);
1614       alloc_reg64(current,i,FTEMP);
1615     }
1616     else current->is32|=1LL<<rt1[i];
1617     dirty_reg(current,rt1[i]);
1618     // If using TLB, need a register for pointer to the mapping table
1619     if(using_tlb) alloc_reg(current,i,TLREG);
1620     // LWL/LWR need a temporary register for the old value
1621     if(opcode[i]==0x22||opcode[i]==0x26)
1622     {
1623       alloc_reg(current,i,FTEMP);
1624       alloc_reg_temp(current,i,-1);
1625     }
1626   }
1627   else
1628   {
1629     // Load to r0 (dummy load)
1630     // but we still need a register to calculate the address
1631     alloc_reg_temp(current,i,-1);
1632   }
1633 }
1634
1635 void store_alloc(struct regstat *current,int i)
1636 {
1637   clear_const(current,rs2[i]);
1638   if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1639   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1640   alloc_reg(current,i,rs2[i]);
1641   if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1642     alloc_reg64(current,i,rs2[i]);
1643     if(rs2[i]) alloc_reg(current,i,FTEMP);
1644   }
1645   // If using TLB, need a register for pointer to the mapping table
1646   if(using_tlb) alloc_reg(current,i,TLREG);
1647   #if defined(HOST_IMM8)
1648   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1649   else alloc_reg(current,i,INVCP);
1650   #endif
1651   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1652     alloc_reg(current,i,FTEMP);
1653   }
1654   // We need a temporary register for address generation
1655   alloc_reg_temp(current,i,-1);
1656 }
1657
1658 void c1ls_alloc(struct regstat *current,int i)
1659 {
1660   //clear_const(current,rs1[i]); // FIXME
1661   clear_const(current,rt1[i]);
1662   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1663   alloc_reg(current,i,CSREG); // Status
1664   alloc_reg(current,i,FTEMP);
1665   if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1666     alloc_reg64(current,i,FTEMP);
1667   }
1668   // If using TLB, need a register for pointer to the mapping table
1669   if(using_tlb) alloc_reg(current,i,TLREG);
1670   #if defined(HOST_IMM8)
1671   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1672   else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1673     alloc_reg(current,i,INVCP);
1674   #endif
1675   // We need a temporary register for address generation
1676   alloc_reg_temp(current,i,-1);
1677 }
1678
1679 void c2ls_alloc(struct regstat *current,int i)
1680 {
1681   clear_const(current,rt1[i]);
1682   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1683   alloc_reg(current,i,FTEMP);
1684   // If using TLB, need a register for pointer to the mapping table
1685   if(using_tlb) alloc_reg(current,i,TLREG);
1686   #if defined(HOST_IMM8)
1687   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1688   else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1689     alloc_reg(current,i,INVCP);
1690   #endif
1691   // We need a temporary register for address generation
1692   alloc_reg_temp(current,i,-1);
1693 }
1694
1695 #ifndef multdiv_alloc
1696 void multdiv_alloc(struct regstat *current,int i)
1697 {
1698   //  case 0x18: MULT
1699   //  case 0x19: MULTU
1700   //  case 0x1A: DIV
1701   //  case 0x1B: DIVU
1702   //  case 0x1C: DMULT
1703   //  case 0x1D: DMULTU
1704   //  case 0x1E: DDIV
1705   //  case 0x1F: DDIVU
1706   clear_const(current,rs1[i]);
1707   clear_const(current,rs2[i]);
1708   if(rs1[i]&&rs2[i])
1709   {
1710     if((opcode2[i]&4)==0) // 32-bit
1711     {
1712       current->u&=~(1LL<<HIREG);
1713       current->u&=~(1LL<<LOREG);
1714       alloc_reg(current,i,HIREG);
1715       alloc_reg(current,i,LOREG);
1716       alloc_reg(current,i,rs1[i]);
1717       alloc_reg(current,i,rs2[i]);
1718       current->is32|=1LL<<HIREG;
1719       current->is32|=1LL<<LOREG;
1720       dirty_reg(current,HIREG);
1721       dirty_reg(current,LOREG);
1722     }
1723     else // 64-bit
1724     {
1725       current->u&=~(1LL<<HIREG);
1726       current->u&=~(1LL<<LOREG);
1727       current->uu&=~(1LL<<HIREG);
1728       current->uu&=~(1LL<<LOREG);
1729       alloc_reg64(current,i,HIREG);
1730       //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1731       alloc_reg64(current,i,rs1[i]);
1732       alloc_reg64(current,i,rs2[i]);
1733       alloc_all(current,i);
1734       current->is32&=~(1LL<<HIREG);
1735       current->is32&=~(1LL<<LOREG);
1736       dirty_reg(current,HIREG);
1737       dirty_reg(current,LOREG);
1738     }
1739   }
1740   else
1741   {
1742     // Multiply by zero is zero.
1743     // MIPS does not have a divide by zero exception.
1744     // The result is undefined, we return zero.
1745     alloc_reg(current,i,HIREG);
1746     alloc_reg(current,i,LOREG);
1747     current->is32|=1LL<<HIREG;
1748     current->is32|=1LL<<LOREG;
1749     dirty_reg(current,HIREG);
1750     dirty_reg(current,LOREG);
1751   }
1752 }
1753 #endif
1754
1755 void cop0_alloc(struct regstat *current,int i)
1756 {
1757   if(opcode2[i]==0) // MFC0
1758   {
1759     if(rt1[i]) {
1760       clear_const(current,rt1[i]);
1761       alloc_all(current,i);
1762       alloc_reg(current,i,rt1[i]);
1763       current->is32|=1LL<<rt1[i];
1764       dirty_reg(current,rt1[i]);
1765     }
1766   }
1767   else if(opcode2[i]==4) // MTC0
1768   {
1769     if(rs1[i]){
1770       clear_const(current,rs1[i]);
1771       alloc_reg(current,i,rs1[i]);
1772       alloc_all(current,i);
1773     }
1774     else {
1775       alloc_all(current,i); // FIXME: Keep r0
1776       current->u&=~1LL;
1777       alloc_reg(current,i,0);
1778     }
1779   }
1780   else
1781   {
1782     // TLBR/TLBWI/TLBWR/TLBP/ERET
1783     assert(opcode2[i]==0x10);
1784     alloc_all(current,i);
1785   }
1786 }
1787
1788 void cop1_alloc(struct regstat *current,int i)
1789 {
1790   alloc_reg(current,i,CSREG); // Load status
1791   if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1792   {
1793     if(rt1[i]){
1794       clear_const(current,rt1[i]);
1795       if(opcode2[i]==1) {
1796         alloc_reg64(current,i,rt1[i]); // DMFC1
1797         current->is32&=~(1LL<<rt1[i]);
1798       }else{
1799         alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1800         current->is32|=1LL<<rt1[i];
1801       }
1802       dirty_reg(current,rt1[i]);
1803     }
1804     alloc_reg_temp(current,i,-1);
1805   }
1806   else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1807   {
1808     if(rs1[i]){
1809       clear_const(current,rs1[i]);
1810       if(opcode2[i]==5)
1811         alloc_reg64(current,i,rs1[i]); // DMTC1
1812       else
1813         alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1814       alloc_reg_temp(current,i,-1);
1815     }
1816     else {
1817       current->u&=~1LL;
1818       alloc_reg(current,i,0);
1819       alloc_reg_temp(current,i,-1);
1820     }
1821   }
1822 }
1823 void fconv_alloc(struct regstat *current,int i)
1824 {
1825   alloc_reg(current,i,CSREG); // Load status
1826   alloc_reg_temp(current,i,-1);
1827 }
1828 void float_alloc(struct regstat *current,int i)
1829 {
1830   alloc_reg(current,i,CSREG); // Load status
1831   alloc_reg_temp(current,i,-1);
1832 }
1833 void c2op_alloc(struct regstat *current,int i)
1834 {
1835   alloc_reg_temp(current,i,-1);
1836 }
1837 void fcomp_alloc(struct regstat *current,int i)
1838 {
1839   alloc_reg(current,i,CSREG); // Load status
1840   alloc_reg(current,i,FSREG); // Load flags
1841   dirty_reg(current,FSREG); // Flag will be modified
1842   alloc_reg_temp(current,i,-1);
1843 }
1844
1845 void syscall_alloc(struct regstat *current,int i)
1846 {
1847   alloc_cc(current,i);
1848   dirty_reg(current,CCREG);
1849   alloc_all(current,i);
1850   current->isconst=0;
1851 }
1852
1853 void delayslot_alloc(struct regstat *current,int i)
1854 {
1855   switch(itype[i]) {
1856     case UJUMP:
1857     case CJUMP:
1858     case SJUMP:
1859     case RJUMP:
1860     case FJUMP:
1861     case SYSCALL:
1862     case HLECALL:
1863     case SPAN:
1864       assem_debug("jump in the delay slot.  this shouldn't happen.\n");//exit(1);
1865       printf("Disabled speculative precompilation\n");
1866       stop_after_jal=1;
1867       break;
1868     case IMM16:
1869       imm16_alloc(current,i);
1870       break;
1871     case LOAD:
1872     case LOADLR:
1873       load_alloc(current,i);
1874       break;
1875     case STORE:
1876     case STORELR:
1877       store_alloc(current,i);
1878       break;
1879     case ALU:
1880       alu_alloc(current,i);
1881       break;
1882     case SHIFT:
1883       shift_alloc(current,i);
1884       break;
1885     case MULTDIV:
1886       multdiv_alloc(current,i);
1887       break;
1888     case SHIFTIMM:
1889       shiftimm_alloc(current,i);
1890       break;
1891     case MOV:
1892       mov_alloc(current,i);
1893       break;
1894     case COP0:
1895       cop0_alloc(current,i);
1896       break;
1897     case COP1:
1898     case COP2:
1899       cop1_alloc(current,i);
1900       break;
1901     case C1LS:
1902       c1ls_alloc(current,i);
1903       break;
1904     case C2LS:
1905       c2ls_alloc(current,i);
1906       break;
1907     case FCONV:
1908       fconv_alloc(current,i);
1909       break;
1910     case FLOAT:
1911       float_alloc(current,i);
1912       break;
1913     case FCOMP:
1914       fcomp_alloc(current,i);
1915       break;
1916     case C2OP:
1917       c2op_alloc(current,i);
1918       break;
1919   }
1920 }
1921
1922 // Special case where a branch and delay slot span two pages in virtual memory
1923 static void pagespan_alloc(struct regstat *current,int i)
1924 {
1925   current->isconst=0;
1926   current->wasconst=0;
1927   regs[i].wasconst=0;
1928   alloc_all(current,i);
1929   alloc_cc(current,i);
1930   dirty_reg(current,CCREG);
1931   if(opcode[i]==3) // JAL
1932   {
1933     alloc_reg(current,i,31);
1934     dirty_reg(current,31);
1935   }
1936   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1937   {
1938     alloc_reg(current,i,rs1[i]);
1939     if (rt1[i]!=0) {
1940       alloc_reg(current,i,rt1[i]);
1941       dirty_reg(current,rt1[i]);
1942     }
1943   }
1944   if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1945   {
1946     if(rs1[i]) alloc_reg(current,i,rs1[i]);
1947     if(rs2[i]) alloc_reg(current,i,rs2[i]);
1948     if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1949     {
1950       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1951       if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1952     }
1953   }
1954   else
1955   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1956   {
1957     if(rs1[i]) alloc_reg(current,i,rs1[i]);
1958     if(!((current->is32>>rs1[i])&1))
1959     {
1960       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1961     }
1962   }
1963   else
1964   if(opcode[i]==0x11) // BC1
1965   {
1966     alloc_reg(current,i,FSREG);
1967     alloc_reg(current,i,CSREG);
1968   }
1969   //else ...
1970 }
1971
1972 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
1973 {
1974   stubs[stubcount][0]=type;
1975   stubs[stubcount][1]=addr;
1976   stubs[stubcount][2]=retaddr;
1977   stubs[stubcount][3]=a;
1978   stubs[stubcount][4]=b;
1979   stubs[stubcount][5]=c;
1980   stubs[stubcount][6]=d;
1981   stubs[stubcount][7]=e;
1982   stubcount++;
1983 }
1984
1985 // Write out a single register
1986 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
1987 {
1988   int hr;
1989   for(hr=0;hr<HOST_REGS;hr++) {
1990     if(hr!=EXCLUDE_REG) {
1991       if((regmap[hr]&63)==r) {
1992         if((dirty>>hr)&1) {
1993           if(regmap[hr]<64) {
1994             emit_storereg(r,hr);
1995 #ifndef FORCE32
1996             if((is32>>regmap[hr])&1) {
1997               emit_sarimm(hr,31,hr);
1998               emit_storereg(r|64,hr);
1999             }
2000 #endif
2001           }else{
2002             emit_storereg(r|64,hr);
2003           }
2004         }
2005       }
2006     }
2007   }
2008 }
2009
2010 int mchecksum()
2011 {
2012   //if(!tracedebug) return 0;
2013   int i;
2014   int sum=0;
2015   for(i=0;i<2097152;i++) {
2016     unsigned int temp=sum;
2017     sum<<=1;
2018     sum|=(~temp)>>31;
2019     sum^=((u_int *)rdram)[i];
2020   }
2021   return sum;
2022 }
2023 int rchecksum()
2024 {
2025   int i;
2026   int sum=0;
2027   for(i=0;i<64;i++)
2028     sum^=((u_int *)reg)[i];
2029   return sum;
2030 }
2031 void rlist()
2032 {
2033   int i;
2034   printf("TRACE: ");
2035   for(i=0;i<32;i++)
2036     printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2037   printf("\n");
2038 #ifndef DISABLE_COP1
2039   printf("TRACE: ");
2040   for(i=0;i<32;i++)
2041     printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2042   printf("\n");
2043 #endif
2044 }
2045
2046 void enabletrace()
2047 {
2048   tracedebug=1;
2049 }
2050
2051 void memdebug(int i)
2052 {
2053   //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2054   //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2055   //rlist();
2056   //if(tracedebug) {
2057   //if(Count>=-2084597794) {
2058   if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2059   //if(0) {
2060     printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2061     //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2062     //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2063     rlist();
2064     #ifdef __i386__
2065     printf("TRACE: %x\n",(&i)[-1]);
2066     #endif
2067     #ifdef __arm__
2068     int j;
2069     printf("TRACE: %x \n",(&j)[10]);
2070     printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2071     #endif
2072     //fflush(stdout);
2073   }
2074   //printf("TRACE: %x\n",(&i)[-1]);
2075 }
2076
2077 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2078 {
2079   printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2080 }
2081
2082 void alu_assemble(int i,struct regstat *i_regs)
2083 {
2084   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2085     if(rt1[i]) {
2086       signed char s1,s2,t;
2087       t=get_reg(i_regs->regmap,rt1[i]);
2088       if(t>=0) {
2089         s1=get_reg(i_regs->regmap,rs1[i]);
2090         s2=get_reg(i_regs->regmap,rs2[i]);
2091         if(rs1[i]&&rs2[i]) {
2092           assert(s1>=0);
2093           assert(s2>=0);
2094           if(opcode2[i]&2) emit_sub(s1,s2,t);
2095           else emit_add(s1,s2,t);
2096         }
2097         else if(rs1[i]) {
2098           if(s1>=0) emit_mov(s1,t);
2099           else emit_loadreg(rs1[i],t);
2100         }
2101         else if(rs2[i]) {
2102           if(s2>=0) {
2103             if(opcode2[i]&2) emit_neg(s2,t);
2104             else emit_mov(s2,t);
2105           }
2106           else {
2107             emit_loadreg(rs2[i],t);
2108             if(opcode2[i]&2) emit_neg(t,t);
2109           }
2110         }
2111         else emit_zeroreg(t);
2112       }
2113     }
2114   }
2115   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2116     if(rt1[i]) {
2117       signed char s1l,s2l,s1h,s2h,tl,th;
2118       tl=get_reg(i_regs->regmap,rt1[i]);
2119       th=get_reg(i_regs->regmap,rt1[i]|64);
2120       if(tl>=0) {
2121         s1l=get_reg(i_regs->regmap,rs1[i]);
2122         s2l=get_reg(i_regs->regmap,rs2[i]);
2123         s1h=get_reg(i_regs->regmap,rs1[i]|64);
2124         s2h=get_reg(i_regs->regmap,rs2[i]|64);
2125         if(rs1[i]&&rs2[i]) {
2126           assert(s1l>=0);
2127           assert(s2l>=0);
2128           if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2129           else emit_adds(s1l,s2l,tl);
2130           if(th>=0) {
2131             #ifdef INVERTED_CARRY
2132             if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2133             #else
2134             if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2135             #endif
2136             else emit_add(s1h,s2h,th);
2137           }
2138         }
2139         else if(rs1[i]) {
2140           if(s1l>=0) emit_mov(s1l,tl);
2141           else emit_loadreg(rs1[i],tl);
2142           if(th>=0) {
2143             if(s1h>=0) emit_mov(s1h,th);
2144             else emit_loadreg(rs1[i]|64,th);
2145           }
2146         }
2147         else if(rs2[i]) {
2148           if(s2l>=0) {
2149             if(opcode2[i]&2) emit_negs(s2l,tl);
2150             else emit_mov(s2l,tl);
2151           }
2152           else {
2153             emit_loadreg(rs2[i],tl);
2154             if(opcode2[i]&2) emit_negs(tl,tl);
2155           }
2156           if(th>=0) {
2157             #ifdef INVERTED_CARRY
2158             if(s2h>=0) emit_mov(s2h,th);
2159             else emit_loadreg(rs2[i]|64,th);
2160             if(opcode2[i]&2) {
2161               emit_adcimm(-1,th); // x86 has inverted carry flag
2162               emit_not(th,th);
2163             }
2164             #else
2165             if(opcode2[i]&2) {
2166               if(s2h>=0) emit_rscimm(s2h,0,th);
2167               else {
2168                 emit_loadreg(rs2[i]|64,th);
2169                 emit_rscimm(th,0,th);
2170               }
2171             }else{
2172               if(s2h>=0) emit_mov(s2h,th);
2173               else emit_loadreg(rs2[i]|64,th);
2174             }
2175             #endif
2176           }
2177         }
2178         else {
2179           emit_zeroreg(tl);
2180           if(th>=0) emit_zeroreg(th);
2181         }
2182       }
2183     }
2184   }
2185   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2186     if(rt1[i]) {
2187       signed char s1l,s1h,s2l,s2h,t;
2188       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2189       {
2190         t=get_reg(i_regs->regmap,rt1[i]);
2191         //assert(t>=0);
2192         if(t>=0) {
2193           s1l=get_reg(i_regs->regmap,rs1[i]);
2194           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2195           s2l=get_reg(i_regs->regmap,rs2[i]);
2196           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2197           if(rs2[i]==0) // rx<r0
2198           {
2199             assert(s1h>=0);
2200             if(opcode2[i]==0x2a) // SLT
2201               emit_shrimm(s1h,31,t);
2202             else // SLTU (unsigned can not be less than zero)
2203               emit_zeroreg(t);
2204           }
2205           else if(rs1[i]==0) // r0<rx
2206           {
2207             assert(s2h>=0);
2208             if(opcode2[i]==0x2a) // SLT
2209               emit_set_gz64_32(s2h,s2l,t);
2210             else // SLTU (set if not zero)
2211               emit_set_nz64_32(s2h,s2l,t);
2212           }
2213           else {
2214             assert(s1l>=0);assert(s1h>=0);
2215             assert(s2l>=0);assert(s2h>=0);
2216             if(opcode2[i]==0x2a) // SLT
2217               emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2218             else // SLTU
2219               emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2220           }
2221         }
2222       } else {
2223         t=get_reg(i_regs->regmap,rt1[i]);
2224         //assert(t>=0);
2225         if(t>=0) {
2226           s1l=get_reg(i_regs->regmap,rs1[i]);
2227           s2l=get_reg(i_regs->regmap,rs2[i]);
2228           if(rs2[i]==0) // rx<r0
2229           {
2230             assert(s1l>=0);
2231             if(opcode2[i]==0x2a) // SLT
2232               emit_shrimm(s1l,31,t);
2233             else // SLTU (unsigned can not be less than zero)
2234               emit_zeroreg(t);
2235           }
2236           else if(rs1[i]==0) // r0<rx
2237           {
2238             assert(s2l>=0);
2239             if(opcode2[i]==0x2a) // SLT
2240               emit_set_gz32(s2l,t);
2241             else // SLTU (set if not zero)
2242               emit_set_nz32(s2l,t);
2243           }
2244           else{
2245             assert(s1l>=0);assert(s2l>=0);
2246             if(opcode2[i]==0x2a) // SLT
2247               emit_set_if_less32(s1l,s2l,t);
2248             else // SLTU
2249               emit_set_if_carry32(s1l,s2l,t);
2250           }
2251         }
2252       }
2253     }
2254   }
2255   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2256     if(rt1[i]) {
2257       signed char s1l,s1h,s2l,s2h,th,tl;
2258       tl=get_reg(i_regs->regmap,rt1[i]);
2259       th=get_reg(i_regs->regmap,rt1[i]|64);
2260       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2261       {
2262         assert(tl>=0);
2263         if(tl>=0) {
2264           s1l=get_reg(i_regs->regmap,rs1[i]);
2265           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2266           s2l=get_reg(i_regs->regmap,rs2[i]);
2267           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2268           if(rs1[i]&&rs2[i]) {
2269             assert(s1l>=0);assert(s1h>=0);
2270             assert(s2l>=0);assert(s2h>=0);
2271             if(opcode2[i]==0x24) { // AND
2272               emit_and(s1l,s2l,tl);
2273               emit_and(s1h,s2h,th);
2274             } else
2275             if(opcode2[i]==0x25) { // OR
2276               emit_or(s1l,s2l,tl);
2277               emit_or(s1h,s2h,th);
2278             } else
2279             if(opcode2[i]==0x26) { // XOR
2280               emit_xor(s1l,s2l,tl);
2281               emit_xor(s1h,s2h,th);
2282             } else
2283             if(opcode2[i]==0x27) { // NOR
2284               emit_or(s1l,s2l,tl);
2285               emit_or(s1h,s2h,th);
2286               emit_not(tl,tl);
2287               emit_not(th,th);
2288             }
2289           }
2290           else
2291           {
2292             if(opcode2[i]==0x24) { // AND
2293               emit_zeroreg(tl);
2294               emit_zeroreg(th);
2295             } else
2296             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2297               if(rs1[i]){
2298                 if(s1l>=0) emit_mov(s1l,tl);
2299                 else emit_loadreg(rs1[i],tl);
2300                 if(s1h>=0) emit_mov(s1h,th);
2301                 else emit_loadreg(rs1[i]|64,th);
2302               }
2303               else
2304               if(rs2[i]){
2305                 if(s2l>=0) emit_mov(s2l,tl);
2306                 else emit_loadreg(rs2[i],tl);
2307                 if(s2h>=0) emit_mov(s2h,th);
2308                 else emit_loadreg(rs2[i]|64,th);
2309               }
2310               else{
2311                 emit_zeroreg(tl);
2312                 emit_zeroreg(th);
2313               }
2314             } else
2315             if(opcode2[i]==0x27) { // NOR
2316               if(rs1[i]){
2317                 if(s1l>=0) emit_not(s1l,tl);
2318                 else{
2319                   emit_loadreg(rs1[i],tl);
2320                   emit_not(tl,tl);
2321                 }
2322                 if(s1h>=0) emit_not(s1h,th);
2323                 else{
2324                   emit_loadreg(rs1[i]|64,th);
2325                   emit_not(th,th);
2326                 }
2327               }
2328               else
2329               if(rs2[i]){
2330                 if(s2l>=0) emit_not(s2l,tl);
2331                 else{
2332                   emit_loadreg(rs2[i],tl);
2333                   emit_not(tl,tl);
2334                 }
2335                 if(s2h>=0) emit_not(s2h,th);
2336                 else{
2337                   emit_loadreg(rs2[i]|64,th);
2338                   emit_not(th,th);
2339                 }
2340               }
2341               else {
2342                 emit_movimm(-1,tl);
2343                 emit_movimm(-1,th);
2344               }
2345             }
2346           }
2347         }
2348       }
2349       else
2350       {
2351         // 32 bit
2352         if(tl>=0) {
2353           s1l=get_reg(i_regs->regmap,rs1[i]);
2354           s2l=get_reg(i_regs->regmap,rs2[i]);
2355           if(rs1[i]&&rs2[i]) {
2356             assert(s1l>=0);
2357             assert(s2l>=0);
2358             if(opcode2[i]==0x24) { // AND
2359               emit_and(s1l,s2l,tl);
2360             } else
2361             if(opcode2[i]==0x25) { // OR
2362               emit_or(s1l,s2l,tl);
2363             } else
2364             if(opcode2[i]==0x26) { // XOR
2365               emit_xor(s1l,s2l,tl);
2366             } else
2367             if(opcode2[i]==0x27) { // NOR
2368               emit_or(s1l,s2l,tl);
2369               emit_not(tl,tl);
2370             }
2371           }
2372           else
2373           {
2374             if(opcode2[i]==0x24) { // AND
2375               emit_zeroreg(tl);
2376             } else
2377             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2378               if(rs1[i]){
2379                 if(s1l>=0) emit_mov(s1l,tl);
2380                 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2381               }
2382               else
2383               if(rs2[i]){
2384                 if(s2l>=0) emit_mov(s2l,tl);
2385                 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2386               }
2387               else emit_zeroreg(tl);
2388             } else
2389             if(opcode2[i]==0x27) { // NOR
2390               if(rs1[i]){
2391                 if(s1l>=0) emit_not(s1l,tl);
2392                 else {
2393                   emit_loadreg(rs1[i],tl);
2394                   emit_not(tl,tl);
2395                 }
2396               }
2397               else
2398               if(rs2[i]){
2399                 if(s2l>=0) emit_not(s2l,tl);
2400                 else {
2401                   emit_loadreg(rs2[i],tl);
2402                   emit_not(tl,tl);
2403                 }
2404               }
2405               else emit_movimm(-1,tl);
2406             }
2407           }
2408         }
2409       }
2410     }
2411   }
2412 }
2413
2414 void imm16_assemble(int i,struct regstat *i_regs)
2415 {
2416   if (opcode[i]==0x0f) { // LUI
2417     if(rt1[i]) {
2418       signed char t;
2419       t=get_reg(i_regs->regmap,rt1[i]);
2420       //assert(t>=0);
2421       if(t>=0) {
2422         if(!((i_regs->isconst>>t)&1))
2423           emit_movimm(imm[i]<<16,t);
2424       }
2425     }
2426   }
2427   if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2428     if(rt1[i]) {
2429       signed char s,t;
2430       t=get_reg(i_regs->regmap,rt1[i]);
2431       s=get_reg(i_regs->regmap,rs1[i]);
2432       if(rs1[i]) {
2433         //assert(t>=0);
2434         //assert(s>=0);
2435         if(t>=0) {
2436           if(!((i_regs->isconst>>t)&1)) {
2437             if(s<0) {
2438               if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2439               emit_addimm(t,imm[i],t);
2440             }else{
2441               if(!((i_regs->wasconst>>s)&1))
2442                 emit_addimm(s,imm[i],t);
2443               else
2444                 emit_movimm(constmap[i][s]+imm[i],t);
2445             }
2446           }
2447         }
2448       } else {
2449         if(t>=0) {
2450           if(!((i_regs->isconst>>t)&1))
2451             emit_movimm(imm[i],t);
2452         }
2453       }
2454     }
2455   }
2456   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2457     if(rt1[i]) {
2458       signed char sh,sl,th,tl;
2459       th=get_reg(i_regs->regmap,rt1[i]|64);
2460       tl=get_reg(i_regs->regmap,rt1[i]);
2461       sh=get_reg(i_regs->regmap,rs1[i]|64);
2462       sl=get_reg(i_regs->regmap,rs1[i]);
2463       if(tl>=0) {
2464         if(rs1[i]) {
2465           assert(sh>=0);
2466           assert(sl>=0);
2467           if(th>=0) {
2468             emit_addimm64_32(sh,sl,imm[i],th,tl);
2469           }
2470           else {
2471             emit_addimm(sl,imm[i],tl);
2472           }
2473         } else {
2474           emit_movimm(imm[i],tl);
2475           if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2476         }
2477       }
2478     }
2479   }
2480   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2481     if(rt1[i]) {
2482       //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2483       signed char sh,sl,t;
2484       t=get_reg(i_regs->regmap,rt1[i]);
2485       sh=get_reg(i_regs->regmap,rs1[i]|64);
2486       sl=get_reg(i_regs->regmap,rs1[i]);
2487       //assert(t>=0);
2488       if(t>=0) {
2489         if(rs1[i]>0) {
2490           if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2491           if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2492             if(opcode[i]==0x0a) { // SLTI
2493               if(sl<0) {
2494                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2495                 emit_slti32(t,imm[i],t);
2496               }else{
2497                 emit_slti32(sl,imm[i],t);
2498               }
2499             }
2500             else { // SLTIU
2501               if(sl<0) {
2502                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2503                 emit_sltiu32(t,imm[i],t);
2504               }else{
2505                 emit_sltiu32(sl,imm[i],t);
2506               }
2507             }
2508           }else{ // 64-bit
2509             assert(sl>=0);
2510             if(opcode[i]==0x0a) // SLTI
2511               emit_slti64_32(sh,sl,imm[i],t);
2512             else // SLTIU
2513               emit_sltiu64_32(sh,sl,imm[i],t);
2514           }
2515         }else{
2516           // SLTI(U) with r0 is just stupid,
2517           // nonetheless examples can be found
2518           if(opcode[i]==0x0a) // SLTI
2519             if(0<imm[i]) emit_movimm(1,t);
2520             else emit_zeroreg(t);
2521           else // SLTIU
2522           {
2523             if(imm[i]) emit_movimm(1,t);
2524             else emit_zeroreg(t);
2525           }
2526         }
2527       }
2528     }
2529   }
2530   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2531     if(rt1[i]) {
2532       signed char sh,sl,th,tl;
2533       th=get_reg(i_regs->regmap,rt1[i]|64);
2534       tl=get_reg(i_regs->regmap,rt1[i]);
2535       sh=get_reg(i_regs->regmap,rs1[i]|64);
2536       sl=get_reg(i_regs->regmap,rs1[i]);
2537       if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2538         if(opcode[i]==0x0c) //ANDI
2539         {
2540           if(rs1[i]) {
2541             if(sl<0) {
2542               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2543               emit_andimm(tl,imm[i],tl);
2544             }else{
2545               if(!((i_regs->wasconst>>sl)&1))
2546                 emit_andimm(sl,imm[i],tl);
2547               else
2548                 emit_movimm(constmap[i][sl]&imm[i],tl);
2549             }
2550           }
2551           else
2552             emit_zeroreg(tl);
2553           if(th>=0) emit_zeroreg(th);
2554         }
2555         else
2556         {
2557           if(rs1[i]) {
2558             if(sl<0) {
2559               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2560             }
2561             if(th>=0) {
2562               if(sh<0) {
2563                 emit_loadreg(rs1[i]|64,th);
2564               }else{
2565                 emit_mov(sh,th);
2566               }
2567             }
2568             if(opcode[i]==0x0d) //ORI
2569             if(sl<0) {
2570               emit_orimm(tl,imm[i],tl);
2571             }else{
2572               if(!((i_regs->wasconst>>sl)&1))
2573                 emit_orimm(sl,imm[i],tl);
2574               else
2575                 emit_movimm(constmap[i][sl]|imm[i],tl);
2576             }
2577             if(opcode[i]==0x0e) //XORI
2578             if(sl<0) {
2579               emit_xorimm(tl,imm[i],tl);
2580             }else{
2581               if(!((i_regs->wasconst>>sl)&1))
2582                 emit_xorimm(sl,imm[i],tl);
2583               else
2584                 emit_movimm(constmap[i][sl]^imm[i],tl);
2585             }
2586           }
2587           else {
2588             emit_movimm(imm[i],tl);
2589             if(th>=0) emit_zeroreg(th);
2590           }
2591         }
2592       }
2593     }
2594   }
2595 }
2596
2597 void shiftimm_assemble(int i,struct regstat *i_regs)
2598 {
2599   if(opcode2[i]<=0x3) // SLL/SRL/SRA
2600   {
2601     if(rt1[i]) {
2602       signed char s,t;
2603       t=get_reg(i_regs->regmap,rt1[i]);
2604       s=get_reg(i_regs->regmap,rs1[i]);
2605       //assert(t>=0);
2606       if(t>=0){
2607         if(rs1[i]==0)
2608         {
2609           emit_zeroreg(t);
2610         }
2611         else
2612         {
2613           if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2614           if(imm[i]) {
2615             if(opcode2[i]==0) // SLL
2616             {
2617               emit_shlimm(s<0?t:s,imm[i],t);
2618             }
2619             if(opcode2[i]==2) // SRL
2620             {
2621               emit_shrimm(s<0?t:s,imm[i],t);
2622             }
2623             if(opcode2[i]==3) // SRA
2624             {
2625               emit_sarimm(s<0?t:s,imm[i],t);
2626             }
2627           }else{
2628             // Shift by zero
2629             if(s>=0 && s!=t) emit_mov(s,t);
2630           }
2631         }
2632       }
2633       //emit_storereg(rt1[i],t); //DEBUG
2634     }
2635   }
2636   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2637   {
2638     if(rt1[i]) {
2639       signed char sh,sl,th,tl;
2640       th=get_reg(i_regs->regmap,rt1[i]|64);
2641       tl=get_reg(i_regs->regmap,rt1[i]);
2642       sh=get_reg(i_regs->regmap,rs1[i]|64);
2643       sl=get_reg(i_regs->regmap,rs1[i]);
2644       if(tl>=0) {
2645         if(rs1[i]==0)
2646         {
2647           emit_zeroreg(tl);
2648           if(th>=0) emit_zeroreg(th);
2649         }
2650         else
2651         {
2652           assert(sl>=0);
2653           assert(sh>=0);
2654           if(imm[i]) {
2655             if(opcode2[i]==0x38) // DSLL
2656             {
2657               if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2658               emit_shlimm(sl,imm[i],tl);
2659             }
2660             if(opcode2[i]==0x3a) // DSRL
2661             {
2662               emit_shrdimm(sl,sh,imm[i],tl);
2663               if(th>=0) emit_shrimm(sh,imm[i],th);
2664             }
2665             if(opcode2[i]==0x3b) // DSRA
2666             {
2667               emit_shrdimm(sl,sh,imm[i],tl);
2668               if(th>=0) emit_sarimm(sh,imm[i],th);
2669             }
2670           }else{
2671             // Shift by zero
2672             if(sl!=tl) emit_mov(sl,tl);
2673             if(th>=0&&sh!=th) emit_mov(sh,th);
2674           }
2675         }
2676       }
2677     }
2678   }
2679   if(opcode2[i]==0x3c) // DSLL32
2680   {
2681     if(rt1[i]) {
2682       signed char sl,tl,th;
2683       tl=get_reg(i_regs->regmap,rt1[i]);
2684       th=get_reg(i_regs->regmap,rt1[i]|64);
2685       sl=get_reg(i_regs->regmap,rs1[i]);
2686       if(th>=0||tl>=0){
2687         assert(tl>=0);
2688         assert(th>=0);
2689         assert(sl>=0);
2690         emit_mov(sl,th);
2691         emit_zeroreg(tl);
2692         if(imm[i]>32)
2693         {
2694           emit_shlimm(th,imm[i]&31,th);
2695         }
2696       }
2697     }
2698   }
2699   if(opcode2[i]==0x3e) // DSRL32
2700   {
2701     if(rt1[i]) {
2702       signed char sh,tl,th;
2703       tl=get_reg(i_regs->regmap,rt1[i]);
2704       th=get_reg(i_regs->regmap,rt1[i]|64);
2705       sh=get_reg(i_regs->regmap,rs1[i]|64);
2706       if(tl>=0){
2707         assert(sh>=0);
2708         emit_mov(sh,tl);
2709         if(th>=0) emit_zeroreg(th);
2710         if(imm[i]>32)
2711         {
2712           emit_shrimm(tl,imm[i]&31,tl);
2713         }
2714       }
2715     }
2716   }
2717   if(opcode2[i]==0x3f) // DSRA32
2718   {
2719     if(rt1[i]) {
2720       signed char sh,tl;
2721       tl=get_reg(i_regs->regmap,rt1[i]);
2722       sh=get_reg(i_regs->regmap,rs1[i]|64);
2723       if(tl>=0){
2724         assert(sh>=0);
2725         emit_mov(sh,tl);
2726         if(imm[i]>32)
2727         {
2728           emit_sarimm(tl,imm[i]&31,tl);
2729         }
2730       }
2731     }
2732   }
2733 }
2734
2735 #ifndef shift_assemble
2736 void shift_assemble(int i,struct regstat *i_regs)
2737 {
2738   printf("Need shift_assemble for this architecture.\n");
2739   exit(1);
2740 }
2741 #endif
2742
2743 void load_assemble(int i,struct regstat *i_regs)
2744 {
2745   int s,th,tl,addr,map=-1;
2746   int offset;
2747   int jaddr=0;
2748   int memtarget=0,c=0;
2749   u_int hr,reglist=0;
2750   th=get_reg(i_regs->regmap,rt1[i]|64);
2751   tl=get_reg(i_regs->regmap,rt1[i]);
2752   s=get_reg(i_regs->regmap,rs1[i]);
2753   offset=imm[i];
2754   for(hr=0;hr<HOST_REGS;hr++) {
2755     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2756   }
2757   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2758   if(s>=0) {
2759     c=(i_regs->wasconst>>s)&1;
2760     memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2761     if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2762   }
2763   //printf("load_assemble: c=%d\n",c);
2764   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2765   // FIXME: Even if the load is a NOP, we should check for pagefaults...
2766 #ifdef PCSX
2767   if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2768     ||rt1[i]==0) {
2769       // could be FIFO, must perform the read
2770       // ||dummy read
2771       assem_debug("(forced read)\n");
2772       tl=get_reg(i_regs->regmap,-1);
2773       assert(tl>=0);
2774   }
2775 #endif
2776   if(offset||s<0||c) addr=tl;
2777   else addr=s;
2778   if(tl>=0) {
2779     //assert(tl>=0);
2780     //assert(rt1[i]);
2781     reglist&=~(1<<tl);
2782     if(th>=0) reglist&=~(1<<th);
2783     if(!using_tlb) {
2784       if(!c) {
2785 //#define R29_HACK 1
2786         #ifdef R29_HACK
2787         // Strmnnrmn's speed hack
2788         if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2789         #endif
2790         {
2791           emit_cmpimm(addr,RAM_SIZE);
2792           jaddr=(int)out;
2793           #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2794           // Hint to branch predictor that the branch is unlikely to be taken
2795           if(rs1[i]>=28)
2796             emit_jno_unlikely(0);
2797           else
2798           #endif
2799           emit_jno(0);
2800         }
2801       }
2802     }else{ // using tlb
2803       int x=0;
2804       if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2805       if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2806       map=get_reg(i_regs->regmap,TLREG);
2807       assert(map>=0);
2808       map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2809       do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2810     }
2811     if (opcode[i]==0x20) { // LB
2812       if(!c||memtarget) {
2813         #ifdef HOST_IMM_ADDR32
2814         if(c)
2815           emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2816         else
2817         #endif
2818         {
2819           //emit_xorimm(addr,3,tl);
2820           //gen_tlb_addr_r(tl,map);
2821           //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2822           int x=0;
2823 #ifdef BIG_ENDIAN_MIPS
2824           if(!c) emit_xorimm(addr,3,tl);
2825           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2826 #else
2827           if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2828           else if (tl!=addr) emit_mov(addr,tl);
2829 #endif
2830           emit_movsbl_indexed_tlb(x,tl,map,tl);
2831         }
2832         if(jaddr)
2833           add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2834       }
2835       else
2836         inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2837     }
2838     if (opcode[i]==0x21) { // LH
2839       if(!c||memtarget) {
2840         #ifdef HOST_IMM_ADDR32
2841         if(c)
2842           emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2843         else
2844         #endif
2845         {
2846           int x=0;
2847 #ifdef BIG_ENDIAN_MIPS
2848           if(!c) emit_xorimm(addr,2,tl);
2849           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2850 #else
2851           if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2852           else if (tl!=addr) emit_mov(addr,tl);
2853 #endif
2854           //#ifdef
2855           //emit_movswl_indexed_tlb(x,tl,map,tl);
2856           //else
2857           if(map>=0) {
2858             gen_tlb_addr_r(tl,map);
2859             emit_movswl_indexed(x,tl,tl);
2860           }else
2861             emit_movswl_indexed((int)rdram-0x80000000+x,tl,tl);
2862         }
2863         if(jaddr)
2864           add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2865       }
2866       else
2867         inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2868     }
2869     if (opcode[i]==0x23) { // LW
2870       if(!c||memtarget) {
2871         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2872         #ifdef HOST_IMM_ADDR32
2873         if(c)
2874           emit_readword_tlb(constmap[i][s]+offset,map,tl);
2875         else
2876         #endif
2877         emit_readword_indexed_tlb(0,addr,map,tl);
2878         if(jaddr)
2879           add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2880       }
2881       else
2882         inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2883     }
2884     if (opcode[i]==0x24) { // LBU
2885       if(!c||memtarget) {
2886         #ifdef HOST_IMM_ADDR32
2887         if(c)
2888           emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2889         else
2890         #endif
2891         {
2892           //emit_xorimm(addr,3,tl);
2893           //gen_tlb_addr_r(tl,map);
2894           //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
2895           int x=0;
2896 #ifdef BIG_ENDIAN_MIPS
2897           if(!c) emit_xorimm(addr,3,tl);
2898           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2899 #else
2900           if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2901           else if (tl!=addr) emit_mov(addr,tl);
2902 #endif
2903           emit_movzbl_indexed_tlb(x,tl,map,tl);
2904         }
2905         if(jaddr)
2906           add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2907       }
2908       else
2909         inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2910     }
2911     if (opcode[i]==0x25) { // LHU
2912       if(!c||memtarget) {
2913         #ifdef HOST_IMM_ADDR32
2914         if(c)
2915           emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2916         else
2917         #endif
2918         {
2919           int x=0;
2920 #ifdef BIG_ENDIAN_MIPS
2921           if(!c) emit_xorimm(addr,2,tl);
2922           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2923 #else
2924           if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2925           else if (tl!=addr) emit_mov(addr,tl);
2926 #endif
2927           //#ifdef
2928           //emit_movzwl_indexed_tlb(x,tl,map,tl);
2929           //#else
2930           if(map>=0) {
2931             gen_tlb_addr_r(tl,map);
2932             emit_movzwl_indexed(x,tl,tl);
2933           }else
2934             emit_movzwl_indexed((int)rdram-0x80000000+x,tl,tl);
2935           if(jaddr)
2936             add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2937         }
2938       }
2939       else
2940         inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2941     }
2942     if (opcode[i]==0x27) { // LWU
2943       assert(th>=0);
2944       if(!c||memtarget) {
2945         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2946         #ifdef HOST_IMM_ADDR32
2947         if(c)
2948           emit_readword_tlb(constmap[i][s]+offset,map,tl);
2949         else
2950         #endif
2951         emit_readword_indexed_tlb(0,addr,map,tl);
2952         if(jaddr)
2953           add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2954       }
2955       else {
2956         inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2957       }
2958       emit_zeroreg(th);
2959     }
2960     if (opcode[i]==0x37) { // LD
2961       if(!c||memtarget) {
2962         //gen_tlb_addr_r(tl,map);
2963         //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
2964         //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
2965         #ifdef HOST_IMM_ADDR32
2966         if(c)
2967           emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
2968         else
2969         #endif
2970         emit_readdword_indexed_tlb(0,addr,map,th,tl);
2971         if(jaddr)
2972           add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2973       }
2974       else
2975         inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2976     }
2977     //emit_storereg(rt1[i],tl); // DEBUG
2978   }
2979   //if(opcode[i]==0x23)
2980   //if(opcode[i]==0x24)
2981   //if(opcode[i]==0x23||opcode[i]==0x24)
2982   /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
2983   {
2984     //emit_pusha();
2985     save_regs(0x100f);
2986         emit_readword((int)&last_count,ECX);
2987         #ifdef __i386__
2988         if(get_reg(i_regs->regmap,CCREG)<0)
2989           emit_loadreg(CCREG,HOST_CCREG);
2990         emit_add(HOST_CCREG,ECX,HOST_CCREG);
2991         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
2992         emit_writeword(HOST_CCREG,(int)&Count);
2993         #endif
2994         #ifdef __arm__
2995         if(get_reg(i_regs->regmap,CCREG)<0)
2996           emit_loadreg(CCREG,0);
2997         else
2998           emit_mov(HOST_CCREG,0);
2999         emit_add(0,ECX,0);
3000         emit_addimm(0,2*ccadj[i],0);
3001         emit_writeword(0,(int)&Count);
3002         #endif
3003     emit_call((int)memdebug);
3004     //emit_popa();
3005     restore_regs(0x100f);
3006   }/**/
3007 }
3008
3009 #ifndef loadlr_assemble
3010 void loadlr_assemble(int i,struct regstat *i_regs)
3011 {
3012   printf("Need loadlr_assemble for this architecture.\n");
3013   exit(1);
3014 }
3015 #endif
3016
3017 void store_assemble(int i,struct regstat *i_regs)
3018 {
3019   int s,th,tl,map=-1;
3020   int addr,temp;
3021   int offset;
3022   int jaddr=0,jaddr2,type;
3023   int memtarget=0,c=0;
3024   int agr=AGEN1+(i&1);
3025   u_int hr,reglist=0;
3026   th=get_reg(i_regs->regmap,rs2[i]|64);
3027   tl=get_reg(i_regs->regmap,rs2[i]);
3028   s=get_reg(i_regs->regmap,rs1[i]);
3029   temp=get_reg(i_regs->regmap,agr);
3030   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3031   offset=imm[i];
3032   if(s>=0) {
3033     c=(i_regs->wasconst>>s)&1;
3034     memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3035     if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3036   }
3037   assert(tl>=0);
3038   assert(temp>=0);
3039   for(hr=0;hr<HOST_REGS;hr++) {
3040     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3041   }
3042   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3043   if(offset||s<0||c) addr=temp;
3044   else addr=s;
3045   if(!using_tlb) {
3046     if(!c) {
3047       #ifdef R29_HACK
3048       // Strmnnrmn's speed hack
3049       memtarget=1;
3050       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3051       #endif
3052       emit_cmpimm(addr,RAM_SIZE);
3053       #ifdef DESTRUCTIVE_SHIFT
3054       if(s==addr) emit_mov(s,temp);
3055       #endif
3056       #ifdef R29_HACK
3057       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3058       #endif
3059       {
3060         jaddr=(int)out;
3061         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3062         // Hint to branch predictor that the branch is unlikely to be taken
3063         if(rs1[i]>=28)
3064           emit_jno_unlikely(0);
3065         else
3066         #endif
3067         emit_jno(0);
3068       }
3069     }
3070   }else{ // using tlb
3071     int x=0;
3072     if (opcode[i]==0x28) x=3; // SB
3073     if (opcode[i]==0x29) x=2; // SH
3074     map=get_reg(i_regs->regmap,TLREG);
3075     assert(map>=0);
3076     map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3077     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3078   }
3079
3080   if (opcode[i]==0x28) { // SB
3081     if(!c||memtarget) {
3082       int x=0;
3083 #ifdef BIG_ENDIAN_MIPS
3084       if(!c) emit_xorimm(addr,3,temp);
3085       else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3086 #else
3087       if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3088       else if (addr!=temp) emit_mov(addr,temp);
3089 #endif
3090       //gen_tlb_addr_w(temp,map);
3091       //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3092       emit_writebyte_indexed_tlb(tl,x,temp,map,temp);
3093     }
3094     type=STOREB_STUB;
3095   }
3096   if (opcode[i]==0x29) { // SH
3097     if(!c||memtarget) {
3098       int x=0;
3099 #ifdef BIG_ENDIAN_MIPS
3100       if(!c) emit_xorimm(addr,2,temp);
3101       else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3102 #else
3103       if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3104       else if (addr!=temp) emit_mov(addr,temp);
3105 #endif
3106       //#ifdef
3107       //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3108       //#else
3109       if(map>=0) {
3110         gen_tlb_addr_w(temp,map);
3111         emit_writehword_indexed(tl,x,temp);
3112       }else
3113         emit_writehword_indexed(tl,(int)rdram-0x80000000+x,temp);
3114     }
3115     type=STOREH_STUB;
3116   }
3117   if (opcode[i]==0x2B) { // SW
3118     if(!c||memtarget)
3119       //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3120       emit_writeword_indexed_tlb(tl,0,addr,map,temp);
3121     type=STOREW_STUB;
3122   }
3123   if (opcode[i]==0x3F) { // SD
3124     if(!c||memtarget) {
3125       if(rs2[i]) {
3126         assert(th>=0);
3127         //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3128         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3129         emit_writedword_indexed_tlb(th,tl,0,addr,map,temp);
3130       }else{
3131         // Store zero
3132         //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3133         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3134         emit_writedword_indexed_tlb(tl,tl,0,addr,map,temp);
3135       }
3136     }
3137     type=STORED_STUB;
3138   }
3139   if(!using_tlb&&(!c||memtarget))
3140     // addr could be a temp, make sure it survives STORE*_STUB
3141     reglist|=1<<addr;
3142   if(jaddr) {
3143     add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3144   } else if(!memtarget) {
3145     inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3146   }
3147   if(!using_tlb) {
3148     if(!c||memtarget) {
3149       #ifdef DESTRUCTIVE_SHIFT
3150       // The x86 shift operation is 'destructive'; it overwrites the
3151       // source register, so we need to make a copy first and use that.
3152       addr=temp;
3153       #endif
3154       #if defined(HOST_IMM8)
3155       int ir=get_reg(i_regs->regmap,INVCP);
3156       assert(ir>=0);
3157       emit_cmpmem_indexedsr12_reg(ir,addr,1);
3158       #else
3159       emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3160       #endif
3161       jaddr2=(int)out;
3162       emit_jne(0);
3163       add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3164     }
3165   }
3166   //if(opcode[i]==0x2B || opcode[i]==0x3F)
3167   //if(opcode[i]==0x2B || opcode[i]==0x28)
3168   //if(opcode[i]==0x2B || opcode[i]==0x29)
3169   //if(opcode[i]==0x2B)
3170   /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3171   {
3172     //emit_pusha();
3173     save_regs(0x100f);
3174         emit_readword((int)&last_count,ECX);
3175         #ifdef __i386__
3176         if(get_reg(i_regs->regmap,CCREG)<0)
3177           emit_loadreg(CCREG,HOST_CCREG);
3178         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3179         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3180         emit_writeword(HOST_CCREG,(int)&Count);
3181         #endif
3182         #ifdef __arm__
3183         if(get_reg(i_regs->regmap,CCREG)<0)
3184           emit_loadreg(CCREG,0);
3185         else
3186           emit_mov(HOST_CCREG,0);
3187         emit_add(0,ECX,0);
3188         emit_addimm(0,2*ccadj[i],0);
3189         emit_writeword(0,(int)&Count);
3190         #endif
3191     emit_call((int)memdebug);
3192     //emit_popa();
3193     restore_regs(0x100f);
3194   }/**/
3195 }
3196
3197 void storelr_assemble(int i,struct regstat *i_regs)
3198 {
3199   int s,th,tl;
3200   int temp;
3201   int temp2;
3202   int offset;
3203   int jaddr=0,jaddr2;
3204   int case1,case2,case3;
3205   int done0,done1,done2;
3206   int memtarget,c=0;
3207   int agr=AGEN1+(i&1);
3208   u_int hr,reglist=0;
3209   th=get_reg(i_regs->regmap,rs2[i]|64);
3210   tl=get_reg(i_regs->regmap,rs2[i]);
3211   s=get_reg(i_regs->regmap,rs1[i]);
3212   temp=get_reg(i_regs->regmap,agr);
3213   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3214   offset=imm[i];
3215   if(s>=0) {
3216     c=(i_regs->isconst>>s)&1;
3217     memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3218     if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3219   }
3220   assert(tl>=0);
3221   for(hr=0;hr<HOST_REGS;hr++) {
3222     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3223   }
3224   if(tl>=0) {
3225     assert(temp>=0);
3226     if(!using_tlb) {
3227       if(!c) {
3228         emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3229         if(!offset&&s!=temp) emit_mov(s,temp);
3230         jaddr=(int)out;
3231         emit_jno(0);
3232       }
3233       else
3234       {
3235         if(!memtarget||!rs1[i]) {
3236           jaddr=(int)out;
3237           emit_jmp(0);
3238         }
3239       }
3240       if((u_int)rdram!=0x80000000)
3241         emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3242     }else{ // using tlb
3243       int map=get_reg(i_regs->regmap,TLREG);
3244       assert(map>=0);
3245       map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3246       if(!c&&!offset&&s>=0) emit_mov(s,temp);
3247       do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3248       if(!jaddr&&!memtarget) {
3249         jaddr=(int)out;
3250         emit_jmp(0);
3251       }
3252       gen_tlb_addr_w(temp,map);
3253     }
3254
3255     if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3256       temp2=get_reg(i_regs->regmap,FTEMP);
3257       if(!rs2[i]) temp2=th=tl;
3258     }
3259
3260 #ifndef BIG_ENDIAN_MIPS
3261     emit_xorimm(temp,3,temp);
3262 #endif
3263     emit_testimm(temp,2);
3264     case2=(int)out;
3265     emit_jne(0);
3266     emit_testimm(temp,1);
3267     case1=(int)out;
3268     emit_jne(0);
3269     // 0
3270     if (opcode[i]==0x2A) { // SWL
3271       emit_writeword_indexed(tl,0,temp);
3272     }
3273     if (opcode[i]==0x2E) { // SWR
3274       emit_writebyte_indexed(tl,3,temp);
3275     }
3276     if (opcode[i]==0x2C) { // SDL
3277       emit_writeword_indexed(th,0,temp);
3278       if(rs2[i]) emit_mov(tl,temp2);
3279     }
3280     if (opcode[i]==0x2D) { // SDR
3281       emit_writebyte_indexed(tl,3,temp);
3282       if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3283     }
3284     done0=(int)out;
3285     emit_jmp(0);
3286     // 1
3287     set_jump_target(case1,(int)out);
3288     if (opcode[i]==0x2A) { // SWL
3289       // Write 3 msb into three least significant bytes
3290       if(rs2[i]) emit_rorimm(tl,8,tl);
3291       emit_writehword_indexed(tl,-1,temp);
3292       if(rs2[i]) emit_rorimm(tl,16,tl);
3293       emit_writebyte_indexed(tl,1,temp);
3294       if(rs2[i]) emit_rorimm(tl,8,tl);
3295     }
3296     if (opcode[i]==0x2E) { // SWR
3297       // Write two lsb into two most significant bytes
3298       emit_writehword_indexed(tl,1,temp);
3299     }
3300     if (opcode[i]==0x2C) { // SDL
3301       if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3302       // Write 3 msb into three least significant bytes
3303       if(rs2[i]) emit_rorimm(th,8,th);
3304       emit_writehword_indexed(th,-1,temp);
3305       if(rs2[i]) emit_rorimm(th,16,th);
3306       emit_writebyte_indexed(th,1,temp);
3307       if(rs2[i]) emit_rorimm(th,8,th);
3308     }
3309     if (opcode[i]==0x2D) { // SDR
3310       if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3311       // Write two lsb into two most significant bytes
3312       emit_writehword_indexed(tl,1,temp);
3313     }
3314     done1=(int)out;
3315     emit_jmp(0);
3316     // 2
3317     set_jump_target(case2,(int)out);
3318     emit_testimm(temp,1);
3319     case3=(int)out;
3320     emit_jne(0);
3321     if (opcode[i]==0x2A) { // SWL
3322       // Write two msb into two least significant bytes
3323       if(rs2[i]) emit_rorimm(tl,16,tl);
3324       emit_writehword_indexed(tl,-2,temp);
3325       if(rs2[i]) emit_rorimm(tl,16,tl);
3326     }
3327     if (opcode[i]==0x2E) { // SWR
3328       // Write 3 lsb into three most significant bytes
3329       emit_writebyte_indexed(tl,-1,temp);
3330       if(rs2[i]) emit_rorimm(tl,8,tl);
3331       emit_writehword_indexed(tl,0,temp);
3332       if(rs2[i]) emit_rorimm(tl,24,tl);
3333     }
3334     if (opcode[i]==0x2C) { // SDL
3335       if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3336       // Write two msb into two least significant bytes
3337       if(rs2[i]) emit_rorimm(th,16,th);
3338       emit_writehword_indexed(th,-2,temp);
3339       if(rs2[i]) emit_rorimm(th,16,th);
3340     }
3341     if (opcode[i]==0x2D) { // SDR
3342       if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3343       // Write 3 lsb into three most significant bytes
3344       emit_writebyte_indexed(tl,-1,temp);
3345       if(rs2[i]) emit_rorimm(tl,8,tl);
3346       emit_writehword_indexed(tl,0,temp);
3347       if(rs2[i]) emit_rorimm(tl,24,tl);
3348     }
3349     done2=(int)out;
3350     emit_jmp(0);
3351     // 3
3352     set_jump_target(case3,(int)out);
3353     if (opcode[i]==0x2A) { // SWL
3354       // Write msb into least significant byte
3355       if(rs2[i]) emit_rorimm(tl,24,tl);
3356       emit_writebyte_indexed(tl,-3,temp);
3357       if(rs2[i]) emit_rorimm(tl,8,tl);
3358     }
3359     if (opcode[i]==0x2E) { // SWR
3360       // Write entire word
3361       emit_writeword_indexed(tl,-3,temp);
3362     }
3363     if (opcode[i]==0x2C) { // SDL
3364       if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3365       // Write msb into least significant byte
3366       if(rs2[i]) emit_rorimm(th,24,th);
3367       emit_writebyte_indexed(th,-3,temp);
3368       if(rs2[i]) emit_rorimm(th,8,th);
3369     }
3370     if (opcode[i]==0x2D) { // SDR
3371       if(rs2[i]) emit_mov(th,temp2);
3372       // Write entire word
3373       emit_writeword_indexed(tl,-3,temp);
3374     }
3375     set_jump_target(done0,(int)out);
3376     set_jump_target(done1,(int)out);
3377     set_jump_target(done2,(int)out);
3378     if (opcode[i]==0x2C) { // SDL
3379       emit_testimm(temp,4);
3380       done0=(int)out;
3381       emit_jne(0);
3382       emit_andimm(temp,~3,temp);
3383       emit_writeword_indexed(temp2,4,temp);
3384       set_jump_target(done0,(int)out);
3385     }
3386     if (opcode[i]==0x2D) { // SDR
3387       emit_testimm(temp,4);
3388       done0=(int)out;
3389       emit_jeq(0);
3390       emit_andimm(temp,~3,temp);
3391       emit_writeword_indexed(temp2,-4,temp);
3392       set_jump_target(done0,(int)out);
3393     }
3394     if(!c||!memtarget)
3395       add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
3396   }
3397   if(!using_tlb) {
3398     emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3399     #if defined(HOST_IMM8)
3400     int ir=get_reg(i_regs->regmap,INVCP);
3401     assert(ir>=0);
3402     emit_cmpmem_indexedsr12_reg(ir,temp,1);
3403     #else
3404     emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3405     #endif
3406     jaddr2=(int)out;
3407     emit_jne(0);
3408     add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3409   }
3410   /*
3411     emit_pusha();
3412     //save_regs(0x100f);
3413         emit_readword((int)&last_count,ECX);
3414         if(get_reg(i_regs->regmap,CCREG)<0)
3415           emit_loadreg(CCREG,HOST_CCREG);
3416         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3417         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3418         emit_writeword(HOST_CCREG,(int)&Count);
3419     emit_call((int)memdebug);
3420     emit_popa();
3421     //restore_regs(0x100f);
3422   /**/
3423 }
3424
3425 void c1ls_assemble(int i,struct regstat *i_regs)
3426 {
3427 #ifndef DISABLE_COP1
3428   int s,th,tl;
3429   int temp,ar;
3430   int map=-1;
3431   int offset;
3432   int c=0;
3433   int jaddr,jaddr2=0,jaddr3,type;
3434   int agr=AGEN1+(i&1);
3435   u_int hr,reglist=0;
3436   th=get_reg(i_regs->regmap,FTEMP|64);
3437   tl=get_reg(i_regs->regmap,FTEMP);
3438   s=get_reg(i_regs->regmap,rs1[i]);
3439   temp=get_reg(i_regs->regmap,agr);
3440   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3441   offset=imm[i];
3442   assert(tl>=0);
3443   assert(rs1[i]>0);
3444   assert(temp>=0);
3445   for(hr=0;hr<HOST_REGS;hr++) {
3446     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3447   }
3448   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3449   if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3450   {
3451     // Loads use a temporary register which we need to save
3452     reglist|=1<<temp;
3453   }
3454   if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3455     ar=temp;
3456   else // LWC1/LDC1
3457     ar=tl;
3458   //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3459   //else c=(i_regs->wasconst>>s)&1;
3460   if(s>=0) c=(i_regs->wasconst>>s)&1;
3461   // Check cop1 unusable
3462   if(!cop1_usable) {
3463     signed char rs=get_reg(i_regs->regmap,CSREG);
3464     assert(rs>=0);
3465     emit_testimm(rs,0x20000000);
3466     jaddr=(int)out;
3467     emit_jeq(0);
3468     add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3469     cop1_usable=1;
3470   }
3471   if (opcode[i]==0x39) { // SWC1 (get float address)
3472     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],tl);
3473   }
3474   if (opcode[i]==0x3D) { // SDC1 (get double address)
3475     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],tl);
3476   }
3477   // Generate address + offset
3478   if(!using_tlb) {
3479     if(!c)
3480       emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3481   }
3482   else
3483   {
3484     map=get_reg(i_regs->regmap,TLREG);
3485     assert(map>=0);
3486     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3487       map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3488     }
3489     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3490       map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3491     }
3492   }
3493   if (opcode[i]==0x39) { // SWC1 (read float)
3494     emit_readword_indexed(0,tl,tl);
3495   }
3496   if (opcode[i]==0x3D) { // SDC1 (read double)
3497     emit_readword_indexed(4,tl,th);
3498     emit_readword_indexed(0,tl,tl);
3499   }
3500   if (opcode[i]==0x31) { // LWC1 (get target address)
3501     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],temp);
3502   }
3503   if (opcode[i]==0x35) { // LDC1 (get target address)
3504     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],temp);
3505   }
3506   if(!using_tlb) {
3507     if(!c) {
3508       jaddr2=(int)out;
3509       emit_jno(0);
3510     }
3511     else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
3512       jaddr2=(int)out;
3513       emit_jmp(0); // inline_readstub/inline_writestub?  Very rare case
3514     }
3515     #ifdef DESTRUCTIVE_SHIFT
3516     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3517       if(!offset&&!c&&s>=0) emit_mov(s,ar);
3518     }
3519     #endif
3520   }else{
3521     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3522       do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3523     }
3524     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3525       do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3526     }
3527   }
3528   if (opcode[i]==0x31) { // LWC1
3529     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3530     //gen_tlb_addr_r(ar,map);
3531     //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3532     #ifdef HOST_IMM_ADDR32
3533     if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3534     else
3535     #endif
3536     emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3537     type=LOADW_STUB;
3538   }
3539   if (opcode[i]==0x35) { // LDC1
3540     assert(th>=0);
3541     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3542     //gen_tlb_addr_r(ar,map);
3543     //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3544     //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3545     #ifdef HOST_IMM_ADDR32
3546     if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3547     else
3548     #endif
3549     emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3550     type=LOADD_STUB;
3551   }
3552   if (opcode[i]==0x39) { // SWC1
3553     //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3554     emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3555     type=STOREW_STUB;
3556   }
3557   if (opcode[i]==0x3D) { // SDC1
3558     assert(th>=0);
3559     //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3560     //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3561     emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3562     type=STORED_STUB;
3563   }
3564   if(!using_tlb) {
3565     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3566       #ifndef DESTRUCTIVE_SHIFT
3567       temp=offset||c||s<0?ar:s;
3568       #endif
3569       #if defined(HOST_IMM8)
3570       int ir=get_reg(i_regs->regmap,INVCP);
3571       assert(ir>=0);
3572       emit_cmpmem_indexedsr12_reg(ir,temp,1);
3573       #else
3574       emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3575       #endif
3576       jaddr3=(int)out;
3577       emit_jne(0);
3578       add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3579     }
3580   }
3581   if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3582   if (opcode[i]==0x31) { // LWC1 (write float)
3583     emit_writeword_indexed(tl,0,temp);
3584   }
3585   if (opcode[i]==0x35) { // LDC1 (write double)
3586     emit_writeword_indexed(th,4,temp);
3587     emit_writeword_indexed(tl,0,temp);
3588   }
3589   //if(opcode[i]==0x39)
3590   /*if(opcode[i]==0x39||opcode[i]==0x31)
3591   {
3592     emit_pusha();
3593         emit_readword((int)&last_count,ECX);
3594         if(get_reg(i_regs->regmap,CCREG)<0)
3595           emit_loadreg(CCREG,HOST_CCREG);
3596         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3597         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3598         emit_writeword(HOST_CCREG,(int)&Count);
3599     emit_call((int)memdebug);
3600     emit_popa();
3601   }/**/
3602 #else
3603   cop1_unusable(i, i_regs);
3604 #endif
3605 }
3606
3607 void c2ls_assemble(int i,struct regstat *i_regs)
3608 {
3609   int s,tl;
3610   int ar;
3611   int offset;
3612   int memtarget=0,c=0;
3613   int jaddr,jaddr2=0,jaddr3,type;
3614   int agr=AGEN1+(i&1);
3615   u_int hr,reglist=0;
3616   u_int copr=(source[i]>>16)&0x1f;
3617   s=get_reg(i_regs->regmap,rs1[i]);
3618   tl=get_reg(i_regs->regmap,FTEMP);
3619   offset=imm[i];
3620   assert(rs1[i]>0);
3621   assert(tl>=0);
3622   assert(!using_tlb);
3623
3624   for(hr=0;hr<HOST_REGS;hr++) {
3625     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3626   }
3627   if(i_regs->regmap[HOST_CCREG]==CCREG)
3628     reglist&=~(1<<HOST_CCREG);
3629
3630   // get the address
3631   if (opcode[i]==0x3a) { // SWC2
3632     ar=get_reg(i_regs->regmap,agr);
3633     if(ar<0) ar=get_reg(i_regs->regmap,-1);
3634     reglist|=1<<ar;
3635   } else { // LWC2
3636     ar=tl;
3637   }
3638   if(s>=0) c=(i_regs->wasconst>>s)&1;
3639   memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3640   if (!offset&&!c&&s>=0) ar=s;
3641   assert(ar>=0);
3642
3643   if (opcode[i]==0x3a) { // SWC2
3644     cop2_get_dreg(copr,tl,HOST_TEMPREG);
3645     type=STOREW_STUB;
3646   }
3647   else
3648     type=LOADW_STUB;
3649
3650   if(c&&!memtarget) {
3651     jaddr2=(int)out;
3652     emit_jmp(0); // inline_readstub/inline_writestub?
3653   }
3654   else {
3655     if(!c) {
3656       emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3657       jaddr2=(int)out;
3658       emit_jno(0);
3659     }
3660     if (opcode[i]==0x32) { // LWC2
3661       #ifdef HOST_IMM_ADDR32
3662       if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3663       else
3664       #endif
3665       emit_readword_indexed(0,ar,tl);
3666     }
3667     if (opcode[i]==0x3a) { // SWC2
3668       #ifdef DESTRUCTIVE_SHIFT
3669       if(!offset&&!c&&s>=0) emit_mov(s,ar);
3670       #endif
3671       emit_writeword_indexed(tl,0,ar);
3672     }
3673   }
3674   if(jaddr2)
3675     add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3676   if (opcode[i]==0x3a) { // SWC2
3677 #if defined(HOST_IMM8)
3678     int ir=get_reg(i_regs->regmap,INVCP);
3679     assert(ir>=0);
3680     emit_cmpmem_indexedsr12_reg(ir,ar,1);
3681 #else
3682     emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3683 #endif
3684     jaddr3=(int)out;
3685     emit_jne(0);
3686     add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3687   }
3688   if (opcode[i]==0x32) { // LWC2
3689     cop2_put_dreg(copr,tl,HOST_TEMPREG);
3690   }
3691 }
3692
3693 #ifndef multdiv_assemble
3694 void multdiv_assemble(int i,struct regstat *i_regs)
3695 {
3696   printf("Need multdiv_assemble for this architecture.\n");
3697   exit(1);
3698 }
3699 #endif
3700
3701 void mov_assemble(int i,struct regstat *i_regs)
3702 {
3703   //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3704   //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3705   //assert(rt1[i]>0);
3706   if(rt1[i]) {
3707     signed char sh,sl,th,tl;
3708     th=get_reg(i_regs->regmap,rt1[i]|64);
3709     tl=get_reg(i_regs->regmap,rt1[i]);
3710     //assert(tl>=0);
3711     if(tl>=0) {
3712       sh=get_reg(i_regs->regmap,rs1[i]|64);
3713       sl=get_reg(i_regs->regmap,rs1[i]);
3714       if(sl>=0) emit_mov(sl,tl);
3715       else emit_loadreg(rs1[i],tl);
3716       if(th>=0) {
3717         if(sh>=0) emit_mov(sh,th);
3718         else emit_loadreg(rs1[i]|64,th);
3719       }
3720     }
3721   }
3722 }
3723
3724 #ifndef fconv_assemble
3725 void fconv_assemble(int i,struct regstat *i_regs)
3726 {
3727   printf("Need fconv_assemble for this architecture.\n");
3728   exit(1);
3729 }
3730 #endif
3731
3732 #if 0
3733 void float_assemble(int i,struct regstat *i_regs)
3734 {
3735   printf("Need float_assemble for this architecture.\n");
3736   exit(1);
3737 }
3738 #endif
3739
3740 void syscall_assemble(int i,struct regstat *i_regs)
3741 {
3742   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3743   assert(ccreg==HOST_CCREG);
3744   assert(!is_delayslot);
3745   emit_movimm(start+i*4,EAX); // Get PC
3746   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right?  There should probably be an extra cycle...
3747   emit_jmp((int)jump_syscall_hle); // XXX
3748 }
3749
3750 void hlecall_assemble(int i,struct regstat *i_regs)
3751 {
3752   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3753   assert(ccreg==HOST_CCREG);
3754   assert(!is_delayslot);
3755   emit_movimm(start+i*4+4,0); // Get PC
3756   emit_movimm((int)psxHLEt[source[i]&7],1);
3757   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // XXX
3758   emit_jmp((int)jump_hlecall);
3759 }
3760
3761 void intcall_assemble(int i,struct regstat *i_regs)
3762 {
3763   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3764   assert(ccreg==HOST_CCREG);
3765   assert(!is_delayslot);
3766   emit_movimm(start+i*4,0); // Get PC
3767   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3768   emit_jmp((int)jump_intcall);
3769 }
3770
3771 void ds_assemble(int i,struct regstat *i_regs)
3772 {
3773   is_delayslot=1;
3774   switch(itype[i]) {
3775     case ALU:
3776       alu_assemble(i,i_regs);break;
3777     case IMM16:
3778       imm16_assemble(i,i_regs);break;
3779     case SHIFT:
3780       shift_assemble(i,i_regs);break;
3781     case SHIFTIMM:
3782       shiftimm_assemble(i,i_regs);break;
3783     case LOAD:
3784       load_assemble(i,i_regs);break;
3785     case LOADLR:
3786       loadlr_assemble(i,i_regs);break;
3787     case STORE:
3788       store_assemble(i,i_regs);break;
3789     case STORELR:
3790       storelr_assemble(i,i_regs);break;
3791     case COP0:
3792       cop0_assemble(i,i_regs);break;
3793     case COP1:
3794       cop1_assemble(i,i_regs);break;
3795     case C1LS:
3796       c1ls_assemble(i,i_regs);break;
3797     case COP2:
3798       cop2_assemble(i,i_regs);break;
3799     case C2LS:
3800       c2ls_assemble(i,i_regs);break;
3801     case C2OP:
3802       c2op_assemble(i,i_regs);break;
3803     case FCONV:
3804       fconv_assemble(i,i_regs);break;
3805     case FLOAT:
3806       float_assemble(i,i_regs);break;
3807     case FCOMP:
3808       fcomp_assemble(i,i_regs);break;
3809     case MULTDIV:
3810       multdiv_assemble(i,i_regs);break;
3811     case MOV:
3812       mov_assemble(i,i_regs);break;
3813     case SYSCALL:
3814     case HLECALL:
3815     case INTCALL:
3816     case SPAN:
3817     case UJUMP:
3818     case RJUMP:
3819     case CJUMP:
3820     case SJUMP:
3821     case FJUMP:
3822       printf("Jump in the delay slot.  This is probably a bug.\n");
3823   }
3824   is_delayslot=0;
3825 }
3826
3827 // Is the branch target a valid internal jump?
3828 int internal_branch(uint64_t i_is32,int addr)
3829 {
3830   if(addr&1) return 0; // Indirect (register) jump
3831   if(addr>=start && addr<start+slen*4-4)
3832   {
3833     int t=(addr-start)>>2;
3834     // Delay slots are not valid branch targets
3835     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
3836     // 64 -> 32 bit transition requires a recompile
3837     /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
3838     {
3839       if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
3840       else printf("optimizable: yes\n");
3841     }*/
3842     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
3843 #ifndef FORCE32
3844     if(requires_32bit[t]&~i_is32) return 0;
3845     else
3846 #endif
3847       return 1;
3848   }
3849   return 0;
3850 }
3851
3852 #ifndef wb_invalidate
3853 void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
3854   uint64_t u,uint64_t uu)
3855 {
3856   int hr;
3857   for(hr=0;hr<HOST_REGS;hr++) {
3858     if(hr!=EXCLUDE_REG) {
3859       if(pre[hr]!=entry[hr]) {
3860         if(pre[hr]>=0) {
3861           if((dirty>>hr)&1) {
3862             if(get_reg(entry,pre[hr])<0) {
3863               if(pre[hr]<64) {
3864                 if(!((u>>pre[hr])&1)) {
3865                   emit_storereg(pre[hr],hr);
3866                   if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
3867                     emit_sarimm(hr,31,hr);
3868                     emit_storereg(pre[hr]|64,hr);
3869                   }
3870                 }
3871               }else{
3872                 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
3873                   emit_storereg(pre[hr],hr);
3874                 }
3875               }
3876             }
3877           }
3878         }
3879       }
3880     }
3881   }
3882   // Move from one register to another (no writeback)
3883   for(hr=0;hr<HOST_REGS;hr++) {
3884     if(hr!=EXCLUDE_REG) {
3885       if(pre[hr]!=entry[hr]) {
3886         if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
3887           int nr;
3888           if((nr=get_reg(entry,pre[hr]))>=0) {
3889             emit_mov(hr,nr);
3890           }
3891         }
3892       }
3893     }
3894   }
3895 }
3896 #endif
3897
3898 // Load the specified registers
3899 // This only loads the registers given as arguments because
3900 // we don't want to load things that will be overwritten
3901 void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
3902 {
3903   int hr;
3904   // Load 32-bit regs
3905   for(hr=0;hr<HOST_REGS;hr++) {
3906     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
3907       if(entry[hr]!=regmap[hr]) {
3908         if(regmap[hr]==rs1||regmap[hr]==rs2)
3909         {
3910           if(regmap[hr]==0) {
3911             emit_zeroreg(hr);
3912           }
3913           else
3914           {
3915             emit_loadreg(regmap[hr],hr);
3916           }
3917         }
3918       }
3919     }
3920   }
3921   //Load 64-bit regs
3922   for(hr=0;hr<HOST_REGS;hr++) {
3923     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
3924       if(entry[hr]!=regmap[hr]) {
3925         if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
3926         {
3927           assert(regmap[hr]!=64);
3928           if((is32>>(regmap[hr]&63))&1) {
3929             int lr=get_reg(regmap,regmap[hr]-64);
3930             if(lr>=0)
3931               emit_sarimm(lr,31,hr);
3932             else
3933               emit_loadreg(regmap[hr],hr);
3934           }
3935           else
3936           {
3937             emit_loadreg(regmap[hr],hr);
3938           }
3939         }
3940       }
3941     }
3942   }
3943 }
3944
3945 // Load registers prior to the start of a loop
3946 // so that they are not loaded within the loop
3947 static void loop_preload(signed char pre[],signed char entry[])
3948 {
3949   int hr;
3950   for(hr=0;hr<HOST_REGS;hr++) {
3951     if(hr!=EXCLUDE_REG) {
3952       if(pre[hr]!=entry[hr]) {
3953         if(entry[hr]>=0) {
3954           if(get_reg(pre,entry[hr])<0) {
3955             assem_debug("loop preload:\n");
3956             //printf("loop preload: %d\n",hr);
3957             if(entry[hr]==0) {
3958               emit_zeroreg(hr);
3959             }
3960             else if(entry[hr]<TEMPREG)
3961             {
3962               emit_loadreg(entry[hr],hr);
3963             }
3964             else if(entry[hr]-64<TEMPREG)
3965             {
3966               emit_loadreg(entry[hr],hr);
3967             }
3968           }
3969         }
3970       }
3971     }
3972   }
3973 }
3974
3975 // Generate address for load/store instruction
3976 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
3977 void address_generation(int i,struct regstat *i_regs,signed char entry[])
3978 {
3979   if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
3980     int ra;
3981     int agr=AGEN1+(i&1);
3982     int mgr=MGEN1+(i&1);
3983     if(itype[i]==LOAD) {
3984       ra=get_reg(i_regs->regmap,rt1[i]);
3985       //if(rt1[i]) assert(ra>=0);
3986     }
3987     if(itype[i]==LOADLR) {
3988       ra=get_reg(i_regs->regmap,FTEMP);
3989     }
3990     if(itype[i]==STORE||itype[i]==STORELR) {
3991       ra=get_reg(i_regs->regmap,agr);
3992       if(ra<0) ra=get_reg(i_regs->regmap,-1);
3993     }
3994     if(itype[i]==C1LS||itype[i]==C2LS) {
3995       if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
3996         ra=get_reg(i_regs->regmap,FTEMP);
3997       else { // SWC1/SDC1/SWC2/SDC2
3998         ra=get_reg(i_regs->regmap,agr);
3999         if(ra<0) ra=get_reg(i_regs->regmap,-1);
4000       }
4001     }
4002     int rs=get_reg(i_regs->regmap,rs1[i]);
4003     int rm=get_reg(i_regs->regmap,TLREG);
4004     if(ra>=0) {
4005       int offset=imm[i];
4006       int c=(i_regs->wasconst>>rs)&1;
4007       if(rs1[i]==0) {
4008         // Using r0 as a base address
4009         /*if(rm>=0) {
4010           if(!entry||entry[rm]!=mgr) {
4011             generate_map_const(offset,rm);
4012           } // else did it in the previous cycle
4013         }*/
4014         if(!entry||entry[ra]!=agr) {
4015           if (opcode[i]==0x22||opcode[i]==0x26) {
4016             emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4017           }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4018             emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4019           }else{
4020             emit_movimm(offset,ra);
4021           }
4022         } // else did it in the previous cycle
4023       }
4024       else if(rs<0) {
4025         if(!entry||entry[ra]!=rs1[i])
4026           emit_loadreg(rs1[i],ra);
4027         //if(!entry||entry[ra]!=rs1[i])
4028         //  printf("poor load scheduling!\n");
4029       }
4030       else if(c) {
4031         if(rm>=0) {
4032           if(!entry||entry[rm]!=mgr) {
4033             if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
4034               // Stores to memory go thru the mapper to detect self-modifying
4035               // code, loads don't.
4036               if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
4037                  (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
4038                 generate_map_const(constmap[i][rs]+offset,rm);
4039             }else{
4040               if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
4041                 generate_map_const(constmap[i][rs]+offset,rm);
4042             }
4043           }
4044         }
4045         if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
4046           if(!entry||entry[ra]!=agr) {
4047             if (opcode[i]==0x22||opcode[i]==0x26) {
4048               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4049             }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4050               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4051             }else{
4052               #ifdef HOST_IMM_ADDR32
4053               if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4054                  (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4055               #endif
4056               emit_movimm(constmap[i][rs]+offset,ra);
4057             }
4058           } // else did it in the previous cycle
4059         } // else load_consts already did it
4060       }
4061       if(offset&&!c&&rs1[i]) {
4062         if(rs>=0) {
4063           emit_addimm(rs,offset,ra);
4064         }else{
4065           emit_addimm(ra,offset,ra);
4066         }
4067       }
4068     }
4069   }
4070   // Preload constants for next instruction
4071   if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
4072     int agr,ra;
4073     #ifndef HOST_IMM_ADDR32
4074     // Mapper entry
4075     agr=MGEN1+((i+1)&1);
4076     ra=get_reg(i_regs->regmap,agr);
4077     if(ra>=0) {
4078       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4079       int offset=imm[i+1];
4080       int c=(regs[i+1].wasconst>>rs)&1;
4081       if(c) {
4082         if(itype[i+1]==STORE||itype[i+1]==STORELR
4083            ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
4084           // Stores to memory go thru the mapper to detect self-modifying
4085           // code, loads don't.
4086           if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4087              (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
4088             generate_map_const(constmap[i+1][rs]+offset,ra);
4089         }else{
4090           if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4091             generate_map_const(constmap[i+1][rs]+offset,ra);
4092         }
4093       }
4094       /*else if(rs1[i]==0) {
4095         generate_map_const(offset,ra);
4096       }*/
4097     }
4098     #endif
4099     // Actual address
4100     agr=AGEN1+((i+1)&1);
4101     ra=get_reg(i_regs->regmap,agr);
4102     if(ra>=0) {
4103       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4104       int offset=imm[i+1];
4105       int c=(regs[i+1].wasconst>>rs)&1;
4106       if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4107         if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4108           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4109         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4110           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4111         }else{
4112           #ifdef HOST_IMM_ADDR32
4113           if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4114              (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4115           #endif
4116           emit_movimm(constmap[i+1][rs]+offset,ra);
4117         }
4118       }
4119       else if(rs1[i+1]==0) {
4120         // Using r0 as a base address
4121         if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4122           emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4123         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4124           emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4125         }else{
4126           emit_movimm(offset,ra);
4127         }
4128       }
4129     }
4130   }
4131 }
4132
4133 int get_final_value(int hr, int i, int *value)
4134 {
4135   int reg=regs[i].regmap[hr];
4136   while(i<slen-1) {
4137     if(regs[i+1].regmap[hr]!=reg) break;
4138     if(!((regs[i+1].isconst>>hr)&1)) break;
4139     if(bt[i+1]) break;
4140     i++;
4141   }
4142   if(i<slen-1) {
4143     if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4144       *value=constmap[i][hr];
4145       return 1;
4146     }
4147     if(!bt[i+1]) {
4148       if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4149         // Load in delay slot, out-of-order execution
4150         if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4151         {
4152           #ifdef HOST_IMM_ADDR32
4153           if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4154           #endif
4155           // Precompute load address
4156           *value=constmap[i][hr]+imm[i+2];
4157           return 1;
4158         }
4159       }
4160       if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4161       {
4162         #ifdef HOST_IMM_ADDR32
4163         if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4164         #endif
4165         // Precompute load address
4166         *value=constmap[i][hr]+imm[i+1];
4167         //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4168         return 1;
4169       }
4170     }
4171   }
4172   *value=constmap[i][hr];
4173   //printf("c=%x\n",(int)constmap[i][hr]);
4174   if(i==slen-1) return 1;
4175   if(reg<64) {
4176     return !((unneeded_reg[i+1]>>reg)&1);
4177   }else{
4178     return !((unneeded_reg_upper[i+1]>>reg)&1);
4179   }
4180 }
4181
4182 // Load registers with known constants
4183 void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4184 {
4185   int hr;
4186   // Load 32-bit regs
4187   for(hr=0;hr<HOST_REGS;hr++) {
4188     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4189       //if(entry[hr]!=regmap[hr]) {
4190       if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4191         if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4192           int value;
4193           if(get_final_value(hr,i,&value)) {
4194             if(value==0) {
4195               emit_zeroreg(hr);
4196             }
4197             else {
4198               emit_movimm(value,hr);
4199             }
4200           }
4201         }
4202       }
4203     }
4204   }
4205   // Load 64-bit regs
4206   for(hr=0;hr<HOST_REGS;hr++) {
4207     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4208       //if(entry[hr]!=regmap[hr]) {
4209       if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4210         if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4211           if((is32>>(regmap[hr]&63))&1) {
4212             int lr=get_reg(regmap,regmap[hr]-64);
4213             assert(lr>=0);
4214             emit_sarimm(lr,31,hr);
4215           }
4216           else
4217           {
4218             int value;
4219             if(get_final_value(hr,i,&value)) {
4220               if(value==0) {
4221                 emit_zeroreg(hr);
4222               }
4223               else {
4224                 emit_movimm(value,hr);
4225               }
4226             }
4227           }
4228         }
4229       }
4230     }
4231   }
4232 }
4233 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4234 {
4235   int hr;
4236   // Load 32-bit regs
4237   for(hr=0;hr<HOST_REGS;hr++) {
4238     if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4239       if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4240         int value=constmap[i][hr];
4241         if(value==0) {
4242           emit_zeroreg(hr);
4243         }
4244         else {
4245           emit_movimm(value,hr);
4246         }
4247       }
4248     }
4249   }
4250   // Load 64-bit regs
4251   for(hr=0;hr<HOST_REGS;hr++) {
4252     if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4253       if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4254         if((is32>>(regmap[hr]&63))&1) {
4255           int lr=get_reg(regmap,regmap[hr]-64);
4256           assert(lr>=0);
4257           emit_sarimm(lr,31,hr);
4258         }
4259         else
4260         {
4261           int value=constmap[i][hr];
4262           if(value==0) {
4263             emit_zeroreg(hr);
4264           }
4265           else {
4266             emit_movimm(value,hr);
4267           }
4268         }
4269       }
4270     }
4271   }
4272 }
4273
4274 // Write out all dirty registers (except cycle count)
4275 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4276 {
4277   int hr;
4278   for(hr=0;hr<HOST_REGS;hr++) {
4279     if(hr!=EXCLUDE_REG) {
4280       if(i_regmap[hr]>0) {
4281         if(i_regmap[hr]!=CCREG) {
4282           if((i_dirty>>hr)&1) {
4283             if(i_regmap[hr]<64) {
4284               emit_storereg(i_regmap[hr],hr);
4285 #ifndef FORCE32
4286               if( ((i_is32>>i_regmap[hr])&1) ) {
4287                 #ifdef DESTRUCTIVE_WRITEBACK
4288                 emit_sarimm(hr,31,hr);
4289                 emit_storereg(i_regmap[hr]|64,hr);
4290                 #else
4291                 emit_sarimm(hr,31,HOST_TEMPREG);
4292                 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4293                 #endif
4294               }
4295 #endif
4296             }else{
4297               if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4298                 emit_storereg(i_regmap[hr],hr);
4299               }
4300             }
4301           }
4302         }
4303       }
4304     }
4305   }
4306 }
4307 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4308 // This writes the registers not written by store_regs_bt
4309 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4310 {
4311   int hr;
4312   int t=(addr-start)>>2;
4313   for(hr=0;hr<HOST_REGS;hr++) {
4314     if(hr!=EXCLUDE_REG) {
4315       if(i_regmap[hr]>0) {
4316         if(i_regmap[hr]!=CCREG) {
4317           if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4318             if((i_dirty>>hr)&1) {
4319               if(i_regmap[hr]<64) {
4320                 emit_storereg(i_regmap[hr],hr);
4321 #ifndef FORCE32
4322                 if( ((i_is32>>i_regmap[hr])&1) ) {
4323                   #ifdef DESTRUCTIVE_WRITEBACK
4324                   emit_sarimm(hr,31,hr);
4325                   emit_storereg(i_regmap[hr]|64,hr);
4326                   #else
4327                   emit_sarimm(hr,31,HOST_TEMPREG);
4328                   emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4329                   #endif
4330                 }
4331 #endif
4332               }else{
4333                 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4334                   emit_storereg(i_regmap[hr],hr);
4335                 }
4336               }
4337             }
4338           }
4339         }
4340       }
4341     }
4342   }
4343 }
4344
4345 // Load all registers (except cycle count)
4346 void load_all_regs(signed char i_regmap[])
4347 {
4348   int hr;
4349   for(hr=0;hr<HOST_REGS;hr++) {
4350     if(hr!=EXCLUDE_REG) {
4351       if(i_regmap[hr]==0) {
4352         emit_zeroreg(hr);
4353       }
4354       else
4355       if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG)
4356       {
4357         emit_loadreg(i_regmap[hr],hr);
4358       }
4359     }
4360   }
4361 }
4362
4363 // Load all current registers also needed by next instruction
4364 void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4365 {
4366   int hr;
4367   for(hr=0;hr<HOST_REGS;hr++) {
4368     if(hr!=EXCLUDE_REG) {
4369       if(get_reg(next_regmap,i_regmap[hr])>=0) {
4370         if(i_regmap[hr]==0) {
4371           emit_zeroreg(hr);
4372         }
4373         else
4374         if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG)
4375         {
4376           emit_loadreg(i_regmap[hr],hr);
4377         }
4378       }
4379     }
4380   }
4381 }
4382
4383 // Load all regs, storing cycle count if necessary
4384 void load_regs_entry(int t)
4385 {
4386   int hr;
4387   if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER,HOST_CCREG);
4388   else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t]*CLOCK_DIVIDER,HOST_CCREG);
4389   if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4390     emit_storereg(CCREG,HOST_CCREG);
4391   }
4392   // Load 32-bit regs
4393   for(hr=0;hr<HOST_REGS;hr++) {
4394     if(regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<64) {
4395       if(regs[t].regmap_entry[hr]==0) {
4396         emit_zeroreg(hr);
4397       }
4398       else if(regs[t].regmap_entry[hr]!=CCREG)
4399       {
4400         emit_loadreg(regs[t].regmap_entry[hr],hr);
4401       }
4402     }
4403   }
4404   // Load 64-bit regs
4405   for(hr=0;hr<HOST_REGS;hr++) {
4406     if(regs[t].regmap_entry[hr]>=64) {
4407       assert(regs[t].regmap_entry[hr]!=64);
4408       if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4409         int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4410         if(lr<0) {
4411           emit_loadreg(regs[t].regmap_entry[hr],hr);
4412         }
4413         else
4414         {
4415           emit_sarimm(lr,31,hr);
4416         }
4417       }
4418       else
4419       {
4420         emit_loadreg(regs[t].regmap_entry[hr],hr);
4421       }
4422     }
4423   }
4424 }
4425
4426 // Store dirty registers prior to branch
4427 void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4428 {
4429   if(internal_branch(i_is32,addr))
4430   {
4431     int t=(addr-start)>>2;
4432     int hr;
4433     for(hr=0;hr<HOST_REGS;hr++) {
4434       if(hr!=EXCLUDE_REG) {
4435         if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4436           if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4437             if((i_dirty>>hr)&1) {
4438               if(i_regmap[hr]<64) {
4439                 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4440                   emit_storereg(i_regmap[hr],hr);
4441                   if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4442                     #ifdef DESTRUCTIVE_WRITEBACK
4443                     emit_sarimm(hr,31,hr);
4444                     emit_storereg(i_regmap[hr]|64,hr);
4445                     #else
4446                     emit_sarimm(hr,31,HOST_TEMPREG);
4447                     emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4448                     #endif
4449                   }
4450                 }
4451               }else{
4452                 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4453                   emit_storereg(i_regmap[hr],hr);
4454                 }
4455               }
4456             }
4457           }
4458         }
4459       }
4460     }
4461   }
4462   else
4463   {
4464     // Branch out of this block, write out all dirty regs
4465     wb_dirtys(i_regmap,i_is32,i_dirty);
4466   }
4467 }
4468
4469 // Load all needed registers for branch target
4470 void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4471 {
4472   //if(addr>=start && addr<(start+slen*4))
4473   if(internal_branch(i_is32,addr))
4474   {
4475     int t=(addr-start)>>2;
4476     int hr;
4477     // Store the cycle count before loading something else
4478     if(i_regmap[HOST_CCREG]!=CCREG) {
4479       assert(i_regmap[HOST_CCREG]==-1);
4480     }
4481     if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4482       emit_storereg(CCREG,HOST_CCREG);
4483     }
4484     // Load 32-bit regs
4485     for(hr=0;hr<HOST_REGS;hr++) {
4486       if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<64) {
4487         #ifdef DESTRUCTIVE_WRITEBACK
4488         if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4489         #else
4490         if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4491         #endif
4492           if(regs[t].regmap_entry[hr]==0) {
4493             emit_zeroreg(hr);
4494           }
4495           else if(regs[t].regmap_entry[hr]!=CCREG)
4496           {
4497             emit_loadreg(regs[t].regmap_entry[hr],hr);
4498           }
4499         }
4500       }
4501     }
4502     //Load 64-bit regs
4503     for(hr=0;hr<HOST_REGS;hr++) {
4504       if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=64) {
4505         if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4506           assert(regs[t].regmap_entry[hr]!=64);
4507           if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4508             int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4509             if(lr<0) {
4510               emit_loadreg(regs[t].regmap_entry[hr],hr);
4511             }
4512             else
4513             {
4514               emit_sarimm(lr,31,hr);
4515             }
4516           }
4517           else
4518           {
4519             emit_loadreg(regs[t].regmap_entry[hr],hr);
4520           }
4521         }
4522         else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4523           int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4524           assert(lr>=0);
4525           emit_sarimm(lr,31,hr);
4526         }
4527       }
4528     }
4529   }
4530 }
4531
4532 int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4533 {
4534   if(addr>=start && addr<start+slen*4-4)
4535   {
4536     int t=(addr-start)>>2;
4537     int hr;
4538     if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4539     for(hr=0;hr<HOST_REGS;hr++)
4540     {
4541       if(hr!=EXCLUDE_REG)
4542       {
4543         if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4544         {
4545           if(regs[t].regmap_entry[hr]!=-1)
4546           {
4547             return 0;
4548           }
4549           else
4550           if((i_dirty>>hr)&1)
4551           {
4552             if(i_regmap[hr]<64)
4553             {
4554               if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4555                 return 0;
4556             }
4557             else
4558             {
4559               if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4560                 return 0;
4561             }
4562           }
4563         }
4564         else // Same register but is it 32-bit or dirty?
4565         if(i_regmap[hr]>=0)
4566         {
4567           if(!((regs[t].dirty>>hr)&1))
4568           {
4569             if((i_dirty>>hr)&1)
4570             {
4571               if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4572               {
4573                 //printf("%x: dirty no match\n",addr);
4574                 return 0;
4575               }
4576             }
4577           }
4578           if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4579           {
4580             //printf("%x: is32 no match\n",addr);
4581             return 0;
4582           }
4583         }
4584       }
4585     }
4586     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4587 #ifndef FORCE32
4588     if(requires_32bit[t]&~i_is32) return 0;
4589 #endif
4590     // Delay slots are not valid branch targets
4591     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4592     // Delay slots require additional processing, so do not match
4593     if(is_ds[t]) return 0;
4594   }
4595   else
4596   {
4597     int hr;
4598     for(hr=0;hr<HOST_REGS;hr++)
4599     {
4600       if(hr!=EXCLUDE_REG)
4601       {
4602         if(i_regmap[hr]>=0)
4603         {
4604           if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4605           {
4606             if((i_dirty>>hr)&1)
4607             {
4608               return 0;
4609             }
4610           }
4611         }
4612       }
4613     }
4614   }
4615   return 1;
4616 }
4617
4618 // Used when a branch jumps into the delay slot of another branch
4619 void ds_assemble_entry(int i)
4620 {
4621   int t=(ba[i]-start)>>2;
4622   if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4623   assem_debug("Assemble delay slot at %x\n",ba[i]);
4624   assem_debug("<->\n");
4625   if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
4626     wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4627   load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4628   address_generation(t,&regs[t],regs[t].regmap_entry);
4629   if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
4630     load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4631   cop1_usable=0;
4632   is_delayslot=0;
4633   switch(itype[t]) {
4634     case ALU:
4635       alu_assemble(t,&regs[t]);break;
4636     case IMM16:
4637       imm16_assemble(t,&regs[t]);break;
4638     case SHIFT:
4639       shift_assemble(t,&regs[t]);break;
4640     case SHIFTIMM:
4641       shiftimm_assemble(t,&regs[t]);break;
4642     case LOAD:
4643       load_assemble(t,&regs[t]);break;
4644     case LOADLR:
4645       loadlr_assemble(t,&regs[t]);break;
4646     case STORE:
4647       store_assemble(t,&regs[t]);break;
4648     case STORELR:
4649       storelr_assemble(t,&regs[t]);break;
4650     case COP0:
4651       cop0_assemble(t,&regs[t]);break;
4652     case COP1:
4653       cop1_assemble(t,&regs[t]);break;
4654     case C1LS:
4655       c1ls_assemble(t,&regs[t]);break;
4656     case COP2:
4657       cop2_assemble(t,&regs[t]);break;
4658     case C2LS:
4659       c2ls_assemble(t,&regs[t]);break;
4660     case C2OP:
4661       c2op_assemble(t,&regs[t]);break;
4662     case FCONV:
4663       fconv_assemble(t,&regs[t]);break;
4664     case FLOAT:
4665       float_assemble(t,&regs[t]);break;
4666     case FCOMP:
4667       fcomp_assemble(t,&regs[t]);break;
4668     case MULTDIV:
4669       multdiv_assemble(t,&regs[t]);break;
4670     case MOV:
4671       mov_assemble(t,&regs[t]);break;
4672     case SYSCALL:
4673     case HLECALL:
4674     case INTCALL:
4675     case SPAN:
4676     case UJUMP:
4677     case RJUMP:
4678     case CJUMP:
4679     case SJUMP:
4680     case FJUMP:
4681       printf("Jump in the delay slot.  This is probably a bug.\n");
4682   }
4683   store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4684   load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4685   if(internal_branch(regs[t].is32,ba[i]+4))
4686     assem_debug("branch: internal\n");
4687   else
4688     assem_debug("branch: external\n");
4689   assert(internal_branch(regs[t].is32,ba[i]+4));
4690   add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4691   emit_jmp(0);
4692 }
4693
4694 void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4695 {
4696   int count;
4697   int jaddr;
4698   int idle=0;
4699   if(itype[i]==RJUMP)
4700   {
4701     *adj=0;
4702   }
4703   //if(ba[i]>=start && ba[i]<(start+slen*4))
4704   if(internal_branch(branch_regs[i].is32,ba[i]))
4705   {
4706     int t=(ba[i]-start)>>2;
4707     if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4708     else *adj=ccadj[t];
4709   }
4710   else
4711   {
4712     *adj=0;
4713   }
4714   count=ccadj[i];
4715   if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4716     // Idle loop
4717     if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4718     idle=(int)out;
4719     //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4720     emit_andimm(HOST_CCREG,3,HOST_CCREG);
4721     jaddr=(int)out;
4722     emit_jmp(0);
4723   }
4724   else if(*adj==0||invert) {
4725     emit_addimm_and_set_flags(CLOCK_DIVIDER*(count+2),HOST_CCREG);
4726     jaddr=(int)out;
4727     emit_jns(0);
4728   }
4729   else
4730   {
4731     emit_cmpimm(HOST_CCREG,-2*(count+2));
4732     jaddr=(int)out;
4733     emit_jns(0);
4734   }
4735   add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4736 }
4737
4738 void do_ccstub(int n)
4739 {
4740   literal_pool(256);
4741   assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
4742   set_jump_target(stubs[n][1],(int)out);
4743   int i=stubs[n][4];
4744   if(stubs[n][6]==NULLDS) {
4745     // Delay slot instruction is nullified ("likely" branch)
4746     wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4747   }
4748   else if(stubs[n][6]!=TAKEN) {
4749     wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4750   }
4751   else {
4752     if(internal_branch(branch_regs[i].is32,ba[i]))
4753       wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4754   }
4755   if(stubs[n][5]!=-1)
4756   {
4757     // Save PC as return address
4758     emit_movimm(stubs[n][5],EAX);
4759     emit_writeword(EAX,(int)&pcaddr);
4760   }
4761   else
4762   {
4763     // Return address depends on which way the branch goes
4764     if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
4765     {
4766       int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4767       int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4768       int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4769       int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4770       if(rs1[i]==0)
4771       {
4772         s1l=s2l;s1h=s2h;
4773         s2l=s2h=-1;
4774       }
4775       else if(rs2[i]==0)
4776       {
4777         s2l=s2h=-1;
4778       }
4779       if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
4780         s1h=s2h=-1;
4781       }
4782       assert(s1l>=0);
4783       #ifdef DESTRUCTIVE_WRITEBACK
4784       if(rs1[i]) {
4785         if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
4786           emit_loadreg(rs1[i],s1l);
4787       }
4788       else {
4789         if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
4790           emit_loadreg(rs2[i],s1l);
4791       }
4792       if(s2l>=0)
4793         if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
4794           emit_loadreg(rs2[i],s2l);
4795       #endif
4796       int hr=0;
4797       int addr,alt,ntaddr;
4798       while(hr<HOST_REGS)
4799       {
4800         if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4801            (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4802            (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4803         {
4804           addr=hr++;break;
4805         }
4806         hr++;
4807       }
4808       while(hr<HOST_REGS)
4809       {
4810         if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4811            (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4812            (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4813         {
4814           alt=hr++;break;
4815         }
4816         hr++;
4817       }
4818       if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
4819       {
4820         while(hr<HOST_REGS)
4821         {
4822           if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4823              (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4824              (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4825           {
4826             ntaddr=hr;break;
4827           }
4828           hr++;
4829         }
4830         assert(hr<HOST_REGS);
4831       }
4832       if((opcode[i]&0x2f)==4) // BEQ
4833       {
4834         #ifdef HAVE_CMOV_IMM
4835         if(s1h<0) {
4836           if(s2l>=0) emit_cmp(s1l,s2l);
4837           else emit_test(s1l,s1l);
4838           emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
4839         }
4840         else
4841         #endif
4842         {
4843           emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4844           if(s1h>=0) {
4845             if(s2h>=0) emit_cmp(s1h,s2h);
4846             else emit_test(s1h,s1h);
4847             emit_cmovne_reg(alt,addr);
4848           }
4849           if(s2l>=0) emit_cmp(s1l,s2l);
4850           else emit_test(s1l,s1l);
4851           emit_cmovne_reg(alt,addr);
4852         }
4853       }
4854       if((opcode[i]&0x2f)==5) // BNE
4855       {
4856         #ifdef HAVE_CMOV_IMM
4857         if(s1h<0) {
4858           if(s2l>=0) emit_cmp(s1l,s2l);
4859           else emit_test(s1l,s1l);
4860           emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
4861         }
4862         else
4863         #endif
4864         {
4865           emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
4866           if(s1h>=0) {
4867             if(s2h>=0) emit_cmp(s1h,s2h);
4868             else emit_test(s1h,s1h);
4869             emit_cmovne_reg(alt,addr);
4870           }
4871           if(s2l>=0) emit_cmp(s1l,s2l);
4872           else emit_test(s1l,s1l);
4873           emit_cmovne_reg(alt,addr);
4874         }
4875       }
4876       if((opcode[i]&0x2f)==6) // BLEZ
4877       {
4878         //emit_movimm(ba[i],alt);
4879         //emit_movimm(start+i*4+8,addr);
4880         emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4881         emit_cmpimm(s1l,1);
4882         if(s1h>=0) emit_mov(addr,ntaddr);
4883         emit_cmovl_reg(alt,addr);
4884         if(s1h>=0) {
4885           emit_test(s1h,s1h);
4886           emit_cmovne_reg(ntaddr,addr);
4887           emit_cmovs_reg(alt,addr);
4888         }
4889       }
4890       if((opcode[i]&0x2f)==7) // BGTZ
4891       {
4892         //emit_movimm(ba[i],addr);
4893         //emit_movimm(start+i*4+8,ntaddr);
4894         emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
4895         emit_cmpimm(s1l,1);
4896         if(s1h>=0) emit_mov(addr,alt);
4897         emit_cmovl_reg(ntaddr,addr);
4898         if(s1h>=0) {
4899           emit_test(s1h,s1h);
4900           emit_cmovne_reg(alt,addr);
4901           emit_cmovs_reg(ntaddr,addr);
4902         }
4903       }
4904       if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
4905       {
4906         //emit_movimm(ba[i],alt);
4907         //emit_movimm(start+i*4+8,addr);
4908         emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4909         if(s1h>=0) emit_test(s1h,s1h);
4910         else emit_test(s1l,s1l);
4911         emit_cmovs_reg(alt,addr);
4912       }
4913       if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
4914       {
4915         //emit_movimm(ba[i],addr);
4916         //emit_movimm(start+i*4+8,alt);
4917         emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4918         if(s1h>=0) emit_test(s1h,s1h);
4919         else emit_test(s1l,s1l);
4920         emit_cmovs_reg(alt,addr);
4921       }
4922       if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
4923         if(source[i]&0x10000) // BC1T
4924         {
4925           //emit_movimm(ba[i],alt);
4926           //emit_movimm(start+i*4+8,addr);
4927           emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4928           emit_testimm(s1l,0x800000);
4929           emit_cmovne_reg(alt,addr);
4930         }
4931         else // BC1F
4932         {
4933           //emit_movimm(ba[i],addr);
4934           //emit_movimm(start+i*4+8,alt);
4935           emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4936           emit_testimm(s1l,0x800000);
4937           emit_cmovne_reg(alt,addr);
4938         }
4939       }
4940       emit_writeword(addr,(int)&pcaddr);
4941     }
4942     else
4943     if(itype[i]==RJUMP)
4944     {
4945       int r=get_reg(branch_regs[i].regmap,rs1[i]);
4946       if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
4947         r=get_reg(branch_regs[i].regmap,RTEMP);
4948       }
4949       emit_writeword(r,(int)&pcaddr);
4950     }
4951     else {printf("Unknown branch type in do_ccstub\n");exit(1);}
4952   }
4953   // Update cycle count
4954   assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
4955   if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
4956   emit_call((int)cc_interrupt);
4957   if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
4958   if(stubs[n][6]==TAKEN) {
4959     if(internal_branch(branch_regs[i].is32,ba[i]))
4960       load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
4961     else if(itype[i]==RJUMP) {
4962       if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
4963         emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
4964       else
4965         emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
4966     }
4967   }else if(stubs[n][6]==NOTTAKEN) {
4968     if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
4969     else load_all_regs(branch_regs[i].regmap);
4970   }else if(stubs[n][6]==NULLDS) {
4971     // Delay slot instruction is nullified ("likely" branch)
4972     if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
4973     else load_all_regs(regs[i].regmap);
4974   }else{
4975     load_all_regs(branch_regs[i].regmap);
4976   }
4977   emit_jmp(stubs[n][2]); // return address
4978
4979   /* This works but uses a lot of memory...
4980   emit_readword((int)&last_count,ECX);
4981   emit_add(HOST_CCREG,ECX,EAX);
4982   emit_writeword(EAX,(int)&Count);
4983   emit_call((int)gen_interupt);
4984   emit_readword((int)&Count,HOST_CCREG);
4985   emit_readword((int)&next_interupt,EAX);
4986   emit_readword((int)&pending_exception,EBX);
4987   emit_writeword(EAX,(int)&last_count);
4988   emit_sub(HOST_CCREG,EAX,HOST_CCREG);
4989   emit_test(EBX,EBX);
4990   int jne_instr=(int)out;
4991   emit_jne(0);
4992   if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
4993   load_all_regs(branch_regs[i].regmap);
4994   emit_jmp(stubs[n][2]); // return address
4995   set_jump_target(jne_instr,(int)out);
4996   emit_readword((int)&pcaddr,EAX);
4997   // Call get_addr_ht instead of doing the hash table here.
4998   // This code is executed infrequently and takes up a lot of space
4999   // so smaller is better.
5000   emit_storereg(CCREG,HOST_CCREG);
5001   emit_pushreg(EAX);
5002   emit_call((int)get_addr_ht);
5003   emit_loadreg(CCREG,HOST_CCREG);
5004   emit_addimm(ESP,4,ESP);
5005   emit_jmpreg(EAX);*/
5006 }
5007
5008 add_to_linker(int addr,int target,int ext)
5009 {
5010   link_addr[linkcount][0]=addr;
5011   link_addr[linkcount][1]=target;
5012   link_addr[linkcount][2]=ext;
5013   linkcount++;
5014 }
5015
5016 void ujump_assemble(int i,struct regstat *i_regs)
5017 {
5018   signed char *i_regmap=i_regs->regmap;
5019   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5020   address_generation(i+1,i_regs,regs[i].regmap_entry);
5021   #ifdef REG_PREFETCH
5022   int temp=get_reg(branch_regs[i].regmap,PTEMP);
5023   if(rt1[i]==31&&temp>=0)
5024   {
5025     int return_address=start+i*4+8;
5026     if(get_reg(branch_regs[i].regmap,31)>0)
5027     if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5028   }
5029   #endif
5030   ds_assemble(i+1,i_regs);
5031   uint64_t bc_unneeded=branch_regs[i].u;
5032   uint64_t bc_unneeded_upper=branch_regs[i].uu;
5033   bc_unneeded|=1|(1LL<<rt1[i]);
5034   bc_unneeded_upper|=1|(1LL<<rt1[i]);
5035   wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5036                 bc_unneeded,bc_unneeded_upper);
5037   load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5038   if(rt1[i]==31) {
5039     int rt;
5040     unsigned int return_address;
5041     assert(rt1[i+1]!=31);
5042     assert(rt2[i+1]!=31);
5043     rt=get_reg(branch_regs[i].regmap,31);
5044     assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5045     //assert(rt>=0);
5046     return_address=start+i*4+8;
5047     if(rt>=0) {
5048       #ifdef USE_MINI_HT
5049       if(internal_branch(branch_regs[i].is32,return_address)) {
5050         int temp=rt+1;
5051         if(temp==EXCLUDE_REG||temp>=HOST_REGS||
5052            branch_regs[i].regmap[temp]>=0)
5053         {
5054           temp=get_reg(branch_regs[i].regmap,-1);
5055         }
5056         #ifdef HOST_TEMPREG
5057         if(temp<0) temp=HOST_TEMPREG;
5058         #endif
5059         if(temp>=0) do_miniht_insert(return_address,rt,temp);
5060         else emit_movimm(return_address,rt);
5061       }
5062       else
5063       #endif
5064       {
5065         #ifdef REG_PREFETCH
5066         if(temp>=0)
5067         {
5068           if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5069         }
5070         #endif
5071         emit_movimm(return_address,rt); // PC into link register
5072         #ifdef IMM_PREFETCH
5073         emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5074         #endif
5075       }
5076     }
5077   }
5078   int cc,adj;
5079   cc=get_reg(branch_regs[i].regmap,CCREG);
5080   assert(cc==HOST_CCREG);
5081   store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5082   #ifdef REG_PREFETCH
5083   if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5084   #endif
5085   do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5086   if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5087   load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5088   if(internal_branch(branch_regs[i].is32,ba[i]))
5089     assem_debug("branch: internal\n");
5090   else
5091     assem_debug("branch: external\n");
5092   if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5093     ds_assemble_entry(i);
5094   }
5095   else {
5096     add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5097     emit_jmp(0);
5098   }
5099 }
5100
5101 void rjump_assemble(int i,struct regstat *i_regs)
5102 {
5103   signed char *i_regmap=i_regs->regmap;
5104   int temp;
5105   int rs,cc,adj;
5106   rs=get_reg(branch_regs[i].regmap,rs1[i]);
5107   assert(rs>=0);
5108   if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5109     // Delay slot abuse, make a copy of the branch address register
5110     temp=get_reg(branch_regs[i].regmap,RTEMP);
5111     assert(temp>=0);
5112     assert(regs[i].regmap[temp]==RTEMP);
5113     emit_mov(rs,temp);
5114     rs=temp;
5115   }
5116   address_generation(i+1,i_regs,regs[i].regmap_entry);
5117   #ifdef REG_PREFETCH
5118   if(rt1[i]==31)
5119   {
5120     if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5121       int return_address=start+i*4+8;
5122       if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5123     }
5124   }
5125   #endif
5126   #ifdef USE_MINI_HT
5127   if(rs1[i]==31) {
5128     int rh=get_reg(regs[i].regmap,RHASH);
5129     if(rh>=0) do_preload_rhash(rh);
5130   }
5131   #endif
5132   ds_assemble(i+1,i_regs);
5133   uint64_t bc_unneeded=branch_regs[i].u;
5134   uint64_t bc_unneeded_upper=branch_regs[i].uu;
5135   bc_unneeded|=1|(1LL<<rt1[i]);
5136   bc_unneeded_upper|=1|(1LL<<rt1[i]);
5137   bc_unneeded&=~(1LL<<rs1[i]);
5138   wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5139                 bc_unneeded,bc_unneeded_upper);
5140   load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5141   if(rt1[i]!=0) {
5142     int rt,return_address;
5143     assert(rt1[i+1]!=rt1[i]);
5144     assert(rt2[i+1]!=rt1[i]);
5145     rt=get_reg(branch_regs[i].regmap,rt1[i]);
5146     assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5147     assert(rt>=0);
5148     return_address=start+i*4+8;
5149     #ifdef REG_PREFETCH
5150     if(temp>=0)
5151     {
5152       if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5153     }
5154     #endif
5155     emit_movimm(return_address,rt); // PC into link register
5156     #ifdef IMM_PREFETCH
5157     emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5158     #endif
5159   }
5160   cc=get_reg(branch_regs[i].regmap,CCREG);
5161   assert(cc==HOST_CCREG);
5162   #ifdef USE_MINI_HT
5163   int rh=get_reg(branch_regs[i].regmap,RHASH);
5164   int ht=get_reg(branch_regs[i].regmap,RHTBL);
5165   if(rs1[i]==31) {
5166     if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5167     do_preload_rhtbl(ht);
5168     do_rhash(rs,rh);
5169   }
5170   #endif
5171   store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5172   #ifdef DESTRUCTIVE_WRITEBACK
5173   if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5174     if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5175       emit_loadreg(rs1[i],rs);
5176     }
5177   }
5178   #endif
5179   #ifdef REG_PREFETCH
5180   if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5181   #endif
5182   #ifdef USE_MINI_HT
5183   if(rs1[i]==31) {
5184     do_miniht_load(ht,rh);
5185   }
5186   #endif
5187   //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5188   //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5189   //assert(adj==0);
5190   emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5191   add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5192   emit_jns(0);
5193   //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5194   #ifdef USE_MINI_HT
5195   if(rs1[i]==31) {
5196     do_miniht_jump(rs,rh,ht);
5197   }
5198   else
5199   #endif
5200   {
5201     //if(rs!=EAX) emit_mov(rs,EAX);
5202     //emit_jmp((int)jump_vaddr_eax);
5203     emit_jmp(jump_vaddr_reg[rs]);
5204   }
5205   /* Check hash table
5206   temp=!rs;
5207   emit_mov(rs,temp);
5208   emit_shrimm(rs,16,rs);
5209   emit_xor(temp,rs,rs);
5210   emit_movzwl_reg(rs,rs);
5211   emit_shlimm(rs,4,rs);
5212   emit_cmpmem_indexed((int)hash_table,rs,temp);
5213   emit_jne((int)out+14);
5214   emit_readword_indexed((int)hash_table+4,rs,rs);
5215   emit_jmpreg(rs);
5216   emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5217   emit_addimm_no_flags(8,rs);
5218   emit_jeq((int)out-17);
5219   // No hit on hash table, call compiler
5220   emit_pushreg(temp);
5221 //DEBUG >
5222 #ifdef DEBUG_CYCLE_COUNT
5223   emit_readword((int)&last_count,ECX);
5224   emit_add(HOST_CCREG,ECX,HOST_CCREG);
5225   emit_readword((int)&next_interupt,ECX);
5226   emit_writeword(HOST_CCREG,(int)&Count);
5227   emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5228   emit_writeword(ECX,(int)&last_count);
5229 #endif
5230 //DEBUG <
5231   emit_storereg(CCREG,HOST_CCREG);
5232   emit_call((int)get_addr);
5233   emit_loadreg(CCREG,HOST_CCREG);
5234   emit_addimm(ESP,4,ESP);
5235   emit_jmpreg(EAX);*/
5236   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5237   if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5238   #endif
5239 }
5240
5241 void cjump_assemble(int i,struct regstat *i_regs)
5242 {
5243   signed char *i_regmap=i_regs->regmap;
5244   int cc;
5245   int match;
5246   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5247   assem_debug("match=%d\n",match);
5248   int s1h,s1l,s2h,s2l;
5249   int prev_cop1_usable=cop1_usable;
5250   int unconditional=0,nop=0;
5251   int only32=0;
5252   int ooo=1;
5253   int invert=0;
5254   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5255   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5256   if(likely[i]) ooo=0;
5257   if(!match) invert=1;
5258   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5259   if(i>(ba[i]-start)>>2) invert=1;
5260   #endif
5261
5262   if(ooo)
5263     if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
5264        (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1])))
5265   {
5266     // Write-after-read dependency prevents out of order execution
5267     // First test branch condition, then execute delay slot, then branch
5268     ooo=0;
5269   }
5270
5271   if(ooo) {
5272     s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5273     s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5274     s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5275     s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5276   }
5277   else {
5278     s1l=get_reg(i_regmap,rs1[i]);
5279     s1h=get_reg(i_regmap,rs1[i]|64);
5280     s2l=get_reg(i_regmap,rs2[i]);
5281     s2h=get_reg(i_regmap,rs2[i]|64);
5282   }
5283   if(rs1[i]==0&&rs2[i]==0)
5284   {
5285     if(opcode[i]&1) nop=1;
5286     else unconditional=1;
5287     //assert(opcode[i]!=5);
5288     //assert(opcode[i]!=7);
5289     //assert(opcode[i]!=0x15);
5290     //assert(opcode[i]!=0x17);
5291   }
5292   else if(rs1[i]==0)
5293   {
5294     s1l=s2l;s1h=s2h;
5295     s2l=s2h=-1;
5296     only32=(regs[i].was32>>rs2[i])&1;
5297   }
5298   else if(rs2[i]==0)
5299   {
5300     s2l=s2h=-1;
5301     only32=(regs[i].was32>>rs1[i])&1;
5302   }
5303   else {
5304     only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5305   }
5306
5307   if(ooo) {
5308     // Out of order execution (delay slot first)
5309     //printf("OOOE\n");
5310     address_generation(i+1,i_regs,regs[i].regmap_entry);
5311     ds_assemble(i+1,i_regs);
5312     int adj;
5313     uint64_t bc_unneeded=branch_regs[i].u;
5314     uint64_t bc_unneeded_upper=branch_regs[i].uu;
5315     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5316     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5317     bc_unneeded|=1;
5318     bc_unneeded_upper|=1;
5319     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5320                   bc_unneeded,bc_unneeded_upper);
5321     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5322     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5323     cc=get_reg(branch_regs[i].regmap,CCREG);
5324     assert(cc==HOST_CCREG);
5325     if(unconditional)
5326       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5327     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5328     //assem_debug("cycle count (adj)\n");
5329     if(unconditional) {
5330       do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5331       if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5332         if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5333         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5334         if(internal)
5335           assem_debug("branch: internal\n");
5336         else
5337           assem_debug("branch: external\n");
5338         if(internal&&is_ds[(ba[i]-start)>>2]) {
5339           ds_assemble_entry(i);
5340         }
5341         else {
5342           add_to_linker((int)out,ba[i],internal);
5343           emit_jmp(0);
5344         }
5345         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5346         if(((u_int)out)&7) emit_addnop(0);
5347         #endif
5348       }
5349     }
5350     else if(nop) {
5351       emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5352       int jaddr=(int)out;
5353       emit_jns(0);
5354       add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5355     }
5356     else {
5357       int taken=0,nottaken=0,nottaken1=0;
5358       do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5359       if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5360       if(!only32)
5361       {
5362         assert(s1h>=0);
5363         if(opcode[i]==4) // BEQ
5364         {
5365           if(s2h>=0) emit_cmp(s1h,s2h);
5366           else emit_test(s1h,s1h);
5367           nottaken1=(int)out;
5368           emit_jne(1);
5369         }
5370         if(opcode[i]==5) // BNE
5371         {
5372           if(s2h>=0) emit_cmp(s1h,s2h);
5373           else emit_test(s1h,s1h);
5374           if(invert) taken=(int)out;
5375           else add_to_linker((int)out,ba[i],internal);
5376           emit_jne(0);
5377         }
5378         if(opcode[i]==6) // BLEZ
5379         {
5380           emit_test(s1h,s1h);
5381           if(invert) taken=(int)out;
5382           else add_to_linker((int)out,ba[i],internal);
5383           emit_js(0);
5384           nottaken1=(int)out;
5385           emit_jne(1);
5386         }
5387         if(opcode[i]==7) // BGTZ
5388         {
5389           emit_test(s1h,s1h);
5390           nottaken1=(int)out;
5391           emit_js(1);
5392           if(invert) taken=(int)out;
5393           else add_to_linker((int)out,ba[i],internal);
5394           emit_jne(0);
5395         }
5396       } // if(!only32)
5397
5398       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5399       assert(s1l>=0);
5400       if(opcode[i]==4) // BEQ
5401       {
5402         if(s2l>=0) emit_cmp(s1l,s2l);
5403         else emit_test(s1l,s1l);
5404         if(invert){
5405           nottaken=(int)out;
5406           emit_jne(1);
5407         }else{
5408           add_to_linker((int)out,ba[i],internal);
5409           emit_jeq(0);
5410         }
5411       }
5412       if(opcode[i]==5) // BNE
5413       {
5414         if(s2l>=0) emit_cmp(s1l,s2l);
5415         else emit_test(s1l,s1l);
5416         if(invert){
5417           nottaken=(int)out;
5418           emit_jeq(1);
5419         }else{
5420           add_to_linker((int)out,ba[i],internal);
5421           emit_jne(0);
5422         }
5423       }
5424       if(opcode[i]==6) // BLEZ
5425       {
5426         emit_cmpimm(s1l,1);
5427         if(invert){
5428           nottaken=(int)out;
5429           emit_jge(1);
5430         }else{
5431           add_to_linker((int)out,ba[i],internal);
5432           emit_jl(0);
5433         }
5434       }
5435       if(opcode[i]==7) // BGTZ
5436       {
5437         emit_cmpimm(s1l,1);
5438         if(invert){
5439           nottaken=(int)out;
5440           emit_jl(1);
5441         }else{
5442           add_to_linker((int)out,ba[i],internal);
5443           emit_jge(0);
5444         }
5445       }
5446       if(invert) {
5447         if(taken) set_jump_target(taken,(int)out);
5448         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5449         if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5450           if(adj) {
5451             emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5452             add_to_linker((int)out,ba[i],internal);
5453           }else{
5454             emit_addnop(13);
5455             add_to_linker((int)out,ba[i],internal*2);
5456           }
5457           emit_jmp(0);
5458         }else
5459         #endif
5460         {
5461           if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5462           store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5463           load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5464           if(internal)
5465             assem_debug("branch: internal\n");
5466           else
5467             assem_debug("branch: external\n");
5468           if(internal&&is_ds[(ba[i]-start)>>2]) {
5469             ds_assemble_entry(i);
5470           }
5471           else {
5472             add_to_linker((int)out,ba[i],internal);
5473             emit_jmp(0);
5474           }
5475         }
5476         set_jump_target(nottaken,(int)out);
5477       }
5478
5479       if(nottaken1) set_jump_target(nottaken1,(int)out);
5480       if(adj) {
5481         if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5482       }
5483     } // (!unconditional)
5484   } // if(ooo)
5485   else
5486   {
5487     // In-order execution (branch first)
5488     //if(likely[i]) printf("IOL\n");
5489     //else
5490     //printf("IOE\n");
5491     int taken=0,nottaken=0,nottaken1=0;
5492     if(!unconditional&&!nop) {
5493       if(!only32)
5494       {
5495         assert(s1h>=0);
5496         if((opcode[i]&0x2f)==4) // BEQ
5497         {
5498           if(s2h>=0) emit_cmp(s1h,s2h);
5499           else emit_test(s1h,s1h);
5500           nottaken1=(int)out;
5501           emit_jne(2);
5502         }
5503         if((opcode[i]&0x2f)==5) // BNE
5504         {
5505           if(s2h>=0) emit_cmp(s1h,s2h);
5506           else emit_test(s1h,s1h);
5507           taken=(int)out;
5508           emit_jne(1);
5509         }
5510         if((opcode[i]&0x2f)==6) // BLEZ
5511         {
5512           emit_test(s1h,s1h);
5513           taken=(int)out;
5514           emit_js(1);
5515           nottaken1=(int)out;
5516           emit_jne(2);
5517         }
5518         if((opcode[i]&0x2f)==7) // BGTZ
5519         {
5520           emit_test(s1h,s1h);
5521           nottaken1=(int)out;
5522           emit_js(2);
5523           taken=(int)out;
5524           emit_jne(1);
5525         }
5526       } // if(!only32)
5527
5528       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5529       assert(s1l>=0);
5530       if((opcode[i]&0x2f)==4) // BEQ
5531       {
5532         if(s2l>=0) emit_cmp(s1l,s2l);
5533         else emit_test(s1l,s1l);
5534         nottaken=(int)out;
5535         emit_jne(2);
5536       }
5537       if((opcode[i]&0x2f)==5) // BNE
5538       {
5539         if(s2l>=0) emit_cmp(s1l,s2l);
5540         else emit_test(s1l,s1l);
5541         nottaken=(int)out;
5542         emit_jeq(2);
5543       }
5544       if((opcode[i]&0x2f)==6) // BLEZ
5545       {
5546         emit_cmpimm(s1l,1);
5547         nottaken=(int)out;
5548         emit_jge(2);
5549       }
5550       if((opcode[i]&0x2f)==7) // BGTZ
5551       {
5552         emit_cmpimm(s1l,1);
5553         nottaken=(int)out;
5554         emit_jl(2);
5555       }
5556     } // if(!unconditional)
5557     int adj;
5558     uint64_t ds_unneeded=branch_regs[i].u;
5559     uint64_t ds_unneeded_upper=branch_regs[i].uu;
5560     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5561     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5562     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5563     ds_unneeded|=1;
5564     ds_unneeded_upper|=1;
5565     // branch taken
5566     if(!nop) {
5567       if(taken) set_jump_target(taken,(int)out);
5568       assem_debug("1:\n");
5569       wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5570                     ds_unneeded,ds_unneeded_upper);
5571       // load regs
5572       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5573       address_generation(i+1,&branch_regs[i],0);
5574       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5575       ds_assemble(i+1,&branch_regs[i]);
5576       cc=get_reg(branch_regs[i].regmap,CCREG);
5577       if(cc==-1) {
5578         emit_loadreg(CCREG,cc=HOST_CCREG);
5579         // CHECK: Is the following instruction (fall thru) allocated ok?
5580       }
5581       assert(cc==HOST_CCREG);
5582       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5583       do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5584       assem_debug("cycle count (adj)\n");
5585       if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5586       load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5587       if(internal)
5588         assem_debug("branch: internal\n");
5589       else
5590         assem_debug("branch: external\n");
5591       if(internal&&is_ds[(ba[i]-start)>>2]) {
5592         ds_assemble_entry(i);
5593       }
5594       else {
5595         add_to_linker((int)out,ba[i],internal);
5596         emit_jmp(0);
5597       }
5598     }
5599     // branch not taken
5600     cop1_usable=prev_cop1_usable;
5601     if(!unconditional) {
5602       if(nottaken1) set_jump_target(nottaken1,(int)out);
5603       set_jump_target(nottaken,(int)out);
5604       assem_debug("2:\n");
5605       if(!likely[i]) {
5606         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5607                       ds_unneeded,ds_unneeded_upper);
5608         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5609         address_generation(i+1,&branch_regs[i],0);
5610         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5611         ds_assemble(i+1,&branch_regs[i]);
5612       }
5613       cc=get_reg(branch_regs[i].regmap,CCREG);
5614       if(cc==-1&&!likely[i]) {
5615         // Cycle count isn't in a register, temporarily load it then write it out
5616         emit_loadreg(CCREG,HOST_CCREG);
5617         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5618         int jaddr=(int)out;
5619         emit_jns(0);
5620         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5621         emit_storereg(CCREG,HOST_CCREG);
5622       }
5623       else{
5624         cc=get_reg(i_regmap,CCREG);
5625         assert(cc==HOST_CCREG);
5626         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5627         int jaddr=(int)out;
5628         emit_jns(0);
5629         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5630       }
5631     }
5632   }
5633 }
5634
5635 void sjump_assemble(int i,struct regstat *i_regs)
5636 {
5637   signed char *i_regmap=i_regs->regmap;
5638   int cc;
5639   int match;
5640   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5641   assem_debug("smatch=%d\n",match);
5642   int s1h,s1l;
5643   int prev_cop1_usable=cop1_usable;
5644   int unconditional=0,nevertaken=0;
5645   int only32=0;
5646   int ooo=1;
5647   int invert=0;
5648   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5649   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5650   if(likely[i]) ooo=0;
5651   if(!match) invert=1;
5652   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5653   if(i>(ba[i]-start)>>2) invert=1;
5654   #endif
5655
5656   //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
5657   //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
5658
5659   if(ooo) {
5660     if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))
5661     {
5662       // Write-after-read dependency prevents out of order execution
5663       // First test branch condition, then execute delay slot, then branch
5664       ooo=0;
5665     }
5666     if(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))
5667       // BxxZAL $ra is available to delay insn, so do it in order
5668       ooo=0;
5669   }
5670
5671   if(ooo) {
5672     s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5673     s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5674   }
5675   else {
5676     s1l=get_reg(i_regmap,rs1[i]);
5677     s1h=get_reg(i_regmap,rs1[i]|64);
5678   }
5679   if(rs1[i]==0)
5680   {
5681     if(opcode2[i]&1) unconditional=1;
5682     else nevertaken=1;
5683     // These are never taken (r0 is never less than zero)
5684     //assert(opcode2[i]!=0);
5685     //assert(opcode2[i]!=2);
5686     //assert(opcode2[i]!=0x10);
5687     //assert(opcode2[i]!=0x12);
5688   }
5689   else {
5690     only32=(regs[i].was32>>rs1[i])&1;
5691   }
5692
5693   if(ooo) {
5694     // Out of order execution (delay slot first)
5695     //printf("OOOE\n");
5696     address_generation(i+1,i_regs,regs[i].regmap_entry);
5697     ds_assemble(i+1,i_regs);
5698     int adj;
5699     uint64_t bc_unneeded=branch_regs[i].u;
5700     uint64_t bc_unneeded_upper=branch_regs[i].uu;
5701     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5702     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5703     bc_unneeded|=1;
5704     bc_unneeded_upper|=1;
5705     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5706                   bc_unneeded,bc_unneeded_upper);
5707     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5708     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5709     if(rt1[i]==31) {
5710       int rt,return_address;
5711       rt=get_reg(branch_regs[i].regmap,31);
5712       assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5713       if(rt>=0) {
5714         // Save the PC even if the branch is not taken
5715         return_address=start+i*4+8;
5716         emit_movimm(return_address,rt); // PC into link register
5717         #ifdef IMM_PREFETCH
5718         if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5719         #endif
5720       }
5721     }
5722     cc=get_reg(branch_regs[i].regmap,CCREG);
5723     assert(cc==HOST_CCREG);
5724     if(unconditional)
5725       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5726     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5727     assem_debug("cycle count (adj)\n");
5728     if(unconditional) {
5729       do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5730       if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5731         if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5732         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5733         if(internal)
5734           assem_debug("branch: internal\n");
5735         else
5736           assem_debug("branch: external\n");
5737         if(internal&&is_ds[(ba[i]-start)>>2]) {
5738           ds_assemble_entry(i);
5739         }
5740         else {
5741           add_to_linker((int)out,ba[i],internal);
5742           emit_jmp(0);
5743         }
5744         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5745         if(((u_int)out)&7) emit_addnop(0);
5746         #endif
5747       }
5748     }
5749     else if(nevertaken) {
5750       emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5751       int jaddr=(int)out;
5752       emit_jns(0);
5753       add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5754     }
5755     else {
5756       int nottaken=0;
5757       do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5758       if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5759       if(!only32)
5760       {
5761         assert(s1h>=0);
5762         if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5763         {
5764           emit_test(s1h,s1h);
5765           if(invert){
5766             nottaken=(int)out;
5767             emit_jns(1);
5768           }else{
5769             add_to_linker((int)out,ba[i],internal);
5770             emit_js(0);
5771           }
5772         }
5773         if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5774         {
5775           emit_test(s1h,s1h);
5776           if(invert){
5777             nottaken=(int)out;
5778             emit_js(1);
5779           }else{
5780             add_to_linker((int)out,ba[i],internal);
5781             emit_jns(0);
5782           }
5783         }
5784       } // if(!only32)
5785       else
5786       {
5787         assert(s1l>=0);
5788         if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5789         {
5790           emit_test(s1l,s1l);
5791           if(invert){
5792             nottaken=(int)out;
5793             emit_jns(1);
5794           }else{
5795             add_to_linker((int)out,ba[i],internal);
5796             emit_js(0);
5797           }
5798         }
5799         if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5800         {
5801           emit_test(s1l,s1l);
5802           if(invert){
5803             nottaken=(int)out;
5804             emit_js(1);
5805           }else{
5806             add_to_linker((int)out,ba[i],internal);
5807             emit_jns(0);
5808           }
5809         }
5810       } // if(!only32)
5811
5812       if(invert) {
5813         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5814         if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5815           if(adj) {
5816             emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5817             add_to_linker((int)out,ba[i],internal);
5818           }else{
5819             emit_addnop(13);
5820             add_to_linker((int)out,ba[i],internal*2);
5821           }
5822           emit_jmp(0);
5823         }else
5824         #endif
5825         {
5826           if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5827           store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5828           load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5829           if(internal)
5830             assem_debug("branch: internal\n");
5831           else
5832             assem_debug("branch: external\n");
5833           if(internal&&is_ds[(ba[i]-start)>>2]) {
5834             ds_assemble_entry(i);
5835           }
5836           else {
5837             add_to_linker((int)out,ba[i],internal);
5838             emit_jmp(0);
5839           }
5840         }
5841         set_jump_target(nottaken,(int)out);
5842       }
5843
5844       if(adj) {
5845         if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5846       }
5847     } // (!unconditional)
5848   } // if(ooo)
5849   else
5850   {
5851     // In-order execution (branch first)
5852     //printf("IOE\n");
5853     int nottaken=0;
5854     if(rt1[i]==31) {
5855       int rt,return_address;
5856       rt=get_reg(branch_regs[i].regmap,31);
5857       if(rt>=0) {
5858         // Save the PC even if the branch is not taken
5859         return_address=start+i*4+8;
5860         emit_movimm(return_address,rt); // PC into link register
5861         #ifdef IMM_PREFETCH
5862         emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5863         #endif
5864       }
5865     }
5866     if(!unconditional) {
5867       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5868       if(!only32)
5869       {
5870         assert(s1h>=0);
5871         if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
5872         {
5873           emit_test(s1h,s1h);
5874           nottaken=(int)out;
5875           emit_jns(1);
5876         }
5877         if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
5878         {
5879           emit_test(s1h,s1h);
5880           nottaken=(int)out;
5881           emit_js(1);
5882         }
5883       } // if(!only32)
5884       else
5885       {
5886         assert(s1l>=0);
5887         if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
5888         {
5889           emit_test(s1l,s1l);
5890           nottaken=(int)out;
5891           emit_jns(1);
5892         }
5893         if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
5894         {
5895           emit_test(s1l,s1l);
5896           nottaken=(int)out;
5897           emit_js(1);
5898         }
5899       }
5900     } // if(!unconditional)
5901     int adj;
5902     uint64_t ds_unneeded=branch_regs[i].u;
5903     uint64_t ds_unneeded_upper=branch_regs[i].uu;
5904     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5905     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5906     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5907     ds_unneeded|=1;
5908     ds_unneeded_upper|=1;
5909     // branch taken
5910     if(!nevertaken) {
5911       //assem_debug("1:\n");
5912       wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5913                     ds_unneeded,ds_unneeded_upper);
5914       // load regs
5915       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5916       address_generation(i+1,&branch_regs[i],0);
5917       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5918       ds_assemble(i+1,&branch_regs[i]);
5919       cc=get_reg(branch_regs[i].regmap,CCREG);
5920       if(cc==-1) {
5921         emit_loadreg(CCREG,cc=HOST_CCREG);
5922         // CHECK: Is the following instruction (fall thru) allocated ok?
5923       }
5924       assert(cc==HOST_CCREG);
5925       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5926       do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5927       assem_debug("cycle count (adj)\n");
5928       if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5929       load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5930       if(internal)
5931         assem_debug("branch: internal\n");
5932       else
5933         assem_debug("branch: external\n");
5934       if(internal&&is_ds[(ba[i]-start)>>2]) {
5935         ds_assemble_entry(i);
5936       }
5937       else {
5938         add_to_linker((int)out,ba[i],internal);
5939         emit_jmp(0);
5940       }
5941     }
5942     // branch not taken
5943     cop1_usable=prev_cop1_usable;
5944     if(!unconditional) {
5945       set_jump_target(nottaken,(int)out);
5946       assem_debug("1:\n");
5947       if(!likely[i]) {
5948         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5949                       ds_unneeded,ds_unneeded_upper);
5950         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5951         address_generation(i+1,&branch_regs[i],0);
5952         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5953         ds_assemble(i+1,&branch_regs[i]);
5954       }
5955       cc=get_reg(branch_regs[i].regmap,CCREG);
5956       if(cc==-1&&!likely[i]) {
5957         // Cycle count isn't in a register, temporarily load it then write it out
5958         emit_loadreg(CCREG,HOST_CCREG);
5959         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5960         int jaddr=(int)out;
5961         emit_jns(0);
5962         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5963         emit_storereg(CCREG,HOST_CCREG);
5964       }
5965       else{
5966         cc=get_reg(i_regmap,CCREG);
5967         assert(cc==HOST_CCREG);
5968         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5969         int jaddr=(int)out;
5970         emit_jns(0);
5971         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5972       }
5973     }
5974   }
5975 }
5976
5977 void fjump_assemble(int i,struct regstat *i_regs)
5978 {
5979   signed char *i_regmap=i_regs->regmap;
5980   int cc;
5981   int match;
5982   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5983   assem_debug("fmatch=%d\n",match);
5984   int fs,cs;
5985   int eaddr;
5986   int ooo=1;
5987   int invert=0;
5988   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5989   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5990   if(likely[i]) ooo=0;
5991   if(!match) invert=1;
5992   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5993   if(i>(ba[i]-start)>>2) invert=1;
5994   #endif
5995
5996   if(ooo)
5997     if(itype[i+1]==FCOMP)
5998   {
5999     // Write-after-read dependency prevents out of order execution
6000     // First test branch condition, then execute delay slot, then branch
6001     ooo=0;
6002   }
6003
6004   if(ooo) {
6005     fs=get_reg(branch_regs[i].regmap,FSREG);
6006     address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
6007   }
6008   else {
6009     fs=get_reg(i_regmap,FSREG);
6010   }
6011
6012   // Check cop1 unusable
6013   if(!cop1_usable) {
6014     cs=get_reg(i_regmap,CSREG);
6015     assert(cs>=0);
6016     emit_testimm(cs,0x20000000);
6017     eaddr=(int)out;
6018     emit_jeq(0);
6019     add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
6020     cop1_usable=1;
6021   }
6022
6023   if(ooo) {
6024     // Out of order execution (delay slot first)
6025     //printf("OOOE\n");
6026     ds_assemble(i+1,i_regs);
6027     int adj;
6028     uint64_t bc_unneeded=branch_regs[i].u;
6029     uint64_t bc_unneeded_upper=branch_regs[i].uu;
6030     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6031     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
6032     bc_unneeded|=1;
6033     bc_unneeded_upper|=1;
6034     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6035                   bc_unneeded,bc_unneeded_upper);
6036     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
6037     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6038     cc=get_reg(branch_regs[i].regmap,CCREG);
6039     assert(cc==HOST_CCREG);
6040     do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6041     assem_debug("cycle count (adj)\n");
6042     if(1) {
6043       int nottaken=0;
6044       if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6045       if(1) {
6046         assert(fs>=0);
6047         emit_testimm(fs,0x800000);
6048         if(source[i]&0x10000) // BC1T
6049         {
6050           if(invert){
6051             nottaken=(int)out;
6052             emit_jeq(1);
6053           }else{
6054             add_to_linker((int)out,ba[i],internal);
6055             emit_jne(0);
6056           }
6057         }
6058         else // BC1F
6059           if(invert){
6060             nottaken=(int)out;
6061             emit_jne(1);
6062           }else{
6063             add_to_linker((int)out,ba[i],internal);
6064             emit_jeq(0);
6065           }
6066         {
6067         }
6068       } // if(!only32)
6069
6070       if(invert) {
6071         if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
6072         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6073         else if(match) emit_addnop(13);
6074         #endif
6075         store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6076         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6077         if(internal)
6078           assem_debug("branch: internal\n");
6079         else
6080           assem_debug("branch: external\n");
6081         if(internal&&is_ds[(ba[i]-start)>>2]) {
6082           ds_assemble_entry(i);
6083         }
6084         else {
6085           add_to_linker((int)out,ba[i],internal);
6086           emit_jmp(0);
6087         }
6088         set_jump_target(nottaken,(int)out);
6089       }
6090
6091       if(adj) {
6092         if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
6093       }
6094     } // (!unconditional)
6095   } // if(ooo)
6096   else
6097   {
6098     // In-order execution (branch first)
6099     //printf("IOE\n");
6100     int nottaken=0;
6101     if(1) {
6102       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6103       if(1) {
6104         assert(fs>=0);
6105         emit_testimm(fs,0x800000);
6106         if(source[i]&0x10000) // BC1T
6107         {
6108           nottaken=(int)out;
6109           emit_jeq(1);
6110         }
6111         else // BC1F
6112         {
6113           nottaken=(int)out;
6114           emit_jne(1);
6115         }
6116       }
6117     } // if(!unconditional)
6118     int adj;
6119     uint64_t ds_unneeded=branch_regs[i].u;
6120     uint64_t ds_unneeded_upper=branch_regs[i].uu;
6121     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6122     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6123     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6124     ds_unneeded|=1;
6125     ds_unneeded_upper|=1;
6126     // branch taken
6127     //assem_debug("1:\n");
6128     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6129                   ds_unneeded,ds_unneeded_upper);
6130     // load regs
6131     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6132     address_generation(i+1,&branch_regs[i],0);
6133     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6134     ds_assemble(i+1,&branch_regs[i]);
6135     cc=get_reg(branch_regs[i].regmap,CCREG);
6136     if(cc==-1) {
6137       emit_loadreg(CCREG,cc=HOST_CCREG);
6138       // CHECK: Is the following instruction (fall thru) allocated ok?
6139     }
6140     assert(cc==HOST_CCREG);
6141     store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6142     do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6143     assem_debug("cycle count (adj)\n");
6144     if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6145     load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6146     if(internal)
6147       assem_debug("branch: internal\n");
6148     else
6149       assem_debug("branch: external\n");
6150     if(internal&&is_ds[(ba[i]-start)>>2]) {
6151       ds_assemble_entry(i);
6152     }
6153     else {
6154       add_to_linker((int)out,ba[i],internal);
6155       emit_jmp(0);
6156     }
6157
6158     // branch not taken
6159     if(1) { // <- FIXME (don't need this)
6160       set_jump_target(nottaken,(int)out);
6161       assem_debug("1:\n");
6162       if(!likely[i]) {
6163         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6164                       ds_unneeded,ds_unneeded_upper);
6165         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6166         address_generation(i+1,&branch_regs[i],0);
6167         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6168         ds_assemble(i+1,&branch_regs[i]);
6169       }
6170       cc=get_reg(branch_regs[i].regmap,CCREG);
6171       if(cc==-1&&!likely[i]) {
6172         // Cycle count isn't in a register, temporarily load it then write it out
6173         emit_loadreg(CCREG,HOST_CCREG);
6174         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6175         int jaddr=(int)out;
6176         emit_jns(0);
6177         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6178         emit_storereg(CCREG,HOST_CCREG);
6179       }
6180       else{
6181         cc=get_reg(i_regmap,CCREG);
6182         assert(cc==HOST_CCREG);
6183         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6184         int jaddr=(int)out;
6185         emit_jns(0);
6186         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6187       }
6188     }
6189   }
6190 }
6191
6192 static void pagespan_assemble(int i,struct regstat *i_regs)
6193 {
6194   int s1l=get_reg(i_regs->regmap,rs1[i]);
6195   int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6196   int s2l=get_reg(i_regs->regmap,rs2[i]);
6197   int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6198   void *nt_branch=NULL;
6199   int taken=0;
6200   int nottaken=0;
6201   int unconditional=0;
6202   if(rs1[i]==0)
6203   {
6204     s1l=s2l;s1h=s2h;
6205     s2l=s2h=-1;
6206   }
6207   else if(rs2[i]==0)
6208   {
6209     s2l=s2h=-1;
6210   }
6211   if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6212     s1h=s2h=-1;
6213   }
6214   int hr=0;
6215   int addr,alt,ntaddr;
6216   if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6217   else {
6218     while(hr<HOST_REGS)
6219     {
6220       if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6221          (i_regs->regmap[hr]&63)!=rs1[i] &&
6222          (i_regs->regmap[hr]&63)!=rs2[i] )
6223       {
6224         addr=hr++;break;
6225       }
6226       hr++;
6227     }
6228   }
6229   while(hr<HOST_REGS)
6230   {
6231     if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6232        (i_regs->regmap[hr]&63)!=rs1[i] &&
6233        (i_regs->regmap[hr]&63)!=rs2[i] )
6234     {
6235       alt=hr++;break;
6236     }
6237     hr++;
6238   }
6239   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6240   {
6241     while(hr<HOST_REGS)
6242     {
6243       if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6244          (i_regs->regmap[hr]&63)!=rs1[i] &&
6245          (i_regs->regmap[hr]&63)!=rs2[i] )
6246       {
6247         ntaddr=hr;break;
6248       }
6249       hr++;
6250     }
6251   }
6252   assert(hr<HOST_REGS);
6253   if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6254     load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6255   }
6256   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6257   if(opcode[i]==2) // J
6258   {
6259     unconditional=1;
6260   }
6261   if(opcode[i]==3) // JAL
6262   {
6263     // TODO: mini_ht
6264     int rt=get_reg(i_regs->regmap,31);
6265     emit_movimm(start+i*4+8,rt);
6266     unconditional=1;
6267   }
6268   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6269   {
6270     emit_mov(s1l,addr);
6271     if(opcode2[i]==9) // JALR
6272     {
6273       int rt=get_reg(i_regs->regmap,rt1[i]);
6274       emit_movimm(start+i*4+8,rt);
6275     }
6276   }
6277   if((opcode[i]&0x3f)==4) // BEQ
6278   {
6279     if(rs1[i]==rs2[i])
6280     {
6281       unconditional=1;
6282     }
6283     else
6284     #ifdef HAVE_CMOV_IMM
6285     if(s1h<0) {
6286       if(s2l>=0) emit_cmp(s1l,s2l);
6287       else emit_test(s1l,s1l);
6288       emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6289     }
6290     else
6291     #endif
6292     {
6293       assert(s1l>=0);
6294       emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6295       if(s1h>=0) {
6296         if(s2h>=0) emit_cmp(s1h,s2h);
6297         else emit_test(s1h,s1h);
6298         emit_cmovne_reg(alt,addr);
6299       }
6300       if(s2l>=0) emit_cmp(s1l,s2l);
6301       else emit_test(s1l,s1l);
6302       emit_cmovne_reg(alt,addr);
6303     }
6304   }
6305   if((opcode[i]&0x3f)==5) // BNE
6306   {
6307     #ifdef HAVE_CMOV_IMM
6308     if(s1h<0) {
6309       if(s2l>=0) emit_cmp(s1l,s2l);
6310       else emit_test(s1l,s1l);
6311       emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6312     }
6313     else
6314     #endif
6315     {
6316       assert(s1l>=0);
6317       emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6318       if(s1h>=0) {
6319         if(s2h>=0) emit_cmp(s1h,s2h);
6320         else emit_test(s1h,s1h);
6321         emit_cmovne_reg(alt,addr);
6322       }
6323       if(s2l>=0) emit_cmp(s1l,s2l);
6324       else emit_test(s1l,s1l);
6325       emit_cmovne_reg(alt,addr);
6326     }
6327   }
6328   if((opcode[i]&0x3f)==0x14) // BEQL
6329   {
6330     if(s1h>=0) {
6331       if(s2h>=0) emit_cmp(s1h,s2h);
6332       else emit_test(s1h,s1h);
6333       nottaken=(int)out;
6334       emit_jne(0);
6335     }
6336     if(s2l>=0) emit_cmp(s1l,s2l);
6337     else emit_test(s1l,s1l);
6338     if(nottaken) set_jump_target(nottaken,(int)out);
6339     nottaken=(int)out;
6340     emit_jne(0);
6341   }
6342   if((opcode[i]&0x3f)==0x15) // BNEL
6343   {
6344     if(s1h>=0) {
6345       if(s2h>=0) emit_cmp(s1h,s2h);
6346       else emit_test(s1h,s1h);
6347       taken=(int)out;
6348       emit_jne(0);
6349     }
6350     if(s2l>=0) emit_cmp(s1l,s2l);
6351     else emit_test(s1l,s1l);
6352     nottaken=(int)out;
6353     emit_jeq(0);
6354     if(taken) set_jump_target(taken,(int)out);
6355   }
6356   if((opcode[i]&0x3f)==6) // BLEZ
6357   {
6358     emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6359     emit_cmpimm(s1l,1);
6360     if(s1h>=0) emit_mov(addr,ntaddr);
6361     emit_cmovl_reg(alt,addr);
6362     if(s1h>=0) {
6363       emit_test(s1h,s1h);
6364       emit_cmovne_reg(ntaddr,addr);
6365       emit_cmovs_reg(alt,addr);
6366     }
6367   }
6368   if((opcode[i]&0x3f)==7) // BGTZ
6369   {
6370     emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6371     emit_cmpimm(s1l,1);
6372     if(s1h>=0) emit_mov(addr,alt);
6373     emit_cmovl_reg(ntaddr,addr);
6374     if(s1h>=0) {
6375       emit_test(s1h,s1h);
6376       emit_cmovne_reg(alt,addr);
6377       emit_cmovs_reg(ntaddr,addr);
6378     }
6379   }
6380   if((opcode[i]&0x3f)==0x16) // BLEZL
6381   {
6382     assert((opcode[i]&0x3f)!=0x16);
6383   }
6384   if((opcode[i]&0x3f)==0x17) // BGTZL
6385   {
6386     assert((opcode[i]&0x3f)!=0x17);
6387   }
6388   assert(opcode[i]!=1); // BLTZ/BGEZ
6389
6390   //FIXME: Check CSREG
6391   if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6392     if((source[i]&0x30000)==0) // BC1F
6393     {
6394       emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6395       emit_testimm(s1l,0x800000);
6396       emit_cmovne_reg(alt,addr);
6397     }
6398     if((source[i]&0x30000)==0x10000) // BC1T
6399     {
6400       emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6401       emit_testimm(s1l,0x800000);
6402       emit_cmovne_reg(alt,addr);
6403     }
6404     if((source[i]&0x30000)==0x20000) // BC1FL
6405     {
6406       emit_testimm(s1l,0x800000);
6407       nottaken=(int)out;
6408       emit_jne(0);
6409     }
6410     if((source[i]&0x30000)==0x30000) // BC1TL
6411     {
6412       emit_testimm(s1l,0x800000);
6413       nottaken=(int)out;
6414       emit_jeq(0);
6415     }
6416   }
6417
6418   assert(i_regs->regmap[HOST_CCREG]==CCREG);
6419   wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6420   if(likely[i]||unconditional)
6421   {
6422     emit_movimm(ba[i],HOST_BTREG);
6423   }
6424   else if(addr!=HOST_BTREG)
6425   {
6426     emit_mov(addr,HOST_BTREG);
6427   }
6428   void *branch_addr=out;
6429   emit_jmp(0);
6430   int target_addr=start+i*4+5;
6431   void *stub=out;
6432   void *compiled_target_addr=check_addr(target_addr);
6433   emit_extjump_ds((int)branch_addr,target_addr);
6434   if(compiled_target_addr) {
6435     set_jump_target((int)branch_addr,(int)compiled_target_addr);
6436     add_link(target_addr,stub);
6437   }
6438   else set_jump_target((int)branch_addr,(int)stub);
6439   if(likely[i]) {
6440     // Not-taken path
6441     set_jump_target((int)nottaken,(int)out);
6442     wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6443     void *branch_addr=out;
6444     emit_jmp(0);
6445     int target_addr=start+i*4+8;
6446     void *stub=out;
6447     void *compiled_target_addr=check_addr(target_addr);
6448     emit_extjump_ds((int)branch_addr,target_addr);
6449     if(compiled_target_addr) {
6450       set_jump_target((int)branch_addr,(int)compiled_target_addr);
6451       add_link(target_addr,stub);
6452     }
6453     else set_jump_target((int)branch_addr,(int)stub);
6454   }
6455 }
6456
6457 // Assemble the delay slot for the above
6458 static void pagespan_ds()
6459 {
6460   assem_debug("initial delay slot:\n");
6461   u_int vaddr=start+1;
6462   u_int page=get_page(vaddr);
6463   u_int vpage=get_vpage(vaddr);
6464   ll_add(jump_dirty+vpage,vaddr,(void *)out);
6465   do_dirty_stub_ds();
6466   ll_add(jump_in+page,vaddr,(void *)out);
6467   assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6468   if(regs[0].regmap[HOST_CCREG]!=CCREG)
6469     wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6470   if(regs[0].regmap[HOST_BTREG]!=BTREG)
6471     emit_writeword(HOST_BTREG,(int)&branch_target);
6472   load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6473   address_generation(0,&regs[0],regs[0].regmap_entry);
6474   if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
6475     load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6476   cop1_usable=0;
6477   is_delayslot=0;
6478   switch(itype[0]) {
6479     case ALU:
6480       alu_assemble(0,&regs[0]);break;
6481     case IMM16:
6482       imm16_assemble(0,&regs[0]);break;
6483     case SHIFT:
6484       shift_assemble(0,&regs[0]);break;
6485     case SHIFTIMM:
6486       shiftimm_assemble(0,&regs[0]);break;
6487     case LOAD:
6488       load_assemble(0,&regs[0]);break;
6489     case LOADLR:
6490       loadlr_assemble(0,&regs[0]);break;
6491     case STORE:
6492       store_assemble(0,&regs[0]);break;
6493     case STORELR:
6494       storelr_assemble(0,&regs[0]);break;
6495     case COP0:
6496       cop0_assemble(0,&regs[0]);break;
6497     case COP1:
6498       cop1_assemble(0,&regs[0]);break;
6499     case C1LS:
6500       c1ls_assemble(0,&regs[0]);break;
6501     case COP2:
6502       cop2_assemble(0,&regs[0]);break;
6503     case C2LS:
6504       c2ls_assemble(0,&regs[0]);break;
6505     case C2OP:
6506       c2op_assemble(0,&regs[0]);break;
6507     case FCONV:
6508       fconv_assemble(0,&regs[0]);break;
6509     case FLOAT:
6510       float_assemble(0,&regs[0]);break;
6511     case FCOMP:
6512       fcomp_assemble(0,&regs[0]);break;
6513     case MULTDIV:
6514       multdiv_assemble(0,&regs[0]);break;
6515     case MOV:
6516       mov_assemble(0,&regs[0]);break;
6517     case SYSCALL:
6518     case HLECALL:
6519     case INTCALL:
6520     case SPAN:
6521     case UJUMP:
6522     case RJUMP:
6523     case CJUMP:
6524     case SJUMP:
6525     case FJUMP:
6526       printf("Jump in the delay slot.  This is probably a bug.\n");
6527   }
6528   int btaddr=get_reg(regs[0].regmap,BTREG);
6529   if(btaddr<0) {
6530     btaddr=get_reg(regs[0].regmap,-1);
6531     emit_readword((int)&branch_target,btaddr);
6532   }
6533   assert(btaddr!=HOST_CCREG);
6534   if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6535 #ifdef HOST_IMM8
6536   emit_movimm(start+4,HOST_TEMPREG);
6537   emit_cmp(btaddr,HOST_TEMPREG);
6538 #else
6539   emit_cmpimm(btaddr,start+4);
6540 #endif
6541   int branch=(int)out;
6542   emit_jeq(0);
6543   store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6544   emit_jmp(jump_vaddr_reg[btaddr]);
6545   set_jump_target(branch,(int)out);
6546   store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6547   load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6548 }
6549
6550 // Basic liveness analysis for MIPS registers
6551 void unneeded_registers(int istart,int iend,int r)
6552 {
6553   int i;
6554   uint64_t u,uu,b,bu;
6555   uint64_t temp_u,temp_uu;
6556   uint64_t tdep;
6557   if(iend==slen-1) {
6558     u=1;uu=1;
6559   }else{
6560     u=unneeded_reg[iend+1];
6561     uu=unneeded_reg_upper[iend+1];
6562     u=1;uu=1;
6563   }
6564   for (i=iend;i>=istart;i--)
6565   {
6566     //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6567     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6568     {
6569       // If subroutine call, flag return address as a possible branch target
6570       if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6571
6572       if(ba[i]<start || ba[i]>=(start+slen*4))
6573       {
6574         // Branch out of this block, flush all regs
6575         u=1;
6576         uu=1;
6577         /* Hexagon hack
6578         if(itype[i]==UJUMP&&rt1[i]==31)
6579         {
6580           uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6581         }
6582         if(itype[i]==RJUMP&&rs1[i]==31)
6583         {
6584           uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6585         }
6586         if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
6587           if(itype[i]==UJUMP&&rt1[i]==31)
6588           {
6589             //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6590             uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6591           }
6592           if(itype[i]==RJUMP&&rs1[i]==31)
6593           {
6594             //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6595             uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6596           }
6597         }*/
6598         branch_unneeded_reg[i]=u;
6599         branch_unneeded_reg_upper[i]=uu;
6600         // Merge in delay slot
6601         tdep=(~uu>>rt1[i+1])&1;
6602         u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6603         uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6604         u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6605         uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6606         uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6607         u|=1;uu|=1;
6608         // If branch is "likely" (and conditional)
6609         // then we skip the delay slot on the fall-thru path
6610         if(likely[i]) {
6611           if(i<slen-1) {
6612             u&=unneeded_reg[i+2];
6613             uu&=unneeded_reg_upper[i+2];
6614           }
6615           else
6616           {
6617             u=1;
6618             uu=1;
6619           }
6620         }
6621       }
6622       else
6623       {
6624         // Internal branch, flag target
6625         bt[(ba[i]-start)>>2]=1;
6626         if(ba[i]<=start+i*4) {
6627           // Backward branch
6628           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6629           {
6630             // Unconditional branch
6631             temp_u=1;temp_uu=1;
6632           } else {
6633             // Conditional branch (not taken case)
6634             temp_u=unneeded_reg[i+2];
6635             temp_uu=unneeded_reg_upper[i+2];
6636           }
6637           // Merge in delay slot
6638           tdep=(~temp_uu>>rt1[i+1])&1;
6639           temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6640           temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6641           temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6642           temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6643           temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6644           temp_u|=1;temp_uu|=1;
6645           // If branch is "likely" (and conditional)
6646           // then we skip the delay slot on the fall-thru path
6647           if(likely[i]) {
6648             if(i<slen-1) {
6649               temp_u&=unneeded_reg[i+2];
6650               temp_uu&=unneeded_reg_upper[i+2];
6651             }
6652             else
6653             {
6654               temp_u=1;
6655               temp_uu=1;
6656             }
6657           }
6658           tdep=(~temp_uu>>rt1[i])&1;
6659           temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6660           temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6661           temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6662           temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6663           temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6664           temp_u|=1;temp_uu|=1;
6665           unneeded_reg[i]=temp_u;
6666           unneeded_reg_upper[i]=temp_uu;
6667           // Only go three levels deep.  This recursion can take an
6668           // excessive amount of time if there are a lot of nested loops.
6669           if(r<2) {
6670             unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6671           }else{
6672             unneeded_reg[(ba[i]-start)>>2]=1;
6673             unneeded_reg_upper[(ba[i]-start)>>2]=1;
6674           }
6675         } /*else*/ if(1) {
6676           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6677           {
6678             // Unconditional branch
6679             u=unneeded_reg[(ba[i]-start)>>2];
6680             uu=unneeded_reg_upper[(ba[i]-start)>>2];
6681             branch_unneeded_reg[i]=u;
6682             branch_unneeded_reg_upper[i]=uu;
6683         //u=1;
6684         //uu=1;
6685         //branch_unneeded_reg[i]=u;
6686         //branch_unneeded_reg_upper[i]=uu;
6687             // Merge in delay slot
6688             tdep=(~uu>>rt1[i+1])&1;
6689             u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6690             uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6691             u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6692             uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6693             uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6694             u|=1;uu|=1;
6695           } else {
6696             // Conditional branch
6697             b=unneeded_reg[(ba[i]-start)>>2];
6698             bu=unneeded_reg_upper[(ba[i]-start)>>2];
6699             branch_unneeded_reg[i]=b;
6700             branch_unneeded_reg_upper[i]=bu;
6701         //b=1;
6702         //bu=1;
6703         //branch_unneeded_reg[i]=b;
6704         //branch_unneeded_reg_upper[i]=bu;
6705             // Branch delay slot
6706             tdep=(~uu>>rt1[i+1])&1;
6707             b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6708             bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6709             b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6710             bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6711             bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6712             b|=1;bu|=1;
6713             // If branch is "likely" then we skip the
6714             // delay slot on the fall-thru path
6715             if(likely[i]) {
6716               u=b;
6717               uu=bu;
6718               if(i<slen-1) {
6719                 u&=unneeded_reg[i+2];
6720                 uu&=unneeded_reg_upper[i+2];
6721         //u=1;
6722         //uu=1;
6723               }
6724             } else {
6725               u&=b;
6726               uu&=bu;
6727         //u=1;
6728         //uu=1;
6729             }
6730             if(i<slen-1) {
6731               branch_unneeded_reg[i]&=unneeded_reg[i+2];
6732               branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6733         //branch_unneeded_reg[i]=1;
6734         //branch_unneeded_reg_upper[i]=1;
6735             } else {
6736               branch_unneeded_reg[i]=1;
6737               branch_unneeded_reg_upper[i]=1;
6738             }
6739           }
6740         }
6741       }
6742     }
6743     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
6744     {
6745       // SYSCALL instruction (software interrupt)
6746       u=1;
6747       uu=1;
6748     }
6749     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6750     {
6751       // ERET instruction (return from interrupt)
6752       u=1;
6753       uu=1;
6754     }
6755     //u=uu=1; // DEBUG
6756     tdep=(~uu>>rt1[i])&1;
6757     // Written registers are unneeded
6758     u|=1LL<<rt1[i];
6759     u|=1LL<<rt2[i];
6760     uu|=1LL<<rt1[i];
6761     uu|=1LL<<rt2[i];
6762     // Accessed registers are needed
6763     u&=~(1LL<<rs1[i]);
6764     u&=~(1LL<<rs2[i]);
6765     uu&=~(1LL<<us1[i]);
6766     uu&=~(1LL<<us2[i]);
6767     // Source-target dependencies
6768     uu&=~(tdep<<dep1[i]);
6769     uu&=~(tdep<<dep2[i]);
6770     // R0 is always unneeded
6771     u|=1;uu|=1;
6772     // Save it
6773     unneeded_reg[i]=u;
6774     unneeded_reg_upper[i]=uu;
6775     /*
6776     printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6777     printf("U:");
6778     int r;
6779     for(r=1;r<=CCREG;r++) {
6780       if((unneeded_reg[i]>>r)&1) {
6781         if(r==HIREG) printf(" HI");
6782         else if(r==LOREG) printf(" LO");
6783         else printf(" r%d",r);
6784       }
6785     }
6786     printf(" UU:");
6787     for(r=1;r<=CCREG;r++) {
6788       if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
6789         if(r==HIREG) printf(" HI");
6790         else if(r==LOREG) printf(" LO");
6791         else printf(" r%d",r);
6792       }
6793     }
6794     printf("\n");*/
6795   }
6796 #ifdef FORCE32
6797   for (i=iend;i>=istart;i--)
6798   {
6799     unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
6800   }
6801 #endif
6802 }
6803
6804 // Identify registers which are likely to contain 32-bit values
6805 // This is used to predict whether any branches will jump to a
6806 // location with 64-bit values in registers.
6807 static void provisional_32bit()
6808 {
6809   int i,j;
6810   uint64_t is32=1;
6811   uint64_t lastbranch=1;
6812
6813   for(i=0;i<slen;i++)
6814   {
6815     if(i>0) {
6816       if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
6817         if(i>1) is32=lastbranch;
6818         else is32=1;
6819       }
6820     }
6821     if(i>1)
6822     {
6823       if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
6824         if(likely[i-2]) {
6825           if(i>2) is32=lastbranch;
6826           else is32=1;
6827         }
6828       }
6829       if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
6830       {
6831         if(rs1[i-2]==0||rs2[i-2]==0)
6832         {
6833           if(rs1[i-2]) {
6834             is32|=1LL<<rs1[i-2];
6835           }
6836           if(rs2[i-2]) {
6837             is32|=1LL<<rs2[i-2];
6838           }
6839         }
6840       }
6841     }
6842     // If something jumps here with 64-bit values
6843     // then promote those registers to 64 bits
6844     if(bt[i])
6845     {
6846       uint64_t temp_is32=is32;
6847       for(j=i-1;j>=0;j--)
6848       {
6849         if(ba[j]==start+i*4)
6850           //temp_is32&=branch_regs[j].is32;
6851           temp_is32&=p32[j];
6852       }
6853       for(j=i;j<slen;j++)
6854       {
6855         if(ba[j]==start+i*4)
6856           temp_is32=1;
6857       }
6858       is32=temp_is32;
6859     }
6860     int type=itype[i];
6861     int op=opcode[i];
6862     int op2=opcode2[i];
6863     int rt=rt1[i];
6864     int s1=rs1[i];
6865     int s2=rs2[i];
6866     if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
6867       // Branches don't write registers, consider the delay slot instead.
6868       type=itype[i+1];
6869       op=opcode[i+1];
6870       op2=opcode2[i+1];
6871       rt=rt1[i+1];
6872       s1=rs1[i+1];
6873       s2=rs2[i+1];
6874       lastbranch=is32;
6875     }
6876     switch(type) {
6877       case LOAD:
6878         if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
6879            opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
6880           is32&=~(1LL<<rt);
6881         else
6882           is32|=1LL<<rt;
6883         break;
6884       case STORE:
6885       case STORELR:
6886         break;
6887       case LOADLR:
6888         if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
6889         if(op==0x22) is32|=1LL<<rt; // LWL
6890         break;
6891       case IMM16:
6892         if (op==0x08||op==0x09|| // ADDI/ADDIU
6893             op==0x0a||op==0x0b|| // SLTI/SLTIU
6894             op==0x0c|| // ANDI
6895             op==0x0f)  // LUI
6896         {
6897           is32|=1LL<<rt;
6898         }
6899         if(op==0x18||op==0x19) { // DADDI/DADDIU
6900           is32&=~(1LL<<rt);
6901           //if(imm[i]==0)
6902           //  is32|=((is32>>s1)&1LL)<<rt;
6903         }
6904         if(op==0x0d||op==0x0e) { // ORI/XORI
6905           uint64_t sr=((is32>>s1)&1LL);
6906           is32&=~(1LL<<rt);
6907           is32|=sr<<rt;
6908         }
6909         break;
6910       case UJUMP:
6911         break;
6912       case RJUMP:
6913         break;
6914       case CJUMP:
6915         break;
6916       case SJUMP:
6917         break;
6918       case FJUMP:
6919         break;
6920       case ALU:
6921         if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
6922           is32|=1LL<<rt;
6923         }
6924         if(op2==0x2a||op2==0x2b) { // SLT/SLTU
6925           is32|=1LL<<rt;
6926         }
6927         else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
6928           uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
6929           is32&=~(1LL<<rt);
6930           is32|=sr<<rt;
6931         }
6932         else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
6933           if(s1==0&&s2==0) {
6934             is32|=1LL<<rt;
6935           }
6936           else if(s2==0) {
6937             uint64_t sr=((is32>>s1)&1LL);
6938             is32&=~(1LL<<rt);
6939             is32|=sr<<rt;
6940           }
6941           else if(s1==0) {
6942             uint64_t sr=((is32>>s2)&1LL);
6943             is32&=~(1LL<<rt);
6944             is32|=sr<<rt;
6945           }
6946           else {
6947             is32&=~(1LL<<rt);
6948           }
6949         }
6950         else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
6951           if(s1==0&&s2==0) {
6952             is32|=1LL<<rt;
6953           }
6954           else if(s2==0) {
6955             uint64_t sr=((is32>>s1)&1LL);
6956             is32&=~(1LL<<rt);
6957             is32|=sr<<rt;
6958           }
6959           else {
6960             is32&=~(1LL<<rt);
6961           }
6962         }
6963         break;
6964       case MULTDIV:
6965         if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
6966           is32&=~((1LL<<HIREG)|(1LL<<LOREG));
6967         }
6968         else {
6969           is32|=(1LL<<HIREG)|(1LL<<LOREG);
6970         }
6971         break;
6972       case MOV:
6973         {
6974           uint64_t sr=((is32>>s1)&1LL);
6975           is32&=~(1LL<<rt);
6976           is32|=sr<<rt;
6977         }
6978         break;
6979       case SHIFT:
6980         if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
6981         else is32|=1LL<<rt; // SLLV/SRLV/SRAV
6982         break;
6983       case SHIFTIMM:
6984         is32|=1LL<<rt;
6985         // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
6986         if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
6987         break;
6988       case COP0:
6989         if(op2==0) is32|=1LL<<rt; // MFC0
6990         break;
6991       case COP1:
6992       case COP2:
6993         if(op2==0) is32|=1LL<<rt; // MFC1
6994         if(op2==1) is32&=~(1LL<<rt); // DMFC1
6995         if(op2==2) is32|=1LL<<rt; // CFC1
6996         break;
6997       case C1LS:
6998       case C2LS:
6999         break;
7000       case FLOAT:
7001       case FCONV:
7002         break;
7003       case FCOMP:
7004         break;
7005       case C2OP:
7006       case SYSCALL:
7007       case HLECALL:
7008         break;
7009       default:
7010         break;
7011     }
7012     is32|=1;
7013     p32[i]=is32;
7014
7015     if(i>0)
7016     {
7017       if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
7018       {
7019         if(rt1[i-1]==31) // JAL/JALR
7020         {
7021           // Subroutine call will return here, don't alloc any registers
7022           is32=1;
7023         }
7024         else if(i+1<slen)
7025         {
7026           // Internal branch will jump here, match registers to caller
7027           is32=0x3FFFFFFFFLL;
7028         }
7029       }
7030     }
7031   }
7032 }
7033
7034 // Identify registers which may be assumed to contain 32-bit values
7035 // and where optimizations will rely on this.
7036 // This is used to determine whether backward branches can safely
7037 // jump to a location with 64-bit values in registers.
7038 static void provisional_r32()
7039 {
7040   u_int r32=0;
7041   int i;
7042
7043   for (i=slen-1;i>=0;i--)
7044   {
7045     int hr;
7046     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7047     {
7048       if(ba[i]<start || ba[i]>=(start+slen*4))
7049       {
7050         // Branch out of this block, don't need anything
7051         r32=0;
7052       }
7053       else
7054       {
7055         // Internal branch
7056         // Need whatever matches the target
7057         // (and doesn't get overwritten by the delay slot instruction)
7058         r32=0;
7059         int t=(ba[i]-start)>>2;
7060         if(ba[i]>start+i*4) {
7061           // Forward branch
7062           //if(!(requires_32bit[t]&~regs[i].was32))
7063           //  r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7064           if(!(pr32[t]&~regs[i].was32))
7065             r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7066         }else{
7067           // Backward branch
7068           if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
7069             r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7070         }
7071       }
7072       // Conditional branch may need registers for following instructions
7073       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7074       {
7075         if(i<slen-2) {
7076           //r32|=requires_32bit[i+2];
7077           r32|=pr32[i+2];
7078           r32&=regs[i].was32;
7079           // Mark this address as a branch target since it may be called
7080           // upon return from interrupt
7081           //bt[i+2]=1;
7082         }
7083       }
7084       // Merge in delay slot
7085       if(!likely[i]) {
7086         // These are overwritten unless the branch is "likely"
7087         // and the delay slot is nullified if not taken
7088         r32&=~(1LL<<rt1[i+1]);
7089         r32&=~(1LL<<rt2[i+1]);
7090       }
7091       // Assume these are needed (delay slot)
7092       if(us1[i+1]>0)
7093       {
7094         if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7095       }
7096       if(us2[i+1]>0)
7097       {
7098         if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7099       }
7100       if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7101       {
7102         if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7103       }
7104       if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7105       {
7106         if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7107       }
7108     }
7109     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7110     {
7111       // SYSCALL instruction (software interrupt)
7112       r32=0;
7113     }
7114     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7115     {
7116       // ERET instruction (return from interrupt)
7117       r32=0;
7118     }
7119     // Check 32 bits
7120     r32&=~(1LL<<rt1[i]);
7121     r32&=~(1LL<<rt2[i]);
7122     if(us1[i]>0)
7123     {
7124       if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7125     }
7126     if(us2[i]>0)
7127     {
7128       if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7129     }
7130     if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7131     {
7132       if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7133     }
7134     if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7135     {
7136       if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7137     }
7138     //requires_32bit[i]=r32;
7139     pr32[i]=r32;
7140
7141     // Dirty registers which are 32-bit, require 32-bit input
7142     // as they will be written as 32-bit values
7143     for(hr=0;hr<HOST_REGS;hr++)
7144     {
7145       if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
7146         if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7147           if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7148           pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7149           //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7150         }
7151       }
7152     }
7153   }
7154 }
7155
7156 // Write back dirty registers as soon as we will no longer modify them,
7157 // so that we don't end up with lots of writes at the branches.
7158 void clean_registers(int istart,int iend,int wr)
7159 {
7160   int i;
7161   int r;
7162   u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7163   u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7164   if(iend==slen-1) {
7165     will_dirty_i=will_dirty_next=0;
7166     wont_dirty_i=wont_dirty_next=0;
7167   }else{
7168     will_dirty_i=will_dirty_next=will_dirty[iend+1];
7169     wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7170   }
7171   for (i=iend;i>=istart;i--)
7172   {
7173     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7174     {
7175       if(ba[i]<start || ba[i]>=(start+slen*4))
7176       {
7177         // Branch out of this block, flush all regs
7178         if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7179         {
7180           // Unconditional branch
7181           will_dirty_i=0;
7182           wont_dirty_i=0;
7183           // Merge in delay slot (will dirty)
7184           for(r=0;r<HOST_REGS;r++) {
7185             if(r!=EXCLUDE_REG) {
7186               if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7187               if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7188               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7189               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7190               if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7191               if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7192               if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7193               if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7194               if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7195               if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7196               if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7197               if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7198               if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7199               if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7200             }
7201           }
7202         }
7203         else
7204         {
7205           // Conditional branch
7206           will_dirty_i=0;
7207           wont_dirty_i=wont_dirty_next;
7208           // Merge in delay slot (will dirty)
7209           for(r=0;r<HOST_REGS;r++) {
7210             if(r!=EXCLUDE_REG) {
7211               if(!likely[i]) {
7212                 // Might not dirty if likely branch is not taken
7213                 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7214                 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7215                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7216                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7217                 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7218                 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7219                 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7220                 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7221                 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7222                 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7223                 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7224                 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7225                 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7226                 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7227               }
7228             }
7229           }
7230         }
7231         // Merge in delay slot (wont dirty)
7232         for(r=0;r<HOST_REGS;r++) {
7233           if(r!=EXCLUDE_REG) {
7234             if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7235             if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7236             if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7237             if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7238             if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7239             if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7240             if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7241             if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7242             if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7243             if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7244           }
7245         }
7246         if(wr) {
7247           #ifndef DESTRUCTIVE_WRITEBACK
7248           branch_regs[i].dirty&=wont_dirty_i;
7249           #endif
7250           branch_regs[i].dirty|=will_dirty_i;
7251         }
7252       }
7253       else
7254       {
7255         // Internal branch
7256         if(ba[i]<=start+i*4) {
7257           // Backward branch
7258           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7259           {
7260             // Unconditional branch
7261             temp_will_dirty=0;
7262             temp_wont_dirty=0;
7263             // Merge in delay slot (will dirty)
7264             for(r=0;r<HOST_REGS;r++) {
7265               if(r!=EXCLUDE_REG) {
7266                 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7267                 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7268                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7269                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7270                 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7271                 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7272                 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7273                 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7274                 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7275                 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7276                 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7277                 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7278                 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7279                 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7280               }
7281             }
7282           } else {
7283             // Conditional branch (not taken case)
7284             temp_will_dirty=will_dirty_next;
7285             temp_wont_dirty=wont_dirty_next;
7286             // Merge in delay slot (will dirty)
7287             for(r=0;r<HOST_REGS;r++) {
7288               if(r!=EXCLUDE_REG) {
7289                 if(!likely[i]) {
7290                   // Will not dirty if likely branch is not taken
7291                   if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7292                   if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7293                   if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7294                   if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7295                   if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7296                   if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7297                   if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7298                   //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7299                   //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7300                   if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7301                   if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7302                   if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7303                   if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7304                   if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7305                 }
7306               }
7307             }
7308           }
7309           // Merge in delay slot (wont dirty)
7310           for(r=0;r<HOST_REGS;r++) {
7311             if(r!=EXCLUDE_REG) {
7312               if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7313               if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7314               if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7315               if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7316               if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7317               if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7318               if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7319               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7320               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7321               if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7322             }
7323           }
7324           // Deal with changed mappings
7325           if(i<iend) {
7326             for(r=0;r<HOST_REGS;r++) {
7327               if(r!=EXCLUDE_REG) {
7328                 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7329                   temp_will_dirty&=~(1<<r);
7330                   temp_wont_dirty&=~(1<<r);
7331                   if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7332                     temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7333                     temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7334                   } else {
7335                     temp_will_dirty|=1<<r;
7336                     temp_wont_dirty|=1<<r;
7337                   }
7338                 }
7339               }
7340             }
7341           }
7342           if(wr) {
7343             will_dirty[i]=temp_will_dirty;
7344             wont_dirty[i]=temp_wont_dirty;
7345             clean_registers((ba[i]-start)>>2,i-1,0);
7346           }else{
7347             // Limit recursion.  It can take an excessive amount
7348             // of time if there are a lot of nested loops.
7349             will_dirty[(ba[i]-start)>>2]=0;
7350             wont_dirty[(ba[i]-start)>>2]=-1;
7351           }
7352         }
7353         /*else*/ if(1)
7354         {
7355           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7356           {
7357             // Unconditional branch
7358             will_dirty_i=0;
7359             wont_dirty_i=0;
7360           //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7361             for(r=0;r<HOST_REGS;r++) {
7362               if(r!=EXCLUDE_REG) {
7363                 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7364                   will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7365                   wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7366                 }
7367               }
7368             }
7369           //}
7370             // Merge in delay slot
7371             for(r=0;r<HOST_REGS;r++) {
7372               if(r!=EXCLUDE_REG) {
7373                 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7374                 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7375                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7376                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7377                 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7378                 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7379                 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7380                 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7381                 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7382                 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7383                 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7384                 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7385                 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7386                 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7387               }
7388             }
7389           } else {
7390             // Conditional branch
7391             will_dirty_i=will_dirty_next;
7392             wont_dirty_i=wont_dirty_next;
7393           //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7394             for(r=0;r<HOST_REGS;r++) {
7395               if(r!=EXCLUDE_REG) {
7396                 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7397                   will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7398                   wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7399                 }
7400                 else
7401                 {
7402                   will_dirty_i&=~(1<<r);
7403                 }
7404                 // Treat delay slot as part of branch too
7405                 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7406                   will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7407                   wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7408                 }
7409                 else
7410                 {
7411                   will_dirty[i+1]&=~(1<<r);
7412                 }*/
7413               }
7414             }
7415           //}
7416             // Merge in delay slot
7417             for(r=0;r<HOST_REGS;r++) {
7418               if(r!=EXCLUDE_REG) {
7419                 if(!likely[i]) {
7420                   // Might not dirty if likely branch is not taken
7421                   if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7422                   if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7423                   if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7424                   if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7425                   if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7426                   if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7427                   if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7428                   //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7429                   //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7430                   if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7431                   if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7432                   if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7433                   if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7434                   if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7435                 }
7436               }
7437             }
7438           }
7439           // Merge in delay slot
7440           for(r=0;r<HOST_REGS;r++) {
7441             if(r!=EXCLUDE_REG) {
7442               if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7443               if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7444               if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7445               if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7446               if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7447               if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7448               if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7449               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7450               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7451               if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7452             }
7453           }
7454           if(wr) {
7455             #ifndef DESTRUCTIVE_WRITEBACK
7456             branch_regs[i].dirty&=wont_dirty_i;
7457             #endif
7458             branch_regs[i].dirty|=will_dirty_i;
7459           }
7460         }
7461       }
7462     }
7463     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7464     {
7465       // SYSCALL instruction (software interrupt)
7466       will_dirty_i=0;
7467       wont_dirty_i=0;
7468     }
7469     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7470     {
7471       // ERET instruction (return from interrupt)
7472       will_dirty_i=0;
7473       wont_dirty_i=0;
7474     }
7475     will_dirty_next=will_dirty_i;
7476     wont_dirty_next=wont_dirty_i;
7477     for(r=0;r<HOST_REGS;r++) {
7478       if(r!=EXCLUDE_REG) {
7479         if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7480         if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7481         if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7482         if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7483         if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7484         if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7485         if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7486         if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7487         if(i>istart) {
7488           if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7489           {
7490             // Don't store a register immediately after writing it,
7491             // may prevent dual-issue.
7492             if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7493             if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7494           }
7495         }
7496       }
7497     }
7498     // Save it
7499     will_dirty[i]=will_dirty_i;
7500     wont_dirty[i]=wont_dirty_i;
7501     // Mark registers that won't be dirtied as not dirty
7502     if(wr) {
7503       /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7504       for(r=0;r<HOST_REGS;r++) {
7505         if((will_dirty_i>>r)&1) {
7506           printf(" r%d",r);
7507         }
7508       }
7509       printf("\n");*/
7510
7511       //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7512         regs[i].dirty|=will_dirty_i;
7513         #ifndef DESTRUCTIVE_WRITEBACK
7514         regs[i].dirty&=wont_dirty_i;
7515         if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7516         {
7517           if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7518             for(r=0;r<HOST_REGS;r++) {
7519               if(r!=EXCLUDE_REG) {
7520                 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7521                   regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7522                 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7523               }
7524             }
7525           }
7526         }
7527         else
7528         {
7529           if(i<iend) {
7530             for(r=0;r<HOST_REGS;r++) {
7531               if(r!=EXCLUDE_REG) {
7532                 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7533                   regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7534                 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7535               }
7536             }
7537           }
7538         }
7539         #endif
7540       //}
7541     }
7542     // Deal with changed mappings
7543     temp_will_dirty=will_dirty_i;
7544     temp_wont_dirty=wont_dirty_i;
7545     for(r=0;r<HOST_REGS;r++) {
7546       if(r!=EXCLUDE_REG) {
7547         int nr;
7548         if(regs[i].regmap[r]==regmap_pre[i][r]) {
7549           if(wr) {
7550             #ifndef DESTRUCTIVE_WRITEBACK
7551             regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7552             #endif
7553             regs[i].wasdirty|=will_dirty_i&(1<<r);
7554           }
7555         }
7556         else if((nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7557           // Register moved to a different register
7558           will_dirty_i&=~(1<<r);
7559           wont_dirty_i&=~(1<<r);
7560           will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7561           wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7562           if(wr) {
7563             #ifndef DESTRUCTIVE_WRITEBACK
7564             regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7565             #endif
7566             regs[i].wasdirty|=will_dirty_i&(1<<r);
7567           }
7568         }
7569         else {
7570           will_dirty_i&=~(1<<r);
7571           wont_dirty_i&=~(1<<r);
7572           if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7573             will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7574             wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7575           } else {
7576             wont_dirty_i|=1<<r;
7577             /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7578           }
7579         }
7580       }
7581     }
7582   }
7583 }
7584
7585   /* disassembly */
7586 void disassemble_inst(int i)
7587 {
7588     if (bt[i]) printf("*"); else printf(" ");
7589     switch(itype[i]) {
7590       case UJUMP:
7591         printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7592       case CJUMP:
7593         printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7594       case SJUMP:
7595         printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7596       case FJUMP:
7597         printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7598       case RJUMP:
7599         if (opcode[i]==0x9&&rt1[i]!=31)
7600           printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7601         else
7602           printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7603         break;
7604       case SPAN:
7605         printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7606       case IMM16:
7607         if(opcode[i]==0xf) //LUI
7608           printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7609         else
7610           printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7611         break;
7612       case LOAD:
7613       case LOADLR:
7614         printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7615         break;
7616       case STORE:
7617       case STORELR:
7618         printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7619         break;
7620       case ALU:
7621       case SHIFT:
7622         printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7623         break;
7624       case MULTDIV:
7625         printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7626         break;
7627       case SHIFTIMM:
7628         printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7629         break;
7630       case MOV:
7631         if((opcode2[i]&0x1d)==0x10)
7632           printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7633         else if((opcode2[i]&0x1d)==0x11)
7634           printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7635         else
7636           printf (" %x: %s\n",start+i*4,insn[i]);
7637         break;
7638       case COP0:
7639         if(opcode2[i]==0)
7640           printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7641         else if(opcode2[i]==4)
7642           printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7643         else printf (" %x: %s\n",start+i*4,insn[i]);
7644         break;
7645       case COP1:
7646         if(opcode2[i]<3)
7647           printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7648         else if(opcode2[i]>3)
7649           printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7650         else printf (" %x: %s\n",start+i*4,insn[i]);
7651         break;
7652       case COP2:
7653         if(opcode2[i]<3)
7654           printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7655         else if(opcode2[i]>3)
7656           printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7657         else printf (" %x: %s\n",start+i*4,insn[i]);
7658         break;
7659       case C1LS:
7660         printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7661         break;
7662       case C2LS:
7663         printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7664         break;
7665       case INTCALL:
7666         printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
7667         break;
7668       default:
7669         //printf (" %s %8x\n",insn[i],source[i]);
7670         printf (" %x: %s\n",start+i*4,insn[i]);
7671     }
7672 }
7673
7674 void new_dynarec_init()
7675 {
7676   printf("Init new dynarec\n");
7677   out=(u_char *)BASE_ADDR;
7678   if (mmap (out, 1<<TARGET_SIZE_2,
7679             PROT_READ | PROT_WRITE | PROT_EXEC,
7680             MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
7681             -1, 0) <= 0) {printf("mmap() failed\n");}
7682 #ifdef MUPEN64
7683   rdword=&readmem_dword;
7684   fake_pc.f.r.rs=&readmem_dword;
7685   fake_pc.f.r.rt=&readmem_dword;
7686   fake_pc.f.r.rd=&readmem_dword;
7687 #endif
7688   int n;
7689   for(n=0x80000;n<0x80800;n++)
7690     invalid_code[n]=1;
7691   for(n=0;n<65536;n++)
7692     hash_table[n][0]=hash_table[n][2]=-1;
7693   memset(mini_ht,-1,sizeof(mini_ht));
7694   memset(restore_candidate,0,sizeof(restore_candidate));
7695   copy=shadow;
7696   expirep=16384; // Expiry pointer, +2 blocks
7697   pending_exception=0;
7698   literalcount=0;
7699 #ifdef HOST_IMM8
7700   // Copy this into local area so we don't have to put it in every literal pool
7701   invc_ptr=invalid_code;
7702 #endif
7703   stop_after_jal=0;
7704   // TLB
7705   using_tlb=0;
7706   for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7707     memory_map[n]=-1;
7708   for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7709     memory_map[n]=((u_int)rdram-0x80000000)>>2;
7710   for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7711     memory_map[n]=-1;
7712 #ifdef MUPEN64
7713   for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
7714     writemem[n] = write_nomem_new;
7715     writememb[n] = write_nomemb_new;
7716     writememh[n] = write_nomemh_new;
7717 #ifndef FORCE32
7718     writememd[n] = write_nomemd_new;
7719 #endif
7720     readmem[n] = read_nomem_new;
7721     readmemb[n] = read_nomemb_new;
7722     readmemh[n] = read_nomemh_new;
7723 #ifndef FORCE32
7724     readmemd[n] = read_nomemd_new;
7725 #endif
7726   }
7727   for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
7728     writemem[n] = write_rdram_new;
7729     writememb[n] = write_rdramb_new;
7730     writememh[n] = write_rdramh_new;
7731 #ifndef FORCE32
7732     writememd[n] = write_rdramd_new;
7733 #endif
7734   }
7735   for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
7736     writemem[n] = write_nomem_new;
7737     writememb[n] = write_nomemb_new;
7738     writememh[n] = write_nomemh_new;
7739 #ifndef FORCE32
7740     writememd[n] = write_nomemd_new;
7741 #endif
7742     readmem[n] = read_nomem_new;
7743     readmemb[n] = read_nomemb_new;
7744     readmemh[n] = read_nomemh_new;
7745 #ifndef FORCE32
7746     readmemd[n] = read_nomemd_new;
7747 #endif
7748   }
7749 #endif
7750   tlb_hacks();
7751   arch_init();
7752 }
7753
7754 void new_dynarec_cleanup()
7755 {
7756   int n;
7757   if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
7758   for(n=0;n<4096;n++) ll_clear(jump_in+n);
7759   for(n=0;n<4096;n++) ll_clear(jump_out+n);
7760   for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7761   #ifdef ROM_COPY
7762   if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
7763   #endif
7764 }
7765
7766 int new_recompile_block(int addr)
7767 {
7768 /*
7769   if(addr==0x800cd050) {
7770     int block;
7771     for(block=0x80000;block<0x80800;block++) invalidate_block(block);
7772     int n;
7773     for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
7774   }
7775 */
7776   //if(Count==365117028) tracedebug=1;
7777   assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7778   //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7779   //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
7780   //if(debug)
7781   //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
7782   //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
7783   /*if(Count>=312978186) {
7784     rlist();
7785   }*/
7786   //rlist();
7787   start = (u_int)addr&~3;
7788   //assert(((u_int)addr&1)==0);
7789 #ifdef PCSX
7790   if (Config.HLE && start == 0x80001000) // hlecall
7791   {
7792     // XXX: is this enough? Maybe check hleSoftCall?
7793     u_int beginning=(u_int)out;
7794     u_int page=get_page(start);
7795     invalid_code[start>>12]=0;
7796     emit_movimm(start,0);
7797     emit_writeword(0,(int)&pcaddr);
7798     emit_jmp((int)new_dyna_leave);
7799 #ifdef __arm__
7800     __clear_cache((void *)beginning,out);
7801 #endif
7802     ll_add(jump_in+page,start,(void *)beginning);
7803     return 0;
7804   }
7805   else if ((u_int)addr < 0x00200000 ||
7806     (0xa0000000 <= addr && addr < 0xa0200000)) {
7807     // used for BIOS calls mostly?
7808     source = (u_int *)((u_int)rdram+(start&0x1fffff));
7809     pagelimit = (addr&0xa0000000)|0x00200000;
7810   }
7811   else if (!Config.HLE && (
7812 /*    (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
7813     (0xbfc00000 <= addr && addr < 0xbfc80000))) {
7814     // BIOS
7815     source = (u_int *)((u_int)psxR+(start&0x7ffff));
7816     pagelimit = (addr&0xfff00000)|0x80000;
7817   }
7818   else
7819 #endif
7820 #ifdef MUPEN64
7821   if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
7822     source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
7823     pagelimit = 0xa4001000;
7824   }
7825   else
7826 #endif
7827   if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
7828     source = (u_int *)((u_int)rdram+start-0x80000000);
7829     pagelimit = 0x80000000+RAM_SIZE;
7830   }
7831 #ifndef DISABLE_TLB
7832   else if ((signed int)addr >= (signed int)0xC0000000) {
7833     //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
7834     //if(tlb_LUT_r[start>>12])
7835       //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
7836     if((signed int)memory_map[start>>12]>=0) {
7837       source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
7838       pagelimit=(start+4096)&0xFFFFF000;
7839       int map=memory_map[start>>12];
7840       int i;
7841       for(i=0;i<5;i++) {
7842         //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
7843         if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
7844       }
7845       assem_debug("pagelimit=%x\n",pagelimit);
7846       assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
7847     }
7848     else {
7849       assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
7850       //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
7851       return -1; // Caller will invoke exception handler
7852     }
7853     //printf("source= %x\n",(int)source);
7854   }
7855 #endif
7856   else {
7857     printf("Compile at bogus memory address: %x \n", (int)addr);
7858     exit(1);
7859   }
7860
7861   /* Pass 1: disassemble */
7862   /* Pass 2: register dependencies, branch targets */
7863   /* Pass 3: register allocation */
7864   /* Pass 4: branch dependencies */
7865   /* Pass 5: pre-alloc */
7866   /* Pass 6: optimize clean/dirty state */
7867   /* Pass 7: flag 32-bit registers */
7868   /* Pass 8: assembly */
7869   /* Pass 9: linker */
7870   /* Pass 10: garbage collection / free memory */
7871
7872   int i,j;
7873   int done=0;
7874   unsigned int type,op,op2;
7875
7876   //printf("addr = %x source = %x %x\n", addr,source,source[0]);
7877
7878   /* Pass 1 disassembly */
7879
7880   for(i=0;!done;i++) {
7881     bt[i]=0;likely[i]=0;op2=0;
7882     opcode[i]=op=source[i]>>26;
7883     switch(op)
7884     {
7885       case 0x00: strcpy(insn[i],"special"); type=NI;
7886         op2=source[i]&0x3f;
7887         switch(op2)
7888         {
7889           case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
7890           case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
7891           case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
7892           case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
7893           case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
7894           case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
7895           case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
7896           case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
7897           case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
7898           case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
7899           case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
7900           case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
7901           case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
7902           case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
7903           case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
7904           case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
7905           case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
7906           case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
7907           case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
7908           case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
7909           case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
7910           case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
7911           case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
7912           case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
7913           case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
7914           case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
7915           case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
7916           case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
7917           case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
7918           case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
7919           case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
7920           case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
7921           case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
7922           case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
7923           case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
7924           case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
7925           case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
7926           case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
7927           case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
7928           case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
7929           case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
7930           case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
7931           case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
7932           case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
7933           case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
7934           case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
7935           case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
7936           case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
7937           case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
7938           case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
7939           case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
7940           case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
7941         }
7942         break;
7943       case 0x01: strcpy(insn[i],"regimm"); type=NI;
7944         op2=(source[i]>>16)&0x1f;
7945         switch(op2)
7946         {
7947           case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
7948           case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
7949           case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
7950           case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
7951           case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
7952           case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
7953           case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
7954           case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
7955           case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
7956           case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
7957           case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
7958           case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
7959           case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
7960           case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
7961         }
7962         break;
7963       case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
7964       case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
7965       case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
7966       case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
7967       case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
7968       case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
7969       case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
7970       case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
7971       case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
7972       case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
7973       case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
7974       case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
7975       case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
7976       case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
7977       case 0x10: strcpy(insn[i],"cop0"); type=NI;
7978         op2=(source[i]>>21)&0x1f;
7979         switch(op2)
7980         {
7981           case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
7982           case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
7983           case 0x10: strcpy(insn[i],"tlb"); type=NI;
7984           switch(source[i]&0x3f)
7985           {
7986             case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
7987             case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
7988             case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
7989             case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
7990 #ifdef PCSX
7991             case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
7992 #else
7993             case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
7994 #endif
7995           }
7996         }
7997         break;
7998       case 0x11: strcpy(insn[i],"cop1"); type=NI;
7999         op2=(source[i]>>21)&0x1f;
8000         switch(op2)
8001         {
8002           case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
8003           case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
8004           case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
8005           case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
8006           case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
8007           case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
8008           case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
8009           switch((source[i]>>16)&0x3)
8010           {
8011             case 0x00: strcpy(insn[i],"BC1F"); break;
8012             case 0x01: strcpy(insn[i],"BC1T"); break;
8013             case 0x02: strcpy(insn[i],"BC1FL"); break;
8014             case 0x03: strcpy(insn[i],"BC1TL"); break;
8015           }
8016           break;
8017           case 0x10: strcpy(insn[i],"C1.S"); type=NI;
8018           switch(source[i]&0x3f)
8019           {
8020             case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
8021             case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
8022             case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
8023             case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
8024             case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
8025             case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
8026             case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
8027             case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
8028             case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
8029             case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
8030             case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
8031             case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
8032             case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
8033             case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
8034             case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
8035             case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
8036             case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
8037             case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
8038             case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
8039             case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
8040             case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
8041             case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
8042             case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
8043             case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
8044             case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
8045             case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
8046             case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
8047             case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
8048             case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
8049             case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
8050             case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
8051             case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
8052             case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
8053             case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
8054             case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
8055           }
8056           break;
8057           case 0x11: strcpy(insn[i],"C1.D"); type=NI;
8058           switch(source[i]&0x3f)
8059           {
8060             case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
8061             case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
8062             case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
8063             case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
8064             case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
8065             case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
8066             case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
8067             case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
8068             case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
8069             case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
8070             case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
8071             case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
8072             case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
8073             case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
8074             case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
8075             case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
8076             case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
8077             case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
8078             case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
8079             case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
8080             case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
8081             case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
8082             case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
8083             case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
8084             case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
8085             case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
8086             case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
8087             case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
8088             case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
8089             case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
8090             case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8091             case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8092             case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8093             case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8094             case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8095           }
8096           break;
8097           case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8098           switch(source[i]&0x3f)
8099           {
8100             case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8101             case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8102           }
8103           break;
8104           case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8105           switch(source[i]&0x3f)
8106           {
8107             case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8108             case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8109           }
8110           break;
8111         }
8112         break;
8113 #ifndef FORCE32
8114       case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8115       case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8116       case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8117       case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8118       case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8119       case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8120       case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8121       case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
8122 #endif
8123       case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8124       case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8125       case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8126       case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8127       case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8128       case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8129       case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
8130       case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
8131       case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8132       case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8133       case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8134       case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
8135 #ifndef FORCE32
8136       case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8137       case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
8138 #endif
8139       case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8140       case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8141       case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8142       case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
8143 #ifndef FORCE32
8144       case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8145       case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8146       case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
8147 #endif
8148       case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8149       case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
8150 #ifndef FORCE32
8151       case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8152       case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8153       case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
8154 #endif
8155 #ifdef PCSX
8156       case 0x12: strcpy(insn[i],"COP2"); type=NI;
8157         // note: COP MIPS-1 encoding differs from MIPS32
8158         op2=(source[i]>>21)&0x1f;
8159         if (source[i]&0x3f) {
8160           if (gte_handlers[source[i]&0x3f]!=NULL) {
8161             snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8162             type=C2OP;
8163           }
8164         }
8165         else switch(op2)
8166         {
8167           case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8168           case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8169           case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8170           case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
8171         }
8172         break;
8173       case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8174       case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8175       case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8176 #endif
8177       default: strcpy(insn[i],"???"); type=NI;
8178         printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
8179         break;
8180     }
8181 #ifdef PCSX
8182     /* detect branch in delay slot early */
8183     if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
8184       opcode[i+1]=source[i+1]>>26;
8185       opcode2[i+1]=source[i+1]&0x3f;
8186       if((0<opcode[i+1]&&opcode[i+1]<8)||(opcode[i+1]==0&&(opcode2[i+1]==8||opcode2[i+1]==9))) {
8187         printf("branch in delay slot @%08x (%08x)\n", addr + i*4+4, addr);
8188         // don't handle first branch and call interpreter if it's hit
8189         type=INTCALL;
8190       }
8191     }
8192 #endif
8193     itype[i]=type;
8194     opcode2[i]=op2;
8195     /* Get registers/immediates */
8196     lt1[i]=0;
8197     us1[i]=0;
8198     us2[i]=0;
8199     dep1[i]=0;
8200     dep2[i]=0;
8201     switch(type) {
8202       case LOAD:
8203         rs1[i]=(source[i]>>21)&0x1f;
8204         rs2[i]=0;
8205         rt1[i]=(source[i]>>16)&0x1f;
8206         rt2[i]=0;
8207         imm[i]=(short)source[i];
8208         break;
8209       case STORE:
8210       case STORELR:
8211         rs1[i]=(source[i]>>21)&0x1f;
8212         rs2[i]=(source[i]>>16)&0x1f;
8213         rt1[i]=0;
8214         rt2[i]=0;
8215         imm[i]=(short)source[i];
8216         if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8217         break;
8218       case LOADLR:
8219         // LWL/LWR only load part of the register,
8220         // therefore the target register must be treated as a source too
8221         rs1[i]=(source[i]>>21)&0x1f;
8222         rs2[i]=(source[i]>>16)&0x1f;
8223         rt1[i]=(source[i]>>16)&0x1f;
8224         rt2[i]=0;
8225         imm[i]=(short)source[i];
8226         if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8227         if(op==0x26) dep1[i]=rt1[i]; // LWR
8228         break;
8229       case IMM16:
8230         if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8231         else rs1[i]=(source[i]>>21)&0x1f;
8232         rs2[i]=0;
8233         rt1[i]=(source[i]>>16)&0x1f;
8234         rt2[i]=0;
8235         if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8236           imm[i]=(unsigned short)source[i];
8237         }else{
8238           imm[i]=(short)source[i];
8239         }
8240         if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8241         if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8242         if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8243         break;
8244       case UJUMP:
8245         rs1[i]=0;
8246         rs2[i]=0;
8247         rt1[i]=0;
8248         rt2[i]=0;
8249         // The JAL instruction writes to r31.
8250         if (op&1) {
8251           rt1[i]=31;
8252         }
8253         rs2[i]=CCREG;
8254         break;
8255       case RJUMP:
8256         rs1[i]=(source[i]>>21)&0x1f;
8257         rs2[i]=0;
8258         rt1[i]=0;
8259         rt2[i]=0;
8260         // The JALR instruction writes to rd.
8261         if (op2&1) {
8262           rt1[i]=(source[i]>>11)&0x1f;
8263         }
8264         rs2[i]=CCREG;
8265         break;
8266       case CJUMP:
8267         rs1[i]=(source[i]>>21)&0x1f;
8268         rs2[i]=(source[i]>>16)&0x1f;
8269         rt1[i]=0;
8270         rt2[i]=0;
8271         if(op&2) { // BGTZ/BLEZ
8272           rs2[i]=0;
8273         }
8274         us1[i]=rs1[i];
8275         us2[i]=rs2[i];
8276         likely[i]=op>>4;
8277         break;
8278       case SJUMP:
8279         rs1[i]=(source[i]>>21)&0x1f;
8280         rs2[i]=CCREG;
8281         rt1[i]=0;
8282         rt2[i]=0;
8283         us1[i]=rs1[i];
8284         if(op2&0x10) { // BxxAL
8285           rt1[i]=31;
8286           // NOTE: If the branch is not taken, r31 is still overwritten
8287         }
8288         likely[i]=(op2&2)>>1;
8289         break;
8290       case FJUMP:
8291         rs1[i]=FSREG;
8292         rs2[i]=CSREG;
8293         rt1[i]=0;
8294         rt2[i]=0;
8295         likely[i]=((source[i])>>17)&1;
8296         break;
8297       case ALU:
8298         rs1[i]=(source[i]>>21)&0x1f; // source
8299         rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8300         rt1[i]=(source[i]>>11)&0x1f; // destination
8301         rt2[i]=0;
8302         if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8303           us1[i]=rs1[i];us2[i]=rs2[i];
8304         }
8305         else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8306           dep1[i]=rs1[i];dep2[i]=rs2[i];
8307         }
8308         else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8309           dep1[i]=rs1[i];dep2[i]=rs2[i];
8310         }
8311         break;
8312       case MULTDIV:
8313         rs1[i]=(source[i]>>21)&0x1f; // source
8314         rs2[i]=(source[i]>>16)&0x1f; // divisor
8315         rt1[i]=HIREG;
8316         rt2[i]=LOREG;
8317         if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8318           us1[i]=rs1[i];us2[i]=rs2[i];
8319         }
8320         break;
8321       case MOV:
8322         rs1[i]=0;
8323         rs2[i]=0;
8324         rt1[i]=0;
8325         rt2[i]=0;
8326         if(op2==0x10) rs1[i]=HIREG; // MFHI
8327         if(op2==0x11) rt1[i]=HIREG; // MTHI
8328         if(op2==0x12) rs1[i]=LOREG; // MFLO
8329         if(op2==0x13) rt1[i]=LOREG; // MTLO
8330         if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8331         if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8332         dep1[i]=rs1[i];
8333         break;
8334       case SHIFT:
8335         rs1[i]=(source[i]>>16)&0x1f; // target of shift
8336         rs2[i]=(source[i]>>21)&0x1f; // shift amount
8337         rt1[i]=(source[i]>>11)&0x1f; // destination
8338         rt2[i]=0;
8339         // DSLLV/DSRLV/DSRAV are 64-bit
8340         if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8341         break;
8342       case SHIFTIMM:
8343         rs1[i]=(source[i]>>16)&0x1f;
8344         rs2[i]=0;
8345         rt1[i]=(source[i]>>11)&0x1f;
8346         rt2[i]=0;
8347         imm[i]=(source[i]>>6)&0x1f;
8348         // DSxx32 instructions
8349         if(op2>=0x3c) imm[i]|=0x20;
8350         // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8351         if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8352         break;
8353       case COP0:
8354         rs1[i]=0;
8355         rs2[i]=0;
8356         rt1[i]=0;
8357         rt2[i]=0;
8358         if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8359         if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8360         if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8361         if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8362         break;
8363       case COP1:
8364       case COP2:
8365         rs1[i]=0;
8366         rs2[i]=0;
8367         rt1[i]=0;
8368         rt2[i]=0;
8369         if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8370         if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8371         if(op2==5) us1[i]=rs1[i]; // DMTC1
8372         rs2[i]=CSREG;
8373         break;
8374       case C1LS:
8375         rs1[i]=(source[i]>>21)&0x1F;
8376         rs2[i]=CSREG;
8377         rt1[i]=0;
8378         rt2[i]=0;
8379         imm[i]=(short)source[i];
8380         break;
8381       case C2LS:
8382         rs1[i]=(source[i]>>21)&0x1F;
8383         rs2[i]=0;
8384         rt1[i]=0;
8385         rt2[i]=0;
8386         imm[i]=(short)source[i];
8387         break;
8388       case FLOAT:
8389       case FCONV:
8390         rs1[i]=0;
8391         rs2[i]=CSREG;
8392         rt1[i]=0;
8393         rt2[i]=0;
8394         break;
8395       case FCOMP:
8396         rs1[i]=FSREG;
8397         rs2[i]=CSREG;
8398         rt1[i]=FSREG;
8399         rt2[i]=0;
8400         break;
8401       case SYSCALL:
8402       case HLECALL:
8403       case INTCALL:
8404         rs1[i]=CCREG;
8405         rs2[i]=0;
8406         rt1[i]=0;
8407         rt2[i]=0;
8408         break;
8409       default:
8410         rs1[i]=0;
8411         rs2[i]=0;
8412         rt1[i]=0;
8413         rt2[i]=0;
8414     }
8415     /* Calculate branch target addresses */
8416     if(type==UJUMP)
8417       ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8418     else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8419       ba[i]=start+i*4+8; // Ignore never taken branch
8420     else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8421       ba[i]=start+i*4+8; // Ignore never taken branch
8422     else if(type==CJUMP||type==SJUMP||type==FJUMP)
8423       ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8424     else ba[i]=-1;
8425     /* Is this the end of the block? */
8426     if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
8427 #ifdef PCSX
8428       // check for link register access in delay slot
8429       int rt1_=rt1[i-1];
8430       if(rt1_!=0&&(rs1[i]==rt1_||rs2[i]==rt1_||rt1[i]==rt1_||rt2[i]==rt1_)) {
8431         printf("link access in delay slot @%08x (%08x)\n", addr + i*4, addr);
8432         ba[i-1]=-1;
8433         itype[i-1]=INTCALL;
8434         done=2;
8435       }
8436       else
8437 #endif
8438       if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
8439         done=2;
8440       }
8441       else {
8442         if(stop_after_jal) done=1;
8443         // Stop on BREAK
8444         if((source[i+1]&0xfc00003f)==0x0d) done=1;
8445       }
8446       // Don't recompile stuff that's already compiled
8447       if(check_addr(start+i*4+4)) done=1;
8448       // Don't get too close to the limit
8449       if(i>MAXBLOCK/2) done=1;
8450     }
8451     if(itype[i]==SYSCALL&&stop_after_jal) done=1;
8452     if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
8453     if(done==2) {
8454       // Does the block continue due to a branch?
8455       for(j=i-1;j>=0;j--)
8456       {
8457         if(ba[j]==start+i*4+4) done=j=0;
8458         if(ba[j]==start+i*4+8) done=j=0;
8459       }
8460     }
8461     //assert(i<MAXBLOCK-1);
8462     if(start+i*4==pagelimit-4) done=1;
8463     assert(start+i*4<pagelimit);
8464     if (i==MAXBLOCK-1) done=1;
8465     // Stop if we're compiling junk
8466     if(itype[i]==NI&&opcode[i]==0x11) {
8467       done=stop_after_jal=1;
8468       printf("Disabled speculative precompilation\n");
8469     }
8470   }
8471   slen=i;
8472   if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8473     if(start+i*4==pagelimit) {
8474       itype[i-1]=SPAN;
8475     }
8476   }
8477   assert(slen>0);
8478
8479   /* Pass 2 - Register dependencies and branch targets */
8480
8481   unneeded_registers(0,slen-1,0);
8482
8483   /* Pass 3 - Register allocation */
8484
8485   struct regstat current; // Current register allocations/status
8486   current.is32=1;
8487   current.dirty=0;
8488   current.u=unneeded_reg[0];
8489   current.uu=unneeded_reg_upper[0];
8490   clear_all_regs(current.regmap);
8491   alloc_reg(&current,0,CCREG);
8492   dirty_reg(&current,CCREG);
8493   current.isconst=0;
8494   current.wasconst=0;
8495   int ds=0;
8496   int cc=0;
8497   int hr;
8498
8499 #ifndef FORCE32
8500   provisional_32bit();
8501 #endif
8502   if((u_int)addr&1) {
8503     // First instruction is delay slot
8504     cc=-1;
8505     bt[1]=1;
8506     ds=1;
8507     unneeded_reg[0]=1;
8508     unneeded_reg_upper[0]=1;
8509     current.regmap[HOST_BTREG]=BTREG;
8510   }
8511
8512   for(i=0;i<slen;i++)
8513   {
8514     if(bt[i])
8515     {
8516       int hr;
8517       for(hr=0;hr<HOST_REGS;hr++)
8518       {
8519         // Is this really necessary?
8520         if(current.regmap[hr]==0) current.regmap[hr]=-1;
8521       }
8522       current.isconst=0;
8523     }
8524     if(i>1)
8525     {
8526       if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8527       {
8528         if(rs1[i-2]==0||rs2[i-2]==0)
8529         {
8530           if(rs1[i-2]) {
8531             current.is32|=1LL<<rs1[i-2];
8532             int hr=get_reg(current.regmap,rs1[i-2]|64);
8533             if(hr>=0) current.regmap[hr]=-1;
8534           }
8535           if(rs2[i-2]) {
8536             current.is32|=1LL<<rs2[i-2];
8537             int hr=get_reg(current.regmap,rs2[i-2]|64);
8538             if(hr>=0) current.regmap[hr]=-1;
8539           }
8540         }
8541       }
8542     }
8543 #ifndef FORCE32
8544     // If something jumps here with 64-bit values
8545     // then promote those registers to 64 bits
8546     if(bt[i])
8547     {
8548       uint64_t temp_is32=current.is32;
8549       for(j=i-1;j>=0;j--)
8550       {
8551         if(ba[j]==start+i*4)
8552           temp_is32&=branch_regs[j].is32;
8553       }
8554       for(j=i;j<slen;j++)
8555       {
8556         if(ba[j]==start+i*4)
8557           //temp_is32=1;
8558           temp_is32&=p32[j];
8559       }
8560       if(temp_is32!=current.is32) {
8561         //printf("dumping 32-bit regs (%x)\n",start+i*4);
8562         #ifdef DESTRUCTIVE_WRITEBACK
8563         for(hr=0;hr<HOST_REGS;hr++)
8564         {
8565           int r=current.regmap[hr];
8566           if(r>0&&r<64)
8567           {
8568             if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8569               temp_is32|=1LL<<r;
8570               //printf("restore %d\n",r);
8571             }
8572           }
8573         }
8574         #endif
8575         current.is32=temp_is32;
8576       }
8577     }
8578 #else
8579     current.is32=-1LL;
8580 #endif
8581
8582     memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8583     regs[i].wasconst=current.isconst;
8584     regs[i].was32=current.is32;
8585     regs[i].wasdirty=current.dirty;
8586     #if defined(DESTRUCTIVE_WRITEBACK) && !defined(FORCE32)
8587     // To change a dirty register from 32 to 64 bits, we must write
8588     // it out during the previous cycle (for branches, 2 cycles)
8589     if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8590     {
8591       uint64_t temp_is32=current.is32;
8592       for(j=i-1;j>=0;j--)
8593       {
8594         if(ba[j]==start+i*4+4)
8595           temp_is32&=branch_regs[j].is32;
8596       }
8597       for(j=i;j<slen;j++)
8598       {
8599         if(ba[j]==start+i*4+4)
8600           //temp_is32=1;
8601           temp_is32&=p32[j];
8602       }
8603       if(temp_is32!=current.is32) {
8604         //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8605         for(hr=0;hr<HOST_REGS;hr++)
8606         {
8607           int r=current.regmap[hr];
8608           if(r>0)
8609           {
8610             if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8611               if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
8612               {
8613                 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
8614                 {
8615                   //printf("dump %d/r%d\n",hr,r);
8616                   current.regmap[hr]=-1;
8617                   if(get_reg(current.regmap,r|64)>=0)
8618                     current.regmap[get_reg(current.regmap,r|64)]=-1;
8619                 }
8620               }
8621             }
8622           }
8623         }
8624       }
8625     }
8626     else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
8627     {
8628       uint64_t temp_is32=current.is32;
8629       for(j=i-1;j>=0;j--)
8630       {
8631         if(ba[j]==start+i*4+8)
8632           temp_is32&=branch_regs[j].is32;
8633       }
8634       for(j=i;j<slen;j++)
8635       {
8636         if(ba[j]==start+i*4+8)
8637           //temp_is32=1;
8638           temp_is32&=p32[j];
8639       }
8640       if(temp_is32!=current.is32) {
8641         //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8642         for(hr=0;hr<HOST_REGS;hr++)
8643         {
8644           int r=current.regmap[hr];
8645           if(r>0)
8646           {
8647             if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8648               if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
8649               {
8650                 //printf("dump %d/r%d\n",hr,r);
8651                 current.regmap[hr]=-1;
8652                 if(get_reg(current.regmap,r|64)>=0)
8653                   current.regmap[get_reg(current.regmap,r|64)]=-1;
8654               }
8655             }
8656           }
8657         }
8658       }
8659     }
8660     #endif
8661     if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8662       if(i+1<slen) {
8663         current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8664         current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8665         if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8666         current.u|=1;
8667         current.uu|=1;
8668       } else {
8669         current.u=1;
8670         current.uu=1;
8671       }
8672     } else {
8673       if(i+1<slen) {
8674         current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
8675         current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8676         if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8677         current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8678         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8679         current.u|=1;
8680         current.uu|=1;
8681       } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
8682     }
8683     is_ds[i]=ds;
8684     if(ds) {
8685       ds=0; // Skip delay slot, already allocated as part of branch
8686       // ...but we need to alloc it in case something jumps here
8687       if(i+1<slen) {
8688         current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
8689         current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
8690       }else{
8691         current.u=branch_unneeded_reg[i-1];
8692         current.uu=branch_unneeded_reg_upper[i-1];
8693       }
8694       current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8695       current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8696       if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8697       current.u|=1;
8698       current.uu|=1;
8699       struct regstat temp;
8700       memcpy(&temp,&current,sizeof(current));
8701       temp.wasdirty=temp.dirty;
8702       temp.was32=temp.is32;
8703       // TODO: Take into account unconditional branches, as below
8704       delayslot_alloc(&temp,i);
8705       memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
8706       regs[i].wasdirty=temp.wasdirty;
8707       regs[i].was32=temp.was32;
8708       regs[i].dirty=temp.dirty;
8709       regs[i].is32=temp.is32;
8710       regs[i].isconst=0;
8711       regs[i].wasconst=0;
8712       current.isconst=0;
8713       // Create entry (branch target) regmap
8714       for(hr=0;hr<HOST_REGS;hr++)
8715       {
8716         int r=temp.regmap[hr];
8717         if(r>=0) {
8718           if(r!=regmap_pre[i][hr]) {
8719             regs[i].regmap_entry[hr]=-1;
8720           }
8721           else
8722           {
8723             if(r<64){
8724               if((current.u>>r)&1) {
8725                 regs[i].regmap_entry[hr]=-1;
8726                 regs[i].regmap[hr]=-1;
8727                 //Don't clear regs in the delay slot as the branch might need them
8728                 //current.regmap[hr]=-1;
8729               }else
8730                 regs[i].regmap_entry[hr]=r;
8731             }
8732             else {
8733               if((current.uu>>(r&63))&1) {
8734                 regs[i].regmap_entry[hr]=-1;
8735                 regs[i].regmap[hr]=-1;
8736                 //Don't clear regs in the delay slot as the branch might need them
8737                 //current.regmap[hr]=-1;
8738               }else
8739                 regs[i].regmap_entry[hr]=r;
8740             }
8741           }
8742         } else {
8743           // First instruction expects CCREG to be allocated
8744           if(i==0&&hr==HOST_CCREG)
8745             regs[i].regmap_entry[hr]=CCREG;
8746           else
8747             regs[i].regmap_entry[hr]=-1;
8748         }
8749       }
8750     }
8751     else { // Not delay slot
8752       switch(itype[i]) {
8753         case UJUMP:
8754           //current.isconst=0; // DEBUG
8755           //current.wasconst=0; // DEBUG
8756           //regs[i].wasconst=0; // DEBUG
8757           clear_const(&current,rt1[i]);
8758           alloc_cc(&current,i);
8759           dirty_reg(&current,CCREG);
8760           if (rt1[i]==31) {
8761             alloc_reg(&current,i,31);
8762             dirty_reg(&current,31);
8763             assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8764             assert(rt1[i+1]!=rt1[i]);
8765             #ifdef REG_PREFETCH
8766             alloc_reg(&current,i,PTEMP);
8767             #endif
8768             //current.is32|=1LL<<rt1[i];
8769           }
8770           delayslot_alloc(&current,i+1);
8771           //current.isconst=0; // DEBUG
8772           ds=1;
8773           //printf("i=%d, isconst=%x\n",i,current.isconst);
8774           break;
8775         case RJUMP:
8776           //current.isconst=0;
8777           //current.wasconst=0;
8778           //regs[i].wasconst=0;
8779           clear_const(&current,rs1[i]);
8780           clear_const(&current,rt1[i]);
8781           alloc_cc(&current,i);
8782           dirty_reg(&current,CCREG);
8783           if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
8784             alloc_reg(&current,i,rs1[i]);
8785             if (rt1[i]!=0) {
8786               alloc_reg(&current,i,rt1[i]);
8787               dirty_reg(&current,rt1[i]);
8788               assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
8789               assert(rt1[i+1]!=rt1[i]);
8790               #ifdef REG_PREFETCH
8791               alloc_reg(&current,i,PTEMP);
8792               #endif
8793             }
8794             #ifdef USE_MINI_HT
8795             if(rs1[i]==31) { // JALR
8796               alloc_reg(&current,i,RHASH);
8797               #ifndef HOST_IMM_ADDR32
8798               alloc_reg(&current,i,RHTBL);
8799               #endif
8800             }
8801             #endif
8802             delayslot_alloc(&current,i+1);
8803           } else {
8804             // The delay slot overwrites our source register,
8805             // allocate a temporary register to hold the old value.
8806             current.isconst=0;
8807             current.wasconst=0;
8808             regs[i].wasconst=0;
8809             delayslot_alloc(&current,i+1);
8810             current.isconst=0;
8811             alloc_reg(&current,i,RTEMP);
8812           }
8813           //current.isconst=0; // DEBUG
8814           ds=1;
8815           break;
8816         case CJUMP:
8817           //current.isconst=0;
8818           //current.wasconst=0;
8819           //regs[i].wasconst=0;
8820           clear_const(&current,rs1[i]);
8821           clear_const(&current,rs2[i]);
8822           if((opcode[i]&0x3E)==4) // BEQ/BNE
8823           {
8824             alloc_cc(&current,i);
8825             dirty_reg(&current,CCREG);
8826             if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8827             if(rs2[i]) alloc_reg(&current,i,rs2[i]);
8828             if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8829             {
8830               if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8831               if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
8832             }
8833             if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
8834                (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
8835               // The delay slot overwrites one of our conditions.
8836               // Allocate the branch condition registers instead.
8837               // Note that such a sequence of instructions could
8838               // be considered a bug since the branch can not be
8839               // re-executed if an exception occurs.
8840               current.isconst=0;
8841               current.wasconst=0;
8842               regs[i].wasconst=0;
8843               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8844               if(rs2[i]) alloc_reg(&current,i,rs2[i]);
8845               if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8846               {
8847                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8848                 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
8849               }
8850             }
8851             else delayslot_alloc(&current,i+1);
8852           }
8853           else
8854           if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
8855           {
8856             alloc_cc(&current,i);
8857             dirty_reg(&current,CCREG);
8858             alloc_reg(&current,i,rs1[i]);
8859             if(!(current.is32>>rs1[i]&1))
8860             {
8861               alloc_reg64(&current,i,rs1[i]);
8862             }
8863             if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
8864               // The delay slot overwrites one of our conditions.
8865               // Allocate the branch condition registers instead.
8866               // Note that such a sequence of instructions could
8867               // be considered a bug since the branch can not be
8868               // re-executed if an exception occurs.
8869               current.isconst=0;
8870               current.wasconst=0;
8871               regs[i].wasconst=0;
8872               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8873               if(!((current.is32>>rs1[i])&1))
8874               {
8875                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8876               }
8877             }
8878             else delayslot_alloc(&current,i+1);
8879           }
8880           else
8881           // Don't alloc the delay slot yet because we might not execute it
8882           if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
8883           {
8884             current.isconst=0;
8885             current.wasconst=0;
8886             regs[i].wasconst=0;
8887             alloc_cc(&current,i);
8888             dirty_reg(&current,CCREG);
8889             alloc_reg(&current,i,rs1[i]);
8890             alloc_reg(&current,i,rs2[i]);
8891             if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8892             {
8893               alloc_reg64(&current,i,rs1[i]);
8894               alloc_reg64(&current,i,rs2[i]);
8895             }
8896           }
8897           else
8898           if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
8899           {
8900             current.isconst=0;
8901             current.wasconst=0;
8902             regs[i].wasconst=0;
8903             alloc_cc(&current,i);
8904             dirty_reg(&current,CCREG);
8905             alloc_reg(&current,i,rs1[i]);
8906             if(!(current.is32>>rs1[i]&1))
8907             {
8908               alloc_reg64(&current,i,rs1[i]);
8909             }
8910           }
8911           ds=1;
8912           //current.isconst=0;
8913           break;
8914         case SJUMP:
8915           //current.isconst=0;
8916           //current.wasconst=0;
8917           //regs[i].wasconst=0;
8918           clear_const(&current,rs1[i]);
8919           clear_const(&current,rt1[i]);
8920           //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
8921           if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
8922           {
8923             alloc_cc(&current,i);
8924             dirty_reg(&current,CCREG);
8925             alloc_reg(&current,i,rs1[i]);
8926             if(!(current.is32>>rs1[i]&1))
8927             {
8928               alloc_reg64(&current,i,rs1[i]);
8929             }
8930             if (rt1[i]==31) { // BLTZAL/BGEZAL
8931               alloc_reg(&current,i,31);
8932               dirty_reg(&current,31);
8933               //#ifdef REG_PREFETCH
8934               //alloc_reg(&current,i,PTEMP);
8935               //#endif
8936               //current.is32|=1LL<<rt1[i];
8937             }
8938             if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
8939               // The delay slot overwrites the branch condition.
8940               // Allocate the branch condition registers instead.
8941               // Note that such a sequence of instructions could
8942               // be considered a bug since the branch can not be
8943               // re-executed if an exception occurs.
8944               current.isconst=0;
8945               current.wasconst=0;
8946               regs[i].wasconst=0;
8947               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8948               if(!((current.is32>>rs1[i])&1))
8949               {
8950                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8951               }
8952             }
8953             else delayslot_alloc(&current,i+1);
8954           }
8955           else
8956           // Don't alloc the delay slot yet because we might not execute it
8957           if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
8958           {
8959             current.isconst=0;
8960             current.wasconst=0;
8961             regs[i].wasconst=0;
8962             alloc_cc(&current,i);
8963             dirty_reg(&current,CCREG);
8964             alloc_reg(&current,i,rs1[i]);
8965             if(!(current.is32>>rs1[i]&1))
8966             {
8967               alloc_reg64(&current,i,rs1[i]);
8968             }
8969           }
8970           ds=1;
8971           //current.isconst=0;
8972           break;
8973         case FJUMP:
8974           current.isconst=0;
8975           current.wasconst=0;
8976           regs[i].wasconst=0;
8977           if(likely[i]==0) // BC1F/BC1T
8978           {
8979             // TODO: Theoretically we can run out of registers here on x86.
8980             // The delay slot can allocate up to six, and we need to check
8981             // CSREG before executing the delay slot.  Possibly we can drop
8982             // the cycle count and then reload it after checking that the
8983             // FPU is in a usable state, or don't do out-of-order execution.
8984             alloc_cc(&current,i);
8985             dirty_reg(&current,CCREG);
8986             alloc_reg(&current,i,FSREG);
8987             alloc_reg(&current,i,CSREG);
8988             if(itype[i+1]==FCOMP) {
8989               // The delay slot overwrites the branch condition.
8990               // Allocate the branch condition registers instead.
8991               // Note that such a sequence of instructions could
8992               // be considered a bug since the branch can not be
8993               // re-executed if an exception occurs.
8994               alloc_cc(&current,i);
8995               dirty_reg(&current,CCREG);
8996               alloc_reg(&current,i,CSREG);
8997               alloc_reg(&current,i,FSREG);
8998             }
8999             else {
9000               delayslot_alloc(&current,i+1);
9001               alloc_reg(&current,i+1,CSREG);
9002             }
9003           }
9004           else
9005           // Don't alloc the delay slot yet because we might not execute it
9006           if(likely[i]) // BC1FL/BC1TL
9007           {
9008             alloc_cc(&current,i);
9009             dirty_reg(&current,CCREG);
9010             alloc_reg(&current,i,CSREG);
9011             alloc_reg(&current,i,FSREG);
9012           }
9013           ds=1;
9014           current.isconst=0;
9015           break;
9016         case IMM16:
9017           imm16_alloc(&current,i);
9018           break;
9019         case LOAD:
9020         case LOADLR:
9021           load_alloc(&current,i);
9022           break;
9023         case STORE:
9024         case STORELR:
9025           store_alloc(&current,i);
9026           break;
9027         case ALU:
9028           alu_alloc(&current,i);
9029           break;
9030         case SHIFT:
9031           shift_alloc(&current,i);
9032           break;
9033         case MULTDIV:
9034           multdiv_alloc(&current,i);
9035           break;
9036         case SHIFTIMM:
9037           shiftimm_alloc(&current,i);
9038           break;
9039         case MOV:
9040           mov_alloc(&current,i);
9041           break;
9042         case COP0:
9043           cop0_alloc(&current,i);
9044           break;
9045         case COP1:
9046         case COP2:
9047           cop1_alloc(&current,i);
9048           break;
9049         case C1LS:
9050           c1ls_alloc(&current,i);
9051           break;
9052         case C2LS:
9053           c2ls_alloc(&current,i);
9054           break;
9055         case C2OP:
9056           c2op_alloc(&current,i);
9057           break;
9058         case FCONV:
9059           fconv_alloc(&current,i);
9060           break;
9061         case FLOAT:
9062           float_alloc(&current,i);
9063           break;
9064         case FCOMP:
9065           fcomp_alloc(&current,i);
9066           break;
9067         case SYSCALL:
9068         case HLECALL:
9069         case INTCALL:
9070           syscall_alloc(&current,i);
9071           break;
9072         case SPAN:
9073           pagespan_alloc(&current,i);
9074           break;
9075       }
9076
9077       // Drop the upper half of registers that have become 32-bit
9078       current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
9079       if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9080         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9081         if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9082         current.uu|=1;
9083       } else {
9084         current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
9085         current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9086         if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9087         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9088         current.uu|=1;
9089       }
9090
9091       // Create entry (branch target) regmap
9092       for(hr=0;hr<HOST_REGS;hr++)
9093       {
9094         int r,or,er;
9095         r=current.regmap[hr];
9096         if(r>=0) {
9097           if(r!=regmap_pre[i][hr]) {
9098             // TODO: delay slot (?)
9099             or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9100             if(or<0||(r&63)>=TEMPREG){
9101               regs[i].regmap_entry[hr]=-1;
9102             }
9103             else
9104             {
9105               // Just move it to a different register
9106               regs[i].regmap_entry[hr]=r;
9107               // If it was dirty before, it's still dirty
9108               if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r&63);
9109             }
9110           }
9111           else
9112           {
9113             // Unneeded
9114             if(r==0){
9115               regs[i].regmap_entry[hr]=0;
9116             }
9117             else
9118             if(r<64){
9119               if((current.u>>r)&1) {
9120                 regs[i].regmap_entry[hr]=-1;
9121                 //regs[i].regmap[hr]=-1;
9122                 current.regmap[hr]=-1;
9123               }else
9124                 regs[i].regmap_entry[hr]=r;
9125             }
9126             else {
9127               if((current.uu>>(r&63))&1) {
9128                 regs[i].regmap_entry[hr]=-1;
9129                 //regs[i].regmap[hr]=-1;
9130                 current.regmap[hr]=-1;
9131               }else
9132                 regs[i].regmap_entry[hr]=r;
9133             }
9134           }
9135         } else {
9136           // Branches expect CCREG to be allocated at the target
9137           if(regmap_pre[i][hr]==CCREG)
9138             regs[i].regmap_entry[hr]=CCREG;
9139           else
9140             regs[i].regmap_entry[hr]=-1;
9141         }
9142       }
9143       memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9144     }
9145     /* Branch post-alloc */
9146     if(i>0)
9147     {
9148       current.was32=current.is32;
9149       current.wasdirty=current.dirty;
9150       switch(itype[i-1]) {
9151         case UJUMP:
9152           memcpy(&branch_regs[i-1],&current,sizeof(current));
9153           branch_regs[i-1].isconst=0;
9154           branch_regs[i-1].wasconst=0;
9155           branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9156           branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9157           alloc_cc(&branch_regs[i-1],i-1);
9158           dirty_reg(&branch_regs[i-1],CCREG);
9159           if(rt1[i-1]==31) { // JAL
9160             alloc_reg(&branch_regs[i-1],i-1,31);
9161             dirty_reg(&branch_regs[i-1],31);
9162             branch_regs[i-1].is32|=1LL<<31;
9163           }
9164           memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9165           memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9166           break;
9167         case RJUMP:
9168           memcpy(&branch_regs[i-1],&current,sizeof(current));
9169           branch_regs[i-1].isconst=0;
9170           branch_regs[i-1].wasconst=0;
9171           branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9172           branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9173           alloc_cc(&branch_regs[i-1],i-1);
9174           dirty_reg(&branch_regs[i-1],CCREG);
9175           alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
9176           if(rt1[i-1]!=0) { // JALR
9177             alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9178             dirty_reg(&branch_regs[i-1],rt1[i-1]);
9179             branch_regs[i-1].is32|=1LL<<rt1[i-1];
9180           }
9181           #ifdef USE_MINI_HT
9182           if(rs1[i-1]==31) { // JALR
9183             alloc_reg(&branch_regs[i-1],i-1,RHASH);
9184             #ifndef HOST_IMM_ADDR32
9185             alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9186             #endif
9187           }
9188           #endif
9189           memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9190           memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9191           break;
9192         case CJUMP:
9193           if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9194           {
9195             alloc_cc(&current,i-1);
9196             dirty_reg(&current,CCREG);
9197             if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9198                (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9199               // The delay slot overwrote one of our conditions
9200               // Delay slot goes after the test (in order)
9201               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9202               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9203               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9204               current.u|=1;
9205               current.uu|=1;
9206               delayslot_alloc(&current,i);
9207               current.isconst=0;
9208             }
9209             else
9210             {
9211               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9212               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9213               // Alloc the branch condition registers
9214               if(rs1[i-1]) alloc_reg(&current,i-1,rs1[i-1]);
9215               if(rs2[i-1]) alloc_reg(&current,i-1,rs2[i-1]);
9216               if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9217               {
9218                 if(rs1[i-1]) alloc_reg64(&current,i-1,rs1[i-1]);
9219                 if(rs2[i-1]) alloc_reg64(&current,i-1,rs2[i-1]);
9220               }
9221             }
9222             memcpy(&branch_regs[i-1],&current,sizeof(current));
9223             branch_regs[i-1].isconst=0;
9224             branch_regs[i-1].wasconst=0;
9225             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9226             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9227           }
9228           else
9229           if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9230           {
9231             alloc_cc(&current,i-1);
9232             dirty_reg(&current,CCREG);
9233             if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9234               // The delay slot overwrote the branch condition
9235               // Delay slot goes after the test (in order)
9236               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9237               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9238               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9239               current.u|=1;
9240               current.uu|=1;
9241               delayslot_alloc(&current,i);
9242               current.isconst=0;
9243             }
9244             else
9245             {
9246               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9247               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9248               // Alloc the branch condition register
9249               alloc_reg(&current,i-1,rs1[i-1]);
9250               if(!(current.is32>>rs1[i-1]&1))
9251               {
9252                 alloc_reg64(&current,i-1,rs1[i-1]);
9253               }
9254             }
9255             memcpy(&branch_regs[i-1],&current,sizeof(current));
9256             branch_regs[i-1].isconst=0;
9257             branch_regs[i-1].wasconst=0;
9258             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9259             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9260           }
9261           else
9262           // Alloc the delay slot in case the branch is taken
9263           if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9264           {
9265             memcpy(&branch_regs[i-1],&current,sizeof(current));
9266             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9267             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9268             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9269             alloc_cc(&branch_regs[i-1],i);
9270             dirty_reg(&branch_regs[i-1],CCREG);
9271             delayslot_alloc(&branch_regs[i-1],i);
9272             branch_regs[i-1].isconst=0;
9273             alloc_reg(&current,i,CCREG); // Not taken path
9274             dirty_reg(&current,CCREG);
9275             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9276           }
9277           else
9278           if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9279           {
9280             memcpy(&branch_regs[i-1],&current,sizeof(current));
9281             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9282             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9283             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9284             alloc_cc(&branch_regs[i-1],i);
9285             dirty_reg(&branch_regs[i-1],CCREG);
9286             delayslot_alloc(&branch_regs[i-1],i);
9287             branch_regs[i-1].isconst=0;
9288             alloc_reg(&current,i,CCREG); // Not taken path
9289             dirty_reg(&current,CCREG);
9290             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9291           }
9292           break;
9293         case SJUMP:
9294           //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9295           if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9296           {
9297             alloc_cc(&current,i-1);
9298             dirty_reg(&current,CCREG);
9299             if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9300               // The delay slot overwrote the branch condition
9301               // Delay slot goes after the test (in order)
9302               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9303               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9304               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9305               current.u|=1;
9306               current.uu|=1;
9307               delayslot_alloc(&current,i);
9308               current.isconst=0;
9309             }
9310             else
9311             {
9312               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9313               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9314               // Alloc the branch condition register
9315               alloc_reg(&current,i-1,rs1[i-1]);
9316               if(!(current.is32>>rs1[i-1]&1))
9317               {
9318                 alloc_reg64(&current,i-1,rs1[i-1]);
9319               }
9320             }
9321             memcpy(&branch_regs[i-1],&current,sizeof(current));
9322             branch_regs[i-1].isconst=0;
9323             branch_regs[i-1].wasconst=0;
9324             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9325             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9326           }
9327           else
9328           // Alloc the delay slot in case the branch is taken
9329           if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9330           {
9331             memcpy(&branch_regs[i-1],&current,sizeof(current));
9332             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9333             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9334             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9335             alloc_cc(&branch_regs[i-1],i);
9336             dirty_reg(&branch_regs[i-1],CCREG);
9337             delayslot_alloc(&branch_regs[i-1],i);
9338             branch_regs[i-1].isconst=0;
9339             alloc_reg(&current,i,CCREG); // Not taken path
9340             dirty_reg(&current,CCREG);
9341             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9342           }
9343           // FIXME: BLTZAL/BGEZAL
9344           if(opcode2[i-1]&0x10) { // BxxZAL
9345             alloc_reg(&branch_regs[i-1],i-1,31);
9346             dirty_reg(&branch_regs[i-1],31);
9347             branch_regs[i-1].is32|=1LL<<31;
9348           }
9349           break;
9350         case FJUMP:
9351           if(likely[i-1]==0) // BC1F/BC1T
9352           {
9353             alloc_cc(&current,i-1);
9354             dirty_reg(&current,CCREG);
9355             if(itype[i]==FCOMP) {
9356               // The delay slot overwrote the branch condition
9357               // Delay slot goes after the test (in order)
9358               delayslot_alloc(&current,i);
9359               current.isconst=0;
9360             }
9361             else
9362             {
9363               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9364               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9365               // Alloc the branch condition register
9366               alloc_reg(&current,i-1,FSREG);
9367             }
9368             memcpy(&branch_regs[i-1],&current,sizeof(current));
9369             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9370           }
9371           else // BC1FL/BC1TL
9372           {
9373             // Alloc the delay slot in case the branch is taken
9374             memcpy(&branch_regs[i-1],&current,sizeof(current));
9375             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9376             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9377             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9378             alloc_cc(&branch_regs[i-1],i);
9379             dirty_reg(&branch_regs[i-1],CCREG);
9380             delayslot_alloc(&branch_regs[i-1],i);
9381             branch_regs[i-1].isconst=0;
9382             alloc_reg(&current,i,CCREG); // Not taken path
9383             dirty_reg(&current,CCREG);
9384             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9385           }
9386           break;
9387       }
9388
9389       if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9390       {
9391         if(rt1[i-1]==31) // JAL/JALR
9392         {
9393           // Subroutine call will return here, don't alloc any registers
9394           current.is32=1;
9395           current.dirty=0;
9396           clear_all_regs(current.regmap);
9397           alloc_reg(&current,i,CCREG);
9398           dirty_reg(&current,CCREG);
9399         }
9400         else if(i+1<slen)
9401         {
9402           // Internal branch will jump here, match registers to caller
9403           current.is32=0x3FFFFFFFFLL;
9404           current.dirty=0;
9405           clear_all_regs(current.regmap);
9406           alloc_reg(&current,i,CCREG);
9407           dirty_reg(&current,CCREG);
9408           for(j=i-1;j>=0;j--)
9409           {
9410             if(ba[j]==start+i*4+4) {
9411               memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9412               current.is32=branch_regs[j].is32;
9413               current.dirty=branch_regs[j].dirty;
9414               break;
9415             }
9416           }
9417           while(j>=0) {
9418             if(ba[j]==start+i*4+4) {
9419               for(hr=0;hr<HOST_REGS;hr++) {
9420                 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9421                   current.regmap[hr]=-1;
9422                 }
9423                 current.is32&=branch_regs[j].is32;
9424                 current.dirty&=branch_regs[j].dirty;
9425               }
9426             }
9427             j--;
9428           }
9429         }
9430       }
9431     }
9432
9433     // Count cycles in between branches
9434     ccadj[i]=cc;
9435     if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
9436     {
9437       cc=0;
9438     }
9439     else
9440     {
9441       cc++;
9442     }
9443
9444     flush_dirty_uppers(&current);
9445     if(!is_ds[i]) {
9446       regs[i].is32=current.is32;
9447       regs[i].dirty=current.dirty;
9448       regs[i].isconst=current.isconst;
9449       memcpy(constmap[i],current.constmap,sizeof(current.constmap));
9450     }
9451     for(hr=0;hr<HOST_REGS;hr++) {
9452       if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
9453         if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9454           regs[i].wasconst&=~(1<<hr);
9455         }
9456       }
9457     }
9458     if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9459   }
9460
9461   /* Pass 4 - Cull unused host registers */
9462
9463   uint64_t nr=0;
9464
9465   for (i=slen-1;i>=0;i--)
9466   {
9467     int hr;
9468     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9469     {
9470       if(ba[i]<start || ba[i]>=(start+slen*4))
9471       {
9472         // Branch out of this block, don't need anything
9473         nr=0;
9474       }
9475       else
9476       {
9477         // Internal branch
9478         // Need whatever matches the target
9479         nr=0;
9480         int t=(ba[i]-start)>>2;
9481         for(hr=0;hr<HOST_REGS;hr++)
9482         {
9483           if(regs[i].regmap_entry[hr]>=0) {
9484             if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9485           }
9486         }
9487       }
9488       // Conditional branch may need registers for following instructions
9489       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9490       {
9491         if(i<slen-2) {
9492           nr|=needed_reg[i+2];
9493           for(hr=0;hr<HOST_REGS;hr++)
9494           {
9495             if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9496             //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9497           }
9498         }
9499       }
9500       // Don't need stuff which is overwritten
9501       if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9502       if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9503       // Merge in delay slot
9504       for(hr=0;hr<HOST_REGS;hr++)
9505       {
9506         if(!likely[i]) {
9507           // These are overwritten unless the branch is "likely"
9508           // and the delay slot is nullified if not taken
9509           if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9510           if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9511         }
9512         if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9513         if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9514         if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9515         if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9516         if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9517         if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9518         if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9519         if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9520         if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9521           if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9522           if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9523         }
9524         if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9525           if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9526           if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9527         }
9528         if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
9529           if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9530           if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9531         }
9532       }
9533     }
9534     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
9535     {
9536       // SYSCALL instruction (software interrupt)
9537       nr=0;
9538     }
9539     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9540     {
9541       // ERET instruction (return from interrupt)
9542       nr=0;
9543     }
9544     else // Non-branch
9545     {
9546       if(i<slen-1) {
9547         for(hr=0;hr<HOST_REGS;hr++) {
9548           if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9549           if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9550           if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9551           if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9552         }
9553       }
9554     }
9555     for(hr=0;hr<HOST_REGS;hr++)
9556     {
9557       // Overwritten registers are not needed
9558       if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9559       if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9560       if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9561       // Source registers are needed
9562       if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9563       if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9564       if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9565       if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9566       if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9567       if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9568       if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9569       if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9570       if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9571         if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9572         if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9573       }
9574       if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
9575         if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9576         if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9577       }
9578       if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
9579         if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9580         if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9581       }
9582       // Don't store a register immediately after writing it,
9583       // may prevent dual-issue.
9584       // But do so if this is a branch target, otherwise we
9585       // might have to load the register before the branch.
9586       if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
9587         if((regmap_pre[i][hr]>0&&regmap_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
9588            (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
9589           if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9590           if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9591         }
9592         if((regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
9593            (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
9594           if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9595           if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9596         }
9597       }
9598     }
9599     // Cycle count is needed at branches.  Assume it is needed at the target too.
9600     if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
9601       if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9602       if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9603     }
9604     // Save it
9605     needed_reg[i]=nr;
9606
9607     // Deallocate unneeded registers
9608     for(hr=0;hr<HOST_REGS;hr++)
9609     {
9610       if(!((nr>>hr)&1)) {
9611         if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
9612         if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9613            (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9614            (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
9615         {
9616           if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9617           {
9618             if(likely[i]) {
9619               regs[i].regmap[hr]=-1;
9620               regs[i].isconst&=~(1<<hr);
9621               if(i<slen-2) regmap_pre[i+2][hr]=-1;
9622             }
9623           }
9624         }
9625         if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9626         {
9627           int d1=0,d2=0,map=0,temp=0;
9628           if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
9629           {
9630             d1=dep1[i+1];
9631             d2=dep2[i+1];
9632           }
9633           if(using_tlb) {
9634             if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
9635                itype[i+1]==STORE || itype[i+1]==STORELR ||
9636                itype[i+1]==C1LS || itype[i+1]==C2LS)
9637             map=TLREG;
9638           } else
9639           if(itype[i+1]==STORE || itype[i+1]==STORELR ||
9640              (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
9641             map=INVCP;
9642           }
9643           if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
9644              itype[i+1]==C1LS || itype[i+1]==C2LS)
9645             temp=FTEMP;
9646           if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9647              (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9648              (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
9649              (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
9650              (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9651              regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
9652              (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
9653              regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
9654              regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
9655              regs[i].regmap[hr]!=map )
9656           {
9657             regs[i].regmap[hr]=-1;
9658             regs[i].isconst&=~(1<<hr);
9659             if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
9660                (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
9661                (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
9662                (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
9663                (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
9664                branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
9665                (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
9666                branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
9667                branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
9668                branch_regs[i].regmap[hr]!=map)
9669             {
9670               branch_regs[i].regmap[hr]=-1;
9671               branch_regs[i].regmap_entry[hr]=-1;
9672               if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9673               {
9674                 if(!likely[i]&&i<slen-2) {
9675                   regmap_pre[i+2][hr]=-1;
9676                 }
9677               }
9678             }
9679           }
9680         }
9681         else
9682         {
9683           // Non-branch
9684           if(i>0)
9685           {
9686             int d1=0,d2=0,map=-1,temp=-1;
9687             if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
9688             {
9689               d1=dep1[i];
9690               d2=dep2[i];
9691             }
9692             if(using_tlb) {
9693               if(itype[i]==LOAD || itype[i]==LOADLR ||
9694                  itype[i]==STORE || itype[i]==STORELR ||
9695                  itype[i]==C1LS || itype[i]==C2LS)
9696               map=TLREG;
9697             } else if(itype[i]==STORE || itype[i]==STORELR ||
9698                       (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
9699               map=INVCP;
9700             }
9701             if(itype[i]==LOADLR || itype[i]==STORELR ||
9702                itype[i]==C1LS || itype[i]==C2LS)
9703               temp=FTEMP;
9704             if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9705                (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
9706                (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9707                regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
9708                (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
9709                (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
9710             {
9711               if(i<slen-1&&!is_ds[i]) {
9712                 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
9713                 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
9714                 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
9715                 {
9716                   printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
9717                   assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
9718                 }
9719                 regmap_pre[i+1][hr]=-1;
9720                 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
9721               }
9722               regs[i].regmap[hr]=-1;
9723               regs[i].isconst&=~(1<<hr);
9724             }
9725           }
9726         }
9727       }
9728     }
9729   }
9730
9731   /* Pass 5 - Pre-allocate registers */
9732
9733   // If a register is allocated during a loop, try to allocate it for the
9734   // entire loop, if possible.  This avoids loading/storing registers
9735   // inside of the loop.
9736
9737   signed char f_regmap[HOST_REGS];
9738   clear_all_regs(f_regmap);
9739   for(i=0;i<slen-1;i++)
9740   {
9741     if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9742     {
9743       if(ba[i]>=start && ba[i]<(start+i*4))
9744       if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
9745       ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
9746       ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
9747       ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
9748       ||itype[i+1]==FCOMP||itype[i+1]==FCONV
9749       ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
9750       {
9751         int t=(ba[i]-start)>>2;
9752         if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
9753         if(t<2||(itype[t-2]!=UJUMP)) // call/ret assumes no registers allocated
9754         for(hr=0;hr<HOST_REGS;hr++)
9755         {
9756           if(regs[i].regmap[hr]>64) {
9757             if(!((regs[i].dirty>>hr)&1))
9758               f_regmap[hr]=regs[i].regmap[hr];
9759             else f_regmap[hr]=-1;
9760           }
9761           else if(regs[i].regmap[hr]>=0) {
9762             if(f_regmap[hr]!=regs[i].regmap[hr]) {
9763               // dealloc old register
9764               int n;
9765               for(n=0;n<HOST_REGS;n++)
9766               {
9767                 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
9768               }
9769               // and alloc new one
9770               f_regmap[hr]=regs[i].regmap[hr];
9771             }
9772           }
9773           if(branch_regs[i].regmap[hr]>64) {
9774             if(!((branch_regs[i].dirty>>hr)&1))
9775               f_regmap[hr]=branch_regs[i].regmap[hr];
9776             else f_regmap[hr]=-1;
9777           }
9778           else if(branch_regs[i].regmap[hr]>=0) {
9779             if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
9780               // dealloc old register
9781               int n;
9782               for(n=0;n<HOST_REGS;n++)
9783               {
9784                 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
9785               }
9786               // and alloc new one
9787               f_regmap[hr]=branch_regs[i].regmap[hr];
9788             }
9789           }
9790           if(itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
9791           ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
9792           ||itype[i+1]==FCOMP||itype[i+1]==FCONV
9793           ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
9794           {
9795             // Test both in case the delay slot is ooo,
9796             // could be done better...
9797             if(count_free_regs(branch_regs[i].regmap)<2
9798              ||count_free_regs(regs[i].regmap)<2)
9799               f_regmap[hr]=branch_regs[i].regmap[hr];
9800           }
9801           // Avoid dirty->clean transition
9802           // #ifdef DESTRUCTIVE_WRITEBACK here?
9803           if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
9804           if(f_regmap[hr]>0) {
9805             if(regs[t].regmap_entry[hr]<0) {
9806               int r=f_regmap[hr];
9807               for(j=t;j<=i;j++)
9808               {
9809                 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9810                 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
9811                 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
9812                 if(r>63) {
9813                   // NB This can exclude the case where the upper-half
9814                   // register is lower numbered than the lower-half
9815                   // register.  Not sure if it's worth fixing...
9816                   if(get_reg(regs[j].regmap,r&63)<0) break;
9817                   if(regs[j].is32&(1LL<<(r&63))) break;
9818                 }
9819                 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
9820                   //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9821                   int k;
9822                   if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
9823                     if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
9824                     if(r>63) {
9825                       if(get_reg(regs[i].regmap,r&63)<0) break;
9826                       if(get_reg(branch_regs[i].regmap,r&63)<0) break;
9827                     }
9828                     k=i;
9829                     while(k>1&&regs[k-1].regmap[hr]==-1) {
9830                       if(itype[k-1]==STORE||itype[k-1]==STORELR
9831                       ||itype[k-1]==C1LS||itype[k-1]==SHIFT||itype[k-1]==COP1
9832                       ||itype[k-1]==FLOAT||itype[k-1]==FCONV||itype[k-1]==FCOMP
9833                       ||itype[k-1]==COP2||itype[k-1]==C2LS||itype[k-1]==C2OP) {
9834                         if(count_free_regs(regs[k-1].regmap)<2) {
9835                           //printf("no free regs for store %x\n",start+(k-1)*4);
9836                           break;
9837                         }
9838                       }
9839                       else
9840                       if(itype[k-1]!=NOP&&itype[k-1]!=MOV&&itype[k-1]!=ALU&&itype[k-1]!=SHIFTIMM&&itype[k-1]!=IMM16&&itype[k-1]!=LOAD) break;
9841                       if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
9842                         //printf("no-match due to different register\n");
9843                         break;
9844                       }
9845                       if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
9846                         //printf("no-match due to branch\n");
9847                         break;
9848                       }
9849                       // call/ret fast path assumes no registers allocated
9850                       if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)) {
9851                         break;
9852                       }
9853                       if(r>63) {
9854                         // NB This can exclude the case where the upper-half
9855                         // register is lower numbered than the lower-half
9856                         // register.  Not sure if it's worth fixing...
9857                         if(get_reg(regs[k-1].regmap,r&63)<0) break;
9858                         if(regs[k-1].is32&(1LL<<(r&63))) break;
9859                       }
9860                       k--;
9861                     }
9862                     if(i<slen-1) {
9863                       if((regs[k].is32&(1LL<<f_regmap[hr]))!=
9864                         (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
9865                         //printf("bad match after branch\n");
9866                         break;
9867                       }
9868                     }
9869                     if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
9870                       //printf("Extend r%d, %x ->\n",hr,start+k*4);
9871                       while(k<i) {
9872                         regs[k].regmap_entry[hr]=f_regmap[hr];
9873                         regs[k].regmap[hr]=f_regmap[hr];
9874                         regmap_pre[k+1][hr]=f_regmap[hr];
9875                         regs[k].wasdirty&=~(1<<hr);
9876                         regs[k].dirty&=~(1<<hr);
9877                         regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
9878                         regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
9879                         regs[k].wasconst&=~(1<<hr);
9880                         regs[k].isconst&=~(1<<hr);
9881                         k++;
9882                       }
9883                     }
9884                     else {
9885                       //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
9886                       break;
9887                     }
9888                     assert(regs[i-1].regmap[hr]==f_regmap[hr]);
9889                     if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
9890                       //printf("OK fill %x (r%d)\n",start+i*4,hr);
9891                       regs[i].regmap_entry[hr]=f_regmap[hr];
9892                       regs[i].regmap[hr]=f_regmap[hr];
9893                       regs[i].wasdirty&=~(1<<hr);
9894                       regs[i].dirty&=~(1<<hr);
9895                       regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
9896                       regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
9897                       regs[i].wasconst&=~(1<<hr);
9898                       regs[i].isconst&=~(1<<hr);
9899                       branch_regs[i].regmap_entry[hr]=f_regmap[hr];
9900                       branch_regs[i].wasdirty&=~(1<<hr);
9901                       branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
9902                       branch_regs[i].regmap[hr]=f_regmap[hr];
9903                       branch_regs[i].dirty&=~(1<<hr);
9904                       branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
9905                       branch_regs[i].wasconst&=~(1<<hr);
9906                       branch_regs[i].isconst&=~(1<<hr);
9907                       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
9908                         regmap_pre[i+2][hr]=f_regmap[hr];
9909                         regs[i+2].wasdirty&=~(1<<hr);
9910                         regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
9911                         assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
9912                           (regs[i+2].was32&(1LL<<f_regmap[hr])));
9913                       }
9914                     }
9915                   }
9916                   for(k=t;k<j;k++) {
9917                     regs[k].regmap_entry[hr]=f_regmap[hr];
9918                     regs[k].regmap[hr]=f_regmap[hr];
9919                     regmap_pre[k+1][hr]=f_regmap[hr];
9920                     regs[k+1].wasdirty&=~(1<<hr);
9921                     regs[k].dirty&=~(1<<hr);
9922                     regs[k].wasconst&=~(1<<hr);
9923                     regs[k].isconst&=~(1<<hr);
9924                   }
9925                   if(regs[j].regmap[hr]==f_regmap[hr])
9926                     regs[j].regmap_entry[hr]=f_regmap[hr];
9927                   break;
9928                 }
9929                 if(j==i) break;
9930                 if(regs[j].regmap[hr]>=0)
9931                   break;
9932                 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
9933                   //printf("no-match due to different register\n");
9934                   break;
9935                 }
9936                 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
9937                   //printf("32/64 mismatch %x %d\n",start+j*4,hr);
9938                   break;
9939                 }
9940                 if(itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS
9941                 ||itype[j]==SHIFT||itype[j]==COP1||itype[j]==FLOAT
9942                 ||itype[j]==FCOMP||itype[j]==FCONV
9943                 ||itype[j]==COP2||itype[j]==C2LS||itype[j]==C2OP) {
9944                   if(count_free_regs(regs[j].regmap)<2) {
9945                     //printf("No free regs for store %x\n",start+j*4);
9946                     break;
9947                   }
9948                 }
9949                 else if(itype[j]!=NOP&&itype[j]!=MOV&&itype[j]!=ALU&&itype[j]!=SHIFTIMM&&itype[j]!=IMM16&&itype[j]!=LOAD) break;
9950                 if(f_regmap[hr]>=64) {
9951                   if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
9952                     break;
9953                   }
9954                   else
9955                   {
9956                     if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
9957                       break;
9958                     }
9959                   }
9960                 }
9961               }
9962             }
9963           }
9964         }
9965       }
9966     }else{
9967       int count=0;
9968       for(hr=0;hr<HOST_REGS;hr++)
9969       {
9970         if(hr!=EXCLUDE_REG) {
9971           if(regs[i].regmap[hr]>64) {
9972             if(!((regs[i].dirty>>hr)&1))
9973               f_regmap[hr]=regs[i].regmap[hr];
9974           }
9975           else if(regs[i].regmap[hr]>=0) {
9976             if(f_regmap[hr]!=regs[i].regmap[hr]) {
9977               // dealloc old register
9978               int n;
9979               for(n=0;n<HOST_REGS;n++)
9980               {
9981                 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
9982               }
9983               // and alloc new one
9984               f_regmap[hr]=regs[i].regmap[hr];
9985             }
9986           }
9987           else if(regs[i].regmap[hr]<0) count++;
9988         }
9989       }
9990       // Try to restore cycle count at branch targets
9991       if(bt[i]) {
9992         for(j=i;j<slen-1;j++) {
9993           if(regs[j].regmap[HOST_CCREG]!=-1) break;
9994           if(itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS
9995           ||itype[j]==SHIFT||itype[j]==COP1||itype[j]==FLOAT
9996           ||itype[j]==FCOMP||itype[j]==FCONV
9997           ||itype[j]==COP2||itype[j]==C2LS||itype[j]==C2OP) {
9998             if(count_free_regs(regs[j].regmap)<2) {
9999               //printf("no free regs for store %x\n",start+j*4);
10000               break;
10001             }
10002           }
10003           else
10004           if(itype[j]!=NOP&&itype[j]!=MOV&&itype[j]!=ALU&&itype[j]!=SHIFTIMM&&itype[j]!=IMM16&&itype[j]!=LOAD) break;
10005         }
10006         if(regs[j].regmap[HOST_CCREG]==CCREG) {
10007           int k=i;
10008           //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
10009           while(k<j) {
10010             regs[k].regmap_entry[HOST_CCREG]=CCREG;
10011             regs[k].regmap[HOST_CCREG]=CCREG;
10012             regmap_pre[k+1][HOST_CCREG]=CCREG;
10013             regs[k+1].wasdirty|=1<<HOST_CCREG;
10014             regs[k].dirty|=1<<HOST_CCREG;
10015             regs[k].wasconst&=~(1<<HOST_CCREG);
10016             regs[k].isconst&=~(1<<HOST_CCREG);
10017             k++;
10018           }
10019           regs[j].regmap_entry[HOST_CCREG]=CCREG;
10020         }
10021         // Work backwards from the branch target
10022         if(j>i&&f_regmap[HOST_CCREG]==CCREG)
10023         {
10024           //printf("Extend backwards\n");
10025           int k;
10026           k=i;
10027           while(regs[k-1].regmap[HOST_CCREG]==-1) {
10028             if(itype[k-1]==STORE||itype[k-1]==STORELR||itype[k-1]==C1LS
10029             ||itype[k-1]==SHIFT||itype[k-1]==COP1||itype[k-1]==FLOAT
10030             ||itype[k-1]==FCONV||itype[k-1]==FCOMP
10031             ||itype[k-1]==COP2||itype[k-1]==C2LS||itype[k-1]==C2OP) {
10032               if(count_free_regs(regs[k-1].regmap)<2) {
10033                 //printf("no free regs for store %x\n",start+(k-1)*4);
10034                 break;
10035               }
10036             }
10037             else
10038             if(itype[k-1]!=NOP&&itype[k-1]!=MOV&&itype[k-1]!=ALU&&itype[k-1]!=SHIFTIMM&&itype[k-1]!=IMM16&&itype[k-1]!=LOAD) break;
10039             k--;
10040           }
10041           if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
10042             //printf("Extend CC, %x ->\n",start+k*4);
10043             while(k<=i) {
10044               regs[k].regmap_entry[HOST_CCREG]=CCREG;
10045               regs[k].regmap[HOST_CCREG]=CCREG;
10046               regmap_pre[k+1][HOST_CCREG]=CCREG;
10047               regs[k+1].wasdirty|=1<<HOST_CCREG;
10048               regs[k].dirty|=1<<HOST_CCREG;
10049               regs[k].wasconst&=~(1<<HOST_CCREG);
10050               regs[k].isconst&=~(1<<HOST_CCREG);
10051               k++;
10052             }
10053           }
10054           else {
10055             //printf("Fail Extend CC, %x ->\n",start+k*4);
10056           }
10057         }
10058       }
10059       if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
10060          itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
10061          itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
10062          itype[i]!=FCONV&&itype[i]!=FCOMP&&
10063          itype[i]!=COP2&&itype[i]!=C2LS&&itype[i]!=C2OP)
10064       {
10065         memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
10066       }
10067     }
10068   }
10069
10070   // This allocates registers (if possible) one instruction prior
10071   // to use, which can avoid a load-use penalty on certain CPUs.
10072   for(i=0;i<slen-1;i++)
10073   {
10074     if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10075     {
10076       if(!bt[i+1])
10077       {
10078         if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
10079            ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
10080         {
10081           if(rs1[i+1]) {
10082             if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10083             {
10084               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10085               {
10086                 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10087                 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10088                 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10089                 regs[i].isconst&=~(1<<hr);
10090                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10091                 constmap[i][hr]=constmap[i+1][hr];
10092                 regs[i+1].wasdirty&=~(1<<hr);
10093                 regs[i].dirty&=~(1<<hr);
10094               }
10095             }
10096           }
10097           if(rs2[i+1]) {
10098             if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10099             {
10100               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10101               {
10102                 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10103                 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10104                 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10105                 regs[i].isconst&=~(1<<hr);
10106                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10107                 constmap[i][hr]=constmap[i+1][hr];
10108                 regs[i+1].wasdirty&=~(1<<hr);
10109                 regs[i].dirty&=~(1<<hr);
10110               }
10111             }
10112           }
10113           if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10114             if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10115             {
10116               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10117               {
10118                 regs[i].regmap[hr]=rs1[i+1];
10119                 regmap_pre[i+1][hr]=rs1[i+1];
10120                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10121                 regs[i].isconst&=~(1<<hr);
10122                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10123                 constmap[i][hr]=constmap[i+1][hr];
10124                 regs[i+1].wasdirty&=~(1<<hr);
10125                 regs[i].dirty&=~(1<<hr);
10126               }
10127             }
10128           }
10129           if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10130             if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10131             {
10132               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10133               {
10134                 regs[i].regmap[hr]=rs1[i+1];
10135                 regmap_pre[i+1][hr]=rs1[i+1];
10136                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10137                 regs[i].isconst&=~(1<<hr);
10138                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10139                 constmap[i][hr]=constmap[i+1][hr];
10140                 regs[i+1].wasdirty&=~(1<<hr);
10141                 regs[i].dirty&=~(1<<hr);
10142               }
10143             }
10144           }
10145           #ifndef HOST_IMM_ADDR32
10146           if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
10147             hr=get_reg(regs[i+1].regmap,TLREG);
10148             if(hr>=0) {
10149               int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10150               if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10151                 int nr;
10152                 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10153                 {
10154                   regs[i].regmap[hr]=MGEN1+((i+1)&1);
10155                   regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10156                   regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10157                   regs[i].isconst&=~(1<<hr);
10158                   regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10159                   constmap[i][hr]=constmap[i+1][hr];
10160                   regs[i+1].wasdirty&=~(1<<hr);
10161                   regs[i].dirty&=~(1<<hr);
10162                 }
10163                 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10164                 {
10165                   // move it to another register
10166                   regs[i+1].regmap[hr]=-1;
10167                   regmap_pre[i+2][hr]=-1;
10168                   regs[i+1].regmap[nr]=TLREG;
10169                   regmap_pre[i+2][nr]=TLREG;
10170                   regs[i].regmap[nr]=MGEN1+((i+1)&1);
10171                   regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10172                   regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10173                   regs[i].isconst&=~(1<<nr);
10174                   regs[i+1].isconst&=~(1<<nr);
10175                   regs[i].dirty&=~(1<<nr);
10176                   regs[i+1].wasdirty&=~(1<<nr);
10177                   regs[i+1].dirty&=~(1<<nr);
10178                   regs[i+2].wasdirty&=~(1<<nr);
10179                 }
10180               }
10181             }
10182           }
10183           #endif
10184           if(itype[i+1]==STORE||itype[i+1]==STORELR
10185              ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
10186             if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10187               hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10188               if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10189               else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10190               assert(hr>=0);
10191               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10192               {
10193                 regs[i].regmap[hr]=rs1[i+1];
10194                 regmap_pre[i+1][hr]=rs1[i+1];
10195                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10196                 regs[i].isconst&=~(1<<hr);
10197                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10198                 constmap[i][hr]=constmap[i+1][hr];
10199                 regs[i+1].wasdirty&=~(1<<hr);
10200                 regs[i].dirty&=~(1<<hr);
10201               }
10202             }
10203           }
10204           if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
10205             if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10206               int nr;
10207               hr=get_reg(regs[i+1].regmap,FTEMP);
10208               assert(hr>=0);
10209               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10210               {
10211                 regs[i].regmap[hr]=rs1[i+1];
10212                 regmap_pre[i+1][hr]=rs1[i+1];
10213                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10214                 regs[i].isconst&=~(1<<hr);
10215                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10216                 constmap[i][hr]=constmap[i+1][hr];
10217                 regs[i+1].wasdirty&=~(1<<hr);
10218                 regs[i].dirty&=~(1<<hr);
10219               }
10220               else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10221               {
10222                 // move it to another register
10223                 regs[i+1].regmap[hr]=-1;
10224                 regmap_pre[i+2][hr]=-1;
10225                 regs[i+1].regmap[nr]=FTEMP;
10226                 regmap_pre[i+2][nr]=FTEMP;
10227                 regs[i].regmap[nr]=rs1[i+1];
10228                 regmap_pre[i+1][nr]=rs1[i+1];
10229                 regs[i+1].regmap_entry[nr]=rs1[i+1];
10230                 regs[i].isconst&=~(1<<nr);
10231                 regs[i+1].isconst&=~(1<<nr);
10232                 regs[i].dirty&=~(1<<nr);
10233                 regs[i+1].wasdirty&=~(1<<nr);
10234                 regs[i+1].dirty&=~(1<<nr);
10235                 regs[i+2].wasdirty&=~(1<<nr);
10236               }
10237             }
10238           }
10239           if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
10240             if(itype[i+1]==LOAD)
10241               hr=get_reg(regs[i+1].regmap,rt1[i+1]);
10242             if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
10243               hr=get_reg(regs[i+1].regmap,FTEMP);
10244             if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
10245               hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10246               if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10247             }
10248             if(hr>=0&&regs[i].regmap[hr]<0) {
10249               int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10250               if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10251                 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10252                 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10253                 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10254                 regs[i].isconst&=~(1<<hr);
10255                 regs[i+1].wasdirty&=~(1<<hr);
10256                 regs[i].dirty&=~(1<<hr);
10257               }
10258             }
10259           }
10260         }
10261       }
10262     }
10263   }
10264
10265   /* Pass 6 - Optimize clean/dirty state */
10266   clean_registers(0,slen-1,1);
10267
10268   /* Pass 7 - Identify 32-bit registers */
10269 #ifndef FORCE32
10270   provisional_r32();
10271
10272   u_int r32=0;
10273
10274   for (i=slen-1;i>=0;i--)
10275   {
10276     int hr;
10277     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10278     {
10279       if(ba[i]<start || ba[i]>=(start+slen*4))
10280       {
10281         // Branch out of this block, don't need anything
10282         r32=0;
10283       }
10284       else
10285       {
10286         // Internal branch
10287         // Need whatever matches the target
10288         // (and doesn't get overwritten by the delay slot instruction)
10289         r32=0;
10290         int t=(ba[i]-start)>>2;
10291         if(ba[i]>start+i*4) {
10292           // Forward branch
10293           if(!(requires_32bit[t]&~regs[i].was32))
10294             r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10295         }else{
10296           // Backward branch
10297           //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10298           //  r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10299           if(!(pr32[t]&~regs[i].was32))
10300             r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10301         }
10302       }
10303       // Conditional branch may need registers for following instructions
10304       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10305       {
10306         if(i<slen-2) {
10307           r32|=requires_32bit[i+2];
10308           r32&=regs[i].was32;
10309           // Mark this address as a branch target since it may be called
10310           // upon return from interrupt
10311           bt[i+2]=1;
10312         }
10313       }
10314       // Merge in delay slot
10315       if(!likely[i]) {
10316         // These are overwritten unless the branch is "likely"
10317         // and the delay slot is nullified if not taken
10318         r32&=~(1LL<<rt1[i+1]);
10319         r32&=~(1LL<<rt2[i+1]);
10320       }
10321       // Assume these are needed (delay slot)
10322       if(us1[i+1]>0)
10323       {
10324         if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10325       }
10326       if(us2[i+1]>0)
10327       {
10328         if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10329       }
10330       if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10331       {
10332         if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10333       }
10334       if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10335       {
10336         if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10337       }
10338     }
10339     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
10340     {
10341       // SYSCALL instruction (software interrupt)
10342       r32=0;
10343     }
10344     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10345     {
10346       // ERET instruction (return from interrupt)
10347       r32=0;
10348     }
10349     // Check 32 bits
10350     r32&=~(1LL<<rt1[i]);
10351     r32&=~(1LL<<rt2[i]);
10352     if(us1[i]>0)
10353     {
10354       if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10355     }
10356     if(us2[i]>0)
10357     {
10358       if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10359     }
10360     if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
10361     {
10362       if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
10363     }
10364     if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
10365     {
10366       if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
10367     }
10368     requires_32bit[i]=r32;
10369
10370     // Dirty registers which are 32-bit, require 32-bit input
10371     // as they will be written as 32-bit values
10372     for(hr=0;hr<HOST_REGS;hr++)
10373     {
10374       if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
10375         if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
10376           if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
10377           requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
10378         }
10379       }
10380     }
10381     //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
10382   }
10383 #endif
10384
10385   if(itype[slen-1]==SPAN) {
10386     bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
10387   }
10388
10389   /* Debug/disassembly */
10390   if((void*)assem_debug==(void*)printf)
10391   for(i=0;i<slen;i++)
10392   {
10393     printf("U:");
10394     int r;
10395     for(r=1;r<=CCREG;r++) {
10396       if((unneeded_reg[i]>>r)&1) {
10397         if(r==HIREG) printf(" HI");
10398         else if(r==LOREG) printf(" LO");
10399         else printf(" r%d",r);
10400       }
10401     }
10402 #ifndef FORCE32
10403     printf(" UU:");
10404     for(r=1;r<=CCREG;r++) {
10405       if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
10406         if(r==HIREG) printf(" HI");
10407         else if(r==LOREG) printf(" LO");
10408         else printf(" r%d",r);
10409       }
10410     }
10411     printf(" 32:");
10412     for(r=0;r<=CCREG;r++) {
10413       //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10414       if((regs[i].was32>>r)&1) {
10415         if(r==CCREG) printf(" CC");
10416         else if(r==HIREG) printf(" HI");
10417         else if(r==LOREG) printf(" LO");
10418         else printf(" r%d",r);
10419       }
10420     }
10421 #endif
10422     printf("\n");
10423     #if defined(__i386__) || defined(__x86_64__)
10424     printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
10425     #endif
10426     #ifdef __arm__
10427     printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
10428     #endif
10429     printf("needs: ");
10430     if(needed_reg[i]&1) printf("eax ");
10431     if((needed_reg[i]>>1)&1) printf("ecx ");
10432     if((needed_reg[i]>>2)&1) printf("edx ");
10433     if((needed_reg[i]>>3)&1) printf("ebx ");
10434     if((needed_reg[i]>>5)&1) printf("ebp ");
10435     if((needed_reg[i]>>6)&1) printf("esi ");
10436     if((needed_reg[i]>>7)&1) printf("edi ");
10437     printf("r:");
10438     for(r=0;r<=CCREG;r++) {
10439       //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10440       if((requires_32bit[i]>>r)&1) {
10441         if(r==CCREG) printf(" CC");
10442         else if(r==HIREG) printf(" HI");
10443         else if(r==LOREG) printf(" LO");
10444         else printf(" r%d",r);
10445       }
10446     }
10447     printf("\n");
10448     /*printf("pr:");
10449     for(r=0;r<=CCREG;r++) {
10450       //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10451       if((pr32[i]>>r)&1) {
10452         if(r==CCREG) printf(" CC");
10453         else if(r==HIREG) printf(" HI");
10454         else if(r==LOREG) printf(" LO");
10455         else printf(" r%d",r);
10456       }
10457     }
10458     if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
10459     printf("\n");*/
10460     #if defined(__i386__) || defined(__x86_64__)
10461     printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
10462     printf("dirty: ");
10463     if(regs[i].wasdirty&1) printf("eax ");
10464     if((regs[i].wasdirty>>1)&1) printf("ecx ");
10465     if((regs[i].wasdirty>>2)&1) printf("edx ");
10466     if((regs[i].wasdirty>>3)&1) printf("ebx ");
10467     if((regs[i].wasdirty>>5)&1) printf("ebp ");
10468     if((regs[i].wasdirty>>6)&1) printf("esi ");
10469     if((regs[i].wasdirty>>7)&1) printf("edi ");
10470     #endif
10471     #ifdef __arm__
10472     printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
10473     printf("dirty: ");
10474     if(regs[i].wasdirty&1) printf("r0 ");
10475     if((regs[i].wasdirty>>1)&1) printf("r1 ");
10476     if((regs[i].wasdirty>>2)&1) printf("r2 ");
10477     if((regs[i].wasdirty>>3)&1) printf("r3 ");
10478     if((regs[i].wasdirty>>4)&1) printf("r4 ");
10479     if((regs[i].wasdirty>>5)&1) printf("r5 ");
10480     if((regs[i].wasdirty>>6)&1) printf("r6 ");
10481     if((regs[i].wasdirty>>7)&1) printf("r7 ");
10482     if((regs[i].wasdirty>>8)&1) printf("r8 ");
10483     if((regs[i].wasdirty>>9)&1) printf("r9 ");
10484     if((regs[i].wasdirty>>10)&1) printf("r10 ");
10485     if((regs[i].wasdirty>>12)&1) printf("r12 ");
10486     #endif
10487     printf("\n");
10488     disassemble_inst(i);
10489     //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
10490     #if defined(__i386__) || defined(__x86_64__)
10491     printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
10492     if(regs[i].dirty&1) printf("eax ");
10493     if((regs[i].dirty>>1)&1) printf("ecx ");
10494     if((regs[i].dirty>>2)&1) printf("edx ");
10495     if((regs[i].dirty>>3)&1) printf("ebx ");
10496     if((regs[i].dirty>>5)&1) printf("ebp ");
10497     if((regs[i].dirty>>6)&1) printf("esi ");
10498     if((regs[i].dirty>>7)&1) printf("edi ");
10499     #endif
10500     #ifdef __arm__
10501     printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
10502     if(regs[i].dirty&1) printf("r0 ");
10503     if((regs[i].dirty>>1)&1) printf("r1 ");
10504     if((regs[i].dirty>>2)&1) printf("r2 ");
10505     if((regs[i].dirty>>3)&1) printf("r3 ");
10506     if((regs[i].dirty>>4)&1) printf("r4 ");
10507     if((regs[i].dirty>>5)&1) printf("r5 ");
10508     if((regs[i].dirty>>6)&1) printf("r6 ");
10509     if((regs[i].dirty>>7)&1) printf("r7 ");
10510     if((regs[i].dirty>>8)&1) printf("r8 ");
10511     if((regs[i].dirty>>9)&1) printf("r9 ");
10512     if((regs[i].dirty>>10)&1) printf("r10 ");
10513     if((regs[i].dirty>>12)&1) printf("r12 ");
10514     #endif
10515     printf("\n");
10516     if(regs[i].isconst) {
10517       printf("constants: ");
10518       #if defined(__i386__) || defined(__x86_64__)
10519       if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
10520       if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
10521       if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
10522       if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
10523       if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
10524       if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
10525       if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
10526       #endif
10527       #ifdef __arm__
10528       if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
10529       if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
10530       if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
10531       if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
10532       if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
10533       if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
10534       if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
10535       if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
10536       if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
10537       if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
10538       if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
10539       if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
10540       #endif
10541       printf("\n");
10542     }
10543 #ifndef FORCE32
10544     printf(" 32:");
10545     for(r=0;r<=CCREG;r++) {
10546       if((regs[i].is32>>r)&1) {
10547         if(r==CCREG) printf(" CC");
10548         else if(r==HIREG) printf(" HI");
10549         else if(r==LOREG) printf(" LO");
10550         else printf(" r%d",r);
10551       }
10552     }
10553     printf("\n");
10554 #endif
10555     /*printf(" p32:");
10556     for(r=0;r<=CCREG;r++) {
10557       if((p32[i]>>r)&1) {
10558         if(r==CCREG) printf(" CC");
10559         else if(r==HIREG) printf(" HI");
10560         else if(r==LOREG) printf(" LO");
10561         else printf(" r%d",r);
10562       }
10563     }
10564     if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
10565     else printf("\n");*/
10566     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10567       #if defined(__i386__) || defined(__x86_64__)
10568       printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
10569       if(branch_regs[i].dirty&1) printf("eax ");
10570       if((branch_regs[i].dirty>>1)&1) printf("ecx ");
10571       if((branch_regs[i].dirty>>2)&1) printf("edx ");
10572       if((branch_regs[i].dirty>>3)&1) printf("ebx ");
10573       if((branch_regs[i].dirty>>5)&1) printf("ebp ");
10574       if((branch_regs[i].dirty>>6)&1) printf("esi ");
10575       if((branch_regs[i].dirty>>7)&1) printf("edi ");
10576       #endif
10577       #ifdef __arm__
10578       printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
10579       if(branch_regs[i].dirty&1) printf("r0 ");
10580       if((branch_regs[i].dirty>>1)&1) printf("r1 ");
10581       if((branch_regs[i].dirty>>2)&1) printf("r2 ");
10582       if((branch_regs[i].dirty>>3)&1) printf("r3 ");
10583       if((branch_regs[i].dirty>>4)&1) printf("r4 ");
10584       if((branch_regs[i].dirty>>5)&1) printf("r5 ");
10585       if((branch_regs[i].dirty>>6)&1) printf("r6 ");
10586       if((branch_regs[i].dirty>>7)&1) printf("r7 ");
10587       if((branch_regs[i].dirty>>8)&1) printf("r8 ");
10588       if((branch_regs[i].dirty>>9)&1) printf("r9 ");
10589       if((branch_regs[i].dirty>>10)&1) printf("r10 ");
10590       if((branch_regs[i].dirty>>12)&1) printf("r12 ");
10591       #endif
10592 #ifndef FORCE32
10593       printf(" 32:");
10594       for(r=0;r<=CCREG;r++) {
10595         if((branch_regs[i].is32>>r)&1) {
10596           if(r==CCREG) printf(" CC");
10597           else if(r==HIREG) printf(" HI");
10598           else if(r==LOREG) printf(" LO");
10599           else printf(" r%d",r);
10600         }
10601       }
10602       printf("\n");
10603 #endif
10604     }
10605   }
10606
10607   /* Pass 8 - Assembly */
10608   linkcount=0;stubcount=0;
10609   ds=0;is_delayslot=0;
10610   cop1_usable=0;
10611   uint64_t is32_pre=0;
10612   u_int dirty_pre=0;
10613   u_int beginning=(u_int)out;
10614   if((u_int)addr&1) {
10615     ds=1;
10616     pagespan_ds();
10617   }
10618   u_int instr_addr0_override=0;
10619
10620 #ifdef PCSX
10621   if (start == 0x80030000) {
10622     // nasty hack for fastbios thing
10623     instr_addr0_override=(u_int)out;
10624     emit_movimm(start,0);
10625     emit_readword((int)&pcaddr,1);
10626     emit_writeword(0,(int)&pcaddr);
10627     emit_cmp(0,1);
10628     emit_jne((int)new_dyna_leave);
10629   }
10630 #endif
10631   for(i=0;i<slen;i++)
10632   {
10633     //if(ds) printf("ds: ");
10634     if((void*)assem_debug==(void*)printf) disassemble_inst(i);
10635     if(ds) {
10636       ds=0; // Skip delay slot
10637       if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
10638       instr_addr[i]=0;
10639     } else {
10640       #ifndef DESTRUCTIVE_WRITEBACK
10641       if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10642       {
10643         wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
10644               unneeded_reg[i],unneeded_reg_upper[i]);
10645         wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
10646               unneeded_reg[i],unneeded_reg_upper[i]);
10647       }
10648       is32_pre=regs[i].is32;
10649       dirty_pre=regs[i].dirty;
10650       #endif
10651       // write back
10652       if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10653       {
10654         wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
10655                       unneeded_reg[i],unneeded_reg_upper[i]);
10656         loop_preload(regmap_pre[i],regs[i].regmap_entry);
10657       }
10658       // branch target entry point
10659       instr_addr[i]=(u_int)out;
10660       assem_debug("<->\n");
10661       // load regs
10662       if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
10663         wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
10664       load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
10665       address_generation(i,&regs[i],regs[i].regmap_entry);
10666       load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
10667       if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10668       {
10669         // Load the delay slot registers if necessary
10670         if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10671           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10672         if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10673           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
10674         if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
10675           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10676       }
10677       else if(i+1<slen)
10678       {
10679         // Preload registers for following instruction
10680         if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10681           if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
10682             load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10683         if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10684           if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
10685             load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
10686       }
10687       // TODO: if(is_ooo(i)) address_generation(i+1);
10688       if(itype[i]==CJUMP||itype[i]==FJUMP)
10689         load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
10690       if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
10691         load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10692       if(bt[i]) cop1_usable=0;
10693       // assemble
10694       switch(itype[i]) {
10695         case ALU:
10696           alu_assemble(i,&regs[i]);break;
10697         case IMM16:
10698           imm16_assemble(i,&regs[i]);break;
10699         case SHIFT:
10700           shift_assemble(i,&regs[i]);break;
10701         case SHIFTIMM:
10702           shiftimm_assemble(i,&regs[i]);break;
10703         case LOAD:
10704           load_assemble(i,&regs[i]);break;
10705         case LOADLR:
10706           loadlr_assemble(i,&regs[i]);break;
10707         case STORE:
10708           store_assemble(i,&regs[i]);break;
10709         case STORELR:
10710           storelr_assemble(i,&regs[i]);break;
10711         case COP0:
10712           cop0_assemble(i,&regs[i]);break;
10713         case COP1:
10714           cop1_assemble(i,&regs[i]);break;
10715         case C1LS:
10716           c1ls_assemble(i,&regs[i]);break;
10717         case COP2:
10718           cop2_assemble(i,&regs[i]);break;
10719         case C2LS:
10720           c2ls_assemble(i,&regs[i]);break;
10721         case C2OP:
10722           c2op_assemble(i,&regs[i]);break;
10723         case FCONV:
10724           fconv_assemble(i,&regs[i]);break;
10725         case FLOAT:
10726           float_assemble(i,&regs[i]);break;
10727         case FCOMP:
10728           fcomp_assemble(i,&regs[i]);break;
10729         case MULTDIV:
10730           multdiv_assemble(i,&regs[i]);break;
10731         case MOV:
10732           mov_assemble(i,&regs[i]);break;
10733         case SYSCALL:
10734           syscall_assemble(i,&regs[i]);break;
10735         case HLECALL:
10736           hlecall_assemble(i,&regs[i]);break;
10737         case INTCALL:
10738           intcall_assemble(i,&regs[i]);break;
10739         case UJUMP:
10740           ujump_assemble(i,&regs[i]);ds=1;break;
10741         case RJUMP:
10742           rjump_assemble(i,&regs[i]);ds=1;break;
10743         case CJUMP:
10744           cjump_assemble(i,&regs[i]);ds=1;break;
10745         case SJUMP:
10746           sjump_assemble(i,&regs[i]);ds=1;break;
10747         case FJUMP:
10748           fjump_assemble(i,&regs[i]);ds=1;break;
10749         case SPAN:
10750           pagespan_assemble(i,&regs[i]);break;
10751       }
10752       if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10753         literal_pool(1024);
10754       else
10755         literal_pool_jumpover(256);
10756     }
10757   }
10758   //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
10759   // If the block did not end with an unconditional branch,
10760   // add a jump to the next instruction.
10761   if(i>1) {
10762     if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
10763       assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10764       assert(i==slen);
10765       if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
10766         store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10767         if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10768           emit_loadreg(CCREG,HOST_CCREG);
10769         emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10770       }
10771       else if(!likely[i-2])
10772       {
10773         store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
10774         assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
10775       }
10776       else
10777       {
10778         store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
10779         assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
10780       }
10781       add_to_linker((int)out,start+i*4,0);
10782       emit_jmp(0);
10783     }
10784   }
10785   else
10786   {
10787     assert(i>0);
10788     assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10789     store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10790     if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10791       emit_loadreg(CCREG,HOST_CCREG);
10792     emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10793     add_to_linker((int)out,start+i*4,0);
10794     emit_jmp(0);
10795   }
10796
10797   // TODO: delay slot stubs?
10798   // Stubs
10799   for(i=0;i<stubcount;i++)
10800   {
10801     switch(stubs[i][0])
10802     {
10803       case LOADB_STUB:
10804       case LOADH_STUB:
10805       case LOADW_STUB:
10806       case LOADD_STUB:
10807       case LOADBU_STUB:
10808       case LOADHU_STUB:
10809         do_readstub(i);break;
10810       case STOREB_STUB:
10811       case STOREH_STUB:
10812       case STOREW_STUB:
10813       case STORED_STUB:
10814         do_writestub(i);break;
10815       case CC_STUB:
10816         do_ccstub(i);break;
10817       case INVCODE_STUB:
10818         do_invstub(i);break;
10819       case FP_STUB:
10820         do_cop1stub(i);break;
10821       case STORELR_STUB:
10822         do_unalignedwritestub(i);break;
10823     }
10824   }
10825
10826   if (instr_addr0_override)
10827     instr_addr[0] = instr_addr0_override;
10828
10829   /* Pass 9 - Linker */
10830   for(i=0;i<linkcount;i++)
10831   {
10832     assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
10833     literal_pool(64);
10834     if(!link_addr[i][2])
10835     {
10836       void *stub=out;
10837       void *addr=check_addr(link_addr[i][1]);
10838       emit_extjump(link_addr[i][0],link_addr[i][1]);
10839       if(addr) {
10840         set_jump_target(link_addr[i][0],(int)addr);
10841         add_link(link_addr[i][1],stub);
10842       }
10843       else set_jump_target(link_addr[i][0],(int)stub);
10844     }
10845     else
10846     {
10847       // Internal branch
10848       int target=(link_addr[i][1]-start)>>2;
10849       assert(target>=0&&target<slen);
10850       assert(instr_addr[target]);
10851       //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10852       //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
10853       //#else
10854       set_jump_target(link_addr[i][0],instr_addr[target]);
10855       //#endif
10856     }
10857   }
10858   // External Branch Targets (jump_in)
10859   if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
10860   for(i=0;i<slen;i++)
10861   {
10862     if(bt[i]||i==0)
10863     {
10864       if(instr_addr[i]) // TODO - delay slots (=null)
10865       {
10866         u_int vaddr=start+i*4;
10867         u_int page=get_page(vaddr);
10868         u_int vpage=get_vpage(vaddr);
10869         literal_pool(256);
10870         //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
10871 #ifndef FORCE32
10872         if(!requires_32bit[i])
10873 #else
10874         if(1)
10875 #endif
10876         {
10877           assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
10878           assem_debug("jump_in: %x\n",start+i*4);
10879           ll_add(jump_dirty+vpage,vaddr,(void *)out);
10880           int entry_point=do_dirty_stub(i);
10881           ll_add(jump_in+page,vaddr,(void *)entry_point);
10882           // If there was an existing entry in the hash table,
10883           // replace it with the new address.
10884           // Don't add new entries.  We'll insert the
10885           // ones that actually get used in check_addr().
10886           int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
10887           if(ht_bin[0]==vaddr) {
10888             ht_bin[1]=entry_point;
10889           }
10890           if(ht_bin[2]==vaddr) {
10891             ht_bin[3]=entry_point;
10892           }
10893         }
10894         else
10895         {
10896           u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
10897           assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
10898           assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
10899           //int entry_point=(int)out;
10900           ////assem_debug("entry_point: %x\n",entry_point);
10901           //load_regs_entry(i);
10902           //if(entry_point==(int)out)
10903           //  entry_point=instr_addr[i];
10904           //else
10905           //  emit_jmp(instr_addr[i]);
10906           //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
10907           ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
10908           int entry_point=do_dirty_stub(i);
10909           ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
10910         }
10911       }
10912     }
10913   }
10914   // Write out the literal pool if necessary
10915   literal_pool(0);
10916   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10917   // Align code
10918   if(((u_int)out)&7) emit_addnop(13);
10919   #endif
10920   assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
10921   //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
10922   memcpy(copy,source,slen*4);
10923   copy+=slen*4;
10924
10925   #ifdef __arm__
10926   __clear_cache((void *)beginning,out);
10927   #endif
10928
10929   // If we're within 256K of the end of the buffer,
10930   // start over from the beginning. (Is 256K enough?)
10931   if((int)out>BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
10932
10933   // Trap writes to any of the pages we compiled
10934   for(i=start>>12;i<=(start+slen*4)>>12;i++) {
10935     invalid_code[i]=0;
10936 #ifndef DISABLE_TLB
10937     memory_map[i]|=0x40000000;
10938     if((signed int)start>=(signed int)0xC0000000) {
10939       assert(using_tlb);
10940       j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
10941       invalid_code[j]=0;
10942       memory_map[j]|=0x40000000;
10943       //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
10944     }
10945 #endif
10946   }
10947
10948   /* Pass 10 - Free memory by expiring oldest blocks */
10949
10950   int end=((((int)out-BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
10951   while(expirep!=end)
10952   {
10953     int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
10954     int base=BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
10955     inv_debug("EXP: Phase %d\n",expirep);
10956     switch((expirep>>11)&3)
10957     {
10958       case 0:
10959         // Clear jump_in and jump_dirty
10960         ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
10961         ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
10962         ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
10963         ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
10964         break;
10965       case 1:
10966         // Clear pointers
10967         ll_kill_pointers(jump_out[expirep&2047],base,shift);
10968         ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
10969         break;
10970       case 2:
10971         // Clear hash table
10972         for(i=0;i<32;i++) {
10973           int *ht_bin=hash_table[((expirep&2047)<<5)+i];
10974           if((ht_bin[3]>>shift)==(base>>shift) ||
10975              ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
10976             inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
10977             ht_bin[2]=ht_bin[3]=-1;
10978           }
10979           if((ht_bin[1]>>shift)==(base>>shift) ||
10980              ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
10981             inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
10982             ht_bin[0]=ht_bin[2];
10983             ht_bin[1]=ht_bin[3];
10984             ht_bin[2]=ht_bin[3]=-1;
10985           }
10986         }
10987         break;
10988       case 3:
10989         // Clear jump_out
10990         ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
10991         ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
10992         break;
10993     }
10994     expirep=(expirep+1)&65535;
10995   }
10996   return 0;
10997 }
10998
10999 // vim:shiftwidth=2:expandtab