libpcsxcore/new_dynarec/new_dynarec.c

   1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
   2  *   Mupen64plus - new_dynarec.c                                           *
   3  *   Copyright (C) 2009-2011 Ari64                                         *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.          *
  19  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
  20
  21 #include <stdlib.h>
  22 #include <stdint.h> //include for uint64_t
  23 #include <assert.h>
  24 #include <sys/mman.h>
  25
  26 #include "emu_if.h" //emulator interface
  27
  28 //#define DISASM
  29 //#define assem_debug printf
  30 //#define inv_debug printf
  31 #define assem_debug(...)
  32 #define inv_debug(...)
  33
  34 #ifdef __i386__
  35 #include "assem_x86.h"
  36 #endif
  37 #ifdef __x86_64__
  38 #include "assem_x64.h"
  39 #endif
  40 #ifdef __arm__
  41 #include "assem_arm.h"
  42 #endif
  43
  44 #undef __clear_cache
  45 #define __clear_cache(start,end) msync(start, (size_t)((void*)end - (void*)start), MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE);
  46
  47
  48 #define MAXBLOCK 4096
  49 #define MAX_OUTPUT_BLOCK_SIZE 262144
  50
  51 struct regstat
  52 {
  53   signed char regmap_entry[HOST_REGS];
  54   signed char regmap[HOST_REGS];
  55   uint64_t was32;
  56   uint64_t is32;
  57   uint64_t wasdirty;
  58   uint64_t dirty;
  59   uint64_t u;
  60   uint64_t uu;
  61   u_int wasconst;
  62   u_int isconst;
  63   u_int loadedconst;             // host regs that have constants loaded
  64   u_int waswritten;              // MIPS regs that were used as store base before
  65 };
  66
  67 struct ll_entry
  68 {
  69   u_int vaddr;
  70   u_int reg32;
  71   void *addr;
  72   struct ll_entry *next;
  73 };
  74
  75   u_int start;
  76   u_int *source;
  77   u_int pagelimit;
  78   char insn[MAXBLOCK][10];
  79   u_char itype[MAXBLOCK];
  80   u_char opcode[MAXBLOCK];
  81   u_char opcode2[MAXBLOCK];
  82   u_char bt[MAXBLOCK];
  83   u_char rs1[MAXBLOCK];
  84   u_char rs2[MAXBLOCK];
  85   u_char rt1[MAXBLOCK];
  86   u_char rt2[MAXBLOCK];
  87   u_char us1[MAXBLOCK];
  88   u_char us2[MAXBLOCK];
  89   u_char dep1[MAXBLOCK];
  90   u_char dep2[MAXBLOCK];
  91   u_char lt1[MAXBLOCK];
  92   static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
  93   static uint64_t gte_rt[MAXBLOCK];
  94   static uint64_t gte_unneeded[MAXBLOCK];
  95   static u_int smrv[32]; // speculated MIPS register values
  96   static u_int smrv_strong; // mask or regs that are likely to have correct values
  97   static u_int smrv_weak; // same, but somewhat less likely
  98   static u_int smrv_strong_next; // same, but after current insn executes
  99   static u_int smrv_weak_next;
 100   int imm[MAXBLOCK];
 101   u_int ba[MAXBLOCK];
 102   char likely[MAXBLOCK];
 103   char is_ds[MAXBLOCK];
 104   char ooo[MAXBLOCK];
 105   uint64_t unneeded_reg[MAXBLOCK];
 106   uint64_t unneeded_reg_upper[MAXBLOCK];
 107   uint64_t branch_unneeded_reg[MAXBLOCK];
 108   uint64_t branch_unneeded_reg_upper[MAXBLOCK];
 109   uint64_t p32[MAXBLOCK];
 110   uint64_t pr32[MAXBLOCK];
 111   signed char regmap_pre[MAXBLOCK][HOST_REGS];
 112   static uint64_t current_constmap[HOST_REGS];
 113   static uint64_t constmap[MAXBLOCK][HOST_REGS];
 114   static struct regstat regs[MAXBLOCK];
 115   static struct regstat branch_regs[MAXBLOCK];
 116   signed char minimum_free_regs[MAXBLOCK];
 117   u_int needed_reg[MAXBLOCK];
 118   uint64_t requires_32bit[MAXBLOCK];
 119   u_int wont_dirty[MAXBLOCK];
 120   u_int will_dirty[MAXBLOCK];
 121   int ccadj[MAXBLOCK];
 122   int slen;
 123   u_int instr_addr[MAXBLOCK];
 124   u_int link_addr[MAXBLOCK][3];
 125   int linkcount;
 126   u_int stubs[MAXBLOCK*3][8];
 127   int stubcount;
 128   u_int literals[1024][2];
 129   int literalcount;
 130   int is_delayslot;
 131   int cop1_usable;
 132   u_char *out;
 133   struct ll_entry *jump_in[4096];
 134   struct ll_entry *jump_out[4096];
 135   struct ll_entry *jump_dirty[4096];
 136   u_int hash_table[65536][4]  __attribute__((aligned(16)));
 137   char shadow[1048576]  __attribute__((aligned(16)));
 138   void *copy;
 139   int expirep;
 140 #ifndef PCSX
 141   u_int using_tlb;
 142 #else
 143   static const u_int using_tlb=0;
 144 #endif
 145   int new_dynarec_did_compile;
 146   int new_dynarec_hacks;
 147   u_int stop_after_jal;
 148 #ifndef RAM_FIXED
 149   static u_int ram_offset;
 150 #else
 151   static const u_int ram_offset=0;
 152 #endif
 153   extern u_char restore_candidate[512];
 154   extern int cycle_count;
 155
 156   /* registers that may be allocated */
 157   /* 1-31 gpr */
 158 #define HIREG 32 // hi
 159 #define LOREG 33 // lo
 160 #define FSREG 34 // FPU status (FCSR)
 161 #define CSREG 35 // Coprocessor status
 162 #define CCREG 36 // Cycle count
 163 #define INVCP 37 // Pointer to invalid_code
 164 #define MMREG 38 // Pointer to memory_map
 165 #define ROREG 39 // ram offset (if rdram!=0x80000000)
 166 #define TEMPREG 40
 167 #define FTEMP 40 // FPU temporary register
 168 #define PTEMP 41 // Prefetch temporary register
 169 #define TLREG 42 // TLB mapping offset
 170 #define RHASH 43 // Return address hash
 171 #define RHTBL 44 // Return address hash table address
 172 #define RTEMP 45 // JR/JALR address register
 173 #define MAXREG 45
 174 #define AGEN1 46 // Address generation temporary register
 175 #define AGEN2 47 // Address generation temporary register
 176 #define MGEN1 48 // Maptable address generation temporary register
 177 #define MGEN2 49 // Maptable address generation temporary register
 178 #define BTREG 50 // Branch target temporary register
 179
 180   /* instruction types */
 181 #define NOP 0     // No operation
 182 #define LOAD 1    // Load
 183 #define STORE 2   // Store
 184 #define LOADLR 3  // Unaligned load
 185 #define STORELR 4 // Unaligned store
 186 #define MOV 5     // Move
 187 #define ALU 6     // Arithmetic/logic
 188 #define MULTDIV 7 // Multiply/divide
 189 #define SHIFT 8   // Shift by register
 190 #define SHIFTIMM 9// Shift by immediate
 191 #define IMM16 10  // 16-bit immediate
 192 #define RJUMP 11  // Unconditional jump to register
 193 #define UJUMP 12  // Unconditional jump
 194 #define CJUMP 13  // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
 195 #define SJUMP 14  // Conditional branch (regimm format)
 196 #define COP0 15   // Coprocessor 0
 197 #define COP1 16   // Coprocessor 1
 198 #define C1LS 17   // Coprocessor 1 load/store
 199 #define FJUMP 18  // Conditional branch (floating point)
 200 #define FLOAT 19  // Floating point unit
 201 #define FCONV 20  // Convert integer to float
 202 #define FCOMP 21  // Floating point compare (sets FSREG)
 203 #define SYSCALL 22// SYSCALL
 204 #define OTHER 23  // Other
 205 #define SPAN 24   // Branch/delay slot spans 2 pages
 206 #define NI 25     // Not implemented
 207 #define HLECALL 26// PCSX fake opcodes for HLE
 208 #define COP2 27   // Coprocessor 2 move
 209 #define C2LS 28   // Coprocessor 2 load/store
 210 #define C2OP 29   // Coprocessor 2 operation
 211 #define INTCALL 30// Call interpreter to handle rare corner cases
 212
 213   /* stubs */
 214 #define CC_STUB 1
 215 #define FP_STUB 2
 216 #define LOADB_STUB 3
 217 #define LOADH_STUB 4
 218 #define LOADW_STUB 5
 219 #define LOADD_STUB 6
 220 #define LOADBU_STUB 7
 221 #define LOADHU_STUB 8
 222 #define STOREB_STUB 9
 223 #define STOREH_STUB 10
 224 #define STOREW_STUB 11
 225 #define STORED_STUB 12
 226 #define STORELR_STUB 13
 227 #define INVCODE_STUB 14
 228
 229   /* branch codes */
 230 #define TAKEN 1
 231 #define NOTTAKEN 2
 232 #define NULLDS 3
 233
 234 // asm linkage
 235 int new_recompile_block(int addr);
 236 void *get_addr_ht(u_int vaddr);
 237 void invalidate_block(u_int block);
 238 void invalidate_addr(u_int addr);
 239 void remove_hash(int vaddr);
 240 void jump_vaddr();
 241 void dyna_linker();
 242 void dyna_linker_ds();
 243 void verify_code();
 244 void verify_code_vm();
 245 void verify_code_ds();
 246 void cc_interrupt();
 247 void fp_exception();
 248 void fp_exception_ds();
 249 void jump_syscall();
 250 void jump_syscall_hle();
 251 void jump_eret();
 252 void jump_hlecall();
 253 void jump_intcall();
 254 void new_dyna_leave();
 255
 256 // TLB
 257 void TLBWI_new();
 258 void TLBWR_new();
 259 void read_nomem_new();
 260 void read_nomemb_new();
 261 void read_nomemh_new();
 262 void read_nomemd_new();
 263 void write_nomem_new();
 264 void write_nomemb_new();
 265 void write_nomemh_new();
 266 void write_nomemd_new();
 267 void write_rdram_new();
 268 void write_rdramb_new();
 269 void write_rdramh_new();
 270 void write_rdramd_new();
 271 extern u_int memory_map[1048576];
 272
 273 // Needed by assembler
 274 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
 275 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
 276 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
 277 void load_all_regs(signed char i_regmap[]);
 278 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
 279 void load_regs_entry(int t);
 280 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
 281
 282 int tracedebug=0;
 283
 284 //#define DEBUG_CYCLE_COUNT 1
 285
 286 #define NO_CYCLE_PENALTY_THR 12
 287
 288 int cycle_multiplier; // 100 for 1.0
 289
 290 static int CLOCK_ADJUST(int x)
 291 {
 292   int s=(x>>31)|1;
 293   return (x * cycle_multiplier + s * 50) / 100;
 294 }
 295
 296 static void tlb_hacks()
 297 {
 298 #ifndef DISABLE_TLB
 299   // Goldeneye hack
 300   if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
 301   {
 302     u_int addr;
 303     int n;
 304     switch (ROM_HEADER->Country_code&0xFF)
 305     {
 306       case 0x45: // U
 307         addr=0x34b30;
 308         break;
 309       case 0x4A: // J
 310         addr=0x34b70;
 311         break;
 312       case 0x50: // E
 313         addr=0x329f0;
 314         break;
 315       default:
 316         // Unknown country code
 317         addr=0;
 318         break;
 319     }
 320     u_int rom_addr=(u_int)rom;
 321     #ifdef ROM_COPY
 322     // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
 323     // in the lower 4G of memory to use this hack.  Copy it if necessary.
 324     if((void *)rom>(void *)0xffffffff) {
 325       munmap(ROM_COPY, 67108864);
 326       if(mmap(ROM_COPY, 12582912,
 327               PROT_READ | PROT_WRITE,
 328               MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
 329               -1, 0) <= 0) {printf("mmap() failed\n");}
 330       memcpy(ROM_COPY,rom,12582912);
 331       rom_addr=(u_int)ROM_COPY;
 332     }
 333     #endif
 334     if(addr) {
 335       for(n=0x7F000;n<0x80000;n++) {
 336         memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
 337       }
 338     }
 339   }
 340 #endif
 341 }
 342
 343 static u_int get_page(u_int vaddr)
 344 {
 345 #ifndef PCSX
 346   u_int page=(vaddr^0x80000000)>>12;
 347 #else
 348   u_int page=vaddr&~0xe0000000;
 349   if (page < 0x1000000)
 350     page &= ~0x0e00000; // RAM mirrors
 351   page>>=12;
 352 #endif
 353 #ifndef DISABLE_TLB
 354   if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
 355 #endif
 356   if(page>2048) page=2048+(page&2047);
 357   return page;
 358 }
 359
 360 #ifndef PCSX
 361 static u_int get_vpage(u_int vaddr)
 362 {
 363   u_int vpage=(vaddr^0x80000000)>>12;
 364 #ifndef DISABLE_TLB
 365   if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
 366 #endif
 367   if(vpage>2048) vpage=2048+(vpage&2047);
 368   return vpage;
 369 }
 370 #else
 371 // no virtual mem in PCSX
 372 static u_int get_vpage(u_int vaddr)
 373 {
 374   return get_page(vaddr);
 375 }
 376 #endif
 377
 378 // Get address from virtual address
 379 // This is called from the recompiled JR/JALR instructions
 380 void *get_addr(u_int vaddr)
 381 {
 382   u_int page=get_page(vaddr);
 383   u_int vpage=get_vpage(vaddr);
 384   struct ll_entry *head;
 385   //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
 386   head=jump_in[page];
 387   while(head!=NULL) {
 388     if(head->vaddr==vaddr&&head->reg32==0) {
 389   //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 390       int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 391       ht_bin[3]=ht_bin[1];
 392       ht_bin[2]=ht_bin[0];
 393       ht_bin[1]=(int)head->addr;
 394       ht_bin[0]=vaddr;
 395       return head->addr;
 396     }
 397     head=head->next;
 398   }
 399   head=jump_dirty[vpage];
 400   while(head!=NULL) {
 401     if(head->vaddr==vaddr&&head->reg32==0) {
 402       //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 403       // Don't restore blocks which are about to expire from the cache
 404       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 405       if(verify_dirty(head->addr)) {
 406         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
 407         invalid_code[vaddr>>12]=0;
 408         inv_code_start=inv_code_end=~0;
 409 #ifndef DISABLE_TLB
 410         memory_map[vaddr>>12]|=0x40000000;
 411 #endif
 412         if(vpage<2048) {
 413 #ifndef DISABLE_TLB
 414           if(tlb_LUT_r[vaddr>>12]) {
 415             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
 416             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
 417           }
 418 #endif
 419           restore_candidate[vpage>>3]|=1<<(vpage&7);
 420         }
 421         else restore_candidate[page>>3]|=1<<(page&7);
 422         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 423         if(ht_bin[0]==vaddr) {
 424           ht_bin[1]=(int)head->addr; // Replace existing entry
 425         }
 426         else
 427         {
 428           ht_bin[3]=ht_bin[1];
 429           ht_bin[2]=ht_bin[0];
 430           ht_bin[1]=(int)head->addr;
 431           ht_bin[0]=vaddr;
 432         }
 433         return head->addr;
 434       }
 435     }
 436     head=head->next;
 437   }
 438   //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
 439   int r=new_recompile_block(vaddr);
 440   if(r==0) return get_addr(vaddr);
 441   // Execute in unmapped page, generate pagefault execption
 442   Status|=2;
 443   Cause=(vaddr<<31)|0x8;
 444   EPC=(vaddr&1)?vaddr-5:vaddr;
 445   BadVAddr=(vaddr&~1);
 446   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
 447   EntryHi=BadVAddr&0xFFFFE000;
 448   return get_addr_ht(0x80000000);
 449 }
 450 // Look up address in hash table first
 451 void *get_addr_ht(u_int vaddr)
 452 {
 453   //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
 454   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 455   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
 456   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
 457   return get_addr(vaddr);
 458 }
 459
 460 void *get_addr_32(u_int vaddr,u_int flags)
 461 {
 462 #ifdef FORCE32
 463   return get_addr(vaddr);
 464 #else
 465   //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
 466   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 467   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
 468   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
 469   u_int page=get_page(vaddr);
 470   u_int vpage=get_vpage(vaddr);
 471   struct ll_entry *head;
 472   head=jump_in[page];
 473   while(head!=NULL) {
 474     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
 475       //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 476       if(head->reg32==0) {
 477         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 478         if(ht_bin[0]==-1) {
 479           ht_bin[1]=(int)head->addr;
 480           ht_bin[0]=vaddr;
 481         }else if(ht_bin[2]==-1) {
 482           ht_bin[3]=(int)head->addr;
 483           ht_bin[2]=vaddr;
 484         }
 485         //ht_bin[3]=ht_bin[1];
 486         //ht_bin[2]=ht_bin[0];
 487         //ht_bin[1]=(int)head->addr;
 488         //ht_bin[0]=vaddr;
 489       }
 490       return head->addr;
 491     }
 492     head=head->next;
 493   }
 494   head=jump_dirty[vpage];
 495   while(head!=NULL) {
 496     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
 497       //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 498       // Don't restore blocks which are about to expire from the cache
 499       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 500       if(verify_dirty(head->addr)) {
 501         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
 502         invalid_code[vaddr>>12]=0;
 503         inv_code_start=inv_code_end=~0;
 504         memory_map[vaddr>>12]|=0x40000000;
 505         if(vpage<2048) {
 506 #ifndef DISABLE_TLB
 507           if(tlb_LUT_r[vaddr>>12]) {
 508             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
 509             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
 510           }
 511 #endif
 512           restore_candidate[vpage>>3]|=1<<(vpage&7);
 513         }
 514         else restore_candidate[page>>3]|=1<<(page&7);
 515         if(head->reg32==0) {
 516           int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 517           if(ht_bin[0]==-1) {
 518             ht_bin[1]=(int)head->addr;
 519             ht_bin[0]=vaddr;
 520           }else if(ht_bin[2]==-1) {
 521             ht_bin[3]=(int)head->addr;
 522             ht_bin[2]=vaddr;
 523           }
 524           //ht_bin[3]=ht_bin[1];
 525           //ht_bin[2]=ht_bin[0];
 526           //ht_bin[1]=(int)head->addr;
 527           //ht_bin[0]=vaddr;
 528         }
 529         return head->addr;
 530       }
 531     }
 532     head=head->next;
 533   }
 534   //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
 535   int r=new_recompile_block(vaddr);
 536   if(r==0) return get_addr(vaddr);
 537   // Execute in unmapped page, generate pagefault execption
 538   Status|=2;
 539   Cause=(vaddr<<31)|0x8;
 540   EPC=(vaddr&1)?vaddr-5:vaddr;
 541   BadVAddr=(vaddr&~1);
 542   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
 543   EntryHi=BadVAddr&0xFFFFE000;
 544   return get_addr_ht(0x80000000);
 545 #endif
 546 }
 547
 548 void clear_all_regs(signed char regmap[])
 549 {
 550   int hr;
 551   for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
 552 }
 553
 554 signed char get_reg(signed char regmap[],int r)
 555 {
 556   int hr;
 557   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
 558   return -1;
 559 }
 560
 561 // Find a register that is available for two consecutive cycles
 562 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
 563 {
 564   int hr;
 565   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
 566   return -1;
 567 }
 568
 569 int count_free_regs(signed char regmap[])
 570 {
 571   int count=0;
 572   int hr;
 573   for(hr=0;hr<HOST_REGS;hr++)
 574   {
 575     if(hr!=EXCLUDE_REG) {
 576       if(regmap[hr]<0) count++;
 577     }
 578   }
 579   return count;
 580 }
 581
 582 void dirty_reg(struct regstat *cur,signed char reg)
 583 {
 584   int hr;
 585   if(!reg) return;
 586   for (hr=0;hr<HOST_REGS;hr++) {
 587     if((cur->regmap[hr]&63)==reg) {
 588       cur->dirty|=1<<hr;
 589     }
 590   }
 591 }
 592
 593 // If we dirty the lower half of a 64 bit register which is now being
 594 // sign-extended, we need to dump the upper half.
 595 // Note: Do this only after completion of the instruction, because
 596 // some instructions may need to read the full 64-bit value even if
 597 // overwriting it (eg SLTI, DSRA32).
 598 static void flush_dirty_uppers(struct regstat *cur)
 599 {
 600   int hr,reg;
 601   for (hr=0;hr<HOST_REGS;hr++) {
 602     if((cur->dirty>>hr)&1) {
 603       reg=cur->regmap[hr];
 604       if(reg>=64)
 605         if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
 606     }
 607   }
 608 }
 609
 610 void set_const(struct regstat *cur,signed char reg,uint64_t value)
 611 {
 612   int hr;
 613   if(!reg) return;
 614   for (hr=0;hr<HOST_REGS;hr++) {
 615     if(cur->regmap[hr]==reg) {
 616       cur->isconst|=1<<hr;
 617       current_constmap[hr]=value;
 618     }
 619     else if((cur->regmap[hr]^64)==reg) {
 620       cur->isconst|=1<<hr;
 621       current_constmap[hr]=value>>32;
 622     }
 623   }
 624 }
 625
 626 void clear_const(struct regstat *cur,signed char reg)
 627 {
 628   int hr;
 629   if(!reg) return;
 630   for (hr=0;hr<HOST_REGS;hr++) {
 631     if((cur->regmap[hr]&63)==reg) {
 632       cur->isconst&=~(1<<hr);
 633     }
 634   }
 635 }
 636
 637 int is_const(struct regstat *cur,signed char reg)
 638 {
 639   int hr;
 640   if(reg<0) return 0;
 641   if(!reg) return 1;
 642   for (hr=0;hr<HOST_REGS;hr++) {
 643     if((cur->regmap[hr]&63)==reg) {
 644       return (cur->isconst>>hr)&1;
 645     }
 646   }
 647   return 0;
 648 }
 649 uint64_t get_const(struct regstat *cur,signed char reg)
 650 {
 651   int hr;
 652   if(!reg) return 0;
 653   for (hr=0;hr<HOST_REGS;hr++) {
 654     if(cur->regmap[hr]==reg) {
 655       return current_constmap[hr];
 656     }
 657   }
 658   printf("Unknown constant in r%d\n",reg);
 659   exit(1);
 660 }
 661
 662 // Least soon needed registers
 663 // Look at the next ten instructions and see which registers
 664 // will be used.  Try not to reallocate these.
 665 void lsn(u_char hsn[], int i, int *preferred_reg)
 666 {
 667   int j;
 668   int b=-1;
 669   for(j=0;j<9;j++)
 670   {
 671     if(i+j>=slen) {
 672       j=slen-i-1;
 673       break;
 674     }
 675     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 676     {
 677       // Don't go past an unconditonal jump
 678       j++;
 679       break;
 680     }
 681   }
 682   for(;j>=0;j--)
 683   {
 684     if(rs1[i+j]) hsn[rs1[i+j]]=j;
 685     if(rs2[i+j]) hsn[rs2[i+j]]=j;
 686     if(rt1[i+j]) hsn[rt1[i+j]]=j;
 687     if(rt2[i+j]) hsn[rt2[i+j]]=j;
 688     if(itype[i+j]==STORE || itype[i+j]==STORELR) {
 689       // Stores can allocate zero
 690       hsn[rs1[i+j]]=j;
 691       hsn[rs2[i+j]]=j;
 692     }
 693     // On some architectures stores need invc_ptr
 694     #if defined(HOST_IMM8)
 695     if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
 696       hsn[INVCP]=j;
 697     }
 698     #endif
 699     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 700     {
 701       hsn[CCREG]=j;
 702       b=j;
 703     }
 704   }
 705   if(b>=0)
 706   {
 707     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 708     {
 709       // Follow first branch
 710       int t=(ba[i+b]-start)>>2;
 711       j=7-b;if(t+j>=slen) j=slen-t-1;
 712       for(;j>=0;j--)
 713       {
 714         if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
 715         if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
 716         //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
 717         //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
 718       }
 719     }
 720     // TODO: preferred register based on backward branch
 721   }
 722   // Delay slot should preferably not overwrite branch conditions or cycle count
 723   if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
 724     if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
 725     if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
 726     hsn[CCREG]=1;
 727     // ...or hash tables
 728     hsn[RHASH]=1;
 729     hsn[RHTBL]=1;
 730   }
 731   // Coprocessor load/store needs FTEMP, even if not declared
 732   if(itype[i]==C1LS||itype[i]==C2LS) {
 733     hsn[FTEMP]=0;
 734   }
 735   // Load L/R also uses FTEMP as a temporary register
 736   if(itype[i]==LOADLR) {
 737     hsn[FTEMP]=0;
 738   }
 739   // Also SWL/SWR/SDL/SDR
 740   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
 741     hsn[FTEMP]=0;
 742   }
 743   // Don't remove the TLB registers either
 744   if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
 745     hsn[TLREG]=0;
 746   }
 747   // Don't remove the miniht registers
 748   if(itype[i]==UJUMP||itype[i]==RJUMP)
 749   {
 750     hsn[RHASH]=0;
 751     hsn[RHTBL]=0;
 752   }
 753 }
 754
 755 // We only want to allocate registers if we're going to use them again soon
 756 int needed_again(int r, int i)
 757 {
 758   int j;
 759   int b=-1;
 760   int rn=10;
 761
 762   if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
 763   {
 764     if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
 765       return 0; // Don't need any registers if exiting the block
 766   }
 767   for(j=0;j<9;j++)
 768   {
 769     if(i+j>=slen) {
 770       j=slen-i-1;
 771       break;
 772     }
 773     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 774     {
 775       // Don't go past an unconditonal jump
 776       j++;
 777       break;
 778     }
 779     if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
 780     {
 781       break;
 782     }
 783   }
 784   for(;j>=1;j--)
 785   {
 786     if(rs1[i+j]==r) rn=j;
 787     if(rs2[i+j]==r) rn=j;
 788     if((unneeded_reg[i+j]>>r)&1) rn=10;
 789     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 790     {
 791       b=j;
 792     }
 793   }
 794   /*
 795   if(b>=0)
 796   {
 797     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 798     {
 799       // Follow first branch
 800       int o=rn;
 801       int t=(ba[i+b]-start)>>2;
 802       j=7-b;if(t+j>=slen) j=slen-t-1;
 803       for(;j>=0;j--)
 804       {
 805         if(!((unneeded_reg[t+j]>>r)&1)) {
 806           if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 807           if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 808         }
 809         else rn=o;
 810       }
 811     }
 812   }*/
 813   if(rn<10) return 1;
 814   return 0;
 815 }
 816
 817 // Try to match register allocations at the end of a loop with those
 818 // at the beginning
 819 int loop_reg(int i, int r, int hr)
 820 {
 821   int j,k;
 822   for(j=0;j<9;j++)
 823   {
 824     if(i+j>=slen) {
 825       j=slen-i-1;
 826       break;
 827     }
 828     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 829     {
 830       // Don't go past an unconditonal jump
 831       j++;
 832       break;
 833     }
 834   }
 835   k=0;
 836   if(i>0){
 837     if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
 838       k--;
 839   }
 840   for(;k<j;k++)
 841   {
 842     if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
 843     if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
 844     if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
 845     {
 846       if(ba[i+k]>=start && ba[i+k]<(start+i*4))
 847       {
 848         int t=(ba[i+k]-start)>>2;
 849         int reg=get_reg(regs[t].regmap_entry,r);
 850         if(reg>=0) return reg;
 851         //reg=get_reg(regs[t+1].regmap_entry,r);
 852         //if(reg>=0) return reg;
 853       }
 854     }
 855   }
 856   return hr;
 857 }
 858
 859
 860 // Allocate every register, preserving source/target regs
 861 void alloc_all(struct regstat *cur,int i)
 862 {
 863   int hr;
 864
 865   for(hr=0;hr<HOST_REGS;hr++) {
 866     if(hr!=EXCLUDE_REG) {
 867       if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
 868          ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
 869       {
 870         cur->regmap[hr]=-1;
 871         cur->dirty&=~(1<<hr);
 872       }
 873       // Don't need zeros
 874       if((cur->regmap[hr]&63)==0)
 875       {
 876         cur->regmap[hr]=-1;
 877         cur->dirty&=~(1<<hr);
 878       }
 879     }
 880   }
 881 }
 882
 883 #ifndef FORCE32
 884 void div64(int64_t dividend,int64_t divisor)
 885 {
 886   lo=dividend/divisor;
 887   hi=dividend%divisor;
 888   //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
 889   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 890 }
 891 void divu64(uint64_t dividend,uint64_t divisor)
 892 {
 893   lo=dividend/divisor;
 894   hi=dividend%divisor;
 895   //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 896   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 897 }
 898
 899 void mult64(uint64_t m1,uint64_t m2)
 900 {
 901    unsigned long long int op1, op2, op3, op4;
 902    unsigned long long int result1, result2, result3, result4;
 903    unsigned long long int temp1, temp2, temp3, temp4;
 904    int sign = 0;
 905
 906    if (m1 < 0)
 907      {
 908     op2 = -m1;
 909     sign = 1 - sign;
 910      }
 911    else op2 = m1;
 912    if (m2 < 0)
 913      {
 914     op4 = -m2;
 915     sign = 1 - sign;
 916      }
 917    else op4 = m2;
 918
 919    op1 = op2 & 0xFFFFFFFF;
 920    op2 = (op2 >> 32) & 0xFFFFFFFF;
 921    op3 = op4 & 0xFFFFFFFF;
 922    op4 = (op4 >> 32) & 0xFFFFFFFF;
 923
 924    temp1 = op1 * op3;
 925    temp2 = (temp1 >> 32) + op1 * op4;
 926    temp3 = op2 * op3;
 927    temp4 = (temp3 >> 32) + op2 * op4;
 928
 929    result1 = temp1 & 0xFFFFFFFF;
 930    result2 = temp2 + (temp3 & 0xFFFFFFFF);
 931    result3 = (result2 >> 32) + temp4;
 932    result4 = (result3 >> 32);
 933
 934    lo = result1 | (result2 << 32);
 935    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
 936    if (sign)
 937      {
 938     hi = ~hi;
 939     if (!lo) hi++;
 940     else lo = ~lo + 1;
 941      }
 942 }
 943
 944 void multu64(uint64_t m1,uint64_t m2)
 945 {
 946    unsigned long long int op1, op2, op3, op4;
 947    unsigned long long int result1, result2, result3, result4;
 948    unsigned long long int temp1, temp2, temp3, temp4;
 949
 950    op1 = m1 & 0xFFFFFFFF;
 951    op2 = (m1 >> 32) & 0xFFFFFFFF;
 952    op3 = m2 & 0xFFFFFFFF;
 953    op4 = (m2 >> 32) & 0xFFFFFFFF;
 954
 955    temp1 = op1 * op3;
 956    temp2 = (temp1 >> 32) + op1 * op4;
 957    temp3 = op2 * op3;
 958    temp4 = (temp3 >> 32) + op2 * op4;
 959
 960    result1 = temp1 & 0xFFFFFFFF;
 961    result2 = temp2 + (temp3 & 0xFFFFFFFF);
 962    result3 = (result2 >> 32) + temp4;
 963    result4 = (result3 >> 32);
 964
 965    lo = result1 | (result2 << 32);
 966    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
 967
 968   //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 969   //                                      ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 970 }
 971
 972 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
 973 {
 974   if(bits) {
 975     original<<=64-bits;
 976     original>>=64-bits;
 977     loaded<<=bits;
 978     original|=loaded;
 979   }
 980   else original=loaded;
 981   return original;
 982 }
 983 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
 984 {
 985   if(bits^56) {
 986     original>>=64-(bits^56);
 987     original<<=64-(bits^56);
 988     loaded>>=bits^56;
 989     original|=loaded;
 990   }
 991   else original=loaded;
 992   return original;
 993 }
 994 #endif
 995
 996 #ifdef __i386__
 997 #include "assem_x86.c"
 998 #endif
 999 #ifdef __x86_64__
1000 #include "assem_x64.c"
1001 #endif
1002 #ifdef __arm__
1003 #include "assem_arm.c"
1004 #endif
1005
1006 // Add virtual address mapping to linked list
1007 void ll_add(struct ll_entry **head,int vaddr,void *addr)
1008 {
1009   struct ll_entry *new_entry;
1010   new_entry=malloc(sizeof(struct ll_entry));
1011   assert(new_entry!=NULL);
1012   new_entry->vaddr=vaddr;
1013   new_entry->reg32=0;
1014   new_entry->addr=addr;
1015   new_entry->next=*head;
1016   *head=new_entry;
1017 }
1018
1019 // Add virtual address mapping for 32-bit compiled block
1020 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
1021 {
1022   ll_add(head,vaddr,addr);
1023 #ifndef FORCE32
1024   (*head)->reg32=reg32;
1025 #endif
1026 }
1027
1028 // Check if an address is already compiled
1029 // but don't return addresses which are about to expire from the cache
1030 void *check_addr(u_int vaddr)
1031 {
1032   u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
1033   if(ht_bin[0]==vaddr) {
1034     if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1035       if(isclean(ht_bin[1])) return (void *)ht_bin[1];
1036   }
1037   if(ht_bin[2]==vaddr) {
1038     if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1039       if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1040   }
1041   u_int page=get_page(vaddr);
1042   struct ll_entry *head;
1043   head=jump_in[page];
1044   while(head!=NULL) {
1045     if(head->vaddr==vaddr&&head->reg32==0) {
1046       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1047         // Update existing entry with current address
1048         if(ht_bin[0]==vaddr) {
1049           ht_bin[1]=(int)head->addr;
1050           return head->addr;
1051         }
1052         if(ht_bin[2]==vaddr) {
1053           ht_bin[3]=(int)head->addr;
1054           return head->addr;
1055         }
1056         // Insert into hash table with low priority.
1057         // Don't evict existing entries, as they are probably
1058         // addresses that are being accessed frequently.
1059         if(ht_bin[0]==-1) {
1060           ht_bin[1]=(int)head->addr;
1061           ht_bin[0]=vaddr;
1062         }else if(ht_bin[2]==-1) {
1063           ht_bin[3]=(int)head->addr;
1064           ht_bin[2]=vaddr;
1065         }
1066         return head->addr;
1067       }
1068     }
1069     head=head->next;
1070   }
1071   return 0;
1072 }
1073
1074 void remove_hash(int vaddr)
1075 {
1076   //printf("remove hash: %x\n",vaddr);
1077   int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1078   if(ht_bin[2]==vaddr) {
1079     ht_bin[2]=ht_bin[3]=-1;
1080   }
1081   if(ht_bin[0]==vaddr) {
1082     ht_bin[0]=ht_bin[2];
1083     ht_bin[1]=ht_bin[3];
1084     ht_bin[2]=ht_bin[3]=-1;
1085   }
1086 }
1087
1088 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1089 {
1090   struct ll_entry *next;
1091   while(*head) {
1092     if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1093        ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1094     {
1095       inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1096       remove_hash((*head)->vaddr);
1097       next=(*head)->next;
1098       free(*head);
1099       *head=next;
1100     }
1101     else
1102     {
1103       head=&((*head)->next);
1104     }
1105   }
1106 }
1107
1108 // Remove all entries from linked list
1109 void ll_clear(struct ll_entry **head)
1110 {
1111   struct ll_entry *cur;
1112   struct ll_entry *next;
1113   if(cur=*head) {
1114     *head=0;
1115     while(cur) {
1116       next=cur->next;
1117       free(cur);
1118       cur=next;
1119     }
1120   }
1121 }
1122
1123 // Dereference the pointers and remove if it matches
1124 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1125 {
1126   while(head) {
1127     int ptr=get_pointer(head->addr);
1128     inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1129     if(((ptr>>shift)==(addr>>shift)) ||
1130        (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1131     {
1132       inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1133       u_int host_addr=(u_int)kill_pointer(head->addr);
1134       #ifdef __arm__
1135         needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1136       #endif
1137     }
1138     head=head->next;
1139   }
1140 }
1141
1142 // This is called when we write to a compiled block (see do_invstub)
1143 void invalidate_page(u_int page)
1144 {
1145   struct ll_entry *head;
1146   struct ll_entry *next;
1147   head=jump_in[page];
1148   jump_in[page]=0;
1149   while(head!=NULL) {
1150     inv_debug("INVALIDATE: %x\n",head->vaddr);
1151     remove_hash(head->vaddr);
1152     next=head->next;
1153     free(head);
1154     head=next;
1155   }
1156   head=jump_out[page];
1157   jump_out[page]=0;
1158   while(head!=NULL) {
1159     inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1160     u_int host_addr=(u_int)kill_pointer(head->addr);
1161     #ifdef __arm__
1162       needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1163     #endif
1164     next=head->next;
1165     free(head);
1166     head=next;
1167   }
1168 }
1169
1170 static void invalidate_block_range(u_int block, u_int first, u_int last)
1171 {
1172   u_int page=get_page(block<<12);
1173   //printf("first=%d last=%d\n",first,last);
1174   invalidate_page(page);
1175   assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1176   assert(last<page+5);
1177   // Invalidate the adjacent pages if a block crosses a 4K boundary
1178   while(first<page) {
1179     invalidate_page(first);
1180     first++;
1181   }
1182   for(first=page+1;first<last;first++) {
1183     invalidate_page(first);
1184   }
1185   #ifdef __arm__
1186     do_clear_cache();
1187   #endif
1188
1189   // Don't trap writes
1190   invalid_code[block]=1;
1191 #ifndef DISABLE_TLB
1192   // If there is a valid TLB entry for this page, remove write protect
1193   if(tlb_LUT_w[block]) {
1194     assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1195     // CHECK: Is this right?
1196     memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1197     u_int real_block=tlb_LUT_w[block]>>12;
1198     invalid_code[real_block]=1;
1199     if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1200   }
1201   else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1202 #endif
1203
1204   #ifdef USE_MINI_HT
1205   memset(mini_ht,-1,sizeof(mini_ht));
1206   #endif
1207 }
1208
1209 void invalidate_block(u_int block)
1210 {
1211   u_int page=get_page(block<<12);
1212   u_int vpage=get_vpage(block<<12);
1213   inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1214   //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1215   u_int first,last;
1216   first=last=page;
1217   struct ll_entry *head;
1218   head=jump_dirty[vpage];
1219   //printf("page=%d vpage=%d\n",page,vpage);
1220   while(head!=NULL) {
1221     u_int start,end;
1222     if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1223       get_bounds((int)head->addr,&start,&end);
1224       //printf("start: %x end: %x\n",start,end);
1225       if(page<2048&&start>=(u_int)rdram&&end<(u_int)rdram+RAM_SIZE) {
1226         if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1227           if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1228           if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1229         }
1230       }
1231 #ifndef DISABLE_TLB
1232       if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1233         if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1234           if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1235           if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1236         }
1237       }
1238 #endif
1239     }
1240     head=head->next;
1241   }
1242   invalidate_block_range(block,first,last);
1243 }
1244
1245 void invalidate_addr(u_int addr)
1246 {
1247 #ifdef PCSX
1248   //static int rhits;
1249   // this check is done by the caller
1250   //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
1251   u_int page=get_vpage(addr);
1252   if(page<2048) { // RAM
1253     struct ll_entry *head;
1254     u_int addr_min=~0, addr_max=0;
1255     u_int mask=RAM_SIZE-1;
1256     u_int addr_main=0x80000000|(addr&mask);
1257     int pg1;
1258     inv_code_start=addr_main&~0xfff;
1259     inv_code_end=addr_main|0xfff;
1260     pg1=page;
1261     if (pg1>0) {
1262       // must check previous page too because of spans..
1263       pg1--;
1264       inv_code_start-=0x1000;
1265     }
1266     for(;pg1<=page;pg1++) {
1267       for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
1268         u_int start,end;
1269         get_bounds((int)head->addr,&start,&end);
1270         if(ram_offset) {
1271           start-=ram_offset;
1272           end-=ram_offset;
1273         }
1274         if(start<=addr_main&&addr_main<end) {
1275           if(start<addr_min) addr_min=start;
1276           if(end>addr_max) addr_max=end;
1277         }
1278         else if(addr_main<start) {
1279           if(start<inv_code_end)
1280             inv_code_end=start-1;
1281         }
1282         else {
1283           if(end>inv_code_start)
1284             inv_code_start=end;
1285         }
1286       }
1287     }
1288     if (addr_min!=~0) {
1289       inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1290       inv_code_start=inv_code_end=~0;
1291       invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1292       return;
1293     }
1294     else {
1295       inv_code_start=(addr&~mask)|(inv_code_start&mask);
1296       inv_code_end=(addr&~mask)|(inv_code_end&mask);
1297       inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);
1298       return;
1299     }
1300   }
1301 #endif
1302   invalidate_block(addr>>12);
1303 }
1304
1305 // This is called when loading a save state.
1306 // Anything could have changed, so invalidate everything.
1307 void invalidate_all_pages()
1308 {
1309   u_int page,n;
1310   for(page=0;page<4096;page++)
1311     invalidate_page(page);
1312   for(page=0;page<1048576;page++)
1313     if(!invalid_code[page]) {
1314       restore_candidate[(page&2047)>>3]|=1<<(page&7);
1315       restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1316     }
1317   #ifdef __arm__
1318   __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1319   #endif
1320   #ifdef USE_MINI_HT
1321   memset(mini_ht,-1,sizeof(mini_ht));
1322   #endif
1323   #ifndef DISABLE_TLB
1324   // TLB
1325   for(page=0;page<0x100000;page++) {
1326     if(tlb_LUT_r[page]) {
1327       memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1328       if(!tlb_LUT_w[page]||!invalid_code[page])
1329         memory_map[page]|=0x40000000; // Write protect
1330     }
1331     else memory_map[page]=-1;
1332     if(page==0x80000) page=0xC0000;
1333   }
1334   tlb_hacks();
1335   #endif
1336 }
1337
1338 // Add an entry to jump_out after making a link
1339 void add_link(u_int vaddr,void *src)
1340 {
1341   u_int page=get_page(vaddr);
1342   inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1343   int *ptr=(int *)(src+4);
1344   assert((*ptr&0x0fff0000)==0x059f0000);
1345   ll_add(jump_out+page,vaddr,src);
1346   //int ptr=get_pointer(src);
1347   //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1348 }
1349
1350 // If a code block was found to be unmodified (bit was set in
1351 // restore_candidate) and it remains unmodified (bit is clear
1352 // in invalid_code) then move the entries for that 4K page from
1353 // the dirty list to the clean list.
1354 void clean_blocks(u_int page)
1355 {
1356   struct ll_entry *head;
1357   inv_debug("INV: clean_blocks page=%d\n",page);
1358   head=jump_dirty[page];
1359   while(head!=NULL) {
1360     if(!invalid_code[head->vaddr>>12]) {
1361       // Don't restore blocks which are about to expire from the cache
1362       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1363         u_int start,end;
1364         if(verify_dirty((int)head->addr)) {
1365           //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1366           u_int i;
1367           u_int inv=0;
1368           get_bounds((int)head->addr,&start,&end);
1369           if(start-(u_int)rdram<RAM_SIZE) {
1370             for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1371               inv|=invalid_code[i];
1372             }
1373           }
1374 #ifndef DISABLE_TLB
1375           if((signed int)head->vaddr>=(signed int)0xC0000000) {
1376             u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1377             //printf("addr=%x start=%x end=%x\n",addr,start,end);
1378             if(addr<start||addr>=end) inv=1;
1379           }
1380 #endif
1381           else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1382             inv=1;
1383           }
1384           if(!inv) {
1385             void * clean_addr=(void *)get_clean_addr((int)head->addr);
1386             if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1387               u_int ppage=page;
1388 #ifndef DISABLE_TLB
1389               if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1390 #endif
1391               inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1392               //printf("page=%x, addr=%x\n",page,head->vaddr);
1393               //assert(head->vaddr>>12==(page|0x80000));
1394               ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1395               int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1396               if(!head->reg32) {
1397                 if(ht_bin[0]==head->vaddr) {
1398                   ht_bin[1]=(int)clean_addr; // Replace existing entry
1399                 }
1400                 if(ht_bin[2]==head->vaddr) {
1401                   ht_bin[3]=(int)clean_addr; // Replace existing entry
1402                 }
1403               }
1404             }
1405           }
1406         }
1407       }
1408     }
1409     head=head->next;
1410   }
1411 }
1412
1413
1414 void mov_alloc(struct regstat *current,int i)
1415 {
1416   // Note: Don't need to actually alloc the source registers
1417   if((~current->is32>>rs1[i])&1) {
1418     //alloc_reg64(current,i,rs1[i]);
1419     alloc_reg64(current,i,rt1[i]);
1420     current->is32&=~(1LL<<rt1[i]);
1421   } else {
1422     //alloc_reg(current,i,rs1[i]);
1423     alloc_reg(current,i,rt1[i]);
1424     current->is32|=(1LL<<rt1[i]);
1425   }
1426   clear_const(current,rs1[i]);
1427   clear_const(current,rt1[i]);
1428   dirty_reg(current,rt1[i]);
1429 }
1430
1431 void shiftimm_alloc(struct regstat *current,int i)
1432 {
1433   if(opcode2[i]<=0x3) // SLL/SRL/SRA
1434   {
1435     if(rt1[i]) {
1436       if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1437       else lt1[i]=rs1[i];
1438       alloc_reg(current,i,rt1[i]);
1439       current->is32|=1LL<<rt1[i];
1440       dirty_reg(current,rt1[i]);
1441       if(is_const(current,rs1[i])) {
1442         int v=get_const(current,rs1[i]);
1443         if(opcode2[i]==0x00) set_const(current,rt1[i],v<<imm[i]);
1444         if(opcode2[i]==0x02) set_const(current,rt1[i],(u_int)v>>imm[i]);
1445         if(opcode2[i]==0x03) set_const(current,rt1[i],v>>imm[i]);
1446       }
1447       else clear_const(current,rt1[i]);
1448     }
1449   }
1450   else
1451   {
1452     clear_const(current,rs1[i]);
1453     clear_const(current,rt1[i]);
1454   }
1455
1456   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1457   {
1458     if(rt1[i]) {
1459       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1460       alloc_reg64(current,i,rt1[i]);
1461       current->is32&=~(1LL<<rt1[i]);
1462       dirty_reg(current,rt1[i]);
1463     }
1464   }
1465   if(opcode2[i]==0x3c) // DSLL32
1466   {
1467     if(rt1[i]) {
1468       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1469       alloc_reg64(current,i,rt1[i]);
1470       current->is32&=~(1LL<<rt1[i]);
1471       dirty_reg(current,rt1[i]);
1472     }
1473   }
1474   if(opcode2[i]==0x3e) // DSRL32
1475   {
1476     if(rt1[i]) {
1477       alloc_reg64(current,i,rs1[i]);
1478       if(imm[i]==32) {
1479         alloc_reg64(current,i,rt1[i]);
1480         current->is32&=~(1LL<<rt1[i]);
1481       } else {
1482         alloc_reg(current,i,rt1[i]);
1483         current->is32|=1LL<<rt1[i];
1484       }
1485       dirty_reg(current,rt1[i]);
1486     }
1487   }
1488   if(opcode2[i]==0x3f) // DSRA32
1489   {
1490     if(rt1[i]) {
1491       alloc_reg64(current,i,rs1[i]);
1492       alloc_reg(current,i,rt1[i]);
1493       current->is32|=1LL<<rt1[i];
1494       dirty_reg(current,rt1[i]);
1495     }
1496   }
1497 }
1498
1499 void shift_alloc(struct regstat *current,int i)
1500 {
1501   if(rt1[i]) {
1502     if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1503     {
1504       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1505       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1506       alloc_reg(current,i,rt1[i]);
1507       if(rt1[i]==rs2[i]) {
1508         alloc_reg_temp(current,i,-1);
1509         minimum_free_regs[i]=1;
1510       }
1511       current->is32|=1LL<<rt1[i];
1512     } else { // DSLLV/DSRLV/DSRAV
1513       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1514       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1515       alloc_reg64(current,i,rt1[i]);
1516       current->is32&=~(1LL<<rt1[i]);
1517       if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1518       {
1519         alloc_reg_temp(current,i,-1);
1520         minimum_free_regs[i]=1;
1521       }
1522     }
1523     clear_const(current,rs1[i]);
1524     clear_const(current,rs2[i]);
1525     clear_const(current,rt1[i]);
1526     dirty_reg(current,rt1[i]);
1527   }
1528 }
1529
1530 void alu_alloc(struct regstat *current,int i)
1531 {
1532   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1533     if(rt1[i]) {
1534       if(rs1[i]&&rs2[i]) {
1535         alloc_reg(current,i,rs1[i]);
1536         alloc_reg(current,i,rs2[i]);
1537       }
1538       else {
1539         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1540         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1541       }
1542       alloc_reg(current,i,rt1[i]);
1543     }
1544     current->is32|=1LL<<rt1[i];
1545   }
1546   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1547     if(rt1[i]) {
1548       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1549       {
1550         alloc_reg64(current,i,rs1[i]);
1551         alloc_reg64(current,i,rs2[i]);
1552         alloc_reg(current,i,rt1[i]);
1553       } else {
1554         alloc_reg(current,i,rs1[i]);
1555         alloc_reg(current,i,rs2[i]);
1556         alloc_reg(current,i,rt1[i]);
1557       }
1558     }
1559     current->is32|=1LL<<rt1[i];
1560   }
1561   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1562     if(rt1[i]) {
1563       if(rs1[i]&&rs2[i]) {
1564         alloc_reg(current,i,rs1[i]);
1565         alloc_reg(current,i,rs2[i]);
1566       }
1567       else
1568       {
1569         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1570         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1571       }
1572       alloc_reg(current,i,rt1[i]);
1573       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1574       {
1575         if(!((current->uu>>rt1[i])&1)) {
1576           alloc_reg64(current,i,rt1[i]);
1577         }
1578         if(get_reg(current->regmap,rt1[i]|64)>=0) {
1579           if(rs1[i]&&rs2[i]) {
1580             alloc_reg64(current,i,rs1[i]);
1581             alloc_reg64(current,i,rs2[i]);
1582           }
1583           else
1584           {
1585             // Is is really worth it to keep 64-bit values in registers?
1586             #ifdef NATIVE_64BIT
1587             if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1588             if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1589             #endif
1590           }
1591         }
1592         current->is32&=~(1LL<<rt1[i]);
1593       } else {
1594         current->is32|=1LL<<rt1[i];
1595       }
1596     }
1597   }
1598   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1599     if(rt1[i]) {
1600       if(rs1[i]&&rs2[i]) {
1601         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1602           alloc_reg64(current,i,rs1[i]);
1603           alloc_reg64(current,i,rs2[i]);
1604           alloc_reg64(current,i,rt1[i]);
1605         } else {
1606           alloc_reg(current,i,rs1[i]);
1607           alloc_reg(current,i,rs2[i]);
1608           alloc_reg(current,i,rt1[i]);
1609         }
1610       }
1611       else {
1612         alloc_reg(current,i,rt1[i]);
1613         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1614           // DADD used as move, or zeroing
1615           // If we have a 64-bit source, then make the target 64 bits too
1616           if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1617             if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1618             alloc_reg64(current,i,rt1[i]);
1619           } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1620             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1621             alloc_reg64(current,i,rt1[i]);
1622           }
1623           if(opcode2[i]>=0x2e&&rs2[i]) {
1624             // DSUB used as negation - 64-bit result
1625             // If we have a 32-bit register, extend it to 64 bits
1626             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1627             alloc_reg64(current,i,rt1[i]);
1628           }
1629         }
1630       }
1631       if(rs1[i]&&rs2[i]) {
1632         current->is32&=~(1LL<<rt1[i]);
1633       } else if(rs1[i]) {
1634         current->is32&=~(1LL<<rt1[i]);
1635         if((current->is32>>rs1[i])&1)
1636           current->is32|=1LL<<rt1[i];
1637       } else if(rs2[i]) {
1638         current->is32&=~(1LL<<rt1[i]);
1639         if((current->is32>>rs2[i])&1)
1640           current->is32|=1LL<<rt1[i];
1641       } else {
1642         current->is32|=1LL<<rt1[i];
1643       }
1644     }
1645   }
1646   clear_const(current,rs1[i]);
1647   clear_const(current,rs2[i]);
1648   clear_const(current,rt1[i]);
1649   dirty_reg(current,rt1[i]);
1650 }
1651
1652 void imm16_alloc(struct regstat *current,int i)
1653 {
1654   if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1655   else lt1[i]=rs1[i];
1656   if(rt1[i]) alloc_reg(current,i,rt1[i]);
1657   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1658     current->is32&=~(1LL<<rt1[i]);
1659     if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1660       // TODO: Could preserve the 32-bit flag if the immediate is zero
1661       alloc_reg64(current,i,rt1[i]);
1662       alloc_reg64(current,i,rs1[i]);
1663     }
1664     clear_const(current,rs1[i]);
1665     clear_const(current,rt1[i]);
1666   }
1667   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1668     if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1669     current->is32|=1LL<<rt1[i];
1670     clear_const(current,rs1[i]);
1671     clear_const(current,rt1[i]);
1672   }
1673   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1674     if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1675       if(rs1[i]!=rt1[i]) {
1676         if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1677         alloc_reg64(current,i,rt1[i]);
1678         current->is32&=~(1LL<<rt1[i]);
1679       }
1680     }
1681     else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1682     if(is_const(current,rs1[i])) {
1683       int v=get_const(current,rs1[i]);
1684       if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1685       if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1686       if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1687     }
1688     else clear_const(current,rt1[i]);
1689   }
1690   else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1691     if(is_const(current,rs1[i])) {
1692       int v=get_const(current,rs1[i]);
1693       set_const(current,rt1[i],v+imm[i]);
1694     }
1695     else clear_const(current,rt1[i]);
1696     current->is32|=1LL<<rt1[i];
1697   }
1698   else {
1699     set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1700     current->is32|=1LL<<rt1[i];
1701   }
1702   dirty_reg(current,rt1[i]);
1703 }
1704
1705 void load_alloc(struct regstat *current,int i)
1706 {
1707   clear_const(current,rt1[i]);
1708   //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1709   if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1710   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1711   if(rt1[i]&&!((current->u>>rt1[i])&1)) {
1712     alloc_reg(current,i,rt1[i]);
1713     assert(get_reg(current->regmap,rt1[i])>=0);
1714     if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1715     {
1716       current->is32&=~(1LL<<rt1[i]);
1717       alloc_reg64(current,i,rt1[i]);
1718     }
1719     else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1720     {
1721       current->is32&=~(1LL<<rt1[i]);
1722       alloc_reg64(current,i,rt1[i]);
1723       alloc_all(current,i);
1724       alloc_reg64(current,i,FTEMP);
1725       minimum_free_regs[i]=HOST_REGS;
1726     }
1727     else current->is32|=1LL<<rt1[i];
1728     dirty_reg(current,rt1[i]);
1729     // If using TLB, need a register for pointer to the mapping table
1730     if(using_tlb) alloc_reg(current,i,TLREG);
1731     // LWL/LWR need a temporary register for the old value
1732     if(opcode[i]==0x22||opcode[i]==0x26)
1733     {
1734       alloc_reg(current,i,FTEMP);
1735       alloc_reg_temp(current,i,-1);
1736       minimum_free_regs[i]=1;
1737     }
1738   }
1739   else
1740   {
1741     // Load to r0 or unneeded register (dummy load)
1742     // but we still need a register to calculate the address
1743     if(opcode[i]==0x22||opcode[i]==0x26)
1744     {
1745       alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1746     }
1747     // If using TLB, need a register for pointer to the mapping table
1748     if(using_tlb) alloc_reg(current,i,TLREG);
1749     alloc_reg_temp(current,i,-1);
1750     minimum_free_regs[i]=1;
1751     if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1752     {
1753       alloc_all(current,i);
1754       alloc_reg64(current,i,FTEMP);
1755       minimum_free_regs[i]=HOST_REGS;
1756     }
1757   }
1758 }
1759
1760 void store_alloc(struct regstat *current,int i)
1761 {
1762   clear_const(current,rs2[i]);
1763   if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1764   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1765   alloc_reg(current,i,rs2[i]);
1766   if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1767     alloc_reg64(current,i,rs2[i]);
1768     if(rs2[i]) alloc_reg(current,i,FTEMP);
1769   }
1770   // If using TLB, need a register for pointer to the mapping table
1771   if(using_tlb) alloc_reg(current,i,TLREG);
1772   #if defined(HOST_IMM8)
1773   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1774   else alloc_reg(current,i,INVCP);
1775   #endif
1776   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1777     alloc_reg(current,i,FTEMP);
1778   }
1779   // We need a temporary register for address generation
1780   alloc_reg_temp(current,i,-1);
1781   minimum_free_regs[i]=1;
1782 }
1783
1784 void c1ls_alloc(struct regstat *current,int i)
1785 {
1786   //clear_const(current,rs1[i]); // FIXME
1787   clear_const(current,rt1[i]);
1788   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1789   alloc_reg(current,i,CSREG); // Status
1790   alloc_reg(current,i,FTEMP);
1791   if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1792     alloc_reg64(current,i,FTEMP);
1793   }
1794   // If using TLB, need a register for pointer to the mapping table
1795   if(using_tlb) alloc_reg(current,i,TLREG);
1796   #if defined(HOST_IMM8)
1797   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1798   else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1799     alloc_reg(current,i,INVCP);
1800   #endif
1801   // We need a temporary register for address generation
1802   alloc_reg_temp(current,i,-1);
1803 }
1804
1805 void c2ls_alloc(struct regstat *current,int i)
1806 {
1807   clear_const(current,rt1[i]);
1808   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1809   alloc_reg(current,i,FTEMP);
1810   // If using TLB, need a register for pointer to the mapping table
1811   if(using_tlb) alloc_reg(current,i,TLREG);
1812   #if defined(HOST_IMM8)
1813   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1814   else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1815     alloc_reg(current,i,INVCP);
1816   #endif
1817   // We need a temporary register for address generation
1818   alloc_reg_temp(current,i,-1);
1819   minimum_free_regs[i]=1;
1820 }
1821
1822 #ifndef multdiv_alloc
1823 void multdiv_alloc(struct regstat *current,int i)
1824 {
1825   //  case 0x18: MULT
1826   //  case 0x19: MULTU
1827   //  case 0x1A: DIV
1828   //  case 0x1B: DIVU
1829   //  case 0x1C: DMULT
1830   //  case 0x1D: DMULTU
1831   //  case 0x1E: DDIV
1832   //  case 0x1F: DDIVU
1833   clear_const(current,rs1[i]);
1834   clear_const(current,rs2[i]);
1835   if(rs1[i]&&rs2[i])
1836   {
1837     if((opcode2[i]&4)==0) // 32-bit
1838     {
1839       current->u&=~(1LL<<HIREG);
1840       current->u&=~(1LL<<LOREG);
1841       alloc_reg(current,i,HIREG);
1842       alloc_reg(current,i,LOREG);
1843       alloc_reg(current,i,rs1[i]);
1844       alloc_reg(current,i,rs2[i]);
1845       current->is32|=1LL<<HIREG;
1846       current->is32|=1LL<<LOREG;
1847       dirty_reg(current,HIREG);
1848       dirty_reg(current,LOREG);
1849     }
1850     else // 64-bit
1851     {
1852       current->u&=~(1LL<<HIREG);
1853       current->u&=~(1LL<<LOREG);
1854       current->uu&=~(1LL<<HIREG);
1855       current->uu&=~(1LL<<LOREG);
1856       alloc_reg64(current,i,HIREG);
1857       //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1858       alloc_reg64(current,i,rs1[i]);
1859       alloc_reg64(current,i,rs2[i]);
1860       alloc_all(current,i);
1861       current->is32&=~(1LL<<HIREG);
1862       current->is32&=~(1LL<<LOREG);
1863       dirty_reg(current,HIREG);
1864       dirty_reg(current,LOREG);
1865       minimum_free_regs[i]=HOST_REGS;
1866     }
1867   }
1868   else
1869   {
1870     // Multiply by zero is zero.
1871     // MIPS does not have a divide by zero exception.
1872     // The result is undefined, we return zero.
1873     alloc_reg(current,i,HIREG);
1874     alloc_reg(current,i,LOREG);
1875     current->is32|=1LL<<HIREG;
1876     current->is32|=1LL<<LOREG;
1877     dirty_reg(current,HIREG);
1878     dirty_reg(current,LOREG);
1879   }
1880 }
1881 #endif
1882
1883 void cop0_alloc(struct regstat *current,int i)
1884 {
1885   if(opcode2[i]==0) // MFC0
1886   {
1887     if(rt1[i]) {
1888       clear_const(current,rt1[i]);
1889       alloc_all(current,i);
1890       alloc_reg(current,i,rt1[i]);
1891       current->is32|=1LL<<rt1[i];
1892       dirty_reg(current,rt1[i]);
1893     }
1894   }
1895   else if(opcode2[i]==4) // MTC0
1896   {
1897     if(rs1[i]){
1898       clear_const(current,rs1[i]);
1899       alloc_reg(current,i,rs1[i]);
1900       alloc_all(current,i);
1901     }
1902     else {
1903       alloc_all(current,i); // FIXME: Keep r0
1904       current->u&=~1LL;
1905       alloc_reg(current,i,0);
1906     }
1907   }
1908   else
1909   {
1910     // TLBR/TLBWI/TLBWR/TLBP/ERET
1911     assert(opcode2[i]==0x10);
1912     alloc_all(current,i);
1913   }
1914   minimum_free_regs[i]=HOST_REGS;
1915 }
1916
1917 void cop1_alloc(struct regstat *current,int i)
1918 {
1919   alloc_reg(current,i,CSREG); // Load status
1920   if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1921   {
1922     if(rt1[i]){
1923       clear_const(current,rt1[i]);
1924       if(opcode2[i]==1) {
1925         alloc_reg64(current,i,rt1[i]); // DMFC1
1926         current->is32&=~(1LL<<rt1[i]);
1927       }else{
1928         alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1929         current->is32|=1LL<<rt1[i];
1930       }
1931       dirty_reg(current,rt1[i]);
1932     }
1933     alloc_reg_temp(current,i,-1);
1934   }
1935   else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1936   {
1937     if(rs1[i]){
1938       clear_const(current,rs1[i]);
1939       if(opcode2[i]==5)
1940         alloc_reg64(current,i,rs1[i]); // DMTC1
1941       else
1942         alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1943       alloc_reg_temp(current,i,-1);
1944     }
1945     else {
1946       current->u&=~1LL;
1947       alloc_reg(current,i,0);
1948       alloc_reg_temp(current,i,-1);
1949     }
1950   }
1951   minimum_free_regs[i]=1;
1952 }
1953 void fconv_alloc(struct regstat *current,int i)
1954 {
1955   alloc_reg(current,i,CSREG); // Load status
1956   alloc_reg_temp(current,i,-1);
1957   minimum_free_regs[i]=1;
1958 }
1959 void float_alloc(struct regstat *current,int i)
1960 {
1961   alloc_reg(current,i,CSREG); // Load status
1962   alloc_reg_temp(current,i,-1);
1963   minimum_free_regs[i]=1;
1964 }
1965 void c2op_alloc(struct regstat *current,int i)
1966 {
1967   alloc_reg_temp(current,i,-1);
1968 }
1969 void fcomp_alloc(struct regstat *current,int i)
1970 {
1971   alloc_reg(current,i,CSREG); // Load status
1972   alloc_reg(current,i,FSREG); // Load flags
1973   dirty_reg(current,FSREG); // Flag will be modified
1974   alloc_reg_temp(current,i,-1);
1975   minimum_free_regs[i]=1;
1976 }
1977
1978 void syscall_alloc(struct regstat *current,int i)
1979 {
1980   alloc_cc(current,i);
1981   dirty_reg(current,CCREG);
1982   alloc_all(current,i);
1983   minimum_free_regs[i]=HOST_REGS;
1984   current->isconst=0;
1985 }
1986
1987 void delayslot_alloc(struct regstat *current,int i)
1988 {
1989   switch(itype[i]) {
1990     case UJUMP:
1991     case CJUMP:
1992     case SJUMP:
1993     case RJUMP:
1994     case FJUMP:
1995     case SYSCALL:
1996     case HLECALL:
1997     case SPAN:
1998       assem_debug("jump in the delay slot.  this shouldn't happen.\n");//exit(1);
1999       printf("Disabled speculative precompilation\n");
2000       stop_after_jal=1;
2001       break;
2002     case IMM16:
2003       imm16_alloc(current,i);
2004       break;
2005     case LOAD:
2006     case LOADLR:
2007       load_alloc(current,i);
2008       break;
2009     case STORE:
2010     case STORELR:
2011       store_alloc(current,i);
2012       break;
2013     case ALU:
2014       alu_alloc(current,i);
2015       break;
2016     case SHIFT:
2017       shift_alloc(current,i);
2018       break;
2019     case MULTDIV:
2020       multdiv_alloc(current,i);
2021       break;
2022     case SHIFTIMM:
2023       shiftimm_alloc(current,i);
2024       break;
2025     case MOV:
2026       mov_alloc(current,i);
2027       break;
2028     case COP0:
2029       cop0_alloc(current,i);
2030       break;
2031     case COP1:
2032     case COP2:
2033       cop1_alloc(current,i);
2034       break;
2035     case C1LS:
2036       c1ls_alloc(current,i);
2037       break;
2038     case C2LS:
2039       c2ls_alloc(current,i);
2040       break;
2041     case FCONV:
2042       fconv_alloc(current,i);
2043       break;
2044     case FLOAT:
2045       float_alloc(current,i);
2046       break;
2047     case FCOMP:
2048       fcomp_alloc(current,i);
2049       break;
2050     case C2OP:
2051       c2op_alloc(current,i);
2052       break;
2053   }
2054 }
2055
2056 // Special case where a branch and delay slot span two pages in virtual memory
2057 static void pagespan_alloc(struct regstat *current,int i)
2058 {
2059   current->isconst=0;
2060   current->wasconst=0;
2061   regs[i].wasconst=0;
2062   minimum_free_regs[i]=HOST_REGS;
2063   alloc_all(current,i);
2064   alloc_cc(current,i);
2065   dirty_reg(current,CCREG);
2066   if(opcode[i]==3) // JAL
2067   {
2068     alloc_reg(current,i,31);
2069     dirty_reg(current,31);
2070   }
2071   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
2072   {
2073     alloc_reg(current,i,rs1[i]);
2074     if (rt1[i]!=0) {
2075       alloc_reg(current,i,rt1[i]);
2076       dirty_reg(current,rt1[i]);
2077     }
2078   }
2079   if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
2080   {
2081     if(rs1[i]) alloc_reg(current,i,rs1[i]);
2082     if(rs2[i]) alloc_reg(current,i,rs2[i]);
2083     if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
2084     {
2085       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2086       if(rs2[i]) alloc_reg64(current,i,rs2[i]);
2087     }
2088   }
2089   else
2090   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
2091   {
2092     if(rs1[i]) alloc_reg(current,i,rs1[i]);
2093     if(!((current->is32>>rs1[i])&1))
2094     {
2095       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2096     }
2097   }
2098   else
2099   if(opcode[i]==0x11) // BC1
2100   {
2101     alloc_reg(current,i,FSREG);
2102     alloc_reg(current,i,CSREG);
2103   }
2104   //else ...
2105 }
2106
2107 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
2108 {
2109   stubs[stubcount][0]=type;
2110   stubs[stubcount][1]=addr;
2111   stubs[stubcount][2]=retaddr;
2112   stubs[stubcount][3]=a;
2113   stubs[stubcount][4]=b;
2114   stubs[stubcount][5]=c;
2115   stubs[stubcount][6]=d;
2116   stubs[stubcount][7]=e;
2117   stubcount++;
2118 }
2119
2120 // Write out a single register
2121 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2122 {
2123   int hr;
2124   for(hr=0;hr<HOST_REGS;hr++) {
2125     if(hr!=EXCLUDE_REG) {
2126       if((regmap[hr]&63)==r) {
2127         if((dirty>>hr)&1) {
2128           if(regmap[hr]<64) {
2129             emit_storereg(r,hr);
2130 #ifndef FORCE32
2131             if((is32>>regmap[hr])&1) {
2132               emit_sarimm(hr,31,hr);
2133               emit_storereg(r|64,hr);
2134             }
2135 #endif
2136           }else{
2137             emit_storereg(r|64,hr);
2138           }
2139         }
2140       }
2141     }
2142   }
2143 }
2144
2145 int mchecksum()
2146 {
2147   //if(!tracedebug) return 0;
2148   int i;
2149   int sum=0;
2150   for(i=0;i<2097152;i++) {
2151     unsigned int temp=sum;
2152     sum<<=1;
2153     sum|=(~temp)>>31;
2154     sum^=((u_int *)rdram)[i];
2155   }
2156   return sum;
2157 }
2158 int rchecksum()
2159 {
2160   int i;
2161   int sum=0;
2162   for(i=0;i<64;i++)
2163     sum^=((u_int *)reg)[i];
2164   return sum;
2165 }
2166 void rlist()
2167 {
2168   int i;
2169   printf("TRACE: ");
2170   for(i=0;i<32;i++)
2171     printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2172   printf("\n");
2173 #ifndef DISABLE_COP1
2174   printf("TRACE: ");
2175   for(i=0;i<32;i++)
2176     printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2177   printf("\n");
2178 #endif
2179 }
2180
2181 void enabletrace()
2182 {
2183   tracedebug=1;
2184 }
2185
2186 void memdebug(int i)
2187 {
2188   //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2189   //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2190   //rlist();
2191   //if(tracedebug) {
2192   //if(Count>=-2084597794) {
2193   if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2194   //if(0) {
2195     printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2196     //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2197     //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2198     rlist();
2199     #ifdef __i386__
2200     printf("TRACE: %x\n",(&i)[-1]);
2201     #endif
2202     #ifdef __arm__
2203     int j;
2204     printf("TRACE: %x \n",(&j)[10]);
2205     printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2206     #endif
2207     //fflush(stdout);
2208   }
2209   //printf("TRACE: %x\n",(&i)[-1]);
2210 }
2211
2212 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2213 {
2214   printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2215 }
2216
2217 void alu_assemble(int i,struct regstat *i_regs)
2218 {
2219   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2220     if(rt1[i]) {
2221       signed char s1,s2,t;
2222       t=get_reg(i_regs->regmap,rt1[i]);
2223       if(t>=0) {
2224         s1=get_reg(i_regs->regmap,rs1[i]);
2225         s2=get_reg(i_regs->regmap,rs2[i]);
2226         if(rs1[i]&&rs2[i]) {
2227           assert(s1>=0);
2228           assert(s2>=0);
2229           if(opcode2[i]&2) emit_sub(s1,s2,t);
2230           else emit_add(s1,s2,t);
2231         }
2232         else if(rs1[i]) {
2233           if(s1>=0) emit_mov(s1,t);
2234           else emit_loadreg(rs1[i],t);
2235         }
2236         else if(rs2[i]) {
2237           if(s2>=0) {
2238             if(opcode2[i]&2) emit_neg(s2,t);
2239             else emit_mov(s2,t);
2240           }
2241           else {
2242             emit_loadreg(rs2[i],t);
2243             if(opcode2[i]&2) emit_neg(t,t);
2244           }
2245         }
2246         else emit_zeroreg(t);
2247       }
2248     }
2249   }
2250   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2251     if(rt1[i]) {
2252       signed char s1l,s2l,s1h,s2h,tl,th;
2253       tl=get_reg(i_regs->regmap,rt1[i]);
2254       th=get_reg(i_regs->regmap,rt1[i]|64);
2255       if(tl>=0) {
2256         s1l=get_reg(i_regs->regmap,rs1[i]);
2257         s2l=get_reg(i_regs->regmap,rs2[i]);
2258         s1h=get_reg(i_regs->regmap,rs1[i]|64);
2259         s2h=get_reg(i_regs->regmap,rs2[i]|64);
2260         if(rs1[i]&&rs2[i]) {
2261           assert(s1l>=0);
2262           assert(s2l>=0);
2263           if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2264           else emit_adds(s1l,s2l,tl);
2265           if(th>=0) {
2266             #ifdef INVERTED_CARRY
2267             if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2268             #else
2269             if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2270             #endif
2271             else emit_add(s1h,s2h,th);
2272           }
2273         }
2274         else if(rs1[i]) {
2275           if(s1l>=0) emit_mov(s1l,tl);
2276           else emit_loadreg(rs1[i],tl);
2277           if(th>=0) {
2278             if(s1h>=0) emit_mov(s1h,th);
2279             else emit_loadreg(rs1[i]|64,th);
2280           }
2281         }
2282         else if(rs2[i]) {
2283           if(s2l>=0) {
2284             if(opcode2[i]&2) emit_negs(s2l,tl);
2285             else emit_mov(s2l,tl);
2286           }
2287           else {
2288             emit_loadreg(rs2[i],tl);
2289             if(opcode2[i]&2) emit_negs(tl,tl);
2290           }
2291           if(th>=0) {
2292             #ifdef INVERTED_CARRY
2293             if(s2h>=0) emit_mov(s2h,th);
2294             else emit_loadreg(rs2[i]|64,th);
2295             if(opcode2[i]&2) {
2296               emit_adcimm(-1,th); // x86 has inverted carry flag
2297               emit_not(th,th);
2298             }
2299             #else
2300             if(opcode2[i]&2) {
2301               if(s2h>=0) emit_rscimm(s2h,0,th);
2302               else {
2303                 emit_loadreg(rs2[i]|64,th);
2304                 emit_rscimm(th,0,th);
2305               }
2306             }else{
2307               if(s2h>=0) emit_mov(s2h,th);
2308               else emit_loadreg(rs2[i]|64,th);
2309             }
2310             #endif
2311           }
2312         }
2313         else {
2314           emit_zeroreg(tl);
2315           if(th>=0) emit_zeroreg(th);
2316         }
2317       }
2318     }
2319   }
2320   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2321     if(rt1[i]) {
2322       signed char s1l,s1h,s2l,s2h,t;
2323       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2324       {
2325         t=get_reg(i_regs->regmap,rt1[i]);
2326         //assert(t>=0);
2327         if(t>=0) {
2328           s1l=get_reg(i_regs->regmap,rs1[i]);
2329           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2330           s2l=get_reg(i_regs->regmap,rs2[i]);
2331           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2332           if(rs2[i]==0) // rx<r0
2333           {
2334             assert(s1h>=0);
2335             if(opcode2[i]==0x2a) // SLT
2336               emit_shrimm(s1h,31,t);
2337             else // SLTU (unsigned can not be less than zero)
2338               emit_zeroreg(t);
2339           }
2340           else if(rs1[i]==0) // r0<rx
2341           {
2342             assert(s2h>=0);
2343             if(opcode2[i]==0x2a) // SLT
2344               emit_set_gz64_32(s2h,s2l,t);
2345             else // SLTU (set if not zero)
2346               emit_set_nz64_32(s2h,s2l,t);
2347           }
2348           else {
2349             assert(s1l>=0);assert(s1h>=0);
2350             assert(s2l>=0);assert(s2h>=0);
2351             if(opcode2[i]==0x2a) // SLT
2352               emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2353             else // SLTU
2354               emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2355           }
2356         }
2357       } else {
2358         t=get_reg(i_regs->regmap,rt1[i]);
2359         //assert(t>=0);
2360         if(t>=0) {
2361           s1l=get_reg(i_regs->regmap,rs1[i]);
2362           s2l=get_reg(i_regs->regmap,rs2[i]);
2363           if(rs2[i]==0) // rx<r0
2364           {
2365             assert(s1l>=0);
2366             if(opcode2[i]==0x2a) // SLT
2367               emit_shrimm(s1l,31,t);
2368             else // SLTU (unsigned can not be less than zero)
2369               emit_zeroreg(t);
2370           }
2371           else if(rs1[i]==0) // r0<rx
2372           {
2373             assert(s2l>=0);
2374             if(opcode2[i]==0x2a) // SLT
2375               emit_set_gz32(s2l,t);
2376             else // SLTU (set if not zero)
2377               emit_set_nz32(s2l,t);
2378           }
2379           else{
2380             assert(s1l>=0);assert(s2l>=0);
2381             if(opcode2[i]==0x2a) // SLT
2382               emit_set_if_less32(s1l,s2l,t);
2383             else // SLTU
2384               emit_set_if_carry32(s1l,s2l,t);
2385           }
2386         }
2387       }
2388     }
2389   }
2390   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2391     if(rt1[i]) {
2392       signed char s1l,s1h,s2l,s2h,th,tl;
2393       tl=get_reg(i_regs->regmap,rt1[i]);
2394       th=get_reg(i_regs->regmap,rt1[i]|64);
2395       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2396       {
2397         assert(tl>=0);
2398         if(tl>=0) {
2399           s1l=get_reg(i_regs->regmap,rs1[i]);
2400           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2401           s2l=get_reg(i_regs->regmap,rs2[i]);
2402           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2403           if(rs1[i]&&rs2[i]) {
2404             assert(s1l>=0);assert(s1h>=0);
2405             assert(s2l>=0);assert(s2h>=0);
2406             if(opcode2[i]==0x24) { // AND
2407               emit_and(s1l,s2l,tl);
2408               emit_and(s1h,s2h,th);
2409             } else
2410             if(opcode2[i]==0x25) { // OR
2411               emit_or(s1l,s2l,tl);
2412               emit_or(s1h,s2h,th);
2413             } else
2414             if(opcode2[i]==0x26) { // XOR
2415               emit_xor(s1l,s2l,tl);
2416               emit_xor(s1h,s2h,th);
2417             } else
2418             if(opcode2[i]==0x27) { // NOR
2419               emit_or(s1l,s2l,tl);
2420               emit_or(s1h,s2h,th);
2421               emit_not(tl,tl);
2422               emit_not(th,th);
2423             }
2424           }
2425           else
2426           {
2427             if(opcode2[i]==0x24) { // AND
2428               emit_zeroreg(tl);
2429               emit_zeroreg(th);
2430             } else
2431             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2432               if(rs1[i]){
2433                 if(s1l>=0) emit_mov(s1l,tl);
2434                 else emit_loadreg(rs1[i],tl);
2435                 if(s1h>=0) emit_mov(s1h,th);
2436                 else emit_loadreg(rs1[i]|64,th);
2437               }
2438               else
2439               if(rs2[i]){
2440                 if(s2l>=0) emit_mov(s2l,tl);
2441                 else emit_loadreg(rs2[i],tl);
2442                 if(s2h>=0) emit_mov(s2h,th);
2443                 else emit_loadreg(rs2[i]|64,th);
2444               }
2445               else{
2446                 emit_zeroreg(tl);
2447                 emit_zeroreg(th);
2448               }
2449             } else
2450             if(opcode2[i]==0x27) { // NOR
2451               if(rs1[i]){
2452                 if(s1l>=0) emit_not(s1l,tl);
2453                 else{
2454                   emit_loadreg(rs1[i],tl);
2455                   emit_not(tl,tl);
2456                 }
2457                 if(s1h>=0) emit_not(s1h,th);
2458                 else{
2459                   emit_loadreg(rs1[i]|64,th);
2460                   emit_not(th,th);
2461                 }
2462               }
2463               else
2464               if(rs2[i]){
2465                 if(s2l>=0) emit_not(s2l,tl);
2466                 else{
2467                   emit_loadreg(rs2[i],tl);
2468                   emit_not(tl,tl);
2469                 }
2470                 if(s2h>=0) emit_not(s2h,th);
2471                 else{
2472                   emit_loadreg(rs2[i]|64,th);
2473                   emit_not(th,th);
2474                 }
2475               }
2476               else {
2477                 emit_movimm(-1,tl);
2478                 emit_movimm(-1,th);
2479               }
2480             }
2481           }
2482         }
2483       }
2484       else
2485       {
2486         // 32 bit
2487         if(tl>=0) {
2488           s1l=get_reg(i_regs->regmap,rs1[i]);
2489           s2l=get_reg(i_regs->regmap,rs2[i]);
2490           if(rs1[i]&&rs2[i]) {
2491             assert(s1l>=0);
2492             assert(s2l>=0);
2493             if(opcode2[i]==0x24) { // AND
2494               emit_and(s1l,s2l,tl);
2495             } else
2496             if(opcode2[i]==0x25) { // OR
2497               emit_or(s1l,s2l,tl);
2498             } else
2499             if(opcode2[i]==0x26) { // XOR
2500               emit_xor(s1l,s2l,tl);
2501             } else
2502             if(opcode2[i]==0x27) { // NOR
2503               emit_or(s1l,s2l,tl);
2504               emit_not(tl,tl);
2505             }
2506           }
2507           else
2508           {
2509             if(opcode2[i]==0x24) { // AND
2510               emit_zeroreg(tl);
2511             } else
2512             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2513               if(rs1[i]){
2514                 if(s1l>=0) emit_mov(s1l,tl);
2515                 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2516               }
2517               else
2518               if(rs2[i]){
2519                 if(s2l>=0) emit_mov(s2l,tl);
2520                 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2521               }
2522               else emit_zeroreg(tl);
2523             } else
2524             if(opcode2[i]==0x27) { // NOR
2525               if(rs1[i]){
2526                 if(s1l>=0) emit_not(s1l,tl);
2527                 else {
2528                   emit_loadreg(rs1[i],tl);
2529                   emit_not(tl,tl);
2530                 }
2531               }
2532               else
2533               if(rs2[i]){
2534                 if(s2l>=0) emit_not(s2l,tl);
2535                 else {
2536                   emit_loadreg(rs2[i],tl);
2537                   emit_not(tl,tl);
2538                 }
2539               }
2540               else emit_movimm(-1,tl);
2541             }
2542           }
2543         }
2544       }
2545     }
2546   }
2547 }
2548
2549 void imm16_assemble(int i,struct regstat *i_regs)
2550 {
2551   if (opcode[i]==0x0f) { // LUI
2552     if(rt1[i]) {
2553       signed char t;
2554       t=get_reg(i_regs->regmap,rt1[i]);
2555       //assert(t>=0);
2556       if(t>=0) {
2557         if(!((i_regs->isconst>>t)&1))
2558           emit_movimm(imm[i]<<16,t);
2559       }
2560     }
2561   }
2562   if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2563     if(rt1[i]) {
2564       signed char s,t;
2565       t=get_reg(i_regs->regmap,rt1[i]);
2566       s=get_reg(i_regs->regmap,rs1[i]);
2567       if(rs1[i]) {
2568         //assert(t>=0);
2569         //assert(s>=0);
2570         if(t>=0) {
2571           if(!((i_regs->isconst>>t)&1)) {
2572             if(s<0) {
2573               if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2574               emit_addimm(t,imm[i],t);
2575             }else{
2576               if(!((i_regs->wasconst>>s)&1))
2577                 emit_addimm(s,imm[i],t);
2578               else
2579                 emit_movimm(constmap[i][s]+imm[i],t);
2580             }
2581           }
2582         }
2583       } else {
2584         if(t>=0) {
2585           if(!((i_regs->isconst>>t)&1))
2586             emit_movimm(imm[i],t);
2587         }
2588       }
2589     }
2590   }
2591   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2592     if(rt1[i]) {
2593       signed char sh,sl,th,tl;
2594       th=get_reg(i_regs->regmap,rt1[i]|64);
2595       tl=get_reg(i_regs->regmap,rt1[i]);
2596       sh=get_reg(i_regs->regmap,rs1[i]|64);
2597       sl=get_reg(i_regs->regmap,rs1[i]);
2598       if(tl>=0) {
2599         if(rs1[i]) {
2600           assert(sh>=0);
2601           assert(sl>=0);
2602           if(th>=0) {
2603             emit_addimm64_32(sh,sl,imm[i],th,tl);
2604           }
2605           else {
2606             emit_addimm(sl,imm[i],tl);
2607           }
2608         } else {
2609           emit_movimm(imm[i],tl);
2610           if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2611         }
2612       }
2613     }
2614   }
2615   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2616     if(rt1[i]) {
2617       //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2618       signed char sh,sl,t;
2619       t=get_reg(i_regs->regmap,rt1[i]);
2620       sh=get_reg(i_regs->regmap,rs1[i]|64);
2621       sl=get_reg(i_regs->regmap,rs1[i]);
2622       //assert(t>=0);
2623       if(t>=0) {
2624         if(rs1[i]>0) {
2625           if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2626           if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2627             if(opcode[i]==0x0a) { // SLTI
2628               if(sl<0) {
2629                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2630                 emit_slti32(t,imm[i],t);
2631               }else{
2632                 emit_slti32(sl,imm[i],t);
2633               }
2634             }
2635             else { // SLTIU
2636               if(sl<0) {
2637                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2638                 emit_sltiu32(t,imm[i],t);
2639               }else{
2640                 emit_sltiu32(sl,imm[i],t);
2641               }
2642             }
2643           }else{ // 64-bit
2644             assert(sl>=0);
2645             if(opcode[i]==0x0a) // SLTI
2646               emit_slti64_32(sh,sl,imm[i],t);
2647             else // SLTIU
2648               emit_sltiu64_32(sh,sl,imm[i],t);
2649           }
2650         }else{
2651           // SLTI(U) with r0 is just stupid,
2652           // nonetheless examples can be found
2653           if(opcode[i]==0x0a) // SLTI
2654             if(0<imm[i]) emit_movimm(1,t);
2655             else emit_zeroreg(t);
2656           else // SLTIU
2657           {
2658             if(imm[i]) emit_movimm(1,t);
2659             else emit_zeroreg(t);
2660           }
2661         }
2662       }
2663     }
2664   }
2665   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2666     if(rt1[i]) {
2667       signed char sh,sl,th,tl;
2668       th=get_reg(i_regs->regmap,rt1[i]|64);
2669       tl=get_reg(i_regs->regmap,rt1[i]);
2670       sh=get_reg(i_regs->regmap,rs1[i]|64);
2671       sl=get_reg(i_regs->regmap,rs1[i]);
2672       if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2673         if(opcode[i]==0x0c) //ANDI
2674         {
2675           if(rs1[i]) {
2676             if(sl<0) {
2677               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2678               emit_andimm(tl,imm[i],tl);
2679             }else{
2680               if(!((i_regs->wasconst>>sl)&1))
2681                 emit_andimm(sl,imm[i],tl);
2682               else
2683                 emit_movimm(constmap[i][sl]&imm[i],tl);
2684             }
2685           }
2686           else
2687             emit_zeroreg(tl);
2688           if(th>=0) emit_zeroreg(th);
2689         }
2690         else
2691         {
2692           if(rs1[i]) {
2693             if(sl<0) {
2694               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2695             }
2696             if(th>=0) {
2697               if(sh<0) {
2698                 emit_loadreg(rs1[i]|64,th);
2699               }else{
2700                 emit_mov(sh,th);
2701               }
2702             }
2703             if(opcode[i]==0x0d) //ORI
2704             if(sl<0) {
2705               emit_orimm(tl,imm[i],tl);
2706             }else{
2707               if(!((i_regs->wasconst>>sl)&1))
2708                 emit_orimm(sl,imm[i],tl);
2709               else
2710                 emit_movimm(constmap[i][sl]|imm[i],tl);
2711             }
2712             if(opcode[i]==0x0e) //XORI
2713             if(sl<0) {
2714               emit_xorimm(tl,imm[i],tl);
2715             }else{
2716               if(!((i_regs->wasconst>>sl)&1))
2717                 emit_xorimm(sl,imm[i],tl);
2718               else
2719                 emit_movimm(constmap[i][sl]^imm[i],tl);
2720             }
2721           }
2722           else {
2723             emit_movimm(imm[i],tl);
2724             if(th>=0) emit_zeroreg(th);
2725           }
2726         }
2727       }
2728     }
2729   }
2730 }
2731
2732 void shiftimm_assemble(int i,struct regstat *i_regs)
2733 {
2734   if(opcode2[i]<=0x3) // SLL/SRL/SRA
2735   {
2736     if(rt1[i]) {
2737       signed char s,t;
2738       t=get_reg(i_regs->regmap,rt1[i]);
2739       s=get_reg(i_regs->regmap,rs1[i]);
2740       //assert(t>=0);
2741       if(t>=0&&!((i_regs->isconst>>t)&1)){
2742         if(rs1[i]==0)
2743         {
2744           emit_zeroreg(t);
2745         }
2746         else
2747         {
2748           if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2749           if(imm[i]) {
2750             if(opcode2[i]==0) // SLL
2751             {
2752               emit_shlimm(s<0?t:s,imm[i],t);
2753             }
2754             if(opcode2[i]==2) // SRL
2755             {
2756               emit_shrimm(s<0?t:s,imm[i],t);
2757             }
2758             if(opcode2[i]==3) // SRA
2759             {
2760               emit_sarimm(s<0?t:s,imm[i],t);
2761             }
2762           }else{
2763             // Shift by zero
2764             if(s>=0 && s!=t) emit_mov(s,t);
2765           }
2766         }
2767       }
2768       //emit_storereg(rt1[i],t); //DEBUG
2769     }
2770   }
2771   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2772   {
2773     if(rt1[i]) {
2774       signed char sh,sl,th,tl;
2775       th=get_reg(i_regs->regmap,rt1[i]|64);
2776       tl=get_reg(i_regs->regmap,rt1[i]);
2777       sh=get_reg(i_regs->regmap,rs1[i]|64);
2778       sl=get_reg(i_regs->regmap,rs1[i]);
2779       if(tl>=0) {
2780         if(rs1[i]==0)
2781         {
2782           emit_zeroreg(tl);
2783           if(th>=0) emit_zeroreg(th);
2784         }
2785         else
2786         {
2787           assert(sl>=0);
2788           assert(sh>=0);
2789           if(imm[i]) {
2790             if(opcode2[i]==0x38) // DSLL
2791             {
2792               if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2793               emit_shlimm(sl,imm[i],tl);
2794             }
2795             if(opcode2[i]==0x3a) // DSRL
2796             {
2797               emit_shrdimm(sl,sh,imm[i],tl);
2798               if(th>=0) emit_shrimm(sh,imm[i],th);
2799             }
2800             if(opcode2[i]==0x3b) // DSRA
2801             {
2802               emit_shrdimm(sl,sh,imm[i],tl);
2803               if(th>=0) emit_sarimm(sh,imm[i],th);
2804             }
2805           }else{
2806             // Shift by zero
2807             if(sl!=tl) emit_mov(sl,tl);
2808             if(th>=0&&sh!=th) emit_mov(sh,th);
2809           }
2810         }
2811       }
2812     }
2813   }
2814   if(opcode2[i]==0x3c) // DSLL32
2815   {
2816     if(rt1[i]) {
2817       signed char sl,tl,th;
2818       tl=get_reg(i_regs->regmap,rt1[i]);
2819       th=get_reg(i_regs->regmap,rt1[i]|64);
2820       sl=get_reg(i_regs->regmap,rs1[i]);
2821       if(th>=0||tl>=0){
2822         assert(tl>=0);
2823         assert(th>=0);
2824         assert(sl>=0);
2825         emit_mov(sl,th);
2826         emit_zeroreg(tl);
2827         if(imm[i]>32)
2828         {
2829           emit_shlimm(th,imm[i]&31,th);
2830         }
2831       }
2832     }
2833   }
2834   if(opcode2[i]==0x3e) // DSRL32
2835   {
2836     if(rt1[i]) {
2837       signed char sh,tl,th;
2838       tl=get_reg(i_regs->regmap,rt1[i]);
2839       th=get_reg(i_regs->regmap,rt1[i]|64);
2840       sh=get_reg(i_regs->regmap,rs1[i]|64);
2841       if(tl>=0){
2842         assert(sh>=0);
2843         emit_mov(sh,tl);
2844         if(th>=0) emit_zeroreg(th);
2845         if(imm[i]>32)
2846         {
2847           emit_shrimm(tl,imm[i]&31,tl);
2848         }
2849       }
2850     }
2851   }
2852   if(opcode2[i]==0x3f) // DSRA32
2853   {
2854     if(rt1[i]) {
2855       signed char sh,tl;
2856       tl=get_reg(i_regs->regmap,rt1[i]);
2857       sh=get_reg(i_regs->regmap,rs1[i]|64);
2858       if(tl>=0){
2859         assert(sh>=0);
2860         emit_mov(sh,tl);
2861         if(imm[i]>32)
2862         {
2863           emit_sarimm(tl,imm[i]&31,tl);
2864         }
2865       }
2866     }
2867   }
2868 }
2869
2870 #ifndef shift_assemble
2871 void shift_assemble(int i,struct regstat *i_regs)
2872 {
2873   printf("Need shift_assemble for this architecture.\n");
2874   exit(1);
2875 }
2876 #endif
2877
2878 void load_assemble(int i,struct regstat *i_regs)
2879 {
2880   int s,th,tl,addr,map=-1;
2881   int offset;
2882   int jaddr=0;
2883   int memtarget=0,c=0;
2884   int fastload_reg_override=0;
2885   u_int hr,reglist=0;
2886   th=get_reg(i_regs->regmap,rt1[i]|64);
2887   tl=get_reg(i_regs->regmap,rt1[i]);
2888   s=get_reg(i_regs->regmap,rs1[i]);
2889   offset=imm[i];
2890   for(hr=0;hr<HOST_REGS;hr++) {
2891     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2892   }
2893   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2894   if(s>=0) {
2895     c=(i_regs->wasconst>>s)&1;
2896     if (c) {
2897       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2898       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2899     }
2900   }
2901   //printf("load_assemble: c=%d\n",c);
2902   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2903   // FIXME: Even if the load is a NOP, we should check for pagefaults...
2904 #ifdef PCSX
2905   if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2906     ||rt1[i]==0) {
2907       // could be FIFO, must perform the read
2908       // ||dummy read
2909       assem_debug("(forced read)\n");
2910       tl=get_reg(i_regs->regmap,-1);
2911       assert(tl>=0);
2912   }
2913 #endif
2914   if(offset||s<0||c) addr=tl;
2915   else addr=s;
2916   //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2917  if(tl>=0) {
2918   //printf("load_assemble: c=%d\n",c);
2919   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2920   assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2921   reglist&=~(1<<tl);
2922   if(th>=0) reglist&=~(1<<th);
2923   if(!using_tlb) {
2924     if(!c) {
2925       #ifdef RAM_OFFSET
2926       map=get_reg(i_regs->regmap,ROREG);
2927       if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2928       #endif
2929 //#define R29_HACK 1
2930       #ifdef R29_HACK
2931       // Strmnnrmn's speed hack
2932       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2933       #endif
2934       {
2935         jaddr=emit_fastpath_cmp_jump(i,addr,&fastload_reg_override);
2936       }
2937     }
2938     else if(ram_offset&&memtarget) {
2939       emit_addimm(addr,ram_offset,HOST_TEMPREG);
2940       fastload_reg_override=HOST_TEMPREG;
2941     }
2942   }else{ // using tlb
2943     int x=0;
2944     if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2945     if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2946     map=get_reg(i_regs->regmap,TLREG);
2947     assert(map>=0);
2948     reglist&=~(1<<map);
2949     map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2950     do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2951   }
2952   int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2953   if (opcode[i]==0x20) { // LB
2954     if(!c||memtarget) {
2955       if(!dummy) {
2956         #ifdef HOST_IMM_ADDR32
2957         if(c)
2958           emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2959         else
2960         #endif
2961         {
2962           //emit_xorimm(addr,3,tl);
2963           //gen_tlb_addr_r(tl,map);
2964           //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2965           int x=0,a=tl;
2966 #ifdef BIG_ENDIAN_MIPS
2967           if(!c) emit_xorimm(addr,3,tl);
2968           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2969 #else
2970           if(!c) a=addr;
2971 #endif
2972           if(fastload_reg_override) a=fastload_reg_override;
2973
2974           emit_movsbl_indexed_tlb(x,a,map,tl);
2975         }
2976       }
2977       if(jaddr)
2978         add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2979     }
2980     else
2981       inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2982   }
2983   if (opcode[i]==0x21) { // LH
2984     if(!c||memtarget) {
2985       if(!dummy) {
2986         #ifdef HOST_IMM_ADDR32
2987         if(c)
2988           emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2989         else
2990         #endif
2991         {
2992           int x=0,a=tl;
2993 #ifdef BIG_ENDIAN_MIPS
2994           if(!c) emit_xorimm(addr,2,tl);
2995           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2996 #else
2997           if(!c) a=addr;
2998 #endif
2999           if(fastload_reg_override) a=fastload_reg_override;
3000           //#ifdef
3001           //emit_movswl_indexed_tlb(x,tl,map,tl);
3002           //else
3003           if(map>=0) {
3004             gen_tlb_addr_r(a,map);
3005             emit_movswl_indexed(x,a,tl);
3006           }else{
3007             #if 1 //def RAM_OFFSET
3008             emit_movswl_indexed(x,a,tl);
3009             #else
3010             emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
3011             #endif
3012           }
3013         }
3014       }
3015       if(jaddr)
3016         add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3017     }
3018     else
3019       inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3020   }
3021   if (opcode[i]==0x23) { // LW
3022     if(!c||memtarget) {
3023       if(!dummy) {
3024         int a=addr;
3025         if(fastload_reg_override) a=fastload_reg_override;
3026         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3027         #ifdef HOST_IMM_ADDR32
3028         if(c)
3029           emit_readword_tlb(constmap[i][s]+offset,map,tl);
3030         else
3031         #endif
3032         emit_readword_indexed_tlb(0,a,map,tl);
3033       }
3034       if(jaddr)
3035         add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3036     }
3037     else
3038       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3039   }
3040   if (opcode[i]==0x24) { // LBU
3041     if(!c||memtarget) {
3042       if(!dummy) {
3043         #ifdef HOST_IMM_ADDR32
3044         if(c)
3045           emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
3046         else
3047         #endif
3048         {
3049           //emit_xorimm(addr,3,tl);
3050           //gen_tlb_addr_r(tl,map);
3051           //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
3052           int x=0,a=tl;
3053 #ifdef BIG_ENDIAN_MIPS
3054           if(!c) emit_xorimm(addr,3,tl);
3055           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3056 #else
3057           if(!c) a=addr;
3058 #endif
3059           if(fastload_reg_override) a=fastload_reg_override;
3060
3061           emit_movzbl_indexed_tlb(x,a,map,tl);
3062         }
3063       }
3064       if(jaddr)
3065         add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3066     }
3067     else
3068       inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3069   }
3070   if (opcode[i]==0x25) { // LHU
3071     if(!c||memtarget) {
3072       if(!dummy) {
3073         #ifdef HOST_IMM_ADDR32
3074         if(c)
3075           emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
3076         else
3077         #endif
3078         {
3079           int x=0,a=tl;
3080 #ifdef BIG_ENDIAN_MIPS
3081           if(!c) emit_xorimm(addr,2,tl);
3082           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3083 #else
3084           if(!c) a=addr;
3085 #endif
3086           if(fastload_reg_override) a=fastload_reg_override;
3087           //#ifdef
3088           //emit_movzwl_indexed_tlb(x,tl,map,tl);
3089           //#else
3090           if(map>=0) {
3091             gen_tlb_addr_r(a,map);
3092             emit_movzwl_indexed(x,a,tl);
3093           }else{
3094             #if 1 //def RAM_OFFSET
3095             emit_movzwl_indexed(x,a,tl);
3096             #else
3097             emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
3098             #endif
3099           }
3100         }
3101       }
3102       if(jaddr)
3103         add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3104     }
3105     else
3106       inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3107   }
3108   if (opcode[i]==0x27) { // LWU
3109     assert(th>=0);
3110     if(!c||memtarget) {
3111       if(!dummy) {
3112         int a=addr;
3113         if(fastload_reg_override) a=fastload_reg_override;
3114         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3115         #ifdef HOST_IMM_ADDR32
3116         if(c)
3117           emit_readword_tlb(constmap[i][s]+offset,map,tl);
3118         else
3119         #endif
3120         emit_readword_indexed_tlb(0,a,map,tl);
3121       }
3122       if(jaddr)
3123         add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3124     }
3125     else {
3126       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3127     }
3128     emit_zeroreg(th);
3129   }
3130   if (opcode[i]==0x37) { // LD
3131     if(!c||memtarget) {
3132       if(!dummy) {
3133         int a=addr;
3134         if(fastload_reg_override) a=fastload_reg_override;
3135         //gen_tlb_addr_r(tl,map);
3136         //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3137         //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3138         #ifdef HOST_IMM_ADDR32
3139         if(c)
3140           emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3141         else
3142         #endif
3143         emit_readdword_indexed_tlb(0,a,map,th,tl);
3144       }
3145       if(jaddr)
3146         add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3147     }
3148     else
3149       inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3150   }
3151  }
3152   //emit_storereg(rt1[i],tl); // DEBUG
3153   //if(opcode[i]==0x23)
3154   //if(opcode[i]==0x24)
3155   //if(opcode[i]==0x23||opcode[i]==0x24)
3156   /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3157   {
3158     //emit_pusha();
3159     save_regs(0x100f);
3160         emit_readword((int)&last_count,ECX);
3161         #ifdef __i386__
3162         if(get_reg(i_regs->regmap,CCREG)<0)
3163           emit_loadreg(CCREG,HOST_CCREG);
3164         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3165         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3166         emit_writeword(HOST_CCREG,(int)&Count);
3167         #endif
3168         #ifdef __arm__
3169         if(get_reg(i_regs->regmap,CCREG)<0)
3170           emit_loadreg(CCREG,0);
3171         else
3172           emit_mov(HOST_CCREG,0);
3173         emit_add(0,ECX,0);
3174         emit_addimm(0,2*ccadj[i],0);
3175         emit_writeword(0,(int)&Count);
3176         #endif
3177     emit_call((int)memdebug);
3178     //emit_popa();
3179     restore_regs(0x100f);
3180   }/**/
3181 }
3182
3183 #ifndef loadlr_assemble
3184 void loadlr_assemble(int i,struct regstat *i_regs)
3185 {
3186   printf("Need loadlr_assemble for this architecture.\n");
3187   exit(1);
3188 }
3189 #endif
3190
3191 void store_assemble(int i,struct regstat *i_regs)
3192 {
3193   int s,th,tl,map=-1;
3194   int addr,temp;
3195   int offset;
3196   int jaddr=0,jaddr2,type;
3197   int memtarget=0,c=0;
3198   int agr=AGEN1+(i&1);
3199   int faststore_reg_override=0;
3200   u_int hr,reglist=0;
3201   th=get_reg(i_regs->regmap,rs2[i]|64);
3202   tl=get_reg(i_regs->regmap,rs2[i]);
3203   s=get_reg(i_regs->regmap,rs1[i]);
3204   temp=get_reg(i_regs->regmap,agr);
3205   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3206   offset=imm[i];
3207   if(s>=0) {
3208     c=(i_regs->wasconst>>s)&1;
3209     if(c) {
3210       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3211       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3212     }
3213   }
3214   assert(tl>=0);
3215   assert(temp>=0);
3216   for(hr=0;hr<HOST_REGS;hr++) {
3217     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3218   }
3219   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3220   if(offset||s<0||c) addr=temp;
3221   else addr=s;
3222   if(!using_tlb) {
3223     if(!c) {
3224       #ifndef PCSX
3225       #ifdef R29_HACK
3226       // Strmnnrmn's speed hack
3227       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3228       #endif
3229       emit_cmpimm(addr,RAM_SIZE);
3230       #ifdef DESTRUCTIVE_SHIFT
3231       if(s==addr) emit_mov(s,temp);
3232       #endif
3233       #ifdef R29_HACK
3234       memtarget=1;
3235       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3236       #endif
3237       {
3238         jaddr=(int)out;
3239         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3240         // Hint to branch predictor that the branch is unlikely to be taken
3241         if(rs1[i]>=28)
3242           emit_jno_unlikely(0);
3243         else
3244         #endif
3245         emit_jno(0);
3246       }
3247       #else
3248         jaddr=emit_fastpath_cmp_jump(i,addr,&faststore_reg_override);
3249       #endif
3250     }
3251     else if(ram_offset&&memtarget) {
3252       emit_addimm(addr,ram_offset,HOST_TEMPREG);
3253       faststore_reg_override=HOST_TEMPREG;
3254     }
3255   }else{ // using tlb
3256     int x=0;
3257     if (opcode[i]==0x28) x=3; // SB
3258     if (opcode[i]==0x29) x=2; // SH
3259     map=get_reg(i_regs->regmap,TLREG);
3260     assert(map>=0);
3261     reglist&=~(1<<map);
3262     map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3263     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3264   }
3265
3266   if (opcode[i]==0x28) { // SB
3267     if(!c||memtarget) {
3268       int x=0,a=temp;
3269 #ifdef BIG_ENDIAN_MIPS
3270       if(!c) emit_xorimm(addr,3,temp);
3271       else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3272 #else
3273       if(!c) a=addr;
3274 #endif
3275       if(faststore_reg_override) a=faststore_reg_override;
3276       //gen_tlb_addr_w(temp,map);
3277       //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3278       emit_writebyte_indexed_tlb(tl,x,a,map,a);
3279     }
3280     type=STOREB_STUB;
3281   }
3282   if (opcode[i]==0x29) { // SH
3283     if(!c||memtarget) {
3284       int x=0,a=temp;
3285 #ifdef BIG_ENDIAN_MIPS
3286       if(!c) emit_xorimm(addr,2,temp);
3287       else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3288 #else
3289       if(!c) a=addr;
3290 #endif
3291       if(faststore_reg_override) a=faststore_reg_override;
3292       //#ifdef
3293       //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3294       //#else
3295       if(map>=0) {
3296         gen_tlb_addr_w(a,map);
3297         emit_writehword_indexed(tl,x,a);
3298       }else
3299         //emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
3300         emit_writehword_indexed(tl,x,a);
3301     }
3302     type=STOREH_STUB;
3303   }
3304   if (opcode[i]==0x2B) { // SW
3305     if(!c||memtarget) {
3306       int a=addr;
3307       if(faststore_reg_override) a=faststore_reg_override;
3308       //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3309       emit_writeword_indexed_tlb(tl,0,a,map,temp);
3310     }
3311     type=STOREW_STUB;
3312   }
3313   if (opcode[i]==0x3F) { // SD
3314     if(!c||memtarget) {
3315       int a=addr;
3316       if(faststore_reg_override) a=faststore_reg_override;
3317       if(rs2[i]) {
3318         assert(th>=0);
3319         //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3320         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3321         emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
3322       }else{
3323         // Store zero
3324         //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3325         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3326         emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
3327       }
3328     }
3329     type=STORED_STUB;
3330   }
3331 #ifdef PCSX
3332   if(jaddr) {
3333     // PCSX store handlers don't check invcode again
3334     reglist|=1<<addr;
3335     add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3336     jaddr=0;
3337   }
3338 #endif
3339   if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3340     if(!c||memtarget) {
3341       #ifdef DESTRUCTIVE_SHIFT
3342       // The x86 shift operation is 'destructive'; it overwrites the
3343       // source register, so we need to make a copy first and use that.
3344       addr=temp;
3345       #endif
3346       #if defined(HOST_IMM8)
3347       int ir=get_reg(i_regs->regmap,INVCP);
3348       assert(ir>=0);
3349       emit_cmpmem_indexedsr12_reg(ir,addr,1);
3350       #else
3351       emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3352       #endif
3353       #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3354       emit_callne(invalidate_addr_reg[addr]);
3355       #else
3356       jaddr2=(int)out;
3357       emit_jne(0);
3358       add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3359       #endif
3360     }
3361   }
3362   u_int addr_val=constmap[i][s]+offset;
3363   if(jaddr) {
3364     add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3365   } else if(c&&!memtarget) {
3366     inline_writestub(type,i,addr_val,i_regs->regmap,rs2[i],ccadj[i],reglist);
3367   }
3368   // basic current block modification detection..
3369   // not looking back as that should be in mips cache already
3370   if(c&&start+i*4<addr_val&&addr_val<start+slen*4) {
3371     printf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4);
3372     assert(i_regs->regmap==regs[i].regmap); // not delay slot
3373     if(i_regs->regmap==regs[i].regmap) {
3374       load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
3375       wb_dirtys(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty);
3376       emit_movimm(start+i*4+4,0);
3377       emit_writeword(0,(int)&pcaddr);
3378       emit_jmp((int)do_interrupt);
3379     }
3380   }
3381   //if(opcode[i]==0x2B || opcode[i]==0x3F)
3382   //if(opcode[i]==0x2B || opcode[i]==0x28)
3383   //if(opcode[i]==0x2B || opcode[i]==0x29)
3384   //if(opcode[i]==0x2B)
3385   /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3386   {
3387     #ifdef __i386__
3388     emit_pusha();
3389     #endif
3390     #ifdef __arm__
3391     save_regs(0x100f);
3392     #endif
3393         emit_readword((int)&last_count,ECX);
3394         #ifdef __i386__
3395         if(get_reg(i_regs->regmap,CCREG)<0)
3396           emit_loadreg(CCREG,HOST_CCREG);
3397         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3398         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3399         emit_writeword(HOST_CCREG,(int)&Count);
3400         #endif
3401         #ifdef __arm__
3402         if(get_reg(i_regs->regmap,CCREG)<0)
3403           emit_loadreg(CCREG,0);
3404         else
3405           emit_mov(HOST_CCREG,0);
3406         emit_add(0,ECX,0);
3407         emit_addimm(0,2*ccadj[i],0);
3408         emit_writeword(0,(int)&Count);
3409         #endif
3410     emit_call((int)memdebug);
3411     #ifdef __i386__
3412     emit_popa();
3413     #endif
3414     #ifdef __arm__
3415     restore_regs(0x100f);
3416     #endif
3417   }/**/
3418 }
3419
3420 void storelr_assemble(int i,struct regstat *i_regs)
3421 {
3422   int s,th,tl;
3423   int temp;
3424   int temp2;
3425   int offset;
3426   int jaddr=0,jaddr2;
3427   int case1,case2,case3;
3428   int done0,done1,done2;
3429   int memtarget=0,c=0;
3430   int agr=AGEN1+(i&1);
3431   u_int hr,reglist=0;
3432   th=get_reg(i_regs->regmap,rs2[i]|64);
3433   tl=get_reg(i_regs->regmap,rs2[i]);
3434   s=get_reg(i_regs->regmap,rs1[i]);
3435   temp=get_reg(i_regs->regmap,agr);
3436   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3437   offset=imm[i];
3438   if(s>=0) {
3439     c=(i_regs->isconst>>s)&1;
3440     if(c) {
3441       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3442       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3443     }
3444   }
3445   assert(tl>=0);
3446   for(hr=0;hr<HOST_REGS;hr++) {
3447     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3448   }
3449   assert(temp>=0);
3450   if(!using_tlb) {
3451     if(!c) {
3452       emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3453       if(!offset&&s!=temp) emit_mov(s,temp);
3454       jaddr=(int)out;
3455       emit_jno(0);
3456     }
3457     else
3458     {
3459       if(!memtarget||!rs1[i]) {
3460         jaddr=(int)out;
3461         emit_jmp(0);
3462       }
3463     }
3464     #ifdef RAM_OFFSET
3465     int map=get_reg(i_regs->regmap,ROREG);
3466     if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3467     gen_tlb_addr_w(temp,map);
3468     #else
3469     if((u_int)rdram!=0x80000000)
3470       emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3471     #endif
3472   }else{ // using tlb
3473     int map=get_reg(i_regs->regmap,TLREG);
3474     assert(map>=0);
3475     reglist&=~(1<<map);
3476     map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3477     if(!c&&!offset&&s>=0) emit_mov(s,temp);
3478     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3479     if(!jaddr&&!memtarget) {
3480       jaddr=(int)out;
3481       emit_jmp(0);
3482     }
3483     gen_tlb_addr_w(temp,map);
3484   }
3485
3486   if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3487     temp2=get_reg(i_regs->regmap,FTEMP);
3488     if(!rs2[i]) temp2=th=tl;
3489   }
3490
3491 #ifndef BIG_ENDIAN_MIPS
3492     emit_xorimm(temp,3,temp);
3493 #endif
3494   emit_testimm(temp,2);
3495   case2=(int)out;
3496   emit_jne(0);
3497   emit_testimm(temp,1);
3498   case1=(int)out;
3499   emit_jne(0);
3500   // 0
3501   if (opcode[i]==0x2A) { // SWL
3502     emit_writeword_indexed(tl,0,temp);
3503   }
3504   if (opcode[i]==0x2E) { // SWR
3505     emit_writebyte_indexed(tl,3,temp);
3506   }
3507   if (opcode[i]==0x2C) { // SDL
3508     emit_writeword_indexed(th,0,temp);
3509     if(rs2[i]) emit_mov(tl,temp2);
3510   }
3511   if (opcode[i]==0x2D) { // SDR
3512     emit_writebyte_indexed(tl,3,temp);
3513     if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3514   }
3515   done0=(int)out;
3516   emit_jmp(0);
3517   // 1
3518   set_jump_target(case1,(int)out);
3519   if (opcode[i]==0x2A) { // SWL
3520     // Write 3 msb into three least significant bytes
3521     if(rs2[i]) emit_rorimm(tl,8,tl);
3522     emit_writehword_indexed(tl,-1,temp);
3523     if(rs2[i]) emit_rorimm(tl,16,tl);
3524     emit_writebyte_indexed(tl,1,temp);
3525     if(rs2[i]) emit_rorimm(tl,8,tl);
3526   }
3527   if (opcode[i]==0x2E) { // SWR
3528     // Write two lsb into two most significant bytes
3529     emit_writehword_indexed(tl,1,temp);
3530   }
3531   if (opcode[i]==0x2C) { // SDL
3532     if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3533     // Write 3 msb into three least significant bytes
3534     if(rs2[i]) emit_rorimm(th,8,th);
3535     emit_writehword_indexed(th,-1,temp);
3536     if(rs2[i]) emit_rorimm(th,16,th);
3537     emit_writebyte_indexed(th,1,temp);
3538     if(rs2[i]) emit_rorimm(th,8,th);
3539   }
3540   if (opcode[i]==0x2D) { // SDR
3541     if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3542     // Write two lsb into two most significant bytes
3543     emit_writehword_indexed(tl,1,temp);
3544   }
3545   done1=(int)out;
3546   emit_jmp(0);
3547   // 2
3548   set_jump_target(case2,(int)out);
3549   emit_testimm(temp,1);
3550   case3=(int)out;
3551   emit_jne(0);
3552   if (opcode[i]==0x2A) { // SWL
3553     // Write two msb into two least significant bytes
3554     if(rs2[i]) emit_rorimm(tl,16,tl);
3555     emit_writehword_indexed(tl,-2,temp);
3556     if(rs2[i]) emit_rorimm(tl,16,tl);
3557   }
3558   if (opcode[i]==0x2E) { // SWR
3559     // Write 3 lsb into three most significant bytes
3560     emit_writebyte_indexed(tl,-1,temp);
3561     if(rs2[i]) emit_rorimm(tl,8,tl);
3562     emit_writehword_indexed(tl,0,temp);
3563     if(rs2[i]) emit_rorimm(tl,24,tl);
3564   }
3565   if (opcode[i]==0x2C) { // SDL
3566     if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3567     // Write two msb into two least significant bytes
3568     if(rs2[i]) emit_rorimm(th,16,th);
3569     emit_writehword_indexed(th,-2,temp);
3570     if(rs2[i]) emit_rorimm(th,16,th);
3571   }
3572   if (opcode[i]==0x2D) { // SDR
3573     if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3574     // Write 3 lsb into three most significant bytes
3575     emit_writebyte_indexed(tl,-1,temp);
3576     if(rs2[i]) emit_rorimm(tl,8,tl);
3577     emit_writehword_indexed(tl,0,temp);
3578     if(rs2[i]) emit_rorimm(tl,24,tl);
3579   }
3580   done2=(int)out;
3581   emit_jmp(0);
3582   // 3
3583   set_jump_target(case3,(int)out);
3584   if (opcode[i]==0x2A) { // SWL
3585     // Write msb into least significant byte
3586     if(rs2[i]) emit_rorimm(tl,24,tl);
3587     emit_writebyte_indexed(tl,-3,temp);
3588     if(rs2[i]) emit_rorimm(tl,8,tl);
3589   }
3590   if (opcode[i]==0x2E) { // SWR
3591     // Write entire word
3592     emit_writeword_indexed(tl,-3,temp);
3593   }
3594   if (opcode[i]==0x2C) { // SDL
3595     if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3596     // Write msb into least significant byte
3597     if(rs2[i]) emit_rorimm(th,24,th);
3598     emit_writebyte_indexed(th,-3,temp);
3599     if(rs2[i]) emit_rorimm(th,8,th);
3600   }
3601   if (opcode[i]==0x2D) { // SDR
3602     if(rs2[i]) emit_mov(th,temp2);
3603     // Write entire word
3604     emit_writeword_indexed(tl,-3,temp);
3605   }
3606   set_jump_target(done0,(int)out);
3607   set_jump_target(done1,(int)out);
3608   set_jump_target(done2,(int)out);
3609   if (opcode[i]==0x2C) { // SDL
3610     emit_testimm(temp,4);
3611     done0=(int)out;
3612     emit_jne(0);
3613     emit_andimm(temp,~3,temp);
3614     emit_writeword_indexed(temp2,4,temp);
3615     set_jump_target(done0,(int)out);
3616   }
3617   if (opcode[i]==0x2D) { // SDR
3618     emit_testimm(temp,4);
3619     done0=(int)out;
3620     emit_jeq(0);
3621     emit_andimm(temp,~3,temp);
3622     emit_writeword_indexed(temp2,-4,temp);
3623     set_jump_target(done0,(int)out);
3624   }
3625   if(!c||!memtarget)
3626     add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
3627   if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3628     #ifdef RAM_OFFSET
3629     int map=get_reg(i_regs->regmap,ROREG);
3630     if(map<0) map=HOST_TEMPREG;
3631     gen_orig_addr_w(temp,map);
3632     #else
3633     emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3634     #endif
3635     #if defined(HOST_IMM8)
3636     int ir=get_reg(i_regs->regmap,INVCP);
3637     assert(ir>=0);
3638     emit_cmpmem_indexedsr12_reg(ir,temp,1);
3639     #else
3640     emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3641     #endif
3642     #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3643     emit_callne(invalidate_addr_reg[temp]);
3644     #else
3645     jaddr2=(int)out;
3646     emit_jne(0);
3647     add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3648     #endif
3649   }
3650   /*
3651     emit_pusha();
3652     //save_regs(0x100f);
3653         emit_readword((int)&last_count,ECX);
3654         if(get_reg(i_regs->regmap,CCREG)<0)
3655           emit_loadreg(CCREG,HOST_CCREG);
3656         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3657         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3658         emit_writeword(HOST_CCREG,(int)&Count);
3659     emit_call((int)memdebug);
3660     emit_popa();
3661     //restore_regs(0x100f);
3662   /**/
3663 }
3664
3665 void c1ls_assemble(int i,struct regstat *i_regs)
3666 {
3667 #ifndef DISABLE_COP1
3668   int s,th,tl;
3669   int temp,ar;
3670   int map=-1;
3671   int offset;
3672   int c=0;
3673   int jaddr,jaddr2=0,jaddr3,type;
3674   int agr=AGEN1+(i&1);
3675   u_int hr,reglist=0;
3676   th=get_reg(i_regs->regmap,FTEMP|64);
3677   tl=get_reg(i_regs->regmap,FTEMP);
3678   s=get_reg(i_regs->regmap,rs1[i]);
3679   temp=get_reg(i_regs->regmap,agr);
3680   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3681   offset=imm[i];
3682   assert(tl>=0);
3683   assert(rs1[i]>0);
3684   assert(temp>=0);
3685   for(hr=0;hr<HOST_REGS;hr++) {
3686     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3687   }
3688   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3689   if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3690   {
3691     // Loads use a temporary register which we need to save
3692     reglist|=1<<temp;
3693   }
3694   if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3695     ar=temp;
3696   else // LWC1/LDC1
3697     ar=tl;
3698   //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3699   //else c=(i_regs->wasconst>>s)&1;
3700   if(s>=0) c=(i_regs->wasconst>>s)&1;
3701   // Check cop1 unusable
3702   if(!cop1_usable) {
3703     signed char rs=get_reg(i_regs->regmap,CSREG);
3704     assert(rs>=0);
3705     emit_testimm(rs,0x20000000);
3706     jaddr=(int)out;
3707     emit_jeq(0);
3708     add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3709     cop1_usable=1;
3710   }
3711   if (opcode[i]==0x39) { // SWC1 (get float address)
3712     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],tl);
3713   }
3714   if (opcode[i]==0x3D) { // SDC1 (get double address)
3715     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],tl);
3716   }
3717   // Generate address + offset
3718   if(!using_tlb) {
3719     if(!c)
3720       emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3721   }
3722   else
3723   {
3724     map=get_reg(i_regs->regmap,TLREG);
3725     assert(map>=0);
3726     reglist&=~(1<<map);
3727     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3728       map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3729     }
3730     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3731       map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3732     }
3733   }
3734   if (opcode[i]==0x39) { // SWC1 (read float)
3735     emit_readword_indexed(0,tl,tl);
3736   }
3737   if (opcode[i]==0x3D) { // SDC1 (read double)
3738     emit_readword_indexed(4,tl,th);
3739     emit_readword_indexed(0,tl,tl);
3740   }
3741   if (opcode[i]==0x31) { // LWC1 (get target address)
3742     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],temp);
3743   }
3744   if (opcode[i]==0x35) { // LDC1 (get target address)
3745     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],temp);
3746   }
3747   if(!using_tlb) {
3748     if(!c) {
3749       jaddr2=(int)out;
3750       emit_jno(0);
3751     }
3752     else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
3753       jaddr2=(int)out;
3754       emit_jmp(0); // inline_readstub/inline_writestub?  Very rare case
3755     }
3756     #ifdef DESTRUCTIVE_SHIFT
3757     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3758       if(!offset&&!c&&s>=0) emit_mov(s,ar);
3759     }
3760     #endif
3761   }else{
3762     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3763       do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3764     }
3765     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3766       do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3767     }
3768   }
3769   if (opcode[i]==0x31) { // LWC1
3770     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3771     //gen_tlb_addr_r(ar,map);
3772     //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3773     #ifdef HOST_IMM_ADDR32
3774     if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3775     else
3776     #endif
3777     emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3778     type=LOADW_STUB;
3779   }
3780   if (opcode[i]==0x35) { // LDC1
3781     assert(th>=0);
3782     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3783     //gen_tlb_addr_r(ar,map);
3784     //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3785     //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3786     #ifdef HOST_IMM_ADDR32
3787     if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3788     else
3789     #endif
3790     emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3791     type=LOADD_STUB;
3792   }
3793   if (opcode[i]==0x39) { // SWC1
3794     //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3795     emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3796     type=STOREW_STUB;
3797   }
3798   if (opcode[i]==0x3D) { // SDC1
3799     assert(th>=0);
3800     //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3801     //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3802     emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3803     type=STORED_STUB;
3804   }
3805   if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3806     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3807       #ifndef DESTRUCTIVE_SHIFT
3808       temp=offset||c||s<0?ar:s;
3809       #endif
3810       #if defined(HOST_IMM8)
3811       int ir=get_reg(i_regs->regmap,INVCP);
3812       assert(ir>=0);
3813       emit_cmpmem_indexedsr12_reg(ir,temp,1);
3814       #else
3815       emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3816       #endif
3817       #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3818       emit_callne(invalidate_addr_reg[temp]);
3819       #else
3820       jaddr3=(int)out;
3821       emit_jne(0);
3822       add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3823       #endif
3824     }
3825   }
3826   if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3827   if (opcode[i]==0x31) { // LWC1 (write float)
3828     emit_writeword_indexed(tl,0,temp);
3829   }
3830   if (opcode[i]==0x35) { // LDC1 (write double)
3831     emit_writeword_indexed(th,4,temp);
3832     emit_writeword_indexed(tl,0,temp);
3833   }
3834   //if(opcode[i]==0x39)
3835   /*if(opcode[i]==0x39||opcode[i]==0x31)
3836   {
3837     emit_pusha();
3838         emit_readword((int)&last_count,ECX);
3839         if(get_reg(i_regs->regmap,CCREG)<0)
3840           emit_loadreg(CCREG,HOST_CCREG);
3841         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3842         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3843         emit_writeword(HOST_CCREG,(int)&Count);
3844     emit_call((int)memdebug);
3845     emit_popa();
3846   }/**/
3847 #else
3848   cop1_unusable(i, i_regs);
3849 #endif
3850 }
3851
3852 void c2ls_assemble(int i,struct regstat *i_regs)
3853 {
3854   int s,tl;
3855   int ar;
3856   int offset;
3857   int memtarget=0,c=0;
3858   int jaddr2=0,jaddr3,type;
3859   int agr=AGEN1+(i&1);
3860   int fastio_reg_override=0;
3861   u_int hr,reglist=0;
3862   u_int copr=(source[i]>>16)&0x1f;
3863   s=get_reg(i_regs->regmap,rs1[i]);
3864   tl=get_reg(i_regs->regmap,FTEMP);
3865   offset=imm[i];
3866   assert(rs1[i]>0);
3867   assert(tl>=0);
3868   assert(!using_tlb);
3869
3870   for(hr=0;hr<HOST_REGS;hr++) {
3871     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3872   }
3873   if(i_regs->regmap[HOST_CCREG]==CCREG)
3874     reglist&=~(1<<HOST_CCREG);
3875
3876   // get the address
3877   if (opcode[i]==0x3a) { // SWC2
3878     ar=get_reg(i_regs->regmap,agr);
3879     if(ar<0) ar=get_reg(i_regs->regmap,-1);
3880     reglist|=1<<ar;
3881   } else { // LWC2
3882     ar=tl;
3883   }
3884   if(s>=0) c=(i_regs->wasconst>>s)&1;
3885   memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3886   if (!offset&&!c&&s>=0) ar=s;
3887   assert(ar>=0);
3888
3889   if (opcode[i]==0x3a) { // SWC2
3890     cop2_get_dreg(copr,tl,HOST_TEMPREG);
3891     type=STOREW_STUB;
3892   }
3893   else
3894     type=LOADW_STUB;
3895
3896   if(c&&!memtarget) {
3897     jaddr2=(int)out;
3898     emit_jmp(0); // inline_readstub/inline_writestub?
3899   }
3900   else {
3901     if(!c) {
3902       jaddr2=emit_fastpath_cmp_jump(i,ar,&fastio_reg_override);
3903     }
3904     else if(ram_offset&&memtarget) {
3905       emit_addimm(ar,ram_offset,HOST_TEMPREG);
3906       fastio_reg_override=HOST_TEMPREG;
3907     }
3908     if (opcode[i]==0x32) { // LWC2
3909       #ifdef HOST_IMM_ADDR32
3910       if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3911       else
3912       #endif
3913       int a=ar;
3914       if(fastio_reg_override) a=fastio_reg_override;
3915       emit_readword_indexed(0,a,tl);
3916     }
3917     if (opcode[i]==0x3a) { // SWC2
3918       #ifdef DESTRUCTIVE_SHIFT
3919       if(!offset&&!c&&s>=0) emit_mov(s,ar);
3920       #endif
3921       int a=ar;
3922       if(fastio_reg_override) a=fastio_reg_override;
3923       emit_writeword_indexed(tl,0,a);
3924     }
3925   }
3926   if(jaddr2)
3927     add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3928   if(opcode[i]==0x3a) // SWC2
3929   if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3930 #if defined(HOST_IMM8)
3931     int ir=get_reg(i_regs->regmap,INVCP);
3932     assert(ir>=0);
3933     emit_cmpmem_indexedsr12_reg(ir,ar,1);
3934 #else
3935     emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3936 #endif
3937     #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3938     emit_callne(invalidate_addr_reg[ar]);
3939     #else
3940     jaddr3=(int)out;
3941     emit_jne(0);
3942     add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3943     #endif
3944   }
3945   if (opcode[i]==0x32) { // LWC2
3946     cop2_put_dreg(copr,tl,HOST_TEMPREG);
3947   }
3948 }
3949
3950 #ifndef multdiv_assemble
3951 void multdiv_assemble(int i,struct regstat *i_regs)
3952 {
3953   printf("Need multdiv_assemble for this architecture.\n");
3954   exit(1);
3955 }
3956 #endif
3957
3958 void mov_assemble(int i,struct regstat *i_regs)
3959 {
3960   //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3961   //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3962   if(rt1[i]) {
3963     signed char sh,sl,th,tl;
3964     th=get_reg(i_regs->regmap,rt1[i]|64);
3965     tl=get_reg(i_regs->regmap,rt1[i]);
3966     //assert(tl>=0);
3967     if(tl>=0) {
3968       sh=get_reg(i_regs->regmap,rs1[i]|64);
3969       sl=get_reg(i_regs->regmap,rs1[i]);
3970       if(sl>=0) emit_mov(sl,tl);
3971       else emit_loadreg(rs1[i],tl);
3972       if(th>=0) {
3973         if(sh>=0) emit_mov(sh,th);
3974         else emit_loadreg(rs1[i]|64,th);
3975       }
3976     }
3977   }
3978 }
3979
3980 #ifndef fconv_assemble
3981 void fconv_assemble(int i,struct regstat *i_regs)
3982 {
3983   printf("Need fconv_assemble for this architecture.\n");
3984   exit(1);
3985 }
3986 #endif
3987
3988 #if 0
3989 void float_assemble(int i,struct regstat *i_regs)
3990 {
3991   printf("Need float_assemble for this architecture.\n");
3992   exit(1);
3993 }
3994 #endif
3995
3996 void syscall_assemble(int i,struct regstat *i_regs)
3997 {
3998   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3999   assert(ccreg==HOST_CCREG);
4000   assert(!is_delayslot);
4001   emit_movimm(start+i*4,EAX); // Get PC
4002   emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // CHECK: is this right?  There should probably be an extra cycle...
4003   emit_jmp((int)jump_syscall_hle); // XXX
4004 }
4005
4006 void hlecall_assemble(int i,struct regstat *i_regs)
4007 {
4008   signed char ccreg=get_reg(i_regs->regmap,CCREG);
4009   assert(ccreg==HOST_CCREG);
4010   assert(!is_delayslot);
4011   emit_movimm(start+i*4+4,0); // Get PC
4012   emit_movimm((int)psxHLEt[source[i]&7],1);
4013   emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // XXX
4014   emit_jmp((int)jump_hlecall);
4015 }
4016
4017 void intcall_assemble(int i,struct regstat *i_regs)
4018 {
4019   signed char ccreg=get_reg(i_regs->regmap,CCREG);
4020   assert(ccreg==HOST_CCREG);
4021   assert(!is_delayslot);
4022   emit_movimm(start+i*4,0); // Get PC
4023   emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
4024   emit_jmp((int)jump_intcall);
4025 }
4026
4027 void ds_assemble(int i,struct regstat *i_regs)
4028 {
4029   speculate_register_values(i);
4030   is_delayslot=1;
4031   switch(itype[i]) {
4032     case ALU:
4033       alu_assemble(i,i_regs);break;
4034     case IMM16:
4035       imm16_assemble(i,i_regs);break;
4036     case SHIFT:
4037       shift_assemble(i,i_regs);break;
4038     case SHIFTIMM:
4039       shiftimm_assemble(i,i_regs);break;
4040     case LOAD:
4041       load_assemble(i,i_regs);break;
4042     case LOADLR:
4043       loadlr_assemble(i,i_regs);break;
4044     case STORE:
4045       store_assemble(i,i_regs);break;
4046     case STORELR:
4047       storelr_assemble(i,i_regs);break;
4048     case COP0:
4049       cop0_assemble(i,i_regs);break;
4050     case COP1:
4051       cop1_assemble(i,i_regs);break;
4052     case C1LS:
4053       c1ls_assemble(i,i_regs);break;
4054     case COP2:
4055       cop2_assemble(i,i_regs);break;
4056     case C2LS:
4057       c2ls_assemble(i,i_regs);break;
4058     case C2OP:
4059       c2op_assemble(i,i_regs);break;
4060     case FCONV:
4061       fconv_assemble(i,i_regs);break;
4062     case FLOAT:
4063       float_assemble(i,i_regs);break;
4064     case FCOMP:
4065       fcomp_assemble(i,i_regs);break;
4066     case MULTDIV:
4067       multdiv_assemble(i,i_regs);break;
4068     case MOV:
4069       mov_assemble(i,i_regs);break;
4070     case SYSCALL:
4071     case HLECALL:
4072     case INTCALL:
4073     case SPAN:
4074     case UJUMP:
4075     case RJUMP:
4076     case CJUMP:
4077     case SJUMP:
4078     case FJUMP:
4079       printf("Jump in the delay slot.  This is probably a bug.\n");
4080   }
4081   is_delayslot=0;
4082 }
4083
4084 // Is the branch target a valid internal jump?
4085 int internal_branch(uint64_t i_is32,int addr)
4086 {
4087   if(addr&1) return 0; // Indirect (register) jump
4088   if(addr>=start && addr<start+slen*4-4)
4089   {
4090     int t=(addr-start)>>2;
4091     // Delay slots are not valid branch targets
4092     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4093     // 64 -> 32 bit transition requires a recompile
4094     /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
4095     {
4096       if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
4097       else printf("optimizable: yes\n");
4098     }*/
4099     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4100 #ifndef FORCE32
4101     if(requires_32bit[t]&~i_is32) return 0;
4102     else
4103 #endif
4104       return 1;
4105   }
4106   return 0;
4107 }
4108
4109 #ifndef wb_invalidate
4110 void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
4111   uint64_t u,uint64_t uu)
4112 {
4113   int hr;
4114   for(hr=0;hr<HOST_REGS;hr++) {
4115     if(hr!=EXCLUDE_REG) {
4116       if(pre[hr]!=entry[hr]) {
4117         if(pre[hr]>=0) {
4118           if((dirty>>hr)&1) {
4119             if(get_reg(entry,pre[hr])<0) {
4120               if(pre[hr]<64) {
4121                 if(!((u>>pre[hr])&1)) {
4122                   emit_storereg(pre[hr],hr);
4123                   if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
4124                     emit_sarimm(hr,31,hr);
4125                     emit_storereg(pre[hr]|64,hr);
4126                   }
4127                 }
4128               }else{
4129                 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
4130                   emit_storereg(pre[hr],hr);
4131                 }
4132               }
4133             }
4134           }
4135         }
4136       }
4137     }
4138   }
4139   // Move from one register to another (no writeback)
4140   for(hr=0;hr<HOST_REGS;hr++) {
4141     if(hr!=EXCLUDE_REG) {
4142       if(pre[hr]!=entry[hr]) {
4143         if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
4144           int nr;
4145           if((nr=get_reg(entry,pre[hr]))>=0) {
4146             emit_mov(hr,nr);
4147           }
4148         }
4149       }
4150     }
4151   }
4152 }
4153 #endif
4154
4155 // Load the specified registers
4156 // This only loads the registers given as arguments because
4157 // we don't want to load things that will be overwritten
4158 void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
4159 {
4160   int hr;
4161   // Load 32-bit regs
4162   for(hr=0;hr<HOST_REGS;hr++) {
4163     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4164       if(entry[hr]!=regmap[hr]) {
4165         if(regmap[hr]==rs1||regmap[hr]==rs2)
4166         {
4167           if(regmap[hr]==0) {
4168             emit_zeroreg(hr);
4169           }
4170           else
4171           {
4172             emit_loadreg(regmap[hr],hr);
4173           }
4174         }
4175       }
4176     }
4177   }
4178   //Load 64-bit regs
4179   for(hr=0;hr<HOST_REGS;hr++) {
4180     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4181       if(entry[hr]!=regmap[hr]) {
4182         if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
4183         {
4184           assert(regmap[hr]!=64);
4185           if((is32>>(regmap[hr]&63))&1) {
4186             int lr=get_reg(regmap,regmap[hr]-64);
4187             if(lr>=0)
4188               emit_sarimm(lr,31,hr);
4189             else
4190               emit_loadreg(regmap[hr],hr);
4191           }
4192           else
4193           {
4194             emit_loadreg(regmap[hr],hr);
4195           }
4196         }
4197       }
4198     }
4199   }
4200 }
4201
4202 // Load registers prior to the start of a loop
4203 // so that they are not loaded within the loop
4204 static void loop_preload(signed char pre[],signed char entry[])
4205 {
4206   int hr;
4207   for(hr=0;hr<HOST_REGS;hr++) {
4208     if(hr!=EXCLUDE_REG) {
4209       if(pre[hr]!=entry[hr]) {
4210         if(entry[hr]>=0) {
4211           if(get_reg(pre,entry[hr])<0) {
4212             assem_debug("loop preload:\n");
4213             //printf("loop preload: %d\n",hr);
4214             if(entry[hr]==0) {
4215               emit_zeroreg(hr);
4216             }
4217             else if(entry[hr]<TEMPREG)
4218             {
4219               emit_loadreg(entry[hr],hr);
4220             }
4221             else if(entry[hr]-64<TEMPREG)
4222             {
4223               emit_loadreg(entry[hr],hr);
4224             }
4225           }
4226         }
4227       }
4228     }
4229   }
4230 }
4231
4232 // Generate address for load/store instruction
4233 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
4234 void address_generation(int i,struct regstat *i_regs,signed char entry[])
4235 {
4236   if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
4237     int ra=-1;
4238     int agr=AGEN1+(i&1);
4239     int mgr=MGEN1+(i&1);
4240     if(itype[i]==LOAD) {
4241       ra=get_reg(i_regs->regmap,rt1[i]);
4242       if(ra<0) ra=get_reg(i_regs->regmap,-1);
4243       assert(ra>=0);
4244     }
4245     if(itype[i]==LOADLR) {
4246       ra=get_reg(i_regs->regmap,FTEMP);
4247     }
4248     if(itype[i]==STORE||itype[i]==STORELR) {
4249       ra=get_reg(i_regs->regmap,agr);
4250       if(ra<0) ra=get_reg(i_regs->regmap,-1);
4251     }
4252     if(itype[i]==C1LS||itype[i]==C2LS) {
4253       if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
4254         ra=get_reg(i_regs->regmap,FTEMP);
4255       else { // SWC1/SDC1/SWC2/SDC2
4256         ra=get_reg(i_regs->regmap,agr);
4257         if(ra<0) ra=get_reg(i_regs->regmap,-1);
4258       }
4259     }
4260     int rs=get_reg(i_regs->regmap,rs1[i]);
4261     int rm=get_reg(i_regs->regmap,TLREG);
4262     if(ra>=0) {
4263       int offset=imm[i];
4264       int c=(i_regs->wasconst>>rs)&1;
4265       if(rs1[i]==0) {
4266         // Using r0 as a base address
4267         /*if(rm>=0) {
4268           if(!entry||entry[rm]!=mgr) {
4269             generate_map_const(offset,rm);
4270           } // else did it in the previous cycle
4271         }*/
4272         if(!entry||entry[ra]!=agr) {
4273           if (opcode[i]==0x22||opcode[i]==0x26) {
4274             emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4275           }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4276             emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4277           }else{
4278             emit_movimm(offset,ra);
4279           }
4280         } // else did it in the previous cycle
4281       }
4282       else if(rs<0) {
4283         if(!entry||entry[ra]!=rs1[i])
4284           emit_loadreg(rs1[i],ra);
4285         //if(!entry||entry[ra]!=rs1[i])
4286         //  printf("poor load scheduling!\n");
4287       }
4288       else if(c) {
4289 #ifndef DISABLE_TLB
4290         if(rm>=0) {
4291           if(!entry||entry[rm]!=mgr) {
4292             if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
4293               // Stores to memory go thru the mapper to detect self-modifying
4294               // code, loads don't.
4295               if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
4296                  (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
4297                 generate_map_const(constmap[i][rs]+offset,rm);
4298             }else{
4299               if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
4300                 generate_map_const(constmap[i][rs]+offset,rm);
4301             }
4302           }
4303         }
4304 #endif
4305         if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
4306           if(!entry||entry[ra]!=agr) {
4307             if (opcode[i]==0x22||opcode[i]==0x26) {
4308               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4309             }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4310               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4311             }else{
4312               #ifdef HOST_IMM_ADDR32
4313               if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4314                  (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4315               #endif
4316               emit_movimm(constmap[i][rs]+offset,ra);
4317               regs[i].loadedconst|=1<<ra;
4318             }
4319           } // else did it in the previous cycle
4320         } // else load_consts already did it
4321       }
4322       if(offset&&!c&&rs1[i]) {
4323         if(rs>=0) {
4324           emit_addimm(rs,offset,ra);
4325         }else{
4326           emit_addimm(ra,offset,ra);
4327         }
4328       }
4329     }
4330   }
4331   // Preload constants for next instruction
4332   if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
4333     int agr,ra;
4334     #if !defined(HOST_IMM_ADDR32) && !defined(DISABLE_TLB)
4335     // Mapper entry
4336     agr=MGEN1+((i+1)&1);
4337     ra=get_reg(i_regs->regmap,agr);
4338     if(ra>=0) {
4339       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4340       int offset=imm[i+1];
4341       int c=(regs[i+1].wasconst>>rs)&1;
4342       if(c) {
4343         if(itype[i+1]==STORE||itype[i+1]==STORELR
4344            ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
4345           // Stores to memory go thru the mapper to detect self-modifying
4346           // code, loads don't.
4347           if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4348              (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
4349             generate_map_const(constmap[i+1][rs]+offset,ra);
4350         }else{
4351           if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4352             generate_map_const(constmap[i+1][rs]+offset,ra);
4353         }
4354       }
4355       /*else if(rs1[i]==0) {
4356         generate_map_const(offset,ra);
4357       }*/
4358     }
4359     #endif
4360     // Actual address
4361     agr=AGEN1+((i+1)&1);
4362     ra=get_reg(i_regs->regmap,agr);
4363     if(ra>=0) {
4364       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4365       int offset=imm[i+1];
4366       int c=(regs[i+1].wasconst>>rs)&1;
4367       if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4368         if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4369           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4370         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4371           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4372         }else{
4373           #ifdef HOST_IMM_ADDR32
4374           if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4375              (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4376           #endif
4377           emit_movimm(constmap[i+1][rs]+offset,ra);
4378           regs[i+1].loadedconst|=1<<ra;
4379         }
4380       }
4381       else if(rs1[i+1]==0) {
4382         // Using r0 as a base address
4383         if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4384           emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4385         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4386           emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4387         }else{
4388           emit_movimm(offset,ra);
4389         }
4390       }
4391     }
4392   }
4393 }
4394
4395 int get_final_value(int hr, int i, int *value)
4396 {
4397   int reg=regs[i].regmap[hr];
4398   while(i<slen-1) {
4399     if(regs[i+1].regmap[hr]!=reg) break;
4400     if(!((regs[i+1].isconst>>hr)&1)) break;
4401     if(bt[i+1]) break;
4402     i++;
4403   }
4404   if(i<slen-1) {
4405     if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4406       *value=constmap[i][hr];
4407       return 1;
4408     }
4409     if(!bt[i+1]) {
4410       if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4411         // Load in delay slot, out-of-order execution
4412         if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4413         {
4414           #ifdef HOST_IMM_ADDR32
4415           if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4416           #endif
4417           // Precompute load address
4418           *value=constmap[i][hr]+imm[i+2];
4419           return 1;
4420         }
4421       }
4422       if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4423       {
4424         #ifdef HOST_IMM_ADDR32
4425         if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4426         #endif
4427         // Precompute load address
4428         *value=constmap[i][hr]+imm[i+1];
4429         //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4430         return 1;
4431       }
4432     }
4433   }
4434   *value=constmap[i][hr];
4435   //printf("c=%x\n",(int)constmap[i][hr]);
4436   if(i==slen-1) return 1;
4437   if(reg<64) {
4438     return !((unneeded_reg[i+1]>>reg)&1);
4439   }else{
4440     return !((unneeded_reg_upper[i+1]>>reg)&1);
4441   }
4442 }
4443
4444 // Load registers with known constants
4445 void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4446 {
4447   int hr,hr2;
4448   // propagate loaded constant flags
4449   if(i==0||bt[i])
4450     regs[i].loadedconst=0;
4451   else {
4452     for(hr=0;hr<HOST_REGS;hr++) {
4453       if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((regs[i-1].isconst>>hr)&1)&&pre[hr]==regmap[hr]
4454          &&regmap[hr]==regs[i-1].regmap[hr]&&((regs[i-1].loadedconst>>hr)&1))
4455       {
4456         regs[i].loadedconst|=1<<hr;
4457       }
4458     }
4459   }
4460   // Load 32-bit regs
4461   for(hr=0;hr<HOST_REGS;hr++) {
4462     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4463       //if(entry[hr]!=regmap[hr]) {
4464       if(!((regs[i].loadedconst>>hr)&1)) {
4465         if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4466           int value,similar=0;
4467           if(get_final_value(hr,i,&value)) {
4468             // see if some other register has similar value
4469             for(hr2=0;hr2<HOST_REGS;hr2++) {
4470               if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
4471                 if(is_similar_value(value,constmap[i][hr2])) {
4472                   similar=1;
4473                   break;
4474                 }
4475               }
4476             }
4477             if(similar) {
4478               int value2;
4479               if(get_final_value(hr2,i,&value2)) // is this needed?
4480                 emit_movimm_from(value2,hr2,value,hr);
4481               else
4482                 emit_movimm(value,hr);
4483             }
4484             else if(value==0) {
4485               emit_zeroreg(hr);
4486             }
4487             else {
4488               emit_movimm(value,hr);
4489             }
4490           }
4491           regs[i].loadedconst|=1<<hr;
4492         }
4493       }
4494     }
4495   }
4496   // Load 64-bit regs
4497   for(hr=0;hr<HOST_REGS;hr++) {
4498     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4499       //if(entry[hr]!=regmap[hr]) {
4500       if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4501         if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4502           if((is32>>(regmap[hr]&63))&1) {
4503             int lr=get_reg(regmap,regmap[hr]-64);
4504             assert(lr>=0);
4505             emit_sarimm(lr,31,hr);
4506           }
4507           else
4508           {
4509             int value;
4510             if(get_final_value(hr,i,&value)) {
4511               if(value==0) {
4512                 emit_zeroreg(hr);
4513               }
4514               else {
4515                 emit_movimm(value,hr);
4516               }
4517             }
4518           }
4519         }
4520       }
4521     }
4522   }
4523 }
4524 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4525 {
4526   int hr;
4527   // Load 32-bit regs
4528   for(hr=0;hr<HOST_REGS;hr++) {
4529     if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4530       if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4531         int value=constmap[i][hr];
4532         if(value==0) {
4533           emit_zeroreg(hr);
4534         }
4535         else {
4536           emit_movimm(value,hr);
4537         }
4538       }
4539     }
4540   }
4541   // Load 64-bit regs
4542   for(hr=0;hr<HOST_REGS;hr++) {
4543     if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4544       if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4545         if((is32>>(regmap[hr]&63))&1) {
4546           int lr=get_reg(regmap,regmap[hr]-64);
4547           assert(lr>=0);
4548           emit_sarimm(lr,31,hr);
4549         }
4550         else
4551         {
4552           int value=constmap[i][hr];
4553           if(value==0) {
4554             emit_zeroreg(hr);
4555           }
4556           else {
4557             emit_movimm(value,hr);
4558           }
4559         }
4560       }
4561     }
4562   }
4563 }
4564
4565 // Write out all dirty registers (except cycle count)
4566 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4567 {
4568   int hr;
4569   for(hr=0;hr<HOST_REGS;hr++) {
4570     if(hr!=EXCLUDE_REG) {
4571       if(i_regmap[hr]>0) {
4572         if(i_regmap[hr]!=CCREG) {
4573           if((i_dirty>>hr)&1) {
4574             if(i_regmap[hr]<64) {
4575               emit_storereg(i_regmap[hr],hr);
4576 #ifndef FORCE32
4577               if( ((i_is32>>i_regmap[hr])&1) ) {
4578                 #ifdef DESTRUCTIVE_WRITEBACK
4579                 emit_sarimm(hr,31,hr);
4580                 emit_storereg(i_regmap[hr]|64,hr);
4581                 #else
4582                 emit_sarimm(hr,31,HOST_TEMPREG);
4583                 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4584                 #endif
4585               }
4586 #endif
4587             }else{
4588               if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4589                 emit_storereg(i_regmap[hr],hr);
4590               }
4591             }
4592           }
4593         }
4594       }
4595     }
4596   }
4597 }
4598 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4599 // This writes the registers not written by store_regs_bt
4600 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4601 {
4602   int hr;
4603   int t=(addr-start)>>2;
4604   for(hr=0;hr<HOST_REGS;hr++) {
4605     if(hr!=EXCLUDE_REG) {
4606       if(i_regmap[hr]>0) {
4607         if(i_regmap[hr]!=CCREG) {
4608           if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4609             if((i_dirty>>hr)&1) {
4610               if(i_regmap[hr]<64) {
4611                 emit_storereg(i_regmap[hr],hr);
4612 #ifndef FORCE32
4613                 if( ((i_is32>>i_regmap[hr])&1) ) {
4614                   #ifdef DESTRUCTIVE_WRITEBACK
4615                   emit_sarimm(hr,31,hr);
4616                   emit_storereg(i_regmap[hr]|64,hr);
4617                   #else
4618                   emit_sarimm(hr,31,HOST_TEMPREG);
4619                   emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4620                   #endif
4621                 }
4622 #endif
4623               }else{
4624                 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4625                   emit_storereg(i_regmap[hr],hr);
4626                 }
4627               }
4628             }
4629           }
4630         }
4631       }
4632     }
4633   }
4634 }
4635
4636 // Load all registers (except cycle count)
4637 void load_all_regs(signed char i_regmap[])
4638 {
4639   int hr;
4640   for(hr=0;hr<HOST_REGS;hr++) {
4641     if(hr!=EXCLUDE_REG) {
4642       if(i_regmap[hr]==0) {
4643         emit_zeroreg(hr);
4644       }
4645       else
4646       if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4647       {
4648         emit_loadreg(i_regmap[hr],hr);
4649       }
4650     }
4651   }
4652 }
4653
4654 // Load all current registers also needed by next instruction
4655 void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4656 {
4657   int hr;
4658   for(hr=0;hr<HOST_REGS;hr++) {
4659     if(hr!=EXCLUDE_REG) {
4660       if(get_reg(next_regmap,i_regmap[hr])>=0) {
4661         if(i_regmap[hr]==0) {
4662           emit_zeroreg(hr);
4663         }
4664         else
4665         if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4666         {
4667           emit_loadreg(i_regmap[hr],hr);
4668         }
4669       }
4670     }
4671   }
4672 }
4673
4674 // Load all regs, storing cycle count if necessary
4675 void load_regs_entry(int t)
4676 {
4677   int hr;
4678   if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
4679   else if(ccadj[t]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST(ccadj[t]),HOST_CCREG);
4680   if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4681     emit_storereg(CCREG,HOST_CCREG);
4682   }
4683   // Load 32-bit regs
4684   for(hr=0;hr<HOST_REGS;hr++) {
4685     if(regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
4686       if(regs[t].regmap_entry[hr]==0) {
4687         emit_zeroreg(hr);
4688       }
4689       else if(regs[t].regmap_entry[hr]!=CCREG)
4690       {
4691         emit_loadreg(regs[t].regmap_entry[hr],hr);
4692       }
4693     }
4694   }
4695   // Load 64-bit regs
4696   for(hr=0;hr<HOST_REGS;hr++) {
4697     if(regs[t].regmap_entry[hr]>=64&&regs[t].regmap_entry[hr]<TEMPREG+64) {
4698       assert(regs[t].regmap_entry[hr]!=64);
4699       if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4700         int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4701         if(lr<0) {
4702           emit_loadreg(regs[t].regmap_entry[hr],hr);
4703         }
4704         else
4705         {
4706           emit_sarimm(lr,31,hr);
4707         }
4708       }
4709       else
4710       {
4711         emit_loadreg(regs[t].regmap_entry[hr],hr);
4712       }
4713     }
4714   }
4715 }
4716
4717 // Store dirty registers prior to branch
4718 void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4719 {
4720   if(internal_branch(i_is32,addr))
4721   {
4722     int t=(addr-start)>>2;
4723     int hr;
4724     for(hr=0;hr<HOST_REGS;hr++) {
4725       if(hr!=EXCLUDE_REG) {
4726         if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4727           if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4728             if((i_dirty>>hr)&1) {
4729               if(i_regmap[hr]<64) {
4730                 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4731                   emit_storereg(i_regmap[hr],hr);
4732                   if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4733                     #ifdef DESTRUCTIVE_WRITEBACK
4734                     emit_sarimm(hr,31,hr);
4735                     emit_storereg(i_regmap[hr]|64,hr);
4736                     #else
4737                     emit_sarimm(hr,31,HOST_TEMPREG);
4738                     emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4739                     #endif
4740                   }
4741                 }
4742               }else{
4743                 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4744                   emit_storereg(i_regmap[hr],hr);
4745                 }
4746               }
4747             }
4748           }
4749         }
4750       }
4751     }
4752   }
4753   else
4754   {
4755     // Branch out of this block, write out all dirty regs
4756     wb_dirtys(i_regmap,i_is32,i_dirty);
4757   }
4758 }
4759
4760 // Load all needed registers for branch target
4761 void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4762 {
4763   //if(addr>=start && addr<(start+slen*4))
4764   if(internal_branch(i_is32,addr))
4765   {
4766     int t=(addr-start)>>2;
4767     int hr;
4768     // Store the cycle count before loading something else
4769     if(i_regmap[HOST_CCREG]!=CCREG) {
4770       assert(i_regmap[HOST_CCREG]==-1);
4771     }
4772     if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4773       emit_storereg(CCREG,HOST_CCREG);
4774     }
4775     // Load 32-bit regs
4776     for(hr=0;hr<HOST_REGS;hr++) {
4777       if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
4778         #ifdef DESTRUCTIVE_WRITEBACK
4779         if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4780         #else
4781         if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4782         #endif
4783           if(regs[t].regmap_entry[hr]==0) {
4784             emit_zeroreg(hr);
4785           }
4786           else if(regs[t].regmap_entry[hr]!=CCREG)
4787           {
4788             emit_loadreg(regs[t].regmap_entry[hr],hr);
4789           }
4790         }
4791       }
4792     }
4793     //Load 64-bit regs
4794     for(hr=0;hr<HOST_REGS;hr++) {
4795       if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=64&&regs[t].regmap_entry[hr]<TEMPREG+64) {
4796         if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4797           assert(regs[t].regmap_entry[hr]!=64);
4798           if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4799             int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4800             if(lr<0) {
4801               emit_loadreg(regs[t].regmap_entry[hr],hr);
4802             }
4803             else
4804             {
4805               emit_sarimm(lr,31,hr);
4806             }
4807           }
4808           else
4809           {
4810             emit_loadreg(regs[t].regmap_entry[hr],hr);
4811           }
4812         }
4813         else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4814           int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4815           assert(lr>=0);
4816           emit_sarimm(lr,31,hr);
4817         }
4818       }
4819     }
4820   }
4821 }
4822
4823 int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4824 {
4825   if(addr>=start && addr<start+slen*4-4)
4826   {
4827     int t=(addr-start)>>2;
4828     int hr;
4829     if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4830     for(hr=0;hr<HOST_REGS;hr++)
4831     {
4832       if(hr!=EXCLUDE_REG)
4833       {
4834         if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4835         {
4836           if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
4837           {
4838             return 0;
4839           }
4840           else
4841           if((i_dirty>>hr)&1)
4842           {
4843             if(i_regmap[hr]<TEMPREG)
4844             {
4845               if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4846                 return 0;
4847             }
4848             else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
4849             {
4850               if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4851                 return 0;
4852             }
4853           }
4854         }
4855         else // Same register but is it 32-bit or dirty?
4856         if(i_regmap[hr]>=0)
4857         {
4858           if(!((regs[t].dirty>>hr)&1))
4859           {
4860             if((i_dirty>>hr)&1)
4861             {
4862               if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4863               {
4864                 //printf("%x: dirty no match\n",addr);
4865                 return 0;
4866               }
4867             }
4868           }
4869           if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4870           {
4871             //printf("%x: is32 no match\n",addr);
4872             return 0;
4873           }
4874         }
4875       }
4876     }
4877     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4878 #ifndef FORCE32
4879     if(requires_32bit[t]&~i_is32) return 0;
4880 #endif
4881     // Delay slots are not valid branch targets
4882     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4883     // Delay slots require additional processing, so do not match
4884     if(is_ds[t]) return 0;
4885   }
4886   else
4887   {
4888     int hr;
4889     for(hr=0;hr<HOST_REGS;hr++)
4890     {
4891       if(hr!=EXCLUDE_REG)
4892       {
4893         if(i_regmap[hr]>=0)
4894         {
4895           if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4896           {
4897             if((i_dirty>>hr)&1)
4898             {
4899               return 0;
4900             }
4901           }
4902         }
4903       }
4904     }
4905   }
4906   return 1;
4907 }
4908
4909 // Used when a branch jumps into the delay slot of another branch
4910 void ds_assemble_entry(int i)
4911 {
4912   int t=(ba[i]-start)>>2;
4913   if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4914   assem_debug("Assemble delay slot at %x\n",ba[i]);
4915   assem_debug("<->\n");
4916   if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
4917     wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4918   load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4919   address_generation(t,&regs[t],regs[t].regmap_entry);
4920   if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
4921     load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4922   cop1_usable=0;
4923   is_delayslot=0;
4924   switch(itype[t]) {
4925     case ALU:
4926       alu_assemble(t,&regs[t]);break;
4927     case IMM16:
4928       imm16_assemble(t,&regs[t]);break;
4929     case SHIFT:
4930       shift_assemble(t,&regs[t]);break;
4931     case SHIFTIMM:
4932       shiftimm_assemble(t,&regs[t]);break;
4933     case LOAD:
4934       load_assemble(t,&regs[t]);break;
4935     case LOADLR:
4936       loadlr_assemble(t,&regs[t]);break;
4937     case STORE:
4938       store_assemble(t,&regs[t]);break;
4939     case STORELR:
4940       storelr_assemble(t,&regs[t]);break;
4941     case COP0:
4942       cop0_assemble(t,&regs[t]);break;
4943     case COP1:
4944       cop1_assemble(t,&regs[t]);break;
4945     case C1LS:
4946       c1ls_assemble(t,&regs[t]);break;
4947     case COP2:
4948       cop2_assemble(t,&regs[t]);break;
4949     case C2LS:
4950       c2ls_assemble(t,&regs[t]);break;
4951     case C2OP:
4952       c2op_assemble(t,&regs[t]);break;
4953     case FCONV:
4954       fconv_assemble(t,&regs[t]);break;
4955     case FLOAT:
4956       float_assemble(t,&regs[t]);break;
4957     case FCOMP:
4958       fcomp_assemble(t,&regs[t]);break;
4959     case MULTDIV:
4960       multdiv_assemble(t,&regs[t]);break;
4961     case MOV:
4962       mov_assemble(t,&regs[t]);break;
4963     case SYSCALL:
4964     case HLECALL:
4965     case INTCALL:
4966     case SPAN:
4967     case UJUMP:
4968     case RJUMP:
4969     case CJUMP:
4970     case SJUMP:
4971     case FJUMP:
4972       printf("Jump in the delay slot.  This is probably a bug.\n");
4973   }
4974   store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4975   load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4976   if(internal_branch(regs[t].is32,ba[i]+4))
4977     assem_debug("branch: internal\n");
4978   else
4979     assem_debug("branch: external\n");
4980   assert(internal_branch(regs[t].is32,ba[i]+4));
4981   add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4982   emit_jmp(0);
4983 }
4984
4985 void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4986 {
4987   int count;
4988   int jaddr;
4989   int idle=0;
4990   int t=0;
4991   if(itype[i]==RJUMP)
4992   {
4993     *adj=0;
4994   }
4995   //if(ba[i]>=start && ba[i]<(start+slen*4))
4996   if(internal_branch(branch_regs[i].is32,ba[i]))
4997   {
4998     t=(ba[i]-start)>>2;
4999     if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
5000     else *adj=ccadj[t];
5001   }
5002   else
5003   {
5004     *adj=0;
5005   }
5006   count=ccadj[i];
5007   if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
5008     // Idle loop
5009     if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
5010     idle=(int)out;
5011     //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
5012     emit_andimm(HOST_CCREG,3,HOST_CCREG);
5013     jaddr=(int)out;
5014     emit_jmp(0);
5015   }
5016   else if(*adj==0||invert) {
5017     int cycles=CLOCK_ADJUST(count+2);
5018     // faster loop HACK
5019     if (t&&*adj) {
5020       int rel=t-i;
5021       if(-NO_CYCLE_PENALTY_THR<rel&&rel<0)
5022         cycles=CLOCK_ADJUST(*adj)+count+2-*adj;
5023     }
5024     emit_addimm_and_set_flags(cycles,HOST_CCREG);
5025     jaddr=(int)out;
5026     emit_jns(0);
5027   }
5028   else
5029   {
5030     emit_cmpimm(HOST_CCREG,-CLOCK_ADJUST(count+2));
5031     jaddr=(int)out;
5032     emit_jns(0);
5033   }
5034   add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
5035 }
5036
5037 void do_ccstub(int n)
5038 {
5039   literal_pool(256);
5040   assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
5041   set_jump_target(stubs[n][1],(int)out);
5042   int i=stubs[n][4];
5043   if(stubs[n][6]==NULLDS) {
5044     // Delay slot instruction is nullified ("likely" branch)
5045     wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
5046   }
5047   else if(stubs[n][6]!=TAKEN) {
5048     wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
5049   }
5050   else {
5051     if(internal_branch(branch_regs[i].is32,ba[i]))
5052       wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5053   }
5054   if(stubs[n][5]!=-1)
5055   {
5056     // Save PC as return address
5057     emit_movimm(stubs[n][5],EAX);
5058     emit_writeword(EAX,(int)&pcaddr);
5059   }
5060   else
5061   {
5062     // Return address depends on which way the branch goes
5063     if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
5064     {
5065       int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5066       int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5067       int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5068       int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5069       if(rs1[i]==0)
5070       {
5071         s1l=s2l;s1h=s2h;
5072         s2l=s2h=-1;
5073       }
5074       else if(rs2[i]==0)
5075       {
5076         s2l=s2h=-1;
5077       }
5078       if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
5079         s1h=s2h=-1;
5080       }
5081       assert(s1l>=0);
5082       #ifdef DESTRUCTIVE_WRITEBACK
5083       if(rs1[i]) {
5084         if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
5085           emit_loadreg(rs1[i],s1l);
5086       }
5087       else {
5088         if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
5089           emit_loadreg(rs2[i],s1l);
5090       }
5091       if(s2l>=0)
5092         if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
5093           emit_loadreg(rs2[i],s2l);
5094       #endif
5095       int hr=0;
5096       int addr=-1,alt=-1,ntaddr=-1;
5097       while(hr<HOST_REGS)
5098       {
5099         if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5100            (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5101            (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5102         {
5103           addr=hr++;break;
5104         }
5105         hr++;
5106       }
5107       while(hr<HOST_REGS)
5108       {
5109         if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5110            (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5111            (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5112         {
5113           alt=hr++;break;
5114         }
5115         hr++;
5116       }
5117       if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
5118       {
5119         while(hr<HOST_REGS)
5120         {
5121           if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5122              (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5123              (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5124           {
5125             ntaddr=hr;break;
5126           }
5127           hr++;
5128         }
5129         assert(hr<HOST_REGS);
5130       }
5131       if((opcode[i]&0x2f)==4) // BEQ
5132       {
5133         #ifdef HAVE_CMOV_IMM
5134         if(s1h<0) {
5135           if(s2l>=0) emit_cmp(s1l,s2l);
5136           else emit_test(s1l,s1l);
5137           emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5138         }
5139         else
5140         #endif
5141         {
5142           emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5143           if(s1h>=0) {
5144             if(s2h>=0) emit_cmp(s1h,s2h);
5145             else emit_test(s1h,s1h);
5146             emit_cmovne_reg(alt,addr);
5147           }
5148           if(s2l>=0) emit_cmp(s1l,s2l);
5149           else emit_test(s1l,s1l);
5150           emit_cmovne_reg(alt,addr);
5151         }
5152       }
5153       if((opcode[i]&0x2f)==5) // BNE
5154       {
5155         #ifdef HAVE_CMOV_IMM
5156         if(s1h<0) {
5157           if(s2l>=0) emit_cmp(s1l,s2l);
5158           else emit_test(s1l,s1l);
5159           emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5160         }
5161         else
5162         #endif
5163         {
5164           emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5165           if(s1h>=0) {
5166             if(s2h>=0) emit_cmp(s1h,s2h);
5167             else emit_test(s1h,s1h);
5168             emit_cmovne_reg(alt,addr);
5169           }
5170           if(s2l>=0) emit_cmp(s1l,s2l);
5171           else emit_test(s1l,s1l);
5172           emit_cmovne_reg(alt,addr);
5173         }
5174       }
5175       if((opcode[i]&0x2f)==6) // BLEZ
5176       {
5177         //emit_movimm(ba[i],alt);
5178         //emit_movimm(start+i*4+8,addr);
5179         emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5180         emit_cmpimm(s1l,1);
5181         if(s1h>=0) emit_mov(addr,ntaddr);
5182         emit_cmovl_reg(alt,addr);
5183         if(s1h>=0) {
5184           emit_test(s1h,s1h);
5185           emit_cmovne_reg(ntaddr,addr);
5186           emit_cmovs_reg(alt,addr);
5187         }
5188       }
5189       if((opcode[i]&0x2f)==7) // BGTZ
5190       {
5191         //emit_movimm(ba[i],addr);
5192         //emit_movimm(start+i*4+8,ntaddr);
5193         emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5194         emit_cmpimm(s1l,1);
5195         if(s1h>=0) emit_mov(addr,alt);
5196         emit_cmovl_reg(ntaddr,addr);
5197         if(s1h>=0) {
5198           emit_test(s1h,s1h);
5199           emit_cmovne_reg(alt,addr);
5200           emit_cmovs_reg(ntaddr,addr);
5201         }
5202       }
5203       if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
5204       {
5205         //emit_movimm(ba[i],alt);
5206         //emit_movimm(start+i*4+8,addr);
5207         emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5208         if(s1h>=0) emit_test(s1h,s1h);
5209         else emit_test(s1l,s1l);
5210         emit_cmovs_reg(alt,addr);
5211       }
5212       if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
5213       {
5214         //emit_movimm(ba[i],addr);
5215         //emit_movimm(start+i*4+8,alt);
5216         emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5217         if(s1h>=0) emit_test(s1h,s1h);
5218         else emit_test(s1l,s1l);
5219         emit_cmovs_reg(alt,addr);
5220       }
5221       if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
5222         if(source[i]&0x10000) // BC1T
5223         {
5224           //emit_movimm(ba[i],alt);
5225           //emit_movimm(start+i*4+8,addr);
5226           emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5227           emit_testimm(s1l,0x800000);
5228           emit_cmovne_reg(alt,addr);
5229         }
5230         else // BC1F
5231         {
5232           //emit_movimm(ba[i],addr);
5233           //emit_movimm(start+i*4+8,alt);
5234           emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5235           emit_testimm(s1l,0x800000);
5236           emit_cmovne_reg(alt,addr);
5237         }
5238       }
5239       emit_writeword(addr,(int)&pcaddr);
5240     }
5241     else
5242     if(itype[i]==RJUMP)
5243     {
5244       int r=get_reg(branch_regs[i].regmap,rs1[i]);
5245       if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5246         r=get_reg(branch_regs[i].regmap,RTEMP);
5247       }
5248       emit_writeword(r,(int)&pcaddr);
5249     }
5250     else {printf("Unknown branch type in do_ccstub\n");exit(1);}
5251   }
5252   // Update cycle count
5253   assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5254   if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG);
5255   emit_call((int)cc_interrupt);
5256   if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG);
5257   if(stubs[n][6]==TAKEN) {
5258     if(internal_branch(branch_regs[i].is32,ba[i]))
5259       load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
5260     else if(itype[i]==RJUMP) {
5261       if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5262         emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5263       else
5264         emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
5265     }
5266   }else if(stubs[n][6]==NOTTAKEN) {
5267     if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5268     else load_all_regs(branch_regs[i].regmap);
5269   }else if(stubs[n][6]==NULLDS) {
5270     // Delay slot instruction is nullified ("likely" branch)
5271     if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5272     else load_all_regs(regs[i].regmap);
5273   }else{
5274     load_all_regs(branch_regs[i].regmap);
5275   }
5276   emit_jmp(stubs[n][2]); // return address
5277
5278   /* This works but uses a lot of memory...
5279   emit_readword((int)&last_count,ECX);
5280   emit_add(HOST_CCREG,ECX,EAX);
5281   emit_writeword(EAX,(int)&Count);
5282   emit_call((int)gen_interupt);
5283   emit_readword((int)&Count,HOST_CCREG);
5284   emit_readword((int)&next_interupt,EAX);
5285   emit_readword((int)&pending_exception,EBX);
5286   emit_writeword(EAX,(int)&last_count);
5287   emit_sub(HOST_CCREG,EAX,HOST_CCREG);
5288   emit_test(EBX,EBX);
5289   int jne_instr=(int)out;
5290   emit_jne(0);
5291   if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
5292   load_all_regs(branch_regs[i].regmap);
5293   emit_jmp(stubs[n][2]); // return address
5294   set_jump_target(jne_instr,(int)out);
5295   emit_readword((int)&pcaddr,EAX);
5296   // Call get_addr_ht instead of doing the hash table here.
5297   // This code is executed infrequently and takes up a lot of space
5298   // so smaller is better.
5299   emit_storereg(CCREG,HOST_CCREG);
5300   emit_pushreg(EAX);
5301   emit_call((int)get_addr_ht);
5302   emit_loadreg(CCREG,HOST_CCREG);
5303   emit_addimm(ESP,4,ESP);
5304   emit_jmpreg(EAX);*/
5305 }
5306
5307 add_to_linker(int addr,int target,int ext)
5308 {
5309   link_addr[linkcount][0]=addr;
5310   link_addr[linkcount][1]=target;
5311   link_addr[linkcount][2]=ext;
5312   linkcount++;
5313 }
5314
5315 static void ujump_assemble_write_ra(int i)
5316 {
5317   int rt;
5318   unsigned int return_address;
5319   rt=get_reg(branch_regs[i].regmap,31);
5320   assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5321   //assert(rt>=0);
5322   return_address=start+i*4+8;
5323   if(rt>=0) {
5324     #ifdef USE_MINI_HT
5325     if(internal_branch(branch_regs[i].is32,return_address)&&rt1[i+1]!=31) {
5326       int temp=-1; // note: must be ds-safe
5327       #ifdef HOST_TEMPREG
5328       temp=HOST_TEMPREG;
5329       #endif
5330       if(temp>=0) do_miniht_insert(return_address,rt,temp);
5331       else emit_movimm(return_address,rt);
5332     }
5333     else
5334     #endif
5335     {
5336       #ifdef REG_PREFETCH
5337       if(temp>=0)
5338       {
5339         if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5340       }
5341       #endif
5342       emit_movimm(return_address,rt); // PC into link register
5343       #ifdef IMM_PREFETCH
5344       emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5345       #endif
5346     }
5347   }
5348 }
5349
5350 void ujump_assemble(int i,struct regstat *i_regs)
5351 {
5352   signed char *i_regmap=i_regs->regmap;
5353   int ra_done=0;
5354   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5355   address_generation(i+1,i_regs,regs[i].regmap_entry);
5356   #ifdef REG_PREFETCH
5357   int temp=get_reg(branch_regs[i].regmap,PTEMP);
5358   if(rt1[i]==31&&temp>=0)
5359   {
5360     int return_address=start+i*4+8;
5361     if(get_reg(branch_regs[i].regmap,31)>0)
5362     if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5363   }
5364   #endif
5365   if(rt1[i]==31&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5366     ujump_assemble_write_ra(i); // writeback ra for DS
5367     ra_done=1;
5368   }
5369   ds_assemble(i+1,i_regs);
5370   uint64_t bc_unneeded=branch_regs[i].u;
5371   uint64_t bc_unneeded_upper=branch_regs[i].uu;
5372   bc_unneeded|=1|(1LL<<rt1[i]);
5373   bc_unneeded_upper|=1|(1LL<<rt1[i]);
5374   wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5375                 bc_unneeded,bc_unneeded_upper);
5376   load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5377   if(!ra_done&&rt1[i]==31)
5378     ujump_assemble_write_ra(i);
5379   int cc,adj;
5380   cc=get_reg(branch_regs[i].regmap,CCREG);
5381   assert(cc==HOST_CCREG);
5382   store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5383   #ifdef REG_PREFETCH
5384   if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5385   #endif
5386   do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5387   if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5388   load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5389   if(internal_branch(branch_regs[i].is32,ba[i]))
5390     assem_debug("branch: internal\n");
5391   else
5392     assem_debug("branch: external\n");
5393   if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5394     ds_assemble_entry(i);
5395   }
5396   else {
5397     add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5398     emit_jmp(0);
5399   }
5400 }
5401
5402 static void rjump_assemble_write_ra(int i)
5403 {
5404   int rt,return_address;
5405   assert(rt1[i+1]!=rt1[i]);
5406   assert(rt2[i+1]!=rt1[i]);
5407   rt=get_reg(branch_regs[i].regmap,rt1[i]);
5408   assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5409   assert(rt>=0);
5410   return_address=start+i*4+8;
5411   #ifdef REG_PREFETCH
5412   if(temp>=0)
5413   {
5414     if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5415   }
5416   #endif
5417   emit_movimm(return_address,rt); // PC into link register
5418   #ifdef IMM_PREFETCH
5419   emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5420   #endif
5421 }
5422
5423 void rjump_assemble(int i,struct regstat *i_regs)
5424 {
5425   signed char *i_regmap=i_regs->regmap;
5426   int temp;
5427   int rs,cc,adj;
5428   int ra_done=0;
5429   rs=get_reg(branch_regs[i].regmap,rs1[i]);
5430   assert(rs>=0);
5431   if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5432     // Delay slot abuse, make a copy of the branch address register
5433     temp=get_reg(branch_regs[i].regmap,RTEMP);
5434     assert(temp>=0);
5435     assert(regs[i].regmap[temp]==RTEMP);
5436     emit_mov(rs,temp);
5437     rs=temp;
5438   }
5439   address_generation(i+1,i_regs,regs[i].regmap_entry);
5440   #ifdef REG_PREFETCH
5441   if(rt1[i]==31)
5442   {
5443     if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5444       int return_address=start+i*4+8;
5445       if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5446     }
5447   }
5448   #endif
5449   #ifdef USE_MINI_HT
5450   if(rs1[i]==31) {
5451     int rh=get_reg(regs[i].regmap,RHASH);
5452     if(rh>=0) do_preload_rhash(rh);
5453   }
5454   #endif
5455   if(rt1[i]!=0&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5456     rjump_assemble_write_ra(i);
5457     ra_done=1;
5458   }
5459   ds_assemble(i+1,i_regs);
5460   uint64_t bc_unneeded=branch_regs[i].u;
5461   uint64_t bc_unneeded_upper=branch_regs[i].uu;
5462   bc_unneeded|=1|(1LL<<rt1[i]);
5463   bc_unneeded_upper|=1|(1LL<<rt1[i]);
5464   bc_unneeded&=~(1LL<<rs1[i]);
5465   wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5466                 bc_unneeded,bc_unneeded_upper);
5467   load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5468   if(!ra_done&&rt1[i]!=0)
5469     rjump_assemble_write_ra(i);
5470   cc=get_reg(branch_regs[i].regmap,CCREG);
5471   assert(cc==HOST_CCREG);
5472   #ifdef USE_MINI_HT
5473   int rh=get_reg(branch_regs[i].regmap,RHASH);
5474   int ht=get_reg(branch_regs[i].regmap,RHTBL);
5475   if(rs1[i]==31) {
5476     if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5477     do_preload_rhtbl(ht);
5478     do_rhash(rs,rh);
5479   }
5480   #endif
5481   store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5482   #ifdef DESTRUCTIVE_WRITEBACK
5483   if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5484     if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5485       emit_loadreg(rs1[i],rs);
5486     }
5487   }
5488   #endif
5489   #ifdef REG_PREFETCH
5490   if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5491   #endif
5492   #ifdef USE_MINI_HT
5493   if(rs1[i]==31) {
5494     do_miniht_load(ht,rh);
5495   }
5496   #endif
5497   //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5498   //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5499   //assert(adj==0);
5500   emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5501   add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5502 #ifdef PCSX
5503   if(itype[i+1]==COP0&&(source[i+1]&0x3f)==0x10)
5504     // special case for RFE
5505     emit_jmp(0);
5506   else
5507 #endif
5508   emit_jns(0);
5509   //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5510   #ifdef USE_MINI_HT
5511   if(rs1[i]==31) {
5512     do_miniht_jump(rs,rh,ht);
5513   }
5514   else
5515   #endif
5516   {
5517     //if(rs!=EAX) emit_mov(rs,EAX);
5518     //emit_jmp((int)jump_vaddr_eax);
5519     emit_jmp(jump_vaddr_reg[rs]);
5520   }
5521   /* Check hash table
5522   temp=!rs;
5523   emit_mov(rs,temp);
5524   emit_shrimm(rs,16,rs);
5525   emit_xor(temp,rs,rs);
5526   emit_movzwl_reg(rs,rs);
5527   emit_shlimm(rs,4,rs);
5528   emit_cmpmem_indexed((int)hash_table,rs,temp);
5529   emit_jne((int)out+14);
5530   emit_readword_indexed((int)hash_table+4,rs,rs);
5531   emit_jmpreg(rs);
5532   emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5533   emit_addimm_no_flags(8,rs);
5534   emit_jeq((int)out-17);
5535   // No hit on hash table, call compiler
5536   emit_pushreg(temp);
5537 //DEBUG >
5538 #ifdef DEBUG_CYCLE_COUNT
5539   emit_readword((int)&last_count,ECX);
5540   emit_add(HOST_CCREG,ECX,HOST_CCREG);
5541   emit_readword((int)&next_interupt,ECX);
5542   emit_writeword(HOST_CCREG,(int)&Count);
5543   emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5544   emit_writeword(ECX,(int)&last_count);
5545 #endif
5546 //DEBUG <
5547   emit_storereg(CCREG,HOST_CCREG);
5548   emit_call((int)get_addr);
5549   emit_loadreg(CCREG,HOST_CCREG);
5550   emit_addimm(ESP,4,ESP);
5551   emit_jmpreg(EAX);*/
5552   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5553   if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5554   #endif
5555 }
5556
5557 void cjump_assemble(int i,struct regstat *i_regs)
5558 {
5559   signed char *i_regmap=i_regs->regmap;
5560   int cc;
5561   int match;
5562   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5563   assem_debug("match=%d\n",match);
5564   int s1h,s1l,s2h,s2l;
5565   int prev_cop1_usable=cop1_usable;
5566   int unconditional=0,nop=0;
5567   int only32=0;
5568   int invert=0;
5569   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5570   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5571   if(!match) invert=1;
5572   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5573   if(i>(ba[i]-start)>>2) invert=1;
5574   #endif
5575
5576   if(ooo[i]) {
5577     s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5578     s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5579     s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5580     s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5581   }
5582   else {
5583     s1l=get_reg(i_regmap,rs1[i]);
5584     s1h=get_reg(i_regmap,rs1[i]|64);
5585     s2l=get_reg(i_regmap,rs2[i]);
5586     s2h=get_reg(i_regmap,rs2[i]|64);
5587   }
5588   if(rs1[i]==0&&rs2[i]==0)
5589   {
5590     if(opcode[i]&1) nop=1;
5591     else unconditional=1;
5592     //assert(opcode[i]!=5);
5593     //assert(opcode[i]!=7);
5594     //assert(opcode[i]!=0x15);
5595     //assert(opcode[i]!=0x17);
5596   }
5597   else if(rs1[i]==0)
5598   {
5599     s1l=s2l;s1h=s2h;
5600     s2l=s2h=-1;
5601     only32=(regs[i].was32>>rs2[i])&1;
5602   }
5603   else if(rs2[i]==0)
5604   {
5605     s2l=s2h=-1;
5606     only32=(regs[i].was32>>rs1[i])&1;
5607   }
5608   else {
5609     only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5610   }
5611
5612   if(ooo[i]) {
5613     // Out of order execution (delay slot first)
5614     //printf("OOOE\n");
5615     address_generation(i+1,i_regs,regs[i].regmap_entry);
5616     ds_assemble(i+1,i_regs);
5617     int adj;
5618     uint64_t bc_unneeded=branch_regs[i].u;
5619     uint64_t bc_unneeded_upper=branch_regs[i].uu;
5620     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5621     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5622     bc_unneeded|=1;
5623     bc_unneeded_upper|=1;
5624     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5625                   bc_unneeded,bc_unneeded_upper);
5626     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5627     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5628     cc=get_reg(branch_regs[i].regmap,CCREG);
5629     assert(cc==HOST_CCREG);
5630     if(unconditional)
5631       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5632     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5633     //assem_debug("cycle count (adj)\n");
5634     if(unconditional) {
5635       do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5636       if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5637         if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5638         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5639         if(internal)
5640           assem_debug("branch: internal\n");
5641         else
5642           assem_debug("branch: external\n");
5643         if(internal&&is_ds[(ba[i]-start)>>2]) {
5644           ds_assemble_entry(i);
5645         }
5646         else {
5647           add_to_linker((int)out,ba[i],internal);
5648           emit_jmp(0);
5649         }
5650         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5651         if(((u_int)out)&7) emit_addnop(0);
5652         #endif
5653       }
5654     }
5655     else if(nop) {
5656       emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5657       int jaddr=(int)out;
5658       emit_jns(0);
5659       add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5660     }
5661     else {
5662       int taken=0,nottaken=0,nottaken1=0;
5663       do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5664       if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5665       if(!only32)
5666       {
5667         assert(s1h>=0);
5668         if(opcode[i]==4) // BEQ
5669         {
5670           if(s2h>=0) emit_cmp(s1h,s2h);
5671           else emit_test(s1h,s1h);
5672           nottaken1=(int)out;
5673           emit_jne(1);
5674         }
5675         if(opcode[i]==5) // BNE
5676         {
5677           if(s2h>=0) emit_cmp(s1h,s2h);
5678           else emit_test(s1h,s1h);
5679           if(invert) taken=(int)out;
5680           else add_to_linker((int)out,ba[i],internal);
5681           emit_jne(0);
5682         }
5683         if(opcode[i]==6) // BLEZ
5684         {
5685           emit_test(s1h,s1h);
5686           if(invert) taken=(int)out;
5687           else add_to_linker((int)out,ba[i],internal);
5688           emit_js(0);
5689           nottaken1=(int)out;
5690           emit_jne(1);
5691         }
5692         if(opcode[i]==7) // BGTZ
5693         {
5694           emit_test(s1h,s1h);
5695           nottaken1=(int)out;
5696           emit_js(1);
5697           if(invert) taken=(int)out;
5698           else add_to_linker((int)out,ba[i],internal);
5699           emit_jne(0);
5700         }
5701       } // if(!only32)
5702
5703       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5704       assert(s1l>=0);
5705       if(opcode[i]==4) // BEQ
5706       {
5707         if(s2l>=0) emit_cmp(s1l,s2l);
5708         else emit_test(s1l,s1l);
5709         if(invert){
5710           nottaken=(int)out;
5711           emit_jne(1);
5712         }else{
5713           add_to_linker((int)out,ba[i],internal);
5714           emit_jeq(0);
5715         }
5716       }
5717       if(opcode[i]==5) // BNE
5718       {
5719         if(s2l>=0) emit_cmp(s1l,s2l);
5720         else emit_test(s1l,s1l);
5721         if(invert){
5722           nottaken=(int)out;
5723           emit_jeq(1);
5724         }else{
5725           add_to_linker((int)out,ba[i],internal);
5726           emit_jne(0);
5727         }
5728       }
5729       if(opcode[i]==6) // BLEZ
5730       {
5731         emit_cmpimm(s1l,1);
5732         if(invert){
5733           nottaken=(int)out;
5734           emit_jge(1);
5735         }else{
5736           add_to_linker((int)out,ba[i],internal);
5737           emit_jl(0);
5738         }
5739       }
5740       if(opcode[i]==7) // BGTZ
5741       {
5742         emit_cmpimm(s1l,1);
5743         if(invert){
5744           nottaken=(int)out;
5745           emit_jl(1);
5746         }else{
5747           add_to_linker((int)out,ba[i],internal);
5748           emit_jge(0);
5749         }
5750       }
5751       if(invert) {
5752         if(taken) set_jump_target(taken,(int)out);
5753         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5754         if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5755           if(adj) {
5756             emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5757             add_to_linker((int)out,ba[i],internal);
5758           }else{
5759             emit_addnop(13);
5760             add_to_linker((int)out,ba[i],internal*2);
5761           }
5762           emit_jmp(0);
5763         }else
5764         #endif
5765         {
5766           if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5767           store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5768           load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5769           if(internal)
5770             assem_debug("branch: internal\n");
5771           else
5772             assem_debug("branch: external\n");
5773           if(internal&&is_ds[(ba[i]-start)>>2]) {
5774             ds_assemble_entry(i);
5775           }
5776           else {
5777             add_to_linker((int)out,ba[i],internal);
5778             emit_jmp(0);
5779           }
5780         }
5781         set_jump_target(nottaken,(int)out);
5782       }
5783
5784       if(nottaken1) set_jump_target(nottaken1,(int)out);
5785       if(adj) {
5786         if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
5787       }
5788     } // (!unconditional)
5789   } // if(ooo)
5790   else
5791   {
5792     // In-order execution (branch first)
5793     //if(likely[i]) printf("IOL\n");
5794     //else
5795     //printf("IOE\n");
5796     int taken=0,nottaken=0,nottaken1=0;
5797     if(!unconditional&&!nop) {
5798       if(!only32)
5799       {
5800         assert(s1h>=0);
5801         if((opcode[i]&0x2f)==4) // BEQ
5802         {
5803           if(s2h>=0) emit_cmp(s1h,s2h);
5804           else emit_test(s1h,s1h);
5805           nottaken1=(int)out;
5806           emit_jne(2);
5807         }
5808         if((opcode[i]&0x2f)==5) // BNE
5809         {
5810           if(s2h>=0) emit_cmp(s1h,s2h);
5811           else emit_test(s1h,s1h);
5812           taken=(int)out;
5813           emit_jne(1);
5814         }
5815         if((opcode[i]&0x2f)==6) // BLEZ
5816         {
5817           emit_test(s1h,s1h);
5818           taken=(int)out;
5819           emit_js(1);
5820           nottaken1=(int)out;
5821           emit_jne(2);
5822         }
5823         if((opcode[i]&0x2f)==7) // BGTZ
5824         {
5825           emit_test(s1h,s1h);
5826           nottaken1=(int)out;
5827           emit_js(2);
5828           taken=(int)out;
5829           emit_jne(1);
5830         }
5831       } // if(!only32)
5832
5833       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5834       assert(s1l>=0);
5835       if((opcode[i]&0x2f)==4) // BEQ
5836       {
5837         if(s2l>=0) emit_cmp(s1l,s2l);
5838         else emit_test(s1l,s1l);
5839         nottaken=(int)out;
5840         emit_jne(2);
5841       }
5842       if((opcode[i]&0x2f)==5) // BNE
5843       {
5844         if(s2l>=0) emit_cmp(s1l,s2l);
5845         else emit_test(s1l,s1l);
5846         nottaken=(int)out;
5847         emit_jeq(2);
5848       }
5849       if((opcode[i]&0x2f)==6) // BLEZ
5850       {
5851         emit_cmpimm(s1l,1);
5852         nottaken=(int)out;
5853         emit_jge(2);
5854       }
5855       if((opcode[i]&0x2f)==7) // BGTZ
5856       {
5857         emit_cmpimm(s1l,1);
5858         nottaken=(int)out;
5859         emit_jl(2);
5860       }
5861     } // if(!unconditional)
5862     int adj;
5863     uint64_t ds_unneeded=branch_regs[i].u;
5864     uint64_t ds_unneeded_upper=branch_regs[i].uu;
5865     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5866     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5867     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5868     ds_unneeded|=1;
5869     ds_unneeded_upper|=1;
5870     // branch taken
5871     if(!nop) {
5872       if(taken) set_jump_target(taken,(int)out);
5873       assem_debug("1:\n");
5874       wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5875                     ds_unneeded,ds_unneeded_upper);
5876       // load regs
5877       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5878       address_generation(i+1,&branch_regs[i],0);
5879       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5880       ds_assemble(i+1,&branch_regs[i]);
5881       cc=get_reg(branch_regs[i].regmap,CCREG);
5882       if(cc==-1) {
5883         emit_loadreg(CCREG,cc=HOST_CCREG);
5884         // CHECK: Is the following instruction (fall thru) allocated ok?
5885       }
5886       assert(cc==HOST_CCREG);
5887       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5888       do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5889       assem_debug("cycle count (adj)\n");
5890       if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5891       load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5892       if(internal)
5893         assem_debug("branch: internal\n");
5894       else
5895         assem_debug("branch: external\n");
5896       if(internal&&is_ds[(ba[i]-start)>>2]) {
5897         ds_assemble_entry(i);
5898       }
5899       else {
5900         add_to_linker((int)out,ba[i],internal);
5901         emit_jmp(0);
5902       }
5903     }
5904     // branch not taken
5905     cop1_usable=prev_cop1_usable;
5906     if(!unconditional) {
5907       if(nottaken1) set_jump_target(nottaken1,(int)out);
5908       set_jump_target(nottaken,(int)out);
5909       assem_debug("2:\n");
5910       if(!likely[i]) {
5911         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5912                       ds_unneeded,ds_unneeded_upper);
5913         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5914         address_generation(i+1,&branch_regs[i],0);
5915         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5916         ds_assemble(i+1,&branch_regs[i]);
5917       }
5918       cc=get_reg(branch_regs[i].regmap,CCREG);
5919       if(cc==-1&&!likely[i]) {
5920         // Cycle count isn't in a register, temporarily load it then write it out
5921         emit_loadreg(CCREG,HOST_CCREG);
5922         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5923         int jaddr=(int)out;
5924         emit_jns(0);
5925         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5926         emit_storereg(CCREG,HOST_CCREG);
5927       }
5928       else{
5929         cc=get_reg(i_regmap,CCREG);
5930         assert(cc==HOST_CCREG);
5931         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5932         int jaddr=(int)out;
5933         emit_jns(0);
5934         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5935       }
5936     }
5937   }
5938 }
5939
5940 void sjump_assemble(int i,struct regstat *i_regs)
5941 {
5942   signed char *i_regmap=i_regs->regmap;
5943   int cc;
5944   int match;
5945   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5946   assem_debug("smatch=%d\n",match);
5947   int s1h,s1l;
5948   int prev_cop1_usable=cop1_usable;
5949   int unconditional=0,nevertaken=0;
5950   int only32=0;
5951   int invert=0;
5952   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5953   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5954   if(!match) invert=1;
5955   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5956   if(i>(ba[i]-start)>>2) invert=1;
5957   #endif
5958
5959   //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
5960   //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
5961
5962   if(ooo[i]) {
5963     s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5964     s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5965   }
5966   else {
5967     s1l=get_reg(i_regmap,rs1[i]);
5968     s1h=get_reg(i_regmap,rs1[i]|64);
5969   }
5970   if(rs1[i]==0)
5971   {
5972     if(opcode2[i]&1) unconditional=1;
5973     else nevertaken=1;
5974     // These are never taken (r0 is never less than zero)
5975     //assert(opcode2[i]!=0);
5976     //assert(opcode2[i]!=2);
5977     //assert(opcode2[i]!=0x10);
5978     //assert(opcode2[i]!=0x12);
5979   }
5980   else {
5981     only32=(regs[i].was32>>rs1[i])&1;
5982   }
5983
5984   if(ooo[i]) {
5985     // Out of order execution (delay slot first)
5986     //printf("OOOE\n");
5987     address_generation(i+1,i_regs,regs[i].regmap_entry);
5988     ds_assemble(i+1,i_regs);
5989     int adj;
5990     uint64_t bc_unneeded=branch_regs[i].u;
5991     uint64_t bc_unneeded_upper=branch_regs[i].uu;
5992     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5993     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5994     bc_unneeded|=1;
5995     bc_unneeded_upper|=1;
5996     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5997                   bc_unneeded,bc_unneeded_upper);
5998     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5999     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6000     if(rt1[i]==31) {
6001       int rt,return_address;
6002       rt=get_reg(branch_regs[i].regmap,31);
6003       assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6004       if(rt>=0) {
6005         // Save the PC even if the branch is not taken
6006         return_address=start+i*4+8;
6007         emit_movimm(return_address,rt); // PC into link register
6008         #ifdef IMM_PREFETCH
6009         if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
6010         #endif
6011       }
6012     }
6013     cc=get_reg(branch_regs[i].regmap,CCREG);
6014     assert(cc==HOST_CCREG);
6015     if(unconditional)
6016       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6017     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
6018     assem_debug("cycle count (adj)\n");
6019     if(unconditional) {
6020       do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
6021       if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
6022         if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6023         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6024         if(internal)
6025           assem_debug("branch: internal\n");
6026         else
6027           assem_debug("branch: external\n");
6028         if(internal&&is_ds[(ba[i]-start)>>2]) {
6029           ds_assemble_entry(i);
6030         }
6031         else {
6032           add_to_linker((int)out,ba[i],internal);
6033           emit_jmp(0);
6034         }
6035         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6036         if(((u_int)out)&7) emit_addnop(0);
6037         #endif
6038       }
6039     }
6040     else if(nevertaken) {
6041       emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
6042       int jaddr=(int)out;
6043       emit_jns(0);
6044       add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6045     }
6046     else {
6047       int nottaken=0;
6048       do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6049       if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6050       if(!only32)
6051       {
6052         assert(s1h>=0);
6053         if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
6054         {
6055           emit_test(s1h,s1h);
6056           if(invert){
6057             nottaken=(int)out;
6058             emit_jns(1);
6059           }else{
6060             add_to_linker((int)out,ba[i],internal);
6061             emit_js(0);
6062           }
6063         }
6064         if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
6065         {
6066           emit_test(s1h,s1h);
6067           if(invert){
6068             nottaken=(int)out;
6069             emit_js(1);
6070           }else{
6071             add_to_linker((int)out,ba[i],internal);
6072             emit_jns(0);
6073           }
6074         }
6075       } // if(!only32)
6076       else
6077       {
6078         assert(s1l>=0);
6079         if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
6080         {
6081           emit_test(s1l,s1l);
6082           if(invert){
6083             nottaken=(int)out;
6084             emit_jns(1);
6085           }else{
6086             add_to_linker((int)out,ba[i],internal);
6087             emit_js(0);
6088           }
6089         }
6090         if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
6091         {
6092           emit_test(s1l,s1l);
6093           if(invert){
6094             nottaken=(int)out;
6095             emit_js(1);
6096           }else{
6097             add_to_linker((int)out,ba[i],internal);
6098             emit_jns(0);
6099           }
6100         }
6101       } // if(!only32)
6102
6103       if(invert) {
6104         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6105         if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
6106           if(adj) {
6107             emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6108             add_to_linker((int)out,ba[i],internal);
6109           }else{
6110             emit_addnop(13);
6111             add_to_linker((int)out,ba[i],internal*2);
6112           }
6113           emit_jmp(0);
6114         }else
6115         #endif
6116         {
6117           if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6118           store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6119           load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6120           if(internal)
6121             assem_debug("branch: internal\n");
6122           else
6123             assem_debug("branch: external\n");
6124           if(internal&&is_ds[(ba[i]-start)>>2]) {
6125             ds_assemble_entry(i);
6126           }
6127           else {
6128             add_to_linker((int)out,ba[i],internal);
6129             emit_jmp(0);
6130           }
6131         }
6132         set_jump_target(nottaken,(int)out);
6133       }
6134
6135       if(adj) {
6136         if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
6137       }
6138     } // (!unconditional)
6139   } // if(ooo)
6140   else
6141   {
6142     // In-order execution (branch first)
6143     //printf("IOE\n");
6144     int nottaken=0;
6145     if(rt1[i]==31) {
6146       int rt,return_address;
6147       rt=get_reg(branch_regs[i].regmap,31);
6148       if(rt>=0) {
6149         // Save the PC even if the branch is not taken
6150         return_address=start+i*4+8;
6151         emit_movimm(return_address,rt); // PC into link register
6152         #ifdef IMM_PREFETCH
6153         emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
6154         #endif
6155       }
6156     }
6157     if(!unconditional) {
6158       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6159       if(!only32)
6160       {
6161         assert(s1h>=0);
6162         if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
6163         {
6164           emit_test(s1h,s1h);
6165           nottaken=(int)out;
6166           emit_jns(1);
6167         }
6168         if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
6169         {
6170           emit_test(s1h,s1h);
6171           nottaken=(int)out;
6172           emit_js(1);
6173         }
6174       } // if(!only32)
6175       else
6176       {
6177         assert(s1l>=0);
6178         if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
6179         {
6180           emit_test(s1l,s1l);
6181           nottaken=(int)out;
6182           emit_jns(1);
6183         }
6184         if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
6185         {
6186           emit_test(s1l,s1l);
6187           nottaken=(int)out;
6188           emit_js(1);
6189         }
6190       }
6191     } // if(!unconditional)
6192     int adj;
6193     uint64_t ds_unneeded=branch_regs[i].u;
6194     uint64_t ds_unneeded_upper=branch_regs[i].uu;
6195     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6196     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6197     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6198     ds_unneeded|=1;
6199     ds_unneeded_upper|=1;
6200     // branch taken
6201     if(!nevertaken) {
6202       //assem_debug("1:\n");
6203       wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6204                     ds_unneeded,ds_unneeded_upper);
6205       // load regs
6206       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6207       address_generation(i+1,&branch_regs[i],0);
6208       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6209       ds_assemble(i+1,&branch_regs[i]);
6210       cc=get_reg(branch_regs[i].regmap,CCREG);
6211       if(cc==-1) {
6212         emit_loadreg(CCREG,cc=HOST_CCREG);
6213         // CHECK: Is the following instruction (fall thru) allocated ok?
6214       }
6215       assert(cc==HOST_CCREG);
6216       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6217       do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6218       assem_debug("cycle count (adj)\n");
6219       if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6220       load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6221       if(internal)
6222         assem_debug("branch: internal\n");
6223       else
6224         assem_debug("branch: external\n");
6225       if(internal&&is_ds[(ba[i]-start)>>2]) {
6226         ds_assemble_entry(i);
6227       }
6228       else {
6229         add_to_linker((int)out,ba[i],internal);
6230         emit_jmp(0);
6231       }
6232     }
6233     // branch not taken
6234     cop1_usable=prev_cop1_usable;
6235     if(!unconditional) {
6236       set_jump_target(nottaken,(int)out);
6237       assem_debug("1:\n");
6238       if(!likely[i]) {
6239         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6240                       ds_unneeded,ds_unneeded_upper);
6241         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6242         address_generation(i+1,&branch_regs[i],0);
6243         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6244         ds_assemble(i+1,&branch_regs[i]);
6245       }
6246       cc=get_reg(branch_regs[i].regmap,CCREG);
6247       if(cc==-1&&!likely[i]) {
6248         // Cycle count isn't in a register, temporarily load it then write it out
6249         emit_loadreg(CCREG,HOST_CCREG);
6250         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6251         int jaddr=(int)out;
6252         emit_jns(0);
6253         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6254         emit_storereg(CCREG,HOST_CCREG);
6255       }
6256       else{
6257         cc=get_reg(i_regmap,CCREG);
6258         assert(cc==HOST_CCREG);
6259         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
6260         int jaddr=(int)out;
6261         emit_jns(0);
6262         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6263       }
6264     }
6265   }
6266 }
6267
6268 void fjump_assemble(int i,struct regstat *i_regs)
6269 {
6270   signed char *i_regmap=i_regs->regmap;
6271   int cc;
6272   int match;
6273   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6274   assem_debug("fmatch=%d\n",match);
6275   int fs,cs;
6276   int eaddr;
6277   int invert=0;
6278   int internal=internal_branch(branch_regs[i].is32,ba[i]);
6279   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
6280   if(!match) invert=1;
6281   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6282   if(i>(ba[i]-start)>>2) invert=1;
6283   #endif
6284
6285   if(ooo[i]) {
6286     fs=get_reg(branch_regs[i].regmap,FSREG);
6287     address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
6288   }
6289   else {
6290     fs=get_reg(i_regmap,FSREG);
6291   }
6292
6293   // Check cop1 unusable
6294   if(!cop1_usable) {
6295     cs=get_reg(i_regmap,CSREG);
6296     assert(cs>=0);
6297     emit_testimm(cs,0x20000000);
6298     eaddr=(int)out;
6299     emit_jeq(0);
6300     add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
6301     cop1_usable=1;
6302   }
6303
6304   if(ooo[i]) {
6305     // Out of order execution (delay slot first)
6306     //printf("OOOE\n");
6307     ds_assemble(i+1,i_regs);
6308     int adj;
6309     uint64_t bc_unneeded=branch_regs[i].u;
6310     uint64_t bc_unneeded_upper=branch_regs[i].uu;
6311     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6312     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
6313     bc_unneeded|=1;
6314     bc_unneeded_upper|=1;
6315     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6316                   bc_unneeded,bc_unneeded_upper);
6317     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
6318     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6319     cc=get_reg(branch_regs[i].regmap,CCREG);
6320     assert(cc==HOST_CCREG);
6321     do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6322     assem_debug("cycle count (adj)\n");
6323     if(1) {
6324       int nottaken=0;
6325       if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6326       if(1) {
6327         assert(fs>=0);
6328         emit_testimm(fs,0x800000);
6329         if(source[i]&0x10000) // BC1T
6330         {
6331           if(invert){
6332             nottaken=(int)out;
6333             emit_jeq(1);
6334           }else{
6335             add_to_linker((int)out,ba[i],internal);
6336             emit_jne(0);
6337           }
6338         }
6339         else // BC1F
6340           if(invert){
6341             nottaken=(int)out;
6342             emit_jne(1);
6343           }else{
6344             add_to_linker((int)out,ba[i],internal);
6345             emit_jeq(0);
6346           }
6347         {
6348         }
6349       } // if(!only32)
6350
6351       if(invert) {
6352         if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6353         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6354         else if(match) emit_addnop(13);
6355         #endif
6356         store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6357         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6358         if(internal)
6359           assem_debug("branch: internal\n");
6360         else
6361           assem_debug("branch: external\n");
6362         if(internal&&is_ds[(ba[i]-start)>>2]) {
6363           ds_assemble_entry(i);
6364         }
6365         else {
6366           add_to_linker((int)out,ba[i],internal);
6367           emit_jmp(0);
6368         }
6369         set_jump_target(nottaken,(int)out);
6370       }
6371
6372       if(adj) {
6373         if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
6374       }
6375     } // (!unconditional)
6376   } // if(ooo)
6377   else
6378   {
6379     // In-order execution (branch first)
6380     //printf("IOE\n");
6381     int nottaken=0;
6382     if(1) {
6383       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6384       if(1) {
6385         assert(fs>=0);
6386         emit_testimm(fs,0x800000);
6387         if(source[i]&0x10000) // BC1T
6388         {
6389           nottaken=(int)out;
6390           emit_jeq(1);
6391         }
6392         else // BC1F
6393         {
6394           nottaken=(int)out;
6395           emit_jne(1);
6396         }
6397       }
6398     } // if(!unconditional)
6399     int adj;
6400     uint64_t ds_unneeded=branch_regs[i].u;
6401     uint64_t ds_unneeded_upper=branch_regs[i].uu;
6402     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6403     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6404     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6405     ds_unneeded|=1;
6406     ds_unneeded_upper|=1;
6407     // branch taken
6408     //assem_debug("1:\n");
6409     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6410                   ds_unneeded,ds_unneeded_upper);
6411     // load regs
6412     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6413     address_generation(i+1,&branch_regs[i],0);
6414     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6415     ds_assemble(i+1,&branch_regs[i]);
6416     cc=get_reg(branch_regs[i].regmap,CCREG);
6417     if(cc==-1) {
6418       emit_loadreg(CCREG,cc=HOST_CCREG);
6419       // CHECK: Is the following instruction (fall thru) allocated ok?
6420     }
6421     assert(cc==HOST_CCREG);
6422     store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6423     do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6424     assem_debug("cycle count (adj)\n");
6425     if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6426     load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6427     if(internal)
6428       assem_debug("branch: internal\n");
6429     else
6430       assem_debug("branch: external\n");
6431     if(internal&&is_ds[(ba[i]-start)>>2]) {
6432       ds_assemble_entry(i);
6433     }
6434     else {
6435       add_to_linker((int)out,ba[i],internal);
6436       emit_jmp(0);
6437     }
6438
6439     // branch not taken
6440     if(1) { // <- FIXME (don't need this)
6441       set_jump_target(nottaken,(int)out);
6442       assem_debug("1:\n");
6443       if(!likely[i]) {
6444         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6445                       ds_unneeded,ds_unneeded_upper);
6446         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6447         address_generation(i+1,&branch_regs[i],0);
6448         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6449         ds_assemble(i+1,&branch_regs[i]);
6450       }
6451       cc=get_reg(branch_regs[i].regmap,CCREG);
6452       if(cc==-1&&!likely[i]) {
6453         // Cycle count isn't in a register, temporarily load it then write it out
6454         emit_loadreg(CCREG,HOST_CCREG);
6455         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6456         int jaddr=(int)out;
6457         emit_jns(0);
6458         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6459         emit_storereg(CCREG,HOST_CCREG);
6460       }
6461       else{
6462         cc=get_reg(i_regmap,CCREG);
6463         assert(cc==HOST_CCREG);
6464         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
6465         int jaddr=(int)out;
6466         emit_jns(0);
6467         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6468       }
6469     }
6470   }
6471 }
6472
6473 static void pagespan_assemble(int i,struct regstat *i_regs)
6474 {
6475   int s1l=get_reg(i_regs->regmap,rs1[i]);
6476   int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6477   int s2l=get_reg(i_regs->regmap,rs2[i]);
6478   int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6479   void *nt_branch=NULL;
6480   int taken=0;
6481   int nottaken=0;
6482   int unconditional=0;
6483   if(rs1[i]==0)
6484   {
6485     s1l=s2l;s1h=s2h;
6486     s2l=s2h=-1;
6487   }
6488   else if(rs2[i]==0)
6489   {
6490     s2l=s2h=-1;
6491   }
6492   if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6493     s1h=s2h=-1;
6494   }
6495   int hr=0;
6496   int addr,alt,ntaddr;
6497   if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6498   else {
6499     while(hr<HOST_REGS)
6500     {
6501       if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6502          (i_regs->regmap[hr]&63)!=rs1[i] &&
6503          (i_regs->regmap[hr]&63)!=rs2[i] )
6504       {
6505         addr=hr++;break;
6506       }
6507       hr++;
6508     }
6509   }
6510   while(hr<HOST_REGS)
6511   {
6512     if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6513        (i_regs->regmap[hr]&63)!=rs1[i] &&
6514        (i_regs->regmap[hr]&63)!=rs2[i] )
6515     {
6516       alt=hr++;break;
6517     }
6518     hr++;
6519   }
6520   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6521   {
6522     while(hr<HOST_REGS)
6523     {
6524       if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6525          (i_regs->regmap[hr]&63)!=rs1[i] &&
6526          (i_regs->regmap[hr]&63)!=rs2[i] )
6527       {
6528         ntaddr=hr;break;
6529       }
6530       hr++;
6531     }
6532   }
6533   assert(hr<HOST_REGS);
6534   if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6535     load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6536   }
6537   emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6538   if(opcode[i]==2) // J
6539   {
6540     unconditional=1;
6541   }
6542   if(opcode[i]==3) // JAL
6543   {
6544     // TODO: mini_ht
6545     int rt=get_reg(i_regs->regmap,31);
6546     emit_movimm(start+i*4+8,rt);
6547     unconditional=1;
6548   }
6549   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6550   {
6551     emit_mov(s1l,addr);
6552     if(opcode2[i]==9) // JALR
6553     {
6554       int rt=get_reg(i_regs->regmap,rt1[i]);
6555       emit_movimm(start+i*4+8,rt);
6556     }
6557   }
6558   if((opcode[i]&0x3f)==4) // BEQ
6559   {
6560     if(rs1[i]==rs2[i])
6561     {
6562       unconditional=1;
6563     }
6564     else
6565     #ifdef HAVE_CMOV_IMM
6566     if(s1h<0) {
6567       if(s2l>=0) emit_cmp(s1l,s2l);
6568       else emit_test(s1l,s1l);
6569       emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6570     }
6571     else
6572     #endif
6573     {
6574       assert(s1l>=0);
6575       emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6576       if(s1h>=0) {
6577         if(s2h>=0) emit_cmp(s1h,s2h);
6578         else emit_test(s1h,s1h);
6579         emit_cmovne_reg(alt,addr);
6580       }
6581       if(s2l>=0) emit_cmp(s1l,s2l);
6582       else emit_test(s1l,s1l);
6583       emit_cmovne_reg(alt,addr);
6584     }
6585   }
6586   if((opcode[i]&0x3f)==5) // BNE
6587   {
6588     #ifdef HAVE_CMOV_IMM
6589     if(s1h<0) {
6590       if(s2l>=0) emit_cmp(s1l,s2l);
6591       else emit_test(s1l,s1l);
6592       emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6593     }
6594     else
6595     #endif
6596     {
6597       assert(s1l>=0);
6598       emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6599       if(s1h>=0) {
6600         if(s2h>=0) emit_cmp(s1h,s2h);
6601         else emit_test(s1h,s1h);
6602         emit_cmovne_reg(alt,addr);
6603       }
6604       if(s2l>=0) emit_cmp(s1l,s2l);
6605       else emit_test(s1l,s1l);
6606       emit_cmovne_reg(alt,addr);
6607     }
6608   }
6609   if((opcode[i]&0x3f)==0x14) // BEQL
6610   {
6611     if(s1h>=0) {
6612       if(s2h>=0) emit_cmp(s1h,s2h);
6613       else emit_test(s1h,s1h);
6614       nottaken=(int)out;
6615       emit_jne(0);
6616     }
6617     if(s2l>=0) emit_cmp(s1l,s2l);
6618     else emit_test(s1l,s1l);
6619     if(nottaken) set_jump_target(nottaken,(int)out);
6620     nottaken=(int)out;
6621     emit_jne(0);
6622   }
6623   if((opcode[i]&0x3f)==0x15) // BNEL
6624   {
6625     if(s1h>=0) {
6626       if(s2h>=0) emit_cmp(s1h,s2h);
6627       else emit_test(s1h,s1h);
6628       taken=(int)out;
6629       emit_jne(0);
6630     }
6631     if(s2l>=0) emit_cmp(s1l,s2l);
6632     else emit_test(s1l,s1l);
6633     nottaken=(int)out;
6634     emit_jeq(0);
6635     if(taken) set_jump_target(taken,(int)out);
6636   }
6637   if((opcode[i]&0x3f)==6) // BLEZ
6638   {
6639     emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6640     emit_cmpimm(s1l,1);
6641     if(s1h>=0) emit_mov(addr,ntaddr);
6642     emit_cmovl_reg(alt,addr);
6643     if(s1h>=0) {
6644       emit_test(s1h,s1h);
6645       emit_cmovne_reg(ntaddr,addr);
6646       emit_cmovs_reg(alt,addr);
6647     }
6648   }
6649   if((opcode[i]&0x3f)==7) // BGTZ
6650   {
6651     emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6652     emit_cmpimm(s1l,1);
6653     if(s1h>=0) emit_mov(addr,alt);
6654     emit_cmovl_reg(ntaddr,addr);
6655     if(s1h>=0) {
6656       emit_test(s1h,s1h);
6657       emit_cmovne_reg(alt,addr);
6658       emit_cmovs_reg(ntaddr,addr);
6659     }
6660   }
6661   if((opcode[i]&0x3f)==0x16) // BLEZL
6662   {
6663     assert((opcode[i]&0x3f)!=0x16);
6664   }
6665   if((opcode[i]&0x3f)==0x17) // BGTZL
6666   {
6667     assert((opcode[i]&0x3f)!=0x17);
6668   }
6669   assert(opcode[i]!=1); // BLTZ/BGEZ
6670
6671   //FIXME: Check CSREG
6672   if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6673     if((source[i]&0x30000)==0) // BC1F
6674     {
6675       emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6676       emit_testimm(s1l,0x800000);
6677       emit_cmovne_reg(alt,addr);
6678     }
6679     if((source[i]&0x30000)==0x10000) // BC1T
6680     {
6681       emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6682       emit_testimm(s1l,0x800000);
6683       emit_cmovne_reg(alt,addr);
6684     }
6685     if((source[i]&0x30000)==0x20000) // BC1FL
6686     {
6687       emit_testimm(s1l,0x800000);
6688       nottaken=(int)out;
6689       emit_jne(0);
6690     }
6691     if((source[i]&0x30000)==0x30000) // BC1TL
6692     {
6693       emit_testimm(s1l,0x800000);
6694       nottaken=(int)out;
6695       emit_jeq(0);
6696     }
6697   }
6698
6699   assert(i_regs->regmap[HOST_CCREG]==CCREG);
6700   wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6701   if(likely[i]||unconditional)
6702   {
6703     emit_movimm(ba[i],HOST_BTREG);
6704   }
6705   else if(addr!=HOST_BTREG)
6706   {
6707     emit_mov(addr,HOST_BTREG);
6708   }
6709   void *branch_addr=out;
6710   emit_jmp(0);
6711   int target_addr=start+i*4+5;
6712   void *stub=out;
6713   void *compiled_target_addr=check_addr(target_addr);
6714   emit_extjump_ds((int)branch_addr,target_addr);
6715   if(compiled_target_addr) {
6716     set_jump_target((int)branch_addr,(int)compiled_target_addr);
6717     add_link(target_addr,stub);
6718   }
6719   else set_jump_target((int)branch_addr,(int)stub);
6720   if(likely[i]) {
6721     // Not-taken path
6722     set_jump_target((int)nottaken,(int)out);
6723     wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6724     void *branch_addr=out;
6725     emit_jmp(0);
6726     int target_addr=start+i*4+8;
6727     void *stub=out;
6728     void *compiled_target_addr=check_addr(target_addr);
6729     emit_extjump_ds((int)branch_addr,target_addr);
6730     if(compiled_target_addr) {
6731       set_jump_target((int)branch_addr,(int)compiled_target_addr);
6732       add_link(target_addr,stub);
6733     }
6734     else set_jump_target((int)branch_addr,(int)stub);
6735   }
6736 }
6737
6738 // Assemble the delay slot for the above
6739 static void pagespan_ds()
6740 {
6741   assem_debug("initial delay slot:\n");
6742   u_int vaddr=start+1;
6743   u_int page=get_page(vaddr);
6744   u_int vpage=get_vpage(vaddr);
6745   ll_add(jump_dirty+vpage,vaddr,(void *)out);
6746   do_dirty_stub_ds();
6747   ll_add(jump_in+page,vaddr,(void *)out);
6748   assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6749   if(regs[0].regmap[HOST_CCREG]!=CCREG)
6750     wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6751   if(regs[0].regmap[HOST_BTREG]!=BTREG)
6752     emit_writeword(HOST_BTREG,(int)&branch_target);
6753   load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6754   address_generation(0,&regs[0],regs[0].regmap_entry);
6755   if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
6756     load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6757   cop1_usable=0;
6758   is_delayslot=0;
6759   switch(itype[0]) {
6760     case ALU:
6761       alu_assemble(0,&regs[0]);break;
6762     case IMM16:
6763       imm16_assemble(0,&regs[0]);break;
6764     case SHIFT:
6765       shift_assemble(0,&regs[0]);break;
6766     case SHIFTIMM:
6767       shiftimm_assemble(0,&regs[0]);break;
6768     case LOAD:
6769       load_assemble(0,&regs[0]);break;
6770     case LOADLR:
6771       loadlr_assemble(0,&regs[0]);break;
6772     case STORE:
6773       store_assemble(0,&regs[0]);break;
6774     case STORELR:
6775       storelr_assemble(0,&regs[0]);break;
6776     case COP0:
6777       cop0_assemble(0,&regs[0]);break;
6778     case COP1:
6779       cop1_assemble(0,&regs[0]);break;
6780     case C1LS:
6781       c1ls_assemble(0,&regs[0]);break;
6782     case COP2:
6783       cop2_assemble(0,&regs[0]);break;
6784     case C2LS:
6785       c2ls_assemble(0,&regs[0]);break;
6786     case C2OP:
6787       c2op_assemble(0,&regs[0]);break;
6788     case FCONV:
6789       fconv_assemble(0,&regs[0]);break;
6790     case FLOAT:
6791       float_assemble(0,&regs[0]);break;
6792     case FCOMP:
6793       fcomp_assemble(0,&regs[0]);break;
6794     case MULTDIV:
6795       multdiv_assemble(0,&regs[0]);break;
6796     case MOV:
6797       mov_assemble(0,&regs[0]);break;
6798     case SYSCALL:
6799     case HLECALL:
6800     case INTCALL:
6801     case SPAN:
6802     case UJUMP:
6803     case RJUMP:
6804     case CJUMP:
6805     case SJUMP:
6806     case FJUMP:
6807       printf("Jump in the delay slot.  This is probably a bug.\n");
6808   }
6809   int btaddr=get_reg(regs[0].regmap,BTREG);
6810   if(btaddr<0) {
6811     btaddr=get_reg(regs[0].regmap,-1);
6812     emit_readword((int)&branch_target,btaddr);
6813   }
6814   assert(btaddr!=HOST_CCREG);
6815   if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6816 #ifdef HOST_IMM8
6817   emit_movimm(start+4,HOST_TEMPREG);
6818   emit_cmp(btaddr,HOST_TEMPREG);
6819 #else
6820   emit_cmpimm(btaddr,start+4);
6821 #endif
6822   int branch=(int)out;
6823   emit_jeq(0);
6824   store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6825   emit_jmp(jump_vaddr_reg[btaddr]);
6826   set_jump_target(branch,(int)out);
6827   store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6828   load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6829 }
6830
6831 // Basic liveness analysis for MIPS registers
6832 void unneeded_registers(int istart,int iend,int r)
6833 {
6834   int i;
6835   uint64_t u,uu,gte_u,b,bu,gte_bu;
6836   uint64_t temp_u,temp_uu,temp_gte_u=0;
6837   uint64_t tdep;
6838   uint64_t gte_u_unknown=0;
6839   if(new_dynarec_hacks&NDHACK_GTE_UNNEEDED)
6840     gte_u_unknown=~0ll;
6841   if(iend==slen-1) {
6842     u=1;uu=1;
6843     gte_u=gte_u_unknown;
6844   }else{
6845     u=unneeded_reg[iend+1];
6846     uu=unneeded_reg_upper[iend+1];
6847     u=1;uu=1;
6848     gte_u=gte_unneeded[iend+1];
6849   }
6850
6851   for (i=iend;i>=istart;i--)
6852   {
6853     //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6854     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6855     {
6856       // If subroutine call, flag return address as a possible branch target
6857       if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6858
6859       if(ba[i]<start || ba[i]>=(start+slen*4))
6860       {
6861         // Branch out of this block, flush all regs
6862         u=1;
6863         uu=1;
6864         gte_u=gte_u_unknown;
6865         /* Hexagon hack
6866         if(itype[i]==UJUMP&&rt1[i]==31)
6867         {
6868           uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6869         }
6870         if(itype[i]==RJUMP&&rs1[i]==31)
6871         {
6872           uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6873         }
6874         if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
6875           if(itype[i]==UJUMP&&rt1[i]==31)
6876           {
6877             //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6878             uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6879           }
6880           if(itype[i]==RJUMP&&rs1[i]==31)
6881           {
6882             //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6883             uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6884           }
6885         }*/
6886         branch_unneeded_reg[i]=u;
6887         branch_unneeded_reg_upper[i]=uu;
6888         // Merge in delay slot
6889         tdep=(~uu>>rt1[i+1])&1;
6890         u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6891         uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6892         u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6893         uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6894         uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6895         u|=1;uu|=1;
6896         gte_u|=gte_rt[i+1];
6897         gte_u&=~gte_rs[i+1];
6898         // If branch is "likely" (and conditional)
6899         // then we skip the delay slot on the fall-thru path
6900         if(likely[i]) {
6901           if(i<slen-1) {
6902             u&=unneeded_reg[i+2];
6903             uu&=unneeded_reg_upper[i+2];
6904             gte_u&=gte_unneeded[i+2];
6905           }
6906           else
6907           {
6908             u=1;
6909             uu=1;
6910             gte_u=gte_u_unknown;
6911           }
6912         }
6913       }
6914       else
6915       {
6916         // Internal branch, flag target
6917         bt[(ba[i]-start)>>2]=1;
6918         if(ba[i]<=start+i*4) {
6919           // Backward branch
6920           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6921           {
6922             // Unconditional branch
6923             temp_u=1;temp_uu=1;
6924             temp_gte_u=0;
6925           } else {
6926             // Conditional branch (not taken case)
6927             temp_u=unneeded_reg[i+2];
6928             temp_uu=unneeded_reg_upper[i+2];
6929             temp_gte_u&=gte_unneeded[i+2];
6930           }
6931           // Merge in delay slot
6932           tdep=(~temp_uu>>rt1[i+1])&1;
6933           temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6934           temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6935           temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6936           temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6937           temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6938           temp_u|=1;temp_uu|=1;
6939           temp_gte_u|=gte_rt[i+1];
6940           temp_gte_u&=~gte_rs[i+1];
6941           // If branch is "likely" (and conditional)
6942           // then we skip the delay slot on the fall-thru path
6943           if(likely[i]) {
6944             if(i<slen-1) {
6945               temp_u&=unneeded_reg[i+2];
6946               temp_uu&=unneeded_reg_upper[i+2];
6947               temp_gte_u&=gte_unneeded[i+2];
6948             }
6949             else
6950             {
6951               temp_u=1;
6952               temp_uu=1;
6953               temp_gte_u=gte_u_unknown;
6954             }
6955           }
6956           tdep=(~temp_uu>>rt1[i])&1;
6957           temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6958           temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6959           temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6960           temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6961           temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6962           temp_u|=1;temp_uu|=1;
6963           temp_gte_u|=gte_rt[i];
6964           temp_gte_u&=~gte_rs[i];
6965           unneeded_reg[i]=temp_u;
6966           unneeded_reg_upper[i]=temp_uu;
6967           gte_unneeded[i]=temp_gte_u;
6968           // Only go three levels deep.  This recursion can take an
6969           // excessive amount of time if there are a lot of nested loops.
6970           if(r<2) {
6971             unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6972           }else{
6973             unneeded_reg[(ba[i]-start)>>2]=1;
6974             unneeded_reg_upper[(ba[i]-start)>>2]=1;
6975             gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown;
6976           }
6977         } /*else*/ if(1) {
6978           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6979           {
6980             // Unconditional branch
6981             u=unneeded_reg[(ba[i]-start)>>2];
6982             uu=unneeded_reg_upper[(ba[i]-start)>>2];
6983             gte_u=gte_unneeded[(ba[i]-start)>>2];
6984             branch_unneeded_reg[i]=u;
6985             branch_unneeded_reg_upper[i]=uu;
6986         //u=1;
6987         //uu=1;
6988         //branch_unneeded_reg[i]=u;
6989         //branch_unneeded_reg_upper[i]=uu;
6990             // Merge in delay slot
6991             tdep=(~uu>>rt1[i+1])&1;
6992             u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6993             uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6994             u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6995             uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6996             uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6997             u|=1;uu|=1;
6998             gte_u|=gte_rt[i+1];
6999             gte_u&=~gte_rs[i+1];
7000           } else {
7001             // Conditional branch
7002             b=unneeded_reg[(ba[i]-start)>>2];
7003             bu=unneeded_reg_upper[(ba[i]-start)>>2];
7004             gte_bu=gte_unneeded[(ba[i]-start)>>2];
7005             branch_unneeded_reg[i]=b;
7006             branch_unneeded_reg_upper[i]=bu;
7007         //b=1;
7008         //bu=1;
7009         //branch_unneeded_reg[i]=b;
7010         //branch_unneeded_reg_upper[i]=bu;
7011             // Branch delay slot
7012             tdep=(~uu>>rt1[i+1])&1;
7013             b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
7014             bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
7015             b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
7016             bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
7017             bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
7018             b|=1;bu|=1;
7019             gte_bu|=gte_rt[i+1];
7020             gte_bu&=~gte_rs[i+1];
7021             // If branch is "likely" then we skip the
7022             // delay slot on the fall-thru path
7023             if(likely[i]) {
7024               u=b;
7025               uu=bu;
7026               gte_u=gte_bu;
7027               if(i<slen-1) {
7028                 u&=unneeded_reg[i+2];
7029                 uu&=unneeded_reg_upper[i+2];
7030                 gte_u&=gte_unneeded[i+2];
7031         //u=1;
7032         //uu=1;
7033               }
7034             } else {
7035               u&=b;
7036               uu&=bu;
7037               gte_u&=gte_bu;
7038         //u=1;
7039         //uu=1;
7040             }
7041             if(i<slen-1) {
7042               branch_unneeded_reg[i]&=unneeded_reg[i+2];
7043               branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
7044         //branch_unneeded_reg[i]=1;
7045         //branch_unneeded_reg_upper[i]=1;
7046             } else {
7047               branch_unneeded_reg[i]=1;
7048               branch_unneeded_reg_upper[i]=1;
7049             }
7050           }
7051         }
7052       }
7053     }
7054     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7055     {
7056       // SYSCALL instruction (software interrupt)
7057       u=1;
7058       uu=1;
7059     }
7060     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7061     {
7062       // ERET instruction (return from interrupt)
7063       u=1;
7064       uu=1;
7065     }
7066     //u=uu=1; // DEBUG
7067     tdep=(~uu>>rt1[i])&1;
7068     // Written registers are unneeded
7069     u|=1LL<<rt1[i];
7070     u|=1LL<<rt2[i];
7071     uu|=1LL<<rt1[i];
7072     uu|=1LL<<rt2[i];
7073     gte_u|=gte_rt[i];
7074     // Accessed registers are needed
7075     u&=~(1LL<<rs1[i]);
7076     u&=~(1LL<<rs2[i]);
7077     uu&=~(1LL<<us1[i]);
7078     uu&=~(1LL<<us2[i]);
7079     gte_u&=~gte_rs[i];
7080     if(gte_rs[i]&&rt1[i]&&(unneeded_reg[i+1]&(1ll<<rt1[i])))
7081       gte_u|=gte_rs[i]&gte_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded
7082     // Source-target dependencies
7083     uu&=~(tdep<<dep1[i]);
7084     uu&=~(tdep<<dep2[i]);
7085     // R0 is always unneeded
7086     u|=1;uu|=1;
7087     // Save it
7088     unneeded_reg[i]=u;
7089     unneeded_reg_upper[i]=uu;
7090     gte_unneeded[i]=gte_u;
7091     /*
7092     printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
7093     printf("U:");
7094     int r;
7095     for(r=1;r<=CCREG;r++) {
7096       if((unneeded_reg[i]>>r)&1) {
7097         if(r==HIREG) printf(" HI");
7098         else if(r==LOREG) printf(" LO");
7099         else printf(" r%d",r);
7100       }
7101     }
7102     printf(" UU:");
7103     for(r=1;r<=CCREG;r++) {
7104       if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
7105         if(r==HIREG) printf(" HI");
7106         else if(r==LOREG) printf(" LO");
7107         else printf(" r%d",r);
7108       }
7109     }
7110     printf("\n");*/
7111   }
7112 #ifdef FORCE32
7113   for (i=iend;i>=istart;i--)
7114   {
7115     unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
7116   }
7117 #endif
7118 }
7119
7120 // Identify registers which are likely to contain 32-bit values
7121 // This is used to predict whether any branches will jump to a
7122 // location with 64-bit values in registers.
7123 static void provisional_32bit()
7124 {
7125   int i,j;
7126   uint64_t is32=1;
7127   uint64_t lastbranch=1;
7128
7129   for(i=0;i<slen;i++)
7130   {
7131     if(i>0) {
7132       if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
7133         if(i>1) is32=lastbranch;
7134         else is32=1;
7135       }
7136     }
7137     if(i>1)
7138     {
7139       if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
7140         if(likely[i-2]) {
7141           if(i>2) is32=lastbranch;
7142           else is32=1;
7143         }
7144       }
7145       if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
7146       {
7147         if(rs1[i-2]==0||rs2[i-2]==0)
7148         {
7149           if(rs1[i-2]) {
7150             is32|=1LL<<rs1[i-2];
7151           }
7152           if(rs2[i-2]) {
7153             is32|=1LL<<rs2[i-2];
7154           }
7155         }
7156       }
7157     }
7158     // If something jumps here with 64-bit values
7159     // then promote those registers to 64 bits
7160     if(bt[i])
7161     {
7162       uint64_t temp_is32=is32;
7163       for(j=i-1;j>=0;j--)
7164       {
7165         if(ba[j]==start+i*4)
7166           //temp_is32&=branch_regs[j].is32;
7167           temp_is32&=p32[j];
7168       }
7169       for(j=i;j<slen;j++)
7170       {
7171         if(ba[j]==start+i*4)
7172           temp_is32=1;
7173       }
7174       is32=temp_is32;
7175     }
7176     int type=itype[i];
7177     int op=opcode[i];
7178     int op2=opcode2[i];
7179     int rt=rt1[i];
7180     int s1=rs1[i];
7181     int s2=rs2[i];
7182     if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
7183       // Branches don't write registers, consider the delay slot instead.
7184       type=itype[i+1];
7185       op=opcode[i+1];
7186       op2=opcode2[i+1];
7187       rt=rt1[i+1];
7188       s1=rs1[i+1];
7189       s2=rs2[i+1];
7190       lastbranch=is32;
7191     }
7192     switch(type) {
7193       case LOAD:
7194         if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
7195            opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
7196           is32&=~(1LL<<rt);
7197         else
7198           is32|=1LL<<rt;
7199         break;
7200       case STORE:
7201       case STORELR:
7202         break;
7203       case LOADLR:
7204         if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
7205         if(op==0x22) is32|=1LL<<rt; // LWL
7206         break;
7207       case IMM16:
7208         if (op==0x08||op==0x09|| // ADDI/ADDIU
7209             op==0x0a||op==0x0b|| // SLTI/SLTIU
7210             op==0x0c|| // ANDI
7211             op==0x0f)  // LUI
7212         {
7213           is32|=1LL<<rt;
7214         }
7215         if(op==0x18||op==0x19) { // DADDI/DADDIU
7216           is32&=~(1LL<<rt);
7217           //if(imm[i]==0)
7218           //  is32|=((is32>>s1)&1LL)<<rt;
7219         }
7220         if(op==0x0d||op==0x0e) { // ORI/XORI
7221           uint64_t sr=((is32>>s1)&1LL);
7222           is32&=~(1LL<<rt);
7223           is32|=sr<<rt;
7224         }
7225         break;
7226       case UJUMP:
7227         break;
7228       case RJUMP:
7229         break;
7230       case CJUMP:
7231         break;
7232       case SJUMP:
7233         break;
7234       case FJUMP:
7235         break;
7236       case ALU:
7237         if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
7238           is32|=1LL<<rt;
7239         }
7240         if(op2==0x2a||op2==0x2b) { // SLT/SLTU
7241           is32|=1LL<<rt;
7242         }
7243         else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
7244           uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
7245           is32&=~(1LL<<rt);
7246           is32|=sr<<rt;
7247         }
7248         else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
7249           if(s1==0&&s2==0) {
7250             is32|=1LL<<rt;
7251           }
7252           else if(s2==0) {
7253             uint64_t sr=((is32>>s1)&1LL);
7254             is32&=~(1LL<<rt);
7255             is32|=sr<<rt;
7256           }
7257           else if(s1==0) {
7258             uint64_t sr=((is32>>s2)&1LL);
7259             is32&=~(1LL<<rt);
7260             is32|=sr<<rt;
7261           }
7262           else {
7263             is32&=~(1LL<<rt);
7264           }
7265         }
7266         else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
7267           if(s1==0&&s2==0) {
7268             is32|=1LL<<rt;
7269           }
7270           else if(s2==0) {
7271             uint64_t sr=((is32>>s1)&1LL);
7272             is32&=~(1LL<<rt);
7273             is32|=sr<<rt;
7274           }
7275           else {
7276             is32&=~(1LL<<rt);
7277           }
7278         }
7279         break;
7280       case MULTDIV:
7281         if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
7282           is32&=~((1LL<<HIREG)|(1LL<<LOREG));
7283         }
7284         else {
7285           is32|=(1LL<<HIREG)|(1LL<<LOREG);
7286         }
7287         break;
7288       case MOV:
7289         {
7290           uint64_t sr=((is32>>s1)&1LL);
7291           is32&=~(1LL<<rt);
7292           is32|=sr<<rt;
7293         }
7294         break;
7295       case SHIFT:
7296         if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
7297         else is32|=1LL<<rt; // SLLV/SRLV/SRAV
7298         break;
7299       case SHIFTIMM:
7300         is32|=1LL<<rt;
7301         // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
7302         if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
7303         break;
7304       case COP0:
7305         if(op2==0) is32|=1LL<<rt; // MFC0
7306         break;
7307       case COP1:
7308       case COP2:
7309         if(op2==0) is32|=1LL<<rt; // MFC1
7310         if(op2==1) is32&=~(1LL<<rt); // DMFC1
7311         if(op2==2) is32|=1LL<<rt; // CFC1
7312         break;
7313       case C1LS:
7314       case C2LS:
7315         break;
7316       case FLOAT:
7317       case FCONV:
7318         break;
7319       case FCOMP:
7320         break;
7321       case C2OP:
7322       case SYSCALL:
7323       case HLECALL:
7324         break;
7325       default:
7326         break;
7327     }
7328     is32|=1;
7329     p32[i]=is32;
7330
7331     if(i>0)
7332     {
7333       if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
7334       {
7335         if(rt1[i-1]==31) // JAL/JALR
7336         {
7337           // Subroutine call will return here, don't alloc any registers
7338           is32=1;
7339         }
7340         else if(i+1<slen)
7341         {
7342           // Internal branch will jump here, match registers to caller
7343           is32=0x3FFFFFFFFLL;
7344         }
7345       }
7346     }
7347   }
7348 }
7349
7350 // Identify registers which may be assumed to contain 32-bit values
7351 // and where optimizations will rely on this.
7352 // This is used to determine whether backward branches can safely
7353 // jump to a location with 64-bit values in registers.
7354 static void provisional_r32()
7355 {
7356   u_int r32=0;
7357   int i;
7358
7359   for (i=slen-1;i>=0;i--)
7360   {
7361     int hr;
7362     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7363     {
7364       if(ba[i]<start || ba[i]>=(start+slen*4))
7365       {
7366         // Branch out of this block, don't need anything
7367         r32=0;
7368       }
7369       else
7370       {
7371         // Internal branch
7372         // Need whatever matches the target
7373         // (and doesn't get overwritten by the delay slot instruction)
7374         r32=0;
7375         int t=(ba[i]-start)>>2;
7376         if(ba[i]>start+i*4) {
7377           // Forward branch
7378           //if(!(requires_32bit[t]&~regs[i].was32))
7379           //  r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7380           if(!(pr32[t]&~regs[i].was32))
7381             r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7382         }else{
7383           // Backward branch
7384           if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
7385             r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7386         }
7387       }
7388       // Conditional branch may need registers for following instructions
7389       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7390       {
7391         if(i<slen-2) {
7392           //r32|=requires_32bit[i+2];
7393           r32|=pr32[i+2];
7394           r32&=regs[i].was32;
7395           // Mark this address as a branch target since it may be called
7396           // upon return from interrupt
7397           //bt[i+2]=1;
7398         }
7399       }
7400       // Merge in delay slot
7401       if(!likely[i]) {
7402         // These are overwritten unless the branch is "likely"
7403         // and the delay slot is nullified if not taken
7404         r32&=~(1LL<<rt1[i+1]);
7405         r32&=~(1LL<<rt2[i+1]);
7406       }
7407       // Assume these are needed (delay slot)
7408       if(us1[i+1]>0)
7409       {
7410         if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7411       }
7412       if(us2[i+1]>0)
7413       {
7414         if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7415       }
7416       if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7417       {
7418         if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7419       }
7420       if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7421       {
7422         if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7423       }
7424     }
7425     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7426     {
7427       // SYSCALL instruction (software interrupt)
7428       r32=0;
7429     }
7430     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7431     {
7432       // ERET instruction (return from interrupt)
7433       r32=0;
7434     }
7435     // Check 32 bits
7436     r32&=~(1LL<<rt1[i]);
7437     r32&=~(1LL<<rt2[i]);
7438     if(us1[i]>0)
7439     {
7440       if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7441     }
7442     if(us2[i]>0)
7443     {
7444       if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7445     }
7446     if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7447     {
7448       if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7449     }
7450     if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7451     {
7452       if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7453     }
7454     //requires_32bit[i]=r32;
7455     pr32[i]=r32;
7456
7457     // Dirty registers which are 32-bit, require 32-bit input
7458     // as they will be written as 32-bit values
7459     for(hr=0;hr<HOST_REGS;hr++)
7460     {
7461       if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
7462         if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7463           if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7464           pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7465           //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7466         }
7467       }
7468     }
7469   }
7470 }
7471
7472 // Write back dirty registers as soon as we will no longer modify them,
7473 // so that we don't end up with lots of writes at the branches.
7474 void clean_registers(int istart,int iend,int wr)
7475 {
7476   int i;
7477   int r;
7478   u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7479   u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7480   if(iend==slen-1) {
7481     will_dirty_i=will_dirty_next=0;
7482     wont_dirty_i=wont_dirty_next=0;
7483   }else{
7484     will_dirty_i=will_dirty_next=will_dirty[iend+1];
7485     wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7486   }
7487   for (i=iend;i>=istart;i--)
7488   {
7489     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7490     {
7491       if(ba[i]<start || ba[i]>=(start+slen*4))
7492       {
7493         // Branch out of this block, flush all regs
7494         if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7495         {
7496           // Unconditional branch
7497           will_dirty_i=0;
7498           wont_dirty_i=0;
7499           // Merge in delay slot (will dirty)
7500           for(r=0;r<HOST_REGS;r++) {
7501             if(r!=EXCLUDE_REG) {
7502               if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7503               if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7504               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7505               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7506               if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7507               if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7508               if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7509               if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7510               if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7511               if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7512               if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7513               if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7514               if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7515               if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7516             }
7517           }
7518         }
7519         else
7520         {
7521           // Conditional branch
7522           will_dirty_i=0;
7523           wont_dirty_i=wont_dirty_next;
7524           // Merge in delay slot (will dirty)
7525           for(r=0;r<HOST_REGS;r++) {
7526             if(r!=EXCLUDE_REG) {
7527               if(!likely[i]) {
7528                 // Might not dirty if likely branch is not taken
7529                 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7530                 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7531                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7532                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7533                 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7534                 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7535                 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7536                 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7537                 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7538                 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7539                 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7540                 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7541                 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7542                 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7543               }
7544             }
7545           }
7546         }
7547         // Merge in delay slot (wont dirty)
7548         for(r=0;r<HOST_REGS;r++) {
7549           if(r!=EXCLUDE_REG) {
7550             if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7551             if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7552             if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7553             if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7554             if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7555             if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7556             if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7557             if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7558             if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7559             if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7560           }
7561         }
7562         if(wr) {
7563           #ifndef DESTRUCTIVE_WRITEBACK
7564           branch_regs[i].dirty&=wont_dirty_i;
7565           #endif
7566           branch_regs[i].dirty|=will_dirty_i;
7567         }
7568       }
7569       else
7570       {
7571         // Internal branch
7572         if(ba[i]<=start+i*4) {
7573           // Backward branch
7574           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7575           {
7576             // Unconditional branch
7577             temp_will_dirty=0;
7578             temp_wont_dirty=0;
7579             // Merge in delay slot (will dirty)
7580             for(r=0;r<HOST_REGS;r++) {
7581               if(r!=EXCLUDE_REG) {
7582                 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7583                 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7584                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7585                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7586                 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7587                 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7588                 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7589                 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7590                 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7591                 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7592                 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7593                 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7594                 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7595                 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7596               }
7597             }
7598           } else {
7599             // Conditional branch (not taken case)
7600             temp_will_dirty=will_dirty_next;
7601             temp_wont_dirty=wont_dirty_next;
7602             // Merge in delay slot (will dirty)
7603             for(r=0;r<HOST_REGS;r++) {
7604               if(r!=EXCLUDE_REG) {
7605                 if(!likely[i]) {
7606                   // Will not dirty if likely branch is not taken
7607                   if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7608                   if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7609                   if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7610                   if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7611                   if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7612                   if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7613                   if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7614                   //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7615                   //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7616                   if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7617                   if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7618                   if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7619                   if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7620                   if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7621                 }
7622               }
7623             }
7624           }
7625           // Merge in delay slot (wont dirty)
7626           for(r=0;r<HOST_REGS;r++) {
7627             if(r!=EXCLUDE_REG) {
7628               if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7629               if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7630               if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7631               if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7632               if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7633               if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7634               if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7635               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7636               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7637               if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7638             }
7639           }
7640           // Deal with changed mappings
7641           if(i<iend) {
7642             for(r=0;r<HOST_REGS;r++) {
7643               if(r!=EXCLUDE_REG) {
7644                 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7645                   temp_will_dirty&=~(1<<r);
7646                   temp_wont_dirty&=~(1<<r);
7647                   if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7648                     temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7649                     temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7650                   } else {
7651                     temp_will_dirty|=1<<r;
7652                     temp_wont_dirty|=1<<r;
7653                   }
7654                 }
7655               }
7656             }
7657           }
7658           if(wr) {
7659             will_dirty[i]=temp_will_dirty;
7660             wont_dirty[i]=temp_wont_dirty;
7661             clean_registers((ba[i]-start)>>2,i-1,0);
7662           }else{
7663             // Limit recursion.  It can take an excessive amount
7664             // of time if there are a lot of nested loops.
7665             will_dirty[(ba[i]-start)>>2]=0;
7666             wont_dirty[(ba[i]-start)>>2]=-1;
7667           }
7668         }
7669         /*else*/ if(1)
7670         {
7671           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7672           {
7673             // Unconditional branch
7674             will_dirty_i=0;
7675             wont_dirty_i=0;
7676           //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7677             for(r=0;r<HOST_REGS;r++) {
7678               if(r!=EXCLUDE_REG) {
7679                 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7680                   will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7681                   wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7682                 }
7683                 if(branch_regs[i].regmap[r]>=0) {
7684                   will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7685                   wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7686                 }
7687               }
7688             }
7689           //}
7690             // Merge in delay slot
7691             for(r=0;r<HOST_REGS;r++) {
7692               if(r!=EXCLUDE_REG) {
7693                 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7694                 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7695                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7696                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7697                 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7698                 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7699                 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7700                 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7701                 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7702                 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7703                 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7704                 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7705                 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7706                 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7707               }
7708             }
7709           } else {
7710             // Conditional branch
7711             will_dirty_i=will_dirty_next;
7712             wont_dirty_i=wont_dirty_next;
7713           //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7714             for(r=0;r<HOST_REGS;r++) {
7715               if(r!=EXCLUDE_REG) {
7716                 signed char target_reg=branch_regs[i].regmap[r];
7717                 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7718                   will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7719                   wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7720                 }
7721                 else if(target_reg>=0) {
7722                   will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7723                   wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7724                 }
7725                 // Treat delay slot as part of branch too
7726                 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7727                   will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7728                   wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7729                 }
7730                 else
7731                 {
7732                   will_dirty[i+1]&=~(1<<r);
7733                 }*/
7734               }
7735             }
7736           //}
7737             // Merge in delay slot
7738             for(r=0;r<HOST_REGS;r++) {
7739               if(r!=EXCLUDE_REG) {
7740                 if(!likely[i]) {
7741                   // Might not dirty if likely branch is not taken
7742                   if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7743                   if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7744                   if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7745                   if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7746                   if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7747                   if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7748                   if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7749                   //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7750                   //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7751                   if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7752                   if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7753                   if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7754                   if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7755                   if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7756                 }
7757               }
7758             }
7759           }
7760           // Merge in delay slot (won't dirty)
7761           for(r=0;r<HOST_REGS;r++) {
7762             if(r!=EXCLUDE_REG) {
7763               if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7764               if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7765               if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7766               if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7767               if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7768               if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7769               if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7770               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7771               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7772               if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7773             }
7774           }
7775           if(wr) {
7776             #ifndef DESTRUCTIVE_WRITEBACK
7777             branch_regs[i].dirty&=wont_dirty_i;
7778             #endif
7779             branch_regs[i].dirty|=will_dirty_i;
7780           }
7781         }
7782       }
7783     }
7784     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7785     {
7786       // SYSCALL instruction (software interrupt)
7787       will_dirty_i=0;
7788       wont_dirty_i=0;
7789     }
7790     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7791     {
7792       // ERET instruction (return from interrupt)
7793       will_dirty_i=0;
7794       wont_dirty_i=0;
7795     }
7796     will_dirty_next=will_dirty_i;
7797     wont_dirty_next=wont_dirty_i;
7798     for(r=0;r<HOST_REGS;r++) {
7799       if(r!=EXCLUDE_REG) {
7800         if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7801         if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7802         if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7803         if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7804         if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7805         if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7806         if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7807         if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7808         if(i>istart) {
7809           if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7810           {
7811             // Don't store a register immediately after writing it,
7812             // may prevent dual-issue.
7813             if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7814             if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7815           }
7816         }
7817       }
7818     }
7819     // Save it
7820     will_dirty[i]=will_dirty_i;
7821     wont_dirty[i]=wont_dirty_i;
7822     // Mark registers that won't be dirtied as not dirty
7823     if(wr) {
7824       /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7825       for(r=0;r<HOST_REGS;r++) {
7826         if((will_dirty_i>>r)&1) {
7827           printf(" r%d",r);
7828         }
7829       }
7830       printf("\n");*/
7831
7832       //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7833         regs[i].dirty|=will_dirty_i;
7834         #ifndef DESTRUCTIVE_WRITEBACK
7835         regs[i].dirty&=wont_dirty_i;
7836         if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7837         {
7838           if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7839             for(r=0;r<HOST_REGS;r++) {
7840               if(r!=EXCLUDE_REG) {
7841                 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7842                   regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7843                 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7844               }
7845             }
7846           }
7847         }
7848         else
7849         {
7850           if(i<iend) {
7851             for(r=0;r<HOST_REGS;r++) {
7852               if(r!=EXCLUDE_REG) {
7853                 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7854                   regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7855                 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7856               }
7857             }
7858           }
7859         }
7860         #endif
7861       //}
7862     }
7863     // Deal with changed mappings
7864     temp_will_dirty=will_dirty_i;
7865     temp_wont_dirty=wont_dirty_i;
7866     for(r=0;r<HOST_REGS;r++) {
7867       if(r!=EXCLUDE_REG) {
7868         int nr;
7869         if(regs[i].regmap[r]==regmap_pre[i][r]) {
7870           if(wr) {
7871             #ifndef DESTRUCTIVE_WRITEBACK
7872             regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7873             #endif
7874             regs[i].wasdirty|=will_dirty_i&(1<<r);
7875           }
7876         }
7877         else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7878           // Register moved to a different register
7879           will_dirty_i&=~(1<<r);
7880           wont_dirty_i&=~(1<<r);
7881           will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7882           wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7883           if(wr) {
7884             #ifndef DESTRUCTIVE_WRITEBACK
7885             regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7886             #endif
7887             regs[i].wasdirty|=will_dirty_i&(1<<r);
7888           }
7889         }
7890         else {
7891           will_dirty_i&=~(1<<r);
7892           wont_dirty_i&=~(1<<r);
7893           if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7894             will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7895             wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7896           } else {
7897             wont_dirty_i|=1<<r;
7898             /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7899           }
7900         }
7901       }
7902     }
7903   }
7904 }
7905
7906 #ifdef DISASM
7907   /* disassembly */
7908 void disassemble_inst(int i)
7909 {
7910     if (bt[i]) printf("*"); else printf(" ");
7911     switch(itype[i]) {
7912       case UJUMP:
7913         printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7914       case CJUMP:
7915         printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7916       case SJUMP:
7917         printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7918       case FJUMP:
7919         printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7920       case RJUMP:
7921         if (opcode[i]==0x9&&rt1[i]!=31)
7922           printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7923         else
7924           printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7925         break;
7926       case SPAN:
7927         printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7928       case IMM16:
7929         if(opcode[i]==0xf) //LUI
7930           printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7931         else
7932           printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7933         break;
7934       case LOAD:
7935       case LOADLR:
7936         printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7937         break;
7938       case STORE:
7939       case STORELR:
7940         printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7941         break;
7942       case ALU:
7943       case SHIFT:
7944         printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7945         break;
7946       case MULTDIV:
7947         printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7948         break;
7949       case SHIFTIMM:
7950         printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7951         break;
7952       case MOV:
7953         if((opcode2[i]&0x1d)==0x10)
7954           printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7955         else if((opcode2[i]&0x1d)==0x11)
7956           printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7957         else
7958           printf (" %x: %s\n",start+i*4,insn[i]);
7959         break;
7960       case COP0:
7961         if(opcode2[i]==0)
7962           printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7963         else if(opcode2[i]==4)
7964           printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7965         else printf (" %x: %s\n",start+i*4,insn[i]);
7966         break;
7967       case COP1:
7968         if(opcode2[i]<3)
7969           printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7970         else if(opcode2[i]>3)
7971           printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7972         else printf (" %x: %s\n",start+i*4,insn[i]);
7973         break;
7974       case COP2:
7975         if(opcode2[i]<3)
7976           printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7977         else if(opcode2[i]>3)
7978           printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7979         else printf (" %x: %s\n",start+i*4,insn[i]);
7980         break;
7981       case C1LS:
7982         printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7983         break;
7984       case C2LS:
7985         printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7986         break;
7987       case INTCALL:
7988         printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
7989         break;
7990       default:
7991         //printf (" %s %8x\n",insn[i],source[i]);
7992         printf (" %x: %s\n",start+i*4,insn[i]);
7993     }
7994 }
7995 #else
7996 static void disassemble_inst(int i) {}
7997 #endif // DISASM
7998
7999 // clear the state completely, instead of just marking
8000 // things invalid like invalidate_all_pages() does
8001 void new_dynarec_clear_full()
8002 {
8003   int n;
8004   out=(u_char *)BASE_ADDR;
8005   memset(invalid_code,1,sizeof(invalid_code));
8006   memset(hash_table,0xff,sizeof(hash_table));
8007   memset(mini_ht,-1,sizeof(mini_ht));
8008   memset(restore_candidate,0,sizeof(restore_candidate));
8009   memset(shadow,0,sizeof(shadow));
8010   copy=shadow;
8011   expirep=16384; // Expiry pointer, +2 blocks
8012   pending_exception=0;
8013   literalcount=0;
8014   stop_after_jal=0;
8015   inv_code_start=inv_code_end=~0;
8016   // TLB
8017 #ifndef DISABLE_TLB
8018   using_tlb=0;
8019   for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
8020     memory_map[n]=-1;
8021   for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
8022     memory_map[n]=((u_int)rdram-0x80000000)>>2;
8023   for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
8024     memory_map[n]=-1;
8025 #endif
8026   for(n=0;n<4096;n++) ll_clear(jump_in+n);
8027   for(n=0;n<4096;n++) ll_clear(jump_out+n);
8028   for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
8029 }
8030
8031 void new_dynarec_init()
8032 {
8033   printf("Init new dynarec\n");
8034   out=(u_char *)BASE_ADDR;
8035 #if BASE_ADDR_FIXED
8036   if (mmap (out, 1<<TARGET_SIZE_2,
8037             PROT_READ | PROT_WRITE | PROT_EXEC,
8038             MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
8039             -1, 0) <= 0) {printf("mmap() failed\n");}
8040 #else
8041   // not all systems allow execute in data segment by default
8042   if (mprotect(out, 1<<TARGET_SIZE_2, PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
8043     printf("mprotect() failed\n");
8044 #endif
8045 #ifdef MUPEN64
8046   rdword=&readmem_dword;
8047   fake_pc.f.r.rs=&readmem_dword;
8048   fake_pc.f.r.rt=&readmem_dword;
8049   fake_pc.f.r.rd=&readmem_dword;
8050 #endif
8051   int n;
8052   cycle_multiplier=200;
8053   new_dynarec_clear_full();
8054 #ifdef HOST_IMM8
8055   // Copy this into local area so we don't have to put it in every literal pool
8056   invc_ptr=invalid_code;
8057 #endif
8058 #ifdef MUPEN64
8059   for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
8060     writemem[n] = write_nomem_new;
8061     writememb[n] = write_nomemb_new;
8062     writememh[n] = write_nomemh_new;
8063 #ifndef FORCE32
8064     writememd[n] = write_nomemd_new;
8065 #endif
8066     readmem[n] = read_nomem_new;
8067     readmemb[n] = read_nomemb_new;
8068     readmemh[n] = read_nomemh_new;
8069 #ifndef FORCE32
8070     readmemd[n] = read_nomemd_new;
8071 #endif
8072   }
8073   for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
8074     writemem[n] = write_rdram_new;
8075     writememb[n] = write_rdramb_new;
8076     writememh[n] = write_rdramh_new;
8077 #ifndef FORCE32
8078     writememd[n] = write_rdramd_new;
8079 #endif
8080   }
8081   for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
8082     writemem[n] = write_nomem_new;
8083     writememb[n] = write_nomemb_new;
8084     writememh[n] = write_nomemh_new;
8085 #ifndef FORCE32
8086     writememd[n] = write_nomemd_new;
8087 #endif
8088     readmem[n] = read_nomem_new;
8089     readmemb[n] = read_nomemb_new;
8090     readmemh[n] = read_nomemh_new;
8091 #ifndef FORCE32
8092     readmemd[n] = read_nomemd_new;
8093 #endif
8094   }
8095 #endif
8096   tlb_hacks();
8097   arch_init();
8098 #ifndef RAM_FIXED
8099   ram_offset=(u_int)rdram-0x80000000;
8100 #endif
8101   if (ram_offset!=0)
8102     printf("warning: RAM is not directly mapped, performance will suffer\n");
8103 }
8104
8105 void new_dynarec_cleanup()
8106 {
8107   int n;
8108   #if BASE_ADDR_FIXED
8109   if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
8110   #endif
8111   for(n=0;n<4096;n++) ll_clear(jump_in+n);
8112   for(n=0;n<4096;n++) ll_clear(jump_out+n);
8113   for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
8114   #ifdef ROM_COPY
8115   if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
8116   #endif
8117 }
8118
8119 int new_recompile_block(int addr)
8120 {
8121 /*
8122   if(addr==0x800cd050) {
8123     int block;
8124     for(block=0x80000;block<0x80800;block++) invalidate_block(block);
8125     int n;
8126     for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
8127   }
8128 */
8129   //if(Count==365117028) tracedebug=1;
8130   assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
8131   //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
8132   //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
8133   //if(debug)
8134   //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
8135   //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
8136   /*if(Count>=312978186) {
8137     rlist();
8138   }*/
8139   //rlist();
8140   start = (u_int)addr&~3;
8141   //assert(((u_int)addr&1)==0);
8142   new_dynarec_did_compile=1;
8143 #ifdef PCSX
8144   if (Config.HLE && start == 0x80001000) // hlecall
8145   {
8146     // XXX: is this enough? Maybe check hleSoftCall?
8147     u_int beginning=(u_int)out;
8148     u_int page=get_page(start);
8149     invalid_code[start>>12]=0;
8150     emit_movimm(start,0);
8151     emit_writeword(0,(int)&pcaddr);
8152     emit_jmp((int)new_dyna_leave);
8153     literal_pool(0);
8154 #ifdef __arm__
8155     __clear_cache((void *)beginning,out);
8156 #endif
8157     ll_add(jump_in+page,start,(void *)beginning);
8158     return 0;
8159   }
8160   else if ((u_int)addr < 0x00200000 ||
8161     (0xa0000000 <= addr && addr < 0xa0200000)) {
8162     // used for BIOS calls mostly?
8163     source = (u_int *)((u_int)rdram+(start&0x1fffff));
8164     pagelimit = (addr&0xa0000000)|0x00200000;
8165   }
8166   else if (!Config.HLE && (
8167 /*    (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
8168     (0xbfc00000 <= addr && addr < 0xbfc80000))) {
8169     // BIOS
8170     source = (u_int *)((u_int)psxR+(start&0x7ffff));
8171     pagelimit = (addr&0xfff00000)|0x80000;
8172   }
8173   else
8174 #endif
8175 #ifdef MUPEN64
8176   if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
8177     source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
8178     pagelimit = 0xa4001000;
8179   }
8180   else
8181 #endif
8182   if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
8183     source = (u_int *)((u_int)rdram+start-0x80000000);
8184     pagelimit = 0x80000000+RAM_SIZE;
8185   }
8186 #ifndef DISABLE_TLB
8187   else if ((signed int)addr >= (signed int)0xC0000000) {
8188     //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
8189     //if(tlb_LUT_r[start>>12])
8190       //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
8191     if((signed int)memory_map[start>>12]>=0) {
8192       source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
8193       pagelimit=(start+4096)&0xFFFFF000;
8194       int map=memory_map[start>>12];
8195       int i;
8196       for(i=0;i<5;i++) {
8197         //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
8198         if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
8199       }
8200       assem_debug("pagelimit=%x\n",pagelimit);
8201       assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
8202     }
8203     else {
8204       assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
8205       //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
8206       return -1; // Caller will invoke exception handler
8207     }
8208     //printf("source= %x\n",(int)source);
8209   }
8210 #endif
8211   else {
8212     printf("Compile at bogus memory address: %x \n", (int)addr);
8213     exit(1);
8214   }
8215
8216   /* Pass 1: disassemble */
8217   /* Pass 2: register dependencies, branch targets */
8218   /* Pass 3: register allocation */
8219   /* Pass 4: branch dependencies */
8220   /* Pass 5: pre-alloc */
8221   /* Pass 6: optimize clean/dirty state */
8222   /* Pass 7: flag 32-bit registers */
8223   /* Pass 8: assembly */
8224   /* Pass 9: linker */
8225   /* Pass 10: garbage collection / free memory */
8226
8227   int i,j;
8228   int done=0;
8229   unsigned int type,op,op2;
8230
8231   //printf("addr = %x source = %x %x\n", addr,source,source[0]);
8232
8233   /* Pass 1 disassembly */
8234
8235   for(i=0;!done;i++) {
8236     bt[i]=0;likely[i]=0;ooo[i]=0;op2=0;
8237     minimum_free_regs[i]=0;
8238     opcode[i]=op=source[i]>>26;
8239     switch(op)
8240     {
8241       case 0x00: strcpy(insn[i],"special"); type=NI;
8242         op2=source[i]&0x3f;
8243         switch(op2)
8244         {
8245           case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
8246           case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
8247           case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
8248           case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
8249           case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
8250           case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
8251           case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
8252           case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
8253           case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
8254           case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
8255           case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
8256           case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
8257           case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
8258           case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
8259           case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
8260           case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
8261           case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
8262           case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
8263           case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
8264           case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
8265           case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
8266           case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
8267           case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
8268           case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
8269           case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
8270           case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
8271           case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
8272           case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
8273           case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
8274           case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
8275           case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
8276           case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
8277           case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
8278           case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
8279           case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
8280 #ifndef FORCE32
8281           case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
8282           case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
8283           case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
8284           case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
8285           case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
8286           case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
8287           case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
8288           case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
8289           case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
8290           case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
8291           case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
8292           case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
8293           case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
8294           case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
8295           case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
8296           case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
8297           case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
8298 #endif
8299         }
8300         break;
8301       case 0x01: strcpy(insn[i],"regimm"); type=NI;
8302         op2=(source[i]>>16)&0x1f;
8303         switch(op2)
8304         {
8305           case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
8306           case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
8307           case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
8308           case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
8309           case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
8310           case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
8311           case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
8312           case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
8313           case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
8314           case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
8315           case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
8316           case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
8317           case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
8318           case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
8319         }
8320         break;
8321       case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
8322       case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
8323       case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
8324       case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
8325       case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
8326       case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
8327       case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
8328       case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
8329       case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
8330       case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
8331       case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
8332       case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
8333       case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
8334       case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
8335       case 0x10: strcpy(insn[i],"cop0"); type=NI;
8336         op2=(source[i]>>21)&0x1f;
8337         switch(op2)
8338         {
8339           case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
8340           case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
8341           case 0x10: strcpy(insn[i],"tlb"); type=NI;
8342           switch(source[i]&0x3f)
8343           {
8344             case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
8345             case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
8346             case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
8347             case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
8348 #ifdef PCSX
8349             case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
8350 #else
8351             case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
8352 #endif
8353           }
8354         }
8355         break;
8356       case 0x11: strcpy(insn[i],"cop1"); type=NI;
8357         op2=(source[i]>>21)&0x1f;
8358         switch(op2)
8359         {
8360           case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
8361           case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
8362           case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
8363           case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
8364           case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
8365           case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
8366           case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
8367           switch((source[i]>>16)&0x3)
8368           {
8369             case 0x00: strcpy(insn[i],"BC1F"); break;
8370             case 0x01: strcpy(insn[i],"BC1T"); break;
8371             case 0x02: strcpy(insn[i],"BC1FL"); break;
8372             case 0x03: strcpy(insn[i],"BC1TL"); break;
8373           }
8374           break;
8375           case 0x10: strcpy(insn[i],"C1.S"); type=NI;
8376           switch(source[i]&0x3f)
8377           {
8378             case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
8379             case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
8380             case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
8381             case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
8382             case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
8383             case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
8384             case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
8385             case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
8386             case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
8387             case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
8388             case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
8389             case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
8390             case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
8391             case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
8392             case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
8393             case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
8394             case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
8395             case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
8396             case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
8397             case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
8398             case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
8399             case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
8400             case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
8401             case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
8402             case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
8403             case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
8404             case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
8405             case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
8406             case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
8407             case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
8408             case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
8409             case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
8410             case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
8411             case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
8412             case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
8413           }
8414           break;
8415           case 0x11: strcpy(insn[i],"C1.D"); type=NI;
8416           switch(source[i]&0x3f)
8417           {
8418             case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
8419             case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
8420             case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
8421             case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
8422             case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
8423             case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
8424             case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
8425             case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
8426             case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
8427             case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
8428             case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
8429             case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
8430             case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
8431             case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
8432             case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
8433             case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
8434             case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
8435             case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
8436             case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
8437             case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
8438             case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
8439             case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
8440             case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
8441             case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
8442             case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
8443             case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
8444             case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
8445             case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
8446             case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
8447             case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
8448             case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8449             case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8450             case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8451             case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8452             case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8453           }
8454           break;
8455           case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8456           switch(source[i]&0x3f)
8457           {
8458             case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8459             case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8460           }
8461           break;
8462           case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8463           switch(source[i]&0x3f)
8464           {
8465             case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8466             case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8467           }
8468           break;
8469         }
8470         break;
8471 #ifndef FORCE32
8472       case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8473       case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8474       case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8475       case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8476       case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8477       case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8478       case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8479       case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
8480 #endif
8481       case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8482       case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8483       case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8484       case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8485       case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8486       case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8487       case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
8488 #ifndef FORCE32
8489       case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
8490 #endif
8491       case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8492       case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8493       case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8494       case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
8495 #ifndef FORCE32
8496       case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8497       case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
8498 #endif
8499       case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8500       case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8501       case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8502       case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
8503 #ifndef FORCE32
8504       case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8505       case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8506       case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
8507 #endif
8508       case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8509       case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
8510 #ifndef FORCE32
8511       case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8512       case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8513       case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
8514 #endif
8515 #ifdef PCSX
8516       case 0x12: strcpy(insn[i],"COP2"); type=NI;
8517         op2=(source[i]>>21)&0x1f;
8518         //if (op2 & 0x10) {
8519         if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
8520           if (gte_handlers[source[i]&0x3f]!=NULL) {
8521             if (gte_regnames[source[i]&0x3f]!=NULL)
8522               strcpy(insn[i],gte_regnames[source[i]&0x3f]);
8523             else
8524               snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8525             type=C2OP;
8526           }
8527         }
8528         else switch(op2)
8529         {
8530           case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8531           case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8532           case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8533           case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
8534         }
8535         break;
8536       case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8537       case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8538       case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8539 #endif
8540       default: strcpy(insn[i],"???"); type=NI;
8541         printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
8542         break;
8543     }
8544     itype[i]=type;
8545     opcode2[i]=op2;
8546     /* Get registers/immediates */
8547     lt1[i]=0;
8548     us1[i]=0;
8549     us2[i]=0;
8550     dep1[i]=0;
8551     dep2[i]=0;
8552     gte_rs[i]=gte_rt[i]=0;
8553     switch(type) {
8554       case LOAD:
8555         rs1[i]=(source[i]>>21)&0x1f;
8556         rs2[i]=0;
8557         rt1[i]=(source[i]>>16)&0x1f;
8558         rt2[i]=0;
8559         imm[i]=(short)source[i];
8560         break;
8561       case STORE:
8562       case STORELR:
8563         rs1[i]=(source[i]>>21)&0x1f;
8564         rs2[i]=(source[i]>>16)&0x1f;
8565         rt1[i]=0;
8566         rt2[i]=0;
8567         imm[i]=(short)source[i];
8568         if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8569         break;
8570       case LOADLR:
8571         // LWL/LWR only load part of the register,
8572         // therefore the target register must be treated as a source too
8573         rs1[i]=(source[i]>>21)&0x1f;
8574         rs2[i]=(source[i]>>16)&0x1f;
8575         rt1[i]=(source[i]>>16)&0x1f;
8576         rt2[i]=0;
8577         imm[i]=(short)source[i];
8578         if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8579         if(op==0x26) dep1[i]=rt1[i]; // LWR
8580         break;
8581       case IMM16:
8582         if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8583         else rs1[i]=(source[i]>>21)&0x1f;
8584         rs2[i]=0;
8585         rt1[i]=(source[i]>>16)&0x1f;
8586         rt2[i]=0;
8587         if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8588           imm[i]=(unsigned short)source[i];
8589         }else{
8590           imm[i]=(short)source[i];
8591         }
8592         if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8593         if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8594         if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8595         break;
8596       case UJUMP:
8597         rs1[i]=0;
8598         rs2[i]=0;
8599         rt1[i]=0;
8600         rt2[i]=0;
8601         // The JAL instruction writes to r31.
8602         if (op&1) {
8603           rt1[i]=31;
8604         }
8605         rs2[i]=CCREG;
8606         break;
8607       case RJUMP:
8608         rs1[i]=(source[i]>>21)&0x1f;
8609         rs2[i]=0;
8610         rt1[i]=0;
8611         rt2[i]=0;
8612         // The JALR instruction writes to rd.
8613         if (op2&1) {
8614           rt1[i]=(source[i]>>11)&0x1f;
8615         }
8616         rs2[i]=CCREG;
8617         break;
8618       case CJUMP:
8619         rs1[i]=(source[i]>>21)&0x1f;
8620         rs2[i]=(source[i]>>16)&0x1f;
8621         rt1[i]=0;
8622         rt2[i]=0;
8623         if(op&2) { // BGTZ/BLEZ
8624           rs2[i]=0;
8625         }
8626         us1[i]=rs1[i];
8627         us2[i]=rs2[i];
8628         likely[i]=op>>4;
8629         break;
8630       case SJUMP:
8631         rs1[i]=(source[i]>>21)&0x1f;
8632         rs2[i]=CCREG;
8633         rt1[i]=0;
8634         rt2[i]=0;
8635         us1[i]=rs1[i];
8636         if(op2&0x10) { // BxxAL
8637           rt1[i]=31;
8638           // NOTE: If the branch is not taken, r31 is still overwritten
8639         }
8640         likely[i]=(op2&2)>>1;
8641         break;
8642       case FJUMP:
8643         rs1[i]=FSREG;
8644         rs2[i]=CSREG;
8645         rt1[i]=0;
8646         rt2[i]=0;
8647         likely[i]=((source[i])>>17)&1;
8648         break;
8649       case ALU:
8650         rs1[i]=(source[i]>>21)&0x1f; // source
8651         rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8652         rt1[i]=(source[i]>>11)&0x1f; // destination
8653         rt2[i]=0;
8654         if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8655           us1[i]=rs1[i];us2[i]=rs2[i];
8656         }
8657         else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8658           dep1[i]=rs1[i];dep2[i]=rs2[i];
8659         }
8660         else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8661           dep1[i]=rs1[i];dep2[i]=rs2[i];
8662         }
8663         break;
8664       case MULTDIV:
8665         rs1[i]=(source[i]>>21)&0x1f; // source
8666         rs2[i]=(source[i]>>16)&0x1f; // divisor
8667         rt1[i]=HIREG;
8668         rt2[i]=LOREG;
8669         if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8670           us1[i]=rs1[i];us2[i]=rs2[i];
8671         }
8672         break;
8673       case MOV:
8674         rs1[i]=0;
8675         rs2[i]=0;
8676         rt1[i]=0;
8677         rt2[i]=0;
8678         if(op2==0x10) rs1[i]=HIREG; // MFHI
8679         if(op2==0x11) rt1[i]=HIREG; // MTHI
8680         if(op2==0x12) rs1[i]=LOREG; // MFLO
8681         if(op2==0x13) rt1[i]=LOREG; // MTLO
8682         if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8683         if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8684         dep1[i]=rs1[i];
8685         break;
8686       case SHIFT:
8687         rs1[i]=(source[i]>>16)&0x1f; // target of shift
8688         rs2[i]=(source[i]>>21)&0x1f; // shift amount
8689         rt1[i]=(source[i]>>11)&0x1f; // destination
8690         rt2[i]=0;
8691         // DSLLV/DSRLV/DSRAV are 64-bit
8692         if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8693         break;
8694       case SHIFTIMM:
8695         rs1[i]=(source[i]>>16)&0x1f;
8696         rs2[i]=0;
8697         rt1[i]=(source[i]>>11)&0x1f;
8698         rt2[i]=0;
8699         imm[i]=(source[i]>>6)&0x1f;
8700         // DSxx32 instructions
8701         if(op2>=0x3c) imm[i]|=0x20;
8702         // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8703         if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8704         break;
8705       case COP0:
8706         rs1[i]=0;
8707         rs2[i]=0;
8708         rt1[i]=0;
8709         rt2[i]=0;
8710         if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8711         if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8712         if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8713         if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8714         break;
8715       case COP1:
8716         rs1[i]=0;
8717         rs2[i]=0;
8718         rt1[i]=0;
8719         rt2[i]=0;
8720         if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8721         if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8722         if(op2==5) us1[i]=rs1[i]; // DMTC1
8723         rs2[i]=CSREG;
8724         break;
8725       case COP2:
8726         rs1[i]=0;
8727         rs2[i]=0;
8728         rt1[i]=0;
8729         rt2[i]=0;
8730         if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC2/CFC2
8731         if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC2/CTC2
8732         rs2[i]=CSREG;
8733         int gr=(source[i]>>11)&0x1F;
8734         switch(op2)
8735         {
8736           case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
8737           case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
8738           case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2
8739           case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
8740         }
8741         break;
8742       case C1LS:
8743         rs1[i]=(source[i]>>21)&0x1F;
8744         rs2[i]=CSREG;
8745         rt1[i]=0;
8746         rt2[i]=0;
8747         imm[i]=(short)source[i];
8748         break;
8749       case C2LS:
8750         rs1[i]=(source[i]>>21)&0x1F;
8751         rs2[i]=0;
8752         rt1[i]=0;
8753         rt2[i]=0;
8754         imm[i]=(short)source[i];
8755         if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
8756         else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
8757         break;
8758       case C2OP:
8759         rs1[i]=0;
8760         rs2[i]=0;
8761         rt1[i]=0;
8762         rt2[i]=0;
8763         gte_rs[i]=gte_reg_reads[source[i]&0x3f];
8764         gte_rt[i]=gte_reg_writes[source[i]&0x3f];
8765         gte_rt[i]|=1ll<<63; // every op changes flags
8766         if((source[i]&0x3f)==GTE_MVMVA) {
8767           int v = (source[i] >> 15) & 3;
8768           gte_rs[i]&=~0xe3fll;
8769           if(v==3) gte_rs[i]|=0xe00ll;
8770           else gte_rs[i]|=3ll<<(v*2);
8771         }
8772         break;
8773       case FLOAT:
8774       case FCONV:
8775         rs1[i]=0;
8776         rs2[i]=CSREG;
8777         rt1[i]=0;
8778         rt2[i]=0;
8779         break;
8780       case FCOMP:
8781         rs1[i]=FSREG;
8782         rs2[i]=CSREG;
8783         rt1[i]=FSREG;
8784         rt2[i]=0;
8785         break;
8786       case SYSCALL:
8787       case HLECALL:
8788       case INTCALL:
8789         rs1[i]=CCREG;
8790         rs2[i]=0;
8791         rt1[i]=0;
8792         rt2[i]=0;
8793         break;
8794       default:
8795         rs1[i]=0;
8796         rs2[i]=0;
8797         rt1[i]=0;
8798         rt2[i]=0;
8799     }
8800     /* Calculate branch target addresses */
8801     if(type==UJUMP)
8802       ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8803     else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8804       ba[i]=start+i*4+8; // Ignore never taken branch
8805     else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8806       ba[i]=start+i*4+8; // Ignore never taken branch
8807     else if(type==CJUMP||type==SJUMP||type==FJUMP)
8808       ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8809     else ba[i]=-1;
8810 #ifdef PCSX
8811     if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
8812       int do_in_intrp=0;
8813       // branch in delay slot?
8814       if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
8815         // don't handle first branch and call interpreter if it's hit
8816         printf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
8817         do_in_intrp=1;
8818       }
8819       // basic load delay detection
8820       else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&rt1[i]!=0) {
8821         int t=(ba[i-1]-start)/4;
8822         if(0 <= t && t < i &&(rt1[i]==rs1[t]||rt1[i]==rs2[t])&&itype[t]!=CJUMP&&itype[t]!=SJUMP) {
8823           // jump target wants DS result - potential load delay effect
8824           printf("load delay @%08x (%08x)\n", addr + i*4, addr);
8825           do_in_intrp=1;
8826           bt[t+1]=1; // expected return from interpreter
8827         }
8828         else if(i>=2&&rt1[i-2]==2&&rt1[i]==2&&rs1[i]!=2&&rs2[i]!=2&&rs1[i-1]!=2&&rs2[i-1]!=2&&
8829               !(i>=3&&(itype[i-3]==RJUMP||itype[i-3]==UJUMP||itype[i-3]==CJUMP||itype[i-3]==SJUMP))) {
8830           // v0 overwrite like this is a sign of trouble, bail out
8831           printf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
8832           do_in_intrp=1;
8833         }
8834       }
8835       if(do_in_intrp) {
8836         rs1[i-1]=CCREG;
8837         rs2[i-1]=rt1[i-1]=rt2[i-1]=0;
8838         ba[i-1]=-1;
8839         itype[i-1]=INTCALL;
8840         done=2;
8841         i--; // don't compile the DS
8842       }
8843     }
8844 #endif
8845     /* Is this the end of the block? */
8846     if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
8847       if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
8848         done=2;
8849       }
8850       else {
8851         if(stop_after_jal) done=1;
8852         // Stop on BREAK
8853         if((source[i+1]&0xfc00003f)==0x0d) done=1;
8854       }
8855       // Don't recompile stuff that's already compiled
8856       if(check_addr(start+i*4+4)) done=1;
8857       // Don't get too close to the limit
8858       if(i>MAXBLOCK/2) done=1;
8859     }
8860     if(itype[i]==SYSCALL&&stop_after_jal) done=1;
8861     if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
8862     if(done==2) {
8863       // Does the block continue due to a branch?
8864       for(j=i-1;j>=0;j--)
8865       {
8866         if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
8867         if(ba[j]==start+i*4+4) done=j=0;
8868         if(ba[j]==start+i*4+8) done=j=0;
8869       }
8870     }
8871     //assert(i<MAXBLOCK-1);
8872     if(start+i*4==pagelimit-4) done=1;
8873     assert(start+i*4<pagelimit);
8874     if (i==MAXBLOCK-1) done=1;
8875     // Stop if we're compiling junk
8876     if(itype[i]==NI&&opcode[i]==0x11) {
8877       done=stop_after_jal=1;
8878       printf("Disabled speculative precompilation\n");
8879     }
8880   }
8881   slen=i;
8882   if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8883     if(start+i*4==pagelimit) {
8884       itype[i-1]=SPAN;
8885     }
8886   }
8887   assert(slen>0);
8888
8889   /* Pass 2 - Register dependencies and branch targets */
8890
8891   unneeded_registers(0,slen-1,0);
8892
8893   /* Pass 3 - Register allocation */
8894
8895   struct regstat current; // Current register allocations/status
8896   current.is32=1;
8897   current.dirty=0;
8898   current.u=unneeded_reg[0];
8899   current.uu=unneeded_reg_upper[0];
8900   clear_all_regs(current.regmap);
8901   alloc_reg(&current,0,CCREG);
8902   dirty_reg(&current,CCREG);
8903   current.isconst=0;
8904   current.wasconst=0;
8905   current.waswritten=0;
8906   int ds=0;
8907   int cc=0;
8908   int hr=-1;
8909
8910 #ifndef FORCE32
8911   provisional_32bit();
8912 #endif
8913   if((u_int)addr&1) {
8914     // First instruction is delay slot
8915     cc=-1;
8916     bt[1]=1;
8917     ds=1;
8918     unneeded_reg[0]=1;
8919     unneeded_reg_upper[0]=1;
8920     current.regmap[HOST_BTREG]=BTREG;
8921   }
8922
8923   for(i=0;i<slen;i++)
8924   {
8925     if(bt[i])
8926     {
8927       int hr;
8928       for(hr=0;hr<HOST_REGS;hr++)
8929       {
8930         // Is this really necessary?
8931         if(current.regmap[hr]==0) current.regmap[hr]=-1;
8932       }
8933       current.isconst=0;
8934       current.waswritten=0;
8935     }
8936     if(i>1)
8937     {
8938       if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8939       {
8940         if(rs1[i-2]==0||rs2[i-2]==0)
8941         {
8942           if(rs1[i-2]) {
8943             current.is32|=1LL<<rs1[i-2];
8944             int hr=get_reg(current.regmap,rs1[i-2]|64);
8945             if(hr>=0) current.regmap[hr]=-1;
8946           }
8947           if(rs2[i-2]) {
8948             current.is32|=1LL<<rs2[i-2];
8949             int hr=get_reg(current.regmap,rs2[i-2]|64);
8950             if(hr>=0) current.regmap[hr]=-1;
8951           }
8952         }
8953       }
8954     }
8955 #ifndef FORCE32
8956     // If something jumps here with 64-bit values
8957     // then promote those registers to 64 bits
8958     if(bt[i])
8959     {
8960       uint64_t temp_is32=current.is32;
8961       for(j=i-1;j>=0;j--)
8962       {
8963         if(ba[j]==start+i*4)
8964           temp_is32&=branch_regs[j].is32;
8965       }
8966       for(j=i;j<slen;j++)
8967       {
8968         if(ba[j]==start+i*4)
8969           //temp_is32=1;
8970           temp_is32&=p32[j];
8971       }
8972       if(temp_is32!=current.is32) {
8973         //printf("dumping 32-bit regs (%x)\n",start+i*4);
8974         #ifndef DESTRUCTIVE_WRITEBACK
8975         if(ds)
8976         #endif
8977         for(hr=0;hr<HOST_REGS;hr++)
8978         {
8979           int r=current.regmap[hr];
8980           if(r>0&&r<64)
8981           {
8982             if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8983               temp_is32|=1LL<<r;
8984               //printf("restore %d\n",r);
8985             }
8986           }
8987         }
8988         current.is32=temp_is32;
8989       }
8990     }
8991 #else
8992     current.is32=-1LL;
8993 #endif
8994
8995     memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8996     regs[i].wasconst=current.isconst;
8997     regs[i].was32=current.is32;
8998     regs[i].wasdirty=current.dirty;
8999     regs[i].loadedconst=0;
9000     #if defined(DESTRUCTIVE_WRITEBACK) && !defined(FORCE32)
9001     // To change a dirty register from 32 to 64 bits, we must write
9002     // it out during the previous cycle (for branches, 2 cycles)
9003     if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
9004     {
9005       uint64_t temp_is32=current.is32;
9006       for(j=i-1;j>=0;j--)
9007       {
9008         if(ba[j]==start+i*4+4)
9009           temp_is32&=branch_regs[j].is32;
9010       }
9011       for(j=i;j<slen;j++)
9012       {
9013         if(ba[j]==start+i*4+4)
9014           //temp_is32=1;
9015           temp_is32&=p32[j];
9016       }
9017       if(temp_is32!=current.is32) {
9018         //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
9019         for(hr=0;hr<HOST_REGS;hr++)
9020         {
9021           int r=current.regmap[hr];
9022           if(r>0)
9023           {
9024             if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
9025               if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
9026               {
9027                 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
9028                 {
9029                   //printf("dump %d/r%d\n",hr,r);
9030                   current.regmap[hr]=-1;
9031                   if(get_reg(current.regmap,r|64)>=0)
9032                     current.regmap[get_reg(current.regmap,r|64)]=-1;
9033                 }
9034               }
9035             }
9036           }
9037         }
9038       }
9039     }
9040     else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
9041     {
9042       uint64_t temp_is32=current.is32;
9043       for(j=i-1;j>=0;j--)
9044       {
9045         if(ba[j]==start+i*4+8)
9046           temp_is32&=branch_regs[j].is32;
9047       }
9048       for(j=i;j<slen;j++)
9049       {
9050         if(ba[j]==start+i*4+8)
9051           //temp_is32=1;
9052           temp_is32&=p32[j];
9053       }
9054       if(temp_is32!=current.is32) {
9055         //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
9056         for(hr=0;hr<HOST_REGS;hr++)
9057         {
9058           int r=current.regmap[hr];
9059           if(r>0)
9060           {
9061             if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
9062               if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
9063               {
9064                 //printf("dump %d/r%d\n",hr,r);
9065                 current.regmap[hr]=-1;
9066                 if(get_reg(current.regmap,r|64)>=0)
9067                   current.regmap[get_reg(current.regmap,r|64)]=-1;
9068               }
9069             }
9070           }
9071         }
9072       }
9073     }
9074     #endif
9075     if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9076       if(i+1<slen) {
9077         current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9078         current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9079         if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9080         current.u|=1;
9081         current.uu|=1;
9082       } else {
9083         current.u=1;
9084         current.uu=1;
9085       }
9086     } else {
9087       if(i+1<slen) {
9088         current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
9089         current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9090         if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9091         current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
9092         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9093         current.u|=1;
9094         current.uu|=1;
9095       } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
9096     }
9097     is_ds[i]=ds;
9098     if(ds) {
9099       ds=0; // Skip delay slot, already allocated as part of branch
9100       // ...but we need to alloc it in case something jumps here
9101       if(i+1<slen) {
9102         current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
9103         current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
9104       }else{
9105         current.u=branch_unneeded_reg[i-1];
9106         current.uu=branch_unneeded_reg_upper[i-1];
9107       }
9108       current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
9109       current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9110       if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9111       current.u|=1;
9112       current.uu|=1;
9113       struct regstat temp;
9114       memcpy(&temp,&current,sizeof(current));
9115       temp.wasdirty=temp.dirty;
9116       temp.was32=temp.is32;
9117       // TODO: Take into account unconditional branches, as below
9118       delayslot_alloc(&temp,i);
9119       memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
9120       regs[i].wasdirty=temp.wasdirty;
9121       regs[i].was32=temp.was32;
9122       regs[i].dirty=temp.dirty;
9123       regs[i].is32=temp.is32;
9124       regs[i].isconst=0;
9125       regs[i].wasconst=0;
9126       current.isconst=0;
9127       // Create entry (branch target) regmap
9128       for(hr=0;hr<HOST_REGS;hr++)
9129       {
9130         int r=temp.regmap[hr];
9131         if(r>=0) {
9132           if(r!=regmap_pre[i][hr]) {
9133             regs[i].regmap_entry[hr]=-1;
9134           }
9135           else
9136           {
9137             if(r<64){
9138               if((current.u>>r)&1) {
9139                 regs[i].regmap_entry[hr]=-1;
9140                 regs[i].regmap[hr]=-1;
9141                 //Don't clear regs in the delay slot as the branch might need them
9142                 //current.regmap[hr]=-1;
9143               }else
9144                 regs[i].regmap_entry[hr]=r;
9145             }
9146             else {
9147               if((current.uu>>(r&63))&1) {
9148                 regs[i].regmap_entry[hr]=-1;
9149                 regs[i].regmap[hr]=-1;
9150                 //Don't clear regs in the delay slot as the branch might need them
9151                 //current.regmap[hr]=-1;
9152               }else
9153                 regs[i].regmap_entry[hr]=r;
9154             }
9155           }
9156         } else {
9157           // First instruction expects CCREG to be allocated
9158           if(i==0&&hr==HOST_CCREG)
9159             regs[i].regmap_entry[hr]=CCREG;
9160           else
9161             regs[i].regmap_entry[hr]=-1;
9162         }
9163       }
9164     }
9165     else { // Not delay slot
9166       switch(itype[i]) {
9167         case UJUMP:
9168           //current.isconst=0; // DEBUG
9169           //current.wasconst=0; // DEBUG
9170           //regs[i].wasconst=0; // DEBUG
9171           clear_const(&current,rt1[i]);
9172           alloc_cc(&current,i);
9173           dirty_reg(&current,CCREG);
9174           if (rt1[i]==31) {
9175             alloc_reg(&current,i,31);
9176             dirty_reg(&current,31);
9177             //assert(rs1[i+1]!=31&&rs2[i+1]!=31);
9178             //assert(rt1[i+1]!=rt1[i]);
9179             #ifdef REG_PREFETCH
9180             alloc_reg(&current,i,PTEMP);
9181             #endif
9182             //current.is32|=1LL<<rt1[i];
9183           }
9184           ooo[i]=1;
9185           delayslot_alloc(&current,i+1);
9186           //current.isconst=0; // DEBUG
9187           ds=1;
9188           //printf("i=%d, isconst=%x\n",i,current.isconst);
9189           break;
9190         case RJUMP:
9191           //current.isconst=0;
9192           //current.wasconst=0;
9193           //regs[i].wasconst=0;
9194           clear_const(&current,rs1[i]);
9195           clear_const(&current,rt1[i]);
9196           alloc_cc(&current,i);
9197           dirty_reg(&current,CCREG);
9198           if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
9199             alloc_reg(&current,i,rs1[i]);
9200             if (rt1[i]!=0) {
9201               alloc_reg(&current,i,rt1[i]);
9202               dirty_reg(&current,rt1[i]);
9203               assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
9204               assert(rt1[i+1]!=rt1[i]);
9205               #ifdef REG_PREFETCH
9206               alloc_reg(&current,i,PTEMP);
9207               #endif
9208             }
9209             #ifdef USE_MINI_HT
9210             if(rs1[i]==31) { // JALR
9211               alloc_reg(&current,i,RHASH);
9212               #ifndef HOST_IMM_ADDR32
9213               alloc_reg(&current,i,RHTBL);
9214               #endif
9215             }
9216             #endif
9217             delayslot_alloc(&current,i+1);
9218           } else {
9219             // The delay slot overwrites our source register,
9220             // allocate a temporary register to hold the old value.
9221             current.isconst=0;
9222             current.wasconst=0;
9223             regs[i].wasconst=0;
9224             delayslot_alloc(&current,i+1);
9225             current.isconst=0;
9226             alloc_reg(&current,i,RTEMP);
9227           }
9228           //current.isconst=0; // DEBUG
9229           ooo[i]=1;
9230           ds=1;
9231           break;
9232         case CJUMP:
9233           //current.isconst=0;
9234           //current.wasconst=0;
9235           //regs[i].wasconst=0;
9236           clear_const(&current,rs1[i]);
9237           clear_const(&current,rs2[i]);
9238           if((opcode[i]&0x3E)==4) // BEQ/BNE
9239           {
9240             alloc_cc(&current,i);
9241             dirty_reg(&current,CCREG);
9242             if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9243             if(rs2[i]) alloc_reg(&current,i,rs2[i]);
9244             if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9245             {
9246               if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9247               if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
9248             }
9249             if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
9250                (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
9251               // The delay slot overwrites one of our conditions.
9252               // Allocate the branch condition registers instead.
9253               current.isconst=0;
9254               current.wasconst=0;
9255               regs[i].wasconst=0;
9256               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9257               if(rs2[i]) alloc_reg(&current,i,rs2[i]);
9258               if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9259               {
9260                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9261                 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
9262               }
9263             }
9264             else
9265             {
9266               ooo[i]=1;
9267               delayslot_alloc(&current,i+1);
9268             }
9269           }
9270           else
9271           if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
9272           {
9273             alloc_cc(&current,i);
9274             dirty_reg(&current,CCREG);
9275             alloc_reg(&current,i,rs1[i]);
9276             if(!(current.is32>>rs1[i]&1))
9277             {
9278               alloc_reg64(&current,i,rs1[i]);
9279             }
9280             if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
9281               // The delay slot overwrites one of our conditions.
9282               // Allocate the branch condition registers instead.
9283               current.isconst=0;
9284               current.wasconst=0;
9285               regs[i].wasconst=0;
9286               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9287               if(!((current.is32>>rs1[i])&1))
9288               {
9289                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9290               }
9291             }
9292             else
9293             {
9294               ooo[i]=1;
9295               delayslot_alloc(&current,i+1);
9296             }
9297           }
9298           else
9299           // Don't alloc the delay slot yet because we might not execute it
9300           if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
9301           {
9302             current.isconst=0;
9303             current.wasconst=0;
9304             regs[i].wasconst=0;
9305             alloc_cc(&current,i);
9306             dirty_reg(&current,CCREG);
9307             alloc_reg(&current,i,rs1[i]);
9308             alloc_reg(&current,i,rs2[i]);
9309             if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9310             {
9311               alloc_reg64(&current,i,rs1[i]);
9312               alloc_reg64(&current,i,rs2[i]);
9313             }
9314           }
9315           else
9316           if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
9317           {
9318             current.isconst=0;
9319             current.wasconst=0;
9320             regs[i].wasconst=0;
9321             alloc_cc(&current,i);
9322             dirty_reg(&current,CCREG);
9323             alloc_reg(&current,i,rs1[i]);
9324             if(!(current.is32>>rs1[i]&1))
9325             {
9326               alloc_reg64(&current,i,rs1[i]);
9327             }
9328           }
9329           ds=1;
9330           //current.isconst=0;
9331           break;
9332         case SJUMP:
9333           //current.isconst=0;
9334           //current.wasconst=0;
9335           //regs[i].wasconst=0;
9336           clear_const(&current,rs1[i]);
9337           clear_const(&current,rt1[i]);
9338           //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
9339           if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
9340           {
9341             alloc_cc(&current,i);
9342             dirty_reg(&current,CCREG);
9343             alloc_reg(&current,i,rs1[i]);
9344             if(!(current.is32>>rs1[i]&1))
9345             {
9346               alloc_reg64(&current,i,rs1[i]);
9347             }
9348             if (rt1[i]==31) { // BLTZAL/BGEZAL
9349               alloc_reg(&current,i,31);
9350               dirty_reg(&current,31);
9351               //#ifdef REG_PREFETCH
9352               //alloc_reg(&current,i,PTEMP);
9353               //#endif
9354               //current.is32|=1LL<<rt1[i];
9355             }
9356             if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) // The delay slot overwrites the branch condition.
9357                ||(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))) { // DS touches $ra
9358               // Allocate the branch condition registers instead.
9359               current.isconst=0;
9360               current.wasconst=0;
9361               regs[i].wasconst=0;
9362               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9363               if(!((current.is32>>rs1[i])&1))
9364               {
9365                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9366               }
9367             }
9368             else
9369             {
9370               ooo[i]=1;
9371               delayslot_alloc(&current,i+1);
9372             }
9373           }
9374           else
9375           // Don't alloc the delay slot yet because we might not execute it
9376           if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
9377           {
9378             current.isconst=0;
9379             current.wasconst=0;
9380             regs[i].wasconst=0;
9381             alloc_cc(&current,i);
9382             dirty_reg(&current,CCREG);
9383             alloc_reg(&current,i,rs1[i]);
9384             if(!(current.is32>>rs1[i]&1))
9385             {
9386               alloc_reg64(&current,i,rs1[i]);
9387             }
9388           }
9389           ds=1;
9390           //current.isconst=0;
9391           break;
9392         case FJUMP:
9393           current.isconst=0;
9394           current.wasconst=0;
9395           regs[i].wasconst=0;
9396           if(likely[i]==0) // BC1F/BC1T
9397           {
9398             // TODO: Theoretically we can run out of registers here on x86.
9399             // The delay slot can allocate up to six, and we need to check
9400             // CSREG before executing the delay slot.  Possibly we can drop
9401             // the cycle count and then reload it after checking that the
9402             // FPU is in a usable state, or don't do out-of-order execution.
9403             alloc_cc(&current,i);
9404             dirty_reg(&current,CCREG);
9405             alloc_reg(&current,i,FSREG);
9406             alloc_reg(&current,i,CSREG);
9407             if(itype[i+1]==FCOMP) {
9408               // The delay slot overwrites the branch condition.
9409               // Allocate the branch condition registers instead.
9410               alloc_cc(&current,i);
9411               dirty_reg(&current,CCREG);
9412               alloc_reg(&current,i,CSREG);
9413               alloc_reg(&current,i,FSREG);
9414             }
9415             else {
9416               ooo[i]=1;
9417               delayslot_alloc(&current,i+1);
9418               alloc_reg(&current,i+1,CSREG);
9419             }
9420           }
9421           else
9422           // Don't alloc the delay slot yet because we might not execute it
9423           if(likely[i]) // BC1FL/BC1TL
9424           {
9425             alloc_cc(&current,i);
9426             dirty_reg(&current,CCREG);
9427             alloc_reg(&current,i,CSREG);
9428             alloc_reg(&current,i,FSREG);
9429           }
9430           ds=1;
9431           current.isconst=0;
9432           break;
9433         case IMM16:
9434           imm16_alloc(&current,i);
9435           break;
9436         case LOAD:
9437         case LOADLR:
9438           load_alloc(&current,i);
9439           break;
9440         case STORE:
9441         case STORELR:
9442           store_alloc(&current,i);
9443           break;
9444         case ALU:
9445           alu_alloc(&current,i);
9446           break;
9447         case SHIFT:
9448           shift_alloc(&current,i);
9449           break;
9450         case MULTDIV:
9451           multdiv_alloc(&current,i);
9452           break;
9453         case SHIFTIMM:
9454           shiftimm_alloc(&current,i);
9455           break;
9456         case MOV:
9457           mov_alloc(&current,i);
9458           break;
9459         case COP0:
9460           cop0_alloc(&current,i);
9461           break;
9462         case COP1:
9463         case COP2:
9464           cop1_alloc(&current,i);
9465           break;
9466         case C1LS:
9467           c1ls_alloc(&current,i);
9468           break;
9469         case C2LS:
9470           c2ls_alloc(&current,i);
9471           break;
9472         case C2OP:
9473           c2op_alloc(&current,i);
9474           break;
9475         case FCONV:
9476           fconv_alloc(&current,i);
9477           break;
9478         case FLOAT:
9479           float_alloc(&current,i);
9480           break;
9481         case FCOMP:
9482           fcomp_alloc(&current,i);
9483           break;
9484         case SYSCALL:
9485         case HLECALL:
9486         case INTCALL:
9487           syscall_alloc(&current,i);
9488           break;
9489         case SPAN:
9490           pagespan_alloc(&current,i);
9491           break;
9492       }
9493
9494       // Drop the upper half of registers that have become 32-bit
9495       current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
9496       if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9497         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9498         if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9499         current.uu|=1;
9500       } else {
9501         current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
9502         current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9503         if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9504         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9505         current.uu|=1;
9506       }
9507
9508       // Create entry (branch target) regmap
9509       for(hr=0;hr<HOST_REGS;hr++)
9510       {
9511         int r,or,er;
9512         r=current.regmap[hr];
9513         if(r>=0) {
9514           if(r!=regmap_pre[i][hr]) {
9515             // TODO: delay slot (?)
9516             or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9517             if(or<0||(r&63)>=TEMPREG){
9518               regs[i].regmap_entry[hr]=-1;
9519             }
9520             else
9521             {
9522               // Just move it to a different register
9523               regs[i].regmap_entry[hr]=r;
9524               // If it was dirty before, it's still dirty
9525               if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r&63);
9526             }
9527           }
9528           else
9529           {
9530             // Unneeded
9531             if(r==0){
9532               regs[i].regmap_entry[hr]=0;
9533             }
9534             else
9535             if(r<64){
9536               if((current.u>>r)&1) {
9537                 regs[i].regmap_entry[hr]=-1;
9538                 //regs[i].regmap[hr]=-1;
9539                 current.regmap[hr]=-1;
9540               }else
9541                 regs[i].regmap_entry[hr]=r;
9542             }
9543             else {
9544               if((current.uu>>(r&63))&1) {
9545                 regs[i].regmap_entry[hr]=-1;
9546                 //regs[i].regmap[hr]=-1;
9547                 current.regmap[hr]=-1;
9548               }else
9549                 regs[i].regmap_entry[hr]=r;
9550             }
9551           }
9552         } else {
9553           // Branches expect CCREG to be allocated at the target
9554           if(regmap_pre[i][hr]==CCREG)
9555             regs[i].regmap_entry[hr]=CCREG;
9556           else
9557             regs[i].regmap_entry[hr]=-1;
9558         }
9559       }
9560       memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9561     }
9562
9563     if(i>0&&(itype[i-1]==STORE||itype[i-1]==STORELR||(itype[i-1]==C2LS&&opcode[i-1]==0x3a))&&(u_int)imm[i-1]<0x800)
9564       current.waswritten|=1<<rs1[i-1];
9565     current.waswritten&=~(1<<rt1[i]);
9566     current.waswritten&=~(1<<rt2[i]);
9567     if((itype[i]==STORE||itype[i]==STORELR||(itype[i]==C2LS&&opcode[i]==0x3a))&&(u_int)imm[i]>=0x800)
9568       current.waswritten&=~(1<<rs1[i]);
9569
9570     /* Branch post-alloc */
9571     if(i>0)
9572     {
9573       current.was32=current.is32;
9574       current.wasdirty=current.dirty;
9575       switch(itype[i-1]) {
9576         case UJUMP:
9577           memcpy(&branch_regs[i-1],&current,sizeof(current));
9578           branch_regs[i-1].isconst=0;
9579           branch_regs[i-1].wasconst=0;
9580           branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9581           branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9582           alloc_cc(&branch_regs[i-1],i-1);
9583           dirty_reg(&branch_regs[i-1],CCREG);
9584           if(rt1[i-1]==31) { // JAL
9585             alloc_reg(&branch_regs[i-1],i-1,31);
9586             dirty_reg(&branch_regs[i-1],31);
9587             branch_regs[i-1].is32|=1LL<<31;
9588           }
9589           memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9590           memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
9591           break;
9592         case RJUMP:
9593           memcpy(&branch_regs[i-1],&current,sizeof(current));
9594           branch_regs[i-1].isconst=0;
9595           branch_regs[i-1].wasconst=0;
9596           branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9597           branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9598           alloc_cc(&branch_regs[i-1],i-1);
9599           dirty_reg(&branch_regs[i-1],CCREG);
9600           alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
9601           if(rt1[i-1]!=0) { // JALR
9602             alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9603             dirty_reg(&branch_regs[i-1],rt1[i-1]);
9604             branch_regs[i-1].is32|=1LL<<rt1[i-1];
9605           }
9606           #ifdef USE_MINI_HT
9607           if(rs1[i-1]==31) { // JALR
9608             alloc_reg(&branch_regs[i-1],i-1,RHASH);
9609             #ifndef HOST_IMM_ADDR32
9610             alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9611             #endif
9612           }
9613           #endif
9614           memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9615           memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
9616           break;
9617         case CJUMP:
9618           if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9619           {
9620             alloc_cc(&current,i-1);
9621             dirty_reg(&current,CCREG);
9622             if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9623                (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9624               // The delay slot overwrote one of our conditions
9625               // Delay slot goes after the test (in order)
9626               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9627               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9628               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9629               current.u|=1;
9630               current.uu|=1;
9631               delayslot_alloc(&current,i);
9632               current.isconst=0;
9633             }
9634             else
9635             {
9636               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9637               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9638               // Alloc the branch condition registers
9639               if(rs1[i-1]) alloc_reg(&current,i-1,rs1[i-1]);
9640               if(rs2[i-1]) alloc_reg(&current,i-1,rs2[i-1]);
9641               if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9642               {
9643                 if(rs1[i-1]) alloc_reg64(&current,i-1,rs1[i-1]);
9644                 if(rs2[i-1]) alloc_reg64(&current,i-1,rs2[i-1]);
9645               }
9646             }
9647             memcpy(&branch_regs[i-1],&current,sizeof(current));
9648             branch_regs[i-1].isconst=0;
9649             branch_regs[i-1].wasconst=0;
9650             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9651             memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
9652           }
9653           else
9654           if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9655           {
9656             alloc_cc(&current,i-1);
9657             dirty_reg(&current,CCREG);
9658             if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9659               // The delay slot overwrote the branch condition
9660               // Delay slot goes after the test (in order)
9661               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9662               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9663               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9664               current.u|=1;
9665               current.uu|=1;
9666               delayslot_alloc(&current,i);
9667               current.isconst=0;
9668             }
9669             else
9670             {
9671               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9672               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9673               // Alloc the branch condition register
9674               alloc_reg(&current,i-1,rs1[i-1]);
9675               if(!(current.is32>>rs1[i-1]&1))
9676               {
9677                 alloc_reg64(&current,i-1,rs1[i-1]);
9678               }
9679             }
9680             memcpy(&branch_regs[i-1],&current,sizeof(current));
9681             branch_regs[i-1].isconst=0;
9682             branch_regs[i-1].wasconst=0;
9683             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9684             memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
9685           }
9686           else
9687           // Alloc the delay slot in case the branch is taken
9688           if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9689           {
9690             memcpy(&branch_regs[i-1],&current,sizeof(current));
9691             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9692             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9693             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9694             alloc_cc(&branch_regs[i-1],i);
9695             dirty_reg(&branch_regs[i-1],CCREG);
9696             delayslot_alloc(&branch_regs[i-1],i);
9697             branch_regs[i-1].isconst=0;
9698             alloc_reg(&current,i,CCREG); // Not taken path
9699             dirty_reg(&current,CCREG);
9700             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9701           }
9702           else
9703           if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9704           {
9705             memcpy(&branch_regs[i-1],&current,sizeof(current));
9706             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9707             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9708             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9709             alloc_cc(&branch_regs[i-1],i);
9710             dirty_reg(&branch_regs[i-1],CCREG);
9711             delayslot_alloc(&branch_regs[i-1],i);
9712             branch_regs[i-1].isconst=0;
9713             alloc_reg(&current,i,CCREG); // Not taken path
9714             dirty_reg(&current,CCREG);
9715             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9716           }
9717           break;
9718         case SJUMP:
9719           //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9720           if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9721           {
9722             alloc_cc(&current,i-1);
9723             dirty_reg(&current,CCREG);
9724             if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9725               // The delay slot overwrote the branch condition
9726               // Delay slot goes after the test (in order)
9727               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9728               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9729               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9730               current.u|=1;
9731               current.uu|=1;
9732               delayslot_alloc(&current,i);
9733               current.isconst=0;
9734             }
9735             else
9736             {
9737               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9738               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9739               // Alloc the branch condition register
9740               alloc_reg(&current,i-1,rs1[i-1]);
9741               if(!(current.is32>>rs1[i-1]&1))
9742               {
9743                 alloc_reg64(&current,i-1,rs1[i-1]);
9744               }
9745             }
9746             memcpy(&branch_regs[i-1],&current,sizeof(current));
9747             branch_regs[i-1].isconst=0;
9748             branch_regs[i-1].wasconst=0;
9749             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9750             memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
9751           }
9752           else
9753           // Alloc the delay slot in case the branch is taken
9754           if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9755           {
9756             memcpy(&branch_regs[i-1],&current,sizeof(current));
9757             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9758             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9759             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9760             alloc_cc(&branch_regs[i-1],i);
9761             dirty_reg(&branch_regs[i-1],CCREG);
9762             delayslot_alloc(&branch_regs[i-1],i);
9763             branch_regs[i-1].isconst=0;
9764             alloc_reg(&current,i,CCREG); // Not taken path
9765             dirty_reg(&current,CCREG);
9766             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9767           }
9768           // FIXME: BLTZAL/BGEZAL
9769           if(opcode2[i-1]&0x10) { // BxxZAL
9770             alloc_reg(&branch_regs[i-1],i-1,31);
9771             dirty_reg(&branch_regs[i-1],31);
9772             branch_regs[i-1].is32|=1LL<<31;
9773           }
9774           break;
9775         case FJUMP:
9776           if(likely[i-1]==0) // BC1F/BC1T
9777           {
9778             alloc_cc(&current,i-1);
9779             dirty_reg(&current,CCREG);
9780             if(itype[i]==FCOMP) {
9781               // The delay slot overwrote the branch condition
9782               // Delay slot goes after the test (in order)
9783               delayslot_alloc(&current,i);
9784               current.isconst=0;
9785             }
9786             else
9787             {
9788               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9789               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9790               // Alloc the branch condition register
9791               alloc_reg(&current,i-1,FSREG);
9792             }
9793             memcpy(&branch_regs[i-1],&current,sizeof(current));
9794             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9795           }
9796           else // BC1FL/BC1TL
9797           {
9798             // Alloc the delay slot in case the branch is taken
9799             memcpy(&branch_regs[i-1],&current,sizeof(current));
9800             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9801             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9802             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9803             alloc_cc(&branch_regs[i-1],i);
9804             dirty_reg(&branch_regs[i-1],CCREG);
9805             delayslot_alloc(&branch_regs[i-1],i);
9806             branch_regs[i-1].isconst=0;
9807             alloc_reg(&current,i,CCREG); // Not taken path
9808             dirty_reg(&current,CCREG);
9809             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9810           }
9811           break;
9812       }
9813
9814       if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9815       {
9816         if(rt1[i-1]==31) // JAL/JALR
9817         {
9818           // Subroutine call will return here, don't alloc any registers
9819           current.is32=1;
9820           current.dirty=0;
9821           clear_all_regs(current.regmap);
9822           alloc_reg(&current,i,CCREG);
9823           dirty_reg(&current,CCREG);
9824         }
9825         else if(i+1<slen)
9826         {
9827           // Internal branch will jump here, match registers to caller
9828           current.is32=0x3FFFFFFFFLL;
9829           current.dirty=0;
9830           clear_all_regs(current.regmap);
9831           alloc_reg(&current,i,CCREG);
9832           dirty_reg(&current,CCREG);
9833           for(j=i-1;j>=0;j--)
9834           {
9835             if(ba[j]==start+i*4+4) {
9836               memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9837               current.is32=branch_regs[j].is32;
9838               current.dirty=branch_regs[j].dirty;
9839               break;
9840             }
9841           }
9842           while(j>=0) {
9843             if(ba[j]==start+i*4+4) {
9844               for(hr=0;hr<HOST_REGS;hr++) {
9845                 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9846                   current.regmap[hr]=-1;
9847                 }
9848                 current.is32&=branch_regs[j].is32;
9849                 current.dirty&=branch_regs[j].dirty;
9850               }
9851             }
9852             j--;
9853           }
9854         }
9855       }
9856     }
9857
9858     // Count cycles in between branches
9859     ccadj[i]=cc;
9860     if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
9861     {
9862       cc=0;
9863     }
9864 #if defined(PCSX) && !defined(DRC_DBG)
9865     else if(itype[i]==C2OP&&gte_cycletab[source[i]&0x3f]>2)
9866     {
9867       // GTE runs in parallel until accessed, divide by 2 for a rough guess
9868       cc+=gte_cycletab[source[i]&0x3f]/2;
9869     }
9870     else if(/*itype[i]==LOAD||itype[i]==STORE||*/itype[i]==C1LS) // load,store causes weird timing issues
9871     {
9872       cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
9873     }
9874     else if(itype[i]==C2LS)
9875     {
9876       cc+=4;
9877     }
9878 #endif
9879     else
9880     {
9881       cc++;
9882     }
9883
9884     flush_dirty_uppers(&current);
9885     if(!is_ds[i]) {
9886       regs[i].is32=current.is32;
9887       regs[i].dirty=current.dirty;
9888       regs[i].isconst=current.isconst;
9889       memcpy(constmap[i],current_constmap,sizeof(current_constmap));
9890     }
9891     for(hr=0;hr<HOST_REGS;hr++) {
9892       if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
9893         if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9894           regs[i].wasconst&=~(1<<hr);
9895         }
9896       }
9897     }
9898     if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9899     regs[i].waswritten=current.waswritten;
9900   }
9901
9902   /* Pass 4 - Cull unused host registers */
9903
9904   uint64_t nr=0;
9905
9906   for (i=slen-1;i>=0;i--)
9907   {
9908     int hr;
9909     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9910     {
9911       if(ba[i]<start || ba[i]>=(start+slen*4))
9912       {
9913         // Branch out of this block, don't need anything
9914         nr=0;
9915       }
9916       else
9917       {
9918         // Internal branch
9919         // Need whatever matches the target
9920         nr=0;
9921         int t=(ba[i]-start)>>2;
9922         for(hr=0;hr<HOST_REGS;hr++)
9923         {
9924           if(regs[i].regmap_entry[hr]>=0) {
9925             if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9926           }
9927         }
9928       }
9929       // Conditional branch may need registers for following instructions
9930       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9931       {
9932         if(i<slen-2) {
9933           nr|=needed_reg[i+2];
9934           for(hr=0;hr<HOST_REGS;hr++)
9935           {
9936             if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9937             //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9938           }
9939         }
9940       }
9941       // Don't need stuff which is overwritten
9942       //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9943       //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9944       // Merge in delay slot
9945       for(hr=0;hr<HOST_REGS;hr++)
9946       {
9947         if(!likely[i]) {
9948           // These are overwritten unless the branch is "likely"
9949           // and the delay slot is nullified if not taken
9950           if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9951           if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9952         }
9953         if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9954         if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9955         if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9956         if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9957         if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9958         if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9959         if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9960         if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9961         if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9962           if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9963           if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9964         }
9965         if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9966           if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9967           if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9968         }
9969         if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
9970           if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9971           if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9972         }
9973       }
9974     }
9975     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
9976     {
9977       // SYSCALL instruction (software interrupt)
9978       nr=0;
9979     }
9980     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9981     {
9982       // ERET instruction (return from interrupt)
9983       nr=0;
9984     }
9985     else // Non-branch
9986     {
9987       if(i<slen-1) {
9988         for(hr=0;hr<HOST_REGS;hr++) {
9989           if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9990           if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9991           if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9992           if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9993         }
9994       }
9995     }
9996     for(hr=0;hr<HOST_REGS;hr++)
9997     {
9998       // Overwritten registers are not needed
9999       if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
10000       if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
10001       if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
10002       // Source registers are needed
10003       if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
10004       if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
10005       if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
10006       if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
10007       if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
10008       if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
10009       if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
10010       if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
10011       if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
10012         if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
10013         if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
10014       }
10015       if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
10016         if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
10017         if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
10018       }
10019       if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
10020         if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
10021         if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
10022       }
10023       // Don't store a register immediately after writing it,
10024       // may prevent dual-issue.
10025       // But do so if this is a branch target, otherwise we
10026       // might have to load the register before the branch.
10027       if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
10028         if((regmap_pre[i][hr]>0&&regmap_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
10029            (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
10030           if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
10031           if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
10032         }
10033         if((regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
10034            (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
10035           if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
10036           if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
10037         }
10038       }
10039     }
10040     // Cycle count is needed at branches.  Assume it is needed at the target too.
10041     if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
10042       if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
10043       if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
10044     }
10045     // Save it
10046     needed_reg[i]=nr;
10047
10048     // Deallocate unneeded registers
10049     for(hr=0;hr<HOST_REGS;hr++)
10050     {
10051       if(!((nr>>hr)&1)) {
10052         if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
10053         if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
10054            (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
10055            (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
10056         {
10057           if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10058           {
10059             if(likely[i]) {
10060               regs[i].regmap[hr]=-1;
10061               regs[i].isconst&=~(1<<hr);
10062               if(i<slen-2) {
10063                 regmap_pre[i+2][hr]=-1;
10064                 regs[i+2].wasconst&=~(1<<hr);
10065               }
10066             }
10067           }
10068         }
10069         if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10070         {
10071           int d1=0,d2=0,map=0,temp=0;
10072           if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
10073           {
10074             d1=dep1[i+1];
10075             d2=dep2[i+1];
10076           }
10077           if(using_tlb) {
10078             if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
10079                itype[i+1]==STORE || itype[i+1]==STORELR ||
10080                itype[i+1]==C1LS || itype[i+1]==C2LS)
10081             map=TLREG;
10082           } else
10083           if(itype[i+1]==STORE || itype[i+1]==STORELR ||
10084              (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
10085             map=INVCP;
10086           }
10087           if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
10088              itype[i+1]==C1LS || itype[i+1]==C2LS)
10089             temp=FTEMP;
10090           if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
10091              (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
10092              (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
10093              (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
10094              (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
10095              regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
10096              (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
10097              regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
10098              regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
10099              regs[i].regmap[hr]!=map )
10100           {
10101             regs[i].regmap[hr]=-1;
10102             regs[i].isconst&=~(1<<hr);
10103             if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
10104                (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
10105                (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
10106                (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
10107                (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
10108                branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
10109                (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
10110                branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
10111                branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
10112                branch_regs[i].regmap[hr]!=map)
10113             {
10114               branch_regs[i].regmap[hr]=-1;
10115               branch_regs[i].regmap_entry[hr]=-1;
10116               if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10117               {
10118                 if(!likely[i]&&i<slen-2) {
10119                   regmap_pre[i+2][hr]=-1;
10120                   regs[i+2].wasconst&=~(1<<hr);
10121                 }
10122               }
10123             }
10124           }
10125         }
10126         else
10127         {
10128           // Non-branch
10129           if(i>0)
10130           {
10131             int d1=0,d2=0,map=-1,temp=-1;
10132             if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
10133             {
10134               d1=dep1[i];
10135               d2=dep2[i];
10136             }
10137             if(using_tlb) {
10138               if(itype[i]==LOAD || itype[i]==LOADLR ||
10139                  itype[i]==STORE || itype[i]==STORELR ||
10140                  itype[i]==C1LS || itype[i]==C2LS)
10141               map=TLREG;
10142             } else if(itype[i]==STORE || itype[i]==STORELR ||
10143                       (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
10144               map=INVCP;
10145             }
10146             if(itype[i]==LOADLR || itype[i]==STORELR ||
10147                itype[i]==C1LS || itype[i]==C2LS)
10148               temp=FTEMP;
10149             if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
10150                (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
10151                (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
10152                regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
10153                (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
10154                (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
10155             {
10156               if(i<slen-1&&!is_ds[i]) {
10157                 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
10158                 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
10159                 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
10160                 {
10161                   printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
10162                   assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
10163                 }
10164                 regmap_pre[i+1][hr]=-1;
10165                 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
10166                 regs[i+1].wasconst&=~(1<<hr);
10167               }
10168               regs[i].regmap[hr]=-1;
10169               regs[i].isconst&=~(1<<hr);
10170             }
10171           }
10172         }
10173       }
10174     }
10175   }
10176
10177   /* Pass 5 - Pre-allocate registers */
10178
10179   // If a register is allocated during a loop, try to allocate it for the
10180   // entire loop, if possible.  This avoids loading/storing registers
10181   // inside of the loop.
10182
10183   signed char f_regmap[HOST_REGS];
10184   clear_all_regs(f_regmap);
10185   for(i=0;i<slen-1;i++)
10186   {
10187     if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10188     {
10189       if(ba[i]>=start && ba[i]<(start+i*4))
10190       if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
10191       ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
10192       ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
10193       ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
10194       ||itype[i+1]==FCOMP||itype[i+1]==FCONV
10195       ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
10196       {
10197         int t=(ba[i]-start)>>2;
10198         if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
10199         if(t<2||(itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||rt1[t-2]!=31) // call/ret assumes no registers allocated
10200         for(hr=0;hr<HOST_REGS;hr++)
10201         {
10202           if(regs[i].regmap[hr]>64) {
10203             if(!((regs[i].dirty>>hr)&1))
10204               f_regmap[hr]=regs[i].regmap[hr];
10205             else f_regmap[hr]=-1;
10206           }
10207           else if(regs[i].regmap[hr]>=0) {
10208             if(f_regmap[hr]!=regs[i].regmap[hr]) {
10209               // dealloc old register
10210               int n;
10211               for(n=0;n<HOST_REGS;n++)
10212               {
10213                 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10214               }
10215               // and alloc new one
10216               f_regmap[hr]=regs[i].regmap[hr];
10217             }
10218           }
10219           if(branch_regs[i].regmap[hr]>64) {
10220             if(!((branch_regs[i].dirty>>hr)&1))
10221               f_regmap[hr]=branch_regs[i].regmap[hr];
10222             else f_regmap[hr]=-1;
10223           }
10224           else if(branch_regs[i].regmap[hr]>=0) {
10225             if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
10226               // dealloc old register
10227               int n;
10228               for(n=0;n<HOST_REGS;n++)
10229               {
10230                 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
10231               }
10232               // and alloc new one
10233               f_regmap[hr]=branch_regs[i].regmap[hr];
10234             }
10235           }
10236           if(ooo[i]) {
10237             if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
10238               f_regmap[hr]=branch_regs[i].regmap[hr];
10239           }else{
10240             if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
10241               f_regmap[hr]=branch_regs[i].regmap[hr];
10242           }
10243           // Avoid dirty->clean transition
10244           #ifdef DESTRUCTIVE_WRITEBACK
10245           if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
10246           #endif
10247           // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
10248           // case above, however it's always a good idea.  We can't hoist the
10249           // load if the register was already allocated, so there's no point
10250           // wasting time analyzing most of these cases.  It only "succeeds"
10251           // when the mapping was different and the load can be replaced with
10252           // a mov, which is of negligible benefit.  So such cases are
10253           // skipped below.
10254           if(f_regmap[hr]>0) {
10255             if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
10256               int r=f_regmap[hr];
10257               for(j=t;j<=i;j++)
10258               {
10259                 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10260                 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
10261                 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
10262                 if(r>63) {
10263                   // NB This can exclude the case where the upper-half
10264                   // register is lower numbered than the lower-half
10265                   // register.  Not sure if it's worth fixing...
10266                   if(get_reg(regs[j].regmap,r&63)<0) break;
10267                   if(get_reg(regs[j].regmap_entry,r&63)<0) break;
10268                   if(regs[j].is32&(1LL<<(r&63))) break;
10269                 }
10270                 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
10271                   //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10272                   int k;
10273                   if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
10274                     if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
10275                     if(r>63) {
10276                       if(get_reg(regs[i].regmap,r&63)<0) break;
10277                       if(get_reg(branch_regs[i].regmap,r&63)<0) break;
10278                     }
10279                     k=i;
10280                     while(k>1&&regs[k-1].regmap[hr]==-1) {
10281                       if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10282                         //printf("no free regs for store %x\n",start+(k-1)*4);
10283                         break;
10284                       }
10285                       if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
10286                         //printf("no-match due to different register\n");
10287                         break;
10288                       }
10289                       if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
10290                         //printf("no-match due to branch\n");
10291                         break;
10292                       }
10293                       // call/ret fast path assumes no registers allocated
10294                       if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)&&rt1[k-3]==31) {
10295                         break;
10296                       }
10297                       if(r>63) {
10298                         // NB This can exclude the case where the upper-half
10299                         // register is lower numbered than the lower-half
10300                         // register.  Not sure if it's worth fixing...
10301                         if(get_reg(regs[k-1].regmap,r&63)<0) break;
10302                         if(regs[k-1].is32&(1LL<<(r&63))) break;
10303                       }
10304                       k--;
10305                     }
10306                     if(i<slen-1) {
10307                       if((regs[k].is32&(1LL<<f_regmap[hr]))!=
10308                         (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
10309                         //printf("bad match after branch\n");
10310                         break;
10311                       }
10312                     }
10313                     if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
10314                       //printf("Extend r%d, %x ->\n",hr,start+k*4);
10315                       while(k<i) {
10316                         regs[k].regmap_entry[hr]=f_regmap[hr];
10317                         regs[k].regmap[hr]=f_regmap[hr];
10318                         regmap_pre[k+1][hr]=f_regmap[hr];
10319                         regs[k].wasdirty&=~(1<<hr);
10320                         regs[k].dirty&=~(1<<hr);
10321                         regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
10322                         regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
10323                         regs[k].wasconst&=~(1<<hr);
10324                         regs[k].isconst&=~(1<<hr);
10325                         k++;
10326                       }
10327                     }
10328                     else {
10329                       //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
10330                       break;
10331                     }
10332                     assert(regs[i-1].regmap[hr]==f_regmap[hr]);
10333                     if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
10334                       //printf("OK fill %x (r%d)\n",start+i*4,hr);
10335                       regs[i].regmap_entry[hr]=f_regmap[hr];
10336                       regs[i].regmap[hr]=f_regmap[hr];
10337                       regs[i].wasdirty&=~(1<<hr);
10338                       regs[i].dirty&=~(1<<hr);
10339                       regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
10340                       regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
10341                       regs[i].wasconst&=~(1<<hr);
10342                       regs[i].isconst&=~(1<<hr);
10343                       branch_regs[i].regmap_entry[hr]=f_regmap[hr];
10344                       branch_regs[i].wasdirty&=~(1<<hr);
10345                       branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
10346                       branch_regs[i].regmap[hr]=f_regmap[hr];
10347                       branch_regs[i].dirty&=~(1<<hr);
10348                       branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
10349                       branch_regs[i].wasconst&=~(1<<hr);
10350                       branch_regs[i].isconst&=~(1<<hr);
10351                       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
10352                         regmap_pre[i+2][hr]=f_regmap[hr];
10353                         regs[i+2].wasdirty&=~(1<<hr);
10354                         regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
10355                         assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
10356                           (regs[i+2].was32&(1LL<<f_regmap[hr])));
10357                       }
10358                     }
10359                   }
10360                   for(k=t;k<j;k++) {
10361                     // Alloc register clean at beginning of loop,
10362                     // but may dirty it in pass 6
10363                     regs[k].regmap_entry[hr]=f_regmap[hr];
10364                     regs[k].regmap[hr]=f_regmap[hr];
10365                     regs[k].dirty&=~(1<<hr);
10366                     regs[k].wasconst&=~(1<<hr);
10367                     regs[k].isconst&=~(1<<hr);
10368                     if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) {
10369                       branch_regs[k].regmap_entry[hr]=f_regmap[hr];
10370                       branch_regs[k].regmap[hr]=f_regmap[hr];
10371                       branch_regs[k].dirty&=~(1<<hr);
10372                       branch_regs[k].wasconst&=~(1<<hr);
10373                       branch_regs[k].isconst&=~(1<<hr);
10374                       if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
10375                         regmap_pre[k+2][hr]=f_regmap[hr];
10376                         regs[k+2].wasdirty&=~(1<<hr);
10377                         assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))==
10378                           (regs[k+2].was32&(1LL<<f_regmap[hr])));
10379                       }
10380                     }
10381                     else
10382                     {
10383                       regmap_pre[k+1][hr]=f_regmap[hr];
10384                       regs[k+1].wasdirty&=~(1<<hr);
10385                     }
10386                   }
10387                   if(regs[j].regmap[hr]==f_regmap[hr])
10388                     regs[j].regmap_entry[hr]=f_regmap[hr];
10389                   break;
10390                 }
10391                 if(j==i) break;
10392                 if(regs[j].regmap[hr]>=0)
10393                   break;
10394                 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
10395                   //printf("no-match due to different register\n");
10396                   break;
10397                 }
10398                 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
10399                   //printf("32/64 mismatch %x %d\n",start+j*4,hr);
10400                   break;
10401                 }
10402                 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10403                 {
10404                   // Stop on unconditional branch
10405                   break;
10406                 }
10407                 if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
10408                 {
10409                   if(ooo[j]) {
10410                     if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
10411                       break;
10412                   }else{
10413                     if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
10414                       break;
10415                   }
10416                   if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
10417                     //printf("no-match due to different register (branch)\n");
10418                     break;
10419                   }
10420                 }
10421                 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10422                   //printf("No free regs for store %x\n",start+j*4);
10423                   break;
10424                 }
10425                 if(f_regmap[hr]>=64) {
10426                   if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
10427                     break;
10428                   }
10429                   else
10430                   {
10431                     if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
10432                       break;
10433                     }
10434                   }
10435                 }
10436               }
10437             }
10438           }
10439         }
10440       }
10441     }else{
10442       // Non branch or undetermined branch target
10443       for(hr=0;hr<HOST_REGS;hr++)
10444       {
10445         if(hr!=EXCLUDE_REG) {
10446           if(regs[i].regmap[hr]>64) {
10447             if(!((regs[i].dirty>>hr)&1))
10448               f_regmap[hr]=regs[i].regmap[hr];
10449           }
10450           else if(regs[i].regmap[hr]>=0) {
10451             if(f_regmap[hr]!=regs[i].regmap[hr]) {
10452               // dealloc old register
10453               int n;
10454               for(n=0;n<HOST_REGS;n++)
10455               {
10456                 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10457               }
10458               // and alloc new one
10459               f_regmap[hr]=regs[i].regmap[hr];
10460             }
10461           }
10462         }
10463       }
10464       // Try to restore cycle count at branch targets
10465       if(bt[i]) {
10466         for(j=i;j<slen-1;j++) {
10467           if(regs[j].regmap[HOST_CCREG]!=-1) break;
10468           if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10469             //printf("no free regs for store %x\n",start+j*4);
10470             break;
10471           }
10472         }
10473         if(regs[j].regmap[HOST_CCREG]==CCREG) {
10474           int k=i;
10475           //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
10476           while(k<j) {
10477             regs[k].regmap_entry[HOST_CCREG]=CCREG;
10478             regs[k].regmap[HOST_CCREG]=CCREG;
10479             regmap_pre[k+1][HOST_CCREG]=CCREG;
10480             regs[k+1].wasdirty|=1<<HOST_CCREG;
10481             regs[k].dirty|=1<<HOST_CCREG;
10482             regs[k].wasconst&=~(1<<HOST_CCREG);
10483             regs[k].isconst&=~(1<<HOST_CCREG);
10484             k++;
10485           }
10486           regs[j].regmap_entry[HOST_CCREG]=CCREG;
10487         }
10488         // Work backwards from the branch target
10489         if(j>i&&f_regmap[HOST_CCREG]==CCREG)
10490         {
10491           //printf("Extend backwards\n");
10492           int k;
10493           k=i;
10494           while(regs[k-1].regmap[HOST_CCREG]==-1) {
10495             if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10496               //printf("no free regs for store %x\n",start+(k-1)*4);
10497               break;
10498             }
10499             k--;
10500           }
10501           if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
10502             //printf("Extend CC, %x ->\n",start+k*4);
10503             while(k<=i) {
10504               regs[k].regmap_entry[HOST_CCREG]=CCREG;
10505               regs[k].regmap[HOST_CCREG]=CCREG;
10506               regmap_pre[k+1][HOST_CCREG]=CCREG;
10507               regs[k+1].wasdirty|=1<<HOST_CCREG;
10508               regs[k].dirty|=1<<HOST_CCREG;
10509               regs[k].wasconst&=~(1<<HOST_CCREG);
10510               regs[k].isconst&=~(1<<HOST_CCREG);
10511               k++;
10512             }
10513           }
10514           else {
10515             //printf("Fail Extend CC, %x ->\n",start+k*4);
10516           }
10517         }
10518       }
10519       if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
10520          itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
10521          itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
10522          itype[i]!=FCONV&&itype[i]!=FCOMP)
10523       {
10524         memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
10525       }
10526     }
10527   }
10528
10529   // Cache memory offset or tlb map pointer if a register is available
10530   #ifndef HOST_IMM_ADDR32
10531   #ifndef RAM_OFFSET
10532   if(using_tlb)
10533   #endif
10534   {
10535     int earliest_available[HOST_REGS];
10536     int loop_start[HOST_REGS];
10537     int score[HOST_REGS];
10538     int end[HOST_REGS];
10539     int reg=using_tlb?MMREG:ROREG;
10540
10541     // Init
10542     for(hr=0;hr<HOST_REGS;hr++) {
10543       score[hr]=0;earliest_available[hr]=0;
10544       loop_start[hr]=MAXBLOCK;
10545     }
10546     for(i=0;i<slen-1;i++)
10547     {
10548       // Can't do anything if no registers are available
10549       if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i]) {
10550         for(hr=0;hr<HOST_REGS;hr++) {
10551           score[hr]=0;earliest_available[hr]=i+1;
10552           loop_start[hr]=MAXBLOCK;
10553         }
10554       }
10555       if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10556         if(!ooo[i]) {
10557           if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) {
10558             for(hr=0;hr<HOST_REGS;hr++) {
10559               score[hr]=0;earliest_available[hr]=i+1;
10560               loop_start[hr]=MAXBLOCK;
10561             }
10562           }
10563         }else{
10564           if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) {
10565             for(hr=0;hr<HOST_REGS;hr++) {
10566               score[hr]=0;earliest_available[hr]=i+1;
10567               loop_start[hr]=MAXBLOCK;
10568             }
10569           }
10570         }
10571       }
10572       // Mark unavailable registers
10573       for(hr=0;hr<HOST_REGS;hr++) {
10574         if(regs[i].regmap[hr]>=0) {
10575           score[hr]=0;earliest_available[hr]=i+1;
10576           loop_start[hr]=MAXBLOCK;
10577         }
10578         if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10579           if(branch_regs[i].regmap[hr]>=0) {
10580             score[hr]=0;earliest_available[hr]=i+2;
10581             loop_start[hr]=MAXBLOCK;
10582           }
10583         }
10584       }
10585       // No register allocations after unconditional jumps
10586       if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10587       {
10588         for(hr=0;hr<HOST_REGS;hr++) {
10589           score[hr]=0;earliest_available[hr]=i+2;
10590           loop_start[hr]=MAXBLOCK;
10591         }
10592         i++; // Skip delay slot too
10593         //printf("skip delay slot: %x\n",start+i*4);
10594       }
10595       else
10596       // Possible match
10597       if(itype[i]==LOAD||itype[i]==LOADLR||
10598          itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) {
10599         for(hr=0;hr<HOST_REGS;hr++) {
10600           if(hr!=EXCLUDE_REG) {
10601             end[hr]=i-1;
10602             for(j=i;j<slen-1;j++) {
10603               if(regs[j].regmap[hr]>=0) break;
10604               if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10605                 if(branch_regs[j].regmap[hr]>=0) break;
10606                 if(ooo[j]) {
10607                   if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) break;
10608                 }else{
10609                   if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) break;
10610                 }
10611               }
10612               else if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) break;
10613               if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10614                 int t=(ba[j]-start)>>2;
10615                 if(t<j&&t>=earliest_available[hr]) {
10616                   if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) { // call/ret assumes no registers allocated
10617                     // Score a point for hoisting loop invariant
10618                     if(t<loop_start[hr]) loop_start[hr]=t;
10619                     //printf("set loop_start: i=%x j=%x (%x)\n",start+i*4,start+j*4,start+t*4);
10620                     score[hr]++;
10621                     end[hr]=j;
10622                   }
10623                 }
10624                 else if(t<j) {
10625                   if(regs[t].regmap[hr]==reg) {
10626                     // Score a point if the branch target matches this register
10627                     score[hr]++;
10628                     end[hr]=j;
10629                   }
10630                 }
10631                 if(itype[j+1]==LOAD||itype[j+1]==LOADLR||
10632                    itype[j+1]==STORE||itype[j+1]==STORELR||itype[j+1]==C1LS) {
10633                   score[hr]++;
10634                   end[hr]=j;
10635                 }
10636               }
10637               if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10638               {
10639                 // Stop on unconditional branch
10640                 break;
10641               }
10642               else
10643               if(itype[j]==LOAD||itype[j]==LOADLR||
10644                  itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS) {
10645                 score[hr]++;
10646                 end[hr]=j;
10647               }
10648             }
10649           }
10650         }
10651         // Find highest score and allocate that register
10652         int maxscore=0;
10653         for(hr=0;hr<HOST_REGS;hr++) {
10654           if(hr!=EXCLUDE_REG) {
10655             if(score[hr]>score[maxscore]) {
10656               maxscore=hr;
10657               //printf("highest score: %d %d (%x->%x)\n",score[hr],hr,start+i*4,start+end[hr]*4);
10658             }
10659           }
10660         }
10661         if(score[maxscore]>1)
10662         {
10663           if(i<loop_start[maxscore]) loop_start[maxscore]=i;
10664           for(j=loop_start[maxscore];j<slen&&j<=end[maxscore];j++) {
10665             //if(regs[j].regmap[maxscore]>=0) {printf("oops: %x %x was %d=%d\n",loop_start[maxscore]*4+start,j*4+start,maxscore,regs[j].regmap[maxscore]);}
10666             assert(regs[j].regmap[maxscore]<0);
10667             if(j>loop_start[maxscore]) regs[j].regmap_entry[maxscore]=reg;
10668             regs[j].regmap[maxscore]=reg;
10669             regs[j].dirty&=~(1<<maxscore);
10670             regs[j].wasconst&=~(1<<maxscore);
10671             regs[j].isconst&=~(1<<maxscore);
10672             if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10673               branch_regs[j].regmap[maxscore]=reg;
10674               branch_regs[j].wasdirty&=~(1<<maxscore);
10675               branch_regs[j].dirty&=~(1<<maxscore);
10676               branch_regs[j].wasconst&=~(1<<maxscore);
10677               branch_regs[j].isconst&=~(1<<maxscore);
10678               if(itype[j]!=RJUMP&&itype[j]!=UJUMP&&(source[j]>>16)!=0x1000) {
10679                 regmap_pre[j+2][maxscore]=reg;
10680                 regs[j+2].wasdirty&=~(1<<maxscore);
10681               }
10682               // loop optimization (loop_preload)
10683               int t=(ba[j]-start)>>2;
10684               if(t==loop_start[maxscore]) {
10685                 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) // call/ret assumes no registers allocated
10686                   regs[t].regmap_entry[maxscore]=reg;
10687               }
10688             }
10689             else
10690             {
10691               if(j<1||(itype[j-1]!=RJUMP&&itype[j-1]!=UJUMP&&itype[j-1]!=CJUMP&&itype[j-1]!=SJUMP&&itype[j-1]!=FJUMP)) {
10692                 regmap_pre[j+1][maxscore]=reg;
10693                 regs[j+1].wasdirty&=~(1<<maxscore);
10694               }
10695             }
10696           }
10697           i=j-1;
10698           if(itype[j-1]==RJUMP||itype[j-1]==UJUMP||itype[j-1]==CJUMP||itype[j-1]==SJUMP||itype[j-1]==FJUMP) i++; // skip delay slot
10699           for(hr=0;hr<HOST_REGS;hr++) {
10700             score[hr]=0;earliest_available[hr]=i+i;
10701             loop_start[hr]=MAXBLOCK;
10702           }
10703         }
10704       }
10705     }
10706   }
10707   #endif
10708
10709   // This allocates registers (if possible) one instruction prior
10710   // to use, which can avoid a load-use penalty on certain CPUs.
10711   for(i=0;i<slen-1;i++)
10712   {
10713     if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10714     {
10715       if(!bt[i+1])
10716       {
10717         if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
10718            ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
10719         {
10720           if(rs1[i+1]) {
10721             if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10722             {
10723               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10724               {
10725                 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10726                 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10727                 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10728                 regs[i].isconst&=~(1<<hr);
10729                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10730                 constmap[i][hr]=constmap[i+1][hr];
10731                 regs[i+1].wasdirty&=~(1<<hr);
10732                 regs[i].dirty&=~(1<<hr);
10733               }
10734             }
10735           }
10736           if(rs2[i+1]) {
10737             if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10738             {
10739               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10740               {
10741                 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10742                 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10743                 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10744                 regs[i].isconst&=~(1<<hr);
10745                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10746                 constmap[i][hr]=constmap[i+1][hr];
10747                 regs[i+1].wasdirty&=~(1<<hr);
10748                 regs[i].dirty&=~(1<<hr);
10749               }
10750             }
10751           }
10752           // Preload target address for load instruction (non-constant)
10753           if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10754             if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10755             {
10756               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10757               {
10758                 regs[i].regmap[hr]=rs1[i+1];
10759                 regmap_pre[i+1][hr]=rs1[i+1];
10760                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10761                 regs[i].isconst&=~(1<<hr);
10762                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10763                 constmap[i][hr]=constmap[i+1][hr];
10764                 regs[i+1].wasdirty&=~(1<<hr);
10765                 regs[i].dirty&=~(1<<hr);
10766               }
10767             }
10768           }
10769           // Load source into target register
10770           if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10771             if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10772             {
10773               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10774               {
10775                 regs[i].regmap[hr]=rs1[i+1];
10776                 regmap_pre[i+1][hr]=rs1[i+1];
10777                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10778                 regs[i].isconst&=~(1<<hr);
10779                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10780                 constmap[i][hr]=constmap[i+1][hr];
10781                 regs[i+1].wasdirty&=~(1<<hr);
10782                 regs[i].dirty&=~(1<<hr);
10783               }
10784             }
10785           }
10786           // Preload map address
10787           #ifndef HOST_IMM_ADDR32
10788           if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
10789             hr=get_reg(regs[i+1].regmap,TLREG);
10790             if(hr>=0) {
10791               int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10792               if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10793                 int nr;
10794                 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10795                 {
10796                   regs[i].regmap[hr]=MGEN1+((i+1)&1);
10797                   regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10798                   regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10799                   regs[i].isconst&=~(1<<hr);
10800                   regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10801                   constmap[i][hr]=constmap[i+1][hr];
10802                   regs[i+1].wasdirty&=~(1<<hr);
10803                   regs[i].dirty&=~(1<<hr);
10804                 }
10805                 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10806                 {
10807                   // move it to another register
10808                   regs[i+1].regmap[hr]=-1;
10809                   regmap_pre[i+2][hr]=-1;
10810                   regs[i+1].regmap[nr]=TLREG;
10811                   regmap_pre[i+2][nr]=TLREG;
10812                   regs[i].regmap[nr]=MGEN1+((i+1)&1);
10813                   regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10814                   regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10815                   regs[i].isconst&=~(1<<nr);
10816                   regs[i+1].isconst&=~(1<<nr);
10817                   regs[i].dirty&=~(1<<nr);
10818                   regs[i+1].wasdirty&=~(1<<nr);
10819                   regs[i+1].dirty&=~(1<<nr);
10820                   regs[i+2].wasdirty&=~(1<<nr);
10821                 }
10822               }
10823             }
10824           }
10825           #endif
10826           // Address for store instruction (non-constant)
10827           if(itype[i+1]==STORE||itype[i+1]==STORELR
10828              ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
10829             if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10830               hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10831               if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10832               else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10833               assert(hr>=0);
10834               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10835               {
10836                 regs[i].regmap[hr]=rs1[i+1];
10837                 regmap_pre[i+1][hr]=rs1[i+1];
10838                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10839                 regs[i].isconst&=~(1<<hr);
10840                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10841                 constmap[i][hr]=constmap[i+1][hr];
10842                 regs[i+1].wasdirty&=~(1<<hr);
10843                 regs[i].dirty&=~(1<<hr);
10844               }
10845             }
10846           }
10847           if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
10848             if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10849               int nr;
10850               hr=get_reg(regs[i+1].regmap,FTEMP);
10851               assert(hr>=0);
10852               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10853               {
10854                 regs[i].regmap[hr]=rs1[i+1];
10855                 regmap_pre[i+1][hr]=rs1[i+1];
10856                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10857                 regs[i].isconst&=~(1<<hr);
10858                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10859                 constmap[i][hr]=constmap[i+1][hr];
10860                 regs[i+1].wasdirty&=~(1<<hr);
10861                 regs[i].dirty&=~(1<<hr);
10862               }
10863               else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10864               {
10865                 // move it to another register
10866                 regs[i+1].regmap[hr]=-1;
10867                 regmap_pre[i+2][hr]=-1;
10868                 regs[i+1].regmap[nr]=FTEMP;
10869                 regmap_pre[i+2][nr]=FTEMP;
10870                 regs[i].regmap[nr]=rs1[i+1];
10871                 regmap_pre[i+1][nr]=rs1[i+1];
10872                 regs[i+1].regmap_entry[nr]=rs1[i+1];
10873                 regs[i].isconst&=~(1<<nr);
10874                 regs[i+1].isconst&=~(1<<nr);
10875                 regs[i].dirty&=~(1<<nr);
10876                 regs[i+1].wasdirty&=~(1<<nr);
10877                 regs[i+1].dirty&=~(1<<nr);
10878                 regs[i+2].wasdirty&=~(1<<nr);
10879               }
10880             }
10881           }
10882           if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
10883             if(itype[i+1]==LOAD)
10884               hr=get_reg(regs[i+1].regmap,rt1[i+1]);
10885             if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
10886               hr=get_reg(regs[i+1].regmap,FTEMP);
10887             if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
10888               hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10889               if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10890             }
10891             if(hr>=0&&regs[i].regmap[hr]<0) {
10892               int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10893               if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10894                 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10895                 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10896                 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10897                 regs[i].isconst&=~(1<<hr);
10898                 regs[i+1].wasdirty&=~(1<<hr);
10899                 regs[i].dirty&=~(1<<hr);
10900               }
10901             }
10902           }
10903         }
10904       }
10905     }
10906   }
10907
10908   /* Pass 6 - Optimize clean/dirty state */
10909   clean_registers(0,slen-1,1);
10910
10911   /* Pass 7 - Identify 32-bit registers */
10912 #ifndef FORCE32
10913   provisional_r32();
10914
10915   u_int r32=0;
10916
10917   for (i=slen-1;i>=0;i--)
10918   {
10919     int hr;
10920     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10921     {
10922       if(ba[i]<start || ba[i]>=(start+slen*4))
10923       {
10924         // Branch out of this block, don't need anything
10925         r32=0;
10926       }
10927       else
10928       {
10929         // Internal branch
10930         // Need whatever matches the target
10931         // (and doesn't get overwritten by the delay slot instruction)
10932         r32=0;
10933         int t=(ba[i]-start)>>2;
10934         if(ba[i]>start+i*4) {
10935           // Forward branch
10936           if(!(requires_32bit[t]&~regs[i].was32))
10937             r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10938         }else{
10939           // Backward branch
10940           //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10941           //  r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10942           if(!(pr32[t]&~regs[i].was32))
10943             r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10944         }
10945       }
10946       // Conditional branch may need registers for following instructions
10947       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10948       {
10949         if(i<slen-2) {
10950           r32|=requires_32bit[i+2];
10951           r32&=regs[i].was32;
10952           // Mark this address as a branch target since it may be called
10953           // upon return from interrupt
10954           bt[i+2]=1;
10955         }
10956       }
10957       // Merge in delay slot
10958       if(!likely[i]) {
10959         // These are overwritten unless the branch is "likely"
10960         // and the delay slot is nullified if not taken
10961         r32&=~(1LL<<rt1[i+1]);
10962         r32&=~(1LL<<rt2[i+1]);
10963       }
10964       // Assume these are needed (delay slot)
10965       if(us1[i+1]>0)
10966       {
10967         if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10968       }
10969       if(us2[i+1]>0)
10970       {
10971         if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10972       }
10973       if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10974       {
10975         if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10976       }
10977       if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10978       {
10979         if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10980       }
10981     }
10982     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
10983     {
10984       // SYSCALL instruction (software interrupt)
10985       r32=0;
10986     }
10987     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10988     {
10989       // ERET instruction (return from interrupt)
10990       r32=0;
10991     }
10992     // Check 32 bits
10993     r32&=~(1LL<<rt1[i]);
10994     r32&=~(1LL<<rt2[i]);
10995     if(us1[i]>0)
10996     {
10997       if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10998     }
10999     if(us2[i]>0)
11000     {
11001       if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
11002     }
11003     if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
11004     {
11005       if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
11006     }
11007     if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
11008     {
11009       if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
11010     }
11011     requires_32bit[i]=r32;
11012
11013     // Dirty registers which are 32-bit, require 32-bit input
11014     // as they will be written as 32-bit values
11015     for(hr=0;hr<HOST_REGS;hr++)
11016     {
11017       if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
11018         if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
11019           if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
11020           requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
11021         }
11022       }
11023     }
11024     //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
11025   }
11026 #else
11027   for (i=slen-1;i>=0;i--)
11028   {
11029     if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
11030     {
11031       // Conditional branch
11032       if((source[i]>>16)!=0x1000&&i<slen-2) {
11033         // Mark this address as a branch target since it may be called
11034         // upon return from interrupt
11035         bt[i+2]=1;
11036       }
11037     }
11038   }
11039 #endif
11040
11041   if(itype[slen-1]==SPAN) {
11042     bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
11043   }
11044
11045 #ifdef DISASM
11046   /* Debug/disassembly */
11047   for(i=0;i<slen;i++)
11048   {
11049     printf("U:");
11050     int r;
11051     for(r=1;r<=CCREG;r++) {
11052       if((unneeded_reg[i]>>r)&1) {
11053         if(r==HIREG) printf(" HI");
11054         else if(r==LOREG) printf(" LO");
11055         else printf(" r%d",r);
11056       }
11057     }
11058 #ifndef FORCE32
11059     printf(" UU:");
11060     for(r=1;r<=CCREG;r++) {
11061       if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
11062         if(r==HIREG) printf(" HI");
11063         else if(r==LOREG) printf(" LO");
11064         else printf(" r%d",r);
11065       }
11066     }
11067     printf(" 32:");
11068     for(r=0;r<=CCREG;r++) {
11069       //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
11070       if((regs[i].was32>>r)&1) {
11071         if(r==CCREG) printf(" CC");
11072         else if(r==HIREG) printf(" HI");
11073         else if(r==LOREG) printf(" LO");
11074         else printf(" r%d",r);
11075       }
11076     }
11077 #endif
11078     printf("\n");
11079     #if defined(__i386__) || defined(__x86_64__)
11080     printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
11081     #endif
11082     #ifdef __arm__
11083     printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
11084     #endif
11085     printf("needs: ");
11086     if(needed_reg[i]&1) printf("eax ");
11087     if((needed_reg[i]>>1)&1) printf("ecx ");
11088     if((needed_reg[i]>>2)&1) printf("edx ");
11089     if((needed_reg[i]>>3)&1) printf("ebx ");
11090     if((needed_reg[i]>>5)&1) printf("ebp ");
11091     if((needed_reg[i]>>6)&1) printf("esi ");
11092     if((needed_reg[i]>>7)&1) printf("edi ");
11093     printf("r:");
11094     for(r=0;r<=CCREG;r++) {
11095       //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
11096       if((requires_32bit[i]>>r)&1) {
11097         if(r==CCREG) printf(" CC");
11098         else if(r==HIREG) printf(" HI");
11099         else if(r==LOREG) printf(" LO");
11100         else printf(" r%d",r);
11101       }
11102     }
11103     printf("\n");
11104     /*printf("pr:");
11105     for(r=0;r<=CCREG;r++) {
11106       //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
11107       if((pr32[i]>>r)&1) {
11108         if(r==CCREG) printf(" CC");
11109         else if(r==HIREG) printf(" HI");
11110         else if(r==LOREG) printf(" LO");
11111         else printf(" r%d",r);
11112       }
11113     }
11114     if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
11115     printf("\n");*/
11116     #if defined(__i386__) || defined(__x86_64__)
11117     printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
11118     printf("dirty: ");
11119     if(regs[i].wasdirty&1) printf("eax ");
11120     if((regs[i].wasdirty>>1)&1) printf("ecx ");
11121     if((regs[i].wasdirty>>2)&1) printf("edx ");
11122     if((regs[i].wasdirty>>3)&1) printf("ebx ");
11123     if((regs[i].wasdirty>>5)&1) printf("ebp ");
11124     if((regs[i].wasdirty>>6)&1) printf("esi ");
11125     if((regs[i].wasdirty>>7)&1) printf("edi ");
11126     #endif
11127     #ifdef __arm__
11128     printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
11129     printf("dirty: ");
11130     if(regs[i].wasdirty&1) printf("r0 ");
11131     if((regs[i].wasdirty>>1)&1) printf("r1 ");
11132     if((regs[i].wasdirty>>2)&1) printf("r2 ");
11133     if((regs[i].wasdirty>>3)&1) printf("r3 ");
11134     if((regs[i].wasdirty>>4)&1) printf("r4 ");
11135     if((regs[i].wasdirty>>5)&1) printf("r5 ");
11136     if((regs[i].wasdirty>>6)&1) printf("r6 ");
11137     if((regs[i].wasdirty>>7)&1) printf("r7 ");
11138     if((regs[i].wasdirty>>8)&1) printf("r8 ");
11139     if((regs[i].wasdirty>>9)&1) printf("r9 ");
11140     if((regs[i].wasdirty>>10)&1) printf("r10 ");
11141     if((regs[i].wasdirty>>12)&1) printf("r12 ");
11142     #endif
11143     printf("\n");
11144     disassemble_inst(i);
11145     //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
11146     #if defined(__i386__) || defined(__x86_64__)
11147     printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
11148     if(regs[i].dirty&1) printf("eax ");
11149     if((regs[i].dirty>>1)&1) printf("ecx ");
11150     if((regs[i].dirty>>2)&1) printf("edx ");
11151     if((regs[i].dirty>>3)&1) printf("ebx ");
11152     if((regs[i].dirty>>5)&1) printf("ebp ");
11153     if((regs[i].dirty>>6)&1) printf("esi ");
11154     if((regs[i].dirty>>7)&1) printf("edi ");
11155     #endif
11156     #ifdef __arm__
11157     printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
11158     if(regs[i].dirty&1) printf("r0 ");
11159     if((regs[i].dirty>>1)&1) printf("r1 ");
11160     if((regs[i].dirty>>2)&1) printf("r2 ");
11161     if((regs[i].dirty>>3)&1) printf("r3 ");
11162     if((regs[i].dirty>>4)&1) printf("r4 ");
11163     if((regs[i].dirty>>5)&1) printf("r5 ");
11164     if((regs[i].dirty>>6)&1) printf("r6 ");
11165     if((regs[i].dirty>>7)&1) printf("r7 ");
11166     if((regs[i].dirty>>8)&1) printf("r8 ");
11167     if((regs[i].dirty>>9)&1) printf("r9 ");
11168     if((regs[i].dirty>>10)&1) printf("r10 ");
11169     if((regs[i].dirty>>12)&1) printf("r12 ");
11170     #endif
11171     printf("\n");
11172     if(regs[i].isconst) {
11173       printf("constants: ");
11174       #if defined(__i386__) || defined(__x86_64__)
11175       if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
11176       if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
11177       if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
11178       if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
11179       if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
11180       if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
11181       if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
11182       #endif
11183       #ifdef __arm__
11184       if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
11185       if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
11186       if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
11187       if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
11188       if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
11189       if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
11190       if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
11191       if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
11192       if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
11193       if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
11194       if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
11195       if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
11196       #endif
11197       printf("\n");
11198     }
11199 #ifndef FORCE32
11200     printf(" 32:");
11201     for(r=0;r<=CCREG;r++) {
11202       if((regs[i].is32>>r)&1) {
11203         if(r==CCREG) printf(" CC");
11204         else if(r==HIREG) printf(" HI");
11205         else if(r==LOREG) printf(" LO");
11206         else printf(" r%d",r);
11207       }
11208     }
11209     printf("\n");
11210 #endif
11211     /*printf(" p32:");
11212     for(r=0;r<=CCREG;r++) {
11213       if((p32[i]>>r)&1) {
11214         if(r==CCREG) printf(" CC");
11215         else if(r==HIREG) printf(" HI");
11216         else if(r==LOREG) printf(" LO");
11217         else printf(" r%d",r);
11218       }
11219     }
11220     if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
11221     else printf("\n");*/
11222     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
11223       #if defined(__i386__) || defined(__x86_64__)
11224       printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
11225       if(branch_regs[i].dirty&1) printf("eax ");
11226       if((branch_regs[i].dirty>>1)&1) printf("ecx ");
11227       if((branch_regs[i].dirty>>2)&1) printf("edx ");
11228       if((branch_regs[i].dirty>>3)&1) printf("ebx ");
11229       if((branch_regs[i].dirty>>5)&1) printf("ebp ");
11230       if((branch_regs[i].dirty>>6)&1) printf("esi ");
11231       if((branch_regs[i].dirty>>7)&1) printf("edi ");
11232       #endif
11233       #ifdef __arm__
11234       printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
11235       if(branch_regs[i].dirty&1) printf("r0 ");
11236       if((branch_regs[i].dirty>>1)&1) printf("r1 ");
11237       if((branch_regs[i].dirty>>2)&1) printf("r2 ");
11238       if((branch_regs[i].dirty>>3)&1) printf("r3 ");
11239       if((branch_regs[i].dirty>>4)&1) printf("r4 ");
11240       if((branch_regs[i].dirty>>5)&1) printf("r5 ");
11241       if((branch_regs[i].dirty>>6)&1) printf("r6 ");
11242       if((branch_regs[i].dirty>>7)&1) printf("r7 ");
11243       if((branch_regs[i].dirty>>8)&1) printf("r8 ");
11244       if((branch_regs[i].dirty>>9)&1) printf("r9 ");
11245       if((branch_regs[i].dirty>>10)&1) printf("r10 ");
11246       if((branch_regs[i].dirty>>12)&1) printf("r12 ");
11247       #endif
11248 #ifndef FORCE32
11249       printf(" 32:");
11250       for(r=0;r<=CCREG;r++) {
11251         if((branch_regs[i].is32>>r)&1) {
11252           if(r==CCREG) printf(" CC");
11253           else if(r==HIREG) printf(" HI");
11254           else if(r==LOREG) printf(" LO");
11255           else printf(" r%d",r);
11256         }
11257       }
11258       printf("\n");
11259 #endif
11260     }
11261   }
11262 #endif // DISASM
11263
11264   /* Pass 8 - Assembly */
11265   linkcount=0;stubcount=0;
11266   ds=0;is_delayslot=0;
11267   cop1_usable=0;
11268   uint64_t is32_pre=0;
11269   u_int dirty_pre=0;
11270   u_int beginning=(u_int)out;
11271   if((u_int)addr&1) {
11272     ds=1;
11273     pagespan_ds();
11274   }
11275   u_int instr_addr0_override=0;
11276
11277 #ifdef PCSX
11278   if (start == 0x80030000) {
11279     // nasty hack for fastbios thing
11280     // override block entry to this code
11281     instr_addr0_override=(u_int)out;
11282     emit_movimm(start,0);
11283     // abuse io address var as a flag that we
11284     // have already returned here once
11285     emit_readword((int)&address,1);
11286     emit_writeword(0,(int)&pcaddr);
11287     emit_writeword(0,(int)&address);
11288     emit_cmp(0,1);
11289     emit_jne((int)new_dyna_leave);
11290   }
11291 #endif
11292   for(i=0;i<slen;i++)
11293   {
11294     //if(ds) printf("ds: ");
11295     disassemble_inst(i);
11296     if(ds) {
11297       ds=0; // Skip delay slot
11298       if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
11299       instr_addr[i]=0;
11300     } else {
11301       speculate_register_values(i);
11302       #ifndef DESTRUCTIVE_WRITEBACK
11303       if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11304       {
11305         wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
11306               unneeded_reg[i],unneeded_reg_upper[i]);
11307         wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
11308               unneeded_reg[i],unneeded_reg_upper[i]);
11309       }
11310       if((itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)&&!likely[i]) {
11311         is32_pre=branch_regs[i].is32;
11312         dirty_pre=branch_regs[i].dirty;
11313       }else{
11314         is32_pre=regs[i].is32;
11315         dirty_pre=regs[i].dirty;
11316       }
11317       #endif
11318       // write back
11319       if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11320       {
11321         wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
11322                       unneeded_reg[i],unneeded_reg_upper[i]);
11323         loop_preload(regmap_pre[i],regs[i].regmap_entry);
11324       }
11325       // branch target entry point
11326       instr_addr[i]=(u_int)out;
11327       assem_debug("<->\n");
11328       // load regs
11329       if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
11330         wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
11331       load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
11332       address_generation(i,&regs[i],regs[i].regmap_entry);
11333       load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
11334       if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
11335       {
11336         // Load the delay slot registers if necessary
11337         if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i]&&(rs1[i+1]!=rt1[i]||rt1[i]==0))
11338           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11339         if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i]&&(rs2[i+1]!=rt1[i]||rt1[i]==0))
11340           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11341         if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
11342           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11343       }
11344       else if(i+1<slen)
11345       {
11346         // Preload registers for following instruction
11347         if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
11348           if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
11349             load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11350         if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
11351           if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
11352             load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11353       }
11354       // TODO: if(is_ooo(i)) address_generation(i+1);
11355       if(itype[i]==CJUMP||itype[i]==FJUMP)
11356         load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
11357       if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
11358         load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11359       if(bt[i]) cop1_usable=0;
11360       // assemble
11361       switch(itype[i]) {
11362         case ALU:
11363           alu_assemble(i,&regs[i]);break;
11364         case IMM16:
11365           imm16_assemble(i,&regs[i]);break;
11366         case SHIFT:
11367           shift_assemble(i,&regs[i]);break;
11368         case SHIFTIMM:
11369           shiftimm_assemble(i,&regs[i]);break;
11370         case LOAD:
11371           load_assemble(i,&regs[i]);break;
11372         case LOADLR:
11373           loadlr_assemble(i,&regs[i]);break;
11374         case STORE:
11375           store_assemble(i,&regs[i]);break;
11376         case STORELR:
11377           storelr_assemble(i,&regs[i]);break;
11378         case COP0:
11379           cop0_assemble(i,&regs[i]);break;
11380         case COP1:
11381           cop1_assemble(i,&regs[i]);break;
11382         case C1LS:
11383           c1ls_assemble(i,&regs[i]);break;
11384         case COP2:
11385           cop2_assemble(i,&regs[i]);break;
11386         case C2LS:
11387           c2ls_assemble(i,&regs[i]);break;
11388         case C2OP:
11389           c2op_assemble(i,&regs[i]);break;
11390         case FCONV:
11391           fconv_assemble(i,&regs[i]);break;
11392         case FLOAT:
11393           float_assemble(i,&regs[i]);break;
11394         case FCOMP:
11395           fcomp_assemble(i,&regs[i]);break;
11396         case MULTDIV:
11397           multdiv_assemble(i,&regs[i]);break;
11398         case MOV:
11399           mov_assemble(i,&regs[i]);break;
11400         case SYSCALL:
11401           syscall_assemble(i,&regs[i]);break;
11402         case HLECALL:
11403           hlecall_assemble(i,&regs[i]);break;
11404         case INTCALL:
11405           intcall_assemble(i,&regs[i]);break;
11406         case UJUMP:
11407           ujump_assemble(i,&regs[i]);ds=1;break;
11408         case RJUMP:
11409           rjump_assemble(i,&regs[i]);ds=1;break;
11410         case CJUMP:
11411           cjump_assemble(i,&regs[i]);ds=1;break;
11412         case SJUMP:
11413           sjump_assemble(i,&regs[i]);ds=1;break;
11414         case FJUMP:
11415           fjump_assemble(i,&regs[i]);ds=1;break;
11416         case SPAN:
11417           pagespan_assemble(i,&regs[i]);break;
11418       }
11419       if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
11420         literal_pool(1024);
11421       else
11422         literal_pool_jumpover(256);
11423     }
11424   }
11425   //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
11426   // If the block did not end with an unconditional branch,
11427   // add a jump to the next instruction.
11428   if(i>1) {
11429     if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
11430       assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11431       assert(i==slen);
11432       if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
11433         store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11434         if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11435           emit_loadreg(CCREG,HOST_CCREG);
11436         emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
11437       }
11438       else if(!likely[i-2])
11439       {
11440         store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
11441         assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
11442       }
11443       else
11444       {
11445         store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
11446         assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
11447       }
11448       add_to_linker((int)out,start+i*4,0);
11449       emit_jmp(0);
11450     }
11451   }
11452   else
11453   {
11454     assert(i>0);
11455     assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11456     store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11457     if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11458       emit_loadreg(CCREG,HOST_CCREG);
11459     emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
11460     add_to_linker((int)out,start+i*4,0);
11461     emit_jmp(0);
11462   }
11463
11464   // TODO: delay slot stubs?
11465   // Stubs
11466   for(i=0;i<stubcount;i++)
11467   {
11468     switch(stubs[i][0])
11469     {
11470       case LOADB_STUB:
11471       case LOADH_STUB:
11472       case LOADW_STUB:
11473       case LOADD_STUB:
11474       case LOADBU_STUB:
11475       case LOADHU_STUB:
11476         do_readstub(i);break;
11477       case STOREB_STUB:
11478       case STOREH_STUB:
11479       case STOREW_STUB:
11480       case STORED_STUB:
11481         do_writestub(i);break;
11482       case CC_STUB:
11483         do_ccstub(i);break;
11484       case INVCODE_STUB:
11485         do_invstub(i);break;
11486       case FP_STUB:
11487         do_cop1stub(i);break;
11488       case STORELR_STUB:
11489         do_unalignedwritestub(i);break;
11490     }
11491   }
11492
11493   if (instr_addr0_override)
11494     instr_addr[0] = instr_addr0_override;
11495
11496   /* Pass 9 - Linker */
11497   for(i=0;i<linkcount;i++)
11498   {
11499     assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
11500     literal_pool(64);
11501     if(!link_addr[i][2])
11502     {
11503       void *stub=out;
11504       void *addr=check_addr(link_addr[i][1]);
11505       emit_extjump(link_addr[i][0],link_addr[i][1]);
11506       if(addr) {
11507         set_jump_target(link_addr[i][0],(int)addr);
11508         add_link(link_addr[i][1],stub);
11509       }
11510       else set_jump_target(link_addr[i][0],(int)stub);
11511     }
11512     else
11513     {
11514       // Internal branch
11515       int target=(link_addr[i][1]-start)>>2;
11516       assert(target>=0&&target<slen);
11517       assert(instr_addr[target]);
11518       //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11519       //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
11520       //#else
11521       set_jump_target(link_addr[i][0],instr_addr[target]);
11522       //#endif
11523     }
11524   }
11525   // External Branch Targets (jump_in)
11526   if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
11527   for(i=0;i<slen;i++)
11528   {
11529     if(bt[i]||i==0)
11530     {
11531       if(instr_addr[i]) // TODO - delay slots (=null)
11532       {
11533         u_int vaddr=start+i*4;
11534         u_int page=get_page(vaddr);
11535         u_int vpage=get_vpage(vaddr);
11536         literal_pool(256);
11537         //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
11538 #ifndef FORCE32
11539         if(!requires_32bit[i])
11540 #else
11541         if(1)
11542 #endif
11543         {
11544           assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11545           assem_debug("jump_in: %x\n",start+i*4);
11546           ll_add(jump_dirty+vpage,vaddr,(void *)out);
11547           int entry_point=do_dirty_stub(i);
11548           ll_add(jump_in+page,vaddr,(void *)entry_point);
11549           // If there was an existing entry in the hash table,
11550           // replace it with the new address.
11551           // Don't add new entries.  We'll insert the
11552           // ones that actually get used in check_addr().
11553           int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
11554           if(ht_bin[0]==vaddr) {
11555             ht_bin[1]=entry_point;
11556           }
11557           if(ht_bin[2]==vaddr) {
11558             ht_bin[3]=entry_point;
11559           }
11560         }
11561         else
11562         {
11563           u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
11564           assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11565           assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
11566           //int entry_point=(int)out;
11567           ////assem_debug("entry_point: %x\n",entry_point);
11568           //load_regs_entry(i);
11569           //if(entry_point==(int)out)
11570           //  entry_point=instr_addr[i];
11571           //else
11572           //  emit_jmp(instr_addr[i]);
11573           //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11574           ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
11575           int entry_point=do_dirty_stub(i);
11576           ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11577         }
11578       }
11579     }
11580   }
11581   // Write out the literal pool if necessary
11582   literal_pool(0);
11583   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11584   // Align code
11585   if(((u_int)out)&7) emit_addnop(13);
11586   #endif
11587   assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
11588   //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
11589   memcpy(copy,source,slen*4);
11590   copy+=slen*4;
11591
11592   #ifdef __arm__
11593   __clear_cache((void *)beginning,out);
11594   #endif
11595
11596   // If we're within 256K of the end of the buffer,
11597   // start over from the beginning. (Is 256K enough?)
11598   if((u_int)out>(u_int)BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
11599
11600   // Trap writes to any of the pages we compiled
11601   for(i=start>>12;i<=(start+slen*4)>>12;i++) {
11602     invalid_code[i]=0;
11603 #ifndef DISABLE_TLB
11604     memory_map[i]|=0x40000000;
11605     if((signed int)start>=(signed int)0xC0000000) {
11606       assert(using_tlb);
11607       j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
11608       invalid_code[j]=0;
11609       memory_map[j]|=0x40000000;
11610       //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
11611     }
11612 #endif
11613   }
11614   inv_code_start=inv_code_end=~0;
11615 #ifdef PCSX
11616   // for PCSX we need to mark all mirrors too
11617   if(get_page(start)<(RAM_SIZE>>12))
11618     for(i=start>>12;i<=(start+slen*4)>>12;i++)
11619       invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]=
11620       invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]=
11621       invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0;
11622 #endif
11623
11624   /* Pass 10 - Free memory by expiring oldest blocks */
11625
11626   int end=((((int)out-(int)BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
11627   while(expirep!=end)
11628   {
11629     int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
11630     int base=(int)BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
11631     inv_debug("EXP: Phase %d\n",expirep);
11632     switch((expirep>>11)&3)
11633     {
11634       case 0:
11635         // Clear jump_in and jump_dirty
11636         ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
11637         ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
11638         ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
11639         ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
11640         break;
11641       case 1:
11642         // Clear pointers
11643         ll_kill_pointers(jump_out[expirep&2047],base,shift);
11644         ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
11645         break;
11646       case 2:
11647         // Clear hash table
11648         for(i=0;i<32;i++) {
11649           int *ht_bin=hash_table[((expirep&2047)<<5)+i];
11650           if((ht_bin[3]>>shift)==(base>>shift) ||
11651              ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11652             inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
11653             ht_bin[2]=ht_bin[3]=-1;
11654           }
11655           if((ht_bin[1]>>shift)==(base>>shift) ||
11656              ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11657             inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
11658             ht_bin[0]=ht_bin[2];
11659             ht_bin[1]=ht_bin[3];
11660             ht_bin[2]=ht_bin[3]=-1;
11661           }
11662         }
11663         break;
11664       case 3:
11665         // Clear jump_out
11666         #ifdef __arm__
11667         if((expirep&2047)==0)
11668           do_clear_cache();
11669         #endif
11670         ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
11671         ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
11672         break;
11673     }
11674     expirep=(expirep+1)&65535;
11675   }
11676   return 0;
11677 }
11678
11679 // vim:shiftwidth=2:expandtab