libpcsxcore/new_dynarec/pcsxmem.c

   1 /*
   2  * (C) Gražvydas "notaz" Ignotas, 2010-2011
   3  *
   4  * This work is licensed under the terms of GNU GPL version 2 or later.
   5  * See the COPYING file in the top-level directory.
   6  */
   7
   8 #include <stdio.h>
   9 #include <sys/mman.h>
  10 #include "../psxhw.h"
  11 #include "../cdrom.h"
  12 #include "../mdec.h"
  13 #include "../gpu.h"
  14 #include "emu_if.h"
  15 #include "pcsxmem.h"
  16
  17 //#define memprintf printf
  18 #define memprintf(...)
  19
  20 static u32 *mem_readtab;
  21 static u32 *mem_writetab;
  22 static u32 mem_iortab[(1+2+4) * 0x1000 / 4];
  23 static u32 mem_iowtab[(1+2+4) * 0x1000 / 4];
  24 static u32 mem_ffwtab[(1+2+4) * 0x1000 / 4];
  25 //static u32 mem_unmrtab[(1+2+4) * 0x1000 / 4];
  26 static u32 mem_unmwtab[(1+2+4) * 0x1000 / 4];
  27
  28 static void map_item(u32 *out, const void *h, u32 flag)
  29 {
  30         u32 hv = (u32)h;
  31         if (hv & 1)
  32                 fprintf(stderr, "%p has LSB set\n", h);
  33         *out = (hv >> 1) | (flag << 31);
  34 }
  35
  36 // size must be power of 2, at least 4k
  37 #define map_l1_mem(tab, i, addr, size, base) \
  38         map_item(&tab[((addr)>>12) + i], (u8 *)(base) - (u32)(addr) - ((i << 12) & ~(size - 1)), 0)
  39
  40 #define IOMEM32(a) (((a) & 0xfff) / 4)
  41 #define IOMEM16(a) (0x1000/4 + (((a) & 0xfff) / 2))
  42 #define IOMEM8(a)  (0x1000/4 + 0x1000/2 + ((a) & 0xfff))
  43
  44 u8 zero_mem[0x1000];
  45
  46 u32 read_mem_dummy()
  47 {
  48         return 0;
  49 }
  50
  51 static void write_mem_dummy(u32 data)
  52 {
  53         memprintf("unmapped w %08x, %08x @%08x %u\n", address, data, psxRegs.pc, psxRegs.cycle);
  54 }
  55
  56 /* IO handlers */
  57 static u32 io_read_sio16()
  58 {
  59         return sioRead8() | (sioRead8() << 8);
  60 }
  61
  62 static u32 io_read_sio32()
  63 {
  64         return sioRead8() | (sioRead8() << 8) | (sioRead8() << 16) | (sioRead8() << 24);
  65 }
  66
  67 static void io_write_sio16(u32 value)
  68 {
  69         sioWrite8((unsigned char)value);
  70         sioWrite8((unsigned char)(value>>8));
  71 }
  72
  73 static void io_write_sio32(u32 value)
  74 {
  75         sioWrite8((unsigned char)value);
  76         sioWrite8((unsigned char)(value >>  8));
  77         sioWrite8((unsigned char)(value >> 16));
  78         sioWrite8((unsigned char)(value >> 24));
  79 }
  80
  81 #ifndef DRC_DBG
  82
  83 static void map_rcnt_rcount0(u32 mode)
  84 {
  85         if (mode & 0x100) { // pixel clock
  86                 map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m1, 1);
  87                 map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m1, 1);
  88         }
  89         else {
  90                 map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m0, 1);
  91                 map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m0, 1);
  92         }
  93 }
  94
  95 static void map_rcnt_rcount1(u32 mode)
  96 {
  97         if (mode & 0x100) { // hcnt
  98                 map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m1, 1);
  99                 map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m1, 1);
 100         }
 101         else {
 102                 map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m0, 1);
 103                 map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m0, 1);
 104         }
 105 }
 106
 107 static void map_rcnt_rcount2(u32 mode)
 108 {
 109         if (mode & 0x01) { // gate
 110                 map_item(&mem_iortab[IOMEM32(0x1120)], &psxH[0x1000], 0);
 111                 map_item(&mem_iortab[IOMEM16(0x1120)], &psxH[0x1000], 0);
 112         }
 113         else if (mode & 0x200) { // clk/8
 114                 map_item(&mem_iortab[IOMEM32(0x1120)], rcnt2_read_count_m1, 1);
 115                 map_item(&mem_iortab[IOMEM16(0x1120)], rcnt2_read_count_m1, 1);
 116         }
 117         else {
 118                 map_item(&mem_iortab[IOMEM32(0x1120)], rcnt2_read_count_m0, 1);
 119                 map_item(&mem_iortab[IOMEM16(0x1120)], rcnt2_read_count_m0, 1);
 120         }
 121 }
 122
 123 #else
 124 #define map_rcnt_rcount0(mode)
 125 #define map_rcnt_rcount1(mode)
 126 #define map_rcnt_rcount2(mode)
 127 #endif
 128
 129 #define make_rcnt_funcs(i) \
 130 static u32 io_rcnt_read_count##i()  { return psxRcntRcount(i); } \
 131 static u32 io_rcnt_read_mode##i()   { return psxRcntRmode(i); } \
 132 static u32 io_rcnt_read_target##i() { return psxRcntRtarget(i); } \
 133 static void io_rcnt_write_count##i(u32 val)  { psxRcntWcount(i, val & 0xffff); } \
 134 static void io_rcnt_write_mode##i(u32 val)   { psxRcntWmode(i, val); map_rcnt_rcount##i(val); } \
 135 static void io_rcnt_write_target##i(u32 val) { psxRcntWtarget(i, val & 0xffff); }
 136
 137 make_rcnt_funcs(0)
 138 make_rcnt_funcs(1)
 139 make_rcnt_funcs(2)
 140
 141 static void io_write_ireg16(u32 value)
 142 {
 143         if (Config.Sio) psxHu16ref(0x1070) |= 0x80;
 144         if (Config.SpuIrq) psxHu16ref(0x1070) |= 0x200;
 145         psxHu16ref(0x1070) &= psxHu16(0x1074) & value;
 146 }
 147
 148 static void io_write_imask16(u32 value)
 149 {
 150         psxHu16ref(0x1074) = value;
 151         if (psxHu16ref(0x1070) & value)
 152                 new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
 153 }
 154
 155 static void io_write_ireg32(u32 value)
 156 {
 157         if (Config.Sio) psxHu32ref(0x1070) |= 0x80;
 158         if (Config.SpuIrq) psxHu32ref(0x1070) |= 0x200;
 159         psxHu32ref(0x1070) &= psxHu32(0x1074) & value;
 160 }
 161
 162 static void io_write_imask32(u32 value)
 163 {
 164         psxHu32ref(0x1074) = value;
 165         if (psxHu32ref(0x1070) & value)
 166                 new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
 167 }
 168
 169 static void io_write_dma_icr32(u32 value)
 170 {
 171         u32 tmp = value & 0x00ff803f;
 172         tmp |= (SWAPu32(HW_DMA_ICR) & ~value) & 0x7f000000;
 173         if ((tmp & HW_DMA_ICR_GLOBAL_ENABLE && tmp & 0x7f000000)
 174             || tmp & HW_DMA_ICR_BUS_ERROR) {
 175                 if (!(SWAPu32(HW_DMA_ICR) & HW_DMA_ICR_IRQ_SENT))
 176                         psxHu32ref(0x1070) |= SWAP32(8);
 177                 tmp |= HW_DMA_ICR_IRQ_SENT;
 178         }
 179         HW_DMA_ICR = SWAPu32(tmp);
 180 }
 181
 182 #define make_dma_func(n) \
 183 static void io_write_chcr##n(u32 value) \
 184 { \
 185         HW_DMA##n##_CHCR = value; \
 186         if (value & 0x01000000 && HW_DMA_PCR & (8 << (n * 4))) { \
 187                 psxDma##n(HW_DMA##n##_MADR, HW_DMA##n##_BCR, value); \
 188         } \
 189 }
 190
 191 make_dma_func(0)
 192 make_dma_func(1)
 193 make_dma_func(2)
 194 make_dma_func(3)
 195 make_dma_func(4)
 196 make_dma_func(6)
 197
 198 static void io_spu_write16(u32 value)
 199 {
 200         // meh
 201         SPU_writeRegister(address, value);
 202 }
 203
 204 static void io_spu_write32(u32 value)
 205 {
 206         SPUwriteRegister wfunc = SPU_writeRegister;
 207         u32 a = address;
 208
 209         wfunc(a, value & 0xffff);
 210         wfunc(a + 2, value >> 16);
 211 }
 212
 213 static u32 io_gpu_read_status(void)
 214 {
 215         u32 v;
 216
 217         // meh2, syncing for img bit, might want to avoid it..
 218         gpuSyncPluginSR();
 219         v = HW_GPU_STATUS;
 220
 221         // XXX: because of large timeslices can't use hSyncCount, using rough
 222         // approximization instead. Perhaps better use hcounter code here or something.
 223         if (hSyncCount < 240 && (HW_GPU_STATUS & PSXGPU_ILACE_BITS) != PSXGPU_ILACE_BITS)
 224                 v |= PSXGPU_LCF & (psxRegs.cycle << 20);
 225         return v;
 226 }
 227
 228 static void io_gpu_write_status(u32 value)
 229 {
 230         GPU_writeStatus(value);
 231         gpuSyncPluginSR();
 232 }
 233
 234 static void map_ram_write(void)
 235 {
 236         int i;
 237
 238         for (i = 0; i < (0x800000 >> 12); i++) {
 239                 map_l1_mem(mem_writetab, i, 0x80000000, 0x200000, psxM);
 240                 map_l1_mem(mem_writetab, i, 0x00000000, 0x200000, psxM);
 241                 map_l1_mem(mem_writetab, i, 0xa0000000, 0x200000, psxM);
 242         }
 243 }
 244
 245 static void unmap_ram_write(void)
 246 {
 247         int i;
 248
 249         for (i = 0; i < (0x800000 >> 12); i++) {
 250                 map_item(&mem_writetab[0x80000|i], mem_unmwtab, 1);
 251                 map_item(&mem_writetab[0x00000|i], mem_unmwtab, 1);
 252                 map_item(&mem_writetab[0xa0000|i], mem_unmwtab, 1);
 253         }
 254 }
 255
 256 static void write_biu(u32 value)
 257 {
 258         memprintf("write_biu %08x, %08x @%08x %u\n", address, value, psxRegs.pc, psxRegs.cycle);
 259
 260         if (address != 0xfffe0130)
 261                 return;
 262
 263         switch (value) {
 264         case 0x800: case 0x804:
 265                 unmap_ram_write();
 266                 break;
 267         case 0: case 0x1e988:
 268                 map_ram_write();
 269                 break;
 270         default:
 271                 printf("write_biu: unexpected val: %08x\n", value);
 272                 break;
 273         }
 274 }
 275
 276 void new_dyna_pcsx_mem_load_state(void)
 277 {
 278         map_rcnt_rcount0(rcnts[0].mode);
 279         map_rcnt_rcount1(rcnts[1].mode);
 280         map_rcnt_rcount2(rcnts[2].mode);
 281 }
 282
 283 int pcsxmem_is_handler_dynamic(u_int addr)
 284 {
 285         if ((addr & 0xfffff000) != 0x1f801000)
 286                 return 0;
 287
 288         addr &= 0xffff;
 289         return addr == 0x1100 || addr == 0x1110 || addr == 0x1120;
 290 }
 291
 292 void new_dyna_pcsx_mem_init(void)
 293 {
 294         int i;
 295
 296         // have to map these further to keep tcache close to .text
 297         mem_readtab = mmap((void *)0x08000000, 0x200000 * 4, PROT_READ | PROT_WRITE,
 298                 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
 299         if (mem_readtab == MAP_FAILED) {
 300                 fprintf(stderr, "failed to map mem tables\n");
 301                 exit(1);
 302         }
 303         mem_writetab = mem_readtab + 0x100000;
 304
 305         // 1st level lookup:
 306         //   0: direct mem
 307         //   1: use 2nd lookup
 308         // 2nd level lookup:
 309         //   0: direct mem variable
 310         //   1: memhandler
 311
 312         // default/unmapped memhandlers
 313         for (i = 0; i < 0x100000; i++) {
 314                 //map_item(&mem_readtab[i], mem_unmrtab, 1);
 315                 map_l1_mem(mem_readtab, i, 0, 0x1000, zero_mem);
 316                 map_item(&mem_writetab[i], mem_unmwtab, 1);
 317         }
 318
 319         // RAM and it's mirrors
 320         for (i = 0; i < (0x800000 >> 12); i++) {
 321                 map_l1_mem(mem_readtab,  i, 0x80000000, 0x200000, psxM);
 322                 map_l1_mem(mem_readtab,  i, 0x00000000, 0x200000, psxM);
 323                 map_l1_mem(mem_readtab,  i, 0xa0000000, 0x200000, psxM);
 324         }
 325         map_ram_write();
 326
 327         // BIOS and it's mirrors
 328         for (i = 0; i < (0x80000 >> 12); i++) {
 329                 map_l1_mem(mem_readtab, i, 0x1fc00000, 0x80000, psxR);
 330                 map_l1_mem(mem_readtab, i, 0xbfc00000, 0x80000, psxR);
 331         }
 332
 333         // scratchpad
 334         map_l1_mem(mem_readtab, 0, 0x1f800000, 0x1000, psxH);
 335         map_l1_mem(mem_writetab, 0, 0x1f800000, 0x1000, psxH);
 336
 337         // I/O
 338         map_item(&mem_readtab[0x1f801000 >> 12], mem_iortab, 1);
 339         map_item(&mem_writetab[0x1f801000 >> 12], mem_iowtab, 1);
 340
 341         // L2
 342         // unmapped tables
 343         for (i = 0; i < (1+2+4) * 0x1000 / 4; i++)
 344                 map_item(&mem_unmwtab[i], write_mem_dummy, 1);
 345
 346         // fill IO tables
 347         for (i = 0; i < 0x1000/4; i++) {
 348                 map_item(&mem_iortab[i], &psxH[0x1000], 0);
 349                 map_item(&mem_iowtab[i], &psxH[0x1000], 0);
 350         }
 351         for (; i < 0x1000/4 + 0x1000/2; i++) {
 352                 map_item(&mem_iortab[i], &psxH[0x1000], 0);
 353                 map_item(&mem_iowtab[i], &psxH[0x1000], 0);
 354         }
 355         for (; i < 0x1000/4 + 0x1000/2 + 0x1000; i++) {
 356                 map_item(&mem_iortab[i], &psxH[0x1000], 0);
 357                 map_item(&mem_iowtab[i], &psxH[0x1000], 0);
 358         }
 359
 360         map_item(&mem_iortab[IOMEM32(0x1040)], io_read_sio32, 1);
 361         map_item(&mem_iortab[IOMEM32(0x1100)], io_rcnt_read_count0, 1);
 362         map_item(&mem_iortab[IOMEM32(0x1104)], io_rcnt_read_mode0, 1);
 363         map_item(&mem_iortab[IOMEM32(0x1108)], io_rcnt_read_target0, 1);
 364         map_item(&mem_iortab[IOMEM32(0x1110)], io_rcnt_read_count1, 1);
 365         map_item(&mem_iortab[IOMEM32(0x1114)], io_rcnt_read_mode1, 1);
 366         map_item(&mem_iortab[IOMEM32(0x1118)], io_rcnt_read_target1, 1);
 367         map_item(&mem_iortab[IOMEM32(0x1120)], io_rcnt_read_count2, 1);
 368         map_item(&mem_iortab[IOMEM32(0x1124)], io_rcnt_read_mode2, 1);
 369         map_item(&mem_iortab[IOMEM32(0x1128)], io_rcnt_read_target2, 1);
 370 //      map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1);
 371         map_item(&mem_iortab[IOMEM32(0x1814)], io_gpu_read_status, 1);
 372         map_item(&mem_iortab[IOMEM32(0x1820)], mdecRead0, 1);
 373         map_item(&mem_iortab[IOMEM32(0x1824)], mdecRead1, 1);
 374
 375         map_item(&mem_iortab[IOMEM16(0x1040)], io_read_sio16, 1);
 376         map_item(&mem_iortab[IOMEM16(0x1044)], sioReadStat16, 1);
 377         map_item(&mem_iortab[IOMEM16(0x1048)], sioReadMode16, 1);
 378         map_item(&mem_iortab[IOMEM16(0x104a)], sioReadCtrl16, 1);
 379         map_item(&mem_iortab[IOMEM16(0x104e)], sioReadBaud16, 1);
 380         map_item(&mem_iortab[IOMEM16(0x1100)], io_rcnt_read_count0, 1);
 381         map_item(&mem_iortab[IOMEM16(0x1104)], io_rcnt_read_mode0, 1);
 382         map_item(&mem_iortab[IOMEM16(0x1108)], io_rcnt_read_target0, 1);
 383         map_item(&mem_iortab[IOMEM16(0x1110)], io_rcnt_read_count1, 1);
 384         map_item(&mem_iortab[IOMEM16(0x1114)], io_rcnt_read_mode1, 1);
 385         map_item(&mem_iortab[IOMEM16(0x1118)], io_rcnt_read_target1, 1);
 386         map_item(&mem_iortab[IOMEM16(0x1120)], io_rcnt_read_count2, 1);
 387         map_item(&mem_iortab[IOMEM16(0x1124)], io_rcnt_read_mode2, 1);
 388         map_item(&mem_iortab[IOMEM16(0x1128)], io_rcnt_read_target2, 1);
 389
 390         map_item(&mem_iortab[IOMEM8(0x1040)], sioRead8, 1);
 391         map_item(&mem_iortab[IOMEM8(0x1800)], cdrRead0, 1);
 392         map_item(&mem_iortab[IOMEM8(0x1801)], cdrRead1, 1);
 393         map_item(&mem_iortab[IOMEM8(0x1802)], cdrRead2, 1);
 394         map_item(&mem_iortab[IOMEM8(0x1803)], cdrRead3, 1);
 395
 396         // write(u32 data)
 397         map_item(&mem_iowtab[IOMEM32(0x1040)], io_write_sio32, 1);
 398         map_item(&mem_iowtab[IOMEM32(0x1070)], io_write_ireg32, 1);
 399         map_item(&mem_iowtab[IOMEM32(0x1074)], io_write_imask32, 1);
 400         map_item(&mem_iowtab[IOMEM32(0x1088)], io_write_chcr0, 1);
 401         map_item(&mem_iowtab[IOMEM32(0x1098)], io_write_chcr1, 1);
 402         map_item(&mem_iowtab[IOMEM32(0x10a8)], io_write_chcr2, 1);
 403         map_item(&mem_iowtab[IOMEM32(0x10b8)], io_write_chcr3, 1);
 404         map_item(&mem_iowtab[IOMEM32(0x10c8)], io_write_chcr4, 1);
 405         map_item(&mem_iowtab[IOMEM32(0x10e8)], io_write_chcr6, 1);
 406         map_item(&mem_iowtab[IOMEM32(0x10f4)], io_write_dma_icr32, 1);
 407         map_item(&mem_iowtab[IOMEM32(0x1100)], io_rcnt_write_count0, 1);
 408         map_item(&mem_iowtab[IOMEM32(0x1104)], io_rcnt_write_mode0, 1);
 409         map_item(&mem_iowtab[IOMEM32(0x1108)], io_rcnt_write_target0, 1);
 410         map_item(&mem_iowtab[IOMEM32(0x1110)], io_rcnt_write_count1, 1);
 411         map_item(&mem_iowtab[IOMEM32(0x1114)], io_rcnt_write_mode1, 1);
 412         map_item(&mem_iowtab[IOMEM32(0x1118)], io_rcnt_write_target1, 1);
 413         map_item(&mem_iowtab[IOMEM32(0x1120)], io_rcnt_write_count2, 1);
 414         map_item(&mem_iowtab[IOMEM32(0x1124)], io_rcnt_write_mode2, 1);
 415         map_item(&mem_iowtab[IOMEM32(0x1128)], io_rcnt_write_target2, 1);
 416 //      map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1);
 417         map_item(&mem_iowtab[IOMEM32(0x1814)], io_gpu_write_status, 1);
 418         map_item(&mem_iowtab[IOMEM32(0x1820)], mdecWrite0, 1);
 419         map_item(&mem_iowtab[IOMEM32(0x1824)], mdecWrite1, 1);
 420
 421         map_item(&mem_iowtab[IOMEM16(0x1040)], io_write_sio16, 1);
 422         map_item(&mem_iowtab[IOMEM16(0x1044)], sioWriteStat16, 1);
 423         map_item(&mem_iowtab[IOMEM16(0x1048)], sioWriteMode16, 1);
 424         map_item(&mem_iowtab[IOMEM16(0x104a)], sioWriteCtrl16, 1);
 425         map_item(&mem_iowtab[IOMEM16(0x104e)], sioWriteBaud16, 1);
 426         map_item(&mem_iowtab[IOMEM16(0x1070)], io_write_ireg16, 1);
 427         map_item(&mem_iowtab[IOMEM16(0x1074)], io_write_imask16, 1);
 428         map_item(&mem_iowtab[IOMEM16(0x1100)], io_rcnt_write_count0, 1);
 429         map_item(&mem_iowtab[IOMEM16(0x1104)], io_rcnt_write_mode0, 1);
 430         map_item(&mem_iowtab[IOMEM16(0x1108)], io_rcnt_write_target0, 1);
 431         map_item(&mem_iowtab[IOMEM16(0x1110)], io_rcnt_write_count1, 1);
 432         map_item(&mem_iowtab[IOMEM16(0x1114)], io_rcnt_write_mode1, 1);
 433         map_item(&mem_iowtab[IOMEM16(0x1118)], io_rcnt_write_target1, 1);
 434         map_item(&mem_iowtab[IOMEM16(0x1120)], io_rcnt_write_count2, 1);
 435         map_item(&mem_iowtab[IOMEM16(0x1124)], io_rcnt_write_mode2, 1);
 436         map_item(&mem_iowtab[IOMEM16(0x1128)], io_rcnt_write_target2, 1);
 437
 438         map_item(&mem_iowtab[IOMEM8(0x1040)], sioWrite8, 1);
 439         map_item(&mem_iowtab[IOMEM8(0x1800)], cdrWrite0, 1);
 440         map_item(&mem_iowtab[IOMEM8(0x1801)], cdrWrite1, 1);
 441         map_item(&mem_iowtab[IOMEM8(0x1802)], cdrWrite2, 1);
 442         map_item(&mem_iowtab[IOMEM8(0x1803)], cdrWrite3, 1);
 443
 444         for (i = 0x1c00; i < 0x1e00; i += 2) {
 445                 map_item(&mem_iowtab[IOMEM16(i)], io_spu_write16, 1);
 446                 map_item(&mem_iowtab[IOMEM32(i)], io_spu_write32, 1);
 447         }
 448
 449         // misc
 450         map_item(&mem_writetab[0xfffe0130 >> 12], mem_ffwtab, 1);
 451         for (i = 0; i < 0x1000/4 + 0x1000/2 + 0x1000; i++)
 452                 map_item(&mem_ffwtab[i], write_biu, 1);
 453
 454         mem_rtab = mem_readtab;
 455         mem_wtab = mem_writetab;
 456
 457         new_dyna_pcsx_mem_load_state();
 458 }
 459
 460 void new_dyna_pcsx_mem_reset(void)
 461 {
 462         int i;
 463
 464         // plugins might change so update the pointers
 465         map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1);
 466
 467         for (i = 0x1c00; i < 0x1e00; i += 2)
 468                 map_item(&mem_iortab[IOMEM16(i)], SPU_readRegister, 1);
 469
 470         map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1);
 471 }