libpcsxcore/new_dynarec/pcsxmem.c

   1 /*
   2  * (C) Gražvydas "notaz" Ignotas, 2010-2011
   3  *
   4  * This work is licensed under the terms of GNU GPL version 2 or later.
   5  * See the COPYING file in the top-level directory.
   6  */
   7
   8 #include <stdio.h>
   9 #include <sys/mman.h>
  10 #include "../psxhw.h"
  11 #include "../cdrom.h"
  12 #include "../mdec.h"
  13 #include "emu_if.h"
  14 #include "pcsxmem.h"
  15
  16 //#define memprintf printf
  17 #define memprintf(...)
  18
  19 static u8 unmapped_mem[0x1000];
  20 int pcsx_ram_is_ro;
  21
  22 static void read_mem8()
  23 {
  24         memprintf("ari64_read_mem8  %08x @%08x %u\n", address, psxRegs.pc, psxRegs.cycle);
  25         readmem_word = psxMemRead8(address) & 0xff;
  26 }
  27
  28 static void read_mem16()
  29 {
  30         memprintf("ari64_read_mem16 %08x @%08x %u\n", address, psxRegs.pc, psxRegs.cycle);
  31         readmem_word = psxMemRead16(address) & 0xffff;
  32 }
  33
  34 static void read_mem32()
  35 {
  36         memprintf("ari64_read_mem32 %08x @%08x %u\n", address, psxRegs.pc, psxRegs.cycle);
  37         readmem_word = psxMemRead32(address);
  38 }
  39
  40 static void write_mem8()
  41 {
  42         memprintf("ari64_write_mem8  %08x,       %02x @%08x %u\n", address, byte, psxRegs.pc, psxRegs.cycle);
  43         psxMemWrite8(address, byte);
  44 }
  45
  46 static void write_mem16()
  47 {
  48         memprintf("ari64_write_mem16 %08x,     %04x @%08x %u\n", address, hword, psxRegs.pc, psxRegs.cycle);
  49         psxMemWrite16(address, hword);
  50 }
  51
  52 static void write_mem32()
  53 {
  54         memprintf("ari64_write_mem32 %08x, %08x @%08x %u\n", address, word, psxRegs.pc, psxRegs.cycle);
  55         psxMemWrite32(address, word);
  56 }
  57
  58 static void read_mem_dummy()
  59 {
  60         readmem_word = 0;
  61 }
  62
  63 static void write_mem_dummy()
  64 {
  65 }
  66
  67 extern void ari_read_ram8();
  68 extern void ari_read_ram16();
  69 extern void ari_read_ram32();
  70 extern void ari_read_ram_mirror8();
  71 extern void ari_read_ram_mirror16();
  72 extern void ari_read_ram_mirror32();
  73 extern void ari_write_ram8();
  74 extern void ari_write_ram16();
  75 extern void ari_write_ram32();
  76 extern void ari_write_ram_mirror8();
  77 extern void ari_write_ram_mirror16();
  78 extern void ari_write_ram_mirror32();
  79 extern void ari_write_ram_mirror_ro32();
  80 extern void ari_read_bios8();
  81 extern void ari_read_bios16();
  82 extern void ari_read_bios32();
  83 extern void ari_read_io8();
  84 extern void ari_read_io16();
  85 extern void ari_read_io32();
  86 extern void ari_write_io8();
  87 extern void ari_write_io16();
  88 extern void ari_write_io32();
  89
  90 void (*readmem[0x10000])();
  91 void (*readmemb[0x10000])();
  92 void (*readmemh[0x10000])();
  93 void (*writemem[0x10000])();
  94 void (*writememb[0x10000])();
  95 void (*writememh[0x10000])();
  96
  97 static void write_biu()
  98 {
  99         memprintf("write_biu %08x, %08x @%08x %u\n", address, word, psxRegs.pc, psxRegs.cycle);
 100
 101         if (address != 0xfffe0130)
 102                 return;
 103
 104         switch (word) {
 105         case 0x800: case 0x804:
 106                 pcsx_ram_is_ro = 1;
 107                 break;
 108         case 0: case 0x1e988:
 109                 pcsx_ram_is_ro = 0;
 110                 break;
 111         default:
 112                 memprintf("write_biu: unexpected val: %08x\n", word);
 113                 break;
 114         }
 115 }
 116
 117 /* IO handlers */
 118 static u32 io_read_sio16()
 119 {
 120         return sioRead8() | (sioRead8() << 8);
 121 }
 122
 123 static u32 io_read_sio32()
 124 {
 125         return sioRead8() | (sioRead8() << 8) | (sioRead8() << 16) | (sioRead8() << 24);
 126 }
 127
 128 static void io_write_sio16(u32 value)
 129 {
 130         sioWrite8((unsigned char)value);
 131         sioWrite8((unsigned char)(value>>8));
 132 }
 133
 134 static void io_write_sio32(u32 value)
 135 {
 136         sioWrite8((unsigned char)value);
 137         sioWrite8((unsigned char)((value&0xff) >>  8));
 138         sioWrite8((unsigned char)((value&0xff) >> 16));
 139         sioWrite8((unsigned char)((value&0xff) >> 24));
 140 }
 141
 142 #define make_rcnt_funcs(i) \
 143 static u32 io_rcnt_read_count##i()  { return psxRcntRcount(i); } \
 144 static u32 io_rcnt_read_mode##i()   { return psxRcntRmode(i); } \
 145 static u32 io_rcnt_read_target##i() { return psxRcntRtarget(i); } \
 146 static void io_rcnt_write_count##i(u32 val)  { psxRcntWcount(i, val & 0xffff); } \
 147 static void io_rcnt_write_mode##i(u32 val)   { psxRcntWmode(i, val); } \
 148 static void io_rcnt_write_target##i(u32 val) { psxRcntWtarget(i, val & 0xffff); }
 149
 150 make_rcnt_funcs(0)
 151 make_rcnt_funcs(1)
 152 make_rcnt_funcs(2)
 153
 154 static void io_write_ireg16(u32 value)
 155 {
 156         if (Config.Sio) psxHu16ref(0x1070) |= 0x80;
 157         if (Config.SpuIrq) psxHu16ref(0x1070) |= 0x200;
 158         psxHu16ref(0x1070) &= psxHu16(0x1074) & value;
 159 }
 160
 161 static void io_write_imask16(u32 value)
 162 {
 163         psxHu16ref(0x1074) = value;
 164         if (psxHu16ref(0x1070) & value)
 165                 new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
 166 }
 167
 168 static void io_write_ireg32(u32 value)
 169 {
 170         if (Config.Sio) psxHu32ref(0x1070) |= 0x80;
 171         if (Config.SpuIrq) psxHu32ref(0x1070) |= 0x200;
 172         psxHu32ref(0x1070) &= psxHu32(0x1074) & value;
 173 }
 174
 175 static void io_write_imask32(u32 value)
 176 {
 177         psxHu32ref(0x1074) = value;
 178         if (psxHu32ref(0x1070) & value)
 179                 new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
 180 }
 181
 182 static void io_write_dma_icr32(u32 value)
 183 {
 184         u32 tmp = value & 0x00ff803f;
 185         tmp |= (SWAPu32(HW_DMA_ICR) & ~value) & 0x7f000000;
 186         if ((tmp & HW_DMA_ICR_GLOBAL_ENABLE && tmp & 0x7f000000)
 187             || tmp & HW_DMA_ICR_BUS_ERROR) {
 188                 if (!(SWAPu32(HW_DMA_ICR) & HW_DMA_ICR_IRQ_SENT))
 189                         psxHu32ref(0x1070) |= SWAP32(8);
 190                 tmp |= HW_DMA_ICR_IRQ_SENT;
 191         }
 192         HW_DMA_ICR = SWAPu32(tmp);
 193 }
 194
 195 #define make_dma_func(n) \
 196 static void io_write_chcr##n(u32 value) \
 197 { \
 198         HW_DMA##n##_CHCR = value; \
 199         if (value & 0x01000000 && HW_DMA_PCR & (8 << (n * 4))) { \
 200                 psxDma##n(HW_DMA##n##_MADR, HW_DMA##n##_BCR, value); \
 201         } \
 202 }
 203
 204 make_dma_func(0)
 205 make_dma_func(1)
 206 make_dma_func(2)
 207 make_dma_func(3)
 208 make_dma_func(4)
 209 make_dma_func(6)
 210
 211 /* IO tables for 1000-1880 */
 212 #define IOADR8(a)  ((a) & 0xfff)
 213 #define IOADR16(a) (((a) & 0xfff) >> 1)
 214 #define IOADR32(a) (((a) & 0xfff) >> 2)
 215
 216 static const void *io_read8 [0x880] = {
 217         [IOADR8(0x1040)] = sioRead8,
 218         [IOADR8(0x1800)] = cdrRead0,
 219         [IOADR8(0x1801)] = cdrRead1,
 220         [IOADR8(0x1802)] = cdrRead2,
 221         [IOADR8(0x1803)] = cdrRead3,
 222 };
 223 static const void *io_read16[0x880/2] = {
 224         [IOADR16(0x1040)] = io_read_sio16,
 225         [IOADR16(0x1044)] = sioReadStat16,
 226         [IOADR16(0x1048)] = sioReadMode16,
 227         [IOADR16(0x104a)] = sioReadCtrl16,
 228         [IOADR16(0x104e)] = sioReadBaud16,
 229         [IOADR16(0x1100)] = io_rcnt_read_count0,
 230         [IOADR16(0x1104)] = io_rcnt_read_mode0,
 231         [IOADR16(0x1108)] = io_rcnt_read_target0,
 232         [IOADR16(0x1110)] = io_rcnt_read_count1,
 233         [IOADR16(0x1114)] = io_rcnt_read_mode1,
 234         [IOADR16(0x1118)] = io_rcnt_read_target1,
 235         [IOADR16(0x1120)] = io_rcnt_read_count2,
 236         [IOADR16(0x1124)] = io_rcnt_read_mode2,
 237         [IOADR16(0x1128)] = io_rcnt_read_target2,
 238 };
 239 static const void *io_read32[0x880/4] = {
 240         [IOADR32(0x1040)] = io_read_sio32,
 241         [IOADR32(0x1100)] = io_rcnt_read_count0,
 242         [IOADR32(0x1104)] = io_rcnt_read_mode0,
 243         [IOADR32(0x1108)] = io_rcnt_read_target0,
 244         [IOADR32(0x1110)] = io_rcnt_read_count1,
 245         [IOADR32(0x1114)] = io_rcnt_read_mode1,
 246         [IOADR32(0x1118)] = io_rcnt_read_target1,
 247         [IOADR32(0x1120)] = io_rcnt_read_count2,
 248         [IOADR32(0x1124)] = io_rcnt_read_mode2,
 249         [IOADR32(0x1128)] = io_rcnt_read_target2,
 250 //      [IOADR32(0x1810)] = GPU_readData,
 251 //      [IOADR32(0x1814)] = GPU_readStatus,
 252         [IOADR32(0x1820)] = mdecRead0,
 253         [IOADR32(0x1824)] = mdecRead1,
 254 };
 255 // write(u32 val)
 256 static const void *io_write8 [0x880] = {
 257         [IOADR8(0x1040)] = sioWrite8,
 258         [IOADR8(0x1800)] = cdrWrite0,
 259         [IOADR8(0x1801)] = cdrWrite1,
 260         [IOADR8(0x1802)] = cdrWrite2,
 261         [IOADR8(0x1803)] = cdrWrite3,
 262 };
 263 static const void *io_write16[0x880/2] = {
 264         [IOADR16(0x1040)] = io_write_sio16,
 265         [IOADR16(0x1044)] = sioWriteStat16,
 266         [IOADR16(0x1048)] = sioWriteMode16,
 267         [IOADR16(0x104a)] = sioWriteCtrl16,
 268         [IOADR16(0x104e)] = sioWriteBaud16,
 269         [IOADR16(0x1070)] = io_write_ireg16,
 270         [IOADR16(0x1074)] = io_write_imask16,
 271         [IOADR16(0x1100)] = io_rcnt_write_count0,
 272         [IOADR16(0x1104)] = io_rcnt_write_mode0,
 273         [IOADR16(0x1108)] = io_rcnt_write_target0,
 274         [IOADR16(0x1110)] = io_rcnt_write_count1,
 275         [IOADR16(0x1114)] = io_rcnt_write_mode1,
 276         [IOADR16(0x1118)] = io_rcnt_write_target1,
 277         [IOADR16(0x1120)] = io_rcnt_write_count2,
 278         [IOADR16(0x1124)] = io_rcnt_write_mode2,
 279         [IOADR16(0x1128)] = io_rcnt_write_target2,
 280 };
 281 static const void *io_write32[0x880/4] = {
 282         [IOADR32(0x1040)] = io_write_sio32,
 283         [IOADR32(0x1070)] = io_write_ireg32,
 284         [IOADR32(0x1074)] = io_write_imask32,
 285         [IOADR32(0x1088)] = io_write_chcr0,
 286         [IOADR32(0x1098)] = io_write_chcr1,
 287         [IOADR32(0x10a8)] = io_write_chcr2,
 288         [IOADR32(0x10b8)] = io_write_chcr3,
 289         [IOADR32(0x10c8)] = io_write_chcr4,
 290         [IOADR32(0x10e8)] = io_write_chcr6,
 291         [IOADR32(0x10f4)] = io_write_dma_icr32,
 292         [IOADR32(0x1100)] = io_rcnt_write_count0,
 293         [IOADR32(0x1104)] = io_rcnt_write_mode0,
 294         [IOADR32(0x1108)] = io_rcnt_write_target0,
 295         [IOADR32(0x1110)] = io_rcnt_write_count1,
 296         [IOADR32(0x1114)] = io_rcnt_write_mode1,
 297         [IOADR32(0x1118)] = io_rcnt_write_target1,
 298         [IOADR32(0x1120)] = io_rcnt_write_count2,
 299         [IOADR32(0x1124)] = io_rcnt_write_mode2,
 300         [IOADR32(0x1128)] = io_rcnt_write_target2,
 301 //      [IOADR32(0x1810)] = GPU_writeData,
 302 //      [IOADR32(0x1814)] = GPU_writeStatus,
 303         [IOADR32(0x1820)] = mdecWrite0,
 304         [IOADR32(0x1824)] = mdecWrite1,
 305 };
 306
 307 // this has to be in .bss to link into dynarec_local
 308 struct {
 309         void *tab_read8;
 310         void *tab_read16;
 311         void *tab_read32;
 312         void *tab_write8;
 313         void *tab_write16;
 314         void *tab_write32;
 315         void *spu_readf;
 316         void *spu_writef;
 317 } nd_pcsx_io;
 318
 319 static u32 *mem_readtab;
 320 static u32 *mem_writetab;
 321 static u32 mem_iortab[(1+2+4) * 0x1000 / 4];
 322 static u32 mem_iowtab[(1+2+4) * 0x1000 / 4];
 323 //static u32 mem_unmrtab[(1+2+4) * 0x1000 / 4];
 324 static u32 mem_unmwtab[(1+2+4) * 0x1000 / 4];
 325
 326 static void map_item(u32 *out, const void *h, u32 flag)
 327 {
 328         u32 hv = (u32)h;
 329         if (hv & 1)
 330                 fprintf(stderr, "%p has LSB set\n", h);
 331         *out = (hv >> 1) | (flag << 31);
 332 }
 333
 334 // size must be power of 2, at least 4k
 335 #define map_l1_mem(tab, i, addr, size, base) \
 336         map_item(&tab[((addr)>>12) + i], (u8 *)(base) - (u32)(addr) - ((i << 12) & ~(size - 1)), 0)
 337
 338 #define IOMEM32(a) (((a) & 0xfff) / 4)
 339 #define IOMEM16(a) (0x1000/4 + (((a) & 0xfff) / 2))
 340 #define IOMEM8(a)  (0x1000/4 + 0x1000/2 + ((a) & 0xfff))
 341
 342 void new_dyna_pcsx_mem_init(void)
 343 {
 344         int i;
 345 #if 1
 346         // have to map these further to keep tcache close to .text
 347         mem_readtab = mmap((void *)0x08000000, 0x200000 * 4, PROT_READ | PROT_WRITE,
 348                 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
 349         if (mem_readtab == MAP_FAILED) {
 350                 fprintf(stderr, "failed to map mem tables\n");
 351                 exit(1);
 352         }
 353         mem_writetab = mem_readtab + 0x100000;
 354
 355         // 1st level lookup:
 356         //   0: direct mem
 357         //   1: use 2nd lookup
 358         // 2nd level lookup:
 359         //   0: direct mem variable
 360         //   1: memhandler
 361
 362         // default/unmapped memhandlers
 363         for (i = 0; i < 0x100000; i++) {
 364                 //map_item(&mem_readtab[i], mem_unmrtab, 1);
 365                 map_l1_mem(mem_readtab, i, 0, 0x1000, unmapped_mem);
 366                 map_item(&mem_writetab[i], mem_unmwtab, 1);
 367         }
 368
 369         // RAM and it's mirrors
 370         for (i = 0; i < (0x800000 >> 12); i++) {
 371                 map_l1_mem(mem_readtab,  i, 0x80000000, 0x200000, psxM);
 372                 map_l1_mem(mem_writetab, i, 0x80000000, 0x200000, psxM);
 373                 map_l1_mem(mem_readtab,  i, 0x00000000, 0x200000, psxM);
 374                 map_l1_mem(mem_writetab, i, 0x00000000, 0x200000, psxM);
 375                 map_l1_mem(mem_readtab,  i, 0xa0000000, 0x200000, psxM);
 376                 map_l1_mem(mem_writetab, i, 0xa0000000, 0x200000, psxM);
 377         }
 378
 379         // stupid BIOS RAM check
 380         // TODO
 381
 382         // BIOS and it's mirrors
 383         for (i = 0; i < (0x80000 >> 12); i++) {
 384                 map_l1_mem(mem_readtab, i, 0x1fc00000, 0x80000, psxR);
 385                 map_l1_mem(mem_readtab, i, 0xbfc00000, 0x80000, psxR);
 386         }
 387
 388         // scratchpad
 389         map_l1_mem(mem_readtab, 0, 0x1f800000, 0x1000, psxH);
 390         map_l1_mem(mem_writetab, 0, 0x1f800000, 0x1000, psxH);
 391
 392         // I/O
 393         map_item(&mem_readtab[0x1f801000 >> 12], mem_iortab, 1);
 394         map_item(&mem_writetab[0x1f801000 >> 12], mem_iowtab, 1);
 395
 396         // L2
 397         // unmapped tables
 398         for (i = 0; i < 0x1000; i++)
 399                 map_item(&mem_unmwtab[i], write_mem_dummy, 1);
 400
 401         // fill IO tables
 402         for (i = 0; i < 0x1000/4; i++) {
 403                 map_item(&mem_iortab[i], &psxH[0x1000], 0);
 404                 map_item(&mem_iowtab[i], &psxH[0x1000], 0);
 405         }
 406         for (; i < 0x1000/4 + 0x1000/2; i++) {
 407                 map_item(&mem_iortab[i], &psxH[0x1000], 0);
 408                 map_item(&mem_iowtab[i], &psxH[0x1000], 0);
 409         }
 410         for (; i < 0x1000/4 + 0x1000/2 + 0x1000; i++) {
 411                 map_item(&mem_iortab[i], &psxH[0x1000], 0);
 412                 map_item(&mem_iowtab[i], &psxH[0x1000], 0);
 413         }
 414
 415         map_item(&mem_iortab[IOMEM32(0x1040)], io_read_sio32, 1);
 416         map_item(&mem_iortab[IOMEM32(0x1100)], io_rcnt_read_count0, 1);
 417         map_item(&mem_iortab[IOMEM32(0x1104)], io_rcnt_read_mode0, 1);
 418         map_item(&mem_iortab[IOMEM32(0x1108)], io_rcnt_read_target0, 1);
 419         map_item(&mem_iortab[IOMEM32(0x1110)], io_rcnt_read_count1, 1);
 420         map_item(&mem_iortab[IOMEM32(0x1114)], io_rcnt_read_mode1, 1);
 421         map_item(&mem_iortab[IOMEM32(0x1118)], io_rcnt_read_target1, 1);
 422         map_item(&mem_iortab[IOMEM32(0x1120)], io_rcnt_read_count2, 1);
 423         map_item(&mem_iortab[IOMEM32(0x1124)], io_rcnt_read_mode2, 1);
 424         map_item(&mem_iortab[IOMEM32(0x1128)], io_rcnt_read_target2, 1);
 425 //      map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1);
 426 //      map_item(&mem_iortab[IOMEM32(0x1814)], GPU_readStatus, 1);
 427         map_item(&mem_iortab[IOMEM32(0x1820)], mdecRead0, 1);
 428         map_item(&mem_iortab[IOMEM32(0x1824)], mdecRead1, 1);
 429
 430         map_item(&mem_iortab[IOMEM16(0x1040)], io_read_sio16, 1);
 431         map_item(&mem_iortab[IOMEM16(0x1044)], sioReadStat16, 1);
 432         map_item(&mem_iortab[IOMEM16(0x1048)], sioReadMode16, 1);
 433         map_item(&mem_iortab[IOMEM16(0x104a)], sioReadCtrl16, 1);
 434         map_item(&mem_iortab[IOMEM16(0x104e)], sioReadBaud16, 1);
 435         map_item(&mem_iortab[IOMEM16(0x1100)], io_rcnt_read_count0, 1);
 436         map_item(&mem_iortab[IOMEM16(0x1104)], io_rcnt_read_mode0, 1);
 437         map_item(&mem_iortab[IOMEM16(0x1108)], io_rcnt_read_target0, 1);
 438         map_item(&mem_iortab[IOMEM16(0x1110)], io_rcnt_read_count1, 1);
 439         map_item(&mem_iortab[IOMEM16(0x1114)], io_rcnt_read_mode1, 1);
 440         map_item(&mem_iortab[IOMEM16(0x1118)], io_rcnt_read_target1, 1);
 441         map_item(&mem_iortab[IOMEM16(0x1120)], io_rcnt_read_count2, 1);
 442         map_item(&mem_iortab[IOMEM16(0x1124)], io_rcnt_read_mode2, 1);
 443         map_item(&mem_iortab[IOMEM16(0x1128)], io_rcnt_read_target2, 1);
 444
 445         map_item(&mem_iortab[IOMEM8(0x1040)], sioRead8, 1);
 446         map_item(&mem_iortab[IOMEM8(0x1800)], cdrRead0, 1);
 447         map_item(&mem_iortab[IOMEM8(0x1801)], cdrRead1, 1);
 448         map_item(&mem_iortab[IOMEM8(0x1802)], cdrRead2, 1);
 449         map_item(&mem_iortab[IOMEM8(0x1803)], cdrRead3, 1);
 450
 451         mem_rtab = mem_readtab;
 452         mem_wtab = mem_writetab;
 453 #endif
 454 ///
 455         // default/unmapped handlers
 456         for (i = 0; i < 0x10000; i++) {
 457                 readmemb[i] = read_mem8;
 458                 readmemh[i] = read_mem16;
 459                 readmem[i] = read_mem32;
 460                 writememb[i] = write_mem8;
 461                 writememh[i] = write_mem16;
 462                 writemem[i] = write_mem32;
 463 #if 1
 464                 readmemb[i] = readmemh[i] = readmem[i] = read_mem_dummy;
 465                 writememb[i] = writememh[i] = writemem[i] = write_mem_dummy;
 466 #endif
 467         }
 468
 469 #if 1
 470         // RAM mirrors
 471         for (i = 0; i < 0x80; i++) {
 472                 readmemb[i] = readmemb[0x8000|i] = readmemb[0xa000|i] = ari_read_ram_mirror8;
 473                 readmemh[i] = readmemh[0x8000|i] = readmemh[0xa000|i] = ari_read_ram_mirror16;
 474                 readmem[i]  = readmem [0x8000|i] = readmem [0xa000|i] = ari_read_ram_mirror32;
 475                 writememb[i] = writememb[0x8000|i] = writememb[0xa000|i] = ari_write_ram_mirror8;
 476                 writememh[i] = writememh[0x8000|i] = writememh[0xa000|i] = ari_write_ram_mirror16;
 477                 writemem[i]  = writemem [0x8000|i] = writemem [0xa000|i] = ari_write_ram_mirror32;
 478         }
 479
 480         // stupid BIOS RAM check
 481         writemem[0] = ari_write_ram_mirror_ro32;
 482         pcsx_ram_is_ro = 0;
 483
 484         // RAM direct
 485         for (i = 0x8000; i < 0x8020; i++) {
 486                 readmemb[i] = ari_read_ram8;
 487                 readmemh[i] = ari_read_ram16;
 488                 readmem[i] = ari_read_ram32;
 489         }
 490
 491         // BIOS and it's mirrors
 492         for (i = 0x1fc0; i < 0x1fc8; i++) {
 493                 readmemb[i] = readmemb[0x8000|i] = readmemb[0xa000|i] = ari_read_bios8;
 494                 readmemh[i] = readmemh[0x8000|i] = readmemh[0xa000|i] = ari_read_bios16;
 495                 readmem[i]  = readmem[0x8000|i]  = readmem[0xa000|i]  = ari_read_bios32;
 496         }
 497
 498         // I/O
 499         readmemb[0x1f80] = ari_read_io8;
 500         readmemh[0x1f80] = ari_read_io16;
 501         readmem[0x1f80]  = ari_read_io32;
 502         writememb[0x1f80] = ari_write_io8;
 503         writememh[0x1f80] = ari_write_io16;
 504         writemem[0x1f80]  = ari_write_io32;
 505
 506         writemem[0xfffe] = write_biu;
 507 #endif
 508
 509         // fill IO tables
 510         nd_pcsx_io.tab_read8 = io_read8;
 511         nd_pcsx_io.tab_read16 = io_read16;
 512         nd_pcsx_io.tab_read32 = io_read32;
 513         nd_pcsx_io.tab_write8 = io_write8;
 514         nd_pcsx_io.tab_write16 = io_write16;
 515         nd_pcsx_io.tab_write32 = io_write32;
 516 }
 517
 518 void new_dyna_pcsx_mem_reset(void)
 519 {
 520         int i;
 521
 522         // plugins might change so update the pointers
 523         map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1);
 524         map_item(&mem_iortab[IOMEM32(0x1814)], GPU_readStatus, 1);
 525
 526         for (i = 0x1c00; i < 0x1e00; i += 2)
 527                 map_item(&mem_iortab[IOMEM16(i)], SPU_readRegister, 1);
 528
 529         nd_pcsx_io.spu_readf = SPU_readRegister;
 530         nd_pcsx_io.spu_writef = SPU_writeRegister;
 531
 532         io_read32[IOADR32(0x1810)] = GPU_readData;
 533         io_read32[IOADR32(0x1814)] = GPU_readStatus;
 534         io_write32[IOADR32(0x1810)] = GPU_writeData;
 535         io_write32[IOADR32(0x1814)] = GPU_writeStatus;
 536 }
 537