libpcsxcore/new_dynarec/pcsxmem.c

   1 /*
   2  * (C) Gražvydas "notaz" Ignotas, 2010-2011
   3  *
   4  * This work is licensed under the terms of GNU GPL version 2 or later.
   5  * See the COPYING file in the top-level directory.
   6  */
   7
   8 #include <stdio.h>
   9 #include <sys/mman.h>
  10 #include "../psxhw.h"
  11 #include "../cdrom.h"
  12 #include "../mdec.h"
  13 #include "../gpu.h"
  14 #include "emu_if.h"
  15 #include "pcsxmem.h"
  16
  17 #ifdef __thumb__
  18 #error the dynarec does not have Thumb support, please remove -mthumb
  19 #endif
  20
  21 //#define memprintf printf
  22 #define memprintf(...)
  23
  24 static u32 *mem_readtab;
  25 static u32 *mem_writetab;
  26 static u32 mem_iortab[(1+2+4) * 0x1000 / 4];
  27 static u32 mem_iowtab[(1+2+4) * 0x1000 / 4];
  28 static u32 mem_ffwtab[(1+2+4) * 0x1000 / 4];
  29 //static u32 mem_unmrtab[(1+2+4) * 0x1000 / 4];
  30 static u32 mem_unmwtab[(1+2+4) * 0x1000 / 4];
  31
  32 static void map_item(u32 *out, const void *h, u32 flag)
  33 {
  34         u32 hv = (u32)h;
  35         if (hv & 1) {
  36                 fprintf(stderr, "FATAL: %p has LSB set\n", h);
  37                 abort();
  38         }
  39         *out = (hv >> 1) | (flag << 31);
  40 }
  41
  42 // size must be power of 2, at least 4k
  43 #define map_l1_mem(tab, i, addr, size, base) \
  44         map_item(&tab[((addr)>>12) + i], (u8 *)(base) - (u32)(addr) - ((i << 12) & ~(size - 1)), 0)
  45
  46 #define IOMEM32(a) (((a) & 0xfff) / 4)
  47 #define IOMEM16(a) (0x1000/4 + (((a) & 0xfff) / 2))
  48 #define IOMEM8(a)  (0x1000/4 + 0x1000/2 + ((a) & 0xfff))
  49
  50 u8 zero_mem[0x1000];
  51
  52 u32 read_mem_dummy()
  53 {
  54         return 0;
  55 }
  56
  57 static void write_mem_dummy(u32 data)
  58 {
  59         memprintf("unmapped w %08x, %08x @%08x %u\n", address, data, psxRegs.pc, psxRegs.cycle);
  60 }
  61
  62 /* IO handlers */
  63 static u32 io_read_sio16()
  64 {
  65         return sioRead8() | (sioRead8() << 8);
  66 }
  67
  68 static u32 io_read_sio32()
  69 {
  70         return sioRead8() | (sioRead8() << 8) | (sioRead8() << 16) | (sioRead8() << 24);
  71 }
  72
  73 static void io_write_sio16(u32 value)
  74 {
  75         sioWrite8((unsigned char)value);
  76         sioWrite8((unsigned char)(value>>8));
  77 }
  78
  79 static void io_write_sio32(u32 value)
  80 {
  81         sioWrite8((unsigned char)value);
  82         sioWrite8((unsigned char)(value >>  8));
  83         sioWrite8((unsigned char)(value >> 16));
  84         sioWrite8((unsigned char)(value >> 24));
  85 }
  86
  87 #ifndef DRC_DBG
  88
  89 static void map_rcnt_rcount0(u32 mode)
  90 {
  91         if (mode & 0x100) { // pixel clock
  92                 map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m1, 1);
  93                 map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m1, 1);
  94         }
  95         else {
  96                 map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m0, 1);
  97                 map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m0, 1);
  98         }
  99 }
 100
 101 static void map_rcnt_rcount1(u32 mode)
 102 {
 103         if (mode & 0x100) { // hcnt
 104                 map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m1, 1);
 105                 map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m1, 1);
 106         }
 107         else {
 108                 map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m0, 1);
 109                 map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m0, 1);
 110         }
 111 }
 112
 113 static void map_rcnt_rcount2(u32 mode)
 114 {
 115         if (mode & 0x01) { // gate
 116                 map_item(&mem_iortab[IOMEM32(0x1120)], &psxH[0x1000], 0);
 117                 map_item(&mem_iortab[IOMEM16(0x1120)], &psxH[0x1000], 0);
 118         }
 119         else if (mode & 0x200) { // clk/8
 120                 map_item(&mem_iortab[IOMEM32(0x1120)], rcnt2_read_count_m1, 1);
 121                 map_item(&mem_iortab[IOMEM16(0x1120)], rcnt2_read_count_m1, 1);
 122         }
 123         else {
 124                 map_item(&mem_iortab[IOMEM32(0x1120)], rcnt2_read_count_m0, 1);
 125                 map_item(&mem_iortab[IOMEM16(0x1120)], rcnt2_read_count_m0, 1);
 126         }
 127 }
 128
 129 #else
 130 #define map_rcnt_rcount0(mode)
 131 #define map_rcnt_rcount1(mode)
 132 #define map_rcnt_rcount2(mode)
 133 #endif
 134
 135 #define make_rcnt_funcs(i) \
 136 static u32 io_rcnt_read_count##i()  { return psxRcntRcount(i); } \
 137 static u32 io_rcnt_read_mode##i()   { return psxRcntRmode(i); } \
 138 static u32 io_rcnt_read_target##i() { return psxRcntRtarget(i); } \
 139 static void io_rcnt_write_count##i(u32 val)  { psxRcntWcount(i, val & 0xffff); } \
 140 static void io_rcnt_write_mode##i(u32 val)   { psxRcntWmode(i, val); map_rcnt_rcount##i(val); } \
 141 static void io_rcnt_write_target##i(u32 val) { psxRcntWtarget(i, val & 0xffff); }
 142
 143 make_rcnt_funcs(0)
 144 make_rcnt_funcs(1)
 145 make_rcnt_funcs(2)
 146
 147 static void io_write_ireg16(u32 value)
 148 {
 149         if (Config.Sio) psxHu16ref(0x1070) |= 0x80;
 150         if (Config.SpuIrq) psxHu16ref(0x1070) |= 0x200;
 151         psxHu16ref(0x1070) &= psxHu16(0x1074) & value;
 152 }
 153
 154 static void io_write_imask16(u32 value)
 155 {
 156         psxHu16ref(0x1074) = value;
 157         if (psxHu16ref(0x1070) & value)
 158                 new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
 159 }
 160
 161 static void io_write_ireg32(u32 value)
 162 {
 163         if (Config.Sio) psxHu32ref(0x1070) |= 0x80;
 164         if (Config.SpuIrq) psxHu32ref(0x1070) |= 0x200;
 165         psxHu32ref(0x1070) &= psxHu32(0x1074) & value;
 166 }
 167
 168 static void io_write_imask32(u32 value)
 169 {
 170         psxHu32ref(0x1074) = value;
 171         if (psxHu32ref(0x1070) & value)
 172                 new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
 173 }
 174
 175 static void io_write_dma_icr32(u32 value)
 176 {
 177         u32 tmp = value & 0x00ff803f;
 178         tmp |= (SWAPu32(HW_DMA_ICR) & ~value) & 0x7f000000;
 179         if ((tmp & HW_DMA_ICR_GLOBAL_ENABLE && tmp & 0x7f000000)
 180             || tmp & HW_DMA_ICR_BUS_ERROR) {
 181                 if (!(SWAPu32(HW_DMA_ICR) & HW_DMA_ICR_IRQ_SENT))
 182                         psxHu32ref(0x1070) |= SWAP32(8);
 183                 tmp |= HW_DMA_ICR_IRQ_SENT;
 184         }
 185         HW_DMA_ICR = SWAPu32(tmp);
 186 }
 187
 188 #define make_dma_func(n) \
 189 static void io_write_chcr##n(u32 value) \
 190 { \
 191         HW_DMA##n##_CHCR = value; \
 192         if (value & 0x01000000 && HW_DMA_PCR & (8 << (n * 4))) { \
 193                 psxDma##n(HW_DMA##n##_MADR, HW_DMA##n##_BCR, value); \
 194         } \
 195 }
 196
 197 make_dma_func(0)
 198 make_dma_func(1)
 199 make_dma_func(2)
 200 make_dma_func(3)
 201 make_dma_func(4)
 202 make_dma_func(6)
 203
 204 static void io_spu_write16(u32 value)
 205 {
 206         // meh
 207         SPU_writeRegister(address, value);
 208 }
 209
 210 static void io_spu_write32(u32 value)
 211 {
 212         SPUwriteRegister wfunc = SPU_writeRegister;
 213         u32 a = address;
 214
 215         wfunc(a, value & 0xffff);
 216         wfunc(a + 2, value >> 16);
 217 }
 218
 219 static u32 io_gpu_read_status(void)
 220 {
 221         u32 v;
 222
 223         // meh2, syncing for img bit, might want to avoid it..
 224         gpuSyncPluginSR();
 225         v = HW_GPU_STATUS;
 226
 227         // XXX: because of large timeslices can't use hSyncCount, using rough
 228         // approximization instead. Perhaps better use hcounter code here or something.
 229         if (hSyncCount < 240 && (HW_GPU_STATUS & PSXGPU_ILACE_BITS) != PSXGPU_ILACE_BITS)
 230                 v |= PSXGPU_LCF & (psxRegs.cycle << 20);
 231         return v;
 232 }
 233
 234 static void io_gpu_write_status(u32 value)
 235 {
 236         GPU_writeStatus(value);
 237         gpuSyncPluginSR();
 238 }
 239
 240 static void map_ram_write(void)
 241 {
 242         int i;
 243
 244         for (i = 0; i < (0x800000 >> 12); i++) {
 245                 map_l1_mem(mem_writetab, i, 0x80000000, 0x200000, psxM);
 246                 map_l1_mem(mem_writetab, i, 0x00000000, 0x200000, psxM);
 247                 map_l1_mem(mem_writetab, i, 0xa0000000, 0x200000, psxM);
 248         }
 249 }
 250
 251 static void unmap_ram_write(void)
 252 {
 253         int i;
 254
 255         for (i = 0; i < (0x800000 >> 12); i++) {
 256                 map_item(&mem_writetab[0x80000|i], mem_unmwtab, 1);
 257                 map_item(&mem_writetab[0x00000|i], mem_unmwtab, 1);
 258                 map_item(&mem_writetab[0xa0000|i], mem_unmwtab, 1);
 259         }
 260 }
 261
 262 static void write_biu(u32 value)
 263 {
 264         memprintf("write_biu %08x, %08x @%08x %u\n", address, value, psxRegs.pc, psxRegs.cycle);
 265
 266         if (address != 0xfffe0130)
 267                 return;
 268
 269         switch (value) {
 270         case 0x800: case 0x804:
 271                 unmap_ram_write();
 272                 break;
 273         case 0: case 0x1e988:
 274                 map_ram_write();
 275                 break;
 276         default:
 277                 printf("write_biu: unexpected val: %08x\n", value);
 278                 break;
 279         }
 280 }
 281
 282 void new_dyna_pcsx_mem_load_state(void)
 283 {
 284         map_rcnt_rcount0(rcnts[0].mode);
 285         map_rcnt_rcount1(rcnts[1].mode);
 286         map_rcnt_rcount2(rcnts[2].mode);
 287 }
 288
 289 int pcsxmem_is_handler_dynamic(u_int addr)
 290 {
 291         if ((addr & 0xfffff000) != 0x1f801000)
 292                 return 0;
 293
 294         addr &= 0xffff;
 295         return addr == 0x1100 || addr == 0x1110 || addr == 0x1120;
 296 }
 297
 298 void new_dyna_pcsx_mem_init(void)
 299 {
 300         int i;
 301
 302         // have to map these further to keep tcache close to .text
 303         mem_readtab = mmap((void *)0x08000000, 0x200000 * 4, PROT_READ | PROT_WRITE,
 304                 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
 305         if (mem_readtab == MAP_FAILED) {
 306                 fprintf(stderr, "failed to map mem tables\n");
 307                 exit(1);
 308         }
 309         mem_writetab = mem_readtab + 0x100000;
 310
 311         // 1st level lookup:
 312         //   0: direct mem
 313         //   1: use 2nd lookup
 314         // 2nd level lookup:
 315         //   0: direct mem variable
 316         //   1: memhandler
 317
 318         // default/unmapped memhandlers
 319         for (i = 0; i < 0x100000; i++) {
 320                 //map_item(&mem_readtab[i], mem_unmrtab, 1);
 321                 map_l1_mem(mem_readtab, i, 0, 0x1000, zero_mem);
 322                 map_item(&mem_writetab[i], mem_unmwtab, 1);
 323         }
 324
 325         // RAM and it's mirrors
 326         for (i = 0; i < (0x800000 >> 12); i++) {
 327                 map_l1_mem(mem_readtab,  i, 0x80000000, 0x200000, psxM);
 328                 map_l1_mem(mem_readtab,  i, 0x00000000, 0x200000, psxM);
 329                 map_l1_mem(mem_readtab,  i, 0xa0000000, 0x200000, psxM);
 330         }
 331         map_ram_write();
 332
 333         // BIOS and it's mirrors
 334         for (i = 0; i < (0x80000 >> 12); i++) {
 335                 map_l1_mem(mem_readtab, i, 0x1fc00000, 0x80000, psxR);
 336                 map_l1_mem(mem_readtab, i, 0xbfc00000, 0x80000, psxR);
 337         }
 338
 339         // scratchpad
 340         map_l1_mem(mem_readtab, 0, 0x1f800000, 0x1000, psxH);
 341         map_l1_mem(mem_writetab, 0, 0x1f800000, 0x1000, psxH);
 342
 343         // I/O
 344         map_item(&mem_readtab[0x1f801000 >> 12], mem_iortab, 1);
 345         map_item(&mem_writetab[0x1f801000 >> 12], mem_iowtab, 1);
 346
 347         // L2
 348         // unmapped tables
 349         for (i = 0; i < (1+2+4) * 0x1000 / 4; i++)
 350                 map_item(&mem_unmwtab[i], write_mem_dummy, 1);
 351
 352         // fill IO tables
 353         for (i = 0; i < 0x1000/4; i++) {
 354                 map_item(&mem_iortab[i], &psxH[0x1000], 0);
 355                 map_item(&mem_iowtab[i], &psxH[0x1000], 0);
 356         }
 357         for (; i < 0x1000/4 + 0x1000/2; i++) {
 358                 map_item(&mem_iortab[i], &psxH[0x1000], 0);
 359                 map_item(&mem_iowtab[i], &psxH[0x1000], 0);
 360         }
 361         for (; i < 0x1000/4 + 0x1000/2 + 0x1000; i++) {
 362                 map_item(&mem_iortab[i], &psxH[0x1000], 0);
 363                 map_item(&mem_iowtab[i], &psxH[0x1000], 0);
 364         }
 365
 366         map_item(&mem_iortab[IOMEM32(0x1040)], io_read_sio32, 1);
 367         map_item(&mem_iortab[IOMEM32(0x1100)], io_rcnt_read_count0, 1);
 368         map_item(&mem_iortab[IOMEM32(0x1104)], io_rcnt_read_mode0, 1);
 369         map_item(&mem_iortab[IOMEM32(0x1108)], io_rcnt_read_target0, 1);
 370         map_item(&mem_iortab[IOMEM32(0x1110)], io_rcnt_read_count1, 1);
 371         map_item(&mem_iortab[IOMEM32(0x1114)], io_rcnt_read_mode1, 1);
 372         map_item(&mem_iortab[IOMEM32(0x1118)], io_rcnt_read_target1, 1);
 373         map_item(&mem_iortab[IOMEM32(0x1120)], io_rcnt_read_count2, 1);
 374         map_item(&mem_iortab[IOMEM32(0x1124)], io_rcnt_read_mode2, 1);
 375         map_item(&mem_iortab[IOMEM32(0x1128)], io_rcnt_read_target2, 1);
 376 //      map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1);
 377         map_item(&mem_iortab[IOMEM32(0x1814)], io_gpu_read_status, 1);
 378         map_item(&mem_iortab[IOMEM32(0x1820)], mdecRead0, 1);
 379         map_item(&mem_iortab[IOMEM32(0x1824)], mdecRead1, 1);
 380
 381         map_item(&mem_iortab[IOMEM16(0x1040)], io_read_sio16, 1);
 382         map_item(&mem_iortab[IOMEM16(0x1044)], sioReadStat16, 1);
 383         map_item(&mem_iortab[IOMEM16(0x1048)], sioReadMode16, 1);
 384         map_item(&mem_iortab[IOMEM16(0x104a)], sioReadCtrl16, 1);
 385         map_item(&mem_iortab[IOMEM16(0x104e)], sioReadBaud16, 1);
 386         map_item(&mem_iortab[IOMEM16(0x1100)], io_rcnt_read_count0, 1);
 387         map_item(&mem_iortab[IOMEM16(0x1104)], io_rcnt_read_mode0, 1);
 388         map_item(&mem_iortab[IOMEM16(0x1108)], io_rcnt_read_target0, 1);
 389         map_item(&mem_iortab[IOMEM16(0x1110)], io_rcnt_read_count1, 1);
 390         map_item(&mem_iortab[IOMEM16(0x1114)], io_rcnt_read_mode1, 1);
 391         map_item(&mem_iortab[IOMEM16(0x1118)], io_rcnt_read_target1, 1);
 392         map_item(&mem_iortab[IOMEM16(0x1120)], io_rcnt_read_count2, 1);
 393         map_item(&mem_iortab[IOMEM16(0x1124)], io_rcnt_read_mode2, 1);
 394         map_item(&mem_iortab[IOMEM16(0x1128)], io_rcnt_read_target2, 1);
 395
 396         map_item(&mem_iortab[IOMEM8(0x1040)], sioRead8, 1);
 397         map_item(&mem_iortab[IOMEM8(0x1800)], cdrRead0, 1);
 398         map_item(&mem_iortab[IOMEM8(0x1801)], cdrRead1, 1);
 399         map_item(&mem_iortab[IOMEM8(0x1802)], cdrRead2, 1);
 400         map_item(&mem_iortab[IOMEM8(0x1803)], cdrRead3, 1);
 401
 402         // write(u32 data)
 403         map_item(&mem_iowtab[IOMEM32(0x1040)], io_write_sio32, 1);
 404         map_item(&mem_iowtab[IOMEM32(0x1070)], io_write_ireg32, 1);
 405         map_item(&mem_iowtab[IOMEM32(0x1074)], io_write_imask32, 1);
 406         map_item(&mem_iowtab[IOMEM32(0x1088)], io_write_chcr0, 1);
 407         map_item(&mem_iowtab[IOMEM32(0x1098)], io_write_chcr1, 1);
 408         map_item(&mem_iowtab[IOMEM32(0x10a8)], io_write_chcr2, 1);
 409         map_item(&mem_iowtab[IOMEM32(0x10b8)], io_write_chcr3, 1);
 410         map_item(&mem_iowtab[IOMEM32(0x10c8)], io_write_chcr4, 1);
 411         map_item(&mem_iowtab[IOMEM32(0x10e8)], io_write_chcr6, 1);
 412         map_item(&mem_iowtab[IOMEM32(0x10f4)], io_write_dma_icr32, 1);
 413         map_item(&mem_iowtab[IOMEM32(0x1100)], io_rcnt_write_count0, 1);
 414         map_item(&mem_iowtab[IOMEM32(0x1104)], io_rcnt_write_mode0, 1);
 415         map_item(&mem_iowtab[IOMEM32(0x1108)], io_rcnt_write_target0, 1);
 416         map_item(&mem_iowtab[IOMEM32(0x1110)], io_rcnt_write_count1, 1);
 417         map_item(&mem_iowtab[IOMEM32(0x1114)], io_rcnt_write_mode1, 1);
 418         map_item(&mem_iowtab[IOMEM32(0x1118)], io_rcnt_write_target1, 1);
 419         map_item(&mem_iowtab[IOMEM32(0x1120)], io_rcnt_write_count2, 1);
 420         map_item(&mem_iowtab[IOMEM32(0x1124)], io_rcnt_write_mode2, 1);
 421         map_item(&mem_iowtab[IOMEM32(0x1128)], io_rcnt_write_target2, 1);
 422 //      map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1);
 423         map_item(&mem_iowtab[IOMEM32(0x1814)], io_gpu_write_status, 1);
 424         map_item(&mem_iowtab[IOMEM32(0x1820)], mdecWrite0, 1);
 425         map_item(&mem_iowtab[IOMEM32(0x1824)], mdecWrite1, 1);
 426
 427         map_item(&mem_iowtab[IOMEM16(0x1040)], io_write_sio16, 1);
 428         map_item(&mem_iowtab[IOMEM16(0x1044)], sioWriteStat16, 1);
 429         map_item(&mem_iowtab[IOMEM16(0x1048)], sioWriteMode16, 1);
 430         map_item(&mem_iowtab[IOMEM16(0x104a)], sioWriteCtrl16, 1);
 431         map_item(&mem_iowtab[IOMEM16(0x104e)], sioWriteBaud16, 1);
 432         map_item(&mem_iowtab[IOMEM16(0x1070)], io_write_ireg16, 1);
 433         map_item(&mem_iowtab[IOMEM16(0x1074)], io_write_imask16, 1);
 434         map_item(&mem_iowtab[IOMEM16(0x1100)], io_rcnt_write_count0, 1);
 435         map_item(&mem_iowtab[IOMEM16(0x1104)], io_rcnt_write_mode0, 1);
 436         map_item(&mem_iowtab[IOMEM16(0x1108)], io_rcnt_write_target0, 1);
 437         map_item(&mem_iowtab[IOMEM16(0x1110)], io_rcnt_write_count1, 1);
 438         map_item(&mem_iowtab[IOMEM16(0x1114)], io_rcnt_write_mode1, 1);
 439         map_item(&mem_iowtab[IOMEM16(0x1118)], io_rcnt_write_target1, 1);
 440         map_item(&mem_iowtab[IOMEM16(0x1120)], io_rcnt_write_count2, 1);
 441         map_item(&mem_iowtab[IOMEM16(0x1124)], io_rcnt_write_mode2, 1);
 442         map_item(&mem_iowtab[IOMEM16(0x1128)], io_rcnt_write_target2, 1);
 443
 444         map_item(&mem_iowtab[IOMEM8(0x1040)], sioWrite8, 1);
 445         map_item(&mem_iowtab[IOMEM8(0x1800)], cdrWrite0, 1);
 446         map_item(&mem_iowtab[IOMEM8(0x1801)], cdrWrite1, 1);
 447         map_item(&mem_iowtab[IOMEM8(0x1802)], cdrWrite2, 1);
 448         map_item(&mem_iowtab[IOMEM8(0x1803)], cdrWrite3, 1);
 449
 450         for (i = 0x1c00; i < 0x1e00; i += 2) {
 451                 map_item(&mem_iowtab[IOMEM16(i)], io_spu_write16, 1);
 452                 map_item(&mem_iowtab[IOMEM32(i)], io_spu_write32, 1);
 453         }
 454
 455         // misc
 456         map_item(&mem_writetab[0xfffe0130 >> 12], mem_ffwtab, 1);
 457         for (i = 0; i < 0x1000/4 + 0x1000/2 + 0x1000; i++)
 458                 map_item(&mem_ffwtab[i], write_biu, 1);
 459
 460         mem_rtab = mem_readtab;
 461         mem_wtab = mem_writetab;
 462
 463         new_dyna_pcsx_mem_load_state();
 464 }
 465
 466 void new_dyna_pcsx_mem_reset(void)
 467 {
 468         int i;
 469
 470         // plugins might change so update the pointers
 471         map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1);
 472
 473         for (i = 0x1c00; i < 0x1e00; i += 2)
 474                 map_item(&mem_iortab[IOMEM16(i)], SPU_readRegister, 1);
 475
 476         map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1);
 477 }