libpcsxcore/psxcounters.c

   1 /***************************************************************************
   2  *   Copyright (C) 2010 by Blade_Arma                                      *
   3  *                                                                         *
   4  *   This program is free software; you can redistribute it and/or modify  *
   5  *   it under the terms of the GNU General Public License as published by  *
   6  *   the Free Software Foundation; either version 2 of the License, or     *
   7  *   (at your option) any later version.                                   *
   8  *                                                                         *
   9  *   This program is distributed in the hope that it will be useful,       *
  10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  12  *   GNU General Public License for more details.                          *
  13  *                                                                         *
  14  *   You should have received a copy of the GNU General Public License     *
  15  *   along with this program; if not, write to the                         *
  16  *   Free Software Foundation, Inc.,                                       *
  17  *   51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA.           *
  18  ***************************************************************************/
  19
  20 /*
  21  * Internal PSX counters.
  22  */
  23
  24 #include "psxcounters.h"
  25 #include "gpu.h"
  26 #include "debug.h"
  27
  28 /******************************************************************************/
  29
  30 enum
  31 {
  32     Rc0Gate           = 0x0001, // 0    not implemented
  33     Rc1Gate           = 0x0001, // 0    not implemented
  34     Rc2Disable        = 0x0001, // 0    partially implemented
  35     RcUnknown1        = 0x0002, // 1    ?
  36     RcUnknown2        = 0x0004, // 2    ?
  37     RcCountToTarget   = 0x0008, // 3
  38     RcIrqOnTarget     = 0x0010, // 4
  39     RcIrqOnOverflow   = 0x0020, // 5
  40     RcIrqRegenerate   = 0x0040, // 6
  41     RcUnknown7        = 0x0080, // 7    ?
  42     Rc0PixelClock     = 0x0100, // 8    fake implementation
  43     Rc1HSyncClock     = 0x0100, // 8
  44     Rc2Unknown8       = 0x0100, // 8    ?
  45     Rc0Unknown9       = 0x0200, // 9    ?
  46     Rc1Unknown9       = 0x0200, // 9    ?
  47     Rc2OneEighthClock = 0x0200, // 9
  48     RcUnknown10       = 0x0400, // 10   ?
  49     RcCountEqTarget   = 0x0800, // 11
  50     RcOverflow        = 0x1000, // 12
  51     RcUnknown13       = 0x2000, // 13   ? (always zero)
  52     RcUnknown14       = 0x4000, // 14   ? (always zero)
  53     RcUnknown15       = 0x8000, // 15   ? (always zero)
  54 };
  55
  56 #define CounterQuantity           ( 4 )
  57 //static const u32 CounterQuantity  = 4;
  58
  59 static const u32 CountToOverflow  = 0;
  60 static const u32 CountToTarget    = 1;
  61
  62 static const u32 FrameRate[]      = { 60, 50 };
  63 static const u32 VBlankStart[]    = { 240, 256 };
  64 static const u32 HSyncTotal[]     = { 263, 313 };
  65 static const u32 SpuUpdInterval[] = { 32, 32 };
  66
  67 #define VERBOSE_LEVEL 0
  68 static const s32 VerboseLevel     = VERBOSE_LEVEL;
  69
  70 /******************************************************************************/
  71
  72 Rcnt rcnts[ CounterQuantity ];
  73
  74 u32 hSyncCount = 0;
  75 u32 frame_counter = 0;
  76 static u32 spuSyncCount = 0;
  77 static u32 hsync_steps = 0;
  78 static u32 base_cycle = 0;
  79
  80 u32 psxNextCounter = 0, psxNextsCounter = 0;
  81
  82 /******************************************************************************/
  83
  84 static inline
  85 void setIrq( u32 irq )
  86 {
  87     psxHu32ref(0x1070) |= SWAPu32(irq);
  88 }
  89
  90 static
  91 void verboseLog( u32 level, const char *str, ... )
  92 {
  93 #if VERBOSE_LEVEL > 0
  94     if( level <= VerboseLevel )
  95     {
  96         va_list va;
  97         char buf[ 4096 ];
  98
  99         va_start( va, str );
 100         vsprintf( buf, str, va );
 101         va_end( va );
 102
 103         printf( "%s", buf );
 104         fflush( stdout );
 105     }
 106 #endif
 107 }
 108
 109 /******************************************************************************/
 110
 111 static inline
 112 void _psxRcntWcount( u32 index, u32 value )
 113 {
 114     if( value > 0xffff )
 115     {
 116         verboseLog( 1, "[RCNT %i] wcount > 0xffff: %x\n", index, value );
 117         value &= 0xffff;
 118     }
 119
 120     rcnts[index].cycleStart  = psxRegs.cycle;
 121     rcnts[index].cycleStart -= value * rcnts[index].rate;
 122
 123     // TODO: <=.
 124     if( value < rcnts[index].target )
 125     {
 126         rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
 127         rcnts[index].counterState = CountToTarget;
 128     }
 129     else
 130     {
 131         rcnts[index].cycle = 0xffff * rcnts[index].rate;
 132         rcnts[index].counterState = CountToOverflow;
 133     }
 134 }
 135
 136 static inline
 137 u32 _psxRcntRcount( u32 index )
 138 {
 139     u32 count;
 140
 141     count  = psxRegs.cycle;
 142     count -= rcnts[index].cycleStart;
 143     if (rcnts[index].rate > 1)
 144         count /= rcnts[index].rate;
 145
 146     if( count > 0xffff )
 147     {
 148         verboseLog( 1, "[RCNT %i] rcount > 0xffff: %x\n", index, count );
 149         count &= 0xffff;
 150     }
 151
 152     return count;
 153 }
 154
 155 /******************************************************************************/
 156
 157 static
 158 void psxRcntSet()
 159 {
 160     s32 countToUpdate;
 161     u32 i;
 162
 163     psxNextsCounter = psxRegs.cycle;
 164     psxNextCounter  = 0x7fffffff;
 165
 166     for( i = 0; i < CounterQuantity; ++i )
 167     {
 168         countToUpdate = rcnts[i].cycle - (psxNextsCounter - rcnts[i].cycleStart);
 169
 170         if( countToUpdate < 0 )
 171         {
 172             psxNextCounter = 0;
 173             break;
 174         }
 175
 176         if( countToUpdate < (s32)psxNextCounter )
 177         {
 178             psxNextCounter = countToUpdate;
 179         }
 180     }
 181
 182     psxRegs.interrupt |= (1 << PSXINT_RCNT);
 183     new_dyna_set_event(PSXINT_RCNT, psxNextCounter);
 184 }
 185
 186 /******************************************************************************/
 187
 188 static
 189 void psxRcntReset( u32 index )
 190 {
 191     u32 count;
 192
 193     rcnts[index].mode |= RcUnknown10;
 194
 195     if( rcnts[index].counterState == CountToTarget )
 196     {
 197         if( rcnts[index].mode & RcCountToTarget )
 198         {
 199             count  = psxRegs.cycle;
 200             count -= rcnts[index].cycleStart;
 201             if (rcnts[index].rate > 1)
 202                 count /= rcnts[index].rate;
 203             count -= rcnts[index].target;
 204         }
 205         else
 206         {
 207             count = _psxRcntRcount( index );
 208         }
 209
 210         _psxRcntWcount( index, count );
 211
 212         if( rcnts[index].mode & RcIrqOnTarget )
 213         {
 214             if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
 215             {
 216                 verboseLog( 3, "[RCNT %i] irq: %x\n", index, count );
 217                 setIrq( rcnts[index].irq );
 218                 rcnts[index].irqState = 1;
 219             }
 220         }
 221
 222         rcnts[index].mode |= RcCountEqTarget;
 223
 224         psxRcntSet();
 225
 226         if( count < 0xffff ) // special case, overflow too?
 227             return;
 228     }
 229
 230     if( rcnts[index].counterState == CountToOverflow )
 231     {
 232         count  = psxRegs.cycle;
 233         count -= rcnts[index].cycleStart;
 234         if (rcnts[index].rate > 1)
 235             count /= rcnts[index].rate;
 236         count -= 0xffff;
 237
 238         _psxRcntWcount( index, count );
 239
 240         if( rcnts[index].mode & RcIrqOnOverflow )
 241         {
 242             if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
 243             {
 244                 verboseLog( 3, "[RCNT %i] irq: %x\n", index, count );
 245                 setIrq( rcnts[index].irq );
 246                 rcnts[index].irqState = 1;
 247             }
 248         }
 249
 250         rcnts[index].mode |= RcOverflow;
 251     }
 252
 253     psxRcntSet();
 254 }
 255
 256 void psxRcntUpdate()
 257 {
 258     u32 cycle;
 259
 260     cycle = psxRegs.cycle;
 261
 262     // rcnt 0.
 263     if( cycle - rcnts[0].cycleStart >= rcnts[0].cycle )
 264     {
 265         psxRcntReset( 0 );
 266     }
 267
 268     // rcnt 1.
 269     if( cycle - rcnts[1].cycleStart >= rcnts[1].cycle )
 270     {
 271         psxRcntReset( 1 );
 272     }
 273
 274     // rcnt 2.
 275     if( cycle - rcnts[2].cycleStart >= rcnts[2].cycle )
 276     {
 277         psxRcntReset( 2 );
 278     }
 279
 280     // rcnt base.
 281     if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle )
 282     {
 283         u32 leftover_cycles = cycle - rcnts[3].cycleStart - rcnts[3].cycle;
 284         u32 next_vsync, next_lace;
 285
 286         spuSyncCount += hsync_steps;
 287         hSyncCount += hsync_steps;
 288
 289         // Update spu.
 290         if( spuSyncCount >= SpuUpdInterval[Config.PsxType] )
 291         {
 292             spuSyncCount = 0;
 293
 294             if( SPU_async )
 295             {
 296                 SPU_async( SpuUpdInterval[Config.PsxType] * rcnts[3].target );
 297             }
 298         }
 299
 300         // VSync irq.
 301         if( hSyncCount == VBlankStart[Config.PsxType] )
 302         {
 303             if( !(HW_GPU_STATUS & PSXGPU_ILACE) )
 304                 HW_GPU_STATUS |= PSXGPU_LCF;
 305
 306             setIrq( 0x01 );
 307
 308             EmuUpdate();
 309             GPU_updateLace();
 310         }
 311
 312         // Update lace. (with InuYasha fix)
 313         if( hSyncCount >= (Config.VSyncWA ? HSyncTotal[Config.PsxType] / BIAS : HSyncTotal[Config.PsxType]) )
 314         {
 315             hSyncCount = 0;
 316             frame_counter++;
 317
 318             HW_GPU_STATUS &= ~PSXGPU_LCF;
 319             if( HW_GPU_STATUS & PSXGPU_ILACE )
 320                 HW_GPU_STATUS |= frame_counter << 31;
 321         }
 322
 323         // Schedule next call, in hsyncs
 324         hsync_steps = SpuUpdInterval[Config.PsxType] - spuSyncCount;
 325         next_vsync = VBlankStart[Config.PsxType] - hSyncCount; // ok to overflow
 326         next_lace = HSyncTotal[Config.PsxType] - hSyncCount;
 327         if( next_vsync && next_vsync < hsync_steps )
 328             hsync_steps = next_vsync;
 329         if( next_lace && next_lace < hsync_steps )
 330             hsync_steps = next_lace;
 331
 332         rcnts[3].cycleStart = cycle - leftover_cycles;
 333         if (Config.PsxType)
 334                 // 20.12 precision, clk / 50 / 313 ~= 2164.14
 335                 base_cycle += hsync_steps * 8864320;
 336         else
 337                 // clk / 60 / 263 ~= 2146.31
 338                 base_cycle += hsync_steps * 8791293;
 339         rcnts[3].cycle = base_cycle >> 12;
 340         base_cycle &= 0xfff;
 341         psxRcntSet();
 342     }
 343
 344 #ifndef NDEBUG
 345     DebugVSync();
 346 #endif
 347 }
 348
 349 /******************************************************************************/
 350
 351 void psxRcntWcount( u32 index, u32 value )
 352 {
 353     verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value );
 354
 355     _psxRcntWcount( index, value );
 356     psxRcntSet();
 357 }
 358
 359 void psxRcntWmode( u32 index, u32 value )
 360 {
 361     verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value );
 362
 363     rcnts[index].mode = value;
 364     rcnts[index].irqState = 0;
 365
 366     switch( index )
 367     {
 368         case 0:
 369             if( value & Rc0PixelClock )
 370             {
 371                 rcnts[index].rate = 5;
 372             }
 373             else
 374             {
 375                 rcnts[index].rate = 1;
 376             }
 377         break;
 378         case 1:
 379             if( value & Rc1HSyncClock )
 380             {
 381                 rcnts[index].rate = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
 382             }
 383             else
 384             {
 385                 rcnts[index].rate = 1;
 386             }
 387         break;
 388         case 2:
 389             if( value & Rc2OneEighthClock )
 390             {
 391                 rcnts[index].rate = 8;
 392             }
 393             else
 394             {
 395                 rcnts[index].rate = 1;
 396             }
 397
 398             // TODO: wcount must work.
 399             if( value & Rc2Disable )
 400             {
 401                 rcnts[index].rate = 0xffffffff;
 402             }
 403         break;
 404     }
 405
 406     _psxRcntWcount( index, 0 );
 407     psxRcntSet();
 408 }
 409
 410 void psxRcntWtarget( u32 index, u32 value )
 411 {
 412     verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value );
 413
 414     rcnts[index].target = value;
 415
 416     _psxRcntWcount( index, _psxRcntRcount( index ) );
 417     psxRcntSet();
 418 }
 419
 420 /******************************************************************************/
 421
 422 u32 psxRcntRcount( u32 index )
 423 {
 424     u32 count;
 425
 426     count = _psxRcntRcount( index );
 427
 428     // Parasite Eve 2 fix.
 429     if( Config.RCntFix )
 430     {
 431         if( index == 2 )
 432         {
 433             if( rcnts[index].counterState == CountToTarget )
 434             {
 435                 count /= BIAS;
 436             }
 437         }
 438     }
 439
 440     verboseLog( 2, "[RCNT %i] rcount: %x\n", index, count );
 441
 442     return count;
 443 }
 444
 445 u32 psxRcntRmode( u32 index )
 446 {
 447     u16 mode;
 448
 449     mode = rcnts[index].mode;
 450     rcnts[index].mode &= 0xe7ff;
 451
 452     verboseLog( 2, "[RCNT %i] rmode: %x\n", index, mode );
 453
 454     return mode;
 455 }
 456
 457 u32 psxRcntRtarget( u32 index )
 458 {
 459     verboseLog( 2, "[RCNT %i] rtarget: %x\n", index, rcnts[index].target );
 460
 461     return rcnts[index].target;
 462 }
 463
 464 /******************************************************************************/
 465
 466 void psxRcntInit()
 467 {
 468     s32 i;
 469
 470     // rcnt 0.
 471     rcnts[0].rate   = 1;
 472     rcnts[0].irq    = 0x10;
 473
 474     // rcnt 1.
 475     rcnts[1].rate   = 1;
 476     rcnts[1].irq    = 0x20;
 477
 478     // rcnt 2.
 479     rcnts[2].rate   = 1;
 480     rcnts[2].irq    = 0x40;
 481
 482     // rcnt base.
 483     rcnts[3].rate   = 1;
 484     rcnts[3].mode   = RcCountToTarget;
 485     rcnts[3].target = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
 486
 487     for( i = 0; i < CounterQuantity; ++i )
 488     {
 489         _psxRcntWcount( i, 0 );
 490     }
 491
 492     hSyncCount = 0;
 493     spuSyncCount = 0;
 494     hsync_steps = 1;
 495
 496     psxRcntSet();
 497 }
 498
 499 /******************************************************************************/
 500
 501 s32 psxRcntFreeze( gzFile f, s32 Mode )
 502 {
 503     gzfreeze( &rcnts, sizeof(rcnts) );
 504     gzfreeze( &hSyncCount, sizeof(hSyncCount) );
 505     gzfreeze( &spuSyncCount, sizeof(spuSyncCount) );
 506     gzfreeze( &psxNextCounter, sizeof(psxNextCounter) );
 507     gzfreeze( &psxNextsCounter, sizeof(psxNextsCounter) );
 508
 509     if (Mode == 0)
 510         hsync_steps = (psxRegs.cycle - rcnts[3].cycleStart) / rcnts[3].target;
 511
 512     base_cycle = 0;
 513
 514     return 0;
 515 }
 516
 517 /******************************************************************************/