libpcsxcore/psxcounters.c

   1 /***************************************************************************
   2  *   Copyright (C) 2010 by Blade_Arma                                      *
   3  *                                                                         *
   4  *   This program is free software; you can redistribute it and/or modify  *
   5  *   it under the terms of the GNU General Public License as published by  *
   6  *   the Free Software Foundation; either version 2 of the License, or     *
   7  *   (at your option) any later version.                                   *
   8  *                                                                         *
   9  *   This program is distributed in the hope that it will be useful,       *
  10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  12  *   GNU General Public License for more details.                          *
  13  *                                                                         *
  14  *   You should have received a copy of the GNU General Public License     *
  15  *   along with this program; if not, write to the                         *
  16  *   Free Software Foundation, Inc.,                                       *
  17  *   51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA.           *
  18  ***************************************************************************/
  19
  20 /*
  21  * Internal PSX counters.
  22  */
  23
  24 #include "psxcounters.h"
  25 #include "gpu.h"
  26 #include "debug.h"
  27
  28 /******************************************************************************/
  29
  30 enum
  31 {
  32     Rc0Gate           = 0x0001, // 0    not implemented
  33     Rc1Gate           = 0x0001, // 0    not implemented
  34     Rc2Disable        = 0x0001, // 0    partially implemented
  35     RcUnknown1        = 0x0002, // 1    ?
  36     RcUnknown2        = 0x0004, // 2    ?
  37     RcCountToTarget   = 0x0008, // 3
  38     RcIrqOnTarget     = 0x0010, // 4
  39     RcIrqOnOverflow   = 0x0020, // 5
  40     RcIrqRegenerate   = 0x0040, // 6
  41     RcUnknown7        = 0x0080, // 7    ?
  42     Rc0PixelClock     = 0x0100, // 8    fake implementation
  43     Rc1HSyncClock     = 0x0100, // 8
  44     Rc2Unknown8       = 0x0100, // 8    ?
  45     Rc0Unknown9       = 0x0200, // 9    ?
  46     Rc1Unknown9       = 0x0200, // 9    ?
  47     Rc2OneEighthClock = 0x0200, // 9
  48     RcUnknown10       = 0x0400, // 10   ?
  49     RcCountEqTarget   = 0x0800, // 11
  50     RcOverflow        = 0x1000, // 12
  51     RcUnknown13       = 0x2000, // 13   ? (always zero)
  52     RcUnknown14       = 0x4000, // 14   ? (always zero)
  53     RcUnknown15       = 0x8000, // 15   ? (always zero)
  54 };
  55
  56 #define CounterQuantity           ( 4 )
  57 //static const u32 CounterQuantity  = 4;
  58
  59 static const u32 CountToOverflow  = 0;
  60 static const u32 CountToTarget    = 1;
  61
  62 static const u32 FrameRate[]      = { 60, 50 };
  63 static const u32 HSyncTotal[]     = { 263, 313 };
  64 static const u32 SpuUpdInterval[] = { 32, 32 };
  65 #define VBlankStart 240
  66
  67 #define VERBOSE_LEVEL 0
  68 static const s32 VerboseLevel     = VERBOSE_LEVEL;
  69
  70 /******************************************************************************/
  71
  72 Rcnt rcnts[ CounterQuantity ];
  73
  74 u32 hSyncCount = 0;
  75 u32 frame_counter = 0;
  76 static u32 spuSyncCount = 0;
  77 static u32 hsync_steps = 0;
  78 static u32 base_cycle = 0;
  79
  80 u32 psxNextCounter = 0, psxNextsCounter = 0;
  81
  82 /******************************************************************************/
  83
  84 static inline
  85 void setIrq( u32 irq )
  86 {
  87     psxHu32ref(0x1070) |= SWAPu32(irq);
  88 }
  89
  90 static
  91 void verboseLog( u32 level, const char *str, ... )
  92 {
  93 #if VERBOSE_LEVEL > 0
  94     if( level <= VerboseLevel )
  95     {
  96         va_list va;
  97         char buf[ 4096 ];
  98
  99         va_start( va, str );
 100         vsprintf( buf, str, va );
 101         va_end( va );
 102
 103         printf( "%s", buf );
 104         fflush( stdout );
 105     }
 106 #endif
 107 }
 108
 109 /******************************************************************************/
 110
 111 static inline
 112 void _psxRcntWcount( u32 index, u32 value )
 113 {
 114     if( value > 0xffff )
 115     {
 116         verboseLog( 1, "[RCNT %i] wcount > 0xffff: %x\n", index, value );
 117         value &= 0xffff;
 118     }
 119
 120     rcnts[index].cycleStart  = psxRegs.cycle;
 121     rcnts[index].cycleStart -= value * rcnts[index].rate;
 122
 123     // TODO: <=.
 124     if( value < rcnts[index].target )
 125     {
 126         rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
 127         rcnts[index].counterState = CountToTarget;
 128     }
 129     else
 130     {
 131         rcnts[index].cycle = 0x10000 * rcnts[index].rate;
 132         rcnts[index].counterState = CountToOverflow;
 133     }
 134 }
 135
 136 static inline
 137 u32 _psxRcntRcount( u32 index )
 138 {
 139     u32 count;
 140
 141     count  = psxRegs.cycle;
 142     count -= rcnts[index].cycleStart;
 143     if (rcnts[index].rate > 1)
 144         count /= rcnts[index].rate;
 145
 146     if( count > 0x10000 )
 147     {
 148         verboseLog( 1, "[RCNT %i] rcount > 0x10000: %x\n", index, count );
 149     }
 150     count &= 0xffff;
 151
 152     return count;
 153 }
 154
 155 static
 156 void _psxRcntWmode( u32 index, u32 value )
 157 {
 158     rcnts[index].mode = value;
 159
 160     switch( index )
 161     {
 162         case 0:
 163             if( value & Rc0PixelClock )
 164             {
 165                 rcnts[index].rate = 5;
 166             }
 167             else
 168             {
 169                 rcnts[index].rate = 1;
 170             }
 171         break;
 172         case 1:
 173             if( value & Rc1HSyncClock )
 174             {
 175                 rcnts[index].rate = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
 176             }
 177             else
 178             {
 179                 rcnts[index].rate = 1;
 180             }
 181         break;
 182         case 2:
 183             if( value & Rc2OneEighthClock )
 184             {
 185                 rcnts[index].rate = 8;
 186             }
 187             else
 188             {
 189                 rcnts[index].rate = 1;
 190             }
 191
 192             // TODO: wcount must work.
 193             if( value & Rc2Disable )
 194             {
 195                 rcnts[index].rate = 0xffffffff;
 196             }
 197         break;
 198     }
 199 }
 200
 201 /******************************************************************************/
 202
 203 static
 204 void psxRcntSet()
 205 {
 206     s32 countToUpdate;
 207     u32 i;
 208
 209     psxNextsCounter = psxRegs.cycle;
 210     psxNextCounter  = 0x7fffffff;
 211
 212     for( i = 0; i < CounterQuantity; ++i )
 213     {
 214         countToUpdate = rcnts[i].cycle - (psxNextsCounter - rcnts[i].cycleStart);
 215
 216         if( countToUpdate < 0 )
 217         {
 218             psxNextCounter = 0;
 219             break;
 220         }
 221
 222         if( countToUpdate < (s32)psxNextCounter )
 223         {
 224             psxNextCounter = countToUpdate;
 225         }
 226     }
 227
 228     psxRegs.interrupt |= (1 << PSXINT_RCNT);
 229     new_dyna_set_event(PSXINT_RCNT, psxNextCounter);
 230 }
 231
 232 /******************************************************************************/
 233
 234 static
 235 void psxRcntReset( u32 index )
 236 {
 237     u32 rcycles;
 238
 239     rcnts[index].mode |= RcUnknown10;
 240
 241     if( rcnts[index].counterState == CountToTarget )
 242     {
 243         rcycles = psxRegs.cycle - rcnts[index].cycleStart;
 244         if( rcnts[index].mode & RcCountToTarget )
 245         {
 246             rcycles -= rcnts[index].target * rcnts[index].rate;
 247             rcnts[index].cycleStart = psxRegs.cycle - rcycles;
 248         }
 249         else
 250         {
 251             rcnts[index].cycle = 0x10000 * rcnts[index].rate;
 252             rcnts[index].counterState = CountToOverflow;
 253         }
 254
 255         if( rcnts[index].mode & RcIrqOnTarget )
 256         {
 257             if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
 258             {
 259                 verboseLog( 3, "[RCNT %i] irq\n", index );
 260                 setIrq( rcnts[index].irq );
 261                 rcnts[index].irqState = 1;
 262             }
 263         }
 264
 265         rcnts[index].mode |= RcCountEqTarget;
 266
 267         if( rcycles < 0x10000 * rcnts[index].rate )
 268             return;
 269     }
 270
 271     if( rcnts[index].counterState == CountToOverflow )
 272     {
 273         rcycles = psxRegs.cycle - rcnts[index].cycleStart;
 274         rcycles -= 0x10000 * rcnts[index].rate;
 275
 276         rcnts[index].cycleStart = psxRegs.cycle - rcycles;
 277
 278         if( rcycles < rcnts[index].target * rcnts[index].rate )
 279         {
 280             rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
 281             rcnts[index].counterState = CountToTarget;
 282         }
 283
 284         if( rcnts[index].mode & RcIrqOnOverflow )
 285         {
 286             if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
 287             {
 288                 verboseLog( 3, "[RCNT %i] irq\n", index );
 289                 setIrq( rcnts[index].irq );
 290                 rcnts[index].irqState = 1;
 291             }
 292         }
 293
 294         rcnts[index].mode |= RcOverflow;
 295     }
 296 }
 297
 298 void psxRcntUpdate()
 299 {
 300     u32 cycle;
 301
 302     cycle = psxRegs.cycle;
 303
 304     // rcnt 0.
 305     if( cycle - rcnts[0].cycleStart >= rcnts[0].cycle )
 306     {
 307         psxRcntReset( 0 );
 308     }
 309
 310     // rcnt 1.
 311     if( cycle - rcnts[1].cycleStart >= rcnts[1].cycle )
 312     {
 313         psxRcntReset( 1 );
 314     }
 315
 316     // rcnt 2.
 317     if( cycle - rcnts[2].cycleStart >= rcnts[2].cycle )
 318     {
 319         psxRcntReset( 2 );
 320     }
 321
 322     // rcnt base.
 323     if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle )
 324     {
 325         u32 leftover_cycles = cycle - rcnts[3].cycleStart - rcnts[3].cycle;
 326         u32 next_vsync, next_lace;
 327
 328         spuSyncCount += hsync_steps;
 329         hSyncCount += hsync_steps;
 330
 331         // Update spu.
 332         if( spuSyncCount >= SpuUpdInterval[Config.PsxType] )
 333         {
 334             spuSyncCount = 0;
 335
 336             if( SPU_async )
 337             {
 338                 SPU_async( SpuUpdInterval[Config.PsxType] * rcnts[3].target );
 339             }
 340         }
 341
 342         // VSync irq.
 343         if( hSyncCount == VBlankStart )
 344         {
 345             HW_GPU_STATUS &= ~PSXGPU_LCF;
 346             GPU_vBlank( 1, 0 );
 347             setIrq( 0x01 );
 348
 349             EmuUpdate();
 350             GPU_updateLace();
 351         }
 352
 353         // Update lace. (with InuYasha fix)
 354         if( hSyncCount >= (Config.VSyncWA ? HSyncTotal[Config.PsxType] / BIAS : HSyncTotal[Config.PsxType]) )
 355         {
 356             hSyncCount = 0;
 357             frame_counter++;
 358
 359             gpuSyncPluginSR();
 360             if( (HW_GPU_STATUS & PSXGPU_ILACE_BITS) == PSXGPU_ILACE_BITS )
 361                 HW_GPU_STATUS |= frame_counter << 31;
 362             GPU_vBlank( 0, HW_GPU_STATUS >> 31 );
 363         }
 364
 365         // Schedule next call, in hsyncs
 366         hsync_steps = SpuUpdInterval[Config.PsxType] - spuSyncCount;
 367         next_vsync = VBlankStart - hSyncCount; // ok to overflow
 368         next_lace = HSyncTotal[Config.PsxType] - hSyncCount;
 369         if( next_vsync && next_vsync < hsync_steps )
 370             hsync_steps = next_vsync;
 371         if( next_lace && next_lace < hsync_steps )
 372             hsync_steps = next_lace;
 373
 374         rcnts[3].cycleStart = cycle - leftover_cycles;
 375         if (Config.PsxType)
 376                 // 20.12 precision, clk / 50 / 313 ~= 2164.14
 377                 base_cycle += hsync_steps * 8864320;
 378         else
 379                 // clk / 60 / 263 ~= 2146.31
 380                 base_cycle += hsync_steps * 8791293;
 381         rcnts[3].cycle = base_cycle >> 12;
 382         base_cycle &= 0xfff;
 383     }
 384
 385     psxRcntSet();
 386
 387 #ifndef NDEBUG
 388     DebugVSync();
 389 #endif
 390 }
 391
 392 /******************************************************************************/
 393
 394 void psxRcntWcount( u32 index, u32 value )
 395 {
 396     verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value );
 397
 398     _psxRcntWcount( index, value );
 399     psxRcntSet();
 400 }
 401
 402 void psxRcntWmode( u32 index, u32 value )
 403 {
 404     verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value );
 405
 406     _psxRcntWmode( index, value );
 407     _psxRcntWcount( index, 0 );
 408
 409     rcnts[index].irqState = 0;
 410     psxRcntSet();
 411 }
 412
 413 void psxRcntWtarget( u32 index, u32 value )
 414 {
 415     verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value );
 416
 417     rcnts[index].target = value;
 418
 419     _psxRcntWcount( index, _psxRcntRcount( index ) );
 420     psxRcntSet();
 421 }
 422
 423 /******************************************************************************/
 424
 425 u32 psxRcntRcount( u32 index )
 426 {
 427     u32 count;
 428
 429     count = _psxRcntRcount( index );
 430
 431     // Parasite Eve 2 fix.
 432     if( Config.RCntFix )
 433     {
 434         if( index == 2 )
 435         {
 436             if( rcnts[index].counterState == CountToTarget )
 437             {
 438                 count /= BIAS;
 439             }
 440         }
 441     }
 442
 443     verboseLog( 2, "[RCNT %i] rcount: %x\n", index, count );
 444
 445     return count;
 446 }
 447
 448 u32 psxRcntRmode( u32 index )
 449 {
 450     u16 mode;
 451
 452     mode = rcnts[index].mode;
 453     rcnts[index].mode &= 0xe7ff;
 454
 455     verboseLog( 2, "[RCNT %i] rmode: %x\n", index, mode );
 456
 457     return mode;
 458 }
 459
 460 u32 psxRcntRtarget( u32 index )
 461 {
 462     verboseLog( 2, "[RCNT %i] rtarget: %x\n", index, rcnts[index].target );
 463
 464     return rcnts[index].target;
 465 }
 466
 467 /******************************************************************************/
 468
 469 void psxRcntInit()
 470 {
 471     s32 i;
 472
 473     // rcnt 0.
 474     rcnts[0].rate   = 1;
 475     rcnts[0].irq    = 0x10;
 476
 477     // rcnt 1.
 478     rcnts[1].rate   = 1;
 479     rcnts[1].irq    = 0x20;
 480
 481     // rcnt 2.
 482     rcnts[2].rate   = 1;
 483     rcnts[2].irq    = 0x40;
 484
 485     // rcnt base.
 486     rcnts[3].rate   = 1;
 487     rcnts[3].mode   = RcCountToTarget;
 488     rcnts[3].target = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
 489
 490     for( i = 0; i < CounterQuantity; ++i )
 491     {
 492         _psxRcntWcount( i, 0 );
 493     }
 494
 495     hSyncCount = 0;
 496     spuSyncCount = 0;
 497     hsync_steps = 1;
 498
 499     psxRcntSet();
 500 }
 501
 502 /******************************************************************************/
 503
 504 s32 psxRcntFreeze( gzFile f, s32 Mode )
 505 {
 506     u32 count;
 507     s32 i;
 508
 509     gzfreeze( &rcnts, sizeof(rcnts) );
 510     gzfreeze( &hSyncCount, sizeof(hSyncCount) );
 511     gzfreeze( &spuSyncCount, sizeof(spuSyncCount) );
 512     gzfreeze( &psxNextCounter, sizeof(psxNextCounter) );
 513     gzfreeze( &psxNextsCounter, sizeof(psxNextsCounter) );
 514
 515     if (Mode == 0)
 516     {
 517         // don't trust things from a savestate
 518         for( i = 0; i < CounterQuantity; ++i )
 519         {
 520             _psxRcntWmode( i, rcnts[i].mode );
 521             count = (psxRegs.cycle - rcnts[i].cycleStart) / rcnts[i].rate;
 522             _psxRcntWcount( i, count );
 523         }
 524         hsync_steps = (psxRegs.cycle - rcnts[3].cycleStart) / rcnts[3].target;
 525         psxRcntSet();
 526
 527         base_cycle = 0;
 528     }
 529
 530     return 0;
 531 }
 532
 533 /******************************************************************************/