libpcsxcore/psxcounters.c

   1 /***************************************************************************
   2  *   Copyright (C) 2010 by Blade_Arma                                      *
   3  *                                                                         *
   4  *   This program is free software; you can redistribute it and/or modify  *
   5  *   it under the terms of the GNU General Public License as published by  *
   6  *   the Free Software Foundation; either version 2 of the License, or     *
   7  *   (at your option) any later version.                                   *
   8  *                                                                         *
   9  *   This program is distributed in the hope that it will be useful,       *
  10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  12  *   GNU General Public License for more details.                          *
  13  *                                                                         *
  14  *   You should have received a copy of the GNU General Public License     *
  15  *   along with this program; if not, write to the                         *
  16  *   Free Software Foundation, Inc.,                                       *
  17  *   51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA.           *
  18  ***************************************************************************/
  19
  20 /*
  21  * Internal PSX counters.
  22  */
  23
  24 #include "psxcounters.h"
  25 #include "debug.h"
  26
  27 /******************************************************************************/
  28
  29 enum
  30 {
  31     Rc0Gate           = 0x0001, // 0    not implemented
  32     Rc1Gate           = 0x0001, // 0    not implemented
  33     Rc2Disable        = 0x0001, // 0    partially implemented
  34     RcUnknown1        = 0x0002, // 1    ?
  35     RcUnknown2        = 0x0004, // 2    ?
  36     RcCountToTarget   = 0x0008, // 3
  37     RcIrqOnTarget     = 0x0010, // 4
  38     RcIrqOnOverflow   = 0x0020, // 5
  39     RcIrqRegenerate   = 0x0040, // 6
  40     RcUnknown7        = 0x0080, // 7    ?
  41     Rc0PixelClock     = 0x0100, // 8    fake implementation
  42     Rc1HSyncClock     = 0x0100, // 8
  43     Rc2Unknown8       = 0x0100, // 8    ?
  44     Rc0Unknown9       = 0x0200, // 9    ?
  45     Rc1Unknown9       = 0x0200, // 9    ?
  46     Rc2OneEighthClock = 0x0200, // 9
  47     RcUnknown10       = 0x0400, // 10   ?
  48     RcCountEqTarget   = 0x0800, // 11
  49     RcOverflow        = 0x1000, // 12
  50     RcUnknown13       = 0x2000, // 13   ? (always zero)
  51     RcUnknown14       = 0x4000, // 14   ? (always zero)
  52     RcUnknown15       = 0x8000, // 15   ? (always zero)
  53 };
  54
  55 #define CounterQuantity           ( 4 )
  56 //static const u32 CounterQuantity  = 4;
  57
  58 static const u32 CountToOverflow  = 0;
  59 static const u32 CountToTarget    = 1;
  60
  61 static const u32 FrameRate[]      = { 60, 50 };
  62 static const u32 VBlankStart[]    = { 240, 256 };
  63 static const u32 HSyncTotal[]     = { 263, 313 };
  64 static const u32 SpuUpdInterval[] = { 32, 32 };
  65
  66 #define VERBOSE_LEVEL 0
  67 static const s32 VerboseLevel     = VERBOSE_LEVEL;
  68
  69 /******************************************************************************/
  70
  71 Rcnt rcnts[ CounterQuantity ];
  72
  73 static u32 hSyncCount = 0;
  74 static u32 spuSyncCount = 0;
  75 static u32 hsync_steps = 0;
  76 static u32 gpu_wants_hcnt = 0;
  77
  78 u32 psxNextCounter = 0, psxNextsCounter = 0;
  79
  80 /******************************************************************************/
  81
  82 static inline
  83 void setIrq( u32 irq )
  84 {
  85     psxHu32ref(0x1070) |= SWAPu32(irq);
  86 }
  87
  88 static
  89 void verboseLog( u32 level, const char *str, ... )
  90 {
  91 #if VERBOSE_LEVEL > 0
  92     if( level <= VerboseLevel )
  93     {
  94         va_list va;
  95         char buf[ 4096 ];
  96
  97         va_start( va, str );
  98         vsprintf( buf, str, va );
  99         va_end( va );
 100
 101         printf( "%s", buf );
 102         fflush( stdout );
 103     }
 104 #endif
 105 }
 106
 107 /******************************************************************************/
 108
 109 static inline
 110 void _psxRcntWcount( u32 index, u32 value )
 111 {
 112     if( value > 0xffff )
 113     {
 114         verboseLog( 1, "[RCNT %i] wcount > 0xffff: %x\n", index, value );
 115         value &= 0xffff;
 116     }
 117
 118     rcnts[index].cycleStart  = psxRegs.cycle;
 119     rcnts[index].cycleStart -= value * rcnts[index].rate;
 120
 121     // TODO: <=.
 122     if( value < rcnts[index].target )
 123     {
 124         rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
 125         rcnts[index].counterState = CountToTarget;
 126     }
 127     else
 128     {
 129         rcnts[index].cycle = 0xffff * rcnts[index].rate;
 130         rcnts[index].counterState = CountToOverflow;
 131     }
 132 }
 133
 134 static inline
 135 u32 _psxRcntRcount( u32 index )
 136 {
 137     u32 count;
 138
 139     count  = psxRegs.cycle;
 140     count -= rcnts[index].cycleStart;
 141     if (rcnts[index].rate > 1)
 142         count /= rcnts[index].rate;
 143
 144     if( count > 0xffff )
 145     {
 146         verboseLog( 1, "[RCNT %i] rcount > 0xffff: %x\n", index, count );
 147         count &= 0xffff;
 148     }
 149
 150     return count;
 151 }
 152
 153 /******************************************************************************/
 154
 155 static
 156 void psxRcntSet()
 157 {
 158     s32 countToUpdate;
 159     u32 i;
 160
 161     psxNextsCounter = psxRegs.cycle;
 162     psxNextCounter  = 0x7fffffff;
 163
 164     for( i = 0; i < CounterQuantity; ++i )
 165     {
 166         countToUpdate = rcnts[i].cycle - (psxNextsCounter - rcnts[i].cycleStart);
 167
 168         if( countToUpdate < 0 )
 169         {
 170             psxNextCounter = 0;
 171             break;
 172         }
 173
 174         if( countToUpdate < (s32)psxNextCounter )
 175         {
 176             psxNextCounter = countToUpdate;
 177         }
 178     }
 179
 180     psxRegs.interrupt |= (1 << PSXINT_RCNT);
 181     new_dyna_set_event(PSXINT_RCNT, psxNextCounter);
 182 }
 183
 184 /******************************************************************************/
 185
 186 static
 187 void psxRcntReset( u32 index )
 188 {
 189     u32 count;
 190
 191     if( rcnts[index].counterState == CountToTarget )
 192     {
 193         if( rcnts[index].mode & RcCountToTarget )
 194         {
 195             count  = psxRegs.cycle;
 196             count -= rcnts[index].cycleStart;
 197             if (rcnts[index].rate > 1)
 198                 count /= rcnts[index].rate;
 199             count -= rcnts[index].target;
 200         }
 201         else
 202         {
 203             count = _psxRcntRcount( index );
 204         }
 205
 206         _psxRcntWcount( index, count );
 207
 208         if( rcnts[index].mode & RcIrqOnTarget )
 209         {
 210             if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
 211             {
 212                 verboseLog( 3, "[RCNT %i] irq: %x\n", index, count );
 213                 setIrq( rcnts[index].irq );
 214                 rcnts[index].irqState = 1;
 215             }
 216         }
 217
 218         rcnts[index].mode |= RcCountEqTarget;
 219     }
 220     else if( rcnts[index].counterState == CountToOverflow )
 221     {
 222         count  = psxRegs.cycle;
 223         count -= rcnts[index].cycleStart;
 224         if (rcnts[index].rate > 1)
 225             count /= rcnts[index].rate;
 226         count -= 0xffff;
 227
 228         _psxRcntWcount( index, count );
 229
 230         if( rcnts[index].mode & RcIrqOnOverflow )
 231         {
 232             if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
 233             {
 234                 verboseLog( 3, "[RCNT %i] irq: %x\n", index, count );
 235                 setIrq( rcnts[index].irq );
 236                 rcnts[index].irqState = 1;
 237             }
 238         }
 239
 240         rcnts[index].mode |= RcOverflow;
 241     }
 242
 243     rcnts[index].mode |= RcUnknown10;
 244
 245     psxRcntSet();
 246 }
 247
 248 void psxRcntUpdate()
 249 {
 250     u32 cycle;
 251
 252     cycle = psxRegs.cycle;
 253
 254     // rcnt 0.
 255     if( cycle - rcnts[0].cycleStart >= rcnts[0].cycle )
 256     {
 257         psxRcntReset( 0 );
 258     }
 259
 260     // rcnt 1.
 261     if( cycle - rcnts[1].cycleStart >= rcnts[1].cycle )
 262     {
 263         psxRcntReset( 1 );
 264     }
 265
 266     // rcnt 2.
 267     if( cycle - rcnts[2].cycleStart >= rcnts[2].cycle )
 268     {
 269         psxRcntReset( 2 );
 270     }
 271
 272     // rcnt base.
 273     if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle )
 274     {
 275         u32 leftover_cycles = cycle - rcnts[3].cycleStart - rcnts[3].cycle;
 276         u32 next_vsync, next_lace;
 277
 278         spuSyncCount += hsync_steps;
 279         hSyncCount += hsync_steps;
 280
 281         // Update spu.
 282         if( spuSyncCount >= SpuUpdInterval[Config.PsxType] )
 283         {
 284             spuSyncCount = 0;
 285
 286             if( SPU_async )
 287             {
 288                 SPU_async( SpuUpdInterval[Config.PsxType] * rcnts[3].target );
 289             }
 290         }
 291
 292         // VSync irq.
 293         if( hSyncCount == VBlankStart[Config.PsxType] )
 294         {
 295             GPU_vBlank( 1, &hSyncCount, &gpu_wants_hcnt );
 296
 297             // For the best times. :D
 298             //setIrq( 0x01 );
 299         }
 300
 301         // Update lace. (with InuYasha fix)
 302         if( hSyncCount >= (Config.VSyncWA ? HSyncTotal[Config.PsxType] / BIAS : HSyncTotal[Config.PsxType]) )
 303         {
 304             hSyncCount = 0;
 305
 306             GPU_vBlank( 0, &hSyncCount, &gpu_wants_hcnt );
 307             setIrq( 0x01 );
 308
 309             EmuUpdate();
 310             GPU_updateLace();
 311         }
 312
 313         // Schedule next call, in hsyncs
 314         hsync_steps = SpuUpdInterval[Config.PsxType] - spuSyncCount;
 315         next_vsync = VBlankStart[Config.PsxType] - hSyncCount; // ok to overflow
 316         next_lace = HSyncTotal[Config.PsxType] - hSyncCount;
 317         if( next_vsync && next_vsync < hsync_steps )
 318             hsync_steps = next_vsync;
 319         if( next_lace && next_lace < hsync_steps )
 320             hsync_steps = next_lace;
 321         if( gpu_wants_hcnt )
 322             hsync_steps = 1;
 323
 324         rcnts[3].cycleStart = cycle - leftover_cycles;
 325         rcnts[3].cycle = hsync_steps * rcnts[3].target;
 326         psxRcntSet();
 327     }
 328
 329 #ifndef NDEBUG
 330     DebugVSync();
 331 #endif
 332 }
 333
 334 /******************************************************************************/
 335
 336 void psxRcntWcount( u32 index, u32 value )
 337 {
 338     verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value );
 339
 340     _psxRcntWcount( index, value );
 341     psxRcntSet();
 342 }
 343
 344 void psxRcntWmode( u32 index, u32 value )
 345 {
 346     verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value );
 347
 348     rcnts[index].mode = value;
 349     rcnts[index].irqState = 0;
 350
 351     switch( index )
 352     {
 353         case 0:
 354             if( value & Rc0PixelClock )
 355             {
 356                 rcnts[index].rate = 5;
 357             }
 358             else
 359             {
 360                 rcnts[index].rate = 1;
 361             }
 362         break;
 363         case 1:
 364             if( value & Rc1HSyncClock )
 365             {
 366                 rcnts[index].rate = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
 367             }
 368             else
 369             {
 370                 rcnts[index].rate = 1;
 371             }
 372         break;
 373         case 2:
 374             if( value & Rc2OneEighthClock )
 375             {
 376                 rcnts[index].rate = 8;
 377             }
 378             else
 379             {
 380                 rcnts[index].rate = 1;
 381             }
 382
 383             // TODO: wcount must work.
 384             if( value & Rc2Disable )
 385             {
 386                 rcnts[index].rate = 0xffffffff;
 387             }
 388         break;
 389     }
 390
 391     _psxRcntWcount( index, 0 );
 392     psxRcntSet();
 393 }
 394
 395 void psxRcntWtarget( u32 index, u32 value )
 396 {
 397     verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value );
 398
 399     rcnts[index].target = value;
 400
 401     _psxRcntWcount( index, _psxRcntRcount( index ) );
 402     psxRcntSet();
 403 }
 404
 405 /******************************************************************************/
 406
 407 u32 psxRcntRcount( u32 index )
 408 {
 409     u32 count;
 410
 411     count = _psxRcntRcount( index );
 412
 413     // Parasite Eve 2 fix.
 414     if( Config.RCntFix )
 415     {
 416         if( index == 2 )
 417         {
 418             if( rcnts[index].counterState == CountToTarget )
 419             {
 420                 count /= BIAS;
 421             }
 422         }
 423     }
 424
 425     verboseLog( 2, "[RCNT %i] rcount: %x\n", index, count );
 426
 427     return count;
 428 }
 429
 430 u32 psxRcntRmode( u32 index )
 431 {
 432     u16 mode;
 433
 434     mode = rcnts[index].mode;
 435     rcnts[index].mode &= 0xe7ff;
 436
 437     verboseLog( 2, "[RCNT %i] rmode: %x\n", index, mode );
 438
 439     return mode;
 440 }
 441
 442 u32 psxRcntRtarget( u32 index )
 443 {
 444     verboseLog( 2, "[RCNT %i] rtarget: %x\n", index, rcnts[index].target );
 445
 446     return rcnts[index].target;
 447 }
 448
 449 /******************************************************************************/
 450
 451 void psxRcntInit()
 452 {
 453     s32 i;
 454
 455     // rcnt 0.
 456     rcnts[0].rate   = 1;
 457     rcnts[0].irq    = 0x10;
 458
 459     // rcnt 1.
 460     rcnts[1].rate   = 1;
 461     rcnts[1].irq    = 0x20;
 462
 463     // rcnt 2.
 464     rcnts[2].rate   = 1;
 465     rcnts[2].irq    = 0x40;
 466
 467     // rcnt base.
 468     rcnts[3].rate   = 1;
 469     rcnts[3].mode   = RcCountToTarget;
 470     rcnts[3].target = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
 471
 472     for( i = 0; i < CounterQuantity; ++i )
 473     {
 474         _psxRcntWcount( i, 0 );
 475     }
 476
 477     hSyncCount = 0;
 478     spuSyncCount = 0;
 479     hsync_steps = 1;
 480
 481     psxRcntSet();
 482 }
 483
 484 /******************************************************************************/
 485
 486 s32 psxRcntFreeze( gzFile f, s32 Mode )
 487 {
 488     gzfreeze( &rcnts, sizeof(rcnts) );
 489     gzfreeze( &hSyncCount, sizeof(hSyncCount) );
 490     gzfreeze( &spuSyncCount, sizeof(spuSyncCount) );
 491     gzfreeze( &psxNextCounter, sizeof(psxNextCounter) );
 492     gzfreeze( &psxNextsCounter, sizeof(psxNextsCounter) );
 493
 494     if (Mode == 0)
 495         hsync_steps = (psxRegs.cycle - rcnts[3].cycleStart) / rcnts[3].target;
 496
 497     return 0;
 498 }
 499
 500 /******************************************************************************/