1 /***************************************************************************
2 * Copyright (C) 2010 by Blade_Arma *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
18 ***************************************************************************/
21 * Internal PSX counters.
24 #include "psxcounters.h"
27 /******************************************************************************/
31 Rc0Gate = 0x0001, // 0 not implemented
32 Rc1Gate = 0x0001, // 0 not implemented
33 Rc2Disable = 0x0001, // 0 partially implemented
34 RcUnknown1 = 0x0002, // 1 ?
35 RcUnknown2 = 0x0004, // 2 ?
36 RcCountToTarget = 0x0008, // 3
37 RcIrqOnTarget = 0x0010, // 4
38 RcIrqOnOverflow = 0x0020, // 5
39 RcIrqRegenerate = 0x0040, // 6
40 RcUnknown7 = 0x0080, // 7 ?
41 Rc0PixelClock = 0x0100, // 8 fake implementation
42 Rc1HSyncClock = 0x0100, // 8
43 Rc2Unknown8 = 0x0100, // 8 ?
44 Rc0Unknown9 = 0x0200, // 9 ?
45 Rc1Unknown9 = 0x0200, // 9 ?
46 Rc2OneEighthClock = 0x0200, // 9
47 RcUnknown10 = 0x0400, // 10 ?
48 RcCountEqTarget = 0x0800, // 11
49 RcOverflow = 0x1000, // 12
50 RcUnknown13 = 0x2000, // 13 ? (always zero)
51 RcUnknown14 = 0x4000, // 14 ? (always zero)
52 RcUnknown15 = 0x8000, // 15 ? (always zero)
55 #define CounterQuantity ( 4 )
56 //static const u32 CounterQuantity = 4;
58 static const u32 CountToOverflow = 0;
59 static const u32 CountToTarget = 1;
61 static const u32 FrameRate[] = { 60, 50 };
62 static const u32 VBlankStart[] = { 240, 256 };
63 static const u32 HSyncTotal[] = { 263, 313 };
64 static const u32 SpuUpdInterval[] = { 32, 32 };
66 #define VERBOSE_LEVEL 0
67 static const s32 VerboseLevel = VERBOSE_LEVEL;
69 /******************************************************************************/
71 Rcnt rcnts[ CounterQuantity ];
73 static u32 hSyncCount = 0;
74 static u32 spuSyncCount = 0;
75 static u32 hsync_steps = 0;
76 static u32 gpu_wants_hcnt = 0;
78 u32 psxNextCounter = 0, psxNextsCounter = 0;
80 /******************************************************************************/
83 void setIrq( u32 irq )
85 psxHu32ref(0x1070) |= SWAPu32(irq);
89 void verboseLog( u32 level, const char *str, ... )
92 if( level <= VerboseLevel )
98 vsprintf( buf, str, va );
107 /******************************************************************************/
110 void _psxRcntWcount( u32 index, u32 value )
114 verboseLog( 1, "[RCNT %i] wcount > 0xffff: %x\n", index, value );
118 rcnts[index].cycleStart = psxRegs.cycle;
119 rcnts[index].cycleStart -= value * rcnts[index].rate;
122 if( value < rcnts[index].target )
124 rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
125 rcnts[index].counterState = CountToTarget;
129 rcnts[index].cycle = 0xffff * rcnts[index].rate;
130 rcnts[index].counterState = CountToOverflow;
135 u32 _psxRcntRcount( u32 index )
139 count = psxRegs.cycle;
140 count -= rcnts[index].cycleStart;
141 if (rcnts[index].rate > 1)
142 count /= rcnts[index].rate;
146 verboseLog( 1, "[RCNT %i] rcount > 0xffff: %x\n", index, count );
153 /******************************************************************************/
161 psxNextsCounter = psxRegs.cycle;
162 psxNextCounter = 0x7fffffff;
164 for( i = 0; i < CounterQuantity; ++i )
166 countToUpdate = rcnts[i].cycle - (psxNextsCounter - rcnts[i].cycleStart);
168 if( countToUpdate < 0 )
174 if( countToUpdate < (s32)psxNextCounter )
176 psxNextCounter = countToUpdate;
181 /******************************************************************************/
184 void psxRcntReset( u32 index )
188 if( rcnts[index].counterState == CountToTarget )
190 if( rcnts[index].mode & RcCountToTarget )
192 count = psxRegs.cycle;
193 count -= rcnts[index].cycleStart;
194 if (rcnts[index].rate > 1)
195 count /= rcnts[index].rate;
196 count -= rcnts[index].target;
200 count = _psxRcntRcount( index );
203 _psxRcntWcount( index, count );
205 if( rcnts[index].mode & RcIrqOnTarget )
207 if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
209 verboseLog( 3, "[RCNT %i] irq: %x\n", index, count );
210 setIrq( rcnts[index].irq );
211 rcnts[index].irqState = 1;
215 rcnts[index].mode |= RcCountEqTarget;
217 else if( rcnts[index].counterState == CountToOverflow )
219 count = psxRegs.cycle;
220 count -= rcnts[index].cycleStart;
221 if (rcnts[index].rate > 1)
222 count /= rcnts[index].rate;
225 _psxRcntWcount( index, count );
227 if( rcnts[index].mode & RcIrqOnOverflow )
229 if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
231 verboseLog( 3, "[RCNT %i] irq: %x\n", index, count );
232 setIrq( rcnts[index].irq );
233 rcnts[index].irqState = 1;
237 rcnts[index].mode |= RcOverflow;
240 rcnts[index].mode |= RcUnknown10;
249 cycle = psxRegs.cycle;
252 if( cycle - rcnts[0].cycleStart >= rcnts[0].cycle )
258 if( cycle - rcnts[1].cycleStart >= rcnts[1].cycle )
264 if( cycle - rcnts[2].cycleStart >= rcnts[2].cycle )
270 if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle )
272 u32 leftover_cycles = cycle - rcnts[3].cycleStart - rcnts[3].cycle;
273 u32 next_vsync, next_lace;
275 spuSyncCount += hsync_steps;
276 hSyncCount += hsync_steps;
279 if( spuSyncCount >= SpuUpdInterval[Config.PsxType] )
285 SPU_async( SpuUpdInterval[Config.PsxType] * rcnts[3].target );
290 if( hSyncCount == VBlankStart[Config.PsxType] )
292 GPU_vBlank( 1, &hSyncCount, &gpu_wants_hcnt );
294 // For the best times. :D
298 // Update lace. (with InuYasha fix)
299 if( hSyncCount >= (Config.VSyncWA ? HSyncTotal[Config.PsxType] / BIAS : HSyncTotal[Config.PsxType]) )
303 GPU_vBlank( 0, &hSyncCount, &gpu_wants_hcnt );
310 // Schedule next call, in hsyncs
311 hsync_steps = SpuUpdInterval[Config.PsxType] - spuSyncCount;
312 next_vsync = VBlankStart[Config.PsxType] - hSyncCount; // ok to overflow
313 next_lace = HSyncTotal[Config.PsxType] - hSyncCount;
314 if( next_vsync && next_vsync < hsync_steps )
315 hsync_steps = next_vsync;
316 if( next_lace && next_lace < hsync_steps )
317 hsync_steps = next_lace;
321 rcnts[3].cycleStart = cycle - leftover_cycles;
322 rcnts[3].cycle = hsync_steps * rcnts[3].target;
331 /******************************************************************************/
333 void psxRcntWcount( u32 index, u32 value )
335 verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value );
337 _psxRcntWcount( index, value );
341 void psxRcntWmode( u32 index, u32 value )
343 verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value );
345 rcnts[index].mode = value;
346 rcnts[index].irqState = 0;
351 if( value & Rc0PixelClock )
353 rcnts[index].rate = 5;
357 rcnts[index].rate = 1;
361 if( value & Rc1HSyncClock )
363 rcnts[index].rate = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
367 rcnts[index].rate = 1;
371 if( value & Rc2OneEighthClock )
373 rcnts[index].rate = 8;
377 rcnts[index].rate = 1;
380 // TODO: wcount must work.
381 if( value & Rc2Disable )
383 rcnts[index].rate = 0xffffffff;
388 _psxRcntWcount( index, 0 );
392 void psxRcntWtarget( u32 index, u32 value )
394 verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value );
396 rcnts[index].target = value;
398 _psxRcntWcount( index, _psxRcntRcount( index ) );
402 /******************************************************************************/
404 u32 psxRcntRcount( u32 index )
408 count = _psxRcntRcount( index );
410 // Parasite Eve 2 fix.
415 if( rcnts[index].counterState == CountToTarget )
422 verboseLog( 2, "[RCNT %i] rcount: %x\n", index, count );
427 u32 psxRcntRmode( u32 index )
431 mode = rcnts[index].mode;
432 rcnts[index].mode &= 0xe7ff;
434 verboseLog( 2, "[RCNT %i] rmode: %x\n", index, mode );
439 u32 psxRcntRtarget( u32 index )
441 verboseLog( 2, "[RCNT %i] rtarget: %x\n", index, rcnts[index].target );
443 return rcnts[index].target;
446 /******************************************************************************/
466 rcnts[3].mode = RcCountToTarget;
467 rcnts[3].target = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
469 for( i = 0; i < CounterQuantity; ++i )
471 _psxRcntWcount( i, 0 );
481 /******************************************************************************/
483 s32 psxRcntFreeze( gzFile f, s32 Mode )
485 gzfreeze( &rcnts, sizeof(rcnts) );
486 gzfreeze( &hSyncCount, sizeof(hSyncCount) );
487 gzfreeze( &spuSyncCount, sizeof(spuSyncCount) );
488 gzfreeze( &psxNextCounter, sizeof(psxNextCounter) );
489 gzfreeze( &psxNextsCounter, sizeof(psxNextsCounter) );
492 hsync_steps = (psxRegs.cycle - rcnts[3].cycleStart) / rcnts[3].target;
497 /******************************************************************************/