libpcsxcore/psxcounters.c

   1 /***************************************************************************
   2  *   Copyright (C) 2010 by Blade_Arma                                      *
   3  *                                                                         *
   4  *   This program is free software; you can redistribute it and/or modify  *
   5  *   it under the terms of the GNU General Public License as published by  *
   6  *   the Free Software Foundation; either version 2 of the License, or     *
   7  *   (at your option) any later version.                                   *
   8  *                                                                         *
   9  *   This program is distributed in the hope that it will be useful,       *
  10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  12  *   GNU General Public License for more details.                          *
  13  *                                                                         *
  14  *   You should have received a copy of the GNU General Public License     *
  15  *   along with this program; if not, write to the                         *
  16  *   Free Software Foundation, Inc.,                                       *
  17  *   51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA.           *
  18  ***************************************************************************/
  19
  20 /*
  21  * Internal PSX counters.
  22  */
  23
  24 #include "psxcounters.h"
  25 #include "gpu.h"
  26 #include "debug.h"
  27
  28 /******************************************************************************/
  29
  30 enum
  31 {
  32     Rc0Gate           = 0x0001, // 0    not implemented
  33     Rc1Gate           = 0x0001, // 0    not implemented
  34     Rc2Disable        = 0x0001, // 0    partially implemented
  35     RcUnknown1        = 0x0002, // 1    ?
  36     RcUnknown2        = 0x0004, // 2    ?
  37     RcCountToTarget   = 0x0008, // 3
  38     RcIrqOnTarget     = 0x0010, // 4
  39     RcIrqOnOverflow   = 0x0020, // 5
  40     RcIrqRegenerate   = 0x0040, // 6
  41     RcUnknown7        = 0x0080, // 7    ?
  42     Rc0PixelClock     = 0x0100, // 8    fake implementation
  43     Rc1HSyncClock     = 0x0100, // 8
  44     Rc2Unknown8       = 0x0100, // 8    ?
  45     Rc0Unknown9       = 0x0200, // 9    ?
  46     Rc1Unknown9       = 0x0200, // 9    ?
  47     Rc2OneEighthClock = 0x0200, // 9
  48     RcUnknown10       = 0x0400, // 10   ?
  49     RcCountEqTarget   = 0x0800, // 11
  50     RcOverflow        = 0x1000, // 12
  51     RcUnknown13       = 0x2000, // 13   ? (always zero)
  52     RcUnknown14       = 0x4000, // 14   ? (always zero)
  53     RcUnknown15       = 0x8000, // 15   ? (always zero)
  54 };
  55
  56 #define CounterQuantity           ( 4 )
  57 //static const u32 CounterQuantity  = 4;
  58
  59 static const u32 CountToOverflow  = 0;
  60 static const u32 CountToTarget    = 1;
  61
  62 static const u32 FrameRate[]      = { 60, 50 };
  63 static const u32 HSyncTotal[]     = { 263, 313 };
  64 static const u32 SpuUpdInterval[] = { 32, 32 };
  65 #define VBlankStart 240
  66
  67 #define VERBOSE_LEVEL 0
  68 static const s32 VerboseLevel     = VERBOSE_LEVEL;
  69
  70 /******************************************************************************/
  71
  72 Rcnt rcnts[ CounterQuantity ];
  73
  74 u32 hSyncCount = 0;
  75 u32 frame_counter = 0;
  76 static u32 spuSyncCount = 0;
  77 static u32 hsync_steps = 0;
  78 static u32 base_cycle = 0;
  79
  80 u32 psxNextCounter = 0, psxNextsCounter = 0;
  81
  82 /******************************************************************************/
  83
  84 static inline
  85 void setIrq( u32 irq )
  86 {
  87     psxHu32ref(0x1070) |= SWAPu32(irq);
  88 }
  89
  90 static
  91 void verboseLog( u32 level, const char *str, ... )
  92 {
  93 #if VERBOSE_LEVEL > 0
  94     if( level <= VerboseLevel )
  95     {
  96         va_list va;
  97         char buf[ 4096 ];
  98
  99         va_start( va, str );
 100         vsprintf( buf, str, va );
 101         va_end( va );
 102
 103         printf( "%s", buf );
 104         fflush( stdout );
 105     }
 106 #endif
 107 }
 108
 109 /******************************************************************************/
 110
 111 static inline
 112 void _psxRcntWcount( u32 index, u32 value )
 113 {
 114     if( value > 0xffff )
 115     {
 116         verboseLog( 1, "[RCNT %i] wcount > 0xffff: %x\n", index, value );
 117         value &= 0xffff;
 118     }
 119
 120     rcnts[index].cycleStart  = psxRegs.cycle;
 121     rcnts[index].cycleStart -= value * rcnts[index].rate;
 122
 123     // TODO: <=.
 124     if( value < rcnts[index].target )
 125     {
 126         rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
 127         rcnts[index].counterState = CountToTarget;
 128     }
 129     else
 130     {
 131         rcnts[index].cycle = 0xffff * rcnts[index].rate;
 132         rcnts[index].counterState = CountToOverflow;
 133     }
 134 }
 135
 136 static inline
 137 u32 _psxRcntRcount( u32 index )
 138 {
 139     u32 count;
 140
 141     count  = psxRegs.cycle;
 142     count -= rcnts[index].cycleStart;
 143     if (rcnts[index].rate > 1)
 144         count /= rcnts[index].rate;
 145
 146     if( count > 0xffff )
 147     {
 148         verboseLog( 1, "[RCNT %i] rcount > 0xffff: %x\n", index, count );
 149         count &= 0xffff;
 150     }
 151
 152     return count;
 153 }
 154
 155 /******************************************************************************/
 156
 157 static
 158 void psxRcntSet()
 159 {
 160     s32 countToUpdate;
 161     u32 i;
 162
 163     psxNextsCounter = psxRegs.cycle;
 164     psxNextCounter  = 0x7fffffff;
 165
 166     for( i = 0; i < CounterQuantity; ++i )
 167     {
 168         countToUpdate = rcnts[i].cycle - (psxNextsCounter - rcnts[i].cycleStart);
 169
 170         if( countToUpdate < 0 )
 171         {
 172             psxNextCounter = 0;
 173             break;
 174         }
 175
 176         if( countToUpdate < (s32)psxNextCounter )
 177         {
 178             psxNextCounter = countToUpdate;
 179         }
 180     }
 181
 182     psxRegs.interrupt |= (1 << PSXINT_RCNT);
 183     new_dyna_set_event(PSXINT_RCNT, psxNextCounter);
 184 }
 185
 186 /******************************************************************************/
 187
 188 static
 189 void psxRcntReset( u32 index )
 190 {
 191     u32 count;
 192
 193     rcnts[index].mode |= RcUnknown10;
 194
 195     if( rcnts[index].counterState == CountToTarget )
 196     {
 197         count  = psxRegs.cycle;
 198         count -= rcnts[index].cycleStart;
 199         if( rcnts[index].rate > 1 )
 200             count /= rcnts[index].rate;
 201         if( rcnts[index].mode & RcCountToTarget )
 202             count -= rcnts[index].target;
 203
 204         _psxRcntWcount( index, count );
 205
 206         if( rcnts[index].mode & RcIrqOnTarget )
 207         {
 208             if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
 209             {
 210                 verboseLog( 3, "[RCNT %i] irq: %x\n", index, count );
 211                 setIrq( rcnts[index].irq );
 212                 rcnts[index].irqState = 1;
 213             }
 214         }
 215
 216         rcnts[index].mode |= RcCountEqTarget;
 217
 218         if( count < 0xffff ) // special case, overflow too?
 219             return;
 220     }
 221
 222     if( rcnts[index].counterState == CountToOverflow )
 223     {
 224         count  = psxRegs.cycle;
 225         count -= rcnts[index].cycleStart;
 226         if (rcnts[index].rate > 1)
 227             count /= rcnts[index].rate;
 228         count -= 0xffff;
 229
 230         _psxRcntWcount( index, count );
 231
 232         if( rcnts[index].mode & RcIrqOnOverflow )
 233         {
 234             if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
 235             {
 236                 verboseLog( 3, "[RCNT %i] irq: %x\n", index, count );
 237                 setIrq( rcnts[index].irq );
 238                 rcnts[index].irqState = 1;
 239             }
 240         }
 241
 242         rcnts[index].mode |= RcOverflow;
 243     }
 244 }
 245
 246 void psxRcntUpdate()
 247 {
 248     u32 cycle;
 249
 250     cycle = psxRegs.cycle;
 251
 252     // rcnt 0.
 253     if( cycle - rcnts[0].cycleStart >= rcnts[0].cycle )
 254     {
 255         psxRcntReset( 0 );
 256     }
 257
 258     // rcnt 1.
 259     if( cycle - rcnts[1].cycleStart >= rcnts[1].cycle )
 260     {
 261         psxRcntReset( 1 );
 262     }
 263
 264     // rcnt 2.
 265     if( cycle - rcnts[2].cycleStart >= rcnts[2].cycle )
 266     {
 267         psxRcntReset( 2 );
 268     }
 269
 270     // rcnt base.
 271     if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle )
 272     {
 273         u32 leftover_cycles = cycle - rcnts[3].cycleStart - rcnts[3].cycle;
 274         u32 next_vsync, next_lace;
 275
 276         spuSyncCount += hsync_steps;
 277         hSyncCount += hsync_steps;
 278
 279         // Update spu.
 280         if( spuSyncCount >= SpuUpdInterval[Config.PsxType] )
 281         {
 282             spuSyncCount = 0;
 283
 284             if( SPU_async )
 285             {
 286                 SPU_async( SpuUpdInterval[Config.PsxType] * rcnts[3].target );
 287             }
 288         }
 289
 290         // VSync irq.
 291         if( hSyncCount == VBlankStart )
 292         {
 293             HW_GPU_STATUS &= ~PSXGPU_LCF;
 294             GPU_vBlank( 1, 0 );
 295             setIrq( 0x01 );
 296
 297             EmuUpdate();
 298             GPU_updateLace();
 299         }
 300
 301         // Update lace. (with InuYasha fix)
 302         if( hSyncCount >= (Config.VSyncWA ? HSyncTotal[Config.PsxType] / BIAS : HSyncTotal[Config.PsxType]) )
 303         {
 304             hSyncCount = 0;
 305             frame_counter++;
 306
 307             gpuSyncPluginSR();
 308             if( (HW_GPU_STATUS & PSXGPU_ILACE_BITS) == PSXGPU_ILACE_BITS )
 309                 HW_GPU_STATUS |= frame_counter << 31;
 310             GPU_vBlank( 0, HW_GPU_STATUS >> 31 );
 311         }
 312
 313         // Schedule next call, in hsyncs
 314         hsync_steps = SpuUpdInterval[Config.PsxType] - spuSyncCount;
 315         next_vsync = VBlankStart - hSyncCount; // ok to overflow
 316         next_lace = HSyncTotal[Config.PsxType] - hSyncCount;
 317         if( next_vsync && next_vsync < hsync_steps )
 318             hsync_steps = next_vsync;
 319         if( next_lace && next_lace < hsync_steps )
 320             hsync_steps = next_lace;
 321
 322         rcnts[3].cycleStart = cycle - leftover_cycles;
 323         if (Config.PsxType)
 324                 // 20.12 precision, clk / 50 / 313 ~= 2164.14
 325                 base_cycle += hsync_steps * 8864320;
 326         else
 327                 // clk / 60 / 263 ~= 2146.31
 328                 base_cycle += hsync_steps * 8791293;
 329         rcnts[3].cycle = base_cycle >> 12;
 330         base_cycle &= 0xfff;
 331     }
 332
 333     psxRcntSet();
 334
 335 #ifndef NDEBUG
 336     DebugVSync();
 337 #endif
 338 }
 339
 340 /******************************************************************************/
 341
 342 void psxRcntWcount( u32 index, u32 value )
 343 {
 344     verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value );
 345
 346     _psxRcntWcount( index, value );
 347     psxRcntSet();
 348 }
 349
 350 void psxRcntWmode( u32 index, u32 value )
 351 {
 352     verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value );
 353
 354     rcnts[index].mode = value;
 355     rcnts[index].irqState = 0;
 356
 357     switch( index )
 358     {
 359         case 0:
 360             if( value & Rc0PixelClock )
 361             {
 362                 rcnts[index].rate = 5;
 363             }
 364             else
 365             {
 366                 rcnts[index].rate = 1;
 367             }
 368         break;
 369         case 1:
 370             if( value & Rc1HSyncClock )
 371             {
 372                 rcnts[index].rate = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
 373             }
 374             else
 375             {
 376                 rcnts[index].rate = 1;
 377             }
 378         break;
 379         case 2:
 380             if( value & Rc2OneEighthClock )
 381             {
 382                 rcnts[index].rate = 8;
 383             }
 384             else
 385             {
 386                 rcnts[index].rate = 1;
 387             }
 388
 389             // TODO: wcount must work.
 390             if( value & Rc2Disable )
 391             {
 392                 rcnts[index].rate = 0xffffffff;
 393             }
 394         break;
 395     }
 396
 397     _psxRcntWcount( index, 0 );
 398     psxRcntSet();
 399 }
 400
 401 void psxRcntWtarget( u32 index, u32 value )
 402 {
 403     verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value );
 404
 405     rcnts[index].target = value;
 406
 407     _psxRcntWcount( index, _psxRcntRcount( index ) );
 408     psxRcntSet();
 409 }
 410
 411 /******************************************************************************/
 412
 413 u32 psxRcntRcount( u32 index )
 414 {
 415     u32 count;
 416
 417     count = _psxRcntRcount( index );
 418
 419     // Parasite Eve 2 fix.
 420     if( Config.RCntFix )
 421     {
 422         if( index == 2 )
 423         {
 424             if( rcnts[index].counterState == CountToTarget )
 425             {
 426                 count /= BIAS;
 427             }
 428         }
 429     }
 430
 431     verboseLog( 2, "[RCNT %i] rcount: %x\n", index, count );
 432
 433     return count;
 434 }
 435
 436 u32 psxRcntRmode( u32 index )
 437 {
 438     u16 mode;
 439
 440     mode = rcnts[index].mode;
 441     rcnts[index].mode &= 0xe7ff;
 442
 443     verboseLog( 2, "[RCNT %i] rmode: %x\n", index, mode );
 444
 445     return mode;
 446 }
 447
 448 u32 psxRcntRtarget( u32 index )
 449 {
 450     verboseLog( 2, "[RCNT %i] rtarget: %x\n", index, rcnts[index].target );
 451
 452     return rcnts[index].target;
 453 }
 454
 455 /******************************************************************************/
 456
 457 void psxRcntInit()
 458 {
 459     s32 i;
 460
 461     // rcnt 0.
 462     rcnts[0].rate   = 1;
 463     rcnts[0].irq    = 0x10;
 464
 465     // rcnt 1.
 466     rcnts[1].rate   = 1;
 467     rcnts[1].irq    = 0x20;
 468
 469     // rcnt 2.
 470     rcnts[2].rate   = 1;
 471     rcnts[2].irq    = 0x40;
 472
 473     // rcnt base.
 474     rcnts[3].rate   = 1;
 475     rcnts[3].mode   = RcCountToTarget;
 476     rcnts[3].target = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
 477
 478     for( i = 0; i < CounterQuantity; ++i )
 479     {
 480         _psxRcntWcount( i, 0 );
 481     }
 482
 483     hSyncCount = 0;
 484     spuSyncCount = 0;
 485     hsync_steps = 1;
 486
 487     psxRcntSet();
 488 }
 489
 490 /******************************************************************************/
 491
 492 s32 psxRcntFreeze( gzFile f, s32 Mode )
 493 {
 494     gzfreeze( &rcnts, sizeof(rcnts) );
 495     gzfreeze( &hSyncCount, sizeof(hSyncCount) );
 496     gzfreeze( &spuSyncCount, sizeof(spuSyncCount) );
 497     gzfreeze( &psxNextCounter, sizeof(psxNextCounter) );
 498     gzfreeze( &psxNextsCounter, sizeof(psxNextsCounter) );
 499
 500     if (Mode == 0)
 501         hsync_steps = (psxRegs.cycle - rcnts[3].cycleStart) / rcnts[3].target;
 502
 503     base_cycle = 0;
 504
 505     return 0;
 506 }
 507
 508 /******************************************************************************/